sdcc/device/include/mcs51/uPSD33xx.h

   1 /*-------------------------------------------------------------------------
   2    uPSD33xx.h - Register Declarations for ST's uPSD33xx "Fast 8032 MCU with
   3    Programmable Logic"
   4    (Based on preliminary datasheet from Jan/2005 )
   5
   6    Copyright (C) 2007, Jesus Calvino-Fraga / jesusc at ece.ubc.ca
   7
   8    This library is free software; you can redistribute it and/or modify it
   9    under the terms of the GNU General Public License as published by the
  10    Free Software Foundation; either version 2, or (at your option) any
  11    later version.
  12
  13    This library is distributed in the hope that it will be useful,
  14    but WITHOUT ANY WARRANTY; without even the implied warranty of
  15    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16    GNU General Public License for more details.
  17
  18    You should have received a copy of the GNU General Public License
  19    along with this library; see the file COPYING. If not, write to the
  20    Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  21    MA 02110-1301, USA.
  22
  23    As a special exception, if you link this library with other files,
  24    some of which are compiled with SDCC, to produce an executable,
  25    this library does not by itself cause the resulting executable to
  26    be covered by the GNU General Public License. This exception does
  27    not however invalidate any other reasons why the executable file
  28    might be covered by the GNU General Public License.
  29 -------------------------------------------------------------------------*/
  30
  31 #ifndef REG_UPSD33XX_H
  32 #define REG_UPSD33XX_H
  33
  34 #include <compiler.h>
  35
  36 //Interrupt vector numbers (see table 16 on datasheet)
  37 #define EXT0_INTERRUPT   ((0x03-3)/8)
  38 #define TIMER0_INTERRUPT ((0x0B-3)/8)
  39 #define EXT1_INTERRUPT   ((0x13-3)/8)
  40 #define TIMER1_INTERRUPT ((0x1B-3)/8)
  41 #define UART0_INTERRUPT  ((0x23-3)/8)
  42 #define TIMER2_INTERRUPT ((0x2B-3)/8)
  43 #define TX2_INTERRUPT    ((0x2B-3)/8)
  44 #define SPI_INTERRUPT    ((0x53-3)/8)
  45 #define I2C_INTERRUPT    ((0x43-3)/8)
  46 #define ADC_INTERRUPT    ((0x3B-3)/8)
  47 #define PCA_INTERRUPT    ((0x5B-3)/8)
  48 #define UART1_INTERRUPT  ((0x4B-3)/8)
  49
  50 SFR(SP,   0x81); // Stack Pointer.
  51 SFR(DPL,  0x82); // Data Pointer Low.
  52 SFR(DPH,  0x83); // Data Pointer High.
  53
  54 SFR(DPTC, 0x85); // Data Pointer Control Register.
  55 SFR(DPS,  0x85); // Data Pointer Control Register alias for SDCC
  56     #define AT 0x40 //0:Manually Select Data Pointer / 1:Auto Toggle between DPTR0 and DPTR1
  57     #define DPSE0 0x01 // 0:DPTR0 Selected for use as DPTR / 1:DPTR1 Selected for use as DPTR
  58
  59 SFR(DPTM, 0x86); // Data Pointer Mode Register.
  60     #define DP1_1 0x08 // DPTR1 Mode Bit 1.
  61     #define DP1_0 0x04 // DPTR1 Mode Bit 0.
  62     #define DP0_1 0x02 // DPTR0 Mode Bit 1.
  63     #define DP0_0 0x01 // DPTR0 Mode Bit 0.
  64     // DPx_1 DPx_0
  65     //   0     0  : DPTRx No Change
  66     //   0     1  : Reserved
  67     //   1     0  : DPTRx Auto Increment
  68     //   1     1  : DPTRx Auto Decrement
  69
  70 SFR(PCON, 0x87); // Power Control.
  71     #define SMOD0  0x80 //Baud Rate Double Bit (UART0)
  72     #define SMOD1  0x40 //Baud Rate Double Bit (UART1)
  73     #define POR    0x10 //Only a power-on reset sets this bit (cold reset).
  74     #define RCLK1  0x08 //Receive Clock Flag (UART1)
  75     #define TCLK1  0x04 //Transmit Clock Flag (UART1)
  76     #define PD     0x02 //Power-Down Mode Enable.
  77     #define IDL    0x01 //Idle Mode Enable.
  78
  79 SFR(TCON, 0x88); // Timer/Counter Control.
  80     SBIT(TF1, 0x88, 7); // Timer 1 overflow flag.
  81     SBIT(TR1, 0x88, 6); // Timer 1 run control flag.
  82     SBIT(TF0, 0x88, 5); // Timer 0 overflow flag.
  83     SBIT(TR0, 0x88, 4); // Timer 0 run control flag.
  84     SBIT(IE1, 0x88, 3); // Interrupt 1 flag.
  85     SBIT(IT1, 0x88, 2); // Interrupt 1 type control bit.
  86     SBIT(IE0, 0x88, 1); // Interrupt 0 flag.
  87     SBIT(IT0, 0x88, 0); // Interrupt 0 type control bit.
  88
  89 SFR(TMOD, 0x89); // Timer/Counter Mode Control.
  90     #define GATE1 0x80 // External enable for timer 1.
  91     #define C_T1  0x40 // Timer or counter select for timer 1.
  92     #define M1_1  0x20 // Operation mode bit 1 for timer 1.
  93     #define M0_1  0x10 // Operation mode bit 0 for timer 1.
  94     #define GATE0 0x08 // External enable for timer 0.
  95     #define C_T0  0x04 // Timer or counter select for timer 0.
  96     #define M1_0  0x02 // Operation mode bit 1 for timer 0.
  97     #define M0_0  0x01 // Operation mode bit 0 for timer 0.
  98
  99 SFR(TL0, 0x8A); // Timer 0 LSB.
 100 SFR(TL1, 0x8B); // Timer 1 LSB.
 101 SFR(TH0, 0x8C); // Timer 0 MSB.
 102 SFR(TH1, 0x8D); // Timer 1 MSB.
 103
 104 //For P1SFS0 and P1SFS1 SFRs details check datasheet Table 31.
 105 SFR(P1SFS0, 0x8E); //Port 1 Special Function Select 0 Register.
 106     #define P1SF07 0x80
 107     #define P1SF06 0x40
 108     #define P1SF05 0x20
 109     #define P1SF04 0x10
 110     #define P1SF03 0x08
 111     #define P1SF02 0x04
 112     #define P1SF01 0x02
 113     #define P1SF00 0x01
 114 SFR(P1SFS1, 0x8F); //Port 1 Special Function Select 1 Register.
 115     #define P1SF17 0x80
 116     #define P1SF16 0x40
 117     #define P1SF15 0x20
 118     #define P1SF14 0x10
 119     #define P1SF13 0x08
 120     #define P1SF12 0x04
 121     #define P1SF11 0x02
 122     #define P1SF10 0x01
 123
 124 SFR(P1, 0x90); // Port 1
 125     SBIT(P1_0, 0x90, 0); // Port 1 bit 0.
 126     SBIT(P1_1, 0x90, 1); // Port 1 bit 1.
 127     SBIT(P1_2, 0x90, 2); // Port 1 bit 2.
 128     SBIT(P1_3, 0x90, 3); // Port 1 bit 3.
 129     SBIT(P1_4, 0x90, 4); // Port 1 bit 4.
 130     SBIT(P1_5, 0x90, 5); // Port 1 bit 5.
 131     SBIT(P1_6, 0x90, 6); // Port 1 bit 6.
 132     SBIT(P1_7, 0x90, 7); // Port 1 bit 7.
 133     //Alternate names (from figure 3)
 134     SBIT(T2,     0x90, 0); //Input to Timer/Counter 2.
 135     SBIT(T2X,    0x90, 1); //Capture/reload trigger for Counter 2.
 136     SBIT(RXD1,   0x90, 2);
 137     SBIT(TXD1,   0x90, 3);
 138     SBIT(SPICLK, 0x90, 4);
 139     SBIT(SPIRXD, 0x90, 5);
 140     SBIT(SPITXD, 0x90, 6);
 141     SBIT(SPISEL, 0x90, 7);
 142
 143 SFR(P3SFS, 0x91); // Port 3 Special Function Select Register
 144     #define P3SF7 0x80
 145     #define P3SF6 0x40
 146     #define P3SF5 0x20
 147     #define P3SF4 0x10
 148     #define P3SF3 0x08
 149     #define P3SF2 0x04
 150     #define P3SF1 0x02
 151     #define P3SF0 0x01
 152
 153 //For P4SFS0 and P4SFS1 SFRs details check datasheet Table 34.
 154 SFR(P4SFS0, 0x92); //Port 4 Special Function Select 0 Register.
 155     #define P4SF07 0x80
 156     #define P4SF06 0x40
 157     #define P4SF05 0x20
 158     #define P4SF04 0x10
 159     #define P4SF03 0x08
 160     #define P4SF02 0x04
 161     #define P4SF01 0x02
 162     #define P4SF00 0x01
 163 SFR(P4SFS1, 0x93); //Port 4 Special Function Select 1 Register.
 164     #define P4SF17 0x80
 165     #define P4SF16 0x40
 166     #define P4SF15 0x20
 167     #define P4SF14 0x10
 168     #define P4SF13 0x08
 169     #define P4SF12 0x04
 170     #define P4SF11 0x02
 171     #define P4SF10 0x01
 172
 173 SFR(ADCPS, 0x94); // ADC pre-scaller?
 174     #define ADCCE  0x08 // ADC Conversion Reference Clock Enable.
 175     //ADC Reference Clock PreScaler. Only three Prescaler values are allowed:
 176     #define ADCPS2 0x02 // Resulting ADC clock is fOSC.
 177     #define ADCPS1 0x01 // Resulting ADC clock is fOSC/2.
 178     #define ADCPS0 0x00 // Resulting ADC clock is fOSC/4.
 179
 180 SFR(ADAT0, 0x95); // A/D result register (bits 0 to 7).
 181 SFR(ADAT1, 0x96); // A/D result register (bits 8 and 9).
 182 SFR(ACON,  0x97); // A/D control register.
 183     #define AINTF  0x80 // ADC Interrupt flag. This bit must be cleared with software.
 184     #define AINTEN 0x40 // ADC Interrupt Enable.
 185     #define ADEN   0x20 // ADC Enable Bit.
 186     #define ADS2   0x10 // Analog channel Select bit 3.
 187     #define ADS1   0x08 // Analog channel Select bit 2.
 188     #define ADS0   0x04 // Analog channel Select bit 1.
 189     #define ADST   0x02 // ADC Start Bit.
 190     #define ADSF   0x01 // ADC Status Bit.
 191
 192 SFR(SCON, 0x98); // For compatibity with legacy code
 193 SFR(SCON0, 0x98); // Serial Port UART0 Control Register
 194     SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0.
 195     SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1.
 196     SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2.
 197     SBIT(REN, 0x98, 4); // Enables serial reception.
 198     SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3.
 199     SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received.
 200     SBIT(TI,  0x98, 1); // Transmit interrupt flag.
 201     SBIT(RI,  0x98, 0); // Receive interrupt flag.
 202
 203 SFR(SBUF, 0x99);  // For compatibity with legacy code.
 204 SFR(SBUF0, 0x99); // Serial Port UART0 Data Buffer.
 205
 206 SFR(BUSCON, 0x9D); // Bus Control Register.
 207     #define EPFQ  0x80 // Enable Pre-Fetch Queue.
 208     #define EBC   0x40 // Enable Branch Cache.
 209     #define WRW1  0x20 // WR Wait bit 2.
 210     #define WRW0  0x10 // WR Wait bit 1.
 211     #define RDW1  0x08 // RD Wait bit 2.
 212     #define RDW0  0x04 // RD Wait bit 1.
 213     #define CW1   0x02 // PSEN Wait bit 2.
 214     #define CW0   0x01 // PSEN Wait bit 1.
 215
 216 SFR(PCACL0,  0xA2); // The low 8 bits of PCA 0 16-bit counter.
 217 SFR(PCACH0,  0xA3); // The high 8 bits of PCA 0 16-bit counter.
 218 SFR(PCACON0, 0xA4); // PCA 0 Control Register.
 219 SFR(PCASTA,  0xA5); // PCA 0 and PCA 1 Status Register.
 220 SFR(PCACL1,  0xBA); // The low 8 bits of PCA 1 16-bit counter.
 221 SFR(PCACH1,  0xBB); // The high 8 bits of PCA 1 16-bit counter.
 222 SFR(PCACON1, 0xBC); // PCA 1 Control Register.
 223
 224 SFR(IEA, 0xA7); // Interrupt Enable Addition Register.
 225     #define EADC 0x80 // Enable ADC Interrupt.
 226     #define ESPI 0x40 // Enable SPI Interrupt.
 227     #define EPCA 0x20 // Enable Programmable Counter Array Interrupt.
 228     #define ES1  0x10 // Enable UART1 Interrupt.
 229     #define EI2C 0x02 // Enable I2C Interrupt.
 230
 231 SFR(IE, 0xA8); // Interrupt Enable Register.
 232     SBIT(EA,  0xA8, 7); // Global disable bit.
 233     SBIT(ET2, 0xA8, 5); // Enable Timer 2 Interrupt.
 234     SBIT(ES0, 0xA8, 4); // Enable UART0 Interrupt.
 235     SBIT(ET1, 0xA8, 3); // Enable Timer 1 Interrupt.
 236     SBIT(EX1, 0xA8, 2); // Enable External Interrupt INT1.
 237     SBIT(ET0, 0xA8, 1); // Enable Timer 0 Interrupt.
 238     SBIT(EX0, 0xA8, 0); // Enable External Interrupt INT0.
 239
 240 SFR(TCMMODE0, 0xA9); // TCM 0 Mode.
 241 SFR(TCMMODE1, 0xAA); // TCM 1 Mode.
 242 SFR(TCMMODE2, 0xAB); // TCM 2 Mode.
 243 SFR(TCMMODE3, 0xBD); // TCM 3 Mode.
 244 SFR(TCMMODE4, 0xBE); // TCM 4 Mode.
 245 SFR(TCMMODE5, 0xBF); // TCM 5 Mode.
 246 //These are the bits for the six SFRs above:
 247     #define EINTF  0x80  // Enable the interrupt flags (INTF) in the Status Register to generate an interrupt.
 248     #define E_COMP 0x40  // Enable the comparator when set.
 249     #define CAP_PE 0x20  // Enable Capture Mode, a positive edge on the CEXn pin.
 250     #define CAP_NE 0x20  // Enable Capture Mode, a negative edge on the CEXn pin.
 251     #define MATCH  0x08  // A match from the comparator sets the INTF bits in the Status Register.
 252     #define TOGGLE 0x04  // A match on the comparator results in a toggling output on CEXn pin.
 253     #define PWM1   0x02  // PWM mode bit 2.
 254     #define PWM0   0x01  // PWM mode bit 1.
 255
 256 SFR(CAPCOML0, 0xAC); // Capture/Compare register low of TCM 0.
 257 SFR(CAPCOMH0, 0xAD); // Capture/Compare register High of TCM 0.
 258 SFR(CAPCOML1, 0xAF); // Capture/Compare register low of TCM 1.
 259 SFR(CAPCOMH1, 0xB1); // Capture/Compare register High of TCM 1.
 260 SFR(CAPCOML2, 0xB2); // Capture/Compare register low of TCM 2.
 261 SFR(CAPCOMH2, 0xB3); // Capture/Compare register High of TCM 2.
 262 SFR(CAPCOML3, 0xC1); // Capture/Compare register low of TCM 3.
 263 SFR(CAPCOMH3, 0xC2); // Capture/Compare register High of TCM 3.
 264 SFR(CAPCOML4, 0xC3); // Capture/Compare register low of TCM 4.
 265 SFR(CAPCOMH4, 0xC4); // Capture/Compare register High of TCM 4.
 266 SFR(CAPCOML5, 0xC5); // Capture/Compare register low of TCM 5.
 267 SFR(CAPCOMH5, 0xC6); // Capture/Compare register High of TCM 5.
 268
 269 SFR(IPA, 0xB7); // Interrupt Priority Addition register.
 270     #define PADC 0x80 // ADC Interrupt priority level.
 271     #define PSPI 0x40 // SPI Interrupt priority level.
 272     #define PPCA 0x20 // PCA Interrupt level.
 273     #define PS1  0x10 // UART1 Interrupt priority.
 274     #define PI2C 0x02 // I2C Interrupt priority level.
 275
 276 SFR(IP, 0xB8);  // Interrupt Priority Register.
 277     SBIT(PT2, 0xB8, 5); // Timer 2 Interrupt priority level.
 278     SBIT(PS0, 0xB8, 4); // UART0 Interrupt priority level.
 279     SBIT(PT1, 0xB8, 3); // Timer 1 Interrupt priority level.
 280     SBIT(PX1, 0xB8, 2); // External Interrupt INT1 priority level.
 281     SBIT(PT0, 0xB8, 1); // Timer 0 Interrupt priority level.
 282     SBIT(PX0, 0xB8, 0); // External Interrupt INT0 priority level.
 283
 284 SFR(WDTRST, 0xA6);   // Watchdog Timer Reset Counter Register.
 285 SFR(WDTKEY, 0xAE);   //Watchdog Timer Key Register.
 286
 287 SFR(P3, 0xB0); // I/O Port 3 Register
 288     SBIT(P3_0, 0xB0, 0); // Port 3 bit 0.
 289     SBIT(P3_1, 0xB0, 1); // Port 3 bit 1.
 290     SBIT(P3_2, 0xB0, 2); // Port 3 bit 2.
 291     SBIT(P3_3, 0xB0, 3); // Port 3 bit 3.
 292     SBIT(P3_4, 0xB0, 4); // Port 3 bit 4.
 293     SBIT(P3_5, 0xB0, 5); // Port 3 bit 5.
 294     SBIT(P3_6, 0xB0, 6); // Port 3 bit 6.
 295     SBIT(P3_7, 0xB0, 7); // Port 3 bit 7.
 296
 297 SFR(P4, 0xC0); // I/O Port 4 Register
 298     SBIT(P4_0, 0xC0, 0); // Port 4 bit 0.
 299     SBIT(P4_1, 0xC0, 1); // Port 4 bit 1.
 300     SBIT(P4_2, 0xC0, 2); // Port 4 bit 2.
 301     SBIT(P4_3, 0xC0, 3); // Port 4 bit 3.
 302     SBIT(P4_4, 0xC0, 4); // Port 4 bit 4.
 303     SBIT(P4_5, 0xC0, 5); // Port 4 bit 5.
 304     SBIT(P4_6, 0xC0, 6); // Port 4 bit 6.
 305     SBIT(P4_7, 0xC0, 7); // Port 4 bit 7.
 306
 307 SFR(PWMF0, 0xB4); // PWM frequency register 0.
 308 SFR(PWMF1, 0xC7); // PWM frequency register 1.
 309
 310 SFR(T2CON, 0xC8); // Timer / Counter 2 Control.
 311     SBIT(TF2,   0xC8, 7); // Timer 2 overflow flag.
 312     SBIT(EXF2,  0xC8, 6); // Timer 2 external flag.
 313     SBIT(RCLK,  0xC8, 5); // Receive clock flag.
 314     SBIT(TCLK,  0xC8, 4); // Transmit clock flag.
 315     SBIT(EXEN2, 0xC8, 3); // Timer 2 external enable flag.
 316     SBIT(TR2,   0xC8, 2); // Start/stop control for timer 2.
 317     SBIT(CNT2,  0xC8, 1); // Timer or coutner select.
 318     SBIT(CAP2,  0xC8, 0); // Capture/reload flag.
 319
 320 SFR(RCAP2L, 0xCA); // Timer 2 Capture LSB.
 321 SFR(RCAP2H, 0xCB); // Timer 2 Capture MSB.
 322 SFR(TL2,    0xCC); // Timer 2 LSB.
 323 SFR(TH2,    0xCD); // Timer 2 MSB.
 324
 325 SFR(IRDACON, 0xCE); //IrDA control register
 326     #define IRDAEN 0x40 // IrDA Enable bit
 327     #define PULSE  0x20 // IrDA Pulse Modulation Select. 0: 1.627us, 1: 3/16 bit time pulses.
 328     #define CDIV4  0x10 //Specify Clock Divider bit 5.
 329     #define CDIV3  0x08 //Specify Clock Divider bit 4.
 330     #define CDIV2  0x04 //Specify Clock Divider bit 3.
 331     #define CDIV1  0x02 //Specify Clock Divider bit 2.
 332     #define CDIV0  0x01 //Specify Clock Divider bit 1.
 333
 334 SFR(CCON0, 0xF9); // Clock Control Register.
 335     #define DBGCE 0x10  // Debug Unit Breakpoint Comparator Enable.
 336     #define CPUAR 0x08  // Automatic MCU Clock Recovery.
 337     #define CPUPS2 0x04 // MCUCLK Pre-Scaler bit 3.
 338     #define CPUPS1 0x02 // MCUCLK Pre-Scaler bit 2.
 339     #define CPUPS0 0x01 // MCUCLK Pre-Scaler bit 1.
 340
 341 SFR(CCON2, 0xFB); // Pre-scaler value for PCA0.
 342     #define PCA0CE  0x10 // PCA0 Clock Enable.
 343     #define PCA0PS3 0x08 // PCA0 Pre-Scaler bit 4.
 344     #define PCA0PS2 0x04 // PCA0 Pre-Scaler bit 3.
 345     #define PCA0PS1 0x02 // PCA0 Pre-Scaler bit 2.
 346     #define PCA0PS0 0x01 // PCA0 Pre-Scaler bit 1.
 347
 348 SFR(CCON3, 0xFC); // Pre-scaler value for PCA1.
 349     #define PCA1CE  0x10 // PCA1 Clock Enable.
 350     #define PCA1PS3 0x08 // PCA1 Pre-Scaler bit 4.
 351     #define PCA1PS2 0x04 // PCA1 Pre-Scaler bit 3.
 352     #define PCA1PS1 0x02 // PCA1 Pre-Scaler bit 2.
 353     #define PCA1PS0 0x01 // PCA1 Pre-Scaler bit 1.
 354
 355 SFR(SPICLKD, 0xD2); // SPI Prescaler (Clock Divider) Register.
 356     #define DIV128 0x80
 357     #define DIV64  0x40
 358     #define DIV32  0x20
 359     #define DIV16  0x10
 360     #define DIV8   0x08
 361     #define DIV4   0x04
 362
 363 SFR(SPISTAT, 0xD3); // SPI Interface Status Register.
 364     #define BUSY   0x10 // SPI Busy.
 365     #define TEISF  0x08 // Transmission End Interrupt Source flag.
 366     #define RORISF 0x04 // Receive Overrun Interrupt Source flag.
 367     #define TISF   0x02 // Transfer Interrupt Source flag.
 368     #define RISF   0x01 // Receive Interrupt Source flag.
 369
 370 SFR(SPITDR, 0xD4); // SPI transmit data register.
 371 SFR(SPIRDR, 0xD5); // SPI receive data register.
 372
 373 SFR(SPICON0, 0xD6); // SPI Control Register 0.
 374     #define TE    0x40 // Transmitter Enable.
 375     #define RE    0x20 // Receiver Enable.
 376     #define SPIEN 0x10 // SPI Enable.
 377     #define SSEL  0x08 // Slave Selection.
 378     #define FLSB  0x04 // First LSB.
 379     #define SPO   0x02 // Sampling Polarity.
 380
 381 SFR(SPICON1, 0xD7); // SPI Interface Control Register 1.
 382     #define TEIE  0x08 // Transmission End Interrupt Enable.
 383     #define RORIE 0x04 // Receive Overrun Interrupt Enable.
 384     #define TIE   0x02 // Transmission Interrupt Enable.
 385     #define RIE   0x01 // Reception Interrupt Enable.
 386
 387 SFR(SCON1, 0x98); // Serial Port Control.
 388     SBIT(SM0, 0x98, 7); // Serial Port Mode Bit 0.
 389     SBIT(SM1, 0x98, 6); // Serial Port Mode Bit 1.
 390     SBIT(SM2, 0x98, 5); // Serial Port Mode Bit 2.
 391     SBIT(REN, 0x98, 4); // Enables serial reception.
 392     SBIT(TB8, 0x98, 3); // The 9th data bit that will be transmitted in Modes 2 and 3.
 393     SBIT(RB8, 0x98, 2); // In Modes 2 and 3, the 9th data bit that was received.
 394     SBIT(TI,  0x98, 1); // Transmit interrupt flag.
 395     SBIT(RI,  0x98, 0); // Receive interrupt flag.
 396
 397 SFR(SBUF1, 0xD9);   // Data buffer for UART1.
 398 SFR(S1SETUP, 0xDB); // I2C START Condition Sample Setup register.
 399     #define EN_SS     0x80 // Enable Sample Setup.
 400     #define SMPL_SET6 0x40 // Sample Setting bit 7.
 401     #define SMPL_SET5 0x20 // Sample Setting bit 6.
 402     #define SMPL_SET4 0x10 // Sample Setting bit 5.
 403     #define SMPL_SET3 0x08 // Sample Setting bit 4.
 404     #define SMPL_SET2 0x04 // Sample Setting bit 3.
 405     #define SMPL_SET1 0x02 // Sample Setting bit 2.
 406     #define SMPL_SET0 0x01 // Sample Setting bit 1.
 407
 408 SFR(S1CON, 0xDC); // I2C Interface Control Register.
 409     #define CR2  0x80 // SCL clock frequency select bit 3.
 410     #define ENI1 0x40 // I2C Interface Enable.
 411     #define STA  0x20 // START flag.
 412     #define STO  0x10 // STOP flag.
 413     #define ADDR 0x08 // Slave mode address.
 414     #define AA   0x04 // Assert Acknowledge enable.
 415     #define CR1  0x02 // SCL clock frequency select bit 2.
 416     #define CR0  0x01 // SCL clock frequency select bit 1.
 417
 418 SFR(S1STA, 0xDD); // I2C Interface Status Register.
 419     #define GC       0x80 // General Call flag.
 420     #define STOP     0x40 // STOP flag.
 421     #define INTR     0x20 // Interrupt flag.
 422     #define TX_MODE  0x10 // Transmission Mode flag.
 423     #define BBUSY    0x08 // Bus Busy flag.
 424     #define BLOST    0x04 // Bus Lost flag.
 425     #define ACK_RESP 0x02 // Not Acknowledge Response flag.
 426     #define SLV      0x01 // Slave Mode flag.
 427
 428 SFR(S1DAT, 0xDE); // I2C Data Shift Register.
 429 SFR(S1ADR, 0xDF); // I2C Address Register (bit 0 not used).
 430
 431 SFR(PSW, 0xD0); // Program Status Word.
 432     SBIT(CY,  0xD0, 7); // Carry Flag.
 433     SBIT(AC,  0xD0, 6); // Auxiliary Carry Flag.
 434     SBIT(F0,  0xD0, 5); // User-Defined Flag.
 435     SBIT(RS1, 0xD0, 4); // Register Bank Select 1.
 436     SBIT(RS0, 0xD0, 3); // Register Bank Select 0.
 437     SBIT(OV,  0xD0, 2); // Overflow Flag.
 438     SBIT(P,   0xD0, 0); // Parity Flag.
 439
 440 SFR(A, 0xE0);
 441 SFR(ACC, 0xE0); // Accumulator
 442     SBIT(ACC_0, 0xE0, 0); // Accumulator bit 0.
 443     SBIT(ACC_1, 0xE0, 1); // Accumulator bit 1.
 444     SBIT(ACC_2, 0xE0, 2); // Accumulator bit 2.
 445     SBIT(ACC_3, 0xE0, 3); // Accumulator bit 3.
 446     SBIT(ACC_4, 0xE0, 4); // Accumulator bit 4.
 447     SBIT(ACC_5, 0xE0, 5); // Accumulator bit 5.
 448     SBIT(ACC_6, 0xE0, 6); // Accumulator bit 6.
 449     SBIT(ACC_7, 0xE0, 7); // Accumulator bit 7.
 450
 451 SFR(B, 0xF0); // B Register
 452     SBIT(B_0, 0xF0, 0); // Register B bit 0.
 453     SBIT(B_1, 0xF0, 1); // Register B bit 1.
 454     SBIT(B_2, 0xF0, 2); // Register B bit 2.
 455     SBIT(B_3, 0xF0, 3); // Register B bit 3.
 456     SBIT(B_4, 0xF0, 4); // Register B bit 4.
 457     SBIT(B_5, 0xF0, 5); // Register B bit 5.
 458     SBIT(B_6, 0xF0, 6); // Register B bit 6.
 459     SBIT(B_7, 0xF0, 7); // Register B bit 7.
 460
 461 // PSD registers definition - by Jan Waclawek - wek at efton dot sk - May 2007
 462 // all defines here are with PSD_ prefix to identify them as PSD-related
 463 //
 464 // Based on uPSD33xx datasheet (preliminary) - Jan 2005, Table 79 at pages 145/146
 465 // and subsequent text
 466
 467 // requires to have PSD_CSIOP defined to the base address of the PSD IO area,
 468 //     as defined in PSDSoftExpress or CUPS
 469 #ifndef PSD_CSIOP
 470 #error PSD_CSIOP has to be #define-d (before #include-ing this file) to the base address of the PSD registers area, according to csiop setting in CUPS/PSDSoftExpress
 471 #else
 472                                          //  -- Port A not available on 52-pin uPSD33xx devices
 473 SFRX(PSD_DATAIN_A,    PSD_CSIOP+0x00);   // MCU I/O Mode Port A Data In Register
 474                                          //   reads 0 if pin is log.0, 1 if pin is log. 1
 475                                          //   READ only
 476 SFRX(PSD_DATAOUT_A,   PSD_CSIOP+0x04);   // MCU I/O Mode Port A Data Out Register
 477                                          //   write 0 to set pin to log. 0, 1 to set pin to log. 1
 478                                          //   read back written value
 479                                          //   reset default = 00
 480 SFRX(PSD_DIRECTION_A, PSD_CSIOP+0x06);   // MCU I/O Mode Port A Direction Register
 481                                          //   write 1 to set pin as output, 0 to set pin as input
 482                                          //   read back written value
 483                                          //   reset default = 00
 484 SFRX(PSD_DRIVE_A,     PSD_CSIOP+0x08);   // Select Open Drain or High Slew Rate for port A
 485                                          //   PA0-PA3: write 0 to select standard push-pull CMOS output, 1 to select High Slew Rate push-pull CMOS output
 486                                          //   PA4-PA7: write 0 to select standard push-pull CMOS output, 1 to select Open Drain output
 487                                          //   reset default = 00
 488 SFRX(PSD_CONTROL_A,   PSD_CSIOP+0x02);   // Selects MCU I/O or Latched Address Out mode for port A
 489                                          //   write 0 to select standard I/O pin, 1 to drive demultiplexed address signal on pin
 490                                          //   read back written value
 491                                          //   reset default = 00
 492 SFRX(PSD_OUTENABLE_A, PSD_CSIOP+0x0C);   // Read state of Output Enable Logic on each I/O port driver of Port A
 493                                          //   1 - driver output is enabled, 0 - driver is off (high impedance)
 494                                          //   READ only
 495
 496                                          // -- for comment on individual registers, see above Port A
 497 SFRX(PSD_DATAIN_B,    PSD_CSIOP+0x01);   // MCU I/O Mode Port B Data In Register
 498 SFRX(PSD_DATAOUT_B,   PSD_CSIOP+0x05);   // MCU I/O Mode Port B Data Out Register
 499 SFRX(PSD_DIRECTION_B, PSD_CSIOP+0x07);   // MCU I/O Mode Port B Direction Register
 500 SFRX(PSD_DRIVE_B,     PSD_CSIOP+0x09);   // Select Open Drain or High Slew Rate for port B
 501                                          // PB0-PB3: standard/High Slew Rate, PB4-PB7: standard/Open Drain
 502 SFRX(PSD_CONTROL_B,   PSD_CSIOP+0x03);   // Selects MCU I/O or Latched Address Out mode for port B
 503 SFRX(PSD_OUTENABLE_B, PSD_CSIOP+0x0D);   // Read state of Output Enable Logic on each I/O port driver of Port B
 504
 505                                          // -- for comment on individual registers, see above Port A
 506                                          // only pins PC2, PC3, PC4, PC7 available; other bits in registers are undefined
 507 SFRX(PSD_DATAIN_C,    PSD_CSIOP+0x10);   // MCU I/O Mode Port C Data In Register
 508 SFRX(PSD_DATAOUT_C,   PSD_CSIOP+0x12);   // MCU I/O Mode Port C Data Out Register
 509 SFRX(PSD_DIRECTION_C, PSD_CSIOP+0x14);   // MCU I/O Mode Port C Direction Register
 510 SFRX(PSD_DRIVE_C,     PSD_CSIOP+0x16);   // Select Open Drain for port C
 511 SFRX(PSD_OUTENABLE_C, PSD_CSIOP+0x1A);   // Read state of Output Enable Logic on each I/O port driver of Port C
 512
 513                                          // -- for comment on individual registers, see above Port A
 514                                          // only pins PD1, PD2 available (PD2 not available on 52-pin package); other bits in registers are undefined
 515 SFRX(PSD_DATAIN_D,    PSD_CSIOP+0x11);   // MCU I/O Mode Port D Data In Register
 516 SFRX(PSD_DATAOUT_D,   PSD_CSIOP+0x13);   // MCU I/O Mode Port D Data Out Register
 517 SFRX(PSD_DIRECTION_D, PSD_CSIOP+0x15);   // MCU I/O Mode Port D Direction Register
 518 SFRX(PSD_DRIVE_D,     PSD_CSIOP+0x17);   // Select High Slew Rate for port D
 519 SFRX(PSD_OUTENABLE_D, PSD_CSIOP+0x1B);   // Read state of Output Enable Logic on each I/O port driver of Port D
 520
 521 SFRX(PSD_IMC_A,       PSD_CSIOP+0x0A);   // Read to obtain logic state of Input Macrocells connected to Port A
 522                                          //   READ only
 523 SFRX(PSD_IMC_B,       PSD_CSIOP+0x0B);   // Read to obtain logic state of Input Macrocells connected to Port B
 524 SFRX(PSD_IMC_C,       PSD_CSIOP+0x18);   // Read to obtain logic state of Input Macrocells connected to Port C
 525                                          //   only pins PC2, PC3, PC4, PC7 available; other bits in register are undefined
 526 SFRX(PSD_OMC_AB,      PSD_CSIOP+0x20);   // Read logic state of macrocells AB. Write to load macrocell AB flip-flops.
 527 SFRX(PSD_OMC_BC,      PSD_CSIOP+0x21);   // Read logic state of macrocells BC. Write to load macrocell BC flip-flops.
 528 SFRX(PSD_OMCMASK_AB,  PSD_CSIOP+0x22);   // Write to set mask for macrocell AB.
 529                                          //    1 blocks READs/WRITEs of OMF, 0 will pass OMF value
 530                                          //    Read back written value.
 531 SFRX(PSD_OMCMASK_BC,  PSD_CSIOP+0x23);   // Write to set mask for macrocell BC.
 532
 533 // -- all three Power Management Register are set to 00 after PowerUp, but unchanged during reset (/RST)
 534 SFRX(PSD_PMMR0,       PSD_CSIOP+0xB0);   // -- Power Management Register 0 - write/read
 535 // bit 0 unused and should be set to 0
 536 #define PSD_APD_ENA            0x02      // 0 - Automatic Power Down (APD) counter is disabled, 1 - APD enabled
 537 // bit 2 unused and should be set to 0
 538 #define PSD_TURBO_DISA         0x08      // 0 - PSD Turbo mode enabled, 1 - Turbo mode off, saving power
 539 #define PSD_BLOCK_CLKIN_PLD    0x10      // 0 - CLKIN to PLD not blocked, 1 - no CLKIN to PLD Input Bus, saving power
 540 #define PSD_BLOCK_CLKIN_OMC    0x20      // 0 - CLKIN to Output Macrocells not blocked, 1 - blocked, saving power
 541 // bits 6 and 7 unused and should be set to 0
 542
 543 SFRX(PSD_PMMR2,       PSD_CSIOP+0xB4);   // -- Power Management Register 2 - write/read
 544 // bits 0 and 1 unused and should be set to 0
 545 #define PSD_BLOCK_WR_PLD       0x04      // 0 - /WR from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power
 546 #define PSD_BLOCK_RD_PLD       0x08      // 0 - /RD from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power
 547 #define PSD_BLOCK_PSEN_PLD     0x10      // 0 - /PSEN from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power
 548 #define PSD_BLOCK_ALE_PLD      0x20      // 0 - ALE from 8032 to PLD Input Bus not blocked, 1 - blocked, saving power
 549 #define PSD_BLOCK_PC7_PDL      0x40      // 0 - input from Port C pin 7 to PLD Input Bus not blocked, 1 - blocked, saving power
 550 // bit 7 unused and should be set to 0
 551
 552 SFRX(PSD_PMMR3,       PSD_CSIOP+0xC7);   // -- Power Management Register 3 - write/read
 553 // bit 0 unused and should be set to 0
 554 #define PSD_FORCE_PD           0x02      // 0 - APD counter, if enabled, will cause powerdown, 1 - powerdown will be entered immediately
 555                                          //   - once set, cleared only by reset condition
 556 // bit 2 not defined by datasheet
 557 // bits 3 to 7 unused and should be set to 0
 558
 559 SFRX(PSD_MAINPROTECT, PSD_CSIOP+0xC0);   // -- Main Flash Memory Protection Definition
 560                                          //   bit 0 to bit 7 - sector 0 to sector 7 protection status
 561                                          //      - 1 - flash sector write protected, 0 - not write protected
 562                                          //   READ only
 563 SFRX(PSD_ALTPROTECT,  PSD_CSIOP+0xC2);   // -- Secondary Flash Memory Protection Definition
 564                                          //   bit 0 to bit 3 - sector 0 to sector 3 protection status
 565                                          //      - 1 - flash sector write protected, 0 - not write protected
 566                                          //   bit 7 - Security Bit
 567                                          //      - 1 - device is secured against external reading and writing, 0 - not secured
 568                                          //   READ only
 569
 570 SFRX(PSD_PAGE,        PSD_CSIOP+0xE0);   // -- Memory Page Register
 571
 572 SFRX(PSD_VM,          PSD_CSIOP+0xE2);   // -- Memory Mapping Register
 573                                          //   Places PSD Module memories into 8032 Program Address Space
 574                                          //   and/or 8032 XDATA Address Space
 575                                          //   Default value of bits 0 to 4 is loaded from Non-Volatile
 576                                          //   setting as specified from PSDsoft Express upon any reset
 577                                          //   or power-up condition. The default value of these bits
 578                                          //   can be overridden by 8032 at run-time.
 579 #define PSD_VM_SRAM_CODE       0x01      // 0 - SRAM not accessible as CODE (/PSEN) memory, 1 - SRAM accessible as CODE memory
 580 #define PSD_VM_ALT_CODE        0x02      // 0 - secondary FLASH not accessible as CODE (/PSEN) memory, 1 - secondary FLASH accessible as CODE memory
 581 #define PSD_VM_MAIN_CODE       0x04      // 0 - primary FLASH not accessible as CODE (/PSEN) memory, 1 - primary FLASH accessible as CODE memory
 582 #define PSD_VM_ALT_XDATA       0x08      // 0 - secondary FLASH not accessible as XDATA (/RD/WR) memory, 1 - secondary FLASH accessible as XDATA memory
 583 #define PSD_VM_MAIN_XDATA      0x10      // 0 - primary FLASH not accessible as XDATA (/RD/WR) memory, 1 - primary FLASH accessible as XDATA memory
 584 // bits 5 and 6 unused
 585 #define PSD_VM_PIO_EN          0x80      // 0 - disable, 1- enable peripheral I/O mode on Port A
 586
 587 // another terminology for FLASH - MAIN/ALTERNATIVE -> PRIMARY/SECONDARY
 588 #define PSD_VM_PRI_CODE   PSD_VM_MAIN_CODE
 589 #define PSD_VM_SEC_CODE   PSD_VM_ALT_CODE
 590 #define PSD_VM_PRI_XDATA  PSD_VM_MAIN_XDATA
 591 #define PSD_VM_SEC_XDATA  PSD_VM_ALT_XDATA
 592
 593 #endif
 594
 595 #endif //REG_UPSD33XX_H