sdcc/device/include/xa51/80c51xa.h

   1 /*
   2  *      XA G3 SFR definitions
   3  *      Extracted directly from Philips documentation
   4  */
   5
   6 #ifndef XA_H
   7 #define XA_H
   8
   9 __sfr __at 0x400 /*unsigned short*/ PSW; /* Program status word */
  10 __sfr __at 0x400 PSWL; /* Program status word (low byte) */
  11 __sfr __at 0x401 PSWH; /* Program status word (high byte) */
  12 __sfr __at 0x402 PSW51; /* 80C51 compatible PSW */
  13 __sfr __at 0x403 SSEL; /* Segment selection register */
  14 __sfr __at 0x404 PCON; /* Power control register */
  15 __sfr __at 0x410 TCON; /* Timer 0 and 1 control register */
  16 __sfr __at 0x411 TSTAT; /* Timer 0 and 1 extended status */
  17 __sfr __at 0x418 T2CON; /* Timer 2 control register */
  18 __sfr __at 0x419 T2MOD; /* Timer 2 mode control */
  19 __sfr __at 0x41F WDCON; /* Watchdog control register */
  20 __sfr __at 0x420 S0CON; /* Serial port 0 control register */
  21 __sfr __at 0x421 S0STAT; /* Serial port 0 extended status */
  22 __sfr __at 0x424 S1CON; /* Serial port 1 control register */
  23 __sfr __at 0x425 S1STAT; /* Serial port 1 extended status */
  24 __sfr __at 0x426 IEL; /* Interrupt enable low byte */
  25 __sfr __at 0x427 IEH; /* Interrupt enable high byte */
  26 __sfr __at 0x42A SWR; /* Software Interrupt Request */
  27 __sfr __at 0x430 P0; /* Port 0 */
  28 __sfr __at 0x431 P1; /* Port 1 */
  29 __sfr __at 0x432 P2; /* Port 2 */
  30 __sfr __at 0x433 P3; /* Port3 */
  31 __sfr __at 0x440 SCR; /* System configuration register */
  32 __sfr __at 0x441 DS; /* Data segment */
  33 __sfr __at 0x442 ES; /* Extra segment */
  34 __sfr __at 0x443 CS; /* Code segment */
  35 __sfr __at 0x450 TL0; /* Timer 0 low byte */
  36 __sfr __at 0x451 TH0; /* Timer 0 high byte */
  37 __sfr __at 0x452 TL1; /* Timer 1 low byte */
  38 __sfr __at 0x453 TH1; /* Timer 1 high byte */
  39 __sfr __at 0x454 RTL0; /* Timer 0 extended reload, low byte */
  40 __sfr __at 0x455 RTH0; /* Timer 0 extended reload, high byte */
  41 __sfr __at 0x456 RTL1; /* Timer 1 extended reload, low byte */
  42 __sfr __at 0x457 RTH1; /* Timer 1 extended reload, high byte */
  43 __sfr __at 0x458 TL2; /* Timer 2 low byte */
  44 __sfr __at 0x459 TH2; /* Timer 2 high byte */
  45 __sfr __at 0x45A T2CAPL; /* Timer 2 capture register, low byte */
  46 __sfr __at 0x45B T2CAPH; /* Timer 2 capture register, high byte */
  47 __sfr __at 0x45C TMOD; /* Timer 0 and 1 mode register */
  48 __sfr __at 0x45D WFEED1; /* Watchdog feed 1 */
  49 __sfr __at 0x45E WFEED2; /* Watchdog feed 2 */
  50 __sfr __at 0x45F WDL; /* Watchdog timer reload */
  51 __sfr __at 0x460 S0BUF; /* Serial port 0 buffer register */
  52 __sfr __at 0x461 S0ADDR; /* Serial port 0 address register */
  53 __sfr __at 0x462 S0ADEN; /* Serial port 0 address enable register */
  54 __sfr __at 0x464 S1BUF; /* Serial port 1 buffer register */
  55 __sfr __at 0x465 S1ADDR; /* Serial port 1 address register */
  56 __sfr __at 0x466 S1ADEN; /* Serial port 1 address enable register */
  57 __sfr __at 0x468 BTRL; /* Bus timing register high byte */
  58 __sfr __at 0x469 BTRH; /* Bus timing register low byte */
  59 __sfr __at 0x46A BCR; /* Bus configuration register */
  60 __sfr __at 0x470 P0CFGA; /* Port 0 configuration A */
  61 __sfr __at 0x471 P1CFGA; /* Port 1 configuration A */
  62 __sfr __at 0x472 P2CFGA; /* Port 2 configuration A */
  63 __sfr __at 0x473 P3CFGA; /* Port 3 configuration A */
  64 __sfr __at 0x47A SWE; /* Software Interrupt Enable */
  65 __sfr __at 0x4A0 IPA0; /* Interrupt priority 0 */
  66 __sfr __at 0x4A1 IPA1; /* Interrupt priority 1 */
  67 __sfr __at 0x4A2 IPA2; /* Interrupt priority 2 */
  68 __sfr __at 0x4A4 IPA4; /* Interrupt priority 4 */
  69 __sfr __at 0x4A5 IPA5; /* Interrupt priority 5 */
  70 __sfr __at 0x4F0 P0CFGB; /* Port 0 configuration B */
  71 __sfr __at 0x4F1 P1CFGB; /* Port 1 configuration B */
  72 __sfr __at 0x4F2 P2CFGB; /* Port 2 configuration B */
  73 __sfr __at 0x4F3 P3CFGB; /* Port 3 configuration B */
  74
  75 __sbit __at 0x33B ETI1; /* TX interrupt enable 1 */
  76 __sbit __at 0x33A ERI1; /* RX interrupt enable 1 */
  77 __sbit __at 0x339 ETI0; /* TX interrupt enable 0 */
  78 __sbit __at 0x338 ERI0; /* RX interrupt enable 0 */
  79 __sbit __at 0x337 EA; /* global int. enable */
  80 __sbit __at 0x334 ET2; /* timer 2 interrupt */
  81 __sbit __at 0x333 ET1; /* timer 1 interrupt */
  82 __sbit __at 0x332 EX1; /* external interrupt 1 */
  83 __sbit __at 0x331 ET0; /* timer 0 interrupt */
  84 __sbit __at 0x330 EX0; /* external interrupt 0 */
  85 __sbit __at 0x221 PD; /* power down */
  86 __sbit __at 0x220 IDL;
  87 __sbit __at 0x20F SM;
  88 __sbit __at 0x20E TM;
  89 __sbit __at 0x20D RS1;
  90 __sbit __at 0x20C RS0;
  91 __sbit __at 0x20B IM3;
  92 __sbit __at 0x20A IM2;
  93 __sbit __at 0x209 IM1;
  94 __sbit __at 0x208 IM0;
  95 __sbit __at 0x307 S0M0;
  96 __sbit __at 0x306 S0M1;
  97 __sbit __at 0x305 S0M2;
  98 __sbit __at 0x304 R0EN;
  99 __sbit __at 0x303 T0B8;
 100 __sbit __at 0x302 R0B8;
 101 __sbit __at 0x301 TI0; /* serial port 0 tx ready */
 102 __sbit __at 0x300 RI0; /* serial port 0 rx ready */
 103 __sbit __at 0x30B FE0;
 104 __sbit __at 0x30A BR0;
 105 __sbit __at 0x309 OE0;
 106 __sbit __at 0x308 STINT0;
 107 __sbit __at 0x327 S1M0;
 108 __sbit __at 0x326 S1M1;
 109 __sbit __at 0x325 S1M2;
 110 __sbit __at 0x324 R1EN;
 111 __sbit __at 0x323 T1B8;
 112 __sbit __at 0x322 R1B8;
 113 __sbit __at 0x321 TI1; /* serial port 0 tx ready */
 114 __sbit __at 0x320 RI1; /* serial port 0 rx ready */
 115 __sbit __at 0x32B FE1;
 116 __sbit __at 0x32A BR1;
 117 __sbit __at 0x329 OE1;
 118 __sbit __at 0x328 STINT1;
 119 __sbit __at 0x356 SWR7;
 120 __sbit __at 0x355 SWR6;
 121 __sbit __at 0x354 SWR5;
 122 __sbit __at 0x353 SWR4;
 123 __sbit __at 0x352 SWR3;
 124 __sbit __at 0x351 SWR2;
 125 __sbit __at 0x350 SWR1;
 126 __sbit __at 0x2C7 TF2;
 127 __sbit __at 0x2C6 EXF2;
 128 __sbit __at 0x2C5 RCLK0;
 129 __sbit __at 0x2C4 TCLK0;
 130 __sbit __at 0x2CD RCLK1;
 131 __sbit __at 0x2CC TCLK1;
 132 __sbit __at 0x2C3 EXEN2;
 133 __sbit __at 0x2C2 TR2;
 134 __sbit __at 0x2C1 CT2;
 135 __sbit __at 0x2C0 CPRL2;
 136 __sbit __at 0x2C9 T2OE;
 137 __sbit __at 0x2C8 DCEN;
 138 __sbit __at 0x287 TF1;
 139 __sbit __at 0x286 TR1;
 140 __sbit __at 0x285 TF0;
 141 __sbit __at 0x284 TR0;
 142 __sbit __at 0x283 IE1;
 143 __sbit __at 0x282 IT1;
 144 __sbit __at 0x281 IE0;
 145 __sbit __at 0x280 IT0;
 146 __sbit __at 0x28A T1OE;
 147 __sbit __at 0x288 T0OE;
 148 __sbit __at 0x2FF PRE2;
 149 __sbit __at 0x2FE PRE1;
 150 __sbit __at 0x2FD PRE0;
 151 __sbit __at 0x2FA WDRUN;
 152 __sbit __at 0x2F9 WDTOF;
 153 __sbit __at 0x2F8 WDMOD;
 154 __sbit __at 0x388 WR1;
 155 __sbit __at 0x38F T2EX;
 156 __sbit __at 0x38C RXD1;
 157 __sbit __at 0x38D TXD1;
 158 __sbit __at 0x398 RXD0;
 159 __sbit __at 0x399 TXD0;
 160 __sbit __at 0x39A INT0;
 161 __sbit __at 0x39B INT1;
 162 __sbit __at 0x39C T0;
 163 __sbit __at 0x39D T1;
 164 __sbit __at 0x39E WR;
 165 __sbit __at 0x39F RD;
 166
 167 /*
 168  * Interrupt stuff
 169  */
 170
 171
 172 /* Vectors */
 173
 174 #define IV_BRKPT 0x04 /* breakpoint vector */
 175 #define IV_TRACE 0x08 /* Trace mode bit set */
 176 #define IV_STKOVER 0x0C /* stack overflow */
 177 #define IV_DIVZERO 0x10 /* divide by zero */
 178 #define IV_IRET 0x14 /* user mode IRET */
 179
 180 #define IV_EX0 0x80
 181 #define IV_T0 0x84
 182 #define IV_EX1 0x88
 183 #define IV_T1 0x8C
 184 #define IV_T2 0x90
 185 #define IV_RI0 0xA0
 186 #define IV_TI0 0xA4
 187 #define IV_RI1 0xA8
 188 #define IV_TI1 0xAC
 189 #define IV_SWI1 0x100 /* software interrupts */
 190 #define IV_SWI2 0x104
 191 #define IV_SWI3 0x108
 192 #define IV_SWI4 0x10C
 193 #define IV_SWI5 0x110
 194 #define IV_SWI6 0x114
 195 #define IV_SWI7 0x118
 196
 197 /* PSW Values for interrupt vectors */
 198
 199 #define IV_PSW 0x8F00 /* System mode, high priority, bank 0 */
 200
 201 #define IV_SYSTEM 0x8000
 202
 203 #define IV_PRI00 0x0000 /* priorities 0 - 15 */
 204 #define IV_PRI01 0x0100
 205 #define IV_PRI02 0x0200
 206 #define IV_PRI03 0x0300
 207 #define IV_PRI04 0x0400
 208 #define IV_PRI05 0x0500
 209 #define IV_PRI06 0x0600
 210 #define IV_PRI07 0x0700
 211 #define IV_PRI08 0x0800
 212 #define IV_PRI09 0x0900
 213 #define IV_PRI10 0x0A00
 214 #define IV_PRI11 0x0B00
 215 #define IV_PRI12 0x0C00
 216 #define IV_PRI13 0x0D00
 217 #define IV_PRI14 0x0E00
 218 #define IV_PRI15 0x0F00
 219
 220 #define IV_BANK0 0x0000
 221 #define IV_BANK1 0x1000
 222 #define IV_BANK2 0x2000
 223 #define IV_BANK3 0x3000
 224
 225 #endif /* XA_H */