sdcc/device/lib/r3ka/crt0.s

   1 ;--------------------------------------------------------------------------
   2 ;  crt0.s - Generic crt0.s for a Rabbit 3000A
   3 ;       derived from "Generic crt0.s for a Z80"
   4 ;
   5 ;  Copyright (C) 2000, Michael Hope
   6 ;  Modified for Rabbit by Leland Morrison 2011
   7 ;  Copyright (C) 2020, Philipp Klaus Krause
   8 ;
   9 ;  This library is free software; you can redistribute it and/or modify it
  10 ;  under the terms of the GNU General Public License as published by the
  11 ;  Free Software Foundation; either version 2, or (at your option) any
  12 ;  later version.
  13 ;
  14 ;  This library is distributed in the hope that it will be useful,
  15 ;  but WITHOUT ANY WARRANTY; without even the implied warranty of
  16 ;  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17 ;  GNU General Public License for more details.
  18 ;
  19 ;  You should have received a copy of the GNU General Public License
  20 ;  along with this library; see the file COPYING. If not, write to the
  21 ;  Free Software Foundation, 51 Franklin Street, Fifth Floor, Boston,
  22 ;   MA 02110-1301, USA.
  23 ;
  24 ;  As a special exception, if you link this library with other files,
  25 ;  some of which are compiled with SDCC, to produce an executable,
  26 ;  this library does not by itself cause the resulting executable to
  27 ;  be covered by the GNU General Public License. This exception does
  28 ;  not however invalidate any other reasons why the executable file
  29 ;   might be covered by the GNU General Public License.
  30 ;--------------------------------------------------------------------------
  31
  32         .module crt0
  33         .globl  _main
  34         .globl  ___sdcc_external_startup
  35
  36 GCSR            .equ    0x00 ; Global control / status register
  37 MMIDR           .equ    0x10
  38 STACKSEG        .equ    0x11
  39 SEGSIZE         .equ    0x13
  40 MB0CR           .equ    0x14 ; Memory Bank 0 Control Register
  41 MB1CR           .equ    0x15 ; Memory Bank 1 Control Register
  42 MB2CR           .equ    0x16 ; Memory Bank 2 Control Register
  43 MB3CR           .equ    0x17 ; Memory Bank 3 Control Register
  44
  45         .area   _HEADER (ABS)
  46
  47         ; Reset vector - assuming smode0 and smode1 input pins are grounded
  48         .org    0
  49
  50         ; Setup internal interrupts. Upper byte of interrupt vector table address. Needs to be even.
  51         ld      a, #2
  52         ld      iir, a
  53
  54         ; Configure physical address space.
  55         ; Leave MB0CR Flash at default slow at /OE0, /CS0
  56         ; Assume slow RAM at /CS1, /OE1, /WE1
  57         ld      a, #0x05
  58         ioi
  59         ld      (MB2CR), a;
  60
  61         ; Configure logical address space. 32 KB root segment followed by 8 KB data segment, 16 KB stack segment, 8 KB xpc segment.
  62         ; By default, SDCC will use the root segment for code and constant data, stack segment for data (including stack). data segment and xpc segment are then unused.
  63         ld      a, #0xa8        ; 16 KB stack segment at 0xa000, 8 KB data segment at 0x8000
  64         ioi
  65         ld      (SEGSIZE), a
  66
  67         ; Configure mapping to physical address space.
  68         ld      a, #0x76
  69         ioi
  70         ld      (STACKSEG), a   ; stack segment base at 0x76000 + 0xa000 = 0x80000
  71
  72         ; Set stack pointer directly above top of stack segment
  73         ld      sp, #0xe000
  74
  75         call ___sdcc_external_startup
  76
  77         ; Initialise global variables. Skip if __sdcc_external_startup returned
  78         ; non-zero value. Note: calling convention version 1 only.
  79         or      a, a
  80         jr      NZ, skip_gsinit
  81         call    gsinit
  82 skip_gsinit:
  83
  84         call    _main
  85         jp      _exit
  86
  87         ; Periodic Interrupt
  88         .org    0x200
  89         push    af
  90         ioi
  91         ld      a, (GCSR) ; clear interrupt
  92         pop     af
  93         ipres
  94         ret
  95
  96         ; Secondary Watchdog - Rabbit 3000A only
  97         .org    0x210
  98         ipres
  99         ret
 100
 101         ; rst 0x10
 102         .org    0x220
 103         ret
 104
 105         ; rst 0x18
 106         .org    0x230
 107         ret
 108
 109         ; rst 0x20
 110         .org    0x240
 111         ret
 112
 113         ; rst 0x28
 114         .org    0x250
 115         ret
 116
 117         ; Syscall instruction - Rabbit 3000A only
 118         .org    0x260
 119         ret
 120
 121         ; rst 0x38
 122         .org    0x270
 123         ret
 124
 125         ; Slave Port
 126         .org    0x280
 127         ipres
 128         ret
 129
 130         ; Timer A
 131         .org    0x2a0
 132         ipres
 133         ret
 134
 135         ; Timer B
 136         .org    0x2b0
 137         ipres
 138         ret
 139
 140         ; Serial Port A
 141         .org    0x2c0
 142         ipres
 143         ret
 144
 145         ; Serial Port B
 146         .org    0x2d0
 147         ipres
 148         ret
 149
 150         ; Serial Port C
 151         .org    0x2e0
 152         ipres
 153         ret
 154
 155         ; Serial Port D
 156         .org    0x2f0
 157         ipres
 158         ret
 159
 160         .org    0x300
 161
 162         ;; Ordering of segments for the linker.
 163         .area   _HOME
 164         .area   _CODE
 165         .area   _INITIALIZER
 166         .area   _GSINIT
 167         .area   _GSFINAL
 168
 169         .area   _DATA
 170         .area   _INITIALIZED
 171         .area   _BSEG
 172         .area   _BSS
 173         .area   _HEAP
 174
 175         .area   _CODE
 176 _exit::
 177         ;; Exit - special code to the emulator
 178         ld      a,#0
 179         rst     #0x28
 180 1$:
 181         ;halt           ; opcode for halt used for 'altd' on rabbit processors
 182         jr      1$
 183
 184         .area   _GSINIT
 185 gsinit::
 186         ld      bc, #l__DATA
 187         ld      a, b
 188         or      a, c
 189         jr      Z, zeroed_data
 190         ld      hl,     #s__DATA
 191         ld      (hl), #0x00
 192         dec     bc
 193         ld      a, b
 194         or      a, c
 195         jr      Z, zeroed_data
 196         ld      e, l
 197         ld      d, h
 198         inc     de
 199         ldir
 200
 201 zeroed_data:
 202
 203         ld      bc, #l__INITIALIZER
 204         ld      a, b
 205         or      a, c
 206         jr      Z, gsinit_next
 207         ld      de, #s__INITIALIZED
 208         ld      hl, #s__INITIALIZER
 209         ldir
 210
 211 gsinit_next:
 212
 213         .area   _GSFINAL
 214         ret
 215