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struct / union in initializer, RFE #901.
[sdcc.git] / sdcc / device / non-free / include / pic14 / pic12f635.h
blob41d6a96d34d12acafbc865756a278adbb27e7f79
1 /*
2 * This declarations of the PIC12F635 MCU.
3 *
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
6 *
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:04 UTC.
8 *
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
12 *
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
21 *
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
23 */
24
25 #ifndef __PIC12F635_H__
26 #define __PIC12F635_H__
27
28 //==============================================================================
29 //
30 // Register Addresses
31 //
32 //==============================================================================
33
34 #ifndef NO_ADDR_DEFINES
35
36 #define INDF_ADDR 0x0000
37 #define TMR0_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR_ADDR 0x0004
41 #define GPIO_ADDR 0x0005
42 #define PORTA_ADDR 0x0005
43 #define PCLATH_ADDR 0x000A
44 #define INTCON_ADDR 0x000B
45 #define PIR1_ADDR 0x000C
46 #define TMR1_ADDR 0x000E
47 #define TMR1L_ADDR 0x000E
48 #define TMR1H_ADDR 0x000F
49 #define T1CON_ADDR 0x0010
50 #define WDTCON_ADDR 0x0018
51 #define CMCON0_ADDR 0x0019
52 #define CMCON1_ADDR 0x001A
53 #define OPTION_REG_ADDR 0x0081
54 #define TRISA_ADDR 0x0085
55 #define TRISIO_ADDR 0x0085
56 #define PIE1_ADDR 0x008C
57 #define PCON_ADDR 0x008E
58 #define OSCCON_ADDR 0x008F
59 #define OSCTUNE_ADDR 0x0090
60 #define LVDCON_ADDR 0x0094
61 #define WPUDA_ADDR 0x0095
62 #define IOCA_ADDR 0x0096
63 #define WDA_ADDR 0x0097
64 #define VRCON_ADDR 0x0099
65 #define EEDAT_ADDR 0x009A
66 #define EEDATA_ADDR 0x009A
67 #define EEADR_ADDR 0x009B
68 #define EECON1_ADDR 0x009C
69 #define EECON2_ADDR 0x009D
70 #define CRCON_ADDR 0x0110
71 #define CRDAT0_ADDR 0x0111
72 #define CRDAT1_ADDR 0x0112
73 #define CRDAT2_ADDR 0x0113
74 #define CRDAT3_ADDR 0x0114
75
76 #endif // #ifndef NO_ADDR_DEFINES
77
78 //==============================================================================
79 //
80 // Register Definitions
81 //
82 //==============================================================================
83
84 extern __at(0x0000) __sfr INDF;
85 extern __at(0x0001) __sfr TMR0;
86 extern __at(0x0002) __sfr PCL;
87
88 //==============================================================================
89 // STATUS Bits
90
91 extern __at(0x0003) __sfr STATUS;
92
93 typedef union
94 {
95 struct
96 {
97 unsigned C : 1;
98 unsigned DC : 1;
99 unsigned Z : 1;
100 unsigned NOT_PD : 1;
101 unsigned NOT_TO : 1;
102 unsigned RP0 : 1;
103 unsigned RP1 : 1;
104 unsigned IRP : 1;
105 };
106
107 struct
108 {
109 unsigned : 5;
110 unsigned RP : 2;
111 unsigned : 1;
112 };
113 } __STATUSbits_t;
114
115 extern __at(0x0003) volatile __STATUSbits_t STATUSbits;
116
117 #define _C 0x01
118 #define _DC 0x02
119 #define _Z 0x04
120 #define _NOT_PD 0x08
121 #define _NOT_TO 0x10
122 #define _RP0 0x20
123 #define _RP1 0x40
124 #define _IRP 0x80
125
126 //==============================================================================
127
128 extern __at(0x0004) __sfr FSR;
129
130 //==============================================================================
131 // GPIO Bits
132
133 extern __at(0x0005) __sfr GPIO;
134
135 typedef union
136 {
137 struct
138 {
139 unsigned GP0 : 1;
140 unsigned GP1 : 1;
141 unsigned GP2 : 1;
142 unsigned GP3 : 1;
143 unsigned GP4 : 1;
144 unsigned GP5 : 1;
145 unsigned : 1;
146 unsigned : 1;
147 };
148
149 struct
150 {
151 unsigned RA0 : 1;
152 unsigned RA1 : 1;
153 unsigned RA2 : 1;
154 unsigned RA3 : 1;
155 unsigned RA4 : 1;
156 unsigned RA5 : 1;
157 unsigned : 1;
158 unsigned : 1;
159 };
160
161 struct
162 {
163 unsigned RA : 6;
164 unsigned : 2;
165 };
166
167 struct
168 {
169 unsigned GP : 6;
170 unsigned : 2;
171 };
172 } __GPIObits_t;
173
174 extern __at(0x0005) volatile __GPIObits_t GPIObits;
175
176 #define _GP0 0x01
177 #define _RA0 0x01
178 #define _GP1 0x02
179 #define _RA1 0x02
180 #define _GP2 0x04
181 #define _RA2 0x04
182 #define _GP3 0x08
183 #define _RA3 0x08
184 #define _GP4 0x10
185 #define _RA4 0x10
186 #define _GP5 0x20
187 #define _RA5 0x20
188
189 //==============================================================================
190
191
192 //==============================================================================
193 // PORTA Bits
194
195 extern __at(0x0005) __sfr PORTA;
196
197 typedef union
198 {
199 struct
200 {
201 unsigned GP0 : 1;
202 unsigned GP1 : 1;
203 unsigned GP2 : 1;
204 unsigned GP3 : 1;
205 unsigned GP4 : 1;
206 unsigned GP5 : 1;
207 unsigned : 1;
208 unsigned : 1;
209 };
210
211 struct
212 {
213 unsigned RA0 : 1;
214 unsigned RA1 : 1;
215 unsigned RA2 : 1;
216 unsigned RA3 : 1;
217 unsigned RA4 : 1;
218 unsigned RA5 : 1;
219 unsigned : 1;
220 unsigned : 1;
221 };
222
223 struct
224 {
225 unsigned RA : 6;
226 unsigned : 2;
227 };
228
229 struct
230 {
231 unsigned GP : 6;
232 unsigned : 2;
233 };
234 } __PORTAbits_t;
235
236 extern __at(0x0005) volatile __PORTAbits_t PORTAbits;
237
238 #define _PORTA_GP0 0x01
239 #define _PORTA_RA0 0x01
240 #define _PORTA_GP1 0x02
241 #define _PORTA_RA1 0x02
242 #define _PORTA_GP2 0x04
243 #define _PORTA_RA2 0x04
244 #define _PORTA_GP3 0x08
245 #define _PORTA_RA3 0x08
246 #define _PORTA_GP4 0x10
247 #define _PORTA_RA4 0x10
248 #define _PORTA_GP5 0x20
249 #define _PORTA_RA5 0x20
250
251 //==============================================================================
252
253 extern __at(0x000A) __sfr PCLATH;
254
255 //==============================================================================
256 // INTCON Bits
257
258 extern __at(0x000B) __sfr INTCON;
259
260 typedef struct
261 {
262 unsigned RAIF : 1;
263 unsigned INTF : 1;
264 unsigned T0IF : 1;
265 unsigned RAIE : 1;
266 unsigned INTE : 1;
267 unsigned T0IE : 1;
268 unsigned PEIE : 1;
269 unsigned GIE : 1;
270 } __INTCONbits_t;
271
272 extern __at(0x000B) volatile __INTCONbits_t INTCONbits;
273
274 #define _RAIF 0x01
275 #define _INTF 0x02
276 #define _T0IF 0x04
277 #define _RAIE 0x08
278 #define _INTE 0x10
279 #define _T0IE 0x20
280 #define _PEIE 0x40
281 #define _GIE 0x80
282
283 //==============================================================================
284
285
286 //==============================================================================
287 // PIR1 Bits
288
289 extern __at(0x000C) __sfr PIR1;
290
291 typedef struct
292 {
293 unsigned TMR1IF : 1;
294 unsigned : 1;
295 unsigned OSFIF : 1;
296 unsigned C1IF : 1;
297 unsigned : 1;
298 unsigned CRIF : 1;
299 unsigned LVDIF : 1;
300 unsigned EEIF : 1;
301 } __PIR1bits_t;
302
303 extern __at(0x000C) volatile __PIR1bits_t PIR1bits;
304
305 #define _TMR1IF 0x01
306 #define _OSFIF 0x04
307 #define _C1IF 0x08
308 #define _CRIF 0x20
309 #define _LVDIF 0x40
310 #define _EEIF 0x80
311
312 //==============================================================================
313
314 extern __at(0x000E) __sfr TMR1;
315 extern __at(0x000E) __sfr TMR1L;
316 extern __at(0x000F) __sfr TMR1H;
317
318 //==============================================================================
319 // T1CON Bits
320
321 extern __at(0x0010) __sfr T1CON;
322
323 typedef union
324 {
325 struct
326 {
327 unsigned TMR1ON : 1;
328 unsigned TMR1CS : 1;
329 unsigned NOT_T1SYNC : 1;
330 unsigned T1OSCEN : 1;
331 unsigned T1CKPS0 : 1;
332 unsigned T1CKPS1 : 1;
333 unsigned TMR1GE : 1;
334 unsigned T1GINV : 1;
335 };
336
337 struct
338 {
339 unsigned : 4;
340 unsigned T1CKPS : 2;
341 unsigned : 2;
342 };
343 } __T1CONbits_t;
344
345 extern __at(0x0010) volatile __T1CONbits_t T1CONbits;
346
347 #define _TMR1ON 0x01
348 #define _TMR1CS 0x02
349 #define _NOT_T1SYNC 0x04
350 #define _T1OSCEN 0x08
351 #define _T1CKPS0 0x10
352 #define _T1CKPS1 0x20
353 #define _TMR1GE 0x40
354 #define _T1GINV 0x80
355
356 //==============================================================================
357
358
359 //==============================================================================
360 // WDTCON Bits
361
362 extern __at(0x0018) __sfr WDTCON;
363
364 typedef union
365 {
366 struct
367 {
368 unsigned SWDTEN : 1;
369 unsigned WDTPS0 : 1;
370 unsigned WDTPS1 : 1;
371 unsigned WDTPS2 : 1;
372 unsigned WDTPS3 : 1;
373 unsigned : 1;
374 unsigned : 1;
375 unsigned : 1;
376 };
377
378 struct
379 {
380 unsigned : 1;
381 unsigned WDTPS : 4;
382 unsigned : 3;
383 };
384 } __WDTCONbits_t;
385
386 extern __at(0x0018) volatile __WDTCONbits_t WDTCONbits;
387
388 #define _SWDTEN 0x01
389 #define _WDTPS0 0x02
390 #define _WDTPS1 0x04
391 #define _WDTPS2 0x08
392 #define _WDTPS3 0x10
393
394 //==============================================================================
395
396
397 //==============================================================================
398 // CMCON0 Bits
399
400 extern __at(0x0019) __sfr CMCON0;
401
402 typedef union
403 {
404 struct
405 {
406 unsigned CM0 : 1;
407 unsigned CM1 : 1;
408 unsigned CM2 : 1;
409 unsigned CIS : 1;
410 unsigned CINV : 1;
411 unsigned : 1;
412 unsigned COUT : 1;
413 unsigned : 1;
414 };
415
416 struct
417 {
418 unsigned : 1;
419 unsigned : 1;
420 unsigned : 1;
421 unsigned : 1;
422 unsigned C1INV : 1;
423 unsigned : 1;
424 unsigned C1OUT : 1;
425 unsigned : 1;
426 };
427
428 struct
429 {
430 unsigned CM : 3;
431 unsigned : 5;
432 };
433 } __CMCON0bits_t;
434
435 extern __at(0x0019) volatile __CMCON0bits_t CMCON0bits;
436
437 #define _CM0 0x01
438 #define _CM1 0x02
439 #define _CM2 0x04
440 #define _CIS 0x08
441 #define _CINV 0x10
442 #define _C1INV 0x10
443 #define _COUT 0x40
444 #define _C1OUT 0x40
445
446 //==============================================================================
447
448
449 //==============================================================================
450 // CMCON1 Bits
451
452 extern __at(0x001A) __sfr CMCON1;
453
454 typedef union
455 {
456 struct
457 {
458 unsigned CMSYNC : 1;
459 unsigned T1GSS : 1;
460 unsigned : 1;
461 unsigned : 1;
462 unsigned : 1;
463 unsigned : 1;
464 unsigned : 1;
465 unsigned : 1;
466 };
467
468 struct
469 {
470 unsigned C1SYNC : 1;
471 unsigned : 1;
472 unsigned : 1;
473 unsigned : 1;
474 unsigned : 1;
475 unsigned : 1;
476 unsigned : 1;
477 unsigned : 1;
478 };
479 } __CMCON1bits_t;
480
481 extern __at(0x001A) volatile __CMCON1bits_t CMCON1bits;
482
483 #define _CMSYNC 0x01
484 #define _C1SYNC 0x01
485 #define _T1GSS 0x02
486
487 //==============================================================================
488
489
490 //==============================================================================
491 // OPTION_REG Bits
492
493 extern __at(0x0081) __sfr OPTION_REG;
494
495 typedef union
496 {
497 struct
498 {
499 unsigned PS0 : 1;
500 unsigned PS1 : 1;
501 unsigned PS2 : 1;
502 unsigned PSA : 1;
503 unsigned T0SE : 1;
504 unsigned T0CS : 1;
505 unsigned INTEDG : 1;
506 unsigned NOT_RAPU : 1;
507 };
508
509 struct
510 {
511 unsigned PS : 3;
512 unsigned : 5;
513 };
514 } __OPTION_REGbits_t;
515
516 extern __at(0x0081) volatile __OPTION_REGbits_t OPTION_REGbits;
517
518 #define _PS0 0x01
519 #define _PS1 0x02
520 #define _PS2 0x04
521 #define _PSA 0x08
522 #define _T0SE 0x10
523 #define _T0CS 0x20
524 #define _INTEDG 0x40
525 #define _NOT_RAPU 0x80
526
527 //==============================================================================
528
529
530 //==============================================================================
531 // TRISA Bits
532
533 extern __at(0x0085) __sfr TRISA;
534
535 typedef union
536 {
537 struct
538 {
539 unsigned TRISIO0 : 1;
540 unsigned TRISIO1 : 1;
541 unsigned TRISIO2 : 1;
542 unsigned TRISIO3 : 1;
543 unsigned TRISIO4 : 1;
544 unsigned TRISIO5 : 1;
545 unsigned : 1;
546 unsigned : 1;
547 };
548
549 struct
550 {
551 unsigned TRISA0 : 1;
552 unsigned TRISA1 : 1;
553 unsigned TRISA2 : 1;
554 unsigned TRISA3 : 1;
555 unsigned TRISA4 : 1;
556 unsigned TRISA5 : 1;
557 unsigned : 1;
558 unsigned : 1;
559 };
560
561 struct
562 {
563 unsigned TRISA : 6;
564 unsigned : 2;
565 };
566
567 struct
568 {
569 unsigned TRISIO : 6;
570 unsigned : 2;
571 };
572 } __TRISAbits_t;
573
574 extern __at(0x0085) volatile __TRISAbits_t TRISAbits;
575
576 #define _TRISIO0 0x01
577 #define _TRISA0 0x01
578 #define _TRISIO1 0x02
579 #define _TRISA1 0x02
580 #define _TRISIO2 0x04
581 #define _TRISA2 0x04
582 #define _TRISIO3 0x08
583 #define _TRISA3 0x08
584 #define _TRISIO4 0x10
585 #define _TRISA4 0x10
586 #define _TRISIO5 0x20
587 #define _TRISA5 0x20
588
589 //==============================================================================
590
591
592 //==============================================================================
593 // TRISIO Bits
594
595 extern __at(0x0085) __sfr TRISIO;
596
597 typedef union
598 {
599 struct
600 {
601 unsigned TRISIO0 : 1;
602 unsigned TRISIO1 : 1;
603 unsigned TRISIO2 : 1;
604 unsigned TRISIO3 : 1;
605 unsigned TRISIO4 : 1;
606 unsigned TRISIO5 : 1;
607 unsigned : 1;
608 unsigned : 1;
609 };
610
611 struct
612 {
613 unsigned TRISA0 : 1;
614 unsigned TRISA1 : 1;
615 unsigned TRISA2 : 1;
616 unsigned TRISA3 : 1;
617 unsigned TRISA4 : 1;
618 unsigned TRISA5 : 1;
619 unsigned : 1;
620 unsigned : 1;
621 };
622
623 struct
624 {
625 unsigned TRISIO : 6;
626 unsigned : 2;
627 };
628
629 struct
630 {
631 unsigned TRISA : 6;
632 unsigned : 2;
633 };
634 } __TRISIObits_t;
635
636 extern __at(0x0085) volatile __TRISIObits_t TRISIObits;
637
638 #define _TRISIO_TRISIO0 0x01
639 #define _TRISIO_TRISA0 0x01
640 #define _TRISIO_TRISIO1 0x02
641 #define _TRISIO_TRISA1 0x02
642 #define _TRISIO_TRISIO2 0x04
643 #define _TRISIO_TRISA2 0x04
644 #define _TRISIO_TRISIO3 0x08
645 #define _TRISIO_TRISA3 0x08
646 #define _TRISIO_TRISIO4 0x10
647 #define _TRISIO_TRISA4 0x10
648 #define _TRISIO_TRISIO5 0x20
649 #define _TRISIO_TRISA5 0x20
650
651 //==============================================================================
652
653
654 //==============================================================================
655 // PIE1 Bits
656
657 extern __at(0x008C) __sfr PIE1;
658
659 typedef struct
660 {
661 unsigned TMR1IE : 1;
662 unsigned : 1;
663 unsigned OSFIE : 1;
664 unsigned C1IE : 1;
665 unsigned : 1;
666 unsigned CRIE : 1;
667 unsigned LVDIE : 1;
668 unsigned EEIE : 1;
669 } __PIE1bits_t;
670
671 extern __at(0x008C) volatile __PIE1bits_t PIE1bits;
672
673 #define _TMR1IE 0x01
674 #define _OSFIE 0x04
675 #define _C1IE 0x08
676 #define _CRIE 0x20
677 #define _LVDIE 0x40
678 #define _EEIE 0x80
679
680 //==============================================================================
681
682
683 //==============================================================================
684 // PCON Bits
685
686 extern __at(0x008E) __sfr PCON;
687
688 typedef union
689 {
690 struct
691 {
692 unsigned NOT_BOR : 1;
693 unsigned NOT_POR : 1;
694 unsigned : 1;
695 unsigned NOT_WUR : 1;
696 unsigned SBOREN : 1;
697 unsigned ULPWUE : 1;
698 unsigned : 1;
699 unsigned : 1;
700 };
701
702 struct
703 {
704 unsigned NOT_BOD : 1;
705 unsigned : 1;
706 unsigned : 1;
707 unsigned : 1;
708 unsigned SBODEN : 1;
709 unsigned : 1;
710 unsigned : 1;
711 unsigned : 1;
712 };
713 } __PCONbits_t;
714
715 extern __at(0x008E) volatile __PCONbits_t PCONbits;
716
717 #define _NOT_BOR 0x01
718 #define _NOT_BOD 0x01
719 #define _NOT_POR 0x02
720 #define _NOT_WUR 0x08
721 #define _SBOREN 0x10
722 #define _SBODEN 0x10
723 #define _ULPWUE 0x20
724
725 //==============================================================================
726
727
728 //==============================================================================
729 // OSCCON Bits
730
731 extern __at(0x008F) __sfr OSCCON;
732
733 typedef union
734 {
735 struct
736 {
737 unsigned SCS : 1;
738 unsigned LTS : 1;
739 unsigned HTS : 1;
740 unsigned OSTS : 1;
741 unsigned IRCF0 : 1;
742 unsigned IRCF1 : 1;
743 unsigned IRCF2 : 1;
744 unsigned : 1;
745 };
746
747 struct
748 {
749 unsigned : 4;
750 unsigned IRCF : 3;
751 unsigned : 1;
752 };
753 } __OSCCONbits_t;
754
755 extern __at(0x008F) volatile __OSCCONbits_t OSCCONbits;
756
757 #define _SCS 0x01
758 #define _LTS 0x02
759 #define _HTS 0x04
760 #define _OSTS 0x08
761 #define _IRCF0 0x10
762 #define _IRCF1 0x20
763 #define _IRCF2 0x40
764
765 //==============================================================================
766
767
768 //==============================================================================
769 // OSCTUNE Bits
770
771 extern __at(0x0090) __sfr OSCTUNE;
772
773 typedef union
774 {
775 struct
776 {
777 unsigned TUN0 : 1;
778 unsigned TUN1 : 1;
779 unsigned TUN2 : 1;
780 unsigned TUN3 : 1;
781 unsigned TUN4 : 1;
782 unsigned : 1;
783 unsigned : 1;
784 unsigned : 1;
785 };
786
787 struct
788 {
789 unsigned TUN : 5;
790 unsigned : 3;
791 };
792 } __OSCTUNEbits_t;
793
794 extern __at(0x0090) volatile __OSCTUNEbits_t OSCTUNEbits;
795
796 #define _TUN0 0x01
797 #define _TUN1 0x02
798 #define _TUN2 0x04
799 #define _TUN3 0x08
800 #define _TUN4 0x10
801
802 //==============================================================================
803
804
805 //==============================================================================
806 // LVDCON Bits
807
808 extern __at(0x0094) __sfr LVDCON;
809
810 typedef union
811 {
812 struct
813 {
814 unsigned LVDL0 : 1;
815 unsigned LVDL1 : 1;
816 unsigned LVDL2 : 1;
817 unsigned : 1;
818 unsigned LVDEN : 1;
819 unsigned IRVST : 1;
820 unsigned : 1;
821 unsigned : 1;
822 };
823
824 struct
825 {
826 unsigned : 1;
827 unsigned : 1;
828 unsigned : 1;
829 unsigned : 1;
830 unsigned PLVDEN : 1;
831 unsigned : 1;
832 unsigned : 1;
833 unsigned : 1;
834 };
835
836 struct
837 {
838 unsigned LVDL : 3;
839 unsigned : 5;
840 };
841 } __LVDCONbits_t;
842
843 extern __at(0x0094) volatile __LVDCONbits_t LVDCONbits;
844
845 #define _LVDL0 0x01
846 #define _LVDL1 0x02
847 #define _LVDL2 0x04
848 #define _LVDEN 0x10
849 #define _PLVDEN 0x10
850 #define _IRVST 0x20
851
852 //==============================================================================
853
854
855 //==============================================================================
856 // WPUDA Bits
857
858 extern __at(0x0095) __sfr WPUDA;
859
860 typedef struct
861 {
862 unsigned WPUDA0 : 1;
863 unsigned WPUDA1 : 1;
864 unsigned WPUDA2 : 1;
865 unsigned : 1;
866 unsigned WPUDA4 : 1;
867 unsigned WPUDA5 : 1;
868 unsigned : 1;
869 unsigned : 1;
870 } __WPUDAbits_t;
871
872 extern __at(0x0095) volatile __WPUDAbits_t WPUDAbits;
873
874 #define _WPUDA0 0x01
875 #define _WPUDA1 0x02
876 #define _WPUDA2 0x04
877 #define _WPUDA4 0x10
878 #define _WPUDA5 0x20
879
880 //==============================================================================
881
882
883 //==============================================================================
884 // IOCA Bits
885
886 extern __at(0x0096) __sfr IOCA;
887
888 typedef union
889 {
890 struct
891 {
892 unsigned IOCA0 : 1;
893 unsigned IOCA1 : 1;
894 unsigned IOCA2 : 1;
895 unsigned IOCA3 : 1;
896 unsigned IOCA4 : 1;
897 unsigned IOCA5 : 1;
898 unsigned : 1;
899 unsigned : 1;
900 };
901
902 struct
903 {
904 unsigned IOCA : 6;
905 unsigned : 2;
906 };
907 } __IOCAbits_t;
908
909 extern __at(0x0096) volatile __IOCAbits_t IOCAbits;
910
911 #define _IOCA0 0x01
912 #define _IOCA1 0x02
913 #define _IOCA2 0x04
914 #define _IOCA3 0x08
915 #define _IOCA4 0x10
916 #define _IOCA5 0x20
917
918 //==============================================================================
919
920
921 //==============================================================================
922 // WDA Bits
923
924 extern __at(0x0097) __sfr WDA;
925
926 typedef struct
927 {
928 unsigned WDA0 : 1;
929 unsigned WDA1 : 1;
930 unsigned WDA2 : 1;
931 unsigned : 1;
932 unsigned WDA4 : 1;
933 unsigned WDA5 : 1;
934 unsigned : 1;
935 unsigned : 1;
936 } __WDAbits_t;
937
938 extern __at(0x0097) volatile __WDAbits_t WDAbits;
939
940 #define _WDA0 0x01
941 #define _WDA1 0x02
942 #define _WDA2 0x04
943 #define _WDA4 0x10
944 #define _WDA5 0x20
945
946 //==============================================================================
947
948
949 //==============================================================================
950 // VRCON Bits
951
952 extern __at(0x0099) __sfr VRCON;
953
954 typedef union
955 {
956 struct
957 {
958 unsigned VR0 : 1;
959 unsigned VR1 : 1;
960 unsigned VR2 : 1;
961 unsigned VR3 : 1;
962 unsigned : 1;
963 unsigned VRR : 1;
964 unsigned : 1;
965 unsigned VREN : 1;
966 };
967
968 struct
969 {
970 unsigned VR : 4;
971 unsigned : 4;
972 };
973 } __VRCONbits_t;
974
975 extern __at(0x0099) volatile __VRCONbits_t VRCONbits;
976
977 #define _VR0 0x01
978 #define _VR1 0x02
979 #define _VR2 0x04
980 #define _VR3 0x08
981 #define _VRR 0x20
982 #define _VREN 0x80
983
984 //==============================================================================
985
986 extern __at(0x009A) __sfr EEDAT;
987 extern __at(0x009A) __sfr EEDATA;
988 extern __at(0x009B) __sfr EEADR;
989
990 //==============================================================================
991 // EECON1 Bits
992
993 extern __at(0x009C) __sfr EECON1;
994
995 typedef struct
996 {
997 unsigned RD : 1;
998 unsigned WR : 1;
999 unsigned WREN : 1;
1000 unsigned WRERR : 1;
1001 unsigned : 1;
1002 unsigned : 1;
1003 unsigned : 1;
1004 unsigned : 1;
1005 } __EECON1bits_t;
1006
1007 extern __at(0x009C) volatile __EECON1bits_t EECON1bits;
1008
1009 #define _RD 0x01
1010 #define _WR 0x02
1011 #define _WREN 0x04
1012 #define _WRERR 0x08
1013
1014 //==============================================================================
1015
1016 extern __at(0x009D) __sfr EECON2;
1017
1018 //==============================================================================
1019 // CRCON Bits
1020
1021 extern __at(0x0110) __sfr CRCON;
1022
1023 typedef union
1024 {
1025 struct
1026 {
1027 unsigned CRREG0 : 1;
1028 unsigned CRREG1 : 1;
1029 unsigned : 1;
1030 unsigned : 1;
1031 unsigned : 1;
1032 unsigned : 1;
1033 unsigned ENC_NOT_DEC : 1;
1034 unsigned GO_NOT_DONE : 1;
1035 };
1036
1037 struct
1038 {
1039 unsigned : 1;
1040 unsigned : 1;
1041 unsigned : 1;
1042 unsigned : 1;
1043 unsigned : 1;
1044 unsigned : 1;
1045 unsigned ENC_DEC : 1;
1046 unsigned GO : 1;
1047 };
1048
1049 struct
1050 {
1051 unsigned CRREG : 2;
1052 unsigned : 6;
1053 };
1054 } __CRCONbits_t;
1055
1056 extern __at(0x0110) volatile __CRCONbits_t CRCONbits;
1057
1058 #define _CRREG0 0x01
1059 #define _CRREG1 0x02
1060 #define _ENC_NOT_DEC 0x40
1061 #define _ENC_DEC 0x40
1062 #define _GO_NOT_DONE 0x80
1063 #define _GO 0x80
1064
1065 //==============================================================================
1066
1067 extern __at(0x0111) __sfr CRDAT0;
1068 extern __at(0x0112) __sfr CRDAT1;
1069 extern __at(0x0113) __sfr CRDAT2;
1070 extern __at(0x0114) __sfr CRDAT3;
1071
1072 //==============================================================================
1073 //
1074 // Configuration Bits
1075 //
1076 //==============================================================================
1077
1078 #define _CONFIG 0x2007
1079
1080 //----------------------------- CONFIG Options -------------------------------
1081
1082 #define _FOSC_LP 0x3FF8 // LP oscillator: Low-power crystal on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT.
1083 #define _LP_OSC 0x3FF8 // LP oscillator: Low-power crystal on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT.
1084 #define _FOSC_XT 0x3FF9 // XT oscillator: Crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT.
1085 #define _XT_OSC 0x3FF9 // XT oscillator: Crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT.
1086 #define _FOSC_HS 0x3FFA // HS oscillator: High-speed crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT.
1087 #define _HS_OSC 0x3FFA // HS oscillator: High-speed crystal/resonator on RA5/T1CKI/OSC1/CLKIN and RA4/T1G/OSC2/CLKOUT.
1088 #define _FOSC_EC 0x3FFB // EC: I/O function on RA4/T1G/OSC2/CLKOUT, CLKIN on RA5/T1CKI/OSC1/CLKIN.
1089 #define _EC_OSC 0x3FFB // EC: I/O function on RA4/T1G/OSC2/CLKOUT, CLKIN on RA5/T1CKI/OSC1/CLKIN.
1090 #define _FOSC_INTOSCIO 0x3FFC // INTOSCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT pin, I/O function on RA5/T1CKI/OSC1/CLKIN.
1091 #define _INTRC_OSC_NOCLKOUT 0x3FFC // INTOSCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT pin, I/O function on RA5/T1CKI/OSC1/CLKIN.
1092 #define _FOSC_INTOSCCLK 0x3FFD // INTOSC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT pin, I/O function on RA5/T1CKI/OSC1/CLKIN.
1093 #define _INTRC_OSC_CLKOUT 0x3FFD // INTOSC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT pin, I/O function on RA5/T1CKI/OSC1/CLKIN.
1094 #define _FOSC_EXTRCIO 0x3FFE // RCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN.
1095 #define _EXTRC_OSC_NOCLKOUT 0x3FFE // RCIO oscillator: I/O function on RA4/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN.
1096 #define _FOSC_EXTRCCLK 0x3FFF // RC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN.
1097 #define _EXTRC_OSC_CLKOUT 0x3FFF // RC oscillator: CLKOUT function on RA4/T1G/OSC2/CLKOUT pin, RC on RA5/T1CKI/OSC1/CLKIN.
1098 #define _WDTE_OFF 0x3FF7 // WDT disabled and can be enabled by SWDTEN bit of the WDTCON register.
1099 #define _WDT_OFF 0x3FF7 // WDT disabled and can be enabled by SWDTEN bit of the WDTCON register.
1100 #define _WDTE_ON 0x3FFF // WDT enabled.
1101 #define _WDT_ON 0x3FFF // WDT enabled.
1102 #define _PWRTE_ON 0x3FEF // PWRT enabled.
1103 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
1104 #define _MCLRE_OFF 0x3FDF // MCLR pin function is alternate function, MCLR function is internally disabled.
1105 #define _MCLRE_ON 0x3FFF // MCLR pin is MCLR function and weak internal pull-up is enabled.
1106 #define _CP_ON 0x3FBF // Program memory is external read and write-protected.
1107 #define _CP_OFF 0x3FFF // Program memory is not code protected.
1108 #define _CPD_ON 0x3F7F // Data memory is external read protected.
1109 #define _CPD_OFF 0x3FFF // Data memory is not code protected.
1110 #define _BOREN_OFF 0x3CFF // BOD and SBODEN disabled.
1111 #define _BOD_OFF 0x3CFF // BOD and SBODEN disabled.
1112 #define _BOREN_SBODEN 0x3DFF // SBODEN controls BOD function.
1113 #define _BOD_SBODEN 0x3DFF // SBODEN controls BOD function.
1114 #define _BOREN_NSLEEP 0x3EFF // BOD enabled while running and disabled in Sleep. SBODEN bit disabled.
1115 #define _BOD_NSLEEP 0x3EFF // BOD enabled while running and disabled in Sleep. SBODEN bit disabled.
1116 #define _BOREN_ON 0x3FFF // BOD enabled and SBOdEN bit disabled.
1117 #define _BOD_ON 0x3FFF // BOD enabled and SBOdEN bit disabled.
1118 #define _IESO_OFF 0x3BFF // Internal External Switchover mode disabled.
1119 #define _IESO_ON 0x3FFF // Internal External Switchover mode enabled.
1120 #define _FCMEN_OFF 0x37FF // Fail-Safe Clock Monitor disabled.
1121 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor enabled.
1122 #define _WURE_ON 0x2FFF // Wake-up and Reset enabled.
1123 #define _WUREN_ON 0x2FFF // Wake-up and Reset enabled.
1124 #define _WURE_OFF 0x3FFF // Standard wake-up and continue enabled.
1125 #define _WUREN_OFF 0x3FFF // Standard wake-up and continue enabled.
1126
1127 //==============================================================================
1128
1129 #define _DEVID1 0x2006
1130
1131 #define _IDLOC0 0x2000
1132 #define _IDLOC1 0x2001
1133 #define _IDLOC2 0x2002
1134 #define _IDLOC3 0x2003
1135
1136 //==============================================================================
1137
1138 #ifndef NO_BIT_DEFINES
1139
1140 #define CM0 CMCON0bits.CM0 // bit 0
1141 #define CM1 CMCON0bits.CM1 // bit 1
1142 #define CM2 CMCON0bits.CM2 // bit 2
1143 #define CIS CMCON0bits.CIS // bit 3
1144 #define CINV CMCON0bits.CINV // bit 4, shadows bit in CMCON0bits
1145 #define C1INV CMCON0bits.C1INV // bit 4, shadows bit in CMCON0bits
1146 #define COUT CMCON0bits.COUT // bit 6, shadows bit in CMCON0bits
1147 #define C1OUT CMCON0bits.C1OUT // bit 6, shadows bit in CMCON0bits
1148
1149 #define CMSYNC CMCON1bits.CMSYNC // bit 0, shadows bit in CMCON1bits
1150 #define C1SYNC CMCON1bits.C1SYNC // bit 0, shadows bit in CMCON1bits
1151 #define T1GSS CMCON1bits.T1GSS // bit 1
1152
1153 #define CRREG0 CRCONbits.CRREG0 // bit 0
1154 #define CRREG1 CRCONbits.CRREG1 // bit 1
1155 #define ENC_NOT_DEC CRCONbits.ENC_NOT_DEC // bit 6, shadows bit in CRCONbits
1156 #define ENC_DEC CRCONbits.ENC_DEC // bit 6, shadows bit in CRCONbits
1157 #define GO_NOT_DONE CRCONbits.GO_NOT_DONE // bit 7, shadows bit in CRCONbits
1158 #define GO CRCONbits.GO // bit 7, shadows bit in CRCONbits
1159
1160 #define RD EECON1bits.RD // bit 0
1161 #define WR EECON1bits.WR // bit 1
1162 #define WREN EECON1bits.WREN // bit 2
1163 #define WRERR EECON1bits.WRERR // bit 3
1164
1165 #define GP0 GPIObits.GP0 // bit 0, shadows bit in GPIObits
1166 #define RA0 GPIObits.RA0 // bit 0, shadows bit in GPIObits
1167 #define GP1 GPIObits.GP1 // bit 1, shadows bit in GPIObits
1168 #define RA1 GPIObits.RA1 // bit 1, shadows bit in GPIObits
1169 #define GP2 GPIObits.GP2 // bit 2, shadows bit in GPIObits
1170 #define RA2 GPIObits.RA2 // bit 2, shadows bit in GPIObits
1171 #define GP3 GPIObits.GP3 // bit 3, shadows bit in GPIObits
1172 #define RA3 GPIObits.RA3 // bit 3, shadows bit in GPIObits
1173 #define GP4 GPIObits.GP4 // bit 4, shadows bit in GPIObits
1174 #define RA4 GPIObits.RA4 // bit 4, shadows bit in GPIObits
1175 #define GP5 GPIObits.GP5 // bit 5, shadows bit in GPIObits
1176 #define RA5 GPIObits.RA5 // bit 5, shadows bit in GPIObits
1177
1178 #define RAIF INTCONbits.RAIF // bit 0
1179 #define INTF INTCONbits.INTF // bit 1
1180 #define T0IF INTCONbits.T0IF // bit 2
1181 #define RAIE INTCONbits.RAIE // bit 3
1182 #define INTE INTCONbits.INTE // bit 4
1183 #define T0IE INTCONbits.T0IE // bit 5
1184 #define PEIE INTCONbits.PEIE // bit 6
1185 #define GIE INTCONbits.GIE // bit 7
1186
1187 #define IOCA0 IOCAbits.IOCA0 // bit 0
1188 #define IOCA1 IOCAbits.IOCA1 // bit 1
1189 #define IOCA2 IOCAbits.IOCA2 // bit 2
1190 #define IOCA3 IOCAbits.IOCA3 // bit 3
1191 #define IOCA4 IOCAbits.IOCA4 // bit 4
1192 #define IOCA5 IOCAbits.IOCA5 // bit 5
1193
1194 #define LVDL0 LVDCONbits.LVDL0 // bit 0
1195 #define LVDL1 LVDCONbits.LVDL1 // bit 1
1196 #define LVDL2 LVDCONbits.LVDL2 // bit 2
1197 #define LVDEN LVDCONbits.LVDEN // bit 4, shadows bit in LVDCONbits
1198 #define PLVDEN LVDCONbits.PLVDEN // bit 4, shadows bit in LVDCONbits
1199 #define IRVST LVDCONbits.IRVST // bit 5
1200
1201 #define PS0 OPTION_REGbits.PS0 // bit 0
1202 #define PS1 OPTION_REGbits.PS1 // bit 1
1203 #define PS2 OPTION_REGbits.PS2 // bit 2
1204 #define PSA OPTION_REGbits.PSA // bit 3
1205 #define T0SE OPTION_REGbits.T0SE // bit 4
1206 #define T0CS OPTION_REGbits.T0CS // bit 5
1207 #define INTEDG OPTION_REGbits.INTEDG // bit 6
1208 #define NOT_RAPU OPTION_REGbits.NOT_RAPU // bit 7
1209
1210 #define SCS OSCCONbits.SCS // bit 0
1211 #define LTS OSCCONbits.LTS // bit 1
1212 #define HTS OSCCONbits.HTS // bit 2
1213 #define OSTS OSCCONbits.OSTS // bit 3
1214 #define IRCF0 OSCCONbits.IRCF0 // bit 4
1215 #define IRCF1 OSCCONbits.IRCF1 // bit 5
1216 #define IRCF2 OSCCONbits.IRCF2 // bit 6
1217
1218 #define TUN0 OSCTUNEbits.TUN0 // bit 0
1219 #define TUN1 OSCTUNEbits.TUN1 // bit 1
1220 #define TUN2 OSCTUNEbits.TUN2 // bit 2
1221 #define TUN3 OSCTUNEbits.TUN3 // bit 3
1222 #define TUN4 OSCTUNEbits.TUN4 // bit 4
1223
1224 #define NOT_BOR PCONbits.NOT_BOR // bit 0, shadows bit in PCONbits
1225 #define NOT_BOD PCONbits.NOT_BOD // bit 0, shadows bit in PCONbits
1226 #define NOT_POR PCONbits.NOT_POR // bit 1
1227 #define NOT_WUR PCONbits.NOT_WUR // bit 3
1228 #define SBOREN PCONbits.SBOREN // bit 4, shadows bit in PCONbits
1229 #define SBODEN PCONbits.SBODEN // bit 4, shadows bit in PCONbits
1230 #define ULPWUE PCONbits.ULPWUE // bit 5
1231
1232 #define TMR1IE PIE1bits.TMR1IE // bit 0
1233 #define OSFIE PIE1bits.OSFIE // bit 2
1234 #define C1IE PIE1bits.C1IE // bit 3
1235 #define CRIE PIE1bits.CRIE // bit 5
1236 #define LVDIE PIE1bits.LVDIE // bit 6
1237 #define EEIE PIE1bits.EEIE // bit 7
1238
1239 #define TMR1IF PIR1bits.TMR1IF // bit 0
1240 #define OSFIF PIR1bits.OSFIF // bit 2
1241 #define C1IF PIR1bits.C1IF // bit 3
1242 #define CRIF PIR1bits.CRIF // bit 5
1243 #define LVDIF PIR1bits.LVDIF // bit 6
1244 #define EEIF PIR1bits.EEIF // bit 7
1245
1246 #define C STATUSbits.C // bit 0
1247 #define DC STATUSbits.DC // bit 1
1248 #define Z STATUSbits.Z // bit 2
1249 #define NOT_PD STATUSbits.NOT_PD // bit 3
1250 #define NOT_TO STATUSbits.NOT_TO // bit 4
1251 #define RP0 STATUSbits.RP0 // bit 5
1252 #define RP1 STATUSbits.RP1 // bit 6
1253 #define IRP STATUSbits.IRP // bit 7
1254
1255 #define TMR1ON T1CONbits.TMR1ON // bit 0
1256 #define TMR1CS T1CONbits.TMR1CS // bit 1
1257 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
1258 #define T1OSCEN T1CONbits.T1OSCEN // bit 3
1259 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
1260 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
1261 #define TMR1GE T1CONbits.TMR1GE // bit 6
1262 #define T1GINV T1CONbits.T1GINV // bit 7
1263
1264 #define TRISIO0 TRISAbits.TRISIO0 // bit 0, shadows bit in TRISAbits
1265 #define TRISA0 TRISAbits.TRISA0 // bit 0, shadows bit in TRISAbits
1266 #define TRISIO1 TRISAbits.TRISIO1 // bit 1, shadows bit in TRISAbits
1267 #define TRISA1 TRISAbits.TRISA1 // bit 1, shadows bit in TRISAbits
1268 #define TRISIO2 TRISAbits.TRISIO2 // bit 2, shadows bit in TRISAbits
1269 #define TRISA2 TRISAbits.TRISA2 // bit 2, shadows bit in TRISAbits
1270 #define TRISIO3 TRISAbits.TRISIO3 // bit 3, shadows bit in TRISAbits
1271 #define TRISA3 TRISAbits.TRISA3 // bit 3, shadows bit in TRISAbits
1272 #define TRISIO4 TRISAbits.TRISIO4 // bit 4, shadows bit in TRISAbits
1273 #define TRISA4 TRISAbits.TRISA4 // bit 4, shadows bit in TRISAbits
1274 #define TRISIO5 TRISAbits.TRISIO5 // bit 5, shadows bit in TRISAbits
1275 #define TRISA5 TRISAbits.TRISA5 // bit 5, shadows bit in TRISAbits
1276
1277 #define VR0 VRCONbits.VR0 // bit 0
1278 #define VR1 VRCONbits.VR1 // bit 1
1279 #define VR2 VRCONbits.VR2 // bit 2
1280 #define VR3 VRCONbits.VR3 // bit 3
1281 #define VRR VRCONbits.VRR // bit 5
1282 #define VREN VRCONbits.VREN // bit 7
1283
1284 #define WDA0 WDAbits.WDA0 // bit 0
1285 #define WDA1 WDAbits.WDA1 // bit 1
1286 #define WDA2 WDAbits.WDA2 // bit 2
1287 #define WDA4 WDAbits.WDA4 // bit 4
1288 #define WDA5 WDAbits.WDA5 // bit 5
1289
1290 #define SWDTEN WDTCONbits.SWDTEN // bit 0
1291 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
1292 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
1293 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
1294 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
1295
1296 #define WPUDA0 WPUDAbits.WPUDA0 // bit 0
1297 #define WPUDA1 WPUDAbits.WPUDA1 // bit 1
1298 #define WPUDA2 WPUDAbits.WPUDA2 // bit 2
1299 #define WPUDA4 WPUDAbits.WPUDA4 // bit 4
1300 #define WPUDA5 WPUDAbits.WPUDA5 // bit 5
1301
1302 #endif // #ifndef NO_BIT_DEFINES
1303
1304 #endif // #ifndef __PIC12F635_H__
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