2 * This declarations of the PIC12HV752 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:04 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC12HV752_H__
26 #define __PIC12HV752_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF_ADDR 0x0000
37 #define TMR0_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR_ADDR 0x0004
41 #define PORTA_ADDR 0x0005
42 #define IOCAF_ADDR 0x0008
43 #define PCLATH_ADDR 0x000A
44 #define INTCON_ADDR 0x000B
45 #define PIR1_ADDR 0x000C
46 #define PIR2_ADDR 0x000D
47 #define TMR1_ADDR 0x000F
48 #define TMR1L_ADDR 0x000F
49 #define TMR1H_ADDR 0x0010
50 #define T1CON_ADDR 0x0011
51 #define T1GCON_ADDR 0x0012
52 #define CCPR1_ADDR 0x0013
53 #define CCPR1L_ADDR 0x0013
54 #define CCPR1H_ADDR 0x0014
55 #define CCP1CON_ADDR 0x0015
56 #define ADRES_ADDR 0x001C
57 #define ADRESL_ADDR 0x001C
58 #define ADRESH_ADDR 0x001D
59 #define ADCON0_ADDR 0x001E
60 #define ADCON1_ADDR 0x001F
61 #define OPTION_REG_ADDR 0x0081
62 #define TRISA_ADDR 0x0085
63 #define IOCAP_ADDR 0x0088
64 #define PIE1_ADDR 0x008C
65 #define PIE2_ADDR 0x008D
66 #define OSCCON_ADDR 0x008F
67 #define FVRCON_ADDR 0x0090
68 #define DACCON0_ADDR 0x0091
69 #define DACCON1_ADDR 0x0092
70 #define C2CON0_ADDR 0x009B
71 #define CM2CON0_ADDR 0x009B
72 #define C2CON1_ADDR 0x009C
73 #define CM2CON1_ADDR 0x009C
74 #define C1CON0_ADDR 0x009D
75 #define CM1CON0_ADDR 0x009D
76 #define C1CON1_ADDR 0x009E
77 #define CM1CON1_ADDR 0x009E
78 #define CMOUT_ADDR 0x009F
79 #define MCOUT_ADDR 0x009F
80 #define LATA_ADDR 0x0105
81 #define IOCAN_ADDR 0x0108
82 #define WPUA_ADDR 0x010C
83 #define SLRCONA_ADDR 0x010D
84 #define PCON_ADDR 0x010F
85 #define TMR2_ADDR 0x0110
86 #define PR2_ADDR 0x0111
87 #define T2CON_ADDR 0x0112
88 #define HLTMR1_ADDR 0x0113
89 #define HLTPR1_ADDR 0x0114
90 #define HLT1CON0_ADDR 0x0115
91 #define HLT1CON1_ADDR 0x0116
92 #define ANSELA_ADDR 0x0185
93 #define APFCON_ADDR 0x0188
94 #define OSCTUNE_ADDR 0x0189
95 #define PMCON1_ADDR 0x018C
96 #define PMCON2_ADDR 0x018D
97 #define PMADR_ADDR 0x018E
98 #define PMADRL_ADDR 0x018E
99 #define PMADRH_ADDR 0x018F
100 #define PMDAT_ADDR 0x0190
101 #define PMDATL_ADDR 0x0190
102 #define PMDATH_ADDR 0x0191
103 #define COG1PH_ADDR 0x0192
104 #define COG1BLK_ADDR 0x0193
105 #define COG1DB_ADDR 0x0194
106 #define COG1CON0_ADDR 0x0195
107 #define COG1CON1_ADDR 0x0196
108 #define COG1ASD_ADDR 0x0197
110 #endif // #ifndef NO_ADDR_DEFINES
112 //==============================================================================
114 // Register Definitions
116 //==============================================================================
118 extern __at(0x0000) __sfr INDF
;
119 extern __at(0x0001) __sfr TMR0
;
120 extern __at(0x0002) __sfr PCL
;
122 //==============================================================================
125 extern __at(0x0003) __sfr STATUS
;
149 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
160 //==============================================================================
162 extern __at(0x0004) __sfr FSR
;
164 //==============================================================================
167 extern __at(0x0005) __sfr PORTA
;
190 extern __at(0x0005) volatile __PORTAbits_t PORTAbits
;
199 //==============================================================================
202 //==============================================================================
205 extern __at(0x0008) __sfr IOCAF
;
228 extern __at(0x0008) volatile __IOCAFbits_t IOCAFbits
;
237 //==============================================================================
239 extern __at(0x000A) __sfr PCLATH
;
241 //==============================================================================
244 extern __at(0x000B) __sfr INTCON
;
258 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
269 //==============================================================================
272 //==============================================================================
275 extern __at(0x000C) __sfr PIR1
;
281 unsigned HLTMR1IF
: 1;
286 unsigned TMR1GIF
: 1;
289 extern __at(0x000C) volatile __PIR1bits_t PIR1bits
;
293 #define _HLTMR1IF 0x04
295 #define _TMR1GIF 0x80
297 //==============================================================================
300 //==============================================================================
303 extern __at(0x000D) __sfr PIR2
;
317 extern __at(0x000D) volatile __PIR2bits_t PIR2bits
;
324 //==============================================================================
326 extern __at(0x000F) __sfr TMR1
;
327 extern __at(0x000F) __sfr TMR1L
;
328 extern __at(0x0010) __sfr TMR1H
;
330 //==============================================================================
333 extern __at(0x0011) __sfr T1CON
;
341 unsigned NOT_T1SYNC
: 1;
343 unsigned T1CKPS0
: 1;
344 unsigned T1CKPS1
: 1;
345 unsigned TMR1CS0
: 1;
346 unsigned TMR1CS1
: 1;
363 extern __at(0x0011) volatile __T1CONbits_t T1CONbits
;
366 #define _NOT_T1SYNC 0x04
367 #define _T1CKPS0 0x10
368 #define _T1CKPS1 0x20
369 #define _TMR1CS0 0x40
370 #define _TMR1CS1 0x80
372 //==============================================================================
375 //==============================================================================
378 extern __at(0x0012) __sfr T1GCON
;
387 unsigned T1GGO_NOT_DONE
: 1;
413 extern __at(0x0012) volatile __T1GCONbits_t T1GCONbits
;
418 #define _T1GGO_NOT_DONE 0x08
425 //==============================================================================
427 extern __at(0x0013) __sfr CCPR1
;
428 extern __at(0x0013) __sfr CCPR1L
;
429 extern __at(0x0014) __sfr CCPR1H
;
431 //==============================================================================
434 extern __at(0x0015) __sfr CCP1CON
;
464 extern __at(0x0015) volatile __CCP1CONbits_t CCP1CONbits
;
473 //==============================================================================
475 extern __at(0x001C) __sfr ADRES
;
476 extern __at(0x001C) __sfr ADRESL
;
477 extern __at(0x001D) __sfr ADRESH
;
479 //==============================================================================
482 extern __at(0x001E) __sfr ADCON0
;
489 unsigned GO_NOT_DONE
: 1;
506 extern __at(0x001E) volatile __ADCON0bits_t ADCON0bits
;
509 #define _GO_NOT_DONE 0x02
517 //==============================================================================
520 //==============================================================================
523 extern __at(0x001F) __sfr ADCON1
;
547 extern __at(0x001F) volatile __ADCON1bits_t ADCON1bits
;
553 //==============================================================================
556 //==============================================================================
559 extern __at(0x0081) __sfr OPTION_REG
;
572 unsigned NOT_RAPU
: 1;
580 } __OPTION_REGbits_t
;
582 extern __at(0x0081) volatile __OPTION_REGbits_t OPTION_REGbits
;
591 #define _NOT_RAPU 0x80
593 //==============================================================================
596 //==============================================================================
599 extern __at(0x0085) __sfr TRISA
;
622 extern __at(0x0085) volatile __TRISAbits_t TRISAbits
;
631 //==============================================================================
634 //==============================================================================
637 extern __at(0x0088) __sfr IOCAP
;
660 extern __at(0x0088) volatile __IOCAPbits_t IOCAPbits
;
669 //==============================================================================
672 //==============================================================================
675 extern __at(0x008C) __sfr PIE1
;
681 unsigned HLTMR1IE
: 1;
686 unsigned TMR1GIE
: 1;
689 extern __at(0x008C) volatile __PIE1bits_t PIE1bits
;
693 #define _HLTMR1IE 0x04
695 #define _TMR1GIE 0x80
697 //==============================================================================
700 //==============================================================================
703 extern __at(0x008D) __sfr PIE2
;
717 extern __at(0x008D) volatile __PIE2bits_t PIE2bits
;
724 //==============================================================================
727 //==============================================================================
730 extern __at(0x008F) __sfr OSCCON
;
754 extern __at(0x008F) volatile __OSCCONbits_t OSCCONbits
;
761 //==============================================================================
764 //==============================================================================
767 extern __at(0x0090) __sfr FVRCON
;
775 unsigned FVRBUFSS
: 1;
776 unsigned FVRBUFEN
: 1;
781 extern __at(0x0090) volatile __FVRCONbits_t FVRCONbits
;
783 #define _FVRBUFSS 0x10
784 #define _FVRBUFEN 0x20
788 //==============================================================================
791 //==============================================================================
794 extern __at(0x0091) __sfr DACCON0
;
800 unsigned DACPSS0
: 1;
808 extern __at(0x0091) volatile __DACCON0bits_t DACCON0bits
;
810 #define _DACPSS0 0x04
815 //==============================================================================
818 //==============================================================================
821 extern __at(0x0092) __sfr DACCON1
;
844 extern __at(0x0092) volatile __DACCON1bits_t DACCON1bits
;
852 //==============================================================================
855 //==============================================================================
858 extern __at(0x009B) __sfr C2CON0
;
872 extern __at(0x009B) volatile __C2CON0bits_t C2CON0bits
;
883 //==============================================================================
886 //==============================================================================
889 extern __at(0x009B) __sfr CM2CON0
;
903 extern __at(0x009B) volatile __CM2CON0bits_t CM2CON0bits
;
905 #define _CM2CON0_C2SYNC 0x01
906 #define _CM2CON0_C2HYS 0x02
907 #define _CM2CON0_C2SP 0x04
908 #define _CM2CON0_C2ZLF 0x08
909 #define _CM2CON0_C2POL 0x10
910 #define _CM2CON0_C2OE 0x20
911 #define _CM2CON0_C2OUT 0x40
912 #define _CM2CON0_C2ON 0x80
914 //==============================================================================
917 //==============================================================================
920 extern __at(0x009C) __sfr C2CON1
;
944 extern __at(0x009C) volatile __C2CON1bits_t C2CON1bits
;
952 //==============================================================================
955 //==============================================================================
958 extern __at(0x009C) __sfr CM2CON1
;
982 extern __at(0x009C) volatile __CM2CON1bits_t CM2CON1bits
;
984 #define _CM2CON1_C2NCH0 0x01
985 #define _CM2CON1_C2PCH0 0x10
986 #define _CM2CON1_C2PCH1 0x20
987 #define _CM2CON1_C2INTN 0x40
988 #define _CM2CON1_C2INTP 0x80
990 //==============================================================================
993 //==============================================================================
996 extern __at(0x009D) __sfr C1CON0
;
1000 unsigned C1SYNC
: 1;
1010 extern __at(0x009D) volatile __C1CON0bits_t C1CON0bits
;
1012 #define _C1SYNC 0x01
1021 //==============================================================================
1024 //==============================================================================
1027 extern __at(0x009D) __sfr CM1CON0
;
1031 unsigned C1SYNC
: 1;
1041 extern __at(0x009D) volatile __CM1CON0bits_t CM1CON0bits
;
1043 #define _CM1CON0_C1SYNC 0x01
1044 #define _CM1CON0_C1HYS 0x02
1045 #define _CM1CON0_C1SP 0x04
1046 #define _CM1CON0_C1ZLF 0x08
1047 #define _CM1CON0_C1POL 0x10
1048 #define _CM1CON0_C1OE 0x20
1049 #define _CM1CON0_C1OUT 0x40
1050 #define _CM1CON0_C1ON 0x80
1052 //==============================================================================
1055 //==============================================================================
1058 extern __at(0x009E) __sfr C1CON1
;
1064 unsigned C1NCH0
: 1;
1068 unsigned C1PCH0
: 1;
1069 unsigned C1PCH1
: 1;
1070 unsigned C1INTN
: 1;
1071 unsigned C1INTP
: 1;
1082 extern __at(0x009E) volatile __C1CON1bits_t C1CON1bits
;
1084 #define _C1NCH0 0x01
1085 #define _C1PCH0 0x10
1086 #define _C1PCH1 0x20
1087 #define _C1INTN 0x40
1088 #define _C1INTP 0x80
1090 //==============================================================================
1093 //==============================================================================
1096 extern __at(0x009E) __sfr CM1CON1
;
1102 unsigned C1NCH0
: 1;
1106 unsigned C1PCH0
: 1;
1107 unsigned C1PCH1
: 1;
1108 unsigned C1INTN
: 1;
1109 unsigned C1INTP
: 1;
1120 extern __at(0x009E) volatile __CM1CON1bits_t CM1CON1bits
;
1122 #define _CM1CON1_C1NCH0 0x01
1123 #define _CM1CON1_C1PCH0 0x10
1124 #define _CM1CON1_C1PCH1 0x20
1125 #define _CM1CON1_C1INTN 0x40
1126 #define _CM1CON1_C1INTP 0x80
1128 //==============================================================================
1131 //==============================================================================
1134 extern __at(0x009F) __sfr CMOUT
;
1138 unsigned MCOUT1
: 1;
1139 unsigned MCOUT2
: 1;
1148 extern __at(0x009F) volatile __CMOUTbits_t CMOUTbits
;
1150 #define _MCOUT1 0x01
1151 #define _MCOUT2 0x02
1153 //==============================================================================
1156 //==============================================================================
1159 extern __at(0x009F) __sfr MCOUT
;
1163 unsigned MCOUT1
: 1;
1164 unsigned MCOUT2
: 1;
1173 extern __at(0x009F) volatile __MCOUTbits_t MCOUTbits
;
1175 #define _MCOUT_MCOUT1 0x01
1176 #define _MCOUT_MCOUT2 0x02
1178 //==============================================================================
1181 //==============================================================================
1184 extern __at(0x0105) __sfr LATA
;
1198 extern __at(0x0105) volatile __LATAbits_t LATAbits
;
1206 //==============================================================================
1209 //==============================================================================
1212 extern __at(0x0108) __sfr IOCAN
;
1218 unsigned IOCAN0
: 1;
1219 unsigned IOCAN1
: 1;
1220 unsigned IOCAN2
: 1;
1221 unsigned IOCAN3
: 1;
1222 unsigned IOCAN4
: 1;
1223 unsigned IOCAN5
: 1;
1235 extern __at(0x0108) volatile __IOCANbits_t IOCANbits
;
1237 #define _IOCAN0 0x01
1238 #define _IOCAN1 0x02
1239 #define _IOCAN2 0x04
1240 #define _IOCAN3 0x08
1241 #define _IOCAN4 0x10
1242 #define _IOCAN5 0x20
1244 //==============================================================================
1247 //==============================================================================
1250 extern __at(0x010C) __sfr WPUA
;
1273 extern __at(0x010C) volatile __WPUAbits_t WPUAbits
;
1282 //==============================================================================
1285 //==============================================================================
1288 extern __at(0x010D) __sfr SLRCONA
;
1302 extern __at(0x010D) volatile __SLRCONAbits_t SLRCONAbits
;
1307 //==============================================================================
1310 //==============================================================================
1313 extern __at(0x010F) __sfr PCON
;
1317 unsigned NOT_BOR
: 1;
1318 unsigned NOT_POR
: 1;
1327 extern __at(0x010F) volatile __PCONbits_t PCONbits
;
1329 #define _NOT_BOR 0x01
1330 #define _NOT_POR 0x02
1332 //==============================================================================
1334 extern __at(0x0110) __sfr TMR2
;
1335 extern __at(0x0111) __sfr PR2
;
1337 //==============================================================================
1340 extern __at(0x0112) __sfr T2CON
;
1346 unsigned T2CKPS0
: 1;
1347 unsigned T2CKPS1
: 1;
1348 unsigned TMR2ON
: 1;
1349 unsigned T2OUTPS0
: 1;
1350 unsigned T2OUTPS1
: 1;
1351 unsigned T2OUTPS2
: 1;
1352 unsigned T2OUTPS3
: 1;
1358 unsigned T2CKPS
: 2;
1365 unsigned T2OUTPS
: 4;
1370 extern __at(0x0112) volatile __T2CONbits_t T2CONbits
;
1372 #define _T2CKPS0 0x01
1373 #define _T2CKPS1 0x02
1374 #define _TMR2ON 0x04
1375 #define _T2OUTPS0 0x08
1376 #define _T2OUTPS1 0x10
1377 #define _T2OUTPS2 0x20
1378 #define _T2OUTPS3 0x40
1380 //==============================================================================
1382 extern __at(0x0113) __sfr HLTMR1
;
1383 extern __at(0x0114) __sfr HLTPR1
;
1385 //==============================================================================
1388 extern __at(0x0115) __sfr HLT1CON0
;
1394 unsigned H1CKPS0
: 1;
1395 unsigned H1CKPS1
: 1;
1397 unsigned H1OUTPS0
: 1;
1398 unsigned H1OUTPS1
: 1;
1399 unsigned H1OUTPS2
: 1;
1400 unsigned H1OUTPS3
: 1;
1406 unsigned H1CKPS
: 2;
1413 unsigned H1OUTPS
: 4;
1418 extern __at(0x0115) volatile __HLT1CON0bits_t HLT1CON0bits
;
1420 #define _H1CKPS0 0x01
1421 #define _H1CKPS1 0x02
1423 #define _H1OUTPS0 0x08
1424 #define _H1OUTPS1 0x10
1425 #define _H1OUTPS2 0x20
1426 #define _H1OUTPS3 0x40
1428 //==============================================================================
1431 //==============================================================================
1434 extern __at(0x0116) __sfr HLT1CON1
;
1440 unsigned H1REREN
: 1;
1441 unsigned H1FEREN
: 1;
1442 unsigned H1ERS0
: 1;
1443 unsigned H1ERS1
: 1;
1444 unsigned H1ERS2
: 1;
1458 extern __at(0x0116) volatile __HLT1CON1bits_t HLT1CON1bits
;
1460 #define _H1REREN 0x01
1461 #define _H1FEREN 0x02
1462 #define _H1ERS0 0x04
1463 #define _H1ERS1 0x08
1464 #define _H1ERS2 0x10
1466 //==============================================================================
1469 //==============================================================================
1472 extern __at(0x0185) __sfr ANSELA
;
1486 extern __at(0x0185) volatile __ANSELAbits_t ANSELAbits
;
1494 //==============================================================================
1497 //==============================================================================
1500 extern __at(0x0188) __sfr APFCON
;
1504 unsigned COG1O0SEL
: 1;
1505 unsigned COG1O1SEL
: 1;
1506 unsigned COG1FSEL
: 1;
1508 unsigned T1GSEL
: 1;
1514 extern __at(0x0188) volatile __APFCONbits_t APFCONbits
;
1516 #define _COG1O0SEL 0x01
1517 #define _COG1O1SEL 0x02
1518 #define _COG1FSEL 0x04
1519 #define _T1GSEL 0x10
1521 //==============================================================================
1524 //==============================================================================
1527 extern __at(0x0189) __sfr OSCTUNE
;
1550 extern __at(0x0189) volatile __OSCTUNEbits_t OSCTUNEbits
;
1558 //==============================================================================
1561 //==============================================================================
1564 extern __at(0x018C) __sfr PMCON1
;
1578 extern __at(0x018C) volatile __PMCON1bits_t PMCON1bits
;
1584 //==============================================================================
1586 extern __at(0x018D) __sfr PMCON2
;
1587 extern __at(0x018E) __sfr PMADR
;
1588 extern __at(0x018E) __sfr PMADRL
;
1589 extern __at(0x018F) __sfr PMADRH
;
1590 extern __at(0x0190) __sfr PMDAT
;
1591 extern __at(0x0190) __sfr PMDATL
;
1592 extern __at(0x0191) __sfr PMDATH
;
1594 //==============================================================================
1597 extern __at(0x0192) __sfr COG1PH
;
1620 extern __at(0x0192) volatile __COG1PHbits_t COG1PHbits
;
1627 //==============================================================================
1630 //==============================================================================
1633 extern __at(0x0193) __sfr COG1BLK
;
1639 unsigned G1BLKF0
: 1;
1640 unsigned G1BLKF1
: 1;
1641 unsigned G1BLKF2
: 1;
1642 unsigned G1BLKF3
: 1;
1643 unsigned G1BLKR0
: 1;
1644 unsigned G1BLKR1
: 1;
1645 unsigned G1BLKR2
: 1;
1646 unsigned G1BLKR3
: 1;
1651 unsigned G1BLKF
: 4;
1658 unsigned G1BLKR
: 4;
1662 extern __at(0x0193) volatile __COG1BLKbits_t COG1BLKbits
;
1664 #define _G1BLKF0 0x01
1665 #define _G1BLKF1 0x02
1666 #define _G1BLKF2 0x04
1667 #define _G1BLKF3 0x08
1668 #define _G1BLKR0 0x10
1669 #define _G1BLKR1 0x20
1670 #define _G1BLKR2 0x40
1671 #define _G1BLKR3 0x80
1673 //==============================================================================
1676 //==============================================================================
1679 extern __at(0x0194) __sfr COG1DB
;
1685 unsigned G1DBF0
: 1;
1686 unsigned G1DBF1
: 1;
1687 unsigned G1DBF2
: 1;
1688 unsigned G1DBF3
: 1;
1689 unsigned G1BDR0
: 1;
1690 unsigned G1BDR1
: 1;
1691 unsigned G1BDR2
: 1;
1692 unsigned G1BDR3
: 1;
1708 extern __at(0x0194) volatile __COG1DBbits_t COG1DBbits
;
1710 #define _G1DBF0 0x01
1711 #define _G1DBF1 0x02
1712 #define _G1DBF2 0x04
1713 #define _G1DBF3 0x08
1714 #define _G1BDR0 0x10
1715 #define _G1BDR1 0x20
1716 #define _G1BDR2 0x40
1717 #define _G1BDR3 0x80
1719 //==============================================================================
1722 //==============================================================================
1725 extern __at(0x0195) __sfr COG1CON0
;
1734 unsigned G1POL0
: 1;
1735 unsigned G1POL1
: 1;
1762 extern __at(0x0195) volatile __COG1CON0bits_t COG1CON0bits
;
1767 #define _G1POL0 0x08
1768 #define _G1POL1 0x10
1773 //==============================================================================
1776 //==============================================================================
1779 extern __at(0x0196) __sfr COG1CON1
;
1791 unsigned G1RSIM
: 1;
1792 unsigned G1FSIM
: 1;
1809 extern __at(0x0196) volatile __COG1CON1bits_t COG1CON1bits
;
1817 #define _G1RSIM 0x40
1818 #define _G1FSIM 0x80
1820 //==============================================================================
1823 //==============================================================================
1826 extern __at(0x0197) __sfr COG1ASD
;
1832 unsigned G1ASDSFLT
: 1;
1833 unsigned G1ASDSC1
: 1;
1834 unsigned G1ASDSC2
: 1;
1835 unsigned G1ASDSHLT
: 1;
1836 unsigned G1ASDL0
: 1;
1837 unsigned G1ASDL1
: 1;
1838 unsigned G1ARSEN
: 1;
1839 unsigned G1ASDE
: 1;
1845 unsigned G1ASDL
: 2;
1850 extern __at(0x0197) volatile __COG1ASDbits_t COG1ASDbits
;
1852 #define _G1ASDSFLT 0x01
1853 #define _G1ASDSC1 0x02
1854 #define _G1ASDSC2 0x04
1855 #define _G1ASDSHLT 0x08
1856 #define _G1ASDL0 0x10
1857 #define _G1ASDL1 0x20
1858 #define _G1ARSEN 0x40
1859 #define _G1ASDE 0x80
1861 //==============================================================================
1864 //==============================================================================
1866 // Configuration Bits
1868 //==============================================================================
1870 #define _CONFIG 0x2007
1872 //----------------------------- CONFIG Options -------------------------------
1874 #define _FOSC0_INT 0x3FFE // Internal oscillator mode. I/O function on RA5/CLKIN.
1875 #define _FOSC0_EC 0x3FFF // EC oscillator mode. CLKIN function on RA5/CLKIN.
1876 #define _WDTE_OFF 0x3FF7 // Watchdog Timer disabled.
1877 #define _WDTE_ON 0x3FFF // Watchdog Timer enabled.
1878 #define _PWRTE_ON 0x3FEF // Power-up Timer enabled.
1879 #define _PWRTE_OFF 0x3FFF // Power-up Timer disabled.
1880 #define _MCLRE_OFF 0x3FDF // MCLR pin is alternate function.
1881 #define _MCLRE_ON 0x3FFF // MCLR pin is MCLR function with internal weak pullup.
1882 #define _CP_ON 0x3FBF // Program memory code protection is enabled.
1883 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
1884 #define _BOREN_DIS 0x3CFF // BOR disabled.
1885 #define _BOREN_SLEEP_DIS 0x3EFF // BOR enabled during operation and disabled in Sleep.
1886 #define _BOREN_EN 0x3FFF // BOR enabled.
1887 #define _WRT_ALL 0x33FF // 000h to 3FFh self-write protected.
1888 #define _WRT_HALF 0x37FF // 000h to 1FFh self-write protected.
1889 #define _WRT_FOURTH 0x3BFF // 000h to 0FFh self-write protected.
1890 #define _WRT_OFF 0x3FFF // Flash self-write protection off.
1891 #define _CLKOUTEN_ON 0x2FFF // CLKOUT function enabled. CLKOUT pin is CLKOUT.
1892 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function disabled. CLKOUT pin acts as I/O.
1894 //==============================================================================
1896 #define _DEVID1 0x2006
1898 #define _IDLOC0 0x2000
1899 #define _IDLOC1 0x2001
1900 #define _IDLOC2 0x2002
1901 #define _IDLOC3 0x2003
1903 //==============================================================================
1905 #ifndef NO_BIT_DEFINES
1907 #define ADON ADCON0bits.ADON // bit 0
1908 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1
1909 #define CHS0 ADCON0bits.CHS0 // bit 2
1910 #define CHS1 ADCON0bits.CHS1 // bit 3
1911 #define CHS2 ADCON0bits.CHS2 // bit 4
1912 #define CHS3 ADCON0bits.CHS3 // bit 5
1913 #define VCFG ADCON0bits.VCFG // bit 6
1914 #define ADFM ADCON0bits.ADFM // bit 7
1916 #define ADCS0 ADCON1bits.ADCS0 // bit 4
1917 #define ADCS1 ADCON1bits.ADCS1 // bit 5
1918 #define ADCS2 ADCON1bits.ADCS2 // bit 6
1920 #define ANSA0 ANSELAbits.ANSA0 // bit 0
1921 #define ANSA1 ANSELAbits.ANSA1 // bit 1
1922 #define ANSA2 ANSELAbits.ANSA2 // bit 2
1923 #define ANSA4 ANSELAbits.ANSA4 // bit 4
1924 #define ANSA5 ANSELAbits.ANSA5 // bit 5
1926 #define COG1O0SEL APFCONbits.COG1O0SEL // bit 0
1927 #define COG1O1SEL APFCONbits.COG1O1SEL // bit 1
1928 #define COG1FSEL APFCONbits.COG1FSEL // bit 2
1929 #define T1GSEL APFCONbits.T1GSEL // bit 4
1931 #define C1SYNC C1CON0bits.C1SYNC // bit 0
1932 #define C1HYS C1CON0bits.C1HYS // bit 1
1933 #define C1SP C1CON0bits.C1SP // bit 2
1934 #define C1ZLF C1CON0bits.C1ZLF // bit 3
1935 #define C1POL C1CON0bits.C1POL // bit 4
1936 #define C1OE C1CON0bits.C1OE // bit 5
1937 #define C1OUT C1CON0bits.C1OUT // bit 6
1938 #define C1ON C1CON0bits.C1ON // bit 7
1940 #define C1NCH0 C1CON1bits.C1NCH0 // bit 0
1941 #define C1PCH0 C1CON1bits.C1PCH0 // bit 4
1942 #define C1PCH1 C1CON1bits.C1PCH1 // bit 5
1943 #define C1INTN C1CON1bits.C1INTN // bit 6
1944 #define C1INTP C1CON1bits.C1INTP // bit 7
1946 #define C2SYNC C2CON0bits.C2SYNC // bit 0
1947 #define C2HYS C2CON0bits.C2HYS // bit 1
1948 #define C2SP C2CON0bits.C2SP // bit 2
1949 #define C2ZLF C2CON0bits.C2ZLF // bit 3
1950 #define C2POL C2CON0bits.C2POL // bit 4
1951 #define C2OE C2CON0bits.C2OE // bit 5
1952 #define C2OUT C2CON0bits.C2OUT // bit 6
1953 #define C2ON C2CON0bits.C2ON // bit 7
1955 #define C2NCH0 C2CON1bits.C2NCH0 // bit 0
1956 #define C2PCH0 C2CON1bits.C2PCH0 // bit 4
1957 #define C2PCH1 C2CON1bits.C2PCH1 // bit 5
1958 #define C2INTN C2CON1bits.C2INTN // bit 6
1959 #define C2INTP C2CON1bits.C2INTP // bit 7
1961 #define CCP1M0 CCP1CONbits.CCP1M0 // bit 0
1962 #define CCP1M1 CCP1CONbits.CCP1M1 // bit 1
1963 #define CCP1M2 CCP1CONbits.CCP1M2 // bit 2
1964 #define CCP1M3 CCP1CONbits.CCP1M3 // bit 3
1965 #define DC1B0 CCP1CONbits.DC1B0 // bit 4
1966 #define DC1B1 CCP1CONbits.DC1B1 // bit 5
1968 #define MCOUT1 CMOUTbits.MCOUT1 // bit 0
1969 #define MCOUT2 CMOUTbits.MCOUT2 // bit 1
1971 #define G1ASDSFLT COG1ASDbits.G1ASDSFLT // bit 0
1972 #define G1ASDSC1 COG1ASDbits.G1ASDSC1 // bit 1
1973 #define G1ASDSC2 COG1ASDbits.G1ASDSC2 // bit 2
1974 #define G1ASDSHLT COG1ASDbits.G1ASDSHLT // bit 3
1975 #define G1ASDL0 COG1ASDbits.G1ASDL0 // bit 4
1976 #define G1ASDL1 COG1ASDbits.G1ASDL1 // bit 5
1977 #define G1ARSEN COG1ASDbits.G1ARSEN // bit 6
1978 #define G1ASDE COG1ASDbits.G1ASDE // bit 7
1980 #define G1BLKF0 COG1BLKbits.G1BLKF0 // bit 0
1981 #define G1BLKF1 COG1BLKbits.G1BLKF1 // bit 1
1982 #define G1BLKF2 COG1BLKbits.G1BLKF2 // bit 2
1983 #define G1BLKF3 COG1BLKbits.G1BLKF3 // bit 3
1984 #define G1BLKR0 COG1BLKbits.G1BLKR0 // bit 4
1985 #define G1BLKR1 COG1BLKbits.G1BLKR1 // bit 5
1986 #define G1BLKR2 COG1BLKbits.G1BLKR2 // bit 6
1987 #define G1BLKR3 COG1BLKbits.G1BLKR3 // bit 7
1989 #define G1CS0 COG1CON0bits.G1CS0 // bit 0
1990 #define G1CS1 COG1CON0bits.G1CS1 // bit 1
1991 #define G1LD COG1CON0bits.G1LD // bit 2
1992 #define G1POL0 COG1CON0bits.G1POL0 // bit 3
1993 #define G1POL1 COG1CON0bits.G1POL1 // bit 4
1994 #define G1OE0 COG1CON0bits.G1OE0 // bit 5
1995 #define G1OE1 COG1CON0bits.G1OE1 // bit 6
1996 #define G1EN COG1CON0bits.G1EN // bit 7
1998 #define G1RS0 COG1CON1bits.G1RS0 // bit 0
1999 #define G1RS1 COG1CON1bits.G1RS1 // bit 1
2000 #define G1RS2 COG1CON1bits.G1RS2 // bit 2
2001 #define G1FS0 COG1CON1bits.G1FS0 // bit 3
2002 #define G1FS1 COG1CON1bits.G1FS1 // bit 4
2003 #define G1FS2 COG1CON1bits.G1FS2 // bit 5
2004 #define G1RSIM COG1CON1bits.G1RSIM // bit 6
2005 #define G1FSIM COG1CON1bits.G1FSIM // bit 7
2007 #define G1DBF0 COG1DBbits.G1DBF0 // bit 0
2008 #define G1DBF1 COG1DBbits.G1DBF1 // bit 1
2009 #define G1DBF2 COG1DBbits.G1DBF2 // bit 2
2010 #define G1DBF3 COG1DBbits.G1DBF3 // bit 3
2011 #define G1BDR0 COG1DBbits.G1BDR0 // bit 4
2012 #define G1BDR1 COG1DBbits.G1BDR1 // bit 5
2013 #define G1BDR2 COG1DBbits.G1BDR2 // bit 6
2014 #define G1BDR3 COG1DBbits.G1BDR3 // bit 7
2016 #define G1PH0 COG1PHbits.G1PH0 // bit 0
2017 #define G1PH1 COG1PHbits.G1PH1 // bit 1
2018 #define G1PH2 COG1PHbits.G1PH2 // bit 2
2019 #define G1PH3 COG1PHbits.G1PH3 // bit 3
2021 #define DACPSS0 DACCON0bits.DACPSS0 // bit 2
2022 #define DACOE DACCON0bits.DACOE // bit 5
2023 #define DACRNG DACCON0bits.DACRNG // bit 6
2024 #define DACEN DACCON0bits.DACEN // bit 7
2026 #define DACR0 DACCON1bits.DACR0 // bit 0
2027 #define DACR1 DACCON1bits.DACR1 // bit 1
2028 #define DACR2 DACCON1bits.DACR2 // bit 2
2029 #define DACR3 DACCON1bits.DACR3 // bit 3
2030 #define DACR4 DACCON1bits.DACR4 // bit 4
2032 #define FVRBUFSS FVRCONbits.FVRBUFSS // bit 4
2033 #define FVRBUFEN FVRCONbits.FVRBUFEN // bit 5
2034 #define FVRRDY FVRCONbits.FVRRDY // bit 6
2035 #define FVREN FVRCONbits.FVREN // bit 7
2037 #define H1CKPS0 HLT1CON0bits.H1CKPS0 // bit 0
2038 #define H1CKPS1 HLT1CON0bits.H1CKPS1 // bit 1
2039 #define H1ON HLT1CON0bits.H1ON // bit 2
2040 #define H1OUTPS0 HLT1CON0bits.H1OUTPS0 // bit 3
2041 #define H1OUTPS1 HLT1CON0bits.H1OUTPS1 // bit 4
2042 #define H1OUTPS2 HLT1CON0bits.H1OUTPS2 // bit 5
2043 #define H1OUTPS3 HLT1CON0bits.H1OUTPS3 // bit 6
2045 #define H1REREN HLT1CON1bits.H1REREN // bit 0
2046 #define H1FEREN HLT1CON1bits.H1FEREN // bit 1
2047 #define H1ERS0 HLT1CON1bits.H1ERS0 // bit 2
2048 #define H1ERS1 HLT1CON1bits.H1ERS1 // bit 3
2049 #define H1ERS2 HLT1CON1bits.H1ERS2 // bit 4
2051 #define IOCIF INTCONbits.IOCIF // bit 0
2052 #define INTF INTCONbits.INTF // bit 1
2053 #define T0IF INTCONbits.T0IF // bit 2
2054 #define IOCIE INTCONbits.IOCIE // bit 3
2055 #define INTE INTCONbits.INTE // bit 4
2056 #define T0IE INTCONbits.T0IE // bit 5
2057 #define PEIE INTCONbits.PEIE // bit 6
2058 #define GIE INTCONbits.GIE // bit 7
2060 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
2061 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
2062 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
2063 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
2064 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
2065 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
2067 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
2068 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
2069 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
2070 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
2071 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
2072 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
2074 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
2075 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
2076 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
2077 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
2078 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
2079 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
2081 #define LATA0 LATAbits.LATA0 // bit 0
2082 #define LATA1 LATAbits.LATA1 // bit 1
2083 #define LATA2 LATAbits.LATA2 // bit 2
2084 #define LATA4 LATAbits.LATA4 // bit 4
2085 #define LATA5 LATAbits.LATA5 // bit 5
2087 #define PS0 OPTION_REGbits.PS0 // bit 0
2088 #define PS1 OPTION_REGbits.PS1 // bit 1
2089 #define PS2 OPTION_REGbits.PS2 // bit 2
2090 #define PSA OPTION_REGbits.PSA // bit 3
2091 #define T0SE OPTION_REGbits.T0SE // bit 4
2092 #define T0CS OPTION_REGbits.T0CS // bit 5
2093 #define INTEDG OPTION_REGbits.INTEDG // bit 6
2094 #define NOT_RAPU OPTION_REGbits.NOT_RAPU // bit 7
2096 #define LTS OSCCONbits.LTS // bit 1
2097 #define HTS OSCCONbits.HTS // bit 2
2098 #define IRCF0 OSCCONbits.IRCF0 // bit 4
2099 #define IRCF1 OSCCONbits.IRCF1 // bit 5
2101 #define TUN0 OSCTUNEbits.TUN0 // bit 0
2102 #define TUN1 OSCTUNEbits.TUN1 // bit 1
2103 #define TUN2 OSCTUNEbits.TUN2 // bit 2
2104 #define TUN3 OSCTUNEbits.TUN3 // bit 3
2105 #define TUN4 OSCTUNEbits.TUN4 // bit 4
2107 #define NOT_BOR PCONbits.NOT_BOR // bit 0
2108 #define NOT_POR PCONbits.NOT_POR // bit 1
2110 #define TMR1IE PIE1bits.TMR1IE // bit 0
2111 #define TMR2IE PIE1bits.TMR2IE // bit 1
2112 #define HLTMR1IE PIE1bits.HLTMR1IE // bit 2
2113 #define ADIE PIE1bits.ADIE // bit 6
2114 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
2116 #define CCP1IE PIE2bits.CCP1IE // bit 0
2117 #define COG1IE PIE2bits.COG1IE // bit 2
2118 #define C1IE PIE2bits.C1IE // bit 4
2119 #define C2IE PIE2bits.C2IE // bit 5
2121 #define TMR1IF PIR1bits.TMR1IF // bit 0
2122 #define TMR2IF PIR1bits.TMR2IF // bit 1
2123 #define HLTMR1IF PIR1bits.HLTMR1IF // bit 2
2124 #define ADIF PIR1bits.ADIF // bit 6
2125 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
2127 #define CCP1IF PIR2bits.CCP1IF // bit 0
2128 #define COG1IF PIR2bits.COG1IF // bit 2
2129 #define C1IF PIR2bits.C1IF // bit 4
2130 #define C2IF PIR2bits.C2IF // bit 5
2132 #define RD PMCON1bits.RD // bit 0
2133 #define WR PMCON1bits.WR // bit 1
2134 #define WREN PMCON1bits.WREN // bit 2
2136 #define RA0 PORTAbits.RA0 // bit 0
2137 #define RA1 PORTAbits.RA1 // bit 1
2138 #define RA2 PORTAbits.RA2 // bit 2
2139 #define RA3 PORTAbits.RA3 // bit 3
2140 #define RA4 PORTAbits.RA4 // bit 4
2141 #define RA5 PORTAbits.RA5 // bit 5
2143 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
2144 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
2146 #define C STATUSbits.C // bit 0
2147 #define DC STATUSbits.DC // bit 1
2148 #define Z STATUSbits.Z // bit 2
2149 #define NOT_PD STATUSbits.NOT_PD // bit 3
2150 #define NOT_TO STATUSbits.NOT_TO // bit 4
2151 #define RP0 STATUSbits.RP0 // bit 5
2152 #define RP1 STATUSbits.RP1 // bit 6
2153 #define IRP STATUSbits.IRP // bit 7
2155 #define TMR1ON T1CONbits.TMR1ON // bit 0
2156 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
2157 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
2158 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
2159 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
2160 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
2162 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
2163 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
2164 #define T1GVAL T1GCONbits.T1GVAL // bit 2
2165 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3, shadows bit in T1GCONbits
2166 #define T1GGO T1GCONbits.T1GGO // bit 3, shadows bit in T1GCONbits
2167 #define T1GSPM T1GCONbits.T1GSPM // bit 4
2168 #define T1GTM T1GCONbits.T1GTM // bit 5
2169 #define T1GPOL T1GCONbits.T1GPOL // bit 6
2170 #define TMR1GE T1GCONbits.TMR1GE // bit 7
2172 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
2173 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
2174 #define TMR2ON T2CONbits.TMR2ON // bit 2
2175 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
2176 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
2177 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
2178 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
2180 #define TRISA0 TRISAbits.TRISA0 // bit 0
2181 #define TRISA1 TRISAbits.TRISA1 // bit 1
2182 #define TRISA2 TRISAbits.TRISA2 // bit 2
2183 #define TRISA3 TRISAbits.TRISA3 // bit 3
2184 #define TRISA4 TRISAbits.TRISA4 // bit 4
2185 #define TRISA5 TRISAbits.TRISA5 // bit 5
2187 #define WPUA0 WPUAbits.WPUA0 // bit 0
2188 #define WPUA1 WPUAbits.WPUA1 // bit 1
2189 #define WPUA2 WPUAbits.WPUA2 // bit 2
2190 #define WPUA3 WPUAbits.WPUA3 // bit 3
2191 #define WPUA4 WPUAbits.WPUA4 // bit 4
2192 #define WPUA5 WPUAbits.WPUA5 // bit 5
2194 #endif // #ifndef NO_BIT_DEFINES
2196 #endif // #ifndef __PIC12HV752_H__