2 * This declarations of the PIC16F1509 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:06 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F1509_H__
26 #define __PIC16F1509_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTB_ADDR 0x000D
52 #define PORTC_ADDR 0x000E
53 #define PIR1_ADDR 0x0011
54 #define PIR2_ADDR 0x0012
55 #define PIR3_ADDR 0x0013
56 #define TMR0_ADDR 0x0015
57 #define TMR1_ADDR 0x0016
58 #define TMR1L_ADDR 0x0016
59 #define TMR1H_ADDR 0x0017
60 #define T1CON_ADDR 0x0018
61 #define T1GCON_ADDR 0x0019
62 #define TMR2_ADDR 0x001A
63 #define PR2_ADDR 0x001B
64 #define T2CON_ADDR 0x001C
65 #define TRISA_ADDR 0x008C
66 #define TRISB_ADDR 0x008D
67 #define TRISC_ADDR 0x008E
68 #define PIE1_ADDR 0x0091
69 #define PIE2_ADDR 0x0092
70 #define PIE3_ADDR 0x0093
71 #define OPTION_REG_ADDR 0x0095
72 #define PCON_ADDR 0x0096
73 #define WDTCON_ADDR 0x0097
74 #define OSCCON_ADDR 0x0099
75 #define OSCSTAT_ADDR 0x009A
76 #define ADRES_ADDR 0x009B
77 #define ADRESL_ADDR 0x009B
78 #define ADRESH_ADDR 0x009C
79 #define ADCON0_ADDR 0x009D
80 #define ADCON1_ADDR 0x009E
81 #define ADCON2_ADDR 0x009F
82 #define LATA_ADDR 0x010C
83 #define LATB_ADDR 0x010D
84 #define LATC_ADDR 0x010E
85 #define CM1CON0_ADDR 0x0111
86 #define CM1CON1_ADDR 0x0112
87 #define CM2CON0_ADDR 0x0113
88 #define CM2CON1_ADDR 0x0114
89 #define CMOUT_ADDR 0x0115
90 #define BORCON_ADDR 0x0116
91 #define FVRCON_ADDR 0x0117
92 #define DACCON0_ADDR 0x0118
93 #define DACCON1_ADDR 0x0119
94 #define APFCON_ADDR 0x011D
95 #define ANSELA_ADDR 0x018C
96 #define ANSELB_ADDR 0x018D
97 #define ANSELC_ADDR 0x018E
98 #define PMADR_ADDR 0x0191
99 #define PMADRL_ADDR 0x0191
100 #define PMADRH_ADDR 0x0192
101 #define PMDAT_ADDR 0x0193
102 #define PMDATL_ADDR 0x0193
103 #define PMDATH_ADDR 0x0194
104 #define PMCON1_ADDR 0x0195
105 #define PMCON2_ADDR 0x0196
106 #define VREGCON_ADDR 0x0197
107 #define RCREG_ADDR 0x0199
108 #define TXREG_ADDR 0x019A
109 #define SPBRG_ADDR 0x019B
110 #define SPBRGL_ADDR 0x019B
111 #define SPBRGH_ADDR 0x019C
112 #define RCSTA_ADDR 0x019D
113 #define TXSTA_ADDR 0x019E
114 #define BAUDCON_ADDR 0x019F
115 #define WPUA_ADDR 0x020C
116 #define WPUB_ADDR 0x020D
117 #define SSP1BUF_ADDR 0x0211
118 #define SSPBUF_ADDR 0x0211
119 #define SSP1ADD_ADDR 0x0212
120 #define SSPADD_ADDR 0x0212
121 #define SSP1MSK_ADDR 0x0213
122 #define SSPMSK_ADDR 0x0213
123 #define SSP1STAT_ADDR 0x0214
124 #define SSPSTAT_ADDR 0x0214
125 #define SSP1CON1_ADDR 0x0215
126 #define SSPCON_ADDR 0x0215
127 #define SSPCON1_ADDR 0x0215
128 #define SSP1CON2_ADDR 0x0216
129 #define SSPCON2_ADDR 0x0216
130 #define SSP1CON3_ADDR 0x0217
131 #define SSPCON3_ADDR 0x0217
132 #define IOCAP_ADDR 0x0391
133 #define IOCAN_ADDR 0x0392
134 #define IOCAF_ADDR 0x0393
135 #define IOCBP_ADDR 0x0394
136 #define IOCBN_ADDR 0x0395
137 #define IOCBF_ADDR 0x0396
138 #define NCO1ACC_ADDR 0x0498
139 #define NCO1ACCL_ADDR 0x0498
140 #define NCO1ACCH_ADDR 0x0499
141 #define NCO1ACCU_ADDR 0x049A
142 #define NCO1INC_ADDR 0x049B
143 #define NCO1INCL_ADDR 0x049B
144 #define NCO1INCH_ADDR 0x049C
145 #define NCO1INCU_ADDR 0x049D
146 #define NCO1CON_ADDR 0x049E
147 #define NCO1CLK_ADDR 0x049F
148 #define PWM1DCL_ADDR 0x0611
149 #define PWM1DCH_ADDR 0x0612
150 #define PWM1CON_ADDR 0x0613
151 #define PWM1CON0_ADDR 0x0613
152 #define PWM2DCL_ADDR 0x0614
153 #define PWM2DCH_ADDR 0x0615
154 #define PWM2CON_ADDR 0x0616
155 #define PWM2CON0_ADDR 0x0616
156 #define PWM3DCL_ADDR 0x0617
157 #define PWM3DCH_ADDR 0x0618
158 #define PWM3CON_ADDR 0x0619
159 #define PWM3CON0_ADDR 0x0619
160 #define PWM4DCL_ADDR 0x061A
161 #define PWM4DCH_ADDR 0x061B
162 #define PWM4CON_ADDR 0x061C
163 #define PWM4CON0_ADDR 0x061C
164 #define CWG1DBR_ADDR 0x0691
165 #define CWG1DBF_ADDR 0x0692
166 #define CWG1CON0_ADDR 0x0693
167 #define CWG1CON1_ADDR 0x0694
168 #define CWG1CON2_ADDR 0x0695
169 #define CLCDATA_ADDR 0x0F0F
170 #define CLC1CON_ADDR 0x0F10
171 #define CLC1POL_ADDR 0x0F11
172 #define CLC1SEL0_ADDR 0x0F12
173 #define CLC1SEL1_ADDR 0x0F13
174 #define CLC1GLS0_ADDR 0x0F14
175 #define CLC1GLS1_ADDR 0x0F15
176 #define CLC1GLS2_ADDR 0x0F16
177 #define CLC1GLS3_ADDR 0x0F17
178 #define CLC2CON_ADDR 0x0F18
179 #define CLC2POL_ADDR 0x0F19
180 #define CLC2SEL0_ADDR 0x0F1A
181 #define CLC2SEL1_ADDR 0x0F1B
182 #define CLC2GLS0_ADDR 0x0F1C
183 #define CLC2GLS1_ADDR 0x0F1D
184 #define CLC2GLS2_ADDR 0x0F1E
185 #define CLC2GLS3_ADDR 0x0F1F
186 #define CLC3CON_ADDR 0x0F20
187 #define CLC3POL_ADDR 0x0F21
188 #define CLC3SEL0_ADDR 0x0F22
189 #define CLC3SEL1_ADDR 0x0F23
190 #define CLC3GLS0_ADDR 0x0F24
191 #define CLC3GLS1_ADDR 0x0F25
192 #define CLC3GLS2_ADDR 0x0F26
193 #define CLC3GLS3_ADDR 0x0F27
194 #define CLC4CON_ADDR 0x0F28
195 #define CLC4POL_ADDR 0x0F29
196 #define CLC4SEL0_ADDR 0x0F2A
197 #define CLC4SEL1_ADDR 0x0F2B
198 #define CLC4GLS0_ADDR 0x0F2C
199 #define CLC4GLS1_ADDR 0x0F2D
200 #define CLC4GLS2_ADDR 0x0F2E
201 #define CLC4GLS3_ADDR 0x0F2F
202 #define ICDIO_ADDR 0x0F8C
203 #define ICDCON0_ADDR 0x0F8D
204 #define ICDSTAT_ADDR 0x0F91
205 #define DEVSEL_ADDR 0x0F95
206 #define ICDINSTL_ADDR 0x0F96
207 #define ICDINSTH_ADDR 0x0F97
208 #define ICDBK0CON_ADDR 0x0F9C
209 #define ICDBK0L_ADDR 0x0F9D
210 #define ICDBK0H_ADDR 0x0F9E
211 #define BSRICDSHAD_ADDR 0x0FE3
212 #define STATUS_SHAD_ADDR 0x0FE4
213 #define WREG_SHAD_ADDR 0x0FE5
214 #define BSR_SHAD_ADDR 0x0FE6
215 #define PCLATH_SHAD_ADDR 0x0FE7
216 #define FSR0L_SHAD_ADDR 0x0FE8
217 #define FSR0H_SHAD_ADDR 0x0FE9
218 #define FSR1L_SHAD_ADDR 0x0FEA
219 #define FSR1H_SHAD_ADDR 0x0FEB
220 #define STKPTR_ADDR 0x0FED
221 #define TOSL_ADDR 0x0FEE
222 #define TOSH_ADDR 0x0FEF
224 #endif // #ifndef NO_ADDR_DEFINES
226 //==============================================================================
228 // Register Definitions
230 //==============================================================================
232 extern __at(0x0000) __sfr INDF0
;
233 extern __at(0x0001) __sfr INDF1
;
234 extern __at(0x0002) __sfr PCL
;
236 //==============================================================================
239 extern __at(0x0003) __sfr STATUS
;
253 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
261 //==============================================================================
263 extern __at(0x0004) __sfr FSR0
;
264 extern __at(0x0004) __sfr FSR0L
;
265 extern __at(0x0005) __sfr FSR0H
;
266 extern __at(0x0006) __sfr FSR1
;
267 extern __at(0x0006) __sfr FSR1L
;
268 extern __at(0x0007) __sfr FSR1H
;
270 //==============================================================================
273 extern __at(0x0008) __sfr BSR
;
296 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
304 //==============================================================================
306 extern __at(0x0009) __sfr WREG
;
307 extern __at(0x000A) __sfr PCLATH
;
309 //==============================================================================
312 extern __at(0x000B) __sfr INTCON
;
341 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
354 //==============================================================================
357 //==============================================================================
360 extern __at(0x000C) __sfr PORTA
;
383 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
392 //==============================================================================
395 //==============================================================================
398 extern __at(0x000D) __sfr PORTB
;
412 extern __at(0x000D) volatile __PORTBbits_t PORTBbits
;
419 //==============================================================================
422 //==============================================================================
425 extern __at(0x000E) __sfr PORTC
;
439 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
450 //==============================================================================
453 //==============================================================================
456 extern __at(0x0011) __sfr PIR1
;
467 unsigned TMR1GIF
: 1;
470 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
478 #define _TMR1GIF 0x80
480 //==============================================================================
483 //==============================================================================
486 extern __at(0x0012) __sfr PIR2
;
500 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
508 //==============================================================================
511 //==============================================================================
514 extern __at(0x0013) __sfr PIR3
;
528 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
535 //==============================================================================
537 extern __at(0x0015) __sfr TMR0
;
538 extern __at(0x0016) __sfr TMR1
;
539 extern __at(0x0016) __sfr TMR1L
;
540 extern __at(0x0017) __sfr TMR1H
;
542 //==============================================================================
545 extern __at(0x0018) __sfr T1CON
;
553 unsigned NOT_T1SYNC
: 1;
554 unsigned T1OSCEN
: 1;
555 unsigned T1CKPS0
: 1;
556 unsigned T1CKPS1
: 1;
557 unsigned TMR1CS0
: 1;
558 unsigned TMR1CS1
: 1;
575 extern __at(0x0018) volatile __T1CONbits_t T1CONbits
;
578 #define _NOT_T1SYNC 0x04
579 #define _T1OSCEN 0x08
580 #define _T1CKPS0 0x10
581 #define _T1CKPS1 0x20
582 #define _TMR1CS0 0x40
583 #define _TMR1CS1 0x80
585 //==============================================================================
588 //==============================================================================
591 extern __at(0x0019) __sfr T1GCON
;
600 unsigned T1GGO_NOT_DONE
: 1;
614 extern __at(0x0019) volatile __T1GCONbits_t T1GCONbits
;
619 #define _T1GGO_NOT_DONE 0x08
625 //==============================================================================
627 extern __at(0x001A) __sfr TMR2
;
628 extern __at(0x001B) __sfr PR2
;
630 //==============================================================================
633 extern __at(0x001C) __sfr T2CON
;
639 unsigned T2CKPS0
: 1;
640 unsigned T2CKPS1
: 1;
642 unsigned T2OUTPS0
: 1;
643 unsigned T2OUTPS1
: 1;
644 unsigned T2OUTPS2
: 1;
645 unsigned T2OUTPS3
: 1;
658 unsigned T2OUTPS
: 4;
663 extern __at(0x001C) volatile __T2CONbits_t T2CONbits
;
665 #define _T2CKPS0 0x01
666 #define _T2CKPS1 0x02
668 #define _T2OUTPS0 0x08
669 #define _T2OUTPS1 0x10
670 #define _T2OUTPS2 0x20
671 #define _T2OUTPS3 0x40
673 //==============================================================================
676 //==============================================================================
679 extern __at(0x008C) __sfr TRISA
;
702 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
711 //==============================================================================
714 //==============================================================================
717 extern __at(0x008D) __sfr TRISB
;
731 extern __at(0x008D) volatile __TRISBbits_t TRISBbits
;
738 //==============================================================================
741 //==============================================================================
744 extern __at(0x008E) __sfr TRISC
;
758 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
769 //==============================================================================
772 //==============================================================================
775 extern __at(0x0091) __sfr PIE1
;
786 unsigned TMR1GIE
: 1;
789 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
797 #define _TMR1GIE 0x80
799 //==============================================================================
802 //==============================================================================
805 extern __at(0x0092) __sfr PIE2
;
819 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
827 //==============================================================================
830 //==============================================================================
833 extern __at(0x0093) __sfr PIE3
;
847 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
854 //==============================================================================
857 //==============================================================================
860 extern __at(0x0095) __sfr OPTION_REG
;
873 unsigned NOT_WPUEN
: 1;
893 } __OPTION_REGbits_t
;
895 extern __at(0x0095) volatile __OPTION_REGbits_t OPTION_REGbits
;
906 #define _NOT_WPUEN 0x80
908 //==============================================================================
911 //==============================================================================
914 extern __at(0x0096) __sfr PCON
;
918 unsigned NOT_BOR
: 1;
919 unsigned NOT_POR
: 1;
921 unsigned NOT_RMCLR
: 1;
922 unsigned NOT_RWDT
: 1;
928 extern __at(0x0096) volatile __PCONbits_t PCONbits
;
930 #define _NOT_BOR 0x01
931 #define _NOT_POR 0x02
933 #define _NOT_RMCLR 0x08
934 #define _NOT_RWDT 0x10
938 //==============================================================================
941 //==============================================================================
944 extern __at(0x0097) __sfr WDTCON
;
968 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
977 //==============================================================================
980 //==============================================================================
983 extern __at(0x0099) __sfr OSCCON
;
1013 extern __at(0x0099) volatile __OSCCONbits_t OSCCONbits
;
1022 //==============================================================================
1025 //==============================================================================
1028 extern __at(0x009A) __sfr OSCSTAT
;
1032 unsigned HFIOFS
: 1;
1033 unsigned LFIOFR
: 1;
1036 unsigned HFIOFR
: 1;
1042 extern __at(0x009A) volatile __OSCSTATbits_t OSCSTATbits
;
1044 #define _HFIOFS 0x01
1045 #define _LFIOFR 0x02
1046 #define _HFIOFR 0x10
1050 //==============================================================================
1052 extern __at(0x009B) __sfr ADRES
;
1053 extern __at(0x009B) __sfr ADRESL
;
1054 extern __at(0x009C) __sfr ADRESH
;
1056 //==============================================================================
1059 extern __at(0x009D) __sfr ADCON0
;
1066 unsigned GO_NOT_DONE
: 1;
1107 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1110 #define _GO_NOT_DONE 0x02
1119 //==============================================================================
1122 //==============================================================================
1125 extern __at(0x009E) __sfr ADCON1
;
1131 unsigned ADPREF0
: 1;
1132 unsigned ADPREF1
: 1;
1143 unsigned ADPREF
: 2;
1148 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1150 #define _ADPREF0 0x01
1151 #define _ADPREF1 0x02
1154 //==============================================================================
1157 //==============================================================================
1160 extern __at(0x009F) __sfr ADCON2
;
1170 unsigned TRIGSEL0
: 1;
1171 unsigned TRIGSEL1
: 1;
1172 unsigned TRIGSEL2
: 1;
1173 unsigned TRIGSEL3
: 1;
1179 unsigned TRIGSEL
: 4;
1183 extern __at(0x009F) volatile __ADCON2bits_t ADCON2bits
;
1185 #define _TRIGSEL0 0x10
1186 #define _TRIGSEL1 0x20
1187 #define _TRIGSEL2 0x40
1188 #define _TRIGSEL3 0x80
1190 //==============================================================================
1193 //==============================================================================
1196 extern __at(0x010C) __sfr LATA
;
1210 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1218 //==============================================================================
1221 //==============================================================================
1224 extern __at(0x010D) __sfr LATB
;
1238 extern __at(0x010D) volatile __LATBbits_t LATBbits
;
1245 //==============================================================================
1248 //==============================================================================
1251 extern __at(0x010E) __sfr LATC
;
1265 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1276 //==============================================================================
1279 //==============================================================================
1282 extern __at(0x0111) __sfr CM1CON0
;
1286 unsigned C1SYNC
: 1;
1296 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1298 #define _C1SYNC 0x01
1306 //==============================================================================
1309 //==============================================================================
1312 extern __at(0x0112) __sfr CM1CON1
;
1318 unsigned C1NCH0
: 1;
1319 unsigned C1NCH1
: 1;
1320 unsigned C1NCH2
: 1;
1322 unsigned C1PCH0
: 1;
1323 unsigned C1PCH1
: 1;
1324 unsigned C1INTN
: 1;
1325 unsigned C1INTP
: 1;
1342 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1344 #define _C1NCH0 0x01
1345 #define _C1NCH1 0x02
1346 #define _C1NCH2 0x04
1347 #define _C1PCH0 0x10
1348 #define _C1PCH1 0x20
1349 #define _C1INTN 0x40
1350 #define _C1INTP 0x80
1352 //==============================================================================
1355 //==============================================================================
1358 extern __at(0x0113) __sfr CM2CON0
;
1362 unsigned C2SYNC
: 1;
1372 extern __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits
;
1374 #define _C2SYNC 0x01
1382 //==============================================================================
1385 //==============================================================================
1388 extern __at(0x0114) __sfr CM2CON1
;
1394 unsigned C2NCH0
: 1;
1395 unsigned C2NCH1
: 1;
1396 unsigned C2NCH2
: 1;
1398 unsigned C2PCH0
: 1;
1399 unsigned C2PCH1
: 1;
1400 unsigned C2INTN
: 1;
1401 unsigned C2INTP
: 1;
1418 extern __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits
;
1420 #define _C2NCH0 0x01
1421 #define _C2NCH1 0x02
1422 #define _C2NCH2 0x04
1423 #define _C2PCH0 0x10
1424 #define _C2PCH1 0x20
1425 #define _C2INTN 0x40
1426 #define _C2INTP 0x80
1428 //==============================================================================
1431 //==============================================================================
1434 extern __at(0x0115) __sfr CMOUT
;
1438 unsigned MC1OUT
: 1;
1439 unsigned MC2OUT
: 1;
1448 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1450 #define _MC1OUT 0x01
1451 #define _MC2OUT 0x02
1453 //==============================================================================
1456 //==============================================================================
1459 extern __at(0x0116) __sfr BORCON
;
1463 unsigned BORRDY
: 1;
1470 unsigned SBOREN
: 1;
1473 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1475 #define _BORRDY 0x01
1477 #define _SBOREN 0x80
1479 //==============================================================================
1482 //==============================================================================
1485 extern __at(0x0117) __sfr FVRCON
;
1491 unsigned ADFVR0
: 1;
1492 unsigned ADFVR1
: 1;
1493 unsigned CDAFVR0
: 1;
1494 unsigned CDAFVR1
: 1;
1497 unsigned FVRRDY
: 1;
1510 unsigned CDAFVR
: 2;
1515 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1517 #define _ADFVR0 0x01
1518 #define _ADFVR1 0x02
1519 #define _CDAFVR0 0x04
1520 #define _CDAFVR1 0x08
1523 #define _FVRRDY 0x40
1526 //==============================================================================
1529 //==============================================================================
1532 extern __at(0x0118) __sfr DACCON0
;
1538 unsigned DACPSS
: 1;
1540 unsigned DACOE2
: 1;
1541 unsigned DACOE1
: 1;
1546 extern __at(0x0118) volatile __DACCON0bits_t DACCON0bits
;
1548 #define _DACPSS 0x04
1549 #define _DACOE2 0x10
1550 #define _DACOE1 0x20
1553 //==============================================================================
1556 //==============================================================================
1559 extern __at(0x0119) __sfr DACCON1
;
1582 extern __at(0x0119) volatile __DACCON1bits_t DACCON1bits
;
1590 //==============================================================================
1593 //==============================================================================
1596 extern __at(0x011D) __sfr APFCON
;
1602 unsigned NCO1SEL
: 1;
1603 unsigned CLC1SEL
: 1;
1605 unsigned T1GSEL
: 1;
1614 unsigned NCOSEL
: 1;
1625 extern __at(0x011D) volatile __APFCONbits_t APFCONbits
;
1627 #define _NCO1SEL 0x01
1628 #define _NCOSEL 0x01
1629 #define _CLC1SEL 0x02
1630 #define _T1GSEL 0x08
1633 //==============================================================================
1636 //==============================================================================
1639 extern __at(0x018C) __sfr ANSELA
;
1653 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1660 //==============================================================================
1663 //==============================================================================
1666 extern __at(0x018D) __sfr ANSELB
;
1680 extern __at(0x018D) volatile __ANSELBbits_t ANSELBbits
;
1685 //==============================================================================
1688 //==============================================================================
1691 extern __at(0x018E) __sfr ANSELC
;
1705 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
1714 //==============================================================================
1716 extern __at(0x0191) __sfr PMADR
;
1717 extern __at(0x0191) __sfr PMADRL
;
1718 extern __at(0x0192) __sfr PMADRH
;
1719 extern __at(0x0193) __sfr PMDAT
;
1720 extern __at(0x0193) __sfr PMDATL
;
1721 extern __at(0x0194) __sfr PMDATH
;
1723 //==============================================================================
1726 extern __at(0x0195) __sfr PMCON1
;
1740 extern __at(0x0195) volatile __PMCON1bits_t PMCON1bits
;
1750 //==============================================================================
1752 extern __at(0x0196) __sfr PMCON2
;
1754 //==============================================================================
1757 extern __at(0x0197) __sfr VREGCON
;
1761 unsigned Reserved
: 1;
1762 unsigned VREGPM
: 1;
1771 extern __at(0x0197) volatile __VREGCONbits_t VREGCONbits
;
1773 #define _Reserved 0x01
1774 #define _VREGPM 0x02
1776 //==============================================================================
1778 extern __at(0x0199) __sfr RCREG
;
1779 extern __at(0x019A) __sfr TXREG
;
1780 extern __at(0x019B) __sfr SPBRG
;
1781 extern __at(0x019B) __sfr SPBRGL
;
1782 extern __at(0x019C) __sfr SPBRGH
;
1784 //==============================================================================
1787 extern __at(0x019D) __sfr RCSTA
;
1801 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
1812 //==============================================================================
1815 //==============================================================================
1818 extern __at(0x019E) __sfr TXSTA
;
1832 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
1843 //==============================================================================
1846 //==============================================================================
1849 extern __at(0x019F) __sfr BAUDCON
;
1860 unsigned ABDOVF
: 1;
1863 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
1870 #define _ABDOVF 0x80
1872 //==============================================================================
1875 //==============================================================================
1878 extern __at(0x020C) __sfr WPUA
;
1901 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
1910 //==============================================================================
1913 //==============================================================================
1916 extern __at(0x020D) __sfr WPUB
;
1930 extern __at(0x020D) volatile __WPUBbits_t WPUBbits
;
1937 //==============================================================================
1939 extern __at(0x0211) __sfr SSP1BUF
;
1940 extern __at(0x0211) __sfr SSPBUF
;
1941 extern __at(0x0212) __sfr SSP1ADD
;
1942 extern __at(0x0212) __sfr SSPADD
;
1943 extern __at(0x0213) __sfr SSP1MSK
;
1944 extern __at(0x0213) __sfr SSPMSK
;
1946 //==============================================================================
1949 extern __at(0x0214) __sfr SSP1STAT
;
1955 unsigned R_NOT_W
: 1;
1958 unsigned D_NOT_A
: 1;
1963 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
1967 #define _R_NOT_W 0x04
1970 #define _D_NOT_A 0x20
1974 //==============================================================================
1977 //==============================================================================
1980 extern __at(0x0214) __sfr SSPSTAT
;
1986 unsigned R_NOT_W
: 1;
1989 unsigned D_NOT_A
: 1;
1994 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
1996 #define _SSPSTAT_BF 0x01
1997 #define _SSPSTAT_UA 0x02
1998 #define _SSPSTAT_R_NOT_W 0x04
1999 #define _SSPSTAT_S 0x08
2000 #define _SSPSTAT_P 0x10
2001 #define _SSPSTAT_D_NOT_A 0x20
2002 #define _SSPSTAT_CKE 0x40
2003 #define _SSPSTAT_SMP 0x80
2005 //==============================================================================
2008 //==============================================================================
2011 extern __at(0x0215) __sfr SSP1CON1
;
2034 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
2045 //==============================================================================
2048 //==============================================================================
2051 extern __at(0x0215) __sfr SSPCON
;
2074 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2076 #define _SSPCON_SSPM0 0x01
2077 #define _SSPCON_SSPM1 0x02
2078 #define _SSPCON_SSPM2 0x04
2079 #define _SSPCON_SSPM3 0x08
2080 #define _SSPCON_CKP 0x10
2081 #define _SSPCON_SSPEN 0x20
2082 #define _SSPCON_SSPOV 0x40
2083 #define _SSPCON_WCOL 0x80
2085 //==============================================================================
2088 //==============================================================================
2091 extern __at(0x0215) __sfr SSPCON1
;
2114 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2116 #define _SSPCON1_SSPM0 0x01
2117 #define _SSPCON1_SSPM1 0x02
2118 #define _SSPCON1_SSPM2 0x04
2119 #define _SSPCON1_SSPM3 0x08
2120 #define _SSPCON1_CKP 0x10
2121 #define _SSPCON1_SSPEN 0x20
2122 #define _SSPCON1_SSPOV 0x40
2123 #define _SSPCON1_WCOL 0x80
2125 //==============================================================================
2128 //==============================================================================
2131 extern __at(0x0216) __sfr SSP1CON2
;
2141 unsigned ACKSTAT
: 1;
2145 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
2153 #define _ACKSTAT 0x40
2156 //==============================================================================
2159 //==============================================================================
2162 extern __at(0x0216) __sfr SSPCON2
;
2172 unsigned ACKSTAT
: 1;
2176 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
2178 #define _SSPCON2_SEN 0x01
2179 #define _SSPCON2_RSEN 0x02
2180 #define _SSPCON2_PEN 0x04
2181 #define _SSPCON2_RCEN 0x08
2182 #define _SSPCON2_ACKEN 0x10
2183 #define _SSPCON2_ACKDT 0x20
2184 #define _SSPCON2_ACKSTAT 0x40
2185 #define _SSPCON2_GCEN 0x80
2187 //==============================================================================
2190 //==============================================================================
2193 extern __at(0x0217) __sfr SSP1CON3
;
2204 unsigned ACKTIM
: 1;
2207 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
2216 #define _ACKTIM 0x80
2218 //==============================================================================
2221 //==============================================================================
2224 extern __at(0x0217) __sfr SSPCON3
;
2235 unsigned ACKTIM
: 1;
2238 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
2240 #define _SSPCON3_DHEN 0x01
2241 #define _SSPCON3_AHEN 0x02
2242 #define _SSPCON3_SBCDE 0x04
2243 #define _SSPCON3_SDAHT 0x08
2244 #define _SSPCON3_BOEN 0x10
2245 #define _SSPCON3_SCIE 0x20
2246 #define _SSPCON3_PCIE 0x40
2247 #define _SSPCON3_ACKTIM 0x80
2249 //==============================================================================
2252 //==============================================================================
2255 extern __at(0x0391) __sfr IOCAP
;
2261 unsigned IOCAP0
: 1;
2262 unsigned IOCAP1
: 1;
2263 unsigned IOCAP2
: 1;
2264 unsigned IOCAP3
: 1;
2265 unsigned IOCAP4
: 1;
2266 unsigned IOCAP5
: 1;
2278 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
2280 #define _IOCAP0 0x01
2281 #define _IOCAP1 0x02
2282 #define _IOCAP2 0x04
2283 #define _IOCAP3 0x08
2284 #define _IOCAP4 0x10
2285 #define _IOCAP5 0x20
2287 //==============================================================================
2290 //==============================================================================
2293 extern __at(0x0392) __sfr IOCAN
;
2299 unsigned IOCAN0
: 1;
2300 unsigned IOCAN1
: 1;
2301 unsigned IOCAN2
: 1;
2302 unsigned IOCAN3
: 1;
2303 unsigned IOCAN4
: 1;
2304 unsigned IOCAN5
: 1;
2316 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
2318 #define _IOCAN0 0x01
2319 #define _IOCAN1 0x02
2320 #define _IOCAN2 0x04
2321 #define _IOCAN3 0x08
2322 #define _IOCAN4 0x10
2323 #define _IOCAN5 0x20
2325 //==============================================================================
2328 //==============================================================================
2331 extern __at(0x0393) __sfr IOCAF
;
2337 unsigned IOCAF0
: 1;
2338 unsigned IOCAF1
: 1;
2339 unsigned IOCAF2
: 1;
2340 unsigned IOCAF3
: 1;
2341 unsigned IOCAF4
: 1;
2342 unsigned IOCAF5
: 1;
2354 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
2356 #define _IOCAF0 0x01
2357 #define _IOCAF1 0x02
2358 #define _IOCAF2 0x04
2359 #define _IOCAF3 0x08
2360 #define _IOCAF4 0x10
2361 #define _IOCAF5 0x20
2363 //==============================================================================
2366 //==============================================================================
2369 extern __at(0x0394) __sfr IOCBP
;
2377 unsigned IOCBP4
: 1;
2378 unsigned IOCBP5
: 1;
2379 unsigned IOCBP6
: 1;
2380 unsigned IOCBP7
: 1;
2383 extern __at(0x0394) volatile __IOCBPbits_t IOCBPbits
;
2385 #define _IOCBP4 0x10
2386 #define _IOCBP5 0x20
2387 #define _IOCBP6 0x40
2388 #define _IOCBP7 0x80
2390 //==============================================================================
2393 //==============================================================================
2396 extern __at(0x0395) __sfr IOCBN
;
2404 unsigned IOCBN4
: 1;
2405 unsigned IOCBN5
: 1;
2406 unsigned IOCBN6
: 1;
2407 unsigned IOCBN7
: 1;
2410 extern __at(0x0395) volatile __IOCBNbits_t IOCBNbits
;
2412 #define _IOCBN4 0x10
2413 #define _IOCBN5 0x20
2414 #define _IOCBN6 0x40
2415 #define _IOCBN7 0x80
2417 //==============================================================================
2420 //==============================================================================
2423 extern __at(0x0396) __sfr IOCBF
;
2431 unsigned IOCBF4
: 1;
2432 unsigned IOCBF5
: 1;
2433 unsigned IOCBF6
: 1;
2434 unsigned IOCBF7
: 1;
2437 extern __at(0x0396) volatile __IOCBFbits_t IOCBFbits
;
2439 #define _IOCBF4 0x10
2440 #define _IOCBF5 0x20
2441 #define _IOCBF6 0x40
2442 #define _IOCBF7 0x80
2444 //==============================================================================
2446 extern __at(0x0498) __sfr NCO1ACC
;
2448 //==============================================================================
2451 extern __at(0x0498) __sfr NCO1ACCL
;
2455 unsigned NCO1ACC0
: 1;
2456 unsigned NCO1ACC1
: 1;
2457 unsigned NCO1ACC2
: 1;
2458 unsigned NCO1ACC3
: 1;
2459 unsigned NCO1ACC4
: 1;
2460 unsigned NCO1ACC5
: 1;
2461 unsigned NCO1ACC6
: 1;
2462 unsigned NCO1ACC7
: 1;
2465 extern __at(0x0498) volatile __NCO1ACCLbits_t NCO1ACCLbits
;
2467 #define _NCO1ACC0 0x01
2468 #define _NCO1ACC1 0x02
2469 #define _NCO1ACC2 0x04
2470 #define _NCO1ACC3 0x08
2471 #define _NCO1ACC4 0x10
2472 #define _NCO1ACC5 0x20
2473 #define _NCO1ACC6 0x40
2474 #define _NCO1ACC7 0x80
2476 //==============================================================================
2479 //==============================================================================
2482 extern __at(0x0499) __sfr NCO1ACCH
;
2486 unsigned NCO1ACC8
: 1;
2487 unsigned NCO1ACC9
: 1;
2488 unsigned NCO1ACC10
: 1;
2489 unsigned NCO1ACC11
: 1;
2490 unsigned NCO1ACC12
: 1;
2491 unsigned NCO1ACC13
: 1;
2492 unsigned NCO1ACC14
: 1;
2493 unsigned NCO1ACC15
: 1;
2496 extern __at(0x0499) volatile __NCO1ACCHbits_t NCO1ACCHbits
;
2498 #define _NCO1ACC8 0x01
2499 #define _NCO1ACC9 0x02
2500 #define _NCO1ACC10 0x04
2501 #define _NCO1ACC11 0x08
2502 #define _NCO1ACC12 0x10
2503 #define _NCO1ACC13 0x20
2504 #define _NCO1ACC14 0x40
2505 #define _NCO1ACC15 0x80
2507 //==============================================================================
2510 //==============================================================================
2513 extern __at(0x049A) __sfr NCO1ACCU
;
2517 unsigned NCO1ACC16
: 1;
2518 unsigned NCO1ACC17
: 1;
2519 unsigned NCO1ACC18
: 1;
2520 unsigned NCO1ACC19
: 1;
2527 extern __at(0x049A) volatile __NCO1ACCUbits_t NCO1ACCUbits
;
2529 #define _NCO1ACC16 0x01
2530 #define _NCO1ACC17 0x02
2531 #define _NCO1ACC18 0x04
2532 #define _NCO1ACC19 0x08
2534 //==============================================================================
2536 extern __at(0x049B) __sfr NCO1INC
;
2538 //==============================================================================
2541 extern __at(0x049B) __sfr NCO1INCL
;
2545 unsigned NCO1INC0
: 1;
2546 unsigned NCO1INC1
: 1;
2547 unsigned NCO1INC2
: 1;
2548 unsigned NCO1INC3
: 1;
2549 unsigned NCO1INC4
: 1;
2550 unsigned NCO1INC5
: 1;
2551 unsigned NCO1INC6
: 1;
2552 unsigned NCO1INC7
: 1;
2555 extern __at(0x049B) volatile __NCO1INCLbits_t NCO1INCLbits
;
2557 #define _NCO1INC0 0x01
2558 #define _NCO1INC1 0x02
2559 #define _NCO1INC2 0x04
2560 #define _NCO1INC3 0x08
2561 #define _NCO1INC4 0x10
2562 #define _NCO1INC5 0x20
2563 #define _NCO1INC6 0x40
2564 #define _NCO1INC7 0x80
2566 //==============================================================================
2569 //==============================================================================
2572 extern __at(0x049C) __sfr NCO1INCH
;
2576 unsigned NCO1INC8
: 1;
2577 unsigned NCO1INC9
: 1;
2578 unsigned NCO1INC10
: 1;
2579 unsigned NCO1INC11
: 1;
2580 unsigned NCO1INC12
: 1;
2581 unsigned NCO1INC13
: 1;
2582 unsigned NCO1INC14
: 1;
2583 unsigned NCO1INC15
: 1;
2586 extern __at(0x049C) volatile __NCO1INCHbits_t NCO1INCHbits
;
2588 #define _NCO1INC8 0x01
2589 #define _NCO1INC9 0x02
2590 #define _NCO1INC10 0x04
2591 #define _NCO1INC11 0x08
2592 #define _NCO1INC12 0x10
2593 #define _NCO1INC13 0x20
2594 #define _NCO1INC14 0x40
2595 #define _NCO1INC15 0x80
2597 //==============================================================================
2599 extern __at(0x049D) __sfr NCO1INCU
;
2601 //==============================================================================
2604 extern __at(0x049E) __sfr NCO1CON
;
2618 extern __at(0x049E) volatile __NCO1CONbits_t NCO1CONbits
;
2626 //==============================================================================
2629 //==============================================================================
2632 extern __at(0x049F) __sfr NCO1CLK
;
2638 unsigned N1CKS0
: 1;
2639 unsigned N1CKS1
: 1;
2643 unsigned N1PWS0
: 1;
2644 unsigned N1PWS1
: 1;
2645 unsigned N1PWS2
: 1;
2661 extern __at(0x049F) volatile __NCO1CLKbits_t NCO1CLKbits
;
2663 #define _N1CKS0 0x01
2664 #define _N1CKS1 0x02
2665 #define _N1PWS0 0x20
2666 #define _N1PWS1 0x40
2667 #define _N1PWS2 0x80
2669 //==============================================================================
2672 //==============================================================================
2675 extern __at(0x0611) __sfr PWM1DCL
;
2687 unsigned PWM1DCL0
: 1;
2688 unsigned PWM1DCL1
: 1;
2694 unsigned PWM1DCL
: 2;
2698 extern __at(0x0611) volatile __PWM1DCLbits_t PWM1DCLbits
;
2700 #define _PWM1DCL0 0x40
2701 #define _PWM1DCL1 0x80
2703 //==============================================================================
2706 //==============================================================================
2709 extern __at(0x0612) __sfr PWM1DCH
;
2713 unsigned PWM1DCH0
: 1;
2714 unsigned PWM1DCH1
: 1;
2715 unsigned PWM1DCH2
: 1;
2716 unsigned PWM1DCH3
: 1;
2717 unsigned PWM1DCH4
: 1;
2718 unsigned PWM1DCH5
: 1;
2719 unsigned PWM1DCH6
: 1;
2720 unsigned PWM1DCH7
: 1;
2723 extern __at(0x0612) volatile __PWM1DCHbits_t PWM1DCHbits
;
2725 #define _PWM1DCH0 0x01
2726 #define _PWM1DCH1 0x02
2727 #define _PWM1DCH2 0x04
2728 #define _PWM1DCH3 0x08
2729 #define _PWM1DCH4 0x10
2730 #define _PWM1DCH5 0x20
2731 #define _PWM1DCH6 0x40
2732 #define _PWM1DCH7 0x80
2734 //==============================================================================
2737 //==============================================================================
2740 extern __at(0x0613) __sfr PWM1CON
;
2748 unsigned PWM1POL
: 1;
2749 unsigned PWM1OUT
: 1;
2750 unsigned PWM1OE
: 1;
2751 unsigned PWM1EN
: 1;
2754 extern __at(0x0613) volatile __PWM1CONbits_t PWM1CONbits
;
2756 #define _PWM1POL 0x10
2757 #define _PWM1OUT 0x20
2758 #define _PWM1OE 0x40
2759 #define _PWM1EN 0x80
2761 //==============================================================================
2764 //==============================================================================
2767 extern __at(0x0613) __sfr PWM1CON0
;
2775 unsigned PWM1POL
: 1;
2776 unsigned PWM1OUT
: 1;
2777 unsigned PWM1OE
: 1;
2778 unsigned PWM1EN
: 1;
2781 extern __at(0x0613) volatile __PWM1CON0bits_t PWM1CON0bits
;
2783 #define _PWM1CON0_PWM1POL 0x10
2784 #define _PWM1CON0_PWM1OUT 0x20
2785 #define _PWM1CON0_PWM1OE 0x40
2786 #define _PWM1CON0_PWM1EN 0x80
2788 //==============================================================================
2791 //==============================================================================
2794 extern __at(0x0614) __sfr PWM2DCL
;
2806 unsigned PWM2DCL0
: 1;
2807 unsigned PWM2DCL1
: 1;
2813 unsigned PWM2DCL
: 2;
2817 extern __at(0x0614) volatile __PWM2DCLbits_t PWM2DCLbits
;
2819 #define _PWM2DCL0 0x40
2820 #define _PWM2DCL1 0x80
2822 //==============================================================================
2825 //==============================================================================
2828 extern __at(0x0615) __sfr PWM2DCH
;
2832 unsigned PWM2DCH0
: 1;
2833 unsigned PWM2DCH1
: 1;
2834 unsigned PWM2DCH2
: 1;
2835 unsigned PWM2DCH3
: 1;
2836 unsigned PWM2DCH4
: 1;
2837 unsigned PWM2DCH5
: 1;
2838 unsigned PWM2DCH6
: 1;
2839 unsigned PWM2DCH7
: 1;
2842 extern __at(0x0615) volatile __PWM2DCHbits_t PWM2DCHbits
;
2844 #define _PWM2DCH0 0x01
2845 #define _PWM2DCH1 0x02
2846 #define _PWM2DCH2 0x04
2847 #define _PWM2DCH3 0x08
2848 #define _PWM2DCH4 0x10
2849 #define _PWM2DCH5 0x20
2850 #define _PWM2DCH6 0x40
2851 #define _PWM2DCH7 0x80
2853 //==============================================================================
2856 //==============================================================================
2859 extern __at(0x0616) __sfr PWM2CON
;
2867 unsigned PWM2POL
: 1;
2868 unsigned PWM2OUT
: 1;
2869 unsigned PWM2OE
: 1;
2870 unsigned PWM2EN
: 1;
2873 extern __at(0x0616) volatile __PWM2CONbits_t PWM2CONbits
;
2875 #define _PWM2POL 0x10
2876 #define _PWM2OUT 0x20
2877 #define _PWM2OE 0x40
2878 #define _PWM2EN 0x80
2880 //==============================================================================
2883 //==============================================================================
2886 extern __at(0x0616) __sfr PWM2CON0
;
2894 unsigned PWM2POL
: 1;
2895 unsigned PWM2OUT
: 1;
2896 unsigned PWM2OE
: 1;
2897 unsigned PWM2EN
: 1;
2900 extern __at(0x0616) volatile __PWM2CON0bits_t PWM2CON0bits
;
2902 #define _PWM2CON0_PWM2POL 0x10
2903 #define _PWM2CON0_PWM2OUT 0x20
2904 #define _PWM2CON0_PWM2OE 0x40
2905 #define _PWM2CON0_PWM2EN 0x80
2907 //==============================================================================
2910 //==============================================================================
2913 extern __at(0x0617) __sfr PWM3DCL
;
2925 unsigned PWM3DCL0
: 1;
2926 unsigned PWM3DCL1
: 1;
2932 unsigned PWM3DCL
: 2;
2936 extern __at(0x0617) volatile __PWM3DCLbits_t PWM3DCLbits
;
2938 #define _PWM3DCL0 0x40
2939 #define _PWM3DCL1 0x80
2941 //==============================================================================
2944 //==============================================================================
2947 extern __at(0x0618) __sfr PWM3DCH
;
2951 unsigned PWM3DCH0
: 1;
2952 unsigned PWM3DCH1
: 1;
2953 unsigned PWM3DCH2
: 1;
2954 unsigned PWM3DCH3
: 1;
2955 unsigned PWM3DCH4
: 1;
2956 unsigned PWM3DCH5
: 1;
2957 unsigned PWM3DCH6
: 1;
2958 unsigned PWM3DCH7
: 1;
2961 extern __at(0x0618) volatile __PWM3DCHbits_t PWM3DCHbits
;
2963 #define _PWM3DCH0 0x01
2964 #define _PWM3DCH1 0x02
2965 #define _PWM3DCH2 0x04
2966 #define _PWM3DCH3 0x08
2967 #define _PWM3DCH4 0x10
2968 #define _PWM3DCH5 0x20
2969 #define _PWM3DCH6 0x40
2970 #define _PWM3DCH7 0x80
2972 //==============================================================================
2975 //==============================================================================
2978 extern __at(0x0619) __sfr PWM3CON
;
2986 unsigned PWM3POL
: 1;
2987 unsigned PWM3OUT
: 1;
2988 unsigned PWM3OE
: 1;
2989 unsigned PWM3EN
: 1;
2992 extern __at(0x0619) volatile __PWM3CONbits_t PWM3CONbits
;
2994 #define _PWM3POL 0x10
2995 #define _PWM3OUT 0x20
2996 #define _PWM3OE 0x40
2997 #define _PWM3EN 0x80
2999 //==============================================================================
3002 //==============================================================================
3005 extern __at(0x0619) __sfr PWM3CON0
;
3013 unsigned PWM3POL
: 1;
3014 unsigned PWM3OUT
: 1;
3015 unsigned PWM3OE
: 1;
3016 unsigned PWM3EN
: 1;
3019 extern __at(0x0619) volatile __PWM3CON0bits_t PWM3CON0bits
;
3021 #define _PWM3CON0_PWM3POL 0x10
3022 #define _PWM3CON0_PWM3OUT 0x20
3023 #define _PWM3CON0_PWM3OE 0x40
3024 #define _PWM3CON0_PWM3EN 0x80
3026 //==============================================================================
3029 //==============================================================================
3032 extern __at(0x061A) __sfr PWM4DCL
;
3044 unsigned PWM4DCL0
: 1;
3045 unsigned PWM4DCL1
: 1;
3051 unsigned PWM4DCL
: 2;
3055 extern __at(0x061A) volatile __PWM4DCLbits_t PWM4DCLbits
;
3057 #define _PWM4DCL0 0x40
3058 #define _PWM4DCL1 0x80
3060 //==============================================================================
3063 //==============================================================================
3066 extern __at(0x061B) __sfr PWM4DCH
;
3070 unsigned PWM4DCH0
: 1;
3071 unsigned PWM4DCH1
: 1;
3072 unsigned PWM4DCH2
: 1;
3073 unsigned PWM4DCH3
: 1;
3074 unsigned PWM4DCH4
: 1;
3075 unsigned PWM4DCH5
: 1;
3076 unsigned PWM4DCH6
: 1;
3077 unsigned PWM4DCH7
: 1;
3080 extern __at(0x061B) volatile __PWM4DCHbits_t PWM4DCHbits
;
3082 #define _PWM4DCH0 0x01
3083 #define _PWM4DCH1 0x02
3084 #define _PWM4DCH2 0x04
3085 #define _PWM4DCH3 0x08
3086 #define _PWM4DCH4 0x10
3087 #define _PWM4DCH5 0x20
3088 #define _PWM4DCH6 0x40
3089 #define _PWM4DCH7 0x80
3091 //==============================================================================
3094 //==============================================================================
3097 extern __at(0x061C) __sfr PWM4CON
;
3105 unsigned PWM4POL
: 1;
3106 unsigned PWM4OUT
: 1;
3107 unsigned PWM4OE
: 1;
3108 unsigned PWM4EN
: 1;
3111 extern __at(0x061C) volatile __PWM4CONbits_t PWM4CONbits
;
3113 #define _PWM4POL 0x10
3114 #define _PWM4OUT 0x20
3115 #define _PWM4OE 0x40
3116 #define _PWM4EN 0x80
3118 //==============================================================================
3121 //==============================================================================
3124 extern __at(0x061C) __sfr PWM4CON0
;
3132 unsigned PWM4POL
: 1;
3133 unsigned PWM4OUT
: 1;
3134 unsigned PWM4OE
: 1;
3135 unsigned PWM4EN
: 1;
3138 extern __at(0x061C) volatile __PWM4CON0bits_t PWM4CON0bits
;
3140 #define _PWM4CON0_PWM4POL 0x10
3141 #define _PWM4CON0_PWM4OUT 0x20
3142 #define _PWM4CON0_PWM4OE 0x40
3143 #define _PWM4CON0_PWM4EN 0x80
3145 //==============================================================================
3148 //==============================================================================
3151 extern __at(0x0691) __sfr CWG1DBR
;
3157 unsigned CWG1DBR0
: 1;
3158 unsigned CWG1DBR1
: 1;
3159 unsigned CWG1DBR2
: 1;
3160 unsigned CWG1DBR3
: 1;
3161 unsigned CWG1DBR4
: 1;
3162 unsigned CWG1DBR5
: 1;
3169 unsigned CWG1DBR
: 6;
3174 extern __at(0x0691) volatile __CWG1DBRbits_t CWG1DBRbits
;
3176 #define _CWG1DBR0 0x01
3177 #define _CWG1DBR1 0x02
3178 #define _CWG1DBR2 0x04
3179 #define _CWG1DBR3 0x08
3180 #define _CWG1DBR4 0x10
3181 #define _CWG1DBR5 0x20
3183 //==============================================================================
3186 //==============================================================================
3189 extern __at(0x0692) __sfr CWG1DBF
;
3195 unsigned CWG1DBF0
: 1;
3196 unsigned CWG1DBF1
: 1;
3197 unsigned CWG1DBF2
: 1;
3198 unsigned CWG1DBF3
: 1;
3199 unsigned CWG1DBF4
: 1;
3200 unsigned CWG1DBF5
: 1;
3207 unsigned CWG1DBF
: 6;
3212 extern __at(0x0692) volatile __CWG1DBFbits_t CWG1DBFbits
;
3214 #define _CWG1DBF0 0x01
3215 #define _CWG1DBF1 0x02
3216 #define _CWG1DBF2 0x04
3217 #define _CWG1DBF3 0x08
3218 #define _CWG1DBF4 0x10
3219 #define _CWG1DBF5 0x20
3221 //==============================================================================
3224 //==============================================================================
3227 extern __at(0x0693) __sfr CWG1CON0
;
3234 unsigned G1POLA
: 1;
3235 unsigned G1POLB
: 1;
3241 extern __at(0x0693) volatile __CWG1CON0bits_t CWG1CON0bits
;
3244 #define _G1POLA 0x08
3245 #define _G1POLB 0x10
3250 //==============================================================================
3253 //==============================================================================
3256 extern __at(0x0694) __sfr CWG1CON1
;
3266 unsigned G1ASDLA0
: 1;
3267 unsigned G1ASDLA1
: 1;
3268 unsigned G1ASDLB0
: 1;
3269 unsigned G1ASDLB1
: 1;
3281 unsigned G1ASDLA
: 2;
3288 unsigned G1ASDLB
: 2;
3292 extern __at(0x0694) volatile __CWG1CON1bits_t CWG1CON1bits
;
3297 #define _G1ASDLA0 0x10
3298 #define _G1ASDLA1 0x20
3299 #define _G1ASDLB0 0x40
3300 #define _G1ASDLB1 0x80
3302 //==============================================================================
3305 //==============================================================================
3308 extern __at(0x0695) __sfr CWG1CON2
;
3312 unsigned G1ASDSCLC2
: 1;
3313 unsigned G1ASDSFLT
: 1;
3314 unsigned G1ASDSC1
: 1;
3315 unsigned G1ASDSC2
: 1;
3318 unsigned G1ARSEN
: 1;
3322 extern __at(0x0695) volatile __CWG1CON2bits_t CWG1CON2bits
;
3324 #define _G1ASDSCLC2 0x01
3325 #define _G1ASDSFLT 0x02
3326 #define _G1ASDSC1 0x04
3327 #define _G1ASDSC2 0x08
3328 #define _G1ARSEN 0x40
3331 //==============================================================================
3334 //==============================================================================
3337 extern __at(0x0F0F) __sfr CLCDATA
;
3341 unsigned MCLC1OUT
: 1;
3342 unsigned MCLC2OUT
: 1;
3343 unsigned MCLC3OUT
: 1;
3344 unsigned MCLC4OUT
: 1;
3351 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
3353 #define _MCLC1OUT 0x01
3354 #define _MCLC2OUT 0x02
3355 #define _MCLC3OUT 0x04
3356 #define _MCLC4OUT 0x08
3358 //==============================================================================
3361 //==============================================================================
3364 extern __at(0x0F10) __sfr CLC1CON
;
3370 unsigned LC1MODE0
: 1;
3371 unsigned LC1MODE1
: 1;
3372 unsigned LC1MODE2
: 1;
3373 unsigned LC1INTN
: 1;
3374 unsigned LC1INTP
: 1;
3375 unsigned LC1OUT
: 1;
3382 unsigned LCMODE0
: 1;
3383 unsigned LCMODE1
: 1;
3384 unsigned LCMODE2
: 1;
3385 unsigned LCINTN
: 1;
3386 unsigned LCINTP
: 1;
3394 unsigned LCMODE
: 3;
3400 unsigned LC1MODE
: 3;
3405 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
3407 #define _LC1MODE0 0x01
3408 #define _LCMODE0 0x01
3409 #define _LC1MODE1 0x02
3410 #define _LCMODE1 0x02
3411 #define _LC1MODE2 0x04
3412 #define _LCMODE2 0x04
3413 #define _LC1INTN 0x08
3414 #define _LCINTN 0x08
3415 #define _LC1INTP 0x10
3416 #define _LCINTP 0x10
3417 #define _LC1OUT 0x20
3424 //==============================================================================
3427 //==============================================================================
3430 extern __at(0x0F11) __sfr CLC1POL
;
3436 unsigned LC1G1POL
: 1;
3437 unsigned LC1G2POL
: 1;
3438 unsigned LC1G3POL
: 1;
3439 unsigned LC1G4POL
: 1;
3443 unsigned LC1POL
: 1;
3459 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
3461 #define _LC1G1POL 0x01
3463 #define _LC1G2POL 0x02
3465 #define _LC1G3POL 0x04
3467 #define _LC1G4POL 0x08
3469 #define _LC1POL 0x80
3472 //==============================================================================
3475 //==============================================================================
3478 extern __at(0x0F12) __sfr CLC1SEL0
;
3484 unsigned LC1D1S0
: 1;
3485 unsigned LC1D1S1
: 1;
3486 unsigned LC1D1S2
: 1;
3488 unsigned LC1D2S0
: 1;
3489 unsigned LC1D2S1
: 1;
3490 unsigned LC1D2S2
: 1;
3508 unsigned LC1D1S
: 3;
3528 unsigned LC1D2S
: 3;
3533 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
3535 #define _LC1D1S0 0x01
3537 #define _LC1D1S1 0x02
3539 #define _LC1D1S2 0x04
3541 #define _LC1D2S0 0x10
3543 #define _LC1D2S1 0x20
3545 #define _LC1D2S2 0x40
3548 //==============================================================================
3551 //==============================================================================
3554 extern __at(0x0F13) __sfr CLC1SEL1
;
3560 unsigned LC1D3S0
: 1;
3561 unsigned LC1D3S1
: 1;
3562 unsigned LC1D3S2
: 1;
3564 unsigned LC1D4S0
: 1;
3565 unsigned LC1D4S1
: 1;
3566 unsigned LC1D4S2
: 1;
3590 unsigned LC1D3S
: 3;
3597 unsigned LC1D4S
: 3;
3609 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
3611 #define _LC1D3S0 0x01
3613 #define _LC1D3S1 0x02
3615 #define _LC1D3S2 0x04
3617 #define _LC1D4S0 0x10
3619 #define _LC1D4S1 0x20
3621 #define _LC1D4S2 0x40
3624 //==============================================================================
3627 //==============================================================================
3630 extern __at(0x0F14) __sfr CLC1GLS0
;
3636 unsigned LC1G1D1N
: 1;
3637 unsigned LC1G1D1T
: 1;
3638 unsigned LC1G1D2N
: 1;
3639 unsigned LC1G1D2T
: 1;
3640 unsigned LC1G1D3N
: 1;
3641 unsigned LC1G1D3T
: 1;
3642 unsigned LC1G1D4N
: 1;
3643 unsigned LC1G1D4T
: 1;
3659 extern __at(0x0F14) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
3661 #define _LC1G1D1N 0x01
3663 #define _LC1G1D1T 0x02
3665 #define _LC1G1D2N 0x04
3667 #define _LC1G1D2T 0x08
3669 #define _LC1G1D3N 0x10
3671 #define _LC1G1D3T 0x20
3673 #define _LC1G1D4N 0x40
3675 #define _LC1G1D4T 0x80
3678 //==============================================================================
3681 //==============================================================================
3684 extern __at(0x0F15) __sfr CLC1GLS1
;
3690 unsigned LC1G2D1N
: 1;
3691 unsigned LC1G2D1T
: 1;
3692 unsigned LC1G2D2N
: 1;
3693 unsigned LC1G2D2T
: 1;
3694 unsigned LC1G2D3N
: 1;
3695 unsigned LC1G2D3T
: 1;
3696 unsigned LC1G2D4N
: 1;
3697 unsigned LC1G2D4T
: 1;
3713 extern __at(0x0F15) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
3715 #define _CLC1GLS1_LC1G2D1N 0x01
3716 #define _CLC1GLS1_D1N 0x01
3717 #define _CLC1GLS1_LC1G2D1T 0x02
3718 #define _CLC1GLS1_D1T 0x02
3719 #define _CLC1GLS1_LC1G2D2N 0x04
3720 #define _CLC1GLS1_D2N 0x04
3721 #define _CLC1GLS1_LC1G2D2T 0x08
3722 #define _CLC1GLS1_D2T 0x08
3723 #define _CLC1GLS1_LC1G2D3N 0x10
3724 #define _CLC1GLS1_D3N 0x10
3725 #define _CLC1GLS1_LC1G2D3T 0x20
3726 #define _CLC1GLS1_D3T 0x20
3727 #define _CLC1GLS1_LC1G2D4N 0x40
3728 #define _CLC1GLS1_D4N 0x40
3729 #define _CLC1GLS1_LC1G2D4T 0x80
3730 #define _CLC1GLS1_D4T 0x80
3732 //==============================================================================
3735 //==============================================================================
3738 extern __at(0x0F16) __sfr CLC1GLS2
;
3744 unsigned LC1G3D1N
: 1;
3745 unsigned LC1G3D1T
: 1;
3746 unsigned LC1G3D2N
: 1;
3747 unsigned LC1G3D2T
: 1;
3748 unsigned LC1G3D3N
: 1;
3749 unsigned LC1G3D3T
: 1;
3750 unsigned LC1G3D4N
: 1;
3751 unsigned LC1G3D4T
: 1;
3767 extern __at(0x0F16) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
3769 #define _CLC1GLS2_LC1G3D1N 0x01
3770 #define _CLC1GLS2_D1N 0x01
3771 #define _CLC1GLS2_LC1G3D1T 0x02
3772 #define _CLC1GLS2_D1T 0x02
3773 #define _CLC1GLS2_LC1G3D2N 0x04
3774 #define _CLC1GLS2_D2N 0x04
3775 #define _CLC1GLS2_LC1G3D2T 0x08
3776 #define _CLC1GLS2_D2T 0x08
3777 #define _CLC1GLS2_LC1G3D3N 0x10
3778 #define _CLC1GLS2_D3N 0x10
3779 #define _CLC1GLS2_LC1G3D3T 0x20
3780 #define _CLC1GLS2_D3T 0x20
3781 #define _CLC1GLS2_LC1G3D4N 0x40
3782 #define _CLC1GLS2_D4N 0x40
3783 #define _CLC1GLS2_LC1G3D4T 0x80
3784 #define _CLC1GLS2_D4T 0x80
3786 //==============================================================================
3789 //==============================================================================
3792 extern __at(0x0F17) __sfr CLC1GLS3
;
3798 unsigned LC1G4D1N
: 1;
3799 unsigned LC1G4D1T
: 1;
3800 unsigned LC1G4D2N
: 1;
3801 unsigned LC1G4D2T
: 1;
3802 unsigned LC1G4D3N
: 1;
3803 unsigned LC1G4D3T
: 1;
3804 unsigned LC1G4D4N
: 1;
3805 unsigned LC1G4D4T
: 1;
3821 extern __at(0x0F17) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
3823 #define _LC1G4D1N 0x01
3825 #define _LC1G4D1T 0x02
3827 #define _LC1G4D2N 0x04
3829 #define _LC1G4D2T 0x08
3831 #define _LC1G4D3N 0x10
3833 #define _LC1G4D3T 0x20
3835 #define _LC1G4D4N 0x40
3837 #define _LC1G4D4T 0x80
3840 //==============================================================================
3843 //==============================================================================
3846 extern __at(0x0F18) __sfr CLC2CON
;
3852 unsigned LC2MODE0
: 1;
3853 unsigned LC2MODE1
: 1;
3854 unsigned LC2MODE2
: 1;
3855 unsigned LC2INTN
: 1;
3856 unsigned LC2INTP
: 1;
3857 unsigned LC2OUT
: 1;
3864 unsigned LCMODE0
: 1;
3865 unsigned LCMODE1
: 1;
3866 unsigned LCMODE2
: 1;
3867 unsigned LCINTN
: 1;
3868 unsigned LCINTP
: 1;
3876 unsigned LC2MODE
: 3;
3882 unsigned LCMODE
: 3;
3887 extern __at(0x0F18) volatile __CLC2CONbits_t CLC2CONbits
;
3889 #define _CLC2CON_LC2MODE0 0x01
3890 #define _CLC2CON_LCMODE0 0x01
3891 #define _CLC2CON_LC2MODE1 0x02
3892 #define _CLC2CON_LCMODE1 0x02
3893 #define _CLC2CON_LC2MODE2 0x04
3894 #define _CLC2CON_LCMODE2 0x04
3895 #define _CLC2CON_LC2INTN 0x08
3896 #define _CLC2CON_LCINTN 0x08
3897 #define _CLC2CON_LC2INTP 0x10
3898 #define _CLC2CON_LCINTP 0x10
3899 #define _CLC2CON_LC2OUT 0x20
3900 #define _CLC2CON_LCOUT 0x20
3901 #define _CLC2CON_LC2OE 0x40
3902 #define _CLC2CON_LCOE 0x40
3903 #define _CLC2CON_LC2EN 0x80
3904 #define _CLC2CON_LCEN 0x80
3906 //==============================================================================
3909 //==============================================================================
3912 extern __at(0x0F19) __sfr CLC2POL
;
3918 unsigned LC2G1POL
: 1;
3919 unsigned LC2G2POL
: 1;
3920 unsigned LC2G3POL
: 1;
3921 unsigned LC2G4POL
: 1;
3925 unsigned LC2POL
: 1;
3941 extern __at(0x0F19) volatile __CLC2POLbits_t CLC2POLbits
;
3943 #define _CLC2POL_LC2G1POL 0x01
3944 #define _CLC2POL_G1POL 0x01
3945 #define _CLC2POL_LC2G2POL 0x02
3946 #define _CLC2POL_G2POL 0x02
3947 #define _CLC2POL_LC2G3POL 0x04
3948 #define _CLC2POL_G3POL 0x04
3949 #define _CLC2POL_LC2G4POL 0x08
3950 #define _CLC2POL_G4POL 0x08
3951 #define _CLC2POL_LC2POL 0x80
3952 #define _CLC2POL_POL 0x80
3954 //==============================================================================
3957 //==============================================================================
3960 extern __at(0x0F1A) __sfr CLC2SEL0
;
3966 unsigned LC2D1S0
: 1;
3967 unsigned LC2D1S1
: 1;
3968 unsigned LC2D1S2
: 1;
3970 unsigned LC2D2S0
: 1;
3971 unsigned LC2D2S1
: 1;
3972 unsigned LC2D2S2
: 1;
3990 unsigned LC2D1S
: 3;
4010 unsigned LC2D2S
: 3;
4015 extern __at(0x0F1A) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
4017 #define _CLC2SEL0_LC2D1S0 0x01
4018 #define _CLC2SEL0_D1S0 0x01
4019 #define _CLC2SEL0_LC2D1S1 0x02
4020 #define _CLC2SEL0_D1S1 0x02
4021 #define _CLC2SEL0_LC2D1S2 0x04
4022 #define _CLC2SEL0_D1S2 0x04
4023 #define _CLC2SEL0_LC2D2S0 0x10
4024 #define _CLC2SEL0_D2S0 0x10
4025 #define _CLC2SEL0_LC2D2S1 0x20
4026 #define _CLC2SEL0_D2S1 0x20
4027 #define _CLC2SEL0_LC2D2S2 0x40
4028 #define _CLC2SEL0_D2S2 0x40
4030 //==============================================================================
4033 //==============================================================================
4036 extern __at(0x0F1B) __sfr CLC2SEL1
;
4042 unsigned LC2D3S0
: 1;
4043 unsigned LC2D3S1
: 1;
4044 unsigned LC2D3S2
: 1;
4046 unsigned LC2D4S0
: 1;
4047 unsigned LC2D4S1
: 1;
4048 unsigned LC2D4S2
: 1;
4066 unsigned LC2D3S
: 3;
4079 unsigned LC2D4S
: 3;
4091 extern __at(0x0F1B) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
4093 #define _CLC2SEL1_LC2D3S0 0x01
4094 #define _CLC2SEL1_D3S0 0x01
4095 #define _CLC2SEL1_LC2D3S1 0x02
4096 #define _CLC2SEL1_D3S1 0x02
4097 #define _CLC2SEL1_LC2D3S2 0x04
4098 #define _CLC2SEL1_D3S2 0x04
4099 #define _CLC2SEL1_LC2D4S0 0x10
4100 #define _CLC2SEL1_D4S0 0x10
4101 #define _CLC2SEL1_LC2D4S1 0x20
4102 #define _CLC2SEL1_D4S1 0x20
4103 #define _CLC2SEL1_LC2D4S2 0x40
4104 #define _CLC2SEL1_D4S2 0x40
4106 //==============================================================================
4109 //==============================================================================
4112 extern __at(0x0F1C) __sfr CLC2GLS0
;
4118 unsigned LC2G1D1N
: 1;
4119 unsigned LC2G1D1T
: 1;
4120 unsigned LC2G1D2N
: 1;
4121 unsigned LC2G1D2T
: 1;
4122 unsigned LC2G1D3N
: 1;
4123 unsigned LC2G1D3T
: 1;
4124 unsigned LC2G1D4N
: 1;
4125 unsigned LC2G1D4T
: 1;
4141 extern __at(0x0F1C) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
4143 #define _CLC2GLS0_LC2G1D1N 0x01
4144 #define _CLC2GLS0_D1N 0x01
4145 #define _CLC2GLS0_LC2G1D1T 0x02
4146 #define _CLC2GLS0_D1T 0x02
4147 #define _CLC2GLS0_LC2G1D2N 0x04
4148 #define _CLC2GLS0_D2N 0x04
4149 #define _CLC2GLS0_LC2G1D2T 0x08
4150 #define _CLC2GLS0_D2T 0x08
4151 #define _CLC2GLS0_LC2G1D3N 0x10
4152 #define _CLC2GLS0_D3N 0x10
4153 #define _CLC2GLS0_LC2G1D3T 0x20
4154 #define _CLC2GLS0_D3T 0x20
4155 #define _CLC2GLS0_LC2G1D4N 0x40
4156 #define _CLC2GLS0_D4N 0x40
4157 #define _CLC2GLS0_LC2G1D4T 0x80
4158 #define _CLC2GLS0_D4T 0x80
4160 //==============================================================================
4163 //==============================================================================
4166 extern __at(0x0F1D) __sfr CLC2GLS1
;
4172 unsigned LC2G2D1N
: 1;
4173 unsigned LC2G2D1T
: 1;
4174 unsigned LC2G2D2N
: 1;
4175 unsigned LC2G2D2T
: 1;
4176 unsigned LC2G2D3N
: 1;
4177 unsigned LC2G2D3T
: 1;
4178 unsigned LC2G2D4N
: 1;
4179 unsigned LC2G2D4T
: 1;
4195 extern __at(0x0F1D) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
4197 #define _CLC2GLS1_LC2G2D1N 0x01
4198 #define _CLC2GLS1_D1N 0x01
4199 #define _CLC2GLS1_LC2G2D1T 0x02
4200 #define _CLC2GLS1_D1T 0x02
4201 #define _CLC2GLS1_LC2G2D2N 0x04
4202 #define _CLC2GLS1_D2N 0x04
4203 #define _CLC2GLS1_LC2G2D2T 0x08
4204 #define _CLC2GLS1_D2T 0x08
4205 #define _CLC2GLS1_LC2G2D3N 0x10
4206 #define _CLC2GLS1_D3N 0x10
4207 #define _CLC2GLS1_LC2G2D3T 0x20
4208 #define _CLC2GLS1_D3T 0x20
4209 #define _CLC2GLS1_LC2G2D4N 0x40
4210 #define _CLC2GLS1_D4N 0x40
4211 #define _CLC2GLS1_LC2G2D4T 0x80
4212 #define _CLC2GLS1_D4T 0x80
4214 //==============================================================================
4217 //==============================================================================
4220 extern __at(0x0F1E) __sfr CLC2GLS2
;
4226 unsigned LC2G3D1N
: 1;
4227 unsigned LC2G3D1T
: 1;
4228 unsigned LC2G3D2N
: 1;
4229 unsigned LC2G3D2T
: 1;
4230 unsigned LC2G3D3N
: 1;
4231 unsigned LC2G3D3T
: 1;
4232 unsigned LC2G3D4N
: 1;
4233 unsigned LC2G3D4T
: 1;
4249 extern __at(0x0F1E) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
4251 #define _CLC2GLS2_LC2G3D1N 0x01
4252 #define _CLC2GLS2_D1N 0x01
4253 #define _CLC2GLS2_LC2G3D1T 0x02
4254 #define _CLC2GLS2_D1T 0x02
4255 #define _CLC2GLS2_LC2G3D2N 0x04
4256 #define _CLC2GLS2_D2N 0x04
4257 #define _CLC2GLS2_LC2G3D2T 0x08
4258 #define _CLC2GLS2_D2T 0x08
4259 #define _CLC2GLS2_LC2G3D3N 0x10
4260 #define _CLC2GLS2_D3N 0x10
4261 #define _CLC2GLS2_LC2G3D3T 0x20
4262 #define _CLC2GLS2_D3T 0x20
4263 #define _CLC2GLS2_LC2G3D4N 0x40
4264 #define _CLC2GLS2_D4N 0x40
4265 #define _CLC2GLS2_LC2G3D4T 0x80
4266 #define _CLC2GLS2_D4T 0x80
4268 //==============================================================================
4271 //==============================================================================
4274 extern __at(0x0F1F) __sfr CLC2GLS3
;
4280 unsigned LC2G4D1N
: 1;
4281 unsigned LC2G4D1T
: 1;
4282 unsigned LC2G4D2N
: 1;
4283 unsigned LC2G4D2T
: 1;
4284 unsigned LC2G4D3N
: 1;
4285 unsigned LC2G4D3T
: 1;
4286 unsigned LC2G4D4N
: 1;
4287 unsigned LC2G4D4T
: 1;
4303 extern __at(0x0F1F) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
4305 #define _CLC2GLS3_LC2G4D1N 0x01
4306 #define _CLC2GLS3_G4D1N 0x01
4307 #define _CLC2GLS3_LC2G4D1T 0x02
4308 #define _CLC2GLS3_G4D1T 0x02
4309 #define _CLC2GLS3_LC2G4D2N 0x04
4310 #define _CLC2GLS3_G4D2N 0x04
4311 #define _CLC2GLS3_LC2G4D2T 0x08
4312 #define _CLC2GLS3_G4D2T 0x08
4313 #define _CLC2GLS3_LC2G4D3N 0x10
4314 #define _CLC2GLS3_G4D3N 0x10
4315 #define _CLC2GLS3_LC2G4D3T 0x20
4316 #define _CLC2GLS3_G4D3T 0x20
4317 #define _CLC2GLS3_LC2G4D4N 0x40
4318 #define _CLC2GLS3_G4D4N 0x40
4319 #define _CLC2GLS3_LC2G4D4T 0x80
4320 #define _CLC2GLS3_G4D4T 0x80
4322 //==============================================================================
4325 //==============================================================================
4328 extern __at(0x0F20) __sfr CLC3CON
;
4334 unsigned LC3MODE0
: 1;
4335 unsigned LC3MODE1
: 1;
4336 unsigned LC3MODE2
: 1;
4337 unsigned LC3INTN
: 1;
4338 unsigned LC3INTP
: 1;
4339 unsigned LC3OUT
: 1;
4346 unsigned LCMODE0
: 1;
4347 unsigned LCMODE1
: 1;
4348 unsigned LCMODE2
: 1;
4349 unsigned LCINTN
: 1;
4350 unsigned LCINTP
: 1;
4358 unsigned LC3MODE
: 3;
4364 unsigned LCMODE
: 3;
4369 extern __at(0x0F20) volatile __CLC3CONbits_t CLC3CONbits
;
4371 #define _CLC3CON_LC3MODE0 0x01
4372 #define _CLC3CON_LCMODE0 0x01
4373 #define _CLC3CON_LC3MODE1 0x02
4374 #define _CLC3CON_LCMODE1 0x02
4375 #define _CLC3CON_LC3MODE2 0x04
4376 #define _CLC3CON_LCMODE2 0x04
4377 #define _CLC3CON_LC3INTN 0x08
4378 #define _CLC3CON_LCINTN 0x08
4379 #define _CLC3CON_LC3INTP 0x10
4380 #define _CLC3CON_LCINTP 0x10
4381 #define _CLC3CON_LC3OUT 0x20
4382 #define _CLC3CON_LCOUT 0x20
4383 #define _CLC3CON_LC3OE 0x40
4384 #define _CLC3CON_LCOE 0x40
4385 #define _CLC3CON_LC3EN 0x80
4386 #define _CLC3CON_LCEN 0x80
4388 //==============================================================================
4391 //==============================================================================
4394 extern __at(0x0F21) __sfr CLC3POL
;
4400 unsigned LC3G1POL
: 1;
4401 unsigned LC3G2POL
: 1;
4402 unsigned LC3G3POL
: 1;
4403 unsigned LC3G4POL
: 1;
4407 unsigned LC3POL
: 1;
4423 extern __at(0x0F21) volatile __CLC3POLbits_t CLC3POLbits
;
4425 #define _CLC3POL_LC3G1POL 0x01
4426 #define _CLC3POL_G1POL 0x01
4427 #define _CLC3POL_LC3G2POL 0x02
4428 #define _CLC3POL_G2POL 0x02
4429 #define _CLC3POL_LC3G3POL 0x04
4430 #define _CLC3POL_G3POL 0x04
4431 #define _CLC3POL_LC3G4POL 0x08
4432 #define _CLC3POL_G4POL 0x08
4433 #define _CLC3POL_LC3POL 0x80
4434 #define _CLC3POL_POL 0x80
4436 //==============================================================================
4439 //==============================================================================
4442 extern __at(0x0F22) __sfr CLC3SEL0
;
4448 unsigned LC3D1S0
: 1;
4449 unsigned LC3D1S1
: 1;
4450 unsigned LC3D1S2
: 1;
4452 unsigned LC3D2S0
: 1;
4453 unsigned LC3D2S1
: 1;
4454 unsigned LC3D2S2
: 1;
4478 unsigned LC3D1S
: 3;
4492 unsigned LC3D2S
: 3;
4497 extern __at(0x0F22) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
4499 #define _CLC3SEL0_LC3D1S0 0x01
4500 #define _CLC3SEL0_D1S0 0x01
4501 #define _CLC3SEL0_LC3D1S1 0x02
4502 #define _CLC3SEL0_D1S1 0x02
4503 #define _CLC3SEL0_LC3D1S2 0x04
4504 #define _CLC3SEL0_D1S2 0x04
4505 #define _CLC3SEL0_LC3D2S0 0x10
4506 #define _CLC3SEL0_D2S0 0x10
4507 #define _CLC3SEL0_LC3D2S1 0x20
4508 #define _CLC3SEL0_D2S1 0x20
4509 #define _CLC3SEL0_LC3D2S2 0x40
4510 #define _CLC3SEL0_D2S2 0x40
4512 //==============================================================================
4515 //==============================================================================
4518 extern __at(0x0F23) __sfr CLC3SEL1
;
4524 unsigned LC3D3S0
: 1;
4525 unsigned LC3D3S1
: 1;
4526 unsigned LC3D3S2
: 1;
4528 unsigned LC3D4S0
: 1;
4529 unsigned LC3D4S1
: 1;
4530 unsigned LC3D4S2
: 1;
4548 unsigned LC3D3S
: 3;
4568 unsigned LC3D4S
: 3;
4573 extern __at(0x0F23) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
4575 #define _CLC3SEL1_LC3D3S0 0x01
4576 #define _CLC3SEL1_D3S0 0x01
4577 #define _CLC3SEL1_LC3D3S1 0x02
4578 #define _CLC3SEL1_D3S1 0x02
4579 #define _CLC3SEL1_LC3D3S2 0x04
4580 #define _CLC3SEL1_D3S2 0x04
4581 #define _CLC3SEL1_LC3D4S0 0x10
4582 #define _CLC3SEL1_D4S0 0x10
4583 #define _CLC3SEL1_LC3D4S1 0x20
4584 #define _CLC3SEL1_D4S1 0x20
4585 #define _CLC3SEL1_LC3D4S2 0x40
4586 #define _CLC3SEL1_D4S2 0x40
4588 //==============================================================================
4591 //==============================================================================
4594 extern __at(0x0F24) __sfr CLC3GLS0
;
4600 unsigned LC3G1D1N
: 1;
4601 unsigned LC3G1D1T
: 1;
4602 unsigned LC3G1D2N
: 1;
4603 unsigned LC3G1D2T
: 1;
4604 unsigned LC3G1D3N
: 1;
4605 unsigned LC3G1D3T
: 1;
4606 unsigned LC3G1D4N
: 1;
4607 unsigned LC3G1D4T
: 1;
4623 extern __at(0x0F24) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
4625 #define _CLC3GLS0_LC3G1D1N 0x01
4626 #define _CLC3GLS0_D1N 0x01
4627 #define _CLC3GLS0_LC3G1D1T 0x02
4628 #define _CLC3GLS0_D1T 0x02
4629 #define _CLC3GLS0_LC3G1D2N 0x04
4630 #define _CLC3GLS0_D2N 0x04
4631 #define _CLC3GLS0_LC3G1D2T 0x08
4632 #define _CLC3GLS0_D2T 0x08
4633 #define _CLC3GLS0_LC3G1D3N 0x10
4634 #define _CLC3GLS0_D3N 0x10
4635 #define _CLC3GLS0_LC3G1D3T 0x20
4636 #define _CLC3GLS0_D3T 0x20
4637 #define _CLC3GLS0_LC3G1D4N 0x40
4638 #define _CLC3GLS0_D4N 0x40
4639 #define _CLC3GLS0_LC3G1D4T 0x80
4640 #define _CLC3GLS0_D4T 0x80
4642 //==============================================================================
4645 //==============================================================================
4648 extern __at(0x0F25) __sfr CLC3GLS1
;
4654 unsigned LC3G2D1N
: 1;
4655 unsigned LC3G2D1T
: 1;
4656 unsigned LC3G2D2N
: 1;
4657 unsigned LC3G2D2T
: 1;
4658 unsigned LC3G2D3N
: 1;
4659 unsigned LC3G2D3T
: 1;
4660 unsigned LC3G2D4N
: 1;
4661 unsigned LC3G2D4T
: 1;
4677 extern __at(0x0F25) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
4679 #define _CLC3GLS1_LC3G2D1N 0x01
4680 #define _CLC3GLS1_D1N 0x01
4681 #define _CLC3GLS1_LC3G2D1T 0x02
4682 #define _CLC3GLS1_D1T 0x02
4683 #define _CLC3GLS1_LC3G2D2N 0x04
4684 #define _CLC3GLS1_D2N 0x04
4685 #define _CLC3GLS1_LC3G2D2T 0x08
4686 #define _CLC3GLS1_D2T 0x08
4687 #define _CLC3GLS1_LC3G2D3N 0x10
4688 #define _CLC3GLS1_D3N 0x10
4689 #define _CLC3GLS1_LC3G2D3T 0x20
4690 #define _CLC3GLS1_D3T 0x20
4691 #define _CLC3GLS1_LC3G2D4N 0x40
4692 #define _CLC3GLS1_D4N 0x40
4693 #define _CLC3GLS1_LC3G2D4T 0x80
4694 #define _CLC3GLS1_D4T 0x80
4696 //==============================================================================
4699 //==============================================================================
4702 extern __at(0x0F26) __sfr CLC3GLS2
;
4708 unsigned LC3G3D1N
: 1;
4709 unsigned LC3G3D1T
: 1;
4710 unsigned LC3G3D2N
: 1;
4711 unsigned LC3G3D2T
: 1;
4712 unsigned LC3G3D3N
: 1;
4713 unsigned LC3G3D3T
: 1;
4714 unsigned LC3G3D4N
: 1;
4715 unsigned LC3G3D4T
: 1;
4731 extern __at(0x0F26) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
4733 #define _CLC3GLS2_LC3G3D1N 0x01
4734 #define _CLC3GLS2_D1N 0x01
4735 #define _CLC3GLS2_LC3G3D1T 0x02
4736 #define _CLC3GLS2_D1T 0x02
4737 #define _CLC3GLS2_LC3G3D2N 0x04
4738 #define _CLC3GLS2_D2N 0x04
4739 #define _CLC3GLS2_LC3G3D2T 0x08
4740 #define _CLC3GLS2_D2T 0x08
4741 #define _CLC3GLS2_LC3G3D3N 0x10
4742 #define _CLC3GLS2_D3N 0x10
4743 #define _CLC3GLS2_LC3G3D3T 0x20
4744 #define _CLC3GLS2_D3T 0x20
4745 #define _CLC3GLS2_LC3G3D4N 0x40
4746 #define _CLC3GLS2_D4N 0x40
4747 #define _CLC3GLS2_LC3G3D4T 0x80
4748 #define _CLC3GLS2_D4T 0x80
4750 //==============================================================================
4753 //==============================================================================
4756 extern __at(0x0F27) __sfr CLC3GLS3
;
4762 unsigned LC3G4D1N
: 1;
4763 unsigned LC3G4D1T
: 1;
4764 unsigned LC3G4D2N
: 1;
4765 unsigned LC3G4D2T
: 1;
4766 unsigned LC3G4D3N
: 1;
4767 unsigned LC3G4D3T
: 1;
4768 unsigned LC3G4D4N
: 1;
4769 unsigned LC3G4D4T
: 1;
4785 extern __at(0x0F27) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
4787 #define _CLC3GLS3_LC3G4D1N 0x01
4788 #define _CLC3GLS3_G4D1N 0x01
4789 #define _CLC3GLS3_LC3G4D1T 0x02
4790 #define _CLC3GLS3_G4D1T 0x02
4791 #define _CLC3GLS3_LC3G4D2N 0x04
4792 #define _CLC3GLS3_G4D2N 0x04
4793 #define _CLC3GLS3_LC3G4D2T 0x08
4794 #define _CLC3GLS3_G4D2T 0x08
4795 #define _CLC3GLS3_LC3G4D3N 0x10
4796 #define _CLC3GLS3_G4D3N 0x10
4797 #define _CLC3GLS3_LC3G4D3T 0x20
4798 #define _CLC3GLS3_G4D3T 0x20
4799 #define _CLC3GLS3_LC3G4D4N 0x40
4800 #define _CLC3GLS3_G4D4N 0x40
4801 #define _CLC3GLS3_LC3G4D4T 0x80
4802 #define _CLC3GLS3_G4D4T 0x80
4804 //==============================================================================
4807 //==============================================================================
4810 extern __at(0x0F28) __sfr CLC4CON
;
4816 unsigned LC4MODE0
: 1;
4817 unsigned LC4MODE1
: 1;
4818 unsigned LC4MODE2
: 1;
4819 unsigned LC4INTN
: 1;
4820 unsigned LC4INTP
: 1;
4821 unsigned LC4OUT
: 1;
4828 unsigned LCMODE0
: 1;
4829 unsigned LCMODE1
: 1;
4830 unsigned LCMODE2
: 1;
4831 unsigned LCINTN
: 1;
4832 unsigned LCINTP
: 1;
4840 unsigned LCMODE
: 3;
4846 unsigned LC4MODE
: 3;
4851 extern __at(0x0F28) volatile __CLC4CONbits_t CLC4CONbits
;
4853 #define _CLC4CON_LC4MODE0 0x01
4854 #define _CLC4CON_LCMODE0 0x01
4855 #define _CLC4CON_LC4MODE1 0x02
4856 #define _CLC4CON_LCMODE1 0x02
4857 #define _CLC4CON_LC4MODE2 0x04
4858 #define _CLC4CON_LCMODE2 0x04
4859 #define _CLC4CON_LC4INTN 0x08
4860 #define _CLC4CON_LCINTN 0x08
4861 #define _CLC4CON_LC4INTP 0x10
4862 #define _CLC4CON_LCINTP 0x10
4863 #define _CLC4CON_LC4OUT 0x20
4864 #define _CLC4CON_LCOUT 0x20
4865 #define _CLC4CON_LC4OE 0x40
4866 #define _CLC4CON_LCOE 0x40
4867 #define _CLC4CON_LC4EN 0x80
4868 #define _CLC4CON_LCEN 0x80
4870 //==============================================================================
4873 //==============================================================================
4876 extern __at(0x0F29) __sfr CLC4POL
;
4882 unsigned LC4G1POL
: 1;
4883 unsigned LC4G2POL
: 1;
4884 unsigned LC4G3POL
: 1;
4885 unsigned LC4G4POL
: 1;
4889 unsigned LC4POL
: 1;
4905 extern __at(0x0F29) volatile __CLC4POLbits_t CLC4POLbits
;
4907 #define _CLC4POL_LC4G1POL 0x01
4908 #define _CLC4POL_G1POL 0x01
4909 #define _CLC4POL_LC4G2POL 0x02
4910 #define _CLC4POL_G2POL 0x02
4911 #define _CLC4POL_LC4G3POL 0x04
4912 #define _CLC4POL_G3POL 0x04
4913 #define _CLC4POL_LC4G4POL 0x08
4914 #define _CLC4POL_G4POL 0x08
4915 #define _CLC4POL_LC4POL 0x80
4916 #define _CLC4POL_POL 0x80
4918 //==============================================================================
4921 //==============================================================================
4924 extern __at(0x0F2A) __sfr CLC4SEL0
;
4930 unsigned LC4D1S0
: 1;
4931 unsigned LC4D1S1
: 1;
4932 unsigned LC4D1S2
: 1;
4934 unsigned LC4D2S0
: 1;
4935 unsigned LC4D2S1
: 1;
4936 unsigned LC4D2S2
: 1;
4954 unsigned LC4D1S
: 3;
4967 unsigned LC4D2S
: 3;
4979 extern __at(0x0F2A) volatile __CLC4SEL0bits_t CLC4SEL0bits
;
4981 #define _CLC4SEL0_LC4D1S0 0x01
4982 #define _CLC4SEL0_D1S0 0x01
4983 #define _CLC4SEL0_LC4D1S1 0x02
4984 #define _CLC4SEL0_D1S1 0x02
4985 #define _CLC4SEL0_LC4D1S2 0x04
4986 #define _CLC4SEL0_D1S2 0x04
4987 #define _CLC4SEL0_LC4D2S0 0x10
4988 #define _CLC4SEL0_D2S0 0x10
4989 #define _CLC4SEL0_LC4D2S1 0x20
4990 #define _CLC4SEL0_D2S1 0x20
4991 #define _CLC4SEL0_LC4D2S2 0x40
4992 #define _CLC4SEL0_D2S2 0x40
4994 //==============================================================================
4997 //==============================================================================
5000 extern __at(0x0F2B) __sfr CLC4SEL1
;
5006 unsigned LC4D3S0
: 1;
5007 unsigned LC4D3S1
: 1;
5008 unsigned LC4D3S2
: 1;
5010 unsigned LC4D4S0
: 1;
5011 unsigned LC4D4S1
: 1;
5012 unsigned LC4D4S2
: 1;
5030 unsigned LC4D3S
: 3;
5050 unsigned LC4D4S
: 3;
5055 extern __at(0x0F2B) volatile __CLC4SEL1bits_t CLC4SEL1bits
;
5057 #define _CLC4SEL1_LC4D3S0 0x01
5058 #define _CLC4SEL1_D3S0 0x01
5059 #define _CLC4SEL1_LC4D3S1 0x02
5060 #define _CLC4SEL1_D3S1 0x02
5061 #define _CLC4SEL1_LC4D3S2 0x04
5062 #define _CLC4SEL1_D3S2 0x04
5063 #define _CLC4SEL1_LC4D4S0 0x10
5064 #define _CLC4SEL1_D4S0 0x10
5065 #define _CLC4SEL1_LC4D4S1 0x20
5066 #define _CLC4SEL1_D4S1 0x20
5067 #define _CLC4SEL1_LC4D4S2 0x40
5068 #define _CLC4SEL1_D4S2 0x40
5070 //==============================================================================
5073 //==============================================================================
5076 extern __at(0x0F2C) __sfr CLC4GLS0
;
5082 unsigned LC4G1D1N
: 1;
5083 unsigned LC4G1D1T
: 1;
5084 unsigned LC4G1D2N
: 1;
5085 unsigned LC4G1D2T
: 1;
5086 unsigned LC4G1D3N
: 1;
5087 unsigned LC4G1D3T
: 1;
5088 unsigned LC4G1D4N
: 1;
5089 unsigned LC4G1D4T
: 1;
5105 extern __at(0x0F2C) volatile __CLC4GLS0bits_t CLC4GLS0bits
;
5107 #define _CLC4GLS0_LC4G1D1N 0x01
5108 #define _CLC4GLS0_D1N 0x01
5109 #define _CLC4GLS0_LC4G1D1T 0x02
5110 #define _CLC4GLS0_D1T 0x02
5111 #define _CLC4GLS0_LC4G1D2N 0x04
5112 #define _CLC4GLS0_D2N 0x04
5113 #define _CLC4GLS0_LC4G1D2T 0x08
5114 #define _CLC4GLS0_D2T 0x08
5115 #define _CLC4GLS0_LC4G1D3N 0x10
5116 #define _CLC4GLS0_D3N 0x10
5117 #define _CLC4GLS0_LC4G1D3T 0x20
5118 #define _CLC4GLS0_D3T 0x20
5119 #define _CLC4GLS0_LC4G1D4N 0x40
5120 #define _CLC4GLS0_D4N 0x40
5121 #define _CLC4GLS0_LC4G1D4T 0x80
5122 #define _CLC4GLS0_D4T 0x80
5124 //==============================================================================
5127 //==============================================================================
5130 extern __at(0x0F2D) __sfr CLC4GLS1
;
5136 unsigned LC4G2D1N
: 1;
5137 unsigned LC4G2D1T
: 1;
5138 unsigned LC4G2D2N
: 1;
5139 unsigned LC4G2D2T
: 1;
5140 unsigned LC4G2D3N
: 1;
5141 unsigned LC4G2D3T
: 1;
5142 unsigned LC4G2D4N
: 1;
5143 unsigned LC4G2D4T
: 1;
5159 extern __at(0x0F2D) volatile __CLC4GLS1bits_t CLC4GLS1bits
;
5161 #define _CLC4GLS1_LC4G2D1N 0x01
5162 #define _CLC4GLS1_D1N 0x01
5163 #define _CLC4GLS1_LC4G2D1T 0x02
5164 #define _CLC4GLS1_D1T 0x02
5165 #define _CLC4GLS1_LC4G2D2N 0x04
5166 #define _CLC4GLS1_D2N 0x04
5167 #define _CLC4GLS1_LC4G2D2T 0x08
5168 #define _CLC4GLS1_D2T 0x08
5169 #define _CLC4GLS1_LC4G2D3N 0x10
5170 #define _CLC4GLS1_D3N 0x10
5171 #define _CLC4GLS1_LC4G2D3T 0x20
5172 #define _CLC4GLS1_D3T 0x20
5173 #define _CLC4GLS1_LC4G2D4N 0x40
5174 #define _CLC4GLS1_D4N 0x40
5175 #define _CLC4GLS1_LC4G2D4T 0x80
5176 #define _CLC4GLS1_D4T 0x80
5178 //==============================================================================
5181 //==============================================================================
5184 extern __at(0x0F2E) __sfr CLC4GLS2
;
5190 unsigned LC4G3D1N
: 1;
5191 unsigned LC4G3D1T
: 1;
5192 unsigned LC4G3D2N
: 1;
5193 unsigned LC4G3D2T
: 1;
5194 unsigned LC4G3D3N
: 1;
5195 unsigned LC4G3D3T
: 1;
5196 unsigned LC4G3D4N
: 1;
5197 unsigned LC4G3D4T
: 1;
5213 extern __at(0x0F2E) volatile __CLC4GLS2bits_t CLC4GLS2bits
;
5215 #define _CLC4GLS2_LC4G3D1N 0x01
5216 #define _CLC4GLS2_D1N 0x01
5217 #define _CLC4GLS2_LC4G3D1T 0x02
5218 #define _CLC4GLS2_D1T 0x02
5219 #define _CLC4GLS2_LC4G3D2N 0x04
5220 #define _CLC4GLS2_D2N 0x04
5221 #define _CLC4GLS2_LC4G3D2T 0x08
5222 #define _CLC4GLS2_D2T 0x08
5223 #define _CLC4GLS2_LC4G3D3N 0x10
5224 #define _CLC4GLS2_D3N 0x10
5225 #define _CLC4GLS2_LC4G3D3T 0x20
5226 #define _CLC4GLS2_D3T 0x20
5227 #define _CLC4GLS2_LC4G3D4N 0x40
5228 #define _CLC4GLS2_D4N 0x40
5229 #define _CLC4GLS2_LC4G3D4T 0x80
5230 #define _CLC4GLS2_D4T 0x80
5232 //==============================================================================
5235 //==============================================================================
5238 extern __at(0x0F2F) __sfr CLC4GLS3
;
5244 unsigned LC4G4D1N
: 1;
5245 unsigned LC4G4D1T
: 1;
5246 unsigned LC4G4D2N
: 1;
5247 unsigned LC4G4D2T
: 1;
5248 unsigned LC4G4D3N
: 1;
5249 unsigned LC4G4D3T
: 1;
5250 unsigned LC4G4D4N
: 1;
5251 unsigned LC4G4D4T
: 1;
5267 extern __at(0x0F2F) volatile __CLC4GLS3bits_t CLC4GLS3bits
;
5269 #define _CLC4GLS3_LC4G4D1N 0x01
5270 #define _CLC4GLS3_G4D1N 0x01
5271 #define _CLC4GLS3_LC4G4D1T 0x02
5272 #define _CLC4GLS3_G4D1T 0x02
5273 #define _CLC4GLS3_LC4G4D2N 0x04
5274 #define _CLC4GLS3_G4D2N 0x04
5275 #define _CLC4GLS3_LC4G4D2T 0x08
5276 #define _CLC4GLS3_G4D2T 0x08
5277 #define _CLC4GLS3_LC4G4D3N 0x10
5278 #define _CLC4GLS3_G4D3N 0x10
5279 #define _CLC4GLS3_LC4G4D3T 0x20
5280 #define _CLC4GLS3_G4D3T 0x20
5281 #define _CLC4GLS3_LC4G4D4N 0x40
5282 #define _CLC4GLS3_G4D4N 0x40
5283 #define _CLC4GLS3_LC4G4D4T 0x80
5284 #define _CLC4GLS3_G4D4T 0x80
5286 //==============================================================================
5289 //==============================================================================
5292 extern __at(0x0F8C) __sfr ICDIO
;
5298 unsigned TRIS_ICDCLK
: 1;
5299 unsigned TRIS_ICDDAT
: 1;
5300 unsigned LAT_ICDCLK
: 1;
5301 unsigned LAT_ICDDAT
: 1;
5302 unsigned PORT_ICDCLK
: 1;
5303 unsigned PORT_ICDDAT
: 1;
5306 extern __at(0x0F8C) volatile __ICDIObits_t ICDIObits
;
5308 #define _TRIS_ICDCLK 0x04
5309 #define _TRIS_ICDDAT 0x08
5310 #define _LAT_ICDCLK 0x10
5311 #define _LAT_ICDDAT 0x20
5312 #define _PORT_ICDCLK 0x40
5313 #define _PORT_ICDDAT 0x80
5315 //==============================================================================
5318 //==============================================================================
5321 extern __at(0x0F8D) __sfr ICDCON0
;
5325 unsigned RSTVEC
: 1;
5328 unsigned DBGINEX
: 1;
5335 extern __at(0x0F8D) volatile __ICDCON0bits_t ICDCON0bits
;
5337 #define _RSTVEC 0x01
5338 #define _DBGINEX 0x08
5343 //==============================================================================
5346 //==============================================================================
5349 extern __at(0x0F91) __sfr ICDSTAT
;
5354 unsigned USRHLTF
: 1;
5359 unsigned TRP0HLTF
: 1;
5360 unsigned TRP1HLTF
: 1;
5363 extern __at(0x0F91) volatile __ICDSTATbits_t ICDSTATbits
;
5365 #define _USRHLTF 0x02
5366 #define _TRP0HLTF 0x40
5367 #define _TRP1HLTF 0x80
5369 //==============================================================================
5372 //==============================================================================
5375 extern __at(0x0F95) __sfr DEVSEL
;
5381 unsigned DEVSEL0
: 1;
5382 unsigned DEVSEL1
: 1;
5383 unsigned DEVSEL2
: 1;
5393 unsigned DEVSEL
: 3;
5398 extern __at(0x0F95) volatile __DEVSELbits_t DEVSELbits
;
5400 #define _DEVSEL0 0x01
5401 #define _DEVSEL1 0x02
5402 #define _DEVSEL2 0x04
5404 //==============================================================================
5407 //==============================================================================
5410 extern __at(0x0F96) __sfr ICDINSTL
;
5414 unsigned DBGIN0
: 1;
5415 unsigned DBGIN1
: 1;
5416 unsigned DBGIN2
: 1;
5417 unsigned DBGIN3
: 1;
5418 unsigned DBGIN4
: 1;
5419 unsigned DBGIN5
: 1;
5420 unsigned DBGIN6
: 1;
5421 unsigned DBGIN7
: 1;
5424 extern __at(0x0F96) volatile __ICDINSTLbits_t ICDINSTLbits
;
5426 #define _DBGIN0 0x01
5427 #define _DBGIN1 0x02
5428 #define _DBGIN2 0x04
5429 #define _DBGIN3 0x08
5430 #define _DBGIN4 0x10
5431 #define _DBGIN5 0x20
5432 #define _DBGIN6 0x40
5433 #define _DBGIN7 0x80
5435 //==============================================================================
5438 //==============================================================================
5441 extern __at(0x0F97) __sfr ICDINSTH
;
5445 unsigned DBGIN8
: 1;
5446 unsigned DBGIN9
: 1;
5447 unsigned DBGIN10
: 1;
5448 unsigned DBGIN11
: 1;
5449 unsigned DBGIN12
: 1;
5450 unsigned DBGIN13
: 1;
5455 extern __at(0x0F97) volatile __ICDINSTHbits_t ICDINSTHbits
;
5457 #define _DBGIN8 0x01
5458 #define _DBGIN9 0x02
5459 #define _DBGIN10 0x04
5460 #define _DBGIN11 0x08
5461 #define _DBGIN12 0x10
5462 #define _DBGIN13 0x20
5464 //==============================================================================
5467 //==============================================================================
5470 extern __at(0x0F9C) __sfr ICDBK0CON
;
5482 } __ICDBK0CONbits_t
;
5484 extern __at(0x0F9C) volatile __ICDBK0CONbits_t ICDBK0CONbits
;
5489 //==============================================================================
5492 //==============================================================================
5495 extern __at(0x0F9D) __sfr ICDBK0L
;
5509 extern __at(0x0F9D) volatile __ICDBK0Lbits_t ICDBK0Lbits
;
5520 //==============================================================================
5523 //==============================================================================
5526 extern __at(0x0F9E) __sfr ICDBK0H
;
5540 extern __at(0x0F9E) volatile __ICDBK0Hbits_t ICDBK0Hbits
;
5550 //==============================================================================
5552 extern __at(0x0FE3) __sfr BSRICDSHAD
;
5554 //==============================================================================
5557 extern __at(0x0FE4) __sfr STATUS_SHAD
;
5561 unsigned C_SHAD
: 1;
5562 unsigned DC_SHAD
: 1;
5563 unsigned Z_SHAD
: 1;
5569 } __STATUS_SHADbits_t
;
5571 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
5573 #define _C_SHAD 0x01
5574 #define _DC_SHAD 0x02
5575 #define _Z_SHAD 0x04
5577 //==============================================================================
5579 extern __at(0x0FE5) __sfr WREG_SHAD
;
5580 extern __at(0x0FE6) __sfr BSR_SHAD
;
5581 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
5582 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
5583 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
5584 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
5585 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
5586 extern __at(0x0FED) __sfr STKPTR
;
5587 extern __at(0x0FEE) __sfr TOSL
;
5588 extern __at(0x0FEF) __sfr TOSH
;
5590 //==============================================================================
5592 // Configuration Bits
5594 //==============================================================================
5596 #define _CONFIG1 0x8007
5597 #define _CONFIG2 0x8008
5599 //----------------------------- CONFIG1 Options -------------------------------
5601 #define _FOSC_LP 0x3FF8 // LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins.
5602 #define _FOSC_XT 0x3FF9 // XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins.
5603 #define _FOSC_HS 0x3FFA // HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins.
5604 #define _FOSC_EXTRC 0x3FFB // EXTRC oscillator: External RC circuit connected to CLKIN pin.
5605 #define _FOSC_INTOSC 0x3FFC // INTOSC oscillator: I/O function on CLKIN pin.
5606 #define _FOSC_ECL 0x3FFD // ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pins.
5607 #define _FOSC_ECM 0x3FFE // ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pins.
5608 #define _FOSC_ECH 0x3FFF // ECH, External Clock, High Power Mode (4-20 MHz): device clock supplied to CLKIN pins.
5609 #define _WDTE_OFF 0x3FE7 // WDT disabled.
5610 #define _WDTE_SWDTEN 0x3FEF // WDT controlled by the SWDTEN bit in the WDTCON register.
5611 #define _WDTE_NSLEEP 0x3FF7 // WDT enabled while running and disabled in Sleep.
5612 #define _WDTE_ON 0x3FFF // WDT enabled.
5613 #define _PWRTE_ON 0x3FDF // PWRT enabled.
5614 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
5615 #define _MCLRE_OFF 0x3FBF // MCLR/VPP pin function is digital input.
5616 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR.
5617 #define _CP_ON 0x3F7F // Program memory code protection is enabled.
5618 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
5619 #define _BOREN_OFF 0x39FF // Brown-out Reset disabled.
5620 #define _BOREN_SBODEN 0x3BFF // Brown-out Reset controlled by the SBOREN bit in the BORCON register.
5621 #define _BOREN_NSLEEP 0x3DFF // Brown-out Reset enabled while running and disabled in Sleep.
5622 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled.
5623 #define _CLKOUTEN_ON 0x37FF // CLKOUT function is enabled on the CLKOUT pin.
5624 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
5625 #define _IESO_OFF 0x2FFF // Internal/External Switchover Mode is disabled.
5626 #define _IESO_ON 0x3FFF // Internal/External Switchover Mode is enabled.
5627 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
5628 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
5630 //----------------------------- CONFIG2 Options -------------------------------
5632 #define _WRT_ALL 0x3FFC // 000h to 1FFFh write protected, no addresses may be modified by EECON control.
5633 #define _WRT_HALF 0x3FFD // 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control.
5634 #define _WRT_BOOT 0x3FFE // 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control.
5635 #define _WRT_OFF 0x3FFF // Write protection off.
5636 #define _STVREN_OFF 0x3DFF // Stack Overflow or Underflow will not cause a Reset.
5637 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
5638 #define _BORV_HI 0x3BFF // Brown-out Reset Voltage (Vbor), high trip point selected.
5639 #define _BORV_LO 0x3FFF // Brown-out Reset Voltage (Vbor), low trip point selected.
5640 #define _LPBOR_ON 0x37FF // Low-Power BOR is enabled.
5641 #define _LPBOR_OFF 0x3FFF // Low-Power BOR is disabled.
5642 #define _DEBUG_ON 0x2FFF // In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger.
5643 #define _DEBUG_OFF 0x3FFF // In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins.
5644 #define _LVP_OFF 0x1FFF // High-voltage on MCLR/VPP must be used for programming.
5645 #define _LVP_ON 0x3FFF // Low-voltage programming enabled.
5647 //==============================================================================
5649 #define _DEVID1 0x8006
5651 #define _IDLOC0 0x8000
5652 #define _IDLOC1 0x8001
5653 #define _IDLOC2 0x8002
5654 #define _IDLOC3 0x8003
5656 //==============================================================================
5658 #ifndef NO_BIT_DEFINES
5660 #define ADON ADCON0bits.ADON // bit 0
5661 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
5662 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
5663 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
5664 #define CHS0 ADCON0bits.CHS0 // bit 2
5665 #define CHS1 ADCON0bits.CHS1 // bit 3
5666 #define CHS2 ADCON0bits.CHS2 // bit 4
5667 #define CHS3 ADCON0bits.CHS3 // bit 5
5668 #define CHS4 ADCON0bits.CHS4 // bit 6
5670 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
5671 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
5672 #define ADFM ADCON1bits.ADFM // bit 7
5674 #define TRIGSEL0 ADCON2bits.TRIGSEL0 // bit 4
5675 #define TRIGSEL1 ADCON2bits.TRIGSEL1 // bit 5
5676 #define TRIGSEL2 ADCON2bits.TRIGSEL2 // bit 6
5677 #define TRIGSEL3 ADCON2bits.TRIGSEL3 // bit 7
5679 #define ANSA0 ANSELAbits.ANSA0 // bit 0
5680 #define ANSA1 ANSELAbits.ANSA1 // bit 1
5681 #define ANSA2 ANSELAbits.ANSA2 // bit 2
5682 #define ANSA4 ANSELAbits.ANSA4 // bit 4
5684 #define ANSB4 ANSELBbits.ANSB4 // bit 4
5685 #define ANSB5 ANSELBbits.ANSB5 // bit 5
5687 #define ANSC0 ANSELCbits.ANSC0 // bit 0
5688 #define ANSC1 ANSELCbits.ANSC1 // bit 1
5689 #define ANSC2 ANSELCbits.ANSC2 // bit 2
5690 #define ANSC3 ANSELCbits.ANSC3 // bit 3
5691 #define ANSC6 ANSELCbits.ANSC6 // bit 6
5692 #define ANSC7 ANSELCbits.ANSC7 // bit 7
5694 #define NCO1SEL APFCONbits.NCO1SEL // bit 0, shadows bit in APFCONbits
5695 #define NCOSEL APFCONbits.NCOSEL // bit 0, shadows bit in APFCONbits
5696 #define CLC1SEL APFCONbits.CLC1SEL // bit 1
5697 #define T1GSEL APFCONbits.T1GSEL // bit 3
5698 #define SSSEL APFCONbits.SSSEL // bit 4
5700 #define ABDEN BAUDCONbits.ABDEN // bit 0
5701 #define WUE BAUDCONbits.WUE // bit 1
5702 #define BRG16 BAUDCONbits.BRG16 // bit 3
5703 #define SCKP BAUDCONbits.SCKP // bit 4
5704 #define RCIDL BAUDCONbits.RCIDL // bit 6
5705 #define ABDOVF BAUDCONbits.ABDOVF // bit 7
5707 #define BORRDY BORCONbits.BORRDY // bit 0
5708 #define BORFS BORCONbits.BORFS // bit 6
5709 #define SBOREN BORCONbits.SBOREN // bit 7
5711 #define BSR0 BSRbits.BSR0 // bit 0
5712 #define BSR1 BSRbits.BSR1 // bit 1
5713 #define BSR2 BSRbits.BSR2 // bit 2
5714 #define BSR3 BSRbits.BSR3 // bit 3
5715 #define BSR4 BSRbits.BSR4 // bit 4
5717 #define LC1MODE0 CLC1CONbits.LC1MODE0 // bit 0, shadows bit in CLC1CONbits
5718 #define LCMODE0 CLC1CONbits.LCMODE0 // bit 0, shadows bit in CLC1CONbits
5719 #define LC1MODE1 CLC1CONbits.LC1MODE1 // bit 1, shadows bit in CLC1CONbits
5720 #define LCMODE1 CLC1CONbits.LCMODE1 // bit 1, shadows bit in CLC1CONbits
5721 #define LC1MODE2 CLC1CONbits.LC1MODE2 // bit 2, shadows bit in CLC1CONbits
5722 #define LCMODE2 CLC1CONbits.LCMODE2 // bit 2, shadows bit in CLC1CONbits
5723 #define LC1INTN CLC1CONbits.LC1INTN // bit 3, shadows bit in CLC1CONbits
5724 #define LCINTN CLC1CONbits.LCINTN // bit 3, shadows bit in CLC1CONbits
5725 #define LC1INTP CLC1CONbits.LC1INTP // bit 4, shadows bit in CLC1CONbits
5726 #define LCINTP CLC1CONbits.LCINTP // bit 4, shadows bit in CLC1CONbits
5727 #define LC1OUT CLC1CONbits.LC1OUT // bit 5, shadows bit in CLC1CONbits
5728 #define LCOUT CLC1CONbits.LCOUT // bit 5, shadows bit in CLC1CONbits
5729 #define LC1OE CLC1CONbits.LC1OE // bit 6, shadows bit in CLC1CONbits
5730 #define LCOE CLC1CONbits.LCOE // bit 6, shadows bit in CLC1CONbits
5731 #define LC1EN CLC1CONbits.LC1EN // bit 7, shadows bit in CLC1CONbits
5732 #define LCEN CLC1CONbits.LCEN // bit 7, shadows bit in CLC1CONbits
5734 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
5735 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
5736 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
5737 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
5738 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
5739 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
5740 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
5741 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
5742 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
5743 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
5744 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
5745 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
5746 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
5747 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
5748 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
5749 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
5751 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
5752 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
5753 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
5754 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
5755 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
5756 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
5757 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
5758 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
5759 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
5760 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
5761 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
5762 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
5763 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
5764 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
5765 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
5766 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
5768 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
5769 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
5770 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
5771 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
5772 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
5773 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
5774 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
5775 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
5776 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
5777 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
5779 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
5780 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
5781 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
5782 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
5783 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
5784 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
5785 #define LC1D2S0 CLC1SEL0bits.LC1D2S0 // bit 4, shadows bit in CLC1SEL0bits
5786 #define D2S0 CLC1SEL0bits.D2S0 // bit 4, shadows bit in CLC1SEL0bits
5787 #define LC1D2S1 CLC1SEL0bits.LC1D2S1 // bit 5, shadows bit in CLC1SEL0bits
5788 #define D2S1 CLC1SEL0bits.D2S1 // bit 5, shadows bit in CLC1SEL0bits
5789 #define LC1D2S2 CLC1SEL0bits.LC1D2S2 // bit 6, shadows bit in CLC1SEL0bits
5790 #define D2S2 CLC1SEL0bits.D2S2 // bit 6, shadows bit in CLC1SEL0bits
5792 #define LC1D3S0 CLC1SEL1bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL1bits
5793 #define D3S0 CLC1SEL1bits.D3S0 // bit 0, shadows bit in CLC1SEL1bits
5794 #define LC1D3S1 CLC1SEL1bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL1bits
5795 #define D3S1 CLC1SEL1bits.D3S1 // bit 1, shadows bit in CLC1SEL1bits
5796 #define LC1D3S2 CLC1SEL1bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL1bits
5797 #define D3S2 CLC1SEL1bits.D3S2 // bit 2, shadows bit in CLC1SEL1bits
5798 #define LC1D4S0 CLC1SEL1bits.LC1D4S0 // bit 4, shadows bit in CLC1SEL1bits
5799 #define D4S0 CLC1SEL1bits.D4S0 // bit 4, shadows bit in CLC1SEL1bits
5800 #define LC1D4S1 CLC1SEL1bits.LC1D4S1 // bit 5, shadows bit in CLC1SEL1bits
5801 #define D4S1 CLC1SEL1bits.D4S1 // bit 5, shadows bit in CLC1SEL1bits
5802 #define LC1D4S2 CLC1SEL1bits.LC1D4S2 // bit 6, shadows bit in CLC1SEL1bits
5803 #define D4S2 CLC1SEL1bits.D4S2 // bit 6, shadows bit in CLC1SEL1bits
5805 #define MCLC1OUT CLCDATAbits.MCLC1OUT // bit 0
5806 #define MCLC2OUT CLCDATAbits.MCLC2OUT // bit 1
5807 #define MCLC3OUT CLCDATAbits.MCLC3OUT // bit 2
5808 #define MCLC4OUT CLCDATAbits.MCLC4OUT // bit 3
5810 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
5811 #define C1HYS CM1CON0bits.C1HYS // bit 1
5812 #define C1SP CM1CON0bits.C1SP // bit 2
5813 #define C1POL CM1CON0bits.C1POL // bit 4
5814 #define C1OE CM1CON0bits.C1OE // bit 5
5815 #define C1OUT CM1CON0bits.C1OUT // bit 6
5816 #define C1ON CM1CON0bits.C1ON // bit 7
5818 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
5819 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
5820 #define C1NCH2 CM1CON1bits.C1NCH2 // bit 2
5821 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 4
5822 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 5
5823 #define C1INTN CM1CON1bits.C1INTN // bit 6
5824 #define C1INTP CM1CON1bits.C1INTP // bit 7
5826 #define C2SYNC CM2CON0bits.C2SYNC // bit 0
5827 #define C2HYS CM2CON0bits.C2HYS // bit 1
5828 #define C2SP CM2CON0bits.C2SP // bit 2
5829 #define C2POL CM2CON0bits.C2POL // bit 4
5830 #define C2OE CM2CON0bits.C2OE // bit 5
5831 #define C2OUT CM2CON0bits.C2OUT // bit 6
5832 #define C2ON CM2CON0bits.C2ON // bit 7
5834 #define C2NCH0 CM2CON1bits.C2NCH0 // bit 0
5835 #define C2NCH1 CM2CON1bits.C2NCH1 // bit 1
5836 #define C2NCH2 CM2CON1bits.C2NCH2 // bit 2
5837 #define C2PCH0 CM2CON1bits.C2PCH0 // bit 4
5838 #define C2PCH1 CM2CON1bits.C2PCH1 // bit 5
5839 #define C2INTN CM2CON1bits.C2INTN // bit 6
5840 #define C2INTP CM2CON1bits.C2INTP // bit 7
5842 #define MC1OUT CMOUTbits.MC1OUT // bit 0
5843 #define MC2OUT CMOUTbits.MC2OUT // bit 1
5845 #define G1CS0 CWG1CON0bits.G1CS0 // bit 0
5846 #define G1POLA CWG1CON0bits.G1POLA // bit 3
5847 #define G1POLB CWG1CON0bits.G1POLB // bit 4
5848 #define G1OEA CWG1CON0bits.G1OEA // bit 5
5849 #define G1OEB CWG1CON0bits.G1OEB // bit 6
5850 #define G1EN CWG1CON0bits.G1EN // bit 7
5852 #define G1IS0 CWG1CON1bits.G1IS0 // bit 0
5853 #define G1IS1 CWG1CON1bits.G1IS1 // bit 1
5854 #define G1IS2 CWG1CON1bits.G1IS2 // bit 2
5855 #define G1ASDLA0 CWG1CON1bits.G1ASDLA0 // bit 4
5856 #define G1ASDLA1 CWG1CON1bits.G1ASDLA1 // bit 5
5857 #define G1ASDLB0 CWG1CON1bits.G1ASDLB0 // bit 6
5858 #define G1ASDLB1 CWG1CON1bits.G1ASDLB1 // bit 7
5860 #define G1ASDSCLC2 CWG1CON2bits.G1ASDSCLC2 // bit 0
5861 #define G1ASDSFLT CWG1CON2bits.G1ASDSFLT // bit 1
5862 #define G1ASDSC1 CWG1CON2bits.G1ASDSC1 // bit 2
5863 #define G1ASDSC2 CWG1CON2bits.G1ASDSC2 // bit 3
5864 #define G1ARSEN CWG1CON2bits.G1ARSEN // bit 6
5865 #define G1ASE CWG1CON2bits.G1ASE // bit 7
5867 #define CWG1DBF0 CWG1DBFbits.CWG1DBF0 // bit 0
5868 #define CWG1DBF1 CWG1DBFbits.CWG1DBF1 // bit 1
5869 #define CWG1DBF2 CWG1DBFbits.CWG1DBF2 // bit 2
5870 #define CWG1DBF3 CWG1DBFbits.CWG1DBF3 // bit 3
5871 #define CWG1DBF4 CWG1DBFbits.CWG1DBF4 // bit 4
5872 #define CWG1DBF5 CWG1DBFbits.CWG1DBF5 // bit 5
5874 #define CWG1DBR0 CWG1DBRbits.CWG1DBR0 // bit 0
5875 #define CWG1DBR1 CWG1DBRbits.CWG1DBR1 // bit 1
5876 #define CWG1DBR2 CWG1DBRbits.CWG1DBR2 // bit 2
5877 #define CWG1DBR3 CWG1DBRbits.CWG1DBR3 // bit 3
5878 #define CWG1DBR4 CWG1DBRbits.CWG1DBR4 // bit 4
5879 #define CWG1DBR5 CWG1DBRbits.CWG1DBR5 // bit 5
5881 #define DACPSS DACCON0bits.DACPSS // bit 2
5882 #define DACOE2 DACCON0bits.DACOE2 // bit 4
5883 #define DACOE1 DACCON0bits.DACOE1 // bit 5
5884 #define DACEN DACCON0bits.DACEN // bit 7
5886 #define DACR0 DACCON1bits.DACR0 // bit 0
5887 #define DACR1 DACCON1bits.DACR1 // bit 1
5888 #define DACR2 DACCON1bits.DACR2 // bit 2
5889 #define DACR3 DACCON1bits.DACR3 // bit 3
5890 #define DACR4 DACCON1bits.DACR4 // bit 4
5892 #define DEVSEL0 DEVSELbits.DEVSEL0 // bit 0
5893 #define DEVSEL1 DEVSELbits.DEVSEL1 // bit 1
5894 #define DEVSEL2 DEVSELbits.DEVSEL2 // bit 2
5896 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
5897 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
5898 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
5899 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
5900 #define TSRNG FVRCONbits.TSRNG // bit 4
5901 #define TSEN FVRCONbits.TSEN // bit 5
5902 #define FVRRDY FVRCONbits.FVRRDY // bit 6
5903 #define FVREN FVRCONbits.FVREN // bit 7
5905 #define BKHLT ICDBK0CONbits.BKHLT // bit 0
5906 #define BKEN ICDBK0CONbits.BKEN // bit 7
5908 #define BKA8 ICDBK0Hbits.BKA8 // bit 0
5909 #define BKA9 ICDBK0Hbits.BKA9 // bit 1
5910 #define BKA10 ICDBK0Hbits.BKA10 // bit 2
5911 #define BKA11 ICDBK0Hbits.BKA11 // bit 3
5912 #define BKA12 ICDBK0Hbits.BKA12 // bit 4
5913 #define BKA13 ICDBK0Hbits.BKA13 // bit 5
5914 #define BKA14 ICDBK0Hbits.BKA14 // bit 6
5916 #define BKA0 ICDBK0Lbits.BKA0 // bit 0
5917 #define BKA1 ICDBK0Lbits.BKA1 // bit 1
5918 #define BKA2 ICDBK0Lbits.BKA2 // bit 2
5919 #define BKA3 ICDBK0Lbits.BKA3 // bit 3
5920 #define BKA4 ICDBK0Lbits.BKA4 // bit 4
5921 #define BKA5 ICDBK0Lbits.BKA5 // bit 5
5922 #define BKA6 ICDBK0Lbits.BKA6 // bit 6
5923 #define BKA7 ICDBK0Lbits.BKA7 // bit 7
5925 #define RSTVEC ICDCON0bits.RSTVEC // bit 0
5926 #define DBGINEX ICDCON0bits.DBGINEX // bit 3
5927 #define SSTEP ICDCON0bits.SSTEP // bit 5
5928 #define FREEZ ICDCON0bits.FREEZ // bit 6
5929 #define INBUG ICDCON0bits.INBUG // bit 7
5931 #define DBGIN8 ICDINSTHbits.DBGIN8 // bit 0
5932 #define DBGIN9 ICDINSTHbits.DBGIN9 // bit 1
5933 #define DBGIN10 ICDINSTHbits.DBGIN10 // bit 2
5934 #define DBGIN11 ICDINSTHbits.DBGIN11 // bit 3
5935 #define DBGIN12 ICDINSTHbits.DBGIN12 // bit 4
5936 #define DBGIN13 ICDINSTHbits.DBGIN13 // bit 5
5938 #define DBGIN0 ICDINSTLbits.DBGIN0 // bit 0
5939 #define DBGIN1 ICDINSTLbits.DBGIN1 // bit 1
5940 #define DBGIN2 ICDINSTLbits.DBGIN2 // bit 2
5941 #define DBGIN3 ICDINSTLbits.DBGIN3 // bit 3
5942 #define DBGIN4 ICDINSTLbits.DBGIN4 // bit 4
5943 #define DBGIN5 ICDINSTLbits.DBGIN5 // bit 5
5944 #define DBGIN6 ICDINSTLbits.DBGIN6 // bit 6
5945 #define DBGIN7 ICDINSTLbits.DBGIN7 // bit 7
5947 #define TRIS_ICDCLK ICDIObits.TRIS_ICDCLK // bit 2
5948 #define TRIS_ICDDAT ICDIObits.TRIS_ICDDAT // bit 3
5949 #define LAT_ICDCLK ICDIObits.LAT_ICDCLK // bit 4
5950 #define LAT_ICDDAT ICDIObits.LAT_ICDDAT // bit 5
5951 #define PORT_ICDCLK ICDIObits.PORT_ICDCLK // bit 6
5952 #define PORT_ICDDAT ICDIObits.PORT_ICDDAT // bit 7
5954 #define USRHLTF ICDSTATbits.USRHLTF // bit 1
5955 #define TRP0HLTF ICDSTATbits.TRP0HLTF // bit 6
5956 #define TRP1HLTF ICDSTATbits.TRP1HLTF // bit 7
5958 #define IOCIF INTCONbits.IOCIF // bit 0
5959 #define INTF INTCONbits.INTF // bit 1
5960 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
5961 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
5962 #define IOCIE INTCONbits.IOCIE // bit 3
5963 #define INTE INTCONbits.INTE // bit 4
5964 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
5965 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
5966 #define PEIE INTCONbits.PEIE // bit 6
5967 #define GIE INTCONbits.GIE // bit 7
5969 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
5970 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
5971 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
5972 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
5973 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
5974 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
5976 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
5977 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
5978 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
5979 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
5980 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
5981 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
5983 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
5984 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
5985 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
5986 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
5987 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
5988 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
5990 #define IOCBF4 IOCBFbits.IOCBF4 // bit 4
5991 #define IOCBF5 IOCBFbits.IOCBF5 // bit 5
5992 #define IOCBF6 IOCBFbits.IOCBF6 // bit 6
5993 #define IOCBF7 IOCBFbits.IOCBF7 // bit 7
5995 #define IOCBN4 IOCBNbits.IOCBN4 // bit 4
5996 #define IOCBN5 IOCBNbits.IOCBN5 // bit 5
5997 #define IOCBN6 IOCBNbits.IOCBN6 // bit 6
5998 #define IOCBN7 IOCBNbits.IOCBN7 // bit 7
6000 #define IOCBP4 IOCBPbits.IOCBP4 // bit 4
6001 #define IOCBP5 IOCBPbits.IOCBP5 // bit 5
6002 #define IOCBP6 IOCBPbits.IOCBP6 // bit 6
6003 #define IOCBP7 IOCBPbits.IOCBP7 // bit 7
6005 #define LATA0 LATAbits.LATA0 // bit 0
6006 #define LATA1 LATAbits.LATA1 // bit 1
6007 #define LATA2 LATAbits.LATA2 // bit 2
6008 #define LATA4 LATAbits.LATA4 // bit 4
6009 #define LATA5 LATAbits.LATA5 // bit 5
6011 #define LATB4 LATBbits.LATB4 // bit 4
6012 #define LATB5 LATBbits.LATB5 // bit 5
6013 #define LATB6 LATBbits.LATB6 // bit 6
6014 #define LATB7 LATBbits.LATB7 // bit 7
6016 #define LATC0 LATCbits.LATC0 // bit 0
6017 #define LATC1 LATCbits.LATC1 // bit 1
6018 #define LATC2 LATCbits.LATC2 // bit 2
6019 #define LATC3 LATCbits.LATC3 // bit 3
6020 #define LATC4 LATCbits.LATC4 // bit 4
6021 #define LATC5 LATCbits.LATC5 // bit 5
6022 #define LATC6 LATCbits.LATC6 // bit 6
6023 #define LATC7 LATCbits.LATC7 // bit 7
6025 #define NCO1ACC8 NCO1ACCHbits.NCO1ACC8 // bit 0
6026 #define NCO1ACC9 NCO1ACCHbits.NCO1ACC9 // bit 1
6027 #define NCO1ACC10 NCO1ACCHbits.NCO1ACC10 // bit 2
6028 #define NCO1ACC11 NCO1ACCHbits.NCO1ACC11 // bit 3
6029 #define NCO1ACC12 NCO1ACCHbits.NCO1ACC12 // bit 4
6030 #define NCO1ACC13 NCO1ACCHbits.NCO1ACC13 // bit 5
6031 #define NCO1ACC14 NCO1ACCHbits.NCO1ACC14 // bit 6
6032 #define NCO1ACC15 NCO1ACCHbits.NCO1ACC15 // bit 7
6034 #define NCO1ACC0 NCO1ACCLbits.NCO1ACC0 // bit 0
6035 #define NCO1ACC1 NCO1ACCLbits.NCO1ACC1 // bit 1
6036 #define NCO1ACC2 NCO1ACCLbits.NCO1ACC2 // bit 2
6037 #define NCO1ACC3 NCO1ACCLbits.NCO1ACC3 // bit 3
6038 #define NCO1ACC4 NCO1ACCLbits.NCO1ACC4 // bit 4
6039 #define NCO1ACC5 NCO1ACCLbits.NCO1ACC5 // bit 5
6040 #define NCO1ACC6 NCO1ACCLbits.NCO1ACC6 // bit 6
6041 #define NCO1ACC7 NCO1ACCLbits.NCO1ACC7 // bit 7
6043 #define NCO1ACC16 NCO1ACCUbits.NCO1ACC16 // bit 0
6044 #define NCO1ACC17 NCO1ACCUbits.NCO1ACC17 // bit 1
6045 #define NCO1ACC18 NCO1ACCUbits.NCO1ACC18 // bit 2
6046 #define NCO1ACC19 NCO1ACCUbits.NCO1ACC19 // bit 3
6048 #define N1CKS0 NCO1CLKbits.N1CKS0 // bit 0
6049 #define N1CKS1 NCO1CLKbits.N1CKS1 // bit 1
6050 #define N1PWS0 NCO1CLKbits.N1PWS0 // bit 5
6051 #define N1PWS1 NCO1CLKbits.N1PWS1 // bit 6
6052 #define N1PWS2 NCO1CLKbits.N1PWS2 // bit 7
6054 #define N1PFM NCO1CONbits.N1PFM // bit 0
6055 #define N1POL NCO1CONbits.N1POL // bit 4
6056 #define N1OUT NCO1CONbits.N1OUT // bit 5
6057 #define N1OE NCO1CONbits.N1OE // bit 6
6058 #define N1EN NCO1CONbits.N1EN // bit 7
6060 #define NCO1INC8 NCO1INCHbits.NCO1INC8 // bit 0
6061 #define NCO1INC9 NCO1INCHbits.NCO1INC9 // bit 1
6062 #define NCO1INC10 NCO1INCHbits.NCO1INC10 // bit 2
6063 #define NCO1INC11 NCO1INCHbits.NCO1INC11 // bit 3
6064 #define NCO1INC12 NCO1INCHbits.NCO1INC12 // bit 4
6065 #define NCO1INC13 NCO1INCHbits.NCO1INC13 // bit 5
6066 #define NCO1INC14 NCO1INCHbits.NCO1INC14 // bit 6
6067 #define NCO1INC15 NCO1INCHbits.NCO1INC15 // bit 7
6069 #define NCO1INC0 NCO1INCLbits.NCO1INC0 // bit 0
6070 #define NCO1INC1 NCO1INCLbits.NCO1INC1 // bit 1
6071 #define NCO1INC2 NCO1INCLbits.NCO1INC2 // bit 2
6072 #define NCO1INC3 NCO1INCLbits.NCO1INC3 // bit 3
6073 #define NCO1INC4 NCO1INCLbits.NCO1INC4 // bit 4
6074 #define NCO1INC5 NCO1INCLbits.NCO1INC5 // bit 5
6075 #define NCO1INC6 NCO1INCLbits.NCO1INC6 // bit 6
6076 #define NCO1INC7 NCO1INCLbits.NCO1INC7 // bit 7
6078 #define PS0 OPTION_REGbits.PS0 // bit 0
6079 #define PS1 OPTION_REGbits.PS1 // bit 1
6080 #define PS2 OPTION_REGbits.PS2 // bit 2
6081 #define PSA OPTION_REGbits.PSA // bit 3
6082 #define TMR0SE OPTION_REGbits.TMR0SE // bit 4, shadows bit in OPTION_REGbits
6083 #define T0SE OPTION_REGbits.T0SE // bit 4, shadows bit in OPTION_REGbits
6084 #define TMR0CS OPTION_REGbits.TMR0CS // bit 5, shadows bit in OPTION_REGbits
6085 #define T0CS OPTION_REGbits.T0CS // bit 5, shadows bit in OPTION_REGbits
6086 #define INTEDG OPTION_REGbits.INTEDG // bit 6
6087 #define NOT_WPUEN OPTION_REGbits.NOT_WPUEN // bit 7
6089 #define SCS0 OSCCONbits.SCS0 // bit 0
6090 #define SCS1 OSCCONbits.SCS1 // bit 1
6091 #define IRCF0 OSCCONbits.IRCF0 // bit 3
6092 #define IRCF1 OSCCONbits.IRCF1 // bit 4
6093 #define IRCF2 OSCCONbits.IRCF2 // bit 5
6094 #define IRCF3 OSCCONbits.IRCF3 // bit 6
6096 #define HFIOFS OSCSTATbits.HFIOFS // bit 0
6097 #define LFIOFR OSCSTATbits.LFIOFR // bit 1
6098 #define HFIOFR OSCSTATbits.HFIOFR // bit 4
6099 #define OSTS OSCSTATbits.OSTS // bit 5
6100 #define SOSCR OSCSTATbits.SOSCR // bit 7
6102 #define NOT_BOR PCONbits.NOT_BOR // bit 0
6103 #define NOT_POR PCONbits.NOT_POR // bit 1
6104 #define NOT_RI PCONbits.NOT_RI // bit 2
6105 #define NOT_RMCLR PCONbits.NOT_RMCLR // bit 3
6106 #define NOT_RWDT PCONbits.NOT_RWDT // bit 4
6107 #define STKUNF PCONbits.STKUNF // bit 6
6108 #define STKOVF PCONbits.STKOVF // bit 7
6110 #define TMR1IE PIE1bits.TMR1IE // bit 0
6111 #define TMR2IE PIE1bits.TMR2IE // bit 1
6112 #define SSP1IE PIE1bits.SSP1IE // bit 3
6113 #define TXIE PIE1bits.TXIE // bit 4
6114 #define RCIE PIE1bits.RCIE // bit 5
6115 #define ADIE PIE1bits.ADIE // bit 6
6116 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
6118 #define NCO1IE PIE2bits.NCO1IE // bit 2
6119 #define BCL1IE PIE2bits.BCL1IE // bit 3
6120 #define C1IE PIE2bits.C1IE // bit 5
6121 #define C2IE PIE2bits.C2IE // bit 6
6122 #define OSFIE PIE2bits.OSFIE // bit 7
6124 #define CLC1IE PIE3bits.CLC1IE // bit 0
6125 #define CLC2IE PIE3bits.CLC2IE // bit 1
6126 #define CLC3IE PIE3bits.CLC3IE // bit 2
6127 #define CLC4IE PIE3bits.CLC4IE // bit 3
6129 #define TMR1IF PIR1bits.TMR1IF // bit 0
6130 #define TMR2IF PIR1bits.TMR2IF // bit 1
6131 #define SSP1IF PIR1bits.SSP1IF // bit 3
6132 #define TXIF PIR1bits.TXIF // bit 4
6133 #define RCIF PIR1bits.RCIF // bit 5
6134 #define ADIF PIR1bits.ADIF // bit 6
6135 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
6137 #define NCO1IF PIR2bits.NCO1IF // bit 2
6138 #define BCL1IF PIR2bits.BCL1IF // bit 3
6139 #define C1IF PIR2bits.C1IF // bit 5
6140 #define C2IF PIR2bits.C2IF // bit 6
6141 #define OSFIF PIR2bits.OSFIF // bit 7
6143 #define CLC1IF PIR3bits.CLC1IF // bit 0
6144 #define CLC2IF PIR3bits.CLC2IF // bit 1
6145 #define CLC3IF PIR3bits.CLC3IF // bit 2
6146 #define CLC4IF PIR3bits.CLC4IF // bit 3
6148 #define RD PMCON1bits.RD // bit 0
6149 #define WR PMCON1bits.WR // bit 1
6150 #define WREN PMCON1bits.WREN // bit 2
6151 #define WRERR PMCON1bits.WRERR // bit 3
6152 #define FREE PMCON1bits.FREE // bit 4
6153 #define LWLO PMCON1bits.LWLO // bit 5
6154 #define CFGS PMCON1bits.CFGS // bit 6
6156 #define RA0 PORTAbits.RA0 // bit 0
6157 #define RA1 PORTAbits.RA1 // bit 1
6158 #define RA2 PORTAbits.RA2 // bit 2
6159 #define RA3 PORTAbits.RA3 // bit 3
6160 #define RA4 PORTAbits.RA4 // bit 4
6161 #define RA5 PORTAbits.RA5 // bit 5
6163 #define RB4 PORTBbits.RB4 // bit 4
6164 #define RB5 PORTBbits.RB5 // bit 5
6165 #define RB6 PORTBbits.RB6 // bit 6
6166 #define RB7 PORTBbits.RB7 // bit 7
6168 #define RC0 PORTCbits.RC0 // bit 0
6169 #define RC1 PORTCbits.RC1 // bit 1
6170 #define RC2 PORTCbits.RC2 // bit 2
6171 #define RC3 PORTCbits.RC3 // bit 3
6172 #define RC4 PORTCbits.RC4 // bit 4
6173 #define RC5 PORTCbits.RC5 // bit 5
6174 #define RC6 PORTCbits.RC6 // bit 6
6175 #define RC7 PORTCbits.RC7 // bit 7
6177 #define PWM1POL PWM1CONbits.PWM1POL // bit 4
6178 #define PWM1OUT PWM1CONbits.PWM1OUT // bit 5
6179 #define PWM1OE PWM1CONbits.PWM1OE // bit 6
6180 #define PWM1EN PWM1CONbits.PWM1EN // bit 7
6182 #define PWM1DCH0 PWM1DCHbits.PWM1DCH0 // bit 0
6183 #define PWM1DCH1 PWM1DCHbits.PWM1DCH1 // bit 1
6184 #define PWM1DCH2 PWM1DCHbits.PWM1DCH2 // bit 2
6185 #define PWM1DCH3 PWM1DCHbits.PWM1DCH3 // bit 3
6186 #define PWM1DCH4 PWM1DCHbits.PWM1DCH4 // bit 4
6187 #define PWM1DCH5 PWM1DCHbits.PWM1DCH5 // bit 5
6188 #define PWM1DCH6 PWM1DCHbits.PWM1DCH6 // bit 6
6189 #define PWM1DCH7 PWM1DCHbits.PWM1DCH7 // bit 7
6191 #define PWM1DCL0 PWM1DCLbits.PWM1DCL0 // bit 6
6192 #define PWM1DCL1 PWM1DCLbits.PWM1DCL1 // bit 7
6194 #define PWM2POL PWM2CONbits.PWM2POL // bit 4
6195 #define PWM2OUT PWM2CONbits.PWM2OUT // bit 5
6196 #define PWM2OE PWM2CONbits.PWM2OE // bit 6
6197 #define PWM2EN PWM2CONbits.PWM2EN // bit 7
6199 #define PWM2DCH0 PWM2DCHbits.PWM2DCH0 // bit 0
6200 #define PWM2DCH1 PWM2DCHbits.PWM2DCH1 // bit 1
6201 #define PWM2DCH2 PWM2DCHbits.PWM2DCH2 // bit 2
6202 #define PWM2DCH3 PWM2DCHbits.PWM2DCH3 // bit 3
6203 #define PWM2DCH4 PWM2DCHbits.PWM2DCH4 // bit 4
6204 #define PWM2DCH5 PWM2DCHbits.PWM2DCH5 // bit 5
6205 #define PWM2DCH6 PWM2DCHbits.PWM2DCH6 // bit 6
6206 #define PWM2DCH7 PWM2DCHbits.PWM2DCH7 // bit 7
6208 #define PWM2DCL0 PWM2DCLbits.PWM2DCL0 // bit 6
6209 #define PWM2DCL1 PWM2DCLbits.PWM2DCL1 // bit 7
6211 #define PWM3POL PWM3CONbits.PWM3POL // bit 4
6212 #define PWM3OUT PWM3CONbits.PWM3OUT // bit 5
6213 #define PWM3OE PWM3CONbits.PWM3OE // bit 6
6214 #define PWM3EN PWM3CONbits.PWM3EN // bit 7
6216 #define PWM3DCH0 PWM3DCHbits.PWM3DCH0 // bit 0
6217 #define PWM3DCH1 PWM3DCHbits.PWM3DCH1 // bit 1
6218 #define PWM3DCH2 PWM3DCHbits.PWM3DCH2 // bit 2
6219 #define PWM3DCH3 PWM3DCHbits.PWM3DCH3 // bit 3
6220 #define PWM3DCH4 PWM3DCHbits.PWM3DCH4 // bit 4
6221 #define PWM3DCH5 PWM3DCHbits.PWM3DCH5 // bit 5
6222 #define PWM3DCH6 PWM3DCHbits.PWM3DCH6 // bit 6
6223 #define PWM3DCH7 PWM3DCHbits.PWM3DCH7 // bit 7
6225 #define PWM3DCL0 PWM3DCLbits.PWM3DCL0 // bit 6
6226 #define PWM3DCL1 PWM3DCLbits.PWM3DCL1 // bit 7
6228 #define PWM4POL PWM4CONbits.PWM4POL // bit 4
6229 #define PWM4OUT PWM4CONbits.PWM4OUT // bit 5
6230 #define PWM4OE PWM4CONbits.PWM4OE // bit 6
6231 #define PWM4EN PWM4CONbits.PWM4EN // bit 7
6233 #define PWM4DCH0 PWM4DCHbits.PWM4DCH0 // bit 0
6234 #define PWM4DCH1 PWM4DCHbits.PWM4DCH1 // bit 1
6235 #define PWM4DCH2 PWM4DCHbits.PWM4DCH2 // bit 2
6236 #define PWM4DCH3 PWM4DCHbits.PWM4DCH3 // bit 3
6237 #define PWM4DCH4 PWM4DCHbits.PWM4DCH4 // bit 4
6238 #define PWM4DCH5 PWM4DCHbits.PWM4DCH5 // bit 5
6239 #define PWM4DCH6 PWM4DCHbits.PWM4DCH6 // bit 6
6240 #define PWM4DCH7 PWM4DCHbits.PWM4DCH7 // bit 7
6242 #define PWM4DCL0 PWM4DCLbits.PWM4DCL0 // bit 6
6243 #define PWM4DCL1 PWM4DCLbits.PWM4DCL1 // bit 7
6245 #define RX9D RCSTAbits.RX9D // bit 0
6246 #define OERR RCSTAbits.OERR // bit 1
6247 #define FERR RCSTAbits.FERR // bit 2
6248 #define ADDEN RCSTAbits.ADDEN // bit 3
6249 #define CREN RCSTAbits.CREN // bit 4
6250 #define SREN RCSTAbits.SREN // bit 5
6251 #define RX9 RCSTAbits.RX9 // bit 6
6252 #define SPEN RCSTAbits.SPEN // bit 7
6254 #define SSPM0 SSP1CON1bits.SSPM0 // bit 0
6255 #define SSPM1 SSP1CON1bits.SSPM1 // bit 1
6256 #define SSPM2 SSP1CON1bits.SSPM2 // bit 2
6257 #define SSPM3 SSP1CON1bits.SSPM3 // bit 3
6258 #define CKP SSP1CON1bits.CKP // bit 4
6259 #define SSPEN SSP1CON1bits.SSPEN // bit 5
6260 #define SSPOV SSP1CON1bits.SSPOV // bit 6
6261 #define WCOL SSP1CON1bits.WCOL // bit 7
6263 #define SEN SSP1CON2bits.SEN // bit 0
6264 #define RSEN SSP1CON2bits.RSEN // bit 1
6265 #define PEN SSP1CON2bits.PEN // bit 2
6266 #define RCEN SSP1CON2bits.RCEN // bit 3
6267 #define ACKEN SSP1CON2bits.ACKEN // bit 4
6268 #define ACKDT SSP1CON2bits.ACKDT // bit 5
6269 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
6270 #define GCEN SSP1CON2bits.GCEN // bit 7
6272 #define DHEN SSP1CON3bits.DHEN // bit 0
6273 #define AHEN SSP1CON3bits.AHEN // bit 1
6274 #define SBCDE SSP1CON3bits.SBCDE // bit 2
6275 #define SDAHT SSP1CON3bits.SDAHT // bit 3
6276 #define BOEN SSP1CON3bits.BOEN // bit 4
6277 #define SCIE SSP1CON3bits.SCIE // bit 5
6278 #define PCIE SSP1CON3bits.PCIE // bit 6
6279 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
6281 #define BF SSP1STATbits.BF // bit 0
6282 #define UA SSP1STATbits.UA // bit 1
6283 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
6284 #define S SSP1STATbits.S // bit 3
6285 #define P SSP1STATbits.P // bit 4
6286 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
6287 #define CKE SSP1STATbits.CKE // bit 6
6288 #define SMP SSP1STATbits.SMP // bit 7
6290 #define C STATUSbits.C // bit 0
6291 #define DC STATUSbits.DC // bit 1
6292 #define Z STATUSbits.Z // bit 2
6293 #define NOT_PD STATUSbits.NOT_PD // bit 3
6294 #define NOT_TO STATUSbits.NOT_TO // bit 4
6296 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
6297 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
6298 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
6300 #define TMR1ON T1CONbits.TMR1ON // bit 0
6301 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
6302 #define T1OSCEN T1CONbits.T1OSCEN // bit 3
6303 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
6304 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
6305 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
6306 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
6308 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
6309 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
6310 #define T1GVAL T1GCONbits.T1GVAL // bit 2
6311 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3
6312 #define T1GSPM T1GCONbits.T1GSPM // bit 4
6313 #define T1GTM T1GCONbits.T1GTM // bit 5
6314 #define T1GPOL T1GCONbits.T1GPOL // bit 6
6315 #define TMR1GE T1GCONbits.TMR1GE // bit 7
6317 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
6318 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
6319 #define TMR2ON T2CONbits.TMR2ON // bit 2
6320 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
6321 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
6322 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
6323 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
6325 #define TRISA0 TRISAbits.TRISA0 // bit 0
6326 #define TRISA1 TRISAbits.TRISA1 // bit 1
6327 #define TRISA2 TRISAbits.TRISA2 // bit 2
6328 #define TRISA3 TRISAbits.TRISA3 // bit 3
6329 #define TRISA4 TRISAbits.TRISA4 // bit 4
6330 #define TRISA5 TRISAbits.TRISA5 // bit 5
6332 #define TRISB4 TRISBbits.TRISB4 // bit 4
6333 #define TRISB5 TRISBbits.TRISB5 // bit 5
6334 #define TRISB6 TRISBbits.TRISB6 // bit 6
6335 #define TRISB7 TRISBbits.TRISB7 // bit 7
6337 #define TRISC0 TRISCbits.TRISC0 // bit 0
6338 #define TRISC1 TRISCbits.TRISC1 // bit 1
6339 #define TRISC2 TRISCbits.TRISC2 // bit 2
6340 #define TRISC3 TRISCbits.TRISC3 // bit 3
6341 #define TRISC4 TRISCbits.TRISC4 // bit 4
6342 #define TRISC5 TRISCbits.TRISC5 // bit 5
6343 #define TRISC6 TRISCbits.TRISC6 // bit 6
6344 #define TRISC7 TRISCbits.TRISC7 // bit 7
6346 #define TX9D TXSTAbits.TX9D // bit 0
6347 #define TRMT TXSTAbits.TRMT // bit 1
6348 #define BRGH TXSTAbits.BRGH // bit 2
6349 #define SENDB TXSTAbits.SENDB // bit 3
6350 #define SYNC TXSTAbits.SYNC // bit 4
6351 #define TXEN TXSTAbits.TXEN // bit 5
6352 #define TX9 TXSTAbits.TX9 // bit 6
6353 #define CSRC TXSTAbits.CSRC // bit 7
6355 #define Reserved VREGCONbits.Reserved // bit 0
6356 #define VREGPM VREGCONbits.VREGPM // bit 1
6358 #define SWDTEN WDTCONbits.SWDTEN // bit 0
6359 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
6360 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
6361 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
6362 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
6363 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
6365 #define WPUA0 WPUAbits.WPUA0 // bit 0
6366 #define WPUA1 WPUAbits.WPUA1 // bit 1
6367 #define WPUA2 WPUAbits.WPUA2 // bit 2
6368 #define WPUA3 WPUAbits.WPUA3 // bit 3
6369 #define WPUA4 WPUAbits.WPUA4 // bit 4
6370 #define WPUA5 WPUAbits.WPUA5 // bit 5
6372 #define WPUB4 WPUBbits.WPUB4 // bit 4
6373 #define WPUB5 WPUBbits.WPUB5 // bit 5
6374 #define WPUB6 WPUBbits.WPUB6 // bit 6
6375 #define WPUB7 WPUBbits.WPUB7 // bit 7
6377 #endif // #ifndef NO_BIT_DEFINES
6379 #endif // #ifndef __PIC16F1509_H__