2 * This declarations of the PIC16F1705 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:11 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F1705_H__
26 #define __PIC16F1705_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTC_ADDR 0x000E
52 #define PIR1_ADDR 0x0011
53 #define PIR2_ADDR 0x0012
54 #define PIR3_ADDR 0x0013
55 #define TMR0_ADDR 0x0015
56 #define TMR1_ADDR 0x0016
57 #define TMR1L_ADDR 0x0016
58 #define TMR1H_ADDR 0x0017
59 #define T1CON_ADDR 0x0018
60 #define T1GCON_ADDR 0x0019
61 #define TMR2_ADDR 0x001A
62 #define PR2_ADDR 0x001B
63 #define T2CON_ADDR 0x001C
64 #define TRISA_ADDR 0x008C
65 #define TRISC_ADDR 0x008E
66 #define PIE1_ADDR 0x0091
67 #define PIE2_ADDR 0x0092
68 #define PIE3_ADDR 0x0093
69 #define OPTION_REG_ADDR 0x0095
70 #define PCON_ADDR 0x0096
71 #define WDTCON_ADDR 0x0097
72 #define OSCTUNE_ADDR 0x0098
73 #define OSCCON_ADDR 0x0099
74 #define OSCSTAT_ADDR 0x009A
75 #define ADRES_ADDR 0x009B
76 #define ADRESL_ADDR 0x009B
77 #define ADRESH_ADDR 0x009C
78 #define ADCON0_ADDR 0x009D
79 #define ADCON1_ADDR 0x009E
80 #define ADCON2_ADDR 0x009F
81 #define LATA_ADDR 0x010C
82 #define LATC_ADDR 0x010E
83 #define CM1CON0_ADDR 0x0111
84 #define CM1CON1_ADDR 0x0112
85 #define CM2CON0_ADDR 0x0113
86 #define CM2CON1_ADDR 0x0114
87 #define CMOUT_ADDR 0x0115
88 #define BORCON_ADDR 0x0116
89 #define FVRCON_ADDR 0x0117
90 #define DAC1CON0_ADDR 0x0118
91 #define DAC1CON1_ADDR 0x0119
92 #define ZCD1CON_ADDR 0x011C
93 #define ANSELA_ADDR 0x018C
94 #define ANSELC_ADDR 0x018E
95 #define PMADR_ADDR 0x0191
96 #define PMADRL_ADDR 0x0191
97 #define PMADRH_ADDR 0x0192
98 #define PMDAT_ADDR 0x0193
99 #define PMDATL_ADDR 0x0193
100 #define PMDATH_ADDR 0x0194
101 #define PMCON1_ADDR 0x0195
102 #define PMCON2_ADDR 0x0196
103 #define VREGCON_ADDR 0x0197
104 #define RC1REG_ADDR 0x0199
105 #define RCREG_ADDR 0x0199
106 #define RCREG1_ADDR 0x0199
107 #define TX1REG_ADDR 0x019A
108 #define TXREG_ADDR 0x019A
109 #define TXREG1_ADDR 0x019A
110 #define SP1BRG_ADDR 0x019B
111 #define SP1BRGL_ADDR 0x019B
112 #define SPBRG_ADDR 0x019B
113 #define SPBRG1_ADDR 0x019B
114 #define SPBRGL_ADDR 0x019B
115 #define SP1BRGH_ADDR 0x019C
116 #define SPBRGH_ADDR 0x019C
117 #define SPBRGH1_ADDR 0x019C
118 #define RC1STA_ADDR 0x019D
119 #define RCSTA_ADDR 0x019D
120 #define RCSTA1_ADDR 0x019D
121 #define TX1STA_ADDR 0x019E
122 #define TXSTA_ADDR 0x019E
123 #define TXSTA1_ADDR 0x019E
124 #define BAUD1CON_ADDR 0x019F
125 #define BAUDCON_ADDR 0x019F
126 #define BAUDCON1_ADDR 0x019F
127 #define BAUDCTL_ADDR 0x019F
128 #define BAUDCTL1_ADDR 0x019F
129 #define WPUA_ADDR 0x020C
130 #define WPUC_ADDR 0x020E
131 #define SSP1BUF_ADDR 0x0211
132 #define SSPBUF_ADDR 0x0211
133 #define SSP1ADD_ADDR 0x0212
134 #define SSPADD_ADDR 0x0212
135 #define SSP1MSK_ADDR 0x0213
136 #define SSPMSK_ADDR 0x0213
137 #define SSP1STAT_ADDR 0x0214
138 #define SSPSTAT_ADDR 0x0214
139 #define SSP1CON_ADDR 0x0215
140 #define SSP1CON1_ADDR 0x0215
141 #define SSPCON_ADDR 0x0215
142 #define SSPCON1_ADDR 0x0215
143 #define SSP1CON2_ADDR 0x0216
144 #define SSPCON2_ADDR 0x0216
145 #define SSP1CON3_ADDR 0x0217
146 #define SSPCON3_ADDR 0x0217
147 #define ODCONA_ADDR 0x028C
148 #define ODCONC_ADDR 0x028E
149 #define CCPR1_ADDR 0x0291
150 #define CCPR1L_ADDR 0x0291
151 #define CCPR1H_ADDR 0x0292
152 #define CCP1CON_ADDR 0x0293
153 #define ECCP1CON_ADDR 0x0293
154 #define CCPR2_ADDR 0x0298
155 #define CCPR2L_ADDR 0x0298
156 #define CCPR2H_ADDR 0x0299
157 #define CCP2CON_ADDR 0x029A
158 #define ECCP2CON_ADDR 0x029A
159 #define CCPTMRS_ADDR 0x029E
160 #define SLRCONA_ADDR 0x030C
161 #define SLRCONC_ADDR 0x030E
162 #define INLVLA_ADDR 0x038C
163 #define INLVLC_ADDR 0x038E
164 #define IOCAP_ADDR 0x0391
165 #define IOCAN_ADDR 0x0392
166 #define IOCAF_ADDR 0x0393
167 #define IOCCP_ADDR 0x0397
168 #define IOCCN_ADDR 0x0398
169 #define IOCCF_ADDR 0x0399
170 #define TMR4_ADDR 0x0415
171 #define PR4_ADDR 0x0416
172 #define T4CON_ADDR 0x0417
173 #define TMR6_ADDR 0x041C
174 #define PR6_ADDR 0x041D
175 #define T6CON_ADDR 0x041E
176 #define OPA1CON_ADDR 0x0511
177 #define OPA2CON_ADDR 0x0515
178 #define PWM3DCL_ADDR 0x0617
179 #define PWM3DCH_ADDR 0x0618
180 #define PWM3CON_ADDR 0x0619
181 #define PWM3CON0_ADDR 0x0619
182 #define PWM4DCL_ADDR 0x061A
183 #define PWM4DCH_ADDR 0x061B
184 #define PWM4CON_ADDR 0x061C
185 #define PWM4CON0_ADDR 0x061C
186 #define COG1PHR_ADDR 0x0691
187 #define COG1PHF_ADDR 0x0692
188 #define COG1BLKR_ADDR 0x0693
189 #define COG1BLKF_ADDR 0x0694
190 #define COG1DBR_ADDR 0x0695
191 #define COG1DBF_ADDR 0x0696
192 #define COG1CON0_ADDR 0x0697
193 #define COG1CON1_ADDR 0x0698
194 #define COG1RIS_ADDR 0x0699
195 #define COG1RSIM_ADDR 0x069A
196 #define COG1FIS_ADDR 0x069B
197 #define COG1FSIM_ADDR 0x069C
198 #define COG1ASD0_ADDR 0x069D
199 #define COG1ASD1_ADDR 0x069E
200 #define COG1STR_ADDR 0x069F
201 #define PPSLOCK_ADDR 0x0E0F
202 #define INTPPS_ADDR 0x0E10
203 #define T0CKIPPS_ADDR 0x0E11
204 #define T1CKIPPS_ADDR 0x0E12
205 #define T1GPPS_ADDR 0x0E13
206 #define CCP1PPS_ADDR 0x0E14
207 #define CCP2PPS_ADDR 0x0E15
208 #define COGINPPS_ADDR 0x0E17
209 #define SSPCLKPPS_ADDR 0x0E20
210 #define SSPDATPPS_ADDR 0x0E21
211 #define SSPSSPPS_ADDR 0x0E22
212 #define RXPPS_ADDR 0x0E24
213 #define CKPPS_ADDR 0x0E25
214 #define CLCIN0PPS_ADDR 0x0E28
215 #define CLCIN1PPS_ADDR 0x0E29
216 #define CLCIN2PPS_ADDR 0x0E2A
217 #define CLCIN3PPS_ADDR 0x0E2B
218 #define RA0PPS_ADDR 0x0E90
219 #define RA1PPS_ADDR 0x0E91
220 #define RA2PPS_ADDR 0x0E92
221 #define RA4PPS_ADDR 0x0E94
222 #define RA5PPS_ADDR 0x0E95
223 #define RC0PPS_ADDR 0x0EA0
224 #define RC1PPS_ADDR 0x0EA1
225 #define RC2PPS_ADDR 0x0EA2
226 #define RC3PPS_ADDR 0x0EA3
227 #define RC4PPS_ADDR 0x0EA4
228 #define RC5PPS_ADDR 0x0EA5
229 #define CLCDATA_ADDR 0x0F0F
230 #define CLC1CON_ADDR 0x0F10
231 #define CLC1POL_ADDR 0x0F11
232 #define CLC1SEL0_ADDR 0x0F12
233 #define CLC1SEL1_ADDR 0x0F13
234 #define CLC1SEL2_ADDR 0x0F14
235 #define CLC1SEL3_ADDR 0x0F15
236 #define CLC1GLS0_ADDR 0x0F16
237 #define CLC1GLS1_ADDR 0x0F17
238 #define CLC1GLS2_ADDR 0x0F18
239 #define CLC1GLS3_ADDR 0x0F19
240 #define CLC2CON_ADDR 0x0F1A
241 #define CLC2POL_ADDR 0x0F1B
242 #define CLC2SEL0_ADDR 0x0F1C
243 #define CLC2SEL1_ADDR 0x0F1D
244 #define CLC2SEL2_ADDR 0x0F1E
245 #define CLC2SEL3_ADDR 0x0F1F
246 #define CLC2GLS0_ADDR 0x0F20
247 #define CLC2GLS1_ADDR 0x0F21
248 #define CLC2GLS2_ADDR 0x0F22
249 #define CLC2GLS3_ADDR 0x0F23
250 #define CLC3CON_ADDR 0x0F24
251 #define CLC3POL_ADDR 0x0F25
252 #define CLC3SEL0_ADDR 0x0F26
253 #define CLC3SEL1_ADDR 0x0F27
254 #define CLC3SEL2_ADDR 0x0F28
255 #define CLC3SEL3_ADDR 0x0F29
256 #define CLC3GLS0_ADDR 0x0F2A
257 #define CLC3GLS1_ADDR 0x0F2B
258 #define CLC3GLS2_ADDR 0x0F2C
259 #define CLC3GLS3_ADDR 0x0F2D
260 #define ICDBK0H_ADDR 0x0F9E
261 #define STATUS_SHAD_ADDR 0x0FE4
262 #define WREG_SHAD_ADDR 0x0FE5
263 #define BSR_SHAD_ADDR 0x0FE6
264 #define PCLATH_SHAD_ADDR 0x0FE7
265 #define FSR0L_SHAD_ADDR 0x0FE8
266 #define FSR0H_SHAD_ADDR 0x0FE9
267 #define FSR1L_SHAD_ADDR 0x0FEA
268 #define FSR1H_SHAD_ADDR 0x0FEB
269 #define STKPTR_ADDR 0x0FED
270 #define TOSL_ADDR 0x0FEE
271 #define TOSH_ADDR 0x0FEF
273 #endif // #ifndef NO_ADDR_DEFINES
275 //==============================================================================
277 // Register Definitions
279 //==============================================================================
281 extern __at(0x0000) __sfr INDF0
;
282 extern __at(0x0001) __sfr INDF1
;
283 extern __at(0x0002) __sfr PCL
;
285 //==============================================================================
288 extern __at(0x0003) __sfr STATUS
;
302 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
310 //==============================================================================
312 extern __at(0x0004) __sfr FSR0
;
313 extern __at(0x0004) __sfr FSR0L
;
314 extern __at(0x0005) __sfr FSR0H
;
315 extern __at(0x0006) __sfr FSR1
;
316 extern __at(0x0006) __sfr FSR1L
;
317 extern __at(0x0007) __sfr FSR1H
;
319 //==============================================================================
322 extern __at(0x0008) __sfr BSR
;
345 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
353 //==============================================================================
355 extern __at(0x0009) __sfr WREG
;
356 extern __at(0x000A) __sfr PCLATH
;
358 //==============================================================================
361 extern __at(0x000B) __sfr INTCON
;
390 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
403 //==============================================================================
406 //==============================================================================
409 extern __at(0x000C) __sfr PORTA
;
432 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
441 //==============================================================================
444 //==============================================================================
447 extern __at(0x000E) __sfr PORTC
;
470 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
479 //==============================================================================
482 //==============================================================================
485 extern __at(0x0011) __sfr PIR1
;
498 unsigned TMR1GIF
: 1;
514 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
524 #define _TMR1GIF 0x80
526 //==============================================================================
529 //==============================================================================
532 extern __at(0x0012) __sfr PIR2
;
546 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
556 //==============================================================================
559 //==============================================================================
562 extern __at(0x0013) __sfr PIR3
;
576 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
584 //==============================================================================
586 extern __at(0x0015) __sfr TMR0
;
587 extern __at(0x0016) __sfr TMR1
;
588 extern __at(0x0016) __sfr TMR1L
;
589 extern __at(0x0017) __sfr TMR1H
;
591 //==============================================================================
594 extern __at(0x0018) __sfr T1CON
;
602 unsigned NOT_T1SYNC
: 1;
603 unsigned T1OSCEN
: 1;
604 unsigned T1CKPS0
: 1;
605 unsigned T1CKPS1
: 1;
606 unsigned TMR1CS0
: 1;
607 unsigned TMR1CS1
: 1;
624 extern __at(0x0018) volatile __T1CONbits_t T1CONbits
;
627 #define _NOT_T1SYNC 0x04
628 #define _T1OSCEN 0x08
629 #define _T1CKPS0 0x10
630 #define _T1CKPS1 0x20
631 #define _TMR1CS0 0x40
632 #define _TMR1CS1 0x80
634 //==============================================================================
637 //==============================================================================
640 extern __at(0x0019) __sfr T1GCON
;
649 unsigned T1GGO_NOT_DONE
: 1;
663 extern __at(0x0019) volatile __T1GCONbits_t T1GCONbits
;
668 #define _T1GGO_NOT_DONE 0x08
674 //==============================================================================
676 extern __at(0x001A) __sfr TMR2
;
677 extern __at(0x001B) __sfr PR2
;
679 //==============================================================================
682 extern __at(0x001C) __sfr T2CON
;
688 unsigned T2CKPS0
: 1;
689 unsigned T2CKPS1
: 1;
691 unsigned T2OUTPS0
: 1;
692 unsigned T2OUTPS1
: 1;
693 unsigned T2OUTPS2
: 1;
694 unsigned T2OUTPS3
: 1;
707 unsigned T2OUTPS
: 4;
712 extern __at(0x001C) volatile __T2CONbits_t T2CONbits
;
714 #define _T2CKPS0 0x01
715 #define _T2CKPS1 0x02
717 #define _T2OUTPS0 0x08
718 #define _T2OUTPS1 0x10
719 #define _T2OUTPS2 0x20
720 #define _T2OUTPS3 0x40
722 //==============================================================================
725 //==============================================================================
728 extern __at(0x008C) __sfr TRISA
;
742 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
750 //==============================================================================
753 //==============================================================================
756 extern __at(0x008E) __sfr TRISC
;
779 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
788 //==============================================================================
791 //==============================================================================
794 extern __at(0x0091) __sfr PIE1
;
807 unsigned TMR1GIE
: 1;
823 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
833 #define _TMR1GIE 0x80
835 //==============================================================================
838 //==============================================================================
841 extern __at(0x0092) __sfr PIE2
;
855 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
865 //==============================================================================
868 //==============================================================================
871 extern __at(0x0093) __sfr PIE3
;
885 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
893 //==============================================================================
896 //==============================================================================
899 extern __at(0x0095) __sfr OPTION_REG
;
912 unsigned NOT_WPUEN
: 1;
932 } __OPTION_REGbits_t
;
934 extern __at(0x0095) volatile __OPTION_REGbits_t OPTION_REGbits
;
945 #define _NOT_WPUEN 0x80
947 //==============================================================================
950 //==============================================================================
953 extern __at(0x0096) __sfr PCON
;
957 unsigned NOT_BOR
: 1;
958 unsigned NOT_POR
: 1;
960 unsigned NOT_RMCLR
: 1;
961 unsigned NOT_RWDT
: 1;
967 extern __at(0x0096) volatile __PCONbits_t PCONbits
;
969 #define _NOT_BOR 0x01
970 #define _NOT_POR 0x02
972 #define _NOT_RMCLR 0x08
973 #define _NOT_RWDT 0x10
977 //==============================================================================
980 //==============================================================================
983 extern __at(0x0097) __sfr WDTCON
;
1007 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1009 #define _SWDTEN 0x01
1010 #define _WDTPS0 0x02
1011 #define _WDTPS1 0x04
1012 #define _WDTPS2 0x08
1013 #define _WDTPS3 0x10
1014 #define _WDTPS4 0x20
1016 //==============================================================================
1019 //==============================================================================
1022 extern __at(0x0098) __sfr OSCTUNE
;
1045 extern __at(0x0098) volatile __OSCTUNEbits_t OSCTUNEbits
;
1054 //==============================================================================
1057 //==============================================================================
1060 extern __at(0x0099) __sfr OSCCON
;
1073 unsigned SPLLEN
: 1;
1090 extern __at(0x0099) volatile __OSCCONbits_t OSCCONbits
;
1098 #define _SPLLEN 0x80
1100 //==============================================================================
1103 //==============================================================================
1106 extern __at(0x009A) __sfr OSCSTAT
;
1110 unsigned HFIOFS
: 1;
1111 unsigned LFIOFR
: 1;
1112 unsigned MFIOFR
: 1;
1113 unsigned HFIOFL
: 1;
1114 unsigned HFIOFR
: 1;
1120 extern __at(0x009A) volatile __OSCSTATbits_t OSCSTATbits
;
1122 #define _HFIOFS 0x01
1123 #define _LFIOFR 0x02
1124 #define _MFIOFR 0x04
1125 #define _HFIOFL 0x08
1126 #define _HFIOFR 0x10
1131 //==============================================================================
1133 extern __at(0x009B) __sfr ADRES
;
1134 extern __at(0x009B) __sfr ADRESL
;
1135 extern __at(0x009C) __sfr ADRESH
;
1137 //==============================================================================
1140 extern __at(0x009D) __sfr ADCON0
;
1147 unsigned GO_NOT_DONE
: 1;
1188 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1191 #define _GO_NOT_DONE 0x02
1200 //==============================================================================
1203 //==============================================================================
1206 extern __at(0x009E) __sfr ADCON1
;
1212 unsigned ADPREF0
: 1;
1213 unsigned ADPREF1
: 1;
1214 unsigned ADNREF
: 1;
1224 unsigned ADPREF
: 2;
1229 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1231 #define _ADPREF0 0x01
1232 #define _ADPREF1 0x02
1233 #define _ADNREF 0x04
1236 //==============================================================================
1239 //==============================================================================
1242 extern __at(0x009F) __sfr ADCON2
;
1252 unsigned TRIGSEL0
: 1;
1253 unsigned TRIGSEL1
: 1;
1254 unsigned TRIGSEL2
: 1;
1255 unsigned TRIGSEL3
: 1;
1261 unsigned TRIGSEL
: 4;
1265 extern __at(0x009F) volatile __ADCON2bits_t ADCON2bits
;
1267 #define _TRIGSEL0 0x10
1268 #define _TRIGSEL1 0x20
1269 #define _TRIGSEL2 0x40
1270 #define _TRIGSEL3 0x80
1272 //==============================================================================
1275 //==============================================================================
1278 extern __at(0x010C) __sfr LATA
;
1292 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1300 //==============================================================================
1303 //==============================================================================
1306 extern __at(0x010E) __sfr LATC
;
1329 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1338 //==============================================================================
1341 //==============================================================================
1344 extern __at(0x0111) __sfr CM1CON0
;
1348 unsigned C1SYNC
: 1;
1358 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1360 #define _C1SYNC 0x01
1368 //==============================================================================
1371 //==============================================================================
1374 extern __at(0x0112) __sfr CM1CON1
;
1380 unsigned C1NCH0
: 1;
1381 unsigned C1NCH1
: 1;
1382 unsigned C1NCH2
: 1;
1383 unsigned C1PCH0
: 1;
1384 unsigned C1PCH1
: 1;
1385 unsigned C1PCH2
: 1;
1386 unsigned C1INTN
: 1;
1387 unsigned C1INTP
: 1;
1404 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1406 #define _C1NCH0 0x01
1407 #define _C1NCH1 0x02
1408 #define _C1NCH2 0x04
1409 #define _C1PCH0 0x08
1410 #define _C1PCH1 0x10
1411 #define _C1PCH2 0x20
1412 #define _C1INTN 0x40
1413 #define _C1INTP 0x80
1415 //==============================================================================
1418 //==============================================================================
1421 extern __at(0x0113) __sfr CM2CON0
;
1425 unsigned C2SYNC
: 1;
1435 extern __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits
;
1437 #define _C2SYNC 0x01
1445 //==============================================================================
1448 //==============================================================================
1451 extern __at(0x0114) __sfr CM2CON1
;
1457 unsigned C2NCH0
: 1;
1458 unsigned C2NCH1
: 1;
1459 unsigned C2NCH2
: 1;
1460 unsigned C2PCH0
: 1;
1461 unsigned C2PCH1
: 1;
1462 unsigned C2PCH2
: 1;
1463 unsigned C2INTN
: 1;
1464 unsigned C2INTP
: 1;
1481 extern __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits
;
1483 #define _C2NCH0 0x01
1484 #define _C2NCH1 0x02
1485 #define _C2NCH2 0x04
1486 #define _C2PCH0 0x08
1487 #define _C2PCH1 0x10
1488 #define _C2PCH2 0x20
1489 #define _C2INTN 0x40
1490 #define _C2INTP 0x80
1492 //==============================================================================
1495 //==============================================================================
1498 extern __at(0x0115) __sfr CMOUT
;
1502 unsigned MC1OUT
: 1;
1503 unsigned MC2OUT
: 1;
1512 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1514 #define _MC1OUT 0x01
1515 #define _MC2OUT 0x02
1517 //==============================================================================
1520 //==============================================================================
1523 extern __at(0x0116) __sfr BORCON
;
1527 unsigned BORRDY
: 1;
1534 unsigned SBOREN
: 1;
1537 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1539 #define _BORRDY 0x01
1541 #define _SBOREN 0x80
1543 //==============================================================================
1546 //==============================================================================
1549 extern __at(0x0117) __sfr FVRCON
;
1555 unsigned ADFVR0
: 1;
1556 unsigned ADFVR1
: 1;
1557 unsigned CDAFVR0
: 1;
1558 unsigned CDAFVR1
: 1;
1561 unsigned FVRRDY
: 1;
1574 unsigned CDAFVR
: 2;
1579 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1581 #define _ADFVR0 0x01
1582 #define _ADFVR1 0x02
1583 #define _CDAFVR0 0x04
1584 #define _CDAFVR1 0x08
1587 #define _FVRRDY 0x40
1590 //==============================================================================
1593 //==============================================================================
1596 extern __at(0x0118) __sfr DAC1CON0
;
1602 unsigned DAC1NSS
: 1;
1604 unsigned DAC1PSS0
: 1;
1605 unsigned DAC1PSS1
: 1;
1606 unsigned DAC1OE2
: 1;
1607 unsigned DAC1OE1
: 1;
1609 unsigned DAC1EN
: 1;
1614 unsigned DACNSS
: 1;
1616 unsigned DACPSS0
: 1;
1617 unsigned DACPSS1
: 1;
1618 unsigned DACOE0
: 1;
1619 unsigned DACOE1
: 1;
1627 unsigned DAC1PSS
: 2;
1634 unsigned DACPSS
: 2;
1646 extern __at(0x0118) volatile __DAC1CON0bits_t DAC1CON0bits
;
1648 #define _DAC1NSS 0x01
1649 #define _DACNSS 0x01
1650 #define _DAC1PSS0 0x04
1651 #define _DACPSS0 0x04
1652 #define _DAC1PSS1 0x08
1653 #define _DACPSS1 0x08
1654 #define _DAC1OE2 0x10
1655 #define _DACOE0 0x10
1656 #define _DAC1OE1 0x20
1657 #define _DACOE1 0x20
1658 #define _DAC1EN 0x80
1661 //==============================================================================
1664 //==============================================================================
1667 extern __at(0x0119) __sfr DAC1CON1
;
1673 unsigned DAC1R0
: 1;
1674 unsigned DAC1R1
: 1;
1675 unsigned DAC1R2
: 1;
1676 unsigned DAC1R3
: 1;
1677 unsigned DAC1R4
: 1;
1678 unsigned DAC1R5
: 1;
1679 unsigned DAC1R6
: 1;
1680 unsigned DAC1R7
: 1;
1696 extern __at(0x0119) volatile __DAC1CON1bits_t DAC1CON1bits
;
1698 #define _DAC1R0 0x01
1700 #define _DAC1R1 0x02
1702 #define _DAC1R2 0x04
1704 #define _DAC1R3 0x08
1706 #define _DAC1R4 0x10
1708 #define _DAC1R5 0x20
1710 #define _DAC1R6 0x40
1712 #define _DAC1R7 0x80
1715 //==============================================================================
1718 //==============================================================================
1721 extern __at(0x011C) __sfr ZCD1CON
;
1725 unsigned ZCD1INTN
: 1;
1726 unsigned ZCD1INTP
: 1;
1729 unsigned ZCD1POL
: 1;
1730 unsigned ZCD1OUT
: 1;
1732 unsigned ZCD1EN
: 1;
1735 extern __at(0x011C) volatile __ZCD1CONbits_t ZCD1CONbits
;
1737 #define _ZCD1INTN 0x01
1738 #define _ZCD1INTP 0x02
1739 #define _ZCD1POL 0x10
1740 #define _ZCD1OUT 0x20
1741 #define _ZCD1EN 0x80
1743 //==============================================================================
1746 //==============================================================================
1749 extern __at(0x018C) __sfr ANSELA
;
1763 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1771 //==============================================================================
1774 //==============================================================================
1777 extern __at(0x018E) __sfr ANSELC
;
1800 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
1809 //==============================================================================
1811 extern __at(0x0191) __sfr PMADR
;
1812 extern __at(0x0191) __sfr PMADRL
;
1813 extern __at(0x0192) __sfr PMADRH
;
1814 extern __at(0x0193) __sfr PMDAT
;
1815 extern __at(0x0193) __sfr PMDATL
;
1816 extern __at(0x0194) __sfr PMDATH
;
1818 //==============================================================================
1821 extern __at(0x0195) __sfr PMCON1
;
1835 extern __at(0x0195) volatile __PMCON1bits_t PMCON1bits
;
1845 //==============================================================================
1847 extern __at(0x0196) __sfr PMCON2
;
1849 //==============================================================================
1852 extern __at(0x0197) __sfr VREGCON
;
1856 unsigned Reserved
: 1;
1857 unsigned VREGPM
: 1;
1866 extern __at(0x0197) volatile __VREGCONbits_t VREGCONbits
;
1868 #define _Reserved 0x01
1869 #define _VREGPM 0x02
1871 //==============================================================================
1873 extern __at(0x0199) __sfr RC1REG
;
1874 extern __at(0x0199) __sfr RCREG
;
1875 extern __at(0x0199) __sfr RCREG1
;
1876 extern __at(0x019A) __sfr TX1REG
;
1877 extern __at(0x019A) __sfr TXREG
;
1878 extern __at(0x019A) __sfr TXREG1
;
1879 extern __at(0x019B) __sfr SP1BRG
;
1880 extern __at(0x019B) __sfr SP1BRGL
;
1881 extern __at(0x019B) __sfr SPBRG
;
1882 extern __at(0x019B) __sfr SPBRG1
;
1883 extern __at(0x019B) __sfr SPBRGL
;
1884 extern __at(0x019C) __sfr SP1BRGH
;
1885 extern __at(0x019C) __sfr SPBRGH
;
1886 extern __at(0x019C) __sfr SPBRGH1
;
1888 //==============================================================================
1891 extern __at(0x019D) __sfr RC1STA
;
1905 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
1916 //==============================================================================
1919 //==============================================================================
1922 extern __at(0x019D) __sfr RCSTA
;
1936 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
1938 #define _RCSTA_RX9D 0x01
1939 #define _RCSTA_OERR 0x02
1940 #define _RCSTA_FERR 0x04
1941 #define _RCSTA_ADDEN 0x08
1942 #define _RCSTA_CREN 0x10
1943 #define _RCSTA_SREN 0x20
1944 #define _RCSTA_RX9 0x40
1945 #define _RCSTA_SPEN 0x80
1947 //==============================================================================
1950 //==============================================================================
1953 extern __at(0x019D) __sfr RCSTA1
;
1967 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
1969 #define _RCSTA1_RX9D 0x01
1970 #define _RCSTA1_OERR 0x02
1971 #define _RCSTA1_FERR 0x04
1972 #define _RCSTA1_ADDEN 0x08
1973 #define _RCSTA1_CREN 0x10
1974 #define _RCSTA1_SREN 0x20
1975 #define _RCSTA1_RX9 0x40
1976 #define _RCSTA1_SPEN 0x80
1978 //==============================================================================
1981 //==============================================================================
1984 extern __at(0x019E) __sfr TX1STA
;
1998 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
2009 //==============================================================================
2012 //==============================================================================
2015 extern __at(0x019E) __sfr TXSTA
;
2029 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
2031 #define _TXSTA_TX9D 0x01
2032 #define _TXSTA_TRMT 0x02
2033 #define _TXSTA_BRGH 0x04
2034 #define _TXSTA_SENDB 0x08
2035 #define _TXSTA_SYNC 0x10
2036 #define _TXSTA_TXEN 0x20
2037 #define _TXSTA_TX9 0x40
2038 #define _TXSTA_CSRC 0x80
2040 //==============================================================================
2043 //==============================================================================
2046 extern __at(0x019E) __sfr TXSTA1
;
2060 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
2062 #define _TXSTA1_TX9D 0x01
2063 #define _TXSTA1_TRMT 0x02
2064 #define _TXSTA1_BRGH 0x04
2065 #define _TXSTA1_SENDB 0x08
2066 #define _TXSTA1_SYNC 0x10
2067 #define _TXSTA1_TXEN 0x20
2068 #define _TXSTA1_TX9 0x40
2069 #define _TXSTA1_CSRC 0x80
2071 //==============================================================================
2074 //==============================================================================
2077 extern __at(0x019F) __sfr BAUD1CON
;
2088 unsigned ABDOVF
: 1;
2091 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
2098 #define _ABDOVF 0x80
2100 //==============================================================================
2103 //==============================================================================
2106 extern __at(0x019F) __sfr BAUDCON
;
2117 unsigned ABDOVF
: 1;
2120 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
2122 #define _BAUDCON_ABDEN 0x01
2123 #define _BAUDCON_WUE 0x02
2124 #define _BAUDCON_BRG16 0x08
2125 #define _BAUDCON_SCKP 0x10
2126 #define _BAUDCON_RCIDL 0x40
2127 #define _BAUDCON_ABDOVF 0x80
2129 //==============================================================================
2132 //==============================================================================
2135 extern __at(0x019F) __sfr BAUDCON1
;
2146 unsigned ABDOVF
: 1;
2149 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
2151 #define _BAUDCON1_ABDEN 0x01
2152 #define _BAUDCON1_WUE 0x02
2153 #define _BAUDCON1_BRG16 0x08
2154 #define _BAUDCON1_SCKP 0x10
2155 #define _BAUDCON1_RCIDL 0x40
2156 #define _BAUDCON1_ABDOVF 0x80
2158 //==============================================================================
2161 //==============================================================================
2164 extern __at(0x019F) __sfr BAUDCTL
;
2175 unsigned ABDOVF
: 1;
2178 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
2180 #define _BAUDCTL_ABDEN 0x01
2181 #define _BAUDCTL_WUE 0x02
2182 #define _BAUDCTL_BRG16 0x08
2183 #define _BAUDCTL_SCKP 0x10
2184 #define _BAUDCTL_RCIDL 0x40
2185 #define _BAUDCTL_ABDOVF 0x80
2187 //==============================================================================
2190 //==============================================================================
2193 extern __at(0x019F) __sfr BAUDCTL1
;
2204 unsigned ABDOVF
: 1;
2207 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
2209 #define _BAUDCTL1_ABDEN 0x01
2210 #define _BAUDCTL1_WUE 0x02
2211 #define _BAUDCTL1_BRG16 0x08
2212 #define _BAUDCTL1_SCKP 0x10
2213 #define _BAUDCTL1_RCIDL 0x40
2214 #define _BAUDCTL1_ABDOVF 0x80
2216 //==============================================================================
2219 //==============================================================================
2222 extern __at(0x020C) __sfr WPUA
;
2245 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
2254 //==============================================================================
2257 //==============================================================================
2260 extern __at(0x020E) __sfr WPUC
;
2283 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
2292 //==============================================================================
2295 //==============================================================================
2298 extern __at(0x0211) __sfr SSP1BUF
;
2304 unsigned SSP1BUF0
: 1;
2305 unsigned SSP1BUF1
: 1;
2306 unsigned SSP1BUF2
: 1;
2307 unsigned SSP1BUF3
: 1;
2308 unsigned SSP1BUF4
: 1;
2309 unsigned SSP1BUF5
: 1;
2310 unsigned SSP1BUF6
: 1;
2311 unsigned SSP1BUF7
: 1;
2327 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
2329 #define _SSP1BUF0 0x01
2331 #define _SSP1BUF1 0x02
2333 #define _SSP1BUF2 0x04
2335 #define _SSP1BUF3 0x08
2337 #define _SSP1BUF4 0x10
2339 #define _SSP1BUF5 0x20
2341 #define _SSP1BUF6 0x40
2343 #define _SSP1BUF7 0x80
2346 //==============================================================================
2349 //==============================================================================
2352 extern __at(0x0211) __sfr SSPBUF
;
2358 unsigned SSP1BUF0
: 1;
2359 unsigned SSP1BUF1
: 1;
2360 unsigned SSP1BUF2
: 1;
2361 unsigned SSP1BUF3
: 1;
2362 unsigned SSP1BUF4
: 1;
2363 unsigned SSP1BUF5
: 1;
2364 unsigned SSP1BUF6
: 1;
2365 unsigned SSP1BUF7
: 1;
2381 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
2383 #define _SSPBUF_SSP1BUF0 0x01
2384 #define _SSPBUF_BUF0 0x01
2385 #define _SSPBUF_SSP1BUF1 0x02
2386 #define _SSPBUF_BUF1 0x02
2387 #define _SSPBUF_SSP1BUF2 0x04
2388 #define _SSPBUF_BUF2 0x04
2389 #define _SSPBUF_SSP1BUF3 0x08
2390 #define _SSPBUF_BUF3 0x08
2391 #define _SSPBUF_SSP1BUF4 0x10
2392 #define _SSPBUF_BUF4 0x10
2393 #define _SSPBUF_SSP1BUF5 0x20
2394 #define _SSPBUF_BUF5 0x20
2395 #define _SSPBUF_SSP1BUF6 0x40
2396 #define _SSPBUF_BUF6 0x40
2397 #define _SSPBUF_SSP1BUF7 0x80
2398 #define _SSPBUF_BUF7 0x80
2400 //==============================================================================
2403 //==============================================================================
2406 extern __at(0x0212) __sfr SSP1ADD
;
2412 unsigned SSP1ADD0
: 1;
2413 unsigned SSP1ADD1
: 1;
2414 unsigned SSP1ADD2
: 1;
2415 unsigned SSP1ADD3
: 1;
2416 unsigned SSP1ADD4
: 1;
2417 unsigned SSP1ADD5
: 1;
2418 unsigned SSP1ADD6
: 1;
2419 unsigned SSP1ADD7
: 1;
2435 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
2437 #define _SSP1ADD0 0x01
2439 #define _SSP1ADD1 0x02
2441 #define _SSP1ADD2 0x04
2443 #define _SSP1ADD3 0x08
2445 #define _SSP1ADD4 0x10
2447 #define _SSP1ADD5 0x20
2449 #define _SSP1ADD6 0x40
2451 #define _SSP1ADD7 0x80
2454 //==============================================================================
2457 //==============================================================================
2460 extern __at(0x0212) __sfr SSPADD
;
2466 unsigned SSP1ADD0
: 1;
2467 unsigned SSP1ADD1
: 1;
2468 unsigned SSP1ADD2
: 1;
2469 unsigned SSP1ADD3
: 1;
2470 unsigned SSP1ADD4
: 1;
2471 unsigned SSP1ADD5
: 1;
2472 unsigned SSP1ADD6
: 1;
2473 unsigned SSP1ADD7
: 1;
2489 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
2491 #define _SSPADD_SSP1ADD0 0x01
2492 #define _SSPADD_ADD0 0x01
2493 #define _SSPADD_SSP1ADD1 0x02
2494 #define _SSPADD_ADD1 0x02
2495 #define _SSPADD_SSP1ADD2 0x04
2496 #define _SSPADD_ADD2 0x04
2497 #define _SSPADD_SSP1ADD3 0x08
2498 #define _SSPADD_ADD3 0x08
2499 #define _SSPADD_SSP1ADD4 0x10
2500 #define _SSPADD_ADD4 0x10
2501 #define _SSPADD_SSP1ADD5 0x20
2502 #define _SSPADD_ADD5 0x20
2503 #define _SSPADD_SSP1ADD6 0x40
2504 #define _SSPADD_ADD6 0x40
2505 #define _SSPADD_SSP1ADD7 0x80
2506 #define _SSPADD_ADD7 0x80
2508 //==============================================================================
2511 //==============================================================================
2514 extern __at(0x0213) __sfr SSP1MSK
;
2520 unsigned SSP1MSK0
: 1;
2521 unsigned SSP1MSK1
: 1;
2522 unsigned SSP1MSK2
: 1;
2523 unsigned SSP1MSK3
: 1;
2524 unsigned SSP1MSK4
: 1;
2525 unsigned SSP1MSK5
: 1;
2526 unsigned SSP1MSK6
: 1;
2527 unsigned SSP1MSK7
: 1;
2543 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
2545 #define _SSP1MSK0 0x01
2547 #define _SSP1MSK1 0x02
2549 #define _SSP1MSK2 0x04
2551 #define _SSP1MSK3 0x08
2553 #define _SSP1MSK4 0x10
2555 #define _SSP1MSK5 0x20
2557 #define _SSP1MSK6 0x40
2559 #define _SSP1MSK7 0x80
2562 //==============================================================================
2565 //==============================================================================
2568 extern __at(0x0213) __sfr SSPMSK
;
2574 unsigned SSP1MSK0
: 1;
2575 unsigned SSP1MSK1
: 1;
2576 unsigned SSP1MSK2
: 1;
2577 unsigned SSP1MSK3
: 1;
2578 unsigned SSP1MSK4
: 1;
2579 unsigned SSP1MSK5
: 1;
2580 unsigned SSP1MSK6
: 1;
2581 unsigned SSP1MSK7
: 1;
2597 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
2599 #define _SSPMSK_SSP1MSK0 0x01
2600 #define _SSPMSK_MSK0 0x01
2601 #define _SSPMSK_SSP1MSK1 0x02
2602 #define _SSPMSK_MSK1 0x02
2603 #define _SSPMSK_SSP1MSK2 0x04
2604 #define _SSPMSK_MSK2 0x04
2605 #define _SSPMSK_SSP1MSK3 0x08
2606 #define _SSPMSK_MSK3 0x08
2607 #define _SSPMSK_SSP1MSK4 0x10
2608 #define _SSPMSK_MSK4 0x10
2609 #define _SSPMSK_SSP1MSK5 0x20
2610 #define _SSPMSK_MSK5 0x20
2611 #define _SSPMSK_SSP1MSK6 0x40
2612 #define _SSPMSK_MSK6 0x40
2613 #define _SSPMSK_SSP1MSK7 0x80
2614 #define _SSPMSK_MSK7 0x80
2616 //==============================================================================
2619 //==============================================================================
2622 extern __at(0x0214) __sfr SSP1STAT
;
2628 unsigned R_NOT_W
: 1;
2631 unsigned D_NOT_A
: 1;
2636 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
2640 #define _R_NOT_W 0x04
2643 #define _D_NOT_A 0x20
2647 //==============================================================================
2650 //==============================================================================
2653 extern __at(0x0214) __sfr SSPSTAT
;
2659 unsigned R_NOT_W
: 1;
2662 unsigned D_NOT_A
: 1;
2667 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
2669 #define _SSPSTAT_BF 0x01
2670 #define _SSPSTAT_UA 0x02
2671 #define _SSPSTAT_R_NOT_W 0x04
2672 #define _SSPSTAT_S 0x08
2673 #define _SSPSTAT_P 0x10
2674 #define _SSPSTAT_D_NOT_A 0x20
2675 #define _SSPSTAT_CKE 0x40
2676 #define _SSPSTAT_SMP 0x80
2678 //==============================================================================
2681 //==============================================================================
2684 extern __at(0x0215) __sfr SSP1CON
;
2707 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
2718 //==============================================================================
2721 //==============================================================================
2724 extern __at(0x0215) __sfr SSP1CON1
;
2747 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
2749 #define _SSP1CON1_SSPM0 0x01
2750 #define _SSP1CON1_SSPM1 0x02
2751 #define _SSP1CON1_SSPM2 0x04
2752 #define _SSP1CON1_SSPM3 0x08
2753 #define _SSP1CON1_CKP 0x10
2754 #define _SSP1CON1_SSPEN 0x20
2755 #define _SSP1CON1_SSPOV 0x40
2756 #define _SSP1CON1_WCOL 0x80
2758 //==============================================================================
2761 //==============================================================================
2764 extern __at(0x0215) __sfr SSPCON
;
2787 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2789 #define _SSPCON_SSPM0 0x01
2790 #define _SSPCON_SSPM1 0x02
2791 #define _SSPCON_SSPM2 0x04
2792 #define _SSPCON_SSPM3 0x08
2793 #define _SSPCON_CKP 0x10
2794 #define _SSPCON_SSPEN 0x20
2795 #define _SSPCON_SSPOV 0x40
2796 #define _SSPCON_WCOL 0x80
2798 //==============================================================================
2801 //==============================================================================
2804 extern __at(0x0215) __sfr SSPCON1
;
2827 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2829 #define _SSPCON1_SSPM0 0x01
2830 #define _SSPCON1_SSPM1 0x02
2831 #define _SSPCON1_SSPM2 0x04
2832 #define _SSPCON1_SSPM3 0x08
2833 #define _SSPCON1_CKP 0x10
2834 #define _SSPCON1_SSPEN 0x20
2835 #define _SSPCON1_SSPOV 0x40
2836 #define _SSPCON1_WCOL 0x80
2838 //==============================================================================
2841 //==============================================================================
2844 extern __at(0x0216) __sfr SSP1CON2
;
2854 unsigned ACKSTAT
: 1;
2858 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
2866 #define _ACKSTAT 0x40
2869 //==============================================================================
2872 //==============================================================================
2875 extern __at(0x0216) __sfr SSPCON2
;
2885 unsigned ACKSTAT
: 1;
2889 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
2891 #define _SSPCON2_SEN 0x01
2892 #define _SSPCON2_RSEN 0x02
2893 #define _SSPCON2_PEN 0x04
2894 #define _SSPCON2_RCEN 0x08
2895 #define _SSPCON2_ACKEN 0x10
2896 #define _SSPCON2_ACKDT 0x20
2897 #define _SSPCON2_ACKSTAT 0x40
2898 #define _SSPCON2_GCEN 0x80
2900 //==============================================================================
2903 //==============================================================================
2906 extern __at(0x0217) __sfr SSP1CON3
;
2917 unsigned ACKTIM
: 1;
2920 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
2929 #define _ACKTIM 0x80
2931 //==============================================================================
2934 //==============================================================================
2937 extern __at(0x0217) __sfr SSPCON3
;
2948 unsigned ACKTIM
: 1;
2951 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
2953 #define _SSPCON3_DHEN 0x01
2954 #define _SSPCON3_AHEN 0x02
2955 #define _SSPCON3_SBCDE 0x04
2956 #define _SSPCON3_SDAHT 0x08
2957 #define _SSPCON3_BOEN 0x10
2958 #define _SSPCON3_SCIE 0x20
2959 #define _SSPCON3_PCIE 0x40
2960 #define _SSPCON3_ACKTIM 0x80
2962 //==============================================================================
2965 //==============================================================================
2968 extern __at(0x028C) __sfr ODCONA
;
2982 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
2990 //==============================================================================
2993 //==============================================================================
2996 extern __at(0x028E) __sfr ODCONC
;
3019 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
3028 //==============================================================================
3030 extern __at(0x0291) __sfr CCPR1
;
3031 extern __at(0x0291) __sfr CCPR1L
;
3032 extern __at(0x0292) __sfr CCPR1H
;
3034 //==============================================================================
3037 extern __at(0x0293) __sfr CCP1CON
;
3043 unsigned CCP1M0
: 1;
3044 unsigned CCP1M1
: 1;
3045 unsigned CCP1M2
: 1;
3046 unsigned CCP1M3
: 1;
3079 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
3081 #define _CCP1M0 0x01
3082 #define _CCP1M1 0x02
3083 #define _CCP1M2 0x04
3084 #define _CCP1M3 0x08
3090 //==============================================================================
3093 //==============================================================================
3096 extern __at(0x0293) __sfr ECCP1CON
;
3102 unsigned CCP1M0
: 1;
3103 unsigned CCP1M1
: 1;
3104 unsigned CCP1M2
: 1;
3105 unsigned CCP1M3
: 1;
3138 extern __at(0x0293) volatile __ECCP1CONbits_t ECCP1CONbits
;
3140 #define _ECCP1CON_CCP1M0 0x01
3141 #define _ECCP1CON_CCP1M1 0x02
3142 #define _ECCP1CON_CCP1M2 0x04
3143 #define _ECCP1CON_CCP1M3 0x08
3144 #define _ECCP1CON_DC1B0 0x10
3145 #define _ECCP1CON_CCP1Y 0x10
3146 #define _ECCP1CON_DC1B1 0x20
3147 #define _ECCP1CON_CCP1X 0x20
3149 //==============================================================================
3151 extern __at(0x0298) __sfr CCPR2
;
3152 extern __at(0x0298) __sfr CCPR2L
;
3153 extern __at(0x0299) __sfr CCPR2H
;
3155 //==============================================================================
3158 extern __at(0x029A) __sfr CCP2CON
;
3164 unsigned CCP2M0
: 1;
3165 unsigned CCP2M1
: 1;
3166 unsigned CCP2M2
: 1;
3167 unsigned CCP2M3
: 1;
3200 extern __at(0x029A) volatile __CCP2CONbits_t CCP2CONbits
;
3202 #define _CCP2M0 0x01
3203 #define _CCP2M1 0x02
3204 #define _CCP2M2 0x04
3205 #define _CCP2M3 0x08
3211 //==============================================================================
3214 //==============================================================================
3217 extern __at(0x029A) __sfr ECCP2CON
;
3223 unsigned CCP2M0
: 1;
3224 unsigned CCP2M1
: 1;
3225 unsigned CCP2M2
: 1;
3226 unsigned CCP2M3
: 1;
3259 extern __at(0x029A) volatile __ECCP2CONbits_t ECCP2CONbits
;
3261 #define _ECCP2CON_CCP2M0 0x01
3262 #define _ECCP2CON_CCP2M1 0x02
3263 #define _ECCP2CON_CCP2M2 0x04
3264 #define _ECCP2CON_CCP2M3 0x08
3265 #define _ECCP2CON_DC2B0 0x10
3266 #define _ECCP2CON_CCP2Y 0x10
3267 #define _ECCP2CON_DC2B1 0x20
3268 #define _ECCP2CON_CCP2X 0x20
3270 //==============================================================================
3273 //==============================================================================
3276 extern __at(0x029E) __sfr CCPTMRS
;
3282 unsigned C1TSEL0
: 1;
3283 unsigned C1TSEL1
: 1;
3284 unsigned C2TSEL0
: 1;
3285 unsigned C2TSEL1
: 1;
3286 unsigned P3TSEL0
: 1;
3287 unsigned P3TSEL1
: 1;
3288 unsigned P4TSEL0
: 1;
3289 unsigned P4TSEL1
: 1;
3294 unsigned C1TSEL
: 2;
3301 unsigned C2TSEL
: 2;
3308 unsigned P3TSEL
: 2;
3315 unsigned P4TSEL
: 2;
3319 extern __at(0x029E) volatile __CCPTMRSbits_t CCPTMRSbits
;
3321 #define _C1TSEL0 0x01
3322 #define _C1TSEL1 0x02
3323 #define _C2TSEL0 0x04
3324 #define _C2TSEL1 0x08
3325 #define _P3TSEL0 0x10
3326 #define _P3TSEL1 0x20
3327 #define _P4TSEL0 0x40
3328 #define _P4TSEL1 0x80
3330 //==============================================================================
3333 //==============================================================================
3336 extern __at(0x030C) __sfr SLRCONA
;
3350 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
3358 //==============================================================================
3361 //==============================================================================
3364 extern __at(0x030E) __sfr SLRCONC
;
3387 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
3396 //==============================================================================
3399 //==============================================================================
3402 extern __at(0x038C) __sfr INLVLA
;
3408 unsigned INLVLA0
: 1;
3409 unsigned INLVLA1
: 1;
3410 unsigned INLVLA2
: 1;
3411 unsigned INLVLA3
: 1;
3412 unsigned INLVLA4
: 1;
3413 unsigned INLVLA5
: 1;
3420 unsigned INLVLA
: 6;
3425 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
3427 #define _INLVLA0 0x01
3428 #define _INLVLA1 0x02
3429 #define _INLVLA2 0x04
3430 #define _INLVLA3 0x08
3431 #define _INLVLA4 0x10
3432 #define _INLVLA5 0x20
3434 //==============================================================================
3437 //==============================================================================
3440 extern __at(0x038E) __sfr INLVLC
;
3446 unsigned INLVLC0
: 1;
3447 unsigned INLVLC1
: 1;
3448 unsigned INLVLC2
: 1;
3449 unsigned INLVLC3
: 1;
3450 unsigned INLVLC4
: 1;
3451 unsigned INLVLC5
: 1;
3458 unsigned INLVLC
: 6;
3463 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
3465 #define _INLVLC0 0x01
3466 #define _INLVLC1 0x02
3467 #define _INLVLC2 0x04
3468 #define _INLVLC3 0x08
3469 #define _INLVLC4 0x10
3470 #define _INLVLC5 0x20
3472 //==============================================================================
3475 //==============================================================================
3478 extern __at(0x0391) __sfr IOCAP
;
3484 unsigned IOCAP0
: 1;
3485 unsigned IOCAP1
: 1;
3486 unsigned IOCAP2
: 1;
3487 unsigned IOCAP3
: 1;
3488 unsigned IOCAP4
: 1;
3489 unsigned IOCAP5
: 1;
3501 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
3503 #define _IOCAP0 0x01
3504 #define _IOCAP1 0x02
3505 #define _IOCAP2 0x04
3506 #define _IOCAP3 0x08
3507 #define _IOCAP4 0x10
3508 #define _IOCAP5 0x20
3510 //==============================================================================
3513 //==============================================================================
3516 extern __at(0x0392) __sfr IOCAN
;
3522 unsigned IOCAN0
: 1;
3523 unsigned IOCAN1
: 1;
3524 unsigned IOCAN2
: 1;
3525 unsigned IOCAN3
: 1;
3526 unsigned IOCAN4
: 1;
3527 unsigned IOCAN5
: 1;
3539 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
3541 #define _IOCAN0 0x01
3542 #define _IOCAN1 0x02
3543 #define _IOCAN2 0x04
3544 #define _IOCAN3 0x08
3545 #define _IOCAN4 0x10
3546 #define _IOCAN5 0x20
3548 //==============================================================================
3551 //==============================================================================
3554 extern __at(0x0393) __sfr IOCAF
;
3560 unsigned IOCAF0
: 1;
3561 unsigned IOCAF1
: 1;
3562 unsigned IOCAF2
: 1;
3563 unsigned IOCAF3
: 1;
3564 unsigned IOCAF4
: 1;
3565 unsigned IOCAF5
: 1;
3577 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
3579 #define _IOCAF0 0x01
3580 #define _IOCAF1 0x02
3581 #define _IOCAF2 0x04
3582 #define _IOCAF3 0x08
3583 #define _IOCAF4 0x10
3584 #define _IOCAF5 0x20
3586 //==============================================================================
3589 //==============================================================================
3592 extern __at(0x0397) __sfr IOCCP
;
3598 unsigned IOCCP0
: 1;
3599 unsigned IOCCP1
: 1;
3600 unsigned IOCCP2
: 1;
3601 unsigned IOCCP3
: 1;
3602 unsigned IOCCP4
: 1;
3603 unsigned IOCCP5
: 1;
3615 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
3617 #define _IOCCP0 0x01
3618 #define _IOCCP1 0x02
3619 #define _IOCCP2 0x04
3620 #define _IOCCP3 0x08
3621 #define _IOCCP4 0x10
3622 #define _IOCCP5 0x20
3624 //==============================================================================
3627 //==============================================================================
3630 extern __at(0x0398) __sfr IOCCN
;
3636 unsigned IOCCN0
: 1;
3637 unsigned IOCCN1
: 1;
3638 unsigned IOCCN2
: 1;
3639 unsigned IOCCN3
: 1;
3640 unsigned IOCCN4
: 1;
3641 unsigned IOCCN5
: 1;
3653 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
3655 #define _IOCCN0 0x01
3656 #define _IOCCN1 0x02
3657 #define _IOCCN2 0x04
3658 #define _IOCCN3 0x08
3659 #define _IOCCN4 0x10
3660 #define _IOCCN5 0x20
3662 //==============================================================================
3665 //==============================================================================
3668 extern __at(0x0399) __sfr IOCCF
;
3674 unsigned IOCCF0
: 1;
3675 unsigned IOCCF1
: 1;
3676 unsigned IOCCF2
: 1;
3677 unsigned IOCCF3
: 1;
3678 unsigned IOCCF4
: 1;
3679 unsigned IOCCF5
: 1;
3691 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
3693 #define _IOCCF0 0x01
3694 #define _IOCCF1 0x02
3695 #define _IOCCF2 0x04
3696 #define _IOCCF3 0x08
3697 #define _IOCCF4 0x10
3698 #define _IOCCF5 0x20
3700 //==============================================================================
3702 extern __at(0x0415) __sfr TMR4
;
3703 extern __at(0x0416) __sfr PR4
;
3705 //==============================================================================
3708 extern __at(0x0417) __sfr T4CON
;
3714 unsigned T4CKPS0
: 1;
3715 unsigned T4CKPS1
: 1;
3716 unsigned TMR4ON
: 1;
3717 unsigned T4OUTPS0
: 1;
3718 unsigned T4OUTPS1
: 1;
3719 unsigned T4OUTPS2
: 1;
3720 unsigned T4OUTPS3
: 1;
3726 unsigned T4CKPS
: 2;
3733 unsigned T4OUTPS
: 4;
3738 extern __at(0x0417) volatile __T4CONbits_t T4CONbits
;
3740 #define _T4CKPS0 0x01
3741 #define _T4CKPS1 0x02
3742 #define _TMR4ON 0x04
3743 #define _T4OUTPS0 0x08
3744 #define _T4OUTPS1 0x10
3745 #define _T4OUTPS2 0x20
3746 #define _T4OUTPS3 0x40
3748 //==============================================================================
3750 extern __at(0x041C) __sfr TMR6
;
3751 extern __at(0x041D) __sfr PR6
;
3753 //==============================================================================
3756 extern __at(0x041E) __sfr T6CON
;
3762 unsigned T6CKPS0
: 1;
3763 unsigned T6CKPS1
: 1;
3764 unsigned TMR6ON
: 1;
3765 unsigned T6OUTPS0
: 1;
3766 unsigned T6OUTPS1
: 1;
3767 unsigned T6OUTPS2
: 1;
3768 unsigned T6OUTPS3
: 1;
3774 unsigned T6CKPS
: 2;
3781 unsigned T6OUTPS
: 4;
3786 extern __at(0x041E) volatile __T6CONbits_t T6CONbits
;
3788 #define _T6CKPS0 0x01
3789 #define _T6CKPS1 0x02
3790 #define _TMR6ON 0x04
3791 #define _T6OUTPS0 0x08
3792 #define _T6OUTPS1 0x10
3793 #define _T6OUTPS2 0x20
3794 #define _T6OUTPS3 0x40
3796 //==============================================================================
3799 //==============================================================================
3802 extern __at(0x0511) __sfr OPA1CON
;
3808 unsigned OPA1PCH0
: 1;
3809 unsigned OPA1PCH1
: 1;
3812 unsigned OPA1UG
: 1;
3814 unsigned OPA1SP
: 1;
3815 unsigned OPA1EN
: 1;
3820 unsigned OPA1PCH
: 2;
3825 extern __at(0x0511) volatile __OPA1CONbits_t OPA1CONbits
;
3827 #define _OPA1PCH0 0x01
3828 #define _OPA1PCH1 0x02
3829 #define _OPA1UG 0x10
3830 #define _OPA1SP 0x40
3831 #define _OPA1EN 0x80
3833 //==============================================================================
3836 //==============================================================================
3839 extern __at(0x0515) __sfr OPA2CON
;
3845 unsigned OPA2PCH0
: 1;
3846 unsigned OPA2PCH1
: 1;
3849 unsigned OPA2UG
: 1;
3851 unsigned OPA2SP
: 1;
3852 unsigned OPA2EN
: 1;
3857 unsigned OPA2PCH
: 2;
3862 extern __at(0x0515) volatile __OPA2CONbits_t OPA2CONbits
;
3864 #define _OPA2PCH0 0x01
3865 #define _OPA2PCH1 0x02
3866 #define _OPA2UG 0x10
3867 #define _OPA2SP 0x40
3868 #define _OPA2EN 0x80
3870 //==============================================================================
3873 //==============================================================================
3876 extern __at(0x0617) __sfr PWM3DCL
;
3888 unsigned PWM3DCL0
: 1;
3889 unsigned PWM3DCL1
: 1;
3895 unsigned PWM3DCL
: 2;
3899 extern __at(0x0617) volatile __PWM3DCLbits_t PWM3DCLbits
;
3901 #define _PWM3DCL0 0x40
3902 #define _PWM3DCL1 0x80
3904 //==============================================================================
3907 //==============================================================================
3910 extern __at(0x0618) __sfr PWM3DCH
;
3914 unsigned PWM3DCH0
: 1;
3915 unsigned PWM3DCH1
: 1;
3916 unsigned PWM3DCH2
: 1;
3917 unsigned PWM3DCH3
: 1;
3918 unsigned PWM3DCH4
: 1;
3919 unsigned PWM3DCH5
: 1;
3920 unsigned PWM3DCH6
: 1;
3921 unsigned PWM3DCH7
: 1;
3924 extern __at(0x0618) volatile __PWM3DCHbits_t PWM3DCHbits
;
3926 #define _PWM3DCH0 0x01
3927 #define _PWM3DCH1 0x02
3928 #define _PWM3DCH2 0x04
3929 #define _PWM3DCH3 0x08
3930 #define _PWM3DCH4 0x10
3931 #define _PWM3DCH5 0x20
3932 #define _PWM3DCH6 0x40
3933 #define _PWM3DCH7 0x80
3935 //==============================================================================
3938 //==============================================================================
3941 extern __at(0x0619) __sfr PWM3CON
;
3949 unsigned PWM3POL
: 1;
3950 unsigned PWM3OUT
: 1;
3952 unsigned PWM3EN
: 1;
3955 extern __at(0x0619) volatile __PWM3CONbits_t PWM3CONbits
;
3957 #define _PWM3POL 0x10
3958 #define _PWM3OUT 0x20
3959 #define _PWM3EN 0x80
3961 //==============================================================================
3964 //==============================================================================
3967 extern __at(0x0619) __sfr PWM3CON0
;
3975 unsigned PWM3POL
: 1;
3976 unsigned PWM3OUT
: 1;
3978 unsigned PWM3EN
: 1;
3981 extern __at(0x0619) volatile __PWM3CON0bits_t PWM3CON0bits
;
3983 #define _PWM3CON0_PWM3POL 0x10
3984 #define _PWM3CON0_PWM3OUT 0x20
3985 #define _PWM3CON0_PWM3EN 0x80
3987 //==============================================================================
3990 //==============================================================================
3993 extern __at(0x061A) __sfr PWM4DCL
;
4005 unsigned PWM4DCL0
: 1;
4006 unsigned PWM4DCL1
: 1;
4012 unsigned PWM4DCL
: 2;
4016 extern __at(0x061A) volatile __PWM4DCLbits_t PWM4DCLbits
;
4018 #define _PWM4DCL0 0x40
4019 #define _PWM4DCL1 0x80
4021 //==============================================================================
4024 //==============================================================================
4027 extern __at(0x061B) __sfr PWM4DCH
;
4031 unsigned PWM4DCH0
: 1;
4032 unsigned PWM4DCH1
: 1;
4033 unsigned PWM4DCH2
: 1;
4034 unsigned PWM4DCH3
: 1;
4035 unsigned PWM4DCH4
: 1;
4036 unsigned PWM4DCH5
: 1;
4037 unsigned PWM4DCH6
: 1;
4038 unsigned PWM4DCH7
: 1;
4041 extern __at(0x061B) volatile __PWM4DCHbits_t PWM4DCHbits
;
4043 #define _PWM4DCH0 0x01
4044 #define _PWM4DCH1 0x02
4045 #define _PWM4DCH2 0x04
4046 #define _PWM4DCH3 0x08
4047 #define _PWM4DCH4 0x10
4048 #define _PWM4DCH5 0x20
4049 #define _PWM4DCH6 0x40
4050 #define _PWM4DCH7 0x80
4052 //==============================================================================
4055 //==============================================================================
4058 extern __at(0x061C) __sfr PWM4CON
;
4066 unsigned PWM4POL
: 1;
4067 unsigned PWM4OUT
: 1;
4069 unsigned PWM4EN
: 1;
4072 extern __at(0x061C) volatile __PWM4CONbits_t PWM4CONbits
;
4074 #define _PWM4POL 0x10
4075 #define _PWM4OUT 0x20
4076 #define _PWM4EN 0x80
4078 //==============================================================================
4081 //==============================================================================
4084 extern __at(0x061C) __sfr PWM4CON0
;
4092 unsigned PWM4POL
: 1;
4093 unsigned PWM4OUT
: 1;
4095 unsigned PWM4EN
: 1;
4098 extern __at(0x061C) volatile __PWM4CON0bits_t PWM4CON0bits
;
4100 #define _PWM4CON0_PWM4POL 0x10
4101 #define _PWM4CON0_PWM4OUT 0x20
4102 #define _PWM4CON0_PWM4EN 0x80
4104 //==============================================================================
4107 //==============================================================================
4110 extern __at(0x0691) __sfr COG1PHR
;
4116 unsigned G1PHR0
: 1;
4117 unsigned G1PHR1
: 1;
4118 unsigned G1PHR2
: 1;
4119 unsigned G1PHR3
: 1;
4120 unsigned G1PHR4
: 1;
4121 unsigned G1PHR5
: 1;
4133 extern __at(0x0691) volatile __COG1PHRbits_t COG1PHRbits
;
4135 #define _G1PHR0 0x01
4136 #define _G1PHR1 0x02
4137 #define _G1PHR2 0x04
4138 #define _G1PHR3 0x08
4139 #define _G1PHR4 0x10
4140 #define _G1PHR5 0x20
4142 //==============================================================================
4145 //==============================================================================
4148 extern __at(0x0692) __sfr COG1PHF
;
4154 unsigned G1PHF0
: 1;
4155 unsigned G1PHF1
: 1;
4156 unsigned G1PHF2
: 1;
4157 unsigned G1PHF3
: 1;
4158 unsigned G1PHF4
: 1;
4159 unsigned G1PHF5
: 1;
4171 extern __at(0x0692) volatile __COG1PHFbits_t COG1PHFbits
;
4173 #define _G1PHF0 0x01
4174 #define _G1PHF1 0x02
4175 #define _G1PHF2 0x04
4176 #define _G1PHF3 0x08
4177 #define _G1PHF4 0x10
4178 #define _G1PHF5 0x20
4180 //==============================================================================
4183 //==============================================================================
4186 extern __at(0x0693) __sfr COG1BLKR
;
4192 unsigned G1BLKR0
: 1;
4193 unsigned G1BLKR1
: 1;
4194 unsigned G1BLKR2
: 1;
4195 unsigned G1BLKR3
: 1;
4196 unsigned G1BLKR4
: 1;
4197 unsigned G1BLKR5
: 1;
4204 unsigned G1BLKR
: 6;
4209 extern __at(0x0693) volatile __COG1BLKRbits_t COG1BLKRbits
;
4211 #define _G1BLKR0 0x01
4212 #define _G1BLKR1 0x02
4213 #define _G1BLKR2 0x04
4214 #define _G1BLKR3 0x08
4215 #define _G1BLKR4 0x10
4216 #define _G1BLKR5 0x20
4218 //==============================================================================
4221 //==============================================================================
4224 extern __at(0x0694) __sfr COG1BLKF
;
4230 unsigned G1BLKF0
: 1;
4231 unsigned G1BLKF1
: 1;
4232 unsigned G1BLKF2
: 1;
4233 unsigned G1BLKF3
: 1;
4234 unsigned G1BLKF4
: 1;
4235 unsigned G1BLKF5
: 1;
4242 unsigned G1BLKF
: 6;
4247 extern __at(0x0694) volatile __COG1BLKFbits_t COG1BLKFbits
;
4249 #define _G1BLKF0 0x01
4250 #define _G1BLKF1 0x02
4251 #define _G1BLKF2 0x04
4252 #define _G1BLKF3 0x08
4253 #define _G1BLKF4 0x10
4254 #define _G1BLKF5 0x20
4256 //==============================================================================
4259 //==============================================================================
4262 extern __at(0x0695) __sfr COG1DBR
;
4268 unsigned G1DBR0
: 1;
4269 unsigned G1DBR1
: 1;
4270 unsigned G1DBR2
: 1;
4271 unsigned G1DBR3
: 1;
4272 unsigned G1DBR4
: 1;
4273 unsigned G1DBR5
: 1;
4285 extern __at(0x0695) volatile __COG1DBRbits_t COG1DBRbits
;
4287 #define _G1DBR0 0x01
4288 #define _G1DBR1 0x02
4289 #define _G1DBR2 0x04
4290 #define _G1DBR3 0x08
4291 #define _G1DBR4 0x10
4292 #define _G1DBR5 0x20
4294 //==============================================================================
4297 //==============================================================================
4300 extern __at(0x0696) __sfr COG1DBF
;
4306 unsigned G1DBF0
: 1;
4307 unsigned G1DBF1
: 1;
4308 unsigned G1DBF2
: 1;
4309 unsigned G1DBF3
: 1;
4310 unsigned G1DBF4
: 1;
4311 unsigned G1DBF5
: 1;
4323 extern __at(0x0696) volatile __COG1DBFbits_t COG1DBFbits
;
4325 #define _G1DBF0 0x01
4326 #define _G1DBF1 0x02
4327 #define _G1DBF2 0x04
4328 #define _G1DBF3 0x08
4329 #define _G1DBF4 0x10
4330 #define _G1DBF5 0x20
4332 //==============================================================================
4335 //==============================================================================
4338 extern __at(0x0697) __sfr COG1CON0
;
4368 extern __at(0x0697) volatile __COG1CON0bits_t COG1CON0bits
;
4378 //==============================================================================
4381 //==============================================================================
4384 extern __at(0x0698) __sfr COG1CON1
;
4388 unsigned G1POLA
: 1;
4389 unsigned G1POLB
: 1;
4390 unsigned G1POLC
: 1;
4391 unsigned G1POLD
: 1;
4394 unsigned G1FDBS
: 1;
4395 unsigned G1RDBS
: 1;
4398 extern __at(0x0698) volatile __COG1CON1bits_t COG1CON1bits
;
4400 #define _G1POLA 0x01
4401 #define _G1POLB 0x02
4402 #define _G1POLC 0x04
4403 #define _G1POLD 0x08
4404 #define _G1FDBS 0x40
4405 #define _G1RDBS 0x80
4407 //==============================================================================
4410 //==============================================================================
4413 extern __at(0x0699) __sfr COG1RIS
;
4419 unsigned G1RIS0
: 1;
4420 unsigned G1RIS1
: 1;
4421 unsigned G1RIS2
: 1;
4422 unsigned G1RIS3
: 1;
4423 unsigned G1RIS4
: 1;
4424 unsigned G1RIS5
: 1;
4425 unsigned G1RIS6
: 1;
4436 extern __at(0x0699) volatile __COG1RISbits_t COG1RISbits
;
4438 #define _G1RIS0 0x01
4439 #define _G1RIS1 0x02
4440 #define _G1RIS2 0x04
4441 #define _G1RIS3 0x08
4442 #define _G1RIS4 0x10
4443 #define _G1RIS5 0x20
4444 #define _G1RIS6 0x40
4446 //==============================================================================
4449 //==============================================================================
4452 extern __at(0x069A) __sfr COG1RSIM
;
4458 unsigned G1RSIM0
: 1;
4459 unsigned G1RSIM1
: 1;
4460 unsigned G1RSIM2
: 1;
4461 unsigned G1RSIM3
: 1;
4462 unsigned G1RSIM4
: 1;
4463 unsigned G1RSIM5
: 1;
4464 unsigned G1RSIM6
: 1;
4470 unsigned G1RSIM
: 7;
4475 extern __at(0x069A) volatile __COG1RSIMbits_t COG1RSIMbits
;
4477 #define _G1RSIM0 0x01
4478 #define _G1RSIM1 0x02
4479 #define _G1RSIM2 0x04
4480 #define _G1RSIM3 0x08
4481 #define _G1RSIM4 0x10
4482 #define _G1RSIM5 0x20
4483 #define _G1RSIM6 0x40
4485 //==============================================================================
4488 //==============================================================================
4491 extern __at(0x069B) __sfr COG1FIS
;
4497 unsigned G1FIS0
: 1;
4498 unsigned G1FIS1
: 1;
4499 unsigned G1FIS2
: 1;
4500 unsigned G1FIS3
: 1;
4501 unsigned G1FIS4
: 1;
4502 unsigned G1FIS5
: 1;
4503 unsigned G1FIS6
: 1;
4514 extern __at(0x069B) volatile __COG1FISbits_t COG1FISbits
;
4516 #define _G1FIS0 0x01
4517 #define _G1FIS1 0x02
4518 #define _G1FIS2 0x04
4519 #define _G1FIS3 0x08
4520 #define _G1FIS4 0x10
4521 #define _G1FIS5 0x20
4522 #define _G1FIS6 0x40
4524 //==============================================================================
4527 //==============================================================================
4530 extern __at(0x069C) __sfr COG1FSIM
;
4536 unsigned G1FSIM0
: 1;
4537 unsigned G1FSIM1
: 1;
4538 unsigned G1FSIM2
: 1;
4539 unsigned G1FSIM3
: 1;
4540 unsigned G1FSIM4
: 1;
4541 unsigned G1FSIM5
: 1;
4542 unsigned G1FSIM6
: 1;
4548 unsigned G1FSIM
: 7;
4553 extern __at(0x069C) volatile __COG1FSIMbits_t COG1FSIMbits
;
4555 #define _G1FSIM0 0x01
4556 #define _G1FSIM1 0x02
4557 #define _G1FSIM2 0x04
4558 #define _G1FSIM3 0x08
4559 #define _G1FSIM4 0x10
4560 #define _G1FSIM5 0x20
4561 #define _G1FSIM6 0x40
4563 //==============================================================================
4566 //==============================================================================
4569 extern __at(0x069D) __sfr COG1ASD0
;
4577 unsigned G1ASDAC0
: 1;
4578 unsigned G1ASDAC1
: 1;
4579 unsigned G1ASDBD0
: 1;
4580 unsigned G1ASDBD1
: 1;
4581 unsigned G1ARSEN
: 1;
4588 unsigned G1ASDAC
: 2;
4595 unsigned G1ASDBD
: 2;
4600 extern __at(0x069D) volatile __COG1ASD0bits_t COG1ASD0bits
;
4602 #define _G1ASDAC0 0x04
4603 #define _G1ASDAC1 0x08
4604 #define _G1ASDBD0 0x10
4605 #define _G1ASDBD1 0x20
4606 #define _G1ARSEN 0x40
4609 //==============================================================================
4612 //==============================================================================
4615 extern __at(0x069E) __sfr COG1ASD1
;
4619 unsigned G1AS0E
: 1;
4620 unsigned G1AS1E
: 1;
4621 unsigned G1AS2E
: 1;
4622 unsigned G1AS3E
: 1;
4629 extern __at(0x069E) volatile __COG1ASD1bits_t COG1ASD1bits
;
4631 #define _G1AS0E 0x01
4632 #define _G1AS1E 0x02
4633 #define _G1AS2E 0x04
4634 #define _G1AS3E 0x08
4636 //==============================================================================
4639 //==============================================================================
4642 extern __at(0x069F) __sfr COG1STR
;
4646 unsigned G1STRA
: 1;
4647 unsigned G1STRB
: 1;
4648 unsigned G1STRC
: 1;
4649 unsigned G1STRD
: 1;
4650 unsigned G1SDATA
: 1;
4651 unsigned G1SDATB
: 1;
4652 unsigned G1SDATC
: 1;
4653 unsigned G1SDATD
: 1;
4656 extern __at(0x069F) volatile __COG1STRbits_t COG1STRbits
;
4658 #define _G1STRA 0x01
4659 #define _G1STRB 0x02
4660 #define _G1STRC 0x04
4661 #define _G1STRD 0x08
4662 #define _G1SDATA 0x10
4663 #define _G1SDATB 0x20
4664 #define _G1SDATC 0x40
4665 #define _G1SDATD 0x80
4667 //==============================================================================
4670 //==============================================================================
4673 extern __at(0x0E0F) __sfr PPSLOCK
;
4677 unsigned PPSLOCKED
: 1;
4687 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
4689 #define _PPSLOCKED 0x01
4691 //==============================================================================
4693 extern __at(0x0E10) __sfr INTPPS
;
4694 extern __at(0x0E11) __sfr T0CKIPPS
;
4695 extern __at(0x0E12) __sfr T1CKIPPS
;
4696 extern __at(0x0E13) __sfr T1GPPS
;
4697 extern __at(0x0E14) __sfr CCP1PPS
;
4698 extern __at(0x0E15) __sfr CCP2PPS
;
4699 extern __at(0x0E17) __sfr COGINPPS
;
4700 extern __at(0x0E20) __sfr SSPCLKPPS
;
4701 extern __at(0x0E21) __sfr SSPDATPPS
;
4702 extern __at(0x0E22) __sfr SSPSSPPS
;
4703 extern __at(0x0E24) __sfr RXPPS
;
4704 extern __at(0x0E25) __sfr CKPPS
;
4705 extern __at(0x0E28) __sfr CLCIN0PPS
;
4706 extern __at(0x0E29) __sfr CLCIN1PPS
;
4707 extern __at(0x0E2A) __sfr CLCIN2PPS
;
4708 extern __at(0x0E2B) __sfr CLCIN3PPS
;
4709 extern __at(0x0E90) __sfr RA0PPS
;
4710 extern __at(0x0E91) __sfr RA1PPS
;
4711 extern __at(0x0E92) __sfr RA2PPS
;
4712 extern __at(0x0E94) __sfr RA4PPS
;
4713 extern __at(0x0E95) __sfr RA5PPS
;
4714 extern __at(0x0EA0) __sfr RC0PPS
;
4715 extern __at(0x0EA1) __sfr RC1PPS
;
4716 extern __at(0x0EA2) __sfr RC2PPS
;
4717 extern __at(0x0EA3) __sfr RC3PPS
;
4718 extern __at(0x0EA4) __sfr RC4PPS
;
4719 extern __at(0x0EA5) __sfr RC5PPS
;
4721 //==============================================================================
4724 extern __at(0x0F0F) __sfr CLCDATA
;
4728 unsigned MCLC1OUT
: 1;
4729 unsigned MCLC2OUT
: 1;
4730 unsigned MCLC3OUT
: 1;
4738 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
4740 #define _MCLC1OUT 0x01
4741 #define _MCLC2OUT 0x02
4742 #define _MCLC3OUT 0x04
4744 //==============================================================================
4747 //==============================================================================
4750 extern __at(0x0F10) __sfr CLC1CON
;
4756 unsigned LC1MODE0
: 1;
4757 unsigned LC1MODE1
: 1;
4758 unsigned LC1MODE2
: 1;
4759 unsigned LC1INTN
: 1;
4760 unsigned LC1INTP
: 1;
4761 unsigned LC1OUT
: 1;
4780 unsigned LC1MODE
: 3;
4791 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
4793 #define _LC1MODE0 0x01
4795 #define _LC1MODE1 0x02
4797 #define _LC1MODE2 0x04
4799 #define _LC1INTN 0x08
4801 #define _LC1INTP 0x10
4803 #define _LC1OUT 0x20
4808 //==============================================================================
4811 //==============================================================================
4814 extern __at(0x0F11) __sfr CLC1POL
;
4820 unsigned LC1G1POL
: 1;
4821 unsigned LC1G2POL
: 1;
4822 unsigned LC1G3POL
: 1;
4823 unsigned LC1G4POL
: 1;
4827 unsigned LC1POL
: 1;
4843 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
4845 #define _LC1G1POL 0x01
4847 #define _LC1G2POL 0x02
4849 #define _LC1G3POL 0x04
4851 #define _LC1G4POL 0x08
4853 #define _LC1POL 0x80
4856 //==============================================================================
4859 //==============================================================================
4862 extern __at(0x0F12) __sfr CLC1SEL0
;
4868 unsigned LC1D1S0
: 1;
4869 unsigned LC1D1S1
: 1;
4870 unsigned LC1D1S2
: 1;
4871 unsigned LC1D1S3
: 1;
4872 unsigned LC1D1S4
: 1;
4898 unsigned LC1D1S
: 5;
4903 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
4905 #define _LC1D1S0 0x01
4907 #define _LC1D1S1 0x02
4909 #define _LC1D1S2 0x04
4911 #define _LC1D1S3 0x08
4913 #define _LC1D1S4 0x10
4916 //==============================================================================
4919 //==============================================================================
4922 extern __at(0x0F13) __sfr CLC1SEL1
;
4928 unsigned LC1D2S0
: 1;
4929 unsigned LC1D2S1
: 1;
4930 unsigned LC1D2S2
: 1;
4931 unsigned LC1D2S3
: 1;
4932 unsigned LC1D2S4
: 1;
4952 unsigned LC1D2S
: 5;
4963 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
4965 #define _LC1D2S0 0x01
4967 #define _LC1D2S1 0x02
4969 #define _LC1D2S2 0x04
4971 #define _LC1D2S3 0x08
4973 #define _LC1D2S4 0x10
4976 //==============================================================================
4979 //==============================================================================
4982 extern __at(0x0F14) __sfr CLC1SEL2
;
4988 unsigned LC1D3S0
: 1;
4989 unsigned LC1D3S1
: 1;
4990 unsigned LC1D3S2
: 1;
4991 unsigned LC1D3S3
: 1;
4992 unsigned LC1D3S4
: 1;
5012 unsigned LC1D3S
: 5;
5023 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
5025 #define _LC1D3S0 0x01
5027 #define _LC1D3S1 0x02
5029 #define _LC1D3S2 0x04
5031 #define _LC1D3S3 0x08
5033 #define _LC1D3S4 0x10
5036 //==============================================================================
5039 //==============================================================================
5042 extern __at(0x0F15) __sfr CLC1SEL3
;
5048 unsigned LC1D4S0
: 1;
5049 unsigned LC1D4S1
: 1;
5050 unsigned LC1D4S2
: 1;
5051 unsigned LC1D4S3
: 1;
5052 unsigned LC1D4S4
: 1;
5078 unsigned LC1D4S
: 5;
5083 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
5085 #define _LC1D4S0 0x01
5087 #define _LC1D4S1 0x02
5089 #define _LC1D4S2 0x04
5091 #define _LC1D4S3 0x08
5093 #define _LC1D4S4 0x10
5096 //==============================================================================
5099 //==============================================================================
5102 extern __at(0x0F16) __sfr CLC1GLS0
;
5108 unsigned LC1G1D1N
: 1;
5109 unsigned LC1G1D1T
: 1;
5110 unsigned LC1G1D2N
: 1;
5111 unsigned LC1G1D2T
: 1;
5112 unsigned LC1G1D3N
: 1;
5113 unsigned LC1G1D3T
: 1;
5114 unsigned LC1G1D4N
: 1;
5115 unsigned LC1G1D4T
: 1;
5131 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
5133 #define _LC1G1D1N 0x01
5135 #define _LC1G1D1T 0x02
5137 #define _LC1G1D2N 0x04
5139 #define _LC1G1D2T 0x08
5141 #define _LC1G1D3N 0x10
5143 #define _LC1G1D3T 0x20
5145 #define _LC1G1D4N 0x40
5147 #define _LC1G1D4T 0x80
5150 //==============================================================================
5153 //==============================================================================
5156 extern __at(0x0F17) __sfr CLC1GLS1
;
5162 unsigned LC1G2D1N
: 1;
5163 unsigned LC1G2D1T
: 1;
5164 unsigned LC1G2D2N
: 1;
5165 unsigned LC1G2D2T
: 1;
5166 unsigned LC1G2D3N
: 1;
5167 unsigned LC1G2D3T
: 1;
5168 unsigned LC1G2D4N
: 1;
5169 unsigned LC1G2D4T
: 1;
5185 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
5187 #define _CLC1GLS1_LC1G2D1N 0x01
5188 #define _CLC1GLS1_D1N 0x01
5189 #define _CLC1GLS1_LC1G2D1T 0x02
5190 #define _CLC1GLS1_D1T 0x02
5191 #define _CLC1GLS1_LC1G2D2N 0x04
5192 #define _CLC1GLS1_D2N 0x04
5193 #define _CLC1GLS1_LC1G2D2T 0x08
5194 #define _CLC1GLS1_D2T 0x08
5195 #define _CLC1GLS1_LC1G2D3N 0x10
5196 #define _CLC1GLS1_D3N 0x10
5197 #define _CLC1GLS1_LC1G2D3T 0x20
5198 #define _CLC1GLS1_D3T 0x20
5199 #define _CLC1GLS1_LC1G2D4N 0x40
5200 #define _CLC1GLS1_D4N 0x40
5201 #define _CLC1GLS1_LC1G2D4T 0x80
5202 #define _CLC1GLS1_D4T 0x80
5204 //==============================================================================
5207 //==============================================================================
5210 extern __at(0x0F18) __sfr CLC1GLS2
;
5216 unsigned LC1G3D1N
: 1;
5217 unsigned LC1G3D1T
: 1;
5218 unsigned LC1G3D2N
: 1;
5219 unsigned LC1G3D2T
: 1;
5220 unsigned LC1G3D3N
: 1;
5221 unsigned LC1G3D3T
: 1;
5222 unsigned LC1G3D4N
: 1;
5223 unsigned LC1G3D4T
: 1;
5239 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
5241 #define _CLC1GLS2_LC1G3D1N 0x01
5242 #define _CLC1GLS2_D1N 0x01
5243 #define _CLC1GLS2_LC1G3D1T 0x02
5244 #define _CLC1GLS2_D1T 0x02
5245 #define _CLC1GLS2_LC1G3D2N 0x04
5246 #define _CLC1GLS2_D2N 0x04
5247 #define _CLC1GLS2_LC1G3D2T 0x08
5248 #define _CLC1GLS2_D2T 0x08
5249 #define _CLC1GLS2_LC1G3D3N 0x10
5250 #define _CLC1GLS2_D3N 0x10
5251 #define _CLC1GLS2_LC1G3D3T 0x20
5252 #define _CLC1GLS2_D3T 0x20
5253 #define _CLC1GLS2_LC1G3D4N 0x40
5254 #define _CLC1GLS2_D4N 0x40
5255 #define _CLC1GLS2_LC1G3D4T 0x80
5256 #define _CLC1GLS2_D4T 0x80
5258 //==============================================================================
5261 //==============================================================================
5264 extern __at(0x0F19) __sfr CLC1GLS3
;
5270 unsigned LC1G4D1N
: 1;
5271 unsigned LC1G4D1T
: 1;
5272 unsigned LC1G4D2N
: 1;
5273 unsigned LC1G4D2T
: 1;
5274 unsigned LC1G4D3N
: 1;
5275 unsigned LC1G4D3T
: 1;
5276 unsigned LC1G4D4N
: 1;
5277 unsigned LC1G4D4T
: 1;
5293 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
5295 #define _LC1G4D1N 0x01
5297 #define _LC1G4D1T 0x02
5299 #define _LC1G4D2N 0x04
5301 #define _LC1G4D2T 0x08
5303 #define _LC1G4D3N 0x10
5305 #define _LC1G4D3T 0x20
5307 #define _LC1G4D4N 0x40
5309 #define _LC1G4D4T 0x80
5312 //==============================================================================
5315 //==============================================================================
5318 extern __at(0x0F1A) __sfr CLC2CON
;
5324 unsigned LC2MODE0
: 1;
5325 unsigned LC2MODE1
: 1;
5326 unsigned LC2MODE2
: 1;
5327 unsigned LC2INTN
: 1;
5328 unsigned LC2INTP
: 1;
5329 unsigned LC2OUT
: 1;
5354 unsigned LC2MODE
: 3;
5359 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
5361 #define _CLC2CON_LC2MODE0 0x01
5362 #define _CLC2CON_MODE0 0x01
5363 #define _CLC2CON_LC2MODE1 0x02
5364 #define _CLC2CON_MODE1 0x02
5365 #define _CLC2CON_LC2MODE2 0x04
5366 #define _CLC2CON_MODE2 0x04
5367 #define _CLC2CON_LC2INTN 0x08
5368 #define _CLC2CON_INTN 0x08
5369 #define _CLC2CON_LC2INTP 0x10
5370 #define _CLC2CON_INTP 0x10
5371 #define _CLC2CON_LC2OUT 0x20
5372 #define _CLC2CON_OUT 0x20
5373 #define _CLC2CON_LC2EN 0x80
5374 #define _CLC2CON_EN 0x80
5376 //==============================================================================
5379 //==============================================================================
5382 extern __at(0x0F1B) __sfr CLC2POL
;
5388 unsigned LC2G1POL
: 1;
5389 unsigned LC2G2POL
: 1;
5390 unsigned LC2G3POL
: 1;
5391 unsigned LC2G4POL
: 1;
5395 unsigned LC2POL
: 1;
5411 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
5413 #define _CLC2POL_LC2G1POL 0x01
5414 #define _CLC2POL_G1POL 0x01
5415 #define _CLC2POL_LC2G2POL 0x02
5416 #define _CLC2POL_G2POL 0x02
5417 #define _CLC2POL_LC2G3POL 0x04
5418 #define _CLC2POL_G3POL 0x04
5419 #define _CLC2POL_LC2G4POL 0x08
5420 #define _CLC2POL_G4POL 0x08
5421 #define _CLC2POL_LC2POL 0x80
5422 #define _CLC2POL_POL 0x80
5424 //==============================================================================
5427 //==============================================================================
5430 extern __at(0x0F1C) __sfr CLC2SEL0
;
5436 unsigned LC2D1S0
: 1;
5437 unsigned LC2D1S1
: 1;
5438 unsigned LC2D1S2
: 1;
5439 unsigned LC2D1S3
: 1;
5440 unsigned LC2D1S4
: 1;
5466 unsigned LC2D1S
: 5;
5471 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
5473 #define _CLC2SEL0_LC2D1S0 0x01
5474 #define _CLC2SEL0_D1S0 0x01
5475 #define _CLC2SEL0_LC2D1S1 0x02
5476 #define _CLC2SEL0_D1S1 0x02
5477 #define _CLC2SEL0_LC2D1S2 0x04
5478 #define _CLC2SEL0_D1S2 0x04
5479 #define _CLC2SEL0_LC2D1S3 0x08
5480 #define _CLC2SEL0_D1S3 0x08
5481 #define _CLC2SEL0_LC2D1S4 0x10
5482 #define _CLC2SEL0_D1S4 0x10
5484 //==============================================================================
5487 //==============================================================================
5490 extern __at(0x0F1D) __sfr CLC2SEL1
;
5496 unsigned LC2D2S0
: 1;
5497 unsigned LC2D2S1
: 1;
5498 unsigned LC2D2S2
: 1;
5499 unsigned LC2D2S3
: 1;
5500 unsigned LC2D2S4
: 1;
5520 unsigned LC2D2S
: 5;
5531 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
5533 #define _CLC2SEL1_LC2D2S0 0x01
5534 #define _CLC2SEL1_D2S0 0x01
5535 #define _CLC2SEL1_LC2D2S1 0x02
5536 #define _CLC2SEL1_D2S1 0x02
5537 #define _CLC2SEL1_LC2D2S2 0x04
5538 #define _CLC2SEL1_D2S2 0x04
5539 #define _CLC2SEL1_LC2D2S3 0x08
5540 #define _CLC2SEL1_D2S3 0x08
5541 #define _CLC2SEL1_LC2D2S4 0x10
5542 #define _CLC2SEL1_D2S4 0x10
5544 //==============================================================================
5547 //==============================================================================
5550 extern __at(0x0F1E) __sfr CLC2SEL2
;
5556 unsigned LC2D3S0
: 1;
5557 unsigned LC2D3S1
: 1;
5558 unsigned LC2D3S2
: 1;
5559 unsigned LC2D3S3
: 1;
5560 unsigned LC2D3S4
: 1;
5580 unsigned LC2D3S
: 5;
5591 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
5593 #define _CLC2SEL2_LC2D3S0 0x01
5594 #define _CLC2SEL2_D3S0 0x01
5595 #define _CLC2SEL2_LC2D3S1 0x02
5596 #define _CLC2SEL2_D3S1 0x02
5597 #define _CLC2SEL2_LC2D3S2 0x04
5598 #define _CLC2SEL2_D3S2 0x04
5599 #define _CLC2SEL2_LC2D3S3 0x08
5600 #define _CLC2SEL2_D3S3 0x08
5601 #define _CLC2SEL2_LC2D3S4 0x10
5602 #define _CLC2SEL2_D3S4 0x10
5604 //==============================================================================
5607 //==============================================================================
5610 extern __at(0x0F1F) __sfr CLC2SEL3
;
5616 unsigned LC2D4S0
: 1;
5617 unsigned LC2D4S1
: 1;
5618 unsigned LC2D4S2
: 1;
5619 unsigned LC2D4S3
: 1;
5620 unsigned LC2D4S4
: 1;
5646 unsigned LC2D4S
: 5;
5651 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
5653 #define _CLC2SEL3_LC2D4S0 0x01
5654 #define _CLC2SEL3_D4S0 0x01
5655 #define _CLC2SEL3_LC2D4S1 0x02
5656 #define _CLC2SEL3_D4S1 0x02
5657 #define _CLC2SEL3_LC2D4S2 0x04
5658 #define _CLC2SEL3_D4S2 0x04
5659 #define _CLC2SEL3_LC2D4S3 0x08
5660 #define _CLC2SEL3_D4S3 0x08
5661 #define _CLC2SEL3_LC2D4S4 0x10
5662 #define _CLC2SEL3_D4S4 0x10
5664 //==============================================================================
5667 //==============================================================================
5670 extern __at(0x0F20) __sfr CLC2GLS0
;
5676 unsigned LC2G1D1N
: 1;
5677 unsigned LC2G1D1T
: 1;
5678 unsigned LC2G1D2N
: 1;
5679 unsigned LC2G1D2T
: 1;
5680 unsigned LC2G1D3N
: 1;
5681 unsigned LC2G1D3T
: 1;
5682 unsigned LC2G1D4N
: 1;
5683 unsigned LC2G1D4T
: 1;
5699 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
5701 #define _CLC2GLS0_LC2G1D1N 0x01
5702 #define _CLC2GLS0_D1N 0x01
5703 #define _CLC2GLS0_LC2G1D1T 0x02
5704 #define _CLC2GLS0_D1T 0x02
5705 #define _CLC2GLS0_LC2G1D2N 0x04
5706 #define _CLC2GLS0_D2N 0x04
5707 #define _CLC2GLS0_LC2G1D2T 0x08
5708 #define _CLC2GLS0_D2T 0x08
5709 #define _CLC2GLS0_LC2G1D3N 0x10
5710 #define _CLC2GLS0_D3N 0x10
5711 #define _CLC2GLS0_LC2G1D3T 0x20
5712 #define _CLC2GLS0_D3T 0x20
5713 #define _CLC2GLS0_LC2G1D4N 0x40
5714 #define _CLC2GLS0_D4N 0x40
5715 #define _CLC2GLS0_LC2G1D4T 0x80
5716 #define _CLC2GLS0_D4T 0x80
5718 //==============================================================================
5721 //==============================================================================
5724 extern __at(0x0F21) __sfr CLC2GLS1
;
5730 unsigned LC2G2D1N
: 1;
5731 unsigned LC2G2D1T
: 1;
5732 unsigned LC2G2D2N
: 1;
5733 unsigned LC2G2D2T
: 1;
5734 unsigned LC2G2D3N
: 1;
5735 unsigned LC2G2D3T
: 1;
5736 unsigned LC2G2D4N
: 1;
5737 unsigned LC2G2D4T
: 1;
5753 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
5755 #define _CLC2GLS1_LC2G2D1N 0x01
5756 #define _CLC2GLS1_D1N 0x01
5757 #define _CLC2GLS1_LC2G2D1T 0x02
5758 #define _CLC2GLS1_D1T 0x02
5759 #define _CLC2GLS1_LC2G2D2N 0x04
5760 #define _CLC2GLS1_D2N 0x04
5761 #define _CLC2GLS1_LC2G2D2T 0x08
5762 #define _CLC2GLS1_D2T 0x08
5763 #define _CLC2GLS1_LC2G2D3N 0x10
5764 #define _CLC2GLS1_D3N 0x10
5765 #define _CLC2GLS1_LC2G2D3T 0x20
5766 #define _CLC2GLS1_D3T 0x20
5767 #define _CLC2GLS1_LC2G2D4N 0x40
5768 #define _CLC2GLS1_D4N 0x40
5769 #define _CLC2GLS1_LC2G2D4T 0x80
5770 #define _CLC2GLS1_D4T 0x80
5772 //==============================================================================
5775 //==============================================================================
5778 extern __at(0x0F22) __sfr CLC2GLS2
;
5784 unsigned LC2G3D1N
: 1;
5785 unsigned LC2G3D1T
: 1;
5786 unsigned LC2G3D2N
: 1;
5787 unsigned LC2G3D2T
: 1;
5788 unsigned LC2G3D3N
: 1;
5789 unsigned LC2G3D3T
: 1;
5790 unsigned LC2G3D4N
: 1;
5791 unsigned LC2G3D4T
: 1;
5807 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
5809 #define _CLC2GLS2_LC2G3D1N 0x01
5810 #define _CLC2GLS2_D1N 0x01
5811 #define _CLC2GLS2_LC2G3D1T 0x02
5812 #define _CLC2GLS2_D1T 0x02
5813 #define _CLC2GLS2_LC2G3D2N 0x04
5814 #define _CLC2GLS2_D2N 0x04
5815 #define _CLC2GLS2_LC2G3D2T 0x08
5816 #define _CLC2GLS2_D2T 0x08
5817 #define _CLC2GLS2_LC2G3D3N 0x10
5818 #define _CLC2GLS2_D3N 0x10
5819 #define _CLC2GLS2_LC2G3D3T 0x20
5820 #define _CLC2GLS2_D3T 0x20
5821 #define _CLC2GLS2_LC2G3D4N 0x40
5822 #define _CLC2GLS2_D4N 0x40
5823 #define _CLC2GLS2_LC2G3D4T 0x80
5824 #define _CLC2GLS2_D4T 0x80
5826 //==============================================================================
5829 //==============================================================================
5832 extern __at(0x0F23) __sfr CLC2GLS3
;
5838 unsigned LC2G4D1N
: 1;
5839 unsigned LC2G4D1T
: 1;
5840 unsigned LC2G4D2N
: 1;
5841 unsigned LC2G4D2T
: 1;
5842 unsigned LC2G4D3N
: 1;
5843 unsigned LC2G4D3T
: 1;
5844 unsigned LC2G4D4N
: 1;
5845 unsigned LC2G4D4T
: 1;
5861 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
5863 #define _CLC2GLS3_LC2G4D1N 0x01
5864 #define _CLC2GLS3_G4D1N 0x01
5865 #define _CLC2GLS3_LC2G4D1T 0x02
5866 #define _CLC2GLS3_G4D1T 0x02
5867 #define _CLC2GLS3_LC2G4D2N 0x04
5868 #define _CLC2GLS3_G4D2N 0x04
5869 #define _CLC2GLS3_LC2G4D2T 0x08
5870 #define _CLC2GLS3_G4D2T 0x08
5871 #define _CLC2GLS3_LC2G4D3N 0x10
5872 #define _CLC2GLS3_G4D3N 0x10
5873 #define _CLC2GLS3_LC2G4D3T 0x20
5874 #define _CLC2GLS3_G4D3T 0x20
5875 #define _CLC2GLS3_LC2G4D4N 0x40
5876 #define _CLC2GLS3_G4D4N 0x40
5877 #define _CLC2GLS3_LC2G4D4T 0x80
5878 #define _CLC2GLS3_G4D4T 0x80
5880 //==============================================================================
5883 //==============================================================================
5886 extern __at(0x0F24) __sfr CLC3CON
;
5892 unsigned LC3MODE0
: 1;
5893 unsigned LC3MODE1
: 1;
5894 unsigned LC3MODE2
: 1;
5895 unsigned LC3INTN
: 1;
5896 unsigned LC3INTP
: 1;
5897 unsigned LC3OUT
: 1;
5916 unsigned LC3MODE
: 3;
5927 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
5929 #define _CLC3CON_LC3MODE0 0x01
5930 #define _CLC3CON_MODE0 0x01
5931 #define _CLC3CON_LC3MODE1 0x02
5932 #define _CLC3CON_MODE1 0x02
5933 #define _CLC3CON_LC3MODE2 0x04
5934 #define _CLC3CON_MODE2 0x04
5935 #define _CLC3CON_LC3INTN 0x08
5936 #define _CLC3CON_INTN 0x08
5937 #define _CLC3CON_LC3INTP 0x10
5938 #define _CLC3CON_INTP 0x10
5939 #define _CLC3CON_LC3OUT 0x20
5940 #define _CLC3CON_OUT 0x20
5941 #define _CLC3CON_LC3EN 0x80
5942 #define _CLC3CON_EN 0x80
5944 //==============================================================================
5947 //==============================================================================
5950 extern __at(0x0F25) __sfr CLC3POL
;
5956 unsigned LC3G1POL
: 1;
5957 unsigned LC3G2POL
: 1;
5958 unsigned LC3G3POL
: 1;
5959 unsigned LC3G4POL
: 1;
5963 unsigned LC3POL
: 1;
5979 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
5981 #define _CLC3POL_LC3G1POL 0x01
5982 #define _CLC3POL_G1POL 0x01
5983 #define _CLC3POL_LC3G2POL 0x02
5984 #define _CLC3POL_G2POL 0x02
5985 #define _CLC3POL_LC3G3POL 0x04
5986 #define _CLC3POL_G3POL 0x04
5987 #define _CLC3POL_LC3G4POL 0x08
5988 #define _CLC3POL_G4POL 0x08
5989 #define _CLC3POL_LC3POL 0x80
5990 #define _CLC3POL_POL 0x80
5992 //==============================================================================
5995 //==============================================================================
5998 extern __at(0x0F26) __sfr CLC3SEL0
;
6004 unsigned LC3D1S0
: 1;
6005 unsigned LC3D1S1
: 1;
6006 unsigned LC3D1S2
: 1;
6007 unsigned LC3D1S3
: 1;
6008 unsigned LC3D1S4
: 1;
6034 unsigned LC3D1S
: 5;
6039 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
6041 #define _CLC3SEL0_LC3D1S0 0x01
6042 #define _CLC3SEL0_D1S0 0x01
6043 #define _CLC3SEL0_LC3D1S1 0x02
6044 #define _CLC3SEL0_D1S1 0x02
6045 #define _CLC3SEL0_LC3D1S2 0x04
6046 #define _CLC3SEL0_D1S2 0x04
6047 #define _CLC3SEL0_LC3D1S3 0x08
6048 #define _CLC3SEL0_D1S3 0x08
6049 #define _CLC3SEL0_LC3D1S4 0x10
6050 #define _CLC3SEL0_D1S4 0x10
6052 //==============================================================================
6055 //==============================================================================
6058 extern __at(0x0F27) __sfr CLC3SEL1
;
6064 unsigned LC3D2S0
: 1;
6065 unsigned LC3D2S1
: 1;
6066 unsigned LC3D2S2
: 1;
6067 unsigned LC3D2S3
: 1;
6068 unsigned LC3D2S4
: 1;
6088 unsigned LC3D2S
: 5;
6099 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
6101 #define _CLC3SEL1_LC3D2S0 0x01
6102 #define _CLC3SEL1_D2S0 0x01
6103 #define _CLC3SEL1_LC3D2S1 0x02
6104 #define _CLC3SEL1_D2S1 0x02
6105 #define _CLC3SEL1_LC3D2S2 0x04
6106 #define _CLC3SEL1_D2S2 0x04
6107 #define _CLC3SEL1_LC3D2S3 0x08
6108 #define _CLC3SEL1_D2S3 0x08
6109 #define _CLC3SEL1_LC3D2S4 0x10
6110 #define _CLC3SEL1_D2S4 0x10
6112 //==============================================================================
6115 //==============================================================================
6118 extern __at(0x0F28) __sfr CLC3SEL2
;
6124 unsigned LC3D3S0
: 1;
6125 unsigned LC3D3S1
: 1;
6126 unsigned LC3D3S2
: 1;
6127 unsigned LC3D3S3
: 1;
6128 unsigned LC3D3S4
: 1;
6154 unsigned LC3D3S
: 5;
6159 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
6161 #define _CLC3SEL2_LC3D3S0 0x01
6162 #define _CLC3SEL2_D3S0 0x01
6163 #define _CLC3SEL2_LC3D3S1 0x02
6164 #define _CLC3SEL2_D3S1 0x02
6165 #define _CLC3SEL2_LC3D3S2 0x04
6166 #define _CLC3SEL2_D3S2 0x04
6167 #define _CLC3SEL2_LC3D3S3 0x08
6168 #define _CLC3SEL2_D3S3 0x08
6169 #define _CLC3SEL2_LC3D3S4 0x10
6170 #define _CLC3SEL2_D3S4 0x10
6172 //==============================================================================
6175 //==============================================================================
6178 extern __at(0x0F29) __sfr CLC3SEL3
;
6184 unsigned LC3D4S0
: 1;
6185 unsigned LC3D4S1
: 1;
6186 unsigned LC3D4S2
: 1;
6187 unsigned LC3D4S3
: 1;
6188 unsigned LC3D4S4
: 1;
6208 unsigned LC3D4S
: 5;
6219 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
6221 #define _CLC3SEL3_LC3D4S0 0x01
6222 #define _CLC3SEL3_D4S0 0x01
6223 #define _CLC3SEL3_LC3D4S1 0x02
6224 #define _CLC3SEL3_D4S1 0x02
6225 #define _CLC3SEL3_LC3D4S2 0x04
6226 #define _CLC3SEL3_D4S2 0x04
6227 #define _CLC3SEL3_LC3D4S3 0x08
6228 #define _CLC3SEL3_D4S3 0x08
6229 #define _CLC3SEL3_LC3D4S4 0x10
6230 #define _CLC3SEL3_D4S4 0x10
6232 //==============================================================================
6235 //==============================================================================
6238 extern __at(0x0F2A) __sfr CLC3GLS0
;
6244 unsigned LC3G1D1N
: 1;
6245 unsigned LC3G1D1T
: 1;
6246 unsigned LC3G1D2N
: 1;
6247 unsigned LC3G1D2T
: 1;
6248 unsigned LC3G1D3N
: 1;
6249 unsigned LC3G1D3T
: 1;
6250 unsigned LC3G1D4N
: 1;
6251 unsigned LC3G1D4T
: 1;
6267 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
6269 #define _CLC3GLS0_LC3G1D1N 0x01
6270 #define _CLC3GLS0_D1N 0x01
6271 #define _CLC3GLS0_LC3G1D1T 0x02
6272 #define _CLC3GLS0_D1T 0x02
6273 #define _CLC3GLS0_LC3G1D2N 0x04
6274 #define _CLC3GLS0_D2N 0x04
6275 #define _CLC3GLS0_LC3G1D2T 0x08
6276 #define _CLC3GLS0_D2T 0x08
6277 #define _CLC3GLS0_LC3G1D3N 0x10
6278 #define _CLC3GLS0_D3N 0x10
6279 #define _CLC3GLS0_LC3G1D3T 0x20
6280 #define _CLC3GLS0_D3T 0x20
6281 #define _CLC3GLS0_LC3G1D4N 0x40
6282 #define _CLC3GLS0_D4N 0x40
6283 #define _CLC3GLS0_LC3G1D4T 0x80
6284 #define _CLC3GLS0_D4T 0x80
6286 //==============================================================================
6289 //==============================================================================
6292 extern __at(0x0F2B) __sfr CLC3GLS1
;
6298 unsigned LC3G2D1N
: 1;
6299 unsigned LC3G2D1T
: 1;
6300 unsigned LC3G2D2N
: 1;
6301 unsigned LC3G2D2T
: 1;
6302 unsigned LC3G2D3N
: 1;
6303 unsigned LC3G2D3T
: 1;
6304 unsigned LC3G2D4N
: 1;
6305 unsigned LC3G2D4T
: 1;
6321 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
6323 #define _CLC3GLS1_LC3G2D1N 0x01
6324 #define _CLC3GLS1_D1N 0x01
6325 #define _CLC3GLS1_LC3G2D1T 0x02
6326 #define _CLC3GLS1_D1T 0x02
6327 #define _CLC3GLS1_LC3G2D2N 0x04
6328 #define _CLC3GLS1_D2N 0x04
6329 #define _CLC3GLS1_LC3G2D2T 0x08
6330 #define _CLC3GLS1_D2T 0x08
6331 #define _CLC3GLS1_LC3G2D3N 0x10
6332 #define _CLC3GLS1_D3N 0x10
6333 #define _CLC3GLS1_LC3G2D3T 0x20
6334 #define _CLC3GLS1_D3T 0x20
6335 #define _CLC3GLS1_LC3G2D4N 0x40
6336 #define _CLC3GLS1_D4N 0x40
6337 #define _CLC3GLS1_LC3G2D4T 0x80
6338 #define _CLC3GLS1_D4T 0x80
6340 //==============================================================================
6343 //==============================================================================
6346 extern __at(0x0F2C) __sfr CLC3GLS2
;
6352 unsigned LC3G3D1N
: 1;
6353 unsigned LC3G3D1T
: 1;
6354 unsigned LC3G3D2N
: 1;
6355 unsigned LC3G3D2T
: 1;
6356 unsigned LC3G3D3N
: 1;
6357 unsigned LC3G3D3T
: 1;
6358 unsigned LC3G3D4N
: 1;
6359 unsigned LC3G3D4T
: 1;
6375 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
6377 #define _CLC3GLS2_LC3G3D1N 0x01
6378 #define _CLC3GLS2_D1N 0x01
6379 #define _CLC3GLS2_LC3G3D1T 0x02
6380 #define _CLC3GLS2_D1T 0x02
6381 #define _CLC3GLS2_LC3G3D2N 0x04
6382 #define _CLC3GLS2_D2N 0x04
6383 #define _CLC3GLS2_LC3G3D2T 0x08
6384 #define _CLC3GLS2_D2T 0x08
6385 #define _CLC3GLS2_LC3G3D3N 0x10
6386 #define _CLC3GLS2_D3N 0x10
6387 #define _CLC3GLS2_LC3G3D3T 0x20
6388 #define _CLC3GLS2_D3T 0x20
6389 #define _CLC3GLS2_LC3G3D4N 0x40
6390 #define _CLC3GLS2_D4N 0x40
6391 #define _CLC3GLS2_LC3G3D4T 0x80
6392 #define _CLC3GLS2_D4T 0x80
6394 //==============================================================================
6397 //==============================================================================
6400 extern __at(0x0F2D) __sfr CLC3GLS3
;
6406 unsigned LC3G4D1N
: 1;
6407 unsigned LC3G4D1T
: 1;
6408 unsigned LC3G4D2N
: 1;
6409 unsigned LC3G4D2T
: 1;
6410 unsigned LC3G4D3N
: 1;
6411 unsigned LC3G4D3T
: 1;
6412 unsigned LC3G4D4N
: 1;
6413 unsigned LC3G4D4T
: 1;
6429 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
6431 #define _CLC3GLS3_LC3G4D1N 0x01
6432 #define _CLC3GLS3_G4D1N 0x01
6433 #define _CLC3GLS3_LC3G4D1T 0x02
6434 #define _CLC3GLS3_G4D1T 0x02
6435 #define _CLC3GLS3_LC3G4D2N 0x04
6436 #define _CLC3GLS3_G4D2N 0x04
6437 #define _CLC3GLS3_LC3G4D2T 0x08
6438 #define _CLC3GLS3_G4D2T 0x08
6439 #define _CLC3GLS3_LC3G4D3N 0x10
6440 #define _CLC3GLS3_G4D3N 0x10
6441 #define _CLC3GLS3_LC3G4D3T 0x20
6442 #define _CLC3GLS3_G4D3T 0x20
6443 #define _CLC3GLS3_LC3G4D4N 0x40
6444 #define _CLC3GLS3_G4D4N 0x40
6445 #define _CLC3GLS3_LC3G4D4T 0x80
6446 #define _CLC3GLS3_G4D4T 0x80
6448 //==============================================================================
6451 //==============================================================================
6454 extern __at(0x0F9E) __sfr ICDBK0H
;
6468 extern __at(0x0F9E) volatile __ICDBK0Hbits_t ICDBK0Hbits
;
6478 //==============================================================================
6481 //==============================================================================
6484 extern __at(0x0FE4) __sfr STATUS_SHAD
;
6488 unsigned C_SHAD
: 1;
6489 unsigned DC_SHAD
: 1;
6490 unsigned Z_SHAD
: 1;
6496 } __STATUS_SHADbits_t
;
6498 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
6500 #define _C_SHAD 0x01
6501 #define _DC_SHAD 0x02
6502 #define _Z_SHAD 0x04
6504 //==============================================================================
6506 extern __at(0x0FE5) __sfr WREG_SHAD
;
6507 extern __at(0x0FE6) __sfr BSR_SHAD
;
6508 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
6509 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
6510 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
6511 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
6512 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
6513 extern __at(0x0FED) __sfr STKPTR
;
6514 extern __at(0x0FEE) __sfr TOSL
;
6515 extern __at(0x0FEF) __sfr TOSH
;
6517 //==============================================================================
6519 // Configuration Bits
6521 //==============================================================================
6523 #define _CONFIG1 0x8007
6524 #define _CONFIG2 0x8008
6526 //----------------------------- CONFIG1 Options -------------------------------
6528 #define _FOSC_LP 0x3FF8 // LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins.
6529 #define _FOSC_XT 0x3FF9 // XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins.
6530 #define _FOSC_HS 0x3FFA // HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins.
6531 #define _FOSC_EXTRC 0x3FFB // EXTRC oscillator: External RC circuit connected to CLKIN pin.
6532 #define _FOSC_INTOSC 0x3FFC // INTOSC oscillator: I/O function on CLKIN pin.
6533 #define _FOSC_ECL 0x3FFD // ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pins.
6534 #define _FOSC_ECM 0x3FFE // ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pins.
6535 #define _FOSC_ECH 0x3FFF // ECH, External Clock, High Power Mode (4-20 MHz): device clock supplied to CLKIN pins.
6536 #define _WDTE_OFF 0x3FE7 // WDT disabled.
6537 #define _WDTE_SWDTEN 0x3FEF // WDT controlled by the SWDTEN bit in the WDTCON register.
6538 #define _WDTE_NSLEEP 0x3FF7 // WDT enabled while running and disabled in Sleep.
6539 #define _WDTE_ON 0x3FFF // WDT enabled.
6540 #define _PWRTE_ON 0x3FDF // PWRT enabled.
6541 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
6542 #define _MCLRE_OFF 0x3FBF // MCLR/VPP pin function is digital input.
6543 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR.
6544 #define _CP_ON 0x3F7F // Program memory code protection is enabled.
6545 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
6546 #define _BOREN_OFF 0x39FF // Brown-out Reset disabled.
6547 #define _BOREN_SBODEN 0x3BFF // Brown-out Reset controlled by the SBOREN bit in the BORCON register.
6548 #define _BOREN_NSLEEP 0x3DFF // Brown-out Reset enabled while running and disabled in Sleep.
6549 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled.
6550 #define _CLKOUTEN_ON 0x37FF // CLKOUT function is enabled on the CLKOUT pin.
6551 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
6552 #define _IESO_OFF 0x2FFF // Internal/External Switchover Mode is disabled.
6553 #define _IESO_ON 0x3FFF // Internal/External Switchover Mode is enabled.
6554 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
6555 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
6557 //----------------------------- CONFIG2 Options -------------------------------
6559 #define _WRT_ALL 0x3FFC // 000h to 1FFFh write protected, no addresses may be modified by EECON control.
6560 #define _WRT_HALF 0x3FFD // 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control.
6561 #define _WRT_BOOT 0x3FFE // 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control.
6562 #define _WRT_OFF 0x3FFF // Write protection off.
6563 #define _PPS1WAY_OFF 0x3FFB // The PPSLOCK bit can be set and cleared repeatedly by software.
6564 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit cannot be cleared once it is set by software.
6565 #define _ZCDDIS_OFF 0x3F7F // Zero-cross detect circuit is enabled at POR.
6566 #define _ZCDDIS_ON 0x3FFF // Zero-cross detect circuit is disabled at POR.
6567 #define _PLLEN_OFF 0x3EFF // 4x PLL is enabled when software sets the SPLLEN bit.
6568 #define _PLLEN_ON 0x3FFF // 4x PLL is always enabled.
6569 #define _STVREN_OFF 0x3DFF // Stack Overflow or Underflow will not cause a Reset.
6570 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
6571 #define _BORV_HI 0x3BFF // Brown-out Reset Voltage (Vbor), high trip point selected.
6572 #define _BORV_LO 0x3FFF // Brown-out Reset Voltage (Vbor), low trip point selected.
6573 #define _LPBOR_ON 0x37FF // Low-Power BOR is enabled.
6574 #define _LPBOR_OFF 0x3FFF // Low-Power BOR is disabled.
6575 #define _DEBUG_ON 0x2FFF // In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger.
6576 #define _DEBUG_OFF 0x3FFF // In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins.
6577 #define _LVP_OFF 0x1FFF // High-voltage on MCLR/VPP must be used for programming.
6578 #define _LVP_ON 0x3FFF // Low-voltage programming enabled.
6580 //==============================================================================
6582 #define _DEVID1 0x8006
6584 #define _IDLOC0 0x8000
6585 #define _IDLOC1 0x8001
6586 #define _IDLOC2 0x8002
6587 #define _IDLOC3 0x8003
6589 //==============================================================================
6591 #ifndef NO_BIT_DEFINES
6593 #define ADON ADCON0bits.ADON // bit 0
6594 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
6595 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
6596 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
6597 #define CHS0 ADCON0bits.CHS0 // bit 2
6598 #define CHS1 ADCON0bits.CHS1 // bit 3
6599 #define CHS2 ADCON0bits.CHS2 // bit 4
6600 #define CHS3 ADCON0bits.CHS3 // bit 5
6601 #define CHS4 ADCON0bits.CHS4 // bit 6
6603 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
6604 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
6605 #define ADNREF ADCON1bits.ADNREF // bit 2
6606 #define ADFM ADCON1bits.ADFM // bit 7
6608 #define TRIGSEL0 ADCON2bits.TRIGSEL0 // bit 4
6609 #define TRIGSEL1 ADCON2bits.TRIGSEL1 // bit 5
6610 #define TRIGSEL2 ADCON2bits.TRIGSEL2 // bit 6
6611 #define TRIGSEL3 ADCON2bits.TRIGSEL3 // bit 7
6613 #define ANSA0 ANSELAbits.ANSA0 // bit 0
6614 #define ANSA1 ANSELAbits.ANSA1 // bit 1
6615 #define ANSA2 ANSELAbits.ANSA2 // bit 2
6616 #define ANSA4 ANSELAbits.ANSA4 // bit 4
6617 #define ANS5 ANSELAbits.ANS5 // bit 5
6619 #define ANSC0 ANSELCbits.ANSC0 // bit 0
6620 #define ANSC1 ANSELCbits.ANSC1 // bit 1
6621 #define ANSC2 ANSELCbits.ANSC2 // bit 2
6622 #define ANSC3 ANSELCbits.ANSC3 // bit 3
6623 #define ANSC4 ANSELCbits.ANSC4 // bit 4
6624 #define ANSC5 ANSELCbits.ANSC5 // bit 5
6626 #define ABDEN BAUD1CONbits.ABDEN // bit 0
6627 #define WUE BAUD1CONbits.WUE // bit 1
6628 #define BRG16 BAUD1CONbits.BRG16 // bit 3
6629 #define SCKP BAUD1CONbits.SCKP // bit 4
6630 #define RCIDL BAUD1CONbits.RCIDL // bit 6
6631 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
6633 #define BORRDY BORCONbits.BORRDY // bit 0
6634 #define BORFS BORCONbits.BORFS // bit 6
6635 #define SBOREN BORCONbits.SBOREN // bit 7
6637 #define BSR0 BSRbits.BSR0 // bit 0
6638 #define BSR1 BSRbits.BSR1 // bit 1
6639 #define BSR2 BSRbits.BSR2 // bit 2
6640 #define BSR3 BSRbits.BSR3 // bit 3
6641 #define BSR4 BSRbits.BSR4 // bit 4
6643 #define CCP1M0 CCP1CONbits.CCP1M0 // bit 0
6644 #define CCP1M1 CCP1CONbits.CCP1M1 // bit 1
6645 #define CCP1M2 CCP1CONbits.CCP1M2 // bit 2
6646 #define CCP1M3 CCP1CONbits.CCP1M3 // bit 3
6647 #define DC1B0 CCP1CONbits.DC1B0 // bit 4, shadows bit in CCP1CONbits
6648 #define CCP1Y CCP1CONbits.CCP1Y // bit 4, shadows bit in CCP1CONbits
6649 #define DC1B1 CCP1CONbits.DC1B1 // bit 5, shadows bit in CCP1CONbits
6650 #define CCP1X CCP1CONbits.CCP1X // bit 5, shadows bit in CCP1CONbits
6652 #define CCP2M0 CCP2CONbits.CCP2M0 // bit 0
6653 #define CCP2M1 CCP2CONbits.CCP2M1 // bit 1
6654 #define CCP2M2 CCP2CONbits.CCP2M2 // bit 2
6655 #define CCP2M3 CCP2CONbits.CCP2M3 // bit 3
6656 #define DC2B0 CCP2CONbits.DC2B0 // bit 4, shadows bit in CCP2CONbits
6657 #define CCP2Y CCP2CONbits.CCP2Y // bit 4, shadows bit in CCP2CONbits
6658 #define DC2B1 CCP2CONbits.DC2B1 // bit 5, shadows bit in CCP2CONbits
6659 #define CCP2X CCP2CONbits.CCP2X // bit 5, shadows bit in CCP2CONbits
6661 #define C1TSEL0 CCPTMRSbits.C1TSEL0 // bit 0
6662 #define C1TSEL1 CCPTMRSbits.C1TSEL1 // bit 1
6663 #define C2TSEL0 CCPTMRSbits.C2TSEL0 // bit 2
6664 #define C2TSEL1 CCPTMRSbits.C2TSEL1 // bit 3
6665 #define P3TSEL0 CCPTMRSbits.P3TSEL0 // bit 4
6666 #define P3TSEL1 CCPTMRSbits.P3TSEL1 // bit 5
6667 #define P4TSEL0 CCPTMRSbits.P4TSEL0 // bit 6
6668 #define P4TSEL1 CCPTMRSbits.P4TSEL1 // bit 7
6670 #define LC1MODE0 CLC1CONbits.LC1MODE0 // bit 0, shadows bit in CLC1CONbits
6671 #define MODE0 CLC1CONbits.MODE0 // bit 0, shadows bit in CLC1CONbits
6672 #define LC1MODE1 CLC1CONbits.LC1MODE1 // bit 1, shadows bit in CLC1CONbits
6673 #define MODE1 CLC1CONbits.MODE1 // bit 1, shadows bit in CLC1CONbits
6674 #define LC1MODE2 CLC1CONbits.LC1MODE2 // bit 2, shadows bit in CLC1CONbits
6675 #define MODE2 CLC1CONbits.MODE2 // bit 2, shadows bit in CLC1CONbits
6676 #define LC1INTN CLC1CONbits.LC1INTN // bit 3, shadows bit in CLC1CONbits
6677 #define INTN CLC1CONbits.INTN // bit 3, shadows bit in CLC1CONbits
6678 #define LC1INTP CLC1CONbits.LC1INTP // bit 4, shadows bit in CLC1CONbits
6679 #define INTP CLC1CONbits.INTP // bit 4, shadows bit in CLC1CONbits
6680 #define LC1OUT CLC1CONbits.LC1OUT // bit 5, shadows bit in CLC1CONbits
6681 #define OUT CLC1CONbits.OUT // bit 5, shadows bit in CLC1CONbits
6682 #define LC1EN CLC1CONbits.LC1EN // bit 7, shadows bit in CLC1CONbits
6683 #define EN CLC1CONbits.EN // bit 7, shadows bit in CLC1CONbits
6685 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
6686 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
6687 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
6688 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
6689 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
6690 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
6691 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
6692 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
6693 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
6694 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
6695 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
6696 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
6697 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
6698 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
6699 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
6700 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
6702 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
6703 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
6704 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
6705 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
6706 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
6707 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
6708 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
6709 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
6710 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
6711 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
6712 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
6713 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
6714 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
6715 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
6716 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
6717 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
6719 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
6720 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
6721 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
6722 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
6723 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
6724 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
6725 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
6726 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
6727 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
6728 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
6730 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
6731 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
6732 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
6733 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
6734 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
6735 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
6736 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
6737 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
6738 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
6739 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
6741 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
6742 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
6743 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
6744 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
6745 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
6746 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
6747 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
6748 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
6749 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
6750 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
6752 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
6753 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
6754 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
6755 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
6756 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
6757 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
6758 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
6759 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
6760 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
6761 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
6763 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
6764 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
6765 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
6766 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
6767 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
6768 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
6769 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
6770 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
6771 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
6772 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
6774 #define MCLC1OUT CLCDATAbits.MCLC1OUT // bit 0
6775 #define MCLC2OUT CLCDATAbits.MCLC2OUT // bit 1
6776 #define MCLC3OUT CLCDATAbits.MCLC3OUT // bit 2
6778 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
6779 #define C1HYS CM1CON0bits.C1HYS // bit 1
6780 #define C1SP CM1CON0bits.C1SP // bit 2
6781 #define C1ZLF CM1CON0bits.C1ZLF // bit 3
6782 #define C1POL CM1CON0bits.C1POL // bit 4
6783 #define C1OUT CM1CON0bits.C1OUT // bit 6
6784 #define C1ON CM1CON0bits.C1ON // bit 7
6786 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
6787 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
6788 #define C1NCH2 CM1CON1bits.C1NCH2 // bit 2
6789 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 3
6790 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 4
6791 #define C1PCH2 CM1CON1bits.C1PCH2 // bit 5
6792 #define C1INTN CM1CON1bits.C1INTN // bit 6
6793 #define C1INTP CM1CON1bits.C1INTP // bit 7
6795 #define C2SYNC CM2CON0bits.C2SYNC // bit 0
6796 #define C2HYS CM2CON0bits.C2HYS // bit 1
6797 #define C2SP CM2CON0bits.C2SP // bit 2
6798 #define C2ZLF CM2CON0bits.C2ZLF // bit 3
6799 #define C2POL CM2CON0bits.C2POL // bit 4
6800 #define C2OUT CM2CON0bits.C2OUT // bit 6
6801 #define C2ON CM2CON0bits.C2ON // bit 7
6803 #define C2NCH0 CM2CON1bits.C2NCH0 // bit 0
6804 #define C2NCH1 CM2CON1bits.C2NCH1 // bit 1
6805 #define C2NCH2 CM2CON1bits.C2NCH2 // bit 2
6806 #define C2PCH0 CM2CON1bits.C2PCH0 // bit 3
6807 #define C2PCH1 CM2CON1bits.C2PCH1 // bit 4
6808 #define C2PCH2 CM2CON1bits.C2PCH2 // bit 5
6809 #define C2INTN CM2CON1bits.C2INTN // bit 6
6810 #define C2INTP CM2CON1bits.C2INTP // bit 7
6812 #define MC1OUT CMOUTbits.MC1OUT // bit 0
6813 #define MC2OUT CMOUTbits.MC2OUT // bit 1
6815 #define G1ASDAC0 COG1ASD0bits.G1ASDAC0 // bit 2
6816 #define G1ASDAC1 COG1ASD0bits.G1ASDAC1 // bit 3
6817 #define G1ASDBD0 COG1ASD0bits.G1ASDBD0 // bit 4
6818 #define G1ASDBD1 COG1ASD0bits.G1ASDBD1 // bit 5
6819 #define G1ARSEN COG1ASD0bits.G1ARSEN // bit 6
6820 #define G1ASE COG1ASD0bits.G1ASE // bit 7
6822 #define G1AS0E COG1ASD1bits.G1AS0E // bit 0
6823 #define G1AS1E COG1ASD1bits.G1AS1E // bit 1
6824 #define G1AS2E COG1ASD1bits.G1AS2E // bit 2
6825 #define G1AS3E COG1ASD1bits.G1AS3E // bit 3
6827 #define G1BLKF0 COG1BLKFbits.G1BLKF0 // bit 0
6828 #define G1BLKF1 COG1BLKFbits.G1BLKF1 // bit 1
6829 #define G1BLKF2 COG1BLKFbits.G1BLKF2 // bit 2
6830 #define G1BLKF3 COG1BLKFbits.G1BLKF3 // bit 3
6831 #define G1BLKF4 COG1BLKFbits.G1BLKF4 // bit 4
6832 #define G1BLKF5 COG1BLKFbits.G1BLKF5 // bit 5
6834 #define G1BLKR0 COG1BLKRbits.G1BLKR0 // bit 0
6835 #define G1BLKR1 COG1BLKRbits.G1BLKR1 // bit 1
6836 #define G1BLKR2 COG1BLKRbits.G1BLKR2 // bit 2
6837 #define G1BLKR3 COG1BLKRbits.G1BLKR3 // bit 3
6838 #define G1BLKR4 COG1BLKRbits.G1BLKR4 // bit 4
6839 #define G1BLKR5 COG1BLKRbits.G1BLKR5 // bit 5
6841 #define G1MD0 COG1CON0bits.G1MD0 // bit 0
6842 #define G1MD1 COG1CON0bits.G1MD1 // bit 1
6843 #define G1MD2 COG1CON0bits.G1MD2 // bit 2
6844 #define G1CS0 COG1CON0bits.G1CS0 // bit 3
6845 #define G1CS1 COG1CON0bits.G1CS1 // bit 4
6846 #define G1LD COG1CON0bits.G1LD // bit 6
6847 #define G1EN COG1CON0bits.G1EN // bit 7
6849 #define G1POLA COG1CON1bits.G1POLA // bit 0
6850 #define G1POLB COG1CON1bits.G1POLB // bit 1
6851 #define G1POLC COG1CON1bits.G1POLC // bit 2
6852 #define G1POLD COG1CON1bits.G1POLD // bit 3
6853 #define G1FDBS COG1CON1bits.G1FDBS // bit 6
6854 #define G1RDBS COG1CON1bits.G1RDBS // bit 7
6856 #define G1DBF0 COG1DBFbits.G1DBF0 // bit 0
6857 #define G1DBF1 COG1DBFbits.G1DBF1 // bit 1
6858 #define G1DBF2 COG1DBFbits.G1DBF2 // bit 2
6859 #define G1DBF3 COG1DBFbits.G1DBF3 // bit 3
6860 #define G1DBF4 COG1DBFbits.G1DBF4 // bit 4
6861 #define G1DBF5 COG1DBFbits.G1DBF5 // bit 5
6863 #define G1DBR0 COG1DBRbits.G1DBR0 // bit 0
6864 #define G1DBR1 COG1DBRbits.G1DBR1 // bit 1
6865 #define G1DBR2 COG1DBRbits.G1DBR2 // bit 2
6866 #define G1DBR3 COG1DBRbits.G1DBR3 // bit 3
6867 #define G1DBR4 COG1DBRbits.G1DBR4 // bit 4
6868 #define G1DBR5 COG1DBRbits.G1DBR5 // bit 5
6870 #define G1FIS0 COG1FISbits.G1FIS0 // bit 0
6871 #define G1FIS1 COG1FISbits.G1FIS1 // bit 1
6872 #define G1FIS2 COG1FISbits.G1FIS2 // bit 2
6873 #define G1FIS3 COG1FISbits.G1FIS3 // bit 3
6874 #define G1FIS4 COG1FISbits.G1FIS4 // bit 4
6875 #define G1FIS5 COG1FISbits.G1FIS5 // bit 5
6876 #define G1FIS6 COG1FISbits.G1FIS6 // bit 6
6878 #define G1FSIM0 COG1FSIMbits.G1FSIM0 // bit 0
6879 #define G1FSIM1 COG1FSIMbits.G1FSIM1 // bit 1
6880 #define G1FSIM2 COG1FSIMbits.G1FSIM2 // bit 2
6881 #define G1FSIM3 COG1FSIMbits.G1FSIM3 // bit 3
6882 #define G1FSIM4 COG1FSIMbits.G1FSIM4 // bit 4
6883 #define G1FSIM5 COG1FSIMbits.G1FSIM5 // bit 5
6884 #define G1FSIM6 COG1FSIMbits.G1FSIM6 // bit 6
6886 #define G1PHF0 COG1PHFbits.G1PHF0 // bit 0
6887 #define G1PHF1 COG1PHFbits.G1PHF1 // bit 1
6888 #define G1PHF2 COG1PHFbits.G1PHF2 // bit 2
6889 #define G1PHF3 COG1PHFbits.G1PHF3 // bit 3
6890 #define G1PHF4 COG1PHFbits.G1PHF4 // bit 4
6891 #define G1PHF5 COG1PHFbits.G1PHF5 // bit 5
6893 #define G1PHR0 COG1PHRbits.G1PHR0 // bit 0
6894 #define G1PHR1 COG1PHRbits.G1PHR1 // bit 1
6895 #define G1PHR2 COG1PHRbits.G1PHR2 // bit 2
6896 #define G1PHR3 COG1PHRbits.G1PHR3 // bit 3
6897 #define G1PHR4 COG1PHRbits.G1PHR4 // bit 4
6898 #define G1PHR5 COG1PHRbits.G1PHR5 // bit 5
6900 #define G1RIS0 COG1RISbits.G1RIS0 // bit 0
6901 #define G1RIS1 COG1RISbits.G1RIS1 // bit 1
6902 #define G1RIS2 COG1RISbits.G1RIS2 // bit 2
6903 #define G1RIS3 COG1RISbits.G1RIS3 // bit 3
6904 #define G1RIS4 COG1RISbits.G1RIS4 // bit 4
6905 #define G1RIS5 COG1RISbits.G1RIS5 // bit 5
6906 #define G1RIS6 COG1RISbits.G1RIS6 // bit 6
6908 #define G1RSIM0 COG1RSIMbits.G1RSIM0 // bit 0
6909 #define G1RSIM1 COG1RSIMbits.G1RSIM1 // bit 1
6910 #define G1RSIM2 COG1RSIMbits.G1RSIM2 // bit 2
6911 #define G1RSIM3 COG1RSIMbits.G1RSIM3 // bit 3
6912 #define G1RSIM4 COG1RSIMbits.G1RSIM4 // bit 4
6913 #define G1RSIM5 COG1RSIMbits.G1RSIM5 // bit 5
6914 #define G1RSIM6 COG1RSIMbits.G1RSIM6 // bit 6
6916 #define G1STRA COG1STRbits.G1STRA // bit 0
6917 #define G1STRB COG1STRbits.G1STRB // bit 1
6918 #define G1STRC COG1STRbits.G1STRC // bit 2
6919 #define G1STRD COG1STRbits.G1STRD // bit 3
6920 #define G1SDATA COG1STRbits.G1SDATA // bit 4
6921 #define G1SDATB COG1STRbits.G1SDATB // bit 5
6922 #define G1SDATC COG1STRbits.G1SDATC // bit 6
6923 #define G1SDATD COG1STRbits.G1SDATD // bit 7
6925 #define DAC1NSS DAC1CON0bits.DAC1NSS // bit 0, shadows bit in DAC1CON0bits
6926 #define DACNSS DAC1CON0bits.DACNSS // bit 0, shadows bit in DAC1CON0bits
6927 #define DAC1PSS0 DAC1CON0bits.DAC1PSS0 // bit 2, shadows bit in DAC1CON0bits
6928 #define DACPSS0 DAC1CON0bits.DACPSS0 // bit 2, shadows bit in DAC1CON0bits
6929 #define DAC1PSS1 DAC1CON0bits.DAC1PSS1 // bit 3, shadows bit in DAC1CON0bits
6930 #define DACPSS1 DAC1CON0bits.DACPSS1 // bit 3, shadows bit in DAC1CON0bits
6931 #define DAC1OE2 DAC1CON0bits.DAC1OE2 // bit 4, shadows bit in DAC1CON0bits
6932 #define DACOE0 DAC1CON0bits.DACOE0 // bit 4, shadows bit in DAC1CON0bits
6933 #define DAC1OE1 DAC1CON0bits.DAC1OE1 // bit 5, shadows bit in DAC1CON0bits
6934 #define DACOE1 DAC1CON0bits.DACOE1 // bit 5, shadows bit in DAC1CON0bits
6935 #define DAC1EN DAC1CON0bits.DAC1EN // bit 7, shadows bit in DAC1CON0bits
6936 #define DACEN DAC1CON0bits.DACEN // bit 7, shadows bit in DAC1CON0bits
6938 #define DAC1R0 DAC1CON1bits.DAC1R0 // bit 0, shadows bit in DAC1CON1bits
6939 #define DACR0 DAC1CON1bits.DACR0 // bit 0, shadows bit in DAC1CON1bits
6940 #define DAC1R1 DAC1CON1bits.DAC1R1 // bit 1, shadows bit in DAC1CON1bits
6941 #define DACR1 DAC1CON1bits.DACR1 // bit 1, shadows bit in DAC1CON1bits
6942 #define DAC1R2 DAC1CON1bits.DAC1R2 // bit 2, shadows bit in DAC1CON1bits
6943 #define DACR2 DAC1CON1bits.DACR2 // bit 2, shadows bit in DAC1CON1bits
6944 #define DAC1R3 DAC1CON1bits.DAC1R3 // bit 3, shadows bit in DAC1CON1bits
6945 #define DACR3 DAC1CON1bits.DACR3 // bit 3, shadows bit in DAC1CON1bits
6946 #define DAC1R4 DAC1CON1bits.DAC1R4 // bit 4, shadows bit in DAC1CON1bits
6947 #define DACR4 DAC1CON1bits.DACR4 // bit 4, shadows bit in DAC1CON1bits
6948 #define DAC1R5 DAC1CON1bits.DAC1R5 // bit 5, shadows bit in DAC1CON1bits
6949 #define DACR5 DAC1CON1bits.DACR5 // bit 5, shadows bit in DAC1CON1bits
6950 #define DAC1R6 DAC1CON1bits.DAC1R6 // bit 6, shadows bit in DAC1CON1bits
6951 #define DACR6 DAC1CON1bits.DACR6 // bit 6, shadows bit in DAC1CON1bits
6952 #define DAC1R7 DAC1CON1bits.DAC1R7 // bit 7, shadows bit in DAC1CON1bits
6953 #define DACR7 DAC1CON1bits.DACR7 // bit 7, shadows bit in DAC1CON1bits
6955 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
6956 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
6957 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
6958 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
6959 #define TSRNG FVRCONbits.TSRNG // bit 4
6960 #define TSEN FVRCONbits.TSEN // bit 5
6961 #define FVRRDY FVRCONbits.FVRRDY // bit 6
6962 #define FVREN FVRCONbits.FVREN // bit 7
6964 #define BKA8 ICDBK0Hbits.BKA8 // bit 0
6965 #define BKA9 ICDBK0Hbits.BKA9 // bit 1
6966 #define BKA10 ICDBK0Hbits.BKA10 // bit 2
6967 #define BKA11 ICDBK0Hbits.BKA11 // bit 3
6968 #define BKA12 ICDBK0Hbits.BKA12 // bit 4
6969 #define BKA13 ICDBK0Hbits.BKA13 // bit 5
6970 #define BKA14 ICDBK0Hbits.BKA14 // bit 6
6972 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
6973 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
6974 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
6975 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
6976 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
6977 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
6979 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
6980 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
6981 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
6982 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
6983 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
6984 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
6986 #define IOCIF INTCONbits.IOCIF // bit 0
6987 #define INTF INTCONbits.INTF // bit 1
6988 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
6989 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
6990 #define IOCIE INTCONbits.IOCIE // bit 3
6991 #define INTE INTCONbits.INTE // bit 4
6992 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
6993 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
6994 #define PEIE INTCONbits.PEIE // bit 6
6995 #define GIE INTCONbits.GIE // bit 7
6997 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
6998 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
6999 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
7000 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
7001 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
7002 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
7004 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
7005 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
7006 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
7007 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
7008 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
7009 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
7011 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
7012 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
7013 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
7014 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
7015 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
7016 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
7018 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
7019 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
7020 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
7021 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
7022 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
7023 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
7025 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
7026 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
7027 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
7028 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
7029 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
7030 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
7032 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
7033 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
7034 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
7035 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
7036 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
7037 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
7039 #define LATA0 LATAbits.LATA0 // bit 0
7040 #define LATA1 LATAbits.LATA1 // bit 1
7041 #define LATA2 LATAbits.LATA2 // bit 2
7042 #define LATA4 LATAbits.LATA4 // bit 4
7043 #define LATA5 LATAbits.LATA5 // bit 5
7045 #define LATC0 LATCbits.LATC0 // bit 0
7046 #define LATC1 LATCbits.LATC1 // bit 1
7047 #define LATC2 LATCbits.LATC2 // bit 2
7048 #define LATC3 LATCbits.LATC3 // bit 3
7049 #define LATC4 LATCbits.LATC4 // bit 4
7050 #define LATC5 LATCbits.LATC5 // bit 5
7052 #define ODA0 ODCONAbits.ODA0 // bit 0
7053 #define ODA1 ODCONAbits.ODA1 // bit 1
7054 #define ODA2 ODCONAbits.ODA2 // bit 2
7055 #define ODA4 ODCONAbits.ODA4 // bit 4
7056 #define ODA5 ODCONAbits.ODA5 // bit 5
7058 #define ODC0 ODCONCbits.ODC0 // bit 0
7059 #define ODC1 ODCONCbits.ODC1 // bit 1
7060 #define ODC2 ODCONCbits.ODC2 // bit 2
7061 #define ODC3 ODCONCbits.ODC3 // bit 3
7062 #define ODC4 ODCONCbits.ODC4 // bit 4
7063 #define ODC5 ODCONCbits.ODC5 // bit 5
7065 #define OPA1PCH0 OPA1CONbits.OPA1PCH0 // bit 0
7066 #define OPA1PCH1 OPA1CONbits.OPA1PCH1 // bit 1
7067 #define OPA1UG OPA1CONbits.OPA1UG // bit 4
7068 #define OPA1SP OPA1CONbits.OPA1SP // bit 6
7069 #define OPA1EN OPA1CONbits.OPA1EN // bit 7
7071 #define OPA2PCH0 OPA2CONbits.OPA2PCH0 // bit 0
7072 #define OPA2PCH1 OPA2CONbits.OPA2PCH1 // bit 1
7073 #define OPA2UG OPA2CONbits.OPA2UG // bit 4
7074 #define OPA2SP OPA2CONbits.OPA2SP // bit 6
7075 #define OPA2EN OPA2CONbits.OPA2EN // bit 7
7077 #define PS0 OPTION_REGbits.PS0 // bit 0
7078 #define PS1 OPTION_REGbits.PS1 // bit 1
7079 #define PS2 OPTION_REGbits.PS2 // bit 2
7080 #define PSA OPTION_REGbits.PSA // bit 3
7081 #define TMR0SE OPTION_REGbits.TMR0SE // bit 4, shadows bit in OPTION_REGbits
7082 #define T0SE OPTION_REGbits.T0SE // bit 4, shadows bit in OPTION_REGbits
7083 #define TMR0CS OPTION_REGbits.TMR0CS // bit 5, shadows bit in OPTION_REGbits
7084 #define T0CS OPTION_REGbits.T0CS // bit 5, shadows bit in OPTION_REGbits
7085 #define INTEDG OPTION_REGbits.INTEDG // bit 6
7086 #define NOT_WPUEN OPTION_REGbits.NOT_WPUEN // bit 7
7088 #define SCS0 OSCCONbits.SCS0 // bit 0
7089 #define SCS1 OSCCONbits.SCS1 // bit 1
7090 #define IRCF0 OSCCONbits.IRCF0 // bit 3
7091 #define IRCF1 OSCCONbits.IRCF1 // bit 4
7092 #define IRCF2 OSCCONbits.IRCF2 // bit 5
7093 #define IRCF3 OSCCONbits.IRCF3 // bit 6
7094 #define SPLLEN OSCCONbits.SPLLEN // bit 7
7096 #define HFIOFS OSCSTATbits.HFIOFS // bit 0
7097 #define LFIOFR OSCSTATbits.LFIOFR // bit 1
7098 #define MFIOFR OSCSTATbits.MFIOFR // bit 2
7099 #define HFIOFL OSCSTATbits.HFIOFL // bit 3
7100 #define HFIOFR OSCSTATbits.HFIOFR // bit 4
7101 #define OSTS OSCSTATbits.OSTS // bit 5
7102 #define PLLR OSCSTATbits.PLLR // bit 6
7103 #define SOSCR OSCSTATbits.SOSCR // bit 7
7105 #define TUN0 OSCTUNEbits.TUN0 // bit 0
7106 #define TUN1 OSCTUNEbits.TUN1 // bit 1
7107 #define TUN2 OSCTUNEbits.TUN2 // bit 2
7108 #define TUN3 OSCTUNEbits.TUN3 // bit 3
7109 #define TUN4 OSCTUNEbits.TUN4 // bit 4
7110 #define TUN5 OSCTUNEbits.TUN5 // bit 5
7112 #define NOT_BOR PCONbits.NOT_BOR // bit 0
7113 #define NOT_POR PCONbits.NOT_POR // bit 1
7114 #define NOT_RI PCONbits.NOT_RI // bit 2
7115 #define NOT_RMCLR PCONbits.NOT_RMCLR // bit 3
7116 #define NOT_RWDT PCONbits.NOT_RWDT // bit 4
7117 #define STKUNF PCONbits.STKUNF // bit 6
7118 #define STKOVF PCONbits.STKOVF // bit 7
7120 #define TMR1IE PIE1bits.TMR1IE // bit 0
7121 #define TMR2IE PIE1bits.TMR2IE // bit 1
7122 #define CCP1IE PIE1bits.CCP1IE // bit 2, shadows bit in PIE1bits
7123 #define CCPIE PIE1bits.CCPIE // bit 2, shadows bit in PIE1bits
7124 #define SSP1IE PIE1bits.SSP1IE // bit 3
7125 #define TXIE PIE1bits.TXIE // bit 4
7126 #define RCIE PIE1bits.RCIE // bit 5
7127 #define ADIE PIE1bits.ADIE // bit 6
7128 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
7130 #define CCP2IE PIE2bits.CCP2IE // bit 0
7131 #define TMR4IE PIE2bits.TMR4IE // bit 1
7132 #define TMR6IE PIE2bits.TMR6IE // bit 2
7133 #define BCL1IE PIE2bits.BCL1IE // bit 3
7134 #define C1IE PIE2bits.C1IE // bit 5
7135 #define C2IE PIE2bits.C2IE // bit 6
7136 #define OSFIE PIE2bits.OSFIE // bit 7
7138 #define CLC1IE PIE3bits.CLC1IE // bit 0
7139 #define CLC2IE PIE3bits.CLC2IE // bit 1
7140 #define CLC3IE PIE3bits.CLC3IE // bit 2
7141 #define ZCDIE PIE3bits.ZCDIE // bit 4
7142 #define COGIE PIE3bits.COGIE // bit 5
7144 #define TMR1IF PIR1bits.TMR1IF // bit 0
7145 #define TMR2IF PIR1bits.TMR2IF // bit 1
7146 #define CCP1IF PIR1bits.CCP1IF // bit 2, shadows bit in PIR1bits
7147 #define CCPIF PIR1bits.CCPIF // bit 2, shadows bit in PIR1bits
7148 #define SSP1IF PIR1bits.SSP1IF // bit 3
7149 #define TXIF PIR1bits.TXIF // bit 4
7150 #define RCIF PIR1bits.RCIF // bit 5
7151 #define ADIF PIR1bits.ADIF // bit 6
7152 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
7154 #define CCP2IF PIR2bits.CCP2IF // bit 0
7155 #define TMR4IF PIR2bits.TMR4IF // bit 1
7156 #define TMR6IF PIR2bits.TMR6IF // bit 2
7157 #define BCL1IF PIR2bits.BCL1IF // bit 3
7158 #define C1IF PIR2bits.C1IF // bit 5
7159 #define C2IF PIR2bits.C2IF // bit 6
7160 #define OSFIF PIR2bits.OSFIF // bit 7
7162 #define CLC1IF PIR3bits.CLC1IF // bit 0
7163 #define CLC2IF PIR3bits.CLC2IF // bit 1
7164 #define CLC3IF PIR3bits.CLC3IF // bit 2
7165 #define ZCDIF PIR3bits.ZCDIF // bit 4
7166 #define COGIF PIR3bits.COGIF // bit 5
7168 #define RD PMCON1bits.RD // bit 0
7169 #define WR PMCON1bits.WR // bit 1
7170 #define WREN PMCON1bits.WREN // bit 2
7171 #define WRERR PMCON1bits.WRERR // bit 3
7172 #define FREE PMCON1bits.FREE // bit 4
7173 #define LWLO PMCON1bits.LWLO // bit 5
7174 #define CFGS PMCON1bits.CFGS // bit 6
7176 #define RA0 PORTAbits.RA0 // bit 0
7177 #define RA1 PORTAbits.RA1 // bit 1
7178 #define RA2 PORTAbits.RA2 // bit 2
7179 #define RA3 PORTAbits.RA3 // bit 3
7180 #define RA4 PORTAbits.RA4 // bit 4
7181 #define RA5 PORTAbits.RA5 // bit 5
7183 #define RC0 PORTCbits.RC0 // bit 0
7184 #define RC1 PORTCbits.RC1 // bit 1
7185 #define RC2 PORTCbits.RC2 // bit 2
7186 #define RC3 PORTCbits.RC3 // bit 3
7187 #define RC4 PORTCbits.RC4 // bit 4
7188 #define RC5 PORTCbits.RC5 // bit 5
7190 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
7192 #define PWM3POL PWM3CONbits.PWM3POL // bit 4
7193 #define PWM3OUT PWM3CONbits.PWM3OUT // bit 5
7194 #define PWM3EN PWM3CONbits.PWM3EN // bit 7
7196 #define PWM3DCH0 PWM3DCHbits.PWM3DCH0 // bit 0
7197 #define PWM3DCH1 PWM3DCHbits.PWM3DCH1 // bit 1
7198 #define PWM3DCH2 PWM3DCHbits.PWM3DCH2 // bit 2
7199 #define PWM3DCH3 PWM3DCHbits.PWM3DCH3 // bit 3
7200 #define PWM3DCH4 PWM3DCHbits.PWM3DCH4 // bit 4
7201 #define PWM3DCH5 PWM3DCHbits.PWM3DCH5 // bit 5
7202 #define PWM3DCH6 PWM3DCHbits.PWM3DCH6 // bit 6
7203 #define PWM3DCH7 PWM3DCHbits.PWM3DCH7 // bit 7
7205 #define PWM3DCL0 PWM3DCLbits.PWM3DCL0 // bit 6
7206 #define PWM3DCL1 PWM3DCLbits.PWM3DCL1 // bit 7
7208 #define PWM4POL PWM4CONbits.PWM4POL // bit 4
7209 #define PWM4OUT PWM4CONbits.PWM4OUT // bit 5
7210 #define PWM4EN PWM4CONbits.PWM4EN // bit 7
7212 #define PWM4DCH0 PWM4DCHbits.PWM4DCH0 // bit 0
7213 #define PWM4DCH1 PWM4DCHbits.PWM4DCH1 // bit 1
7214 #define PWM4DCH2 PWM4DCHbits.PWM4DCH2 // bit 2
7215 #define PWM4DCH3 PWM4DCHbits.PWM4DCH3 // bit 3
7216 #define PWM4DCH4 PWM4DCHbits.PWM4DCH4 // bit 4
7217 #define PWM4DCH5 PWM4DCHbits.PWM4DCH5 // bit 5
7218 #define PWM4DCH6 PWM4DCHbits.PWM4DCH6 // bit 6
7219 #define PWM4DCH7 PWM4DCHbits.PWM4DCH7 // bit 7
7221 #define PWM4DCL0 PWM4DCLbits.PWM4DCL0 // bit 6
7222 #define PWM4DCL1 PWM4DCLbits.PWM4DCL1 // bit 7
7224 #define RX9D RC1STAbits.RX9D // bit 0
7225 #define OERR RC1STAbits.OERR // bit 1
7226 #define FERR RC1STAbits.FERR // bit 2
7227 #define ADDEN RC1STAbits.ADDEN // bit 3
7228 #define CREN RC1STAbits.CREN // bit 4
7229 #define SREN RC1STAbits.SREN // bit 5
7230 #define RX9 RC1STAbits.RX9 // bit 6
7231 #define SPEN RC1STAbits.SPEN // bit 7
7233 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
7234 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
7235 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
7236 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
7237 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
7239 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
7240 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
7241 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
7242 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
7243 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
7244 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
7246 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
7247 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
7248 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
7249 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
7250 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
7251 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
7252 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
7253 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
7254 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
7255 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
7256 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
7257 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
7258 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
7259 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
7260 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
7261 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
7263 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
7264 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
7265 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
7266 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
7267 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
7268 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
7269 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
7270 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
7271 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
7272 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
7273 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
7274 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
7275 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
7276 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
7277 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
7278 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
7280 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
7281 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
7282 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
7283 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
7284 #define CKP SSP1CONbits.CKP // bit 4
7285 #define SSPEN SSP1CONbits.SSPEN // bit 5
7286 #define SSPOV SSP1CONbits.SSPOV // bit 6
7287 #define WCOL SSP1CONbits.WCOL // bit 7
7289 #define SEN SSP1CON2bits.SEN // bit 0
7290 #define RSEN SSP1CON2bits.RSEN // bit 1
7291 #define PEN SSP1CON2bits.PEN // bit 2
7292 #define RCEN SSP1CON2bits.RCEN // bit 3
7293 #define ACKEN SSP1CON2bits.ACKEN // bit 4
7294 #define ACKDT SSP1CON2bits.ACKDT // bit 5
7295 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
7296 #define GCEN SSP1CON2bits.GCEN // bit 7
7298 #define DHEN SSP1CON3bits.DHEN // bit 0
7299 #define AHEN SSP1CON3bits.AHEN // bit 1
7300 #define SBCDE SSP1CON3bits.SBCDE // bit 2
7301 #define SDAHT SSP1CON3bits.SDAHT // bit 3
7302 #define BOEN SSP1CON3bits.BOEN // bit 4
7303 #define SCIE SSP1CON3bits.SCIE // bit 5
7304 #define PCIE SSP1CON3bits.PCIE // bit 6
7305 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
7307 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
7308 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
7309 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
7310 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
7311 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
7312 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
7313 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
7314 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
7315 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
7316 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
7317 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
7318 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
7319 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
7320 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
7321 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
7322 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
7324 #define BF SSP1STATbits.BF // bit 0
7325 #define UA SSP1STATbits.UA // bit 1
7326 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
7327 #define S SSP1STATbits.S // bit 3
7328 #define P SSP1STATbits.P // bit 4
7329 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
7330 #define CKE SSP1STATbits.CKE // bit 6
7331 #define SMP SSP1STATbits.SMP // bit 7
7333 #define C STATUSbits.C // bit 0
7334 #define DC STATUSbits.DC // bit 1
7335 #define Z STATUSbits.Z // bit 2
7336 #define NOT_PD STATUSbits.NOT_PD // bit 3
7337 #define NOT_TO STATUSbits.NOT_TO // bit 4
7339 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
7340 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
7341 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
7343 #define TMR1ON T1CONbits.TMR1ON // bit 0
7344 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
7345 #define T1OSCEN T1CONbits.T1OSCEN // bit 3
7346 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
7347 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
7348 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
7349 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
7351 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
7352 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
7353 #define T1GVAL T1GCONbits.T1GVAL // bit 2
7354 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3
7355 #define T1GSPM T1GCONbits.T1GSPM // bit 4
7356 #define T1GTM T1GCONbits.T1GTM // bit 5
7357 #define T1GPOL T1GCONbits.T1GPOL // bit 6
7358 #define TMR1GE T1GCONbits.TMR1GE // bit 7
7360 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
7361 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
7362 #define TMR2ON T2CONbits.TMR2ON // bit 2
7363 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
7364 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
7365 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
7366 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
7368 #define T4CKPS0 T4CONbits.T4CKPS0 // bit 0
7369 #define T4CKPS1 T4CONbits.T4CKPS1 // bit 1
7370 #define TMR4ON T4CONbits.TMR4ON // bit 2
7371 #define T4OUTPS0 T4CONbits.T4OUTPS0 // bit 3
7372 #define T4OUTPS1 T4CONbits.T4OUTPS1 // bit 4
7373 #define T4OUTPS2 T4CONbits.T4OUTPS2 // bit 5
7374 #define T4OUTPS3 T4CONbits.T4OUTPS3 // bit 6
7376 #define T6CKPS0 T6CONbits.T6CKPS0 // bit 0
7377 #define T6CKPS1 T6CONbits.T6CKPS1 // bit 1
7378 #define TMR6ON T6CONbits.TMR6ON // bit 2
7379 #define T6OUTPS0 T6CONbits.T6OUTPS0 // bit 3
7380 #define T6OUTPS1 T6CONbits.T6OUTPS1 // bit 4
7381 #define T6OUTPS2 T6CONbits.T6OUTPS2 // bit 5
7382 #define T6OUTPS3 T6CONbits.T6OUTPS3 // bit 6
7384 #define TRISA0 TRISAbits.TRISA0 // bit 0
7385 #define TRISA1 TRISAbits.TRISA1 // bit 1
7386 #define TRISA2 TRISAbits.TRISA2 // bit 2
7387 #define TRISA4 TRISAbits.TRISA4 // bit 4
7388 #define TRISA5 TRISAbits.TRISA5 // bit 5
7390 #define TRISC0 TRISCbits.TRISC0 // bit 0
7391 #define TRISC1 TRISCbits.TRISC1 // bit 1
7392 #define TRISC2 TRISCbits.TRISC2 // bit 2
7393 #define TRISC3 TRISCbits.TRISC3 // bit 3
7394 #define TRISC4 TRISCbits.TRISC4 // bit 4
7395 #define TRISC5 TRISCbits.TRISC5 // bit 5
7397 #define TX9D TX1STAbits.TX9D // bit 0
7398 #define TRMT TX1STAbits.TRMT // bit 1
7399 #define BRGH TX1STAbits.BRGH // bit 2
7400 #define SENDB TX1STAbits.SENDB // bit 3
7401 #define SYNC TX1STAbits.SYNC // bit 4
7402 #define TXEN TX1STAbits.TXEN // bit 5
7403 #define TX9 TX1STAbits.TX9 // bit 6
7404 #define CSRC TX1STAbits.CSRC // bit 7
7406 #define Reserved VREGCONbits.Reserved // bit 0
7407 #define VREGPM VREGCONbits.VREGPM // bit 1
7409 #define SWDTEN WDTCONbits.SWDTEN // bit 0
7410 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
7411 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
7412 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
7413 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
7414 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
7416 #define WPUA0 WPUAbits.WPUA0 // bit 0
7417 #define WPUA1 WPUAbits.WPUA1 // bit 1
7418 #define WPUA2 WPUAbits.WPUA2 // bit 2
7419 #define WPUA3 WPUAbits.WPUA3 // bit 3
7420 #define WPUA4 WPUAbits.WPUA4 // bit 4
7421 #define WPUA5 WPUAbits.WPUA5 // bit 5
7423 #define WPUC0 WPUCbits.WPUC0 // bit 0
7424 #define WPUC1 WPUCbits.WPUC1 // bit 1
7425 #define WPUC2 WPUCbits.WPUC2 // bit 2
7426 #define WPUC3 WPUCbits.WPUC3 // bit 3
7427 #define WPUC4 WPUCbits.WPUC4 // bit 4
7428 #define WPUC5 WPUCbits.WPUC5 // bit 5
7430 #define ZCD1INTN ZCD1CONbits.ZCD1INTN // bit 0
7431 #define ZCD1INTP ZCD1CONbits.ZCD1INTP // bit 1
7432 #define ZCD1POL ZCD1CONbits.ZCD1POL // bit 4
7433 #define ZCD1OUT ZCD1CONbits.ZCD1OUT // bit 5
7434 #define ZCD1EN ZCD1CONbits.ZCD1EN // bit 7
7436 #endif // #ifndef NO_BIT_DEFINES
7438 #endif // #ifndef __PIC16F1705_H__