2 * This declarations of the PIC16F1708 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:11 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F1708_H__
26 #define __PIC16F1708_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTB_ADDR 0x000D
52 #define PORTC_ADDR 0x000E
53 #define PIR1_ADDR 0x0011
54 #define PIR2_ADDR 0x0012
55 #define PIR3_ADDR 0x0013
56 #define TMR0_ADDR 0x0015
57 #define TMR1_ADDR 0x0016
58 #define TMR1L_ADDR 0x0016
59 #define TMR1H_ADDR 0x0017
60 #define T1CON_ADDR 0x0018
61 #define T1GCON_ADDR 0x0019
62 #define TMR2_ADDR 0x001A
63 #define PR2_ADDR 0x001B
64 #define T2CON_ADDR 0x001C
65 #define TRISA_ADDR 0x008C
66 #define TRISB_ADDR 0x008D
67 #define TRISC_ADDR 0x008E
68 #define PIE1_ADDR 0x0091
69 #define PIE2_ADDR 0x0092
70 #define PIE3_ADDR 0x0093
71 #define OPTION_REG_ADDR 0x0095
72 #define PCON_ADDR 0x0096
73 #define WDTCON_ADDR 0x0097
74 #define OSCTUNE_ADDR 0x0098
75 #define OSCCON_ADDR 0x0099
76 #define OSCSTAT_ADDR 0x009A
77 #define ADRES_ADDR 0x009B
78 #define ADRESL_ADDR 0x009B
79 #define ADRESH_ADDR 0x009C
80 #define ADCON0_ADDR 0x009D
81 #define ADCON1_ADDR 0x009E
82 #define ADCON2_ADDR 0x009F
83 #define LATA_ADDR 0x010C
84 #define LATB_ADDR 0x010D
85 #define LATC_ADDR 0x010E
86 #define CM1CON0_ADDR 0x0111
87 #define CM1CON1_ADDR 0x0112
88 #define CM2CON0_ADDR 0x0113
89 #define CM2CON1_ADDR 0x0114
90 #define CMOUT_ADDR 0x0115
91 #define BORCON_ADDR 0x0116
92 #define FVRCON_ADDR 0x0117
93 #define DAC1CON0_ADDR 0x0118
94 #define DAC1CON1_ADDR 0x0119
95 #define ZCD1CON_ADDR 0x011C
96 #define ANSELA_ADDR 0x018C
97 #define ANSELB_ADDR 0x018D
98 #define ANSELC_ADDR 0x018E
99 #define PMADR_ADDR 0x0191
100 #define PMADRL_ADDR 0x0191
101 #define PMADRH_ADDR 0x0192
102 #define PMDAT_ADDR 0x0193
103 #define PMDATL_ADDR 0x0193
104 #define PMDATH_ADDR 0x0194
105 #define PMCON1_ADDR 0x0195
106 #define PMCON2_ADDR 0x0196
107 #define VREGCON_ADDR 0x0197
108 #define RC1REG_ADDR 0x0199
109 #define RCREG_ADDR 0x0199
110 #define RCREG1_ADDR 0x0199
111 #define TX1REG_ADDR 0x019A
112 #define TXREG_ADDR 0x019A
113 #define TXREG1_ADDR 0x019A
114 #define SP1BRG_ADDR 0x019B
115 #define SP1BRGL_ADDR 0x019B
116 #define SPBRG_ADDR 0x019B
117 #define SPBRG1_ADDR 0x019B
118 #define SPBRGL_ADDR 0x019B
119 #define SP1BRGH_ADDR 0x019C
120 #define SPBRGH_ADDR 0x019C
121 #define SPBRGH1_ADDR 0x019C
122 #define RC1STA_ADDR 0x019D
123 #define RCSTA_ADDR 0x019D
124 #define RCSTA1_ADDR 0x019D
125 #define TX1STA_ADDR 0x019E
126 #define TXSTA_ADDR 0x019E
127 #define TXSTA1_ADDR 0x019E
128 #define BAUD1CON_ADDR 0x019F
129 #define BAUDCON_ADDR 0x019F
130 #define BAUDCON1_ADDR 0x019F
131 #define BAUDCTL_ADDR 0x019F
132 #define BAUDCTL1_ADDR 0x019F
133 #define WPUA_ADDR 0x020C
134 #define WPUB_ADDR 0x020D
135 #define WPUC_ADDR 0x020E
136 #define SSP1BUF_ADDR 0x0211
137 #define SSPBUF_ADDR 0x0211
138 #define SSP1ADD_ADDR 0x0212
139 #define SSPADD_ADDR 0x0212
140 #define SSP1MSK_ADDR 0x0213
141 #define SSPMSK_ADDR 0x0213
142 #define SSP1STAT_ADDR 0x0214
143 #define SSPSTAT_ADDR 0x0214
144 #define SSP1CON_ADDR 0x0215
145 #define SSP1CON1_ADDR 0x0215
146 #define SSPCON_ADDR 0x0215
147 #define SSPCON1_ADDR 0x0215
148 #define SSP1CON2_ADDR 0x0216
149 #define SSPCON2_ADDR 0x0216
150 #define SSP1CON3_ADDR 0x0217
151 #define SSPCON3_ADDR 0x0217
152 #define ODCONA_ADDR 0x028C
153 #define ODCONB_ADDR 0x028D
154 #define ODCONC_ADDR 0x028E
155 #define CCPR1_ADDR 0x0291
156 #define CCPR1L_ADDR 0x0291
157 #define CCPR1H_ADDR 0x0292
158 #define CCP1CON_ADDR 0x0293
159 #define ECCP1CON_ADDR 0x0293
160 #define CCPR2_ADDR 0x0298
161 #define CCPR2L_ADDR 0x0298
162 #define CCPR2H_ADDR 0x0299
163 #define CCP2CON_ADDR 0x029A
164 #define ECCP2CON_ADDR 0x029A
165 #define CCPTMRS_ADDR 0x029E
166 #define SLRCONA_ADDR 0x030C
167 #define SLRCONB_ADDR 0x030D
168 #define SLRCONC_ADDR 0x030E
169 #define INLVLA_ADDR 0x038C
170 #define INLVLB_ADDR 0x038D
171 #define INLVLC_ADDR 0x038E
172 #define IOCAP_ADDR 0x0391
173 #define IOCAN_ADDR 0x0392
174 #define IOCAF_ADDR 0x0393
175 #define IOCBP_ADDR 0x0394
176 #define IOCBN_ADDR 0x0395
177 #define IOCBF_ADDR 0x0396
178 #define IOCCP_ADDR 0x0397
179 #define IOCCN_ADDR 0x0398
180 #define IOCCF_ADDR 0x0399
181 #define TMR4_ADDR 0x0415
182 #define PR4_ADDR 0x0416
183 #define T4CON_ADDR 0x0417
184 #define TMR6_ADDR 0x041C
185 #define PR6_ADDR 0x041D
186 #define T6CON_ADDR 0x041E
187 #define OPA1CON_ADDR 0x0511
188 #define OPA2CON_ADDR 0x0515
189 #define PWM3DCL_ADDR 0x0617
190 #define PWM3DCH_ADDR 0x0618
191 #define PWM3CON_ADDR 0x0619
192 #define PWM3CON0_ADDR 0x0619
193 #define PWM4DCL_ADDR 0x061A
194 #define PWM4DCH_ADDR 0x061B
195 #define PWM4CON_ADDR 0x061C
196 #define PWM4CON0_ADDR 0x061C
197 #define COG1PHR_ADDR 0x0691
198 #define COG1PHF_ADDR 0x0692
199 #define COG1BLKR_ADDR 0x0693
200 #define COG1BLKF_ADDR 0x0694
201 #define COG1DBR_ADDR 0x0695
202 #define COG1DBF_ADDR 0x0696
203 #define COG1CON0_ADDR 0x0697
204 #define COG1CON1_ADDR 0x0698
205 #define COG1RIS_ADDR 0x0699
206 #define COG1RSIM_ADDR 0x069A
207 #define COG1FIS_ADDR 0x069B
208 #define COG1FSIM_ADDR 0x069C
209 #define COG1ASD0_ADDR 0x069D
210 #define COG1ASD1_ADDR 0x069E
211 #define COG1STR_ADDR 0x069F
212 #define PPSLOCK_ADDR 0x0E0F
213 #define INTPPS_ADDR 0x0E10
214 #define T0CKIPPS_ADDR 0x0E11
215 #define T1CKIPPS_ADDR 0x0E12
216 #define T1GPPS_ADDR 0x0E13
217 #define CCP1PPS_ADDR 0x0E14
218 #define CCP2PPS_ADDR 0x0E15
219 #define COGINPPS_ADDR 0x0E17
220 #define SSPCLKPPS_ADDR 0x0E20
221 #define SSPDATPPS_ADDR 0x0E21
222 #define SSPSSPPS_ADDR 0x0E22
223 #define RXPPS_ADDR 0x0E24
224 #define CKPPS_ADDR 0x0E25
225 #define CLCIN0PPS_ADDR 0x0E28
226 #define CLCIN1PPS_ADDR 0x0E29
227 #define CLCIN2PPS_ADDR 0x0E2A
228 #define CLCIN3PPS_ADDR 0x0E2B
229 #define RA0PPS_ADDR 0x0E90
230 #define RA1PPS_ADDR 0x0E91
231 #define RA2PPS_ADDR 0x0E92
232 #define RA4PPS_ADDR 0x0E94
233 #define RA5PPS_ADDR 0x0E95
234 #define RB4PPS_ADDR 0x0E9C
235 #define RB5PPS_ADDR 0x0E9D
236 #define RB6PPS_ADDR 0x0E9E
237 #define RB7PPS_ADDR 0x0E9F
238 #define RC0PPS_ADDR 0x0EA0
239 #define RC1PPS_ADDR 0x0EA1
240 #define RC2PPS_ADDR 0x0EA2
241 #define RC3PPS_ADDR 0x0EA3
242 #define RC4PPS_ADDR 0x0EA4
243 #define RC5PPS_ADDR 0x0EA5
244 #define RC6PPS_ADDR 0x0EA6
245 #define RC7PPS_ADDR 0x0EA7
246 #define CLCDATA_ADDR 0x0F0F
247 #define CLC1CON_ADDR 0x0F10
248 #define CLC1POL_ADDR 0x0F11
249 #define CLC1SEL0_ADDR 0x0F12
250 #define CLC1SEL1_ADDR 0x0F13
251 #define CLC1SEL2_ADDR 0x0F14
252 #define CLC1SEL3_ADDR 0x0F15
253 #define CLC1GLS0_ADDR 0x0F16
254 #define CLC1GLS1_ADDR 0x0F17
255 #define CLC1GLS2_ADDR 0x0F18
256 #define CLC1GLS3_ADDR 0x0F19
257 #define CLC2CON_ADDR 0x0F1A
258 #define CLC2POL_ADDR 0x0F1B
259 #define CLC2SEL0_ADDR 0x0F1C
260 #define CLC2SEL1_ADDR 0x0F1D
261 #define CLC2SEL2_ADDR 0x0F1E
262 #define CLC2SEL3_ADDR 0x0F1F
263 #define CLC2GLS0_ADDR 0x0F20
264 #define CLC2GLS1_ADDR 0x0F21
265 #define CLC2GLS2_ADDR 0x0F22
266 #define CLC2GLS3_ADDR 0x0F23
267 #define CLC3CON_ADDR 0x0F24
268 #define CLC3POL_ADDR 0x0F25
269 #define CLC3SEL0_ADDR 0x0F26
270 #define CLC3SEL1_ADDR 0x0F27
271 #define CLC3SEL2_ADDR 0x0F28
272 #define CLC3SEL3_ADDR 0x0F29
273 #define CLC3GLS0_ADDR 0x0F2A
274 #define CLC3GLS1_ADDR 0x0F2B
275 #define CLC3GLS2_ADDR 0x0F2C
276 #define CLC3GLS3_ADDR 0x0F2D
277 #define STATUS_SHAD_ADDR 0x0FE4
278 #define WREG_SHAD_ADDR 0x0FE5
279 #define BSR_SHAD_ADDR 0x0FE6
280 #define PCLATH_SHAD_ADDR 0x0FE7
281 #define FSR0L_SHAD_ADDR 0x0FE8
282 #define FSR0H_SHAD_ADDR 0x0FE9
283 #define FSR1L_SHAD_ADDR 0x0FEA
284 #define FSR1H_SHAD_ADDR 0x0FEB
285 #define STKPTR_ADDR 0x0FED
286 #define TOSL_ADDR 0x0FEE
287 #define TOSH_ADDR 0x0FEF
289 #endif // #ifndef NO_ADDR_DEFINES
291 //==============================================================================
293 // Register Definitions
295 //==============================================================================
297 extern __at(0x0000) __sfr INDF0
;
298 extern __at(0x0001) __sfr INDF1
;
299 extern __at(0x0002) __sfr PCL
;
301 //==============================================================================
304 extern __at(0x0003) __sfr STATUS
;
318 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
326 //==============================================================================
328 extern __at(0x0004) __sfr FSR0
;
329 extern __at(0x0004) __sfr FSR0L
;
330 extern __at(0x0005) __sfr FSR0H
;
331 extern __at(0x0006) __sfr FSR1
;
332 extern __at(0x0006) __sfr FSR1L
;
333 extern __at(0x0007) __sfr FSR1H
;
335 //==============================================================================
338 extern __at(0x0008) __sfr BSR
;
361 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
369 //==============================================================================
371 extern __at(0x0009) __sfr WREG
;
372 extern __at(0x000A) __sfr PCLATH
;
374 //==============================================================================
377 extern __at(0x000B) __sfr INTCON
;
406 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
419 //==============================================================================
422 //==============================================================================
425 extern __at(0x000C) __sfr PORTA
;
448 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
457 //==============================================================================
460 //==============================================================================
463 extern __at(0x000D) __sfr PORTB
;
477 extern __at(0x000D) volatile __PORTBbits_t PORTBbits
;
484 //==============================================================================
487 //==============================================================================
490 extern __at(0x000E) __sfr PORTC
;
504 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
515 //==============================================================================
518 //==============================================================================
521 extern __at(0x0011) __sfr PIR1
;
534 unsigned TMR1GIF
: 1;
550 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
560 #define _TMR1GIF 0x80
562 //==============================================================================
565 //==============================================================================
568 extern __at(0x0012) __sfr PIR2
;
582 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
592 //==============================================================================
595 //==============================================================================
598 extern __at(0x0013) __sfr PIR3
;
612 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
620 //==============================================================================
622 extern __at(0x0015) __sfr TMR0
;
623 extern __at(0x0016) __sfr TMR1
;
624 extern __at(0x0016) __sfr TMR1L
;
625 extern __at(0x0017) __sfr TMR1H
;
627 //==============================================================================
630 extern __at(0x0018) __sfr T1CON
;
638 unsigned NOT_T1SYNC
: 1;
639 unsigned T1OSCEN
: 1;
640 unsigned T1CKPS0
: 1;
641 unsigned T1CKPS1
: 1;
642 unsigned TMR1CS0
: 1;
643 unsigned TMR1CS1
: 1;
660 extern __at(0x0018) volatile __T1CONbits_t T1CONbits
;
663 #define _NOT_T1SYNC 0x04
664 #define _T1OSCEN 0x08
665 #define _T1CKPS0 0x10
666 #define _T1CKPS1 0x20
667 #define _TMR1CS0 0x40
668 #define _TMR1CS1 0x80
670 //==============================================================================
673 //==============================================================================
676 extern __at(0x0019) __sfr T1GCON
;
685 unsigned T1GGO_NOT_DONE
: 1;
699 extern __at(0x0019) volatile __T1GCONbits_t T1GCONbits
;
704 #define _T1GGO_NOT_DONE 0x08
710 //==============================================================================
712 extern __at(0x001A) __sfr TMR2
;
713 extern __at(0x001B) __sfr PR2
;
715 //==============================================================================
718 extern __at(0x001C) __sfr T2CON
;
724 unsigned T2CKPS0
: 1;
725 unsigned T2CKPS1
: 1;
727 unsigned T2OUTPS0
: 1;
728 unsigned T2OUTPS1
: 1;
729 unsigned T2OUTPS2
: 1;
730 unsigned T2OUTPS3
: 1;
743 unsigned T2OUTPS
: 4;
748 extern __at(0x001C) volatile __T2CONbits_t T2CONbits
;
750 #define _T2CKPS0 0x01
751 #define _T2CKPS1 0x02
753 #define _T2OUTPS0 0x08
754 #define _T2OUTPS1 0x10
755 #define _T2OUTPS2 0x20
756 #define _T2OUTPS3 0x40
758 //==============================================================================
761 //==============================================================================
764 extern __at(0x008C) __sfr TRISA
;
778 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
786 //==============================================================================
789 //==============================================================================
792 extern __at(0x008D) __sfr TRISB
;
806 extern __at(0x008D) volatile __TRISBbits_t TRISBbits
;
813 //==============================================================================
816 //==============================================================================
819 extern __at(0x008E) __sfr TRISC
;
833 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
844 //==============================================================================
847 //==============================================================================
850 extern __at(0x0091) __sfr PIE1
;
863 unsigned TMR1GIE
: 1;
879 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
889 #define _TMR1GIE 0x80
891 //==============================================================================
894 //==============================================================================
897 extern __at(0x0092) __sfr PIE2
;
911 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
921 //==============================================================================
924 //==============================================================================
927 extern __at(0x0093) __sfr PIE3
;
941 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
949 //==============================================================================
952 //==============================================================================
955 extern __at(0x0095) __sfr OPTION_REG
;
968 unsigned NOT_WPUEN
: 1;
988 } __OPTION_REGbits_t
;
990 extern __at(0x0095) volatile __OPTION_REGbits_t OPTION_REGbits
;
1000 #define _INTEDG 0x40
1001 #define _NOT_WPUEN 0x80
1003 //==============================================================================
1006 //==============================================================================
1009 extern __at(0x0096) __sfr PCON
;
1013 unsigned NOT_BOR
: 1;
1014 unsigned NOT_POR
: 1;
1015 unsigned NOT_RI
: 1;
1016 unsigned NOT_RMCLR
: 1;
1017 unsigned NOT_RWDT
: 1;
1019 unsigned STKUNF
: 1;
1020 unsigned STKOVF
: 1;
1023 extern __at(0x0096) volatile __PCONbits_t PCONbits
;
1025 #define _NOT_BOR 0x01
1026 #define _NOT_POR 0x02
1027 #define _NOT_RI 0x04
1028 #define _NOT_RMCLR 0x08
1029 #define _NOT_RWDT 0x10
1030 #define _STKUNF 0x40
1031 #define _STKOVF 0x80
1033 //==============================================================================
1036 //==============================================================================
1039 extern __at(0x0097) __sfr WDTCON
;
1045 unsigned SWDTEN
: 1;
1046 unsigned WDTPS0
: 1;
1047 unsigned WDTPS1
: 1;
1048 unsigned WDTPS2
: 1;
1049 unsigned WDTPS3
: 1;
1050 unsigned WDTPS4
: 1;
1063 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1065 #define _SWDTEN 0x01
1066 #define _WDTPS0 0x02
1067 #define _WDTPS1 0x04
1068 #define _WDTPS2 0x08
1069 #define _WDTPS3 0x10
1070 #define _WDTPS4 0x20
1072 //==============================================================================
1075 //==============================================================================
1078 extern __at(0x0098) __sfr OSCTUNE
;
1101 extern __at(0x0098) volatile __OSCTUNEbits_t OSCTUNEbits
;
1110 //==============================================================================
1113 //==============================================================================
1116 extern __at(0x0099) __sfr OSCCON
;
1129 unsigned SPLLEN
: 1;
1146 extern __at(0x0099) volatile __OSCCONbits_t OSCCONbits
;
1154 #define _SPLLEN 0x80
1156 //==============================================================================
1159 //==============================================================================
1162 extern __at(0x009A) __sfr OSCSTAT
;
1166 unsigned HFIOFS
: 1;
1167 unsigned LFIOFR
: 1;
1168 unsigned MFIOFR
: 1;
1169 unsigned HFIOFL
: 1;
1170 unsigned HFIOFR
: 1;
1176 extern __at(0x009A) volatile __OSCSTATbits_t OSCSTATbits
;
1178 #define _HFIOFS 0x01
1179 #define _LFIOFR 0x02
1180 #define _MFIOFR 0x04
1181 #define _HFIOFL 0x08
1182 #define _HFIOFR 0x10
1187 //==============================================================================
1189 extern __at(0x009B) __sfr ADRES
;
1190 extern __at(0x009B) __sfr ADRESL
;
1191 extern __at(0x009C) __sfr ADRESH
;
1193 //==============================================================================
1196 extern __at(0x009D) __sfr ADCON0
;
1203 unsigned GO_NOT_DONE
: 1;
1244 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1247 #define _GO_NOT_DONE 0x02
1256 //==============================================================================
1259 //==============================================================================
1262 extern __at(0x009E) __sfr ADCON1
;
1268 unsigned ADPREF0
: 1;
1269 unsigned ADPREF1
: 1;
1270 unsigned ADNREF
: 1;
1280 unsigned ADPREF
: 2;
1292 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1294 #define _ADPREF0 0x01
1295 #define _ADPREF1 0x02
1296 #define _ADNREF 0x04
1302 //==============================================================================
1305 //==============================================================================
1308 extern __at(0x009F) __sfr ADCON2
;
1318 unsigned TRIGSEL0
: 1;
1319 unsigned TRIGSEL1
: 1;
1320 unsigned TRIGSEL2
: 1;
1321 unsigned TRIGSEL3
: 1;
1327 unsigned TRIGSEL
: 4;
1331 extern __at(0x009F) volatile __ADCON2bits_t ADCON2bits
;
1333 #define _TRIGSEL0 0x10
1334 #define _TRIGSEL1 0x20
1335 #define _TRIGSEL2 0x40
1336 #define _TRIGSEL3 0x80
1338 //==============================================================================
1341 //==============================================================================
1344 extern __at(0x010C) __sfr LATA
;
1358 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1366 //==============================================================================
1369 //==============================================================================
1372 extern __at(0x010D) __sfr LATB
;
1386 extern __at(0x010D) volatile __LATBbits_t LATBbits
;
1393 //==============================================================================
1396 //==============================================================================
1399 extern __at(0x010E) __sfr LATC
;
1413 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1424 //==============================================================================
1427 //==============================================================================
1430 extern __at(0x0111) __sfr CM1CON0
;
1434 unsigned C1SYNC
: 1;
1444 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1446 #define _C1SYNC 0x01
1454 //==============================================================================
1457 //==============================================================================
1460 extern __at(0x0112) __sfr CM1CON1
;
1466 unsigned C1NCH0
: 1;
1467 unsigned C1NCH1
: 1;
1468 unsigned C1NCH2
: 1;
1469 unsigned C1PCH0
: 1;
1470 unsigned C1PCH1
: 1;
1471 unsigned C1PCH2
: 1;
1472 unsigned C1INTN
: 1;
1473 unsigned C1INTP
: 1;
1490 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1492 #define _C1NCH0 0x01
1493 #define _C1NCH1 0x02
1494 #define _C1NCH2 0x04
1495 #define _C1PCH0 0x08
1496 #define _C1PCH1 0x10
1497 #define _C1PCH2 0x20
1498 #define _C1INTN 0x40
1499 #define _C1INTP 0x80
1501 //==============================================================================
1504 //==============================================================================
1507 extern __at(0x0113) __sfr CM2CON0
;
1511 unsigned C2SYNC
: 1;
1521 extern __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits
;
1523 #define _C2SYNC 0x01
1531 //==============================================================================
1534 //==============================================================================
1537 extern __at(0x0114) __sfr CM2CON1
;
1543 unsigned C2NCH0
: 1;
1544 unsigned C2NCH1
: 1;
1545 unsigned C2NCH2
: 1;
1546 unsigned C2PCH0
: 1;
1547 unsigned C2PCH1
: 1;
1548 unsigned C2PCH2
: 1;
1549 unsigned C2INTN
: 1;
1550 unsigned C2INTP
: 1;
1567 extern __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits
;
1569 #define _C2NCH0 0x01
1570 #define _C2NCH1 0x02
1571 #define _C2NCH2 0x04
1572 #define _C2PCH0 0x08
1573 #define _C2PCH1 0x10
1574 #define _C2PCH2 0x20
1575 #define _C2INTN 0x40
1576 #define _C2INTP 0x80
1578 //==============================================================================
1581 //==============================================================================
1584 extern __at(0x0115) __sfr CMOUT
;
1588 unsigned MC1OUT
: 1;
1589 unsigned MC2OUT
: 1;
1598 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1600 #define _MC1OUT 0x01
1601 #define _MC2OUT 0x02
1603 //==============================================================================
1606 //==============================================================================
1609 extern __at(0x0116) __sfr BORCON
;
1613 unsigned BORRDY
: 1;
1620 unsigned SBOREN
: 1;
1623 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1625 #define _BORRDY 0x01
1627 #define _SBOREN 0x80
1629 //==============================================================================
1632 //==============================================================================
1635 extern __at(0x0117) __sfr FVRCON
;
1641 unsigned ADFVR0
: 1;
1642 unsigned ADFVR1
: 1;
1643 unsigned CDAFVR0
: 1;
1644 unsigned CDAFVR1
: 1;
1647 unsigned FVRRDY
: 1;
1660 unsigned CDAFVR
: 2;
1665 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1667 #define _ADFVR0 0x01
1668 #define _ADFVR1 0x02
1669 #define _CDAFVR0 0x04
1670 #define _CDAFVR1 0x08
1673 #define _FVRRDY 0x40
1676 //==============================================================================
1679 //==============================================================================
1682 extern __at(0x0118) __sfr DAC1CON0
;
1688 unsigned DAC1NSS
: 1;
1690 unsigned DAC1PSS0
: 1;
1691 unsigned DAC1PSS1
: 1;
1692 unsigned DAC1OE2
: 1;
1693 unsigned DAC1OE1
: 1;
1695 unsigned DAC1EN
: 1;
1700 unsigned DACNSS
: 1;
1702 unsigned DACPSS0
: 1;
1703 unsigned DACPSS1
: 1;
1704 unsigned DACOE0
: 1;
1705 unsigned DACOE1
: 1;
1713 unsigned DACPSS
: 2;
1720 unsigned DAC1PSS
: 2;
1732 extern __at(0x0118) volatile __DAC1CON0bits_t DAC1CON0bits
;
1734 #define _DAC1NSS 0x01
1735 #define _DACNSS 0x01
1736 #define _DAC1PSS0 0x04
1737 #define _DACPSS0 0x04
1738 #define _DAC1PSS1 0x08
1739 #define _DACPSS1 0x08
1740 #define _DAC1OE2 0x10
1741 #define _DACOE0 0x10
1742 #define _DAC1OE1 0x20
1743 #define _DACOE1 0x20
1744 #define _DAC1EN 0x80
1747 //==============================================================================
1750 //==============================================================================
1753 extern __at(0x0119) __sfr DAC1CON1
;
1759 unsigned DAC1R0
: 1;
1760 unsigned DAC1R1
: 1;
1761 unsigned DAC1R2
: 1;
1762 unsigned DAC1R3
: 1;
1763 unsigned DAC1R4
: 1;
1764 unsigned DAC1R5
: 1;
1765 unsigned DAC1R6
: 1;
1766 unsigned DAC1R7
: 1;
1782 extern __at(0x0119) volatile __DAC1CON1bits_t DAC1CON1bits
;
1784 #define _DAC1R0 0x01
1786 #define _DAC1R1 0x02
1788 #define _DAC1R2 0x04
1790 #define _DAC1R3 0x08
1792 #define _DAC1R4 0x10
1794 #define _DAC1R5 0x20
1796 #define _DAC1R6 0x40
1798 #define _DAC1R7 0x80
1801 //==============================================================================
1804 //==============================================================================
1807 extern __at(0x011C) __sfr ZCD1CON
;
1811 unsigned ZCD1INTN
: 1;
1812 unsigned ZCD1INTP
: 1;
1815 unsigned ZCD1POL
: 1;
1816 unsigned ZCD1OUT
: 1;
1818 unsigned ZCD1EN
: 1;
1821 extern __at(0x011C) volatile __ZCD1CONbits_t ZCD1CONbits
;
1823 #define _ZCD1INTN 0x01
1824 #define _ZCD1INTP 0x02
1825 #define _ZCD1POL 0x10
1826 #define _ZCD1OUT 0x20
1827 #define _ZCD1EN 0x80
1829 //==============================================================================
1832 //==============================================================================
1835 extern __at(0x018C) __sfr ANSELA
;
1849 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1857 //==============================================================================
1860 //==============================================================================
1863 extern __at(0x018D) __sfr ANSELB
;
1877 extern __at(0x018D) volatile __ANSELBbits_t ANSELBbits
;
1884 //==============================================================================
1887 //==============================================================================
1890 extern __at(0x018E) __sfr ANSELC
;
1904 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
1913 //==============================================================================
1915 extern __at(0x0191) __sfr PMADR
;
1916 extern __at(0x0191) __sfr PMADRL
;
1917 extern __at(0x0192) __sfr PMADRH
;
1918 extern __at(0x0193) __sfr PMDAT
;
1919 extern __at(0x0193) __sfr PMDATL
;
1920 extern __at(0x0194) __sfr PMDATH
;
1922 //==============================================================================
1925 extern __at(0x0195) __sfr PMCON1
;
1939 extern __at(0x0195) volatile __PMCON1bits_t PMCON1bits
;
1949 //==============================================================================
1951 extern __at(0x0196) __sfr PMCON2
;
1953 //==============================================================================
1956 extern __at(0x0197) __sfr VREGCON
;
1960 unsigned Reserved
: 1;
1961 unsigned VREGPM
: 1;
1970 extern __at(0x0197) volatile __VREGCONbits_t VREGCONbits
;
1972 #define _Reserved 0x01
1973 #define _VREGPM 0x02
1975 //==============================================================================
1977 extern __at(0x0199) __sfr RC1REG
;
1978 extern __at(0x0199) __sfr RCREG
;
1979 extern __at(0x0199) __sfr RCREG1
;
1980 extern __at(0x019A) __sfr TX1REG
;
1981 extern __at(0x019A) __sfr TXREG
;
1982 extern __at(0x019A) __sfr TXREG1
;
1983 extern __at(0x019B) __sfr SP1BRG
;
1984 extern __at(0x019B) __sfr SP1BRGL
;
1985 extern __at(0x019B) __sfr SPBRG
;
1986 extern __at(0x019B) __sfr SPBRG1
;
1987 extern __at(0x019B) __sfr SPBRGL
;
1988 extern __at(0x019C) __sfr SP1BRGH
;
1989 extern __at(0x019C) __sfr SPBRGH
;
1990 extern __at(0x019C) __sfr SPBRGH1
;
1992 //==============================================================================
1995 extern __at(0x019D) __sfr RC1STA
;
2009 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
2020 //==============================================================================
2023 //==============================================================================
2026 extern __at(0x019D) __sfr RCSTA
;
2040 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
2042 #define _RCSTA_RX9D 0x01
2043 #define _RCSTA_OERR 0x02
2044 #define _RCSTA_FERR 0x04
2045 #define _RCSTA_ADDEN 0x08
2046 #define _RCSTA_CREN 0x10
2047 #define _RCSTA_SREN 0x20
2048 #define _RCSTA_RX9 0x40
2049 #define _RCSTA_SPEN 0x80
2051 //==============================================================================
2054 //==============================================================================
2057 extern __at(0x019D) __sfr RCSTA1
;
2071 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
2073 #define _RCSTA1_RX9D 0x01
2074 #define _RCSTA1_OERR 0x02
2075 #define _RCSTA1_FERR 0x04
2076 #define _RCSTA1_ADDEN 0x08
2077 #define _RCSTA1_CREN 0x10
2078 #define _RCSTA1_SREN 0x20
2079 #define _RCSTA1_RX9 0x40
2080 #define _RCSTA1_SPEN 0x80
2082 //==============================================================================
2085 //==============================================================================
2088 extern __at(0x019E) __sfr TX1STA
;
2102 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
2113 //==============================================================================
2116 //==============================================================================
2119 extern __at(0x019E) __sfr TXSTA
;
2133 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
2135 #define _TXSTA_TX9D 0x01
2136 #define _TXSTA_TRMT 0x02
2137 #define _TXSTA_BRGH 0x04
2138 #define _TXSTA_SENDB 0x08
2139 #define _TXSTA_SYNC 0x10
2140 #define _TXSTA_TXEN 0x20
2141 #define _TXSTA_TX9 0x40
2142 #define _TXSTA_CSRC 0x80
2144 //==============================================================================
2147 //==============================================================================
2150 extern __at(0x019E) __sfr TXSTA1
;
2164 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
2166 #define _TXSTA1_TX9D 0x01
2167 #define _TXSTA1_TRMT 0x02
2168 #define _TXSTA1_BRGH 0x04
2169 #define _TXSTA1_SENDB 0x08
2170 #define _TXSTA1_SYNC 0x10
2171 #define _TXSTA1_TXEN 0x20
2172 #define _TXSTA1_TX9 0x40
2173 #define _TXSTA1_CSRC 0x80
2175 //==============================================================================
2178 //==============================================================================
2181 extern __at(0x019F) __sfr BAUD1CON
;
2192 unsigned ABDOVF
: 1;
2195 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
2202 #define _ABDOVF 0x80
2204 //==============================================================================
2207 //==============================================================================
2210 extern __at(0x019F) __sfr BAUDCON
;
2221 unsigned ABDOVF
: 1;
2224 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
2226 #define _BAUDCON_ABDEN 0x01
2227 #define _BAUDCON_WUE 0x02
2228 #define _BAUDCON_BRG16 0x08
2229 #define _BAUDCON_SCKP 0x10
2230 #define _BAUDCON_RCIDL 0x40
2231 #define _BAUDCON_ABDOVF 0x80
2233 //==============================================================================
2236 //==============================================================================
2239 extern __at(0x019F) __sfr BAUDCON1
;
2250 unsigned ABDOVF
: 1;
2253 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
2255 #define _BAUDCON1_ABDEN 0x01
2256 #define _BAUDCON1_WUE 0x02
2257 #define _BAUDCON1_BRG16 0x08
2258 #define _BAUDCON1_SCKP 0x10
2259 #define _BAUDCON1_RCIDL 0x40
2260 #define _BAUDCON1_ABDOVF 0x80
2262 //==============================================================================
2265 //==============================================================================
2268 extern __at(0x019F) __sfr BAUDCTL
;
2279 unsigned ABDOVF
: 1;
2282 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
2284 #define _BAUDCTL_ABDEN 0x01
2285 #define _BAUDCTL_WUE 0x02
2286 #define _BAUDCTL_BRG16 0x08
2287 #define _BAUDCTL_SCKP 0x10
2288 #define _BAUDCTL_RCIDL 0x40
2289 #define _BAUDCTL_ABDOVF 0x80
2291 //==============================================================================
2294 //==============================================================================
2297 extern __at(0x019F) __sfr BAUDCTL1
;
2308 unsigned ABDOVF
: 1;
2311 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
2313 #define _BAUDCTL1_ABDEN 0x01
2314 #define _BAUDCTL1_WUE 0x02
2315 #define _BAUDCTL1_BRG16 0x08
2316 #define _BAUDCTL1_SCKP 0x10
2317 #define _BAUDCTL1_RCIDL 0x40
2318 #define _BAUDCTL1_ABDOVF 0x80
2320 //==============================================================================
2323 //==============================================================================
2326 extern __at(0x020C) __sfr WPUA
;
2349 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
2358 //==============================================================================
2361 //==============================================================================
2364 extern __at(0x020D) __sfr WPUB
;
2378 extern __at(0x020D) volatile __WPUBbits_t WPUBbits
;
2385 //==============================================================================
2388 //==============================================================================
2391 extern __at(0x020E) __sfr WPUC
;
2405 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
2416 //==============================================================================
2419 //==============================================================================
2422 extern __at(0x0211) __sfr SSP1BUF
;
2428 unsigned SSP1BUF0
: 1;
2429 unsigned SSP1BUF1
: 1;
2430 unsigned SSP1BUF2
: 1;
2431 unsigned SSP1BUF3
: 1;
2432 unsigned SSP1BUF4
: 1;
2433 unsigned SSP1BUF5
: 1;
2434 unsigned SSP1BUF6
: 1;
2435 unsigned SSP1BUF7
: 1;
2451 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
2453 #define _SSP1BUF0 0x01
2455 #define _SSP1BUF1 0x02
2457 #define _SSP1BUF2 0x04
2459 #define _SSP1BUF3 0x08
2461 #define _SSP1BUF4 0x10
2463 #define _SSP1BUF5 0x20
2465 #define _SSP1BUF6 0x40
2467 #define _SSP1BUF7 0x80
2470 //==============================================================================
2473 //==============================================================================
2476 extern __at(0x0211) __sfr SSPBUF
;
2482 unsigned SSP1BUF0
: 1;
2483 unsigned SSP1BUF1
: 1;
2484 unsigned SSP1BUF2
: 1;
2485 unsigned SSP1BUF3
: 1;
2486 unsigned SSP1BUF4
: 1;
2487 unsigned SSP1BUF5
: 1;
2488 unsigned SSP1BUF6
: 1;
2489 unsigned SSP1BUF7
: 1;
2505 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
2507 #define _SSPBUF_SSP1BUF0 0x01
2508 #define _SSPBUF_BUF0 0x01
2509 #define _SSPBUF_SSP1BUF1 0x02
2510 #define _SSPBUF_BUF1 0x02
2511 #define _SSPBUF_SSP1BUF2 0x04
2512 #define _SSPBUF_BUF2 0x04
2513 #define _SSPBUF_SSP1BUF3 0x08
2514 #define _SSPBUF_BUF3 0x08
2515 #define _SSPBUF_SSP1BUF4 0x10
2516 #define _SSPBUF_BUF4 0x10
2517 #define _SSPBUF_SSP1BUF5 0x20
2518 #define _SSPBUF_BUF5 0x20
2519 #define _SSPBUF_SSP1BUF6 0x40
2520 #define _SSPBUF_BUF6 0x40
2521 #define _SSPBUF_SSP1BUF7 0x80
2522 #define _SSPBUF_BUF7 0x80
2524 //==============================================================================
2527 //==============================================================================
2530 extern __at(0x0212) __sfr SSP1ADD
;
2536 unsigned SSP1ADD0
: 1;
2537 unsigned SSP1ADD1
: 1;
2538 unsigned SSP1ADD2
: 1;
2539 unsigned SSP1ADD3
: 1;
2540 unsigned SSP1ADD4
: 1;
2541 unsigned SSP1ADD5
: 1;
2542 unsigned SSP1ADD6
: 1;
2543 unsigned SSP1ADD7
: 1;
2559 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
2561 #define _SSP1ADD0 0x01
2563 #define _SSP1ADD1 0x02
2565 #define _SSP1ADD2 0x04
2567 #define _SSP1ADD3 0x08
2569 #define _SSP1ADD4 0x10
2571 #define _SSP1ADD5 0x20
2573 #define _SSP1ADD6 0x40
2575 #define _SSP1ADD7 0x80
2578 //==============================================================================
2581 //==============================================================================
2584 extern __at(0x0212) __sfr SSPADD
;
2590 unsigned SSP1ADD0
: 1;
2591 unsigned SSP1ADD1
: 1;
2592 unsigned SSP1ADD2
: 1;
2593 unsigned SSP1ADD3
: 1;
2594 unsigned SSP1ADD4
: 1;
2595 unsigned SSP1ADD5
: 1;
2596 unsigned SSP1ADD6
: 1;
2597 unsigned SSP1ADD7
: 1;
2613 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
2615 #define _SSPADD_SSP1ADD0 0x01
2616 #define _SSPADD_ADD0 0x01
2617 #define _SSPADD_SSP1ADD1 0x02
2618 #define _SSPADD_ADD1 0x02
2619 #define _SSPADD_SSP1ADD2 0x04
2620 #define _SSPADD_ADD2 0x04
2621 #define _SSPADD_SSP1ADD3 0x08
2622 #define _SSPADD_ADD3 0x08
2623 #define _SSPADD_SSP1ADD4 0x10
2624 #define _SSPADD_ADD4 0x10
2625 #define _SSPADD_SSP1ADD5 0x20
2626 #define _SSPADD_ADD5 0x20
2627 #define _SSPADD_SSP1ADD6 0x40
2628 #define _SSPADD_ADD6 0x40
2629 #define _SSPADD_SSP1ADD7 0x80
2630 #define _SSPADD_ADD7 0x80
2632 //==============================================================================
2635 //==============================================================================
2638 extern __at(0x0213) __sfr SSP1MSK
;
2644 unsigned SSP1MSK0
: 1;
2645 unsigned SSP1MSK1
: 1;
2646 unsigned SSP1MSK2
: 1;
2647 unsigned SSP1MSK3
: 1;
2648 unsigned SSP1MSK4
: 1;
2649 unsigned SSP1MSK5
: 1;
2650 unsigned SSP1MSK6
: 1;
2651 unsigned SSP1MSK7
: 1;
2667 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
2669 #define _SSP1MSK0 0x01
2671 #define _SSP1MSK1 0x02
2673 #define _SSP1MSK2 0x04
2675 #define _SSP1MSK3 0x08
2677 #define _SSP1MSK4 0x10
2679 #define _SSP1MSK5 0x20
2681 #define _SSP1MSK6 0x40
2683 #define _SSP1MSK7 0x80
2686 //==============================================================================
2689 //==============================================================================
2692 extern __at(0x0213) __sfr SSPMSK
;
2698 unsigned SSP1MSK0
: 1;
2699 unsigned SSP1MSK1
: 1;
2700 unsigned SSP1MSK2
: 1;
2701 unsigned SSP1MSK3
: 1;
2702 unsigned SSP1MSK4
: 1;
2703 unsigned SSP1MSK5
: 1;
2704 unsigned SSP1MSK6
: 1;
2705 unsigned SSP1MSK7
: 1;
2721 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
2723 #define _SSPMSK_SSP1MSK0 0x01
2724 #define _SSPMSK_MSK0 0x01
2725 #define _SSPMSK_SSP1MSK1 0x02
2726 #define _SSPMSK_MSK1 0x02
2727 #define _SSPMSK_SSP1MSK2 0x04
2728 #define _SSPMSK_MSK2 0x04
2729 #define _SSPMSK_SSP1MSK3 0x08
2730 #define _SSPMSK_MSK3 0x08
2731 #define _SSPMSK_SSP1MSK4 0x10
2732 #define _SSPMSK_MSK4 0x10
2733 #define _SSPMSK_SSP1MSK5 0x20
2734 #define _SSPMSK_MSK5 0x20
2735 #define _SSPMSK_SSP1MSK6 0x40
2736 #define _SSPMSK_MSK6 0x40
2737 #define _SSPMSK_SSP1MSK7 0x80
2738 #define _SSPMSK_MSK7 0x80
2740 //==============================================================================
2743 //==============================================================================
2746 extern __at(0x0214) __sfr SSP1STAT
;
2752 unsigned R_NOT_W
: 1;
2755 unsigned D_NOT_A
: 1;
2760 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
2764 #define _R_NOT_W 0x04
2767 #define _D_NOT_A 0x20
2771 //==============================================================================
2774 //==============================================================================
2777 extern __at(0x0214) __sfr SSPSTAT
;
2783 unsigned R_NOT_W
: 1;
2786 unsigned D_NOT_A
: 1;
2791 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
2793 #define _SSPSTAT_BF 0x01
2794 #define _SSPSTAT_UA 0x02
2795 #define _SSPSTAT_R_NOT_W 0x04
2796 #define _SSPSTAT_S 0x08
2797 #define _SSPSTAT_P 0x10
2798 #define _SSPSTAT_D_NOT_A 0x20
2799 #define _SSPSTAT_CKE 0x40
2800 #define _SSPSTAT_SMP 0x80
2802 //==============================================================================
2805 //==============================================================================
2808 extern __at(0x0215) __sfr SSP1CON
;
2831 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
2842 //==============================================================================
2845 //==============================================================================
2848 extern __at(0x0215) __sfr SSP1CON1
;
2871 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
2873 #define _SSP1CON1_SSPM0 0x01
2874 #define _SSP1CON1_SSPM1 0x02
2875 #define _SSP1CON1_SSPM2 0x04
2876 #define _SSP1CON1_SSPM3 0x08
2877 #define _SSP1CON1_CKP 0x10
2878 #define _SSP1CON1_SSPEN 0x20
2879 #define _SSP1CON1_SSPOV 0x40
2880 #define _SSP1CON1_WCOL 0x80
2882 //==============================================================================
2885 //==============================================================================
2888 extern __at(0x0215) __sfr SSPCON
;
2911 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2913 #define _SSPCON_SSPM0 0x01
2914 #define _SSPCON_SSPM1 0x02
2915 #define _SSPCON_SSPM2 0x04
2916 #define _SSPCON_SSPM3 0x08
2917 #define _SSPCON_CKP 0x10
2918 #define _SSPCON_SSPEN 0x20
2919 #define _SSPCON_SSPOV 0x40
2920 #define _SSPCON_WCOL 0x80
2922 //==============================================================================
2925 //==============================================================================
2928 extern __at(0x0215) __sfr SSPCON1
;
2951 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2953 #define _SSPCON1_SSPM0 0x01
2954 #define _SSPCON1_SSPM1 0x02
2955 #define _SSPCON1_SSPM2 0x04
2956 #define _SSPCON1_SSPM3 0x08
2957 #define _SSPCON1_CKP 0x10
2958 #define _SSPCON1_SSPEN 0x20
2959 #define _SSPCON1_SSPOV 0x40
2960 #define _SSPCON1_WCOL 0x80
2962 //==============================================================================
2965 //==============================================================================
2968 extern __at(0x0216) __sfr SSP1CON2
;
2978 unsigned ACKSTAT
: 1;
2982 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
2990 #define _ACKSTAT 0x40
2993 //==============================================================================
2996 //==============================================================================
2999 extern __at(0x0216) __sfr SSPCON2
;
3009 unsigned ACKSTAT
: 1;
3013 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
3015 #define _SSPCON2_SEN 0x01
3016 #define _SSPCON2_RSEN 0x02
3017 #define _SSPCON2_PEN 0x04
3018 #define _SSPCON2_RCEN 0x08
3019 #define _SSPCON2_ACKEN 0x10
3020 #define _SSPCON2_ACKDT 0x20
3021 #define _SSPCON2_ACKSTAT 0x40
3022 #define _SSPCON2_GCEN 0x80
3024 //==============================================================================
3027 //==============================================================================
3030 extern __at(0x0217) __sfr SSP1CON3
;
3041 unsigned ACKTIM
: 1;
3044 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
3053 #define _ACKTIM 0x80
3055 //==============================================================================
3058 //==============================================================================
3061 extern __at(0x0217) __sfr SSPCON3
;
3072 unsigned ACKTIM
: 1;
3075 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
3077 #define _SSPCON3_DHEN 0x01
3078 #define _SSPCON3_AHEN 0x02
3079 #define _SSPCON3_SBCDE 0x04
3080 #define _SSPCON3_SDAHT 0x08
3081 #define _SSPCON3_BOEN 0x10
3082 #define _SSPCON3_SCIE 0x20
3083 #define _SSPCON3_PCIE 0x40
3084 #define _SSPCON3_ACKTIM 0x80
3086 //==============================================================================
3089 //==============================================================================
3092 extern __at(0x028C) __sfr ODCONA
;
3106 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
3114 //==============================================================================
3117 //==============================================================================
3120 extern __at(0x028D) __sfr ODCONB
;
3134 extern __at(0x028D) volatile __ODCONBbits_t ODCONBbits
;
3141 //==============================================================================
3144 //==============================================================================
3147 extern __at(0x028E) __sfr ODCONC
;
3161 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
3172 //==============================================================================
3174 extern __at(0x0291) __sfr CCPR1
;
3175 extern __at(0x0291) __sfr CCPR1L
;
3176 extern __at(0x0292) __sfr CCPR1H
;
3178 //==============================================================================
3181 extern __at(0x0293) __sfr CCP1CON
;
3187 unsigned CCP1M0
: 1;
3188 unsigned CCP1M1
: 1;
3189 unsigned CCP1M2
: 1;
3190 unsigned CCP1M3
: 1;
3223 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
3225 #define _CCP1M0 0x01
3226 #define _CCP1M1 0x02
3227 #define _CCP1M2 0x04
3228 #define _CCP1M3 0x08
3234 //==============================================================================
3237 //==============================================================================
3240 extern __at(0x0293) __sfr ECCP1CON
;
3246 unsigned CCP1M0
: 1;
3247 unsigned CCP1M1
: 1;
3248 unsigned CCP1M2
: 1;
3249 unsigned CCP1M3
: 1;
3282 extern __at(0x0293) volatile __ECCP1CONbits_t ECCP1CONbits
;
3284 #define _ECCP1CON_CCP1M0 0x01
3285 #define _ECCP1CON_CCP1M1 0x02
3286 #define _ECCP1CON_CCP1M2 0x04
3287 #define _ECCP1CON_CCP1M3 0x08
3288 #define _ECCP1CON_DC1B0 0x10
3289 #define _ECCP1CON_CCP1Y 0x10
3290 #define _ECCP1CON_DC1B1 0x20
3291 #define _ECCP1CON_CCP1X 0x20
3293 //==============================================================================
3295 extern __at(0x0298) __sfr CCPR2
;
3296 extern __at(0x0298) __sfr CCPR2L
;
3297 extern __at(0x0299) __sfr CCPR2H
;
3299 //==============================================================================
3302 extern __at(0x029A) __sfr CCP2CON
;
3308 unsigned CCP2M0
: 1;
3309 unsigned CCP2M1
: 1;
3310 unsigned CCP2M2
: 1;
3311 unsigned CCP2M3
: 1;
3344 extern __at(0x029A) volatile __CCP2CONbits_t CCP2CONbits
;
3346 #define _CCP2M0 0x01
3347 #define _CCP2M1 0x02
3348 #define _CCP2M2 0x04
3349 #define _CCP2M3 0x08
3355 //==============================================================================
3358 //==============================================================================
3361 extern __at(0x029A) __sfr ECCP2CON
;
3367 unsigned CCP2M0
: 1;
3368 unsigned CCP2M1
: 1;
3369 unsigned CCP2M2
: 1;
3370 unsigned CCP2M3
: 1;
3403 extern __at(0x029A) volatile __ECCP2CONbits_t ECCP2CONbits
;
3405 #define _ECCP2CON_CCP2M0 0x01
3406 #define _ECCP2CON_CCP2M1 0x02
3407 #define _ECCP2CON_CCP2M2 0x04
3408 #define _ECCP2CON_CCP2M3 0x08
3409 #define _ECCP2CON_DC2B0 0x10
3410 #define _ECCP2CON_CCP2Y 0x10
3411 #define _ECCP2CON_DC2B1 0x20
3412 #define _ECCP2CON_CCP2X 0x20
3414 //==============================================================================
3417 //==============================================================================
3420 extern __at(0x029E) __sfr CCPTMRS
;
3426 unsigned C1TSEL0
: 1;
3427 unsigned C1TSEL1
: 1;
3428 unsigned C2TSEL0
: 1;
3429 unsigned C2TSEL1
: 1;
3430 unsigned P3TSEL0
: 1;
3431 unsigned P3TSEL1
: 1;
3432 unsigned P4TSEL0
: 1;
3433 unsigned P4TSEL1
: 1;
3438 unsigned C1TSEL
: 2;
3445 unsigned C2TSEL
: 2;
3452 unsigned P3TSEL
: 2;
3459 unsigned P4TSEL
: 2;
3463 extern __at(0x029E) volatile __CCPTMRSbits_t CCPTMRSbits
;
3465 #define _C1TSEL0 0x01
3466 #define _C1TSEL1 0x02
3467 #define _C2TSEL0 0x04
3468 #define _C2TSEL1 0x08
3469 #define _P3TSEL0 0x10
3470 #define _P3TSEL1 0x20
3471 #define _P4TSEL0 0x40
3472 #define _P4TSEL1 0x80
3474 //==============================================================================
3477 //==============================================================================
3480 extern __at(0x030C) __sfr SLRCONA
;
3494 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
3502 //==============================================================================
3505 //==============================================================================
3508 extern __at(0x030D) __sfr SLRCONB
;
3522 extern __at(0x030D) volatile __SLRCONBbits_t SLRCONBbits
;
3529 //==============================================================================
3532 //==============================================================================
3535 extern __at(0x030E) __sfr SLRCONC
;
3549 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
3560 //==============================================================================
3563 //==============================================================================
3566 extern __at(0x038C) __sfr INLVLA
;
3572 unsigned INLVLA0
: 1;
3573 unsigned INLVLA1
: 1;
3574 unsigned INLVLA2
: 1;
3575 unsigned INLVLA3
: 1;
3576 unsigned INLVLA4
: 1;
3577 unsigned INLVLA5
: 1;
3584 unsigned INLVLA
: 6;
3589 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
3591 #define _INLVLA0 0x01
3592 #define _INLVLA1 0x02
3593 #define _INLVLA2 0x04
3594 #define _INLVLA3 0x08
3595 #define _INLVLA4 0x10
3596 #define _INLVLA5 0x20
3598 //==============================================================================
3601 //==============================================================================
3604 extern __at(0x038D) __sfr INLVLB
;
3612 unsigned INLVLB4
: 1;
3613 unsigned INLVLB5
: 1;
3614 unsigned INLVLB6
: 1;
3615 unsigned INLVLB7
: 1;
3618 extern __at(0x038D) volatile __INLVLBbits_t INLVLBbits
;
3620 #define _INLVLB4 0x10
3621 #define _INLVLB5 0x20
3622 #define _INLVLB6 0x40
3623 #define _INLVLB7 0x80
3625 //==============================================================================
3628 //==============================================================================
3631 extern __at(0x038E) __sfr INLVLC
;
3635 unsigned INLVLC0
: 1;
3636 unsigned INLVLC1
: 1;
3637 unsigned INLVLC2
: 1;
3638 unsigned INLVLC3
: 1;
3639 unsigned INLVLC4
: 1;
3640 unsigned INLVLC5
: 1;
3641 unsigned INLVLC6
: 1;
3642 unsigned INLVLC7
: 1;
3645 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
3647 #define _INLVLC0 0x01
3648 #define _INLVLC1 0x02
3649 #define _INLVLC2 0x04
3650 #define _INLVLC3 0x08
3651 #define _INLVLC4 0x10
3652 #define _INLVLC5 0x20
3653 #define _INLVLC6 0x40
3654 #define _INLVLC7 0x80
3656 //==============================================================================
3659 //==============================================================================
3662 extern __at(0x0391) __sfr IOCAP
;
3668 unsigned IOCAP0
: 1;
3669 unsigned IOCAP1
: 1;
3670 unsigned IOCAP2
: 1;
3671 unsigned IOCAP3
: 1;
3672 unsigned IOCAP4
: 1;
3673 unsigned IOCAP5
: 1;
3685 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
3687 #define _IOCAP0 0x01
3688 #define _IOCAP1 0x02
3689 #define _IOCAP2 0x04
3690 #define _IOCAP3 0x08
3691 #define _IOCAP4 0x10
3692 #define _IOCAP5 0x20
3694 //==============================================================================
3697 //==============================================================================
3700 extern __at(0x0392) __sfr IOCAN
;
3706 unsigned IOCAN0
: 1;
3707 unsigned IOCAN1
: 1;
3708 unsigned IOCAN2
: 1;
3709 unsigned IOCAN3
: 1;
3710 unsigned IOCAN4
: 1;
3711 unsigned IOCAN5
: 1;
3723 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
3725 #define _IOCAN0 0x01
3726 #define _IOCAN1 0x02
3727 #define _IOCAN2 0x04
3728 #define _IOCAN3 0x08
3729 #define _IOCAN4 0x10
3730 #define _IOCAN5 0x20
3732 //==============================================================================
3735 //==============================================================================
3738 extern __at(0x0393) __sfr IOCAF
;
3744 unsigned IOCAF0
: 1;
3745 unsigned IOCAF1
: 1;
3746 unsigned IOCAF2
: 1;
3747 unsigned IOCAF3
: 1;
3748 unsigned IOCAF4
: 1;
3749 unsigned IOCAF5
: 1;
3761 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
3763 #define _IOCAF0 0x01
3764 #define _IOCAF1 0x02
3765 #define _IOCAF2 0x04
3766 #define _IOCAF3 0x08
3767 #define _IOCAF4 0x10
3768 #define _IOCAF5 0x20
3770 //==============================================================================
3773 //==============================================================================
3776 extern __at(0x0394) __sfr IOCBP
;
3784 unsigned IOCBP4
: 1;
3785 unsigned IOCBP5
: 1;
3786 unsigned IOCBP6
: 1;
3787 unsigned IOCBP7
: 1;
3790 extern __at(0x0394) volatile __IOCBPbits_t IOCBPbits
;
3792 #define _IOCBP4 0x10
3793 #define _IOCBP5 0x20
3794 #define _IOCBP6 0x40
3795 #define _IOCBP7 0x80
3797 //==============================================================================
3800 //==============================================================================
3803 extern __at(0x0395) __sfr IOCBN
;
3811 unsigned IOCBN4
: 1;
3812 unsigned IOCBN5
: 1;
3813 unsigned IOCBN6
: 1;
3814 unsigned IOCBN7
: 1;
3817 extern __at(0x0395) volatile __IOCBNbits_t IOCBNbits
;
3819 #define _IOCBN4 0x10
3820 #define _IOCBN5 0x20
3821 #define _IOCBN6 0x40
3822 #define _IOCBN7 0x80
3824 //==============================================================================
3827 //==============================================================================
3830 extern __at(0x0396) __sfr IOCBF
;
3838 unsigned IOCBF4
: 1;
3839 unsigned IOCBF5
: 1;
3840 unsigned IOCBF6
: 1;
3841 unsigned IOCBF7
: 1;
3844 extern __at(0x0396) volatile __IOCBFbits_t IOCBFbits
;
3846 #define _IOCBF4 0x10
3847 #define _IOCBF5 0x20
3848 #define _IOCBF6 0x40
3849 #define _IOCBF7 0x80
3851 //==============================================================================
3854 //==============================================================================
3857 extern __at(0x0397) __sfr IOCCP
;
3861 unsigned IOCCP0
: 1;
3862 unsigned IOCCP1
: 1;
3863 unsigned IOCCP2
: 1;
3864 unsigned IOCCP3
: 1;
3865 unsigned IOCCP4
: 1;
3866 unsigned IOCCP5
: 1;
3867 unsigned IOCCP6
: 1;
3868 unsigned IOCCP7
: 1;
3871 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
3873 #define _IOCCP0 0x01
3874 #define _IOCCP1 0x02
3875 #define _IOCCP2 0x04
3876 #define _IOCCP3 0x08
3877 #define _IOCCP4 0x10
3878 #define _IOCCP5 0x20
3879 #define _IOCCP6 0x40
3880 #define _IOCCP7 0x80
3882 //==============================================================================
3885 //==============================================================================
3888 extern __at(0x0398) __sfr IOCCN
;
3892 unsigned IOCCN0
: 1;
3893 unsigned IOCCN1
: 1;
3894 unsigned IOCCN2
: 1;
3895 unsigned IOCCN3
: 1;
3896 unsigned IOCCN4
: 1;
3897 unsigned IOCCN5
: 1;
3898 unsigned IOCCN6
: 1;
3899 unsigned IOCCN7
: 1;
3902 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
3904 #define _IOCCN0 0x01
3905 #define _IOCCN1 0x02
3906 #define _IOCCN2 0x04
3907 #define _IOCCN3 0x08
3908 #define _IOCCN4 0x10
3909 #define _IOCCN5 0x20
3910 #define _IOCCN6 0x40
3911 #define _IOCCN7 0x80
3913 //==============================================================================
3916 //==============================================================================
3919 extern __at(0x0399) __sfr IOCCF
;
3923 unsigned IOCCF0
: 1;
3924 unsigned IOCCF1
: 1;
3925 unsigned IOCCF2
: 1;
3926 unsigned IOCCF3
: 1;
3927 unsigned IOCCF4
: 1;
3928 unsigned IOCCF5
: 1;
3929 unsigned IOCCF6
: 1;
3930 unsigned IOCCF7
: 1;
3933 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
3935 #define _IOCCF0 0x01
3936 #define _IOCCF1 0x02
3937 #define _IOCCF2 0x04
3938 #define _IOCCF3 0x08
3939 #define _IOCCF4 0x10
3940 #define _IOCCF5 0x20
3941 #define _IOCCF6 0x40
3942 #define _IOCCF7 0x80
3944 //==============================================================================
3946 extern __at(0x0415) __sfr TMR4
;
3947 extern __at(0x0416) __sfr PR4
;
3949 //==============================================================================
3952 extern __at(0x0417) __sfr T4CON
;
3958 unsigned T4CKPS0
: 1;
3959 unsigned T4CKPS1
: 1;
3960 unsigned TMR4ON
: 1;
3961 unsigned T4OUTPS0
: 1;
3962 unsigned T4OUTPS1
: 1;
3963 unsigned T4OUTPS2
: 1;
3964 unsigned T4OUTPS3
: 1;
3970 unsigned T4CKPS
: 2;
3977 unsigned T4OUTPS
: 4;
3982 extern __at(0x0417) volatile __T4CONbits_t T4CONbits
;
3984 #define _T4CKPS0 0x01
3985 #define _T4CKPS1 0x02
3986 #define _TMR4ON 0x04
3987 #define _T4OUTPS0 0x08
3988 #define _T4OUTPS1 0x10
3989 #define _T4OUTPS2 0x20
3990 #define _T4OUTPS3 0x40
3992 //==============================================================================
3994 extern __at(0x041C) __sfr TMR6
;
3995 extern __at(0x041D) __sfr PR6
;
3997 //==============================================================================
4000 extern __at(0x041E) __sfr T6CON
;
4006 unsigned T6CKPS0
: 1;
4007 unsigned T6CKPS1
: 1;
4008 unsigned TMR6ON
: 1;
4009 unsigned T6OUTPS0
: 1;
4010 unsigned T6OUTPS1
: 1;
4011 unsigned T6OUTPS2
: 1;
4012 unsigned T6OUTPS3
: 1;
4018 unsigned T6CKPS
: 2;
4025 unsigned T6OUTPS
: 4;
4030 extern __at(0x041E) volatile __T6CONbits_t T6CONbits
;
4032 #define _T6CKPS0 0x01
4033 #define _T6CKPS1 0x02
4034 #define _TMR6ON 0x04
4035 #define _T6OUTPS0 0x08
4036 #define _T6OUTPS1 0x10
4037 #define _T6OUTPS2 0x20
4038 #define _T6OUTPS3 0x40
4040 //==============================================================================
4043 //==============================================================================
4046 extern __at(0x0511) __sfr OPA1CON
;
4052 unsigned OPA1PCH0
: 1;
4053 unsigned OPA1PCH1
: 1;
4056 unsigned OPA1UG
: 1;
4058 unsigned OPA1SP
: 1;
4059 unsigned OPA1EN
: 1;
4064 unsigned OPA1PCH
: 2;
4069 extern __at(0x0511) volatile __OPA1CONbits_t OPA1CONbits
;
4071 #define _OPA1PCH0 0x01
4072 #define _OPA1PCH1 0x02
4073 #define _OPA1UG 0x10
4074 #define _OPA1SP 0x40
4075 #define _OPA1EN 0x80
4077 //==============================================================================
4080 //==============================================================================
4083 extern __at(0x0515) __sfr OPA2CON
;
4089 unsigned OPA2PCH0
: 1;
4090 unsigned OPA2PCH1
: 1;
4093 unsigned OPA2UG
: 1;
4095 unsigned OPA2SP
: 1;
4096 unsigned OPA2EN
: 1;
4101 unsigned OPA2PCH
: 2;
4106 extern __at(0x0515) volatile __OPA2CONbits_t OPA2CONbits
;
4108 #define _OPA2PCH0 0x01
4109 #define _OPA2PCH1 0x02
4110 #define _OPA2UG 0x10
4111 #define _OPA2SP 0x40
4112 #define _OPA2EN 0x80
4114 //==============================================================================
4117 //==============================================================================
4120 extern __at(0x0617) __sfr PWM3DCL
;
4132 unsigned PWM3DCL0
: 1;
4133 unsigned PWM3DCL1
: 1;
4139 unsigned PWM3DCL
: 2;
4143 extern __at(0x0617) volatile __PWM3DCLbits_t PWM3DCLbits
;
4145 #define _PWM3DCL0 0x40
4146 #define _PWM3DCL1 0x80
4148 //==============================================================================
4151 //==============================================================================
4154 extern __at(0x0618) __sfr PWM3DCH
;
4158 unsigned PWM3DCH0
: 1;
4159 unsigned PWM3DCH1
: 1;
4160 unsigned PWM3DCH2
: 1;
4161 unsigned PWM3DCH3
: 1;
4162 unsigned PWM3DCH4
: 1;
4163 unsigned PWM3DCH5
: 1;
4164 unsigned PWM3DCH6
: 1;
4165 unsigned PWM3DCH7
: 1;
4168 extern __at(0x0618) volatile __PWM3DCHbits_t PWM3DCHbits
;
4170 #define _PWM3DCH0 0x01
4171 #define _PWM3DCH1 0x02
4172 #define _PWM3DCH2 0x04
4173 #define _PWM3DCH3 0x08
4174 #define _PWM3DCH4 0x10
4175 #define _PWM3DCH5 0x20
4176 #define _PWM3DCH6 0x40
4177 #define _PWM3DCH7 0x80
4179 //==============================================================================
4182 //==============================================================================
4185 extern __at(0x0619) __sfr PWM3CON
;
4193 unsigned PWM3POL
: 1;
4194 unsigned PWM3OUT
: 1;
4196 unsigned PWM3EN
: 1;
4199 extern __at(0x0619) volatile __PWM3CONbits_t PWM3CONbits
;
4201 #define _PWM3POL 0x10
4202 #define _PWM3OUT 0x20
4203 #define _PWM3EN 0x80
4205 //==============================================================================
4208 //==============================================================================
4211 extern __at(0x0619) __sfr PWM3CON0
;
4219 unsigned PWM3POL
: 1;
4220 unsigned PWM3OUT
: 1;
4222 unsigned PWM3EN
: 1;
4225 extern __at(0x0619) volatile __PWM3CON0bits_t PWM3CON0bits
;
4227 #define _PWM3CON0_PWM3POL 0x10
4228 #define _PWM3CON0_PWM3OUT 0x20
4229 #define _PWM3CON0_PWM3EN 0x80
4231 //==============================================================================
4234 //==============================================================================
4237 extern __at(0x061A) __sfr PWM4DCL
;
4249 unsigned PWM4DCL0
: 1;
4250 unsigned PWM4DCL1
: 1;
4256 unsigned PWM4DCL
: 2;
4260 extern __at(0x061A) volatile __PWM4DCLbits_t PWM4DCLbits
;
4262 #define _PWM4DCL0 0x40
4263 #define _PWM4DCL1 0x80
4265 //==============================================================================
4268 //==============================================================================
4271 extern __at(0x061B) __sfr PWM4DCH
;
4275 unsigned PWM4DCH0
: 1;
4276 unsigned PWM4DCH1
: 1;
4277 unsigned PWM4DCH2
: 1;
4278 unsigned PWM4DCH3
: 1;
4279 unsigned PWM4DCH4
: 1;
4280 unsigned PWM4DCH5
: 1;
4281 unsigned PWM4DCH6
: 1;
4282 unsigned PWM4DCH7
: 1;
4285 extern __at(0x061B) volatile __PWM4DCHbits_t PWM4DCHbits
;
4287 #define _PWM4DCH0 0x01
4288 #define _PWM4DCH1 0x02
4289 #define _PWM4DCH2 0x04
4290 #define _PWM4DCH3 0x08
4291 #define _PWM4DCH4 0x10
4292 #define _PWM4DCH5 0x20
4293 #define _PWM4DCH6 0x40
4294 #define _PWM4DCH7 0x80
4296 //==============================================================================
4299 //==============================================================================
4302 extern __at(0x061C) __sfr PWM4CON
;
4310 unsigned PWM4POL
: 1;
4311 unsigned PWM4OUT
: 1;
4313 unsigned PWM4EN
: 1;
4316 extern __at(0x061C) volatile __PWM4CONbits_t PWM4CONbits
;
4318 #define _PWM4POL 0x10
4319 #define _PWM4OUT 0x20
4320 #define _PWM4EN 0x80
4322 //==============================================================================
4325 //==============================================================================
4328 extern __at(0x061C) __sfr PWM4CON0
;
4336 unsigned PWM4POL
: 1;
4337 unsigned PWM4OUT
: 1;
4339 unsigned PWM4EN
: 1;
4342 extern __at(0x061C) volatile __PWM4CON0bits_t PWM4CON0bits
;
4344 #define _PWM4CON0_PWM4POL 0x10
4345 #define _PWM4CON0_PWM4OUT 0x20
4346 #define _PWM4CON0_PWM4EN 0x80
4348 //==============================================================================
4351 //==============================================================================
4354 extern __at(0x0691) __sfr COG1PHR
;
4360 unsigned G1PHR0
: 1;
4361 unsigned G1PHR1
: 1;
4362 unsigned G1PHR2
: 1;
4363 unsigned G1PHR3
: 1;
4364 unsigned G1PHR4
: 1;
4365 unsigned G1PHR5
: 1;
4377 extern __at(0x0691) volatile __COG1PHRbits_t COG1PHRbits
;
4379 #define _G1PHR0 0x01
4380 #define _G1PHR1 0x02
4381 #define _G1PHR2 0x04
4382 #define _G1PHR3 0x08
4383 #define _G1PHR4 0x10
4384 #define _G1PHR5 0x20
4386 //==============================================================================
4389 //==============================================================================
4392 extern __at(0x0692) __sfr COG1PHF
;
4398 unsigned G1PHF0
: 1;
4399 unsigned G1PHF1
: 1;
4400 unsigned G1PHF2
: 1;
4401 unsigned G1PHF3
: 1;
4402 unsigned G1PHF4
: 1;
4403 unsigned G1PHF5
: 1;
4415 extern __at(0x0692) volatile __COG1PHFbits_t COG1PHFbits
;
4417 #define _G1PHF0 0x01
4418 #define _G1PHF1 0x02
4419 #define _G1PHF2 0x04
4420 #define _G1PHF3 0x08
4421 #define _G1PHF4 0x10
4422 #define _G1PHF5 0x20
4424 //==============================================================================
4427 //==============================================================================
4430 extern __at(0x0693) __sfr COG1BLKR
;
4436 unsigned G1BLKR0
: 1;
4437 unsigned G1BLKR1
: 1;
4438 unsigned G1BLKR2
: 1;
4439 unsigned G1BLKR3
: 1;
4440 unsigned G1BLKR4
: 1;
4441 unsigned G1BLKR5
: 1;
4448 unsigned G1BLKR
: 6;
4453 extern __at(0x0693) volatile __COG1BLKRbits_t COG1BLKRbits
;
4455 #define _G1BLKR0 0x01
4456 #define _G1BLKR1 0x02
4457 #define _G1BLKR2 0x04
4458 #define _G1BLKR3 0x08
4459 #define _G1BLKR4 0x10
4460 #define _G1BLKR5 0x20
4462 //==============================================================================
4465 //==============================================================================
4468 extern __at(0x0694) __sfr COG1BLKF
;
4474 unsigned G1BLKF0
: 1;
4475 unsigned G1BLKF1
: 1;
4476 unsigned G1BLKF2
: 1;
4477 unsigned G1BLKF3
: 1;
4478 unsigned G1BLKF4
: 1;
4479 unsigned G1BLKF5
: 1;
4486 unsigned G1BLKF
: 6;
4491 extern __at(0x0694) volatile __COG1BLKFbits_t COG1BLKFbits
;
4493 #define _G1BLKF0 0x01
4494 #define _G1BLKF1 0x02
4495 #define _G1BLKF2 0x04
4496 #define _G1BLKF3 0x08
4497 #define _G1BLKF4 0x10
4498 #define _G1BLKF5 0x20
4500 //==============================================================================
4503 //==============================================================================
4506 extern __at(0x0695) __sfr COG1DBR
;
4512 unsigned G1DBR0
: 1;
4513 unsigned G1DBR1
: 1;
4514 unsigned G1DBR2
: 1;
4515 unsigned G1DBR3
: 1;
4516 unsigned G1DBR4
: 1;
4517 unsigned G1DBR5
: 1;
4529 extern __at(0x0695) volatile __COG1DBRbits_t COG1DBRbits
;
4531 #define _G1DBR0 0x01
4532 #define _G1DBR1 0x02
4533 #define _G1DBR2 0x04
4534 #define _G1DBR3 0x08
4535 #define _G1DBR4 0x10
4536 #define _G1DBR5 0x20
4538 //==============================================================================
4541 //==============================================================================
4544 extern __at(0x0696) __sfr COG1DBF
;
4550 unsigned G1DBF0
: 1;
4551 unsigned G1DBF1
: 1;
4552 unsigned G1DBF2
: 1;
4553 unsigned G1DBF3
: 1;
4554 unsigned G1DBF4
: 1;
4555 unsigned G1DBF5
: 1;
4567 extern __at(0x0696) volatile __COG1DBFbits_t COG1DBFbits
;
4569 #define _G1DBF0 0x01
4570 #define _G1DBF1 0x02
4571 #define _G1DBF2 0x04
4572 #define _G1DBF3 0x08
4573 #define _G1DBF4 0x10
4574 #define _G1DBF5 0x20
4576 //==============================================================================
4579 //==============================================================================
4582 extern __at(0x0697) __sfr COG1CON0
;
4612 extern __at(0x0697) volatile __COG1CON0bits_t COG1CON0bits
;
4622 //==============================================================================
4625 //==============================================================================
4628 extern __at(0x0698) __sfr COG1CON1
;
4632 unsigned G1POLA
: 1;
4633 unsigned G1POLB
: 1;
4634 unsigned G1POLC
: 1;
4635 unsigned G1POLD
: 1;
4638 unsigned G1FDBS
: 1;
4639 unsigned G1RDBS
: 1;
4642 extern __at(0x0698) volatile __COG1CON1bits_t COG1CON1bits
;
4644 #define _G1POLA 0x01
4645 #define _G1POLB 0x02
4646 #define _G1POLC 0x04
4647 #define _G1POLD 0x08
4648 #define _G1FDBS 0x40
4649 #define _G1RDBS 0x80
4651 //==============================================================================
4654 //==============================================================================
4657 extern __at(0x0699) __sfr COG1RIS
;
4663 unsigned G1RIS0
: 1;
4664 unsigned G1RIS1
: 1;
4665 unsigned G1RIS2
: 1;
4666 unsigned G1RIS3
: 1;
4667 unsigned G1RIS4
: 1;
4668 unsigned G1RIS5
: 1;
4669 unsigned G1RIS6
: 1;
4680 extern __at(0x0699) volatile __COG1RISbits_t COG1RISbits
;
4682 #define _G1RIS0 0x01
4683 #define _G1RIS1 0x02
4684 #define _G1RIS2 0x04
4685 #define _G1RIS3 0x08
4686 #define _G1RIS4 0x10
4687 #define _G1RIS5 0x20
4688 #define _G1RIS6 0x40
4690 //==============================================================================
4693 //==============================================================================
4696 extern __at(0x069A) __sfr COG1RSIM
;
4702 unsigned G1RSIM0
: 1;
4703 unsigned G1RSIM1
: 1;
4704 unsigned G1RSIM2
: 1;
4705 unsigned G1RSIM3
: 1;
4706 unsigned G1RSIM4
: 1;
4707 unsigned G1RSIM5
: 1;
4708 unsigned G1RSIM6
: 1;
4714 unsigned G1RSIM
: 7;
4719 extern __at(0x069A) volatile __COG1RSIMbits_t COG1RSIMbits
;
4721 #define _G1RSIM0 0x01
4722 #define _G1RSIM1 0x02
4723 #define _G1RSIM2 0x04
4724 #define _G1RSIM3 0x08
4725 #define _G1RSIM4 0x10
4726 #define _G1RSIM5 0x20
4727 #define _G1RSIM6 0x40
4729 //==============================================================================
4732 //==============================================================================
4735 extern __at(0x069B) __sfr COG1FIS
;
4741 unsigned G1FIS0
: 1;
4742 unsigned G1FIS1
: 1;
4743 unsigned G1FIS2
: 1;
4744 unsigned G1FIS3
: 1;
4745 unsigned G1FIS4
: 1;
4746 unsigned G1FIS5
: 1;
4747 unsigned G1FIS6
: 1;
4758 extern __at(0x069B) volatile __COG1FISbits_t COG1FISbits
;
4760 #define _G1FIS0 0x01
4761 #define _G1FIS1 0x02
4762 #define _G1FIS2 0x04
4763 #define _G1FIS3 0x08
4764 #define _G1FIS4 0x10
4765 #define _G1FIS5 0x20
4766 #define _G1FIS6 0x40
4768 //==============================================================================
4771 //==============================================================================
4774 extern __at(0x069C) __sfr COG1FSIM
;
4780 unsigned G1FSIM0
: 1;
4781 unsigned G1FSIM1
: 1;
4782 unsigned G1FSIM2
: 1;
4783 unsigned G1FSIM3
: 1;
4784 unsigned G1FSIM4
: 1;
4785 unsigned G1FSIM5
: 1;
4786 unsigned G1FSIM6
: 1;
4792 unsigned G1FSIM
: 7;
4797 extern __at(0x069C) volatile __COG1FSIMbits_t COG1FSIMbits
;
4799 #define _G1FSIM0 0x01
4800 #define _G1FSIM1 0x02
4801 #define _G1FSIM2 0x04
4802 #define _G1FSIM3 0x08
4803 #define _G1FSIM4 0x10
4804 #define _G1FSIM5 0x20
4805 #define _G1FSIM6 0x40
4807 //==============================================================================
4810 //==============================================================================
4813 extern __at(0x069D) __sfr COG1ASD0
;
4821 unsigned G1ASDAC0
: 1;
4822 unsigned G1ASDAC1
: 1;
4823 unsigned G1ASDBD0
: 1;
4824 unsigned G1ASDBD1
: 1;
4825 unsigned G1ARSEN
: 1;
4832 unsigned G1ASDAC
: 2;
4839 unsigned G1ASDBD
: 2;
4844 extern __at(0x069D) volatile __COG1ASD0bits_t COG1ASD0bits
;
4846 #define _G1ASDAC0 0x04
4847 #define _G1ASDAC1 0x08
4848 #define _G1ASDBD0 0x10
4849 #define _G1ASDBD1 0x20
4850 #define _G1ARSEN 0x40
4853 //==============================================================================
4856 //==============================================================================
4859 extern __at(0x069E) __sfr COG1ASD1
;
4863 unsigned G1AS0E
: 1;
4864 unsigned G1AS1E
: 1;
4865 unsigned G1AS2E
: 1;
4866 unsigned G1AS3E
: 1;
4873 extern __at(0x069E) volatile __COG1ASD1bits_t COG1ASD1bits
;
4875 #define _G1AS0E 0x01
4876 #define _G1AS1E 0x02
4877 #define _G1AS2E 0x04
4878 #define _G1AS3E 0x08
4880 //==============================================================================
4883 //==============================================================================
4886 extern __at(0x069F) __sfr COG1STR
;
4890 unsigned G1STRA
: 1;
4891 unsigned G1STRB
: 1;
4892 unsigned G1STRC
: 1;
4893 unsigned G1STRD
: 1;
4894 unsigned G1SDATA
: 1;
4895 unsigned G1SDATB
: 1;
4896 unsigned G1SDATC
: 1;
4897 unsigned G1SDATD
: 1;
4900 extern __at(0x069F) volatile __COG1STRbits_t COG1STRbits
;
4902 #define _G1STRA 0x01
4903 #define _G1STRB 0x02
4904 #define _G1STRC 0x04
4905 #define _G1STRD 0x08
4906 #define _G1SDATA 0x10
4907 #define _G1SDATB 0x20
4908 #define _G1SDATC 0x40
4909 #define _G1SDATD 0x80
4911 //==============================================================================
4914 //==============================================================================
4917 extern __at(0x0E0F) __sfr PPSLOCK
;
4921 unsigned PPSLOCKED
: 1;
4931 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
4933 #define _PPSLOCKED 0x01
4935 //==============================================================================
4937 extern __at(0x0E10) __sfr INTPPS
;
4938 extern __at(0x0E11) __sfr T0CKIPPS
;
4939 extern __at(0x0E12) __sfr T1CKIPPS
;
4940 extern __at(0x0E13) __sfr T1GPPS
;
4941 extern __at(0x0E14) __sfr CCP1PPS
;
4942 extern __at(0x0E15) __sfr CCP2PPS
;
4943 extern __at(0x0E17) __sfr COGINPPS
;
4944 extern __at(0x0E20) __sfr SSPCLKPPS
;
4945 extern __at(0x0E21) __sfr SSPDATPPS
;
4946 extern __at(0x0E22) __sfr SSPSSPPS
;
4947 extern __at(0x0E24) __sfr RXPPS
;
4948 extern __at(0x0E25) __sfr CKPPS
;
4949 extern __at(0x0E28) __sfr CLCIN0PPS
;
4950 extern __at(0x0E29) __sfr CLCIN1PPS
;
4951 extern __at(0x0E2A) __sfr CLCIN2PPS
;
4952 extern __at(0x0E2B) __sfr CLCIN3PPS
;
4953 extern __at(0x0E90) __sfr RA0PPS
;
4954 extern __at(0x0E91) __sfr RA1PPS
;
4955 extern __at(0x0E92) __sfr RA2PPS
;
4956 extern __at(0x0E94) __sfr RA4PPS
;
4957 extern __at(0x0E95) __sfr RA5PPS
;
4958 extern __at(0x0E9C) __sfr RB4PPS
;
4959 extern __at(0x0E9D) __sfr RB5PPS
;
4960 extern __at(0x0E9E) __sfr RB6PPS
;
4961 extern __at(0x0E9F) __sfr RB7PPS
;
4962 extern __at(0x0EA0) __sfr RC0PPS
;
4963 extern __at(0x0EA1) __sfr RC1PPS
;
4964 extern __at(0x0EA2) __sfr RC2PPS
;
4965 extern __at(0x0EA3) __sfr RC3PPS
;
4966 extern __at(0x0EA4) __sfr RC4PPS
;
4967 extern __at(0x0EA5) __sfr RC5PPS
;
4968 extern __at(0x0EA6) __sfr RC6PPS
;
4969 extern __at(0x0EA7) __sfr RC7PPS
;
4971 //==============================================================================
4974 extern __at(0x0F0F) __sfr CLCDATA
;
4978 unsigned MCLC1OUT
: 1;
4979 unsigned MCLC2OUT
: 1;
4980 unsigned MCLC3OUT
: 1;
4988 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
4990 #define _MCLC1OUT 0x01
4991 #define _MCLC2OUT 0x02
4992 #define _MCLC3OUT 0x04
4994 //==============================================================================
4997 //==============================================================================
5000 extern __at(0x0F10) __sfr CLC1CON
;
5006 unsigned LC1MODE0
: 1;
5007 unsigned LC1MODE1
: 1;
5008 unsigned LC1MODE2
: 1;
5009 unsigned LC1INTN
: 1;
5010 unsigned LC1INTP
: 1;
5011 unsigned LC1OUT
: 1;
5030 unsigned LC1MODE
: 3;
5041 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
5043 #define _LC1MODE0 0x01
5045 #define _LC1MODE1 0x02
5047 #define _LC1MODE2 0x04
5049 #define _LC1INTN 0x08
5051 #define _LC1INTP 0x10
5053 #define _LC1OUT 0x20
5058 //==============================================================================
5061 //==============================================================================
5064 extern __at(0x0F11) __sfr CLC1POL
;
5070 unsigned LC1G1POL
: 1;
5071 unsigned LC1G2POL
: 1;
5072 unsigned LC1G3POL
: 1;
5073 unsigned LC1G4POL
: 1;
5077 unsigned LC1POL
: 1;
5093 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
5095 #define _LC1G1POL 0x01
5097 #define _LC1G2POL 0x02
5099 #define _LC1G3POL 0x04
5101 #define _LC1G4POL 0x08
5103 #define _LC1POL 0x80
5106 //==============================================================================
5109 //==============================================================================
5112 extern __at(0x0F12) __sfr CLC1SEL0
;
5118 unsigned LC1D1S0
: 1;
5119 unsigned LC1D1S1
: 1;
5120 unsigned LC1D1S2
: 1;
5121 unsigned LC1D1S3
: 1;
5122 unsigned LC1D1S4
: 1;
5142 unsigned LC1D1S
: 5;
5153 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
5155 #define _LC1D1S0 0x01
5157 #define _LC1D1S1 0x02
5159 #define _LC1D1S2 0x04
5161 #define _LC1D1S3 0x08
5163 #define _LC1D1S4 0x10
5166 //==============================================================================
5169 //==============================================================================
5172 extern __at(0x0F13) __sfr CLC1SEL1
;
5178 unsigned LC1D2S0
: 1;
5179 unsigned LC1D2S1
: 1;
5180 unsigned LC1D2S2
: 1;
5181 unsigned LC1D2S3
: 1;
5182 unsigned LC1D2S4
: 1;
5208 unsigned LC1D2S
: 5;
5213 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
5215 #define _LC1D2S0 0x01
5217 #define _LC1D2S1 0x02
5219 #define _LC1D2S2 0x04
5221 #define _LC1D2S3 0x08
5223 #define _LC1D2S4 0x10
5226 //==============================================================================
5229 //==============================================================================
5232 extern __at(0x0F14) __sfr CLC1SEL2
;
5238 unsigned LC1D3S0
: 1;
5239 unsigned LC1D3S1
: 1;
5240 unsigned LC1D3S2
: 1;
5241 unsigned LC1D3S3
: 1;
5242 unsigned LC1D3S4
: 1;
5268 unsigned LC1D3S
: 5;
5273 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
5275 #define _LC1D3S0 0x01
5277 #define _LC1D3S1 0x02
5279 #define _LC1D3S2 0x04
5281 #define _LC1D3S3 0x08
5283 #define _LC1D3S4 0x10
5286 //==============================================================================
5289 //==============================================================================
5292 extern __at(0x0F15) __sfr CLC1SEL3
;
5298 unsigned LC1D4S0
: 1;
5299 unsigned LC1D4S1
: 1;
5300 unsigned LC1D4S2
: 1;
5301 unsigned LC1D4S3
: 1;
5302 unsigned LC1D4S4
: 1;
5322 unsigned LC1D4S
: 5;
5333 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
5335 #define _LC1D4S0 0x01
5337 #define _LC1D4S1 0x02
5339 #define _LC1D4S2 0x04
5341 #define _LC1D4S3 0x08
5343 #define _LC1D4S4 0x10
5346 //==============================================================================
5349 //==============================================================================
5352 extern __at(0x0F16) __sfr CLC1GLS0
;
5358 unsigned LC1G1D1N
: 1;
5359 unsigned LC1G1D1T
: 1;
5360 unsigned LC1G1D2N
: 1;
5361 unsigned LC1G1D2T
: 1;
5362 unsigned LC1G1D3N
: 1;
5363 unsigned LC1G1D3T
: 1;
5364 unsigned LC1G1D4N
: 1;
5365 unsigned LC1G1D4T
: 1;
5381 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
5383 #define _LC1G1D1N 0x01
5385 #define _LC1G1D1T 0x02
5387 #define _LC1G1D2N 0x04
5389 #define _LC1G1D2T 0x08
5391 #define _LC1G1D3N 0x10
5393 #define _LC1G1D3T 0x20
5395 #define _LC1G1D4N 0x40
5397 #define _LC1G1D4T 0x80
5400 //==============================================================================
5403 //==============================================================================
5406 extern __at(0x0F17) __sfr CLC1GLS1
;
5412 unsigned LC1G2D1N
: 1;
5413 unsigned LC1G2D1T
: 1;
5414 unsigned LC1G2D2N
: 1;
5415 unsigned LC1G2D2T
: 1;
5416 unsigned LC1G2D3N
: 1;
5417 unsigned LC1G2D3T
: 1;
5418 unsigned LC1G2D4N
: 1;
5419 unsigned LC1G2D4T
: 1;
5435 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
5437 #define _CLC1GLS1_LC1G2D1N 0x01
5438 #define _CLC1GLS1_D1N 0x01
5439 #define _CLC1GLS1_LC1G2D1T 0x02
5440 #define _CLC1GLS1_D1T 0x02
5441 #define _CLC1GLS1_LC1G2D2N 0x04
5442 #define _CLC1GLS1_D2N 0x04
5443 #define _CLC1GLS1_LC1G2D2T 0x08
5444 #define _CLC1GLS1_D2T 0x08
5445 #define _CLC1GLS1_LC1G2D3N 0x10
5446 #define _CLC1GLS1_D3N 0x10
5447 #define _CLC1GLS1_LC1G2D3T 0x20
5448 #define _CLC1GLS1_D3T 0x20
5449 #define _CLC1GLS1_LC1G2D4N 0x40
5450 #define _CLC1GLS1_D4N 0x40
5451 #define _CLC1GLS1_LC1G2D4T 0x80
5452 #define _CLC1GLS1_D4T 0x80
5454 //==============================================================================
5457 //==============================================================================
5460 extern __at(0x0F18) __sfr CLC1GLS2
;
5466 unsigned LC1G3D1N
: 1;
5467 unsigned LC1G3D1T
: 1;
5468 unsigned LC1G3D2N
: 1;
5469 unsigned LC1G3D2T
: 1;
5470 unsigned LC1G3D3N
: 1;
5471 unsigned LC1G3D3T
: 1;
5472 unsigned LC1G3D4N
: 1;
5473 unsigned LC1G3D4T
: 1;
5489 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
5491 #define _CLC1GLS2_LC1G3D1N 0x01
5492 #define _CLC1GLS2_D1N 0x01
5493 #define _CLC1GLS2_LC1G3D1T 0x02
5494 #define _CLC1GLS2_D1T 0x02
5495 #define _CLC1GLS2_LC1G3D2N 0x04
5496 #define _CLC1GLS2_D2N 0x04
5497 #define _CLC1GLS2_LC1G3D2T 0x08
5498 #define _CLC1GLS2_D2T 0x08
5499 #define _CLC1GLS2_LC1G3D3N 0x10
5500 #define _CLC1GLS2_D3N 0x10
5501 #define _CLC1GLS2_LC1G3D3T 0x20
5502 #define _CLC1GLS2_D3T 0x20
5503 #define _CLC1GLS2_LC1G3D4N 0x40
5504 #define _CLC1GLS2_D4N 0x40
5505 #define _CLC1GLS2_LC1G3D4T 0x80
5506 #define _CLC1GLS2_D4T 0x80
5508 //==============================================================================
5511 //==============================================================================
5514 extern __at(0x0F19) __sfr CLC1GLS3
;
5520 unsigned LC1G4D1N
: 1;
5521 unsigned LC1G4D1T
: 1;
5522 unsigned LC1G4D2N
: 1;
5523 unsigned LC1G4D2T
: 1;
5524 unsigned LC1G4D3N
: 1;
5525 unsigned LC1G4D3T
: 1;
5526 unsigned LC1G4D4N
: 1;
5527 unsigned LC1G4D4T
: 1;
5543 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
5545 #define _LC1G4D1N 0x01
5547 #define _LC1G4D1T 0x02
5549 #define _LC1G4D2N 0x04
5551 #define _LC1G4D2T 0x08
5553 #define _LC1G4D3N 0x10
5555 #define _LC1G4D3T 0x20
5557 #define _LC1G4D4N 0x40
5559 #define _LC1G4D4T 0x80
5562 //==============================================================================
5565 //==============================================================================
5568 extern __at(0x0F1A) __sfr CLC2CON
;
5574 unsigned LC2MODE0
: 1;
5575 unsigned LC2MODE1
: 1;
5576 unsigned LC2MODE2
: 1;
5577 unsigned LC2INTN
: 1;
5578 unsigned LC2INTP
: 1;
5579 unsigned LC2OUT
: 1;
5598 unsigned LC2MODE
: 3;
5609 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
5611 #define _CLC2CON_LC2MODE0 0x01
5612 #define _CLC2CON_MODE0 0x01
5613 #define _CLC2CON_LC2MODE1 0x02
5614 #define _CLC2CON_MODE1 0x02
5615 #define _CLC2CON_LC2MODE2 0x04
5616 #define _CLC2CON_MODE2 0x04
5617 #define _CLC2CON_LC2INTN 0x08
5618 #define _CLC2CON_INTN 0x08
5619 #define _CLC2CON_LC2INTP 0x10
5620 #define _CLC2CON_INTP 0x10
5621 #define _CLC2CON_LC2OUT 0x20
5622 #define _CLC2CON_OUT 0x20
5623 #define _CLC2CON_LC2EN 0x80
5624 #define _CLC2CON_EN 0x80
5626 //==============================================================================
5629 //==============================================================================
5632 extern __at(0x0F1B) __sfr CLC2POL
;
5638 unsigned LC2G1POL
: 1;
5639 unsigned LC2G2POL
: 1;
5640 unsigned LC2G3POL
: 1;
5641 unsigned LC2G4POL
: 1;
5645 unsigned LC2POL
: 1;
5661 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
5663 #define _CLC2POL_LC2G1POL 0x01
5664 #define _CLC2POL_G1POL 0x01
5665 #define _CLC2POL_LC2G2POL 0x02
5666 #define _CLC2POL_G2POL 0x02
5667 #define _CLC2POL_LC2G3POL 0x04
5668 #define _CLC2POL_G3POL 0x04
5669 #define _CLC2POL_LC2G4POL 0x08
5670 #define _CLC2POL_G4POL 0x08
5671 #define _CLC2POL_LC2POL 0x80
5672 #define _CLC2POL_POL 0x80
5674 //==============================================================================
5677 //==============================================================================
5680 extern __at(0x0F1C) __sfr CLC2SEL0
;
5686 unsigned LC2D1S0
: 1;
5687 unsigned LC2D1S1
: 1;
5688 unsigned LC2D1S2
: 1;
5689 unsigned LC2D1S3
: 1;
5690 unsigned LC2D1S4
: 1;
5710 unsigned LC2D1S
: 5;
5721 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
5723 #define _CLC2SEL0_LC2D1S0 0x01
5724 #define _CLC2SEL0_D1S0 0x01
5725 #define _CLC2SEL0_LC2D1S1 0x02
5726 #define _CLC2SEL0_D1S1 0x02
5727 #define _CLC2SEL0_LC2D1S2 0x04
5728 #define _CLC2SEL0_D1S2 0x04
5729 #define _CLC2SEL0_LC2D1S3 0x08
5730 #define _CLC2SEL0_D1S3 0x08
5731 #define _CLC2SEL0_LC2D1S4 0x10
5732 #define _CLC2SEL0_D1S4 0x10
5734 //==============================================================================
5737 //==============================================================================
5740 extern __at(0x0F1D) __sfr CLC2SEL1
;
5746 unsigned LC2D2S0
: 1;
5747 unsigned LC2D2S1
: 1;
5748 unsigned LC2D2S2
: 1;
5749 unsigned LC2D2S3
: 1;
5750 unsigned LC2D2S4
: 1;
5770 unsigned LC2D2S
: 5;
5781 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
5783 #define _CLC2SEL1_LC2D2S0 0x01
5784 #define _CLC2SEL1_D2S0 0x01
5785 #define _CLC2SEL1_LC2D2S1 0x02
5786 #define _CLC2SEL1_D2S1 0x02
5787 #define _CLC2SEL1_LC2D2S2 0x04
5788 #define _CLC2SEL1_D2S2 0x04
5789 #define _CLC2SEL1_LC2D2S3 0x08
5790 #define _CLC2SEL1_D2S3 0x08
5791 #define _CLC2SEL1_LC2D2S4 0x10
5792 #define _CLC2SEL1_D2S4 0x10
5794 //==============================================================================
5797 //==============================================================================
5800 extern __at(0x0F1E) __sfr CLC2SEL2
;
5806 unsigned LC2D3S0
: 1;
5807 unsigned LC2D3S1
: 1;
5808 unsigned LC2D3S2
: 1;
5809 unsigned LC2D3S3
: 1;
5810 unsigned LC2D3S4
: 1;
5830 unsigned LC2D3S
: 5;
5841 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
5843 #define _CLC2SEL2_LC2D3S0 0x01
5844 #define _CLC2SEL2_D3S0 0x01
5845 #define _CLC2SEL2_LC2D3S1 0x02
5846 #define _CLC2SEL2_D3S1 0x02
5847 #define _CLC2SEL2_LC2D3S2 0x04
5848 #define _CLC2SEL2_D3S2 0x04
5849 #define _CLC2SEL2_LC2D3S3 0x08
5850 #define _CLC2SEL2_D3S3 0x08
5851 #define _CLC2SEL2_LC2D3S4 0x10
5852 #define _CLC2SEL2_D3S4 0x10
5854 //==============================================================================
5857 //==============================================================================
5860 extern __at(0x0F1F) __sfr CLC2SEL3
;
5866 unsigned LC2D4S0
: 1;
5867 unsigned LC2D4S1
: 1;
5868 unsigned LC2D4S2
: 1;
5869 unsigned LC2D4S3
: 1;
5870 unsigned LC2D4S4
: 1;
5896 unsigned LC2D4S
: 5;
5901 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
5903 #define _CLC2SEL3_LC2D4S0 0x01
5904 #define _CLC2SEL3_D4S0 0x01
5905 #define _CLC2SEL3_LC2D4S1 0x02
5906 #define _CLC2SEL3_D4S1 0x02
5907 #define _CLC2SEL3_LC2D4S2 0x04
5908 #define _CLC2SEL3_D4S2 0x04
5909 #define _CLC2SEL3_LC2D4S3 0x08
5910 #define _CLC2SEL3_D4S3 0x08
5911 #define _CLC2SEL3_LC2D4S4 0x10
5912 #define _CLC2SEL3_D4S4 0x10
5914 //==============================================================================
5917 //==============================================================================
5920 extern __at(0x0F20) __sfr CLC2GLS0
;
5926 unsigned LC2G1D1N
: 1;
5927 unsigned LC2G1D1T
: 1;
5928 unsigned LC2G1D2N
: 1;
5929 unsigned LC2G1D2T
: 1;
5930 unsigned LC2G1D3N
: 1;
5931 unsigned LC2G1D3T
: 1;
5932 unsigned LC2G1D4N
: 1;
5933 unsigned LC2G1D4T
: 1;
5949 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
5951 #define _CLC2GLS0_LC2G1D1N 0x01
5952 #define _CLC2GLS0_D1N 0x01
5953 #define _CLC2GLS0_LC2G1D1T 0x02
5954 #define _CLC2GLS0_D1T 0x02
5955 #define _CLC2GLS0_LC2G1D2N 0x04
5956 #define _CLC2GLS0_D2N 0x04
5957 #define _CLC2GLS0_LC2G1D2T 0x08
5958 #define _CLC2GLS0_D2T 0x08
5959 #define _CLC2GLS0_LC2G1D3N 0x10
5960 #define _CLC2GLS0_D3N 0x10
5961 #define _CLC2GLS0_LC2G1D3T 0x20
5962 #define _CLC2GLS0_D3T 0x20
5963 #define _CLC2GLS0_LC2G1D4N 0x40
5964 #define _CLC2GLS0_D4N 0x40
5965 #define _CLC2GLS0_LC2G1D4T 0x80
5966 #define _CLC2GLS0_D4T 0x80
5968 //==============================================================================
5971 //==============================================================================
5974 extern __at(0x0F21) __sfr CLC2GLS1
;
5980 unsigned LC2G2D1N
: 1;
5981 unsigned LC2G2D1T
: 1;
5982 unsigned LC2G2D2N
: 1;
5983 unsigned LC2G2D2T
: 1;
5984 unsigned LC2G2D3N
: 1;
5985 unsigned LC2G2D3T
: 1;
5986 unsigned LC2G2D4N
: 1;
5987 unsigned LC2G2D4T
: 1;
6003 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
6005 #define _CLC2GLS1_LC2G2D1N 0x01
6006 #define _CLC2GLS1_D1N 0x01
6007 #define _CLC2GLS1_LC2G2D1T 0x02
6008 #define _CLC2GLS1_D1T 0x02
6009 #define _CLC2GLS1_LC2G2D2N 0x04
6010 #define _CLC2GLS1_D2N 0x04
6011 #define _CLC2GLS1_LC2G2D2T 0x08
6012 #define _CLC2GLS1_D2T 0x08
6013 #define _CLC2GLS1_LC2G2D3N 0x10
6014 #define _CLC2GLS1_D3N 0x10
6015 #define _CLC2GLS1_LC2G2D3T 0x20
6016 #define _CLC2GLS1_D3T 0x20
6017 #define _CLC2GLS1_LC2G2D4N 0x40
6018 #define _CLC2GLS1_D4N 0x40
6019 #define _CLC2GLS1_LC2G2D4T 0x80
6020 #define _CLC2GLS1_D4T 0x80
6022 //==============================================================================
6025 //==============================================================================
6028 extern __at(0x0F22) __sfr CLC2GLS2
;
6034 unsigned LC2G3D1N
: 1;
6035 unsigned LC2G3D1T
: 1;
6036 unsigned LC2G3D2N
: 1;
6037 unsigned LC2G3D2T
: 1;
6038 unsigned LC2G3D3N
: 1;
6039 unsigned LC2G3D3T
: 1;
6040 unsigned LC2G3D4N
: 1;
6041 unsigned LC2G3D4T
: 1;
6057 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
6059 #define _CLC2GLS2_LC2G3D1N 0x01
6060 #define _CLC2GLS2_D1N 0x01
6061 #define _CLC2GLS2_LC2G3D1T 0x02
6062 #define _CLC2GLS2_D1T 0x02
6063 #define _CLC2GLS2_LC2G3D2N 0x04
6064 #define _CLC2GLS2_D2N 0x04
6065 #define _CLC2GLS2_LC2G3D2T 0x08
6066 #define _CLC2GLS2_D2T 0x08
6067 #define _CLC2GLS2_LC2G3D3N 0x10
6068 #define _CLC2GLS2_D3N 0x10
6069 #define _CLC2GLS2_LC2G3D3T 0x20
6070 #define _CLC2GLS2_D3T 0x20
6071 #define _CLC2GLS2_LC2G3D4N 0x40
6072 #define _CLC2GLS2_D4N 0x40
6073 #define _CLC2GLS2_LC2G3D4T 0x80
6074 #define _CLC2GLS2_D4T 0x80
6076 //==============================================================================
6079 //==============================================================================
6082 extern __at(0x0F23) __sfr CLC2GLS3
;
6088 unsigned LC2G4D1N
: 1;
6089 unsigned LC2G4D1T
: 1;
6090 unsigned LC2G4D2N
: 1;
6091 unsigned LC2G4D2T
: 1;
6092 unsigned LC2G4D3N
: 1;
6093 unsigned LC2G4D3T
: 1;
6094 unsigned LC2G4D4N
: 1;
6095 unsigned LC2G4D4T
: 1;
6111 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
6113 #define _CLC2GLS3_LC2G4D1N 0x01
6114 #define _CLC2GLS3_G4D1N 0x01
6115 #define _CLC2GLS3_LC2G4D1T 0x02
6116 #define _CLC2GLS3_G4D1T 0x02
6117 #define _CLC2GLS3_LC2G4D2N 0x04
6118 #define _CLC2GLS3_G4D2N 0x04
6119 #define _CLC2GLS3_LC2G4D2T 0x08
6120 #define _CLC2GLS3_G4D2T 0x08
6121 #define _CLC2GLS3_LC2G4D3N 0x10
6122 #define _CLC2GLS3_G4D3N 0x10
6123 #define _CLC2GLS3_LC2G4D3T 0x20
6124 #define _CLC2GLS3_G4D3T 0x20
6125 #define _CLC2GLS3_LC2G4D4N 0x40
6126 #define _CLC2GLS3_G4D4N 0x40
6127 #define _CLC2GLS3_LC2G4D4T 0x80
6128 #define _CLC2GLS3_G4D4T 0x80
6130 //==============================================================================
6133 //==============================================================================
6136 extern __at(0x0F24) __sfr CLC3CON
;
6142 unsigned LC3MODE0
: 1;
6143 unsigned LC3MODE1
: 1;
6144 unsigned LC3MODE2
: 1;
6145 unsigned LC3INTN
: 1;
6146 unsigned LC3INTP
: 1;
6147 unsigned LC3OUT
: 1;
6172 unsigned LC3MODE
: 3;
6177 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
6179 #define _CLC3CON_LC3MODE0 0x01
6180 #define _CLC3CON_MODE0 0x01
6181 #define _CLC3CON_LC3MODE1 0x02
6182 #define _CLC3CON_MODE1 0x02
6183 #define _CLC3CON_LC3MODE2 0x04
6184 #define _CLC3CON_MODE2 0x04
6185 #define _CLC3CON_LC3INTN 0x08
6186 #define _CLC3CON_INTN 0x08
6187 #define _CLC3CON_LC3INTP 0x10
6188 #define _CLC3CON_INTP 0x10
6189 #define _CLC3CON_LC3OUT 0x20
6190 #define _CLC3CON_OUT 0x20
6191 #define _CLC3CON_LC3EN 0x80
6192 #define _CLC3CON_EN 0x80
6194 //==============================================================================
6197 //==============================================================================
6200 extern __at(0x0F25) __sfr CLC3POL
;
6206 unsigned LC3G1POL
: 1;
6207 unsigned LC3G2POL
: 1;
6208 unsigned LC3G3POL
: 1;
6209 unsigned LC3G4POL
: 1;
6213 unsigned LC3POL
: 1;
6229 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
6231 #define _CLC3POL_LC3G1POL 0x01
6232 #define _CLC3POL_G1POL 0x01
6233 #define _CLC3POL_LC3G2POL 0x02
6234 #define _CLC3POL_G2POL 0x02
6235 #define _CLC3POL_LC3G3POL 0x04
6236 #define _CLC3POL_G3POL 0x04
6237 #define _CLC3POL_LC3G4POL 0x08
6238 #define _CLC3POL_G4POL 0x08
6239 #define _CLC3POL_LC3POL 0x80
6240 #define _CLC3POL_POL 0x80
6242 //==============================================================================
6245 //==============================================================================
6248 extern __at(0x0F26) __sfr CLC3SEL0
;
6254 unsigned LC3D1S0
: 1;
6255 unsigned LC3D1S1
: 1;
6256 unsigned LC3D1S2
: 1;
6257 unsigned LC3D1S3
: 1;
6258 unsigned LC3D1S4
: 1;
6278 unsigned LC3D1S
: 5;
6289 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
6291 #define _CLC3SEL0_LC3D1S0 0x01
6292 #define _CLC3SEL0_D1S0 0x01
6293 #define _CLC3SEL0_LC3D1S1 0x02
6294 #define _CLC3SEL0_D1S1 0x02
6295 #define _CLC3SEL0_LC3D1S2 0x04
6296 #define _CLC3SEL0_D1S2 0x04
6297 #define _CLC3SEL0_LC3D1S3 0x08
6298 #define _CLC3SEL0_D1S3 0x08
6299 #define _CLC3SEL0_LC3D1S4 0x10
6300 #define _CLC3SEL0_D1S4 0x10
6302 //==============================================================================
6305 //==============================================================================
6308 extern __at(0x0F27) __sfr CLC3SEL1
;
6314 unsigned LC3D2S0
: 1;
6315 unsigned LC3D2S1
: 1;
6316 unsigned LC3D2S2
: 1;
6317 unsigned LC3D2S3
: 1;
6318 unsigned LC3D2S4
: 1;
6344 unsigned LC3D2S
: 5;
6349 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
6351 #define _CLC3SEL1_LC3D2S0 0x01
6352 #define _CLC3SEL1_D2S0 0x01
6353 #define _CLC3SEL1_LC3D2S1 0x02
6354 #define _CLC3SEL1_D2S1 0x02
6355 #define _CLC3SEL1_LC3D2S2 0x04
6356 #define _CLC3SEL1_D2S2 0x04
6357 #define _CLC3SEL1_LC3D2S3 0x08
6358 #define _CLC3SEL1_D2S3 0x08
6359 #define _CLC3SEL1_LC3D2S4 0x10
6360 #define _CLC3SEL1_D2S4 0x10
6362 //==============================================================================
6365 //==============================================================================
6368 extern __at(0x0F28) __sfr CLC3SEL2
;
6374 unsigned LC3D3S0
: 1;
6375 unsigned LC3D3S1
: 1;
6376 unsigned LC3D3S2
: 1;
6377 unsigned LC3D3S3
: 1;
6378 unsigned LC3D3S4
: 1;
6398 unsigned LC3D3S
: 5;
6409 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
6411 #define _CLC3SEL2_LC3D3S0 0x01
6412 #define _CLC3SEL2_D3S0 0x01
6413 #define _CLC3SEL2_LC3D3S1 0x02
6414 #define _CLC3SEL2_D3S1 0x02
6415 #define _CLC3SEL2_LC3D3S2 0x04
6416 #define _CLC3SEL2_D3S2 0x04
6417 #define _CLC3SEL2_LC3D3S3 0x08
6418 #define _CLC3SEL2_D3S3 0x08
6419 #define _CLC3SEL2_LC3D3S4 0x10
6420 #define _CLC3SEL2_D3S4 0x10
6422 //==============================================================================
6425 //==============================================================================
6428 extern __at(0x0F29) __sfr CLC3SEL3
;
6434 unsigned LC3D4S0
: 1;
6435 unsigned LC3D4S1
: 1;
6436 unsigned LC3D4S2
: 1;
6437 unsigned LC3D4S3
: 1;
6438 unsigned LC3D4S4
: 1;
6464 unsigned LC3D4S
: 5;
6469 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
6471 #define _CLC3SEL3_LC3D4S0 0x01
6472 #define _CLC3SEL3_D4S0 0x01
6473 #define _CLC3SEL3_LC3D4S1 0x02
6474 #define _CLC3SEL3_D4S1 0x02
6475 #define _CLC3SEL3_LC3D4S2 0x04
6476 #define _CLC3SEL3_D4S2 0x04
6477 #define _CLC3SEL3_LC3D4S3 0x08
6478 #define _CLC3SEL3_D4S3 0x08
6479 #define _CLC3SEL3_LC3D4S4 0x10
6480 #define _CLC3SEL3_D4S4 0x10
6482 //==============================================================================
6485 //==============================================================================
6488 extern __at(0x0F2A) __sfr CLC3GLS0
;
6494 unsigned LC3G1D1N
: 1;
6495 unsigned LC3G1D1T
: 1;
6496 unsigned LC3G1D2N
: 1;
6497 unsigned LC3G1D2T
: 1;
6498 unsigned LC3G1D3N
: 1;
6499 unsigned LC3G1D3T
: 1;
6500 unsigned LC3G1D4N
: 1;
6501 unsigned LC3G1D4T
: 1;
6517 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
6519 #define _CLC3GLS0_LC3G1D1N 0x01
6520 #define _CLC3GLS0_D1N 0x01
6521 #define _CLC3GLS0_LC3G1D1T 0x02
6522 #define _CLC3GLS0_D1T 0x02
6523 #define _CLC3GLS0_LC3G1D2N 0x04
6524 #define _CLC3GLS0_D2N 0x04
6525 #define _CLC3GLS0_LC3G1D2T 0x08
6526 #define _CLC3GLS0_D2T 0x08
6527 #define _CLC3GLS0_LC3G1D3N 0x10
6528 #define _CLC3GLS0_D3N 0x10
6529 #define _CLC3GLS0_LC3G1D3T 0x20
6530 #define _CLC3GLS0_D3T 0x20
6531 #define _CLC3GLS0_LC3G1D4N 0x40
6532 #define _CLC3GLS0_D4N 0x40
6533 #define _CLC3GLS0_LC3G1D4T 0x80
6534 #define _CLC3GLS0_D4T 0x80
6536 //==============================================================================
6539 //==============================================================================
6542 extern __at(0x0F2B) __sfr CLC3GLS1
;
6548 unsigned LC3G2D1N
: 1;
6549 unsigned LC3G2D1T
: 1;
6550 unsigned LC3G2D2N
: 1;
6551 unsigned LC3G2D2T
: 1;
6552 unsigned LC3G2D3N
: 1;
6553 unsigned LC3G2D3T
: 1;
6554 unsigned LC3G2D4N
: 1;
6555 unsigned LC3G2D4T
: 1;
6571 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
6573 #define _CLC3GLS1_LC3G2D1N 0x01
6574 #define _CLC3GLS1_D1N 0x01
6575 #define _CLC3GLS1_LC3G2D1T 0x02
6576 #define _CLC3GLS1_D1T 0x02
6577 #define _CLC3GLS1_LC3G2D2N 0x04
6578 #define _CLC3GLS1_D2N 0x04
6579 #define _CLC3GLS1_LC3G2D2T 0x08
6580 #define _CLC3GLS1_D2T 0x08
6581 #define _CLC3GLS1_LC3G2D3N 0x10
6582 #define _CLC3GLS1_D3N 0x10
6583 #define _CLC3GLS1_LC3G2D3T 0x20
6584 #define _CLC3GLS1_D3T 0x20
6585 #define _CLC3GLS1_LC3G2D4N 0x40
6586 #define _CLC3GLS1_D4N 0x40
6587 #define _CLC3GLS1_LC3G2D4T 0x80
6588 #define _CLC3GLS1_D4T 0x80
6590 //==============================================================================
6593 //==============================================================================
6596 extern __at(0x0F2C) __sfr CLC3GLS2
;
6602 unsigned LC3G3D1N
: 1;
6603 unsigned LC3G3D1T
: 1;
6604 unsigned LC3G3D2N
: 1;
6605 unsigned LC3G3D2T
: 1;
6606 unsigned LC3G3D3N
: 1;
6607 unsigned LC3G3D3T
: 1;
6608 unsigned LC3G3D4N
: 1;
6609 unsigned LC3G3D4T
: 1;
6625 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
6627 #define _CLC3GLS2_LC3G3D1N 0x01
6628 #define _CLC3GLS2_D1N 0x01
6629 #define _CLC3GLS2_LC3G3D1T 0x02
6630 #define _CLC3GLS2_D1T 0x02
6631 #define _CLC3GLS2_LC3G3D2N 0x04
6632 #define _CLC3GLS2_D2N 0x04
6633 #define _CLC3GLS2_LC3G3D2T 0x08
6634 #define _CLC3GLS2_D2T 0x08
6635 #define _CLC3GLS2_LC3G3D3N 0x10
6636 #define _CLC3GLS2_D3N 0x10
6637 #define _CLC3GLS2_LC3G3D3T 0x20
6638 #define _CLC3GLS2_D3T 0x20
6639 #define _CLC3GLS2_LC3G3D4N 0x40
6640 #define _CLC3GLS2_D4N 0x40
6641 #define _CLC3GLS2_LC3G3D4T 0x80
6642 #define _CLC3GLS2_D4T 0x80
6644 //==============================================================================
6647 //==============================================================================
6650 extern __at(0x0F2D) __sfr CLC3GLS3
;
6656 unsigned LC3G4D1N
: 1;
6657 unsigned LC3G4D1T
: 1;
6658 unsigned LC3G4D2N
: 1;
6659 unsigned LC3G4D2T
: 1;
6660 unsigned LC3G4D3N
: 1;
6661 unsigned LC3G4D3T
: 1;
6662 unsigned LC3G4D4N
: 1;
6663 unsigned LC3G4D4T
: 1;
6679 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
6681 #define _CLC3GLS3_LC3G4D1N 0x01
6682 #define _CLC3GLS3_G4D1N 0x01
6683 #define _CLC3GLS3_LC3G4D1T 0x02
6684 #define _CLC3GLS3_G4D1T 0x02
6685 #define _CLC3GLS3_LC3G4D2N 0x04
6686 #define _CLC3GLS3_G4D2N 0x04
6687 #define _CLC3GLS3_LC3G4D2T 0x08
6688 #define _CLC3GLS3_G4D2T 0x08
6689 #define _CLC3GLS3_LC3G4D3N 0x10
6690 #define _CLC3GLS3_G4D3N 0x10
6691 #define _CLC3GLS3_LC3G4D3T 0x20
6692 #define _CLC3GLS3_G4D3T 0x20
6693 #define _CLC3GLS3_LC3G4D4N 0x40
6694 #define _CLC3GLS3_G4D4N 0x40
6695 #define _CLC3GLS3_LC3G4D4T 0x80
6696 #define _CLC3GLS3_G4D4T 0x80
6698 //==============================================================================
6701 //==============================================================================
6704 extern __at(0x0FE4) __sfr STATUS_SHAD
;
6708 unsigned C_SHAD
: 1;
6709 unsigned DC_SHAD
: 1;
6710 unsigned Z_SHAD
: 1;
6716 } __STATUS_SHADbits_t
;
6718 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
6720 #define _C_SHAD 0x01
6721 #define _DC_SHAD 0x02
6722 #define _Z_SHAD 0x04
6724 //==============================================================================
6726 extern __at(0x0FE5) __sfr WREG_SHAD
;
6727 extern __at(0x0FE6) __sfr BSR_SHAD
;
6728 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
6729 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
6730 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
6731 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
6732 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
6733 extern __at(0x0FED) __sfr STKPTR
;
6734 extern __at(0x0FEE) __sfr TOSL
;
6735 extern __at(0x0FEF) __sfr TOSH
;
6737 //==============================================================================
6739 // Configuration Bits
6741 //==============================================================================
6743 #define _CONFIG1 0x8007
6744 #define _CONFIG2 0x8008
6746 //----------------------------- CONFIG1 Options -------------------------------
6748 #define _FOSC_LP 0x3FF8 // LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins.
6749 #define _FOSC_XT 0x3FF9 // XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins.
6750 #define _FOSC_HS 0x3FFA // HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins.
6751 #define _FOSC_EXTRC 0x3FFB // EXTRC oscillator: External RC circuit connected to CLKIN pin.
6752 #define _FOSC_INTOSC 0x3FFC // INTOSC oscillator: I/O function on CLKIN pin.
6753 #define _FOSC_ECL 0x3FFD // ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pins.
6754 #define _FOSC_ECM 0x3FFE // ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pins.
6755 #define _FOSC_ECH 0x3FFF // ECH, External Clock, High Power Mode (4-20 MHz): device clock supplied to CLKIN pins.
6756 #define _WDTE_OFF 0x3FE7 // WDT disabled.
6757 #define _WDTE_SWDTEN 0x3FEF // WDT controlled by the SWDTEN bit in the WDTCON register.
6758 #define _WDTE_NSLEEP 0x3FF7 // WDT enabled while running and disabled in Sleep.
6759 #define _WDTE_ON 0x3FFF // WDT enabled.
6760 #define _PWRTE_ON 0x3FDF // PWRT enabled.
6761 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
6762 #define _MCLRE_OFF 0x3FBF // MCLR/VPP pin function is digital input.
6763 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR.
6764 #define _CP_ON 0x3F7F // Program memory code protection is enabled.
6765 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
6766 #define _BOREN_OFF 0x39FF // Brown-out Reset disabled.
6767 #define _BOREN_SBODEN 0x3BFF // Brown-out Reset controlled by the SBOREN bit in the BORCON register.
6768 #define _BOREN_NSLEEP 0x3DFF // Brown-out Reset enabled while running and disabled in Sleep.
6769 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled.
6770 #define _CLKOUTEN_ON 0x37FF // CLKOUT function is enabled on the CLKOUT pin.
6771 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
6772 #define _IESO_OFF 0x2FFF // Internal/External Switchover Mode is disabled.
6773 #define _IESO_ON 0x3FFF // Internal/External Switchover Mode is enabled.
6774 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
6775 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
6777 //----------------------------- CONFIG2 Options -------------------------------
6779 #define _WRT_ALL 0x3FFC // 000h to 1FFFh write protected, no addresses may be modified by EECON control.
6780 #define _WRT_HALF 0x3FFD // 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control.
6781 #define _WRT_BOOT 0x3FFE // 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control.
6782 #define _WRT_OFF 0x3FFF // Write protection off.
6783 #define _PPS1WAY_OFF 0x3FFB // The PPSLOCK bit can be set and cleared repeatedly by software.
6784 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit cannot be cleared once it is set by software.
6785 #define _ZCDDIS_OFF 0x3F7F // Zero-cross detect circuit is enabled at POR.
6786 #define _ZCDDIS_ON 0x3FFF // Zero-cross detect circuit is disabled at POR.
6787 #define _PLLEN_OFF 0x3EFF // 4x PLL is enabled when software sets the SPLLEN bit.
6788 #define _PLLEN_ON 0x3FFF // 4x PLL is always enabled.
6789 #define _STVREN_OFF 0x3DFF // Stack Overflow or Underflow will not cause a Reset.
6790 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
6791 #define _BORV_HI 0x3BFF // Brown-out Reset Voltage (Vbor), high trip point selected.
6792 #define _BORV_LO 0x3FFF // Brown-out Reset Voltage (Vbor), low trip point selected.
6793 #define _LPBOR_ON 0x37FF // Low-Power BOR is enabled.
6794 #define _LPBOR_OFF 0x3FFF // Low-Power BOR is disabled.
6795 #define _DEBUG_ON 0x2FFF // In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger.
6796 #define _DEBUG_OFF 0x3FFF // In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins.
6797 #define _LVP_OFF 0x1FFF // High-voltage on MCLR/VPP must be used for programming.
6798 #define _LVP_ON 0x3FFF // Low-voltage programming enabled.
6800 //==============================================================================
6802 #define _DEVID1 0x8006
6804 #define _IDLOC0 0x8000
6805 #define _IDLOC1 0x8001
6806 #define _IDLOC2 0x8002
6807 #define _IDLOC3 0x8003
6809 //==============================================================================
6811 #ifndef NO_BIT_DEFINES
6813 #define ADON ADCON0bits.ADON // bit 0
6814 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
6815 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
6816 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
6817 #define CHS0 ADCON0bits.CHS0 // bit 2
6818 #define CHS1 ADCON0bits.CHS1 // bit 3
6819 #define CHS2 ADCON0bits.CHS2 // bit 4
6820 #define CHS3 ADCON0bits.CHS3 // bit 5
6821 #define CHS4 ADCON0bits.CHS4 // bit 6
6823 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
6824 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
6825 #define ADNREF ADCON1bits.ADNREF // bit 2
6826 #define ADCS0 ADCON1bits.ADCS0 // bit 4
6827 #define ADCS1 ADCON1bits.ADCS1 // bit 5
6828 #define ADCS2 ADCON1bits.ADCS2 // bit 6
6829 #define ADFM ADCON1bits.ADFM // bit 7
6831 #define TRIGSEL0 ADCON2bits.TRIGSEL0 // bit 4
6832 #define TRIGSEL1 ADCON2bits.TRIGSEL1 // bit 5
6833 #define TRIGSEL2 ADCON2bits.TRIGSEL2 // bit 6
6834 #define TRIGSEL3 ADCON2bits.TRIGSEL3 // bit 7
6836 #define ANSA0 ANSELAbits.ANSA0 // bit 0
6837 #define ANSA1 ANSELAbits.ANSA1 // bit 1
6838 #define ANSA2 ANSELAbits.ANSA2 // bit 2
6839 #define ANSA4 ANSELAbits.ANSA4 // bit 4
6840 #define ANS5 ANSELAbits.ANS5 // bit 5
6842 #define ANSB4 ANSELBbits.ANSB4 // bit 4
6843 #define ANSB5 ANSELBbits.ANSB5 // bit 5
6844 #define ANSB6 ANSELBbits.ANSB6 // bit 6
6845 #define ANSB7 ANSELBbits.ANSB7 // bit 7
6847 #define ANSC0 ANSELCbits.ANSC0 // bit 0
6848 #define ANSC1 ANSELCbits.ANSC1 // bit 1
6849 #define ANSC2 ANSELCbits.ANSC2 // bit 2
6850 #define ANSC3 ANSELCbits.ANSC3 // bit 3
6851 #define ANSC6 ANSELCbits.ANSC6 // bit 6
6852 #define ANSC7 ANSELCbits.ANSC7 // bit 7
6854 #define ABDEN BAUD1CONbits.ABDEN // bit 0
6855 #define WUE BAUD1CONbits.WUE // bit 1
6856 #define BRG16 BAUD1CONbits.BRG16 // bit 3
6857 #define SCKP BAUD1CONbits.SCKP // bit 4
6858 #define RCIDL BAUD1CONbits.RCIDL // bit 6
6859 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
6861 #define BORRDY BORCONbits.BORRDY // bit 0
6862 #define BORFS BORCONbits.BORFS // bit 6
6863 #define SBOREN BORCONbits.SBOREN // bit 7
6865 #define BSR0 BSRbits.BSR0 // bit 0
6866 #define BSR1 BSRbits.BSR1 // bit 1
6867 #define BSR2 BSRbits.BSR2 // bit 2
6868 #define BSR3 BSRbits.BSR3 // bit 3
6869 #define BSR4 BSRbits.BSR4 // bit 4
6871 #define CCP1M0 CCP1CONbits.CCP1M0 // bit 0
6872 #define CCP1M1 CCP1CONbits.CCP1M1 // bit 1
6873 #define CCP1M2 CCP1CONbits.CCP1M2 // bit 2
6874 #define CCP1M3 CCP1CONbits.CCP1M3 // bit 3
6875 #define DC1B0 CCP1CONbits.DC1B0 // bit 4, shadows bit in CCP1CONbits
6876 #define CCP1Y CCP1CONbits.CCP1Y // bit 4, shadows bit in CCP1CONbits
6877 #define DC1B1 CCP1CONbits.DC1B1 // bit 5, shadows bit in CCP1CONbits
6878 #define CCP1X CCP1CONbits.CCP1X // bit 5, shadows bit in CCP1CONbits
6880 #define CCP2M0 CCP2CONbits.CCP2M0 // bit 0
6881 #define CCP2M1 CCP2CONbits.CCP2M1 // bit 1
6882 #define CCP2M2 CCP2CONbits.CCP2M2 // bit 2
6883 #define CCP2M3 CCP2CONbits.CCP2M3 // bit 3
6884 #define DC2B0 CCP2CONbits.DC2B0 // bit 4, shadows bit in CCP2CONbits
6885 #define CCP2Y CCP2CONbits.CCP2Y // bit 4, shadows bit in CCP2CONbits
6886 #define DC2B1 CCP2CONbits.DC2B1 // bit 5, shadows bit in CCP2CONbits
6887 #define CCP2X CCP2CONbits.CCP2X // bit 5, shadows bit in CCP2CONbits
6889 #define C1TSEL0 CCPTMRSbits.C1TSEL0 // bit 0
6890 #define C1TSEL1 CCPTMRSbits.C1TSEL1 // bit 1
6891 #define C2TSEL0 CCPTMRSbits.C2TSEL0 // bit 2
6892 #define C2TSEL1 CCPTMRSbits.C2TSEL1 // bit 3
6893 #define P3TSEL0 CCPTMRSbits.P3TSEL0 // bit 4
6894 #define P3TSEL1 CCPTMRSbits.P3TSEL1 // bit 5
6895 #define P4TSEL0 CCPTMRSbits.P4TSEL0 // bit 6
6896 #define P4TSEL1 CCPTMRSbits.P4TSEL1 // bit 7
6898 #define LC1MODE0 CLC1CONbits.LC1MODE0 // bit 0, shadows bit in CLC1CONbits
6899 #define MODE0 CLC1CONbits.MODE0 // bit 0, shadows bit in CLC1CONbits
6900 #define LC1MODE1 CLC1CONbits.LC1MODE1 // bit 1, shadows bit in CLC1CONbits
6901 #define MODE1 CLC1CONbits.MODE1 // bit 1, shadows bit in CLC1CONbits
6902 #define LC1MODE2 CLC1CONbits.LC1MODE2 // bit 2, shadows bit in CLC1CONbits
6903 #define MODE2 CLC1CONbits.MODE2 // bit 2, shadows bit in CLC1CONbits
6904 #define LC1INTN CLC1CONbits.LC1INTN // bit 3, shadows bit in CLC1CONbits
6905 #define INTN CLC1CONbits.INTN // bit 3, shadows bit in CLC1CONbits
6906 #define LC1INTP CLC1CONbits.LC1INTP // bit 4, shadows bit in CLC1CONbits
6907 #define INTP CLC1CONbits.INTP // bit 4, shadows bit in CLC1CONbits
6908 #define LC1OUT CLC1CONbits.LC1OUT // bit 5, shadows bit in CLC1CONbits
6909 #define OUT CLC1CONbits.OUT // bit 5, shadows bit in CLC1CONbits
6910 #define LC1EN CLC1CONbits.LC1EN // bit 7, shadows bit in CLC1CONbits
6911 #define EN CLC1CONbits.EN // bit 7, shadows bit in CLC1CONbits
6913 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
6914 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
6915 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
6916 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
6917 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
6918 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
6919 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
6920 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
6921 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
6922 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
6923 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
6924 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
6925 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
6926 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
6927 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
6928 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
6930 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
6931 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
6932 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
6933 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
6934 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
6935 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
6936 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
6937 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
6938 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
6939 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
6940 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
6941 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
6942 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
6943 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
6944 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
6945 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
6947 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
6948 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
6949 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
6950 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
6951 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
6952 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
6953 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
6954 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
6955 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
6956 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
6958 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
6959 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
6960 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
6961 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
6962 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
6963 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
6964 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
6965 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
6966 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
6967 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
6969 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
6970 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
6971 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
6972 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
6973 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
6974 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
6975 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
6976 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
6977 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
6978 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
6980 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
6981 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
6982 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
6983 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
6984 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
6985 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
6986 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
6987 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
6988 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
6989 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
6991 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
6992 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
6993 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
6994 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
6995 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
6996 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
6997 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
6998 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
6999 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
7000 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
7002 #define MCLC1OUT CLCDATAbits.MCLC1OUT // bit 0
7003 #define MCLC2OUT CLCDATAbits.MCLC2OUT // bit 1
7004 #define MCLC3OUT CLCDATAbits.MCLC3OUT // bit 2
7006 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
7007 #define C1HYS CM1CON0bits.C1HYS // bit 1
7008 #define C1SP CM1CON0bits.C1SP // bit 2
7009 #define C1ZLF CM1CON0bits.C1ZLF // bit 3
7010 #define C1POL CM1CON0bits.C1POL // bit 4
7011 #define C1OUT CM1CON0bits.C1OUT // bit 6
7012 #define C1ON CM1CON0bits.C1ON // bit 7
7014 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
7015 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
7016 #define C1NCH2 CM1CON1bits.C1NCH2 // bit 2
7017 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 3
7018 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 4
7019 #define C1PCH2 CM1CON1bits.C1PCH2 // bit 5
7020 #define C1INTN CM1CON1bits.C1INTN // bit 6
7021 #define C1INTP CM1CON1bits.C1INTP // bit 7
7023 #define C2SYNC CM2CON0bits.C2SYNC // bit 0
7024 #define C2HYS CM2CON0bits.C2HYS // bit 1
7025 #define C2SP CM2CON0bits.C2SP // bit 2
7026 #define C2ZLF CM2CON0bits.C2ZLF // bit 3
7027 #define C2POL CM2CON0bits.C2POL // bit 4
7028 #define C2OUT CM2CON0bits.C2OUT // bit 6
7029 #define C2ON CM2CON0bits.C2ON // bit 7
7031 #define C2NCH0 CM2CON1bits.C2NCH0 // bit 0
7032 #define C2NCH1 CM2CON1bits.C2NCH1 // bit 1
7033 #define C2NCH2 CM2CON1bits.C2NCH2 // bit 2
7034 #define C2PCH0 CM2CON1bits.C2PCH0 // bit 3
7035 #define C2PCH1 CM2CON1bits.C2PCH1 // bit 4
7036 #define C2PCH2 CM2CON1bits.C2PCH2 // bit 5
7037 #define C2INTN CM2CON1bits.C2INTN // bit 6
7038 #define C2INTP CM2CON1bits.C2INTP // bit 7
7040 #define MC1OUT CMOUTbits.MC1OUT // bit 0
7041 #define MC2OUT CMOUTbits.MC2OUT // bit 1
7043 #define G1ASDAC0 COG1ASD0bits.G1ASDAC0 // bit 2
7044 #define G1ASDAC1 COG1ASD0bits.G1ASDAC1 // bit 3
7045 #define G1ASDBD0 COG1ASD0bits.G1ASDBD0 // bit 4
7046 #define G1ASDBD1 COG1ASD0bits.G1ASDBD1 // bit 5
7047 #define G1ARSEN COG1ASD0bits.G1ARSEN // bit 6
7048 #define G1ASE COG1ASD0bits.G1ASE // bit 7
7050 #define G1AS0E COG1ASD1bits.G1AS0E // bit 0
7051 #define G1AS1E COG1ASD1bits.G1AS1E // bit 1
7052 #define G1AS2E COG1ASD1bits.G1AS2E // bit 2
7053 #define G1AS3E COG1ASD1bits.G1AS3E // bit 3
7055 #define G1BLKF0 COG1BLKFbits.G1BLKF0 // bit 0
7056 #define G1BLKF1 COG1BLKFbits.G1BLKF1 // bit 1
7057 #define G1BLKF2 COG1BLKFbits.G1BLKF2 // bit 2
7058 #define G1BLKF3 COG1BLKFbits.G1BLKF3 // bit 3
7059 #define G1BLKF4 COG1BLKFbits.G1BLKF4 // bit 4
7060 #define G1BLKF5 COG1BLKFbits.G1BLKF5 // bit 5
7062 #define G1BLKR0 COG1BLKRbits.G1BLKR0 // bit 0
7063 #define G1BLKR1 COG1BLKRbits.G1BLKR1 // bit 1
7064 #define G1BLKR2 COG1BLKRbits.G1BLKR2 // bit 2
7065 #define G1BLKR3 COG1BLKRbits.G1BLKR3 // bit 3
7066 #define G1BLKR4 COG1BLKRbits.G1BLKR4 // bit 4
7067 #define G1BLKR5 COG1BLKRbits.G1BLKR5 // bit 5
7069 #define G1MD0 COG1CON0bits.G1MD0 // bit 0
7070 #define G1MD1 COG1CON0bits.G1MD1 // bit 1
7071 #define G1MD2 COG1CON0bits.G1MD2 // bit 2
7072 #define G1CS0 COG1CON0bits.G1CS0 // bit 3
7073 #define G1CS1 COG1CON0bits.G1CS1 // bit 4
7074 #define G1LD COG1CON0bits.G1LD // bit 6
7075 #define G1EN COG1CON0bits.G1EN // bit 7
7077 #define G1POLA COG1CON1bits.G1POLA // bit 0
7078 #define G1POLB COG1CON1bits.G1POLB // bit 1
7079 #define G1POLC COG1CON1bits.G1POLC // bit 2
7080 #define G1POLD COG1CON1bits.G1POLD // bit 3
7081 #define G1FDBS COG1CON1bits.G1FDBS // bit 6
7082 #define G1RDBS COG1CON1bits.G1RDBS // bit 7
7084 #define G1DBF0 COG1DBFbits.G1DBF0 // bit 0
7085 #define G1DBF1 COG1DBFbits.G1DBF1 // bit 1
7086 #define G1DBF2 COG1DBFbits.G1DBF2 // bit 2
7087 #define G1DBF3 COG1DBFbits.G1DBF3 // bit 3
7088 #define G1DBF4 COG1DBFbits.G1DBF4 // bit 4
7089 #define G1DBF5 COG1DBFbits.G1DBF5 // bit 5
7091 #define G1DBR0 COG1DBRbits.G1DBR0 // bit 0
7092 #define G1DBR1 COG1DBRbits.G1DBR1 // bit 1
7093 #define G1DBR2 COG1DBRbits.G1DBR2 // bit 2
7094 #define G1DBR3 COG1DBRbits.G1DBR3 // bit 3
7095 #define G1DBR4 COG1DBRbits.G1DBR4 // bit 4
7096 #define G1DBR5 COG1DBRbits.G1DBR5 // bit 5
7098 #define G1FIS0 COG1FISbits.G1FIS0 // bit 0
7099 #define G1FIS1 COG1FISbits.G1FIS1 // bit 1
7100 #define G1FIS2 COG1FISbits.G1FIS2 // bit 2
7101 #define G1FIS3 COG1FISbits.G1FIS3 // bit 3
7102 #define G1FIS4 COG1FISbits.G1FIS4 // bit 4
7103 #define G1FIS5 COG1FISbits.G1FIS5 // bit 5
7104 #define G1FIS6 COG1FISbits.G1FIS6 // bit 6
7106 #define G1FSIM0 COG1FSIMbits.G1FSIM0 // bit 0
7107 #define G1FSIM1 COG1FSIMbits.G1FSIM1 // bit 1
7108 #define G1FSIM2 COG1FSIMbits.G1FSIM2 // bit 2
7109 #define G1FSIM3 COG1FSIMbits.G1FSIM3 // bit 3
7110 #define G1FSIM4 COG1FSIMbits.G1FSIM4 // bit 4
7111 #define G1FSIM5 COG1FSIMbits.G1FSIM5 // bit 5
7112 #define G1FSIM6 COG1FSIMbits.G1FSIM6 // bit 6
7114 #define G1PHF0 COG1PHFbits.G1PHF0 // bit 0
7115 #define G1PHF1 COG1PHFbits.G1PHF1 // bit 1
7116 #define G1PHF2 COG1PHFbits.G1PHF2 // bit 2
7117 #define G1PHF3 COG1PHFbits.G1PHF3 // bit 3
7118 #define G1PHF4 COG1PHFbits.G1PHF4 // bit 4
7119 #define G1PHF5 COG1PHFbits.G1PHF5 // bit 5
7121 #define G1PHR0 COG1PHRbits.G1PHR0 // bit 0
7122 #define G1PHR1 COG1PHRbits.G1PHR1 // bit 1
7123 #define G1PHR2 COG1PHRbits.G1PHR2 // bit 2
7124 #define G1PHR3 COG1PHRbits.G1PHR3 // bit 3
7125 #define G1PHR4 COG1PHRbits.G1PHR4 // bit 4
7126 #define G1PHR5 COG1PHRbits.G1PHR5 // bit 5
7128 #define G1RIS0 COG1RISbits.G1RIS0 // bit 0
7129 #define G1RIS1 COG1RISbits.G1RIS1 // bit 1
7130 #define G1RIS2 COG1RISbits.G1RIS2 // bit 2
7131 #define G1RIS3 COG1RISbits.G1RIS3 // bit 3
7132 #define G1RIS4 COG1RISbits.G1RIS4 // bit 4
7133 #define G1RIS5 COG1RISbits.G1RIS5 // bit 5
7134 #define G1RIS6 COG1RISbits.G1RIS6 // bit 6
7136 #define G1RSIM0 COG1RSIMbits.G1RSIM0 // bit 0
7137 #define G1RSIM1 COG1RSIMbits.G1RSIM1 // bit 1
7138 #define G1RSIM2 COG1RSIMbits.G1RSIM2 // bit 2
7139 #define G1RSIM3 COG1RSIMbits.G1RSIM3 // bit 3
7140 #define G1RSIM4 COG1RSIMbits.G1RSIM4 // bit 4
7141 #define G1RSIM5 COG1RSIMbits.G1RSIM5 // bit 5
7142 #define G1RSIM6 COG1RSIMbits.G1RSIM6 // bit 6
7144 #define G1STRA COG1STRbits.G1STRA // bit 0
7145 #define G1STRB COG1STRbits.G1STRB // bit 1
7146 #define G1STRC COG1STRbits.G1STRC // bit 2
7147 #define G1STRD COG1STRbits.G1STRD // bit 3
7148 #define G1SDATA COG1STRbits.G1SDATA // bit 4
7149 #define G1SDATB COG1STRbits.G1SDATB // bit 5
7150 #define G1SDATC COG1STRbits.G1SDATC // bit 6
7151 #define G1SDATD COG1STRbits.G1SDATD // bit 7
7153 #define DAC1NSS DAC1CON0bits.DAC1NSS // bit 0, shadows bit in DAC1CON0bits
7154 #define DACNSS DAC1CON0bits.DACNSS // bit 0, shadows bit in DAC1CON0bits
7155 #define DAC1PSS0 DAC1CON0bits.DAC1PSS0 // bit 2, shadows bit in DAC1CON0bits
7156 #define DACPSS0 DAC1CON0bits.DACPSS0 // bit 2, shadows bit in DAC1CON0bits
7157 #define DAC1PSS1 DAC1CON0bits.DAC1PSS1 // bit 3, shadows bit in DAC1CON0bits
7158 #define DACPSS1 DAC1CON0bits.DACPSS1 // bit 3, shadows bit in DAC1CON0bits
7159 #define DAC1OE2 DAC1CON0bits.DAC1OE2 // bit 4, shadows bit in DAC1CON0bits
7160 #define DACOE0 DAC1CON0bits.DACOE0 // bit 4, shadows bit in DAC1CON0bits
7161 #define DAC1OE1 DAC1CON0bits.DAC1OE1 // bit 5, shadows bit in DAC1CON0bits
7162 #define DACOE1 DAC1CON0bits.DACOE1 // bit 5, shadows bit in DAC1CON0bits
7163 #define DAC1EN DAC1CON0bits.DAC1EN // bit 7, shadows bit in DAC1CON0bits
7164 #define DACEN DAC1CON0bits.DACEN // bit 7, shadows bit in DAC1CON0bits
7166 #define DAC1R0 DAC1CON1bits.DAC1R0 // bit 0, shadows bit in DAC1CON1bits
7167 #define DACR0 DAC1CON1bits.DACR0 // bit 0, shadows bit in DAC1CON1bits
7168 #define DAC1R1 DAC1CON1bits.DAC1R1 // bit 1, shadows bit in DAC1CON1bits
7169 #define DACR1 DAC1CON1bits.DACR1 // bit 1, shadows bit in DAC1CON1bits
7170 #define DAC1R2 DAC1CON1bits.DAC1R2 // bit 2, shadows bit in DAC1CON1bits
7171 #define DACR2 DAC1CON1bits.DACR2 // bit 2, shadows bit in DAC1CON1bits
7172 #define DAC1R3 DAC1CON1bits.DAC1R3 // bit 3, shadows bit in DAC1CON1bits
7173 #define DACR3 DAC1CON1bits.DACR3 // bit 3, shadows bit in DAC1CON1bits
7174 #define DAC1R4 DAC1CON1bits.DAC1R4 // bit 4, shadows bit in DAC1CON1bits
7175 #define DACR4 DAC1CON1bits.DACR4 // bit 4, shadows bit in DAC1CON1bits
7176 #define DAC1R5 DAC1CON1bits.DAC1R5 // bit 5, shadows bit in DAC1CON1bits
7177 #define DACR5 DAC1CON1bits.DACR5 // bit 5, shadows bit in DAC1CON1bits
7178 #define DAC1R6 DAC1CON1bits.DAC1R6 // bit 6, shadows bit in DAC1CON1bits
7179 #define DACR6 DAC1CON1bits.DACR6 // bit 6, shadows bit in DAC1CON1bits
7180 #define DAC1R7 DAC1CON1bits.DAC1R7 // bit 7, shadows bit in DAC1CON1bits
7181 #define DACR7 DAC1CON1bits.DACR7 // bit 7, shadows bit in DAC1CON1bits
7183 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
7184 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
7185 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
7186 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
7187 #define TSRNG FVRCONbits.TSRNG // bit 4
7188 #define TSEN FVRCONbits.TSEN // bit 5
7189 #define FVRRDY FVRCONbits.FVRRDY // bit 6
7190 #define FVREN FVRCONbits.FVREN // bit 7
7192 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
7193 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
7194 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
7195 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
7196 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
7197 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
7199 #define INLVLB4 INLVLBbits.INLVLB4 // bit 4
7200 #define INLVLB5 INLVLBbits.INLVLB5 // bit 5
7201 #define INLVLB6 INLVLBbits.INLVLB6 // bit 6
7202 #define INLVLB7 INLVLBbits.INLVLB7 // bit 7
7204 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
7205 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
7206 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
7207 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
7208 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
7209 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
7210 #define INLVLC6 INLVLCbits.INLVLC6 // bit 6
7211 #define INLVLC7 INLVLCbits.INLVLC7 // bit 7
7213 #define IOCIF INTCONbits.IOCIF // bit 0
7214 #define INTF INTCONbits.INTF // bit 1
7215 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
7216 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
7217 #define IOCIE INTCONbits.IOCIE // bit 3
7218 #define INTE INTCONbits.INTE // bit 4
7219 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
7220 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
7221 #define PEIE INTCONbits.PEIE // bit 6
7222 #define GIE INTCONbits.GIE // bit 7
7224 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
7225 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
7226 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
7227 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
7228 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
7229 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
7231 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
7232 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
7233 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
7234 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
7235 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
7236 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
7238 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
7239 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
7240 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
7241 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
7242 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
7243 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
7245 #define IOCBF4 IOCBFbits.IOCBF4 // bit 4
7246 #define IOCBF5 IOCBFbits.IOCBF5 // bit 5
7247 #define IOCBF6 IOCBFbits.IOCBF6 // bit 6
7248 #define IOCBF7 IOCBFbits.IOCBF7 // bit 7
7250 #define IOCBN4 IOCBNbits.IOCBN4 // bit 4
7251 #define IOCBN5 IOCBNbits.IOCBN5 // bit 5
7252 #define IOCBN6 IOCBNbits.IOCBN6 // bit 6
7253 #define IOCBN7 IOCBNbits.IOCBN7 // bit 7
7255 #define IOCBP4 IOCBPbits.IOCBP4 // bit 4
7256 #define IOCBP5 IOCBPbits.IOCBP5 // bit 5
7257 #define IOCBP6 IOCBPbits.IOCBP6 // bit 6
7258 #define IOCBP7 IOCBPbits.IOCBP7 // bit 7
7260 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
7261 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
7262 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
7263 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
7264 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
7265 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
7266 #define IOCCF6 IOCCFbits.IOCCF6 // bit 6
7267 #define IOCCF7 IOCCFbits.IOCCF7 // bit 7
7269 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
7270 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
7271 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
7272 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
7273 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
7274 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
7275 #define IOCCN6 IOCCNbits.IOCCN6 // bit 6
7276 #define IOCCN7 IOCCNbits.IOCCN7 // bit 7
7278 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
7279 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
7280 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
7281 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
7282 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
7283 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
7284 #define IOCCP6 IOCCPbits.IOCCP6 // bit 6
7285 #define IOCCP7 IOCCPbits.IOCCP7 // bit 7
7287 #define LATA0 LATAbits.LATA0 // bit 0
7288 #define LATA1 LATAbits.LATA1 // bit 1
7289 #define LATA2 LATAbits.LATA2 // bit 2
7290 #define LATA4 LATAbits.LATA4 // bit 4
7291 #define LATA5 LATAbits.LATA5 // bit 5
7293 #define LATB4 LATBbits.LATB4 // bit 4
7294 #define LATB5 LATBbits.LATB5 // bit 5
7295 #define LATB6 LATBbits.LATB6 // bit 6
7296 #define LATB7 LATBbits.LATB7 // bit 7
7298 #define LATC0 LATCbits.LATC0 // bit 0
7299 #define LATC1 LATCbits.LATC1 // bit 1
7300 #define LATC2 LATCbits.LATC2 // bit 2
7301 #define LATC3 LATCbits.LATC3 // bit 3
7302 #define LATC4 LATCbits.LATC4 // bit 4
7303 #define LATC5 LATCbits.LATC5 // bit 5
7304 #define LATC6 LATCbits.LATC6 // bit 6
7305 #define LATC7 LATCbits.LATC7 // bit 7
7307 #define ODA0 ODCONAbits.ODA0 // bit 0
7308 #define ODA1 ODCONAbits.ODA1 // bit 1
7309 #define ODA2 ODCONAbits.ODA2 // bit 2
7310 #define ODA4 ODCONAbits.ODA4 // bit 4
7311 #define ODA5 ODCONAbits.ODA5 // bit 5
7313 #define ODB4 ODCONBbits.ODB4 // bit 4
7314 #define ODB5 ODCONBbits.ODB5 // bit 5
7315 #define ODB6 ODCONBbits.ODB6 // bit 6
7316 #define ODB7 ODCONBbits.ODB7 // bit 7
7318 #define ODC0 ODCONCbits.ODC0 // bit 0
7319 #define ODC1 ODCONCbits.ODC1 // bit 1
7320 #define ODC2 ODCONCbits.ODC2 // bit 2
7321 #define ODC3 ODCONCbits.ODC3 // bit 3
7322 #define ODC4 ODCONCbits.ODC4 // bit 4
7323 #define ODC5 ODCONCbits.ODC5 // bit 5
7324 #define ODC6 ODCONCbits.ODC6 // bit 6
7325 #define ODC7 ODCONCbits.ODC7 // bit 7
7327 #define OPA1PCH0 OPA1CONbits.OPA1PCH0 // bit 0
7328 #define OPA1PCH1 OPA1CONbits.OPA1PCH1 // bit 1
7329 #define OPA1UG OPA1CONbits.OPA1UG // bit 4
7330 #define OPA1SP OPA1CONbits.OPA1SP // bit 6
7331 #define OPA1EN OPA1CONbits.OPA1EN // bit 7
7333 #define OPA2PCH0 OPA2CONbits.OPA2PCH0 // bit 0
7334 #define OPA2PCH1 OPA2CONbits.OPA2PCH1 // bit 1
7335 #define OPA2UG OPA2CONbits.OPA2UG // bit 4
7336 #define OPA2SP OPA2CONbits.OPA2SP // bit 6
7337 #define OPA2EN OPA2CONbits.OPA2EN // bit 7
7339 #define PS0 OPTION_REGbits.PS0 // bit 0
7340 #define PS1 OPTION_REGbits.PS1 // bit 1
7341 #define PS2 OPTION_REGbits.PS2 // bit 2
7342 #define PSA OPTION_REGbits.PSA // bit 3
7343 #define TMR0SE OPTION_REGbits.TMR0SE // bit 4, shadows bit in OPTION_REGbits
7344 #define T0SE OPTION_REGbits.T0SE // bit 4, shadows bit in OPTION_REGbits
7345 #define TMR0CS OPTION_REGbits.TMR0CS // bit 5, shadows bit in OPTION_REGbits
7346 #define T0CS OPTION_REGbits.T0CS // bit 5, shadows bit in OPTION_REGbits
7347 #define INTEDG OPTION_REGbits.INTEDG // bit 6
7348 #define NOT_WPUEN OPTION_REGbits.NOT_WPUEN // bit 7
7350 #define SCS0 OSCCONbits.SCS0 // bit 0
7351 #define SCS1 OSCCONbits.SCS1 // bit 1
7352 #define IRCF0 OSCCONbits.IRCF0 // bit 3
7353 #define IRCF1 OSCCONbits.IRCF1 // bit 4
7354 #define IRCF2 OSCCONbits.IRCF2 // bit 5
7355 #define IRCF3 OSCCONbits.IRCF3 // bit 6
7356 #define SPLLEN OSCCONbits.SPLLEN // bit 7
7358 #define HFIOFS OSCSTATbits.HFIOFS // bit 0
7359 #define LFIOFR OSCSTATbits.LFIOFR // bit 1
7360 #define MFIOFR OSCSTATbits.MFIOFR // bit 2
7361 #define HFIOFL OSCSTATbits.HFIOFL // bit 3
7362 #define HFIOFR OSCSTATbits.HFIOFR // bit 4
7363 #define OSTS OSCSTATbits.OSTS // bit 5
7364 #define PLLR OSCSTATbits.PLLR // bit 6
7365 #define SOSCR OSCSTATbits.SOSCR // bit 7
7367 #define TUN0 OSCTUNEbits.TUN0 // bit 0
7368 #define TUN1 OSCTUNEbits.TUN1 // bit 1
7369 #define TUN2 OSCTUNEbits.TUN2 // bit 2
7370 #define TUN3 OSCTUNEbits.TUN3 // bit 3
7371 #define TUN4 OSCTUNEbits.TUN4 // bit 4
7372 #define TUN5 OSCTUNEbits.TUN5 // bit 5
7374 #define NOT_BOR PCONbits.NOT_BOR // bit 0
7375 #define NOT_POR PCONbits.NOT_POR // bit 1
7376 #define NOT_RI PCONbits.NOT_RI // bit 2
7377 #define NOT_RMCLR PCONbits.NOT_RMCLR // bit 3
7378 #define NOT_RWDT PCONbits.NOT_RWDT // bit 4
7379 #define STKUNF PCONbits.STKUNF // bit 6
7380 #define STKOVF PCONbits.STKOVF // bit 7
7382 #define TMR1IE PIE1bits.TMR1IE // bit 0
7383 #define TMR2IE PIE1bits.TMR2IE // bit 1
7384 #define CCP1IE PIE1bits.CCP1IE // bit 2, shadows bit in PIE1bits
7385 #define CCPIE PIE1bits.CCPIE // bit 2, shadows bit in PIE1bits
7386 #define SSP1IE PIE1bits.SSP1IE // bit 3
7387 #define TXIE PIE1bits.TXIE // bit 4
7388 #define RCIE PIE1bits.RCIE // bit 5
7389 #define ADIE PIE1bits.ADIE // bit 6
7390 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
7392 #define CCP2IE PIE2bits.CCP2IE // bit 0
7393 #define TMR4IE PIE2bits.TMR4IE // bit 1
7394 #define TMR6IE PIE2bits.TMR6IE // bit 2
7395 #define BCL1IE PIE2bits.BCL1IE // bit 3
7396 #define C1IE PIE2bits.C1IE // bit 5
7397 #define C2IE PIE2bits.C2IE // bit 6
7398 #define OSFIE PIE2bits.OSFIE // bit 7
7400 #define CLC1IE PIE3bits.CLC1IE // bit 0
7401 #define CLC2IE PIE3bits.CLC2IE // bit 1
7402 #define CLC3IE PIE3bits.CLC3IE // bit 2
7403 #define ZCDIE PIE3bits.ZCDIE // bit 4
7404 #define COGIE PIE3bits.COGIE // bit 5
7406 #define TMR1IF PIR1bits.TMR1IF // bit 0
7407 #define TMR2IF PIR1bits.TMR2IF // bit 1
7408 #define CCP1IF PIR1bits.CCP1IF // bit 2, shadows bit in PIR1bits
7409 #define CCPIF PIR1bits.CCPIF // bit 2, shadows bit in PIR1bits
7410 #define SSP1IF PIR1bits.SSP1IF // bit 3
7411 #define TXIF PIR1bits.TXIF // bit 4
7412 #define RCIF PIR1bits.RCIF // bit 5
7413 #define ADIF PIR1bits.ADIF // bit 6
7414 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
7416 #define CCP2IF PIR2bits.CCP2IF // bit 0
7417 #define TMR4IF PIR2bits.TMR4IF // bit 1
7418 #define TMR6IF PIR2bits.TMR6IF // bit 2
7419 #define BCL1IF PIR2bits.BCL1IF // bit 3
7420 #define C1IF PIR2bits.C1IF // bit 5
7421 #define C2IF PIR2bits.C2IF // bit 6
7422 #define OSFIF PIR2bits.OSFIF // bit 7
7424 #define CLC1IF PIR3bits.CLC1IF // bit 0
7425 #define CLC2IF PIR3bits.CLC2IF // bit 1
7426 #define CLC3IF PIR3bits.CLC3IF // bit 2
7427 #define ZCDIF PIR3bits.ZCDIF // bit 4
7428 #define COGIF PIR3bits.COGIF // bit 5
7430 #define RD PMCON1bits.RD // bit 0
7431 #define WR PMCON1bits.WR // bit 1
7432 #define WREN PMCON1bits.WREN // bit 2
7433 #define WRERR PMCON1bits.WRERR // bit 3
7434 #define FREE PMCON1bits.FREE // bit 4
7435 #define LWLO PMCON1bits.LWLO // bit 5
7436 #define CFGS PMCON1bits.CFGS // bit 6
7438 #define RA0 PORTAbits.RA0 // bit 0
7439 #define RA1 PORTAbits.RA1 // bit 1
7440 #define RA2 PORTAbits.RA2 // bit 2
7441 #define RA3 PORTAbits.RA3 // bit 3
7442 #define RA4 PORTAbits.RA4 // bit 4
7443 #define RA5 PORTAbits.RA5 // bit 5
7445 #define RB4 PORTBbits.RB4 // bit 4
7446 #define RB5 PORTBbits.RB5 // bit 5
7447 #define RB6 PORTBbits.RB6 // bit 6
7448 #define RB7 PORTBbits.RB7 // bit 7
7450 #define RC0 PORTCbits.RC0 // bit 0
7451 #define RC1 PORTCbits.RC1 // bit 1
7452 #define RC2 PORTCbits.RC2 // bit 2
7453 #define RC3 PORTCbits.RC3 // bit 3
7454 #define RC4 PORTCbits.RC4 // bit 4
7455 #define RC5 PORTCbits.RC5 // bit 5
7456 #define RC6 PORTCbits.RC6 // bit 6
7457 #define RC7 PORTCbits.RC7 // bit 7
7459 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
7461 #define PWM3POL PWM3CONbits.PWM3POL // bit 4
7462 #define PWM3OUT PWM3CONbits.PWM3OUT // bit 5
7463 #define PWM3EN PWM3CONbits.PWM3EN // bit 7
7465 #define PWM3DCH0 PWM3DCHbits.PWM3DCH0 // bit 0
7466 #define PWM3DCH1 PWM3DCHbits.PWM3DCH1 // bit 1
7467 #define PWM3DCH2 PWM3DCHbits.PWM3DCH2 // bit 2
7468 #define PWM3DCH3 PWM3DCHbits.PWM3DCH3 // bit 3
7469 #define PWM3DCH4 PWM3DCHbits.PWM3DCH4 // bit 4
7470 #define PWM3DCH5 PWM3DCHbits.PWM3DCH5 // bit 5
7471 #define PWM3DCH6 PWM3DCHbits.PWM3DCH6 // bit 6
7472 #define PWM3DCH7 PWM3DCHbits.PWM3DCH7 // bit 7
7474 #define PWM3DCL0 PWM3DCLbits.PWM3DCL0 // bit 6
7475 #define PWM3DCL1 PWM3DCLbits.PWM3DCL1 // bit 7
7477 #define PWM4POL PWM4CONbits.PWM4POL // bit 4
7478 #define PWM4OUT PWM4CONbits.PWM4OUT // bit 5
7479 #define PWM4EN PWM4CONbits.PWM4EN // bit 7
7481 #define PWM4DCH0 PWM4DCHbits.PWM4DCH0 // bit 0
7482 #define PWM4DCH1 PWM4DCHbits.PWM4DCH1 // bit 1
7483 #define PWM4DCH2 PWM4DCHbits.PWM4DCH2 // bit 2
7484 #define PWM4DCH3 PWM4DCHbits.PWM4DCH3 // bit 3
7485 #define PWM4DCH4 PWM4DCHbits.PWM4DCH4 // bit 4
7486 #define PWM4DCH5 PWM4DCHbits.PWM4DCH5 // bit 5
7487 #define PWM4DCH6 PWM4DCHbits.PWM4DCH6 // bit 6
7488 #define PWM4DCH7 PWM4DCHbits.PWM4DCH7 // bit 7
7490 #define PWM4DCL0 PWM4DCLbits.PWM4DCL0 // bit 6
7491 #define PWM4DCL1 PWM4DCLbits.PWM4DCL1 // bit 7
7493 #define RX9D RC1STAbits.RX9D // bit 0
7494 #define OERR RC1STAbits.OERR // bit 1
7495 #define FERR RC1STAbits.FERR // bit 2
7496 #define ADDEN RC1STAbits.ADDEN // bit 3
7497 #define CREN RC1STAbits.CREN // bit 4
7498 #define SREN RC1STAbits.SREN // bit 5
7499 #define RX9 RC1STAbits.RX9 // bit 6
7500 #define SPEN RC1STAbits.SPEN // bit 7
7502 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
7503 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
7504 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
7505 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
7506 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
7508 #define SLRB4 SLRCONBbits.SLRB4 // bit 4
7509 #define SLRB5 SLRCONBbits.SLRB5 // bit 5
7510 #define SLRB6 SLRCONBbits.SLRB6 // bit 6
7511 #define SLRB7 SLRCONBbits.SLRB7 // bit 7
7513 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
7514 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
7515 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
7516 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
7517 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
7518 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
7519 #define SLRC6 SLRCONCbits.SLRC6 // bit 6
7520 #define SLRC7 SLRCONCbits.SLRC7 // bit 7
7522 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
7523 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
7524 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
7525 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
7526 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
7527 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
7528 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
7529 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
7530 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
7531 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
7532 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
7533 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
7534 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
7535 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
7536 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
7537 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
7539 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
7540 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
7541 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
7542 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
7543 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
7544 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
7545 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
7546 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
7547 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
7548 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
7549 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
7550 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
7551 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
7552 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
7553 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
7554 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
7556 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
7557 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
7558 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
7559 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
7560 #define CKP SSP1CONbits.CKP // bit 4
7561 #define SSPEN SSP1CONbits.SSPEN // bit 5
7562 #define SSPOV SSP1CONbits.SSPOV // bit 6
7563 #define WCOL SSP1CONbits.WCOL // bit 7
7565 #define SEN SSP1CON2bits.SEN // bit 0
7566 #define RSEN SSP1CON2bits.RSEN // bit 1
7567 #define PEN SSP1CON2bits.PEN // bit 2
7568 #define RCEN SSP1CON2bits.RCEN // bit 3
7569 #define ACKEN SSP1CON2bits.ACKEN // bit 4
7570 #define ACKDT SSP1CON2bits.ACKDT // bit 5
7571 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
7572 #define GCEN SSP1CON2bits.GCEN // bit 7
7574 #define DHEN SSP1CON3bits.DHEN // bit 0
7575 #define AHEN SSP1CON3bits.AHEN // bit 1
7576 #define SBCDE SSP1CON3bits.SBCDE // bit 2
7577 #define SDAHT SSP1CON3bits.SDAHT // bit 3
7578 #define BOEN SSP1CON3bits.BOEN // bit 4
7579 #define SCIE SSP1CON3bits.SCIE // bit 5
7580 #define PCIE SSP1CON3bits.PCIE // bit 6
7581 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
7583 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
7584 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
7585 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
7586 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
7587 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
7588 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
7589 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
7590 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
7591 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
7592 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
7593 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
7594 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
7595 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
7596 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
7597 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
7598 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
7600 #define BF SSP1STATbits.BF // bit 0
7601 #define UA SSP1STATbits.UA // bit 1
7602 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
7603 #define S SSP1STATbits.S // bit 3
7604 #define P SSP1STATbits.P // bit 4
7605 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
7606 #define CKE SSP1STATbits.CKE // bit 6
7607 #define SMP SSP1STATbits.SMP // bit 7
7609 #define C STATUSbits.C // bit 0
7610 #define DC STATUSbits.DC // bit 1
7611 #define Z STATUSbits.Z // bit 2
7612 #define NOT_PD STATUSbits.NOT_PD // bit 3
7613 #define NOT_TO STATUSbits.NOT_TO // bit 4
7615 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
7616 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
7617 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
7619 #define TMR1ON T1CONbits.TMR1ON // bit 0
7620 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
7621 #define T1OSCEN T1CONbits.T1OSCEN // bit 3
7622 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
7623 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
7624 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
7625 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
7627 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
7628 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
7629 #define T1GVAL T1GCONbits.T1GVAL // bit 2
7630 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3
7631 #define T1GSPM T1GCONbits.T1GSPM // bit 4
7632 #define T1GTM T1GCONbits.T1GTM // bit 5
7633 #define T1GPOL T1GCONbits.T1GPOL // bit 6
7634 #define TMR1GE T1GCONbits.TMR1GE // bit 7
7636 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
7637 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
7638 #define TMR2ON T2CONbits.TMR2ON // bit 2
7639 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
7640 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
7641 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
7642 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
7644 #define T4CKPS0 T4CONbits.T4CKPS0 // bit 0
7645 #define T4CKPS1 T4CONbits.T4CKPS1 // bit 1
7646 #define TMR4ON T4CONbits.TMR4ON // bit 2
7647 #define T4OUTPS0 T4CONbits.T4OUTPS0 // bit 3
7648 #define T4OUTPS1 T4CONbits.T4OUTPS1 // bit 4
7649 #define T4OUTPS2 T4CONbits.T4OUTPS2 // bit 5
7650 #define T4OUTPS3 T4CONbits.T4OUTPS3 // bit 6
7652 #define T6CKPS0 T6CONbits.T6CKPS0 // bit 0
7653 #define T6CKPS1 T6CONbits.T6CKPS1 // bit 1
7654 #define TMR6ON T6CONbits.TMR6ON // bit 2
7655 #define T6OUTPS0 T6CONbits.T6OUTPS0 // bit 3
7656 #define T6OUTPS1 T6CONbits.T6OUTPS1 // bit 4
7657 #define T6OUTPS2 T6CONbits.T6OUTPS2 // bit 5
7658 #define T6OUTPS3 T6CONbits.T6OUTPS3 // bit 6
7660 #define TRISA0 TRISAbits.TRISA0 // bit 0
7661 #define TRISA1 TRISAbits.TRISA1 // bit 1
7662 #define TRISA2 TRISAbits.TRISA2 // bit 2
7663 #define TRISA4 TRISAbits.TRISA4 // bit 4
7664 #define TRISA5 TRISAbits.TRISA5 // bit 5
7666 #define TRISB4 TRISBbits.TRISB4 // bit 4
7667 #define TRISB5 TRISBbits.TRISB5 // bit 5
7668 #define TRISB6 TRISBbits.TRISB6 // bit 6
7669 #define TRISB7 TRISBbits.TRISB7 // bit 7
7671 #define TRISC0 TRISCbits.TRISC0 // bit 0
7672 #define TRISC1 TRISCbits.TRISC1 // bit 1
7673 #define TRISC2 TRISCbits.TRISC2 // bit 2
7674 #define TRISC3 TRISCbits.TRISC3 // bit 3
7675 #define TRISC4 TRISCbits.TRISC4 // bit 4
7676 #define TRISC5 TRISCbits.TRISC5 // bit 5
7677 #define TRISC6 TRISCbits.TRISC6 // bit 6
7678 #define TRISC7 TRISCbits.TRISC7 // bit 7
7680 #define TX9D TX1STAbits.TX9D // bit 0
7681 #define TRMT TX1STAbits.TRMT // bit 1
7682 #define BRGH TX1STAbits.BRGH // bit 2
7683 #define SENDB TX1STAbits.SENDB // bit 3
7684 #define SYNC TX1STAbits.SYNC // bit 4
7685 #define TXEN TX1STAbits.TXEN // bit 5
7686 #define TX9 TX1STAbits.TX9 // bit 6
7687 #define CSRC TX1STAbits.CSRC // bit 7
7689 #define Reserved VREGCONbits.Reserved // bit 0
7690 #define VREGPM VREGCONbits.VREGPM // bit 1
7692 #define SWDTEN WDTCONbits.SWDTEN // bit 0
7693 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
7694 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
7695 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
7696 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
7697 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
7699 #define WPUA0 WPUAbits.WPUA0 // bit 0
7700 #define WPUA1 WPUAbits.WPUA1 // bit 1
7701 #define WPUA2 WPUAbits.WPUA2 // bit 2
7702 #define WPUA3 WPUAbits.WPUA3 // bit 3
7703 #define WPUA4 WPUAbits.WPUA4 // bit 4
7704 #define WPUA5 WPUAbits.WPUA5 // bit 5
7706 #define WPUB4 WPUBbits.WPUB4 // bit 4
7707 #define WPUB5 WPUBbits.WPUB5 // bit 5
7708 #define WPUB6 WPUBbits.WPUB6 // bit 6
7709 #define WPUB7 WPUBbits.WPUB7 // bit 7
7711 #define WPUC0 WPUCbits.WPUC0 // bit 0
7712 #define WPUC1 WPUCbits.WPUC1 // bit 1
7713 #define WPUC2 WPUCbits.WPUC2 // bit 2
7714 #define WPUC3 WPUCbits.WPUC3 // bit 3
7715 #define WPUC4 WPUCbits.WPUC4 // bit 4
7716 #define WPUC5 WPUCbits.WPUC5 // bit 5
7717 #define WPUC6 WPUCbits.WPUC6 // bit 6
7718 #define WPUC7 WPUCbits.WPUC7 // bit 7
7720 #define ZCD1INTN ZCD1CONbits.ZCD1INTN // bit 0
7721 #define ZCD1INTP ZCD1CONbits.ZCD1INTP // bit 1
7722 #define ZCD1POL ZCD1CONbits.ZCD1POL // bit 4
7723 #define ZCD1OUT ZCD1CONbits.ZCD1OUT // bit 5
7724 #define ZCD1EN ZCD1CONbits.ZCD1EN // bit 7
7726 #endif // #ifndef NO_BIT_DEFINES
7728 #endif // #ifndef __PIC16F1708_H__