2 * This declarations of the PIC16F1709 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:12 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F1709_H__
26 #define __PIC16F1709_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTB_ADDR 0x000D
52 #define PORTC_ADDR 0x000E
53 #define PIR1_ADDR 0x0011
54 #define PIR2_ADDR 0x0012
55 #define PIR3_ADDR 0x0013
56 #define TMR0_ADDR 0x0015
57 #define TMR1_ADDR 0x0016
58 #define TMR1L_ADDR 0x0016
59 #define TMR1H_ADDR 0x0017
60 #define T1CON_ADDR 0x0018
61 #define T1GCON_ADDR 0x0019
62 #define TMR2_ADDR 0x001A
63 #define PR2_ADDR 0x001B
64 #define T2CON_ADDR 0x001C
65 #define TRISA_ADDR 0x008C
66 #define TRISB_ADDR 0x008D
67 #define TRISC_ADDR 0x008E
68 #define PIE1_ADDR 0x0091
69 #define PIE2_ADDR 0x0092
70 #define PIE3_ADDR 0x0093
71 #define OPTION_REG_ADDR 0x0095
72 #define PCON_ADDR 0x0096
73 #define WDTCON_ADDR 0x0097
74 #define OSCTUNE_ADDR 0x0098
75 #define OSCCON_ADDR 0x0099
76 #define OSCSTAT_ADDR 0x009A
77 #define ADRES_ADDR 0x009B
78 #define ADRESL_ADDR 0x009B
79 #define ADRESH_ADDR 0x009C
80 #define ADCON0_ADDR 0x009D
81 #define ADCON1_ADDR 0x009E
82 #define ADCON2_ADDR 0x009F
83 #define LATA_ADDR 0x010C
84 #define LATB_ADDR 0x010D
85 #define LATC_ADDR 0x010E
86 #define CM1CON0_ADDR 0x0111
87 #define CM1CON1_ADDR 0x0112
88 #define CM2CON0_ADDR 0x0113
89 #define CM2CON1_ADDR 0x0114
90 #define CMOUT_ADDR 0x0115
91 #define BORCON_ADDR 0x0116
92 #define FVRCON_ADDR 0x0117
93 #define DAC1CON0_ADDR 0x0118
94 #define DAC1CON1_ADDR 0x0119
95 #define ZCD1CON_ADDR 0x011C
96 #define ANSELA_ADDR 0x018C
97 #define ANSELB_ADDR 0x018D
98 #define ANSELC_ADDR 0x018E
99 #define PMADR_ADDR 0x0191
100 #define PMADRL_ADDR 0x0191
101 #define PMADRH_ADDR 0x0192
102 #define PMDAT_ADDR 0x0193
103 #define PMDATL_ADDR 0x0193
104 #define PMDATH_ADDR 0x0194
105 #define PMCON1_ADDR 0x0195
106 #define PMCON2_ADDR 0x0196
107 #define VREGCON_ADDR 0x0197
108 #define RC1REG_ADDR 0x0199
109 #define RCREG_ADDR 0x0199
110 #define RCREG1_ADDR 0x0199
111 #define TX1REG_ADDR 0x019A
112 #define TXREG_ADDR 0x019A
113 #define TXREG1_ADDR 0x019A
114 #define SP1BRG_ADDR 0x019B
115 #define SP1BRGL_ADDR 0x019B
116 #define SPBRG_ADDR 0x019B
117 #define SPBRG1_ADDR 0x019B
118 #define SPBRGL_ADDR 0x019B
119 #define SP1BRGH_ADDR 0x019C
120 #define SPBRGH_ADDR 0x019C
121 #define SPBRGH1_ADDR 0x019C
122 #define RC1STA_ADDR 0x019D
123 #define RCSTA_ADDR 0x019D
124 #define RCSTA1_ADDR 0x019D
125 #define TX1STA_ADDR 0x019E
126 #define TXSTA_ADDR 0x019E
127 #define TXSTA1_ADDR 0x019E
128 #define BAUD1CON_ADDR 0x019F
129 #define BAUDCON_ADDR 0x019F
130 #define BAUDCON1_ADDR 0x019F
131 #define BAUDCTL_ADDR 0x019F
132 #define BAUDCTL1_ADDR 0x019F
133 #define WPUA_ADDR 0x020C
134 #define WPUB_ADDR 0x020D
135 #define WPUC_ADDR 0x020E
136 #define SSP1BUF_ADDR 0x0211
137 #define SSPBUF_ADDR 0x0211
138 #define SSP1ADD_ADDR 0x0212
139 #define SSPADD_ADDR 0x0212
140 #define SSP1MSK_ADDR 0x0213
141 #define SSPMSK_ADDR 0x0213
142 #define SSP1STAT_ADDR 0x0214
143 #define SSPSTAT_ADDR 0x0214
144 #define SSP1CON_ADDR 0x0215
145 #define SSP1CON1_ADDR 0x0215
146 #define SSPCON_ADDR 0x0215
147 #define SSPCON1_ADDR 0x0215
148 #define SSP1CON2_ADDR 0x0216
149 #define SSPCON2_ADDR 0x0216
150 #define SSP1CON3_ADDR 0x0217
151 #define SSPCON3_ADDR 0x0217
152 #define ODCONA_ADDR 0x028C
153 #define ODCONB_ADDR 0x028D
154 #define ODCONC_ADDR 0x028E
155 #define CCPR1_ADDR 0x0291
156 #define CCPR1L_ADDR 0x0291
157 #define CCPR1H_ADDR 0x0292
158 #define CCP1CON_ADDR 0x0293
159 #define ECCP1CON_ADDR 0x0293
160 #define CCPR2_ADDR 0x0298
161 #define CCPR2L_ADDR 0x0298
162 #define CCPR2H_ADDR 0x0299
163 #define CCP2CON_ADDR 0x029A
164 #define ECCP2CON_ADDR 0x029A
165 #define CCPTMRS_ADDR 0x029E
166 #define SLRCONA_ADDR 0x030C
167 #define SLRCONB_ADDR 0x030D
168 #define SLRCONC_ADDR 0x030E
169 #define INLVLA_ADDR 0x038C
170 #define INLVLB_ADDR 0x038D
171 #define INLVLC_ADDR 0x038E
172 #define IOCAP_ADDR 0x0391
173 #define IOCAN_ADDR 0x0392
174 #define IOCAF_ADDR 0x0393
175 #define IOCBP_ADDR 0x0394
176 #define IOCBN_ADDR 0x0395
177 #define IOCBF_ADDR 0x0396
178 #define IOCCP_ADDR 0x0397
179 #define IOCCN_ADDR 0x0398
180 #define IOCCF_ADDR 0x0399
181 #define TMR4_ADDR 0x0415
182 #define PR4_ADDR 0x0416
183 #define T4CON_ADDR 0x0417
184 #define TMR6_ADDR 0x041C
185 #define PR6_ADDR 0x041D
186 #define T6CON_ADDR 0x041E
187 #define OPA1CON_ADDR 0x0511
188 #define OPA2CON_ADDR 0x0515
189 #define PWM3DCL_ADDR 0x0617
190 #define PWM3DCH_ADDR 0x0618
191 #define PWM3CON_ADDR 0x0619
192 #define PWM3CON0_ADDR 0x0619
193 #define PWM4DCL_ADDR 0x061A
194 #define PWM4DCH_ADDR 0x061B
195 #define PWM4CON_ADDR 0x061C
196 #define PWM4CON0_ADDR 0x061C
197 #define COG1PHR_ADDR 0x0691
198 #define COG1PHF_ADDR 0x0692
199 #define COG1BLKR_ADDR 0x0693
200 #define COG1BLKF_ADDR 0x0694
201 #define COG1DBR_ADDR 0x0695
202 #define COG1DBF_ADDR 0x0696
203 #define COG1CON0_ADDR 0x0697
204 #define COG1CON1_ADDR 0x0698
205 #define COG1RIS_ADDR 0x0699
206 #define COG1RSIM_ADDR 0x069A
207 #define COG1FIS_ADDR 0x069B
208 #define COG1FSIM_ADDR 0x069C
209 #define COG1ASD0_ADDR 0x069D
210 #define COG1ASD1_ADDR 0x069E
211 #define COG1STR_ADDR 0x069F
212 #define PPSLOCK_ADDR 0x0E0F
213 #define INTPPS_ADDR 0x0E10
214 #define T0CKIPPS_ADDR 0x0E11
215 #define T1CKIPPS_ADDR 0x0E12
216 #define T1GPPS_ADDR 0x0E13
217 #define CCP1PPS_ADDR 0x0E14
218 #define CCP2PPS_ADDR 0x0E15
219 #define COGINPPS_ADDR 0x0E17
220 #define SSPCLKPPS_ADDR 0x0E20
221 #define SSPDATPPS_ADDR 0x0E21
222 #define SSPSSPPS_ADDR 0x0E22
223 #define RXPPS_ADDR 0x0E24
224 #define CKPPS_ADDR 0x0E25
225 #define CLCIN0PPS_ADDR 0x0E28
226 #define CLCIN1PPS_ADDR 0x0E29
227 #define CLCIN2PPS_ADDR 0x0E2A
228 #define CLCIN3PPS_ADDR 0x0E2B
229 #define RA0PPS_ADDR 0x0E90
230 #define RA1PPS_ADDR 0x0E91
231 #define RA2PPS_ADDR 0x0E92
232 #define RA4PPS_ADDR 0x0E94
233 #define RA5PPS_ADDR 0x0E95
234 #define RB4PPS_ADDR 0x0E9C
235 #define RB5PPS_ADDR 0x0E9D
236 #define RB6PPS_ADDR 0x0E9E
237 #define RB7PPS_ADDR 0x0E9F
238 #define RC0PPS_ADDR 0x0EA0
239 #define RC1PPS_ADDR 0x0EA1
240 #define RC2PPS_ADDR 0x0EA2
241 #define RC3PPS_ADDR 0x0EA3
242 #define RC4PPS_ADDR 0x0EA4
243 #define RC5PPS_ADDR 0x0EA5
244 #define RC6PPS_ADDR 0x0EA6
245 #define RC7PPS_ADDR 0x0EA7
246 #define CLCDATA_ADDR 0x0F0F
247 #define CLC1CON_ADDR 0x0F10
248 #define CLC1POL_ADDR 0x0F11
249 #define CLC1SEL0_ADDR 0x0F12
250 #define CLC1SEL1_ADDR 0x0F13
251 #define CLC1SEL2_ADDR 0x0F14
252 #define CLC1SEL3_ADDR 0x0F15
253 #define CLC1GLS0_ADDR 0x0F16
254 #define CLC1GLS1_ADDR 0x0F17
255 #define CLC1GLS2_ADDR 0x0F18
256 #define CLC1GLS3_ADDR 0x0F19
257 #define CLC2CON_ADDR 0x0F1A
258 #define CLC2POL_ADDR 0x0F1B
259 #define CLC2SEL0_ADDR 0x0F1C
260 #define CLC2SEL1_ADDR 0x0F1D
261 #define CLC2SEL2_ADDR 0x0F1E
262 #define CLC2SEL3_ADDR 0x0F1F
263 #define CLC2GLS0_ADDR 0x0F20
264 #define CLC2GLS1_ADDR 0x0F21
265 #define CLC2GLS2_ADDR 0x0F22
266 #define CLC2GLS3_ADDR 0x0F23
267 #define CLC3CON_ADDR 0x0F24
268 #define CLC3POL_ADDR 0x0F25
269 #define CLC3SEL0_ADDR 0x0F26
270 #define CLC3SEL1_ADDR 0x0F27
271 #define CLC3SEL2_ADDR 0x0F28
272 #define CLC3SEL3_ADDR 0x0F29
273 #define CLC3GLS0_ADDR 0x0F2A
274 #define CLC3GLS1_ADDR 0x0F2B
275 #define CLC3GLS2_ADDR 0x0F2C
276 #define CLC3GLS3_ADDR 0x0F2D
277 #define ICDBK0H_ADDR 0x0F9E
278 #define STATUS_SHAD_ADDR 0x0FE4
279 #define WREG_SHAD_ADDR 0x0FE5
280 #define BSR_SHAD_ADDR 0x0FE6
281 #define PCLATH_SHAD_ADDR 0x0FE7
282 #define FSR0L_SHAD_ADDR 0x0FE8
283 #define FSR0H_SHAD_ADDR 0x0FE9
284 #define FSR1L_SHAD_ADDR 0x0FEA
285 #define FSR1H_SHAD_ADDR 0x0FEB
286 #define STKPTR_ADDR 0x0FED
287 #define TOSL_ADDR 0x0FEE
288 #define TOSH_ADDR 0x0FEF
290 #endif // #ifndef NO_ADDR_DEFINES
292 //==============================================================================
294 // Register Definitions
296 //==============================================================================
298 extern __at(0x0000) __sfr INDF0
;
299 extern __at(0x0001) __sfr INDF1
;
300 extern __at(0x0002) __sfr PCL
;
302 //==============================================================================
305 extern __at(0x0003) __sfr STATUS
;
319 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
327 //==============================================================================
329 extern __at(0x0004) __sfr FSR0
;
330 extern __at(0x0004) __sfr FSR0L
;
331 extern __at(0x0005) __sfr FSR0H
;
332 extern __at(0x0006) __sfr FSR1
;
333 extern __at(0x0006) __sfr FSR1L
;
334 extern __at(0x0007) __sfr FSR1H
;
336 //==============================================================================
339 extern __at(0x0008) __sfr BSR
;
362 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
370 //==============================================================================
372 extern __at(0x0009) __sfr WREG
;
373 extern __at(0x000A) __sfr PCLATH
;
375 //==============================================================================
378 extern __at(0x000B) __sfr INTCON
;
407 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
420 //==============================================================================
423 //==============================================================================
426 extern __at(0x000C) __sfr PORTA
;
449 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
458 //==============================================================================
461 //==============================================================================
464 extern __at(0x000D) __sfr PORTB
;
478 extern __at(0x000D) volatile __PORTBbits_t PORTBbits
;
485 //==============================================================================
488 //==============================================================================
491 extern __at(0x000E) __sfr PORTC
;
505 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
516 //==============================================================================
519 //==============================================================================
522 extern __at(0x0011) __sfr PIR1
;
535 unsigned TMR1GIF
: 1;
551 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
561 #define _TMR1GIF 0x80
563 //==============================================================================
566 //==============================================================================
569 extern __at(0x0012) __sfr PIR2
;
583 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
593 //==============================================================================
596 //==============================================================================
599 extern __at(0x0013) __sfr PIR3
;
613 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
621 //==============================================================================
623 extern __at(0x0015) __sfr TMR0
;
624 extern __at(0x0016) __sfr TMR1
;
625 extern __at(0x0016) __sfr TMR1L
;
626 extern __at(0x0017) __sfr TMR1H
;
628 //==============================================================================
631 extern __at(0x0018) __sfr T1CON
;
639 unsigned NOT_T1SYNC
: 1;
640 unsigned T1OSCEN
: 1;
641 unsigned T1CKPS0
: 1;
642 unsigned T1CKPS1
: 1;
643 unsigned TMR1CS0
: 1;
644 unsigned TMR1CS1
: 1;
661 extern __at(0x0018) volatile __T1CONbits_t T1CONbits
;
664 #define _NOT_T1SYNC 0x04
665 #define _T1OSCEN 0x08
666 #define _T1CKPS0 0x10
667 #define _T1CKPS1 0x20
668 #define _TMR1CS0 0x40
669 #define _TMR1CS1 0x80
671 //==============================================================================
674 //==============================================================================
677 extern __at(0x0019) __sfr T1GCON
;
686 unsigned T1GGO_NOT_DONE
: 1;
700 extern __at(0x0019) volatile __T1GCONbits_t T1GCONbits
;
705 #define _T1GGO_NOT_DONE 0x08
711 //==============================================================================
713 extern __at(0x001A) __sfr TMR2
;
714 extern __at(0x001B) __sfr PR2
;
716 //==============================================================================
719 extern __at(0x001C) __sfr T2CON
;
725 unsigned T2CKPS0
: 1;
726 unsigned T2CKPS1
: 1;
728 unsigned T2OUTPS0
: 1;
729 unsigned T2OUTPS1
: 1;
730 unsigned T2OUTPS2
: 1;
731 unsigned T2OUTPS3
: 1;
744 unsigned T2OUTPS
: 4;
749 extern __at(0x001C) volatile __T2CONbits_t T2CONbits
;
751 #define _T2CKPS0 0x01
752 #define _T2CKPS1 0x02
754 #define _T2OUTPS0 0x08
755 #define _T2OUTPS1 0x10
756 #define _T2OUTPS2 0x20
757 #define _T2OUTPS3 0x40
759 //==============================================================================
762 //==============================================================================
765 extern __at(0x008C) __sfr TRISA
;
779 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
787 //==============================================================================
790 //==============================================================================
793 extern __at(0x008D) __sfr TRISB
;
807 extern __at(0x008D) volatile __TRISBbits_t TRISBbits
;
814 //==============================================================================
817 //==============================================================================
820 extern __at(0x008E) __sfr TRISC
;
834 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
845 //==============================================================================
848 //==============================================================================
851 extern __at(0x0091) __sfr PIE1
;
864 unsigned TMR1GIE
: 1;
880 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
890 #define _TMR1GIE 0x80
892 //==============================================================================
895 //==============================================================================
898 extern __at(0x0092) __sfr PIE2
;
912 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
922 //==============================================================================
925 //==============================================================================
928 extern __at(0x0093) __sfr PIE3
;
942 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
950 //==============================================================================
953 //==============================================================================
956 extern __at(0x0095) __sfr OPTION_REG
;
969 unsigned NOT_WPUEN
: 1;
989 } __OPTION_REGbits_t
;
991 extern __at(0x0095) volatile __OPTION_REGbits_t OPTION_REGbits
;
1001 #define _INTEDG 0x40
1002 #define _NOT_WPUEN 0x80
1004 //==============================================================================
1007 //==============================================================================
1010 extern __at(0x0096) __sfr PCON
;
1014 unsigned NOT_BOR
: 1;
1015 unsigned NOT_POR
: 1;
1016 unsigned NOT_RI
: 1;
1017 unsigned NOT_RMCLR
: 1;
1018 unsigned NOT_RWDT
: 1;
1020 unsigned STKUNF
: 1;
1021 unsigned STKOVF
: 1;
1024 extern __at(0x0096) volatile __PCONbits_t PCONbits
;
1026 #define _NOT_BOR 0x01
1027 #define _NOT_POR 0x02
1028 #define _NOT_RI 0x04
1029 #define _NOT_RMCLR 0x08
1030 #define _NOT_RWDT 0x10
1031 #define _STKUNF 0x40
1032 #define _STKOVF 0x80
1034 //==============================================================================
1037 //==============================================================================
1040 extern __at(0x0097) __sfr WDTCON
;
1046 unsigned SWDTEN
: 1;
1047 unsigned WDTPS0
: 1;
1048 unsigned WDTPS1
: 1;
1049 unsigned WDTPS2
: 1;
1050 unsigned WDTPS3
: 1;
1051 unsigned WDTPS4
: 1;
1064 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1066 #define _SWDTEN 0x01
1067 #define _WDTPS0 0x02
1068 #define _WDTPS1 0x04
1069 #define _WDTPS2 0x08
1070 #define _WDTPS3 0x10
1071 #define _WDTPS4 0x20
1073 //==============================================================================
1076 //==============================================================================
1079 extern __at(0x0098) __sfr OSCTUNE
;
1102 extern __at(0x0098) volatile __OSCTUNEbits_t OSCTUNEbits
;
1111 //==============================================================================
1114 //==============================================================================
1117 extern __at(0x0099) __sfr OSCCON
;
1130 unsigned SPLLEN
: 1;
1147 extern __at(0x0099) volatile __OSCCONbits_t OSCCONbits
;
1155 #define _SPLLEN 0x80
1157 //==============================================================================
1160 //==============================================================================
1163 extern __at(0x009A) __sfr OSCSTAT
;
1167 unsigned HFIOFS
: 1;
1168 unsigned LFIOFR
: 1;
1169 unsigned MFIOFR
: 1;
1170 unsigned HFIOFL
: 1;
1171 unsigned HFIOFR
: 1;
1177 extern __at(0x009A) volatile __OSCSTATbits_t OSCSTATbits
;
1179 #define _HFIOFS 0x01
1180 #define _LFIOFR 0x02
1181 #define _MFIOFR 0x04
1182 #define _HFIOFL 0x08
1183 #define _HFIOFR 0x10
1188 //==============================================================================
1190 extern __at(0x009B) __sfr ADRES
;
1191 extern __at(0x009B) __sfr ADRESL
;
1192 extern __at(0x009C) __sfr ADRESH
;
1194 //==============================================================================
1197 extern __at(0x009D) __sfr ADCON0
;
1204 unsigned GO_NOT_DONE
: 1;
1245 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1248 #define _GO_NOT_DONE 0x02
1257 //==============================================================================
1260 //==============================================================================
1263 extern __at(0x009E) __sfr ADCON1
;
1269 unsigned ADPREF0
: 1;
1270 unsigned ADPREF1
: 1;
1271 unsigned ADNREF
: 1;
1281 unsigned ADPREF
: 2;
1286 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1288 #define _ADPREF0 0x01
1289 #define _ADPREF1 0x02
1290 #define _ADNREF 0x04
1293 //==============================================================================
1296 //==============================================================================
1299 extern __at(0x009F) __sfr ADCON2
;
1309 unsigned TRIGSEL0
: 1;
1310 unsigned TRIGSEL1
: 1;
1311 unsigned TRIGSEL2
: 1;
1312 unsigned TRIGSEL3
: 1;
1318 unsigned TRIGSEL
: 4;
1322 extern __at(0x009F) volatile __ADCON2bits_t ADCON2bits
;
1324 #define _TRIGSEL0 0x10
1325 #define _TRIGSEL1 0x20
1326 #define _TRIGSEL2 0x40
1327 #define _TRIGSEL3 0x80
1329 //==============================================================================
1332 //==============================================================================
1335 extern __at(0x010C) __sfr LATA
;
1349 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1357 //==============================================================================
1360 //==============================================================================
1363 extern __at(0x010D) __sfr LATB
;
1377 extern __at(0x010D) volatile __LATBbits_t LATBbits
;
1384 //==============================================================================
1387 //==============================================================================
1390 extern __at(0x010E) __sfr LATC
;
1404 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1415 //==============================================================================
1418 //==============================================================================
1421 extern __at(0x0111) __sfr CM1CON0
;
1425 unsigned C1SYNC
: 1;
1435 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1437 #define _C1SYNC 0x01
1445 //==============================================================================
1448 //==============================================================================
1451 extern __at(0x0112) __sfr CM1CON1
;
1457 unsigned C1NCH0
: 1;
1458 unsigned C1NCH1
: 1;
1459 unsigned C1NCH2
: 1;
1460 unsigned C1PCH0
: 1;
1461 unsigned C1PCH1
: 1;
1462 unsigned C1PCH2
: 1;
1463 unsigned C1INTN
: 1;
1464 unsigned C1INTP
: 1;
1481 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1483 #define _C1NCH0 0x01
1484 #define _C1NCH1 0x02
1485 #define _C1NCH2 0x04
1486 #define _C1PCH0 0x08
1487 #define _C1PCH1 0x10
1488 #define _C1PCH2 0x20
1489 #define _C1INTN 0x40
1490 #define _C1INTP 0x80
1492 //==============================================================================
1495 //==============================================================================
1498 extern __at(0x0113) __sfr CM2CON0
;
1502 unsigned C2SYNC
: 1;
1512 extern __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits
;
1514 #define _C2SYNC 0x01
1522 //==============================================================================
1525 //==============================================================================
1528 extern __at(0x0114) __sfr CM2CON1
;
1534 unsigned C2NCH0
: 1;
1535 unsigned C2NCH1
: 1;
1536 unsigned C2NCH2
: 1;
1537 unsigned C2PCH0
: 1;
1538 unsigned C2PCH1
: 1;
1539 unsigned C2PCH2
: 1;
1540 unsigned C2INTN
: 1;
1541 unsigned C2INTP
: 1;
1558 extern __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits
;
1560 #define _C2NCH0 0x01
1561 #define _C2NCH1 0x02
1562 #define _C2NCH2 0x04
1563 #define _C2PCH0 0x08
1564 #define _C2PCH1 0x10
1565 #define _C2PCH2 0x20
1566 #define _C2INTN 0x40
1567 #define _C2INTP 0x80
1569 //==============================================================================
1572 //==============================================================================
1575 extern __at(0x0115) __sfr CMOUT
;
1579 unsigned MC1OUT
: 1;
1580 unsigned MC2OUT
: 1;
1589 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1591 #define _MC1OUT 0x01
1592 #define _MC2OUT 0x02
1594 //==============================================================================
1597 //==============================================================================
1600 extern __at(0x0116) __sfr BORCON
;
1604 unsigned BORRDY
: 1;
1611 unsigned SBOREN
: 1;
1614 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1616 #define _BORRDY 0x01
1618 #define _SBOREN 0x80
1620 //==============================================================================
1623 //==============================================================================
1626 extern __at(0x0117) __sfr FVRCON
;
1632 unsigned ADFVR0
: 1;
1633 unsigned ADFVR1
: 1;
1634 unsigned CDAFVR0
: 1;
1635 unsigned CDAFVR1
: 1;
1638 unsigned FVRRDY
: 1;
1651 unsigned CDAFVR
: 2;
1656 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1658 #define _ADFVR0 0x01
1659 #define _ADFVR1 0x02
1660 #define _CDAFVR0 0x04
1661 #define _CDAFVR1 0x08
1664 #define _FVRRDY 0x40
1667 //==============================================================================
1670 //==============================================================================
1673 extern __at(0x0118) __sfr DAC1CON0
;
1679 unsigned DAC1NSS
: 1;
1681 unsigned DAC1PSS0
: 1;
1682 unsigned DAC1PSS1
: 1;
1683 unsigned DAC1OE2
: 1;
1684 unsigned DAC1OE1
: 1;
1686 unsigned DAC1EN
: 1;
1691 unsigned DACNSS
: 1;
1693 unsigned DACPSS0
: 1;
1694 unsigned DACPSS1
: 1;
1695 unsigned DACOE0
: 1;
1696 unsigned DACOE1
: 1;
1704 unsigned DAC1PSS
: 2;
1711 unsigned DACPSS
: 2;
1723 extern __at(0x0118) volatile __DAC1CON0bits_t DAC1CON0bits
;
1725 #define _DAC1NSS 0x01
1726 #define _DACNSS 0x01
1727 #define _DAC1PSS0 0x04
1728 #define _DACPSS0 0x04
1729 #define _DAC1PSS1 0x08
1730 #define _DACPSS1 0x08
1731 #define _DAC1OE2 0x10
1732 #define _DACOE0 0x10
1733 #define _DAC1OE1 0x20
1734 #define _DACOE1 0x20
1735 #define _DAC1EN 0x80
1738 //==============================================================================
1741 //==============================================================================
1744 extern __at(0x0119) __sfr DAC1CON1
;
1750 unsigned DAC1R0
: 1;
1751 unsigned DAC1R1
: 1;
1752 unsigned DAC1R2
: 1;
1753 unsigned DAC1R3
: 1;
1754 unsigned DAC1R4
: 1;
1755 unsigned DAC1R5
: 1;
1756 unsigned DAC1R6
: 1;
1757 unsigned DAC1R7
: 1;
1773 extern __at(0x0119) volatile __DAC1CON1bits_t DAC1CON1bits
;
1775 #define _DAC1R0 0x01
1777 #define _DAC1R1 0x02
1779 #define _DAC1R2 0x04
1781 #define _DAC1R3 0x08
1783 #define _DAC1R4 0x10
1785 #define _DAC1R5 0x20
1787 #define _DAC1R6 0x40
1789 #define _DAC1R7 0x80
1792 //==============================================================================
1795 //==============================================================================
1798 extern __at(0x011C) __sfr ZCD1CON
;
1802 unsigned ZCD1INTN
: 1;
1803 unsigned ZCD1INTP
: 1;
1806 unsigned ZCD1POL
: 1;
1807 unsigned ZCD1OUT
: 1;
1809 unsigned ZCD1EN
: 1;
1812 extern __at(0x011C) volatile __ZCD1CONbits_t ZCD1CONbits
;
1814 #define _ZCD1INTN 0x01
1815 #define _ZCD1INTP 0x02
1816 #define _ZCD1POL 0x10
1817 #define _ZCD1OUT 0x20
1818 #define _ZCD1EN 0x80
1820 //==============================================================================
1823 //==============================================================================
1826 extern __at(0x018C) __sfr ANSELA
;
1840 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1848 //==============================================================================
1851 //==============================================================================
1854 extern __at(0x018D) __sfr ANSELB
;
1868 extern __at(0x018D) volatile __ANSELBbits_t ANSELBbits
;
1873 //==============================================================================
1876 //==============================================================================
1879 extern __at(0x018E) __sfr ANSELC
;
1893 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
1902 //==============================================================================
1904 extern __at(0x0191) __sfr PMADR
;
1905 extern __at(0x0191) __sfr PMADRL
;
1906 extern __at(0x0192) __sfr PMADRH
;
1907 extern __at(0x0193) __sfr PMDAT
;
1908 extern __at(0x0193) __sfr PMDATL
;
1909 extern __at(0x0194) __sfr PMDATH
;
1911 //==============================================================================
1914 extern __at(0x0195) __sfr PMCON1
;
1928 extern __at(0x0195) volatile __PMCON1bits_t PMCON1bits
;
1938 //==============================================================================
1940 extern __at(0x0196) __sfr PMCON2
;
1942 //==============================================================================
1945 extern __at(0x0197) __sfr VREGCON
;
1949 unsigned Reserved
: 1;
1950 unsigned VREGPM
: 1;
1959 extern __at(0x0197) volatile __VREGCONbits_t VREGCONbits
;
1961 #define _Reserved 0x01
1962 #define _VREGPM 0x02
1964 //==============================================================================
1966 extern __at(0x0199) __sfr RC1REG
;
1967 extern __at(0x0199) __sfr RCREG
;
1968 extern __at(0x0199) __sfr RCREG1
;
1969 extern __at(0x019A) __sfr TX1REG
;
1970 extern __at(0x019A) __sfr TXREG
;
1971 extern __at(0x019A) __sfr TXREG1
;
1972 extern __at(0x019B) __sfr SP1BRG
;
1973 extern __at(0x019B) __sfr SP1BRGL
;
1974 extern __at(0x019B) __sfr SPBRG
;
1975 extern __at(0x019B) __sfr SPBRG1
;
1976 extern __at(0x019B) __sfr SPBRGL
;
1977 extern __at(0x019C) __sfr SP1BRGH
;
1978 extern __at(0x019C) __sfr SPBRGH
;
1979 extern __at(0x019C) __sfr SPBRGH1
;
1981 //==============================================================================
1984 extern __at(0x019D) __sfr RC1STA
;
1998 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
2009 //==============================================================================
2012 //==============================================================================
2015 extern __at(0x019D) __sfr RCSTA
;
2029 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
2031 #define _RCSTA_RX9D 0x01
2032 #define _RCSTA_OERR 0x02
2033 #define _RCSTA_FERR 0x04
2034 #define _RCSTA_ADDEN 0x08
2035 #define _RCSTA_CREN 0x10
2036 #define _RCSTA_SREN 0x20
2037 #define _RCSTA_RX9 0x40
2038 #define _RCSTA_SPEN 0x80
2040 //==============================================================================
2043 //==============================================================================
2046 extern __at(0x019D) __sfr RCSTA1
;
2060 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
2062 #define _RCSTA1_RX9D 0x01
2063 #define _RCSTA1_OERR 0x02
2064 #define _RCSTA1_FERR 0x04
2065 #define _RCSTA1_ADDEN 0x08
2066 #define _RCSTA1_CREN 0x10
2067 #define _RCSTA1_SREN 0x20
2068 #define _RCSTA1_RX9 0x40
2069 #define _RCSTA1_SPEN 0x80
2071 //==============================================================================
2074 //==============================================================================
2077 extern __at(0x019E) __sfr TX1STA
;
2091 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
2102 //==============================================================================
2105 //==============================================================================
2108 extern __at(0x019E) __sfr TXSTA
;
2122 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
2124 #define _TXSTA_TX9D 0x01
2125 #define _TXSTA_TRMT 0x02
2126 #define _TXSTA_BRGH 0x04
2127 #define _TXSTA_SENDB 0x08
2128 #define _TXSTA_SYNC 0x10
2129 #define _TXSTA_TXEN 0x20
2130 #define _TXSTA_TX9 0x40
2131 #define _TXSTA_CSRC 0x80
2133 //==============================================================================
2136 //==============================================================================
2139 extern __at(0x019E) __sfr TXSTA1
;
2153 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
2155 #define _TXSTA1_TX9D 0x01
2156 #define _TXSTA1_TRMT 0x02
2157 #define _TXSTA1_BRGH 0x04
2158 #define _TXSTA1_SENDB 0x08
2159 #define _TXSTA1_SYNC 0x10
2160 #define _TXSTA1_TXEN 0x20
2161 #define _TXSTA1_TX9 0x40
2162 #define _TXSTA1_CSRC 0x80
2164 //==============================================================================
2167 //==============================================================================
2170 extern __at(0x019F) __sfr BAUD1CON
;
2181 unsigned ABDOVF
: 1;
2184 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
2191 #define _ABDOVF 0x80
2193 //==============================================================================
2196 //==============================================================================
2199 extern __at(0x019F) __sfr BAUDCON
;
2210 unsigned ABDOVF
: 1;
2213 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
2215 #define _BAUDCON_ABDEN 0x01
2216 #define _BAUDCON_WUE 0x02
2217 #define _BAUDCON_BRG16 0x08
2218 #define _BAUDCON_SCKP 0x10
2219 #define _BAUDCON_RCIDL 0x40
2220 #define _BAUDCON_ABDOVF 0x80
2222 //==============================================================================
2225 //==============================================================================
2228 extern __at(0x019F) __sfr BAUDCON1
;
2239 unsigned ABDOVF
: 1;
2242 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
2244 #define _BAUDCON1_ABDEN 0x01
2245 #define _BAUDCON1_WUE 0x02
2246 #define _BAUDCON1_BRG16 0x08
2247 #define _BAUDCON1_SCKP 0x10
2248 #define _BAUDCON1_RCIDL 0x40
2249 #define _BAUDCON1_ABDOVF 0x80
2251 //==============================================================================
2254 //==============================================================================
2257 extern __at(0x019F) __sfr BAUDCTL
;
2268 unsigned ABDOVF
: 1;
2271 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
2273 #define _BAUDCTL_ABDEN 0x01
2274 #define _BAUDCTL_WUE 0x02
2275 #define _BAUDCTL_BRG16 0x08
2276 #define _BAUDCTL_SCKP 0x10
2277 #define _BAUDCTL_RCIDL 0x40
2278 #define _BAUDCTL_ABDOVF 0x80
2280 //==============================================================================
2283 //==============================================================================
2286 extern __at(0x019F) __sfr BAUDCTL1
;
2297 unsigned ABDOVF
: 1;
2300 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
2302 #define _BAUDCTL1_ABDEN 0x01
2303 #define _BAUDCTL1_WUE 0x02
2304 #define _BAUDCTL1_BRG16 0x08
2305 #define _BAUDCTL1_SCKP 0x10
2306 #define _BAUDCTL1_RCIDL 0x40
2307 #define _BAUDCTL1_ABDOVF 0x80
2309 //==============================================================================
2312 //==============================================================================
2315 extern __at(0x020C) __sfr WPUA
;
2338 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
2347 //==============================================================================
2350 //==============================================================================
2353 extern __at(0x020D) __sfr WPUB
;
2367 extern __at(0x020D) volatile __WPUBbits_t WPUBbits
;
2374 //==============================================================================
2377 //==============================================================================
2380 extern __at(0x020E) __sfr WPUC
;
2394 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
2405 //==============================================================================
2408 //==============================================================================
2411 extern __at(0x0211) __sfr SSP1BUF
;
2417 unsigned SSP1BUF0
: 1;
2418 unsigned SSP1BUF1
: 1;
2419 unsigned SSP1BUF2
: 1;
2420 unsigned SSP1BUF3
: 1;
2421 unsigned SSP1BUF4
: 1;
2422 unsigned SSP1BUF5
: 1;
2423 unsigned SSP1BUF6
: 1;
2424 unsigned SSP1BUF7
: 1;
2440 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
2442 #define _SSP1BUF0 0x01
2444 #define _SSP1BUF1 0x02
2446 #define _SSP1BUF2 0x04
2448 #define _SSP1BUF3 0x08
2450 #define _SSP1BUF4 0x10
2452 #define _SSP1BUF5 0x20
2454 #define _SSP1BUF6 0x40
2456 #define _SSP1BUF7 0x80
2459 //==============================================================================
2462 //==============================================================================
2465 extern __at(0x0211) __sfr SSPBUF
;
2471 unsigned SSP1BUF0
: 1;
2472 unsigned SSP1BUF1
: 1;
2473 unsigned SSP1BUF2
: 1;
2474 unsigned SSP1BUF3
: 1;
2475 unsigned SSP1BUF4
: 1;
2476 unsigned SSP1BUF5
: 1;
2477 unsigned SSP1BUF6
: 1;
2478 unsigned SSP1BUF7
: 1;
2494 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
2496 #define _SSPBUF_SSP1BUF0 0x01
2497 #define _SSPBUF_BUF0 0x01
2498 #define _SSPBUF_SSP1BUF1 0x02
2499 #define _SSPBUF_BUF1 0x02
2500 #define _SSPBUF_SSP1BUF2 0x04
2501 #define _SSPBUF_BUF2 0x04
2502 #define _SSPBUF_SSP1BUF3 0x08
2503 #define _SSPBUF_BUF3 0x08
2504 #define _SSPBUF_SSP1BUF4 0x10
2505 #define _SSPBUF_BUF4 0x10
2506 #define _SSPBUF_SSP1BUF5 0x20
2507 #define _SSPBUF_BUF5 0x20
2508 #define _SSPBUF_SSP1BUF6 0x40
2509 #define _SSPBUF_BUF6 0x40
2510 #define _SSPBUF_SSP1BUF7 0x80
2511 #define _SSPBUF_BUF7 0x80
2513 //==============================================================================
2516 //==============================================================================
2519 extern __at(0x0212) __sfr SSP1ADD
;
2525 unsigned SSP1ADD0
: 1;
2526 unsigned SSP1ADD1
: 1;
2527 unsigned SSP1ADD2
: 1;
2528 unsigned SSP1ADD3
: 1;
2529 unsigned SSP1ADD4
: 1;
2530 unsigned SSP1ADD5
: 1;
2531 unsigned SSP1ADD6
: 1;
2532 unsigned SSP1ADD7
: 1;
2548 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
2550 #define _SSP1ADD0 0x01
2552 #define _SSP1ADD1 0x02
2554 #define _SSP1ADD2 0x04
2556 #define _SSP1ADD3 0x08
2558 #define _SSP1ADD4 0x10
2560 #define _SSP1ADD5 0x20
2562 #define _SSP1ADD6 0x40
2564 #define _SSP1ADD7 0x80
2567 //==============================================================================
2570 //==============================================================================
2573 extern __at(0x0212) __sfr SSPADD
;
2579 unsigned SSP1ADD0
: 1;
2580 unsigned SSP1ADD1
: 1;
2581 unsigned SSP1ADD2
: 1;
2582 unsigned SSP1ADD3
: 1;
2583 unsigned SSP1ADD4
: 1;
2584 unsigned SSP1ADD5
: 1;
2585 unsigned SSP1ADD6
: 1;
2586 unsigned SSP1ADD7
: 1;
2602 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
2604 #define _SSPADD_SSP1ADD0 0x01
2605 #define _SSPADD_ADD0 0x01
2606 #define _SSPADD_SSP1ADD1 0x02
2607 #define _SSPADD_ADD1 0x02
2608 #define _SSPADD_SSP1ADD2 0x04
2609 #define _SSPADD_ADD2 0x04
2610 #define _SSPADD_SSP1ADD3 0x08
2611 #define _SSPADD_ADD3 0x08
2612 #define _SSPADD_SSP1ADD4 0x10
2613 #define _SSPADD_ADD4 0x10
2614 #define _SSPADD_SSP1ADD5 0x20
2615 #define _SSPADD_ADD5 0x20
2616 #define _SSPADD_SSP1ADD6 0x40
2617 #define _SSPADD_ADD6 0x40
2618 #define _SSPADD_SSP1ADD7 0x80
2619 #define _SSPADD_ADD7 0x80
2621 //==============================================================================
2624 //==============================================================================
2627 extern __at(0x0213) __sfr SSP1MSK
;
2633 unsigned SSP1MSK0
: 1;
2634 unsigned SSP1MSK1
: 1;
2635 unsigned SSP1MSK2
: 1;
2636 unsigned SSP1MSK3
: 1;
2637 unsigned SSP1MSK4
: 1;
2638 unsigned SSP1MSK5
: 1;
2639 unsigned SSP1MSK6
: 1;
2640 unsigned SSP1MSK7
: 1;
2656 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
2658 #define _SSP1MSK0 0x01
2660 #define _SSP1MSK1 0x02
2662 #define _SSP1MSK2 0x04
2664 #define _SSP1MSK3 0x08
2666 #define _SSP1MSK4 0x10
2668 #define _SSP1MSK5 0x20
2670 #define _SSP1MSK6 0x40
2672 #define _SSP1MSK7 0x80
2675 //==============================================================================
2678 //==============================================================================
2681 extern __at(0x0213) __sfr SSPMSK
;
2687 unsigned SSP1MSK0
: 1;
2688 unsigned SSP1MSK1
: 1;
2689 unsigned SSP1MSK2
: 1;
2690 unsigned SSP1MSK3
: 1;
2691 unsigned SSP1MSK4
: 1;
2692 unsigned SSP1MSK5
: 1;
2693 unsigned SSP1MSK6
: 1;
2694 unsigned SSP1MSK7
: 1;
2710 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
2712 #define _SSPMSK_SSP1MSK0 0x01
2713 #define _SSPMSK_MSK0 0x01
2714 #define _SSPMSK_SSP1MSK1 0x02
2715 #define _SSPMSK_MSK1 0x02
2716 #define _SSPMSK_SSP1MSK2 0x04
2717 #define _SSPMSK_MSK2 0x04
2718 #define _SSPMSK_SSP1MSK3 0x08
2719 #define _SSPMSK_MSK3 0x08
2720 #define _SSPMSK_SSP1MSK4 0x10
2721 #define _SSPMSK_MSK4 0x10
2722 #define _SSPMSK_SSP1MSK5 0x20
2723 #define _SSPMSK_MSK5 0x20
2724 #define _SSPMSK_SSP1MSK6 0x40
2725 #define _SSPMSK_MSK6 0x40
2726 #define _SSPMSK_SSP1MSK7 0x80
2727 #define _SSPMSK_MSK7 0x80
2729 //==============================================================================
2732 //==============================================================================
2735 extern __at(0x0214) __sfr SSP1STAT
;
2741 unsigned R_NOT_W
: 1;
2744 unsigned D_NOT_A
: 1;
2749 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
2753 #define _R_NOT_W 0x04
2756 #define _D_NOT_A 0x20
2760 //==============================================================================
2763 //==============================================================================
2766 extern __at(0x0214) __sfr SSPSTAT
;
2772 unsigned R_NOT_W
: 1;
2775 unsigned D_NOT_A
: 1;
2780 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
2782 #define _SSPSTAT_BF 0x01
2783 #define _SSPSTAT_UA 0x02
2784 #define _SSPSTAT_R_NOT_W 0x04
2785 #define _SSPSTAT_S 0x08
2786 #define _SSPSTAT_P 0x10
2787 #define _SSPSTAT_D_NOT_A 0x20
2788 #define _SSPSTAT_CKE 0x40
2789 #define _SSPSTAT_SMP 0x80
2791 //==============================================================================
2794 //==============================================================================
2797 extern __at(0x0215) __sfr SSP1CON
;
2820 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
2831 //==============================================================================
2834 //==============================================================================
2837 extern __at(0x0215) __sfr SSP1CON1
;
2860 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
2862 #define _SSP1CON1_SSPM0 0x01
2863 #define _SSP1CON1_SSPM1 0x02
2864 #define _SSP1CON1_SSPM2 0x04
2865 #define _SSP1CON1_SSPM3 0x08
2866 #define _SSP1CON1_CKP 0x10
2867 #define _SSP1CON1_SSPEN 0x20
2868 #define _SSP1CON1_SSPOV 0x40
2869 #define _SSP1CON1_WCOL 0x80
2871 //==============================================================================
2874 //==============================================================================
2877 extern __at(0x0215) __sfr SSPCON
;
2900 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2902 #define _SSPCON_SSPM0 0x01
2903 #define _SSPCON_SSPM1 0x02
2904 #define _SSPCON_SSPM2 0x04
2905 #define _SSPCON_SSPM3 0x08
2906 #define _SSPCON_CKP 0x10
2907 #define _SSPCON_SSPEN 0x20
2908 #define _SSPCON_SSPOV 0x40
2909 #define _SSPCON_WCOL 0x80
2911 //==============================================================================
2914 //==============================================================================
2917 extern __at(0x0215) __sfr SSPCON1
;
2940 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2942 #define _SSPCON1_SSPM0 0x01
2943 #define _SSPCON1_SSPM1 0x02
2944 #define _SSPCON1_SSPM2 0x04
2945 #define _SSPCON1_SSPM3 0x08
2946 #define _SSPCON1_CKP 0x10
2947 #define _SSPCON1_SSPEN 0x20
2948 #define _SSPCON1_SSPOV 0x40
2949 #define _SSPCON1_WCOL 0x80
2951 //==============================================================================
2954 //==============================================================================
2957 extern __at(0x0216) __sfr SSP1CON2
;
2967 unsigned ACKSTAT
: 1;
2971 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
2979 #define _ACKSTAT 0x40
2982 //==============================================================================
2985 //==============================================================================
2988 extern __at(0x0216) __sfr SSPCON2
;
2998 unsigned ACKSTAT
: 1;
3002 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
3004 #define _SSPCON2_SEN 0x01
3005 #define _SSPCON2_RSEN 0x02
3006 #define _SSPCON2_PEN 0x04
3007 #define _SSPCON2_RCEN 0x08
3008 #define _SSPCON2_ACKEN 0x10
3009 #define _SSPCON2_ACKDT 0x20
3010 #define _SSPCON2_ACKSTAT 0x40
3011 #define _SSPCON2_GCEN 0x80
3013 //==============================================================================
3016 //==============================================================================
3019 extern __at(0x0217) __sfr SSP1CON3
;
3030 unsigned ACKTIM
: 1;
3033 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
3042 #define _ACKTIM 0x80
3044 //==============================================================================
3047 //==============================================================================
3050 extern __at(0x0217) __sfr SSPCON3
;
3061 unsigned ACKTIM
: 1;
3064 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
3066 #define _SSPCON3_DHEN 0x01
3067 #define _SSPCON3_AHEN 0x02
3068 #define _SSPCON3_SBCDE 0x04
3069 #define _SSPCON3_SDAHT 0x08
3070 #define _SSPCON3_BOEN 0x10
3071 #define _SSPCON3_SCIE 0x20
3072 #define _SSPCON3_PCIE 0x40
3073 #define _SSPCON3_ACKTIM 0x80
3075 //==============================================================================
3078 //==============================================================================
3081 extern __at(0x028C) __sfr ODCONA
;
3095 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
3103 //==============================================================================
3106 //==============================================================================
3109 extern __at(0x028D) __sfr ODCONB
;
3123 extern __at(0x028D) volatile __ODCONBbits_t ODCONBbits
;
3130 //==============================================================================
3133 //==============================================================================
3136 extern __at(0x028E) __sfr ODCONC
;
3150 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
3161 //==============================================================================
3163 extern __at(0x0291) __sfr CCPR1
;
3164 extern __at(0x0291) __sfr CCPR1L
;
3165 extern __at(0x0292) __sfr CCPR1H
;
3167 //==============================================================================
3170 extern __at(0x0293) __sfr CCP1CON
;
3176 unsigned CCP1M0
: 1;
3177 unsigned CCP1M1
: 1;
3178 unsigned CCP1M2
: 1;
3179 unsigned CCP1M3
: 1;
3212 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
3214 #define _CCP1M0 0x01
3215 #define _CCP1M1 0x02
3216 #define _CCP1M2 0x04
3217 #define _CCP1M3 0x08
3223 //==============================================================================
3226 //==============================================================================
3229 extern __at(0x0293) __sfr ECCP1CON
;
3235 unsigned CCP1M0
: 1;
3236 unsigned CCP1M1
: 1;
3237 unsigned CCP1M2
: 1;
3238 unsigned CCP1M3
: 1;
3271 extern __at(0x0293) volatile __ECCP1CONbits_t ECCP1CONbits
;
3273 #define _ECCP1CON_CCP1M0 0x01
3274 #define _ECCP1CON_CCP1M1 0x02
3275 #define _ECCP1CON_CCP1M2 0x04
3276 #define _ECCP1CON_CCP1M3 0x08
3277 #define _ECCP1CON_DC1B0 0x10
3278 #define _ECCP1CON_CCP1Y 0x10
3279 #define _ECCP1CON_DC1B1 0x20
3280 #define _ECCP1CON_CCP1X 0x20
3282 //==============================================================================
3284 extern __at(0x0298) __sfr CCPR2
;
3285 extern __at(0x0298) __sfr CCPR2L
;
3286 extern __at(0x0299) __sfr CCPR2H
;
3288 //==============================================================================
3291 extern __at(0x029A) __sfr CCP2CON
;
3297 unsigned CCP2M0
: 1;
3298 unsigned CCP2M1
: 1;
3299 unsigned CCP2M2
: 1;
3300 unsigned CCP2M3
: 1;
3333 extern __at(0x029A) volatile __CCP2CONbits_t CCP2CONbits
;
3335 #define _CCP2M0 0x01
3336 #define _CCP2M1 0x02
3337 #define _CCP2M2 0x04
3338 #define _CCP2M3 0x08
3344 //==============================================================================
3347 //==============================================================================
3350 extern __at(0x029A) __sfr ECCP2CON
;
3356 unsigned CCP2M0
: 1;
3357 unsigned CCP2M1
: 1;
3358 unsigned CCP2M2
: 1;
3359 unsigned CCP2M3
: 1;
3392 extern __at(0x029A) volatile __ECCP2CONbits_t ECCP2CONbits
;
3394 #define _ECCP2CON_CCP2M0 0x01
3395 #define _ECCP2CON_CCP2M1 0x02
3396 #define _ECCP2CON_CCP2M2 0x04
3397 #define _ECCP2CON_CCP2M3 0x08
3398 #define _ECCP2CON_DC2B0 0x10
3399 #define _ECCP2CON_CCP2Y 0x10
3400 #define _ECCP2CON_DC2B1 0x20
3401 #define _ECCP2CON_CCP2X 0x20
3403 //==============================================================================
3406 //==============================================================================
3409 extern __at(0x029E) __sfr CCPTMRS
;
3415 unsigned C1TSEL0
: 1;
3416 unsigned C1TSEL1
: 1;
3417 unsigned C2TSEL0
: 1;
3418 unsigned C2TSEL1
: 1;
3419 unsigned P3TSEL0
: 1;
3420 unsigned P3TSEL1
: 1;
3421 unsigned P4TSEL0
: 1;
3422 unsigned P4TSEL1
: 1;
3427 unsigned C1TSEL
: 2;
3434 unsigned C2TSEL
: 2;
3441 unsigned P3TSEL
: 2;
3448 unsigned P4TSEL
: 2;
3452 extern __at(0x029E) volatile __CCPTMRSbits_t CCPTMRSbits
;
3454 #define _C1TSEL0 0x01
3455 #define _C1TSEL1 0x02
3456 #define _C2TSEL0 0x04
3457 #define _C2TSEL1 0x08
3458 #define _P3TSEL0 0x10
3459 #define _P3TSEL1 0x20
3460 #define _P4TSEL0 0x40
3461 #define _P4TSEL1 0x80
3463 //==============================================================================
3466 //==============================================================================
3469 extern __at(0x030C) __sfr SLRCONA
;
3483 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
3491 //==============================================================================
3494 //==============================================================================
3497 extern __at(0x030D) __sfr SLRCONB
;
3511 extern __at(0x030D) volatile __SLRCONBbits_t SLRCONBbits
;
3518 //==============================================================================
3521 //==============================================================================
3524 extern __at(0x030E) __sfr SLRCONC
;
3538 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
3549 //==============================================================================
3552 //==============================================================================
3555 extern __at(0x038C) __sfr INLVLA
;
3561 unsigned INLVLA0
: 1;
3562 unsigned INLVLA1
: 1;
3563 unsigned INLVLA2
: 1;
3564 unsigned INLVLA3
: 1;
3565 unsigned INLVLA4
: 1;
3566 unsigned INLVLA5
: 1;
3573 unsigned INLVLA
: 6;
3578 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
3580 #define _INLVLA0 0x01
3581 #define _INLVLA1 0x02
3582 #define _INLVLA2 0x04
3583 #define _INLVLA3 0x08
3584 #define _INLVLA4 0x10
3585 #define _INLVLA5 0x20
3587 //==============================================================================
3590 //==============================================================================
3593 extern __at(0x038D) __sfr INLVLB
;
3601 unsigned INLVLB4
: 1;
3602 unsigned INLVLB5
: 1;
3603 unsigned INLVLB6
: 1;
3604 unsigned INLVLB7
: 1;
3607 extern __at(0x038D) volatile __INLVLBbits_t INLVLBbits
;
3609 #define _INLVLB4 0x10
3610 #define _INLVLB5 0x20
3611 #define _INLVLB6 0x40
3612 #define _INLVLB7 0x80
3614 //==============================================================================
3617 //==============================================================================
3620 extern __at(0x038E) __sfr INLVLC
;
3624 unsigned INLVLC0
: 1;
3625 unsigned INLVLC1
: 1;
3626 unsigned INLVLC2
: 1;
3627 unsigned INLVLC3
: 1;
3628 unsigned INLVLC4
: 1;
3629 unsigned INLVLC5
: 1;
3630 unsigned INLVLC6
: 1;
3631 unsigned INLVLC7
: 1;
3634 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
3636 #define _INLVLC0 0x01
3637 #define _INLVLC1 0x02
3638 #define _INLVLC2 0x04
3639 #define _INLVLC3 0x08
3640 #define _INLVLC4 0x10
3641 #define _INLVLC5 0x20
3642 #define _INLVLC6 0x40
3643 #define _INLVLC7 0x80
3645 //==============================================================================
3648 //==============================================================================
3651 extern __at(0x0391) __sfr IOCAP
;
3657 unsigned IOCAP0
: 1;
3658 unsigned IOCAP1
: 1;
3659 unsigned IOCAP2
: 1;
3660 unsigned IOCAP3
: 1;
3661 unsigned IOCAP4
: 1;
3662 unsigned IOCAP5
: 1;
3674 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
3676 #define _IOCAP0 0x01
3677 #define _IOCAP1 0x02
3678 #define _IOCAP2 0x04
3679 #define _IOCAP3 0x08
3680 #define _IOCAP4 0x10
3681 #define _IOCAP5 0x20
3683 //==============================================================================
3686 //==============================================================================
3689 extern __at(0x0392) __sfr IOCAN
;
3695 unsigned IOCAN0
: 1;
3696 unsigned IOCAN1
: 1;
3697 unsigned IOCAN2
: 1;
3698 unsigned IOCAN3
: 1;
3699 unsigned IOCAN4
: 1;
3700 unsigned IOCAN5
: 1;
3712 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
3714 #define _IOCAN0 0x01
3715 #define _IOCAN1 0x02
3716 #define _IOCAN2 0x04
3717 #define _IOCAN3 0x08
3718 #define _IOCAN4 0x10
3719 #define _IOCAN5 0x20
3721 //==============================================================================
3724 //==============================================================================
3727 extern __at(0x0393) __sfr IOCAF
;
3733 unsigned IOCAF0
: 1;
3734 unsigned IOCAF1
: 1;
3735 unsigned IOCAF2
: 1;
3736 unsigned IOCAF3
: 1;
3737 unsigned IOCAF4
: 1;
3738 unsigned IOCAF5
: 1;
3750 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
3752 #define _IOCAF0 0x01
3753 #define _IOCAF1 0x02
3754 #define _IOCAF2 0x04
3755 #define _IOCAF3 0x08
3756 #define _IOCAF4 0x10
3757 #define _IOCAF5 0x20
3759 //==============================================================================
3762 //==============================================================================
3765 extern __at(0x0394) __sfr IOCBP
;
3773 unsigned IOCBP4
: 1;
3774 unsigned IOCBP5
: 1;
3775 unsigned IOCBP6
: 1;
3776 unsigned IOCBP7
: 1;
3779 extern __at(0x0394) volatile __IOCBPbits_t IOCBPbits
;
3781 #define _IOCBP4 0x10
3782 #define _IOCBP5 0x20
3783 #define _IOCBP6 0x40
3784 #define _IOCBP7 0x80
3786 //==============================================================================
3789 //==============================================================================
3792 extern __at(0x0395) __sfr IOCBN
;
3800 unsigned IOCBN4
: 1;
3801 unsigned IOCBN5
: 1;
3802 unsigned IOCBN6
: 1;
3803 unsigned IOCBN7
: 1;
3806 extern __at(0x0395) volatile __IOCBNbits_t IOCBNbits
;
3808 #define _IOCBN4 0x10
3809 #define _IOCBN5 0x20
3810 #define _IOCBN6 0x40
3811 #define _IOCBN7 0x80
3813 //==============================================================================
3816 //==============================================================================
3819 extern __at(0x0396) __sfr IOCBF
;
3827 unsigned IOCBF4
: 1;
3828 unsigned IOCBF5
: 1;
3829 unsigned IOCBF6
: 1;
3830 unsigned IOCBF7
: 1;
3833 extern __at(0x0396) volatile __IOCBFbits_t IOCBFbits
;
3835 #define _IOCBF4 0x10
3836 #define _IOCBF5 0x20
3837 #define _IOCBF6 0x40
3838 #define _IOCBF7 0x80
3840 //==============================================================================
3843 //==============================================================================
3846 extern __at(0x0397) __sfr IOCCP
;
3850 unsigned IOCCP0
: 1;
3851 unsigned IOCCP1
: 1;
3852 unsigned IOCCP2
: 1;
3853 unsigned IOCCP3
: 1;
3854 unsigned IOCCP4
: 1;
3855 unsigned IOCCP5
: 1;
3856 unsigned IOCCP6
: 1;
3857 unsigned IOCCP7
: 1;
3860 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
3862 #define _IOCCP0 0x01
3863 #define _IOCCP1 0x02
3864 #define _IOCCP2 0x04
3865 #define _IOCCP3 0x08
3866 #define _IOCCP4 0x10
3867 #define _IOCCP5 0x20
3868 #define _IOCCP6 0x40
3869 #define _IOCCP7 0x80
3871 //==============================================================================
3874 //==============================================================================
3877 extern __at(0x0398) __sfr IOCCN
;
3881 unsigned IOCCN0
: 1;
3882 unsigned IOCCN1
: 1;
3883 unsigned IOCCN2
: 1;
3884 unsigned IOCCN3
: 1;
3885 unsigned IOCCN4
: 1;
3886 unsigned IOCCN5
: 1;
3887 unsigned IOCCN6
: 1;
3888 unsigned IOCCN7
: 1;
3891 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
3893 #define _IOCCN0 0x01
3894 #define _IOCCN1 0x02
3895 #define _IOCCN2 0x04
3896 #define _IOCCN3 0x08
3897 #define _IOCCN4 0x10
3898 #define _IOCCN5 0x20
3899 #define _IOCCN6 0x40
3900 #define _IOCCN7 0x80
3902 //==============================================================================
3905 //==============================================================================
3908 extern __at(0x0399) __sfr IOCCF
;
3912 unsigned IOCCF0
: 1;
3913 unsigned IOCCF1
: 1;
3914 unsigned IOCCF2
: 1;
3915 unsigned IOCCF3
: 1;
3916 unsigned IOCCF4
: 1;
3917 unsigned IOCCF5
: 1;
3918 unsigned IOCCF6
: 1;
3919 unsigned IOCCF7
: 1;
3922 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
3924 #define _IOCCF0 0x01
3925 #define _IOCCF1 0x02
3926 #define _IOCCF2 0x04
3927 #define _IOCCF3 0x08
3928 #define _IOCCF4 0x10
3929 #define _IOCCF5 0x20
3930 #define _IOCCF6 0x40
3931 #define _IOCCF7 0x80
3933 //==============================================================================
3935 extern __at(0x0415) __sfr TMR4
;
3936 extern __at(0x0416) __sfr PR4
;
3938 //==============================================================================
3941 extern __at(0x0417) __sfr T4CON
;
3947 unsigned T4CKPS0
: 1;
3948 unsigned T4CKPS1
: 1;
3949 unsigned TMR4ON
: 1;
3950 unsigned T4OUTPS0
: 1;
3951 unsigned T4OUTPS1
: 1;
3952 unsigned T4OUTPS2
: 1;
3953 unsigned T4OUTPS3
: 1;
3959 unsigned T4CKPS
: 2;
3966 unsigned T4OUTPS
: 4;
3971 extern __at(0x0417) volatile __T4CONbits_t T4CONbits
;
3973 #define _T4CKPS0 0x01
3974 #define _T4CKPS1 0x02
3975 #define _TMR4ON 0x04
3976 #define _T4OUTPS0 0x08
3977 #define _T4OUTPS1 0x10
3978 #define _T4OUTPS2 0x20
3979 #define _T4OUTPS3 0x40
3981 //==============================================================================
3983 extern __at(0x041C) __sfr TMR6
;
3984 extern __at(0x041D) __sfr PR6
;
3986 //==============================================================================
3989 extern __at(0x041E) __sfr T6CON
;
3995 unsigned T6CKPS0
: 1;
3996 unsigned T6CKPS1
: 1;
3997 unsigned TMR6ON
: 1;
3998 unsigned T6OUTPS0
: 1;
3999 unsigned T6OUTPS1
: 1;
4000 unsigned T6OUTPS2
: 1;
4001 unsigned T6OUTPS3
: 1;
4007 unsigned T6CKPS
: 2;
4014 unsigned T6OUTPS
: 4;
4019 extern __at(0x041E) volatile __T6CONbits_t T6CONbits
;
4021 #define _T6CKPS0 0x01
4022 #define _T6CKPS1 0x02
4023 #define _TMR6ON 0x04
4024 #define _T6OUTPS0 0x08
4025 #define _T6OUTPS1 0x10
4026 #define _T6OUTPS2 0x20
4027 #define _T6OUTPS3 0x40
4029 //==============================================================================
4032 //==============================================================================
4035 extern __at(0x0511) __sfr OPA1CON
;
4041 unsigned OPA1PCH0
: 1;
4042 unsigned OPA1PCH1
: 1;
4045 unsigned OPA1UG
: 1;
4047 unsigned OPA1SP
: 1;
4048 unsigned OPA1EN
: 1;
4053 unsigned OPA1PCH
: 2;
4058 extern __at(0x0511) volatile __OPA1CONbits_t OPA1CONbits
;
4060 #define _OPA1PCH0 0x01
4061 #define _OPA1PCH1 0x02
4062 #define _OPA1UG 0x10
4063 #define _OPA1SP 0x40
4064 #define _OPA1EN 0x80
4066 //==============================================================================
4069 //==============================================================================
4072 extern __at(0x0515) __sfr OPA2CON
;
4078 unsigned OPA2PCH0
: 1;
4079 unsigned OPA2PCH1
: 1;
4082 unsigned OPA2UG
: 1;
4084 unsigned OPA2SP
: 1;
4085 unsigned OPA2EN
: 1;
4090 unsigned OPA2PCH
: 2;
4095 extern __at(0x0515) volatile __OPA2CONbits_t OPA2CONbits
;
4097 #define _OPA2PCH0 0x01
4098 #define _OPA2PCH1 0x02
4099 #define _OPA2UG 0x10
4100 #define _OPA2SP 0x40
4101 #define _OPA2EN 0x80
4103 //==============================================================================
4106 //==============================================================================
4109 extern __at(0x0617) __sfr PWM3DCL
;
4121 unsigned PWM3DCL0
: 1;
4122 unsigned PWM3DCL1
: 1;
4128 unsigned PWM3DCL
: 2;
4132 extern __at(0x0617) volatile __PWM3DCLbits_t PWM3DCLbits
;
4134 #define _PWM3DCL0 0x40
4135 #define _PWM3DCL1 0x80
4137 //==============================================================================
4140 //==============================================================================
4143 extern __at(0x0618) __sfr PWM3DCH
;
4147 unsigned PWM3DCH0
: 1;
4148 unsigned PWM3DCH1
: 1;
4149 unsigned PWM3DCH2
: 1;
4150 unsigned PWM3DCH3
: 1;
4151 unsigned PWM3DCH4
: 1;
4152 unsigned PWM3DCH5
: 1;
4153 unsigned PWM3DCH6
: 1;
4154 unsigned PWM3DCH7
: 1;
4157 extern __at(0x0618) volatile __PWM3DCHbits_t PWM3DCHbits
;
4159 #define _PWM3DCH0 0x01
4160 #define _PWM3DCH1 0x02
4161 #define _PWM3DCH2 0x04
4162 #define _PWM3DCH3 0x08
4163 #define _PWM3DCH4 0x10
4164 #define _PWM3DCH5 0x20
4165 #define _PWM3DCH6 0x40
4166 #define _PWM3DCH7 0x80
4168 //==============================================================================
4171 //==============================================================================
4174 extern __at(0x0619) __sfr PWM3CON
;
4182 unsigned PWM3POL
: 1;
4183 unsigned PWM3OUT
: 1;
4185 unsigned PWM3EN
: 1;
4188 extern __at(0x0619) volatile __PWM3CONbits_t PWM3CONbits
;
4190 #define _PWM3POL 0x10
4191 #define _PWM3OUT 0x20
4192 #define _PWM3EN 0x80
4194 //==============================================================================
4197 //==============================================================================
4200 extern __at(0x0619) __sfr PWM3CON0
;
4208 unsigned PWM3POL
: 1;
4209 unsigned PWM3OUT
: 1;
4211 unsigned PWM3EN
: 1;
4214 extern __at(0x0619) volatile __PWM3CON0bits_t PWM3CON0bits
;
4216 #define _PWM3CON0_PWM3POL 0x10
4217 #define _PWM3CON0_PWM3OUT 0x20
4218 #define _PWM3CON0_PWM3EN 0x80
4220 //==============================================================================
4223 //==============================================================================
4226 extern __at(0x061A) __sfr PWM4DCL
;
4238 unsigned PWM4DCL0
: 1;
4239 unsigned PWM4DCL1
: 1;
4245 unsigned PWM4DCL
: 2;
4249 extern __at(0x061A) volatile __PWM4DCLbits_t PWM4DCLbits
;
4251 #define _PWM4DCL0 0x40
4252 #define _PWM4DCL1 0x80
4254 //==============================================================================
4257 //==============================================================================
4260 extern __at(0x061B) __sfr PWM4DCH
;
4264 unsigned PWM4DCH0
: 1;
4265 unsigned PWM4DCH1
: 1;
4266 unsigned PWM4DCH2
: 1;
4267 unsigned PWM4DCH3
: 1;
4268 unsigned PWM4DCH4
: 1;
4269 unsigned PWM4DCH5
: 1;
4270 unsigned PWM4DCH6
: 1;
4271 unsigned PWM4DCH7
: 1;
4274 extern __at(0x061B) volatile __PWM4DCHbits_t PWM4DCHbits
;
4276 #define _PWM4DCH0 0x01
4277 #define _PWM4DCH1 0x02
4278 #define _PWM4DCH2 0x04
4279 #define _PWM4DCH3 0x08
4280 #define _PWM4DCH4 0x10
4281 #define _PWM4DCH5 0x20
4282 #define _PWM4DCH6 0x40
4283 #define _PWM4DCH7 0x80
4285 //==============================================================================
4288 //==============================================================================
4291 extern __at(0x061C) __sfr PWM4CON
;
4299 unsigned PWM4POL
: 1;
4300 unsigned PWM4OUT
: 1;
4302 unsigned PWM4EN
: 1;
4305 extern __at(0x061C) volatile __PWM4CONbits_t PWM4CONbits
;
4307 #define _PWM4POL 0x10
4308 #define _PWM4OUT 0x20
4309 #define _PWM4EN 0x80
4311 //==============================================================================
4314 //==============================================================================
4317 extern __at(0x061C) __sfr PWM4CON0
;
4325 unsigned PWM4POL
: 1;
4326 unsigned PWM4OUT
: 1;
4328 unsigned PWM4EN
: 1;
4331 extern __at(0x061C) volatile __PWM4CON0bits_t PWM4CON0bits
;
4333 #define _PWM4CON0_PWM4POL 0x10
4334 #define _PWM4CON0_PWM4OUT 0x20
4335 #define _PWM4CON0_PWM4EN 0x80
4337 //==============================================================================
4340 //==============================================================================
4343 extern __at(0x0691) __sfr COG1PHR
;
4349 unsigned G1PHR0
: 1;
4350 unsigned G1PHR1
: 1;
4351 unsigned G1PHR2
: 1;
4352 unsigned G1PHR3
: 1;
4353 unsigned G1PHR4
: 1;
4354 unsigned G1PHR5
: 1;
4366 extern __at(0x0691) volatile __COG1PHRbits_t COG1PHRbits
;
4368 #define _G1PHR0 0x01
4369 #define _G1PHR1 0x02
4370 #define _G1PHR2 0x04
4371 #define _G1PHR3 0x08
4372 #define _G1PHR4 0x10
4373 #define _G1PHR5 0x20
4375 //==============================================================================
4378 //==============================================================================
4381 extern __at(0x0692) __sfr COG1PHF
;
4387 unsigned G1PHF0
: 1;
4388 unsigned G1PHF1
: 1;
4389 unsigned G1PHF2
: 1;
4390 unsigned G1PHF3
: 1;
4391 unsigned G1PHF4
: 1;
4392 unsigned G1PHF5
: 1;
4404 extern __at(0x0692) volatile __COG1PHFbits_t COG1PHFbits
;
4406 #define _G1PHF0 0x01
4407 #define _G1PHF1 0x02
4408 #define _G1PHF2 0x04
4409 #define _G1PHF3 0x08
4410 #define _G1PHF4 0x10
4411 #define _G1PHF5 0x20
4413 //==============================================================================
4416 //==============================================================================
4419 extern __at(0x0693) __sfr COG1BLKR
;
4425 unsigned G1BLKR0
: 1;
4426 unsigned G1BLKR1
: 1;
4427 unsigned G1BLKR2
: 1;
4428 unsigned G1BLKR3
: 1;
4429 unsigned G1BLKR4
: 1;
4430 unsigned G1BLKR5
: 1;
4437 unsigned G1BLKR
: 6;
4442 extern __at(0x0693) volatile __COG1BLKRbits_t COG1BLKRbits
;
4444 #define _G1BLKR0 0x01
4445 #define _G1BLKR1 0x02
4446 #define _G1BLKR2 0x04
4447 #define _G1BLKR3 0x08
4448 #define _G1BLKR4 0x10
4449 #define _G1BLKR5 0x20
4451 //==============================================================================
4454 //==============================================================================
4457 extern __at(0x0694) __sfr COG1BLKF
;
4463 unsigned G1BLKF0
: 1;
4464 unsigned G1BLKF1
: 1;
4465 unsigned G1BLKF2
: 1;
4466 unsigned G1BLKF3
: 1;
4467 unsigned G1BLKF4
: 1;
4468 unsigned G1BLKF5
: 1;
4475 unsigned G1BLKF
: 6;
4480 extern __at(0x0694) volatile __COG1BLKFbits_t COG1BLKFbits
;
4482 #define _G1BLKF0 0x01
4483 #define _G1BLKF1 0x02
4484 #define _G1BLKF2 0x04
4485 #define _G1BLKF3 0x08
4486 #define _G1BLKF4 0x10
4487 #define _G1BLKF5 0x20
4489 //==============================================================================
4492 //==============================================================================
4495 extern __at(0x0695) __sfr COG1DBR
;
4501 unsigned G1DBR0
: 1;
4502 unsigned G1DBR1
: 1;
4503 unsigned G1DBR2
: 1;
4504 unsigned G1DBR3
: 1;
4505 unsigned G1DBR4
: 1;
4506 unsigned G1DBR5
: 1;
4518 extern __at(0x0695) volatile __COG1DBRbits_t COG1DBRbits
;
4520 #define _G1DBR0 0x01
4521 #define _G1DBR1 0x02
4522 #define _G1DBR2 0x04
4523 #define _G1DBR3 0x08
4524 #define _G1DBR4 0x10
4525 #define _G1DBR5 0x20
4527 //==============================================================================
4530 //==============================================================================
4533 extern __at(0x0696) __sfr COG1DBF
;
4539 unsigned G1DBF0
: 1;
4540 unsigned G1DBF1
: 1;
4541 unsigned G1DBF2
: 1;
4542 unsigned G1DBF3
: 1;
4543 unsigned G1DBF4
: 1;
4544 unsigned G1DBF5
: 1;
4556 extern __at(0x0696) volatile __COG1DBFbits_t COG1DBFbits
;
4558 #define _G1DBF0 0x01
4559 #define _G1DBF1 0x02
4560 #define _G1DBF2 0x04
4561 #define _G1DBF3 0x08
4562 #define _G1DBF4 0x10
4563 #define _G1DBF5 0x20
4565 //==============================================================================
4568 //==============================================================================
4571 extern __at(0x0697) __sfr COG1CON0
;
4601 extern __at(0x0697) volatile __COG1CON0bits_t COG1CON0bits
;
4611 //==============================================================================
4614 //==============================================================================
4617 extern __at(0x0698) __sfr COG1CON1
;
4621 unsigned G1POLA
: 1;
4622 unsigned G1POLB
: 1;
4623 unsigned G1POLC
: 1;
4624 unsigned G1POLD
: 1;
4627 unsigned G1FDBS
: 1;
4628 unsigned G1RDBS
: 1;
4631 extern __at(0x0698) volatile __COG1CON1bits_t COG1CON1bits
;
4633 #define _G1POLA 0x01
4634 #define _G1POLB 0x02
4635 #define _G1POLC 0x04
4636 #define _G1POLD 0x08
4637 #define _G1FDBS 0x40
4638 #define _G1RDBS 0x80
4640 //==============================================================================
4643 //==============================================================================
4646 extern __at(0x0699) __sfr COG1RIS
;
4652 unsigned G1RIS0
: 1;
4653 unsigned G1RIS1
: 1;
4654 unsigned G1RIS2
: 1;
4655 unsigned G1RIS3
: 1;
4656 unsigned G1RIS4
: 1;
4657 unsigned G1RIS5
: 1;
4658 unsigned G1RIS6
: 1;
4669 extern __at(0x0699) volatile __COG1RISbits_t COG1RISbits
;
4671 #define _G1RIS0 0x01
4672 #define _G1RIS1 0x02
4673 #define _G1RIS2 0x04
4674 #define _G1RIS3 0x08
4675 #define _G1RIS4 0x10
4676 #define _G1RIS5 0x20
4677 #define _G1RIS6 0x40
4679 //==============================================================================
4682 //==============================================================================
4685 extern __at(0x069A) __sfr COG1RSIM
;
4691 unsigned G1RSIM0
: 1;
4692 unsigned G1RSIM1
: 1;
4693 unsigned G1RSIM2
: 1;
4694 unsigned G1RSIM3
: 1;
4695 unsigned G1RSIM4
: 1;
4696 unsigned G1RSIM5
: 1;
4697 unsigned G1RSIM6
: 1;
4703 unsigned G1RSIM
: 7;
4708 extern __at(0x069A) volatile __COG1RSIMbits_t COG1RSIMbits
;
4710 #define _G1RSIM0 0x01
4711 #define _G1RSIM1 0x02
4712 #define _G1RSIM2 0x04
4713 #define _G1RSIM3 0x08
4714 #define _G1RSIM4 0x10
4715 #define _G1RSIM5 0x20
4716 #define _G1RSIM6 0x40
4718 //==============================================================================
4721 //==============================================================================
4724 extern __at(0x069B) __sfr COG1FIS
;
4730 unsigned G1FIS0
: 1;
4731 unsigned G1FIS1
: 1;
4732 unsigned G1FIS2
: 1;
4733 unsigned G1FIS3
: 1;
4734 unsigned G1FIS4
: 1;
4735 unsigned G1FIS5
: 1;
4736 unsigned G1FIS6
: 1;
4747 extern __at(0x069B) volatile __COG1FISbits_t COG1FISbits
;
4749 #define _G1FIS0 0x01
4750 #define _G1FIS1 0x02
4751 #define _G1FIS2 0x04
4752 #define _G1FIS3 0x08
4753 #define _G1FIS4 0x10
4754 #define _G1FIS5 0x20
4755 #define _G1FIS6 0x40
4757 //==============================================================================
4760 //==============================================================================
4763 extern __at(0x069C) __sfr COG1FSIM
;
4769 unsigned G1FSIM0
: 1;
4770 unsigned G1FSIM1
: 1;
4771 unsigned G1FSIM2
: 1;
4772 unsigned G1FSIM3
: 1;
4773 unsigned G1FSIM4
: 1;
4774 unsigned G1FSIM5
: 1;
4775 unsigned G1FSIM6
: 1;
4781 unsigned G1FSIM
: 7;
4786 extern __at(0x069C) volatile __COG1FSIMbits_t COG1FSIMbits
;
4788 #define _G1FSIM0 0x01
4789 #define _G1FSIM1 0x02
4790 #define _G1FSIM2 0x04
4791 #define _G1FSIM3 0x08
4792 #define _G1FSIM4 0x10
4793 #define _G1FSIM5 0x20
4794 #define _G1FSIM6 0x40
4796 //==============================================================================
4799 //==============================================================================
4802 extern __at(0x069D) __sfr COG1ASD0
;
4810 unsigned G1ASDAC0
: 1;
4811 unsigned G1ASDAC1
: 1;
4812 unsigned G1ASDBD0
: 1;
4813 unsigned G1ASDBD1
: 1;
4814 unsigned G1ARSEN
: 1;
4821 unsigned G1ASDAC
: 2;
4828 unsigned G1ASDBD
: 2;
4833 extern __at(0x069D) volatile __COG1ASD0bits_t COG1ASD0bits
;
4835 #define _G1ASDAC0 0x04
4836 #define _G1ASDAC1 0x08
4837 #define _G1ASDBD0 0x10
4838 #define _G1ASDBD1 0x20
4839 #define _G1ARSEN 0x40
4842 //==============================================================================
4845 //==============================================================================
4848 extern __at(0x069E) __sfr COG1ASD1
;
4852 unsigned G1AS0E
: 1;
4853 unsigned G1AS1E
: 1;
4854 unsigned G1AS2E
: 1;
4855 unsigned G1AS3E
: 1;
4862 extern __at(0x069E) volatile __COG1ASD1bits_t COG1ASD1bits
;
4864 #define _G1AS0E 0x01
4865 #define _G1AS1E 0x02
4866 #define _G1AS2E 0x04
4867 #define _G1AS3E 0x08
4869 //==============================================================================
4872 //==============================================================================
4875 extern __at(0x069F) __sfr COG1STR
;
4879 unsigned G1STRA
: 1;
4880 unsigned G1STRB
: 1;
4881 unsigned G1STRC
: 1;
4882 unsigned G1STRD
: 1;
4883 unsigned G1SDATA
: 1;
4884 unsigned G1SDATB
: 1;
4885 unsigned G1SDATC
: 1;
4886 unsigned G1SDATD
: 1;
4889 extern __at(0x069F) volatile __COG1STRbits_t COG1STRbits
;
4891 #define _G1STRA 0x01
4892 #define _G1STRB 0x02
4893 #define _G1STRC 0x04
4894 #define _G1STRD 0x08
4895 #define _G1SDATA 0x10
4896 #define _G1SDATB 0x20
4897 #define _G1SDATC 0x40
4898 #define _G1SDATD 0x80
4900 //==============================================================================
4903 //==============================================================================
4906 extern __at(0x0E0F) __sfr PPSLOCK
;
4910 unsigned PPSLOCKED
: 1;
4920 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
4922 #define _PPSLOCKED 0x01
4924 //==============================================================================
4926 extern __at(0x0E10) __sfr INTPPS
;
4927 extern __at(0x0E11) __sfr T0CKIPPS
;
4928 extern __at(0x0E12) __sfr T1CKIPPS
;
4929 extern __at(0x0E13) __sfr T1GPPS
;
4930 extern __at(0x0E14) __sfr CCP1PPS
;
4931 extern __at(0x0E15) __sfr CCP2PPS
;
4932 extern __at(0x0E17) __sfr COGINPPS
;
4933 extern __at(0x0E20) __sfr SSPCLKPPS
;
4934 extern __at(0x0E21) __sfr SSPDATPPS
;
4935 extern __at(0x0E22) __sfr SSPSSPPS
;
4936 extern __at(0x0E24) __sfr RXPPS
;
4937 extern __at(0x0E25) __sfr CKPPS
;
4938 extern __at(0x0E28) __sfr CLCIN0PPS
;
4939 extern __at(0x0E29) __sfr CLCIN1PPS
;
4940 extern __at(0x0E2A) __sfr CLCIN2PPS
;
4941 extern __at(0x0E2B) __sfr CLCIN3PPS
;
4942 extern __at(0x0E90) __sfr RA0PPS
;
4943 extern __at(0x0E91) __sfr RA1PPS
;
4944 extern __at(0x0E92) __sfr RA2PPS
;
4945 extern __at(0x0E94) __sfr RA4PPS
;
4946 extern __at(0x0E95) __sfr RA5PPS
;
4947 extern __at(0x0E9C) __sfr RB4PPS
;
4948 extern __at(0x0E9D) __sfr RB5PPS
;
4949 extern __at(0x0E9E) __sfr RB6PPS
;
4950 extern __at(0x0E9F) __sfr RB7PPS
;
4951 extern __at(0x0EA0) __sfr RC0PPS
;
4952 extern __at(0x0EA1) __sfr RC1PPS
;
4953 extern __at(0x0EA2) __sfr RC2PPS
;
4954 extern __at(0x0EA3) __sfr RC3PPS
;
4955 extern __at(0x0EA4) __sfr RC4PPS
;
4956 extern __at(0x0EA5) __sfr RC5PPS
;
4957 extern __at(0x0EA6) __sfr RC6PPS
;
4958 extern __at(0x0EA7) __sfr RC7PPS
;
4960 //==============================================================================
4963 extern __at(0x0F0F) __sfr CLCDATA
;
4967 unsigned MCLC1OUT
: 1;
4968 unsigned MCLC2OUT
: 1;
4969 unsigned MCLC3OUT
: 1;
4977 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
4979 #define _MCLC1OUT 0x01
4980 #define _MCLC2OUT 0x02
4981 #define _MCLC3OUT 0x04
4983 //==============================================================================
4986 //==============================================================================
4989 extern __at(0x0F10) __sfr CLC1CON
;
4995 unsigned LC1MODE0
: 1;
4996 unsigned LC1MODE1
: 1;
4997 unsigned LC1MODE2
: 1;
4998 unsigned LC1INTN
: 1;
4999 unsigned LC1INTP
: 1;
5000 unsigned LC1OUT
: 1;
5025 unsigned LC1MODE
: 3;
5030 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
5032 #define _LC1MODE0 0x01
5034 #define _LC1MODE1 0x02
5036 #define _LC1MODE2 0x04
5038 #define _LC1INTN 0x08
5040 #define _LC1INTP 0x10
5042 #define _LC1OUT 0x20
5047 //==============================================================================
5050 //==============================================================================
5053 extern __at(0x0F11) __sfr CLC1POL
;
5059 unsigned LC1G1POL
: 1;
5060 unsigned LC1G2POL
: 1;
5061 unsigned LC1G3POL
: 1;
5062 unsigned LC1G4POL
: 1;
5066 unsigned LC1POL
: 1;
5082 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
5084 #define _LC1G1POL 0x01
5086 #define _LC1G2POL 0x02
5088 #define _LC1G3POL 0x04
5090 #define _LC1G4POL 0x08
5092 #define _LC1POL 0x80
5095 //==============================================================================
5098 //==============================================================================
5101 extern __at(0x0F12) __sfr CLC1SEL0
;
5107 unsigned LC1D1S0
: 1;
5108 unsigned LC1D1S1
: 1;
5109 unsigned LC1D1S2
: 1;
5110 unsigned LC1D1S3
: 1;
5111 unsigned LC1D1S4
: 1;
5131 unsigned LC1D1S
: 5;
5142 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
5144 #define _LC1D1S0 0x01
5146 #define _LC1D1S1 0x02
5148 #define _LC1D1S2 0x04
5150 #define _LC1D1S3 0x08
5152 #define _LC1D1S4 0x10
5155 //==============================================================================
5158 //==============================================================================
5161 extern __at(0x0F13) __sfr CLC1SEL1
;
5167 unsigned LC1D2S0
: 1;
5168 unsigned LC1D2S1
: 1;
5169 unsigned LC1D2S2
: 1;
5170 unsigned LC1D2S3
: 1;
5171 unsigned LC1D2S4
: 1;
5197 unsigned LC1D2S
: 5;
5202 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
5204 #define _LC1D2S0 0x01
5206 #define _LC1D2S1 0x02
5208 #define _LC1D2S2 0x04
5210 #define _LC1D2S3 0x08
5212 #define _LC1D2S4 0x10
5215 //==============================================================================
5218 //==============================================================================
5221 extern __at(0x0F14) __sfr CLC1SEL2
;
5227 unsigned LC1D3S0
: 1;
5228 unsigned LC1D3S1
: 1;
5229 unsigned LC1D3S2
: 1;
5230 unsigned LC1D3S3
: 1;
5231 unsigned LC1D3S4
: 1;
5251 unsigned LC1D3S
: 5;
5262 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
5264 #define _LC1D3S0 0x01
5266 #define _LC1D3S1 0x02
5268 #define _LC1D3S2 0x04
5270 #define _LC1D3S3 0x08
5272 #define _LC1D3S4 0x10
5275 //==============================================================================
5278 //==============================================================================
5281 extern __at(0x0F15) __sfr CLC1SEL3
;
5287 unsigned LC1D4S0
: 1;
5288 unsigned LC1D4S1
: 1;
5289 unsigned LC1D4S2
: 1;
5290 unsigned LC1D4S3
: 1;
5291 unsigned LC1D4S4
: 1;
5317 unsigned LC1D4S
: 5;
5322 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
5324 #define _LC1D4S0 0x01
5326 #define _LC1D4S1 0x02
5328 #define _LC1D4S2 0x04
5330 #define _LC1D4S3 0x08
5332 #define _LC1D4S4 0x10
5335 //==============================================================================
5338 //==============================================================================
5341 extern __at(0x0F16) __sfr CLC1GLS0
;
5347 unsigned LC1G1D1N
: 1;
5348 unsigned LC1G1D1T
: 1;
5349 unsigned LC1G1D2N
: 1;
5350 unsigned LC1G1D2T
: 1;
5351 unsigned LC1G1D3N
: 1;
5352 unsigned LC1G1D3T
: 1;
5353 unsigned LC1G1D4N
: 1;
5354 unsigned LC1G1D4T
: 1;
5370 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
5372 #define _LC1G1D1N 0x01
5374 #define _LC1G1D1T 0x02
5376 #define _LC1G1D2N 0x04
5378 #define _LC1G1D2T 0x08
5380 #define _LC1G1D3N 0x10
5382 #define _LC1G1D3T 0x20
5384 #define _LC1G1D4N 0x40
5386 #define _LC1G1D4T 0x80
5389 //==============================================================================
5392 //==============================================================================
5395 extern __at(0x0F17) __sfr CLC1GLS1
;
5401 unsigned LC1G2D1N
: 1;
5402 unsigned LC1G2D1T
: 1;
5403 unsigned LC1G2D2N
: 1;
5404 unsigned LC1G2D2T
: 1;
5405 unsigned LC1G2D3N
: 1;
5406 unsigned LC1G2D3T
: 1;
5407 unsigned LC1G2D4N
: 1;
5408 unsigned LC1G2D4T
: 1;
5424 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
5426 #define _CLC1GLS1_LC1G2D1N 0x01
5427 #define _CLC1GLS1_D1N 0x01
5428 #define _CLC1GLS1_LC1G2D1T 0x02
5429 #define _CLC1GLS1_D1T 0x02
5430 #define _CLC1GLS1_LC1G2D2N 0x04
5431 #define _CLC1GLS1_D2N 0x04
5432 #define _CLC1GLS1_LC1G2D2T 0x08
5433 #define _CLC1GLS1_D2T 0x08
5434 #define _CLC1GLS1_LC1G2D3N 0x10
5435 #define _CLC1GLS1_D3N 0x10
5436 #define _CLC1GLS1_LC1G2D3T 0x20
5437 #define _CLC1GLS1_D3T 0x20
5438 #define _CLC1GLS1_LC1G2D4N 0x40
5439 #define _CLC1GLS1_D4N 0x40
5440 #define _CLC1GLS1_LC1G2D4T 0x80
5441 #define _CLC1GLS1_D4T 0x80
5443 //==============================================================================
5446 //==============================================================================
5449 extern __at(0x0F18) __sfr CLC1GLS2
;
5455 unsigned LC1G3D1N
: 1;
5456 unsigned LC1G3D1T
: 1;
5457 unsigned LC1G3D2N
: 1;
5458 unsigned LC1G3D2T
: 1;
5459 unsigned LC1G3D3N
: 1;
5460 unsigned LC1G3D3T
: 1;
5461 unsigned LC1G3D4N
: 1;
5462 unsigned LC1G3D4T
: 1;
5478 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
5480 #define _CLC1GLS2_LC1G3D1N 0x01
5481 #define _CLC1GLS2_D1N 0x01
5482 #define _CLC1GLS2_LC1G3D1T 0x02
5483 #define _CLC1GLS2_D1T 0x02
5484 #define _CLC1GLS2_LC1G3D2N 0x04
5485 #define _CLC1GLS2_D2N 0x04
5486 #define _CLC1GLS2_LC1G3D2T 0x08
5487 #define _CLC1GLS2_D2T 0x08
5488 #define _CLC1GLS2_LC1G3D3N 0x10
5489 #define _CLC1GLS2_D3N 0x10
5490 #define _CLC1GLS2_LC1G3D3T 0x20
5491 #define _CLC1GLS2_D3T 0x20
5492 #define _CLC1GLS2_LC1G3D4N 0x40
5493 #define _CLC1GLS2_D4N 0x40
5494 #define _CLC1GLS2_LC1G3D4T 0x80
5495 #define _CLC1GLS2_D4T 0x80
5497 //==============================================================================
5500 //==============================================================================
5503 extern __at(0x0F19) __sfr CLC1GLS3
;
5509 unsigned LC1G4D1N
: 1;
5510 unsigned LC1G4D1T
: 1;
5511 unsigned LC1G4D2N
: 1;
5512 unsigned LC1G4D2T
: 1;
5513 unsigned LC1G4D3N
: 1;
5514 unsigned LC1G4D3T
: 1;
5515 unsigned LC1G4D4N
: 1;
5516 unsigned LC1G4D4T
: 1;
5532 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
5534 #define _LC1G4D1N 0x01
5536 #define _LC1G4D1T 0x02
5538 #define _LC1G4D2N 0x04
5540 #define _LC1G4D2T 0x08
5542 #define _LC1G4D3N 0x10
5544 #define _LC1G4D3T 0x20
5546 #define _LC1G4D4N 0x40
5548 #define _LC1G4D4T 0x80
5551 //==============================================================================
5554 //==============================================================================
5557 extern __at(0x0F1A) __sfr CLC2CON
;
5563 unsigned LC2MODE0
: 1;
5564 unsigned LC2MODE1
: 1;
5565 unsigned LC2MODE2
: 1;
5566 unsigned LC2INTN
: 1;
5567 unsigned LC2INTP
: 1;
5568 unsigned LC2OUT
: 1;
5593 unsigned LC2MODE
: 3;
5598 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
5600 #define _CLC2CON_LC2MODE0 0x01
5601 #define _CLC2CON_MODE0 0x01
5602 #define _CLC2CON_LC2MODE1 0x02
5603 #define _CLC2CON_MODE1 0x02
5604 #define _CLC2CON_LC2MODE2 0x04
5605 #define _CLC2CON_MODE2 0x04
5606 #define _CLC2CON_LC2INTN 0x08
5607 #define _CLC2CON_INTN 0x08
5608 #define _CLC2CON_LC2INTP 0x10
5609 #define _CLC2CON_INTP 0x10
5610 #define _CLC2CON_LC2OUT 0x20
5611 #define _CLC2CON_OUT 0x20
5612 #define _CLC2CON_LC2EN 0x80
5613 #define _CLC2CON_EN 0x80
5615 //==============================================================================
5618 //==============================================================================
5621 extern __at(0x0F1B) __sfr CLC2POL
;
5627 unsigned LC2G1POL
: 1;
5628 unsigned LC2G2POL
: 1;
5629 unsigned LC2G3POL
: 1;
5630 unsigned LC2G4POL
: 1;
5634 unsigned LC2POL
: 1;
5650 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
5652 #define _CLC2POL_LC2G1POL 0x01
5653 #define _CLC2POL_G1POL 0x01
5654 #define _CLC2POL_LC2G2POL 0x02
5655 #define _CLC2POL_G2POL 0x02
5656 #define _CLC2POL_LC2G3POL 0x04
5657 #define _CLC2POL_G3POL 0x04
5658 #define _CLC2POL_LC2G4POL 0x08
5659 #define _CLC2POL_G4POL 0x08
5660 #define _CLC2POL_LC2POL 0x80
5661 #define _CLC2POL_POL 0x80
5663 //==============================================================================
5666 //==============================================================================
5669 extern __at(0x0F1C) __sfr CLC2SEL0
;
5675 unsigned LC2D1S0
: 1;
5676 unsigned LC2D1S1
: 1;
5677 unsigned LC2D1S2
: 1;
5678 unsigned LC2D1S3
: 1;
5679 unsigned LC2D1S4
: 1;
5705 unsigned LC2D1S
: 5;
5710 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
5712 #define _CLC2SEL0_LC2D1S0 0x01
5713 #define _CLC2SEL0_D1S0 0x01
5714 #define _CLC2SEL0_LC2D1S1 0x02
5715 #define _CLC2SEL0_D1S1 0x02
5716 #define _CLC2SEL0_LC2D1S2 0x04
5717 #define _CLC2SEL0_D1S2 0x04
5718 #define _CLC2SEL0_LC2D1S3 0x08
5719 #define _CLC2SEL0_D1S3 0x08
5720 #define _CLC2SEL0_LC2D1S4 0x10
5721 #define _CLC2SEL0_D1S4 0x10
5723 //==============================================================================
5726 //==============================================================================
5729 extern __at(0x0F1D) __sfr CLC2SEL1
;
5735 unsigned LC2D2S0
: 1;
5736 unsigned LC2D2S1
: 1;
5737 unsigned LC2D2S2
: 1;
5738 unsigned LC2D2S3
: 1;
5739 unsigned LC2D2S4
: 1;
5759 unsigned LC2D2S
: 5;
5770 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
5772 #define _CLC2SEL1_LC2D2S0 0x01
5773 #define _CLC2SEL1_D2S0 0x01
5774 #define _CLC2SEL1_LC2D2S1 0x02
5775 #define _CLC2SEL1_D2S1 0x02
5776 #define _CLC2SEL1_LC2D2S2 0x04
5777 #define _CLC2SEL1_D2S2 0x04
5778 #define _CLC2SEL1_LC2D2S3 0x08
5779 #define _CLC2SEL1_D2S3 0x08
5780 #define _CLC2SEL1_LC2D2S4 0x10
5781 #define _CLC2SEL1_D2S4 0x10
5783 //==============================================================================
5786 //==============================================================================
5789 extern __at(0x0F1E) __sfr CLC2SEL2
;
5795 unsigned LC2D3S0
: 1;
5796 unsigned LC2D3S1
: 1;
5797 unsigned LC2D3S2
: 1;
5798 unsigned LC2D3S3
: 1;
5799 unsigned LC2D3S4
: 1;
5825 unsigned LC2D3S
: 5;
5830 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
5832 #define _CLC2SEL2_LC2D3S0 0x01
5833 #define _CLC2SEL2_D3S0 0x01
5834 #define _CLC2SEL2_LC2D3S1 0x02
5835 #define _CLC2SEL2_D3S1 0x02
5836 #define _CLC2SEL2_LC2D3S2 0x04
5837 #define _CLC2SEL2_D3S2 0x04
5838 #define _CLC2SEL2_LC2D3S3 0x08
5839 #define _CLC2SEL2_D3S3 0x08
5840 #define _CLC2SEL2_LC2D3S4 0x10
5841 #define _CLC2SEL2_D3S4 0x10
5843 //==============================================================================
5846 //==============================================================================
5849 extern __at(0x0F1F) __sfr CLC2SEL3
;
5855 unsigned LC2D4S0
: 1;
5856 unsigned LC2D4S1
: 1;
5857 unsigned LC2D4S2
: 1;
5858 unsigned LC2D4S3
: 1;
5859 unsigned LC2D4S4
: 1;
5885 unsigned LC2D4S
: 5;
5890 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
5892 #define _CLC2SEL3_LC2D4S0 0x01
5893 #define _CLC2SEL3_D4S0 0x01
5894 #define _CLC2SEL3_LC2D4S1 0x02
5895 #define _CLC2SEL3_D4S1 0x02
5896 #define _CLC2SEL3_LC2D4S2 0x04
5897 #define _CLC2SEL3_D4S2 0x04
5898 #define _CLC2SEL3_LC2D4S3 0x08
5899 #define _CLC2SEL3_D4S3 0x08
5900 #define _CLC2SEL3_LC2D4S4 0x10
5901 #define _CLC2SEL3_D4S4 0x10
5903 //==============================================================================
5906 //==============================================================================
5909 extern __at(0x0F20) __sfr CLC2GLS0
;
5915 unsigned LC2G1D1N
: 1;
5916 unsigned LC2G1D1T
: 1;
5917 unsigned LC2G1D2N
: 1;
5918 unsigned LC2G1D2T
: 1;
5919 unsigned LC2G1D3N
: 1;
5920 unsigned LC2G1D3T
: 1;
5921 unsigned LC2G1D4N
: 1;
5922 unsigned LC2G1D4T
: 1;
5938 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
5940 #define _CLC2GLS0_LC2G1D1N 0x01
5941 #define _CLC2GLS0_D1N 0x01
5942 #define _CLC2GLS0_LC2G1D1T 0x02
5943 #define _CLC2GLS0_D1T 0x02
5944 #define _CLC2GLS0_LC2G1D2N 0x04
5945 #define _CLC2GLS0_D2N 0x04
5946 #define _CLC2GLS0_LC2G1D2T 0x08
5947 #define _CLC2GLS0_D2T 0x08
5948 #define _CLC2GLS0_LC2G1D3N 0x10
5949 #define _CLC2GLS0_D3N 0x10
5950 #define _CLC2GLS0_LC2G1D3T 0x20
5951 #define _CLC2GLS0_D3T 0x20
5952 #define _CLC2GLS0_LC2G1D4N 0x40
5953 #define _CLC2GLS0_D4N 0x40
5954 #define _CLC2GLS0_LC2G1D4T 0x80
5955 #define _CLC2GLS0_D4T 0x80
5957 //==============================================================================
5960 //==============================================================================
5963 extern __at(0x0F21) __sfr CLC2GLS1
;
5969 unsigned LC2G2D1N
: 1;
5970 unsigned LC2G2D1T
: 1;
5971 unsigned LC2G2D2N
: 1;
5972 unsigned LC2G2D2T
: 1;
5973 unsigned LC2G2D3N
: 1;
5974 unsigned LC2G2D3T
: 1;
5975 unsigned LC2G2D4N
: 1;
5976 unsigned LC2G2D4T
: 1;
5992 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
5994 #define _CLC2GLS1_LC2G2D1N 0x01
5995 #define _CLC2GLS1_D1N 0x01
5996 #define _CLC2GLS1_LC2G2D1T 0x02
5997 #define _CLC2GLS1_D1T 0x02
5998 #define _CLC2GLS1_LC2G2D2N 0x04
5999 #define _CLC2GLS1_D2N 0x04
6000 #define _CLC2GLS1_LC2G2D2T 0x08
6001 #define _CLC2GLS1_D2T 0x08
6002 #define _CLC2GLS1_LC2G2D3N 0x10
6003 #define _CLC2GLS1_D3N 0x10
6004 #define _CLC2GLS1_LC2G2D3T 0x20
6005 #define _CLC2GLS1_D3T 0x20
6006 #define _CLC2GLS1_LC2G2D4N 0x40
6007 #define _CLC2GLS1_D4N 0x40
6008 #define _CLC2GLS1_LC2G2D4T 0x80
6009 #define _CLC2GLS1_D4T 0x80
6011 //==============================================================================
6014 //==============================================================================
6017 extern __at(0x0F22) __sfr CLC2GLS2
;
6023 unsigned LC2G3D1N
: 1;
6024 unsigned LC2G3D1T
: 1;
6025 unsigned LC2G3D2N
: 1;
6026 unsigned LC2G3D2T
: 1;
6027 unsigned LC2G3D3N
: 1;
6028 unsigned LC2G3D3T
: 1;
6029 unsigned LC2G3D4N
: 1;
6030 unsigned LC2G3D4T
: 1;
6046 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
6048 #define _CLC2GLS2_LC2G3D1N 0x01
6049 #define _CLC2GLS2_D1N 0x01
6050 #define _CLC2GLS2_LC2G3D1T 0x02
6051 #define _CLC2GLS2_D1T 0x02
6052 #define _CLC2GLS2_LC2G3D2N 0x04
6053 #define _CLC2GLS2_D2N 0x04
6054 #define _CLC2GLS2_LC2G3D2T 0x08
6055 #define _CLC2GLS2_D2T 0x08
6056 #define _CLC2GLS2_LC2G3D3N 0x10
6057 #define _CLC2GLS2_D3N 0x10
6058 #define _CLC2GLS2_LC2G3D3T 0x20
6059 #define _CLC2GLS2_D3T 0x20
6060 #define _CLC2GLS2_LC2G3D4N 0x40
6061 #define _CLC2GLS2_D4N 0x40
6062 #define _CLC2GLS2_LC2G3D4T 0x80
6063 #define _CLC2GLS2_D4T 0x80
6065 //==============================================================================
6068 //==============================================================================
6071 extern __at(0x0F23) __sfr CLC2GLS3
;
6077 unsigned LC2G4D1N
: 1;
6078 unsigned LC2G4D1T
: 1;
6079 unsigned LC2G4D2N
: 1;
6080 unsigned LC2G4D2T
: 1;
6081 unsigned LC2G4D3N
: 1;
6082 unsigned LC2G4D3T
: 1;
6083 unsigned LC2G4D4N
: 1;
6084 unsigned LC2G4D4T
: 1;
6100 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
6102 #define _CLC2GLS3_LC2G4D1N 0x01
6103 #define _CLC2GLS3_G4D1N 0x01
6104 #define _CLC2GLS3_LC2G4D1T 0x02
6105 #define _CLC2GLS3_G4D1T 0x02
6106 #define _CLC2GLS3_LC2G4D2N 0x04
6107 #define _CLC2GLS3_G4D2N 0x04
6108 #define _CLC2GLS3_LC2G4D2T 0x08
6109 #define _CLC2GLS3_G4D2T 0x08
6110 #define _CLC2GLS3_LC2G4D3N 0x10
6111 #define _CLC2GLS3_G4D3N 0x10
6112 #define _CLC2GLS3_LC2G4D3T 0x20
6113 #define _CLC2GLS3_G4D3T 0x20
6114 #define _CLC2GLS3_LC2G4D4N 0x40
6115 #define _CLC2GLS3_G4D4N 0x40
6116 #define _CLC2GLS3_LC2G4D4T 0x80
6117 #define _CLC2GLS3_G4D4T 0x80
6119 //==============================================================================
6122 //==============================================================================
6125 extern __at(0x0F24) __sfr CLC3CON
;
6131 unsigned LC3MODE0
: 1;
6132 unsigned LC3MODE1
: 1;
6133 unsigned LC3MODE2
: 1;
6134 unsigned LC3INTN
: 1;
6135 unsigned LC3INTP
: 1;
6136 unsigned LC3OUT
: 1;
6155 unsigned LC3MODE
: 3;
6166 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
6168 #define _CLC3CON_LC3MODE0 0x01
6169 #define _CLC3CON_MODE0 0x01
6170 #define _CLC3CON_LC3MODE1 0x02
6171 #define _CLC3CON_MODE1 0x02
6172 #define _CLC3CON_LC3MODE2 0x04
6173 #define _CLC3CON_MODE2 0x04
6174 #define _CLC3CON_LC3INTN 0x08
6175 #define _CLC3CON_INTN 0x08
6176 #define _CLC3CON_LC3INTP 0x10
6177 #define _CLC3CON_INTP 0x10
6178 #define _CLC3CON_LC3OUT 0x20
6179 #define _CLC3CON_OUT 0x20
6180 #define _CLC3CON_LC3EN 0x80
6181 #define _CLC3CON_EN 0x80
6183 //==============================================================================
6186 //==============================================================================
6189 extern __at(0x0F25) __sfr CLC3POL
;
6195 unsigned LC3G1POL
: 1;
6196 unsigned LC3G2POL
: 1;
6197 unsigned LC3G3POL
: 1;
6198 unsigned LC3G4POL
: 1;
6202 unsigned LC3POL
: 1;
6218 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
6220 #define _CLC3POL_LC3G1POL 0x01
6221 #define _CLC3POL_G1POL 0x01
6222 #define _CLC3POL_LC3G2POL 0x02
6223 #define _CLC3POL_G2POL 0x02
6224 #define _CLC3POL_LC3G3POL 0x04
6225 #define _CLC3POL_G3POL 0x04
6226 #define _CLC3POL_LC3G4POL 0x08
6227 #define _CLC3POL_G4POL 0x08
6228 #define _CLC3POL_LC3POL 0x80
6229 #define _CLC3POL_POL 0x80
6231 //==============================================================================
6234 //==============================================================================
6237 extern __at(0x0F26) __sfr CLC3SEL0
;
6243 unsigned LC3D1S0
: 1;
6244 unsigned LC3D1S1
: 1;
6245 unsigned LC3D1S2
: 1;
6246 unsigned LC3D1S3
: 1;
6247 unsigned LC3D1S4
: 1;
6273 unsigned LC3D1S
: 5;
6278 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
6280 #define _CLC3SEL0_LC3D1S0 0x01
6281 #define _CLC3SEL0_D1S0 0x01
6282 #define _CLC3SEL0_LC3D1S1 0x02
6283 #define _CLC3SEL0_D1S1 0x02
6284 #define _CLC3SEL0_LC3D1S2 0x04
6285 #define _CLC3SEL0_D1S2 0x04
6286 #define _CLC3SEL0_LC3D1S3 0x08
6287 #define _CLC3SEL0_D1S3 0x08
6288 #define _CLC3SEL0_LC3D1S4 0x10
6289 #define _CLC3SEL0_D1S4 0x10
6291 //==============================================================================
6294 //==============================================================================
6297 extern __at(0x0F27) __sfr CLC3SEL1
;
6303 unsigned LC3D2S0
: 1;
6304 unsigned LC3D2S1
: 1;
6305 unsigned LC3D2S2
: 1;
6306 unsigned LC3D2S3
: 1;
6307 unsigned LC3D2S4
: 1;
6333 unsigned LC3D2S
: 5;
6338 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
6340 #define _CLC3SEL1_LC3D2S0 0x01
6341 #define _CLC3SEL1_D2S0 0x01
6342 #define _CLC3SEL1_LC3D2S1 0x02
6343 #define _CLC3SEL1_D2S1 0x02
6344 #define _CLC3SEL1_LC3D2S2 0x04
6345 #define _CLC3SEL1_D2S2 0x04
6346 #define _CLC3SEL1_LC3D2S3 0x08
6347 #define _CLC3SEL1_D2S3 0x08
6348 #define _CLC3SEL1_LC3D2S4 0x10
6349 #define _CLC3SEL1_D2S4 0x10
6351 //==============================================================================
6354 //==============================================================================
6357 extern __at(0x0F28) __sfr CLC3SEL2
;
6363 unsigned LC3D3S0
: 1;
6364 unsigned LC3D3S1
: 1;
6365 unsigned LC3D3S2
: 1;
6366 unsigned LC3D3S3
: 1;
6367 unsigned LC3D3S4
: 1;
6393 unsigned LC3D3S
: 5;
6398 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
6400 #define _CLC3SEL2_LC3D3S0 0x01
6401 #define _CLC3SEL2_D3S0 0x01
6402 #define _CLC3SEL2_LC3D3S1 0x02
6403 #define _CLC3SEL2_D3S1 0x02
6404 #define _CLC3SEL2_LC3D3S2 0x04
6405 #define _CLC3SEL2_D3S2 0x04
6406 #define _CLC3SEL2_LC3D3S3 0x08
6407 #define _CLC3SEL2_D3S3 0x08
6408 #define _CLC3SEL2_LC3D3S4 0x10
6409 #define _CLC3SEL2_D3S4 0x10
6411 //==============================================================================
6414 //==============================================================================
6417 extern __at(0x0F29) __sfr CLC3SEL3
;
6423 unsigned LC3D4S0
: 1;
6424 unsigned LC3D4S1
: 1;
6425 unsigned LC3D4S2
: 1;
6426 unsigned LC3D4S3
: 1;
6427 unsigned LC3D4S4
: 1;
6447 unsigned LC3D4S
: 5;
6458 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
6460 #define _CLC3SEL3_LC3D4S0 0x01
6461 #define _CLC3SEL3_D4S0 0x01
6462 #define _CLC3SEL3_LC3D4S1 0x02
6463 #define _CLC3SEL3_D4S1 0x02
6464 #define _CLC3SEL3_LC3D4S2 0x04
6465 #define _CLC3SEL3_D4S2 0x04
6466 #define _CLC3SEL3_LC3D4S3 0x08
6467 #define _CLC3SEL3_D4S3 0x08
6468 #define _CLC3SEL3_LC3D4S4 0x10
6469 #define _CLC3SEL3_D4S4 0x10
6471 //==============================================================================
6474 //==============================================================================
6477 extern __at(0x0F2A) __sfr CLC3GLS0
;
6483 unsigned LC3G1D1N
: 1;
6484 unsigned LC3G1D1T
: 1;
6485 unsigned LC3G1D2N
: 1;
6486 unsigned LC3G1D2T
: 1;
6487 unsigned LC3G1D3N
: 1;
6488 unsigned LC3G1D3T
: 1;
6489 unsigned LC3G1D4N
: 1;
6490 unsigned LC3G1D4T
: 1;
6506 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
6508 #define _CLC3GLS0_LC3G1D1N 0x01
6509 #define _CLC3GLS0_D1N 0x01
6510 #define _CLC3GLS0_LC3G1D1T 0x02
6511 #define _CLC3GLS0_D1T 0x02
6512 #define _CLC3GLS0_LC3G1D2N 0x04
6513 #define _CLC3GLS0_D2N 0x04
6514 #define _CLC3GLS0_LC3G1D2T 0x08
6515 #define _CLC3GLS0_D2T 0x08
6516 #define _CLC3GLS0_LC3G1D3N 0x10
6517 #define _CLC3GLS0_D3N 0x10
6518 #define _CLC3GLS0_LC3G1D3T 0x20
6519 #define _CLC3GLS0_D3T 0x20
6520 #define _CLC3GLS0_LC3G1D4N 0x40
6521 #define _CLC3GLS0_D4N 0x40
6522 #define _CLC3GLS0_LC3G1D4T 0x80
6523 #define _CLC3GLS0_D4T 0x80
6525 //==============================================================================
6528 //==============================================================================
6531 extern __at(0x0F2B) __sfr CLC3GLS1
;
6537 unsigned LC3G2D1N
: 1;
6538 unsigned LC3G2D1T
: 1;
6539 unsigned LC3G2D2N
: 1;
6540 unsigned LC3G2D2T
: 1;
6541 unsigned LC3G2D3N
: 1;
6542 unsigned LC3G2D3T
: 1;
6543 unsigned LC3G2D4N
: 1;
6544 unsigned LC3G2D4T
: 1;
6560 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
6562 #define _CLC3GLS1_LC3G2D1N 0x01
6563 #define _CLC3GLS1_D1N 0x01
6564 #define _CLC3GLS1_LC3G2D1T 0x02
6565 #define _CLC3GLS1_D1T 0x02
6566 #define _CLC3GLS1_LC3G2D2N 0x04
6567 #define _CLC3GLS1_D2N 0x04
6568 #define _CLC3GLS1_LC3G2D2T 0x08
6569 #define _CLC3GLS1_D2T 0x08
6570 #define _CLC3GLS1_LC3G2D3N 0x10
6571 #define _CLC3GLS1_D3N 0x10
6572 #define _CLC3GLS1_LC3G2D3T 0x20
6573 #define _CLC3GLS1_D3T 0x20
6574 #define _CLC3GLS1_LC3G2D4N 0x40
6575 #define _CLC3GLS1_D4N 0x40
6576 #define _CLC3GLS1_LC3G2D4T 0x80
6577 #define _CLC3GLS1_D4T 0x80
6579 //==============================================================================
6582 //==============================================================================
6585 extern __at(0x0F2C) __sfr CLC3GLS2
;
6591 unsigned LC3G3D1N
: 1;
6592 unsigned LC3G3D1T
: 1;
6593 unsigned LC3G3D2N
: 1;
6594 unsigned LC3G3D2T
: 1;
6595 unsigned LC3G3D3N
: 1;
6596 unsigned LC3G3D3T
: 1;
6597 unsigned LC3G3D4N
: 1;
6598 unsigned LC3G3D4T
: 1;
6614 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
6616 #define _CLC3GLS2_LC3G3D1N 0x01
6617 #define _CLC3GLS2_D1N 0x01
6618 #define _CLC3GLS2_LC3G3D1T 0x02
6619 #define _CLC3GLS2_D1T 0x02
6620 #define _CLC3GLS2_LC3G3D2N 0x04
6621 #define _CLC3GLS2_D2N 0x04
6622 #define _CLC3GLS2_LC3G3D2T 0x08
6623 #define _CLC3GLS2_D2T 0x08
6624 #define _CLC3GLS2_LC3G3D3N 0x10
6625 #define _CLC3GLS2_D3N 0x10
6626 #define _CLC3GLS2_LC3G3D3T 0x20
6627 #define _CLC3GLS2_D3T 0x20
6628 #define _CLC3GLS2_LC3G3D4N 0x40
6629 #define _CLC3GLS2_D4N 0x40
6630 #define _CLC3GLS2_LC3G3D4T 0x80
6631 #define _CLC3GLS2_D4T 0x80
6633 //==============================================================================
6636 //==============================================================================
6639 extern __at(0x0F2D) __sfr CLC3GLS3
;
6645 unsigned LC3G4D1N
: 1;
6646 unsigned LC3G4D1T
: 1;
6647 unsigned LC3G4D2N
: 1;
6648 unsigned LC3G4D2T
: 1;
6649 unsigned LC3G4D3N
: 1;
6650 unsigned LC3G4D3T
: 1;
6651 unsigned LC3G4D4N
: 1;
6652 unsigned LC3G4D4T
: 1;
6668 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
6670 #define _CLC3GLS3_LC3G4D1N 0x01
6671 #define _CLC3GLS3_G4D1N 0x01
6672 #define _CLC3GLS3_LC3G4D1T 0x02
6673 #define _CLC3GLS3_G4D1T 0x02
6674 #define _CLC3GLS3_LC3G4D2N 0x04
6675 #define _CLC3GLS3_G4D2N 0x04
6676 #define _CLC3GLS3_LC3G4D2T 0x08
6677 #define _CLC3GLS3_G4D2T 0x08
6678 #define _CLC3GLS3_LC3G4D3N 0x10
6679 #define _CLC3GLS3_G4D3N 0x10
6680 #define _CLC3GLS3_LC3G4D3T 0x20
6681 #define _CLC3GLS3_G4D3T 0x20
6682 #define _CLC3GLS3_LC3G4D4N 0x40
6683 #define _CLC3GLS3_G4D4N 0x40
6684 #define _CLC3GLS3_LC3G4D4T 0x80
6685 #define _CLC3GLS3_G4D4T 0x80
6687 //==============================================================================
6690 //==============================================================================
6693 extern __at(0x0F9E) __sfr ICDBK0H
;
6707 extern __at(0x0F9E) volatile __ICDBK0Hbits_t ICDBK0Hbits
;
6717 //==============================================================================
6720 //==============================================================================
6723 extern __at(0x0FE4) __sfr STATUS_SHAD
;
6727 unsigned C_SHAD
: 1;
6728 unsigned DC_SHAD
: 1;
6729 unsigned Z_SHAD
: 1;
6735 } __STATUS_SHADbits_t
;
6737 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
6739 #define _C_SHAD 0x01
6740 #define _DC_SHAD 0x02
6741 #define _Z_SHAD 0x04
6743 //==============================================================================
6745 extern __at(0x0FE5) __sfr WREG_SHAD
;
6746 extern __at(0x0FE6) __sfr BSR_SHAD
;
6747 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
6748 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
6749 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
6750 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
6751 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
6752 extern __at(0x0FED) __sfr STKPTR
;
6753 extern __at(0x0FEE) __sfr TOSL
;
6754 extern __at(0x0FEF) __sfr TOSH
;
6756 //==============================================================================
6758 // Configuration Bits
6760 //==============================================================================
6762 #define _CONFIG1 0x8007
6763 #define _CONFIG2 0x8008
6765 //----------------------------- CONFIG1 Options -------------------------------
6767 #define _FOSC_LP 0x3FF8 // LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins.
6768 #define _FOSC_XT 0x3FF9 // XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins.
6769 #define _FOSC_HS 0x3FFA // HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins.
6770 #define _FOSC_EXTRC 0x3FFB // EXTRC oscillator: External RC circuit connected to CLKIN pin.
6771 #define _FOSC_INTOSC 0x3FFC // INTOSC oscillator: I/O function on CLKIN pin.
6772 #define _FOSC_ECL 0x3FFD // ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pins.
6773 #define _FOSC_ECM 0x3FFE // ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pins.
6774 #define _FOSC_ECH 0x3FFF // ECH, External Clock, High Power Mode (4-20 MHz): device clock supplied to CLKIN pins.
6775 #define _WDTE_OFF 0x3FE7 // WDT disabled.
6776 #define _WDTE_SWDTEN 0x3FEF // WDT controlled by the SWDTEN bit in the WDTCON register.
6777 #define _WDTE_NSLEEP 0x3FF7 // WDT enabled while running and disabled in Sleep.
6778 #define _WDTE_ON 0x3FFF // WDT enabled.
6779 #define _PWRTE_ON 0x3FDF // PWRT enabled.
6780 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
6781 #define _MCLRE_OFF 0x3FBF // MCLR/VPP pin function is digital input.
6782 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR.
6783 #define _CP_ON 0x3F7F // Program memory code protection is enabled.
6784 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
6785 #define _BOREN_OFF 0x39FF // Brown-out Reset disabled.
6786 #define _BOREN_SBODEN 0x3BFF // Brown-out Reset controlled by the SBOREN bit in the BORCON register.
6787 #define _BOREN_NSLEEP 0x3DFF // Brown-out Reset enabled while running and disabled in Sleep.
6788 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled.
6789 #define _CLKOUTEN_ON 0x37FF // CLKOUT function is enabled on the CLKOUT pin.
6790 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
6791 #define _IESO_OFF 0x2FFF // Internal/External Switchover Mode is disabled.
6792 #define _IESO_ON 0x3FFF // Internal/External Switchover Mode is enabled.
6793 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
6794 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
6796 //----------------------------- CONFIG2 Options -------------------------------
6798 #define _WRT_ALL 0x3FFC // 000h to 1FFFh write protected, no addresses may be modified by EECON control.
6799 #define _WRT_HALF 0x3FFD // 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control.
6800 #define _WRT_BOOT 0x3FFE // 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control.
6801 #define _WRT_OFF 0x3FFF // Write protection off.
6802 #define _PPS1WAY_OFF 0x3FFB // The PPSLOCK bit can be set and cleared repeatedly by software.
6803 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit cannot be cleared once it is set by software.
6804 #define _ZCDDIS_OFF 0x3F7F // Zero-cross detect circuit is enabled at POR.
6805 #define _ZCDDIS_ON 0x3FFF // Zero-cross detect circuit is disabled at POR.
6806 #define _PLLEN_OFF 0x3EFF // 4x PLL is enabled when software sets the SPLLEN bit.
6807 #define _PLLEN_ON 0x3FFF // 4x PLL is always enabled.
6808 #define _STVREN_OFF 0x3DFF // Stack Overflow or Underflow will not cause a Reset.
6809 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
6810 #define _BORV_HI 0x3BFF // Brown-out Reset Voltage (Vbor), high trip point selected.
6811 #define _BORV_LO 0x3FFF // Brown-out Reset Voltage (Vbor), low trip point selected.
6812 #define _LPBOR_ON 0x37FF // Low-Power BOR is enabled.
6813 #define _LPBOR_OFF 0x3FFF // Low-Power BOR is disabled.
6814 #define _DEBUG_ON 0x2FFF // In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger.
6815 #define _DEBUG_OFF 0x3FFF // In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins.
6816 #define _LVP_OFF 0x1FFF // High-voltage on MCLR/VPP must be used for programming.
6817 #define _LVP_ON 0x3FFF // Low-voltage programming enabled.
6819 //==============================================================================
6821 #define _DEVID1 0x8006
6823 #define _IDLOC0 0x8000
6824 #define _IDLOC1 0x8001
6825 #define _IDLOC2 0x8002
6826 #define _IDLOC3 0x8003
6828 //==============================================================================
6830 #ifndef NO_BIT_DEFINES
6832 #define ADON ADCON0bits.ADON // bit 0
6833 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
6834 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
6835 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
6836 #define CHS0 ADCON0bits.CHS0 // bit 2
6837 #define CHS1 ADCON0bits.CHS1 // bit 3
6838 #define CHS2 ADCON0bits.CHS2 // bit 4
6839 #define CHS3 ADCON0bits.CHS3 // bit 5
6840 #define CHS4 ADCON0bits.CHS4 // bit 6
6842 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
6843 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
6844 #define ADNREF ADCON1bits.ADNREF // bit 2
6845 #define ADFM ADCON1bits.ADFM // bit 7
6847 #define TRIGSEL0 ADCON2bits.TRIGSEL0 // bit 4
6848 #define TRIGSEL1 ADCON2bits.TRIGSEL1 // bit 5
6849 #define TRIGSEL2 ADCON2bits.TRIGSEL2 // bit 6
6850 #define TRIGSEL3 ADCON2bits.TRIGSEL3 // bit 7
6852 #define ANSA0 ANSELAbits.ANSA0 // bit 0
6853 #define ANSA1 ANSELAbits.ANSA1 // bit 1
6854 #define ANSA2 ANSELAbits.ANSA2 // bit 2
6855 #define ANSA4 ANSELAbits.ANSA4 // bit 4
6856 #define ANS5 ANSELAbits.ANS5 // bit 5
6858 #define ANSB4 ANSELBbits.ANSB4 // bit 4
6859 #define ANSB5 ANSELBbits.ANSB5 // bit 5
6861 #define ANSC0 ANSELCbits.ANSC0 // bit 0
6862 #define ANSC1 ANSELCbits.ANSC1 // bit 1
6863 #define ANSC2 ANSELCbits.ANSC2 // bit 2
6864 #define ANSC3 ANSELCbits.ANSC3 // bit 3
6865 #define ANSC6 ANSELCbits.ANSC6 // bit 6
6866 #define ANSC7 ANSELCbits.ANSC7 // bit 7
6868 #define ABDEN BAUD1CONbits.ABDEN // bit 0
6869 #define WUE BAUD1CONbits.WUE // bit 1
6870 #define BRG16 BAUD1CONbits.BRG16 // bit 3
6871 #define SCKP BAUD1CONbits.SCKP // bit 4
6872 #define RCIDL BAUD1CONbits.RCIDL // bit 6
6873 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
6875 #define BORRDY BORCONbits.BORRDY // bit 0
6876 #define BORFS BORCONbits.BORFS // bit 6
6877 #define SBOREN BORCONbits.SBOREN // bit 7
6879 #define BSR0 BSRbits.BSR0 // bit 0
6880 #define BSR1 BSRbits.BSR1 // bit 1
6881 #define BSR2 BSRbits.BSR2 // bit 2
6882 #define BSR3 BSRbits.BSR3 // bit 3
6883 #define BSR4 BSRbits.BSR4 // bit 4
6885 #define CCP1M0 CCP1CONbits.CCP1M0 // bit 0
6886 #define CCP1M1 CCP1CONbits.CCP1M1 // bit 1
6887 #define CCP1M2 CCP1CONbits.CCP1M2 // bit 2
6888 #define CCP1M3 CCP1CONbits.CCP1M3 // bit 3
6889 #define DC1B0 CCP1CONbits.DC1B0 // bit 4, shadows bit in CCP1CONbits
6890 #define CCP1Y CCP1CONbits.CCP1Y // bit 4, shadows bit in CCP1CONbits
6891 #define DC1B1 CCP1CONbits.DC1B1 // bit 5, shadows bit in CCP1CONbits
6892 #define CCP1X CCP1CONbits.CCP1X // bit 5, shadows bit in CCP1CONbits
6894 #define CCP2M0 CCP2CONbits.CCP2M0 // bit 0
6895 #define CCP2M1 CCP2CONbits.CCP2M1 // bit 1
6896 #define CCP2M2 CCP2CONbits.CCP2M2 // bit 2
6897 #define CCP2M3 CCP2CONbits.CCP2M3 // bit 3
6898 #define DC2B0 CCP2CONbits.DC2B0 // bit 4, shadows bit in CCP2CONbits
6899 #define CCP2Y CCP2CONbits.CCP2Y // bit 4, shadows bit in CCP2CONbits
6900 #define DC2B1 CCP2CONbits.DC2B1 // bit 5, shadows bit in CCP2CONbits
6901 #define CCP2X CCP2CONbits.CCP2X // bit 5, shadows bit in CCP2CONbits
6903 #define C1TSEL0 CCPTMRSbits.C1TSEL0 // bit 0
6904 #define C1TSEL1 CCPTMRSbits.C1TSEL1 // bit 1
6905 #define C2TSEL0 CCPTMRSbits.C2TSEL0 // bit 2
6906 #define C2TSEL1 CCPTMRSbits.C2TSEL1 // bit 3
6907 #define P3TSEL0 CCPTMRSbits.P3TSEL0 // bit 4
6908 #define P3TSEL1 CCPTMRSbits.P3TSEL1 // bit 5
6909 #define P4TSEL0 CCPTMRSbits.P4TSEL0 // bit 6
6910 #define P4TSEL1 CCPTMRSbits.P4TSEL1 // bit 7
6912 #define LC1MODE0 CLC1CONbits.LC1MODE0 // bit 0, shadows bit in CLC1CONbits
6913 #define MODE0 CLC1CONbits.MODE0 // bit 0, shadows bit in CLC1CONbits
6914 #define LC1MODE1 CLC1CONbits.LC1MODE1 // bit 1, shadows bit in CLC1CONbits
6915 #define MODE1 CLC1CONbits.MODE1 // bit 1, shadows bit in CLC1CONbits
6916 #define LC1MODE2 CLC1CONbits.LC1MODE2 // bit 2, shadows bit in CLC1CONbits
6917 #define MODE2 CLC1CONbits.MODE2 // bit 2, shadows bit in CLC1CONbits
6918 #define LC1INTN CLC1CONbits.LC1INTN // bit 3, shadows bit in CLC1CONbits
6919 #define INTN CLC1CONbits.INTN // bit 3, shadows bit in CLC1CONbits
6920 #define LC1INTP CLC1CONbits.LC1INTP // bit 4, shadows bit in CLC1CONbits
6921 #define INTP CLC1CONbits.INTP // bit 4, shadows bit in CLC1CONbits
6922 #define LC1OUT CLC1CONbits.LC1OUT // bit 5, shadows bit in CLC1CONbits
6923 #define OUT CLC1CONbits.OUT // bit 5, shadows bit in CLC1CONbits
6924 #define LC1EN CLC1CONbits.LC1EN // bit 7, shadows bit in CLC1CONbits
6925 #define EN CLC1CONbits.EN // bit 7, shadows bit in CLC1CONbits
6927 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
6928 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
6929 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
6930 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
6931 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
6932 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
6933 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
6934 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
6935 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
6936 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
6937 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
6938 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
6939 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
6940 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
6941 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
6942 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
6944 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
6945 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
6946 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
6947 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
6948 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
6949 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
6950 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
6951 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
6952 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
6953 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
6954 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
6955 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
6956 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
6957 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
6958 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
6959 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
6961 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
6962 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
6963 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
6964 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
6965 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
6966 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
6967 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
6968 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
6969 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
6970 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
6972 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
6973 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
6974 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
6975 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
6976 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
6977 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
6978 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
6979 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
6980 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
6981 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
6983 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
6984 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
6985 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
6986 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
6987 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
6988 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
6989 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
6990 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
6991 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
6992 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
6994 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
6995 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
6996 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
6997 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
6998 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
6999 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
7000 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
7001 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
7002 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
7003 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
7005 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
7006 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
7007 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
7008 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
7009 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
7010 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
7011 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
7012 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
7013 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
7014 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
7016 #define MCLC1OUT CLCDATAbits.MCLC1OUT // bit 0
7017 #define MCLC2OUT CLCDATAbits.MCLC2OUT // bit 1
7018 #define MCLC3OUT CLCDATAbits.MCLC3OUT // bit 2
7020 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
7021 #define C1HYS CM1CON0bits.C1HYS // bit 1
7022 #define C1SP CM1CON0bits.C1SP // bit 2
7023 #define C1ZLF CM1CON0bits.C1ZLF // bit 3
7024 #define C1POL CM1CON0bits.C1POL // bit 4
7025 #define C1OUT CM1CON0bits.C1OUT // bit 6
7026 #define C1ON CM1CON0bits.C1ON // bit 7
7028 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
7029 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
7030 #define C1NCH2 CM1CON1bits.C1NCH2 // bit 2
7031 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 3
7032 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 4
7033 #define C1PCH2 CM1CON1bits.C1PCH2 // bit 5
7034 #define C1INTN CM1CON1bits.C1INTN // bit 6
7035 #define C1INTP CM1CON1bits.C1INTP // bit 7
7037 #define C2SYNC CM2CON0bits.C2SYNC // bit 0
7038 #define C2HYS CM2CON0bits.C2HYS // bit 1
7039 #define C2SP CM2CON0bits.C2SP // bit 2
7040 #define C2ZLF CM2CON0bits.C2ZLF // bit 3
7041 #define C2POL CM2CON0bits.C2POL // bit 4
7042 #define C2OUT CM2CON0bits.C2OUT // bit 6
7043 #define C2ON CM2CON0bits.C2ON // bit 7
7045 #define C2NCH0 CM2CON1bits.C2NCH0 // bit 0
7046 #define C2NCH1 CM2CON1bits.C2NCH1 // bit 1
7047 #define C2NCH2 CM2CON1bits.C2NCH2 // bit 2
7048 #define C2PCH0 CM2CON1bits.C2PCH0 // bit 3
7049 #define C2PCH1 CM2CON1bits.C2PCH1 // bit 4
7050 #define C2PCH2 CM2CON1bits.C2PCH2 // bit 5
7051 #define C2INTN CM2CON1bits.C2INTN // bit 6
7052 #define C2INTP CM2CON1bits.C2INTP // bit 7
7054 #define MC1OUT CMOUTbits.MC1OUT // bit 0
7055 #define MC2OUT CMOUTbits.MC2OUT // bit 1
7057 #define G1ASDAC0 COG1ASD0bits.G1ASDAC0 // bit 2
7058 #define G1ASDAC1 COG1ASD0bits.G1ASDAC1 // bit 3
7059 #define G1ASDBD0 COG1ASD0bits.G1ASDBD0 // bit 4
7060 #define G1ASDBD1 COG1ASD0bits.G1ASDBD1 // bit 5
7061 #define G1ARSEN COG1ASD0bits.G1ARSEN // bit 6
7062 #define G1ASE COG1ASD0bits.G1ASE // bit 7
7064 #define G1AS0E COG1ASD1bits.G1AS0E // bit 0
7065 #define G1AS1E COG1ASD1bits.G1AS1E // bit 1
7066 #define G1AS2E COG1ASD1bits.G1AS2E // bit 2
7067 #define G1AS3E COG1ASD1bits.G1AS3E // bit 3
7069 #define G1BLKF0 COG1BLKFbits.G1BLKF0 // bit 0
7070 #define G1BLKF1 COG1BLKFbits.G1BLKF1 // bit 1
7071 #define G1BLKF2 COG1BLKFbits.G1BLKF2 // bit 2
7072 #define G1BLKF3 COG1BLKFbits.G1BLKF3 // bit 3
7073 #define G1BLKF4 COG1BLKFbits.G1BLKF4 // bit 4
7074 #define G1BLKF5 COG1BLKFbits.G1BLKF5 // bit 5
7076 #define G1BLKR0 COG1BLKRbits.G1BLKR0 // bit 0
7077 #define G1BLKR1 COG1BLKRbits.G1BLKR1 // bit 1
7078 #define G1BLKR2 COG1BLKRbits.G1BLKR2 // bit 2
7079 #define G1BLKR3 COG1BLKRbits.G1BLKR3 // bit 3
7080 #define G1BLKR4 COG1BLKRbits.G1BLKR4 // bit 4
7081 #define G1BLKR5 COG1BLKRbits.G1BLKR5 // bit 5
7083 #define G1MD0 COG1CON0bits.G1MD0 // bit 0
7084 #define G1MD1 COG1CON0bits.G1MD1 // bit 1
7085 #define G1MD2 COG1CON0bits.G1MD2 // bit 2
7086 #define G1CS0 COG1CON0bits.G1CS0 // bit 3
7087 #define G1CS1 COG1CON0bits.G1CS1 // bit 4
7088 #define G1LD COG1CON0bits.G1LD // bit 6
7089 #define G1EN COG1CON0bits.G1EN // bit 7
7091 #define G1POLA COG1CON1bits.G1POLA // bit 0
7092 #define G1POLB COG1CON1bits.G1POLB // bit 1
7093 #define G1POLC COG1CON1bits.G1POLC // bit 2
7094 #define G1POLD COG1CON1bits.G1POLD // bit 3
7095 #define G1FDBS COG1CON1bits.G1FDBS // bit 6
7096 #define G1RDBS COG1CON1bits.G1RDBS // bit 7
7098 #define G1DBF0 COG1DBFbits.G1DBF0 // bit 0
7099 #define G1DBF1 COG1DBFbits.G1DBF1 // bit 1
7100 #define G1DBF2 COG1DBFbits.G1DBF2 // bit 2
7101 #define G1DBF3 COG1DBFbits.G1DBF3 // bit 3
7102 #define G1DBF4 COG1DBFbits.G1DBF4 // bit 4
7103 #define G1DBF5 COG1DBFbits.G1DBF5 // bit 5
7105 #define G1DBR0 COG1DBRbits.G1DBR0 // bit 0
7106 #define G1DBR1 COG1DBRbits.G1DBR1 // bit 1
7107 #define G1DBR2 COG1DBRbits.G1DBR2 // bit 2
7108 #define G1DBR3 COG1DBRbits.G1DBR3 // bit 3
7109 #define G1DBR4 COG1DBRbits.G1DBR4 // bit 4
7110 #define G1DBR5 COG1DBRbits.G1DBR5 // bit 5
7112 #define G1FIS0 COG1FISbits.G1FIS0 // bit 0
7113 #define G1FIS1 COG1FISbits.G1FIS1 // bit 1
7114 #define G1FIS2 COG1FISbits.G1FIS2 // bit 2
7115 #define G1FIS3 COG1FISbits.G1FIS3 // bit 3
7116 #define G1FIS4 COG1FISbits.G1FIS4 // bit 4
7117 #define G1FIS5 COG1FISbits.G1FIS5 // bit 5
7118 #define G1FIS6 COG1FISbits.G1FIS6 // bit 6
7120 #define G1FSIM0 COG1FSIMbits.G1FSIM0 // bit 0
7121 #define G1FSIM1 COG1FSIMbits.G1FSIM1 // bit 1
7122 #define G1FSIM2 COG1FSIMbits.G1FSIM2 // bit 2
7123 #define G1FSIM3 COG1FSIMbits.G1FSIM3 // bit 3
7124 #define G1FSIM4 COG1FSIMbits.G1FSIM4 // bit 4
7125 #define G1FSIM5 COG1FSIMbits.G1FSIM5 // bit 5
7126 #define G1FSIM6 COG1FSIMbits.G1FSIM6 // bit 6
7128 #define G1PHF0 COG1PHFbits.G1PHF0 // bit 0
7129 #define G1PHF1 COG1PHFbits.G1PHF1 // bit 1
7130 #define G1PHF2 COG1PHFbits.G1PHF2 // bit 2
7131 #define G1PHF3 COG1PHFbits.G1PHF3 // bit 3
7132 #define G1PHF4 COG1PHFbits.G1PHF4 // bit 4
7133 #define G1PHF5 COG1PHFbits.G1PHF5 // bit 5
7135 #define G1PHR0 COG1PHRbits.G1PHR0 // bit 0
7136 #define G1PHR1 COG1PHRbits.G1PHR1 // bit 1
7137 #define G1PHR2 COG1PHRbits.G1PHR2 // bit 2
7138 #define G1PHR3 COG1PHRbits.G1PHR3 // bit 3
7139 #define G1PHR4 COG1PHRbits.G1PHR4 // bit 4
7140 #define G1PHR5 COG1PHRbits.G1PHR5 // bit 5
7142 #define G1RIS0 COG1RISbits.G1RIS0 // bit 0
7143 #define G1RIS1 COG1RISbits.G1RIS1 // bit 1
7144 #define G1RIS2 COG1RISbits.G1RIS2 // bit 2
7145 #define G1RIS3 COG1RISbits.G1RIS3 // bit 3
7146 #define G1RIS4 COG1RISbits.G1RIS4 // bit 4
7147 #define G1RIS5 COG1RISbits.G1RIS5 // bit 5
7148 #define G1RIS6 COG1RISbits.G1RIS6 // bit 6
7150 #define G1RSIM0 COG1RSIMbits.G1RSIM0 // bit 0
7151 #define G1RSIM1 COG1RSIMbits.G1RSIM1 // bit 1
7152 #define G1RSIM2 COG1RSIMbits.G1RSIM2 // bit 2
7153 #define G1RSIM3 COG1RSIMbits.G1RSIM3 // bit 3
7154 #define G1RSIM4 COG1RSIMbits.G1RSIM4 // bit 4
7155 #define G1RSIM5 COG1RSIMbits.G1RSIM5 // bit 5
7156 #define G1RSIM6 COG1RSIMbits.G1RSIM6 // bit 6
7158 #define G1STRA COG1STRbits.G1STRA // bit 0
7159 #define G1STRB COG1STRbits.G1STRB // bit 1
7160 #define G1STRC COG1STRbits.G1STRC // bit 2
7161 #define G1STRD COG1STRbits.G1STRD // bit 3
7162 #define G1SDATA COG1STRbits.G1SDATA // bit 4
7163 #define G1SDATB COG1STRbits.G1SDATB // bit 5
7164 #define G1SDATC COG1STRbits.G1SDATC // bit 6
7165 #define G1SDATD COG1STRbits.G1SDATD // bit 7
7167 #define DAC1NSS DAC1CON0bits.DAC1NSS // bit 0, shadows bit in DAC1CON0bits
7168 #define DACNSS DAC1CON0bits.DACNSS // bit 0, shadows bit in DAC1CON0bits
7169 #define DAC1PSS0 DAC1CON0bits.DAC1PSS0 // bit 2, shadows bit in DAC1CON0bits
7170 #define DACPSS0 DAC1CON0bits.DACPSS0 // bit 2, shadows bit in DAC1CON0bits
7171 #define DAC1PSS1 DAC1CON0bits.DAC1PSS1 // bit 3, shadows bit in DAC1CON0bits
7172 #define DACPSS1 DAC1CON0bits.DACPSS1 // bit 3, shadows bit in DAC1CON0bits
7173 #define DAC1OE2 DAC1CON0bits.DAC1OE2 // bit 4, shadows bit in DAC1CON0bits
7174 #define DACOE0 DAC1CON0bits.DACOE0 // bit 4, shadows bit in DAC1CON0bits
7175 #define DAC1OE1 DAC1CON0bits.DAC1OE1 // bit 5, shadows bit in DAC1CON0bits
7176 #define DACOE1 DAC1CON0bits.DACOE1 // bit 5, shadows bit in DAC1CON0bits
7177 #define DAC1EN DAC1CON0bits.DAC1EN // bit 7, shadows bit in DAC1CON0bits
7178 #define DACEN DAC1CON0bits.DACEN // bit 7, shadows bit in DAC1CON0bits
7180 #define DAC1R0 DAC1CON1bits.DAC1R0 // bit 0, shadows bit in DAC1CON1bits
7181 #define DACR0 DAC1CON1bits.DACR0 // bit 0, shadows bit in DAC1CON1bits
7182 #define DAC1R1 DAC1CON1bits.DAC1R1 // bit 1, shadows bit in DAC1CON1bits
7183 #define DACR1 DAC1CON1bits.DACR1 // bit 1, shadows bit in DAC1CON1bits
7184 #define DAC1R2 DAC1CON1bits.DAC1R2 // bit 2, shadows bit in DAC1CON1bits
7185 #define DACR2 DAC1CON1bits.DACR2 // bit 2, shadows bit in DAC1CON1bits
7186 #define DAC1R3 DAC1CON1bits.DAC1R3 // bit 3, shadows bit in DAC1CON1bits
7187 #define DACR3 DAC1CON1bits.DACR3 // bit 3, shadows bit in DAC1CON1bits
7188 #define DAC1R4 DAC1CON1bits.DAC1R4 // bit 4, shadows bit in DAC1CON1bits
7189 #define DACR4 DAC1CON1bits.DACR4 // bit 4, shadows bit in DAC1CON1bits
7190 #define DAC1R5 DAC1CON1bits.DAC1R5 // bit 5, shadows bit in DAC1CON1bits
7191 #define DACR5 DAC1CON1bits.DACR5 // bit 5, shadows bit in DAC1CON1bits
7192 #define DAC1R6 DAC1CON1bits.DAC1R6 // bit 6, shadows bit in DAC1CON1bits
7193 #define DACR6 DAC1CON1bits.DACR6 // bit 6, shadows bit in DAC1CON1bits
7194 #define DAC1R7 DAC1CON1bits.DAC1R7 // bit 7, shadows bit in DAC1CON1bits
7195 #define DACR7 DAC1CON1bits.DACR7 // bit 7, shadows bit in DAC1CON1bits
7197 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
7198 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
7199 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
7200 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
7201 #define TSRNG FVRCONbits.TSRNG // bit 4
7202 #define TSEN FVRCONbits.TSEN // bit 5
7203 #define FVRRDY FVRCONbits.FVRRDY // bit 6
7204 #define FVREN FVRCONbits.FVREN // bit 7
7206 #define BKA8 ICDBK0Hbits.BKA8 // bit 0
7207 #define BKA9 ICDBK0Hbits.BKA9 // bit 1
7208 #define BKA10 ICDBK0Hbits.BKA10 // bit 2
7209 #define BKA11 ICDBK0Hbits.BKA11 // bit 3
7210 #define BKA12 ICDBK0Hbits.BKA12 // bit 4
7211 #define BKA13 ICDBK0Hbits.BKA13 // bit 5
7212 #define BKA14 ICDBK0Hbits.BKA14 // bit 6
7214 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
7215 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
7216 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
7217 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
7218 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
7219 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
7221 #define INLVLB4 INLVLBbits.INLVLB4 // bit 4
7222 #define INLVLB5 INLVLBbits.INLVLB5 // bit 5
7223 #define INLVLB6 INLVLBbits.INLVLB6 // bit 6
7224 #define INLVLB7 INLVLBbits.INLVLB7 // bit 7
7226 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
7227 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
7228 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
7229 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
7230 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
7231 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
7232 #define INLVLC6 INLVLCbits.INLVLC6 // bit 6
7233 #define INLVLC7 INLVLCbits.INLVLC7 // bit 7
7235 #define IOCIF INTCONbits.IOCIF // bit 0
7236 #define INTF INTCONbits.INTF // bit 1
7237 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
7238 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
7239 #define IOCIE INTCONbits.IOCIE // bit 3
7240 #define INTE INTCONbits.INTE // bit 4
7241 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
7242 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
7243 #define PEIE INTCONbits.PEIE // bit 6
7244 #define GIE INTCONbits.GIE // bit 7
7246 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
7247 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
7248 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
7249 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
7250 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
7251 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
7253 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
7254 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
7255 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
7256 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
7257 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
7258 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
7260 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
7261 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
7262 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
7263 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
7264 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
7265 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
7267 #define IOCBF4 IOCBFbits.IOCBF4 // bit 4
7268 #define IOCBF5 IOCBFbits.IOCBF5 // bit 5
7269 #define IOCBF6 IOCBFbits.IOCBF6 // bit 6
7270 #define IOCBF7 IOCBFbits.IOCBF7 // bit 7
7272 #define IOCBN4 IOCBNbits.IOCBN4 // bit 4
7273 #define IOCBN5 IOCBNbits.IOCBN5 // bit 5
7274 #define IOCBN6 IOCBNbits.IOCBN6 // bit 6
7275 #define IOCBN7 IOCBNbits.IOCBN7 // bit 7
7277 #define IOCBP4 IOCBPbits.IOCBP4 // bit 4
7278 #define IOCBP5 IOCBPbits.IOCBP5 // bit 5
7279 #define IOCBP6 IOCBPbits.IOCBP6 // bit 6
7280 #define IOCBP7 IOCBPbits.IOCBP7 // bit 7
7282 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
7283 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
7284 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
7285 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
7286 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
7287 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
7288 #define IOCCF6 IOCCFbits.IOCCF6 // bit 6
7289 #define IOCCF7 IOCCFbits.IOCCF7 // bit 7
7291 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
7292 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
7293 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
7294 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
7295 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
7296 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
7297 #define IOCCN6 IOCCNbits.IOCCN6 // bit 6
7298 #define IOCCN7 IOCCNbits.IOCCN7 // bit 7
7300 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
7301 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
7302 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
7303 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
7304 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
7305 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
7306 #define IOCCP6 IOCCPbits.IOCCP6 // bit 6
7307 #define IOCCP7 IOCCPbits.IOCCP7 // bit 7
7309 #define LATA0 LATAbits.LATA0 // bit 0
7310 #define LATA1 LATAbits.LATA1 // bit 1
7311 #define LATA2 LATAbits.LATA2 // bit 2
7312 #define LATA4 LATAbits.LATA4 // bit 4
7313 #define LATA5 LATAbits.LATA5 // bit 5
7315 #define LATB4 LATBbits.LATB4 // bit 4
7316 #define LATB5 LATBbits.LATB5 // bit 5
7317 #define LATB6 LATBbits.LATB6 // bit 6
7318 #define LATB7 LATBbits.LATB7 // bit 7
7320 #define LATC0 LATCbits.LATC0 // bit 0
7321 #define LATC1 LATCbits.LATC1 // bit 1
7322 #define LATC2 LATCbits.LATC2 // bit 2
7323 #define LATC3 LATCbits.LATC3 // bit 3
7324 #define LATC4 LATCbits.LATC4 // bit 4
7325 #define LATC5 LATCbits.LATC5 // bit 5
7326 #define LATC6 LATCbits.LATC6 // bit 6
7327 #define LATC7 LATCbits.LATC7 // bit 7
7329 #define ODA0 ODCONAbits.ODA0 // bit 0
7330 #define ODA1 ODCONAbits.ODA1 // bit 1
7331 #define ODA2 ODCONAbits.ODA2 // bit 2
7332 #define ODA4 ODCONAbits.ODA4 // bit 4
7333 #define ODA5 ODCONAbits.ODA5 // bit 5
7335 #define ODB4 ODCONBbits.ODB4 // bit 4
7336 #define ODB5 ODCONBbits.ODB5 // bit 5
7337 #define ODB6 ODCONBbits.ODB6 // bit 6
7338 #define ODB7 ODCONBbits.ODB7 // bit 7
7340 #define ODC0 ODCONCbits.ODC0 // bit 0
7341 #define ODC1 ODCONCbits.ODC1 // bit 1
7342 #define ODC2 ODCONCbits.ODC2 // bit 2
7343 #define ODC3 ODCONCbits.ODC3 // bit 3
7344 #define ODC4 ODCONCbits.ODC4 // bit 4
7345 #define ODC5 ODCONCbits.ODC5 // bit 5
7346 #define ODC6 ODCONCbits.ODC6 // bit 6
7347 #define ODC7 ODCONCbits.ODC7 // bit 7
7349 #define OPA1PCH0 OPA1CONbits.OPA1PCH0 // bit 0
7350 #define OPA1PCH1 OPA1CONbits.OPA1PCH1 // bit 1
7351 #define OPA1UG OPA1CONbits.OPA1UG // bit 4
7352 #define OPA1SP OPA1CONbits.OPA1SP // bit 6
7353 #define OPA1EN OPA1CONbits.OPA1EN // bit 7
7355 #define OPA2PCH0 OPA2CONbits.OPA2PCH0 // bit 0
7356 #define OPA2PCH1 OPA2CONbits.OPA2PCH1 // bit 1
7357 #define OPA2UG OPA2CONbits.OPA2UG // bit 4
7358 #define OPA2SP OPA2CONbits.OPA2SP // bit 6
7359 #define OPA2EN OPA2CONbits.OPA2EN // bit 7
7361 #define PS0 OPTION_REGbits.PS0 // bit 0
7362 #define PS1 OPTION_REGbits.PS1 // bit 1
7363 #define PS2 OPTION_REGbits.PS2 // bit 2
7364 #define PSA OPTION_REGbits.PSA // bit 3
7365 #define TMR0SE OPTION_REGbits.TMR0SE // bit 4, shadows bit in OPTION_REGbits
7366 #define T0SE OPTION_REGbits.T0SE // bit 4, shadows bit in OPTION_REGbits
7367 #define TMR0CS OPTION_REGbits.TMR0CS // bit 5, shadows bit in OPTION_REGbits
7368 #define T0CS OPTION_REGbits.T0CS // bit 5, shadows bit in OPTION_REGbits
7369 #define INTEDG OPTION_REGbits.INTEDG // bit 6
7370 #define NOT_WPUEN OPTION_REGbits.NOT_WPUEN // bit 7
7372 #define SCS0 OSCCONbits.SCS0 // bit 0
7373 #define SCS1 OSCCONbits.SCS1 // bit 1
7374 #define IRCF0 OSCCONbits.IRCF0 // bit 3
7375 #define IRCF1 OSCCONbits.IRCF1 // bit 4
7376 #define IRCF2 OSCCONbits.IRCF2 // bit 5
7377 #define IRCF3 OSCCONbits.IRCF3 // bit 6
7378 #define SPLLEN OSCCONbits.SPLLEN // bit 7
7380 #define HFIOFS OSCSTATbits.HFIOFS // bit 0
7381 #define LFIOFR OSCSTATbits.LFIOFR // bit 1
7382 #define MFIOFR OSCSTATbits.MFIOFR // bit 2
7383 #define HFIOFL OSCSTATbits.HFIOFL // bit 3
7384 #define HFIOFR OSCSTATbits.HFIOFR // bit 4
7385 #define OSTS OSCSTATbits.OSTS // bit 5
7386 #define PLLR OSCSTATbits.PLLR // bit 6
7387 #define SOSCR OSCSTATbits.SOSCR // bit 7
7389 #define TUN0 OSCTUNEbits.TUN0 // bit 0
7390 #define TUN1 OSCTUNEbits.TUN1 // bit 1
7391 #define TUN2 OSCTUNEbits.TUN2 // bit 2
7392 #define TUN3 OSCTUNEbits.TUN3 // bit 3
7393 #define TUN4 OSCTUNEbits.TUN4 // bit 4
7394 #define TUN5 OSCTUNEbits.TUN5 // bit 5
7396 #define NOT_BOR PCONbits.NOT_BOR // bit 0
7397 #define NOT_POR PCONbits.NOT_POR // bit 1
7398 #define NOT_RI PCONbits.NOT_RI // bit 2
7399 #define NOT_RMCLR PCONbits.NOT_RMCLR // bit 3
7400 #define NOT_RWDT PCONbits.NOT_RWDT // bit 4
7401 #define STKUNF PCONbits.STKUNF // bit 6
7402 #define STKOVF PCONbits.STKOVF // bit 7
7404 #define TMR1IE PIE1bits.TMR1IE // bit 0
7405 #define TMR2IE PIE1bits.TMR2IE // bit 1
7406 #define CCP1IE PIE1bits.CCP1IE // bit 2, shadows bit in PIE1bits
7407 #define CCPIE PIE1bits.CCPIE // bit 2, shadows bit in PIE1bits
7408 #define SSP1IE PIE1bits.SSP1IE // bit 3
7409 #define TXIE PIE1bits.TXIE // bit 4
7410 #define RCIE PIE1bits.RCIE // bit 5
7411 #define ADIE PIE1bits.ADIE // bit 6
7412 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
7414 #define CCP2IE PIE2bits.CCP2IE // bit 0
7415 #define TMR4IE PIE2bits.TMR4IE // bit 1
7416 #define TMR6IE PIE2bits.TMR6IE // bit 2
7417 #define BCL1IE PIE2bits.BCL1IE // bit 3
7418 #define C1IE PIE2bits.C1IE // bit 5
7419 #define C2IE PIE2bits.C2IE // bit 6
7420 #define OSFIE PIE2bits.OSFIE // bit 7
7422 #define CLC1IE PIE3bits.CLC1IE // bit 0
7423 #define CLC2IE PIE3bits.CLC2IE // bit 1
7424 #define CLC3IE PIE3bits.CLC3IE // bit 2
7425 #define ZCDIE PIE3bits.ZCDIE // bit 4
7426 #define COGIE PIE3bits.COGIE // bit 5
7428 #define TMR1IF PIR1bits.TMR1IF // bit 0
7429 #define TMR2IF PIR1bits.TMR2IF // bit 1
7430 #define CCP1IF PIR1bits.CCP1IF // bit 2, shadows bit in PIR1bits
7431 #define CCPIF PIR1bits.CCPIF // bit 2, shadows bit in PIR1bits
7432 #define SSP1IF PIR1bits.SSP1IF // bit 3
7433 #define TXIF PIR1bits.TXIF // bit 4
7434 #define RCIF PIR1bits.RCIF // bit 5
7435 #define ADIF PIR1bits.ADIF // bit 6
7436 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
7438 #define CCP2IF PIR2bits.CCP2IF // bit 0
7439 #define TMR4IF PIR2bits.TMR4IF // bit 1
7440 #define TMR6IF PIR2bits.TMR6IF // bit 2
7441 #define BCL1IF PIR2bits.BCL1IF // bit 3
7442 #define C1IF PIR2bits.C1IF // bit 5
7443 #define C2IF PIR2bits.C2IF // bit 6
7444 #define OSFIF PIR2bits.OSFIF // bit 7
7446 #define CLC1IF PIR3bits.CLC1IF // bit 0
7447 #define CLC2IF PIR3bits.CLC2IF // bit 1
7448 #define CLC3IF PIR3bits.CLC3IF // bit 2
7449 #define ZCDIF PIR3bits.ZCDIF // bit 4
7450 #define COGIF PIR3bits.COGIF // bit 5
7452 #define RD PMCON1bits.RD // bit 0
7453 #define WR PMCON1bits.WR // bit 1
7454 #define WREN PMCON1bits.WREN // bit 2
7455 #define WRERR PMCON1bits.WRERR // bit 3
7456 #define FREE PMCON1bits.FREE // bit 4
7457 #define LWLO PMCON1bits.LWLO // bit 5
7458 #define CFGS PMCON1bits.CFGS // bit 6
7460 #define RA0 PORTAbits.RA0 // bit 0
7461 #define RA1 PORTAbits.RA1 // bit 1
7462 #define RA2 PORTAbits.RA2 // bit 2
7463 #define RA3 PORTAbits.RA3 // bit 3
7464 #define RA4 PORTAbits.RA4 // bit 4
7465 #define RA5 PORTAbits.RA5 // bit 5
7467 #define RB4 PORTBbits.RB4 // bit 4
7468 #define RB5 PORTBbits.RB5 // bit 5
7469 #define RB6 PORTBbits.RB6 // bit 6
7470 #define RB7 PORTBbits.RB7 // bit 7
7472 #define RC0 PORTCbits.RC0 // bit 0
7473 #define RC1 PORTCbits.RC1 // bit 1
7474 #define RC2 PORTCbits.RC2 // bit 2
7475 #define RC3 PORTCbits.RC3 // bit 3
7476 #define RC4 PORTCbits.RC4 // bit 4
7477 #define RC5 PORTCbits.RC5 // bit 5
7478 #define RC6 PORTCbits.RC6 // bit 6
7479 #define RC7 PORTCbits.RC7 // bit 7
7481 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
7483 #define PWM3POL PWM3CONbits.PWM3POL // bit 4
7484 #define PWM3OUT PWM3CONbits.PWM3OUT // bit 5
7485 #define PWM3EN PWM3CONbits.PWM3EN // bit 7
7487 #define PWM3DCH0 PWM3DCHbits.PWM3DCH0 // bit 0
7488 #define PWM3DCH1 PWM3DCHbits.PWM3DCH1 // bit 1
7489 #define PWM3DCH2 PWM3DCHbits.PWM3DCH2 // bit 2
7490 #define PWM3DCH3 PWM3DCHbits.PWM3DCH3 // bit 3
7491 #define PWM3DCH4 PWM3DCHbits.PWM3DCH4 // bit 4
7492 #define PWM3DCH5 PWM3DCHbits.PWM3DCH5 // bit 5
7493 #define PWM3DCH6 PWM3DCHbits.PWM3DCH6 // bit 6
7494 #define PWM3DCH7 PWM3DCHbits.PWM3DCH7 // bit 7
7496 #define PWM3DCL0 PWM3DCLbits.PWM3DCL0 // bit 6
7497 #define PWM3DCL1 PWM3DCLbits.PWM3DCL1 // bit 7
7499 #define PWM4POL PWM4CONbits.PWM4POL // bit 4
7500 #define PWM4OUT PWM4CONbits.PWM4OUT // bit 5
7501 #define PWM4EN PWM4CONbits.PWM4EN // bit 7
7503 #define PWM4DCH0 PWM4DCHbits.PWM4DCH0 // bit 0
7504 #define PWM4DCH1 PWM4DCHbits.PWM4DCH1 // bit 1
7505 #define PWM4DCH2 PWM4DCHbits.PWM4DCH2 // bit 2
7506 #define PWM4DCH3 PWM4DCHbits.PWM4DCH3 // bit 3
7507 #define PWM4DCH4 PWM4DCHbits.PWM4DCH4 // bit 4
7508 #define PWM4DCH5 PWM4DCHbits.PWM4DCH5 // bit 5
7509 #define PWM4DCH6 PWM4DCHbits.PWM4DCH6 // bit 6
7510 #define PWM4DCH7 PWM4DCHbits.PWM4DCH7 // bit 7
7512 #define PWM4DCL0 PWM4DCLbits.PWM4DCL0 // bit 6
7513 #define PWM4DCL1 PWM4DCLbits.PWM4DCL1 // bit 7
7515 #define RX9D RC1STAbits.RX9D // bit 0
7516 #define OERR RC1STAbits.OERR // bit 1
7517 #define FERR RC1STAbits.FERR // bit 2
7518 #define ADDEN RC1STAbits.ADDEN // bit 3
7519 #define CREN RC1STAbits.CREN // bit 4
7520 #define SREN RC1STAbits.SREN // bit 5
7521 #define RX9 RC1STAbits.RX9 // bit 6
7522 #define SPEN RC1STAbits.SPEN // bit 7
7524 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
7525 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
7526 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
7527 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
7528 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
7530 #define SLRB4 SLRCONBbits.SLRB4 // bit 4
7531 #define SLRB5 SLRCONBbits.SLRB5 // bit 5
7532 #define SLRB6 SLRCONBbits.SLRB6 // bit 6
7533 #define SLRB7 SLRCONBbits.SLRB7 // bit 7
7535 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
7536 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
7537 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
7538 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
7539 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
7540 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
7541 #define SLRC6 SLRCONCbits.SLRC6 // bit 6
7542 #define SLRC7 SLRCONCbits.SLRC7 // bit 7
7544 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
7545 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
7546 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
7547 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
7548 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
7549 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
7550 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
7551 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
7552 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
7553 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
7554 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
7555 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
7556 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
7557 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
7558 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
7559 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
7561 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
7562 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
7563 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
7564 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
7565 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
7566 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
7567 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
7568 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
7569 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
7570 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
7571 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
7572 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
7573 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
7574 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
7575 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
7576 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
7578 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
7579 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
7580 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
7581 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
7582 #define CKP SSP1CONbits.CKP // bit 4
7583 #define SSPEN SSP1CONbits.SSPEN // bit 5
7584 #define SSPOV SSP1CONbits.SSPOV // bit 6
7585 #define WCOL SSP1CONbits.WCOL // bit 7
7587 #define SEN SSP1CON2bits.SEN // bit 0
7588 #define RSEN SSP1CON2bits.RSEN // bit 1
7589 #define PEN SSP1CON2bits.PEN // bit 2
7590 #define RCEN SSP1CON2bits.RCEN // bit 3
7591 #define ACKEN SSP1CON2bits.ACKEN // bit 4
7592 #define ACKDT SSP1CON2bits.ACKDT // bit 5
7593 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
7594 #define GCEN SSP1CON2bits.GCEN // bit 7
7596 #define DHEN SSP1CON3bits.DHEN // bit 0
7597 #define AHEN SSP1CON3bits.AHEN // bit 1
7598 #define SBCDE SSP1CON3bits.SBCDE // bit 2
7599 #define SDAHT SSP1CON3bits.SDAHT // bit 3
7600 #define BOEN SSP1CON3bits.BOEN // bit 4
7601 #define SCIE SSP1CON3bits.SCIE // bit 5
7602 #define PCIE SSP1CON3bits.PCIE // bit 6
7603 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
7605 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
7606 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
7607 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
7608 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
7609 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
7610 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
7611 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
7612 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
7613 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
7614 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
7615 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
7616 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
7617 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
7618 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
7619 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
7620 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
7622 #define BF SSP1STATbits.BF // bit 0
7623 #define UA SSP1STATbits.UA // bit 1
7624 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
7625 #define S SSP1STATbits.S // bit 3
7626 #define P SSP1STATbits.P // bit 4
7627 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
7628 #define CKE SSP1STATbits.CKE // bit 6
7629 #define SMP SSP1STATbits.SMP // bit 7
7631 #define C STATUSbits.C // bit 0
7632 #define DC STATUSbits.DC // bit 1
7633 #define Z STATUSbits.Z // bit 2
7634 #define NOT_PD STATUSbits.NOT_PD // bit 3
7635 #define NOT_TO STATUSbits.NOT_TO // bit 4
7637 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
7638 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
7639 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
7641 #define TMR1ON T1CONbits.TMR1ON // bit 0
7642 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
7643 #define T1OSCEN T1CONbits.T1OSCEN // bit 3
7644 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
7645 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
7646 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
7647 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
7649 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
7650 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
7651 #define T1GVAL T1GCONbits.T1GVAL // bit 2
7652 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3
7653 #define T1GSPM T1GCONbits.T1GSPM // bit 4
7654 #define T1GTM T1GCONbits.T1GTM // bit 5
7655 #define T1GPOL T1GCONbits.T1GPOL // bit 6
7656 #define TMR1GE T1GCONbits.TMR1GE // bit 7
7658 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
7659 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
7660 #define TMR2ON T2CONbits.TMR2ON // bit 2
7661 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
7662 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
7663 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
7664 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
7666 #define T4CKPS0 T4CONbits.T4CKPS0 // bit 0
7667 #define T4CKPS1 T4CONbits.T4CKPS1 // bit 1
7668 #define TMR4ON T4CONbits.TMR4ON // bit 2
7669 #define T4OUTPS0 T4CONbits.T4OUTPS0 // bit 3
7670 #define T4OUTPS1 T4CONbits.T4OUTPS1 // bit 4
7671 #define T4OUTPS2 T4CONbits.T4OUTPS2 // bit 5
7672 #define T4OUTPS3 T4CONbits.T4OUTPS3 // bit 6
7674 #define T6CKPS0 T6CONbits.T6CKPS0 // bit 0
7675 #define T6CKPS1 T6CONbits.T6CKPS1 // bit 1
7676 #define TMR6ON T6CONbits.TMR6ON // bit 2
7677 #define T6OUTPS0 T6CONbits.T6OUTPS0 // bit 3
7678 #define T6OUTPS1 T6CONbits.T6OUTPS1 // bit 4
7679 #define T6OUTPS2 T6CONbits.T6OUTPS2 // bit 5
7680 #define T6OUTPS3 T6CONbits.T6OUTPS3 // bit 6
7682 #define TRISA0 TRISAbits.TRISA0 // bit 0
7683 #define TRISA1 TRISAbits.TRISA1 // bit 1
7684 #define TRISA2 TRISAbits.TRISA2 // bit 2
7685 #define TRISA4 TRISAbits.TRISA4 // bit 4
7686 #define TRISA5 TRISAbits.TRISA5 // bit 5
7688 #define TRISB4 TRISBbits.TRISB4 // bit 4
7689 #define TRISB5 TRISBbits.TRISB5 // bit 5
7690 #define TRISB6 TRISBbits.TRISB6 // bit 6
7691 #define TRISB7 TRISBbits.TRISB7 // bit 7
7693 #define TRISC0 TRISCbits.TRISC0 // bit 0
7694 #define TRISC1 TRISCbits.TRISC1 // bit 1
7695 #define TRISC2 TRISCbits.TRISC2 // bit 2
7696 #define TRISC3 TRISCbits.TRISC3 // bit 3
7697 #define TRISC4 TRISCbits.TRISC4 // bit 4
7698 #define TRISC5 TRISCbits.TRISC5 // bit 5
7699 #define TRISC6 TRISCbits.TRISC6 // bit 6
7700 #define TRISC7 TRISCbits.TRISC7 // bit 7
7702 #define TX9D TX1STAbits.TX9D // bit 0
7703 #define TRMT TX1STAbits.TRMT // bit 1
7704 #define BRGH TX1STAbits.BRGH // bit 2
7705 #define SENDB TX1STAbits.SENDB // bit 3
7706 #define SYNC TX1STAbits.SYNC // bit 4
7707 #define TXEN TX1STAbits.TXEN // bit 5
7708 #define TX9 TX1STAbits.TX9 // bit 6
7709 #define CSRC TX1STAbits.CSRC // bit 7
7711 #define Reserved VREGCONbits.Reserved // bit 0
7712 #define VREGPM VREGCONbits.VREGPM // bit 1
7714 #define SWDTEN WDTCONbits.SWDTEN // bit 0
7715 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
7716 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
7717 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
7718 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
7719 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
7721 #define WPUA0 WPUAbits.WPUA0 // bit 0
7722 #define WPUA1 WPUAbits.WPUA1 // bit 1
7723 #define WPUA2 WPUAbits.WPUA2 // bit 2
7724 #define WPUA3 WPUAbits.WPUA3 // bit 3
7725 #define WPUA4 WPUAbits.WPUA4 // bit 4
7726 #define WPUA5 WPUAbits.WPUA5 // bit 5
7728 #define WPUB4 WPUBbits.WPUB4 // bit 4
7729 #define WPUB5 WPUBbits.WPUB5 // bit 5
7730 #define WPUB6 WPUBbits.WPUB6 // bit 6
7731 #define WPUB7 WPUBbits.WPUB7 // bit 7
7733 #define WPUC0 WPUCbits.WPUC0 // bit 0
7734 #define WPUC1 WPUCbits.WPUC1 // bit 1
7735 #define WPUC2 WPUCbits.WPUC2 // bit 2
7736 #define WPUC3 WPUCbits.WPUC3 // bit 3
7737 #define WPUC4 WPUCbits.WPUC4 // bit 4
7738 #define WPUC5 WPUCbits.WPUC5 // bit 5
7739 #define WPUC6 WPUCbits.WPUC6 // bit 6
7740 #define WPUC7 WPUCbits.WPUC7 // bit 7
7742 #define ZCD1INTN ZCD1CONbits.ZCD1INTN // bit 0
7743 #define ZCD1INTP ZCD1CONbits.ZCD1INTP // bit 1
7744 #define ZCD1POL ZCD1CONbits.ZCD1POL // bit 4
7745 #define ZCD1OUT ZCD1CONbits.ZCD1OUT // bit 5
7746 #define ZCD1EN ZCD1CONbits.ZCD1EN // bit 7
7748 #endif // #ifndef NO_BIT_DEFINES
7750 #endif // #ifndef __PIC16F1709_H__