2 * This declarations of the PIC16F1765 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:13 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F1765_H__
26 #define __PIC16F1765_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTC_ADDR 0x000E
52 #define PIR1_ADDR 0x0011
53 #define PIR2_ADDR 0x0012
54 #define PIR3_ADDR 0x0013
55 #define PIR4_ADDR 0x0014
56 #define TMR0_ADDR 0x0015
57 #define TMR1_ADDR 0x0016
58 #define TMR1L_ADDR 0x0016
59 #define TMR1H_ADDR 0x0017
60 #define T1CON_ADDR 0x0018
61 #define T1GCON_ADDR 0x0019
62 #define T2TMR_ADDR 0x001A
63 #define TMR2_ADDR 0x001A
64 #define PR2_ADDR 0x001B
65 #define T2PR_ADDR 0x001B
66 #define T2CON_ADDR 0x001C
67 #define T2HLT_ADDR 0x001D
68 #define T2CLKCON_ADDR 0x001E
69 #define T2RST_ADDR 0x001F
70 #define TRISA_ADDR 0x008C
71 #define TRISC_ADDR 0x008E
72 #define PIE1_ADDR 0x0091
73 #define PIE2_ADDR 0x0092
74 #define PIE3_ADDR 0x0093
75 #define PIE4_ADDR 0x0094
76 #define OPTION_REG_ADDR 0x0095
77 #define PCON_ADDR 0x0096
78 #define WDTCON_ADDR 0x0097
79 #define OSCTUNE_ADDR 0x0098
80 #define OSCCON_ADDR 0x0099
81 #define OSCSTAT_ADDR 0x009A
82 #define ADRES_ADDR 0x009B
83 #define ADRESL_ADDR 0x009B
84 #define ADRESH_ADDR 0x009C
85 #define ADCON0_ADDR 0x009D
86 #define ADCON1_ADDR 0x009E
87 #define ADCON2_ADDR 0x009F
88 #define LATA_ADDR 0x010C
89 #define LATC_ADDR 0x010E
90 #define CMOUT_ADDR 0x010F
91 #define CM1CON0_ADDR 0x0110
92 #define CM1CON1_ADDR 0x0111
93 #define CM1NSEL_ADDR 0x0112
94 #define CM1PSEL_ADDR 0x0113
95 #define CM2CON0_ADDR 0x0114
96 #define CM2CON1_ADDR 0x0115
97 #define CM2NSEL_ADDR 0x0116
98 #define CM2PSEL_ADDR 0x0117
99 #define ANSELA_ADDR 0x018C
100 #define ANSELC_ADDR 0x018E
101 #define PMADR_ADDR 0x0191
102 #define PMADRL_ADDR 0x0191
103 #define PMADRH_ADDR 0x0192
104 #define PMDAT_ADDR 0x0193
105 #define PMDATL_ADDR 0x0193
106 #define PMDATH_ADDR 0x0194
107 #define PMCON1_ADDR 0x0195
108 #define PMCON2_ADDR 0x0196
109 #define VREGCON_ADDR 0x0197
110 #define RC1REG_ADDR 0x0199
111 #define RCREG_ADDR 0x0199
112 #define RCREG1_ADDR 0x0199
113 #define TX1REG_ADDR 0x019A
114 #define TXREG_ADDR 0x019A
115 #define TXREG1_ADDR 0x019A
116 #define SP1BRG_ADDR 0x019B
117 #define SP1BRGL_ADDR 0x019B
118 #define SPBRG_ADDR 0x019B
119 #define SPBRG1_ADDR 0x019B
120 #define SPBRGL_ADDR 0x019B
121 #define SP1BRGH_ADDR 0x019C
122 #define SPBRGH_ADDR 0x019C
123 #define SPBRGH1_ADDR 0x019C
124 #define RC1STA_ADDR 0x019D
125 #define RCSTA_ADDR 0x019D
126 #define RCSTA1_ADDR 0x019D
127 #define TX1STA_ADDR 0x019E
128 #define TXSTA_ADDR 0x019E
129 #define TXSTA1_ADDR 0x019E
130 #define BAUD1CON_ADDR 0x019F
131 #define BAUDCON_ADDR 0x019F
132 #define BAUDCON1_ADDR 0x019F
133 #define BAUDCTL_ADDR 0x019F
134 #define BAUDCTL1_ADDR 0x019F
135 #define WPUA_ADDR 0x020C
136 #define WPUC_ADDR 0x020E
137 #define SSP1BUF_ADDR 0x0211
138 #define SSPBUF_ADDR 0x0211
139 #define SSP1ADD_ADDR 0x0212
140 #define SSPADD_ADDR 0x0212
141 #define SSP1MSK_ADDR 0x0213
142 #define SSPMSK_ADDR 0x0213
143 #define SSP1STAT_ADDR 0x0214
144 #define SSPSTAT_ADDR 0x0214
145 #define SSP1CON_ADDR 0x0215
146 #define SSP1CON1_ADDR 0x0215
147 #define SSPCON_ADDR 0x0215
148 #define SSPCON1_ADDR 0x0215
149 #define SSP1CON2_ADDR 0x0216
150 #define SSPCON2_ADDR 0x0216
151 #define SSP1CON3_ADDR 0x0217
152 #define SSPCON3_ADDR 0x0217
153 #define BORCON_ADDR 0x021D
154 #define FVRCON_ADDR 0x021E
155 #define ZCD1CON_ADDR 0x021F
156 #define ODCONA_ADDR 0x028C
157 #define ODCONC_ADDR 0x028E
158 #define CCPR1_ADDR 0x0291
159 #define CCPR1L_ADDR 0x0291
160 #define CCPR1H_ADDR 0x0292
161 #define CCP1CON_ADDR 0x0293
162 #define CCP1CAP_ADDR 0x0294
163 #define CCPTMRS_ADDR 0x029E
164 #define SLRCONA_ADDR 0x030C
165 #define SLRCONC_ADDR 0x030E
166 #define INLVLA_ADDR 0x038C
167 #define INLVLC_ADDR 0x038E
168 #define IOCAP_ADDR 0x0391
169 #define IOCAN_ADDR 0x0392
170 #define IOCAF_ADDR 0x0393
171 #define IOCCP_ADDR 0x0397
172 #define IOCCN_ADDR 0x0398
173 #define IOCCF_ADDR 0x0399
174 #define MD1CON0_ADDR 0x039B
175 #define MD1CON1_ADDR 0x039C
176 #define MD1SRC_ADDR 0x039D
177 #define MD1CARL_ADDR 0x039E
178 #define MD1CARH_ADDR 0x039F
179 #define HIDRVC_ADDR 0x040E
180 #define T4TMR_ADDR 0x0413
181 #define TMR4_ADDR 0x0413
182 #define PR4_ADDR 0x0414
183 #define T4PR_ADDR 0x0414
184 #define T4CON_ADDR 0x0415
185 #define T4HLT_ADDR 0x0416
186 #define T4CLKCON_ADDR 0x0417
187 #define T4RST_ADDR 0x0418
188 #define T6TMR_ADDR 0x041A
189 #define TMR6_ADDR 0x041A
190 #define PR6_ADDR 0x041B
191 #define T6PR_ADDR 0x041B
192 #define T6CON_ADDR 0x041C
193 #define T6HLT_ADDR 0x041D
194 #define T6CLKCON_ADDR 0x041E
195 #define T6RST_ADDR 0x041F
196 #define TMR3_ADDR 0x0493
197 #define TMR3L_ADDR 0x0493
198 #define TMR3H_ADDR 0x0494
199 #define T3CON_ADDR 0x0495
200 #define T3GCON_ADDR 0x0496
201 #define TMR5_ADDR 0x049A
202 #define TMR5L_ADDR 0x049A
203 #define TMR5H_ADDR 0x049B
204 #define T5CON_ADDR 0x049C
205 #define T5GCON_ADDR 0x049D
206 #define OPA1NCHS_ADDR 0x050F
207 #define OPA1PCHS_ADDR 0x0510
208 #define OPA1CON_ADDR 0x0511
209 #define OPA1ORS_ADDR 0x0512
210 #define DACLD_ADDR 0x0590
211 #define DAC1CON0_ADDR 0x0591
212 #define DAC1CON1_ADDR 0x0592
213 #define DAC1REF_ADDR 0x0592
214 #define DAC1REFL_ADDR 0x0592
215 #define DAC1CON2_ADDR 0x0593
216 #define DAC1REFH_ADDR 0x0593
217 #define DAC3CON0_ADDR 0x0597
218 #define DAC3CON1_ADDR 0x0598
219 #define DAC3REF_ADDR 0x0598
220 #define PWM3DCL_ADDR 0x0617
221 #define PWM3DCH_ADDR 0x0618
222 #define PWM3CON_ADDR 0x0619
223 #define COG1PHR_ADDR 0x068D
224 #define COG1PHF_ADDR 0x068E
225 #define COG1BLKR_ADDR 0x068F
226 #define COG1BLKF_ADDR 0x0690
227 #define COG1DBR_ADDR 0x0691
228 #define COG1DBF_ADDR 0x0692
229 #define COG1CON0_ADDR 0x0693
230 #define COG1CON1_ADDR 0x0694
231 #define COG1RIS0_ADDR 0x0695
232 #define COG1RIS1_ADDR 0x0696
233 #define COG1RSIM0_ADDR 0x0697
234 #define COG1RSIM1_ADDR 0x0698
235 #define COG1FIS0_ADDR 0x0699
236 #define COG1FIS1_ADDR 0x069A
237 #define COG1FSIM0_ADDR 0x069B
238 #define COG1FSIM1_ADDR 0x069C
239 #define COG1ASD0_ADDR 0x069D
240 #define COG1ASD1_ADDR 0x069E
241 #define COG1STR_ADDR 0x069F
242 #define PRG1RTSS_ADDR 0x0794
243 #define PRG1FTSS_ADDR 0x0795
244 #define PRG1INS_ADDR 0x0796
245 #define PRG1CON0_ADDR 0x0797
246 #define PRG1CON1_ADDR 0x0798
247 #define PRG1CON2_ADDR 0x0799
248 #define PWMEN_ADDR 0x0D8E
249 #define PWMLD_ADDR 0x0D8F
250 #define PWMOUT_ADDR 0x0D90
251 #define PWM5PH_ADDR 0x0D91
252 #define PWM5PHL_ADDR 0x0D91
253 #define PWM5PHH_ADDR 0x0D92
254 #define PWM5DC_ADDR 0x0D93
255 #define PWM5DCL_ADDR 0x0D93
256 #define PWM5DCH_ADDR 0x0D94
257 #define PWM5PR_ADDR 0x0D95
258 #define PWM5PRL_ADDR 0x0D95
259 #define PWM5PRH_ADDR 0x0D96
260 #define PWM5OF_ADDR 0x0D97
261 #define PWM5OFL_ADDR 0x0D97
262 #define PWM5OFH_ADDR 0x0D98
263 #define PWM5TMR_ADDR 0x0D99
264 #define PWM5TMRL_ADDR 0x0D99
265 #define PWM5TMRH_ADDR 0x0D9A
266 #define PWM5CON_ADDR 0x0D9B
267 #define PWM5INTCON_ADDR 0x0D9C
268 #define PWM5INTE_ADDR 0x0D9C
269 #define PWM5INTF_ADDR 0x0D9D
270 #define PWM5INTFLG_ADDR 0x0D9D
271 #define PWM5CLKCON_ADDR 0x0D9E
272 #define PWM5LDCON_ADDR 0x0D9F
273 #define PWM5OFCON_ADDR 0x0DA0
274 #define PPSLOCK_ADDR 0x0E0F
275 #define INTPPS_ADDR 0x0E10
276 #define T0CKIPPS_ADDR 0x0E11
277 #define T1CKIPPS_ADDR 0x0E12
278 #define T1GPPS_ADDR 0x0E13
279 #define CCP1PPS_ADDR 0x0E14
280 #define COG1INPPS_ADDR 0x0E16
281 #define T2CKIPPS_ADDR 0x0E19
282 #define T3CKIPPS_ADDR 0x0E1A
283 #define T3GPPS_ADDR 0x0E1B
284 #define T4CKIPPS_ADDR 0x0E1C
285 #define T5CKIPPS_ADDR 0x0E1D
286 #define T5GPPS_ADDR 0x0E1E
287 #define T6CKIPPS_ADDR 0x0E1F
288 #define SSPCLKPPS_ADDR 0x0E20
289 #define SSPDATPPS_ADDR 0x0E21
290 #define SSPSSPPS_ADDR 0x0E22
291 #define RXPPS_ADDR 0x0E24
292 #define CKPPS_ADDR 0x0E25
293 #define CLCIN0PPS_ADDR 0x0E28
294 #define CLCIN1PPS_ADDR 0x0E29
295 #define CLCIN2PPS_ADDR 0x0E2A
296 #define CLCIN3PPS_ADDR 0x0E2B
297 #define PRG1RPPS_ADDR 0x0E2C
298 #define PRG1FPPS_ADDR 0x0E2D
299 #define MD1CHPPS_ADDR 0x0E30
300 #define MD1CLPPS_ADDR 0x0E31
301 #define MD1MODPPS_ADDR 0x0E32
302 #define RA0PPS_ADDR 0x0E90
303 #define RA1PPS_ADDR 0x0E91
304 #define RA2PPS_ADDR 0x0E92
305 #define RA4PPS_ADDR 0x0E94
306 #define RA5PPS_ADDR 0x0E95
307 #define RC0PPS_ADDR 0x0EA0
308 #define RC1PPS_ADDR 0x0EA1
309 #define RC2PPS_ADDR 0x0EA2
310 #define RC3PPS_ADDR 0x0EA3
311 #define RC4PPS_ADDR 0x0EA4
312 #define RC5PPS_ADDR 0x0EA5
313 #define CLCDATA_ADDR 0x0F0F
314 #define CLC1CON_ADDR 0x0F10
315 #define CLC1POL_ADDR 0x0F11
316 #define CLC1SEL0_ADDR 0x0F12
317 #define CLC1SEL1_ADDR 0x0F13
318 #define CLC1SEL2_ADDR 0x0F14
319 #define CLC1SEL3_ADDR 0x0F15
320 #define CLC1GLS0_ADDR 0x0F16
321 #define CLC1GLS1_ADDR 0x0F17
322 #define CLC1GLS2_ADDR 0x0F18
323 #define CLC1GLS3_ADDR 0x0F19
324 #define CLC2CON_ADDR 0x0F1A
325 #define CLC2POL_ADDR 0x0F1B
326 #define CLC2SEL0_ADDR 0x0F1C
327 #define CLC2SEL1_ADDR 0x0F1D
328 #define CLC2SEL2_ADDR 0x0F1E
329 #define CLC2SEL3_ADDR 0x0F1F
330 #define CLC2GLS0_ADDR 0x0F20
331 #define CLC2GLS1_ADDR 0x0F21
332 #define CLC2GLS2_ADDR 0x0F22
333 #define CLC2GLS3_ADDR 0x0F23
334 #define CLC3CON_ADDR 0x0F24
335 #define CLC3POL_ADDR 0x0F25
336 #define CLC3SEL0_ADDR 0x0F26
337 #define CLC3SEL1_ADDR 0x0F27
338 #define CLC3SEL2_ADDR 0x0F28
339 #define CLC3SEL3_ADDR 0x0F29
340 #define CLC3GLS0_ADDR 0x0F2A
341 #define CLC3GLS1_ADDR 0x0F2B
342 #define CLC3GLS2_ADDR 0x0F2C
343 #define CLC3GLS3_ADDR 0x0F2D
344 #define STATUS_SHAD_ADDR 0x0FE4
345 #define WREG_SHAD_ADDR 0x0FE5
346 #define BSR_SHAD_ADDR 0x0FE6
347 #define PCLATH_SHAD_ADDR 0x0FE7
348 #define FSR0L_SHAD_ADDR 0x0FE8
349 #define FSR0H_SHAD_ADDR 0x0FE9
350 #define FSR1L_SHAD_ADDR 0x0FEA
351 #define FSR1H_SHAD_ADDR 0x0FEB
352 #define STKPTR_ADDR 0x0FED
353 #define TOSL_ADDR 0x0FEE
354 #define TOSH_ADDR 0x0FEF
356 #endif // #ifndef NO_ADDR_DEFINES
358 //==============================================================================
360 // Register Definitions
362 //==============================================================================
364 extern __at(0x0000) __sfr INDF0
;
365 extern __at(0x0001) __sfr INDF1
;
366 extern __at(0x0002) __sfr PCL
;
368 //==============================================================================
371 extern __at(0x0003) __sfr STATUS
;
385 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
393 //==============================================================================
395 extern __at(0x0004) __sfr FSR0
;
396 extern __at(0x0004) __sfr FSR0L
;
397 extern __at(0x0005) __sfr FSR0H
;
398 extern __at(0x0006) __sfr FSR1
;
399 extern __at(0x0006) __sfr FSR1L
;
400 extern __at(0x0007) __sfr FSR1H
;
402 //==============================================================================
405 extern __at(0x0008) __sfr BSR
;
428 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
436 //==============================================================================
438 extern __at(0x0009) __sfr WREG
;
439 extern __at(0x000A) __sfr PCLATH
;
441 //==============================================================================
444 extern __at(0x000B) __sfr INTCON
;
473 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
486 //==============================================================================
489 //==============================================================================
492 extern __at(0x000C) __sfr PORTA
;
515 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
524 //==============================================================================
527 //==============================================================================
530 extern __at(0x000E) __sfr PORTC
;
553 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
562 //==============================================================================
565 //==============================================================================
568 extern __at(0x0011) __sfr PIR1
;
581 unsigned TMR1GIF
: 1;
597 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
607 #define _TMR1GIF 0x80
609 //==============================================================================
612 //==============================================================================
615 extern __at(0x0012) __sfr PIR2
;
629 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
636 //==============================================================================
639 //==============================================================================
642 extern __at(0x0013) __sfr PIR3
;
656 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
665 //==============================================================================
668 //==============================================================================
671 extern __at(0x0014) __sfr PIR4
;
678 unsigned TMR3GIF
: 1;
680 unsigned TMR5GIF
: 1;
685 extern __at(0x0014) volatile __PIR4bits_t PIR4bits
;
690 #define _TMR3GIF 0x08
692 #define _TMR5GIF 0x20
694 //==============================================================================
696 extern __at(0x0015) __sfr TMR0
;
697 extern __at(0x0016) __sfr TMR1
;
698 extern __at(0x0016) __sfr TMR1L
;
699 extern __at(0x0017) __sfr TMR1H
;
701 //==============================================================================
704 extern __at(0x0018) __sfr T1CON
;
712 unsigned NOT_SYNC
: 1;
726 unsigned T1CKPS0
: 1;
727 unsigned T1CKPS1
: 1;
736 unsigned NOT_T1SYNC
: 1;
737 unsigned T1OSCEN
: 1;
740 unsigned TMR1CS0
: 1;
741 unsigned TMR1CS1
: 1;
789 extern __at(0x0018) volatile __T1CONbits_t T1CONbits
;
791 #define _T1CON_ON 0x01
792 #define _T1CON_TMRON 0x01
793 #define _T1CON_TMR1ON 0x01
794 #define _T1CON_T1ON 0x01
795 #define _T1CON_NOT_SYNC 0x04
796 #define _T1CON_SYNC 0x04
797 #define _T1CON_NOT_T1SYNC 0x04
798 #define _T1CON_OSCEN 0x08
799 #define _T1CON_SOSCEN 0x08
800 #define _T1CON_T1OSCEN 0x08
801 #define _T1CON_CKPS0 0x10
802 #define _T1CON_T1CKPS0 0x10
803 #define _T1CON_CKPS1 0x20
804 #define _T1CON_T1CKPS1 0x20
805 #define _T1CON_CS0 0x40
806 #define _T1CON_T1CS0 0x40
807 #define _T1CON_TMR1CS0 0x40
808 #define _T1CON_CS1 0x80
809 #define _T1CON_T1CS1 0x80
810 #define _T1CON_TMR1CS1 0x80
812 //==============================================================================
815 //==============================================================================
818 extern __at(0x0019) __sfr T1GCON
;
827 unsigned GGO_NOT_DONE
: 1;
839 unsigned T1GGO_NOT_DONE
: 1;
871 extern __at(0x0019) volatile __T1GCONbits_t T1GCONbits
;
879 #define _GGO_NOT_DONE 0x08
880 #define _T1GGO_NOT_DONE 0x08
891 //==============================================================================
893 extern __at(0x001A) __sfr T2TMR
;
894 extern __at(0x001A) __sfr TMR2
;
895 extern __at(0x001B) __sfr PR2
;
896 extern __at(0x001B) __sfr T2PR
;
898 //==============================================================================
901 extern __at(0x001C) __sfr T2CON
;
919 unsigned T2OUTPS0
: 1;
920 unsigned T2OUTPS1
: 1;
921 unsigned T2OUTPS2
: 1;
922 unsigned T2OUTPS3
: 1;
923 unsigned T2CKPS0
: 1;
924 unsigned T2CKPS1
: 1;
925 unsigned T2CKPS2
: 1;
943 unsigned T2OUTPS
: 4;
968 extern __at(0x001C) volatile __T2CONbits_t T2CONbits
;
970 #define _T2CON_OUTPS0 0x01
971 #define _T2CON_T2OUTPS0 0x01
972 #define _T2CON_OUTPS1 0x02
973 #define _T2CON_T2OUTPS1 0x02
974 #define _T2CON_OUTPS2 0x04
975 #define _T2CON_T2OUTPS2 0x04
976 #define _T2CON_OUTPS3 0x08
977 #define _T2CON_T2OUTPS3 0x08
978 #define _T2CON_CKPS0 0x10
979 #define _T2CON_T2CKPS0 0x10
980 #define _T2CON_CKPS1 0x20
981 #define _T2CON_T2CKPS1 0x20
982 #define _T2CON_CKPS2 0x40
983 #define _T2CON_T2CKPS2 0x40
984 #define _T2CON_ON 0x80
985 #define _T2CON_T2ON 0x80
986 #define _T2CON_TMR2ON 0x80
988 //==============================================================================
991 //==============================================================================
994 extern __at(0x001D) __sfr T2HLT
;
1005 unsigned CKSYNC
: 1;
1012 unsigned T2MODE0
: 1;
1013 unsigned T2MODE1
: 1;
1014 unsigned T2MODE2
: 1;
1015 unsigned T2MODE3
: 1;
1016 unsigned T2MODE4
: 1;
1017 unsigned T2CKSYNC
: 1;
1018 unsigned T2CKPOL
: 1;
1019 unsigned T2PSYNC
: 1;
1030 unsigned T2MODE
: 5;
1035 extern __at(0x001D) volatile __T2HLTbits_t T2HLTbits
;
1037 #define _T2HLT_MODE0 0x01
1038 #define _T2HLT_T2MODE0 0x01
1039 #define _T2HLT_MODE1 0x02
1040 #define _T2HLT_T2MODE1 0x02
1041 #define _T2HLT_MODE2 0x04
1042 #define _T2HLT_T2MODE2 0x04
1043 #define _T2HLT_MODE3 0x08
1044 #define _T2HLT_T2MODE3 0x08
1045 #define _T2HLT_MODE4 0x10
1046 #define _T2HLT_T2MODE4 0x10
1047 #define _T2HLT_CKSYNC 0x20
1048 #define _T2HLT_T2CKSYNC 0x20
1049 #define _T2HLT_CKPOL 0x40
1050 #define _T2HLT_T2CKPOL 0x40
1051 #define _T2HLT_PSYNC 0x80
1052 #define _T2HLT_T2PSYNC 0x80
1054 //==============================================================================
1057 //==============================================================================
1060 extern __at(0x001E) __sfr T2CLKCON
;
1101 extern __at(0x001E) volatile __T2CLKCONbits_t T2CLKCONbits
;
1103 #define _T2CLKCON_CS0 0x01
1104 #define _T2CLKCON_T2CS0 0x01
1105 #define _T2CLKCON_CS1 0x02
1106 #define _T2CLKCON_T2CS1 0x02
1107 #define _T2CLKCON_CS2 0x04
1108 #define _T2CLKCON_T2CS2 0x04
1109 #define _T2CLKCON_CS3 0x08
1110 #define _T2CLKCON_T2CS3 0x08
1112 //==============================================================================
1115 //==============================================================================
1118 extern __at(0x001F) __sfr T2RST
;
1136 unsigned T2RSEL0
: 1;
1137 unsigned T2RSEL1
: 1;
1138 unsigned T2RSEL2
: 1;
1139 unsigned T2RSEL3
: 1;
1148 unsigned T2RSEL
: 4;
1159 extern __at(0x001F) volatile __T2RSTbits_t T2RSTbits
;
1162 #define _T2RSEL0 0x01
1164 #define _T2RSEL1 0x02
1166 #define _T2RSEL2 0x04
1168 #define _T2RSEL3 0x08
1170 //==============================================================================
1173 //==============================================================================
1176 extern __at(0x008C) __sfr TRISA
;
1180 unsigned TRISA0
: 1;
1181 unsigned TRISA1
: 1;
1182 unsigned TRISA2
: 1;
1184 unsigned TRISA4
: 1;
1185 unsigned TRISA5
: 1;
1190 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
1192 #define _TRISA0 0x01
1193 #define _TRISA1 0x02
1194 #define _TRISA2 0x04
1195 #define _TRISA4 0x10
1196 #define _TRISA5 0x20
1198 //==============================================================================
1201 //==============================================================================
1204 extern __at(0x008E) __sfr TRISC
;
1210 unsigned TRISC0
: 1;
1211 unsigned TRISC1
: 1;
1212 unsigned TRISC2
: 1;
1213 unsigned TRISC3
: 1;
1214 unsigned TRISC4
: 1;
1215 unsigned TRISC5
: 1;
1227 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
1229 #define _TRISC0 0x01
1230 #define _TRISC1 0x02
1231 #define _TRISC2 0x04
1232 #define _TRISC3 0x08
1233 #define _TRISC4 0x10
1234 #define _TRISC5 0x20
1236 //==============================================================================
1239 //==============================================================================
1242 extern __at(0x0091) __sfr PIE1
;
1248 unsigned TMR1IE
: 1;
1249 unsigned TMR2IE
: 1;
1250 unsigned CCP1IE
: 1;
1251 unsigned SSP1IE
: 1;
1255 unsigned TMR1GIE
: 1;
1271 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
1273 #define _TMR1IE 0x01
1274 #define _TMR2IE 0x02
1275 #define _CCP1IE 0x04
1277 #define _SSP1IE 0x08
1281 #define _TMR1GIE 0x80
1283 //==============================================================================
1286 //==============================================================================
1289 extern __at(0x0092) __sfr PIE2
;
1296 unsigned BCL1IE
: 1;
1303 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
1305 #define _BCL1IE 0x08
1310 //==============================================================================
1313 //==============================================================================
1316 extern __at(0x0093) __sfr PIE3
;
1320 unsigned CLC1IE
: 1;
1321 unsigned CLC2IE
: 1;
1322 unsigned CLC3IE
: 1;
1326 unsigned PWM5IE
: 1;
1330 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
1332 #define _CLC1IE 0x01
1333 #define _CLC2IE 0x02
1334 #define _CLC3IE 0x04
1337 #define _PWM5IE 0x40
1339 //==============================================================================
1342 //==============================================================================
1345 extern __at(0x0094) __sfr PIE4
;
1349 unsigned TMR4IE
: 1;
1350 unsigned TMR6IE
: 1;
1351 unsigned TMR3IE
: 1;
1352 unsigned TMR3GIE
: 1;
1353 unsigned TMR5IE
: 1;
1354 unsigned TMR5GIE
: 1;
1359 extern __at(0x0094) volatile __PIE4bits_t PIE4bits
;
1361 #define _TMR4IE 0x01
1362 #define _TMR6IE 0x02
1363 #define _TMR3IE 0x04
1364 #define _TMR3GIE 0x08
1365 #define _TMR5IE 0x10
1366 #define _TMR5GIE 0x20
1368 //==============================================================================
1371 //==============================================================================
1374 extern __at(0x0095) __sfr OPTION_REG
;
1384 unsigned TMR0SE
: 1;
1385 unsigned TMR0CS
: 1;
1386 unsigned INTEDG
: 1;
1387 unsigned NOT_WPUEN
: 1;
1407 } __OPTION_REGbits_t
;
1409 extern __at(0x0095) volatile __OPTION_REGbits_t OPTION_REGbits
;
1415 #define _TMR0SE 0x10
1417 #define _TMR0CS 0x20
1419 #define _INTEDG 0x40
1420 #define _NOT_WPUEN 0x80
1422 //==============================================================================
1425 //==============================================================================
1428 extern __at(0x0096) __sfr PCON
;
1432 unsigned NOT_BOR
: 1;
1433 unsigned NOT_POR
: 1;
1434 unsigned NOT_RI
: 1;
1435 unsigned NOT_RMCLR
: 1;
1436 unsigned NOT_RWDT
: 1;
1438 unsigned STKUNF
: 1;
1439 unsigned STKOVF
: 1;
1442 extern __at(0x0096) volatile __PCONbits_t PCONbits
;
1444 #define _NOT_BOR 0x01
1445 #define _NOT_POR 0x02
1446 #define _NOT_RI 0x04
1447 #define _NOT_RMCLR 0x08
1448 #define _NOT_RWDT 0x10
1449 #define _STKUNF 0x40
1450 #define _STKOVF 0x80
1452 //==============================================================================
1455 //==============================================================================
1458 extern __at(0x0097) __sfr WDTCON
;
1464 unsigned SWDTEN
: 1;
1465 unsigned WDTPS0
: 1;
1466 unsigned WDTPS1
: 1;
1467 unsigned WDTPS2
: 1;
1468 unsigned WDTPS3
: 1;
1469 unsigned WDTPS4
: 1;
1482 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1484 #define _SWDTEN 0x01
1485 #define _WDTPS0 0x02
1486 #define _WDTPS1 0x04
1487 #define _WDTPS2 0x08
1488 #define _WDTPS3 0x10
1489 #define _WDTPS4 0x20
1491 //==============================================================================
1494 //==============================================================================
1497 extern __at(0x0098) __sfr OSCTUNE
;
1520 extern __at(0x0098) volatile __OSCTUNEbits_t OSCTUNEbits
;
1529 //==============================================================================
1532 //==============================================================================
1535 extern __at(0x0099) __sfr OSCCON
;
1548 unsigned SPLLEN
: 1;
1565 extern __at(0x0099) volatile __OSCCONbits_t OSCCONbits
;
1573 #define _SPLLEN 0x80
1575 //==============================================================================
1578 //==============================================================================
1581 extern __at(0x009A) __sfr OSCSTAT
;
1585 unsigned HFIOFS
: 1;
1586 unsigned LFIOFR
: 1;
1587 unsigned MFIOFR
: 1;
1588 unsigned HFIOFL
: 1;
1589 unsigned HFIOFR
: 1;
1595 extern __at(0x009A) volatile __OSCSTATbits_t OSCSTATbits
;
1597 #define _HFIOFS 0x01
1598 #define _LFIOFR 0x02
1599 #define _MFIOFR 0x04
1600 #define _HFIOFL 0x08
1601 #define _HFIOFR 0x10
1606 //==============================================================================
1608 extern __at(0x009B) __sfr ADRES
;
1609 extern __at(0x009B) __sfr ADRESL
;
1610 extern __at(0x009C) __sfr ADRESH
;
1612 //==============================================================================
1615 extern __at(0x009D) __sfr ADCON0
;
1622 unsigned GO_NOT_DONE
: 1;
1663 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1666 #define _GO_NOT_DONE 0x02
1675 //==============================================================================
1678 //==============================================================================
1681 extern __at(0x009E) __sfr ADCON1
;
1687 unsigned ADPREF0
: 1;
1688 unsigned ADPREF1
: 1;
1689 unsigned ADNREF
: 1;
1699 unsigned ADPREF
: 2;
1704 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1706 #define _ADPREF0 0x01
1707 #define _ADPREF1 0x02
1708 #define _ADNREF 0x04
1711 //==============================================================================
1714 //==============================================================================
1717 extern __at(0x009F) __sfr ADCON2
;
1726 unsigned TRIGSEL0
: 1;
1727 unsigned TRIGSEL1
: 1;
1728 unsigned TRIGSEL2
: 1;
1729 unsigned TRIGSEL3
: 1;
1730 unsigned TRIGSEL4
: 1;
1736 unsigned TRIGSEL
: 5;
1740 extern __at(0x009F) volatile __ADCON2bits_t ADCON2bits
;
1742 #define _TRIGSEL0 0x08
1743 #define _TRIGSEL1 0x10
1744 #define _TRIGSEL2 0x20
1745 #define _TRIGSEL3 0x40
1746 #define _TRIGSEL4 0x80
1748 //==============================================================================
1751 //==============================================================================
1754 extern __at(0x010C) __sfr LATA
;
1768 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1776 //==============================================================================
1779 //==============================================================================
1782 extern __at(0x010E) __sfr LATC
;
1805 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1814 //==============================================================================
1817 //==============================================================================
1820 extern __at(0x010F) __sfr CMOUT
;
1824 unsigned MC1OUT
: 1;
1825 unsigned MC2OUT
: 1;
1834 extern __at(0x010F) volatile __CMOUTbits_t CMOUTbits
;
1836 #define _MC1OUT 0x01
1837 #define _MC2OUT 0x02
1839 //==============================================================================
1842 //==============================================================================
1845 extern __at(0x0110) __sfr CM1CON0
;
1853 unsigned Reserved
: 1;
1863 unsigned C1SYNC
: 1;
1874 extern __at(0x0110) volatile __CM1CON0bits_t CM1CON0bits
;
1876 #define _CM1CON0_SYNC 0x01
1877 #define _CM1CON0_C1SYNC 0x01
1878 #define _CM1CON0_HYS 0x02
1879 #define _CM1CON0_C1HYS 0x02
1880 #define _CM1CON0_Reserved 0x04
1881 #define _CM1CON0_C1SP 0x04
1882 #define _CM1CON0_ZLF 0x08
1883 #define _CM1CON0_C1ZLF 0x08
1884 #define _CM1CON0_POL 0x10
1885 #define _CM1CON0_C1POL 0x10
1886 #define _CM1CON0_OUT 0x40
1887 #define _CM1CON0_C1OUT 0x40
1888 #define _CM1CON0_ON 0x80
1889 #define _CM1CON0_C1ON 0x80
1891 //==============================================================================
1894 //==============================================================================
1897 extern __at(0x0111) __sfr CM1CON1
;
1915 unsigned C1INTN
: 1;
1916 unsigned C1INTP
: 1;
1926 extern __at(0x0111) volatile __CM1CON1bits_t CM1CON1bits
;
1928 #define _CM1CON1_INTN 0x01
1929 #define _CM1CON1_C1INTN 0x01
1930 #define _CM1CON1_INTP 0x02
1931 #define _CM1CON1_C1INTP 0x02
1933 //==============================================================================
1936 //==============================================================================
1939 extern __at(0x0112) __sfr CM1NSEL
;
1957 unsigned C1NCH0
: 1;
1958 unsigned C1NCH1
: 1;
1959 unsigned C1NCH2
: 1;
1980 extern __at(0x0112) volatile __CM1NSELbits_t CM1NSELbits
;
1983 #define _C1NCH0 0x01
1985 #define _C1NCH1 0x02
1987 #define _C1NCH2 0x04
1989 //==============================================================================
1992 //==============================================================================
1995 extern __at(0x0113) __sfr CM1PSEL
;
2013 unsigned C1PCH0
: 1;
2014 unsigned C1PCH1
: 1;
2015 unsigned C1PCH2
: 1;
2016 unsigned C1PCH3
: 1;
2036 extern __at(0x0113) volatile __CM1PSELbits_t CM1PSELbits
;
2039 #define _C1PCH0 0x01
2041 #define _C1PCH1 0x02
2043 #define _C1PCH2 0x04
2045 #define _C1PCH3 0x08
2047 //==============================================================================
2050 //==============================================================================
2053 extern __at(0x0114) __sfr CM2CON0
;
2061 unsigned Reserved
: 1;
2071 unsigned C2SYNC
: 1;
2082 extern __at(0x0114) volatile __CM2CON0bits_t CM2CON0bits
;
2084 #define _CM2CON0_SYNC 0x01
2085 #define _CM2CON0_C2SYNC 0x01
2086 #define _CM2CON0_HYS 0x02
2087 #define _CM2CON0_C2HYS 0x02
2088 #define _CM2CON0_Reserved 0x04
2089 #define _CM2CON0_C2SP 0x04
2090 #define _CM2CON0_ZLF 0x08
2091 #define _CM2CON0_C2ZLF 0x08
2092 #define _CM2CON0_POL 0x10
2093 #define _CM2CON0_C2POL 0x10
2094 #define _CM2CON0_OUT 0x40
2095 #define _CM2CON0_C2OUT 0x40
2096 #define _CM2CON0_ON 0x80
2097 #define _CM2CON0_C2ON 0x80
2099 //==============================================================================
2102 //==============================================================================
2105 extern __at(0x0115) __sfr CM2CON1
;
2123 unsigned C2INTN
: 1;
2124 unsigned C2INTP
: 1;
2134 extern __at(0x0115) volatile __CM2CON1bits_t CM2CON1bits
;
2136 #define _CM2CON1_INTN 0x01
2137 #define _CM2CON1_C2INTN 0x01
2138 #define _CM2CON1_INTP 0x02
2139 #define _CM2CON1_C2INTP 0x02
2141 //==============================================================================
2144 //==============================================================================
2147 extern __at(0x0116) __sfr CM2NSEL
;
2165 unsigned C2NCH0
: 1;
2166 unsigned C2NCH1
: 1;
2167 unsigned C2NCH2
: 1;
2188 extern __at(0x0116) volatile __CM2NSELbits_t CM2NSELbits
;
2190 #define _CM2NSEL_NCH0 0x01
2191 #define _CM2NSEL_C2NCH0 0x01
2192 #define _CM2NSEL_NCH1 0x02
2193 #define _CM2NSEL_C2NCH1 0x02
2194 #define _CM2NSEL_NCH2 0x04
2195 #define _CM2NSEL_C2NCH2 0x04
2197 //==============================================================================
2200 //==============================================================================
2203 extern __at(0x0117) __sfr CM2PSEL
;
2221 unsigned C2PCH0
: 1;
2222 unsigned C2PCH1
: 1;
2223 unsigned C2PCH2
: 1;
2224 unsigned C2PCH3
: 1;
2244 extern __at(0x0117) volatile __CM2PSELbits_t CM2PSELbits
;
2246 #define _CM2PSEL_PCH0 0x01
2247 #define _CM2PSEL_C2PCH0 0x01
2248 #define _CM2PSEL_PCH1 0x02
2249 #define _CM2PSEL_C2PCH1 0x02
2250 #define _CM2PSEL_PCH2 0x04
2251 #define _CM2PSEL_C2PCH2 0x04
2252 #define _CM2PSEL_PCH3 0x08
2253 #define _CM2PSEL_C2PCH3 0x08
2255 //==============================================================================
2258 //==============================================================================
2261 extern __at(0x018C) __sfr ANSELA
;
2275 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
2282 //==============================================================================
2285 //==============================================================================
2288 extern __at(0x018E) __sfr ANSELC
;
2311 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
2318 //==============================================================================
2320 extern __at(0x0191) __sfr PMADR
;
2321 extern __at(0x0191) __sfr PMADRL
;
2322 extern __at(0x0192) __sfr PMADRH
;
2323 extern __at(0x0193) __sfr PMDAT
;
2324 extern __at(0x0193) __sfr PMDATL
;
2325 extern __at(0x0194) __sfr PMDATH
;
2327 //==============================================================================
2330 extern __at(0x0195) __sfr PMCON1
;
2344 extern __at(0x0195) volatile __PMCON1bits_t PMCON1bits
;
2354 //==============================================================================
2356 extern __at(0x0196) __sfr PMCON2
;
2358 //==============================================================================
2361 extern __at(0x0197) __sfr VREGCON
;
2365 unsigned Reserved
: 1;
2366 unsigned VREGPM
: 1;
2375 extern __at(0x0197) volatile __VREGCONbits_t VREGCONbits
;
2377 #define _VREGCON_Reserved 0x01
2378 #define _VREGCON_VREGPM 0x02
2380 //==============================================================================
2382 extern __at(0x0199) __sfr RC1REG
;
2383 extern __at(0x0199) __sfr RCREG
;
2384 extern __at(0x0199) __sfr RCREG1
;
2385 extern __at(0x019A) __sfr TX1REG
;
2386 extern __at(0x019A) __sfr TXREG
;
2387 extern __at(0x019A) __sfr TXREG1
;
2388 extern __at(0x019B) __sfr SP1BRG
;
2389 extern __at(0x019B) __sfr SP1BRGL
;
2390 extern __at(0x019B) __sfr SPBRG
;
2391 extern __at(0x019B) __sfr SPBRG1
;
2392 extern __at(0x019B) __sfr SPBRGL
;
2393 extern __at(0x019C) __sfr SP1BRGH
;
2394 extern __at(0x019C) __sfr SPBRGH
;
2395 extern __at(0x019C) __sfr SPBRGH1
;
2397 //==============================================================================
2400 extern __at(0x019D) __sfr RC1STA
;
2414 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
2425 //==============================================================================
2428 //==============================================================================
2431 extern __at(0x019D) __sfr RCSTA
;
2445 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
2447 #define _RCSTA_RX9D 0x01
2448 #define _RCSTA_OERR 0x02
2449 #define _RCSTA_FERR 0x04
2450 #define _RCSTA_ADDEN 0x08
2451 #define _RCSTA_CREN 0x10
2452 #define _RCSTA_SREN 0x20
2453 #define _RCSTA_RX9 0x40
2454 #define _RCSTA_SPEN 0x80
2456 //==============================================================================
2459 //==============================================================================
2462 extern __at(0x019D) __sfr RCSTA1
;
2476 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
2478 #define _RCSTA1_RX9D 0x01
2479 #define _RCSTA1_OERR 0x02
2480 #define _RCSTA1_FERR 0x04
2481 #define _RCSTA1_ADDEN 0x08
2482 #define _RCSTA1_CREN 0x10
2483 #define _RCSTA1_SREN 0x20
2484 #define _RCSTA1_RX9 0x40
2485 #define _RCSTA1_SPEN 0x80
2487 //==============================================================================
2490 //==============================================================================
2493 extern __at(0x019E) __sfr TX1STA
;
2507 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
2509 #define _TX1STA_TX9D 0x01
2510 #define _TX1STA_TRMT 0x02
2511 #define _TX1STA_BRGH 0x04
2512 #define _TX1STA_SENDB 0x08
2513 #define _TX1STA_SYNC 0x10
2514 #define _TX1STA_TXEN 0x20
2515 #define _TX1STA_TX9 0x40
2516 #define _TX1STA_CSRC 0x80
2518 //==============================================================================
2521 //==============================================================================
2524 extern __at(0x019E) __sfr TXSTA
;
2538 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
2540 #define _TXSTA_TX9D 0x01
2541 #define _TXSTA_TRMT 0x02
2542 #define _TXSTA_BRGH 0x04
2543 #define _TXSTA_SENDB 0x08
2544 #define _TXSTA_SYNC 0x10
2545 #define _TXSTA_TXEN 0x20
2546 #define _TXSTA_TX9 0x40
2547 #define _TXSTA_CSRC 0x80
2549 //==============================================================================
2552 //==============================================================================
2555 extern __at(0x019E) __sfr TXSTA1
;
2569 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
2571 #define _TXSTA1_TX9D 0x01
2572 #define _TXSTA1_TRMT 0x02
2573 #define _TXSTA1_BRGH 0x04
2574 #define _TXSTA1_SENDB 0x08
2575 #define _TXSTA1_SYNC 0x10
2576 #define _TXSTA1_TXEN 0x20
2577 #define _TXSTA1_TX9 0x40
2578 #define _TXSTA1_CSRC 0x80
2580 //==============================================================================
2583 //==============================================================================
2586 extern __at(0x019F) __sfr BAUD1CON
;
2597 unsigned ABDOVF
: 1;
2600 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
2607 #define _ABDOVF 0x80
2609 //==============================================================================
2612 //==============================================================================
2615 extern __at(0x019F) __sfr BAUDCON
;
2626 unsigned ABDOVF
: 1;
2629 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
2631 #define _BAUDCON_ABDEN 0x01
2632 #define _BAUDCON_WUE 0x02
2633 #define _BAUDCON_BRG16 0x08
2634 #define _BAUDCON_SCKP 0x10
2635 #define _BAUDCON_RCIDL 0x40
2636 #define _BAUDCON_ABDOVF 0x80
2638 //==============================================================================
2641 //==============================================================================
2644 extern __at(0x019F) __sfr BAUDCON1
;
2655 unsigned ABDOVF
: 1;
2658 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
2660 #define _BAUDCON1_ABDEN 0x01
2661 #define _BAUDCON1_WUE 0x02
2662 #define _BAUDCON1_BRG16 0x08
2663 #define _BAUDCON1_SCKP 0x10
2664 #define _BAUDCON1_RCIDL 0x40
2665 #define _BAUDCON1_ABDOVF 0x80
2667 //==============================================================================
2670 //==============================================================================
2673 extern __at(0x019F) __sfr BAUDCTL
;
2684 unsigned ABDOVF
: 1;
2687 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
2689 #define _BAUDCTL_ABDEN 0x01
2690 #define _BAUDCTL_WUE 0x02
2691 #define _BAUDCTL_BRG16 0x08
2692 #define _BAUDCTL_SCKP 0x10
2693 #define _BAUDCTL_RCIDL 0x40
2694 #define _BAUDCTL_ABDOVF 0x80
2696 //==============================================================================
2699 //==============================================================================
2702 extern __at(0x019F) __sfr BAUDCTL1
;
2713 unsigned ABDOVF
: 1;
2716 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
2718 #define _BAUDCTL1_ABDEN 0x01
2719 #define _BAUDCTL1_WUE 0x02
2720 #define _BAUDCTL1_BRG16 0x08
2721 #define _BAUDCTL1_SCKP 0x10
2722 #define _BAUDCTL1_RCIDL 0x40
2723 #define _BAUDCTL1_ABDOVF 0x80
2725 //==============================================================================
2728 //==============================================================================
2731 extern __at(0x020C) __sfr WPUA
;
2754 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
2763 //==============================================================================
2766 //==============================================================================
2769 extern __at(0x020E) __sfr WPUC
;
2792 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
2801 //==============================================================================
2804 //==============================================================================
2807 extern __at(0x0211) __sfr SSP1BUF
;
2813 unsigned SSP1BUF0
: 1;
2814 unsigned SSP1BUF1
: 1;
2815 unsigned SSP1BUF2
: 1;
2816 unsigned SSP1BUF3
: 1;
2817 unsigned SSP1BUF4
: 1;
2818 unsigned SSP1BUF5
: 1;
2819 unsigned SSP1BUF6
: 1;
2820 unsigned SSP1BUF7
: 1;
2836 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
2838 #define _SSP1BUF0 0x01
2840 #define _SSP1BUF1 0x02
2842 #define _SSP1BUF2 0x04
2844 #define _SSP1BUF3 0x08
2846 #define _SSP1BUF4 0x10
2848 #define _SSP1BUF5 0x20
2850 #define _SSP1BUF6 0x40
2852 #define _SSP1BUF7 0x80
2855 //==============================================================================
2858 //==============================================================================
2861 extern __at(0x0211) __sfr SSPBUF
;
2867 unsigned SSP1BUF0
: 1;
2868 unsigned SSP1BUF1
: 1;
2869 unsigned SSP1BUF2
: 1;
2870 unsigned SSP1BUF3
: 1;
2871 unsigned SSP1BUF4
: 1;
2872 unsigned SSP1BUF5
: 1;
2873 unsigned SSP1BUF6
: 1;
2874 unsigned SSP1BUF7
: 1;
2890 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
2892 #define _SSPBUF_SSP1BUF0 0x01
2893 #define _SSPBUF_BUF0 0x01
2894 #define _SSPBUF_SSP1BUF1 0x02
2895 #define _SSPBUF_BUF1 0x02
2896 #define _SSPBUF_SSP1BUF2 0x04
2897 #define _SSPBUF_BUF2 0x04
2898 #define _SSPBUF_SSP1BUF3 0x08
2899 #define _SSPBUF_BUF3 0x08
2900 #define _SSPBUF_SSP1BUF4 0x10
2901 #define _SSPBUF_BUF4 0x10
2902 #define _SSPBUF_SSP1BUF5 0x20
2903 #define _SSPBUF_BUF5 0x20
2904 #define _SSPBUF_SSP1BUF6 0x40
2905 #define _SSPBUF_BUF6 0x40
2906 #define _SSPBUF_SSP1BUF7 0x80
2907 #define _SSPBUF_BUF7 0x80
2909 //==============================================================================
2912 //==============================================================================
2915 extern __at(0x0212) __sfr SSP1ADD
;
2921 unsigned SSP1ADD0
: 1;
2922 unsigned SSP1ADD1
: 1;
2923 unsigned SSP1ADD2
: 1;
2924 unsigned SSP1ADD3
: 1;
2925 unsigned SSP1ADD4
: 1;
2926 unsigned SSP1ADD5
: 1;
2927 unsigned SSP1ADD6
: 1;
2928 unsigned SSP1ADD7
: 1;
2944 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
2946 #define _SSP1ADD0 0x01
2948 #define _SSP1ADD1 0x02
2950 #define _SSP1ADD2 0x04
2952 #define _SSP1ADD3 0x08
2954 #define _SSP1ADD4 0x10
2956 #define _SSP1ADD5 0x20
2958 #define _SSP1ADD6 0x40
2960 #define _SSP1ADD7 0x80
2963 //==============================================================================
2966 //==============================================================================
2969 extern __at(0x0212) __sfr SSPADD
;
2975 unsigned SSP1ADD0
: 1;
2976 unsigned SSP1ADD1
: 1;
2977 unsigned SSP1ADD2
: 1;
2978 unsigned SSP1ADD3
: 1;
2979 unsigned SSP1ADD4
: 1;
2980 unsigned SSP1ADD5
: 1;
2981 unsigned SSP1ADD6
: 1;
2982 unsigned SSP1ADD7
: 1;
2998 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
3000 #define _SSPADD_SSP1ADD0 0x01
3001 #define _SSPADD_ADD0 0x01
3002 #define _SSPADD_SSP1ADD1 0x02
3003 #define _SSPADD_ADD1 0x02
3004 #define _SSPADD_SSP1ADD2 0x04
3005 #define _SSPADD_ADD2 0x04
3006 #define _SSPADD_SSP1ADD3 0x08
3007 #define _SSPADD_ADD3 0x08
3008 #define _SSPADD_SSP1ADD4 0x10
3009 #define _SSPADD_ADD4 0x10
3010 #define _SSPADD_SSP1ADD5 0x20
3011 #define _SSPADD_ADD5 0x20
3012 #define _SSPADD_SSP1ADD6 0x40
3013 #define _SSPADD_ADD6 0x40
3014 #define _SSPADD_SSP1ADD7 0x80
3015 #define _SSPADD_ADD7 0x80
3017 //==============================================================================
3020 //==============================================================================
3023 extern __at(0x0213) __sfr SSP1MSK
;
3029 unsigned SSP1MSK0
: 1;
3030 unsigned SSP1MSK1
: 1;
3031 unsigned SSP1MSK2
: 1;
3032 unsigned SSP1MSK3
: 1;
3033 unsigned SSP1MSK4
: 1;
3034 unsigned SSP1MSK5
: 1;
3035 unsigned SSP1MSK6
: 1;
3036 unsigned SSP1MSK7
: 1;
3052 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
3054 #define _SSP1MSK0 0x01
3056 #define _SSP1MSK1 0x02
3058 #define _SSP1MSK2 0x04
3060 #define _SSP1MSK3 0x08
3062 #define _SSP1MSK4 0x10
3064 #define _SSP1MSK5 0x20
3066 #define _SSP1MSK6 0x40
3068 #define _SSP1MSK7 0x80
3071 //==============================================================================
3074 //==============================================================================
3077 extern __at(0x0213) __sfr SSPMSK
;
3083 unsigned SSP1MSK0
: 1;
3084 unsigned SSP1MSK1
: 1;
3085 unsigned SSP1MSK2
: 1;
3086 unsigned SSP1MSK3
: 1;
3087 unsigned SSP1MSK4
: 1;
3088 unsigned SSP1MSK5
: 1;
3089 unsigned SSP1MSK6
: 1;
3090 unsigned SSP1MSK7
: 1;
3106 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
3108 #define _SSPMSK_SSP1MSK0 0x01
3109 #define _SSPMSK_MSK0 0x01
3110 #define _SSPMSK_SSP1MSK1 0x02
3111 #define _SSPMSK_MSK1 0x02
3112 #define _SSPMSK_SSP1MSK2 0x04
3113 #define _SSPMSK_MSK2 0x04
3114 #define _SSPMSK_SSP1MSK3 0x08
3115 #define _SSPMSK_MSK3 0x08
3116 #define _SSPMSK_SSP1MSK4 0x10
3117 #define _SSPMSK_MSK4 0x10
3118 #define _SSPMSK_SSP1MSK5 0x20
3119 #define _SSPMSK_MSK5 0x20
3120 #define _SSPMSK_SSP1MSK6 0x40
3121 #define _SSPMSK_MSK6 0x40
3122 #define _SSPMSK_SSP1MSK7 0x80
3123 #define _SSPMSK_MSK7 0x80
3125 //==============================================================================
3128 //==============================================================================
3131 extern __at(0x0214) __sfr SSP1STAT
;
3137 unsigned R_NOT_W
: 1;
3140 unsigned D_NOT_A
: 1;
3145 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
3149 #define _R_NOT_W 0x04
3152 #define _D_NOT_A 0x20
3156 //==============================================================================
3159 //==============================================================================
3162 extern __at(0x0214) __sfr SSPSTAT
;
3168 unsigned R_NOT_W
: 1;
3171 unsigned D_NOT_A
: 1;
3176 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
3178 #define _SSPSTAT_BF 0x01
3179 #define _SSPSTAT_UA 0x02
3180 #define _SSPSTAT_R_NOT_W 0x04
3181 #define _SSPSTAT_S 0x08
3182 #define _SSPSTAT_P 0x10
3183 #define _SSPSTAT_D_NOT_A 0x20
3184 #define _SSPSTAT_CKE 0x40
3185 #define _SSPSTAT_SMP 0x80
3187 //==============================================================================
3190 //==============================================================================
3193 extern __at(0x0215) __sfr SSP1CON
;
3216 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
3227 //==============================================================================
3230 //==============================================================================
3233 extern __at(0x0215) __sfr SSP1CON1
;
3256 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
3258 #define _SSP1CON1_SSPM0 0x01
3259 #define _SSP1CON1_SSPM1 0x02
3260 #define _SSP1CON1_SSPM2 0x04
3261 #define _SSP1CON1_SSPM3 0x08
3262 #define _SSP1CON1_CKP 0x10
3263 #define _SSP1CON1_SSPEN 0x20
3264 #define _SSP1CON1_SSPOV 0x40
3265 #define _SSP1CON1_WCOL 0x80
3267 //==============================================================================
3270 //==============================================================================
3273 extern __at(0x0215) __sfr SSPCON
;
3296 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
3298 #define _SSPCON_SSPM0 0x01
3299 #define _SSPCON_SSPM1 0x02
3300 #define _SSPCON_SSPM2 0x04
3301 #define _SSPCON_SSPM3 0x08
3302 #define _SSPCON_CKP 0x10
3303 #define _SSPCON_SSPEN 0x20
3304 #define _SSPCON_SSPOV 0x40
3305 #define _SSPCON_WCOL 0x80
3307 //==============================================================================
3310 //==============================================================================
3313 extern __at(0x0215) __sfr SSPCON1
;
3336 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
3338 #define _SSPCON1_SSPM0 0x01
3339 #define _SSPCON1_SSPM1 0x02
3340 #define _SSPCON1_SSPM2 0x04
3341 #define _SSPCON1_SSPM3 0x08
3342 #define _SSPCON1_CKP 0x10
3343 #define _SSPCON1_SSPEN 0x20
3344 #define _SSPCON1_SSPOV 0x40
3345 #define _SSPCON1_WCOL 0x80
3347 //==============================================================================
3350 //==============================================================================
3353 extern __at(0x0216) __sfr SSP1CON2
;
3363 unsigned ACKSTAT
: 1;
3367 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
3375 #define _ACKSTAT 0x40
3378 //==============================================================================
3381 //==============================================================================
3384 extern __at(0x0216) __sfr SSPCON2
;
3394 unsigned ACKSTAT
: 1;
3398 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
3400 #define _SSPCON2_SEN 0x01
3401 #define _SSPCON2_RSEN 0x02
3402 #define _SSPCON2_PEN 0x04
3403 #define _SSPCON2_RCEN 0x08
3404 #define _SSPCON2_ACKEN 0x10
3405 #define _SSPCON2_ACKDT 0x20
3406 #define _SSPCON2_ACKSTAT 0x40
3407 #define _SSPCON2_GCEN 0x80
3409 //==============================================================================
3412 //==============================================================================
3415 extern __at(0x0217) __sfr SSP1CON3
;
3426 unsigned ACKTIM
: 1;
3429 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
3438 #define _ACKTIM 0x80
3440 //==============================================================================
3443 //==============================================================================
3446 extern __at(0x0217) __sfr SSPCON3
;
3457 unsigned ACKTIM
: 1;
3460 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
3462 #define _SSPCON3_DHEN 0x01
3463 #define _SSPCON3_AHEN 0x02
3464 #define _SSPCON3_SBCDE 0x04
3465 #define _SSPCON3_SDAHT 0x08
3466 #define _SSPCON3_BOEN 0x10
3467 #define _SSPCON3_SCIE 0x20
3468 #define _SSPCON3_PCIE 0x40
3469 #define _SSPCON3_ACKTIM 0x80
3471 //==============================================================================
3474 //==============================================================================
3477 extern __at(0x021D) __sfr BORCON
;
3481 unsigned BORRDY
: 1;
3488 unsigned SBOREN
: 1;
3491 extern __at(0x021D) volatile __BORCONbits_t BORCONbits
;
3493 #define _BORRDY 0x01
3495 #define _SBOREN 0x80
3497 //==============================================================================
3500 //==============================================================================
3503 extern __at(0x021E) __sfr FVRCON
;
3513 unsigned FVRRDY
: 1;
3517 extern __at(0x021E) volatile __FVRCONbits_t FVRCONbits
;
3521 #define _FVRRDY 0x40
3524 //==============================================================================
3527 //==============================================================================
3530 extern __at(0x021F) __sfr ZCD1CON
;
3534 unsigned ZCD1INTN
: 1;
3535 unsigned ZCD1INTP
: 1;
3538 unsigned ZCD1POL
: 1;
3539 unsigned ZCD1OUT
: 1;
3541 unsigned ZCD1EN
: 1;
3544 extern __at(0x021F) volatile __ZCD1CONbits_t ZCD1CONbits
;
3546 #define _ZCD1INTN 0x01
3547 #define _ZCD1INTP 0x02
3548 #define _ZCD1POL 0x10
3549 #define _ZCD1OUT 0x20
3550 #define _ZCD1EN 0x80
3552 //==============================================================================
3555 //==============================================================================
3558 extern __at(0x028C) __sfr ODCONA
;
3572 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
3580 //==============================================================================
3583 //==============================================================================
3586 extern __at(0x028E) __sfr ODCONC
;
3609 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
3618 //==============================================================================
3620 extern __at(0x0291) __sfr CCPR1
;
3621 extern __at(0x0291) __sfr CCPR1L
;
3622 extern __at(0x0292) __sfr CCPR1H
;
3624 //==============================================================================
3627 extern __at(0x0293) __sfr CCP1CON
;
3645 unsigned CCP1MODE0
: 1;
3646 unsigned CCP1MODE1
: 1;
3647 unsigned CCP1MODE2
: 1;
3648 unsigned CCP1MODE3
: 1;
3649 unsigned CCP1FMT
: 1;
3650 unsigned CCP1OUT
: 1;
3652 unsigned CCP1EN
: 1;
3657 unsigned CCP1MODE
: 4;
3668 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
3671 #define _CCP1MODE0 0x01
3673 #define _CCP1MODE1 0x02
3675 #define _CCP1MODE2 0x04
3677 #define _CCP1MODE3 0x08
3679 #define _CCP1FMT 0x10
3681 #define _CCP1OUT 0x20
3683 #define _CCP1EN 0x80
3685 //==============================================================================
3688 //==============================================================================
3691 extern __at(0x0294) __sfr CCP1CAP
;
3709 unsigned CCP1CTS0
: 1;
3710 unsigned CCP1CTS1
: 1;
3711 unsigned CCP1CTS2
: 1;
3727 unsigned CCP1CTS
: 3;
3732 extern __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits
;
3735 #define _CCP1CTS0 0x01
3737 #define _CCP1CTS1 0x02
3739 #define _CCP1CTS2 0x04
3741 //==============================================================================
3744 //==============================================================================
3747 extern __at(0x029E) __sfr CCPTMRS
;
3753 unsigned C1TSEL0
: 1;
3754 unsigned C1TSEL1
: 1;
3757 unsigned P3TSEL0
: 1;
3758 unsigned P3TSEL1
: 1;
3765 unsigned C1TSEL
: 2;
3772 unsigned P3TSEL
: 2;
3777 extern __at(0x029E) volatile __CCPTMRSbits_t CCPTMRSbits
;
3779 #define _C1TSEL0 0x01
3780 #define _C1TSEL1 0x02
3781 #define _P3TSEL0 0x10
3782 #define _P3TSEL1 0x20
3784 //==============================================================================
3787 //==============================================================================
3790 extern __at(0x030C) __sfr SLRCONA
;
3804 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
3812 //==============================================================================
3815 //==============================================================================
3818 extern __at(0x030E) __sfr SLRCONC
;
3841 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
3850 //==============================================================================
3853 //==============================================================================
3856 extern __at(0x038C) __sfr INLVLA
;
3862 unsigned INLVLA0
: 1;
3863 unsigned INLVLA1
: 1;
3864 unsigned INLVLA2
: 1;
3865 unsigned INLVLA3
: 1;
3866 unsigned INLVLA4
: 1;
3867 unsigned INLVLA5
: 1;
3874 unsigned INLVLA
: 6;
3879 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
3881 #define _INLVLA0 0x01
3882 #define _INLVLA1 0x02
3883 #define _INLVLA2 0x04
3884 #define _INLVLA3 0x08
3885 #define _INLVLA4 0x10
3886 #define _INLVLA5 0x20
3888 //==============================================================================
3891 //==============================================================================
3894 extern __at(0x038E) __sfr INLVLC
;
3900 unsigned INLVLC0
: 1;
3901 unsigned INLVLC1
: 1;
3902 unsigned INLVLC2
: 1;
3903 unsigned INLVLC3
: 1;
3904 unsigned INLVLC4
: 1;
3905 unsigned INLVLC5
: 1;
3912 unsigned INLVLC
: 6;
3917 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
3919 #define _INLVLC0 0x01
3920 #define _INLVLC1 0x02
3921 #define _INLVLC2 0x04
3922 #define _INLVLC3 0x08
3923 #define _INLVLC4 0x10
3924 #define _INLVLC5 0x20
3926 //==============================================================================
3929 //==============================================================================
3932 extern __at(0x0391) __sfr IOCAP
;
3938 unsigned IOCAP0
: 1;
3939 unsigned IOCAP1
: 1;
3940 unsigned IOCAP2
: 1;
3941 unsigned IOCAP3
: 1;
3942 unsigned IOCAP4
: 1;
3943 unsigned IOCAP5
: 1;
3955 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
3957 #define _IOCAP0 0x01
3958 #define _IOCAP1 0x02
3959 #define _IOCAP2 0x04
3960 #define _IOCAP3 0x08
3961 #define _IOCAP4 0x10
3962 #define _IOCAP5 0x20
3964 //==============================================================================
3967 //==============================================================================
3970 extern __at(0x0392) __sfr IOCAN
;
3976 unsigned IOCAN0
: 1;
3977 unsigned IOCAN1
: 1;
3978 unsigned IOCAN2
: 1;
3979 unsigned IOCAN3
: 1;
3980 unsigned IOCAN4
: 1;
3981 unsigned IOCAN5
: 1;
3993 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
3995 #define _IOCAN0 0x01
3996 #define _IOCAN1 0x02
3997 #define _IOCAN2 0x04
3998 #define _IOCAN3 0x08
3999 #define _IOCAN4 0x10
4000 #define _IOCAN5 0x20
4002 //==============================================================================
4005 //==============================================================================
4008 extern __at(0x0393) __sfr IOCAF
;
4014 unsigned IOCAF0
: 1;
4015 unsigned IOCAF1
: 1;
4016 unsigned IOCAF2
: 1;
4017 unsigned IOCAF3
: 1;
4018 unsigned IOCAF4
: 1;
4019 unsigned IOCAF5
: 1;
4031 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
4033 #define _IOCAF0 0x01
4034 #define _IOCAF1 0x02
4035 #define _IOCAF2 0x04
4036 #define _IOCAF3 0x08
4037 #define _IOCAF4 0x10
4038 #define _IOCAF5 0x20
4040 //==============================================================================
4043 //==============================================================================
4046 extern __at(0x0397) __sfr IOCCP
;
4052 unsigned IOCCP0
: 1;
4053 unsigned IOCCP1
: 1;
4054 unsigned IOCCP2
: 1;
4055 unsigned IOCCP3
: 1;
4056 unsigned IOCCP4
: 1;
4057 unsigned IOCCP5
: 1;
4069 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
4071 #define _IOCCP0 0x01
4072 #define _IOCCP1 0x02
4073 #define _IOCCP2 0x04
4074 #define _IOCCP3 0x08
4075 #define _IOCCP4 0x10
4076 #define _IOCCP5 0x20
4078 //==============================================================================
4081 //==============================================================================
4084 extern __at(0x0398) __sfr IOCCN
;
4090 unsigned IOCCN0
: 1;
4091 unsigned IOCCN1
: 1;
4092 unsigned IOCCN2
: 1;
4093 unsigned IOCCN3
: 1;
4094 unsigned IOCCN4
: 1;
4095 unsigned IOCCN5
: 1;
4107 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
4109 #define _IOCCN0 0x01
4110 #define _IOCCN1 0x02
4111 #define _IOCCN2 0x04
4112 #define _IOCCN3 0x08
4113 #define _IOCCN4 0x10
4114 #define _IOCCN5 0x20
4116 //==============================================================================
4119 //==============================================================================
4122 extern __at(0x0399) __sfr IOCCF
;
4128 unsigned IOCCF0
: 1;
4129 unsigned IOCCF1
: 1;
4130 unsigned IOCCF2
: 1;
4131 unsigned IOCCF3
: 1;
4132 unsigned IOCCF4
: 1;
4133 unsigned IOCCF5
: 1;
4145 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
4147 #define _IOCCF0 0x01
4148 #define _IOCCF1 0x02
4149 #define _IOCCF2 0x04
4150 #define _IOCCF3 0x08
4151 #define _IOCCF4 0x10
4152 #define _IOCCF5 0x20
4154 //==============================================================================
4157 //==============================================================================
4160 extern __at(0x039B) __sfr MD1CON0
;
4178 unsigned MD1BIT
: 1;
4182 unsigned MD1OPOL
: 1;
4183 unsigned MD1OUT
: 1;
4189 extern __at(0x039B) volatile __MD1CON0bits_t MD1CON0bits
;
4191 #define _MD1CON0_BIT 0x01
4192 #define _MD1CON0_MD1BIT 0x01
4193 #define _MD1CON0_OPOL 0x10
4194 #define _MD1CON0_MD1OPOL 0x10
4195 #define _MD1CON0_OUT 0x20
4196 #define _MD1CON0_MD1OUT 0x20
4197 #define _MD1CON0_EN 0x80
4198 #define _MD1CON0_MD1EN 0x80
4200 //==============================================================================
4203 //==============================================================================
4206 extern __at(0x039C) __sfr MD1CON1
;
4212 unsigned CLSYNC
: 1;
4216 unsigned CHSYNC
: 1;
4224 unsigned MD1CLSYNC
: 1;
4225 unsigned MD1CLPOL
: 1;
4228 unsigned MD1CHSYNC
: 1;
4229 unsigned MD1CHPOL
: 1;
4235 extern __at(0x039C) volatile __MD1CON1bits_t MD1CON1bits
;
4237 #define _CLSYNC 0x01
4238 #define _MD1CLSYNC 0x01
4240 #define _MD1CLPOL 0x02
4241 #define _CHSYNC 0x10
4242 #define _MD1CHSYNC 0x10
4244 #define _MD1CHPOL 0x20
4246 //==============================================================================
4249 //==============================================================================
4252 extern __at(0x039D) __sfr MD1SRC
;
4270 unsigned MD1MS0
: 1;
4271 unsigned MD1MS1
: 1;
4272 unsigned MD1MS2
: 1;
4273 unsigned MD1MS3
: 1;
4274 unsigned MD1MS4
: 1;
4293 extern __at(0x039D) volatile __MD1SRCbits_t MD1SRCbits
;
4296 #define _MD1MS0 0x01
4298 #define _MD1MS1 0x02
4300 #define _MD1MS2 0x04
4302 #define _MD1MS3 0x08
4304 #define _MD1MS4 0x10
4306 //==============================================================================
4309 //==============================================================================
4312 extern __at(0x039E) __sfr MD1CARL
;
4330 unsigned MD1CL0
: 1;
4331 unsigned MD1CL1
: 1;
4332 unsigned MD1CL2
: 1;
4333 unsigned MD1CL3
: 1;
4353 extern __at(0x039E) volatile __MD1CARLbits_t MD1CARLbits
;
4356 #define _MD1CL0 0x01
4358 #define _MD1CL1 0x02
4360 #define _MD1CL2 0x04
4362 #define _MD1CL3 0x08
4364 //==============================================================================
4367 //==============================================================================
4370 extern __at(0x039F) __sfr MD1CARH
;
4388 unsigned MD1CH0
: 1;
4389 unsigned MD1CH1
: 1;
4390 unsigned MD1CH2
: 1;
4391 unsigned MD1CH3
: 1;
4411 extern __at(0x039F) volatile __MD1CARHbits_t MD1CARHbits
;
4414 #define _MD1CH0 0x01
4416 #define _MD1CH1 0x02
4418 #define _MD1CH2 0x04
4420 #define _MD1CH3 0x08
4422 //==============================================================================
4425 //==============================================================================
4428 extern __at(0x040E) __sfr HIDRVC
;
4442 extern __at(0x040E) volatile __HIDRVCbits_t HIDRVCbits
;
4447 //==============================================================================
4449 extern __at(0x0413) __sfr T4TMR
;
4450 extern __at(0x0413) __sfr TMR4
;
4451 extern __at(0x0414) __sfr PR4
;
4452 extern __at(0x0414) __sfr T4PR
;
4454 //==============================================================================
4457 extern __at(0x0415) __sfr T4CON
;
4463 unsigned OUTPS0
: 1;
4464 unsigned OUTPS1
: 1;
4465 unsigned OUTPS2
: 1;
4466 unsigned OUTPS3
: 1;
4475 unsigned T4OUTPS0
: 1;
4476 unsigned T4OUTPS1
: 1;
4477 unsigned T4OUTPS2
: 1;
4478 unsigned T4OUTPS3
: 1;
4479 unsigned T4CKPS0
: 1;
4480 unsigned T4CKPS1
: 1;
4481 unsigned T4CKPS2
: 1;
4494 unsigned TMR4ON
: 1;
4505 unsigned T4OUTPS
: 4;
4519 unsigned T4CKPS
: 3;
4524 extern __at(0x0415) volatile __T4CONbits_t T4CONbits
;
4526 #define _T4CON_OUTPS0 0x01
4527 #define _T4CON_T4OUTPS0 0x01
4528 #define _T4CON_OUTPS1 0x02
4529 #define _T4CON_T4OUTPS1 0x02
4530 #define _T4CON_OUTPS2 0x04
4531 #define _T4CON_T4OUTPS2 0x04
4532 #define _T4CON_OUTPS3 0x08
4533 #define _T4CON_T4OUTPS3 0x08
4534 #define _T4CON_CKPS0 0x10
4535 #define _T4CON_T4CKPS0 0x10
4536 #define _T4CON_CKPS1 0x20
4537 #define _T4CON_T4CKPS1 0x20
4538 #define _T4CON_CKPS2 0x40
4539 #define _T4CON_T4CKPS2 0x40
4540 #define _T4CON_ON 0x80
4541 #define _T4CON_T4ON 0x80
4542 #define _T4CON_TMR4ON 0x80
4544 //==============================================================================
4547 //==============================================================================
4550 extern __at(0x0416) __sfr T4HLT
;
4561 unsigned CKSYNC
: 1;
4568 unsigned T4MODE0
: 1;
4569 unsigned T4MODE1
: 1;
4570 unsigned T4MODE2
: 1;
4571 unsigned T4MODE3
: 1;
4572 unsigned T4MODE4
: 1;
4573 unsigned T4CKSYNC
: 1;
4574 unsigned T4CKPOL
: 1;
4575 unsigned T4PSYNC
: 1;
4586 unsigned T4MODE
: 5;
4591 extern __at(0x0416) volatile __T4HLTbits_t T4HLTbits
;
4593 #define _T4HLT_MODE0 0x01
4594 #define _T4HLT_T4MODE0 0x01
4595 #define _T4HLT_MODE1 0x02
4596 #define _T4HLT_T4MODE1 0x02
4597 #define _T4HLT_MODE2 0x04
4598 #define _T4HLT_T4MODE2 0x04
4599 #define _T4HLT_MODE3 0x08
4600 #define _T4HLT_T4MODE3 0x08
4601 #define _T4HLT_MODE4 0x10
4602 #define _T4HLT_T4MODE4 0x10
4603 #define _T4HLT_CKSYNC 0x20
4604 #define _T4HLT_T4CKSYNC 0x20
4605 #define _T4HLT_CKPOL 0x40
4606 #define _T4HLT_T4CKPOL 0x40
4607 #define _T4HLT_PSYNC 0x80
4608 #define _T4HLT_T4PSYNC 0x80
4610 //==============================================================================
4613 //==============================================================================
4616 extern __at(0x0417) __sfr T4CLKCON
;
4657 extern __at(0x0417) volatile __T4CLKCONbits_t T4CLKCONbits
;
4659 #define _T4CLKCON_CS0 0x01
4660 #define _T4CLKCON_T4CS0 0x01
4661 #define _T4CLKCON_CS1 0x02
4662 #define _T4CLKCON_T4CS1 0x02
4663 #define _T4CLKCON_CS2 0x04
4664 #define _T4CLKCON_T4CS2 0x04
4665 #define _T4CLKCON_CS3 0x08
4666 #define _T4CLKCON_T4CS3 0x08
4668 //==============================================================================
4671 //==============================================================================
4674 extern __at(0x0418) __sfr T4RST
;
4692 unsigned T4RSEL0
: 1;
4693 unsigned T4RSEL1
: 1;
4694 unsigned T4RSEL2
: 1;
4695 unsigned T4RSEL3
: 1;
4710 unsigned T4RSEL
: 4;
4715 extern __at(0x0418) volatile __T4RSTbits_t T4RSTbits
;
4717 #define _T4RST_RSEL0 0x01
4718 #define _T4RST_T4RSEL0 0x01
4719 #define _T4RST_RSEL1 0x02
4720 #define _T4RST_T4RSEL1 0x02
4721 #define _T4RST_RSEL2 0x04
4722 #define _T4RST_T4RSEL2 0x04
4723 #define _T4RST_RSEL3 0x08
4724 #define _T4RST_T4RSEL3 0x08
4726 //==============================================================================
4728 extern __at(0x041A) __sfr T6TMR
;
4729 extern __at(0x041A) __sfr TMR6
;
4730 extern __at(0x041B) __sfr PR6
;
4731 extern __at(0x041B) __sfr T6PR
;
4733 //==============================================================================
4736 extern __at(0x041C) __sfr T6CON
;
4742 unsigned OUTPS0
: 1;
4743 unsigned OUTPS1
: 1;
4744 unsigned OUTPS2
: 1;
4745 unsigned OUTPS3
: 1;
4754 unsigned T6OUTPS0
: 1;
4755 unsigned T6OUTPS1
: 1;
4756 unsigned T6OUTPS2
: 1;
4757 unsigned T6OUTPS3
: 1;
4758 unsigned T6CKPS0
: 1;
4759 unsigned T6CKPS1
: 1;
4760 unsigned T6CKPS2
: 1;
4773 unsigned TMR6ON
: 1;
4778 unsigned T6OUTPS
: 4;
4798 unsigned T6CKPS
: 3;
4803 extern __at(0x041C) volatile __T6CONbits_t T6CONbits
;
4805 #define _T6CON_OUTPS0 0x01
4806 #define _T6CON_T6OUTPS0 0x01
4807 #define _T6CON_OUTPS1 0x02
4808 #define _T6CON_T6OUTPS1 0x02
4809 #define _T6CON_OUTPS2 0x04
4810 #define _T6CON_T6OUTPS2 0x04
4811 #define _T6CON_OUTPS3 0x08
4812 #define _T6CON_T6OUTPS3 0x08
4813 #define _T6CON_CKPS0 0x10
4814 #define _T6CON_T6CKPS0 0x10
4815 #define _T6CON_CKPS1 0x20
4816 #define _T6CON_T6CKPS1 0x20
4817 #define _T6CON_CKPS2 0x40
4818 #define _T6CON_T6CKPS2 0x40
4819 #define _T6CON_ON 0x80
4820 #define _T6CON_T6ON 0x80
4821 #define _T6CON_TMR6ON 0x80
4823 //==============================================================================
4826 //==============================================================================
4829 extern __at(0x041D) __sfr T6HLT
;
4840 unsigned CKSYNC
: 1;
4847 unsigned T6MODE0
: 1;
4848 unsigned T6MODE1
: 1;
4849 unsigned T6MODE2
: 1;
4850 unsigned T6MODE3
: 1;
4851 unsigned T6MODE4
: 1;
4852 unsigned T6CKSYNC
: 1;
4853 unsigned T6CKPOL
: 1;
4854 unsigned T6PSYNC
: 1;
4865 unsigned T6MODE
: 5;
4870 extern __at(0x041D) volatile __T6HLTbits_t T6HLTbits
;
4872 #define _T6HLT_MODE0 0x01
4873 #define _T6HLT_T6MODE0 0x01
4874 #define _T6HLT_MODE1 0x02
4875 #define _T6HLT_T6MODE1 0x02
4876 #define _T6HLT_MODE2 0x04
4877 #define _T6HLT_T6MODE2 0x04
4878 #define _T6HLT_MODE3 0x08
4879 #define _T6HLT_T6MODE3 0x08
4880 #define _T6HLT_MODE4 0x10
4881 #define _T6HLT_T6MODE4 0x10
4882 #define _T6HLT_CKSYNC 0x20
4883 #define _T6HLT_T6CKSYNC 0x20
4884 #define _T6HLT_CKPOL 0x40
4885 #define _T6HLT_T6CKPOL 0x40
4886 #define _T6HLT_PSYNC 0x80
4887 #define _T6HLT_T6PSYNC 0x80
4889 //==============================================================================
4892 //==============================================================================
4895 extern __at(0x041E) __sfr T6CLKCON
;
4936 extern __at(0x041E) volatile __T6CLKCONbits_t T6CLKCONbits
;
4938 #define _T6CLKCON_CS0 0x01
4939 #define _T6CLKCON_T6CS0 0x01
4940 #define _T6CLKCON_CS1 0x02
4941 #define _T6CLKCON_T6CS1 0x02
4942 #define _T6CLKCON_CS2 0x04
4943 #define _T6CLKCON_T6CS2 0x04
4944 #define _T6CLKCON_CS3 0x08
4945 #define _T6CLKCON_T6CS3 0x08
4947 //==============================================================================
4950 //==============================================================================
4953 extern __at(0x041F) __sfr T6RST
;
4971 unsigned T6RSEL0
: 1;
4972 unsigned T6RSEL1
: 1;
4973 unsigned T6RSEL2
: 1;
4974 unsigned T6RSEL3
: 1;
4989 unsigned T6RSEL
: 4;
4994 extern __at(0x041F) volatile __T6RSTbits_t T6RSTbits
;
4996 #define _T6RST_RSEL0 0x01
4997 #define _T6RST_T6RSEL0 0x01
4998 #define _T6RST_RSEL1 0x02
4999 #define _T6RST_T6RSEL1 0x02
5000 #define _T6RST_RSEL2 0x04
5001 #define _T6RST_T6RSEL2 0x04
5002 #define _T6RST_RSEL3 0x08
5003 #define _T6RST_T6RSEL3 0x08
5005 //==============================================================================
5007 extern __at(0x0493) __sfr TMR3
;
5008 extern __at(0x0493) __sfr TMR3L
;
5009 extern __at(0x0494) __sfr TMR3H
;
5011 //==============================================================================
5014 extern __at(0x0495) __sfr T3CON
;
5022 unsigned NOT_SYNC
: 1;
5036 unsigned T3CKPS0
: 1;
5037 unsigned T3CKPS1
: 1;
5044 unsigned TMR3ON
: 1;
5046 unsigned NOT_T3SYNC
: 1;
5050 unsigned TMR3CS0
: 1;
5051 unsigned TMR3CS1
: 1;
5076 unsigned T3CKPS
: 2;
5089 unsigned TMR3CS
: 2;
5099 extern __at(0x0495) volatile __T3CONbits_t T3CONbits
;
5101 #define _T3CON_ON 0x01
5102 #define _T3CON_TMRON 0x01
5103 #define _T3CON_TMR3ON 0x01
5104 #define _T3CON_T3ON 0x01
5105 #define _T3CON_NOT_SYNC 0x04
5106 #define _T3CON_SYNC 0x04
5107 #define _T3CON_NOT_T3SYNC 0x04
5108 #define _T3CON_CKPS0 0x10
5109 #define _T3CON_T3CKPS0 0x10
5110 #define _T3CON_CKPS1 0x20
5111 #define _T3CON_T3CKPS1 0x20
5112 #define _T3CON_CS0 0x40
5113 #define _T3CON_T3CS0 0x40
5114 #define _T3CON_TMR3CS0 0x40
5115 #define _T3CON_CS1 0x80
5116 #define _T3CON_T3CS1 0x80
5117 #define _T3CON_TMR3CS1 0x80
5119 //==============================================================================
5122 //==============================================================================
5125 extern __at(0x0496) __sfr T3GCON
;
5134 unsigned GGO_NOT_DONE
: 1;
5143 unsigned T3GSS0
: 1;
5144 unsigned T3GSS1
: 1;
5145 unsigned T3GVAL
: 1;
5146 unsigned T3GGO_NOT_DONE
: 1;
5147 unsigned T3GSPM
: 1;
5149 unsigned T3GPOL
: 1;
5162 unsigned TMR3GE
: 1;
5178 extern __at(0x0496) volatile __T3GCONbits_t T3GCONbits
;
5180 #define _T3GCON_GSS0 0x01
5181 #define _T3GCON_T3GSS0 0x01
5182 #define _T3GCON_GSS1 0x02
5183 #define _T3GCON_T3GSS1 0x02
5184 #define _T3GCON_GVAL 0x04
5185 #define _T3GCON_T3GVAL 0x04
5186 #define _T3GCON_GGO_NOT_DONE 0x08
5187 #define _T3GCON_T3GGO_NOT_DONE 0x08
5188 #define _T3GCON_GSPM 0x10
5189 #define _T3GCON_T3GSPM 0x10
5190 #define _T3GCON_GTM 0x20
5191 #define _T3GCON_T3GTM 0x20
5192 #define _T3GCON_GPOL 0x40
5193 #define _T3GCON_T3GPOL 0x40
5194 #define _T3GCON_GE 0x80
5195 #define _T3GCON_T3GE 0x80
5196 #define _T3GCON_TMR3GE 0x80
5198 //==============================================================================
5200 extern __at(0x049A) __sfr TMR5
;
5201 extern __at(0x049A) __sfr TMR5L
;
5202 extern __at(0x049B) __sfr TMR5H
;
5204 //==============================================================================
5207 extern __at(0x049C) __sfr T5CON
;
5215 unsigned NOT_SYNC
: 1;
5229 unsigned T5CKPS0
: 1;
5230 unsigned T5CKPS1
: 1;
5237 unsigned TMR5ON
: 1;
5239 unsigned NOT_T5SYNC
: 1;
5243 unsigned TMR5CS0
: 1;
5244 unsigned TMR5CS1
: 1;
5262 unsigned T5CKPS
: 2;
5276 unsigned TMR5CS
: 2;
5292 extern __at(0x049C) volatile __T5CONbits_t T5CONbits
;
5294 #define _T5CON_ON 0x01
5295 #define _T5CON_TMRON 0x01
5296 #define _T5CON_TMR5ON 0x01
5297 #define _T5CON_T5ON 0x01
5298 #define _T5CON_NOT_SYNC 0x04
5299 #define _T5CON_SYNC 0x04
5300 #define _T5CON_NOT_T5SYNC 0x04
5301 #define _T5CON_CKPS0 0x10
5302 #define _T5CON_T5CKPS0 0x10
5303 #define _T5CON_CKPS1 0x20
5304 #define _T5CON_T5CKPS1 0x20
5305 #define _T5CON_CS0 0x40
5306 #define _T5CON_T5CS0 0x40
5307 #define _T5CON_TMR5CS0 0x40
5308 #define _T5CON_CS1 0x80
5309 #define _T5CON_T5CS1 0x80
5310 #define _T5CON_TMR5CS1 0x80
5312 //==============================================================================
5315 //==============================================================================
5318 extern __at(0x049D) __sfr T5GCON
;
5327 unsigned GGO_NOT_DONE
: 1;
5336 unsigned T5GSS0
: 1;
5337 unsigned T5GSS1
: 1;
5338 unsigned T5GVAL
: 1;
5339 unsigned T5GGO_NOT_DONE
: 1;
5340 unsigned T5GSPM
: 1;
5342 unsigned T5GPOL
: 1;
5355 unsigned TMR5GE
: 1;
5371 extern __at(0x049D) volatile __T5GCONbits_t T5GCONbits
;
5373 #define _T5GCON_GSS0 0x01
5374 #define _T5GCON_T5GSS0 0x01
5375 #define _T5GCON_GSS1 0x02
5376 #define _T5GCON_T5GSS1 0x02
5377 #define _T5GCON_GVAL 0x04
5378 #define _T5GCON_T5GVAL 0x04
5379 #define _T5GCON_GGO_NOT_DONE 0x08
5380 #define _T5GCON_T5GGO_NOT_DONE 0x08
5381 #define _T5GCON_GSPM 0x10
5382 #define _T5GCON_T5GSPM 0x10
5383 #define _T5GCON_GTM 0x20
5384 #define _T5GCON_T5GTM 0x20
5385 #define _T5GCON_GPOL 0x40
5386 #define _T5GCON_T5GPOL 0x40
5387 #define _T5GCON_GE 0x80
5388 #define _T5GCON_T5GE 0x80
5389 #define _T5GCON_TMR5GE 0x80
5391 //==============================================================================
5393 extern __at(0x050F) __sfr OPA1NCHS
;
5394 extern __at(0x0510) __sfr OPA1PCHS
;
5396 //==============================================================================
5399 extern __at(0x0511) __sfr OPA1CON
;
5417 unsigned OPA1ORM0
: 1;
5418 unsigned OPA1ORM1
: 1;
5419 unsigned OPA1ORPOL
: 1;
5421 unsigned OPA1UG
: 1;
5424 unsigned OPA1EN
: 1;
5435 unsigned OPA1ORM
: 2;
5440 extern __at(0x0511) volatile __OPA1CONbits_t OPA1CONbits
;
5442 #define _OPA1CON_ORM0 0x01
5443 #define _OPA1CON_OPA1ORM0 0x01
5444 #define _OPA1CON_ORM1 0x02
5445 #define _OPA1CON_OPA1ORM1 0x02
5446 #define _OPA1CON_ORPOL 0x04
5447 #define _OPA1CON_OPA1ORPOL 0x04
5448 #define _OPA1CON_UG 0x10
5449 #define _OPA1CON_OPA1UG 0x10
5450 #define _OPA1CON_EN 0x80
5451 #define _OPA1CON_OPA1EN 0x80
5453 //==============================================================================
5455 extern __at(0x0512) __sfr OPA1ORS
;
5457 //==============================================================================
5460 extern __at(0x0590) __sfr DACLD
;
5464 unsigned DAC1LD
: 1;
5474 extern __at(0x0590) volatile __DACLDbits_t DACLDbits
;
5476 #define _DAC1LD 0x01
5478 //==============================================================================
5481 //==============================================================================
5484 extern __at(0x0591) __sfr DAC1CON0
;
5502 unsigned DACNSS0
: 1;
5504 unsigned DACPSS0
: 1;
5505 unsigned DACPSS1
: 1;
5514 unsigned DAC1NSS0
: 1;
5516 unsigned DAC1PSS0
: 1;
5517 unsigned DAC1PSS1
: 1;
5519 unsigned DACOE1
: 1;
5520 unsigned DAC1FM
: 1;
5521 unsigned DAC1EN
: 1;
5543 unsigned DAC1OE1
: 1;
5551 unsigned DACPSS
: 2;
5565 unsigned DAC1PSS
: 2;
5570 extern __at(0x0591) volatile __DAC1CON0bits_t DAC1CON0bits
;
5572 #define _DAC1CON0_NSS0 0x01
5573 #define _DAC1CON0_DACNSS0 0x01
5574 #define _DAC1CON0_DAC1NSS0 0x01
5575 #define _DAC1CON0_PSS0 0x04
5576 #define _DAC1CON0_DACPSS0 0x04
5577 #define _DAC1CON0_DAC1PSS0 0x04
5578 #define _DAC1CON0_PSS1 0x08
5579 #define _DAC1CON0_DACPSS1 0x08
5580 #define _DAC1CON0_DAC1PSS1 0x08
5581 #define _DAC1CON0_OE1 0x20
5582 #define _DAC1CON0_OE 0x20
5583 #define _DAC1CON0_DACOE1 0x20
5584 #define _DAC1CON0_DACOE 0x20
5585 #define _DAC1CON0_DAC1OE1 0x20
5586 #define _DAC1CON0_FM 0x40
5587 #define _DAC1CON0_DACFM 0x40
5588 #define _DAC1CON0_DAC1FM 0x40
5589 #define _DAC1CON0_EN 0x80
5590 #define _DAC1CON0_DACEN 0x80
5591 #define _DAC1CON0_DAC1EN 0x80
5593 //==============================================================================
5596 //==============================================================================
5599 extern __at(0x0592) __sfr DAC1CON1
;
5617 unsigned DAC1REF0
: 1;
5618 unsigned DAC1REF1
: 1;
5619 unsigned DAC1REF2
: 1;
5620 unsigned DAC1REF3
: 1;
5621 unsigned DAC1REF4
: 1;
5622 unsigned DAC1REF5
: 1;
5623 unsigned DAC1REF6
: 1;
5624 unsigned DAC1REF7
: 1;
5641 unsigned DAC1R0
: 1;
5642 unsigned DAC1R1
: 1;
5643 unsigned DAC1R2
: 1;
5644 unsigned DAC1R3
: 1;
5645 unsigned DAC1R4
: 1;
5646 unsigned DAC1R5
: 1;
5647 unsigned DAC1R6
: 1;
5648 unsigned DAC1R7
: 1;
5652 extern __at(0x0592) volatile __DAC1CON1bits_t DAC1CON1bits
;
5655 #define _DAC1REF0 0x01
5657 #define _DAC1R0 0x01
5659 #define _DAC1REF1 0x02
5661 #define _DAC1R1 0x02
5663 #define _DAC1REF2 0x04
5665 #define _DAC1R2 0x04
5667 #define _DAC1REF3 0x08
5669 #define _DAC1R3 0x08
5671 #define _DAC1REF4 0x10
5673 #define _DAC1R4 0x10
5675 #define _DAC1REF5 0x20
5677 #define _DAC1R5 0x20
5679 #define _DAC1REF6 0x40
5681 #define _DAC1R6 0x40
5683 #define _DAC1REF7 0x80
5685 #define _DAC1R7 0x80
5687 //==============================================================================
5689 extern __at(0x0592) __sfr DAC1REF
;
5691 //==============================================================================
5694 extern __at(0x0592) __sfr DAC1REFL
;
5712 unsigned DAC1REF0
: 1;
5713 unsigned DAC1REF1
: 1;
5714 unsigned DAC1REF2
: 1;
5715 unsigned DAC1REF3
: 1;
5716 unsigned DAC1REF4
: 1;
5717 unsigned DAC1REF5
: 1;
5718 unsigned DAC1REF6
: 1;
5719 unsigned DAC1REF7
: 1;
5736 unsigned DAC1R0
: 1;
5737 unsigned DAC1R1
: 1;
5738 unsigned DAC1R2
: 1;
5739 unsigned DAC1R3
: 1;
5740 unsigned DAC1R4
: 1;
5741 unsigned DAC1R5
: 1;
5742 unsigned DAC1R6
: 1;
5743 unsigned DAC1R7
: 1;
5747 extern __at(0x0592) volatile __DAC1REFLbits_t DAC1REFLbits
;
5749 #define _DAC1REFL_REF0 0x01
5750 #define _DAC1REFL_DAC1REF0 0x01
5751 #define _DAC1REFL_R0 0x01
5752 #define _DAC1REFL_DAC1R0 0x01
5753 #define _DAC1REFL_REF1 0x02
5754 #define _DAC1REFL_DAC1REF1 0x02
5755 #define _DAC1REFL_R1 0x02
5756 #define _DAC1REFL_DAC1R1 0x02
5757 #define _DAC1REFL_REF2 0x04
5758 #define _DAC1REFL_DAC1REF2 0x04
5759 #define _DAC1REFL_R2 0x04
5760 #define _DAC1REFL_DAC1R2 0x04
5761 #define _DAC1REFL_REF3 0x08
5762 #define _DAC1REFL_DAC1REF3 0x08
5763 #define _DAC1REFL_R3 0x08
5764 #define _DAC1REFL_DAC1R3 0x08
5765 #define _DAC1REFL_REF4 0x10
5766 #define _DAC1REFL_DAC1REF4 0x10
5767 #define _DAC1REFL_R4 0x10
5768 #define _DAC1REFL_DAC1R4 0x10
5769 #define _DAC1REFL_REF5 0x20
5770 #define _DAC1REFL_DAC1REF5 0x20
5771 #define _DAC1REFL_R5 0x20
5772 #define _DAC1REFL_DAC1R5 0x20
5773 #define _DAC1REFL_REF6 0x40
5774 #define _DAC1REFL_DAC1REF6 0x40
5775 #define _DAC1REFL_R6 0x40
5776 #define _DAC1REFL_DAC1R6 0x40
5777 #define _DAC1REFL_REF7 0x80
5778 #define _DAC1REFL_DAC1REF7 0x80
5779 #define _DAC1REFL_R7 0x80
5780 #define _DAC1REFL_DAC1R7 0x80
5782 //==============================================================================
5785 //==============================================================================
5788 extern __at(0x0593) __sfr DAC1CON2
;
5806 unsigned DAC1REF8
: 1;
5807 unsigned DAC1REF9
: 1;
5808 unsigned DAC1REF10
: 1;
5809 unsigned DAC1REF11
: 1;
5810 unsigned DAC1REF12
: 1;
5811 unsigned DAC1REF13
: 1;
5812 unsigned DAC1REF14
: 1;
5813 unsigned DAC1REF15
: 1;
5830 unsigned DAC1R8
: 1;
5831 unsigned DAC1R9
: 1;
5832 unsigned DAC1R10
: 1;
5833 unsigned DAC1R11
: 1;
5834 unsigned DAC1R12
: 1;
5835 unsigned DAC1R13
: 1;
5836 unsigned DAC1R14
: 1;
5837 unsigned DAC1R15
: 1;
5841 extern __at(0x0593) volatile __DAC1CON2bits_t DAC1CON2bits
;
5844 #define _DAC1REF8 0x01
5846 #define _DAC1R8 0x01
5848 #define _DAC1REF9 0x02
5850 #define _DAC1R9 0x02
5852 #define _DAC1REF10 0x04
5854 #define _DAC1R10 0x04
5856 #define _DAC1REF11 0x08
5858 #define _DAC1R11 0x08
5860 #define _DAC1REF12 0x10
5862 #define _DAC1R12 0x10
5864 #define _DAC1REF13 0x20
5866 #define _DAC1R13 0x20
5868 #define _DAC1REF14 0x40
5870 #define _DAC1R14 0x40
5872 #define _DAC1REF15 0x80
5874 #define _DAC1R15 0x80
5876 //==============================================================================
5879 //==============================================================================
5882 extern __at(0x0593) __sfr DAC1REFH
;
5900 unsigned DAC1REF8
: 1;
5901 unsigned DAC1REF9
: 1;
5902 unsigned DAC1REF10
: 1;
5903 unsigned DAC1REF11
: 1;
5904 unsigned DAC1REF12
: 1;
5905 unsigned DAC1REF13
: 1;
5906 unsigned DAC1REF14
: 1;
5907 unsigned DAC1REF15
: 1;
5924 unsigned DAC1R8
: 1;
5925 unsigned DAC1R9
: 1;
5926 unsigned DAC1R10
: 1;
5927 unsigned DAC1R11
: 1;
5928 unsigned DAC1R12
: 1;
5929 unsigned DAC1R13
: 1;
5930 unsigned DAC1R14
: 1;
5931 unsigned DAC1R15
: 1;
5935 extern __at(0x0593) volatile __DAC1REFHbits_t DAC1REFHbits
;
5937 #define _DAC1REFH_REF8 0x01
5938 #define _DAC1REFH_DAC1REF8 0x01
5939 #define _DAC1REFH_R8 0x01
5940 #define _DAC1REFH_DAC1R8 0x01
5941 #define _DAC1REFH_REF9 0x02
5942 #define _DAC1REFH_DAC1REF9 0x02
5943 #define _DAC1REFH_R9 0x02
5944 #define _DAC1REFH_DAC1R9 0x02
5945 #define _DAC1REFH_REF10 0x04
5946 #define _DAC1REFH_DAC1REF10 0x04
5947 #define _DAC1REFH_R10 0x04
5948 #define _DAC1REFH_DAC1R10 0x04
5949 #define _DAC1REFH_REF11 0x08
5950 #define _DAC1REFH_DAC1REF11 0x08
5951 #define _DAC1REFH_R11 0x08
5952 #define _DAC1REFH_DAC1R11 0x08
5953 #define _DAC1REFH_REF12 0x10
5954 #define _DAC1REFH_DAC1REF12 0x10
5955 #define _DAC1REFH_R12 0x10
5956 #define _DAC1REFH_DAC1R12 0x10
5957 #define _DAC1REFH_REF13 0x20
5958 #define _DAC1REFH_DAC1REF13 0x20
5959 #define _DAC1REFH_R13 0x20
5960 #define _DAC1REFH_DAC1R13 0x20
5961 #define _DAC1REFH_REF14 0x40
5962 #define _DAC1REFH_DAC1REF14 0x40
5963 #define _DAC1REFH_R14 0x40
5964 #define _DAC1REFH_DAC1R14 0x40
5965 #define _DAC1REFH_REF15 0x80
5966 #define _DAC1REFH_DAC1REF15 0x80
5967 #define _DAC1REFH_R15 0x80
5968 #define _DAC1REFH_DAC1R15 0x80
5970 //==============================================================================
5973 //==============================================================================
5976 extern __at(0x0597) __sfr DAC3CON0
;
5994 unsigned DACNSS
: 1;
5996 unsigned DACPSS0
: 1;
5997 unsigned DACPSS1
: 1;
5999 unsigned DACOE1
: 1;
6006 unsigned DAC3NSS
: 1;
6008 unsigned DAC3PSS0
: 1;
6009 unsigned DAC3PSS1
: 1;
6011 unsigned DAC3OE1
: 1;
6013 unsigned DAC3EN
: 1;
6026 unsigned DACPSS
: 2;
6033 unsigned DAC3PSS
: 2;
6038 extern __at(0x0597) volatile __DAC3CON0bits_t DAC3CON0bits
;
6040 #define _DAC3CON0_NSS 0x01
6041 #define _DAC3CON0_DACNSS 0x01
6042 #define _DAC3CON0_DAC3NSS 0x01
6043 #define _DAC3CON0_PSS0 0x04
6044 #define _DAC3CON0_DACPSS0 0x04
6045 #define _DAC3CON0_DAC3PSS0 0x04
6046 #define _DAC3CON0_PSS1 0x08
6047 #define _DAC3CON0_DACPSS1 0x08
6048 #define _DAC3CON0_DAC3PSS1 0x08
6049 #define _DAC3CON0_OE1 0x20
6050 #define _DAC3CON0_DACOE1 0x20
6051 #define _DAC3CON0_DAC3OE1 0x20
6052 #define _DAC3CON0_EN 0x80
6053 #define _DAC3CON0_DACEN 0x80
6054 #define _DAC3CON0_DAC3EN 0x80
6056 //==============================================================================
6059 //==============================================================================
6062 extern __at(0x0598) __sfr DAC3CON1
;
6085 unsigned DAC3REF5
: 1;
6092 unsigned DAC3R0
: 1;
6093 unsigned DAC3R1
: 1;
6094 unsigned DAC3R2
: 1;
6095 unsigned DAC3R3
: 1;
6096 unsigned DAC3R4
: 1;
6116 unsigned DAC3REF0
: 1;
6117 unsigned DAC3REF1
: 1;
6118 unsigned DAC3REF2
: 1;
6119 unsigned DAC3REF3
: 1;
6120 unsigned DAC3REF4
: 1;
6134 unsigned DAC3REF
: 6;
6157 extern __at(0x0598) volatile __DAC3CON1bits_t DAC3CON1bits
;
6159 #define _DAC3CON1_DACR0 0x01
6160 #define _DAC3CON1_R0 0x01
6161 #define _DAC3CON1_DAC3R0 0x01
6162 #define _DAC3CON1_REF0 0x01
6163 #define _DAC3CON1_DAC3REF0 0x01
6164 #define _DAC3CON1_DACR1 0x02
6165 #define _DAC3CON1_R1 0x02
6166 #define _DAC3CON1_DAC3R1 0x02
6167 #define _DAC3CON1_REF1 0x02
6168 #define _DAC3CON1_DAC3REF1 0x02
6169 #define _DAC3CON1_DACR2 0x04
6170 #define _DAC3CON1_R2 0x04
6171 #define _DAC3CON1_DAC3R2 0x04
6172 #define _DAC3CON1_REF2 0x04
6173 #define _DAC3CON1_DAC3REF2 0x04
6174 #define _DAC3CON1_DACR3 0x08
6175 #define _DAC3CON1_R3 0x08
6176 #define _DAC3CON1_DAC3R3 0x08
6177 #define _DAC3CON1_REF3 0x08
6178 #define _DAC3CON1_DAC3REF3 0x08
6179 #define _DAC3CON1_DACR4 0x10
6180 #define _DAC3CON1_R4 0x10
6181 #define _DAC3CON1_DAC3R4 0x10
6182 #define _DAC3CON1_REF4 0x10
6183 #define _DAC3CON1_DAC3REF4 0x10
6184 #define _DAC3CON1_REF5 0x20
6185 #define _DAC3CON1_DAC3REF5 0x20
6187 //==============================================================================
6190 //==============================================================================
6193 extern __at(0x0598) __sfr DAC3REF
;
6216 unsigned DAC3REF5
: 1;
6223 unsigned DAC3R0
: 1;
6224 unsigned DAC3R1
: 1;
6225 unsigned DAC3R2
: 1;
6226 unsigned DAC3R3
: 1;
6227 unsigned DAC3R4
: 1;
6247 unsigned DAC3REF0
: 1;
6248 unsigned DAC3REF1
: 1;
6249 unsigned DAC3REF2
: 1;
6250 unsigned DAC3REF3
: 1;
6251 unsigned DAC3REF4
: 1;
6271 unsigned DAC3REF
: 6;
6288 extern __at(0x0598) volatile __DAC3REFbits_t DAC3REFbits
;
6290 #define _DAC3REF_DACR0 0x01
6291 #define _DAC3REF_R0 0x01
6292 #define _DAC3REF_DAC3R0 0x01
6293 #define _DAC3REF_REF0 0x01
6294 #define _DAC3REF_DAC3REF0 0x01
6295 #define _DAC3REF_DACR1 0x02
6296 #define _DAC3REF_R1 0x02
6297 #define _DAC3REF_DAC3R1 0x02
6298 #define _DAC3REF_REF1 0x02
6299 #define _DAC3REF_DAC3REF1 0x02
6300 #define _DAC3REF_DACR2 0x04
6301 #define _DAC3REF_R2 0x04
6302 #define _DAC3REF_DAC3R2 0x04
6303 #define _DAC3REF_REF2 0x04
6304 #define _DAC3REF_DAC3REF2 0x04
6305 #define _DAC3REF_DACR3 0x08
6306 #define _DAC3REF_R3 0x08
6307 #define _DAC3REF_DAC3R3 0x08
6308 #define _DAC3REF_REF3 0x08
6309 #define _DAC3REF_DAC3REF3 0x08
6310 #define _DAC3REF_DACR4 0x10
6311 #define _DAC3REF_R4 0x10
6312 #define _DAC3REF_DAC3R4 0x10
6313 #define _DAC3REF_REF4 0x10
6314 #define _DAC3REF_DAC3REF4 0x10
6315 #define _DAC3REF_REF5 0x20
6316 #define _DAC3REF_DAC3REF5 0x20
6318 //==============================================================================
6321 //==============================================================================
6324 extern __at(0x0617) __sfr PWM3DCL
;
6348 unsigned PWM3DC0
: 1;
6349 unsigned PWM3DC1
: 1;
6360 unsigned PWMPW0
: 1;
6361 unsigned PWMPW1
: 1;
6373 unsigned PWM3DC
: 2;
6383 extern __at(0x0617) volatile __PWM3DCLbits_t PWM3DCLbits
;
6386 #define _PWM3DC0 0x40
6387 #define _PWMPW0 0x40
6389 #define _PWM3DC1 0x80
6390 #define _PWMPW1 0x80
6392 //==============================================================================
6395 //==============================================================================
6398 extern __at(0x0618) __sfr PWM3DCH
;
6416 unsigned PWM3DC2
: 1;
6417 unsigned PWM3DC3
: 1;
6418 unsigned PWM3DC4
: 1;
6419 unsigned PWM3DC5
: 1;
6420 unsigned PWM3DC6
: 1;
6421 unsigned PWM3DC7
: 1;
6422 unsigned PWM3DC8
: 1;
6423 unsigned PWM3DC9
: 1;
6428 unsigned PWMPW2
: 1;
6429 unsigned PWMPW3
: 1;
6430 unsigned PWMPW4
: 1;
6431 unsigned PWMPW5
: 1;
6432 unsigned PWMPW6
: 1;
6433 unsigned PWMPW7
: 1;
6434 unsigned PWMPW8
: 1;
6435 unsigned PWMPW9
: 1;
6439 extern __at(0x0618) volatile __PWM3DCHbits_t PWM3DCHbits
;
6442 #define _PWM3DC2 0x01
6443 #define _PWMPW2 0x01
6445 #define _PWM3DC3 0x02
6446 #define _PWMPW3 0x02
6448 #define _PWM3DC4 0x04
6449 #define _PWMPW4 0x04
6451 #define _PWM3DC5 0x08
6452 #define _PWMPW5 0x08
6454 #define _PWM3DC6 0x10
6455 #define _PWMPW6 0x10
6457 #define _PWM3DC7 0x20
6458 #define _PWMPW7 0x20
6460 #define _PWM3DC8 0x40
6461 #define _PWMPW8 0x40
6463 #define _PWM3DC9 0x80
6464 #define _PWMPW9 0x80
6466 //==============================================================================
6469 //==============================================================================
6472 extern __at(0x0619) __sfr PWM3CON
;
6494 unsigned PWM3POL
: 1;
6495 unsigned PWM3OUT
: 1;
6497 unsigned PWM3EN
: 1;
6501 extern __at(0x0619) volatile __PWM3CONbits_t PWM3CONbits
;
6503 #define _PWM3CON_POL 0x10
6504 #define _PWM3CON_PWM3POL 0x10
6505 #define _PWM3CON_OUT 0x20
6506 #define _PWM3CON_PWM3OUT 0x20
6507 #define _PWM3CON_EN 0x80
6508 #define _PWM3CON_PWM3EN 0x80
6510 //==============================================================================
6513 //==============================================================================
6516 extern __at(0x068D) __sfr COG1PHR
;
6534 unsigned G1PHR0
: 1;
6535 unsigned G1PHR1
: 1;
6536 unsigned G1PHR2
: 1;
6537 unsigned G1PHR3
: 1;
6538 unsigned G1PHR4
: 1;
6539 unsigned G1PHR5
: 1;
6557 extern __at(0x068D) volatile __COG1PHRbits_t COG1PHRbits
;
6560 #define _G1PHR0 0x01
6562 #define _G1PHR1 0x02
6564 #define _G1PHR2 0x04
6566 #define _G1PHR3 0x08
6568 #define _G1PHR4 0x10
6570 #define _G1PHR5 0x20
6572 //==============================================================================
6575 //==============================================================================
6578 extern __at(0x068E) __sfr COG1PHF
;
6596 unsigned G1PHF0
: 1;
6597 unsigned G1PHF1
: 1;
6598 unsigned G1PHF2
: 1;
6599 unsigned G1PHF3
: 1;
6600 unsigned G1PHF4
: 1;
6601 unsigned G1PHF5
: 1;
6619 extern __at(0x068E) volatile __COG1PHFbits_t COG1PHFbits
;
6622 #define _G1PHF0 0x01
6624 #define _G1PHF1 0x02
6626 #define _G1PHF2 0x04
6628 #define _G1PHF3 0x08
6630 #define _G1PHF4 0x10
6632 #define _G1PHF5 0x20
6634 //==============================================================================
6637 //==============================================================================
6640 extern __at(0x068F) __sfr COG1BLKR
;
6658 unsigned G1BLKR0
: 1;
6659 unsigned G1BLKR1
: 1;
6660 unsigned G1BLKR2
: 1;
6661 unsigned G1BLKR3
: 1;
6662 unsigned G1BLKR4
: 1;
6663 unsigned G1BLKR5
: 1;
6676 unsigned G1BLKR
: 6;
6681 extern __at(0x068F) volatile __COG1BLKRbits_t COG1BLKRbits
;
6684 #define _G1BLKR0 0x01
6686 #define _G1BLKR1 0x02
6688 #define _G1BLKR2 0x04
6690 #define _G1BLKR3 0x08
6692 #define _G1BLKR4 0x10
6694 #define _G1BLKR5 0x20
6696 //==============================================================================
6699 //==============================================================================
6702 extern __at(0x0690) __sfr COG1BLKF
;
6720 unsigned G1BLKF0
: 1;
6721 unsigned G1BLKF1
: 1;
6722 unsigned G1BLKF2
: 1;
6723 unsigned G1BLKF3
: 1;
6724 unsigned G1BLKF4
: 1;
6725 unsigned G1BLKF5
: 1;
6738 unsigned G1BLKF
: 6;
6743 extern __at(0x0690) volatile __COG1BLKFbits_t COG1BLKFbits
;
6746 #define _G1BLKF0 0x01
6748 #define _G1BLKF1 0x02
6750 #define _G1BLKF2 0x04
6752 #define _G1BLKF3 0x08
6754 #define _G1BLKF4 0x10
6756 #define _G1BLKF5 0x20
6758 //==============================================================================
6761 //==============================================================================
6764 extern __at(0x0691) __sfr COG1DBR
;
6782 unsigned G1DBR0
: 1;
6783 unsigned G1DBR1
: 1;
6784 unsigned G1DBR2
: 1;
6785 unsigned G1DBR3
: 1;
6786 unsigned G1DBR4
: 1;
6787 unsigned G1DBR5
: 1;
6805 extern __at(0x0691) volatile __COG1DBRbits_t COG1DBRbits
;
6808 #define _G1DBR0 0x01
6810 #define _G1DBR1 0x02
6812 #define _G1DBR2 0x04
6814 #define _G1DBR3 0x08
6816 #define _G1DBR4 0x10
6818 #define _G1DBR5 0x20
6820 //==============================================================================
6823 //==============================================================================
6826 extern __at(0x0692) __sfr COG1DBF
;
6844 unsigned G1DBF0
: 1;
6845 unsigned G1DBF1
: 1;
6846 unsigned G1DBF2
: 1;
6847 unsigned G1DBF3
: 1;
6848 unsigned G1DBF4
: 1;
6849 unsigned G1DBF5
: 1;
6867 extern __at(0x0692) volatile __COG1DBFbits_t COG1DBFbits
;
6870 #define _G1DBF0 0x01
6872 #define _G1DBF1 0x02
6874 #define _G1DBF2 0x04
6876 #define _G1DBF3 0x08
6878 #define _G1DBF4 0x10
6880 #define _G1DBF5 0x20
6882 //==============================================================================
6885 //==============================================================================
6888 extern __at(0x0693) __sfr COG1CON0
;
6943 extern __at(0x0693) volatile __COG1CON0bits_t COG1CON0bits
;
6945 #define _COG1CON0_MD0 0x01
6946 #define _COG1CON0_G1MD0 0x01
6947 #define _COG1CON0_MD1 0x02
6948 #define _COG1CON0_G1MD1 0x02
6949 #define _COG1CON0_MD2 0x04
6950 #define _COG1CON0_G1MD2 0x04
6951 #define _COG1CON0_CS0 0x08
6952 #define _COG1CON0_G1CS0 0x08
6953 #define _COG1CON0_CS1 0x10
6954 #define _COG1CON0_G1CS1 0x10
6955 #define _COG1CON0_LD 0x40
6956 #define _COG1CON0_G1LD 0x40
6957 #define _COG1CON0_EN 0x80
6958 #define _COG1CON0_G1EN 0x80
6960 //==============================================================================
6963 //==============================================================================
6966 extern __at(0x0694) __sfr COG1CON1
;
6984 unsigned G1POLA
: 1;
6985 unsigned G1POLB
: 1;
6986 unsigned G1POLC
: 1;
6987 unsigned G1POLD
: 1;
6990 unsigned G1FDBS
: 1;
6991 unsigned G1RDBS
: 1;
6995 extern __at(0x0694) volatile __COG1CON1bits_t COG1CON1bits
;
6998 #define _G1POLA 0x01
7000 #define _G1POLB 0x02
7002 #define _G1POLC 0x04
7004 #define _G1POLD 0x08
7006 #define _G1FDBS 0x40
7008 #define _G1RDBS 0x80
7010 //==============================================================================
7013 //==============================================================================
7016 extern __at(0x0695) __sfr COG1RIS0
;
7034 unsigned G1RIS0
: 1;
7035 unsigned G1RIS1
: 1;
7036 unsigned G1RIS2
: 1;
7037 unsigned G1RIS3
: 1;
7038 unsigned G1RIS4
: 1;
7039 unsigned G1RIS5
: 1;
7040 unsigned G1RIS6
: 1;
7041 unsigned G1RIS7
: 1;
7045 extern __at(0x0695) volatile __COG1RIS0bits_t COG1RIS0bits
;
7048 #define _G1RIS0 0x01
7050 #define _G1RIS1 0x02
7052 #define _G1RIS2 0x04
7054 #define _G1RIS3 0x08
7056 #define _G1RIS4 0x10
7058 #define _G1RIS5 0x20
7060 #define _G1RIS6 0x40
7062 #define _G1RIS7 0x80
7064 //==============================================================================
7067 //==============================================================================
7070 extern __at(0x0696) __sfr COG1RIS1
;
7088 unsigned G1RIS8
: 1;
7089 unsigned G1RIS9
: 1;
7090 unsigned G1RIS10
: 1;
7091 unsigned G1RIS11
: 1;
7092 unsigned G1RIS12
: 1;
7093 unsigned G1RIS13
: 1;
7094 unsigned G1RIS14
: 1;
7099 extern __at(0x0696) volatile __COG1RIS1bits_t COG1RIS1bits
;
7102 #define _G1RIS8 0x01
7104 #define _G1RIS9 0x02
7106 #define _G1RIS10 0x04
7108 #define _G1RIS11 0x08
7110 #define _G1RIS12 0x10
7112 #define _G1RIS13 0x20
7114 #define _G1RIS14 0x40
7116 //==============================================================================
7119 //==============================================================================
7122 extern __at(0x0697) __sfr COG1RSIM0
;
7140 unsigned G1RSIM0
: 1;
7141 unsigned G1RSIM1
: 1;
7142 unsigned G1RSIM2
: 1;
7143 unsigned G1RSIM3
: 1;
7144 unsigned G1RSIM4
: 1;
7145 unsigned G1RSIM5
: 1;
7146 unsigned G1RSIM6
: 1;
7147 unsigned G1RSIM7
: 1;
7149 } __COG1RSIM0bits_t
;
7151 extern __at(0x0697) volatile __COG1RSIM0bits_t COG1RSIM0bits
;
7154 #define _G1RSIM0 0x01
7156 #define _G1RSIM1 0x02
7158 #define _G1RSIM2 0x04
7160 #define _G1RSIM3 0x08
7162 #define _G1RSIM4 0x10
7164 #define _G1RSIM5 0x20
7166 #define _G1RSIM6 0x40
7168 #define _G1RSIM7 0x80
7170 //==============================================================================
7173 //==============================================================================
7176 extern __at(0x0698) __sfr COG1RSIM1
;
7184 unsigned RSIM10
: 1;
7185 unsigned RSIM11
: 1;
7186 unsigned RSIM12
: 1;
7187 unsigned RSIM13
: 1;
7188 unsigned RSIM14
: 1;
7194 unsigned G1RSIM8
: 1;
7195 unsigned G1RSIM9
: 1;
7196 unsigned G1RSIM10
: 1;
7197 unsigned G1RSIM11
: 1;
7198 unsigned G1RSIM12
: 1;
7199 unsigned G1RSIM13
: 1;
7200 unsigned G1RSIM14
: 1;
7203 } __COG1RSIM1bits_t
;
7205 extern __at(0x0698) volatile __COG1RSIM1bits_t COG1RSIM1bits
;
7208 #define _G1RSIM8 0x01
7210 #define _G1RSIM9 0x02
7211 #define _RSIM10 0x04
7212 #define _G1RSIM10 0x04
7213 #define _RSIM11 0x08
7214 #define _G1RSIM11 0x08
7215 #define _RSIM12 0x10
7216 #define _G1RSIM12 0x10
7217 #define _RSIM13 0x20
7218 #define _G1RSIM13 0x20
7219 #define _RSIM14 0x40
7220 #define _G1RSIM14 0x40
7222 //==============================================================================
7225 //==============================================================================
7228 extern __at(0x0699) __sfr COG1FIS0
;
7246 unsigned G1FIS0
: 1;
7247 unsigned G1FIS1
: 1;
7248 unsigned G1FIS2
: 1;
7249 unsigned G1FIS3
: 1;
7250 unsigned G1FIS4
: 1;
7251 unsigned G1FIS5
: 1;
7252 unsigned G1FIS6
: 1;
7253 unsigned G1FIS7
: 1;
7257 extern __at(0x0699) volatile __COG1FIS0bits_t COG1FIS0bits
;
7260 #define _G1FIS0 0x01
7262 #define _G1FIS1 0x02
7264 #define _G1FIS2 0x04
7266 #define _G1FIS3 0x08
7268 #define _G1FIS4 0x10
7270 #define _G1FIS5 0x20
7272 #define _G1FIS6 0x40
7274 #define _G1FIS7 0x80
7276 //==============================================================================
7279 //==============================================================================
7282 extern __at(0x069A) __sfr COG1FIS1
;
7300 unsigned G1FIS8
: 1;
7301 unsigned G1FIS9
: 1;
7302 unsigned G1FIS10
: 1;
7303 unsigned G1FIS11
: 1;
7304 unsigned G1FIS12
: 1;
7305 unsigned G1FIS13
: 1;
7306 unsigned G1FIS14
: 1;
7311 extern __at(0x069A) volatile __COG1FIS1bits_t COG1FIS1bits
;
7314 #define _G1FIS8 0x01
7316 #define _G1FIS9 0x02
7318 #define _G1FIS10 0x04
7320 #define _G1FIS11 0x08
7322 #define _G1FIS12 0x10
7324 #define _G1FIS13 0x20
7326 #define _G1FIS14 0x40
7328 //==============================================================================
7331 //==============================================================================
7334 extern __at(0x069B) __sfr COG1FSIM0
;
7352 unsigned G1FSIM0
: 1;
7353 unsigned G1FSIM1
: 1;
7354 unsigned G1FSIM2
: 1;
7355 unsigned G1FSIM3
: 1;
7356 unsigned G1FSIM4
: 1;
7357 unsigned G1FSIM5
: 1;
7358 unsigned G1FSIM6
: 1;
7359 unsigned G1FSIM7
: 1;
7361 } __COG1FSIM0bits_t
;
7363 extern __at(0x069B) volatile __COG1FSIM0bits_t COG1FSIM0bits
;
7366 #define _G1FSIM0 0x01
7368 #define _G1FSIM1 0x02
7370 #define _G1FSIM2 0x04
7372 #define _G1FSIM3 0x08
7374 #define _G1FSIM4 0x10
7376 #define _G1FSIM5 0x20
7378 #define _G1FSIM6 0x40
7380 #define _G1FSIM7 0x80
7382 //==============================================================================
7385 //==============================================================================
7388 extern __at(0x069C) __sfr COG1FSIM1
;
7396 unsigned FSIM10
: 1;
7397 unsigned FSIM11
: 1;
7398 unsigned FSIM12
: 1;
7399 unsigned FSIM13
: 1;
7400 unsigned FSIM14
: 1;
7406 unsigned G1FSIM8
: 1;
7407 unsigned G1FSIM9
: 1;
7408 unsigned G1FSIM10
: 1;
7409 unsigned G1FSIM11
: 1;
7410 unsigned G1FSIM12
: 1;
7411 unsigned G1FSIM13
: 1;
7412 unsigned G1FSIM14
: 1;
7415 } __COG1FSIM1bits_t
;
7417 extern __at(0x069C) volatile __COG1FSIM1bits_t COG1FSIM1bits
;
7420 #define _G1FSIM8 0x01
7422 #define _G1FSIM9 0x02
7423 #define _FSIM10 0x04
7424 #define _G1FSIM10 0x04
7425 #define _FSIM11 0x08
7426 #define _G1FSIM11 0x08
7427 #define _FSIM12 0x10
7428 #define _G1FSIM12 0x10
7429 #define _FSIM13 0x20
7430 #define _G1FSIM13 0x20
7431 #define _FSIM14 0x40
7432 #define _G1FSIM14 0x40
7434 //==============================================================================
7437 //==============================================================================
7440 extern __at(0x069D) __sfr COG1ASD0
;
7448 unsigned ASDAC0
: 1;
7449 unsigned ASDAC1
: 1;
7450 unsigned ASDBD0
: 1;
7451 unsigned ASDBD1
: 1;
7460 unsigned G1ASDAC0
: 1;
7461 unsigned G1ASDAC1
: 1;
7462 unsigned G1ASDBD0
: 1;
7463 unsigned G1ASDBD1
: 1;
7476 unsigned G1ARSEN
: 1;
7488 unsigned G1ASREN
: 1;
7495 unsigned G1ASDAC
: 2;
7516 unsigned G1ASDBD
: 2;
7521 extern __at(0x069D) volatile __COG1ASD0bits_t COG1ASD0bits
;
7523 #define _ASDAC0 0x04
7524 #define _G1ASDAC0 0x04
7525 #define _ASDAC1 0x08
7526 #define _G1ASDAC1 0x08
7527 #define _ASDBD0 0x10
7528 #define _G1ASDBD0 0x10
7529 #define _ASDBD1 0x20
7530 #define _G1ASDBD1 0x20
7533 #define _G1ARSEN 0x40
7534 #define _G1ASREN 0x40
7538 //==============================================================================
7541 //==============================================================================
7544 extern __at(0x069E) __sfr COG1ASD1
;
7562 unsigned G1AS0E
: 1;
7563 unsigned G1AS1E
: 1;
7564 unsigned G1AS2E
: 1;
7565 unsigned G1AS3E
: 1;
7566 unsigned G1AS4E
: 1;
7567 unsigned G1AS5E
: 1;
7568 unsigned G1AS6E
: 1;
7569 unsigned G1AS7E
: 1;
7573 extern __at(0x069E) volatile __COG1ASD1bits_t COG1ASD1bits
;
7576 #define _G1AS0E 0x01
7578 #define _G1AS1E 0x02
7580 #define _G1AS2E 0x04
7582 #define _G1AS3E 0x08
7584 #define _G1AS4E 0x10
7586 #define _G1AS5E 0x20
7588 #define _G1AS6E 0x40
7590 #define _G1AS7E 0x80
7592 //==============================================================================
7595 //==============================================================================
7598 extern __at(0x069F) __sfr COG1STR
;
7616 unsigned G1STRA
: 1;
7617 unsigned G1STRB
: 1;
7618 unsigned G1STRC
: 1;
7619 unsigned G1STRD
: 1;
7620 unsigned G1SDATA
: 1;
7621 unsigned G1SDATB
: 1;
7622 unsigned G1SDATC
: 1;
7623 unsigned G1SDATD
: 1;
7627 extern __at(0x069F) volatile __COG1STRbits_t COG1STRbits
;
7630 #define _G1STRA 0x01
7632 #define _G1STRB 0x02
7634 #define _G1STRC 0x04
7636 #define _G1STRD 0x08
7638 #define _G1SDATA 0x10
7640 #define _G1SDATB 0x20
7642 #define _G1SDATC 0x40
7644 #define _G1SDATD 0x80
7646 //==============================================================================
7649 //==============================================================================
7652 extern __at(0x0794) __sfr PRG1RTSS
;
7670 unsigned RG1RTSS0
: 1;
7671 unsigned RG1RTSS1
: 1;
7672 unsigned RG1RTSS2
: 1;
7673 unsigned RG1RTSS3
: 1;
7682 unsigned RG1RTSS
: 4;
7693 extern __at(0x0794) volatile __PRG1RTSSbits_t PRG1RTSSbits
;
7696 #define _RG1RTSS0 0x01
7698 #define _RG1RTSS1 0x02
7700 #define _RG1RTSS2 0x04
7702 #define _RG1RTSS3 0x08
7704 //==============================================================================
7707 //==============================================================================
7710 extern __at(0x0795) __sfr PRG1FTSS
;
7728 unsigned RG1FTSS0
: 1;
7729 unsigned RG1FTSS1
: 1;
7730 unsigned RG1FTSS2
: 1;
7731 unsigned RG1FTSS3
: 1;
7746 unsigned RG1FTSS
: 4;
7751 extern __at(0x0795) volatile __PRG1FTSSbits_t PRG1FTSSbits
;
7754 #define _RG1FTSS0 0x01
7756 #define _RG1FTSS1 0x02
7758 #define _RG1FTSS2 0x04
7760 #define _RG1FTSS3 0x08
7762 //==============================================================================
7765 //==============================================================================
7768 extern __at(0x0796) __sfr PRG1INS
;
7786 unsigned RG1INS0
: 1;
7787 unsigned RG1INS1
: 1;
7788 unsigned RG1INS2
: 1;
7789 unsigned RG1INS3
: 1;
7804 unsigned RG1INS
: 4;
7809 extern __at(0x0796) volatile __PRG1INSbits_t PRG1INSbits
;
7812 #define _RG1INS0 0x01
7814 #define _RG1INS1 0x02
7816 #define _RG1INS2 0x04
7818 #define _RG1INS3 0x08
7820 //==============================================================================
7823 //==============================================================================
7826 extern __at(0x0797) __sfr PRG1CON0
;
7846 unsigned RG1MODE0
: 1;
7847 unsigned RG1MODE1
: 1;
7848 unsigned RG1REDG
: 1;
7849 unsigned RG1FEDG
: 1;
7864 unsigned RG1MODE
: 2;
7869 extern __at(0x0797) volatile __PRG1CON0bits_t PRG1CON0bits
;
7871 #define _PRG1CON0_GO 0x01
7872 #define _PRG1CON0_RG1GO 0x01
7873 #define _PRG1CON0_OS 0x02
7874 #define _PRG1CON0_RG1OS 0x02
7875 #define _PRG1CON0_MODE0 0x04
7876 #define _PRG1CON0_RG1MODE0 0x04
7877 #define _PRG1CON0_MODE1 0x08
7878 #define _PRG1CON0_RG1MODE1 0x08
7879 #define _PRG1CON0_REDG 0x10
7880 #define _PRG1CON0_RG1REDG 0x10
7881 #define _PRG1CON0_FEDG 0x20
7882 #define _PRG1CON0_RG1FEDG 0x20
7883 #define _PRG1CON0_EN 0x80
7884 #define _PRG1CON0_RG1EN 0x80
7886 //==============================================================================
7889 //==============================================================================
7892 extern __at(0x0798) __sfr PRG1CON1
;
7910 unsigned RG1RPOL
: 1;
7911 unsigned RG1FPOL
: 1;
7912 unsigned RG1RDY
: 1;
7921 extern __at(0x0798) volatile __PRG1CON1bits_t PRG1CON1bits
;
7924 #define _RG1RPOL 0x01
7926 #define _RG1FPOL 0x02
7928 #define _RG1RDY 0x04
7930 //==============================================================================
7933 //==============================================================================
7936 extern __at(0x0799) __sfr PRG1CON2
;
7954 unsigned RG1ISET0
: 1;
7955 unsigned RG1ISET1
: 1;
7956 unsigned RG1ISET2
: 1;
7957 unsigned RG1ISET3
: 1;
7958 unsigned RG1ISET4
: 1;
7966 unsigned RG1ISET
: 5;
7977 extern __at(0x0799) volatile __PRG1CON2bits_t PRG1CON2bits
;
7980 #define _RG1ISET0 0x01
7982 #define _RG1ISET1 0x02
7984 #define _RG1ISET2 0x04
7986 #define _RG1ISET3 0x08
7988 #define _RG1ISET4 0x10
7990 //==============================================================================
7993 //==============================================================================
7996 extern __at(0x0D8E) __sfr PWMEN
;
8004 unsigned MPWM5EN
: 1;
8010 extern __at(0x0D8E) volatile __PWMENbits_t PWMENbits
;
8012 #define _MPWM5EN 0x10
8014 //==============================================================================
8017 //==============================================================================
8020 extern __at(0x0D8F) __sfr PWMLD
;
8028 unsigned MPWM5LD
: 1;
8034 extern __at(0x0D8F) volatile __PWMLDbits_t PWMLDbits
;
8036 #define _MPWM5LD 0x10
8038 //==============================================================================
8041 //==============================================================================
8044 extern __at(0x0D90) __sfr PWMOUT
;
8052 unsigned MPWM5OUT
: 1;
8058 extern __at(0x0D90) volatile __PWMOUTbits_t PWMOUTbits
;
8060 #define _MPWM5OUT 0x10
8062 //==============================================================================
8064 extern __at(0x0D91) __sfr PWM5PH
;
8066 //==============================================================================
8069 extern __at(0x0D91) __sfr PWM5PHL
;
8073 unsigned PWM5PHL0
: 1;
8074 unsigned PWM5PHL1
: 1;
8075 unsigned PWM5PHL2
: 1;
8076 unsigned PWM5PHL3
: 1;
8077 unsigned PWM5PHL4
: 1;
8078 unsigned PWM5PHL5
: 1;
8079 unsigned PWM5PHL6
: 1;
8080 unsigned PWM5PHL7
: 1;
8083 extern __at(0x0D91) volatile __PWM5PHLbits_t PWM5PHLbits
;
8085 #define _PWM5PHL0 0x01
8086 #define _PWM5PHL1 0x02
8087 #define _PWM5PHL2 0x04
8088 #define _PWM5PHL3 0x08
8089 #define _PWM5PHL4 0x10
8090 #define _PWM5PHL5 0x20
8091 #define _PWM5PHL6 0x40
8092 #define _PWM5PHL7 0x80
8094 //==============================================================================
8097 //==============================================================================
8100 extern __at(0x0D92) __sfr PWM5PHH
;
8104 unsigned PWM5PHH0
: 1;
8105 unsigned PWM5PHH1
: 1;
8106 unsigned PWM5PHH2
: 1;
8107 unsigned PWM5PHH3
: 1;
8108 unsigned PWM5PHH4
: 1;
8109 unsigned PWM5PHH5
: 1;
8110 unsigned PWM5PHH6
: 1;
8111 unsigned PWM5PHH7
: 1;
8114 extern __at(0x0D92) volatile __PWM5PHHbits_t PWM5PHHbits
;
8116 #define _PWM5PHH0 0x01
8117 #define _PWM5PHH1 0x02
8118 #define _PWM5PHH2 0x04
8119 #define _PWM5PHH3 0x08
8120 #define _PWM5PHH4 0x10
8121 #define _PWM5PHH5 0x20
8122 #define _PWM5PHH6 0x40
8123 #define _PWM5PHH7 0x80
8125 //==============================================================================
8127 extern __at(0x0D93) __sfr PWM5DC
;
8129 //==============================================================================
8132 extern __at(0x0D93) __sfr PWM5DCL
;
8136 unsigned PWM5DCL0
: 1;
8137 unsigned PWM5DCL1
: 1;
8138 unsigned PWM5DCL2
: 1;
8139 unsigned PWM5DCL3
: 1;
8140 unsigned PWM5DCL4
: 1;
8141 unsigned PWM5DCL5
: 1;
8142 unsigned PWM5DCL6
: 1;
8143 unsigned PWM5DCL7
: 1;
8146 extern __at(0x0D93) volatile __PWM5DCLbits_t PWM5DCLbits
;
8148 #define _PWM5DCL0 0x01
8149 #define _PWM5DCL1 0x02
8150 #define _PWM5DCL2 0x04
8151 #define _PWM5DCL3 0x08
8152 #define _PWM5DCL4 0x10
8153 #define _PWM5DCL5 0x20
8154 #define _PWM5DCL6 0x40
8155 #define _PWM5DCL7 0x80
8157 //==============================================================================
8160 //==============================================================================
8163 extern __at(0x0D94) __sfr PWM5DCH
;
8167 unsigned PWM5DCH0
: 1;
8168 unsigned PWM5DCH1
: 1;
8169 unsigned PWM5DCH2
: 1;
8170 unsigned PWM5DCH3
: 1;
8171 unsigned PWM5DCH4
: 1;
8172 unsigned PWM5DCH5
: 1;
8173 unsigned PWM5DCH6
: 1;
8174 unsigned PWM5DCH7
: 1;
8177 extern __at(0x0D94) volatile __PWM5DCHbits_t PWM5DCHbits
;
8179 #define _PWM5DCH0 0x01
8180 #define _PWM5DCH1 0x02
8181 #define _PWM5DCH2 0x04
8182 #define _PWM5DCH3 0x08
8183 #define _PWM5DCH4 0x10
8184 #define _PWM5DCH5 0x20
8185 #define _PWM5DCH6 0x40
8186 #define _PWM5DCH7 0x80
8188 //==============================================================================
8190 extern __at(0x0D95) __sfr PWM5PR
;
8192 //==============================================================================
8195 extern __at(0x0D95) __sfr PWM5PRL
;
8199 unsigned PWM5PRL0
: 1;
8200 unsigned PWM5PRL1
: 1;
8201 unsigned PWM5PRL2
: 1;
8202 unsigned PWM5PRL3
: 1;
8203 unsigned PWM5PRL4
: 1;
8204 unsigned PWM5PRL5
: 1;
8205 unsigned PWM5PRL6
: 1;
8206 unsigned PWM5PRL7
: 1;
8209 extern __at(0x0D95) volatile __PWM5PRLbits_t PWM5PRLbits
;
8211 #define _PWM5PRL0 0x01
8212 #define _PWM5PRL1 0x02
8213 #define _PWM5PRL2 0x04
8214 #define _PWM5PRL3 0x08
8215 #define _PWM5PRL4 0x10
8216 #define _PWM5PRL5 0x20
8217 #define _PWM5PRL6 0x40
8218 #define _PWM5PRL7 0x80
8220 //==============================================================================
8223 //==============================================================================
8226 extern __at(0x0D96) __sfr PWM5PRH
;
8230 unsigned PWM5PRH0
: 1;
8231 unsigned PWM5PRH1
: 1;
8232 unsigned PWM5PRH2
: 1;
8233 unsigned PWM5PRH3
: 1;
8234 unsigned PWM5PRH4
: 1;
8235 unsigned PWM5PRH5
: 1;
8236 unsigned PWM5PRH6
: 1;
8237 unsigned PWM5PRH7
: 1;
8240 extern __at(0x0D96) volatile __PWM5PRHbits_t PWM5PRHbits
;
8242 #define _PWM5PRH0 0x01
8243 #define _PWM5PRH1 0x02
8244 #define _PWM5PRH2 0x04
8245 #define _PWM5PRH3 0x08
8246 #define _PWM5PRH4 0x10
8247 #define _PWM5PRH5 0x20
8248 #define _PWM5PRH6 0x40
8249 #define _PWM5PRH7 0x80
8251 //==============================================================================
8253 extern __at(0x0D97) __sfr PWM5OF
;
8255 //==============================================================================
8258 extern __at(0x0D97) __sfr PWM5OFL
;
8262 unsigned PWM5OFL0
: 1;
8263 unsigned PWM5OFL1
: 1;
8264 unsigned PWM5OFL2
: 1;
8265 unsigned PWM5OFL3
: 1;
8266 unsigned PWM5OFL4
: 1;
8267 unsigned PWM5OFL5
: 1;
8268 unsigned PWM5OFL6
: 1;
8269 unsigned PWM5OFL7
: 1;
8272 extern __at(0x0D97) volatile __PWM5OFLbits_t PWM5OFLbits
;
8274 #define _PWM5OFL0 0x01
8275 #define _PWM5OFL1 0x02
8276 #define _PWM5OFL2 0x04
8277 #define _PWM5OFL3 0x08
8278 #define _PWM5OFL4 0x10
8279 #define _PWM5OFL5 0x20
8280 #define _PWM5OFL6 0x40
8281 #define _PWM5OFL7 0x80
8283 //==============================================================================
8286 //==============================================================================
8289 extern __at(0x0D98) __sfr PWM5OFH
;
8293 unsigned PWM5OFH0
: 1;
8294 unsigned PWM5OFH1
: 1;
8295 unsigned PWM5OFH2
: 1;
8296 unsigned PWM5OFH3
: 1;
8297 unsigned PWM5OFH4
: 1;
8298 unsigned PWM5OFH5
: 1;
8299 unsigned PWM5OFH6
: 1;
8300 unsigned PWM5OFH7
: 1;
8303 extern __at(0x0D98) volatile __PWM5OFHbits_t PWM5OFHbits
;
8305 #define _PWM5OFH0 0x01
8306 #define _PWM5OFH1 0x02
8307 #define _PWM5OFH2 0x04
8308 #define _PWM5OFH3 0x08
8309 #define _PWM5OFH4 0x10
8310 #define _PWM5OFH5 0x20
8311 #define _PWM5OFH6 0x40
8312 #define _PWM5OFH7 0x80
8314 //==============================================================================
8316 extern __at(0x0D99) __sfr PWM5TMR
;
8318 //==============================================================================
8321 extern __at(0x0D99) __sfr PWM5TMRL
;
8325 unsigned PWM5TMRL0
: 1;
8326 unsigned PWM5TMRL1
: 1;
8327 unsigned PWM5TMRL2
: 1;
8328 unsigned PWM5TMRL3
: 1;
8329 unsigned PWM5TMRL4
: 1;
8330 unsigned PWM5TMRL5
: 1;
8331 unsigned PWM5TMRL6
: 1;
8332 unsigned PWM5TMRL7
: 1;
8335 extern __at(0x0D99) volatile __PWM5TMRLbits_t PWM5TMRLbits
;
8337 #define _PWM5TMRL0 0x01
8338 #define _PWM5TMRL1 0x02
8339 #define _PWM5TMRL2 0x04
8340 #define _PWM5TMRL3 0x08
8341 #define _PWM5TMRL4 0x10
8342 #define _PWM5TMRL5 0x20
8343 #define _PWM5TMRL6 0x40
8344 #define _PWM5TMRL7 0x80
8346 //==============================================================================
8349 //==============================================================================
8352 extern __at(0x0D9A) __sfr PWM5TMRH
;
8356 unsigned PWM5TMRH0
: 1;
8357 unsigned PWM5TMRH1
: 1;
8358 unsigned PWM5TMRH2
: 1;
8359 unsigned PWM5TMRH3
: 1;
8360 unsigned PWM5TMRH4
: 1;
8361 unsigned PWM5TMRH5
: 1;
8362 unsigned PWM5TMRH6
: 1;
8363 unsigned PWM5TMRH7
: 1;
8366 extern __at(0x0D9A) volatile __PWM5TMRHbits_t PWM5TMRHbits
;
8368 #define _PWM5TMRH0 0x01
8369 #define _PWM5TMRH1 0x02
8370 #define _PWM5TMRH2 0x04
8371 #define _PWM5TMRH3 0x08
8372 #define _PWM5TMRH4 0x10
8373 #define _PWM5TMRH5 0x20
8374 #define _PWM5TMRH6 0x40
8375 #define _PWM5TMRH7 0x80
8377 //==============================================================================
8380 //==============================================================================
8383 extern __at(0x0D9B) __sfr PWM5CON
;
8391 unsigned PWM5MODE0
: 1;
8392 unsigned PWM5MODE1
: 1;
8405 unsigned PWM5POL
: 1;
8406 unsigned PWM5OUT
: 1;
8408 unsigned PWM5EN
: 1;
8421 unsigned PWM5MODE
: 2;
8426 extern __at(0x0D9B) volatile __PWM5CONbits_t PWM5CONbits
;
8428 #define _PWM5CON_PWM5MODE0 0x04
8429 #define _PWM5CON_MODE0 0x04
8430 #define _PWM5CON_PWM5MODE1 0x08
8431 #define _PWM5CON_MODE1 0x08
8432 #define _PWM5CON_POL 0x10
8433 #define _PWM5CON_PWM5POL 0x10
8434 #define _PWM5CON_OUT 0x20
8435 #define _PWM5CON_PWM5OUT 0x20
8436 #define _PWM5CON_EN 0x80
8437 #define _PWM5CON_PWM5EN 0x80
8439 //==============================================================================
8442 //==============================================================================
8445 extern __at(0x0D9C) __sfr PWM5INTCON
;
8463 unsigned PWM5PRIE
: 1;
8464 unsigned PWM5DCIE
: 1;
8465 unsigned PWM5PHIE
: 1;
8466 unsigned PWM5OFIE
: 1;
8472 } __PWM5INTCONbits_t
;
8474 extern __at(0x0D9C) volatile __PWM5INTCONbits_t PWM5INTCONbits
;
8477 #define _PWM5PRIE 0x01
8479 #define _PWM5DCIE 0x02
8481 #define _PWM5PHIE 0x04
8483 #define _PWM5OFIE 0x08
8485 //==============================================================================
8488 //==============================================================================
8491 extern __at(0x0D9C) __sfr PWM5INTE
;
8509 unsigned PWM5PRIE
: 1;
8510 unsigned PWM5DCIE
: 1;
8511 unsigned PWM5PHIE
: 1;
8512 unsigned PWM5OFIE
: 1;
8520 extern __at(0x0D9C) volatile __PWM5INTEbits_t PWM5INTEbits
;
8522 #define _PWM5INTE_PRIE 0x01
8523 #define _PWM5INTE_PWM5PRIE 0x01
8524 #define _PWM5INTE_DCIE 0x02
8525 #define _PWM5INTE_PWM5DCIE 0x02
8526 #define _PWM5INTE_PHIE 0x04
8527 #define _PWM5INTE_PWM5PHIE 0x04
8528 #define _PWM5INTE_OFIE 0x08
8529 #define _PWM5INTE_PWM5OFIE 0x08
8531 //==============================================================================
8534 //==============================================================================
8537 extern __at(0x0D9D) __sfr PWM5INTF
;
8555 unsigned PWM5PRIF
: 1;
8556 unsigned PWM5DCIF
: 1;
8557 unsigned PWM5PHIF
: 1;
8558 unsigned PWM5OFIF
: 1;
8566 extern __at(0x0D9D) volatile __PWM5INTFbits_t PWM5INTFbits
;
8569 #define _PWM5PRIF 0x01
8571 #define _PWM5DCIF 0x02
8573 #define _PWM5PHIF 0x04
8575 #define _PWM5OFIF 0x08
8577 //==============================================================================
8580 //==============================================================================
8583 extern __at(0x0D9D) __sfr PWM5INTFLG
;
8601 unsigned PWM5PRIF
: 1;
8602 unsigned PWM5DCIF
: 1;
8603 unsigned PWM5PHIF
: 1;
8604 unsigned PWM5OFIF
: 1;
8610 } __PWM5INTFLGbits_t
;
8612 extern __at(0x0D9D) volatile __PWM5INTFLGbits_t PWM5INTFLGbits
;
8614 #define _PWM5INTFLG_PRIF 0x01
8615 #define _PWM5INTFLG_PWM5PRIF 0x01
8616 #define _PWM5INTFLG_DCIF 0x02
8617 #define _PWM5INTFLG_PWM5DCIF 0x02
8618 #define _PWM5INTFLG_PHIF 0x04
8619 #define _PWM5INTFLG_PWM5PHIF 0x04
8620 #define _PWM5INTFLG_OFIF 0x08
8621 #define _PWM5INTFLG_PWM5OFIF 0x08
8623 //==============================================================================
8626 //==============================================================================
8629 extern __at(0x0D9E) __sfr PWM5CLKCON
;
8635 unsigned PWM5CS0
: 1;
8636 unsigned PWM5CS1
: 1;
8637 unsigned PWM5CS2
: 1;
8639 unsigned PWM5PS0
: 1;
8640 unsigned PWM5PS1
: 1;
8641 unsigned PWM5PS2
: 1;
8659 unsigned PWM5CS
: 3;
8672 unsigned PWM5PS
: 3;
8682 } __PWM5CLKCONbits_t
;
8684 extern __at(0x0D9E) volatile __PWM5CLKCONbits_t PWM5CLKCONbits
;
8686 #define _PWM5CLKCON_PWM5CS0 0x01
8687 #define _PWM5CLKCON_CS0 0x01
8688 #define _PWM5CLKCON_PWM5CS1 0x02
8689 #define _PWM5CLKCON_CS1 0x02
8690 #define _PWM5CLKCON_PWM5CS2 0x04
8691 #define _PWM5CLKCON_CS2 0x04
8692 #define _PWM5CLKCON_PWM5PS0 0x10
8693 #define _PWM5CLKCON_PS0 0x10
8694 #define _PWM5CLKCON_PWM5PS1 0x20
8695 #define _PWM5CLKCON_PS1 0x20
8696 #define _PWM5CLKCON_PWM5PS2 0x40
8697 #define _PWM5CLKCON_PS2 0x40
8699 //==============================================================================
8702 //==============================================================================
8705 extern __at(0x0D9F) __sfr PWM5LDCON
;
8730 unsigned PWM5LD
: 1;
8732 } __PWM5LDCONbits_t
;
8734 extern __at(0x0D9F) volatile __PWM5LDCONbits_t PWM5LDCONbits
;
8737 #define _PWM5LD 0x80
8739 //==============================================================================
8742 //==============================================================================
8745 extern __at(0x0DA0) __sfr PWM5OFCON
;
8767 unsigned PWM5OFMC
: 1;
8772 } __PWM5OFCONbits_t
;
8774 extern __at(0x0DA0) volatile __PWM5OFCONbits_t PWM5OFCONbits
;
8777 #define _PWM5OFMC 0x10
8779 //==============================================================================
8782 //==============================================================================
8785 extern __at(0x0E0F) __sfr PPSLOCK
;
8789 unsigned PPSLOCKED
: 1;
8799 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
8801 #define _PPSLOCKED 0x01
8803 //==============================================================================
8805 extern __at(0x0E10) __sfr INTPPS
;
8806 extern __at(0x0E11) __sfr T0CKIPPS
;
8807 extern __at(0x0E12) __sfr T1CKIPPS
;
8808 extern __at(0x0E13) __sfr T1GPPS
;
8809 extern __at(0x0E14) __sfr CCP1PPS
;
8810 extern __at(0x0E16) __sfr COG1INPPS
;
8811 extern __at(0x0E19) __sfr T2CKIPPS
;
8812 extern __at(0x0E1A) __sfr T3CKIPPS
;
8813 extern __at(0x0E1B) __sfr T3GPPS
;
8814 extern __at(0x0E1C) __sfr T4CKIPPS
;
8815 extern __at(0x0E1D) __sfr T5CKIPPS
;
8816 extern __at(0x0E1E) __sfr T5GPPS
;
8817 extern __at(0x0E1F) __sfr T6CKIPPS
;
8818 extern __at(0x0E20) __sfr SSPCLKPPS
;
8819 extern __at(0x0E21) __sfr SSPDATPPS
;
8820 extern __at(0x0E22) __sfr SSPSSPPS
;
8821 extern __at(0x0E24) __sfr RXPPS
;
8822 extern __at(0x0E25) __sfr CKPPS
;
8823 extern __at(0x0E28) __sfr CLCIN0PPS
;
8824 extern __at(0x0E29) __sfr CLCIN1PPS
;
8825 extern __at(0x0E2A) __sfr CLCIN2PPS
;
8826 extern __at(0x0E2B) __sfr CLCIN3PPS
;
8827 extern __at(0x0E2C) __sfr PRG1RPPS
;
8828 extern __at(0x0E2D) __sfr PRG1FPPS
;
8829 extern __at(0x0E30) __sfr MD1CHPPS
;
8830 extern __at(0x0E31) __sfr MD1CLPPS
;
8831 extern __at(0x0E32) __sfr MD1MODPPS
;
8832 extern __at(0x0E90) __sfr RA0PPS
;
8833 extern __at(0x0E91) __sfr RA1PPS
;
8834 extern __at(0x0E92) __sfr RA2PPS
;
8835 extern __at(0x0E94) __sfr RA4PPS
;
8836 extern __at(0x0E95) __sfr RA5PPS
;
8837 extern __at(0x0EA0) __sfr RC0PPS
;
8838 extern __at(0x0EA1) __sfr RC1PPS
;
8839 extern __at(0x0EA2) __sfr RC2PPS
;
8840 extern __at(0x0EA3) __sfr RC3PPS
;
8841 extern __at(0x0EA4) __sfr RC4PPS
;
8842 extern __at(0x0EA5) __sfr RC5PPS
;
8844 //==============================================================================
8847 extern __at(0x0F0F) __sfr CLCDATA
;
8851 unsigned MCLC1OUT
: 1;
8852 unsigned MCLC2OUT
: 1;
8853 unsigned MCLC3OUT
: 1;
8861 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
8863 #define _MCLC1OUT 0x01
8864 #define _MCLC2OUT 0x02
8865 #define _MCLC3OUT 0x04
8867 //==============================================================================
8870 //==============================================================================
8873 extern __at(0x0F10) __sfr CLC1CON
;
8879 unsigned LC1MODE0
: 1;
8880 unsigned LC1MODE1
: 1;
8881 unsigned LC1MODE2
: 1;
8882 unsigned LC1INTN
: 1;
8883 unsigned LC1INTP
: 1;
8884 unsigned LC1OUT
: 1;
8903 unsigned LC1MODE
: 3;
8914 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
8916 #define _CLC1CON_LC1MODE0 0x01
8917 #define _CLC1CON_MODE0 0x01
8918 #define _CLC1CON_LC1MODE1 0x02
8919 #define _CLC1CON_MODE1 0x02
8920 #define _CLC1CON_LC1MODE2 0x04
8921 #define _CLC1CON_MODE2 0x04
8922 #define _CLC1CON_LC1INTN 0x08
8923 #define _CLC1CON_INTN 0x08
8924 #define _CLC1CON_LC1INTP 0x10
8925 #define _CLC1CON_INTP 0x10
8926 #define _CLC1CON_LC1OUT 0x20
8927 #define _CLC1CON_OUT 0x20
8928 #define _CLC1CON_LC1EN 0x80
8929 #define _CLC1CON_EN 0x80
8931 //==============================================================================
8934 //==============================================================================
8937 extern __at(0x0F11) __sfr CLC1POL
;
8943 unsigned LC1G1POL
: 1;
8944 unsigned LC1G2POL
: 1;
8945 unsigned LC1G3POL
: 1;
8946 unsigned LC1G4POL
: 1;
8950 unsigned LC1POL
: 1;
8966 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
8968 #define _LC1G1POL 0x01
8970 #define _LC1G2POL 0x02
8972 #define _LC1G3POL 0x04
8974 #define _LC1G4POL 0x08
8976 #define _LC1POL 0x80
8979 //==============================================================================
8982 //==============================================================================
8985 extern __at(0x0F12) __sfr CLC1SEL0
;
8991 unsigned LC1D1S0
: 1;
8992 unsigned LC1D1S1
: 1;
8993 unsigned LC1D1S2
: 1;
8994 unsigned LC1D1S3
: 1;
8995 unsigned LC1D1S4
: 1;
9021 unsigned LC1D1S
: 5;
9026 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
9028 #define _LC1D1S0 0x01
9030 #define _LC1D1S1 0x02
9032 #define _LC1D1S2 0x04
9034 #define _LC1D1S3 0x08
9036 #define _LC1D1S4 0x10
9039 //==============================================================================
9042 //==============================================================================
9045 extern __at(0x0F13) __sfr CLC1SEL1
;
9051 unsigned LC1D2S0
: 1;
9052 unsigned LC1D2S1
: 1;
9053 unsigned LC1D2S2
: 1;
9054 unsigned LC1D2S3
: 1;
9055 unsigned LC1D2S4
: 1;
9075 unsigned LC1D2S
: 5;
9086 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
9088 #define _LC1D2S0 0x01
9090 #define _LC1D2S1 0x02
9092 #define _LC1D2S2 0x04
9094 #define _LC1D2S3 0x08
9096 #define _LC1D2S4 0x10
9099 //==============================================================================
9102 //==============================================================================
9105 extern __at(0x0F14) __sfr CLC1SEL2
;
9111 unsigned LC1D3S0
: 1;
9112 unsigned LC1D3S1
: 1;
9113 unsigned LC1D3S2
: 1;
9114 unsigned LC1D3S3
: 1;
9115 unsigned LC1D3S4
: 1;
9135 unsigned LC1D3S
: 5;
9146 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
9148 #define _LC1D3S0 0x01
9150 #define _LC1D3S1 0x02
9152 #define _LC1D3S2 0x04
9154 #define _LC1D3S3 0x08
9156 #define _LC1D3S4 0x10
9159 //==============================================================================
9162 //==============================================================================
9165 extern __at(0x0F15) __sfr CLC1SEL3
;
9171 unsigned LC1D4S0
: 1;
9172 unsigned LC1D4S1
: 1;
9173 unsigned LC1D4S2
: 1;
9174 unsigned LC1D4S3
: 1;
9175 unsigned LC1D4S4
: 1;
9201 unsigned LC1D4S
: 5;
9206 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
9208 #define _LC1D4S0 0x01
9210 #define _LC1D4S1 0x02
9212 #define _LC1D4S2 0x04
9214 #define _LC1D4S3 0x08
9216 #define _LC1D4S4 0x10
9219 //==============================================================================
9222 //==============================================================================
9225 extern __at(0x0F16) __sfr CLC1GLS0
;
9231 unsigned LC1G1D1N
: 1;
9232 unsigned LC1G1D1T
: 1;
9233 unsigned LC1G1D2N
: 1;
9234 unsigned LC1G1D2T
: 1;
9235 unsigned LC1G1D3N
: 1;
9236 unsigned LC1G1D3T
: 1;
9237 unsigned LC1G1D4N
: 1;
9238 unsigned LC1G1D4T
: 1;
9254 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
9256 #define _LC1G1D1N 0x01
9258 #define _LC1G1D1T 0x02
9260 #define _LC1G1D2N 0x04
9262 #define _LC1G1D2T 0x08
9264 #define _LC1G1D3N 0x10
9266 #define _LC1G1D3T 0x20
9268 #define _LC1G1D4N 0x40
9270 #define _LC1G1D4T 0x80
9273 //==============================================================================
9276 //==============================================================================
9279 extern __at(0x0F17) __sfr CLC1GLS1
;
9285 unsigned LC1G2D1N
: 1;
9286 unsigned LC1G2D1T
: 1;
9287 unsigned LC1G2D2N
: 1;
9288 unsigned LC1G2D2T
: 1;
9289 unsigned LC1G2D3N
: 1;
9290 unsigned LC1G2D3T
: 1;
9291 unsigned LC1G2D4N
: 1;
9292 unsigned LC1G2D4T
: 1;
9308 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
9310 #define _CLC1GLS1_LC1G2D1N 0x01
9311 #define _CLC1GLS1_D1N 0x01
9312 #define _CLC1GLS1_LC1G2D1T 0x02
9313 #define _CLC1GLS1_D1T 0x02
9314 #define _CLC1GLS1_LC1G2D2N 0x04
9315 #define _CLC1GLS1_D2N 0x04
9316 #define _CLC1GLS1_LC1G2D2T 0x08
9317 #define _CLC1GLS1_D2T 0x08
9318 #define _CLC1GLS1_LC1G2D3N 0x10
9319 #define _CLC1GLS1_D3N 0x10
9320 #define _CLC1GLS1_LC1G2D3T 0x20
9321 #define _CLC1GLS1_D3T 0x20
9322 #define _CLC1GLS1_LC1G2D4N 0x40
9323 #define _CLC1GLS1_D4N 0x40
9324 #define _CLC1GLS1_LC1G2D4T 0x80
9325 #define _CLC1GLS1_D4T 0x80
9327 //==============================================================================
9330 //==============================================================================
9333 extern __at(0x0F18) __sfr CLC1GLS2
;
9339 unsigned LC1G3D1N
: 1;
9340 unsigned LC1G3D1T
: 1;
9341 unsigned LC1G3D2N
: 1;
9342 unsigned LC1G3D2T
: 1;
9343 unsigned LC1G3D3N
: 1;
9344 unsigned LC1G3D3T
: 1;
9345 unsigned LC1G3D4N
: 1;
9346 unsigned LC1G3D4T
: 1;
9362 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
9364 #define _CLC1GLS2_LC1G3D1N 0x01
9365 #define _CLC1GLS2_D1N 0x01
9366 #define _CLC1GLS2_LC1G3D1T 0x02
9367 #define _CLC1GLS2_D1T 0x02
9368 #define _CLC1GLS2_LC1G3D2N 0x04
9369 #define _CLC1GLS2_D2N 0x04
9370 #define _CLC1GLS2_LC1G3D2T 0x08
9371 #define _CLC1GLS2_D2T 0x08
9372 #define _CLC1GLS2_LC1G3D3N 0x10
9373 #define _CLC1GLS2_D3N 0x10
9374 #define _CLC1GLS2_LC1G3D3T 0x20
9375 #define _CLC1GLS2_D3T 0x20
9376 #define _CLC1GLS2_LC1G3D4N 0x40
9377 #define _CLC1GLS2_D4N 0x40
9378 #define _CLC1GLS2_LC1G3D4T 0x80
9379 #define _CLC1GLS2_D4T 0x80
9381 //==============================================================================
9384 //==============================================================================
9387 extern __at(0x0F19) __sfr CLC1GLS3
;
9393 unsigned LC1G4D1N
: 1;
9394 unsigned LC1G4D1T
: 1;
9395 unsigned LC1G4D2N
: 1;
9396 unsigned LC1G4D2T
: 1;
9397 unsigned LC1G4D3N
: 1;
9398 unsigned LC1G4D3T
: 1;
9399 unsigned LC1G4D4N
: 1;
9400 unsigned LC1G4D4T
: 1;
9416 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
9418 #define _LC1G4D1N 0x01
9420 #define _LC1G4D1T 0x02
9422 #define _LC1G4D2N 0x04
9424 #define _LC1G4D2T 0x08
9426 #define _LC1G4D3N 0x10
9428 #define _LC1G4D3T 0x20
9430 #define _LC1G4D4N 0x40
9432 #define _LC1G4D4T 0x80
9435 //==============================================================================
9438 //==============================================================================
9441 extern __at(0x0F1A) __sfr CLC2CON
;
9447 unsigned LC2MODE0
: 1;
9448 unsigned LC2MODE1
: 1;
9449 unsigned LC2MODE2
: 1;
9450 unsigned LC2INTN
: 1;
9451 unsigned LC2INTP
: 1;
9452 unsigned LC2OUT
: 1;
9477 unsigned LC2MODE
: 3;
9482 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
9484 #define _CLC2CON_LC2MODE0 0x01
9485 #define _CLC2CON_MODE0 0x01
9486 #define _CLC2CON_LC2MODE1 0x02
9487 #define _CLC2CON_MODE1 0x02
9488 #define _CLC2CON_LC2MODE2 0x04
9489 #define _CLC2CON_MODE2 0x04
9490 #define _CLC2CON_LC2INTN 0x08
9491 #define _CLC2CON_INTN 0x08
9492 #define _CLC2CON_LC2INTP 0x10
9493 #define _CLC2CON_INTP 0x10
9494 #define _CLC2CON_LC2OUT 0x20
9495 #define _CLC2CON_OUT 0x20
9496 #define _CLC2CON_LC2EN 0x80
9497 #define _CLC2CON_EN 0x80
9499 //==============================================================================
9502 //==============================================================================
9505 extern __at(0x0F1B) __sfr CLC2POL
;
9511 unsigned LC2G1POL
: 1;
9512 unsigned LC2G2POL
: 1;
9513 unsigned LC2G3POL
: 1;
9514 unsigned LC2G4POL
: 1;
9518 unsigned LC2POL
: 1;
9534 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
9536 #define _CLC2POL_LC2G1POL 0x01
9537 #define _CLC2POL_G1POL 0x01
9538 #define _CLC2POL_LC2G2POL 0x02
9539 #define _CLC2POL_G2POL 0x02
9540 #define _CLC2POL_LC2G3POL 0x04
9541 #define _CLC2POL_G3POL 0x04
9542 #define _CLC2POL_LC2G4POL 0x08
9543 #define _CLC2POL_G4POL 0x08
9544 #define _CLC2POL_LC2POL 0x80
9545 #define _CLC2POL_POL 0x80
9547 //==============================================================================
9550 //==============================================================================
9553 extern __at(0x0F1C) __sfr CLC2SEL0
;
9559 unsigned LC2D1S0
: 1;
9560 unsigned LC2D1S1
: 1;
9561 unsigned LC2D1S2
: 1;
9562 unsigned LC2D1S3
: 1;
9563 unsigned LC2D1S4
: 1;
9583 unsigned LC2D1S
: 5;
9594 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
9596 #define _CLC2SEL0_LC2D1S0 0x01
9597 #define _CLC2SEL0_D1S0 0x01
9598 #define _CLC2SEL0_LC2D1S1 0x02
9599 #define _CLC2SEL0_D1S1 0x02
9600 #define _CLC2SEL0_LC2D1S2 0x04
9601 #define _CLC2SEL0_D1S2 0x04
9602 #define _CLC2SEL0_LC2D1S3 0x08
9603 #define _CLC2SEL0_D1S3 0x08
9604 #define _CLC2SEL0_LC2D1S4 0x10
9605 #define _CLC2SEL0_D1S4 0x10
9607 //==============================================================================
9610 //==============================================================================
9613 extern __at(0x0F1D) __sfr CLC2SEL1
;
9619 unsigned LC2D2S0
: 1;
9620 unsigned LC2D2S1
: 1;
9621 unsigned LC2D2S2
: 1;
9622 unsigned LC2D2S3
: 1;
9623 unsigned LC2D2S4
: 1;
9649 unsigned LC2D2S
: 5;
9654 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
9656 #define _CLC2SEL1_LC2D2S0 0x01
9657 #define _CLC2SEL1_D2S0 0x01
9658 #define _CLC2SEL1_LC2D2S1 0x02
9659 #define _CLC2SEL1_D2S1 0x02
9660 #define _CLC2SEL1_LC2D2S2 0x04
9661 #define _CLC2SEL1_D2S2 0x04
9662 #define _CLC2SEL1_LC2D2S3 0x08
9663 #define _CLC2SEL1_D2S3 0x08
9664 #define _CLC2SEL1_LC2D2S4 0x10
9665 #define _CLC2SEL1_D2S4 0x10
9667 //==============================================================================
9670 //==============================================================================
9673 extern __at(0x0F1E) __sfr CLC2SEL2
;
9679 unsigned LC2D3S0
: 1;
9680 unsigned LC2D3S1
: 1;
9681 unsigned LC2D3S2
: 1;
9682 unsigned LC2D3S3
: 1;
9683 unsigned LC2D3S4
: 1;
9709 unsigned LC2D3S
: 5;
9714 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
9716 #define _CLC2SEL2_LC2D3S0 0x01
9717 #define _CLC2SEL2_D3S0 0x01
9718 #define _CLC2SEL2_LC2D3S1 0x02
9719 #define _CLC2SEL2_D3S1 0x02
9720 #define _CLC2SEL2_LC2D3S2 0x04
9721 #define _CLC2SEL2_D3S2 0x04
9722 #define _CLC2SEL2_LC2D3S3 0x08
9723 #define _CLC2SEL2_D3S3 0x08
9724 #define _CLC2SEL2_LC2D3S4 0x10
9725 #define _CLC2SEL2_D3S4 0x10
9727 //==============================================================================
9730 //==============================================================================
9733 extern __at(0x0F1F) __sfr CLC2SEL3
;
9739 unsigned LC2D4S0
: 1;
9740 unsigned LC2D4S1
: 1;
9741 unsigned LC2D4S2
: 1;
9742 unsigned LC2D4S3
: 1;
9743 unsigned LC2D4S4
: 1;
9763 unsigned LC2D4S
: 5;
9774 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
9776 #define _CLC2SEL3_LC2D4S0 0x01
9777 #define _CLC2SEL3_D4S0 0x01
9778 #define _CLC2SEL3_LC2D4S1 0x02
9779 #define _CLC2SEL3_D4S1 0x02
9780 #define _CLC2SEL3_LC2D4S2 0x04
9781 #define _CLC2SEL3_D4S2 0x04
9782 #define _CLC2SEL3_LC2D4S3 0x08
9783 #define _CLC2SEL3_D4S3 0x08
9784 #define _CLC2SEL3_LC2D4S4 0x10
9785 #define _CLC2SEL3_D4S4 0x10
9787 //==============================================================================
9790 //==============================================================================
9793 extern __at(0x0F20) __sfr CLC2GLS0
;
9799 unsigned LC2G1D1N
: 1;
9800 unsigned LC2G1D1T
: 1;
9801 unsigned LC2G1D2N
: 1;
9802 unsigned LC2G1D2T
: 1;
9803 unsigned LC2G1D3N
: 1;
9804 unsigned LC2G1D3T
: 1;
9805 unsigned LC2G1D4N
: 1;
9806 unsigned LC2G1D4T
: 1;
9822 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
9824 #define _CLC2GLS0_LC2G1D1N 0x01
9825 #define _CLC2GLS0_D1N 0x01
9826 #define _CLC2GLS0_LC2G1D1T 0x02
9827 #define _CLC2GLS0_D1T 0x02
9828 #define _CLC2GLS0_LC2G1D2N 0x04
9829 #define _CLC2GLS0_D2N 0x04
9830 #define _CLC2GLS0_LC2G1D2T 0x08
9831 #define _CLC2GLS0_D2T 0x08
9832 #define _CLC2GLS0_LC2G1D3N 0x10
9833 #define _CLC2GLS0_D3N 0x10
9834 #define _CLC2GLS0_LC2G1D3T 0x20
9835 #define _CLC2GLS0_D3T 0x20
9836 #define _CLC2GLS0_LC2G1D4N 0x40
9837 #define _CLC2GLS0_D4N 0x40
9838 #define _CLC2GLS0_LC2G1D4T 0x80
9839 #define _CLC2GLS0_D4T 0x80
9841 //==============================================================================
9844 //==============================================================================
9847 extern __at(0x0F21) __sfr CLC2GLS1
;
9853 unsigned LC2G2D1N
: 1;
9854 unsigned LC2G2D1T
: 1;
9855 unsigned LC2G2D2N
: 1;
9856 unsigned LC2G2D2T
: 1;
9857 unsigned LC2G2D3N
: 1;
9858 unsigned LC2G2D3T
: 1;
9859 unsigned LC2G2D4N
: 1;
9860 unsigned LC2G2D4T
: 1;
9876 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
9878 #define _CLC2GLS1_LC2G2D1N 0x01
9879 #define _CLC2GLS1_D1N 0x01
9880 #define _CLC2GLS1_LC2G2D1T 0x02
9881 #define _CLC2GLS1_D1T 0x02
9882 #define _CLC2GLS1_LC2G2D2N 0x04
9883 #define _CLC2GLS1_D2N 0x04
9884 #define _CLC2GLS1_LC2G2D2T 0x08
9885 #define _CLC2GLS1_D2T 0x08
9886 #define _CLC2GLS1_LC2G2D3N 0x10
9887 #define _CLC2GLS1_D3N 0x10
9888 #define _CLC2GLS1_LC2G2D3T 0x20
9889 #define _CLC2GLS1_D3T 0x20
9890 #define _CLC2GLS1_LC2G2D4N 0x40
9891 #define _CLC2GLS1_D4N 0x40
9892 #define _CLC2GLS1_LC2G2D4T 0x80
9893 #define _CLC2GLS1_D4T 0x80
9895 //==============================================================================
9898 //==============================================================================
9901 extern __at(0x0F22) __sfr CLC2GLS2
;
9907 unsigned LC2G3D1N
: 1;
9908 unsigned LC2G3D1T
: 1;
9909 unsigned LC2G3D2N
: 1;
9910 unsigned LC2G3D2T
: 1;
9911 unsigned LC2G3D3N
: 1;
9912 unsigned LC2G3D3T
: 1;
9913 unsigned LC2G3D4N
: 1;
9914 unsigned LC2G3D4T
: 1;
9930 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
9932 #define _CLC2GLS2_LC2G3D1N 0x01
9933 #define _CLC2GLS2_D1N 0x01
9934 #define _CLC2GLS2_LC2G3D1T 0x02
9935 #define _CLC2GLS2_D1T 0x02
9936 #define _CLC2GLS2_LC2G3D2N 0x04
9937 #define _CLC2GLS2_D2N 0x04
9938 #define _CLC2GLS2_LC2G3D2T 0x08
9939 #define _CLC2GLS2_D2T 0x08
9940 #define _CLC2GLS2_LC2G3D3N 0x10
9941 #define _CLC2GLS2_D3N 0x10
9942 #define _CLC2GLS2_LC2G3D3T 0x20
9943 #define _CLC2GLS2_D3T 0x20
9944 #define _CLC2GLS2_LC2G3D4N 0x40
9945 #define _CLC2GLS2_D4N 0x40
9946 #define _CLC2GLS2_LC2G3D4T 0x80
9947 #define _CLC2GLS2_D4T 0x80
9949 //==============================================================================
9952 //==============================================================================
9955 extern __at(0x0F23) __sfr CLC2GLS3
;
9961 unsigned LC2G4D1N
: 1;
9962 unsigned LC2G4D1T
: 1;
9963 unsigned LC2G4D2N
: 1;
9964 unsigned LC2G4D2T
: 1;
9965 unsigned LC2G4D3N
: 1;
9966 unsigned LC2G4D3T
: 1;
9967 unsigned LC2G4D4N
: 1;
9968 unsigned LC2G4D4T
: 1;
9984 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
9986 #define _CLC2GLS3_LC2G4D1N 0x01
9987 #define _CLC2GLS3_G4D1N 0x01
9988 #define _CLC2GLS3_LC2G4D1T 0x02
9989 #define _CLC2GLS3_G4D1T 0x02
9990 #define _CLC2GLS3_LC2G4D2N 0x04
9991 #define _CLC2GLS3_G4D2N 0x04
9992 #define _CLC2GLS3_LC2G4D2T 0x08
9993 #define _CLC2GLS3_G4D2T 0x08
9994 #define _CLC2GLS3_LC2G4D3N 0x10
9995 #define _CLC2GLS3_G4D3N 0x10
9996 #define _CLC2GLS3_LC2G4D3T 0x20
9997 #define _CLC2GLS3_G4D3T 0x20
9998 #define _CLC2GLS3_LC2G4D4N 0x40
9999 #define _CLC2GLS3_G4D4N 0x40
10000 #define _CLC2GLS3_LC2G4D4T 0x80
10001 #define _CLC2GLS3_G4D4T 0x80
10003 //==============================================================================
10006 //==============================================================================
10009 extern __at(0x0F24) __sfr CLC3CON
;
10015 unsigned LC3MODE0
: 1;
10016 unsigned LC3MODE1
: 1;
10017 unsigned LC3MODE2
: 1;
10018 unsigned LC3INTN
: 1;
10019 unsigned LC3INTP
: 1;
10020 unsigned LC3OUT
: 1;
10022 unsigned LC3EN
: 1;
10027 unsigned MODE0
: 1;
10028 unsigned MODE1
: 1;
10029 unsigned MODE2
: 1;
10039 unsigned LC3MODE
: 3;
10050 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
10052 #define _CLC3CON_LC3MODE0 0x01
10053 #define _CLC3CON_MODE0 0x01
10054 #define _CLC3CON_LC3MODE1 0x02
10055 #define _CLC3CON_MODE1 0x02
10056 #define _CLC3CON_LC3MODE2 0x04
10057 #define _CLC3CON_MODE2 0x04
10058 #define _CLC3CON_LC3INTN 0x08
10059 #define _CLC3CON_INTN 0x08
10060 #define _CLC3CON_LC3INTP 0x10
10061 #define _CLC3CON_INTP 0x10
10062 #define _CLC3CON_LC3OUT 0x20
10063 #define _CLC3CON_OUT 0x20
10064 #define _CLC3CON_LC3EN 0x80
10065 #define _CLC3CON_EN 0x80
10067 //==============================================================================
10070 //==============================================================================
10073 extern __at(0x0F25) __sfr CLC3POL
;
10079 unsigned LC3G1POL
: 1;
10080 unsigned LC3G2POL
: 1;
10081 unsigned LC3G3POL
: 1;
10082 unsigned LC3G4POL
: 1;
10086 unsigned LC3POL
: 1;
10091 unsigned G1POL
: 1;
10092 unsigned G2POL
: 1;
10093 unsigned G3POL
: 1;
10094 unsigned G4POL
: 1;
10102 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
10104 #define _CLC3POL_LC3G1POL 0x01
10105 #define _CLC3POL_G1POL 0x01
10106 #define _CLC3POL_LC3G2POL 0x02
10107 #define _CLC3POL_G2POL 0x02
10108 #define _CLC3POL_LC3G3POL 0x04
10109 #define _CLC3POL_G3POL 0x04
10110 #define _CLC3POL_LC3G4POL 0x08
10111 #define _CLC3POL_G4POL 0x08
10112 #define _CLC3POL_LC3POL 0x80
10113 #define _CLC3POL_POL 0x80
10115 //==============================================================================
10118 //==============================================================================
10121 extern __at(0x0F26) __sfr CLC3SEL0
;
10127 unsigned LC3D1S0
: 1;
10128 unsigned LC3D1S1
: 1;
10129 unsigned LC3D1S2
: 1;
10130 unsigned LC3D1S3
: 1;
10131 unsigned LC3D1S4
: 1;
10157 unsigned LC3D1S
: 5;
10160 } __CLC3SEL0bits_t
;
10162 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
10164 #define _CLC3SEL0_LC3D1S0 0x01
10165 #define _CLC3SEL0_D1S0 0x01
10166 #define _CLC3SEL0_LC3D1S1 0x02
10167 #define _CLC3SEL0_D1S1 0x02
10168 #define _CLC3SEL0_LC3D1S2 0x04
10169 #define _CLC3SEL0_D1S2 0x04
10170 #define _CLC3SEL0_LC3D1S3 0x08
10171 #define _CLC3SEL0_D1S3 0x08
10172 #define _CLC3SEL0_LC3D1S4 0x10
10173 #define _CLC3SEL0_D1S4 0x10
10175 //==============================================================================
10178 //==============================================================================
10181 extern __at(0x0F27) __sfr CLC3SEL1
;
10187 unsigned LC3D2S0
: 1;
10188 unsigned LC3D2S1
: 1;
10189 unsigned LC3D2S2
: 1;
10190 unsigned LC3D2S3
: 1;
10191 unsigned LC3D2S4
: 1;
10211 unsigned LC3D2S
: 5;
10220 } __CLC3SEL1bits_t
;
10222 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
10224 #define _CLC3SEL1_LC3D2S0 0x01
10225 #define _CLC3SEL1_D2S0 0x01
10226 #define _CLC3SEL1_LC3D2S1 0x02
10227 #define _CLC3SEL1_D2S1 0x02
10228 #define _CLC3SEL1_LC3D2S2 0x04
10229 #define _CLC3SEL1_D2S2 0x04
10230 #define _CLC3SEL1_LC3D2S3 0x08
10231 #define _CLC3SEL1_D2S3 0x08
10232 #define _CLC3SEL1_LC3D2S4 0x10
10233 #define _CLC3SEL1_D2S4 0x10
10235 //==============================================================================
10238 //==============================================================================
10241 extern __at(0x0F28) __sfr CLC3SEL2
;
10247 unsigned LC3D3S0
: 1;
10248 unsigned LC3D3S1
: 1;
10249 unsigned LC3D3S2
: 1;
10250 unsigned LC3D3S3
: 1;
10251 unsigned LC3D3S4
: 1;
10271 unsigned LC3D3S
: 5;
10280 } __CLC3SEL2bits_t
;
10282 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
10284 #define _CLC3SEL2_LC3D3S0 0x01
10285 #define _CLC3SEL2_D3S0 0x01
10286 #define _CLC3SEL2_LC3D3S1 0x02
10287 #define _CLC3SEL2_D3S1 0x02
10288 #define _CLC3SEL2_LC3D3S2 0x04
10289 #define _CLC3SEL2_D3S2 0x04
10290 #define _CLC3SEL2_LC3D3S3 0x08
10291 #define _CLC3SEL2_D3S3 0x08
10292 #define _CLC3SEL2_LC3D3S4 0x10
10293 #define _CLC3SEL2_D3S4 0x10
10295 //==============================================================================
10298 //==============================================================================
10301 extern __at(0x0F29) __sfr CLC3SEL3
;
10307 unsigned LC3D4S0
: 1;
10308 unsigned LC3D4S1
: 1;
10309 unsigned LC3D4S2
: 1;
10310 unsigned LC3D4S3
: 1;
10311 unsigned LC3D4S4
: 1;
10331 unsigned LC3D4S
: 5;
10340 } __CLC3SEL3bits_t
;
10342 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
10344 #define _CLC3SEL3_LC3D4S0 0x01
10345 #define _CLC3SEL3_D4S0 0x01
10346 #define _CLC3SEL3_LC3D4S1 0x02
10347 #define _CLC3SEL3_D4S1 0x02
10348 #define _CLC3SEL3_LC3D4S2 0x04
10349 #define _CLC3SEL3_D4S2 0x04
10350 #define _CLC3SEL3_LC3D4S3 0x08
10351 #define _CLC3SEL3_D4S3 0x08
10352 #define _CLC3SEL3_LC3D4S4 0x10
10353 #define _CLC3SEL3_D4S4 0x10
10355 //==============================================================================
10358 //==============================================================================
10361 extern __at(0x0F2A) __sfr CLC3GLS0
;
10367 unsigned LC3G1D1N
: 1;
10368 unsigned LC3G1D1T
: 1;
10369 unsigned LC3G1D2N
: 1;
10370 unsigned LC3G1D2T
: 1;
10371 unsigned LC3G1D3N
: 1;
10372 unsigned LC3G1D3T
: 1;
10373 unsigned LC3G1D4N
: 1;
10374 unsigned LC3G1D4T
: 1;
10388 } __CLC3GLS0bits_t
;
10390 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
10392 #define _CLC3GLS0_LC3G1D1N 0x01
10393 #define _CLC3GLS0_D1N 0x01
10394 #define _CLC3GLS0_LC3G1D1T 0x02
10395 #define _CLC3GLS0_D1T 0x02
10396 #define _CLC3GLS0_LC3G1D2N 0x04
10397 #define _CLC3GLS0_D2N 0x04
10398 #define _CLC3GLS0_LC3G1D2T 0x08
10399 #define _CLC3GLS0_D2T 0x08
10400 #define _CLC3GLS0_LC3G1D3N 0x10
10401 #define _CLC3GLS0_D3N 0x10
10402 #define _CLC3GLS0_LC3G1D3T 0x20
10403 #define _CLC3GLS0_D3T 0x20
10404 #define _CLC3GLS0_LC3G1D4N 0x40
10405 #define _CLC3GLS0_D4N 0x40
10406 #define _CLC3GLS0_LC3G1D4T 0x80
10407 #define _CLC3GLS0_D4T 0x80
10409 //==============================================================================
10412 //==============================================================================
10415 extern __at(0x0F2B) __sfr CLC3GLS1
;
10421 unsigned LC3G2D1N
: 1;
10422 unsigned LC3G2D1T
: 1;
10423 unsigned LC3G2D2N
: 1;
10424 unsigned LC3G2D2T
: 1;
10425 unsigned LC3G2D3N
: 1;
10426 unsigned LC3G2D3T
: 1;
10427 unsigned LC3G2D4N
: 1;
10428 unsigned LC3G2D4T
: 1;
10442 } __CLC3GLS1bits_t
;
10444 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
10446 #define _CLC3GLS1_LC3G2D1N 0x01
10447 #define _CLC3GLS1_D1N 0x01
10448 #define _CLC3GLS1_LC3G2D1T 0x02
10449 #define _CLC3GLS1_D1T 0x02
10450 #define _CLC3GLS1_LC3G2D2N 0x04
10451 #define _CLC3GLS1_D2N 0x04
10452 #define _CLC3GLS1_LC3G2D2T 0x08
10453 #define _CLC3GLS1_D2T 0x08
10454 #define _CLC3GLS1_LC3G2D3N 0x10
10455 #define _CLC3GLS1_D3N 0x10
10456 #define _CLC3GLS1_LC3G2D3T 0x20
10457 #define _CLC3GLS1_D3T 0x20
10458 #define _CLC3GLS1_LC3G2D4N 0x40
10459 #define _CLC3GLS1_D4N 0x40
10460 #define _CLC3GLS1_LC3G2D4T 0x80
10461 #define _CLC3GLS1_D4T 0x80
10463 //==============================================================================
10466 //==============================================================================
10469 extern __at(0x0F2C) __sfr CLC3GLS2
;
10475 unsigned LC3G3D1N
: 1;
10476 unsigned LC3G3D1T
: 1;
10477 unsigned LC3G3D2N
: 1;
10478 unsigned LC3G3D2T
: 1;
10479 unsigned LC3G3D3N
: 1;
10480 unsigned LC3G3D3T
: 1;
10481 unsigned LC3G3D4N
: 1;
10482 unsigned LC3G3D4T
: 1;
10496 } __CLC3GLS2bits_t
;
10498 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
10500 #define _CLC3GLS2_LC3G3D1N 0x01
10501 #define _CLC3GLS2_D1N 0x01
10502 #define _CLC3GLS2_LC3G3D1T 0x02
10503 #define _CLC3GLS2_D1T 0x02
10504 #define _CLC3GLS2_LC3G3D2N 0x04
10505 #define _CLC3GLS2_D2N 0x04
10506 #define _CLC3GLS2_LC3G3D2T 0x08
10507 #define _CLC3GLS2_D2T 0x08
10508 #define _CLC3GLS2_LC3G3D3N 0x10
10509 #define _CLC3GLS2_D3N 0x10
10510 #define _CLC3GLS2_LC3G3D3T 0x20
10511 #define _CLC3GLS2_D3T 0x20
10512 #define _CLC3GLS2_LC3G3D4N 0x40
10513 #define _CLC3GLS2_D4N 0x40
10514 #define _CLC3GLS2_LC3G3D4T 0x80
10515 #define _CLC3GLS2_D4T 0x80
10517 //==============================================================================
10520 //==============================================================================
10523 extern __at(0x0F2D) __sfr CLC3GLS3
;
10529 unsigned LC3G4D1N
: 1;
10530 unsigned LC3G4D1T
: 1;
10531 unsigned LC3G4D2N
: 1;
10532 unsigned LC3G4D2T
: 1;
10533 unsigned LC3G4D3N
: 1;
10534 unsigned LC3G4D3T
: 1;
10535 unsigned LC3G4D4N
: 1;
10536 unsigned LC3G4D4T
: 1;
10541 unsigned G4D1N
: 1;
10542 unsigned G4D1T
: 1;
10543 unsigned G4D2N
: 1;
10544 unsigned G4D2T
: 1;
10545 unsigned G4D3N
: 1;
10546 unsigned G4D3T
: 1;
10547 unsigned G4D4N
: 1;
10548 unsigned G4D4T
: 1;
10550 } __CLC3GLS3bits_t
;
10552 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
10554 #define _CLC3GLS3_LC3G4D1N 0x01
10555 #define _CLC3GLS3_G4D1N 0x01
10556 #define _CLC3GLS3_LC3G4D1T 0x02
10557 #define _CLC3GLS3_G4D1T 0x02
10558 #define _CLC3GLS3_LC3G4D2N 0x04
10559 #define _CLC3GLS3_G4D2N 0x04
10560 #define _CLC3GLS3_LC3G4D2T 0x08
10561 #define _CLC3GLS3_G4D2T 0x08
10562 #define _CLC3GLS3_LC3G4D3N 0x10
10563 #define _CLC3GLS3_G4D3N 0x10
10564 #define _CLC3GLS3_LC3G4D3T 0x20
10565 #define _CLC3GLS3_G4D3T 0x20
10566 #define _CLC3GLS3_LC3G4D4N 0x40
10567 #define _CLC3GLS3_G4D4N 0x40
10568 #define _CLC3GLS3_LC3G4D4T 0x80
10569 #define _CLC3GLS3_G4D4T 0x80
10571 //==============================================================================
10574 //==============================================================================
10575 // STATUS_SHAD Bits
10577 extern __at(0x0FE4) __sfr STATUS_SHAD
;
10581 unsigned C_SHAD
: 1;
10582 unsigned DC_SHAD
: 1;
10583 unsigned Z_SHAD
: 1;
10589 } __STATUS_SHADbits_t
;
10591 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
10593 #define _C_SHAD 0x01
10594 #define _DC_SHAD 0x02
10595 #define _Z_SHAD 0x04
10597 //==============================================================================
10599 extern __at(0x0FE5) __sfr WREG_SHAD
;
10600 extern __at(0x0FE6) __sfr BSR_SHAD
;
10601 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
10602 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
10603 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
10604 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
10605 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
10606 extern __at(0x0FED) __sfr STKPTR
;
10607 extern __at(0x0FEE) __sfr TOSL
;
10608 extern __at(0x0FEF) __sfr TOSH
;
10610 //==============================================================================
10612 // Configuration Bits
10614 //==============================================================================
10616 #define _CONFIG1 0x8007
10617 #define _CONFIG2 0x8008
10619 //----------------------------- CONFIG1 Options -------------------------------
10621 #define _FOSC_LP 0x3FF8 // LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins.
10622 #define _FOSC_XT 0x3FF9 // XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins.
10623 #define _FOSC_HS 0x3FFA // HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins.
10624 #define _FOSC_EXTRC 0x3FFB // EXTRC oscillator: External RC circuit connected to CLKIN pin.
10625 #define _FOSC_INTOSC 0x3FFC // INTOSC oscillator: I/O function on CLKIN pin.
10626 #define _FOSC_ECL 0x3FFD // ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pins.
10627 #define _FOSC_ECM 0x3FFE // ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pins.
10628 #define _FOSC_ECH 0x3FFF // ECH, External Clock, High Power Mode (4-20 MHz): device clock supplied to CLKIN pins.
10629 #define _WDTE_OFF 0x3FE7 // WDT disabled.
10630 #define _WDTE_SWDTEN 0x3FEF // WDT controlled by the SWDTEN bit in the WDTCON register.
10631 #define _WDTE_NSLEEP 0x3FF7 // WDT enabled while running and disabled in Sleep.
10632 #define _WDTE_ON 0x3FFF // WDT enabled.
10633 #define _PWRTE_ON 0x3FDF // PWRT enabled.
10634 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
10635 #define _MCLRE_OFF 0x3FBF // MCLR/VPP pin function is digital input.
10636 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR.
10637 #define _CP_ON 0x3F7F // Program memory code protection is enabled.
10638 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
10639 #define _BOREN_OFF 0x39FF // Brown-out Reset disabled.
10640 #define _BOREN_SBODEN 0x3BFF // Brown-out Reset controlled by the SBOREN bit in the BORCON register.
10641 #define _BOREN_NSLEEP 0x3DFF // Brown-out Reset enabled while running and disabled in Sleep.
10642 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled.
10643 #define _CLKOUTEN_ON 0x37FF // CLKOUT function is enabled on the CLKOUT pin.
10644 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
10645 #define _IESO_OFF 0x2FFF // Internal/External Switchover Mode is disabled.
10646 #define _IESO_ON 0x3FFF // Internal/External Switchover Mode is enabled.
10647 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
10648 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
10650 //----------------------------- CONFIG2 Options -------------------------------
10652 #define _WRT_ALL 0x3FFC // 000h to 1FFFh write protected, no addresses may be modified by EECON control.
10653 #define _WRT_HALF 0x3FFD // 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control.
10654 #define _WRT_BOOT 0x3FFE // 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control.
10655 #define _WRT_OFF 0x3FFF // Write protection off.
10656 #define _PPS1WAY_OFF 0x3FFB // The PPSLOCK bit can be set and cleared repeatedly by software.
10657 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit cannot be cleared once it is set by software.
10658 #define _ZCD_ON 0x3F7F // Zero-cross detect circuit is enabled at POR.
10659 #define _ZCD_OFF 0x3FFF // Zero-cross detect circuit is disabled at POR.
10660 #define _PLLEN_OFF 0x3EFF // 4x PLL is enabled when software sets the SPLLEN bit.
10661 #define _PLLEN_ON 0x3FFF // 4x PLL is always enabled.
10662 #define _STVREN_OFF 0x3DFF // Stack Overflow or Underflow will not cause a Reset.
10663 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
10664 #define _BORV_HI 0x3BFF // Brown-out Reset Voltage (Vbor), high trip point selected.
10665 #define _BORV_LO 0x3FFF // Brown-out Reset Voltage (Vbor), low trip point selected.
10666 #define _LPBOR_ON 0x37FF // Low-Power BOR is enabled.
10667 #define _LPBOR_OFF 0x3FFF // Low-Power BOR is disabled.
10668 #define _DEBUG_ON 0x2FFF // In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger.
10669 #define _DEBUG_OFF 0x3FFF // In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins.
10670 #define _LVP_OFF 0x1FFF // High-voltage on MCLR/VPP must be used for programming.
10671 #define _LVP_ON 0x3FFF // Low-voltage programming enabled.
10673 //==============================================================================
10675 #define _DEVID1 0x8006
10677 #define _IDLOC0 0x8000
10678 #define _IDLOC1 0x8001
10679 #define _IDLOC2 0x8002
10680 #define _IDLOC3 0x8003
10682 //==============================================================================
10684 #ifndef NO_BIT_DEFINES
10686 #define ADON ADCON0bits.ADON // bit 0
10687 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
10688 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
10689 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
10690 #define CHS0 ADCON0bits.CHS0 // bit 2
10691 #define CHS1 ADCON0bits.CHS1 // bit 3
10692 #define CHS2 ADCON0bits.CHS2 // bit 4
10693 #define CHS3 ADCON0bits.CHS3 // bit 5
10694 #define CHS4 ADCON0bits.CHS4 // bit 6
10696 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
10697 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
10698 #define ADNREF ADCON1bits.ADNREF // bit 2
10699 #define ADFM ADCON1bits.ADFM // bit 7
10701 #define TRIGSEL0 ADCON2bits.TRIGSEL0 // bit 3
10702 #define TRIGSEL1 ADCON2bits.TRIGSEL1 // bit 4
10703 #define TRIGSEL2 ADCON2bits.TRIGSEL2 // bit 5
10704 #define TRIGSEL3 ADCON2bits.TRIGSEL3 // bit 6
10705 #define TRIGSEL4 ADCON2bits.TRIGSEL4 // bit 7
10707 #define ANSA0 ANSELAbits.ANSA0 // bit 0
10708 #define ANSA1 ANSELAbits.ANSA1 // bit 1
10709 #define ANSA2 ANSELAbits.ANSA2 // bit 2
10710 #define ANSA4 ANSELAbits.ANSA4 // bit 4
10712 #define ANSC0 ANSELCbits.ANSC0 // bit 0
10713 #define ANSC1 ANSELCbits.ANSC1 // bit 1
10714 #define ANSC2 ANSELCbits.ANSC2 // bit 2
10715 #define ANSC3 ANSELCbits.ANSC3 // bit 3
10717 #define ABDEN BAUD1CONbits.ABDEN // bit 0
10718 #define WUE BAUD1CONbits.WUE // bit 1
10719 #define BRG16 BAUD1CONbits.BRG16 // bit 3
10720 #define SCKP BAUD1CONbits.SCKP // bit 4
10721 #define RCIDL BAUD1CONbits.RCIDL // bit 6
10722 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
10724 #define BORRDY BORCONbits.BORRDY // bit 0
10725 #define BORFS BORCONbits.BORFS // bit 6
10726 #define SBOREN BORCONbits.SBOREN // bit 7
10728 #define BSR0 BSRbits.BSR0 // bit 0
10729 #define BSR1 BSRbits.BSR1 // bit 1
10730 #define BSR2 BSRbits.BSR2 // bit 2
10731 #define BSR3 BSRbits.BSR3 // bit 3
10732 #define BSR4 BSRbits.BSR4 // bit 4
10734 #define CTS0 CCP1CAPbits.CTS0 // bit 0, shadows bit in CCP1CAPbits
10735 #define CCP1CTS0 CCP1CAPbits.CCP1CTS0 // bit 0, shadows bit in CCP1CAPbits
10736 #define CTS1 CCP1CAPbits.CTS1 // bit 1, shadows bit in CCP1CAPbits
10737 #define CCP1CTS1 CCP1CAPbits.CCP1CTS1 // bit 1, shadows bit in CCP1CAPbits
10738 #define CTS2 CCP1CAPbits.CTS2 // bit 2, shadows bit in CCP1CAPbits
10739 #define CCP1CTS2 CCP1CAPbits.CCP1CTS2 // bit 2, shadows bit in CCP1CAPbits
10741 #define MODE0 CCP1CONbits.MODE0 // bit 0, shadows bit in CCP1CONbits
10742 #define CCP1MODE0 CCP1CONbits.CCP1MODE0 // bit 0, shadows bit in CCP1CONbits
10743 #define MODE1 CCP1CONbits.MODE1 // bit 1, shadows bit in CCP1CONbits
10744 #define CCP1MODE1 CCP1CONbits.CCP1MODE1 // bit 1, shadows bit in CCP1CONbits
10745 #define MODE2 CCP1CONbits.MODE2 // bit 2, shadows bit in CCP1CONbits
10746 #define CCP1MODE2 CCP1CONbits.CCP1MODE2 // bit 2, shadows bit in CCP1CONbits
10747 #define MODE3 CCP1CONbits.MODE3 // bit 3, shadows bit in CCP1CONbits
10748 #define CCP1MODE3 CCP1CONbits.CCP1MODE3 // bit 3, shadows bit in CCP1CONbits
10749 #define FMT CCP1CONbits.FMT // bit 4, shadows bit in CCP1CONbits
10750 #define CCP1FMT CCP1CONbits.CCP1FMT // bit 4, shadows bit in CCP1CONbits
10751 #define OUT CCP1CONbits.OUT // bit 5, shadows bit in CCP1CONbits
10752 #define CCP1OUT CCP1CONbits.CCP1OUT // bit 5, shadows bit in CCP1CONbits
10753 #define EN CCP1CONbits.EN // bit 7, shadows bit in CCP1CONbits
10754 #define CCP1EN CCP1CONbits.CCP1EN // bit 7, shadows bit in CCP1CONbits
10756 #define C1TSEL0 CCPTMRSbits.C1TSEL0 // bit 0
10757 #define C1TSEL1 CCPTMRSbits.C1TSEL1 // bit 1
10758 #define P3TSEL0 CCPTMRSbits.P3TSEL0 // bit 4
10759 #define P3TSEL1 CCPTMRSbits.P3TSEL1 // bit 5
10761 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
10762 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
10763 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
10764 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
10765 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
10766 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
10767 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
10768 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
10769 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
10770 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
10771 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
10772 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
10773 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
10774 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
10775 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
10776 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
10778 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
10779 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
10780 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
10781 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
10782 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
10783 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
10784 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
10785 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
10786 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
10787 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
10788 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
10789 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
10790 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
10791 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
10792 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
10793 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
10795 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
10796 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
10797 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
10798 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
10799 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
10800 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
10801 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
10802 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
10803 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
10804 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
10806 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
10807 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
10808 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
10809 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
10810 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
10811 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
10812 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
10813 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
10814 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
10815 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
10817 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
10818 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
10819 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
10820 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
10821 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
10822 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
10823 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
10824 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
10825 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
10826 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
10828 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
10829 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
10830 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
10831 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
10832 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
10833 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
10834 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
10835 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
10836 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
10837 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
10839 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
10840 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
10841 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
10842 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
10843 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
10844 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
10845 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
10846 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
10847 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
10848 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
10850 #define MCLC1OUT CLCDATAbits.MCLC1OUT // bit 0
10851 #define MCLC2OUT CLCDATAbits.MCLC2OUT // bit 1
10852 #define MCLC3OUT CLCDATAbits.MCLC3OUT // bit 2
10854 #define NCH0 CM1NSELbits.NCH0 // bit 0, shadows bit in CM1NSELbits
10855 #define C1NCH0 CM1NSELbits.C1NCH0 // bit 0, shadows bit in CM1NSELbits
10856 #define NCH1 CM1NSELbits.NCH1 // bit 1, shadows bit in CM1NSELbits
10857 #define C1NCH1 CM1NSELbits.C1NCH1 // bit 1, shadows bit in CM1NSELbits
10858 #define NCH2 CM1NSELbits.NCH2 // bit 2, shadows bit in CM1NSELbits
10859 #define C1NCH2 CM1NSELbits.C1NCH2 // bit 2, shadows bit in CM1NSELbits
10861 #define PCH0 CM1PSELbits.PCH0 // bit 0, shadows bit in CM1PSELbits
10862 #define C1PCH0 CM1PSELbits.C1PCH0 // bit 0, shadows bit in CM1PSELbits
10863 #define PCH1 CM1PSELbits.PCH1 // bit 1, shadows bit in CM1PSELbits
10864 #define C1PCH1 CM1PSELbits.C1PCH1 // bit 1, shadows bit in CM1PSELbits
10865 #define PCH2 CM1PSELbits.PCH2 // bit 2, shadows bit in CM1PSELbits
10866 #define C1PCH2 CM1PSELbits.C1PCH2 // bit 2, shadows bit in CM1PSELbits
10867 #define PCH3 CM1PSELbits.PCH3 // bit 3, shadows bit in CM1PSELbits
10868 #define C1PCH3 CM1PSELbits.C1PCH3 // bit 3, shadows bit in CM1PSELbits
10870 #define MC1OUT CMOUTbits.MC1OUT // bit 0
10871 #define MC2OUT CMOUTbits.MC2OUT // bit 1
10873 #define ASDAC0 COG1ASD0bits.ASDAC0 // bit 2, shadows bit in COG1ASD0bits
10874 #define G1ASDAC0 COG1ASD0bits.G1ASDAC0 // bit 2, shadows bit in COG1ASD0bits
10875 #define ASDAC1 COG1ASD0bits.ASDAC1 // bit 3, shadows bit in COG1ASD0bits
10876 #define G1ASDAC1 COG1ASD0bits.G1ASDAC1 // bit 3, shadows bit in COG1ASD0bits
10877 #define ASDBD0 COG1ASD0bits.ASDBD0 // bit 4, shadows bit in COG1ASD0bits
10878 #define G1ASDBD0 COG1ASD0bits.G1ASDBD0 // bit 4, shadows bit in COG1ASD0bits
10879 #define ASDBD1 COG1ASD0bits.ASDBD1 // bit 5, shadows bit in COG1ASD0bits
10880 #define G1ASDBD1 COG1ASD0bits.G1ASDBD1 // bit 5, shadows bit in COG1ASD0bits
10881 #define ASREN COG1ASD0bits.ASREN // bit 6, shadows bit in COG1ASD0bits
10882 #define ARSEN COG1ASD0bits.ARSEN // bit 6, shadows bit in COG1ASD0bits
10883 #define G1ARSEN COG1ASD0bits.G1ARSEN // bit 6, shadows bit in COG1ASD0bits
10884 #define G1ASREN COG1ASD0bits.G1ASREN // bit 6, shadows bit in COG1ASD0bits
10885 #define ASE COG1ASD0bits.ASE // bit 7, shadows bit in COG1ASD0bits
10886 #define G1ASE COG1ASD0bits.G1ASE // bit 7, shadows bit in COG1ASD0bits
10888 #define AS0E COG1ASD1bits.AS0E // bit 0, shadows bit in COG1ASD1bits
10889 #define G1AS0E COG1ASD1bits.G1AS0E // bit 0, shadows bit in COG1ASD1bits
10890 #define AS1E COG1ASD1bits.AS1E // bit 1, shadows bit in COG1ASD1bits
10891 #define G1AS1E COG1ASD1bits.G1AS1E // bit 1, shadows bit in COG1ASD1bits
10892 #define AS2E COG1ASD1bits.AS2E // bit 2, shadows bit in COG1ASD1bits
10893 #define G1AS2E COG1ASD1bits.G1AS2E // bit 2, shadows bit in COG1ASD1bits
10894 #define AS3E COG1ASD1bits.AS3E // bit 3, shadows bit in COG1ASD1bits
10895 #define G1AS3E COG1ASD1bits.G1AS3E // bit 3, shadows bit in COG1ASD1bits
10896 #define AS4E COG1ASD1bits.AS4E // bit 4, shadows bit in COG1ASD1bits
10897 #define G1AS4E COG1ASD1bits.G1AS4E // bit 4, shadows bit in COG1ASD1bits
10898 #define AS5E COG1ASD1bits.AS5E // bit 5, shadows bit in COG1ASD1bits
10899 #define G1AS5E COG1ASD1bits.G1AS5E // bit 5, shadows bit in COG1ASD1bits
10900 #define AS6E COG1ASD1bits.AS6E // bit 6, shadows bit in COG1ASD1bits
10901 #define G1AS6E COG1ASD1bits.G1AS6E // bit 6, shadows bit in COG1ASD1bits
10902 #define AS7E COG1ASD1bits.AS7E // bit 7, shadows bit in COG1ASD1bits
10903 #define G1AS7E COG1ASD1bits.G1AS7E // bit 7, shadows bit in COG1ASD1bits
10905 #define BLKF0 COG1BLKFbits.BLKF0 // bit 0, shadows bit in COG1BLKFbits
10906 #define G1BLKF0 COG1BLKFbits.G1BLKF0 // bit 0, shadows bit in COG1BLKFbits
10907 #define BLKF1 COG1BLKFbits.BLKF1 // bit 1, shadows bit in COG1BLKFbits
10908 #define G1BLKF1 COG1BLKFbits.G1BLKF1 // bit 1, shadows bit in COG1BLKFbits
10909 #define BLKF2 COG1BLKFbits.BLKF2 // bit 2, shadows bit in COG1BLKFbits
10910 #define G1BLKF2 COG1BLKFbits.G1BLKF2 // bit 2, shadows bit in COG1BLKFbits
10911 #define BLKF3 COG1BLKFbits.BLKF3 // bit 3, shadows bit in COG1BLKFbits
10912 #define G1BLKF3 COG1BLKFbits.G1BLKF3 // bit 3, shadows bit in COG1BLKFbits
10913 #define BLKF4 COG1BLKFbits.BLKF4 // bit 4, shadows bit in COG1BLKFbits
10914 #define G1BLKF4 COG1BLKFbits.G1BLKF4 // bit 4, shadows bit in COG1BLKFbits
10915 #define BLKF5 COG1BLKFbits.BLKF5 // bit 5, shadows bit in COG1BLKFbits
10916 #define G1BLKF5 COG1BLKFbits.G1BLKF5 // bit 5, shadows bit in COG1BLKFbits
10918 #define BLKR0 COG1BLKRbits.BLKR0 // bit 0, shadows bit in COG1BLKRbits
10919 #define G1BLKR0 COG1BLKRbits.G1BLKR0 // bit 0, shadows bit in COG1BLKRbits
10920 #define BLKR1 COG1BLKRbits.BLKR1 // bit 1, shadows bit in COG1BLKRbits
10921 #define G1BLKR1 COG1BLKRbits.G1BLKR1 // bit 1, shadows bit in COG1BLKRbits
10922 #define BLKR2 COG1BLKRbits.BLKR2 // bit 2, shadows bit in COG1BLKRbits
10923 #define G1BLKR2 COG1BLKRbits.G1BLKR2 // bit 2, shadows bit in COG1BLKRbits
10924 #define BLKR3 COG1BLKRbits.BLKR3 // bit 3, shadows bit in COG1BLKRbits
10925 #define G1BLKR3 COG1BLKRbits.G1BLKR3 // bit 3, shadows bit in COG1BLKRbits
10926 #define BLKR4 COG1BLKRbits.BLKR4 // bit 4, shadows bit in COG1BLKRbits
10927 #define G1BLKR4 COG1BLKRbits.G1BLKR4 // bit 4, shadows bit in COG1BLKRbits
10928 #define BLKR5 COG1BLKRbits.BLKR5 // bit 5, shadows bit in COG1BLKRbits
10929 #define G1BLKR5 COG1BLKRbits.G1BLKR5 // bit 5, shadows bit in COG1BLKRbits
10931 #define POLA COG1CON1bits.POLA // bit 0, shadows bit in COG1CON1bits
10932 #define G1POLA COG1CON1bits.G1POLA // bit 0, shadows bit in COG1CON1bits
10933 #define POLB COG1CON1bits.POLB // bit 1, shadows bit in COG1CON1bits
10934 #define G1POLB COG1CON1bits.G1POLB // bit 1, shadows bit in COG1CON1bits
10935 #define POLC COG1CON1bits.POLC // bit 2, shadows bit in COG1CON1bits
10936 #define G1POLC COG1CON1bits.G1POLC // bit 2, shadows bit in COG1CON1bits
10937 #define POLD COG1CON1bits.POLD // bit 3, shadows bit in COG1CON1bits
10938 #define G1POLD COG1CON1bits.G1POLD // bit 3, shadows bit in COG1CON1bits
10939 #define FDBS COG1CON1bits.FDBS // bit 6, shadows bit in COG1CON1bits
10940 #define G1FDBS COG1CON1bits.G1FDBS // bit 6, shadows bit in COG1CON1bits
10941 #define RDBS COG1CON1bits.RDBS // bit 7, shadows bit in COG1CON1bits
10942 #define G1RDBS COG1CON1bits.G1RDBS // bit 7, shadows bit in COG1CON1bits
10944 #define DBF0 COG1DBFbits.DBF0 // bit 0, shadows bit in COG1DBFbits
10945 #define G1DBF0 COG1DBFbits.G1DBF0 // bit 0, shadows bit in COG1DBFbits
10946 #define DBF1 COG1DBFbits.DBF1 // bit 1, shadows bit in COG1DBFbits
10947 #define G1DBF1 COG1DBFbits.G1DBF1 // bit 1, shadows bit in COG1DBFbits
10948 #define DBF2 COG1DBFbits.DBF2 // bit 2, shadows bit in COG1DBFbits
10949 #define G1DBF2 COG1DBFbits.G1DBF2 // bit 2, shadows bit in COG1DBFbits
10950 #define DBF3 COG1DBFbits.DBF3 // bit 3, shadows bit in COG1DBFbits
10951 #define G1DBF3 COG1DBFbits.G1DBF3 // bit 3, shadows bit in COG1DBFbits
10952 #define DBF4 COG1DBFbits.DBF4 // bit 4, shadows bit in COG1DBFbits
10953 #define G1DBF4 COG1DBFbits.G1DBF4 // bit 4, shadows bit in COG1DBFbits
10954 #define DBF5 COG1DBFbits.DBF5 // bit 5, shadows bit in COG1DBFbits
10955 #define G1DBF5 COG1DBFbits.G1DBF5 // bit 5, shadows bit in COG1DBFbits
10957 #define DBR0 COG1DBRbits.DBR0 // bit 0, shadows bit in COG1DBRbits
10958 #define G1DBR0 COG1DBRbits.G1DBR0 // bit 0, shadows bit in COG1DBRbits
10959 #define DBR1 COG1DBRbits.DBR1 // bit 1, shadows bit in COG1DBRbits
10960 #define G1DBR1 COG1DBRbits.G1DBR1 // bit 1, shadows bit in COG1DBRbits
10961 #define DBR2 COG1DBRbits.DBR2 // bit 2, shadows bit in COG1DBRbits
10962 #define G1DBR2 COG1DBRbits.G1DBR2 // bit 2, shadows bit in COG1DBRbits
10963 #define DBR3 COG1DBRbits.DBR3 // bit 3, shadows bit in COG1DBRbits
10964 #define G1DBR3 COG1DBRbits.G1DBR3 // bit 3, shadows bit in COG1DBRbits
10965 #define DBR4 COG1DBRbits.DBR4 // bit 4, shadows bit in COG1DBRbits
10966 #define G1DBR4 COG1DBRbits.G1DBR4 // bit 4, shadows bit in COG1DBRbits
10967 #define DBR5 COG1DBRbits.DBR5 // bit 5, shadows bit in COG1DBRbits
10968 #define G1DBR5 COG1DBRbits.G1DBR5 // bit 5, shadows bit in COG1DBRbits
10970 #define FIS0 COG1FIS0bits.FIS0 // bit 0, shadows bit in COG1FIS0bits
10971 #define G1FIS0 COG1FIS0bits.G1FIS0 // bit 0, shadows bit in COG1FIS0bits
10972 #define FIS1 COG1FIS0bits.FIS1 // bit 1, shadows bit in COG1FIS0bits
10973 #define G1FIS1 COG1FIS0bits.G1FIS1 // bit 1, shadows bit in COG1FIS0bits
10974 #define FIS2 COG1FIS0bits.FIS2 // bit 2, shadows bit in COG1FIS0bits
10975 #define G1FIS2 COG1FIS0bits.G1FIS2 // bit 2, shadows bit in COG1FIS0bits
10976 #define FIS3 COG1FIS0bits.FIS3 // bit 3, shadows bit in COG1FIS0bits
10977 #define G1FIS3 COG1FIS0bits.G1FIS3 // bit 3, shadows bit in COG1FIS0bits
10978 #define FIS4 COG1FIS0bits.FIS4 // bit 4, shadows bit in COG1FIS0bits
10979 #define G1FIS4 COG1FIS0bits.G1FIS4 // bit 4, shadows bit in COG1FIS0bits
10980 #define FIS5 COG1FIS0bits.FIS5 // bit 5, shadows bit in COG1FIS0bits
10981 #define G1FIS5 COG1FIS0bits.G1FIS5 // bit 5, shadows bit in COG1FIS0bits
10982 #define FIS6 COG1FIS0bits.FIS6 // bit 6, shadows bit in COG1FIS0bits
10983 #define G1FIS6 COG1FIS0bits.G1FIS6 // bit 6, shadows bit in COG1FIS0bits
10984 #define FIS7 COG1FIS0bits.FIS7 // bit 7, shadows bit in COG1FIS0bits
10985 #define G1FIS7 COG1FIS0bits.G1FIS7 // bit 7, shadows bit in COG1FIS0bits
10987 #define FIS8 COG1FIS1bits.FIS8 // bit 0, shadows bit in COG1FIS1bits
10988 #define G1FIS8 COG1FIS1bits.G1FIS8 // bit 0, shadows bit in COG1FIS1bits
10989 #define FIS9 COG1FIS1bits.FIS9 // bit 1, shadows bit in COG1FIS1bits
10990 #define G1FIS9 COG1FIS1bits.G1FIS9 // bit 1, shadows bit in COG1FIS1bits
10991 #define FIS10 COG1FIS1bits.FIS10 // bit 2, shadows bit in COG1FIS1bits
10992 #define G1FIS10 COG1FIS1bits.G1FIS10 // bit 2, shadows bit in COG1FIS1bits
10993 #define FIS11 COG1FIS1bits.FIS11 // bit 3, shadows bit in COG1FIS1bits
10994 #define G1FIS11 COG1FIS1bits.G1FIS11 // bit 3, shadows bit in COG1FIS1bits
10995 #define FIS12 COG1FIS1bits.FIS12 // bit 4, shadows bit in COG1FIS1bits
10996 #define G1FIS12 COG1FIS1bits.G1FIS12 // bit 4, shadows bit in COG1FIS1bits
10997 #define FIS13 COG1FIS1bits.FIS13 // bit 5, shadows bit in COG1FIS1bits
10998 #define G1FIS13 COG1FIS1bits.G1FIS13 // bit 5, shadows bit in COG1FIS1bits
10999 #define FIS14 COG1FIS1bits.FIS14 // bit 6, shadows bit in COG1FIS1bits
11000 #define G1FIS14 COG1FIS1bits.G1FIS14 // bit 6, shadows bit in COG1FIS1bits
11002 #define FSIM0 COG1FSIM0bits.FSIM0 // bit 0, shadows bit in COG1FSIM0bits
11003 #define G1FSIM0 COG1FSIM0bits.G1FSIM0 // bit 0, shadows bit in COG1FSIM0bits
11004 #define FSIM1 COG1FSIM0bits.FSIM1 // bit 1, shadows bit in COG1FSIM0bits
11005 #define G1FSIM1 COG1FSIM0bits.G1FSIM1 // bit 1, shadows bit in COG1FSIM0bits
11006 #define FSIM2 COG1FSIM0bits.FSIM2 // bit 2, shadows bit in COG1FSIM0bits
11007 #define G1FSIM2 COG1FSIM0bits.G1FSIM2 // bit 2, shadows bit in COG1FSIM0bits
11008 #define FSIM3 COG1FSIM0bits.FSIM3 // bit 3, shadows bit in COG1FSIM0bits
11009 #define G1FSIM3 COG1FSIM0bits.G1FSIM3 // bit 3, shadows bit in COG1FSIM0bits
11010 #define FSIM4 COG1FSIM0bits.FSIM4 // bit 4, shadows bit in COG1FSIM0bits
11011 #define G1FSIM4 COG1FSIM0bits.G1FSIM4 // bit 4, shadows bit in COG1FSIM0bits
11012 #define FSIM5 COG1FSIM0bits.FSIM5 // bit 5, shadows bit in COG1FSIM0bits
11013 #define G1FSIM5 COG1FSIM0bits.G1FSIM5 // bit 5, shadows bit in COG1FSIM0bits
11014 #define FSIM6 COG1FSIM0bits.FSIM6 // bit 6, shadows bit in COG1FSIM0bits
11015 #define G1FSIM6 COG1FSIM0bits.G1FSIM6 // bit 6, shadows bit in COG1FSIM0bits
11016 #define FSIM7 COG1FSIM0bits.FSIM7 // bit 7, shadows bit in COG1FSIM0bits
11017 #define G1FSIM7 COG1FSIM0bits.G1FSIM7 // bit 7, shadows bit in COG1FSIM0bits
11019 #define FSIM8 COG1FSIM1bits.FSIM8 // bit 0, shadows bit in COG1FSIM1bits
11020 #define G1FSIM8 COG1FSIM1bits.G1FSIM8 // bit 0, shadows bit in COG1FSIM1bits
11021 #define FSIM9 COG1FSIM1bits.FSIM9 // bit 1, shadows bit in COG1FSIM1bits
11022 #define G1FSIM9 COG1FSIM1bits.G1FSIM9 // bit 1, shadows bit in COG1FSIM1bits
11023 #define FSIM10 COG1FSIM1bits.FSIM10 // bit 2, shadows bit in COG1FSIM1bits
11024 #define G1FSIM10 COG1FSIM1bits.G1FSIM10 // bit 2, shadows bit in COG1FSIM1bits
11025 #define FSIM11 COG1FSIM1bits.FSIM11 // bit 3, shadows bit in COG1FSIM1bits
11026 #define G1FSIM11 COG1FSIM1bits.G1FSIM11 // bit 3, shadows bit in COG1FSIM1bits
11027 #define FSIM12 COG1FSIM1bits.FSIM12 // bit 4, shadows bit in COG1FSIM1bits
11028 #define G1FSIM12 COG1FSIM1bits.G1FSIM12 // bit 4, shadows bit in COG1FSIM1bits
11029 #define FSIM13 COG1FSIM1bits.FSIM13 // bit 5, shadows bit in COG1FSIM1bits
11030 #define G1FSIM13 COG1FSIM1bits.G1FSIM13 // bit 5, shadows bit in COG1FSIM1bits
11031 #define FSIM14 COG1FSIM1bits.FSIM14 // bit 6, shadows bit in COG1FSIM1bits
11032 #define G1FSIM14 COG1FSIM1bits.G1FSIM14 // bit 6, shadows bit in COG1FSIM1bits
11034 #define PHF0 COG1PHFbits.PHF0 // bit 0, shadows bit in COG1PHFbits
11035 #define G1PHF0 COG1PHFbits.G1PHF0 // bit 0, shadows bit in COG1PHFbits
11036 #define PHF1 COG1PHFbits.PHF1 // bit 1, shadows bit in COG1PHFbits
11037 #define G1PHF1 COG1PHFbits.G1PHF1 // bit 1, shadows bit in COG1PHFbits
11038 #define PHF2 COG1PHFbits.PHF2 // bit 2, shadows bit in COG1PHFbits
11039 #define G1PHF2 COG1PHFbits.G1PHF2 // bit 2, shadows bit in COG1PHFbits
11040 #define PHF3 COG1PHFbits.PHF3 // bit 3, shadows bit in COG1PHFbits
11041 #define G1PHF3 COG1PHFbits.G1PHF3 // bit 3, shadows bit in COG1PHFbits
11042 #define PHF4 COG1PHFbits.PHF4 // bit 4, shadows bit in COG1PHFbits
11043 #define G1PHF4 COG1PHFbits.G1PHF4 // bit 4, shadows bit in COG1PHFbits
11044 #define PHF5 COG1PHFbits.PHF5 // bit 5, shadows bit in COG1PHFbits
11045 #define G1PHF5 COG1PHFbits.G1PHF5 // bit 5, shadows bit in COG1PHFbits
11047 #define PHR0 COG1PHRbits.PHR0 // bit 0, shadows bit in COG1PHRbits
11048 #define G1PHR0 COG1PHRbits.G1PHR0 // bit 0, shadows bit in COG1PHRbits
11049 #define PHR1 COG1PHRbits.PHR1 // bit 1, shadows bit in COG1PHRbits
11050 #define G1PHR1 COG1PHRbits.G1PHR1 // bit 1, shadows bit in COG1PHRbits
11051 #define PHR2 COG1PHRbits.PHR2 // bit 2, shadows bit in COG1PHRbits
11052 #define G1PHR2 COG1PHRbits.G1PHR2 // bit 2, shadows bit in COG1PHRbits
11053 #define PHR3 COG1PHRbits.PHR3 // bit 3, shadows bit in COG1PHRbits
11054 #define G1PHR3 COG1PHRbits.G1PHR3 // bit 3, shadows bit in COG1PHRbits
11055 #define PHR4 COG1PHRbits.PHR4 // bit 4, shadows bit in COG1PHRbits
11056 #define G1PHR4 COG1PHRbits.G1PHR4 // bit 4, shadows bit in COG1PHRbits
11057 #define PHR5 COG1PHRbits.PHR5 // bit 5, shadows bit in COG1PHRbits
11058 #define G1PHR5 COG1PHRbits.G1PHR5 // bit 5, shadows bit in COG1PHRbits
11060 #define RIS0 COG1RIS0bits.RIS0 // bit 0, shadows bit in COG1RIS0bits
11061 #define G1RIS0 COG1RIS0bits.G1RIS0 // bit 0, shadows bit in COG1RIS0bits
11062 #define RIS1 COG1RIS0bits.RIS1 // bit 1, shadows bit in COG1RIS0bits
11063 #define G1RIS1 COG1RIS0bits.G1RIS1 // bit 1, shadows bit in COG1RIS0bits
11064 #define RIS2 COG1RIS0bits.RIS2 // bit 2, shadows bit in COG1RIS0bits
11065 #define G1RIS2 COG1RIS0bits.G1RIS2 // bit 2, shadows bit in COG1RIS0bits
11066 #define RIS3 COG1RIS0bits.RIS3 // bit 3, shadows bit in COG1RIS0bits
11067 #define G1RIS3 COG1RIS0bits.G1RIS3 // bit 3, shadows bit in COG1RIS0bits
11068 #define RIS4 COG1RIS0bits.RIS4 // bit 4, shadows bit in COG1RIS0bits
11069 #define G1RIS4 COG1RIS0bits.G1RIS4 // bit 4, shadows bit in COG1RIS0bits
11070 #define RIS5 COG1RIS0bits.RIS5 // bit 5, shadows bit in COG1RIS0bits
11071 #define G1RIS5 COG1RIS0bits.G1RIS5 // bit 5, shadows bit in COG1RIS0bits
11072 #define RIS6 COG1RIS0bits.RIS6 // bit 6, shadows bit in COG1RIS0bits
11073 #define G1RIS6 COG1RIS0bits.G1RIS6 // bit 6, shadows bit in COG1RIS0bits
11074 #define RIS7 COG1RIS0bits.RIS7 // bit 7, shadows bit in COG1RIS0bits
11075 #define G1RIS7 COG1RIS0bits.G1RIS7 // bit 7, shadows bit in COG1RIS0bits
11077 #define RIS8 COG1RIS1bits.RIS8 // bit 0, shadows bit in COG1RIS1bits
11078 #define G1RIS8 COG1RIS1bits.G1RIS8 // bit 0, shadows bit in COG1RIS1bits
11079 #define RIS9 COG1RIS1bits.RIS9 // bit 1, shadows bit in COG1RIS1bits
11080 #define G1RIS9 COG1RIS1bits.G1RIS9 // bit 1, shadows bit in COG1RIS1bits
11081 #define RIS10 COG1RIS1bits.RIS10 // bit 2, shadows bit in COG1RIS1bits
11082 #define G1RIS10 COG1RIS1bits.G1RIS10 // bit 2, shadows bit in COG1RIS1bits
11083 #define RIS11 COG1RIS1bits.RIS11 // bit 3, shadows bit in COG1RIS1bits
11084 #define G1RIS11 COG1RIS1bits.G1RIS11 // bit 3, shadows bit in COG1RIS1bits
11085 #define RIS12 COG1RIS1bits.RIS12 // bit 4, shadows bit in COG1RIS1bits
11086 #define G1RIS12 COG1RIS1bits.G1RIS12 // bit 4, shadows bit in COG1RIS1bits
11087 #define RIS13 COG1RIS1bits.RIS13 // bit 5, shadows bit in COG1RIS1bits
11088 #define G1RIS13 COG1RIS1bits.G1RIS13 // bit 5, shadows bit in COG1RIS1bits
11089 #define RIS14 COG1RIS1bits.RIS14 // bit 6, shadows bit in COG1RIS1bits
11090 #define G1RIS14 COG1RIS1bits.G1RIS14 // bit 6, shadows bit in COG1RIS1bits
11092 #define RSIM0 COG1RSIM0bits.RSIM0 // bit 0, shadows bit in COG1RSIM0bits
11093 #define G1RSIM0 COG1RSIM0bits.G1RSIM0 // bit 0, shadows bit in COG1RSIM0bits
11094 #define RSIM1 COG1RSIM0bits.RSIM1 // bit 1, shadows bit in COG1RSIM0bits
11095 #define G1RSIM1 COG1RSIM0bits.G1RSIM1 // bit 1, shadows bit in COG1RSIM0bits
11096 #define RSIM2 COG1RSIM0bits.RSIM2 // bit 2, shadows bit in COG1RSIM0bits
11097 #define G1RSIM2 COG1RSIM0bits.G1RSIM2 // bit 2, shadows bit in COG1RSIM0bits
11098 #define RSIM3 COG1RSIM0bits.RSIM3 // bit 3, shadows bit in COG1RSIM0bits
11099 #define G1RSIM3 COG1RSIM0bits.G1RSIM3 // bit 3, shadows bit in COG1RSIM0bits
11100 #define RSIM4 COG1RSIM0bits.RSIM4 // bit 4, shadows bit in COG1RSIM0bits
11101 #define G1RSIM4 COG1RSIM0bits.G1RSIM4 // bit 4, shadows bit in COG1RSIM0bits
11102 #define RSIM5 COG1RSIM0bits.RSIM5 // bit 5, shadows bit in COG1RSIM0bits
11103 #define G1RSIM5 COG1RSIM0bits.G1RSIM5 // bit 5, shadows bit in COG1RSIM0bits
11104 #define RSIM6 COG1RSIM0bits.RSIM6 // bit 6, shadows bit in COG1RSIM0bits
11105 #define G1RSIM6 COG1RSIM0bits.G1RSIM6 // bit 6, shadows bit in COG1RSIM0bits
11106 #define RSIM7 COG1RSIM0bits.RSIM7 // bit 7, shadows bit in COG1RSIM0bits
11107 #define G1RSIM7 COG1RSIM0bits.G1RSIM7 // bit 7, shadows bit in COG1RSIM0bits
11109 #define RSIM8 COG1RSIM1bits.RSIM8 // bit 0, shadows bit in COG1RSIM1bits
11110 #define G1RSIM8 COG1RSIM1bits.G1RSIM8 // bit 0, shadows bit in COG1RSIM1bits
11111 #define RSIM9 COG1RSIM1bits.RSIM9 // bit 1, shadows bit in COG1RSIM1bits
11112 #define G1RSIM9 COG1RSIM1bits.G1RSIM9 // bit 1, shadows bit in COG1RSIM1bits
11113 #define RSIM10 COG1RSIM1bits.RSIM10 // bit 2, shadows bit in COG1RSIM1bits
11114 #define G1RSIM10 COG1RSIM1bits.G1RSIM10 // bit 2, shadows bit in COG1RSIM1bits
11115 #define RSIM11 COG1RSIM1bits.RSIM11 // bit 3, shadows bit in COG1RSIM1bits
11116 #define G1RSIM11 COG1RSIM1bits.G1RSIM11 // bit 3, shadows bit in COG1RSIM1bits
11117 #define RSIM12 COG1RSIM1bits.RSIM12 // bit 4, shadows bit in COG1RSIM1bits
11118 #define G1RSIM12 COG1RSIM1bits.G1RSIM12 // bit 4, shadows bit in COG1RSIM1bits
11119 #define RSIM13 COG1RSIM1bits.RSIM13 // bit 5, shadows bit in COG1RSIM1bits
11120 #define G1RSIM13 COG1RSIM1bits.G1RSIM13 // bit 5, shadows bit in COG1RSIM1bits
11121 #define RSIM14 COG1RSIM1bits.RSIM14 // bit 6, shadows bit in COG1RSIM1bits
11122 #define G1RSIM14 COG1RSIM1bits.G1RSIM14 // bit 6, shadows bit in COG1RSIM1bits
11124 #define STRA COG1STRbits.STRA // bit 0, shadows bit in COG1STRbits
11125 #define G1STRA COG1STRbits.G1STRA // bit 0, shadows bit in COG1STRbits
11126 #define STRB COG1STRbits.STRB // bit 1, shadows bit in COG1STRbits
11127 #define G1STRB COG1STRbits.G1STRB // bit 1, shadows bit in COG1STRbits
11128 #define STRC COG1STRbits.STRC // bit 2, shadows bit in COG1STRbits
11129 #define G1STRC COG1STRbits.G1STRC // bit 2, shadows bit in COG1STRbits
11130 #define STRD COG1STRbits.STRD // bit 3, shadows bit in COG1STRbits
11131 #define G1STRD COG1STRbits.G1STRD // bit 3, shadows bit in COG1STRbits
11132 #define SDATA COG1STRbits.SDATA // bit 4, shadows bit in COG1STRbits
11133 #define G1SDATA COG1STRbits.G1SDATA // bit 4, shadows bit in COG1STRbits
11134 #define SDATB COG1STRbits.SDATB // bit 5, shadows bit in COG1STRbits
11135 #define G1SDATB COG1STRbits.G1SDATB // bit 5, shadows bit in COG1STRbits
11136 #define SDATC COG1STRbits.SDATC // bit 6, shadows bit in COG1STRbits
11137 #define G1SDATC COG1STRbits.G1SDATC // bit 6, shadows bit in COG1STRbits
11138 #define SDATD COG1STRbits.SDATD // bit 7, shadows bit in COG1STRbits
11139 #define G1SDATD COG1STRbits.G1SDATD // bit 7, shadows bit in COG1STRbits
11141 #define REF0 DAC1CON1bits.REF0 // bit 0, shadows bit in DAC1CON1bits
11142 #define DAC1REF0 DAC1CON1bits.DAC1REF0 // bit 0, shadows bit in DAC1CON1bits
11143 #define R0 DAC1CON1bits.R0 // bit 0, shadows bit in DAC1CON1bits
11144 #define DAC1R0 DAC1CON1bits.DAC1R0 // bit 0, shadows bit in DAC1CON1bits
11145 #define REF1 DAC1CON1bits.REF1 // bit 1, shadows bit in DAC1CON1bits
11146 #define DAC1REF1 DAC1CON1bits.DAC1REF1 // bit 1, shadows bit in DAC1CON1bits
11147 #define R1 DAC1CON1bits.R1 // bit 1, shadows bit in DAC1CON1bits
11148 #define DAC1R1 DAC1CON1bits.DAC1R1 // bit 1, shadows bit in DAC1CON1bits
11149 #define REF2 DAC1CON1bits.REF2 // bit 2, shadows bit in DAC1CON1bits
11150 #define DAC1REF2 DAC1CON1bits.DAC1REF2 // bit 2, shadows bit in DAC1CON1bits
11151 #define R2 DAC1CON1bits.R2 // bit 2, shadows bit in DAC1CON1bits
11152 #define DAC1R2 DAC1CON1bits.DAC1R2 // bit 2, shadows bit in DAC1CON1bits
11153 #define REF3 DAC1CON1bits.REF3 // bit 3, shadows bit in DAC1CON1bits
11154 #define DAC1REF3 DAC1CON1bits.DAC1REF3 // bit 3, shadows bit in DAC1CON1bits
11155 #define R3 DAC1CON1bits.R3 // bit 3, shadows bit in DAC1CON1bits
11156 #define DAC1R3 DAC1CON1bits.DAC1R3 // bit 3, shadows bit in DAC1CON1bits
11157 #define REF4 DAC1CON1bits.REF4 // bit 4, shadows bit in DAC1CON1bits
11158 #define DAC1REF4 DAC1CON1bits.DAC1REF4 // bit 4, shadows bit in DAC1CON1bits
11159 #define R4 DAC1CON1bits.R4 // bit 4, shadows bit in DAC1CON1bits
11160 #define DAC1R4 DAC1CON1bits.DAC1R4 // bit 4, shadows bit in DAC1CON1bits
11161 #define REF5 DAC1CON1bits.REF5 // bit 5, shadows bit in DAC1CON1bits
11162 #define DAC1REF5 DAC1CON1bits.DAC1REF5 // bit 5, shadows bit in DAC1CON1bits
11163 #define R5 DAC1CON1bits.R5 // bit 5, shadows bit in DAC1CON1bits
11164 #define DAC1R5 DAC1CON1bits.DAC1R5 // bit 5, shadows bit in DAC1CON1bits
11165 #define REF6 DAC1CON1bits.REF6 // bit 6, shadows bit in DAC1CON1bits
11166 #define DAC1REF6 DAC1CON1bits.DAC1REF6 // bit 6, shadows bit in DAC1CON1bits
11167 #define R6 DAC1CON1bits.R6 // bit 6, shadows bit in DAC1CON1bits
11168 #define DAC1R6 DAC1CON1bits.DAC1R6 // bit 6, shadows bit in DAC1CON1bits
11169 #define REF7 DAC1CON1bits.REF7 // bit 7, shadows bit in DAC1CON1bits
11170 #define DAC1REF7 DAC1CON1bits.DAC1REF7 // bit 7, shadows bit in DAC1CON1bits
11171 #define R7 DAC1CON1bits.R7 // bit 7, shadows bit in DAC1CON1bits
11172 #define DAC1R7 DAC1CON1bits.DAC1R7 // bit 7, shadows bit in DAC1CON1bits
11174 #define REF8 DAC1CON2bits.REF8 // bit 0, shadows bit in DAC1CON2bits
11175 #define DAC1REF8 DAC1CON2bits.DAC1REF8 // bit 0, shadows bit in DAC1CON2bits
11176 #define R8 DAC1CON2bits.R8 // bit 0, shadows bit in DAC1CON2bits
11177 #define DAC1R8 DAC1CON2bits.DAC1R8 // bit 0, shadows bit in DAC1CON2bits
11178 #define REF9 DAC1CON2bits.REF9 // bit 1, shadows bit in DAC1CON2bits
11179 #define DAC1REF9 DAC1CON2bits.DAC1REF9 // bit 1, shadows bit in DAC1CON2bits
11180 #define R9 DAC1CON2bits.R9 // bit 1, shadows bit in DAC1CON2bits
11181 #define DAC1R9 DAC1CON2bits.DAC1R9 // bit 1, shadows bit in DAC1CON2bits
11182 #define REF10 DAC1CON2bits.REF10 // bit 2, shadows bit in DAC1CON2bits
11183 #define DAC1REF10 DAC1CON2bits.DAC1REF10 // bit 2, shadows bit in DAC1CON2bits
11184 #define R10 DAC1CON2bits.R10 // bit 2, shadows bit in DAC1CON2bits
11185 #define DAC1R10 DAC1CON2bits.DAC1R10 // bit 2, shadows bit in DAC1CON2bits
11186 #define REF11 DAC1CON2bits.REF11 // bit 3, shadows bit in DAC1CON2bits
11187 #define DAC1REF11 DAC1CON2bits.DAC1REF11 // bit 3, shadows bit in DAC1CON2bits
11188 #define R11 DAC1CON2bits.R11 // bit 3, shadows bit in DAC1CON2bits
11189 #define DAC1R11 DAC1CON2bits.DAC1R11 // bit 3, shadows bit in DAC1CON2bits
11190 #define REF12 DAC1CON2bits.REF12 // bit 4, shadows bit in DAC1CON2bits
11191 #define DAC1REF12 DAC1CON2bits.DAC1REF12 // bit 4, shadows bit in DAC1CON2bits
11192 #define R12 DAC1CON2bits.R12 // bit 4, shadows bit in DAC1CON2bits
11193 #define DAC1R12 DAC1CON2bits.DAC1R12 // bit 4, shadows bit in DAC1CON2bits
11194 #define REF13 DAC1CON2bits.REF13 // bit 5, shadows bit in DAC1CON2bits
11195 #define DAC1REF13 DAC1CON2bits.DAC1REF13 // bit 5, shadows bit in DAC1CON2bits
11196 #define R13 DAC1CON2bits.R13 // bit 5, shadows bit in DAC1CON2bits
11197 #define DAC1R13 DAC1CON2bits.DAC1R13 // bit 5, shadows bit in DAC1CON2bits
11198 #define REF14 DAC1CON2bits.REF14 // bit 6, shadows bit in DAC1CON2bits
11199 #define DAC1REF14 DAC1CON2bits.DAC1REF14 // bit 6, shadows bit in DAC1CON2bits
11200 #define R14 DAC1CON2bits.R14 // bit 6, shadows bit in DAC1CON2bits
11201 #define DAC1R14 DAC1CON2bits.DAC1R14 // bit 6, shadows bit in DAC1CON2bits
11202 #define REF15 DAC1CON2bits.REF15 // bit 7, shadows bit in DAC1CON2bits
11203 #define DAC1REF15 DAC1CON2bits.DAC1REF15 // bit 7, shadows bit in DAC1CON2bits
11204 #define R15 DAC1CON2bits.R15 // bit 7, shadows bit in DAC1CON2bits
11205 #define DAC1R15 DAC1CON2bits.DAC1R15 // bit 7, shadows bit in DAC1CON2bits
11207 #define DAC1LD DACLDbits.DAC1LD // bit 0
11209 #define TSRNG FVRCONbits.TSRNG // bit 4
11210 #define TSEN FVRCONbits.TSEN // bit 5
11211 #define FVRRDY FVRCONbits.FVRRDY // bit 6
11212 #define FVREN FVRCONbits.FVREN // bit 7
11214 #define HIDC4 HIDRVCbits.HIDC4 // bit 4
11215 #define HIDC5 HIDRVCbits.HIDC5 // bit 5
11217 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
11218 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
11219 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
11220 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
11221 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
11222 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
11224 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
11225 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
11226 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
11227 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
11228 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
11229 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
11231 #define IOCIF INTCONbits.IOCIF // bit 0
11232 #define INTF INTCONbits.INTF // bit 1
11233 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
11234 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
11235 #define IOCIE INTCONbits.IOCIE // bit 3
11236 #define INTE INTCONbits.INTE // bit 4
11237 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
11238 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
11239 #define PEIE INTCONbits.PEIE // bit 6
11240 #define GIE INTCONbits.GIE // bit 7
11242 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
11243 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
11244 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
11245 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
11246 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
11247 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
11249 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
11250 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
11251 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
11252 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
11253 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
11254 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
11256 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
11257 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
11258 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
11259 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
11260 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
11261 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
11263 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
11264 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
11265 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
11266 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
11267 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
11268 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
11270 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
11271 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
11272 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
11273 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
11274 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
11275 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
11277 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
11278 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
11279 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
11280 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
11281 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
11282 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
11284 #define LATA0 LATAbits.LATA0 // bit 0
11285 #define LATA1 LATAbits.LATA1 // bit 1
11286 #define LATA2 LATAbits.LATA2 // bit 2
11287 #define LATA4 LATAbits.LATA4 // bit 4
11288 #define LATA5 LATAbits.LATA5 // bit 5
11290 #define LATC0 LATCbits.LATC0 // bit 0
11291 #define LATC1 LATCbits.LATC1 // bit 1
11292 #define LATC2 LATCbits.LATC2 // bit 2
11293 #define LATC3 LATCbits.LATC3 // bit 3
11294 #define LATC4 LATCbits.LATC4 // bit 4
11295 #define LATC5 LATCbits.LATC5 // bit 5
11297 #define CH0 MD1CARHbits.CH0 // bit 0, shadows bit in MD1CARHbits
11298 #define MD1CH0 MD1CARHbits.MD1CH0 // bit 0, shadows bit in MD1CARHbits
11299 #define CH1 MD1CARHbits.CH1 // bit 1, shadows bit in MD1CARHbits
11300 #define MD1CH1 MD1CARHbits.MD1CH1 // bit 1, shadows bit in MD1CARHbits
11301 #define CH2 MD1CARHbits.CH2 // bit 2, shadows bit in MD1CARHbits
11302 #define MD1CH2 MD1CARHbits.MD1CH2 // bit 2, shadows bit in MD1CARHbits
11303 #define CH3 MD1CARHbits.CH3 // bit 3, shadows bit in MD1CARHbits
11304 #define MD1CH3 MD1CARHbits.MD1CH3 // bit 3, shadows bit in MD1CARHbits
11306 #define CL0 MD1CARLbits.CL0 // bit 0, shadows bit in MD1CARLbits
11307 #define MD1CL0 MD1CARLbits.MD1CL0 // bit 0, shadows bit in MD1CARLbits
11308 #define CL1 MD1CARLbits.CL1 // bit 1, shadows bit in MD1CARLbits
11309 #define MD1CL1 MD1CARLbits.MD1CL1 // bit 1, shadows bit in MD1CARLbits
11310 #define CL2 MD1CARLbits.CL2 // bit 2, shadows bit in MD1CARLbits
11311 #define MD1CL2 MD1CARLbits.MD1CL2 // bit 2, shadows bit in MD1CARLbits
11312 #define CL3 MD1CARLbits.CL3 // bit 3, shadows bit in MD1CARLbits
11313 #define MD1CL3 MD1CARLbits.MD1CL3 // bit 3, shadows bit in MD1CARLbits
11315 #define CLSYNC MD1CON1bits.CLSYNC // bit 0, shadows bit in MD1CON1bits
11316 #define MD1CLSYNC MD1CON1bits.MD1CLSYNC // bit 0, shadows bit in MD1CON1bits
11317 #define CLPOL MD1CON1bits.CLPOL // bit 1, shadows bit in MD1CON1bits
11318 #define MD1CLPOL MD1CON1bits.MD1CLPOL // bit 1, shadows bit in MD1CON1bits
11319 #define CHSYNC MD1CON1bits.CHSYNC // bit 4, shadows bit in MD1CON1bits
11320 #define MD1CHSYNC MD1CON1bits.MD1CHSYNC // bit 4, shadows bit in MD1CON1bits
11321 #define CHPOL MD1CON1bits.CHPOL // bit 5, shadows bit in MD1CON1bits
11322 #define MD1CHPOL MD1CON1bits.MD1CHPOL // bit 5, shadows bit in MD1CON1bits
11324 #define MS0 MD1SRCbits.MS0 // bit 0, shadows bit in MD1SRCbits
11325 #define MD1MS0 MD1SRCbits.MD1MS0 // bit 0, shadows bit in MD1SRCbits
11326 #define MS1 MD1SRCbits.MS1 // bit 1, shadows bit in MD1SRCbits
11327 #define MD1MS1 MD1SRCbits.MD1MS1 // bit 1, shadows bit in MD1SRCbits
11328 #define MS2 MD1SRCbits.MS2 // bit 2, shadows bit in MD1SRCbits
11329 #define MD1MS2 MD1SRCbits.MD1MS2 // bit 2, shadows bit in MD1SRCbits
11330 #define MS3 MD1SRCbits.MS3 // bit 3, shadows bit in MD1SRCbits
11331 #define MD1MS3 MD1SRCbits.MD1MS3 // bit 3, shadows bit in MD1SRCbits
11332 #define MS4 MD1SRCbits.MS4 // bit 4, shadows bit in MD1SRCbits
11333 #define MD1MS4 MD1SRCbits.MD1MS4 // bit 4, shadows bit in MD1SRCbits
11335 #define ODA0 ODCONAbits.ODA0 // bit 0
11336 #define ODA1 ODCONAbits.ODA1 // bit 1
11337 #define ODA2 ODCONAbits.ODA2 // bit 2
11338 #define ODA4 ODCONAbits.ODA4 // bit 4
11339 #define ODA5 ODCONAbits.ODA5 // bit 5
11341 #define ODC0 ODCONCbits.ODC0 // bit 0
11342 #define ODC1 ODCONCbits.ODC1 // bit 1
11343 #define ODC2 ODCONCbits.ODC2 // bit 2
11344 #define ODC3 ODCONCbits.ODC3 // bit 3
11345 #define ODC4 ODCONCbits.ODC4 // bit 4
11346 #define ODC5 ODCONCbits.ODC5 // bit 5
11348 #define PS0 OPTION_REGbits.PS0 // bit 0
11349 #define PS1 OPTION_REGbits.PS1 // bit 1
11350 #define PS2 OPTION_REGbits.PS2 // bit 2
11351 #define PSA OPTION_REGbits.PSA // bit 3
11352 #define TMR0SE OPTION_REGbits.TMR0SE // bit 4, shadows bit in OPTION_REGbits
11353 #define T0SE OPTION_REGbits.T0SE // bit 4, shadows bit in OPTION_REGbits
11354 #define TMR0CS OPTION_REGbits.TMR0CS // bit 5, shadows bit in OPTION_REGbits
11355 #define T0CS OPTION_REGbits.T0CS // bit 5, shadows bit in OPTION_REGbits
11356 #define INTEDG OPTION_REGbits.INTEDG // bit 6
11357 #define NOT_WPUEN OPTION_REGbits.NOT_WPUEN // bit 7
11359 #define SCS0 OSCCONbits.SCS0 // bit 0
11360 #define SCS1 OSCCONbits.SCS1 // bit 1
11361 #define IRCF0 OSCCONbits.IRCF0 // bit 3
11362 #define IRCF1 OSCCONbits.IRCF1 // bit 4
11363 #define IRCF2 OSCCONbits.IRCF2 // bit 5
11364 #define IRCF3 OSCCONbits.IRCF3 // bit 6
11365 #define SPLLEN OSCCONbits.SPLLEN // bit 7
11367 #define HFIOFS OSCSTATbits.HFIOFS // bit 0
11368 #define LFIOFR OSCSTATbits.LFIOFR // bit 1
11369 #define MFIOFR OSCSTATbits.MFIOFR // bit 2
11370 #define HFIOFL OSCSTATbits.HFIOFL // bit 3
11371 #define HFIOFR OSCSTATbits.HFIOFR // bit 4
11372 #define OSTS OSCSTATbits.OSTS // bit 5
11373 #define PLLR OSCSTATbits.PLLR // bit 6
11374 #define SOSCR OSCSTATbits.SOSCR // bit 7
11376 #define TUN0 OSCTUNEbits.TUN0 // bit 0
11377 #define TUN1 OSCTUNEbits.TUN1 // bit 1
11378 #define TUN2 OSCTUNEbits.TUN2 // bit 2
11379 #define TUN3 OSCTUNEbits.TUN3 // bit 3
11380 #define TUN4 OSCTUNEbits.TUN4 // bit 4
11381 #define TUN5 OSCTUNEbits.TUN5 // bit 5
11383 #define NOT_BOR PCONbits.NOT_BOR // bit 0
11384 #define NOT_POR PCONbits.NOT_POR // bit 1
11385 #define NOT_RI PCONbits.NOT_RI // bit 2
11386 #define NOT_RMCLR PCONbits.NOT_RMCLR // bit 3
11387 #define NOT_RWDT PCONbits.NOT_RWDT // bit 4
11388 #define STKUNF PCONbits.STKUNF // bit 6
11389 #define STKOVF PCONbits.STKOVF // bit 7
11391 #define TMR1IE PIE1bits.TMR1IE // bit 0
11392 #define TMR2IE PIE1bits.TMR2IE // bit 1
11393 #define CCP1IE PIE1bits.CCP1IE // bit 2, shadows bit in PIE1bits
11394 #define CCPIE PIE1bits.CCPIE // bit 2, shadows bit in PIE1bits
11395 #define SSP1IE PIE1bits.SSP1IE // bit 3
11396 #define TXIE PIE1bits.TXIE // bit 4
11397 #define RCIE PIE1bits.RCIE // bit 5
11398 #define ADIE PIE1bits.ADIE // bit 6
11399 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
11401 #define BCL1IE PIE2bits.BCL1IE // bit 3
11402 #define C1IE PIE2bits.C1IE // bit 5
11403 #define C2IE PIE2bits.C2IE // bit 6
11404 #define OSFIE PIE2bits.OSFIE // bit 7
11406 #define CLC1IE PIE3bits.CLC1IE // bit 0
11407 #define CLC2IE PIE3bits.CLC2IE // bit 1
11408 #define CLC3IE PIE3bits.CLC3IE // bit 2
11409 #define ZCDIE PIE3bits.ZCDIE // bit 4
11410 #define COGIE PIE3bits.COGIE // bit 5
11411 #define PWM5IE PIE3bits.PWM5IE // bit 6
11413 #define TMR4IE PIE4bits.TMR4IE // bit 0
11414 #define TMR6IE PIE4bits.TMR6IE // bit 1
11415 #define TMR3IE PIE4bits.TMR3IE // bit 2
11416 #define TMR3GIE PIE4bits.TMR3GIE // bit 3
11417 #define TMR5IE PIE4bits.TMR5IE // bit 4
11418 #define TMR5GIE PIE4bits.TMR5GIE // bit 5
11420 #define TMR1IF PIR1bits.TMR1IF // bit 0
11421 #define TMR2IF PIR1bits.TMR2IF // bit 1
11422 #define CCP1IF PIR1bits.CCP1IF // bit 2, shadows bit in PIR1bits
11423 #define CCPIF PIR1bits.CCPIF // bit 2, shadows bit in PIR1bits
11424 #define SSP1IF PIR1bits.SSP1IF // bit 3
11425 #define TXIF PIR1bits.TXIF // bit 4
11426 #define RCIF PIR1bits.RCIF // bit 5
11427 #define ADIF PIR1bits.ADIF // bit 6
11428 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
11430 #define BCL1IF PIR2bits.BCL1IF // bit 3
11431 #define C1IF PIR2bits.C1IF // bit 5
11432 #define C2IF PIR2bits.C2IF // bit 6
11433 #define OSFIF PIR2bits.OSFIF // bit 7
11435 #define CLC1IF PIR3bits.CLC1IF // bit 0
11436 #define CLC2IF PIR3bits.CLC2IF // bit 1
11437 #define CLC3IF PIR3bits.CLC3IF // bit 2
11438 #define ZCDIF PIR3bits.ZCDIF // bit 4
11439 #define COG1IF PIR3bits.COG1IF // bit 5
11440 #define PWM5IF PIR3bits.PWM5IF // bit 6
11442 #define TMR4IF PIR4bits.TMR4IF // bit 0
11443 #define TMR6IF PIR4bits.TMR6IF // bit 1
11444 #define TMR3IF PIR4bits.TMR3IF // bit 2
11445 #define TMR3GIF PIR4bits.TMR3GIF // bit 3
11446 #define TMR5IF PIR4bits.TMR5IF // bit 4
11447 #define TMR5GIF PIR4bits.TMR5GIF // bit 5
11449 #define RD PMCON1bits.RD // bit 0
11450 #define WR PMCON1bits.WR // bit 1
11451 #define WREN PMCON1bits.WREN // bit 2
11452 #define WRERR PMCON1bits.WRERR // bit 3
11453 #define FREE PMCON1bits.FREE // bit 4
11454 #define LWLO PMCON1bits.LWLO // bit 5
11455 #define CFGS PMCON1bits.CFGS // bit 6
11457 #define RA0 PORTAbits.RA0 // bit 0
11458 #define RA1 PORTAbits.RA1 // bit 1
11459 #define RA2 PORTAbits.RA2 // bit 2
11460 #define RA3 PORTAbits.RA3 // bit 3
11461 #define RA4 PORTAbits.RA4 // bit 4
11462 #define RA5 PORTAbits.RA5 // bit 5
11464 #define RC0 PORTCbits.RC0 // bit 0
11465 #define RC1 PORTCbits.RC1 // bit 1
11466 #define RC2 PORTCbits.RC2 // bit 2
11467 #define RC3 PORTCbits.RC3 // bit 3
11468 #define RC4 PORTCbits.RC4 // bit 4
11469 #define RC5 PORTCbits.RC5 // bit 5
11471 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
11473 #define RPOL PRG1CON1bits.RPOL // bit 0, shadows bit in PRG1CON1bits
11474 #define RG1RPOL PRG1CON1bits.RG1RPOL // bit 0, shadows bit in PRG1CON1bits
11475 #define FPOL PRG1CON1bits.FPOL // bit 1, shadows bit in PRG1CON1bits
11476 #define RG1FPOL PRG1CON1bits.RG1FPOL // bit 1, shadows bit in PRG1CON1bits
11477 #define RDY PRG1CON1bits.RDY // bit 2, shadows bit in PRG1CON1bits
11478 #define RG1RDY PRG1CON1bits.RG1RDY // bit 2, shadows bit in PRG1CON1bits
11480 #define ISET0 PRG1CON2bits.ISET0 // bit 0, shadows bit in PRG1CON2bits
11481 #define RG1ISET0 PRG1CON2bits.RG1ISET0 // bit 0, shadows bit in PRG1CON2bits
11482 #define ISET1 PRG1CON2bits.ISET1 // bit 1, shadows bit in PRG1CON2bits
11483 #define RG1ISET1 PRG1CON2bits.RG1ISET1 // bit 1, shadows bit in PRG1CON2bits
11484 #define ISET2 PRG1CON2bits.ISET2 // bit 2, shadows bit in PRG1CON2bits
11485 #define RG1ISET2 PRG1CON2bits.RG1ISET2 // bit 2, shadows bit in PRG1CON2bits
11486 #define ISET3 PRG1CON2bits.ISET3 // bit 3, shadows bit in PRG1CON2bits
11487 #define RG1ISET3 PRG1CON2bits.RG1ISET3 // bit 3, shadows bit in PRG1CON2bits
11488 #define ISET4 PRG1CON2bits.ISET4 // bit 4, shadows bit in PRG1CON2bits
11489 #define RG1ISET4 PRG1CON2bits.RG1ISET4 // bit 4, shadows bit in PRG1CON2bits
11491 #define FTSS0 PRG1FTSSbits.FTSS0 // bit 0, shadows bit in PRG1FTSSbits
11492 #define RG1FTSS0 PRG1FTSSbits.RG1FTSS0 // bit 0, shadows bit in PRG1FTSSbits
11493 #define FTSS1 PRG1FTSSbits.FTSS1 // bit 1, shadows bit in PRG1FTSSbits
11494 #define RG1FTSS1 PRG1FTSSbits.RG1FTSS1 // bit 1, shadows bit in PRG1FTSSbits
11495 #define FTSS2 PRG1FTSSbits.FTSS2 // bit 2, shadows bit in PRG1FTSSbits
11496 #define RG1FTSS2 PRG1FTSSbits.RG1FTSS2 // bit 2, shadows bit in PRG1FTSSbits
11497 #define FTSS3 PRG1FTSSbits.FTSS3 // bit 3, shadows bit in PRG1FTSSbits
11498 #define RG1FTSS3 PRG1FTSSbits.RG1FTSS3 // bit 3, shadows bit in PRG1FTSSbits
11500 #define INS0 PRG1INSbits.INS0 // bit 0, shadows bit in PRG1INSbits
11501 #define RG1INS0 PRG1INSbits.RG1INS0 // bit 0, shadows bit in PRG1INSbits
11502 #define INS1 PRG1INSbits.INS1 // bit 1, shadows bit in PRG1INSbits
11503 #define RG1INS1 PRG1INSbits.RG1INS1 // bit 1, shadows bit in PRG1INSbits
11504 #define INS2 PRG1INSbits.INS2 // bit 2, shadows bit in PRG1INSbits
11505 #define RG1INS2 PRG1INSbits.RG1INS2 // bit 2, shadows bit in PRG1INSbits
11506 #define INS3 PRG1INSbits.INS3 // bit 3, shadows bit in PRG1INSbits
11507 #define RG1INS3 PRG1INSbits.RG1INS3 // bit 3, shadows bit in PRG1INSbits
11509 #define RTSS0 PRG1RTSSbits.RTSS0 // bit 0, shadows bit in PRG1RTSSbits
11510 #define RG1RTSS0 PRG1RTSSbits.RG1RTSS0 // bit 0, shadows bit in PRG1RTSSbits
11511 #define RTSS1 PRG1RTSSbits.RTSS1 // bit 1, shadows bit in PRG1RTSSbits
11512 #define RG1RTSS1 PRG1RTSSbits.RG1RTSS1 // bit 1, shadows bit in PRG1RTSSbits
11513 #define RTSS2 PRG1RTSSbits.RTSS2 // bit 2, shadows bit in PRG1RTSSbits
11514 #define RG1RTSS2 PRG1RTSSbits.RG1RTSS2 // bit 2, shadows bit in PRG1RTSSbits
11515 #define RTSS3 PRG1RTSSbits.RTSS3 // bit 3, shadows bit in PRG1RTSSbits
11516 #define RG1RTSS3 PRG1RTSSbits.RG1RTSS3 // bit 3, shadows bit in PRG1RTSSbits
11518 #define DC2 PWM3DCHbits.DC2 // bit 0, shadows bit in PWM3DCHbits
11519 #define PWM3DC2 PWM3DCHbits.PWM3DC2 // bit 0, shadows bit in PWM3DCHbits
11520 #define PWMPW2 PWM3DCHbits.PWMPW2 // bit 0, shadows bit in PWM3DCHbits
11521 #define DC3 PWM3DCHbits.DC3 // bit 1, shadows bit in PWM3DCHbits
11522 #define PWM3DC3 PWM3DCHbits.PWM3DC3 // bit 1, shadows bit in PWM3DCHbits
11523 #define PWMPW3 PWM3DCHbits.PWMPW3 // bit 1, shadows bit in PWM3DCHbits
11524 #define DC4 PWM3DCHbits.DC4 // bit 2, shadows bit in PWM3DCHbits
11525 #define PWM3DC4 PWM3DCHbits.PWM3DC4 // bit 2, shadows bit in PWM3DCHbits
11526 #define PWMPW4 PWM3DCHbits.PWMPW4 // bit 2, shadows bit in PWM3DCHbits
11527 #define DC5 PWM3DCHbits.DC5 // bit 3, shadows bit in PWM3DCHbits
11528 #define PWM3DC5 PWM3DCHbits.PWM3DC5 // bit 3, shadows bit in PWM3DCHbits
11529 #define PWMPW5 PWM3DCHbits.PWMPW5 // bit 3, shadows bit in PWM3DCHbits
11530 #define DC6 PWM3DCHbits.DC6 // bit 4, shadows bit in PWM3DCHbits
11531 #define PWM3DC6 PWM3DCHbits.PWM3DC6 // bit 4, shadows bit in PWM3DCHbits
11532 #define PWMPW6 PWM3DCHbits.PWMPW6 // bit 4, shadows bit in PWM3DCHbits
11533 #define DC7 PWM3DCHbits.DC7 // bit 5, shadows bit in PWM3DCHbits
11534 #define PWM3DC7 PWM3DCHbits.PWM3DC7 // bit 5, shadows bit in PWM3DCHbits
11535 #define PWMPW7 PWM3DCHbits.PWMPW7 // bit 5, shadows bit in PWM3DCHbits
11536 #define DC8 PWM3DCHbits.DC8 // bit 6, shadows bit in PWM3DCHbits
11537 #define PWM3DC8 PWM3DCHbits.PWM3DC8 // bit 6, shadows bit in PWM3DCHbits
11538 #define PWMPW8 PWM3DCHbits.PWMPW8 // bit 6, shadows bit in PWM3DCHbits
11539 #define DC9 PWM3DCHbits.DC9 // bit 7, shadows bit in PWM3DCHbits
11540 #define PWM3DC9 PWM3DCHbits.PWM3DC9 // bit 7, shadows bit in PWM3DCHbits
11541 #define PWMPW9 PWM3DCHbits.PWMPW9 // bit 7, shadows bit in PWM3DCHbits
11543 #define DC0 PWM3DCLbits.DC0 // bit 6, shadows bit in PWM3DCLbits
11544 #define PWM3DC0 PWM3DCLbits.PWM3DC0 // bit 6, shadows bit in PWM3DCLbits
11545 #define PWMPW0 PWM3DCLbits.PWMPW0 // bit 6, shadows bit in PWM3DCLbits
11546 #define DC1 PWM3DCLbits.DC1 // bit 7, shadows bit in PWM3DCLbits
11547 #define PWM3DC1 PWM3DCLbits.PWM3DC1 // bit 7, shadows bit in PWM3DCLbits
11548 #define PWMPW1 PWM3DCLbits.PWMPW1 // bit 7, shadows bit in PWM3DCLbits
11550 #define PWM5DCH0 PWM5DCHbits.PWM5DCH0 // bit 0
11551 #define PWM5DCH1 PWM5DCHbits.PWM5DCH1 // bit 1
11552 #define PWM5DCH2 PWM5DCHbits.PWM5DCH2 // bit 2
11553 #define PWM5DCH3 PWM5DCHbits.PWM5DCH3 // bit 3
11554 #define PWM5DCH4 PWM5DCHbits.PWM5DCH4 // bit 4
11555 #define PWM5DCH5 PWM5DCHbits.PWM5DCH5 // bit 5
11556 #define PWM5DCH6 PWM5DCHbits.PWM5DCH6 // bit 6
11557 #define PWM5DCH7 PWM5DCHbits.PWM5DCH7 // bit 7
11559 #define PWM5DCL0 PWM5DCLbits.PWM5DCL0 // bit 0
11560 #define PWM5DCL1 PWM5DCLbits.PWM5DCL1 // bit 1
11561 #define PWM5DCL2 PWM5DCLbits.PWM5DCL2 // bit 2
11562 #define PWM5DCL3 PWM5DCLbits.PWM5DCL3 // bit 3
11563 #define PWM5DCL4 PWM5DCLbits.PWM5DCL4 // bit 4
11564 #define PWM5DCL5 PWM5DCLbits.PWM5DCL5 // bit 5
11565 #define PWM5DCL6 PWM5DCLbits.PWM5DCL6 // bit 6
11566 #define PWM5DCL7 PWM5DCLbits.PWM5DCL7 // bit 7
11568 #define PRIE PWM5INTCONbits.PRIE // bit 0, shadows bit in PWM5INTCONbits
11569 #define PWM5PRIE PWM5INTCONbits.PWM5PRIE // bit 0, shadows bit in PWM5INTCONbits
11570 #define DCIE PWM5INTCONbits.DCIE // bit 1, shadows bit in PWM5INTCONbits
11571 #define PWM5DCIE PWM5INTCONbits.PWM5DCIE // bit 1, shadows bit in PWM5INTCONbits
11572 #define PHIE PWM5INTCONbits.PHIE // bit 2, shadows bit in PWM5INTCONbits
11573 #define PWM5PHIE PWM5INTCONbits.PWM5PHIE // bit 2, shadows bit in PWM5INTCONbits
11574 #define OFIE PWM5INTCONbits.OFIE // bit 3, shadows bit in PWM5INTCONbits
11575 #define PWM5OFIE PWM5INTCONbits.PWM5OFIE // bit 3, shadows bit in PWM5INTCONbits
11577 #define PRIF PWM5INTFbits.PRIF // bit 0, shadows bit in PWM5INTFbits
11578 #define PWM5PRIF PWM5INTFbits.PWM5PRIF // bit 0, shadows bit in PWM5INTFbits
11579 #define DCIF PWM5INTFbits.DCIF // bit 1, shadows bit in PWM5INTFbits
11580 #define PWM5DCIF PWM5INTFbits.PWM5DCIF // bit 1, shadows bit in PWM5INTFbits
11581 #define PHIF PWM5INTFbits.PHIF // bit 2, shadows bit in PWM5INTFbits
11582 #define PWM5PHIF PWM5INTFbits.PWM5PHIF // bit 2, shadows bit in PWM5INTFbits
11583 #define OFIF PWM5INTFbits.OFIF // bit 3, shadows bit in PWM5INTFbits
11584 #define PWM5OFIF PWM5INTFbits.PWM5OFIF // bit 3, shadows bit in PWM5INTFbits
11586 #define LDA PWM5LDCONbits.LDA // bit 7, shadows bit in PWM5LDCONbits
11587 #define PWM5LD PWM5LDCONbits.PWM5LD // bit 7, shadows bit in PWM5LDCONbits
11589 #define OFO PWM5OFCONbits.OFO // bit 4, shadows bit in PWM5OFCONbits
11590 #define PWM5OFMC PWM5OFCONbits.PWM5OFMC // bit 4, shadows bit in PWM5OFCONbits
11592 #define PWM5OFH0 PWM5OFHbits.PWM5OFH0 // bit 0
11593 #define PWM5OFH1 PWM5OFHbits.PWM5OFH1 // bit 1
11594 #define PWM5OFH2 PWM5OFHbits.PWM5OFH2 // bit 2
11595 #define PWM5OFH3 PWM5OFHbits.PWM5OFH3 // bit 3
11596 #define PWM5OFH4 PWM5OFHbits.PWM5OFH4 // bit 4
11597 #define PWM5OFH5 PWM5OFHbits.PWM5OFH5 // bit 5
11598 #define PWM5OFH6 PWM5OFHbits.PWM5OFH6 // bit 6
11599 #define PWM5OFH7 PWM5OFHbits.PWM5OFH7 // bit 7
11601 #define PWM5OFL0 PWM5OFLbits.PWM5OFL0 // bit 0
11602 #define PWM5OFL1 PWM5OFLbits.PWM5OFL1 // bit 1
11603 #define PWM5OFL2 PWM5OFLbits.PWM5OFL2 // bit 2
11604 #define PWM5OFL3 PWM5OFLbits.PWM5OFL3 // bit 3
11605 #define PWM5OFL4 PWM5OFLbits.PWM5OFL4 // bit 4
11606 #define PWM5OFL5 PWM5OFLbits.PWM5OFL5 // bit 5
11607 #define PWM5OFL6 PWM5OFLbits.PWM5OFL6 // bit 6
11608 #define PWM5OFL7 PWM5OFLbits.PWM5OFL7 // bit 7
11610 #define PWM5PHH0 PWM5PHHbits.PWM5PHH0 // bit 0
11611 #define PWM5PHH1 PWM5PHHbits.PWM5PHH1 // bit 1
11612 #define PWM5PHH2 PWM5PHHbits.PWM5PHH2 // bit 2
11613 #define PWM5PHH3 PWM5PHHbits.PWM5PHH3 // bit 3
11614 #define PWM5PHH4 PWM5PHHbits.PWM5PHH4 // bit 4
11615 #define PWM5PHH5 PWM5PHHbits.PWM5PHH5 // bit 5
11616 #define PWM5PHH6 PWM5PHHbits.PWM5PHH6 // bit 6
11617 #define PWM5PHH7 PWM5PHHbits.PWM5PHH7 // bit 7
11619 #define PWM5PHL0 PWM5PHLbits.PWM5PHL0 // bit 0
11620 #define PWM5PHL1 PWM5PHLbits.PWM5PHL1 // bit 1
11621 #define PWM5PHL2 PWM5PHLbits.PWM5PHL2 // bit 2
11622 #define PWM5PHL3 PWM5PHLbits.PWM5PHL3 // bit 3
11623 #define PWM5PHL4 PWM5PHLbits.PWM5PHL4 // bit 4
11624 #define PWM5PHL5 PWM5PHLbits.PWM5PHL5 // bit 5
11625 #define PWM5PHL6 PWM5PHLbits.PWM5PHL6 // bit 6
11626 #define PWM5PHL7 PWM5PHLbits.PWM5PHL7 // bit 7
11628 #define PWM5PRH0 PWM5PRHbits.PWM5PRH0 // bit 0
11629 #define PWM5PRH1 PWM5PRHbits.PWM5PRH1 // bit 1
11630 #define PWM5PRH2 PWM5PRHbits.PWM5PRH2 // bit 2
11631 #define PWM5PRH3 PWM5PRHbits.PWM5PRH3 // bit 3
11632 #define PWM5PRH4 PWM5PRHbits.PWM5PRH4 // bit 4
11633 #define PWM5PRH5 PWM5PRHbits.PWM5PRH5 // bit 5
11634 #define PWM5PRH6 PWM5PRHbits.PWM5PRH6 // bit 6
11635 #define PWM5PRH7 PWM5PRHbits.PWM5PRH7 // bit 7
11637 #define PWM5PRL0 PWM5PRLbits.PWM5PRL0 // bit 0
11638 #define PWM5PRL1 PWM5PRLbits.PWM5PRL1 // bit 1
11639 #define PWM5PRL2 PWM5PRLbits.PWM5PRL2 // bit 2
11640 #define PWM5PRL3 PWM5PRLbits.PWM5PRL3 // bit 3
11641 #define PWM5PRL4 PWM5PRLbits.PWM5PRL4 // bit 4
11642 #define PWM5PRL5 PWM5PRLbits.PWM5PRL5 // bit 5
11643 #define PWM5PRL6 PWM5PRLbits.PWM5PRL6 // bit 6
11644 #define PWM5PRL7 PWM5PRLbits.PWM5PRL7 // bit 7
11646 #define PWM5TMRH0 PWM5TMRHbits.PWM5TMRH0 // bit 0
11647 #define PWM5TMRH1 PWM5TMRHbits.PWM5TMRH1 // bit 1
11648 #define PWM5TMRH2 PWM5TMRHbits.PWM5TMRH2 // bit 2
11649 #define PWM5TMRH3 PWM5TMRHbits.PWM5TMRH3 // bit 3
11650 #define PWM5TMRH4 PWM5TMRHbits.PWM5TMRH4 // bit 4
11651 #define PWM5TMRH5 PWM5TMRHbits.PWM5TMRH5 // bit 5
11652 #define PWM5TMRH6 PWM5TMRHbits.PWM5TMRH6 // bit 6
11653 #define PWM5TMRH7 PWM5TMRHbits.PWM5TMRH7 // bit 7
11655 #define PWM5TMRL0 PWM5TMRLbits.PWM5TMRL0 // bit 0
11656 #define PWM5TMRL1 PWM5TMRLbits.PWM5TMRL1 // bit 1
11657 #define PWM5TMRL2 PWM5TMRLbits.PWM5TMRL2 // bit 2
11658 #define PWM5TMRL3 PWM5TMRLbits.PWM5TMRL3 // bit 3
11659 #define PWM5TMRL4 PWM5TMRLbits.PWM5TMRL4 // bit 4
11660 #define PWM5TMRL5 PWM5TMRLbits.PWM5TMRL5 // bit 5
11661 #define PWM5TMRL6 PWM5TMRLbits.PWM5TMRL6 // bit 6
11662 #define PWM5TMRL7 PWM5TMRLbits.PWM5TMRL7 // bit 7
11664 #define MPWM5EN PWMENbits.MPWM5EN // bit 4
11666 #define MPWM5LD PWMLDbits.MPWM5LD // bit 4
11668 #define MPWM5OUT PWMOUTbits.MPWM5OUT // bit 4
11670 #define RX9D RC1STAbits.RX9D // bit 0
11671 #define OERR RC1STAbits.OERR // bit 1
11672 #define FERR RC1STAbits.FERR // bit 2
11673 #define ADDEN RC1STAbits.ADDEN // bit 3
11674 #define CREN RC1STAbits.CREN // bit 4
11675 #define SREN RC1STAbits.SREN // bit 5
11676 #define RX9 RC1STAbits.RX9 // bit 6
11677 #define SPEN RC1STAbits.SPEN // bit 7
11679 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
11680 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
11681 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
11682 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
11683 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
11685 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
11686 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
11687 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
11688 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
11689 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
11690 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
11692 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
11693 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
11694 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
11695 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
11696 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
11697 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
11698 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
11699 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
11700 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
11701 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
11702 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
11703 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
11704 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
11705 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
11706 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
11707 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
11709 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
11710 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
11711 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
11712 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
11713 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
11714 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
11715 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
11716 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
11717 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
11718 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
11719 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
11720 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
11721 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
11722 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
11723 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
11724 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
11726 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
11727 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
11728 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
11729 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
11730 #define CKP SSP1CONbits.CKP // bit 4
11731 #define SSPEN SSP1CONbits.SSPEN // bit 5
11732 #define SSPOV SSP1CONbits.SSPOV // bit 6
11733 #define WCOL SSP1CONbits.WCOL // bit 7
11735 #define SEN SSP1CON2bits.SEN // bit 0
11736 #define RSEN SSP1CON2bits.RSEN // bit 1
11737 #define PEN SSP1CON2bits.PEN // bit 2
11738 #define RCEN SSP1CON2bits.RCEN // bit 3
11739 #define ACKEN SSP1CON2bits.ACKEN // bit 4
11740 #define ACKDT SSP1CON2bits.ACKDT // bit 5
11741 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
11742 #define GCEN SSP1CON2bits.GCEN // bit 7
11744 #define DHEN SSP1CON3bits.DHEN // bit 0
11745 #define AHEN SSP1CON3bits.AHEN // bit 1
11746 #define SBCDE SSP1CON3bits.SBCDE // bit 2
11747 #define SDAHT SSP1CON3bits.SDAHT // bit 3
11748 #define BOEN SSP1CON3bits.BOEN // bit 4
11749 #define SCIE SSP1CON3bits.SCIE // bit 5
11750 #define PCIE SSP1CON3bits.PCIE // bit 6
11751 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
11753 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
11754 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
11755 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
11756 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
11757 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
11758 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
11759 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
11760 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
11761 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
11762 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
11763 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
11764 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
11765 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
11766 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
11767 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
11768 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
11770 #define BF SSP1STATbits.BF // bit 0
11771 #define UA SSP1STATbits.UA // bit 1
11772 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
11773 #define S SSP1STATbits.S // bit 3
11774 #define P SSP1STATbits.P // bit 4
11775 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
11776 #define CKE SSP1STATbits.CKE // bit 6
11777 #define SMP SSP1STATbits.SMP // bit 7
11779 #define C STATUSbits.C // bit 0
11780 #define DC STATUSbits.DC // bit 1
11781 #define Z STATUSbits.Z // bit 2
11782 #define NOT_PD STATUSbits.NOT_PD // bit 3
11783 #define NOT_TO STATUSbits.NOT_TO // bit 4
11785 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
11786 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
11787 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
11789 #define GSS0 T1GCONbits.GSS0 // bit 0, shadows bit in T1GCONbits
11790 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0, shadows bit in T1GCONbits
11791 #define GSS1 T1GCONbits.GSS1 // bit 1, shadows bit in T1GCONbits
11792 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1, shadows bit in T1GCONbits
11793 #define GVAL T1GCONbits.GVAL // bit 2, shadows bit in T1GCONbits
11794 #define T1GVAL T1GCONbits.T1GVAL // bit 2, shadows bit in T1GCONbits
11795 #define GGO_NOT_DONE T1GCONbits.GGO_NOT_DONE // bit 3, shadows bit in T1GCONbits
11796 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3, shadows bit in T1GCONbits
11797 #define GSPM T1GCONbits.GSPM // bit 4, shadows bit in T1GCONbits
11798 #define T1GSPM T1GCONbits.T1GSPM // bit 4, shadows bit in T1GCONbits
11799 #define GTM T1GCONbits.GTM // bit 5, shadows bit in T1GCONbits
11800 #define T1GTM T1GCONbits.T1GTM // bit 5, shadows bit in T1GCONbits
11801 #define GPOL T1GCONbits.GPOL // bit 6, shadows bit in T1GCONbits
11802 #define T1GPOL T1GCONbits.T1GPOL // bit 6, shadows bit in T1GCONbits
11803 #define GE T1GCONbits.GE // bit 7, shadows bit in T1GCONbits
11804 #define T1GE T1GCONbits.T1GE // bit 7, shadows bit in T1GCONbits
11805 #define TMR1GE T1GCONbits.TMR1GE // bit 7, shadows bit in T1GCONbits
11807 #define RSEL0 T2RSTbits.RSEL0 // bit 0, shadows bit in T2RSTbits
11808 #define T2RSEL0 T2RSTbits.T2RSEL0 // bit 0, shadows bit in T2RSTbits
11809 #define RSEL1 T2RSTbits.RSEL1 // bit 1, shadows bit in T2RSTbits
11810 #define T2RSEL1 T2RSTbits.T2RSEL1 // bit 1, shadows bit in T2RSTbits
11811 #define RSEL2 T2RSTbits.RSEL2 // bit 2, shadows bit in T2RSTbits
11812 #define T2RSEL2 T2RSTbits.T2RSEL2 // bit 2, shadows bit in T2RSTbits
11813 #define RSEL3 T2RSTbits.RSEL3 // bit 3, shadows bit in T2RSTbits
11814 #define T2RSEL3 T2RSTbits.T2RSEL3 // bit 3, shadows bit in T2RSTbits
11816 #define TRISA0 TRISAbits.TRISA0 // bit 0
11817 #define TRISA1 TRISAbits.TRISA1 // bit 1
11818 #define TRISA2 TRISAbits.TRISA2 // bit 2
11819 #define TRISA4 TRISAbits.TRISA4 // bit 4
11820 #define TRISA5 TRISAbits.TRISA5 // bit 5
11822 #define TRISC0 TRISCbits.TRISC0 // bit 0
11823 #define TRISC1 TRISCbits.TRISC1 // bit 1
11824 #define TRISC2 TRISCbits.TRISC2 // bit 2
11825 #define TRISC3 TRISCbits.TRISC3 // bit 3
11826 #define TRISC4 TRISCbits.TRISC4 // bit 4
11827 #define TRISC5 TRISCbits.TRISC5 // bit 5
11829 #define SWDTEN WDTCONbits.SWDTEN // bit 0
11830 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
11831 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
11832 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
11833 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
11834 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
11836 #define WPUA0 WPUAbits.WPUA0 // bit 0
11837 #define WPUA1 WPUAbits.WPUA1 // bit 1
11838 #define WPUA2 WPUAbits.WPUA2 // bit 2
11839 #define WPUA3 WPUAbits.WPUA3 // bit 3
11840 #define WPUA4 WPUAbits.WPUA4 // bit 4
11841 #define WPUA5 WPUAbits.WPUA5 // bit 5
11843 #define WPUC0 WPUCbits.WPUC0 // bit 0
11844 #define WPUC1 WPUCbits.WPUC1 // bit 1
11845 #define WPUC2 WPUCbits.WPUC2 // bit 2
11846 #define WPUC3 WPUCbits.WPUC3 // bit 3
11847 #define WPUC4 WPUCbits.WPUC4 // bit 4
11848 #define WPUC5 WPUCbits.WPUC5 // bit 5
11850 #define ZCD1INTN ZCD1CONbits.ZCD1INTN // bit 0
11851 #define ZCD1INTP ZCD1CONbits.ZCD1INTP // bit 1
11852 #define ZCD1POL ZCD1CONbits.ZCD1POL // bit 4
11853 #define ZCD1OUT ZCD1CONbits.ZCD1OUT // bit 5
11854 #define ZCD1EN ZCD1CONbits.ZCD1EN // bit 7
11856 #endif // #ifndef NO_BIT_DEFINES
11858 #endif // #ifndef __PIC16F1765_H__