2 * This declarations of the PIC16F1773 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:15 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F1773_H__
26 #define __PIC16F1773_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTB_ADDR 0x000D
52 #define PORTC_ADDR 0x000E
53 #define PORTE_ADDR 0x0010
54 #define PIR1_ADDR 0x0011
55 #define PIR2_ADDR 0x0012
56 #define PIR3_ADDR 0x0013
57 #define PIR4_ADDR 0x0014
58 #define PIR5_ADDR 0x0015
59 #define PIR6_ADDR 0x0016
60 #define TMR0_ADDR 0x0017
61 #define TMR1_ADDR 0x0018
62 #define TMR1L_ADDR 0x0018
63 #define TMR1H_ADDR 0x0019
64 #define T1CON_ADDR 0x001A
65 #define T1GCON_ADDR 0x001B
66 #define TMR3_ADDR 0x001C
67 #define TMR3L_ADDR 0x001C
68 #define TMR3H_ADDR 0x001D
69 #define T3CON_ADDR 0x001E
70 #define T3GCON_ADDR 0x001F
71 #define TRISA_ADDR 0x008C
72 #define TRISB_ADDR 0x008D
73 #define TRISC_ADDR 0x008E
74 #define TRISE_ADDR 0x0090
75 #define PIE1_ADDR 0x0091
76 #define PIE2_ADDR 0x0092
77 #define PIE3_ADDR 0x0093
78 #define PIE4_ADDR 0x0094
79 #define PIE5_ADDR 0x0095
80 #define PIE6_ADDR 0x0096
81 #define OPTION_REG_ADDR 0x0097
82 #define PCON_ADDR 0x0098
83 #define WDTCON_ADDR 0x0099
84 #define OSCTUNE_ADDR 0x009A
85 #define OSCCON_ADDR 0x009B
86 #define OSCSTAT_ADDR 0x009C
87 #define BORCON_ADDR 0x009D
88 #define FVRCON_ADDR 0x009E
89 #define ZCD1CON_ADDR 0x009F
90 #define LATA_ADDR 0x010C
91 #define LATB_ADDR 0x010D
92 #define LATC_ADDR 0x010E
93 #define CMOUT_ADDR 0x0111
94 #define CM1CON0_ADDR 0x0112
95 #define CM1CON1_ADDR 0x0113
96 #define CM1NSEL_ADDR 0x0114
97 #define CM1PSEL_ADDR 0x0115
98 #define CM2CON0_ADDR 0x0116
99 #define CM2CON1_ADDR 0x0117
100 #define CM2NSEL_ADDR 0x0118
101 #define CM2PSEL_ADDR 0x0119
102 #define CM3CON0_ADDR 0x011A
103 #define CM3CON1_ADDR 0x011B
104 #define CM3NSEL_ADDR 0x011C
105 #define CM3PSEL_ADDR 0x011D
106 #define ANSELA_ADDR 0x018C
107 #define ANSELB_ADDR 0x018D
108 #define ANSELC_ADDR 0x018E
109 #define PMADR_ADDR 0x0191
110 #define PMADRL_ADDR 0x0191
111 #define PMADRH_ADDR 0x0192
112 #define PMDAT_ADDR 0x0193
113 #define PMDATL_ADDR 0x0193
114 #define PMDATH_ADDR 0x0194
115 #define PMCON1_ADDR 0x0195
116 #define PMCON2_ADDR 0x0196
117 #define VREGCON_ADDR 0x0197
118 #define RC1REG_ADDR 0x0199
119 #define RCREG_ADDR 0x0199
120 #define RCREG1_ADDR 0x0199
121 #define TX1REG_ADDR 0x019A
122 #define TXREG_ADDR 0x019A
123 #define TXREG1_ADDR 0x019A
124 #define SP1BRG_ADDR 0x019B
125 #define SP1BRGL_ADDR 0x019B
126 #define SPBRG_ADDR 0x019B
127 #define SPBRG1_ADDR 0x019B
128 #define SPBRGL_ADDR 0x019B
129 #define SP1BRGH_ADDR 0x019C
130 #define SPBRGH_ADDR 0x019C
131 #define SPBRGH1_ADDR 0x019C
132 #define RC1STA_ADDR 0x019D
133 #define RCSTA_ADDR 0x019D
134 #define RCSTA1_ADDR 0x019D
135 #define TX1STA_ADDR 0x019E
136 #define TXSTA_ADDR 0x019E
137 #define TXSTA1_ADDR 0x019E
138 #define BAUD1CON_ADDR 0x019F
139 #define BAUDCON_ADDR 0x019F
140 #define BAUDCON1_ADDR 0x019F
141 #define BAUDCTL_ADDR 0x019F
142 #define BAUDCTL1_ADDR 0x019F
143 #define WPUA_ADDR 0x020C
144 #define WPUB_ADDR 0x020D
145 #define WPUC_ADDR 0x020E
146 #define WPUE_ADDR 0x0210
147 #define SSP1BUF_ADDR 0x0211
148 #define SSPBUF_ADDR 0x0211
149 #define SSP1ADD_ADDR 0x0212
150 #define SSPADD_ADDR 0x0212
151 #define SSP1MSK_ADDR 0x0213
152 #define SSPMSK_ADDR 0x0213
153 #define SSP1STAT_ADDR 0x0214
154 #define SSPSTAT_ADDR 0x0214
155 #define SSP1CON_ADDR 0x0215
156 #define SSP1CON1_ADDR 0x0215
157 #define SSPCON_ADDR 0x0215
158 #define SSPCON1_ADDR 0x0215
159 #define SSP1CON2_ADDR 0x0216
160 #define SSPCON2_ADDR 0x0216
161 #define SSP1CON3_ADDR 0x0217
162 #define SSPCON3_ADDR 0x0217
163 #define MD3CON0_ADDR 0x021B
164 #define MD3CON1_ADDR 0x021C
165 #define MD3SRC_ADDR 0x021D
166 #define MD3CARL_ADDR 0x021E
167 #define MD3CARH_ADDR 0x021F
168 #define ODCONA_ADDR 0x028C
169 #define ODCONB_ADDR 0x028D
170 #define ODCONC_ADDR 0x028E
171 #define CCPR1_ADDR 0x0291
172 #define CCPR1L_ADDR 0x0291
173 #define CCPR1H_ADDR 0x0292
174 #define CCP1CON_ADDR 0x0293
175 #define CCP1CAP_ADDR 0x0294
176 #define CCPR2_ADDR 0x0295
177 #define CCPR2L_ADDR 0x0295
178 #define CCPR2H_ADDR 0x0296
179 #define CCP2CON_ADDR 0x0297
180 #define CCP2CAP_ADDR 0x0298
181 #define CCPR7_ADDR 0x0299
182 #define CCPR7L_ADDR 0x0299
183 #define CCPR7H_ADDR 0x029A
184 #define CCP7CON_ADDR 0x029B
185 #define CCP7CAP_ADDR 0x029C
186 #define CCPTMRS1_ADDR 0x029E
187 #define CCPTMRS2_ADDR 0x029F
188 #define SLRCONA_ADDR 0x030C
189 #define SLRCONB_ADDR 0x030D
190 #define SLRCONC_ADDR 0x030E
191 #define MD1CON0_ADDR 0x0315
192 #define MD1CON1_ADDR 0x0316
193 #define MD1SRC_ADDR 0x0317
194 #define MD1CARL_ADDR 0x0318
195 #define MD1CARH_ADDR 0x0319
196 #define MD2CON0_ADDR 0x031B
197 #define MD2CON1_ADDR 0x031C
198 #define MD2SRC_ADDR 0x031D
199 #define MD2CARL_ADDR 0x031E
200 #define MD2CARH_ADDR 0x031F
201 #define INLVLA_ADDR 0x038C
202 #define INLVLB_ADDR 0x038D
203 #define INLVLC_ADDR 0x038E
204 #define INLVE_ADDR 0x0390
205 #define IOCAP_ADDR 0x0391
206 #define IOCAN_ADDR 0x0392
207 #define IOCAF_ADDR 0x0393
208 #define IOCBP_ADDR 0x0394
209 #define IOCBN_ADDR 0x0395
210 #define IOCBF_ADDR 0x0396
211 #define IOCCP_ADDR 0x0397
212 #define IOCCN_ADDR 0x0398
213 #define IOCCF_ADDR 0x0399
214 #define IOCEP_ADDR 0x039D
215 #define IOCEN_ADDR 0x039E
216 #define IOCEF_ADDR 0x039F
217 #define HIDRVB_ADDR 0x040D
218 #define TMR5_ADDR 0x040F
219 #define TMR5L_ADDR 0x040F
220 #define TMR5H_ADDR 0x0410
221 #define T5CON_ADDR 0x0411
222 #define T5GCON_ADDR 0x0412
223 #define T4TMR_ADDR 0x0413
224 #define TMR4_ADDR 0x0413
225 #define PR4_ADDR 0x0414
226 #define T4PR_ADDR 0x0414
227 #define T4CON_ADDR 0x0415
228 #define T4HLT_ADDR 0x0416
229 #define T4CLKCON_ADDR 0x0417
230 #define T4RST_ADDR 0x0418
231 #define T6TMR_ADDR 0x041A
232 #define TMR6_ADDR 0x041A
233 #define PR6_ADDR 0x041B
234 #define T6PR_ADDR 0x041B
235 #define T6CON_ADDR 0x041C
236 #define T6HLT_ADDR 0x041D
237 #define T6CLKCON_ADDR 0x041E
238 #define T6RST_ADDR 0x041F
239 #define ADRESL_ADDR 0x048E
240 #define ADRESH_ADDR 0x048F
241 #define ADCON0_ADDR 0x0490
242 #define ADCON1_ADDR 0x0491
243 #define ADCON2_ADDR 0x0492
244 #define T2TMR_ADDR 0x0493
245 #define TMR2_ADDR 0x0493
246 #define PR2_ADDR 0x0494
247 #define T2PR_ADDR 0x0494
248 #define T2CON_ADDR 0x0495
249 #define T2HLT_ADDR 0x0496
250 #define T2CLKCON_ADDR 0x0497
251 #define T2RST_ADDR 0x0498
252 #define T8TMR_ADDR 0x049A
253 #define TMR8_ADDR 0x049A
254 #define PR8_ADDR 0x049B
255 #define T8PR_ADDR 0x049B
256 #define T8CON_ADDR 0x049C
257 #define T8HLT_ADDR 0x049D
258 #define T8CLKCON_ADDR 0x049E
259 #define T8RST_ADDR 0x049F
260 #define OPA1NCHS_ADDR 0x050F
261 #define OPA1PCHS_ADDR 0x0510
262 #define OPA1CON_ADDR 0x0511
263 #define OPA1ORS_ADDR 0x0512
264 #define OPA2NCHS_ADDR 0x0513
265 #define OPA2PCHS_ADDR 0x0514
266 #define OPA2CON_ADDR 0x0515
267 #define OPA2ORS_ADDR 0x0516
268 #define OPA3NCHS_ADDR 0x0517
269 #define OPA3PCHS_ADDR 0x0518
270 #define OPA3CON_ADDR 0x0519
271 #define OPA3ORS_ADDR 0x051A
272 #define DACLD_ADDR 0x058D
273 #define DAC1CON0_ADDR 0x058E
274 #define DAC1CON1_ADDR 0x058F
275 #define DAC1REF_ADDR 0x058F
276 #define DAC1REFL_ADDR 0x058F
277 #define DAC1CON2_ADDR 0x0590
278 #define DAC1REFH_ADDR 0x0590
279 #define DAC2CON0_ADDR 0x0591
280 #define DAC2CON1_ADDR 0x0592
281 #define DAC2REF_ADDR 0x0592
282 #define DAC2REFL_ADDR 0x0592
283 #define DAC2CON2_ADDR 0x0593
284 #define DAC2REFH_ADDR 0x0593
285 #define DAC3CON0_ADDR 0x0594
286 #define DAC3CON1_ADDR 0x0595
287 #define DAC3REF_ADDR 0x0595
288 #define DAC4CON0_ADDR 0x0596
289 #define DAC4CON1_ADDR 0x0597
290 #define DAC4REF_ADDR 0x0597
291 #define DAC5CON0_ADDR 0x0598
292 #define DAC5CON1_ADDR 0x0599
293 #define DAC5REF_ADDR 0x0599
294 #define DAC5REFL_ADDR 0x0599
295 #define DAC5CON2_ADDR 0x059A
296 #define DAC5REFH_ADDR 0x059A
297 #define DAC7CON0_ADDR 0x059E
298 #define DAC7CON1_ADDR 0x059F
299 #define DAC7REF_ADDR 0x059F
300 #define PWM3DCL_ADDR 0x0614
301 #define PWM3DCH_ADDR 0x0615
302 #define PWM3CON_ADDR 0x0616
303 #define PWM4DCL_ADDR 0x0617
304 #define PWM4DCH_ADDR 0x0618
305 #define PWM4CON_ADDR 0x0619
306 #define PWM9DCL_ADDR 0x061A
307 #define PWM9DCH_ADDR 0x061B
308 #define PWM9CON_ADDR 0x061C
309 #define COG1PHR_ADDR 0x068D
310 #define COG1PHF_ADDR 0x068E
311 #define COG1BLKR_ADDR 0x068F
312 #define COG1BLKF_ADDR 0x0690
313 #define COG1DBR_ADDR 0x0691
314 #define COG1DBF_ADDR 0x0692
315 #define COG1CON0_ADDR 0x0693
316 #define COG1CON1_ADDR 0x0694
317 #define COG1RIS0_ADDR 0x0695
318 #define COG1RIS1_ADDR 0x0696
319 #define COG1RSIM0_ADDR 0x0697
320 #define COG1RSIM1_ADDR 0x0698
321 #define COG1FIS0_ADDR 0x0699
322 #define COG1FIS1_ADDR 0x069A
323 #define COG1FSIM0_ADDR 0x069B
324 #define COG1FSIM1_ADDR 0x069C
325 #define COG1ASD0_ADDR 0x069D
326 #define COG1ASD1_ADDR 0x069E
327 #define COG1STR_ADDR 0x069F
328 #define COG2PHR_ADDR 0x070D
329 #define COG2PHF_ADDR 0x070E
330 #define COG2BLKR_ADDR 0x070F
331 #define COG2BLKF_ADDR 0x0710
332 #define COG2DBR_ADDR 0x0711
333 #define COG2DBF_ADDR 0x0712
334 #define COG2CON0_ADDR 0x0713
335 #define COG2CON1_ADDR 0x0714
336 #define COG2RIS0_ADDR 0x0715
337 #define COG2RIS1_ADDR 0x0716
338 #define COG2RSIM0_ADDR 0x0717
339 #define COG2RSIM1_ADDR 0x0718
340 #define COG2FIS0_ADDR 0x0719
341 #define COG2FIS1_ADDR 0x071A
342 #define COG2FSIM0_ADDR 0x071B
343 #define COG2FSIM1_ADDR 0x071C
344 #define COG2ASD0_ADDR 0x071D
345 #define COG2ASD1_ADDR 0x071E
346 #define COG2STR_ADDR 0x071F
347 #define PRG1RTSS_ADDR 0x078E
348 #define PRG1FTSS_ADDR 0x078F
349 #define PRG1INS_ADDR 0x0790
350 #define PRG1CON0_ADDR 0x0791
351 #define PRG1CON1_ADDR 0x0792
352 #define PRG1CON2_ADDR 0x0793
353 #define PRG2RTSS_ADDR 0x0794
354 #define PRG2FTSS_ADDR 0x0795
355 #define PRG2INS_ADDR 0x0796
356 #define PRG2CON0_ADDR 0x0797
357 #define PRG2CON1_ADDR 0x0798
358 #define PRG2CON2_ADDR 0x0799
359 #define PRG3RTSS_ADDR 0x079A
360 #define PRG3FTSS_ADDR 0x079B
361 #define PRG3INS_ADDR 0x079C
362 #define PRG3CON0_ADDR 0x079D
363 #define PRG3CON1_ADDR 0x079E
364 #define PRG3CON2_ADDR 0x079F
365 #define COG3PHR_ADDR 0x080D
366 #define COG3PHF_ADDR 0x080E
367 #define COG3BLKR_ADDR 0x080F
368 #define COG3BLKF_ADDR 0x0810
369 #define COG3DBR_ADDR 0x0811
370 #define COG3DBF_ADDR 0x0812
371 #define COG3CON0_ADDR 0x0813
372 #define COG3CON1_ADDR 0x0814
373 #define COG3RIS0_ADDR 0x0815
374 #define COG3RIS1_ADDR 0x0816
375 #define COG3RSIM0_ADDR 0x0817
376 #define COG3RSIM1_ADDR 0x0818
377 #define COG3FIS0_ADDR 0x0819
378 #define COG3FIS1_ADDR 0x081A
379 #define COG3FSIM0_ADDR 0x081B
380 #define COG3FSIM1_ADDR 0x081C
381 #define COG3ASD0_ADDR 0x081D
382 #define COG3ASD1_ADDR 0x081E
383 #define COG3STR_ADDR 0x081F
384 #define CM4CON0_ADDR 0x090C
385 #define CM4CON1_ADDR 0x090D
386 #define CM4NSEL_ADDR 0x090E
387 #define CM4PSEL_ADDR 0x090F
388 #define CM5CON0_ADDR 0x0910
389 #define CM5CON1_ADDR 0x0911
390 #define CM5NSEL_ADDR 0x0912
391 #define CM5PSEL_ADDR 0x0913
392 #define CM6CON0_ADDR 0x0914
393 #define CM6CON1_ADDR 0x0915
394 #define CM6NSEL_ADDR 0x0916
395 #define CM6PSEL_ADDR 0x0917
396 #define PWMEN_ADDR 0x0D8E
397 #define PWMLD_ADDR 0x0D8F
398 #define PWMOUT_ADDR 0x0D90
399 #define PWM5PH_ADDR 0x0D91
400 #define PWM5PHL_ADDR 0x0D91
401 #define PWM5PHH_ADDR 0x0D92
402 #define PWM5DC_ADDR 0x0D93
403 #define PWM5DCL_ADDR 0x0D93
404 #define PWM5DCH_ADDR 0x0D94
405 #define PWM5PR_ADDR 0x0D95
406 #define PWM5PRL_ADDR 0x0D95
407 #define PWM5PRH_ADDR 0x0D96
408 #define PWM5OF_ADDR 0x0D97
409 #define PWM5OFL_ADDR 0x0D97
410 #define PWM5OFH_ADDR 0x0D98
411 #define PWM5TMR_ADDR 0x0D99
412 #define PWM5TMRL_ADDR 0x0D99
413 #define PWM5TMRH_ADDR 0x0D9A
414 #define PWM5CON_ADDR 0x0D9B
415 #define PWM5INTCON_ADDR 0x0D9C
416 #define PWM5INTE_ADDR 0x0D9C
417 #define PWM5INTF_ADDR 0x0D9D
418 #define PWM5INTFLG_ADDR 0x0D9D
419 #define PWM5CLKCON_ADDR 0x0D9E
420 #define PWM5LDCON_ADDR 0x0D9F
421 #define PWM5OFCON_ADDR 0x0DA0
422 #define PWM6PH_ADDR 0x0DA1
423 #define PWM6PHL_ADDR 0x0DA1
424 #define PWM6PHH_ADDR 0x0DA2
425 #define PWM6DC_ADDR 0x0DA3
426 #define PWM6DCL_ADDR 0x0DA3
427 #define PWM6DCH_ADDR 0x0DA4
428 #define PWM6PR_ADDR 0x0DA5
429 #define PWM6PRL_ADDR 0x0DA5
430 #define PWM6PRH_ADDR 0x0DA6
431 #define PWM6OF_ADDR 0x0DA7
432 #define PWM6OFL_ADDR 0x0DA7
433 #define PWM6OFH_ADDR 0x0DA8
434 #define PWM6TMR_ADDR 0x0DA9
435 #define PWM6TMRL_ADDR 0x0DA9
436 #define PWM6TMRH_ADDR 0x0DAA
437 #define PWM6CON_ADDR 0x0DAB
438 #define PWM6INTCON_ADDR 0x0DAC
439 #define PWM6INTE_ADDR 0x0DAC
440 #define PWM6INTF_ADDR 0x0DAD
441 #define PWM6INTFLG_ADDR 0x0DAD
442 #define PWM6CLKCON_ADDR 0x0DAE
443 #define PWM6LDCON_ADDR 0x0DAF
444 #define PWM6OFCON_ADDR 0x0DB0
445 #define PWM11PH_ADDR 0x0DB1
446 #define PWM11PHL_ADDR 0x0DB1
447 #define PWM11PHH_ADDR 0x0DB2
448 #define PWM11DC_ADDR 0x0DB3
449 #define PWM11DCL_ADDR 0x0DB3
450 #define PWM11DCH_ADDR 0x0DB4
451 #define PWM11PR_ADDR 0x0DB5
452 #define PWM11PRL_ADDR 0x0DB5
453 #define PWM11PRH_ADDR 0x0DB6
454 #define PWM11OF_ADDR 0x0DB7
455 #define PWM11OFL_ADDR 0x0DB7
456 #define PWM11OFH_ADDR 0x0DB8
457 #define PWM11TMR_ADDR 0x0DB9
458 #define PWM11TMRL_ADDR 0x0DB9
459 #define PWM11TMRH_ADDR 0x0DBA
460 #define PWM11CON_ADDR 0x0DBB
461 #define PWM11INTCON_ADDR 0x0DBC
462 #define PWM11INTE_ADDR 0x0DBC
463 #define PWM11INTF_ADDR 0x0DBD
464 #define PWM11INTFLG_ADDR 0x0DBD
465 #define PWM11CLKCON_ADDR 0x0DBE
466 #define PWM11LDCON_ADDR 0x0DBF
467 #define PWM11OFCON_ADDR 0x0DC0
468 #define PPSLOCK_ADDR 0x0E0C
469 #define INTPPS_ADDR 0x0E0D
470 #define T0CKIPPS_ADDR 0x0E0E
471 #define T1CKIPPS_ADDR 0x0E0F
472 #define T1GPPS_ADDR 0x0E10
473 #define T3CKIPPS_ADDR 0x0E11
474 #define T3GPPS_ADDR 0x0E12
475 #define T5CKIPPS_ADDR 0x0E13
476 #define T5GPPS_ADDR 0x0E14
477 #define T2CKIPPS_ADDR 0x0E15
478 #define T4CKIPPS_ADDR 0x0E16
479 #define T6CKIPPS_ADDR 0x0E17
480 #define T8CKIPPS_ADDR 0x0E18
481 #define CCP1PPS_ADDR 0x0E19
482 #define CCP2PPS_ADDR 0x0E1A
483 #define CCP7PPS_ADDR 0x0E1B
484 #define COG1INPPS_ADDR 0x0E1D
485 #define COG2INPPS_ADDR 0x0E1E
486 #define COG3INPPS_ADDR 0x0E1F
487 #define MD1CLPPS_ADDR 0x0E21
488 #define MD1CHPPS_ADDR 0x0E22
489 #define MD1MODPPS_ADDR 0x0E23
490 #define MD2CLPPS_ADDR 0x0E24
491 #define MD2CHPPS_ADDR 0x0E25
492 #define MD2MODPPS_ADDR 0x0E26
493 #define MD3CLPPS_ADDR 0x0E27
494 #define MD3CHPPS_ADDR 0x0E28
495 #define MD3MODPPS_ADDR 0x0E29
496 #define PRG1RPPS_ADDR 0x0E2D
497 #define PRG1FPPS_ADDR 0x0E2E
498 #define PRG2RPPS_ADDR 0x0E2F
499 #define PRG2FPPS_ADDR 0x0E30
500 #define PRG3RPPS_ADDR 0x0E31
501 #define PRG3FPPS_ADDR 0x0E32
502 #define CLCIN0PPS_ADDR 0x0E35
503 #define CLCIN1PPS_ADDR 0x0E36
504 #define CLCIN2PPS_ADDR 0x0E37
505 #define CLCIN3PPS_ADDR 0x0E38
506 #define ADCACTPPS_ADDR 0x0E39
507 #define SSPCLKPPS_ADDR 0x0E3A
508 #define SSPDATPPS_ADDR 0x0E3B
509 #define SSPSSPPS_ADDR 0x0E3C
510 #define RXPPS_ADDR 0x0E3D
511 #define CKPPS_ADDR 0x0E3E
512 #define RA0PPS_ADDR 0x0E90
513 #define RA1PPS_ADDR 0x0E91
514 #define RA2PPS_ADDR 0x0E92
515 #define RA3PPS_ADDR 0x0E93
516 #define RA4PPS_ADDR 0x0E94
517 #define RA5PPS_ADDR 0x0E95
518 #define RA6PPS_ADDR 0x0E96
519 #define RA7PPS_ADDR 0x0E97
520 #define RB0PPS_ADDR 0x0E98
521 #define RB1PPS_ADDR 0x0E99
522 #define RB2PPS_ADDR 0x0E9A
523 #define RB3PPS_ADDR 0x0E9B
524 #define RB4PPS_ADDR 0x0E9C
525 #define RB5PPS_ADDR 0x0E9D
526 #define RB6PPS_ADDR 0x0E9E
527 #define RB7PPS_ADDR 0x0E9F
528 #define RC0PPS_ADDR 0x0EA0
529 #define RC1PPS_ADDR 0x0EA1
530 #define RC2PPS_ADDR 0x0EA2
531 #define RC3PPS_ADDR 0x0EA3
532 #define RC4PPS_ADDR 0x0EA4
533 #define RC5PPS_ADDR 0x0EA5
534 #define RC6PPS_ADDR 0x0EA6
535 #define RC7PPS_ADDR 0x0EA7
536 #define CLCDATA_ADDR 0x0F0F
537 #define CLC1CON_ADDR 0x0F10
538 #define CLC1POL_ADDR 0x0F11
539 #define CLC1SEL0_ADDR 0x0F12
540 #define CLC1SEL1_ADDR 0x0F13
541 #define CLC1SEL2_ADDR 0x0F14
542 #define CLC1SEL3_ADDR 0x0F15
543 #define CLC1GLS0_ADDR 0x0F16
544 #define CLC1GLS1_ADDR 0x0F17
545 #define CLC1GLS2_ADDR 0x0F18
546 #define CLC1GLS3_ADDR 0x0F19
547 #define CLC2CON_ADDR 0x0F1A
548 #define CLC2POL_ADDR 0x0F1B
549 #define CLC2SEL0_ADDR 0x0F1C
550 #define CLC2SEL1_ADDR 0x0F1D
551 #define CLC2SEL2_ADDR 0x0F1E
552 #define CLC2SEL3_ADDR 0x0F1F
553 #define CLC2GLS0_ADDR 0x0F20
554 #define CLC2GLS1_ADDR 0x0F21
555 #define CLC2GLS2_ADDR 0x0F22
556 #define CLC2GLS3_ADDR 0x0F23
557 #define CLC3CON_ADDR 0x0F24
558 #define CLC3POL_ADDR 0x0F25
559 #define CLC3SEL0_ADDR 0x0F26
560 #define CLC3SEL1_ADDR 0x0F27
561 #define CLC3SEL2_ADDR 0x0F28
562 #define CLC3SEL3_ADDR 0x0F29
563 #define CLC3GLS0_ADDR 0x0F2A
564 #define CLC3GLS1_ADDR 0x0F2B
565 #define CLC3GLS2_ADDR 0x0F2C
566 #define CLC3GLS3_ADDR 0x0F2D
567 #define CLC4CON_ADDR 0x0F2E
568 #define CLC4POL_ADDR 0x0F2F
569 #define CLC4SEL0_ADDR 0x0F30
570 #define CLC4SEL1_ADDR 0x0F31
571 #define CLC4SEL2_ADDR 0x0F32
572 #define CLC4SEL3_ADDR 0x0F33
573 #define CLC4GLS0_ADDR 0x0F34
574 #define CLC4GLS1_ADDR 0x0F35
575 #define CLC4GLS2_ADDR 0x0F36
576 #define CLC4GLS3_ADDR 0x0F37
577 #define STATUS_SHAD_ADDR 0x0FE4
578 #define WREG_SHAD_ADDR 0x0FE5
579 #define BSR_SHAD_ADDR 0x0FE6
580 #define PCLATH_SHAD_ADDR 0x0FE7
581 #define FSR0L_SHAD_ADDR 0x0FE8
582 #define FSR0H_SHAD_ADDR 0x0FE9
583 #define FSR1L_SHAD_ADDR 0x0FEA
584 #define FSR1H_SHAD_ADDR 0x0FEB
585 #define STKPTR_ADDR 0x0FED
586 #define TOSL_ADDR 0x0FEE
587 #define TOSH_ADDR 0x0FEF
589 #endif // #ifndef NO_ADDR_DEFINES
591 //==============================================================================
593 // Register Definitions
595 //==============================================================================
597 extern __at(0x0000) __sfr INDF0
;
598 extern __at(0x0001) __sfr INDF1
;
599 extern __at(0x0002) __sfr PCL
;
601 //==============================================================================
604 extern __at(0x0003) __sfr STATUS
;
618 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
626 //==============================================================================
628 extern __at(0x0004) __sfr FSR0
;
629 extern __at(0x0004) __sfr FSR0L
;
630 extern __at(0x0005) __sfr FSR0H
;
631 extern __at(0x0006) __sfr FSR1
;
632 extern __at(0x0006) __sfr FSR1L
;
633 extern __at(0x0007) __sfr FSR1H
;
635 //==============================================================================
638 extern __at(0x0008) __sfr BSR
;
661 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
669 //==============================================================================
671 extern __at(0x0009) __sfr WREG
;
672 extern __at(0x000A) __sfr PCLATH
;
674 //==============================================================================
677 extern __at(0x000B) __sfr INTCON
;
706 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
719 //==============================================================================
722 //==============================================================================
725 extern __at(0x000C) __sfr PORTA
;
739 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
750 //==============================================================================
753 //==============================================================================
756 extern __at(0x000D) __sfr PORTB
;
770 extern __at(0x000D) volatile __PORTBbits_t PORTBbits
;
781 //==============================================================================
784 //==============================================================================
787 extern __at(0x000E) __sfr PORTC
;
801 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
812 //==============================================================================
815 //==============================================================================
818 extern __at(0x0010) __sfr PORTE
;
832 extern __at(0x0010) volatile __PORTEbits_t PORTEbits
;
836 //==============================================================================
839 //==============================================================================
842 extern __at(0x0011) __sfr PIR1
;
855 unsigned TMR1GIF
: 1;
871 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
881 #define _TMR1GIF 0x80
883 //==============================================================================
886 //==============================================================================
889 extern __at(0x0012) __sfr PIR2
;
903 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
914 //==============================================================================
917 //==============================================================================
920 extern __at(0x0013) __sfr PIR3
;
934 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
943 //==============================================================================
946 //==============================================================================
949 extern __at(0x0014) __sfr PIR4
;
956 unsigned TMR3GIF
: 1;
958 unsigned TMR5GIF
: 1;
963 extern __at(0x0014) volatile __PIR4bits_t PIR4bits
;
968 #define _TMR3GIF 0x08
970 #define _TMR5GIF 0x20
973 //==============================================================================
976 //==============================================================================
979 extern __at(0x0015) __sfr PIR5
;
993 extern __at(0x0015) volatile __PIR5bits_t PIR5bits
;
1000 //==============================================================================
1003 //==============================================================================
1006 extern __at(0x0016) __sfr PIR6
;
1010 unsigned PWM5IF
: 1;
1011 unsigned PWM6IF
: 1;
1012 unsigned PWM11IF
: 1;
1020 extern __at(0x0016) volatile __PIR6bits_t PIR6bits
;
1022 #define _PWM5IF 0x01
1023 #define _PWM6IF 0x02
1024 #define _PWM11IF 0x04
1026 //==============================================================================
1028 extern __at(0x0017) __sfr TMR0
;
1029 extern __at(0x0018) __sfr TMR1
;
1030 extern __at(0x0018) __sfr TMR1L
;
1031 extern __at(0x0019) __sfr TMR1H
;
1033 //==============================================================================
1036 extern __at(0x001A) __sfr T1CON
;
1044 unsigned NOT_SYNC
: 1;
1057 unsigned SOSCEN
: 1;
1058 unsigned T1CKPS0
: 1;
1059 unsigned T1CKPS1
: 1;
1066 unsigned TMR1ON
: 1;
1068 unsigned NOT_T1SYNC
: 1;
1069 unsigned T1OSCEN
: 1;
1072 unsigned TMR1CS0
: 1;
1073 unsigned TMR1CS1
: 1;
1091 unsigned T1CKPS
: 2;
1117 unsigned TMR1CS
: 2;
1121 extern __at(0x001A) volatile __T1CONbits_t T1CONbits
;
1123 #define _T1CON_ON 0x01
1124 #define _T1CON_TMRON 0x01
1125 #define _T1CON_TMR1ON 0x01
1126 #define _T1CON_T1ON 0x01
1127 #define _T1CON_NOT_SYNC 0x04
1128 #define _T1CON_SYNC 0x04
1129 #define _T1CON_NOT_T1SYNC 0x04
1130 #define _T1CON_OSCEN 0x08
1131 #define _T1CON_SOSCEN 0x08
1132 #define _T1CON_T1OSCEN 0x08
1133 #define _T1CON_CKPS0 0x10
1134 #define _T1CON_T1CKPS0 0x10
1135 #define _T1CON_CKPS1 0x20
1136 #define _T1CON_T1CKPS1 0x20
1137 #define _T1CON_CS0 0x40
1138 #define _T1CON_T1CS0 0x40
1139 #define _T1CON_TMR1CS0 0x40
1140 #define _T1CON_CS1 0x80
1141 #define _T1CON_T1CS1 0x80
1142 #define _T1CON_TMR1CS1 0x80
1144 //==============================================================================
1147 //==============================================================================
1150 extern __at(0x001B) __sfr T1GCON
;
1159 unsigned GGO_NOT_DONE
: 1;
1168 unsigned T1GSS0
: 1;
1169 unsigned T1GSS1
: 1;
1170 unsigned T1GVAL
: 1;
1171 unsigned T1GGO_NOT_DONE
: 1;
1172 unsigned T1GSPM
: 1;
1174 unsigned T1GPOL
: 1;
1187 unsigned TMR1GE
: 1;
1203 extern __at(0x001B) volatile __T1GCONbits_t T1GCONbits
;
1206 #define _T1GSS0 0x01
1208 #define _T1GSS1 0x02
1210 #define _T1GVAL 0x04
1211 #define _GGO_NOT_DONE 0x08
1212 #define _T1GGO_NOT_DONE 0x08
1214 #define _T1GSPM 0x10
1218 #define _T1GPOL 0x40
1221 #define _TMR1GE 0x80
1223 //==============================================================================
1225 extern __at(0x001C) __sfr TMR3
;
1226 extern __at(0x001C) __sfr TMR3L
;
1227 extern __at(0x001D) __sfr TMR3H
;
1229 //==============================================================================
1232 extern __at(0x001E) __sfr T3CON
;
1240 unsigned NOT_SYNC
: 1;
1253 unsigned SOSCEN
: 1;
1254 unsigned T3CKPS0
: 1;
1255 unsigned T3CKPS1
: 1;
1262 unsigned TMR3ON
: 1;
1264 unsigned NOT_T3SYNC
: 1;
1265 unsigned T3OSCEN
: 1;
1268 unsigned TMR3CS0
: 1;
1269 unsigned TMR3CS1
: 1;
1287 unsigned T3CKPS
: 2;
1313 unsigned TMR3CS
: 2;
1317 extern __at(0x001E) volatile __T3CONbits_t T3CONbits
;
1319 #define _T3CON_ON 0x01
1320 #define _T3CON_TMRON 0x01
1321 #define _T3CON_TMR3ON 0x01
1322 #define _T3CON_T3ON 0x01
1323 #define _T3CON_NOT_SYNC 0x04
1324 #define _T3CON_SYNC 0x04
1325 #define _T3CON_NOT_T3SYNC 0x04
1326 #define _T3CON_OSCEN 0x08
1327 #define _T3CON_SOSCEN 0x08
1328 #define _T3CON_T3OSCEN 0x08
1329 #define _T3CON_CKPS0 0x10
1330 #define _T3CON_T3CKPS0 0x10
1331 #define _T3CON_CKPS1 0x20
1332 #define _T3CON_T3CKPS1 0x20
1333 #define _T3CON_CS0 0x40
1334 #define _T3CON_T3CS0 0x40
1335 #define _T3CON_TMR3CS0 0x40
1336 #define _T3CON_CS1 0x80
1337 #define _T3CON_T3CS1 0x80
1338 #define _T3CON_TMR3CS1 0x80
1340 //==============================================================================
1343 //==============================================================================
1346 extern __at(0x001F) __sfr T3GCON
;
1355 unsigned GGO_NOT_DONE
: 1;
1364 unsigned T3GSS0
: 1;
1365 unsigned T3GSS1
: 1;
1366 unsigned T3GVAL
: 1;
1367 unsigned T3GGO_NOT_DONE
: 1;
1368 unsigned T3GSPM
: 1;
1370 unsigned T3GPOL
: 1;
1383 unsigned TMR3GE
: 1;
1399 extern __at(0x001F) volatile __T3GCONbits_t T3GCONbits
;
1401 #define _T3GCON_GSS0 0x01
1402 #define _T3GCON_T3GSS0 0x01
1403 #define _T3GCON_GSS1 0x02
1404 #define _T3GCON_T3GSS1 0x02
1405 #define _T3GCON_GVAL 0x04
1406 #define _T3GCON_T3GVAL 0x04
1407 #define _T3GCON_GGO_NOT_DONE 0x08
1408 #define _T3GCON_T3GGO_NOT_DONE 0x08
1409 #define _T3GCON_GSPM 0x10
1410 #define _T3GCON_T3GSPM 0x10
1411 #define _T3GCON_GTM 0x20
1412 #define _T3GCON_T3GTM 0x20
1413 #define _T3GCON_GPOL 0x40
1414 #define _T3GCON_T3GPOL 0x40
1415 #define _T3GCON_GE 0x80
1416 #define _T3GCON_T3GE 0x80
1417 #define _T3GCON_TMR3GE 0x80
1419 //==============================================================================
1422 //==============================================================================
1425 extern __at(0x008C) __sfr TRISA
;
1429 unsigned TRISA0
: 1;
1430 unsigned TRISA1
: 1;
1431 unsigned TRISA2
: 1;
1432 unsigned TRISA3
: 1;
1433 unsigned TRISA4
: 1;
1434 unsigned TRISA5
: 1;
1435 unsigned TRISA6
: 1;
1436 unsigned TRISA7
: 1;
1439 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
1441 #define _TRISA0 0x01
1442 #define _TRISA1 0x02
1443 #define _TRISA2 0x04
1444 #define _TRISA3 0x08
1445 #define _TRISA4 0x10
1446 #define _TRISA5 0x20
1447 #define _TRISA6 0x40
1448 #define _TRISA7 0x80
1450 //==============================================================================
1453 //==============================================================================
1456 extern __at(0x008D) __sfr TRISB
;
1460 unsigned TRISB0
: 1;
1461 unsigned TRISB1
: 1;
1462 unsigned TRISB2
: 1;
1463 unsigned TRISB3
: 1;
1464 unsigned TRISB4
: 1;
1465 unsigned TRISB5
: 1;
1466 unsigned TRISB6
: 1;
1467 unsigned TRISB7
: 1;
1470 extern __at(0x008D) volatile __TRISBbits_t TRISBbits
;
1472 #define _TRISB0 0x01
1473 #define _TRISB1 0x02
1474 #define _TRISB2 0x04
1475 #define _TRISB3 0x08
1476 #define _TRISB4 0x10
1477 #define _TRISB5 0x20
1478 #define _TRISB6 0x40
1479 #define _TRISB7 0x80
1481 //==============================================================================
1484 //==============================================================================
1487 extern __at(0x008E) __sfr TRISC
;
1491 unsigned TRISC0
: 1;
1492 unsigned TRISC1
: 1;
1493 unsigned TRISC2
: 1;
1494 unsigned TRISC3
: 1;
1495 unsigned TRISC4
: 1;
1496 unsigned TRISC5
: 1;
1497 unsigned TRISC6
: 1;
1498 unsigned TRISC7
: 1;
1501 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
1503 #define _TRISC0 0x01
1504 #define _TRISC1 0x02
1505 #define _TRISC2 0x04
1506 #define _TRISC3 0x08
1507 #define _TRISC4 0x10
1508 #define _TRISC5 0x20
1509 #define _TRISC6 0x40
1510 #define _TRISC7 0x80
1512 //==============================================================================
1515 //==============================================================================
1518 extern __at(0x0090) __sfr TRISE
;
1525 unsigned TRISE3
: 1;
1532 extern __at(0x0090) volatile __TRISEbits_t TRISEbits
;
1534 #define _TRISE3 0x08
1536 //==============================================================================
1539 //==============================================================================
1542 extern __at(0x0091) __sfr PIE1
;
1548 unsigned TMR1IE
: 1;
1549 unsigned TMR2IE
: 1;
1550 unsigned CCP1IE
: 1;
1551 unsigned SSP1IE
: 1;
1555 unsigned TMR1GIE
: 1;
1571 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
1573 #define _TMR1IE 0x01
1574 #define _TMR2IE 0x02
1575 #define _CCP1IE 0x04
1577 #define _SSP1IE 0x08
1581 #define _TMR1GIE 0x80
1583 //==============================================================================
1586 //==============================================================================
1589 extern __at(0x0092) __sfr PIE2
;
1593 unsigned CCP2IE
: 1;
1596 unsigned BCL1IE
: 1;
1603 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
1605 #define _CCP2IE 0x01
1608 #define _BCL1IE 0x08
1614 //==============================================================================
1617 //==============================================================================
1620 extern __at(0x0093) __sfr PIE3
;
1624 unsigned CLC1IE
: 1;
1625 unsigned CLC2IE
: 1;
1626 unsigned CLC3IE
: 1;
1627 unsigned CLC4IE
: 1;
1629 unsigned COG2IE
: 1;
1634 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
1636 #define _CLC1IE 0x01
1637 #define _CLC2IE 0x02
1638 #define _CLC3IE 0x04
1639 #define _CLC4IE 0x08
1641 #define _COG2IE 0x20
1643 //==============================================================================
1646 //==============================================================================
1649 extern __at(0x0094) __sfr PIE4
;
1653 unsigned TMR4IE
: 1;
1654 unsigned TMR6IE
: 1;
1655 unsigned TMR3IE
: 1;
1656 unsigned TMR3GIE
: 1;
1657 unsigned TMR5IE
: 1;
1658 unsigned TMR5GIE
: 1;
1659 unsigned TMR8IE
: 1;
1663 extern __at(0x0094) volatile __PIE4bits_t PIE4bits
;
1665 #define _TMR4IE 0x01
1666 #define _TMR6IE 0x02
1667 #define _TMR3IE 0x04
1668 #define _TMR3GIE 0x08
1669 #define _TMR5IE 0x10
1670 #define _TMR5GIE 0x20
1671 #define _TMR8IE 0x40
1673 //==============================================================================
1676 //==============================================================================
1679 extern __at(0x0095) __sfr PIE5
;
1687 unsigned COG3IE
: 1;
1689 unsigned CCP7IE
: 1;
1693 extern __at(0x0095) volatile __PIE5bits_t PIE5bits
;
1697 #define _COG3IE 0x10
1698 #define _CCP7IE 0x40
1700 //==============================================================================
1703 //==============================================================================
1706 extern __at(0x0096) __sfr PIE6
;
1710 unsigned PWM5IE
: 1;
1711 unsigned PWM6IE
: 1;
1712 unsigned PWM11IE
: 1;
1720 extern __at(0x0096) volatile __PIE6bits_t PIE6bits
;
1722 #define _PWM5IE 0x01
1723 #define _PWM6IE 0x02
1724 #define _PWM11IE 0x04
1726 //==============================================================================
1729 //==============================================================================
1732 extern __at(0x0097) __sfr OPTION_REG
;
1742 unsigned TMR0SE
: 1;
1743 unsigned TMR0CS
: 1;
1744 unsigned INTEDG
: 1;
1745 unsigned NOT_WPUEN
: 1;
1765 } __OPTION_REGbits_t
;
1767 extern __at(0x0097) volatile __OPTION_REGbits_t OPTION_REGbits
;
1773 #define _TMR0SE 0x10
1775 #define _TMR0CS 0x20
1777 #define _INTEDG 0x40
1778 #define _NOT_WPUEN 0x80
1780 //==============================================================================
1783 //==============================================================================
1786 extern __at(0x0098) __sfr PCON
;
1790 unsigned NOT_BOR
: 1;
1791 unsigned NOT_POR
: 1;
1792 unsigned NOT_RI
: 1;
1793 unsigned NOT_RMCLR
: 1;
1794 unsigned NOT_RWDT
: 1;
1796 unsigned STKUNF
: 1;
1797 unsigned STKOVF
: 1;
1800 extern __at(0x0098) volatile __PCONbits_t PCONbits
;
1802 #define _NOT_BOR 0x01
1803 #define _NOT_POR 0x02
1804 #define _NOT_RI 0x04
1805 #define _NOT_RMCLR 0x08
1806 #define _NOT_RWDT 0x10
1807 #define _STKUNF 0x40
1808 #define _STKOVF 0x80
1810 //==============================================================================
1813 //==============================================================================
1816 extern __at(0x0099) __sfr WDTCON
;
1822 unsigned SWDTEN
: 1;
1823 unsigned WDTPS0
: 1;
1824 unsigned WDTPS1
: 1;
1825 unsigned WDTPS2
: 1;
1826 unsigned WDTPS3
: 1;
1827 unsigned WDTPS4
: 1;
1840 extern __at(0x0099) volatile __WDTCONbits_t WDTCONbits
;
1842 #define _SWDTEN 0x01
1843 #define _WDTPS0 0x02
1844 #define _WDTPS1 0x04
1845 #define _WDTPS2 0x08
1846 #define _WDTPS3 0x10
1847 #define _WDTPS4 0x20
1849 //==============================================================================
1852 //==============================================================================
1855 extern __at(0x009A) __sfr OSCTUNE
;
1878 extern __at(0x009A) volatile __OSCTUNEbits_t OSCTUNEbits
;
1887 //==============================================================================
1890 //==============================================================================
1893 extern __at(0x009B) __sfr OSCCON
;
1906 unsigned SPLLEN
: 1;
1923 extern __at(0x009B) volatile __OSCCONbits_t OSCCONbits
;
1931 #define _SPLLEN 0x80
1933 //==============================================================================
1936 //==============================================================================
1939 extern __at(0x009C) __sfr OSCSTAT
;
1943 unsigned HFIOFS
: 1;
1944 unsigned LFIOFR
: 1;
1945 unsigned MFIOFR
: 1;
1946 unsigned HFIOFL
: 1;
1947 unsigned HFIOFR
: 1;
1953 extern __at(0x009C) volatile __OSCSTATbits_t OSCSTATbits
;
1955 #define _HFIOFS 0x01
1956 #define _LFIOFR 0x02
1957 #define _MFIOFR 0x04
1958 #define _HFIOFL 0x08
1959 #define _HFIOFR 0x10
1964 //==============================================================================
1967 //==============================================================================
1970 extern __at(0x009D) __sfr BORCON
;
1974 unsigned BORRDY
: 1;
1981 unsigned SBOREN
: 1;
1984 extern __at(0x009D) volatile __BORCONbits_t BORCONbits
;
1986 #define _BORRDY 0x01
1988 #define _SBOREN 0x80
1990 //==============================================================================
1993 //==============================================================================
1996 extern __at(0x009E) __sfr FVRCON
;
2006 unsigned FVRRDY
: 1;
2010 extern __at(0x009E) volatile __FVRCONbits_t FVRCONbits
;
2014 #define _FVRRDY 0x40
2017 //==============================================================================
2020 //==============================================================================
2023 extern __at(0x009F) __sfr ZCD1CON
;
2027 unsigned ZCD1INTN
: 1;
2028 unsigned ZCD1INTP
: 1;
2031 unsigned ZCD1POL
: 1;
2032 unsigned ZCD1OUT
: 1;
2034 unsigned ZCD1EN
: 1;
2037 extern __at(0x009F) volatile __ZCD1CONbits_t ZCD1CONbits
;
2039 #define _ZCD1INTN 0x01
2040 #define _ZCD1INTP 0x02
2041 #define _ZCD1POL 0x10
2042 #define _ZCD1OUT 0x20
2043 #define _ZCD1EN 0x80
2045 //==============================================================================
2048 //==============================================================================
2051 extern __at(0x010C) __sfr LATA
;
2065 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
2076 //==============================================================================
2079 //==============================================================================
2082 extern __at(0x010D) __sfr LATB
;
2096 extern __at(0x010D) volatile __LATBbits_t LATBbits
;
2107 //==============================================================================
2110 //==============================================================================
2113 extern __at(0x010E) __sfr LATC
;
2127 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
2138 //==============================================================================
2141 //==============================================================================
2144 extern __at(0x0111) __sfr CMOUT
;
2148 unsigned MC1OUT
: 1;
2149 unsigned MC2OUT
: 1;
2150 unsigned MC3OUT
: 1;
2151 unsigned MC4OUT
: 1;
2152 unsigned MC5OUT
: 1;
2153 unsigned MC6OUT
: 1;
2158 extern __at(0x0111) volatile __CMOUTbits_t CMOUTbits
;
2160 #define _MC1OUT 0x01
2161 #define _MC2OUT 0x02
2162 #define _MC3OUT 0x04
2163 #define _MC4OUT 0x08
2164 #define _MC5OUT 0x10
2165 #define _MC6OUT 0x20
2167 //==============================================================================
2170 //==============================================================================
2173 extern __at(0x0112) __sfr CM1CON0
;
2181 unsigned Reserved
: 1;
2191 unsigned C1SYNC
: 1;
2202 extern __at(0x0112) volatile __CM1CON0bits_t CM1CON0bits
;
2204 #define _CM1CON0_SYNC 0x01
2205 #define _CM1CON0_C1SYNC 0x01
2206 #define _CM1CON0_HYS 0x02
2207 #define _CM1CON0_C1HYS 0x02
2208 #define _CM1CON0_Reserved 0x04
2209 #define _CM1CON0_C1SP 0x04
2210 #define _CM1CON0_ZLF 0x08
2211 #define _CM1CON0_C1ZLF 0x08
2212 #define _CM1CON0_POL 0x10
2213 #define _CM1CON0_C1POL 0x10
2214 #define _CM1CON0_OUT 0x40
2215 #define _CM1CON0_C1OUT 0x40
2216 #define _CM1CON0_ON 0x80
2217 #define _CM1CON0_C1ON 0x80
2219 //==============================================================================
2222 //==============================================================================
2225 extern __at(0x0113) __sfr CM1CON1
;
2243 unsigned C1INTN
: 1;
2244 unsigned C1INTP
: 1;
2254 extern __at(0x0113) volatile __CM1CON1bits_t CM1CON1bits
;
2256 #define _CM1CON1_INTN 0x01
2257 #define _CM1CON1_C1INTN 0x01
2258 #define _CM1CON1_INTP 0x02
2259 #define _CM1CON1_C1INTP 0x02
2261 //==============================================================================
2264 //==============================================================================
2267 extern __at(0x0114) __sfr CM1NSEL
;
2273 unsigned C1NCH0
: 1;
2274 unsigned C1NCH1
: 1;
2275 unsigned C1NCH2
: 1;
2276 unsigned C1NCH3
: 1;
2290 extern __at(0x0114) volatile __CM1NSELbits_t CM1NSELbits
;
2292 #define _C1NCH0 0x01
2293 #define _C1NCH1 0x02
2294 #define _C1NCH2 0x04
2295 #define _C1NCH3 0x08
2297 //==============================================================================
2300 //==============================================================================
2303 extern __at(0x0115) __sfr CM1PSEL
;
2321 unsigned C1PCH0
: 1;
2322 unsigned C1PCH1
: 1;
2323 unsigned C1PCH2
: 1;
2324 unsigned C1PCH3
: 1;
2344 extern __at(0x0115) volatile __CM1PSELbits_t CM1PSELbits
;
2347 #define _C1PCH0 0x01
2349 #define _C1PCH1 0x02
2351 #define _C1PCH2 0x04
2353 #define _C1PCH3 0x08
2355 //==============================================================================
2358 //==============================================================================
2361 extern __at(0x0116) __sfr CM2CON0
;
2369 unsigned Reserved
: 1;
2379 unsigned C2SYNC
: 1;
2390 extern __at(0x0116) volatile __CM2CON0bits_t CM2CON0bits
;
2392 #define _CM2CON0_SYNC 0x01
2393 #define _CM2CON0_C2SYNC 0x01
2394 #define _CM2CON0_HYS 0x02
2395 #define _CM2CON0_C2HYS 0x02
2396 #define _CM2CON0_Reserved 0x04
2397 #define _CM2CON0_C2SP 0x04
2398 #define _CM2CON0_ZLF 0x08
2399 #define _CM2CON0_C2ZLF 0x08
2400 #define _CM2CON0_POL 0x10
2401 #define _CM2CON0_C2POL 0x10
2402 #define _CM2CON0_OUT 0x40
2403 #define _CM2CON0_C2OUT 0x40
2404 #define _CM2CON0_ON 0x80
2405 #define _CM2CON0_C2ON 0x80
2407 //==============================================================================
2410 //==============================================================================
2413 extern __at(0x0117) __sfr CM2CON1
;
2431 unsigned C2INTN
: 1;
2432 unsigned C2INTP
: 1;
2442 extern __at(0x0117) volatile __CM2CON1bits_t CM2CON1bits
;
2444 #define _CM2CON1_INTN 0x01
2445 #define _CM2CON1_C2INTN 0x01
2446 #define _CM2CON1_INTP 0x02
2447 #define _CM2CON1_C2INTP 0x02
2449 //==============================================================================
2452 //==============================================================================
2455 extern __at(0x0118) __sfr CM2NSEL
;
2461 unsigned C2NCH0
: 1;
2462 unsigned C2NCH1
: 1;
2463 unsigned C2NCH2
: 1;
2464 unsigned C2NCH3
: 1;
2478 extern __at(0x0118) volatile __CM2NSELbits_t CM2NSELbits
;
2480 #define _C2NCH0 0x01
2481 #define _C2NCH1 0x02
2482 #define _C2NCH2 0x04
2483 #define _C2NCH3 0x08
2485 //==============================================================================
2488 //==============================================================================
2491 extern __at(0x0119) __sfr CM2PSEL
;
2509 unsigned C2PCH0
: 1;
2510 unsigned C2PCH1
: 1;
2511 unsigned C2PCH2
: 1;
2512 unsigned C2PCH3
: 1;
2532 extern __at(0x0119) volatile __CM2PSELbits_t CM2PSELbits
;
2534 #define _CM2PSEL_PCH0 0x01
2535 #define _CM2PSEL_C2PCH0 0x01
2536 #define _CM2PSEL_PCH1 0x02
2537 #define _CM2PSEL_C2PCH1 0x02
2538 #define _CM2PSEL_PCH2 0x04
2539 #define _CM2PSEL_C2PCH2 0x04
2540 #define _CM2PSEL_PCH3 0x08
2541 #define _CM2PSEL_C2PCH3 0x08
2543 //==============================================================================
2546 //==============================================================================
2549 extern __at(0x011A) __sfr CM3CON0
;
2557 unsigned Reserved
: 1;
2567 unsigned C3SYNC
: 1;
2578 extern __at(0x011A) volatile __CM3CON0bits_t CM3CON0bits
;
2580 #define _CM3CON0_SYNC 0x01
2581 #define _CM3CON0_C3SYNC 0x01
2582 #define _CM3CON0_HYS 0x02
2583 #define _CM3CON0_C3HYS 0x02
2584 #define _CM3CON0_Reserved 0x04
2585 #define _CM3CON0_C3SP 0x04
2586 #define _CM3CON0_ZLF 0x08
2587 #define _CM3CON0_C3ZLF 0x08
2588 #define _CM3CON0_POL 0x10
2589 #define _CM3CON0_C3POL 0x10
2590 #define _CM3CON0_OUT 0x40
2591 #define _CM3CON0_C3OUT 0x40
2592 #define _CM3CON0_ON 0x80
2593 #define _CM3CON0_C3ON 0x80
2595 //==============================================================================
2598 //==============================================================================
2601 extern __at(0x011B) __sfr CM3CON1
;
2619 unsigned C3INTN
: 1;
2620 unsigned C3INTP
: 1;
2630 extern __at(0x011B) volatile __CM3CON1bits_t CM3CON1bits
;
2632 #define _CM3CON1_INTN 0x01
2633 #define _CM3CON1_C3INTN 0x01
2634 #define _CM3CON1_INTP 0x02
2635 #define _CM3CON1_C3INTP 0x02
2637 //==============================================================================
2640 //==============================================================================
2643 extern __at(0x011C) __sfr CM3NSEL
;
2649 unsigned C3NCH0
: 1;
2650 unsigned C3NCH1
: 1;
2651 unsigned C3NCH2
: 1;
2652 unsigned C3NCH3
: 1;
2666 extern __at(0x011C) volatile __CM3NSELbits_t CM3NSELbits
;
2668 #define _C3NCH0 0x01
2669 #define _C3NCH1 0x02
2670 #define _C3NCH2 0x04
2671 #define _C3NCH3 0x08
2673 //==============================================================================
2676 //==============================================================================
2679 extern __at(0x011D) __sfr CM3PSEL
;
2697 unsigned C3PCH0
: 1;
2698 unsigned C3PCH1
: 1;
2699 unsigned C3PCH2
: 1;
2700 unsigned C3PCH3
: 1;
2720 extern __at(0x011D) volatile __CM3PSELbits_t CM3PSELbits
;
2722 #define _CM3PSEL_PCH0 0x01
2723 #define _CM3PSEL_C3PCH0 0x01
2724 #define _CM3PSEL_PCH1 0x02
2725 #define _CM3PSEL_C3PCH1 0x02
2726 #define _CM3PSEL_PCH2 0x04
2727 #define _CM3PSEL_C3PCH2 0x04
2728 #define _CM3PSEL_PCH3 0x08
2729 #define _CM3PSEL_C3PCH3 0x08
2731 //==============================================================================
2734 //==============================================================================
2737 extern __at(0x018C) __sfr ANSELA
;
2760 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
2769 //==============================================================================
2772 //==============================================================================
2775 extern __at(0x018D) __sfr ANSELB
;
2798 extern __at(0x018D) volatile __ANSELBbits_t ANSELBbits
;
2807 //==============================================================================
2810 //==============================================================================
2813 extern __at(0x018E) __sfr ANSELC
;
2827 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
2836 //==============================================================================
2838 extern __at(0x0191) __sfr PMADR
;
2839 extern __at(0x0191) __sfr PMADRL
;
2840 extern __at(0x0192) __sfr PMADRH
;
2841 extern __at(0x0193) __sfr PMDAT
;
2842 extern __at(0x0193) __sfr PMDATL
;
2843 extern __at(0x0194) __sfr PMDATH
;
2845 //==============================================================================
2848 extern __at(0x0195) __sfr PMCON1
;
2862 extern __at(0x0195) volatile __PMCON1bits_t PMCON1bits
;
2872 //==============================================================================
2874 extern __at(0x0196) __sfr PMCON2
;
2876 //==============================================================================
2879 extern __at(0x0197) __sfr VREGCON
;
2885 unsigned VREGPM0
: 1;
2886 unsigned VREGPM1
: 1;
2897 unsigned VREGPM
: 2;
2902 extern __at(0x0197) volatile __VREGCONbits_t VREGCONbits
;
2904 #define _VREGPM0 0x01
2905 #define _VREGPM1 0x02
2907 //==============================================================================
2909 extern __at(0x0199) __sfr RC1REG
;
2910 extern __at(0x0199) __sfr RCREG
;
2911 extern __at(0x0199) __sfr RCREG1
;
2912 extern __at(0x019A) __sfr TX1REG
;
2913 extern __at(0x019A) __sfr TXREG
;
2914 extern __at(0x019A) __sfr TXREG1
;
2915 extern __at(0x019B) __sfr SP1BRG
;
2916 extern __at(0x019B) __sfr SP1BRGL
;
2917 extern __at(0x019B) __sfr SPBRG
;
2918 extern __at(0x019B) __sfr SPBRG1
;
2919 extern __at(0x019B) __sfr SPBRGL
;
2920 extern __at(0x019C) __sfr SP1BRGH
;
2921 extern __at(0x019C) __sfr SPBRGH
;
2922 extern __at(0x019C) __sfr SPBRGH1
;
2924 //==============================================================================
2927 extern __at(0x019D) __sfr RC1STA
;
2941 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
2952 //==============================================================================
2955 //==============================================================================
2958 extern __at(0x019D) __sfr RCSTA
;
2972 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
2974 #define _RCSTA_RX9D 0x01
2975 #define _RCSTA_OERR 0x02
2976 #define _RCSTA_FERR 0x04
2977 #define _RCSTA_ADDEN 0x08
2978 #define _RCSTA_CREN 0x10
2979 #define _RCSTA_SREN 0x20
2980 #define _RCSTA_RX9 0x40
2981 #define _RCSTA_SPEN 0x80
2983 //==============================================================================
2986 //==============================================================================
2989 extern __at(0x019D) __sfr RCSTA1
;
3003 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
3005 #define _RCSTA1_RX9D 0x01
3006 #define _RCSTA1_OERR 0x02
3007 #define _RCSTA1_FERR 0x04
3008 #define _RCSTA1_ADDEN 0x08
3009 #define _RCSTA1_CREN 0x10
3010 #define _RCSTA1_SREN 0x20
3011 #define _RCSTA1_RX9 0x40
3012 #define _RCSTA1_SPEN 0x80
3014 //==============================================================================
3017 //==============================================================================
3020 extern __at(0x019E) __sfr TX1STA
;
3034 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
3036 #define _TX1STA_TX9D 0x01
3037 #define _TX1STA_TRMT 0x02
3038 #define _TX1STA_BRGH 0x04
3039 #define _TX1STA_SENDB 0x08
3040 #define _TX1STA_SYNC 0x10
3041 #define _TX1STA_TXEN 0x20
3042 #define _TX1STA_TX9 0x40
3043 #define _TX1STA_CSRC 0x80
3045 //==============================================================================
3048 //==============================================================================
3051 extern __at(0x019E) __sfr TXSTA
;
3065 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
3067 #define _TXSTA_TX9D 0x01
3068 #define _TXSTA_TRMT 0x02
3069 #define _TXSTA_BRGH 0x04
3070 #define _TXSTA_SENDB 0x08
3071 #define _TXSTA_SYNC 0x10
3072 #define _TXSTA_TXEN 0x20
3073 #define _TXSTA_TX9 0x40
3074 #define _TXSTA_CSRC 0x80
3076 //==============================================================================
3079 //==============================================================================
3082 extern __at(0x019E) __sfr TXSTA1
;
3096 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
3098 #define _TXSTA1_TX9D 0x01
3099 #define _TXSTA1_TRMT 0x02
3100 #define _TXSTA1_BRGH 0x04
3101 #define _TXSTA1_SENDB 0x08
3102 #define _TXSTA1_SYNC 0x10
3103 #define _TXSTA1_TXEN 0x20
3104 #define _TXSTA1_TX9 0x40
3105 #define _TXSTA1_CSRC 0x80
3107 //==============================================================================
3110 //==============================================================================
3113 extern __at(0x019F) __sfr BAUD1CON
;
3124 unsigned ABDOVF
: 1;
3127 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
3134 #define _ABDOVF 0x80
3136 //==============================================================================
3139 //==============================================================================
3142 extern __at(0x019F) __sfr BAUDCON
;
3153 unsigned ABDOVF
: 1;
3156 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
3158 #define _BAUDCON_ABDEN 0x01
3159 #define _BAUDCON_WUE 0x02
3160 #define _BAUDCON_BRG16 0x08
3161 #define _BAUDCON_SCKP 0x10
3162 #define _BAUDCON_RCIDL 0x40
3163 #define _BAUDCON_ABDOVF 0x80
3165 //==============================================================================
3168 //==============================================================================
3171 extern __at(0x019F) __sfr BAUDCON1
;
3182 unsigned ABDOVF
: 1;
3185 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
3187 #define _BAUDCON1_ABDEN 0x01
3188 #define _BAUDCON1_WUE 0x02
3189 #define _BAUDCON1_BRG16 0x08
3190 #define _BAUDCON1_SCKP 0x10
3191 #define _BAUDCON1_RCIDL 0x40
3192 #define _BAUDCON1_ABDOVF 0x80
3194 //==============================================================================
3197 //==============================================================================
3200 extern __at(0x019F) __sfr BAUDCTL
;
3211 unsigned ABDOVF
: 1;
3214 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
3216 #define _BAUDCTL_ABDEN 0x01
3217 #define _BAUDCTL_WUE 0x02
3218 #define _BAUDCTL_BRG16 0x08
3219 #define _BAUDCTL_SCKP 0x10
3220 #define _BAUDCTL_RCIDL 0x40
3221 #define _BAUDCTL_ABDOVF 0x80
3223 //==============================================================================
3226 //==============================================================================
3229 extern __at(0x019F) __sfr BAUDCTL1
;
3240 unsigned ABDOVF
: 1;
3243 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
3245 #define _BAUDCTL1_ABDEN 0x01
3246 #define _BAUDCTL1_WUE 0x02
3247 #define _BAUDCTL1_BRG16 0x08
3248 #define _BAUDCTL1_SCKP 0x10
3249 #define _BAUDCTL1_RCIDL 0x40
3250 #define _BAUDCTL1_ABDOVF 0x80
3252 //==============================================================================
3255 //==============================================================================
3258 extern __at(0x020C) __sfr WPUA
;
3272 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
3283 //==============================================================================
3286 //==============================================================================
3289 extern __at(0x020D) __sfr WPUB
;
3303 extern __at(0x020D) volatile __WPUBbits_t WPUBbits
;
3314 //==============================================================================
3317 //==============================================================================
3320 extern __at(0x020E) __sfr WPUC
;
3334 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
3345 //==============================================================================
3348 //==============================================================================
3351 extern __at(0x0210) __sfr WPUE
;
3365 extern __at(0x0210) volatile __WPUEbits_t WPUEbits
;
3369 //==============================================================================
3372 //==============================================================================
3375 extern __at(0x0211) __sfr SSP1BUF
;
3381 unsigned SSP1BUF0
: 1;
3382 unsigned SSP1BUF1
: 1;
3383 unsigned SSP1BUF2
: 1;
3384 unsigned SSP1BUF3
: 1;
3385 unsigned SSP1BUF4
: 1;
3386 unsigned SSP1BUF5
: 1;
3387 unsigned SSP1BUF6
: 1;
3388 unsigned SSP1BUF7
: 1;
3404 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
3406 #define _SSP1BUF0 0x01
3408 #define _SSP1BUF1 0x02
3410 #define _SSP1BUF2 0x04
3412 #define _SSP1BUF3 0x08
3414 #define _SSP1BUF4 0x10
3416 #define _SSP1BUF5 0x20
3418 #define _SSP1BUF6 0x40
3420 #define _SSP1BUF7 0x80
3423 //==============================================================================
3426 //==============================================================================
3429 extern __at(0x0211) __sfr SSPBUF
;
3435 unsigned SSP1BUF0
: 1;
3436 unsigned SSP1BUF1
: 1;
3437 unsigned SSP1BUF2
: 1;
3438 unsigned SSP1BUF3
: 1;
3439 unsigned SSP1BUF4
: 1;
3440 unsigned SSP1BUF5
: 1;
3441 unsigned SSP1BUF6
: 1;
3442 unsigned SSP1BUF7
: 1;
3458 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
3460 #define _SSPBUF_SSP1BUF0 0x01
3461 #define _SSPBUF_BUF0 0x01
3462 #define _SSPBUF_SSP1BUF1 0x02
3463 #define _SSPBUF_BUF1 0x02
3464 #define _SSPBUF_SSP1BUF2 0x04
3465 #define _SSPBUF_BUF2 0x04
3466 #define _SSPBUF_SSP1BUF3 0x08
3467 #define _SSPBUF_BUF3 0x08
3468 #define _SSPBUF_SSP1BUF4 0x10
3469 #define _SSPBUF_BUF4 0x10
3470 #define _SSPBUF_SSP1BUF5 0x20
3471 #define _SSPBUF_BUF5 0x20
3472 #define _SSPBUF_SSP1BUF6 0x40
3473 #define _SSPBUF_BUF6 0x40
3474 #define _SSPBUF_SSP1BUF7 0x80
3475 #define _SSPBUF_BUF7 0x80
3477 //==============================================================================
3480 //==============================================================================
3483 extern __at(0x0212) __sfr SSP1ADD
;
3489 unsigned SSP1ADD0
: 1;
3490 unsigned SSP1ADD1
: 1;
3491 unsigned SSP1ADD2
: 1;
3492 unsigned SSP1ADD3
: 1;
3493 unsigned SSP1ADD4
: 1;
3494 unsigned SSP1ADD5
: 1;
3495 unsigned SSP1ADD6
: 1;
3496 unsigned SSP1ADD7
: 1;
3512 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
3514 #define _SSP1ADD0 0x01
3516 #define _SSP1ADD1 0x02
3518 #define _SSP1ADD2 0x04
3520 #define _SSP1ADD3 0x08
3522 #define _SSP1ADD4 0x10
3524 #define _SSP1ADD5 0x20
3526 #define _SSP1ADD6 0x40
3528 #define _SSP1ADD7 0x80
3531 //==============================================================================
3534 //==============================================================================
3537 extern __at(0x0212) __sfr SSPADD
;
3543 unsigned SSP1ADD0
: 1;
3544 unsigned SSP1ADD1
: 1;
3545 unsigned SSP1ADD2
: 1;
3546 unsigned SSP1ADD3
: 1;
3547 unsigned SSP1ADD4
: 1;
3548 unsigned SSP1ADD5
: 1;
3549 unsigned SSP1ADD6
: 1;
3550 unsigned SSP1ADD7
: 1;
3566 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
3568 #define _SSPADD_SSP1ADD0 0x01
3569 #define _SSPADD_ADD0 0x01
3570 #define _SSPADD_SSP1ADD1 0x02
3571 #define _SSPADD_ADD1 0x02
3572 #define _SSPADD_SSP1ADD2 0x04
3573 #define _SSPADD_ADD2 0x04
3574 #define _SSPADD_SSP1ADD3 0x08
3575 #define _SSPADD_ADD3 0x08
3576 #define _SSPADD_SSP1ADD4 0x10
3577 #define _SSPADD_ADD4 0x10
3578 #define _SSPADD_SSP1ADD5 0x20
3579 #define _SSPADD_ADD5 0x20
3580 #define _SSPADD_SSP1ADD6 0x40
3581 #define _SSPADD_ADD6 0x40
3582 #define _SSPADD_SSP1ADD7 0x80
3583 #define _SSPADD_ADD7 0x80
3585 //==============================================================================
3588 //==============================================================================
3591 extern __at(0x0213) __sfr SSP1MSK
;
3597 unsigned SSP1MSK0
: 1;
3598 unsigned SSP1MSK1
: 1;
3599 unsigned SSP1MSK2
: 1;
3600 unsigned SSP1MSK3
: 1;
3601 unsigned SSP1MSK4
: 1;
3602 unsigned SSP1MSK5
: 1;
3603 unsigned SSP1MSK6
: 1;
3604 unsigned SSP1MSK7
: 1;
3620 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
3622 #define _SSP1MSK0 0x01
3624 #define _SSP1MSK1 0x02
3626 #define _SSP1MSK2 0x04
3628 #define _SSP1MSK3 0x08
3630 #define _SSP1MSK4 0x10
3632 #define _SSP1MSK5 0x20
3634 #define _SSP1MSK6 0x40
3636 #define _SSP1MSK7 0x80
3639 //==============================================================================
3642 //==============================================================================
3645 extern __at(0x0213) __sfr SSPMSK
;
3651 unsigned SSP1MSK0
: 1;
3652 unsigned SSP1MSK1
: 1;
3653 unsigned SSP1MSK2
: 1;
3654 unsigned SSP1MSK3
: 1;
3655 unsigned SSP1MSK4
: 1;
3656 unsigned SSP1MSK5
: 1;
3657 unsigned SSP1MSK6
: 1;
3658 unsigned SSP1MSK7
: 1;
3674 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
3676 #define _SSPMSK_SSP1MSK0 0x01
3677 #define _SSPMSK_MSK0 0x01
3678 #define _SSPMSK_SSP1MSK1 0x02
3679 #define _SSPMSK_MSK1 0x02
3680 #define _SSPMSK_SSP1MSK2 0x04
3681 #define _SSPMSK_MSK2 0x04
3682 #define _SSPMSK_SSP1MSK3 0x08
3683 #define _SSPMSK_MSK3 0x08
3684 #define _SSPMSK_SSP1MSK4 0x10
3685 #define _SSPMSK_MSK4 0x10
3686 #define _SSPMSK_SSP1MSK5 0x20
3687 #define _SSPMSK_MSK5 0x20
3688 #define _SSPMSK_SSP1MSK6 0x40
3689 #define _SSPMSK_MSK6 0x40
3690 #define _SSPMSK_SSP1MSK7 0x80
3691 #define _SSPMSK_MSK7 0x80
3693 //==============================================================================
3696 //==============================================================================
3699 extern __at(0x0214) __sfr SSP1STAT
;
3705 unsigned R_NOT_W
: 1;
3708 unsigned D_NOT_A
: 1;
3713 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
3717 #define _R_NOT_W 0x04
3720 #define _D_NOT_A 0x20
3724 //==============================================================================
3727 //==============================================================================
3730 extern __at(0x0214) __sfr SSPSTAT
;
3736 unsigned R_NOT_W
: 1;
3739 unsigned D_NOT_A
: 1;
3744 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
3746 #define _SSPSTAT_BF 0x01
3747 #define _SSPSTAT_UA 0x02
3748 #define _SSPSTAT_R_NOT_W 0x04
3749 #define _SSPSTAT_S 0x08
3750 #define _SSPSTAT_P 0x10
3751 #define _SSPSTAT_D_NOT_A 0x20
3752 #define _SSPSTAT_CKE 0x40
3753 #define _SSPSTAT_SMP 0x80
3755 //==============================================================================
3758 //==============================================================================
3761 extern __at(0x0215) __sfr SSP1CON
;
3784 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
3795 //==============================================================================
3798 //==============================================================================
3801 extern __at(0x0215) __sfr SSP1CON1
;
3824 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
3826 #define _SSP1CON1_SSPM0 0x01
3827 #define _SSP1CON1_SSPM1 0x02
3828 #define _SSP1CON1_SSPM2 0x04
3829 #define _SSP1CON1_SSPM3 0x08
3830 #define _SSP1CON1_CKP 0x10
3831 #define _SSP1CON1_SSPEN 0x20
3832 #define _SSP1CON1_SSPOV 0x40
3833 #define _SSP1CON1_WCOL 0x80
3835 //==============================================================================
3838 //==============================================================================
3841 extern __at(0x0215) __sfr SSPCON
;
3864 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
3866 #define _SSPCON_SSPM0 0x01
3867 #define _SSPCON_SSPM1 0x02
3868 #define _SSPCON_SSPM2 0x04
3869 #define _SSPCON_SSPM3 0x08
3870 #define _SSPCON_CKP 0x10
3871 #define _SSPCON_SSPEN 0x20
3872 #define _SSPCON_SSPOV 0x40
3873 #define _SSPCON_WCOL 0x80
3875 //==============================================================================
3878 //==============================================================================
3881 extern __at(0x0215) __sfr SSPCON1
;
3904 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
3906 #define _SSPCON1_SSPM0 0x01
3907 #define _SSPCON1_SSPM1 0x02
3908 #define _SSPCON1_SSPM2 0x04
3909 #define _SSPCON1_SSPM3 0x08
3910 #define _SSPCON1_CKP 0x10
3911 #define _SSPCON1_SSPEN 0x20
3912 #define _SSPCON1_SSPOV 0x40
3913 #define _SSPCON1_WCOL 0x80
3915 //==============================================================================
3918 //==============================================================================
3921 extern __at(0x0216) __sfr SSP1CON2
;
3931 unsigned ACKSTAT
: 1;
3935 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
3943 #define _ACKSTAT 0x40
3946 //==============================================================================
3949 //==============================================================================
3952 extern __at(0x0216) __sfr SSPCON2
;
3962 unsigned ACKSTAT
: 1;
3966 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
3968 #define _SSPCON2_SEN 0x01
3969 #define _SSPCON2_RSEN 0x02
3970 #define _SSPCON2_PEN 0x04
3971 #define _SSPCON2_RCEN 0x08
3972 #define _SSPCON2_ACKEN 0x10
3973 #define _SSPCON2_ACKDT 0x20
3974 #define _SSPCON2_ACKSTAT 0x40
3975 #define _SSPCON2_GCEN 0x80
3977 //==============================================================================
3980 //==============================================================================
3983 extern __at(0x0217) __sfr SSP1CON3
;
3994 unsigned ACKTIM
: 1;
3997 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
4006 #define _ACKTIM 0x80
4008 //==============================================================================
4011 //==============================================================================
4014 extern __at(0x0217) __sfr SSPCON3
;
4025 unsigned ACKTIM
: 1;
4028 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
4030 #define _SSPCON3_DHEN 0x01
4031 #define _SSPCON3_AHEN 0x02
4032 #define _SSPCON3_SBCDE 0x04
4033 #define _SSPCON3_SDAHT 0x08
4034 #define _SSPCON3_BOEN 0x10
4035 #define _SSPCON3_SCIE 0x20
4036 #define _SSPCON3_PCIE 0x40
4037 #define _SSPCON3_ACKTIM 0x80
4039 //==============================================================================
4042 //==============================================================================
4045 extern __at(0x021B) __sfr MD3CON0
;
4063 unsigned MD3BIT
: 1;
4067 unsigned MD3OPOL
: 1;
4068 unsigned MD3OUT
: 1;
4074 extern __at(0x021B) volatile __MD3CON0bits_t MD3CON0bits
;
4076 #define _MD3CON0_BIT 0x01
4077 #define _MD3CON0_MD3BIT 0x01
4078 #define _MD3CON0_OPOL 0x10
4079 #define _MD3CON0_MD3OPOL 0x10
4080 #define _MD3CON0_OUT 0x20
4081 #define _MD3CON0_MD3OUT 0x20
4082 #define _MD3CON0_EN 0x80
4083 #define _MD3CON0_MD3EN 0x80
4085 //==============================================================================
4088 //==============================================================================
4091 extern __at(0x021C) __sfr MD3CON1
;
4097 unsigned CLSYNC
: 1;
4101 unsigned CHSYNC
: 1;
4109 unsigned MD3CLSYNC
: 1;
4110 unsigned MD3CLPOL
: 1;
4113 unsigned MD3CHSYNC
: 1;
4114 unsigned MD3CHPOL
: 1;
4120 extern __at(0x021C) volatile __MD3CON1bits_t MD3CON1bits
;
4122 #define _MD3CON1_CLSYNC 0x01
4123 #define _MD3CON1_MD3CLSYNC 0x01
4124 #define _MD3CON1_CLPOL 0x02
4125 #define _MD3CON1_MD3CLPOL 0x02
4126 #define _MD3CON1_CHSYNC 0x10
4127 #define _MD3CON1_MD3CHSYNC 0x10
4128 #define _MD3CON1_CHPOL 0x20
4129 #define _MD3CON1_MD3CHPOL 0x20
4131 //==============================================================================
4134 //==============================================================================
4137 extern __at(0x021D) __sfr MD3SRC
;
4155 unsigned MD3MS0
: 1;
4156 unsigned MD3MS1
: 1;
4157 unsigned MD3MS2
: 1;
4158 unsigned MD3MS3
: 1;
4159 unsigned MD3MS4
: 1;
4178 extern __at(0x021D) volatile __MD3SRCbits_t MD3SRCbits
;
4180 #define _MD3SRC_MS0 0x01
4181 #define _MD3SRC_MD3MS0 0x01
4182 #define _MD3SRC_MS1 0x02
4183 #define _MD3SRC_MD3MS1 0x02
4184 #define _MD3SRC_MS2 0x04
4185 #define _MD3SRC_MD3MS2 0x04
4186 #define _MD3SRC_MS3 0x08
4187 #define _MD3SRC_MD3MS3 0x08
4188 #define _MD3SRC_MS4 0x10
4189 #define _MD3SRC_MD3MS4 0x10
4191 //==============================================================================
4194 //==============================================================================
4197 extern __at(0x021E) __sfr MD3CARL
;
4215 unsigned MD3CL0
: 1;
4216 unsigned MD3CL1
: 1;
4217 unsigned MD3CL2
: 1;
4218 unsigned MD3CL3
: 1;
4238 extern __at(0x021E) volatile __MD3CARLbits_t MD3CARLbits
;
4240 #define _MD3CARL_CL0 0x01
4241 #define _MD3CARL_MD3CL0 0x01
4242 #define _MD3CARL_CL1 0x02
4243 #define _MD3CARL_MD3CL1 0x02
4244 #define _MD3CARL_CL2 0x04
4245 #define _MD3CARL_MD3CL2 0x04
4246 #define _MD3CARL_CL3 0x08
4247 #define _MD3CARL_MD3CL3 0x08
4248 #define _MD3CARL_CL4 0x10
4250 //==============================================================================
4253 //==============================================================================
4256 extern __at(0x021F) __sfr MD3CARH
;
4274 unsigned MD3CH0
: 1;
4275 unsigned MD3CH1
: 1;
4276 unsigned MD3CH2
: 1;
4277 unsigned MD3CH3
: 1;
4297 extern __at(0x021F) volatile __MD3CARHbits_t MD3CARHbits
;
4299 #define _MD3CARH_CH0 0x01
4300 #define _MD3CARH_MD3CH0 0x01
4301 #define _MD3CARH_CH1 0x02
4302 #define _MD3CARH_MD3CH1 0x02
4303 #define _MD3CARH_CH2 0x04
4304 #define _MD3CARH_MD3CH2 0x04
4305 #define _MD3CARH_CH3 0x08
4306 #define _MD3CARH_MD3CH3 0x08
4307 #define _MD3CARH_CH4 0x10
4309 //==============================================================================
4312 //==============================================================================
4315 extern __at(0x028C) __sfr ODCONA
;
4329 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
4340 //==============================================================================
4343 //==============================================================================
4346 extern __at(0x028D) __sfr ODCONB
;
4369 extern __at(0x028D) volatile __ODCONBbits_t ODCONBbits
;
4371 #define _ODCONB_ODA0 0x01
4372 #define _ODCONB_ODA1 0x02
4373 #define _ODCONB_ODA2 0x04
4374 #define _ODCONB_ODA3 0x08
4375 #define _ODCONB_ODB4 0x10
4376 #define _ODCONB_ODB5 0x20
4377 #define _ODCONB_ODB6 0x40
4378 #define _ODCONB_ODB7 0x80
4380 //==============================================================================
4383 //==============================================================================
4386 extern __at(0x028E) __sfr ODCONC
;
4400 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
4411 //==============================================================================
4413 extern __at(0x0291) __sfr CCPR1
;
4414 extern __at(0x0291) __sfr CCPR1L
;
4415 extern __at(0x0292) __sfr CCPR1H
;
4417 //==============================================================================
4420 extern __at(0x0293) __sfr CCP1CON
;
4438 unsigned CCP1MODE0
: 1;
4439 unsigned CCP1MODE1
: 1;
4440 unsigned CCP1MODE2
: 1;
4441 unsigned CCP1MODE3
: 1;
4442 unsigned CCP1FMT
: 1;
4443 unsigned CCP1OUT
: 1;
4445 unsigned CCP1EN
: 1;
4450 unsigned CCP1MODE
: 4;
4461 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
4464 #define _CCP1MODE0 0x01
4466 #define _CCP1MODE1 0x02
4468 #define _CCP1MODE2 0x04
4470 #define _CCP1MODE3 0x08
4472 #define _CCP1FMT 0x10
4474 #define _CCP1OUT 0x20
4476 #define _CCP1EN 0x80
4478 //==============================================================================
4481 //==============================================================================
4484 extern __at(0x0294) __sfr CCP1CAP
;
4502 unsigned CCP1CTS0
: 1;
4503 unsigned CCP1CTS1
: 1;
4504 unsigned CCP1CTS2
: 1;
4505 unsigned CCP1CTS3
: 1;
4520 unsigned CCP1CTS
: 4;
4525 extern __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits
;
4528 #define _CCP1CTS0 0x01
4530 #define _CCP1CTS1 0x02
4532 #define _CCP1CTS2 0x04
4534 #define _CCP1CTS3 0x08
4536 //==============================================================================
4538 extern __at(0x0295) __sfr CCPR2
;
4539 extern __at(0x0295) __sfr CCPR2L
;
4540 extern __at(0x0296) __sfr CCPR2H
;
4542 //==============================================================================
4545 extern __at(0x0297) __sfr CCP2CON
;
4563 unsigned CCP2MODE0
: 1;
4564 unsigned CCP2MODE1
: 1;
4565 unsigned CCP2MODE2
: 1;
4566 unsigned CCP2MODE3
: 1;
4567 unsigned CCP2FMT
: 1;
4568 unsigned CCP2OUT
: 1;
4570 unsigned CCP2EN
: 1;
4581 unsigned CCP2MODE
: 4;
4586 extern __at(0x0297) volatile __CCP2CONbits_t CCP2CONbits
;
4588 #define _CCP2CON_MODE0 0x01
4589 #define _CCP2CON_CCP2MODE0 0x01
4590 #define _CCP2CON_MODE1 0x02
4591 #define _CCP2CON_CCP2MODE1 0x02
4592 #define _CCP2CON_MODE2 0x04
4593 #define _CCP2CON_CCP2MODE2 0x04
4594 #define _CCP2CON_MODE3 0x08
4595 #define _CCP2CON_CCP2MODE3 0x08
4596 #define _CCP2CON_FMT 0x10
4597 #define _CCP2CON_CCP2FMT 0x10
4598 #define _CCP2CON_OUT 0x20
4599 #define _CCP2CON_CCP2OUT 0x20
4600 #define _CCP2CON_EN 0x80
4601 #define _CCP2CON_CCP2EN 0x80
4603 //==============================================================================
4606 //==============================================================================
4609 extern __at(0x0298) __sfr CCP2CAP
;
4627 unsigned CCP2CTS0
: 1;
4628 unsigned CCP2CTS1
: 1;
4629 unsigned CCP2CTS2
: 1;
4630 unsigned CCP2CTS3
: 1;
4645 unsigned CCP2CTS
: 4;
4650 extern __at(0x0298) volatile __CCP2CAPbits_t CCP2CAPbits
;
4652 #define _CCP2CAP_CTS0 0x01
4653 #define _CCP2CAP_CCP2CTS0 0x01
4654 #define _CCP2CAP_CTS1 0x02
4655 #define _CCP2CAP_CCP2CTS1 0x02
4656 #define _CCP2CAP_CTS2 0x04
4657 #define _CCP2CAP_CCP2CTS2 0x04
4658 #define _CCP2CAP_CTS3 0x08
4659 #define _CCP2CAP_CCP2CTS3 0x08
4661 //==============================================================================
4663 extern __at(0x0299) __sfr CCPR7
;
4664 extern __at(0x0299) __sfr CCPR7L
;
4665 extern __at(0x029A) __sfr CCPR7H
;
4667 //==============================================================================
4670 extern __at(0x029B) __sfr CCP7CON
;
4688 unsigned CCP7MODE0
: 1;
4689 unsigned CCP7MODE1
: 1;
4690 unsigned CCP7MODE2
: 1;
4691 unsigned CCP7MODE3
: 1;
4692 unsigned CCP7FMT
: 1;
4693 unsigned CCP7OUT
: 1;
4695 unsigned CCP7EN
: 1;
4700 unsigned CCP7MODE
: 4;
4711 extern __at(0x029B) volatile __CCP7CONbits_t CCP7CONbits
;
4713 #define _CCP7CON_MODE0 0x01
4714 #define _CCP7CON_CCP7MODE0 0x01
4715 #define _CCP7CON_MODE1 0x02
4716 #define _CCP7CON_CCP7MODE1 0x02
4717 #define _CCP7CON_MODE2 0x04
4718 #define _CCP7CON_CCP7MODE2 0x04
4719 #define _CCP7CON_MODE3 0x08
4720 #define _CCP7CON_CCP7MODE3 0x08
4721 #define _CCP7CON_FMT 0x10
4722 #define _CCP7CON_CCP7FMT 0x10
4723 #define _CCP7CON_OUT 0x20
4724 #define _CCP7CON_CCP7OUT 0x20
4725 #define _CCP7CON_EN 0x80
4726 #define _CCP7CON_CCP7EN 0x80
4728 //==============================================================================
4731 //==============================================================================
4734 extern __at(0x029C) __sfr CCP7CAP
;
4752 unsigned CCP7CTS0
: 1;
4753 unsigned CCP7CTS1
: 1;
4754 unsigned CCP7CTS2
: 1;
4755 unsigned CCP7CTS3
: 1;
4764 unsigned CCP7CTS
: 4;
4775 extern __at(0x029C) volatile __CCP7CAPbits_t CCP7CAPbits
;
4777 #define _CCP7CAP_CTS0 0x01
4778 #define _CCP7CAP_CCP7CTS0 0x01
4779 #define _CCP7CAP_CTS1 0x02
4780 #define _CCP7CAP_CCP7CTS1 0x02
4781 #define _CCP7CAP_CTS2 0x04
4782 #define _CCP7CAP_CCP7CTS2 0x04
4783 #define _CCP7CAP_CTS3 0x08
4784 #define _CCP7CAP_CCP7CTS3 0x08
4786 //==============================================================================
4789 //==============================================================================
4792 extern __at(0x029E) __sfr CCPTMRS1
;
4798 unsigned C1TSEL0
: 1;
4799 unsigned C1TSEL1
: 1;
4800 unsigned C2TSEL0
: 1;
4801 unsigned C2TSEL1
: 1;
4802 unsigned C7TSEL0
: 1;
4803 unsigned C7TSEL1
: 1;
4810 unsigned C1TSEL
: 2;
4817 unsigned C2TSEL
: 2;
4824 unsigned C7TSEL
: 2;
4829 extern __at(0x029E) volatile __CCPTMRS1bits_t CCPTMRS1bits
;
4831 #define _C1TSEL0 0x01
4832 #define _C1TSEL1 0x02
4833 #define _C2TSEL0 0x04
4834 #define _C2TSEL1 0x08
4835 #define _C7TSEL0 0x10
4836 #define _C7TSEL1 0x20
4838 //==============================================================================
4841 //==============================================================================
4844 extern __at(0x029F) __sfr CCPTMRS2
;
4850 unsigned P3TSEL0
: 1;
4851 unsigned P3TSEL1
: 1;
4852 unsigned P4TSEL0
: 1;
4853 unsigned P4TSEL1
: 1;
4854 unsigned P9TSEL0
: 1;
4855 unsigned P9TSEL1
: 1;
4862 unsigned P3TSEL
: 2;
4869 unsigned P4TSEL
: 2;
4876 unsigned P9TSEL
: 2;
4881 extern __at(0x029F) volatile __CCPTMRS2bits_t CCPTMRS2bits
;
4883 #define _P3TSEL0 0x01
4884 #define _P3TSEL1 0x02
4885 #define _P4TSEL0 0x04
4886 #define _P4TSEL1 0x08
4887 #define _P9TSEL0 0x10
4888 #define _P9TSEL1 0x20
4890 //==============================================================================
4893 //==============================================================================
4896 extern __at(0x030C) __sfr SLRCONA
;
4910 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
4921 //==============================================================================
4924 //==============================================================================
4927 extern __at(0x030D) __sfr SLRCONB
;
4941 extern __at(0x030D) volatile __SLRCONBbits_t SLRCONBbits
;
4952 //==============================================================================
4955 //==============================================================================
4958 extern __at(0x030E) __sfr SLRCONC
;
4972 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
4983 //==============================================================================
4986 //==============================================================================
4989 extern __at(0x0315) __sfr MD1CON0
;
5007 unsigned MD1BIT
: 1;
5011 unsigned MD1OPOL
: 1;
5012 unsigned MD1OUT
: 1;
5018 extern __at(0x0315) volatile __MD1CON0bits_t MD1CON0bits
;
5020 #define _MD1CON0_BIT 0x01
5021 #define _MD1CON0_MD1BIT 0x01
5022 #define _MD1CON0_OPOL 0x10
5023 #define _MD1CON0_MD1OPOL 0x10
5024 #define _MD1CON0_OUT 0x20
5025 #define _MD1CON0_MD1OUT 0x20
5026 #define _MD1CON0_EN 0x80
5027 #define _MD1CON0_MD1EN 0x80
5029 //==============================================================================
5032 //==============================================================================
5035 extern __at(0x0316) __sfr MD1CON1
;
5041 unsigned CLSYNC
: 1;
5045 unsigned CHSYNC
: 1;
5053 unsigned MD1CLSYNC
: 1;
5054 unsigned MD1CLPOL
: 1;
5057 unsigned MD1CHSYNC
: 1;
5058 unsigned MD1CHPOL
: 1;
5064 extern __at(0x0316) volatile __MD1CON1bits_t MD1CON1bits
;
5066 #define _CLSYNC 0x01
5067 #define _MD1CLSYNC 0x01
5069 #define _MD1CLPOL 0x02
5070 #define _CHSYNC 0x10
5071 #define _MD1CHSYNC 0x10
5073 #define _MD1CHPOL 0x20
5075 //==============================================================================
5078 //==============================================================================
5081 extern __at(0x0317) __sfr MD1SRC
;
5099 unsigned MD1MS0
: 1;
5100 unsigned MD1MS1
: 1;
5101 unsigned MD1MS2
: 1;
5102 unsigned MD1MS3
: 1;
5103 unsigned MD1MS4
: 1;
5122 extern __at(0x0317) volatile __MD1SRCbits_t MD1SRCbits
;
5125 #define _MD1MS0 0x01
5127 #define _MD1MS1 0x02
5129 #define _MD1MS2 0x04
5131 #define _MD1MS3 0x08
5133 #define _MD1MS4 0x10
5135 //==============================================================================
5138 //==============================================================================
5141 extern __at(0x0318) __sfr MD1CARL
;
5159 unsigned MD1CL0
: 1;
5160 unsigned MD1CL1
: 1;
5161 unsigned MD1CL2
: 1;
5162 unsigned MD1CL3
: 1;
5182 extern __at(0x0318) volatile __MD1CARLbits_t MD1CARLbits
;
5185 #define _MD1CL0 0x01
5187 #define _MD1CL1 0x02
5189 #define _MD1CL2 0x04
5191 #define _MD1CL3 0x08
5194 //==============================================================================
5197 //==============================================================================
5200 extern __at(0x0319) __sfr MD1CARH
;
5218 unsigned MD1CH0
: 1;
5219 unsigned MD1CH1
: 1;
5220 unsigned MD1CH2
: 1;
5221 unsigned MD1CH3
: 1;
5241 extern __at(0x0319) volatile __MD1CARHbits_t MD1CARHbits
;
5244 #define _MD1CH0 0x01
5246 #define _MD1CH1 0x02
5248 #define _MD1CH2 0x04
5250 #define _MD1CH3 0x08
5253 //==============================================================================
5256 //==============================================================================
5259 extern __at(0x031B) __sfr MD2CON0
;
5277 unsigned MD2BIT
: 1;
5281 unsigned MD2OPOL
: 1;
5282 unsigned MD2OUT
: 1;
5288 extern __at(0x031B) volatile __MD2CON0bits_t MD2CON0bits
;
5290 #define _MD2CON0_BIT 0x01
5291 #define _MD2CON0_MD2BIT 0x01
5292 #define _MD2CON0_OPOL 0x10
5293 #define _MD2CON0_MD2OPOL 0x10
5294 #define _MD2CON0_OUT 0x20
5295 #define _MD2CON0_MD2OUT 0x20
5296 #define _MD2CON0_EN 0x80
5297 #define _MD2CON0_MD2EN 0x80
5299 //==============================================================================
5302 //==============================================================================
5305 extern __at(0x031C) __sfr MD2CON1
;
5311 unsigned CLSYNC
: 1;
5315 unsigned CHSYNC
: 1;
5323 unsigned MD2CLSYNC
: 1;
5324 unsigned MD2CLPOL
: 1;
5327 unsigned MD2CHSYNC
: 1;
5328 unsigned MD2CHPOL
: 1;
5334 extern __at(0x031C) volatile __MD2CON1bits_t MD2CON1bits
;
5336 #define _MD2CON1_CLSYNC 0x01
5337 #define _MD2CON1_MD2CLSYNC 0x01
5338 #define _MD2CON1_CLPOL 0x02
5339 #define _MD2CON1_MD2CLPOL 0x02
5340 #define _MD2CON1_CHSYNC 0x10
5341 #define _MD2CON1_MD2CHSYNC 0x10
5342 #define _MD2CON1_CHPOL 0x20
5343 #define _MD2CON1_MD2CHPOL 0x20
5345 //==============================================================================
5348 //==============================================================================
5351 extern __at(0x031D) __sfr MD2SRC
;
5369 unsigned MD2MS0
: 1;
5370 unsigned MD2MS1
: 1;
5371 unsigned MD2MS2
: 1;
5372 unsigned MD2MS3
: 1;
5373 unsigned MD2MS4
: 1;
5392 extern __at(0x031D) volatile __MD2SRCbits_t MD2SRCbits
;
5394 #define _MD2SRC_MS0 0x01
5395 #define _MD2SRC_MD2MS0 0x01
5396 #define _MD2SRC_MS1 0x02
5397 #define _MD2SRC_MD2MS1 0x02
5398 #define _MD2SRC_MS2 0x04
5399 #define _MD2SRC_MD2MS2 0x04
5400 #define _MD2SRC_MS3 0x08
5401 #define _MD2SRC_MD2MS3 0x08
5402 #define _MD2SRC_MS4 0x10
5403 #define _MD2SRC_MD2MS4 0x10
5405 //==============================================================================
5408 //==============================================================================
5411 extern __at(0x031E) __sfr MD2CARL
;
5429 unsigned MD2CL0
: 1;
5430 unsigned MD2CL1
: 1;
5431 unsigned MD2CL2
: 1;
5432 unsigned MD2CL3
: 1;
5452 extern __at(0x031E) volatile __MD2CARLbits_t MD2CARLbits
;
5454 #define _MD2CARL_CL0 0x01
5455 #define _MD2CARL_MD2CL0 0x01
5456 #define _MD2CARL_CL1 0x02
5457 #define _MD2CARL_MD2CL1 0x02
5458 #define _MD2CARL_CL2 0x04
5459 #define _MD2CARL_MD2CL2 0x04
5460 #define _MD2CARL_CL3 0x08
5461 #define _MD2CARL_MD2CL3 0x08
5462 #define _MD2CARL_CL4 0x10
5464 //==============================================================================
5467 //==============================================================================
5470 extern __at(0x031F) __sfr MD2CARH
;
5488 unsigned MD2CH0
: 1;
5489 unsigned MD2CH1
: 1;
5490 unsigned MD2CH2
: 1;
5491 unsigned MD2CH3
: 1;
5511 extern __at(0x031F) volatile __MD2CARHbits_t MD2CARHbits
;
5513 #define _MD2CARH_CH0 0x01
5514 #define _MD2CARH_MD2CH0 0x01
5515 #define _MD2CARH_CH1 0x02
5516 #define _MD2CARH_MD2CH1 0x02
5517 #define _MD2CARH_CH2 0x04
5518 #define _MD2CARH_MD2CH2 0x04
5519 #define _MD2CARH_CH3 0x08
5520 #define _MD2CARH_MD2CH3 0x08
5521 #define _MD2CARH_CH4 0x10
5523 //==============================================================================
5526 //==============================================================================
5529 extern __at(0x038C) __sfr INLVLA
;
5535 unsigned INLVLA0
: 1;
5536 unsigned INLVLA1
: 1;
5537 unsigned INLVLA2
: 1;
5538 unsigned INLVLA3
: 1;
5539 unsigned INLVLA4
: 1;
5540 unsigned INLVLA5
: 1;
5541 unsigned INLVA6
: 1;
5542 unsigned INLVA7
: 1;
5547 unsigned INLVLA
: 6;
5552 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
5554 #define _INLVLA0 0x01
5555 #define _INLVLA1 0x02
5556 #define _INLVLA2 0x04
5557 #define _INLVLA3 0x08
5558 #define _INLVLA4 0x10
5559 #define _INLVLA5 0x20
5560 #define _INLVA6 0x40
5561 #define _INLVA7 0x80
5563 //==============================================================================
5566 //==============================================================================
5569 extern __at(0x038D) __sfr INLVLB
;
5575 unsigned INLVB0
: 1;
5576 unsigned INLVB1
: 1;
5577 unsigned INLVB2
: 1;
5578 unsigned INLVB3
: 1;
5579 unsigned INLVLB4
: 1;
5580 unsigned INLVLB5
: 1;
5581 unsigned INLVLB6
: 1;
5582 unsigned INLVLB7
: 1;
5592 extern __at(0x038D) volatile __INLVLBbits_t INLVLBbits
;
5594 #define _INLVB0 0x01
5595 #define _INLVB1 0x02
5596 #define _INLVB2 0x04
5597 #define _INLVB3 0x08
5598 #define _INLVLB4 0x10
5599 #define _INLVLB5 0x20
5600 #define _INLVLB6 0x40
5601 #define _INLVLB7 0x80
5603 //==============================================================================
5606 //==============================================================================
5609 extern __at(0x038E) __sfr INLVLC
;
5613 unsigned INLVLC0
: 1;
5614 unsigned INLVLC1
: 1;
5615 unsigned INLVLC2
: 1;
5616 unsigned INLVLC3
: 1;
5617 unsigned INLVLC4
: 1;
5618 unsigned INLVLC5
: 1;
5619 unsigned INLVLC6
: 1;
5620 unsigned INLVLC7
: 1;
5623 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
5625 #define _INLVLC0 0x01
5626 #define _INLVLC1 0x02
5627 #define _INLVLC2 0x04
5628 #define _INLVLC3 0x08
5629 #define _INLVLC4 0x10
5630 #define _INLVLC5 0x20
5631 #define _INLVLC6 0x40
5632 #define _INLVLC7 0x80
5634 //==============================================================================
5637 //==============================================================================
5640 extern __at(0x0390) __sfr INLVE
;
5647 unsigned INLVE3
: 1;
5654 extern __at(0x0390) volatile __INLVEbits_t INLVEbits
;
5656 #define _INLVE3 0x08
5658 //==============================================================================
5661 //==============================================================================
5664 extern __at(0x0391) __sfr IOCAP
;
5668 unsigned IOCAP0
: 1;
5669 unsigned IOCAP1
: 1;
5670 unsigned IOCAP2
: 1;
5671 unsigned IOCAP3
: 1;
5672 unsigned IOCAP4
: 1;
5673 unsigned IOCAP5
: 1;
5674 unsigned IOCAP6
: 1;
5675 unsigned IOCAP7
: 1;
5678 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
5680 #define _IOCAP0 0x01
5681 #define _IOCAP1 0x02
5682 #define _IOCAP2 0x04
5683 #define _IOCAP3 0x08
5684 #define _IOCAP4 0x10
5685 #define _IOCAP5 0x20
5686 #define _IOCAP6 0x40
5687 #define _IOCAP7 0x80
5689 //==============================================================================
5692 //==============================================================================
5695 extern __at(0x0392) __sfr IOCAN
;
5699 unsigned IOCAN0
: 1;
5700 unsigned IOCAN1
: 1;
5701 unsigned IOCAN2
: 1;
5702 unsigned IOCAN3
: 1;
5703 unsigned IOCAN4
: 1;
5704 unsigned IOCAN5
: 1;
5705 unsigned IOCAN6
: 1;
5706 unsigned IOCAN7
: 1;
5709 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
5711 #define _IOCAN0 0x01
5712 #define _IOCAN1 0x02
5713 #define _IOCAN2 0x04
5714 #define _IOCAN3 0x08
5715 #define _IOCAN4 0x10
5716 #define _IOCAN5 0x20
5717 #define _IOCAN6 0x40
5718 #define _IOCAN7 0x80
5720 //==============================================================================
5723 //==============================================================================
5726 extern __at(0x0393) __sfr IOCAF
;
5730 unsigned IOCAF0
: 1;
5731 unsigned IOCAF1
: 1;
5732 unsigned IOCAF2
: 1;
5733 unsigned IOCAF3
: 1;
5734 unsigned IOCAF4
: 1;
5735 unsigned IOCAF5
: 1;
5736 unsigned IOCAF6
: 1;
5737 unsigned IOCAF7
: 1;
5740 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
5742 #define _IOCAF0 0x01
5743 #define _IOCAF1 0x02
5744 #define _IOCAF2 0x04
5745 #define _IOCAF3 0x08
5746 #define _IOCAF4 0x10
5747 #define _IOCAF5 0x20
5748 #define _IOCAF6 0x40
5749 #define _IOCAF7 0x80
5751 //==============================================================================
5754 //==============================================================================
5757 extern __at(0x0394) __sfr IOCBP
;
5761 unsigned IOCBP0
: 1;
5762 unsigned IOCBP1
: 1;
5763 unsigned IOCBP2
: 1;
5764 unsigned IOCBP3
: 1;
5765 unsigned IOCBP4
: 1;
5766 unsigned IOCBP5
: 1;
5767 unsigned IOCBP6
: 1;
5768 unsigned IOCBP7
: 1;
5771 extern __at(0x0394) volatile __IOCBPbits_t IOCBPbits
;
5773 #define _IOCBP0 0x01
5774 #define _IOCBP1 0x02
5775 #define _IOCBP2 0x04
5776 #define _IOCBP3 0x08
5777 #define _IOCBP4 0x10
5778 #define _IOCBP5 0x20
5779 #define _IOCBP6 0x40
5780 #define _IOCBP7 0x80
5782 //==============================================================================
5785 //==============================================================================
5788 extern __at(0x0395) __sfr IOCBN
;
5792 unsigned IOCBN0
: 1;
5793 unsigned IOCBN1
: 1;
5794 unsigned IOCBN2
: 1;
5795 unsigned IOCBN3
: 1;
5796 unsigned IOCBN4
: 1;
5797 unsigned IOCBN5
: 1;
5798 unsigned IOCBN6
: 1;
5799 unsigned IOCBN7
: 1;
5802 extern __at(0x0395) volatile __IOCBNbits_t IOCBNbits
;
5804 #define _IOCBN0 0x01
5805 #define _IOCBN1 0x02
5806 #define _IOCBN2 0x04
5807 #define _IOCBN3 0x08
5808 #define _IOCBN4 0x10
5809 #define _IOCBN5 0x20
5810 #define _IOCBN6 0x40
5811 #define _IOCBN7 0x80
5813 //==============================================================================
5816 //==============================================================================
5819 extern __at(0x0396) __sfr IOCBF
;
5823 unsigned IOCBF0
: 1;
5824 unsigned IOCBF1
: 1;
5825 unsigned IOCBF2
: 1;
5826 unsigned IOCBF3
: 1;
5827 unsigned IOCBF4
: 1;
5828 unsigned IOCBF5
: 1;
5829 unsigned IOCBF6
: 1;
5830 unsigned IOCBF7
: 1;
5833 extern __at(0x0396) volatile __IOCBFbits_t IOCBFbits
;
5835 #define _IOCBF0 0x01
5836 #define _IOCBF1 0x02
5837 #define _IOCBF2 0x04
5838 #define _IOCBF3 0x08
5839 #define _IOCBF4 0x10
5840 #define _IOCBF5 0x20
5841 #define _IOCBF6 0x40
5842 #define _IOCBF7 0x80
5844 //==============================================================================
5847 //==============================================================================
5850 extern __at(0x0397) __sfr IOCCP
;
5854 unsigned IOCCP0
: 1;
5855 unsigned IOCCP1
: 1;
5856 unsigned IOCCP2
: 1;
5857 unsigned IOCCP3
: 1;
5858 unsigned IOCCP4
: 1;
5859 unsigned IOCCP5
: 1;
5860 unsigned IOCCP6
: 1;
5861 unsigned IOCCP7
: 1;
5864 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
5866 #define _IOCCP0 0x01
5867 #define _IOCCP1 0x02
5868 #define _IOCCP2 0x04
5869 #define _IOCCP3 0x08
5870 #define _IOCCP4 0x10
5871 #define _IOCCP5 0x20
5872 #define _IOCCP6 0x40
5873 #define _IOCCP7 0x80
5875 //==============================================================================
5878 //==============================================================================
5881 extern __at(0x0398) __sfr IOCCN
;
5885 unsigned IOCCN0
: 1;
5886 unsigned IOCCN1
: 1;
5887 unsigned IOCCN2
: 1;
5888 unsigned IOCCN3
: 1;
5889 unsigned IOCCN4
: 1;
5890 unsigned IOCCN5
: 1;
5891 unsigned IOCCN6
: 1;
5892 unsigned IOCCN7
: 1;
5895 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
5897 #define _IOCCN0 0x01
5898 #define _IOCCN1 0x02
5899 #define _IOCCN2 0x04
5900 #define _IOCCN3 0x08
5901 #define _IOCCN4 0x10
5902 #define _IOCCN5 0x20
5903 #define _IOCCN6 0x40
5904 #define _IOCCN7 0x80
5906 //==============================================================================
5909 //==============================================================================
5912 extern __at(0x0399) __sfr IOCCF
;
5916 unsigned IOCCF0
: 1;
5917 unsigned IOCCF1
: 1;
5918 unsigned IOCCF2
: 1;
5919 unsigned IOCCF3
: 1;
5920 unsigned IOCCF4
: 1;
5921 unsigned IOCCF5
: 1;
5922 unsigned IOCCF6
: 1;
5923 unsigned IOCCF7
: 1;
5926 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
5928 #define _IOCCF0 0x01
5929 #define _IOCCF1 0x02
5930 #define _IOCCF2 0x04
5931 #define _IOCCF3 0x08
5932 #define _IOCCF4 0x10
5933 #define _IOCCF5 0x20
5934 #define _IOCCF6 0x40
5935 #define _IOCCF7 0x80
5937 //==============================================================================
5940 //==============================================================================
5943 extern __at(0x039D) __sfr IOCEP
;
5950 unsigned IOCEP3
: 1;
5957 extern __at(0x039D) volatile __IOCEPbits_t IOCEPbits
;
5959 #define _IOCEP3 0x08
5961 //==============================================================================
5964 //==============================================================================
5967 extern __at(0x039E) __sfr IOCEN
;
5974 unsigned IOCEN3
: 1;
5981 extern __at(0x039E) volatile __IOCENbits_t IOCENbits
;
5983 #define _IOCEN3 0x08
5985 //==============================================================================
5988 //==============================================================================
5991 extern __at(0x039F) __sfr IOCEF
;
5998 unsigned IOCEF3
: 1;
6005 extern __at(0x039F) volatile __IOCEFbits_t IOCEFbits
;
6007 #define _IOCEF3 0x08
6009 //==============================================================================
6012 //==============================================================================
6015 extern __at(0x040D) __sfr HIDRVB
;
6038 extern __at(0x040D) volatile __HIDRVBbits_t HIDRVBbits
;
6043 //==============================================================================
6045 extern __at(0x040F) __sfr TMR5
;
6046 extern __at(0x040F) __sfr TMR5L
;
6047 extern __at(0x0410) __sfr TMR5H
;
6049 //==============================================================================
6052 extern __at(0x0411) __sfr T5CON
;
6060 unsigned NOT_SYNC
: 1;
6073 unsigned SOSCEN
: 1;
6074 unsigned T5CKPS0
: 1;
6075 unsigned T5CKPS1
: 1;
6082 unsigned TMR5ON
: 1;
6084 unsigned NOT_T5SYNC
: 1;
6085 unsigned T5OSCEN
: 1;
6088 unsigned TMR5CS0
: 1;
6089 unsigned TMR5CS1
: 1;
6114 unsigned T5CKPS
: 2;
6121 unsigned TMR5CS
: 2;
6137 extern __at(0x0411) volatile __T5CONbits_t T5CONbits
;
6139 #define _T5CON_ON 0x01
6140 #define _T5CON_TMRON 0x01
6141 #define _T5CON_TMR5ON 0x01
6142 #define _T5CON_T5ON 0x01
6143 #define _T5CON_NOT_SYNC 0x04
6144 #define _T5CON_SYNC 0x04
6145 #define _T5CON_NOT_T5SYNC 0x04
6146 #define _T5CON_OSCEN 0x08
6147 #define _T5CON_SOSCEN 0x08
6148 #define _T5CON_T5OSCEN 0x08
6149 #define _T5CON_CKPS0 0x10
6150 #define _T5CON_T5CKPS0 0x10
6151 #define _T5CON_CKPS1 0x20
6152 #define _T5CON_T5CKPS1 0x20
6153 #define _T5CON_CS0 0x40
6154 #define _T5CON_T5CS0 0x40
6155 #define _T5CON_TMR5CS0 0x40
6156 #define _T5CON_CS1 0x80
6157 #define _T5CON_T5CS1 0x80
6158 #define _T5CON_TMR5CS1 0x80
6160 //==============================================================================
6163 //==============================================================================
6166 extern __at(0x0412) __sfr T5GCON
;
6175 unsigned GGO_NOT_DONE
: 1;
6184 unsigned T5GSS0
: 1;
6185 unsigned T5GSS1
: 1;
6186 unsigned T5GVAL
: 1;
6187 unsigned T5GGO_NOT_DONE
: 1;
6188 unsigned T5GSPM
: 1;
6190 unsigned T5GPOL
: 1;
6203 unsigned TMR5GE
: 1;
6219 extern __at(0x0412) volatile __T5GCONbits_t T5GCONbits
;
6221 #define _T5GCON_GSS0 0x01
6222 #define _T5GCON_T5GSS0 0x01
6223 #define _T5GCON_GSS1 0x02
6224 #define _T5GCON_T5GSS1 0x02
6225 #define _T5GCON_GVAL 0x04
6226 #define _T5GCON_T5GVAL 0x04
6227 #define _T5GCON_GGO_NOT_DONE 0x08
6228 #define _T5GCON_T5GGO_NOT_DONE 0x08
6229 #define _T5GCON_GSPM 0x10
6230 #define _T5GCON_T5GSPM 0x10
6231 #define _T5GCON_GTM 0x20
6232 #define _T5GCON_T5GTM 0x20
6233 #define _T5GCON_GPOL 0x40
6234 #define _T5GCON_T5GPOL 0x40
6235 #define _T5GCON_GE 0x80
6236 #define _T5GCON_T5GE 0x80
6237 #define _T5GCON_TMR5GE 0x80
6239 //==============================================================================
6241 extern __at(0x0413) __sfr T4TMR
;
6242 extern __at(0x0413) __sfr TMR4
;
6243 extern __at(0x0414) __sfr PR4
;
6244 extern __at(0x0414) __sfr T4PR
;
6246 //==============================================================================
6249 extern __at(0x0415) __sfr T4CON
;
6255 unsigned OUTPS0
: 1;
6256 unsigned OUTPS1
: 1;
6257 unsigned OUTPS2
: 1;
6258 unsigned OUTPS3
: 1;
6267 unsigned T4OUTPS0
: 1;
6268 unsigned T4OUTPS1
: 1;
6269 unsigned T4OUTPS2
: 1;
6270 unsigned T4OUTPS3
: 1;
6271 unsigned T4CKPS0
: 1;
6272 unsigned T4CKPS1
: 1;
6273 unsigned T4CKPS2
: 1;
6286 unsigned TMR4ON
: 1;
6297 unsigned T4OUTPS
: 4;
6311 unsigned T4CKPS
: 3;
6316 extern __at(0x0415) volatile __T4CONbits_t T4CONbits
;
6318 #define _T4CON_OUTPS0 0x01
6319 #define _T4CON_T4OUTPS0 0x01
6320 #define _T4CON_OUTPS1 0x02
6321 #define _T4CON_T4OUTPS1 0x02
6322 #define _T4CON_OUTPS2 0x04
6323 #define _T4CON_T4OUTPS2 0x04
6324 #define _T4CON_OUTPS3 0x08
6325 #define _T4CON_T4OUTPS3 0x08
6326 #define _T4CON_CKPS0 0x10
6327 #define _T4CON_T4CKPS0 0x10
6328 #define _T4CON_CKPS1 0x20
6329 #define _T4CON_T4CKPS1 0x20
6330 #define _T4CON_CKPS2 0x40
6331 #define _T4CON_T4CKPS2 0x40
6332 #define _T4CON_ON 0x80
6333 #define _T4CON_T4ON 0x80
6334 #define _T4CON_TMR4ON 0x80
6336 //==============================================================================
6339 //==============================================================================
6342 extern __at(0x0416) __sfr T4HLT
;
6353 unsigned CKSYNC
: 1;
6360 unsigned T4MODE0
: 1;
6361 unsigned T4MODE1
: 1;
6362 unsigned T4MODE2
: 1;
6363 unsigned T4MODE3
: 1;
6364 unsigned T4MODE4
: 1;
6365 unsigned T4CKSYNC
: 1;
6366 unsigned T4CKPOL
: 1;
6367 unsigned T4PSYNC
: 1;
6372 unsigned T4MODE
: 5;
6383 extern __at(0x0416) volatile __T4HLTbits_t T4HLTbits
;
6385 #define _T4HLT_MODE0 0x01
6386 #define _T4HLT_T4MODE0 0x01
6387 #define _T4HLT_MODE1 0x02
6388 #define _T4HLT_T4MODE1 0x02
6389 #define _T4HLT_MODE2 0x04
6390 #define _T4HLT_T4MODE2 0x04
6391 #define _T4HLT_MODE3 0x08
6392 #define _T4HLT_T4MODE3 0x08
6393 #define _T4HLT_MODE4 0x10
6394 #define _T4HLT_T4MODE4 0x10
6395 #define _T4HLT_CKSYNC 0x20
6396 #define _T4HLT_T4CKSYNC 0x20
6397 #define _T4HLT_CKPOL 0x40
6398 #define _T4HLT_T4CKPOL 0x40
6399 #define _T4HLT_PSYNC 0x80
6400 #define _T4HLT_T4PSYNC 0x80
6402 //==============================================================================
6405 //==============================================================================
6408 extern __at(0x0417) __sfr T4CLKCON
;
6449 extern __at(0x0417) volatile __T4CLKCONbits_t T4CLKCONbits
;
6451 #define _T4CLKCON_CS0 0x01
6452 #define _T4CLKCON_T4CS0 0x01
6453 #define _T4CLKCON_CS1 0x02
6454 #define _T4CLKCON_T4CS1 0x02
6455 #define _T4CLKCON_CS2 0x04
6456 #define _T4CLKCON_T4CS2 0x04
6457 #define _T4CLKCON_CS3 0x08
6458 #define _T4CLKCON_T4CS3 0x08
6460 //==============================================================================
6463 //==============================================================================
6466 extern __at(0x0418) __sfr T4RST
;
6484 unsigned T4RSEL0
: 1;
6485 unsigned T4RSEL1
: 1;
6486 unsigned T4RSEL2
: 1;
6487 unsigned T4RSEL3
: 1;
6488 unsigned T4RSEL4
: 1;
6496 unsigned T4RSEL
: 5;
6507 extern __at(0x0418) volatile __T4RSTbits_t T4RSTbits
;
6509 #define _T4RST_RSEL0 0x01
6510 #define _T4RST_T4RSEL0 0x01
6511 #define _T4RST_RSEL1 0x02
6512 #define _T4RST_T4RSEL1 0x02
6513 #define _T4RST_RSEL2 0x04
6514 #define _T4RST_T4RSEL2 0x04
6515 #define _T4RST_RSEL3 0x08
6516 #define _T4RST_T4RSEL3 0x08
6517 #define _T4RST_RSEL4 0x10
6518 #define _T4RST_T4RSEL4 0x10
6520 //==============================================================================
6522 extern __at(0x041A) __sfr T6TMR
;
6523 extern __at(0x041A) __sfr TMR6
;
6524 extern __at(0x041B) __sfr PR6
;
6525 extern __at(0x041B) __sfr T6PR
;
6527 //==============================================================================
6530 extern __at(0x041C) __sfr T6CON
;
6536 unsigned OUTPS0
: 1;
6537 unsigned OUTPS1
: 1;
6538 unsigned OUTPS2
: 1;
6539 unsigned OUTPS3
: 1;
6548 unsigned T6OUTPS0
: 1;
6549 unsigned T6OUTPS1
: 1;
6550 unsigned T6OUTPS2
: 1;
6551 unsigned T6OUTPS3
: 1;
6552 unsigned T6CKPS0
: 1;
6553 unsigned T6CKPS1
: 1;
6554 unsigned T6CKPS2
: 1;
6567 unsigned TMR6ON
: 1;
6578 unsigned T6OUTPS
: 4;
6585 unsigned T6CKPS
: 3;
6597 extern __at(0x041C) volatile __T6CONbits_t T6CONbits
;
6599 #define _T6CON_OUTPS0 0x01
6600 #define _T6CON_T6OUTPS0 0x01
6601 #define _T6CON_OUTPS1 0x02
6602 #define _T6CON_T6OUTPS1 0x02
6603 #define _T6CON_OUTPS2 0x04
6604 #define _T6CON_T6OUTPS2 0x04
6605 #define _T6CON_OUTPS3 0x08
6606 #define _T6CON_T6OUTPS3 0x08
6607 #define _T6CON_CKPS0 0x10
6608 #define _T6CON_T6CKPS0 0x10
6609 #define _T6CON_CKPS1 0x20
6610 #define _T6CON_T6CKPS1 0x20
6611 #define _T6CON_CKPS2 0x40
6612 #define _T6CON_T6CKPS2 0x40
6613 #define _T6CON_ON 0x80
6614 #define _T6CON_T6ON 0x80
6615 #define _T6CON_TMR6ON 0x80
6617 //==============================================================================
6620 //==============================================================================
6623 extern __at(0x041D) __sfr T6HLT
;
6634 unsigned CKSYNC
: 1;
6641 unsigned T6MODE0
: 1;
6642 unsigned T6MODE1
: 1;
6643 unsigned T6MODE2
: 1;
6644 unsigned T6MODE3
: 1;
6645 unsigned T6MODE4
: 1;
6646 unsigned T6CKSYNC
: 1;
6647 unsigned T6CKPOL
: 1;
6648 unsigned T6PSYNC
: 1;
6659 unsigned T6MODE
: 5;
6664 extern __at(0x041D) volatile __T6HLTbits_t T6HLTbits
;
6666 #define _T6HLT_MODE0 0x01
6667 #define _T6HLT_T6MODE0 0x01
6668 #define _T6HLT_MODE1 0x02
6669 #define _T6HLT_T6MODE1 0x02
6670 #define _T6HLT_MODE2 0x04
6671 #define _T6HLT_T6MODE2 0x04
6672 #define _T6HLT_MODE3 0x08
6673 #define _T6HLT_T6MODE3 0x08
6674 #define _T6HLT_MODE4 0x10
6675 #define _T6HLT_T6MODE4 0x10
6676 #define _T6HLT_CKSYNC 0x20
6677 #define _T6HLT_T6CKSYNC 0x20
6678 #define _T6HLT_CKPOL 0x40
6679 #define _T6HLT_T6CKPOL 0x40
6680 #define _T6HLT_PSYNC 0x80
6681 #define _T6HLT_T6PSYNC 0x80
6683 //==============================================================================
6686 //==============================================================================
6689 extern __at(0x041E) __sfr T6CLKCON
;
6730 extern __at(0x041E) volatile __T6CLKCONbits_t T6CLKCONbits
;
6732 #define _T6CLKCON_CS0 0x01
6733 #define _T6CLKCON_T6CS0 0x01
6734 #define _T6CLKCON_CS1 0x02
6735 #define _T6CLKCON_T6CS1 0x02
6736 #define _T6CLKCON_CS2 0x04
6737 #define _T6CLKCON_T6CS2 0x04
6738 #define _T6CLKCON_CS3 0x08
6739 #define _T6CLKCON_T6CS3 0x08
6741 //==============================================================================
6744 //==============================================================================
6747 extern __at(0x041F) __sfr T6RST
;
6765 unsigned T6RSEL0
: 1;
6766 unsigned T6RSEL1
: 1;
6767 unsigned T6RSEL2
: 1;
6768 unsigned T6RSEL3
: 1;
6769 unsigned T6RSEL4
: 1;
6783 unsigned T6RSEL
: 5;
6788 extern __at(0x041F) volatile __T6RSTbits_t T6RSTbits
;
6790 #define _T6RST_RSEL0 0x01
6791 #define _T6RST_T6RSEL0 0x01
6792 #define _T6RST_RSEL1 0x02
6793 #define _T6RST_T6RSEL1 0x02
6794 #define _T6RST_RSEL2 0x04
6795 #define _T6RST_T6RSEL2 0x04
6796 #define _T6RST_RSEL3 0x08
6797 #define _T6RST_T6RSEL3 0x08
6798 #define _T6RST_RSEL4 0x10
6799 #define _T6RST_T6RSEL4 0x10
6801 //==============================================================================
6803 extern __at(0x048E) __sfr ADRESL
;
6804 extern __at(0x048F) __sfr ADRESH
;
6806 //==============================================================================
6809 extern __at(0x0490) __sfr ADCON0
;
6823 extern __at(0x0490) volatile __ADCON0bits_t ADCON0bits
;
6828 //==============================================================================
6831 //==============================================================================
6834 extern __at(0x0491) __sfr ADCON1
;
6840 unsigned ADNREF
: 1;
6848 extern __at(0x0491) volatile __ADCON1bits_t ADCON1bits
;
6850 #define _ADNREF 0x04
6853 //==============================================================================
6855 extern __at(0x0492) __sfr ADCON2
;
6856 extern __at(0x0493) __sfr T2TMR
;
6857 extern __at(0x0493) __sfr TMR2
;
6858 extern __at(0x0494) __sfr PR2
;
6859 extern __at(0x0494) __sfr T2PR
;
6861 //==============================================================================
6864 extern __at(0x0495) __sfr T2CON
;
6870 unsigned OUTPS0
: 1;
6871 unsigned OUTPS1
: 1;
6872 unsigned OUTPS2
: 1;
6873 unsigned OUTPS3
: 1;
6882 unsigned T2OUTPS0
: 1;
6883 unsigned T2OUTPS1
: 1;
6884 unsigned T2OUTPS2
: 1;
6885 unsigned T2OUTPS3
: 1;
6886 unsigned T2CKPS0
: 1;
6887 unsigned T2CKPS1
: 1;
6888 unsigned T2CKPS2
: 1;
6901 unsigned TMR2ON
: 1;
6912 unsigned T2OUTPS
: 4;
6919 unsigned T2CKPS
: 3;
6931 extern __at(0x0495) volatile __T2CONbits_t T2CONbits
;
6933 #define _T2CON_OUTPS0 0x01
6934 #define _T2CON_T2OUTPS0 0x01
6935 #define _T2CON_OUTPS1 0x02
6936 #define _T2CON_T2OUTPS1 0x02
6937 #define _T2CON_OUTPS2 0x04
6938 #define _T2CON_T2OUTPS2 0x04
6939 #define _T2CON_OUTPS3 0x08
6940 #define _T2CON_T2OUTPS3 0x08
6941 #define _T2CON_CKPS0 0x10
6942 #define _T2CON_T2CKPS0 0x10
6943 #define _T2CON_CKPS1 0x20
6944 #define _T2CON_T2CKPS1 0x20
6945 #define _T2CON_CKPS2 0x40
6946 #define _T2CON_T2CKPS2 0x40
6947 #define _T2CON_ON 0x80
6948 #define _T2CON_T2ON 0x80
6949 #define _T2CON_TMR2ON 0x80
6951 //==============================================================================
6954 //==============================================================================
6957 extern __at(0x0496) __sfr T2HLT
;
6968 unsigned CKSYNC
: 1;
6975 unsigned T2MODE0
: 1;
6976 unsigned T2MODE1
: 1;
6977 unsigned T2MODE2
: 1;
6978 unsigned T2MODE3
: 1;
6979 unsigned T2MODE4
: 1;
6980 unsigned T2CKSYNC
: 1;
6981 unsigned T2CKPOL
: 1;
6982 unsigned T2PSYNC
: 1;
6987 unsigned T2MODE
: 5;
6998 extern __at(0x0496) volatile __T2HLTbits_t T2HLTbits
;
7000 #define _T2HLT_MODE0 0x01
7001 #define _T2HLT_T2MODE0 0x01
7002 #define _T2HLT_MODE1 0x02
7003 #define _T2HLT_T2MODE1 0x02
7004 #define _T2HLT_MODE2 0x04
7005 #define _T2HLT_T2MODE2 0x04
7006 #define _T2HLT_MODE3 0x08
7007 #define _T2HLT_T2MODE3 0x08
7008 #define _T2HLT_MODE4 0x10
7009 #define _T2HLT_T2MODE4 0x10
7010 #define _T2HLT_CKSYNC 0x20
7011 #define _T2HLT_T2CKSYNC 0x20
7012 #define _T2HLT_CKPOL 0x40
7013 #define _T2HLT_T2CKPOL 0x40
7014 #define _T2HLT_PSYNC 0x80
7015 #define _T2HLT_T2PSYNC 0x80
7017 //==============================================================================
7020 //==============================================================================
7023 extern __at(0x0497) __sfr T2CLKCON
;
7064 extern __at(0x0497) volatile __T2CLKCONbits_t T2CLKCONbits
;
7066 #define _T2CLKCON_CS0 0x01
7067 #define _T2CLKCON_T2CS0 0x01
7068 #define _T2CLKCON_CS1 0x02
7069 #define _T2CLKCON_T2CS1 0x02
7070 #define _T2CLKCON_CS2 0x04
7071 #define _T2CLKCON_T2CS2 0x04
7072 #define _T2CLKCON_CS3 0x08
7073 #define _T2CLKCON_T2CS3 0x08
7075 //==============================================================================
7078 //==============================================================================
7081 extern __at(0x0498) __sfr T2RST
;
7099 unsigned T2RSEL0
: 1;
7100 unsigned T2RSEL1
: 1;
7101 unsigned T2RSEL2
: 1;
7102 unsigned T2RSEL3
: 1;
7103 unsigned T2RSEL4
: 1;
7117 unsigned T2RSEL
: 5;
7122 extern __at(0x0498) volatile __T2RSTbits_t T2RSTbits
;
7125 #define _T2RSEL0 0x01
7127 #define _T2RSEL1 0x02
7129 #define _T2RSEL2 0x04
7131 #define _T2RSEL3 0x08
7133 #define _T2RSEL4 0x10
7135 //==============================================================================
7137 extern __at(0x049A) __sfr T8TMR
;
7138 extern __at(0x049A) __sfr TMR8
;
7139 extern __at(0x049B) __sfr PR8
;
7140 extern __at(0x049B) __sfr T8PR
;
7142 //==============================================================================
7145 extern __at(0x049C) __sfr T8CON
;
7151 unsigned OUTPS0
: 1;
7152 unsigned OUTPS1
: 1;
7153 unsigned OUTPS2
: 1;
7154 unsigned OUTPS3
: 1;
7163 unsigned T8OUTPS0
: 1;
7164 unsigned T8OUTPS1
: 1;
7165 unsigned T8OUTPS2
: 1;
7166 unsigned T8OUTPS3
: 1;
7167 unsigned T8CKPS0
: 1;
7168 unsigned T8CKPS1
: 1;
7169 unsigned T8CKPS2
: 1;
7182 unsigned TMR8ON
: 1;
7187 unsigned T8OUTPS
: 4;
7207 unsigned T8CKPS
: 3;
7212 extern __at(0x049C) volatile __T8CONbits_t T8CONbits
;
7214 #define _T8CON_OUTPS0 0x01
7215 #define _T8CON_T8OUTPS0 0x01
7216 #define _T8CON_OUTPS1 0x02
7217 #define _T8CON_T8OUTPS1 0x02
7218 #define _T8CON_OUTPS2 0x04
7219 #define _T8CON_T8OUTPS2 0x04
7220 #define _T8CON_OUTPS3 0x08
7221 #define _T8CON_T8OUTPS3 0x08
7222 #define _T8CON_CKPS0 0x10
7223 #define _T8CON_T8CKPS0 0x10
7224 #define _T8CON_CKPS1 0x20
7225 #define _T8CON_T8CKPS1 0x20
7226 #define _T8CON_CKPS2 0x40
7227 #define _T8CON_T8CKPS2 0x40
7228 #define _T8CON_ON 0x80
7229 #define _T8CON_T8ON 0x80
7230 #define _T8CON_TMR8ON 0x80
7232 //==============================================================================
7235 //==============================================================================
7238 extern __at(0x049D) __sfr T8HLT
;
7249 unsigned CKSYNC
: 1;
7256 unsigned T8MODE0
: 1;
7257 unsigned T8MODE1
: 1;
7258 unsigned T8MODE2
: 1;
7259 unsigned T8MODE3
: 1;
7260 unsigned T8MODE4
: 1;
7261 unsigned T8CKSYNC
: 1;
7262 unsigned T8CKPOL
: 1;
7263 unsigned T8PSYNC
: 1;
7274 unsigned T8MODE
: 5;
7279 extern __at(0x049D) volatile __T8HLTbits_t T8HLTbits
;
7281 #define _T8HLT_MODE0 0x01
7282 #define _T8HLT_T8MODE0 0x01
7283 #define _T8HLT_MODE1 0x02
7284 #define _T8HLT_T8MODE1 0x02
7285 #define _T8HLT_MODE2 0x04
7286 #define _T8HLT_T8MODE2 0x04
7287 #define _T8HLT_MODE3 0x08
7288 #define _T8HLT_T8MODE3 0x08
7289 #define _T8HLT_MODE4 0x10
7290 #define _T8HLT_T8MODE4 0x10
7291 #define _T8HLT_CKSYNC 0x20
7292 #define _T8HLT_T8CKSYNC 0x20
7293 #define _T8HLT_CKPOL 0x40
7294 #define _T8HLT_T8CKPOL 0x40
7295 #define _T8HLT_PSYNC 0x80
7296 #define _T8HLT_T8PSYNC 0x80
7298 //==============================================================================
7301 //==============================================================================
7304 extern __at(0x049E) __sfr T8CLKCON
;
7345 extern __at(0x049E) volatile __T8CLKCONbits_t T8CLKCONbits
;
7347 #define _T8CLKCON_CS0 0x01
7348 #define _T8CLKCON_T8CS0 0x01
7349 #define _T8CLKCON_CS1 0x02
7350 #define _T8CLKCON_T8CS1 0x02
7351 #define _T8CLKCON_CS2 0x04
7352 #define _T8CLKCON_T8CS2 0x04
7353 #define _T8CLKCON_CS3 0x08
7354 #define _T8CLKCON_T8CS3 0x08
7356 //==============================================================================
7359 //==============================================================================
7362 extern __at(0x049F) __sfr T8RST
;
7380 unsigned T8RSEL0
: 1;
7381 unsigned T8RSEL1
: 1;
7382 unsigned T8RSEL2
: 1;
7383 unsigned T8RSEL3
: 1;
7384 unsigned T8RSEL4
: 1;
7392 unsigned T8RSEL
: 5;
7403 extern __at(0x049F) volatile __T8RSTbits_t T8RSTbits
;
7405 #define _T8RST_RSEL0 0x01
7406 #define _T8RST_T8RSEL0 0x01
7407 #define _T8RST_RSEL1 0x02
7408 #define _T8RST_T8RSEL1 0x02
7409 #define _T8RST_RSEL2 0x04
7410 #define _T8RST_T8RSEL2 0x04
7411 #define _T8RST_RSEL3 0x08
7412 #define _T8RST_T8RSEL3 0x08
7413 #define _T8RST_RSEL4 0x10
7414 #define _T8RST_T8RSEL4 0x10
7416 //==============================================================================
7418 extern __at(0x050F) __sfr OPA1NCHS
;
7419 extern __at(0x0510) __sfr OPA1PCHS
;
7421 //==============================================================================
7424 extern __at(0x0511) __sfr OPA1CON
;
7442 unsigned OPA1ORM0
: 1;
7443 unsigned OPA1ORM1
: 1;
7444 unsigned OPA1ORPOL
: 1;
7446 unsigned OPA1UG
: 1;
7449 unsigned OPA1EN
: 1;
7454 unsigned OPA1ORM
: 2;
7465 extern __at(0x0511) volatile __OPA1CONbits_t OPA1CONbits
;
7467 #define _OPA1CON_ORM0 0x01
7468 #define _OPA1CON_OPA1ORM0 0x01
7469 #define _OPA1CON_ORM1 0x02
7470 #define _OPA1CON_OPA1ORM1 0x02
7471 #define _OPA1CON_ORPOL 0x04
7472 #define _OPA1CON_OPA1ORPOL 0x04
7473 #define _OPA1CON_UG 0x10
7474 #define _OPA1CON_OPA1UG 0x10
7475 #define _OPA1CON_EN 0x80
7476 #define _OPA1CON_OPA1EN 0x80
7478 //==============================================================================
7480 extern __at(0x0512) __sfr OPA1ORS
;
7481 extern __at(0x0513) __sfr OPA2NCHS
;
7482 extern __at(0x0514) __sfr OPA2PCHS
;
7484 //==============================================================================
7487 extern __at(0x0515) __sfr OPA2CON
;
7505 unsigned OPA2ORM0
: 1;
7506 unsigned OPA2ORM1
: 1;
7507 unsigned OPA2ORPOL
: 1;
7509 unsigned OPA2UG
: 1;
7512 unsigned OPA2EN
: 1;
7517 unsigned OPA2ORM
: 2;
7528 extern __at(0x0515) volatile __OPA2CONbits_t OPA2CONbits
;
7530 #define _OPA2CON_ORM0 0x01
7531 #define _OPA2CON_OPA2ORM0 0x01
7532 #define _OPA2CON_ORM1 0x02
7533 #define _OPA2CON_OPA2ORM1 0x02
7534 #define _OPA2CON_ORPOL 0x04
7535 #define _OPA2CON_OPA2ORPOL 0x04
7536 #define _OPA2CON_UG 0x10
7537 #define _OPA2CON_OPA2UG 0x10
7538 #define _OPA2CON_EN 0x80
7539 #define _OPA2CON_OPA2EN 0x80
7541 //==============================================================================
7543 extern __at(0x0516) __sfr OPA2ORS
;
7544 extern __at(0x0517) __sfr OPA3NCHS
;
7545 extern __at(0x0518) __sfr OPA3PCHS
;
7547 //==============================================================================
7550 extern __at(0x0519) __sfr OPA3CON
;
7568 unsigned OPA3ORM0
: 1;
7569 unsigned OPA3ORM1
: 1;
7570 unsigned OPA3ORPOL
: 1;
7572 unsigned OPA3UG
: 1;
7574 unsigned OPA3SP
: 1;
7575 unsigned OPA3EN
: 1;
7586 unsigned OPA3ORM
: 2;
7591 extern __at(0x0519) volatile __OPA3CONbits_t OPA3CONbits
;
7593 #define _OPA3CON_ORM0 0x01
7594 #define _OPA3CON_OPA3ORM0 0x01
7595 #define _OPA3CON_ORM1 0x02
7596 #define _OPA3CON_OPA3ORM1 0x02
7597 #define _OPA3CON_ORPOL 0x04
7598 #define _OPA3CON_OPA3ORPOL 0x04
7599 #define _OPA3CON_UG 0x10
7600 #define _OPA3CON_OPA3UG 0x10
7601 #define _OPA3CON_SP 0x40
7602 #define _OPA3CON_OPA3SP 0x40
7603 #define _OPA3CON_EN 0x80
7604 #define _OPA3CON_OPA3EN 0x80
7606 //==============================================================================
7608 extern __at(0x051A) __sfr OPA3ORS
;
7610 //==============================================================================
7613 extern __at(0x058D) __sfr DACLD
;
7617 unsigned DAC1LD
: 1;
7618 unsigned DAC2LD
: 1;
7621 unsigned DAC5LD
: 1;
7627 extern __at(0x058D) volatile __DACLDbits_t DACLDbits
;
7629 #define _DAC1LD 0x01
7630 #define _DAC2LD 0x02
7631 #define _DAC5LD 0x10
7633 //==============================================================================
7636 //==============================================================================
7639 extern __at(0x058E) __sfr DAC1CON0
;
7657 unsigned DACNSS0
: 1;
7658 unsigned DACNSS1
: 1;
7659 unsigned DACPSS0
: 1;
7660 unsigned DACPSS1
: 1;
7661 unsigned DACOE2
: 1;
7669 unsigned DAC1NSS0
: 1;
7670 unsigned DAC1NSS1
: 1;
7671 unsigned DAC1PSS0
: 1;
7672 unsigned DAC1PSS1
: 1;
7673 unsigned DAC1OE2
: 1;
7674 unsigned DACOE1
: 1;
7675 unsigned DAC1FM
: 1;
7676 unsigned DAC1EN
: 1;
7698 unsigned DAC1OE1
: 1;
7705 unsigned DAC1NSS
: 2;
7711 unsigned DACNSS
: 2;
7724 unsigned DACPSS
: 2;
7738 unsigned DAC1PSS
: 2;
7743 extern __at(0x058E) volatile __DAC1CON0bits_t DAC1CON0bits
;
7745 #define _DAC1CON0_NSS0 0x01
7746 #define _DAC1CON0_DACNSS0 0x01
7747 #define _DAC1CON0_DAC1NSS0 0x01
7748 #define _DAC1CON0_NSS1 0x02
7749 #define _DAC1CON0_DACNSS1 0x02
7750 #define _DAC1CON0_DAC1NSS1 0x02
7751 #define _DAC1CON0_PSS0 0x04
7752 #define _DAC1CON0_DACPSS0 0x04
7753 #define _DAC1CON0_DAC1PSS0 0x04
7754 #define _DAC1CON0_PSS1 0x08
7755 #define _DAC1CON0_DACPSS1 0x08
7756 #define _DAC1CON0_DAC1PSS1 0x08
7757 #define _DAC1CON0_OE2 0x10
7758 #define _DAC1CON0_DACOE2 0x10
7759 #define _DAC1CON0_DAC1OE2 0x10
7760 #define _DAC1CON0_OE1 0x20
7761 #define _DAC1CON0_OE 0x20
7762 #define _DAC1CON0_DACOE1 0x20
7763 #define _DAC1CON0_DACOE 0x20
7764 #define _DAC1CON0_DAC1OE1 0x20
7765 #define _DAC1CON0_FM 0x40
7766 #define _DAC1CON0_DACFM 0x40
7767 #define _DAC1CON0_DAC1FM 0x40
7768 #define _DAC1CON0_EN 0x80
7769 #define _DAC1CON0_DACEN 0x80
7770 #define _DAC1CON0_DAC1EN 0x80
7772 //==============================================================================
7775 //==============================================================================
7778 extern __at(0x058F) __sfr DAC1CON1
;
7796 unsigned DAC1REF0
: 1;
7797 unsigned DAC1REF1
: 1;
7798 unsigned DAC1REF2
: 1;
7799 unsigned DAC1REF3
: 1;
7800 unsigned DAC1REF4
: 1;
7801 unsigned DAC1REF5
: 1;
7802 unsigned DAC1REF6
: 1;
7803 unsigned DAC1REF7
: 1;
7820 unsigned DAC1R0
: 1;
7821 unsigned DAC1R1
: 1;
7822 unsigned DAC1R2
: 1;
7823 unsigned DAC1R3
: 1;
7824 unsigned DAC1R4
: 1;
7825 unsigned DAC1R5
: 1;
7826 unsigned DAC1R6
: 1;
7827 unsigned DAC1R7
: 1;
7831 extern __at(0x058F) volatile __DAC1CON1bits_t DAC1CON1bits
;
7834 #define _DAC1REF0 0x01
7836 #define _DAC1R0 0x01
7838 #define _DAC1REF1 0x02
7840 #define _DAC1R1 0x02
7842 #define _DAC1REF2 0x04
7844 #define _DAC1R2 0x04
7846 #define _DAC1REF3 0x08
7848 #define _DAC1R3 0x08
7850 #define _DAC1REF4 0x10
7852 #define _DAC1R4 0x10
7854 #define _DAC1REF5 0x20
7856 #define _DAC1R5 0x20
7858 #define _DAC1REF6 0x40
7860 #define _DAC1R6 0x40
7862 #define _DAC1REF7 0x80
7864 #define _DAC1R7 0x80
7866 //==============================================================================
7868 extern __at(0x058F) __sfr DAC1REF
;
7870 //==============================================================================
7873 extern __at(0x058F) __sfr DAC1REFL
;
7891 unsigned DAC1REF0
: 1;
7892 unsigned DAC1REF1
: 1;
7893 unsigned DAC1REF2
: 1;
7894 unsigned DAC1REF3
: 1;
7895 unsigned DAC1REF4
: 1;
7896 unsigned DAC1REF5
: 1;
7897 unsigned DAC1REF6
: 1;
7898 unsigned DAC1REF7
: 1;
7915 unsigned DAC1R0
: 1;
7916 unsigned DAC1R1
: 1;
7917 unsigned DAC1R2
: 1;
7918 unsigned DAC1R3
: 1;
7919 unsigned DAC1R4
: 1;
7920 unsigned DAC1R5
: 1;
7921 unsigned DAC1R6
: 1;
7922 unsigned DAC1R7
: 1;
7926 extern __at(0x058F) volatile __DAC1REFLbits_t DAC1REFLbits
;
7928 #define _DAC1REFL_REF0 0x01
7929 #define _DAC1REFL_DAC1REF0 0x01
7930 #define _DAC1REFL_R0 0x01
7931 #define _DAC1REFL_DAC1R0 0x01
7932 #define _DAC1REFL_REF1 0x02
7933 #define _DAC1REFL_DAC1REF1 0x02
7934 #define _DAC1REFL_R1 0x02
7935 #define _DAC1REFL_DAC1R1 0x02
7936 #define _DAC1REFL_REF2 0x04
7937 #define _DAC1REFL_DAC1REF2 0x04
7938 #define _DAC1REFL_R2 0x04
7939 #define _DAC1REFL_DAC1R2 0x04
7940 #define _DAC1REFL_REF3 0x08
7941 #define _DAC1REFL_DAC1REF3 0x08
7942 #define _DAC1REFL_R3 0x08
7943 #define _DAC1REFL_DAC1R3 0x08
7944 #define _DAC1REFL_REF4 0x10
7945 #define _DAC1REFL_DAC1REF4 0x10
7946 #define _DAC1REFL_R4 0x10
7947 #define _DAC1REFL_DAC1R4 0x10
7948 #define _DAC1REFL_REF5 0x20
7949 #define _DAC1REFL_DAC1REF5 0x20
7950 #define _DAC1REFL_R5 0x20
7951 #define _DAC1REFL_DAC1R5 0x20
7952 #define _DAC1REFL_REF6 0x40
7953 #define _DAC1REFL_DAC1REF6 0x40
7954 #define _DAC1REFL_R6 0x40
7955 #define _DAC1REFL_DAC1R6 0x40
7956 #define _DAC1REFL_REF7 0x80
7957 #define _DAC1REFL_DAC1REF7 0x80
7958 #define _DAC1REFL_R7 0x80
7959 #define _DAC1REFL_DAC1R7 0x80
7961 //==============================================================================
7964 //==============================================================================
7967 extern __at(0x0590) __sfr DAC1CON2
;
7985 unsigned DAC1REF8
: 1;
7986 unsigned DAC1REF9
: 1;
7987 unsigned DAC1REF10
: 1;
7988 unsigned DAC1REF11
: 1;
7989 unsigned DAC1REF12
: 1;
7990 unsigned DAC1REF13
: 1;
7991 unsigned DAC1REF14
: 1;
7992 unsigned DAC1REF15
: 1;
8009 unsigned DAC1R8
: 1;
8010 unsigned DAC1R9
: 1;
8011 unsigned DAC1R10
: 1;
8012 unsigned DAC1R11
: 1;
8013 unsigned DAC1R12
: 1;
8014 unsigned DAC1R13
: 1;
8015 unsigned DAC1R14
: 1;
8016 unsigned DAC1R15
: 1;
8020 extern __at(0x0590) volatile __DAC1CON2bits_t DAC1CON2bits
;
8023 #define _DAC1REF8 0x01
8025 #define _DAC1R8 0x01
8027 #define _DAC1REF9 0x02
8029 #define _DAC1R9 0x02
8031 #define _DAC1REF10 0x04
8033 #define _DAC1R10 0x04
8035 #define _DAC1REF11 0x08
8037 #define _DAC1R11 0x08
8039 #define _DAC1REF12 0x10
8041 #define _DAC1R12 0x10
8043 #define _DAC1REF13 0x20
8045 #define _DAC1R13 0x20
8047 #define _DAC1REF14 0x40
8049 #define _DAC1R14 0x40
8051 #define _DAC1REF15 0x80
8053 #define _DAC1R15 0x80
8055 //==============================================================================
8058 //==============================================================================
8061 extern __at(0x0590) __sfr DAC1REFH
;
8079 unsigned DAC1REF8
: 1;
8080 unsigned DAC1REF9
: 1;
8081 unsigned DAC1REF10
: 1;
8082 unsigned DAC1REF11
: 1;
8083 unsigned DAC1REF12
: 1;
8084 unsigned DAC1REF13
: 1;
8085 unsigned DAC1REF14
: 1;
8086 unsigned DAC1REF15
: 1;
8103 unsigned DAC1R8
: 1;
8104 unsigned DAC1R9
: 1;
8105 unsigned DAC1R10
: 1;
8106 unsigned DAC1R11
: 1;
8107 unsigned DAC1R12
: 1;
8108 unsigned DAC1R13
: 1;
8109 unsigned DAC1R14
: 1;
8110 unsigned DAC1R15
: 1;
8114 extern __at(0x0590) volatile __DAC1REFHbits_t DAC1REFHbits
;
8116 #define _DAC1REFH_REF8 0x01
8117 #define _DAC1REFH_DAC1REF8 0x01
8118 #define _DAC1REFH_R8 0x01
8119 #define _DAC1REFH_DAC1R8 0x01
8120 #define _DAC1REFH_REF9 0x02
8121 #define _DAC1REFH_DAC1REF9 0x02
8122 #define _DAC1REFH_R9 0x02
8123 #define _DAC1REFH_DAC1R9 0x02
8124 #define _DAC1REFH_REF10 0x04
8125 #define _DAC1REFH_DAC1REF10 0x04
8126 #define _DAC1REFH_R10 0x04
8127 #define _DAC1REFH_DAC1R10 0x04
8128 #define _DAC1REFH_REF11 0x08
8129 #define _DAC1REFH_DAC1REF11 0x08
8130 #define _DAC1REFH_R11 0x08
8131 #define _DAC1REFH_DAC1R11 0x08
8132 #define _DAC1REFH_REF12 0x10
8133 #define _DAC1REFH_DAC1REF12 0x10
8134 #define _DAC1REFH_R12 0x10
8135 #define _DAC1REFH_DAC1R12 0x10
8136 #define _DAC1REFH_REF13 0x20
8137 #define _DAC1REFH_DAC1REF13 0x20
8138 #define _DAC1REFH_R13 0x20
8139 #define _DAC1REFH_DAC1R13 0x20
8140 #define _DAC1REFH_REF14 0x40
8141 #define _DAC1REFH_DAC1REF14 0x40
8142 #define _DAC1REFH_R14 0x40
8143 #define _DAC1REFH_DAC1R14 0x40
8144 #define _DAC1REFH_REF15 0x80
8145 #define _DAC1REFH_DAC1REF15 0x80
8146 #define _DAC1REFH_R15 0x80
8147 #define _DAC1REFH_DAC1R15 0x80
8149 //==============================================================================
8152 //==============================================================================
8155 extern __at(0x0591) __sfr DAC2CON0
;
8173 unsigned DACNSS0
: 1;
8174 unsigned DACNSS1
: 1;
8175 unsigned DACPSS0
: 1;
8176 unsigned DACPSS1
: 1;
8177 unsigned DACOE2
: 1;
8185 unsigned DAC2NSS0
: 1;
8186 unsigned DAC2NSS1
: 1;
8187 unsigned DAC2PSS0
: 1;
8188 unsigned DAC2PSS1
: 1;
8189 unsigned DAC2OE2
: 1;
8190 unsigned DACOE1
: 1;
8191 unsigned DAC2FM
: 1;
8192 unsigned DAC2EN
: 1;
8214 unsigned DAC2OE1
: 1;
8221 unsigned DAC2NSS
: 2;
8233 unsigned DACNSS
: 2;
8240 unsigned DAC2PSS
: 2;
8254 unsigned DACPSS
: 2;
8259 extern __at(0x0591) volatile __DAC2CON0bits_t DAC2CON0bits
;
8261 #define _DAC2CON0_NSS0 0x01
8262 #define _DAC2CON0_DACNSS0 0x01
8263 #define _DAC2CON0_DAC2NSS0 0x01
8264 #define _DAC2CON0_NSS1 0x02
8265 #define _DAC2CON0_DACNSS1 0x02
8266 #define _DAC2CON0_DAC2NSS1 0x02
8267 #define _DAC2CON0_PSS0 0x04
8268 #define _DAC2CON0_DACPSS0 0x04
8269 #define _DAC2CON0_DAC2PSS0 0x04
8270 #define _DAC2CON0_PSS1 0x08
8271 #define _DAC2CON0_DACPSS1 0x08
8272 #define _DAC2CON0_DAC2PSS1 0x08
8273 #define _DAC2CON0_OE2 0x10
8274 #define _DAC2CON0_DACOE2 0x10
8275 #define _DAC2CON0_DAC2OE2 0x10
8276 #define _DAC2CON0_OE1 0x20
8277 #define _DAC2CON0_OE 0x20
8278 #define _DAC2CON0_DACOE1 0x20
8279 #define _DAC2CON0_DACOE 0x20
8280 #define _DAC2CON0_DAC2OE1 0x20
8281 #define _DAC2CON0_FM 0x40
8282 #define _DAC2CON0_DACFM 0x40
8283 #define _DAC2CON0_DAC2FM 0x40
8284 #define _DAC2CON0_EN 0x80
8285 #define _DAC2CON0_DACEN 0x80
8286 #define _DAC2CON0_DAC2EN 0x80
8288 //==============================================================================
8291 //==============================================================================
8294 extern __at(0x0592) __sfr DAC2CON1
;
8312 unsigned DAC2REF0
: 1;
8313 unsigned DAC2REF1
: 1;
8314 unsigned DAC2REF2
: 1;
8315 unsigned DAC2REF3
: 1;
8316 unsigned DAC2REF4
: 1;
8317 unsigned DAC2REF5
: 1;
8318 unsigned DAC2REF6
: 1;
8319 unsigned DAC2REF7
: 1;
8336 unsigned DAC2R0
: 1;
8337 unsigned DAC2R1
: 1;
8338 unsigned DAC2R2
: 1;
8339 unsigned DAC2R3
: 1;
8340 unsigned DAC2R4
: 1;
8341 unsigned DAC2R5
: 1;
8342 unsigned DAC2R6
: 1;
8343 unsigned DAC2R7
: 1;
8347 extern __at(0x0592) volatile __DAC2CON1bits_t DAC2CON1bits
;
8349 #define _DAC2CON1_REF0 0x01
8350 #define _DAC2CON1_DAC2REF0 0x01
8351 #define _DAC2CON1_R0 0x01
8352 #define _DAC2CON1_DAC2R0 0x01
8353 #define _DAC2CON1_REF1 0x02
8354 #define _DAC2CON1_DAC2REF1 0x02
8355 #define _DAC2CON1_R1 0x02
8356 #define _DAC2CON1_DAC2R1 0x02
8357 #define _DAC2CON1_REF2 0x04
8358 #define _DAC2CON1_DAC2REF2 0x04
8359 #define _DAC2CON1_R2 0x04
8360 #define _DAC2CON1_DAC2R2 0x04
8361 #define _DAC2CON1_REF3 0x08
8362 #define _DAC2CON1_DAC2REF3 0x08
8363 #define _DAC2CON1_R3 0x08
8364 #define _DAC2CON1_DAC2R3 0x08
8365 #define _DAC2CON1_REF4 0x10
8366 #define _DAC2CON1_DAC2REF4 0x10
8367 #define _DAC2CON1_R4 0x10
8368 #define _DAC2CON1_DAC2R4 0x10
8369 #define _DAC2CON1_REF5 0x20
8370 #define _DAC2CON1_DAC2REF5 0x20
8371 #define _DAC2CON1_R5 0x20
8372 #define _DAC2CON1_DAC2R5 0x20
8373 #define _DAC2CON1_REF6 0x40
8374 #define _DAC2CON1_DAC2REF6 0x40
8375 #define _DAC2CON1_R6 0x40
8376 #define _DAC2CON1_DAC2R6 0x40
8377 #define _DAC2CON1_REF7 0x80
8378 #define _DAC2CON1_DAC2REF7 0x80
8379 #define _DAC2CON1_R7 0x80
8380 #define _DAC2CON1_DAC2R7 0x80
8382 //==============================================================================
8384 extern __at(0x0592) __sfr DAC2REF
;
8386 //==============================================================================
8389 extern __at(0x0592) __sfr DAC2REFL
;
8407 unsigned DAC2REF0
: 1;
8408 unsigned DAC2REF1
: 1;
8409 unsigned DAC2REF2
: 1;
8410 unsigned DAC2REF3
: 1;
8411 unsigned DAC2REF4
: 1;
8412 unsigned DAC2REF5
: 1;
8413 unsigned DAC2REF6
: 1;
8414 unsigned DAC2REF7
: 1;
8431 unsigned DAC2R0
: 1;
8432 unsigned DAC2R1
: 1;
8433 unsigned DAC2R2
: 1;
8434 unsigned DAC2R3
: 1;
8435 unsigned DAC2R4
: 1;
8436 unsigned DAC2R5
: 1;
8437 unsigned DAC2R6
: 1;
8438 unsigned DAC2R7
: 1;
8442 extern __at(0x0592) volatile __DAC2REFLbits_t DAC2REFLbits
;
8444 #define _DAC2REFL_REF0 0x01
8445 #define _DAC2REFL_DAC2REF0 0x01
8446 #define _DAC2REFL_R0 0x01
8447 #define _DAC2REFL_DAC2R0 0x01
8448 #define _DAC2REFL_REF1 0x02
8449 #define _DAC2REFL_DAC2REF1 0x02
8450 #define _DAC2REFL_R1 0x02
8451 #define _DAC2REFL_DAC2R1 0x02
8452 #define _DAC2REFL_REF2 0x04
8453 #define _DAC2REFL_DAC2REF2 0x04
8454 #define _DAC2REFL_R2 0x04
8455 #define _DAC2REFL_DAC2R2 0x04
8456 #define _DAC2REFL_REF3 0x08
8457 #define _DAC2REFL_DAC2REF3 0x08
8458 #define _DAC2REFL_R3 0x08
8459 #define _DAC2REFL_DAC2R3 0x08
8460 #define _DAC2REFL_REF4 0x10
8461 #define _DAC2REFL_DAC2REF4 0x10
8462 #define _DAC2REFL_R4 0x10
8463 #define _DAC2REFL_DAC2R4 0x10
8464 #define _DAC2REFL_REF5 0x20
8465 #define _DAC2REFL_DAC2REF5 0x20
8466 #define _DAC2REFL_R5 0x20
8467 #define _DAC2REFL_DAC2R5 0x20
8468 #define _DAC2REFL_REF6 0x40
8469 #define _DAC2REFL_DAC2REF6 0x40
8470 #define _DAC2REFL_R6 0x40
8471 #define _DAC2REFL_DAC2R6 0x40
8472 #define _DAC2REFL_REF7 0x80
8473 #define _DAC2REFL_DAC2REF7 0x80
8474 #define _DAC2REFL_R7 0x80
8475 #define _DAC2REFL_DAC2R7 0x80
8477 //==============================================================================
8480 //==============================================================================
8483 extern __at(0x0593) __sfr DAC2CON2
;
8501 unsigned DAC2REF8
: 1;
8502 unsigned DAC2REF9
: 1;
8503 unsigned DAC2REF10
: 1;
8504 unsigned DAC2REF11
: 1;
8505 unsigned DAC2REF12
: 1;
8506 unsigned DAC2REF13
: 1;
8507 unsigned DAC2REF14
: 1;
8508 unsigned DAC2REF15
: 1;
8525 unsigned DAC2R8
: 1;
8526 unsigned DAC2R9
: 1;
8527 unsigned DAC2R10
: 1;
8528 unsigned DAC2R11
: 1;
8529 unsigned DAC2R12
: 1;
8530 unsigned DAC2R13
: 1;
8531 unsigned DAC2R14
: 1;
8532 unsigned DAC2R15
: 1;
8536 extern __at(0x0593) volatile __DAC2CON2bits_t DAC2CON2bits
;
8538 #define _DAC2CON2_REF8 0x01
8539 #define _DAC2CON2_DAC2REF8 0x01
8540 #define _DAC2CON2_R8 0x01
8541 #define _DAC2CON2_DAC2R8 0x01
8542 #define _DAC2CON2_REF9 0x02
8543 #define _DAC2CON2_DAC2REF9 0x02
8544 #define _DAC2CON2_R9 0x02
8545 #define _DAC2CON2_DAC2R9 0x02
8546 #define _DAC2CON2_REF10 0x04
8547 #define _DAC2CON2_DAC2REF10 0x04
8548 #define _DAC2CON2_R10 0x04
8549 #define _DAC2CON2_DAC2R10 0x04
8550 #define _DAC2CON2_REF11 0x08
8551 #define _DAC2CON2_DAC2REF11 0x08
8552 #define _DAC2CON2_R11 0x08
8553 #define _DAC2CON2_DAC2R11 0x08
8554 #define _DAC2CON2_REF12 0x10
8555 #define _DAC2CON2_DAC2REF12 0x10
8556 #define _DAC2CON2_R12 0x10
8557 #define _DAC2CON2_DAC2R12 0x10
8558 #define _DAC2CON2_REF13 0x20
8559 #define _DAC2CON2_DAC2REF13 0x20
8560 #define _DAC2CON2_R13 0x20
8561 #define _DAC2CON2_DAC2R13 0x20
8562 #define _DAC2CON2_REF14 0x40
8563 #define _DAC2CON2_DAC2REF14 0x40
8564 #define _DAC2CON2_R14 0x40
8565 #define _DAC2CON2_DAC2R14 0x40
8566 #define _DAC2CON2_REF15 0x80
8567 #define _DAC2CON2_DAC2REF15 0x80
8568 #define _DAC2CON2_R15 0x80
8569 #define _DAC2CON2_DAC2R15 0x80
8571 //==============================================================================
8574 //==============================================================================
8577 extern __at(0x0593) __sfr DAC2REFH
;
8595 unsigned DAC2REF8
: 1;
8596 unsigned DAC2REF9
: 1;
8597 unsigned DAC2REF10
: 1;
8598 unsigned DAC2REF11
: 1;
8599 unsigned DAC2REF12
: 1;
8600 unsigned DAC2REF13
: 1;
8601 unsigned DAC2REF14
: 1;
8602 unsigned DAC2REF15
: 1;
8619 unsigned DAC2R8
: 1;
8620 unsigned DAC2R9
: 1;
8621 unsigned DAC2R10
: 1;
8622 unsigned DAC2R11
: 1;
8623 unsigned DAC2R12
: 1;
8624 unsigned DAC2R13
: 1;
8625 unsigned DAC2R14
: 1;
8626 unsigned DAC2R15
: 1;
8630 extern __at(0x0593) volatile __DAC2REFHbits_t DAC2REFHbits
;
8632 #define _DAC2REFH_REF8 0x01
8633 #define _DAC2REFH_DAC2REF8 0x01
8634 #define _DAC2REFH_R8 0x01
8635 #define _DAC2REFH_DAC2R8 0x01
8636 #define _DAC2REFH_REF9 0x02
8637 #define _DAC2REFH_DAC2REF9 0x02
8638 #define _DAC2REFH_R9 0x02
8639 #define _DAC2REFH_DAC2R9 0x02
8640 #define _DAC2REFH_REF10 0x04
8641 #define _DAC2REFH_DAC2REF10 0x04
8642 #define _DAC2REFH_R10 0x04
8643 #define _DAC2REFH_DAC2R10 0x04
8644 #define _DAC2REFH_REF11 0x08
8645 #define _DAC2REFH_DAC2REF11 0x08
8646 #define _DAC2REFH_R11 0x08
8647 #define _DAC2REFH_DAC2R11 0x08
8648 #define _DAC2REFH_REF12 0x10
8649 #define _DAC2REFH_DAC2REF12 0x10
8650 #define _DAC2REFH_R12 0x10
8651 #define _DAC2REFH_DAC2R12 0x10
8652 #define _DAC2REFH_REF13 0x20
8653 #define _DAC2REFH_DAC2REF13 0x20
8654 #define _DAC2REFH_R13 0x20
8655 #define _DAC2REFH_DAC2R13 0x20
8656 #define _DAC2REFH_REF14 0x40
8657 #define _DAC2REFH_DAC2REF14 0x40
8658 #define _DAC2REFH_R14 0x40
8659 #define _DAC2REFH_DAC2R14 0x40
8660 #define _DAC2REFH_REF15 0x80
8661 #define _DAC2REFH_DAC2REF15 0x80
8662 #define _DAC2REFH_R15 0x80
8663 #define _DAC2REFH_DAC2R15 0x80
8665 //==============================================================================
8668 //==============================================================================
8671 extern __at(0x0594) __sfr DAC3CON0
;
8689 unsigned DACNSS0
: 1;
8690 unsigned DACNSS1
: 1;
8691 unsigned DACPSS0
: 1;
8692 unsigned DACPSS1
: 1;
8693 unsigned DACOE2
: 1;
8694 unsigned DACOE1
: 1;
8701 unsigned DAC3NSS0
: 1;
8702 unsigned DAC3NSS1
: 1;
8703 unsigned DAC3PSS0
: 1;
8704 unsigned DAC3PSS1
: 1;
8705 unsigned DAC3OE2
: 1;
8706 unsigned DAC3OE1
: 1;
8708 unsigned DAC3EN
: 1;
8713 unsigned DAC3NSS
: 2;
8725 unsigned DACNSS
: 2;
8732 unsigned DAC3PSS
: 2;
8739 unsigned DACPSS
: 2;
8751 extern __at(0x0594) volatile __DAC3CON0bits_t DAC3CON0bits
;
8753 #define _DAC3CON0_NSS0 0x01
8754 #define _DAC3CON0_DACNSS0 0x01
8755 #define _DAC3CON0_DAC3NSS0 0x01
8756 #define _DAC3CON0_NSS1 0x02
8757 #define _DAC3CON0_DACNSS1 0x02
8758 #define _DAC3CON0_DAC3NSS1 0x02
8759 #define _DAC3CON0_PSS0 0x04
8760 #define _DAC3CON0_DACPSS0 0x04
8761 #define _DAC3CON0_DAC3PSS0 0x04
8762 #define _DAC3CON0_PSS1 0x08
8763 #define _DAC3CON0_DACPSS1 0x08
8764 #define _DAC3CON0_DAC3PSS1 0x08
8765 #define _DAC3CON0_OE2 0x10
8766 #define _DAC3CON0_DACOE2 0x10
8767 #define _DAC3CON0_DAC3OE2 0x10
8768 #define _DAC3CON0_OE1 0x20
8769 #define _DAC3CON0_DACOE1 0x20
8770 #define _DAC3CON0_DAC3OE1 0x20
8771 #define _DAC3CON0_EN 0x80
8772 #define _DAC3CON0_DACEN 0x80
8773 #define _DAC3CON0_DAC3EN 0x80
8775 //==============================================================================
8778 //==============================================================================
8781 extern __at(0x0595) __sfr DAC3CON1
;
8811 unsigned DAC3R0
: 1;
8812 unsigned DAC3R1
: 1;
8813 unsigned DAC3R2
: 1;
8814 unsigned DAC3R3
: 1;
8815 unsigned DAC3R4
: 1;
8835 unsigned DAC3REF0
: 1;
8836 unsigned DAC3REF1
: 1;
8837 unsigned DAC3REF2
: 1;
8838 unsigned DAC3REF3
: 1;
8839 unsigned DAC3REF4
: 1;
8865 unsigned DAC3REF
: 5;
8876 extern __at(0x0595) volatile __DAC3CON1bits_t DAC3CON1bits
;
8878 #define _DAC3CON1_DACR0 0x01
8879 #define _DAC3CON1_R0 0x01
8880 #define _DAC3CON1_DAC3R0 0x01
8881 #define _DAC3CON1_REF0 0x01
8882 #define _DAC3CON1_DAC3REF0 0x01
8883 #define _DAC3CON1_DACR1 0x02
8884 #define _DAC3CON1_R1 0x02
8885 #define _DAC3CON1_DAC3R1 0x02
8886 #define _DAC3CON1_REF1 0x02
8887 #define _DAC3CON1_DAC3REF1 0x02
8888 #define _DAC3CON1_DACR2 0x04
8889 #define _DAC3CON1_R2 0x04
8890 #define _DAC3CON1_DAC3R2 0x04
8891 #define _DAC3CON1_REF2 0x04
8892 #define _DAC3CON1_DAC3REF2 0x04
8893 #define _DAC3CON1_DACR3 0x08
8894 #define _DAC3CON1_R3 0x08
8895 #define _DAC3CON1_DAC3R3 0x08
8896 #define _DAC3CON1_REF3 0x08
8897 #define _DAC3CON1_DAC3REF3 0x08
8898 #define _DAC3CON1_DACR4 0x10
8899 #define _DAC3CON1_R4 0x10
8900 #define _DAC3CON1_DAC3R4 0x10
8901 #define _DAC3CON1_REF4 0x10
8902 #define _DAC3CON1_DAC3REF4 0x10
8904 //==============================================================================
8907 //==============================================================================
8910 extern __at(0x0595) __sfr DAC3REF
;
8940 unsigned DAC3R0
: 1;
8941 unsigned DAC3R1
: 1;
8942 unsigned DAC3R2
: 1;
8943 unsigned DAC3R3
: 1;
8944 unsigned DAC3R4
: 1;
8964 unsigned DAC3REF0
: 1;
8965 unsigned DAC3REF1
: 1;
8966 unsigned DAC3REF2
: 1;
8967 unsigned DAC3REF3
: 1;
8968 unsigned DAC3REF4
: 1;
8982 unsigned DAC3REF
: 5;
9005 extern __at(0x0595) volatile __DAC3REFbits_t DAC3REFbits
;
9007 #define _DAC3REF_DACR0 0x01
9008 #define _DAC3REF_R0 0x01
9009 #define _DAC3REF_DAC3R0 0x01
9010 #define _DAC3REF_REF0 0x01
9011 #define _DAC3REF_DAC3REF0 0x01
9012 #define _DAC3REF_DACR1 0x02
9013 #define _DAC3REF_R1 0x02
9014 #define _DAC3REF_DAC3R1 0x02
9015 #define _DAC3REF_REF1 0x02
9016 #define _DAC3REF_DAC3REF1 0x02
9017 #define _DAC3REF_DACR2 0x04
9018 #define _DAC3REF_R2 0x04
9019 #define _DAC3REF_DAC3R2 0x04
9020 #define _DAC3REF_REF2 0x04
9021 #define _DAC3REF_DAC3REF2 0x04
9022 #define _DAC3REF_DACR3 0x08
9023 #define _DAC3REF_R3 0x08
9024 #define _DAC3REF_DAC3R3 0x08
9025 #define _DAC3REF_REF3 0x08
9026 #define _DAC3REF_DAC3REF3 0x08
9027 #define _DAC3REF_DACR4 0x10
9028 #define _DAC3REF_R4 0x10
9029 #define _DAC3REF_DAC3R4 0x10
9030 #define _DAC3REF_REF4 0x10
9031 #define _DAC3REF_DAC3REF4 0x10
9033 //==============================================================================
9036 //==============================================================================
9039 extern __at(0x0596) __sfr DAC4CON0
;
9057 unsigned DACNSS0
: 1;
9058 unsigned DACNSS1
: 1;
9059 unsigned DACPSS0
: 1;
9060 unsigned DACPSS1
: 1;
9061 unsigned DACOE2
: 1;
9062 unsigned DACOE1
: 1;
9069 unsigned DAC4NSS0
: 1;
9070 unsigned DAC4NSS1
: 1;
9071 unsigned DAC4PSS0
: 1;
9072 unsigned DAC4PSS1
: 1;
9073 unsigned DAC4OE2
: 1;
9074 unsigned DAC4OE1
: 1;
9076 unsigned DAC4EN
: 1;
9087 unsigned DACNSS
: 2;
9093 unsigned DAC4NSS
: 2;
9100 unsigned DAC4PSS
: 2;
9114 unsigned DACPSS
: 2;
9119 extern __at(0x0596) volatile __DAC4CON0bits_t DAC4CON0bits
;
9121 #define _DAC4CON0_NSS0 0x01
9122 #define _DAC4CON0_DACNSS0 0x01
9123 #define _DAC4CON0_DAC4NSS0 0x01
9124 #define _DAC4CON0_NSS1 0x02
9125 #define _DAC4CON0_DACNSS1 0x02
9126 #define _DAC4CON0_DAC4NSS1 0x02
9127 #define _DAC4CON0_PSS0 0x04
9128 #define _DAC4CON0_DACPSS0 0x04
9129 #define _DAC4CON0_DAC4PSS0 0x04
9130 #define _DAC4CON0_PSS1 0x08
9131 #define _DAC4CON0_DACPSS1 0x08
9132 #define _DAC4CON0_DAC4PSS1 0x08
9133 #define _DAC4CON0_OE2 0x10
9134 #define _DAC4CON0_DACOE2 0x10
9135 #define _DAC4CON0_DAC4OE2 0x10
9136 #define _DAC4CON0_OE1 0x20
9137 #define _DAC4CON0_DACOE1 0x20
9138 #define _DAC4CON0_DAC4OE1 0x20
9139 #define _DAC4CON0_EN 0x80
9140 #define _DAC4CON0_DACEN 0x80
9141 #define _DAC4CON0_DAC4EN 0x80
9143 //==============================================================================
9146 //==============================================================================
9149 extern __at(0x0597) __sfr DAC4CON1
;
9179 unsigned DAC4R0
: 1;
9180 unsigned DAC4R1
: 1;
9181 unsigned DAC4R2
: 1;
9182 unsigned DAC4R3
: 1;
9183 unsigned DAC4R4
: 1;
9203 unsigned DAC4REF0
: 1;
9204 unsigned DAC4REF1
: 1;
9205 unsigned DAC4REF2
: 1;
9206 unsigned DAC4REF3
: 1;
9207 unsigned DAC4REF4
: 1;
9215 unsigned DAC4REF
: 5;
9244 extern __at(0x0597) volatile __DAC4CON1bits_t DAC4CON1bits
;
9246 #define _DAC4CON1_DACR0 0x01
9247 #define _DAC4CON1_R0 0x01
9248 #define _DAC4CON1_DAC4R0 0x01
9249 #define _DAC4CON1_REF0 0x01
9250 #define _DAC4CON1_DAC4REF0 0x01
9251 #define _DAC4CON1_DACR1 0x02
9252 #define _DAC4CON1_R1 0x02
9253 #define _DAC4CON1_DAC4R1 0x02
9254 #define _DAC4CON1_REF1 0x02
9255 #define _DAC4CON1_DAC4REF1 0x02
9256 #define _DAC4CON1_DACR2 0x04
9257 #define _DAC4CON1_R2 0x04
9258 #define _DAC4CON1_DAC4R2 0x04
9259 #define _DAC4CON1_REF2 0x04
9260 #define _DAC4CON1_DAC4REF2 0x04
9261 #define _DAC4CON1_DACR3 0x08
9262 #define _DAC4CON1_R3 0x08
9263 #define _DAC4CON1_DAC4R3 0x08
9264 #define _DAC4CON1_REF3 0x08
9265 #define _DAC4CON1_DAC4REF3 0x08
9266 #define _DAC4CON1_DACR4 0x10
9267 #define _DAC4CON1_R4 0x10
9268 #define _DAC4CON1_DAC4R4 0x10
9269 #define _DAC4CON1_REF4 0x10
9270 #define _DAC4CON1_DAC4REF4 0x10
9272 //==============================================================================
9275 //==============================================================================
9278 extern __at(0x0597) __sfr DAC4REF
;
9308 unsigned DAC4R0
: 1;
9309 unsigned DAC4R1
: 1;
9310 unsigned DAC4R2
: 1;
9311 unsigned DAC4R3
: 1;
9312 unsigned DAC4R4
: 1;
9332 unsigned DAC4REF0
: 1;
9333 unsigned DAC4REF1
: 1;
9334 unsigned DAC4REF2
: 1;
9335 unsigned DAC4REF3
: 1;
9336 unsigned DAC4REF4
: 1;
9356 unsigned DAC4REF
: 5;
9373 extern __at(0x0597) volatile __DAC4REFbits_t DAC4REFbits
;
9375 #define _DAC4REF_DACR0 0x01
9376 #define _DAC4REF_R0 0x01
9377 #define _DAC4REF_DAC4R0 0x01
9378 #define _DAC4REF_REF0 0x01
9379 #define _DAC4REF_DAC4REF0 0x01
9380 #define _DAC4REF_DACR1 0x02
9381 #define _DAC4REF_R1 0x02
9382 #define _DAC4REF_DAC4R1 0x02
9383 #define _DAC4REF_REF1 0x02
9384 #define _DAC4REF_DAC4REF1 0x02
9385 #define _DAC4REF_DACR2 0x04
9386 #define _DAC4REF_R2 0x04
9387 #define _DAC4REF_DAC4R2 0x04
9388 #define _DAC4REF_REF2 0x04
9389 #define _DAC4REF_DAC4REF2 0x04
9390 #define _DAC4REF_DACR3 0x08
9391 #define _DAC4REF_R3 0x08
9392 #define _DAC4REF_DAC4R3 0x08
9393 #define _DAC4REF_REF3 0x08
9394 #define _DAC4REF_DAC4REF3 0x08
9395 #define _DAC4REF_DACR4 0x10
9396 #define _DAC4REF_R4 0x10
9397 #define _DAC4REF_DAC4R4 0x10
9398 #define _DAC4REF_REF4 0x10
9399 #define _DAC4REF_DAC4REF4 0x10
9401 //==============================================================================
9404 //==============================================================================
9407 extern __at(0x0598) __sfr DAC5CON0
;
9425 unsigned DACNSS0
: 1;
9426 unsigned DACNSS1
: 1;
9427 unsigned DACPSS0
: 1;
9428 unsigned DACPSS1
: 1;
9429 unsigned DACOE2
: 1;
9437 unsigned DAC5NSS0
: 1;
9438 unsigned DAC5NSS1
: 1;
9439 unsigned DAC5PSS0
: 1;
9440 unsigned DAC5PSS1
: 1;
9441 unsigned DAC5OE2
: 1;
9442 unsigned DACOE1
: 1;
9443 unsigned DAC5FM
: 1;
9444 unsigned DAC5EN
: 1;
9466 unsigned DAC5OE1
: 1;
9479 unsigned DACNSS
: 2;
9485 unsigned DAC5NSS
: 2;
9492 unsigned DACPSS
: 2;
9499 unsigned DAC5PSS
: 2;
9511 extern __at(0x0598) volatile __DAC5CON0bits_t DAC5CON0bits
;
9513 #define _DAC5CON0_NSS0 0x01
9514 #define _DAC5CON0_DACNSS0 0x01
9515 #define _DAC5CON0_DAC5NSS0 0x01
9516 #define _DAC5CON0_NSS1 0x02
9517 #define _DAC5CON0_DACNSS1 0x02
9518 #define _DAC5CON0_DAC5NSS1 0x02
9519 #define _DAC5CON0_PSS0 0x04
9520 #define _DAC5CON0_DACPSS0 0x04
9521 #define _DAC5CON0_DAC5PSS0 0x04
9522 #define _DAC5CON0_PSS1 0x08
9523 #define _DAC5CON0_DACPSS1 0x08
9524 #define _DAC5CON0_DAC5PSS1 0x08
9525 #define _DAC5CON0_OE2 0x10
9526 #define _DAC5CON0_DACOE2 0x10
9527 #define _DAC5CON0_DAC5OE2 0x10
9528 #define _DAC5CON0_OE1 0x20
9529 #define _DAC5CON0_OE 0x20
9530 #define _DAC5CON0_DACOE1 0x20
9531 #define _DAC5CON0_DACOE 0x20
9532 #define _DAC5CON0_DAC5OE1 0x20
9533 #define _DAC5CON0_FM 0x40
9534 #define _DAC5CON0_DACFM 0x40
9535 #define _DAC5CON0_DAC5FM 0x40
9536 #define _DAC5CON0_EN 0x80
9537 #define _DAC5CON0_DACEN 0x80
9538 #define _DAC5CON0_DAC5EN 0x80
9540 //==============================================================================
9543 //==============================================================================
9546 extern __at(0x0599) __sfr DAC5CON1
;
9564 unsigned DAC5REF0
: 1;
9565 unsigned DAC5REF1
: 1;
9566 unsigned DAC5REF2
: 1;
9567 unsigned DAC5REF3
: 1;
9568 unsigned DAC5REF4
: 1;
9569 unsigned DAC5REF5
: 1;
9570 unsigned DAC5REF6
: 1;
9571 unsigned DAC5REF7
: 1;
9588 unsigned DAC5R0
: 1;
9589 unsigned DAC5R1
: 1;
9590 unsigned DAC5R2
: 1;
9591 unsigned DAC5R3
: 1;
9592 unsigned DAC5R4
: 1;
9593 unsigned DAC5R5
: 1;
9594 unsigned DAC5R6
: 1;
9595 unsigned DAC5R7
: 1;
9599 extern __at(0x0599) volatile __DAC5CON1bits_t DAC5CON1bits
;
9601 #define _DAC5CON1_REF0 0x01
9602 #define _DAC5CON1_DAC5REF0 0x01
9603 #define _DAC5CON1_R0 0x01
9604 #define _DAC5CON1_DAC5R0 0x01
9605 #define _DAC5CON1_REF1 0x02
9606 #define _DAC5CON1_DAC5REF1 0x02
9607 #define _DAC5CON1_R1 0x02
9608 #define _DAC5CON1_DAC5R1 0x02
9609 #define _DAC5CON1_REF2 0x04
9610 #define _DAC5CON1_DAC5REF2 0x04
9611 #define _DAC5CON1_R2 0x04
9612 #define _DAC5CON1_DAC5R2 0x04
9613 #define _DAC5CON1_REF3 0x08
9614 #define _DAC5CON1_DAC5REF3 0x08
9615 #define _DAC5CON1_R3 0x08
9616 #define _DAC5CON1_DAC5R3 0x08
9617 #define _DAC5CON1_REF4 0x10
9618 #define _DAC5CON1_DAC5REF4 0x10
9619 #define _DAC5CON1_R4 0x10
9620 #define _DAC5CON1_DAC5R4 0x10
9621 #define _DAC5CON1_REF5 0x20
9622 #define _DAC5CON1_DAC5REF5 0x20
9623 #define _DAC5CON1_R5 0x20
9624 #define _DAC5CON1_DAC5R5 0x20
9625 #define _DAC5CON1_REF6 0x40
9626 #define _DAC5CON1_DAC5REF6 0x40
9627 #define _DAC5CON1_R6 0x40
9628 #define _DAC5CON1_DAC5R6 0x40
9629 #define _DAC5CON1_REF7 0x80
9630 #define _DAC5CON1_DAC5REF7 0x80
9631 #define _DAC5CON1_R7 0x80
9632 #define _DAC5CON1_DAC5R7 0x80
9634 //==============================================================================
9636 extern __at(0x0599) __sfr DAC5REF
;
9638 //==============================================================================
9641 extern __at(0x0599) __sfr DAC5REFL
;
9659 unsigned DAC5REF0
: 1;
9660 unsigned DAC5REF1
: 1;
9661 unsigned DAC5REF2
: 1;
9662 unsigned DAC5REF3
: 1;
9663 unsigned DAC5REF4
: 1;
9664 unsigned DAC5REF5
: 1;
9665 unsigned DAC5REF6
: 1;
9666 unsigned DAC5REF7
: 1;
9683 unsigned DAC5R0
: 1;
9684 unsigned DAC5R1
: 1;
9685 unsigned DAC5R2
: 1;
9686 unsigned DAC5R3
: 1;
9687 unsigned DAC5R4
: 1;
9688 unsigned DAC5R5
: 1;
9689 unsigned DAC5R6
: 1;
9690 unsigned DAC5R7
: 1;
9694 extern __at(0x0599) volatile __DAC5REFLbits_t DAC5REFLbits
;
9696 #define _DAC5REFL_REF0 0x01
9697 #define _DAC5REFL_DAC5REF0 0x01
9698 #define _DAC5REFL_R0 0x01
9699 #define _DAC5REFL_DAC5R0 0x01
9700 #define _DAC5REFL_REF1 0x02
9701 #define _DAC5REFL_DAC5REF1 0x02
9702 #define _DAC5REFL_R1 0x02
9703 #define _DAC5REFL_DAC5R1 0x02
9704 #define _DAC5REFL_REF2 0x04
9705 #define _DAC5REFL_DAC5REF2 0x04
9706 #define _DAC5REFL_R2 0x04
9707 #define _DAC5REFL_DAC5R2 0x04
9708 #define _DAC5REFL_REF3 0x08
9709 #define _DAC5REFL_DAC5REF3 0x08
9710 #define _DAC5REFL_R3 0x08
9711 #define _DAC5REFL_DAC5R3 0x08
9712 #define _DAC5REFL_REF4 0x10
9713 #define _DAC5REFL_DAC5REF4 0x10
9714 #define _DAC5REFL_R4 0x10
9715 #define _DAC5REFL_DAC5R4 0x10
9716 #define _DAC5REFL_REF5 0x20
9717 #define _DAC5REFL_DAC5REF5 0x20
9718 #define _DAC5REFL_R5 0x20
9719 #define _DAC5REFL_DAC5R5 0x20
9720 #define _DAC5REFL_REF6 0x40
9721 #define _DAC5REFL_DAC5REF6 0x40
9722 #define _DAC5REFL_R6 0x40
9723 #define _DAC5REFL_DAC5R6 0x40
9724 #define _DAC5REFL_REF7 0x80
9725 #define _DAC5REFL_DAC5REF7 0x80
9726 #define _DAC5REFL_R7 0x80
9727 #define _DAC5REFL_DAC5R7 0x80
9729 //==============================================================================
9732 //==============================================================================
9735 extern __at(0x059A) __sfr DAC5CON2
;
9753 unsigned DAC5REF8
: 1;
9754 unsigned DAC5REF9
: 1;
9755 unsigned DAC5REF10
: 1;
9756 unsigned DAC5REF11
: 1;
9757 unsigned DAC5REF12
: 1;
9758 unsigned DAC5REF13
: 1;
9759 unsigned DAC5REF14
: 1;
9760 unsigned DAC5REF15
: 1;
9777 unsigned DAC5R8
: 1;
9778 unsigned DAC5R9
: 1;
9779 unsigned DAC5R10
: 1;
9780 unsigned DAC5R11
: 1;
9781 unsigned DAC5R12
: 1;
9782 unsigned DAC5R13
: 1;
9783 unsigned DAC5R14
: 1;
9784 unsigned DAC5R15
: 1;
9788 extern __at(0x059A) volatile __DAC5CON2bits_t DAC5CON2bits
;
9790 #define _DAC5CON2_REF8 0x01
9791 #define _DAC5CON2_DAC5REF8 0x01
9792 #define _DAC5CON2_R8 0x01
9793 #define _DAC5CON2_DAC5R8 0x01
9794 #define _DAC5CON2_REF9 0x02
9795 #define _DAC5CON2_DAC5REF9 0x02
9796 #define _DAC5CON2_R9 0x02
9797 #define _DAC5CON2_DAC5R9 0x02
9798 #define _DAC5CON2_REF10 0x04
9799 #define _DAC5CON2_DAC5REF10 0x04
9800 #define _DAC5CON2_R10 0x04
9801 #define _DAC5CON2_DAC5R10 0x04
9802 #define _DAC5CON2_REF11 0x08
9803 #define _DAC5CON2_DAC5REF11 0x08
9804 #define _DAC5CON2_R11 0x08
9805 #define _DAC5CON2_DAC5R11 0x08
9806 #define _DAC5CON2_REF12 0x10
9807 #define _DAC5CON2_DAC5REF12 0x10
9808 #define _DAC5CON2_R12 0x10
9809 #define _DAC5CON2_DAC5R12 0x10
9810 #define _DAC5CON2_REF13 0x20
9811 #define _DAC5CON2_DAC5REF13 0x20
9812 #define _DAC5CON2_R13 0x20
9813 #define _DAC5CON2_DAC5R13 0x20
9814 #define _DAC5CON2_REF14 0x40
9815 #define _DAC5CON2_DAC5REF14 0x40
9816 #define _DAC5CON2_R14 0x40
9817 #define _DAC5CON2_DAC5R14 0x40
9818 #define _DAC5CON2_REF15 0x80
9819 #define _DAC5CON2_DAC5REF15 0x80
9820 #define _DAC5CON2_R15 0x80
9821 #define _DAC5CON2_DAC5R15 0x80
9823 //==============================================================================
9826 //==============================================================================
9829 extern __at(0x059A) __sfr DAC5REFH
;
9847 unsigned DAC5REF8
: 1;
9848 unsigned DAC5REF9
: 1;
9849 unsigned DAC5REF10
: 1;
9850 unsigned DAC5REF11
: 1;
9851 unsigned DAC5REF12
: 1;
9852 unsigned DAC5REF13
: 1;
9853 unsigned DAC5REF14
: 1;
9854 unsigned DAC5REF15
: 1;
9871 unsigned DAC5R8
: 1;
9872 unsigned DAC5R9
: 1;
9873 unsigned DAC5R10
: 1;
9874 unsigned DAC5R11
: 1;
9875 unsigned DAC5R12
: 1;
9876 unsigned DAC5R13
: 1;
9877 unsigned DAC5R14
: 1;
9878 unsigned DAC5R15
: 1;
9882 extern __at(0x059A) volatile __DAC5REFHbits_t DAC5REFHbits
;
9884 #define _DAC5REFH_REF8 0x01
9885 #define _DAC5REFH_DAC5REF8 0x01
9886 #define _DAC5REFH_R8 0x01
9887 #define _DAC5REFH_DAC5R8 0x01
9888 #define _DAC5REFH_REF9 0x02
9889 #define _DAC5REFH_DAC5REF9 0x02
9890 #define _DAC5REFH_R9 0x02
9891 #define _DAC5REFH_DAC5R9 0x02
9892 #define _DAC5REFH_REF10 0x04
9893 #define _DAC5REFH_DAC5REF10 0x04
9894 #define _DAC5REFH_R10 0x04
9895 #define _DAC5REFH_DAC5R10 0x04
9896 #define _DAC5REFH_REF11 0x08
9897 #define _DAC5REFH_DAC5REF11 0x08
9898 #define _DAC5REFH_R11 0x08
9899 #define _DAC5REFH_DAC5R11 0x08
9900 #define _DAC5REFH_REF12 0x10
9901 #define _DAC5REFH_DAC5REF12 0x10
9902 #define _DAC5REFH_R12 0x10
9903 #define _DAC5REFH_DAC5R12 0x10
9904 #define _DAC5REFH_REF13 0x20
9905 #define _DAC5REFH_DAC5REF13 0x20
9906 #define _DAC5REFH_R13 0x20
9907 #define _DAC5REFH_DAC5R13 0x20
9908 #define _DAC5REFH_REF14 0x40
9909 #define _DAC5REFH_DAC5REF14 0x40
9910 #define _DAC5REFH_R14 0x40
9911 #define _DAC5REFH_DAC5R14 0x40
9912 #define _DAC5REFH_REF15 0x80
9913 #define _DAC5REFH_DAC5REF15 0x80
9914 #define _DAC5REFH_R15 0x80
9915 #define _DAC5REFH_DAC5R15 0x80
9917 //==============================================================================
9920 //==============================================================================
9923 extern __at(0x059E) __sfr DAC7CON0
;
9941 unsigned DACNSS0
: 1;
9942 unsigned DACNSS1
: 1;
9943 unsigned DACPSS0
: 1;
9944 unsigned DACPSS1
: 1;
9945 unsigned DACOE2
: 1;
9946 unsigned DACOE1
: 1;
9953 unsigned DAC7NSS0
: 1;
9954 unsigned DAC7NSS1
: 1;
9955 unsigned DAC7PSS0
: 1;
9956 unsigned DAC7PSS1
: 1;
9957 unsigned DAC7OE2
: 1;
9958 unsigned DAC7OE1
: 1;
9960 unsigned DAC7EN
: 1;
9965 unsigned DAC7NSS
: 2;
9971 unsigned DACNSS
: 2;
9984 unsigned DACPSS
: 2;
9998 unsigned DAC7PSS
: 2;
10001 } __DAC7CON0bits_t
;
10003 extern __at(0x059E) volatile __DAC7CON0bits_t DAC7CON0bits
;
10005 #define _DAC7CON0_NSS0 0x01
10006 #define _DAC7CON0_DACNSS0 0x01
10007 #define _DAC7CON0_DAC7NSS0 0x01
10008 #define _DAC7CON0_NSS1 0x02
10009 #define _DAC7CON0_DACNSS1 0x02
10010 #define _DAC7CON0_DAC7NSS1 0x02
10011 #define _DAC7CON0_PSS0 0x04
10012 #define _DAC7CON0_DACPSS0 0x04
10013 #define _DAC7CON0_DAC7PSS0 0x04
10014 #define _DAC7CON0_PSS1 0x08
10015 #define _DAC7CON0_DACPSS1 0x08
10016 #define _DAC7CON0_DAC7PSS1 0x08
10017 #define _DAC7CON0_OE2 0x10
10018 #define _DAC7CON0_DACOE2 0x10
10019 #define _DAC7CON0_DAC7OE2 0x10
10020 #define _DAC7CON0_OE1 0x20
10021 #define _DAC7CON0_DACOE1 0x20
10022 #define _DAC7CON0_DAC7OE1 0x20
10023 #define _DAC7CON0_EN 0x80
10024 #define _DAC7CON0_DACEN 0x80
10025 #define _DAC7CON0_DAC7EN 0x80
10027 //==============================================================================
10030 //==============================================================================
10033 extern __at(0x059F) __sfr DAC7CON1
;
10039 unsigned DACR0
: 1;
10040 unsigned DACR1
: 1;
10041 unsigned DACR2
: 1;
10042 unsigned DACR3
: 1;
10043 unsigned DACR4
: 1;
10063 unsigned DAC7R0
: 1;
10064 unsigned DAC7R1
: 1;
10065 unsigned DAC7R2
: 1;
10066 unsigned DAC7R3
: 1;
10067 unsigned DAC7R4
: 1;
10087 unsigned DAC7REF0
: 1;
10088 unsigned DAC7REF1
: 1;
10089 unsigned DAC7REF2
: 1;
10090 unsigned DAC7REF3
: 1;
10091 unsigned DAC7REF4
: 1;
10111 unsigned DAC7REF
: 5;
10117 unsigned DAC7R
: 5;
10126 } __DAC7CON1bits_t
;
10128 extern __at(0x059F) volatile __DAC7CON1bits_t DAC7CON1bits
;
10130 #define _DAC7CON1_DACR0 0x01
10131 #define _DAC7CON1_R0 0x01
10132 #define _DAC7CON1_DAC7R0 0x01
10133 #define _DAC7CON1_REF0 0x01
10134 #define _DAC7CON1_DAC7REF0 0x01
10135 #define _DAC7CON1_DACR1 0x02
10136 #define _DAC7CON1_R1 0x02
10137 #define _DAC7CON1_DAC7R1 0x02
10138 #define _DAC7CON1_REF1 0x02
10139 #define _DAC7CON1_DAC7REF1 0x02
10140 #define _DAC7CON1_DACR2 0x04
10141 #define _DAC7CON1_R2 0x04
10142 #define _DAC7CON1_DAC7R2 0x04
10143 #define _DAC7CON1_REF2 0x04
10144 #define _DAC7CON1_DAC7REF2 0x04
10145 #define _DAC7CON1_DACR3 0x08
10146 #define _DAC7CON1_R3 0x08
10147 #define _DAC7CON1_DAC7R3 0x08
10148 #define _DAC7CON1_REF3 0x08
10149 #define _DAC7CON1_DAC7REF3 0x08
10150 #define _DAC7CON1_DACR4 0x10
10151 #define _DAC7CON1_R4 0x10
10152 #define _DAC7CON1_DAC7R4 0x10
10153 #define _DAC7CON1_REF4 0x10
10154 #define _DAC7CON1_DAC7REF4 0x10
10156 //==============================================================================
10159 //==============================================================================
10162 extern __at(0x059F) __sfr DAC7REF
;
10168 unsigned DACR0
: 1;
10169 unsigned DACR1
: 1;
10170 unsigned DACR2
: 1;
10171 unsigned DACR3
: 1;
10172 unsigned DACR4
: 1;
10192 unsigned DAC7R0
: 1;
10193 unsigned DAC7R1
: 1;
10194 unsigned DAC7R2
: 1;
10195 unsigned DAC7R3
: 1;
10196 unsigned DAC7R4
: 1;
10216 unsigned DAC7REF0
: 1;
10217 unsigned DAC7REF1
: 1;
10218 unsigned DAC7REF2
: 1;
10219 unsigned DAC7REF3
: 1;
10220 unsigned DAC7REF4
: 1;
10234 unsigned DAC7REF
: 5;
10240 unsigned DAC7R
: 5;
10257 extern __at(0x059F) volatile __DAC7REFbits_t DAC7REFbits
;
10259 #define _DAC7REF_DACR0 0x01
10260 #define _DAC7REF_R0 0x01
10261 #define _DAC7REF_DAC7R0 0x01
10262 #define _DAC7REF_REF0 0x01
10263 #define _DAC7REF_DAC7REF0 0x01
10264 #define _DAC7REF_DACR1 0x02
10265 #define _DAC7REF_R1 0x02
10266 #define _DAC7REF_DAC7R1 0x02
10267 #define _DAC7REF_REF1 0x02
10268 #define _DAC7REF_DAC7REF1 0x02
10269 #define _DAC7REF_DACR2 0x04
10270 #define _DAC7REF_R2 0x04
10271 #define _DAC7REF_DAC7R2 0x04
10272 #define _DAC7REF_REF2 0x04
10273 #define _DAC7REF_DAC7REF2 0x04
10274 #define _DAC7REF_DACR3 0x08
10275 #define _DAC7REF_R3 0x08
10276 #define _DAC7REF_DAC7R3 0x08
10277 #define _DAC7REF_REF3 0x08
10278 #define _DAC7REF_DAC7REF3 0x08
10279 #define _DAC7REF_DACR4 0x10
10280 #define _DAC7REF_R4 0x10
10281 #define _DAC7REF_DAC7R4 0x10
10282 #define _DAC7REF_REF4 0x10
10283 #define _DAC7REF_DAC7REF4 0x10
10285 //==============================================================================
10288 //==============================================================================
10291 extern __at(0x0614) __sfr PWM3DCL
;
10315 unsigned PWM3DC0
: 1;
10316 unsigned PWM3DC1
: 1;
10327 unsigned PWMPW0
: 1;
10328 unsigned PWMPW1
: 1;
10334 unsigned PWM3DC
: 2;
10340 unsigned PWMPW
: 2;
10350 extern __at(0x0614) volatile __PWM3DCLbits_t PWM3DCLbits
;
10353 #define _PWM3DC0 0x40
10354 #define _PWMPW0 0x40
10356 #define _PWM3DC1 0x80
10357 #define _PWMPW1 0x80
10359 //==============================================================================
10362 //==============================================================================
10365 extern __at(0x0615) __sfr PWM3DCH
;
10383 unsigned PWM3DC2
: 1;
10384 unsigned PWM3DC3
: 1;
10385 unsigned PWM3DC4
: 1;
10386 unsigned PWM3DC5
: 1;
10387 unsigned PWM3DC6
: 1;
10388 unsigned PWM3DC7
: 1;
10389 unsigned PWM3DC8
: 1;
10390 unsigned PWM3DC9
: 1;
10395 unsigned PWMPW2
: 1;
10396 unsigned PWMPW3
: 1;
10397 unsigned PWMPW4
: 1;
10398 unsigned PWMPW5
: 1;
10399 unsigned PWMPW6
: 1;
10400 unsigned PWMPW7
: 1;
10401 unsigned PWMPW8
: 1;
10402 unsigned PWMPW9
: 1;
10406 extern __at(0x0615) volatile __PWM3DCHbits_t PWM3DCHbits
;
10409 #define _PWM3DC2 0x01
10410 #define _PWMPW2 0x01
10412 #define _PWM3DC3 0x02
10413 #define _PWMPW3 0x02
10415 #define _PWM3DC4 0x04
10416 #define _PWMPW4 0x04
10418 #define _PWM3DC5 0x08
10419 #define _PWMPW5 0x08
10421 #define _PWM3DC6 0x10
10422 #define _PWMPW6 0x10
10424 #define _PWM3DC7 0x20
10425 #define _PWMPW7 0x20
10427 #define _PWM3DC8 0x40
10428 #define _PWMPW8 0x40
10430 #define _PWM3DC9 0x80
10431 #define _PWMPW9 0x80
10433 //==============================================================================
10436 //==============================================================================
10439 extern __at(0x0616) __sfr PWM3CON
;
10461 unsigned PWM3POL
: 1;
10462 unsigned PWM3OUT
: 1;
10464 unsigned PWM3EN
: 1;
10468 extern __at(0x0616) volatile __PWM3CONbits_t PWM3CONbits
;
10470 #define _PWM3CON_POL 0x10
10471 #define _PWM3CON_PWM3POL 0x10
10472 #define _PWM3CON_OUT 0x20
10473 #define _PWM3CON_PWM3OUT 0x20
10474 #define _PWM3CON_EN 0x80
10475 #define _PWM3CON_PWM3EN 0x80
10477 //==============================================================================
10480 //==============================================================================
10483 extern __at(0x0617) __sfr PWM4DCL
;
10507 unsigned PWM4DC0
: 1;
10508 unsigned PWM4DC1
: 1;
10519 unsigned PWMPW0
: 1;
10520 unsigned PWMPW1
: 1;
10526 unsigned PWMPW
: 2;
10532 unsigned PWM4DC
: 2;
10542 extern __at(0x0617) volatile __PWM4DCLbits_t PWM4DCLbits
;
10544 #define _PWM4DCL_DC0 0x40
10545 #define _PWM4DCL_PWM4DC0 0x40
10546 #define _PWM4DCL_PWMPW0 0x40
10547 #define _PWM4DCL_DC1 0x80
10548 #define _PWM4DCL_PWM4DC1 0x80
10549 #define _PWM4DCL_PWMPW1 0x80
10551 //==============================================================================
10554 //==============================================================================
10557 extern __at(0x0618) __sfr PWM4DCH
;
10575 unsigned PWM4DC2
: 1;
10576 unsigned PWM4DC3
: 1;
10577 unsigned PWM4DC4
: 1;
10578 unsigned PWM4DC5
: 1;
10579 unsigned PWM4DC6
: 1;
10580 unsigned PWM4DC7
: 1;
10581 unsigned PWM4DC8
: 1;
10582 unsigned PWM4DC9
: 1;
10587 unsigned PWMPW2
: 1;
10588 unsigned PWMPW3
: 1;
10589 unsigned PWMPW4
: 1;
10590 unsigned PWMPW5
: 1;
10591 unsigned PWMPW6
: 1;
10592 unsigned PWMPW7
: 1;
10593 unsigned PWMPW8
: 1;
10594 unsigned PWMPW9
: 1;
10598 extern __at(0x0618) volatile __PWM4DCHbits_t PWM4DCHbits
;
10600 #define _PWM4DCH_DC2 0x01
10601 #define _PWM4DCH_PWM4DC2 0x01
10602 #define _PWM4DCH_PWMPW2 0x01
10603 #define _PWM4DCH_DC3 0x02
10604 #define _PWM4DCH_PWM4DC3 0x02
10605 #define _PWM4DCH_PWMPW3 0x02
10606 #define _PWM4DCH_DC4 0x04
10607 #define _PWM4DCH_PWM4DC4 0x04
10608 #define _PWM4DCH_PWMPW4 0x04
10609 #define _PWM4DCH_DC5 0x08
10610 #define _PWM4DCH_PWM4DC5 0x08
10611 #define _PWM4DCH_PWMPW5 0x08
10612 #define _PWM4DCH_DC6 0x10
10613 #define _PWM4DCH_PWM4DC6 0x10
10614 #define _PWM4DCH_PWMPW6 0x10
10615 #define _PWM4DCH_DC7 0x20
10616 #define _PWM4DCH_PWM4DC7 0x20
10617 #define _PWM4DCH_PWMPW7 0x20
10618 #define _PWM4DCH_DC8 0x40
10619 #define _PWM4DCH_PWM4DC8 0x40
10620 #define _PWM4DCH_PWMPW8 0x40
10621 #define _PWM4DCH_DC9 0x80
10622 #define _PWM4DCH_PWM4DC9 0x80
10623 #define _PWM4DCH_PWMPW9 0x80
10625 //==============================================================================
10628 //==============================================================================
10631 extern __at(0x0619) __sfr PWM4CON
;
10653 unsigned PWM4POL
: 1;
10654 unsigned PWM4OUT
: 1;
10656 unsigned PWM4EN
: 1;
10660 extern __at(0x0619) volatile __PWM4CONbits_t PWM4CONbits
;
10662 #define _PWM4CON_POL 0x10
10663 #define _PWM4CON_PWM4POL 0x10
10664 #define _PWM4CON_OUT 0x20
10665 #define _PWM4CON_PWM4OUT 0x20
10666 #define _PWM4CON_EN 0x80
10667 #define _PWM4CON_PWM4EN 0x80
10669 //==============================================================================
10672 //==============================================================================
10675 extern __at(0x061A) __sfr PWM9DCL
;
10699 unsigned PWM9DC0
: 1;
10700 unsigned PWM9DC1
: 1;
10711 unsigned PWMPW0
: 1;
10712 unsigned PWMPW1
: 1;
10718 unsigned PWMPW
: 2;
10724 unsigned PWM9DC
: 2;
10734 extern __at(0x061A) volatile __PWM9DCLbits_t PWM9DCLbits
;
10736 #define _PWM9DCL_DC0 0x40
10737 #define _PWM9DCL_PWM9DC0 0x40
10738 #define _PWM9DCL_PWMPW0 0x40
10739 #define _PWM9DCL_DC1 0x80
10740 #define _PWM9DCL_PWM9DC1 0x80
10741 #define _PWM9DCL_PWMPW1 0x80
10743 //==============================================================================
10746 //==============================================================================
10749 extern __at(0x061B) __sfr PWM9DCH
;
10767 unsigned PWM9DC2
: 1;
10768 unsigned PWM9DC3
: 1;
10769 unsigned PWM9DC4
: 1;
10770 unsigned PWM9DC5
: 1;
10771 unsigned PWM9DC6
: 1;
10772 unsigned PWM9DC7
: 1;
10773 unsigned PWM9DC8
: 1;
10774 unsigned PWM9DC9
: 1;
10779 unsigned PWMPW2
: 1;
10780 unsigned PWMPW3
: 1;
10781 unsigned PWMPW4
: 1;
10782 unsigned PWMPW5
: 1;
10783 unsigned PWMPW6
: 1;
10784 unsigned PWMPW7
: 1;
10785 unsigned PWMPW8
: 1;
10786 unsigned PWMPW9
: 1;
10790 extern __at(0x061B) volatile __PWM9DCHbits_t PWM9DCHbits
;
10792 #define _PWM9DCH_DC2 0x01
10793 #define _PWM9DCH_PWM9DC2 0x01
10794 #define _PWM9DCH_PWMPW2 0x01
10795 #define _PWM9DCH_DC3 0x02
10796 #define _PWM9DCH_PWM9DC3 0x02
10797 #define _PWM9DCH_PWMPW3 0x02
10798 #define _PWM9DCH_DC4 0x04
10799 #define _PWM9DCH_PWM9DC4 0x04
10800 #define _PWM9DCH_PWMPW4 0x04
10801 #define _PWM9DCH_DC5 0x08
10802 #define _PWM9DCH_PWM9DC5 0x08
10803 #define _PWM9DCH_PWMPW5 0x08
10804 #define _PWM9DCH_DC6 0x10
10805 #define _PWM9DCH_PWM9DC6 0x10
10806 #define _PWM9DCH_PWMPW6 0x10
10807 #define _PWM9DCH_DC7 0x20
10808 #define _PWM9DCH_PWM9DC7 0x20
10809 #define _PWM9DCH_PWMPW7 0x20
10810 #define _PWM9DCH_DC8 0x40
10811 #define _PWM9DCH_PWM9DC8 0x40
10812 #define _PWM9DCH_PWMPW8 0x40
10813 #define _PWM9DCH_DC9 0x80
10814 #define _PWM9DCH_PWM9DC9 0x80
10815 #define _PWM9DCH_PWMPW9 0x80
10817 //==============================================================================
10820 //==============================================================================
10823 extern __at(0x061C) __sfr PWM9CON
;
10845 unsigned PWM9POL
: 1;
10846 unsigned PWM9OUT
: 1;
10847 unsigned PWM9OE
: 1;
10848 unsigned PWM9EN
: 1;
10852 extern __at(0x061C) volatile __PWM9CONbits_t PWM9CONbits
;
10854 #define _PWM9CON_POL 0x10
10855 #define _PWM9CON_PWM9POL 0x10
10856 #define _PWM9CON_OUT 0x20
10857 #define _PWM9CON_PWM9OUT 0x20
10858 #define _PWM9CON_OE 0x40
10859 #define _PWM9CON_PWM9OE 0x40
10860 #define _PWM9CON_EN 0x80
10861 #define _PWM9CON_PWM9EN 0x80
10863 //==============================================================================
10866 //==============================================================================
10869 extern __at(0x068D) __sfr COG1PHR
;
10887 unsigned G1PHR0
: 1;
10888 unsigned G1PHR1
: 1;
10889 unsigned G1PHR2
: 1;
10890 unsigned G1PHR3
: 1;
10891 unsigned G1PHR4
: 1;
10892 unsigned G1PHR5
: 1;
10899 unsigned G1PHR
: 6;
10910 extern __at(0x068D) volatile __COG1PHRbits_t COG1PHRbits
;
10913 #define _G1PHR0 0x01
10915 #define _G1PHR1 0x02
10917 #define _G1PHR2 0x04
10919 #define _G1PHR3 0x08
10921 #define _G1PHR4 0x10
10923 #define _G1PHR5 0x20
10925 //==============================================================================
10928 //==============================================================================
10931 extern __at(0x068E) __sfr COG1PHF
;
10949 unsigned G1PHF0
: 1;
10950 unsigned G1PHF1
: 1;
10951 unsigned G1PHF2
: 1;
10952 unsigned G1PHF3
: 1;
10953 unsigned G1PHF4
: 1;
10954 unsigned G1PHF5
: 1;
10967 unsigned G1PHF
: 6;
10972 extern __at(0x068E) volatile __COG1PHFbits_t COG1PHFbits
;
10975 #define _G1PHF0 0x01
10977 #define _G1PHF1 0x02
10979 #define _G1PHF2 0x04
10981 #define _G1PHF3 0x08
10983 #define _G1PHF4 0x10
10985 #define _G1PHF5 0x20
10987 //==============================================================================
10990 //==============================================================================
10993 extern __at(0x068F) __sfr COG1BLKR
;
10999 unsigned BLKR0
: 1;
11000 unsigned BLKR1
: 1;
11001 unsigned BLKR2
: 1;
11002 unsigned BLKR3
: 1;
11003 unsigned BLKR4
: 1;
11004 unsigned BLKR5
: 1;
11011 unsigned G1BLKR0
: 1;
11012 unsigned G1BLKR1
: 1;
11013 unsigned G1BLKR2
: 1;
11014 unsigned G1BLKR3
: 1;
11015 unsigned G1BLKR4
: 1;
11016 unsigned G1BLKR5
: 1;
11023 unsigned G1BLKR
: 6;
11032 } __COG1BLKRbits_t
;
11034 extern __at(0x068F) volatile __COG1BLKRbits_t COG1BLKRbits
;
11036 #define _BLKR0 0x01
11037 #define _G1BLKR0 0x01
11038 #define _BLKR1 0x02
11039 #define _G1BLKR1 0x02
11040 #define _BLKR2 0x04
11041 #define _G1BLKR2 0x04
11042 #define _BLKR3 0x08
11043 #define _G1BLKR3 0x08
11044 #define _BLKR4 0x10
11045 #define _G1BLKR4 0x10
11046 #define _BLKR5 0x20
11047 #define _G1BLKR5 0x20
11049 //==============================================================================
11052 //==============================================================================
11055 extern __at(0x0690) __sfr COG1BLKF
;
11061 unsigned BLKF0
: 1;
11062 unsigned BLKF1
: 1;
11063 unsigned BLKF2
: 1;
11064 unsigned BLKF3
: 1;
11065 unsigned BLKF4
: 1;
11066 unsigned BLKF5
: 1;
11073 unsigned G1BLKF0
: 1;
11074 unsigned G1BLKF1
: 1;
11075 unsigned G1BLKF2
: 1;
11076 unsigned G1BLKF3
: 1;
11077 unsigned G1BLKF4
: 1;
11078 unsigned G1BLKF5
: 1;
11091 unsigned G1BLKF
: 6;
11094 } __COG1BLKFbits_t
;
11096 extern __at(0x0690) volatile __COG1BLKFbits_t COG1BLKFbits
;
11098 #define _BLKF0 0x01
11099 #define _G1BLKF0 0x01
11100 #define _BLKF1 0x02
11101 #define _G1BLKF1 0x02
11102 #define _BLKF2 0x04
11103 #define _G1BLKF2 0x04
11104 #define _BLKF3 0x08
11105 #define _G1BLKF3 0x08
11106 #define _BLKF4 0x10
11107 #define _G1BLKF4 0x10
11108 #define _BLKF5 0x20
11109 #define _G1BLKF5 0x20
11111 //==============================================================================
11114 //==============================================================================
11117 extern __at(0x0691) __sfr COG1DBR
;
11135 unsigned G1DBR0
: 1;
11136 unsigned G1DBR1
: 1;
11137 unsigned G1DBR2
: 1;
11138 unsigned G1DBR3
: 1;
11139 unsigned G1DBR4
: 1;
11140 unsigned G1DBR5
: 1;
11147 unsigned G1DBR
: 6;
11158 extern __at(0x0691) volatile __COG1DBRbits_t COG1DBRbits
;
11161 #define _G1DBR0 0x01
11163 #define _G1DBR1 0x02
11165 #define _G1DBR2 0x04
11167 #define _G1DBR3 0x08
11169 #define _G1DBR4 0x10
11171 #define _G1DBR5 0x20
11173 //==============================================================================
11176 //==============================================================================
11179 extern __at(0x0692) __sfr COG1DBF
;
11197 unsigned G1DBF0
: 1;
11198 unsigned G1DBF1
: 1;
11199 unsigned G1DBF2
: 1;
11200 unsigned G1DBF3
: 1;
11201 unsigned G1DBF4
: 1;
11202 unsigned G1DBF5
: 1;
11209 unsigned G1DBF
: 6;
11220 extern __at(0x0692) volatile __COG1DBFbits_t COG1DBFbits
;
11223 #define _G1DBF0 0x01
11225 #define _G1DBF1 0x02
11227 #define _G1DBF2 0x04
11229 #define _G1DBF3 0x08
11231 #define _G1DBF4 0x10
11233 #define _G1DBF5 0x20
11235 //==============================================================================
11238 //==============================================================================
11241 extern __at(0x0693) __sfr COG1CON0
;
11259 unsigned G1MD0
: 1;
11260 unsigned G1MD1
: 1;
11261 unsigned G1MD2
: 1;
11262 unsigned G1CS0
: 1;
11263 unsigned G1CS1
: 1;
11294 } __COG1CON0bits_t
;
11296 extern __at(0x0693) volatile __COG1CON0bits_t COG1CON0bits
;
11298 #define _COG1CON0_MD0 0x01
11299 #define _COG1CON0_G1MD0 0x01
11300 #define _COG1CON0_MD1 0x02
11301 #define _COG1CON0_G1MD1 0x02
11302 #define _COG1CON0_MD2 0x04
11303 #define _COG1CON0_G1MD2 0x04
11304 #define _COG1CON0_CS0 0x08
11305 #define _COG1CON0_G1CS0 0x08
11306 #define _COG1CON0_CS1 0x10
11307 #define _COG1CON0_G1CS1 0x10
11308 #define _COG1CON0_LD 0x40
11309 #define _COG1CON0_G1LD 0x40
11310 #define _COG1CON0_EN 0x80
11311 #define _COG1CON0_G1EN 0x80
11313 //==============================================================================
11316 //==============================================================================
11319 extern __at(0x0694) __sfr COG1CON1
;
11337 unsigned G1POLA
: 1;
11338 unsigned G1POLB
: 1;
11339 unsigned G1POLC
: 1;
11340 unsigned G1POLD
: 1;
11343 unsigned G1FDBS
: 1;
11344 unsigned G1RDBS
: 1;
11346 } __COG1CON1bits_t
;
11348 extern __at(0x0694) volatile __COG1CON1bits_t COG1CON1bits
;
11351 #define _G1POLA 0x01
11353 #define _G1POLB 0x02
11355 #define _G1POLC 0x04
11357 #define _G1POLD 0x08
11359 #define _G1FDBS 0x40
11361 #define _G1RDBS 0x80
11363 //==============================================================================
11366 //==============================================================================
11369 extern __at(0x0695) __sfr COG1RIS0
;
11387 unsigned G1RIS0
: 1;
11388 unsigned G1RIS1
: 1;
11389 unsigned G1RIS2
: 1;
11390 unsigned G1RIS3
: 1;
11391 unsigned G1RIS4
: 1;
11392 unsigned G1RIS5
: 1;
11393 unsigned G1RIS6
: 1;
11394 unsigned G1RIS7
: 1;
11396 } __COG1RIS0bits_t
;
11398 extern __at(0x0695) volatile __COG1RIS0bits_t COG1RIS0bits
;
11401 #define _G1RIS0 0x01
11403 #define _G1RIS1 0x02
11405 #define _G1RIS2 0x04
11407 #define _G1RIS3 0x08
11409 #define _G1RIS4 0x10
11411 #define _G1RIS5 0x20
11413 #define _G1RIS6 0x40
11415 #define _G1RIS7 0x80
11417 //==============================================================================
11420 //==============================================================================
11423 extern __at(0x0696) __sfr COG1RIS1
;
11431 unsigned RIS10
: 1;
11432 unsigned RIS11
: 1;
11433 unsigned RIS12
: 1;
11434 unsigned RIS13
: 1;
11435 unsigned RIS14
: 1;
11436 unsigned RIS15
: 1;
11441 unsigned G1RIS8
: 1;
11442 unsigned G1RIS9
: 1;
11443 unsigned G1RIS10
: 1;
11444 unsigned G1RIS11
: 1;
11445 unsigned G1RIS12
: 1;
11446 unsigned G1RIS13
: 1;
11447 unsigned G1RIS14
: 1;
11448 unsigned G1RIS15
: 1;
11450 } __COG1RIS1bits_t
;
11452 extern __at(0x0696) volatile __COG1RIS1bits_t COG1RIS1bits
;
11455 #define _G1RIS8 0x01
11457 #define _G1RIS9 0x02
11458 #define _RIS10 0x04
11459 #define _G1RIS10 0x04
11460 #define _RIS11 0x08
11461 #define _G1RIS11 0x08
11462 #define _RIS12 0x10
11463 #define _G1RIS12 0x10
11464 #define _RIS13 0x20
11465 #define _G1RIS13 0x20
11466 #define _RIS14 0x40
11467 #define _G1RIS14 0x40
11468 #define _RIS15 0x80
11469 #define _G1RIS15 0x80
11471 //==============================================================================
11474 //==============================================================================
11477 extern __at(0x0697) __sfr COG1RSIM0
;
11483 unsigned RSIM0
: 1;
11484 unsigned RSIM1
: 1;
11485 unsigned RSIM2
: 1;
11486 unsigned RSIM3
: 1;
11487 unsigned RSIM4
: 1;
11488 unsigned RSIM5
: 1;
11489 unsigned RSIM6
: 1;
11490 unsigned RSIM7
: 1;
11495 unsigned G1RSIM0
: 1;
11496 unsigned G1RSIM1
: 1;
11497 unsigned G1RSIM2
: 1;
11498 unsigned G1RSIM3
: 1;
11499 unsigned G1RSIM4
: 1;
11500 unsigned G1RSIM5
: 1;
11501 unsigned G1RSIM6
: 1;
11502 unsigned G1RSIM7
: 1;
11504 } __COG1RSIM0bits_t
;
11506 extern __at(0x0697) volatile __COG1RSIM0bits_t COG1RSIM0bits
;
11508 #define _RSIM0 0x01
11509 #define _G1RSIM0 0x01
11510 #define _RSIM1 0x02
11511 #define _G1RSIM1 0x02
11512 #define _RSIM2 0x04
11513 #define _G1RSIM2 0x04
11514 #define _RSIM3 0x08
11515 #define _G1RSIM3 0x08
11516 #define _RSIM4 0x10
11517 #define _G1RSIM4 0x10
11518 #define _RSIM5 0x20
11519 #define _G1RSIM5 0x20
11520 #define _RSIM6 0x40
11521 #define _G1RSIM6 0x40
11522 #define _RSIM7 0x80
11523 #define _G1RSIM7 0x80
11525 //==============================================================================
11528 //==============================================================================
11531 extern __at(0x0698) __sfr COG1RSIM1
;
11537 unsigned RSIM8
: 1;
11538 unsigned RSIM9
: 1;
11539 unsigned RSIM10
: 1;
11540 unsigned RSIM11
: 1;
11541 unsigned RSIM12
: 1;
11542 unsigned RSIM13
: 1;
11543 unsigned RSIM14
: 1;
11544 unsigned RSIM15
: 1;
11549 unsigned G1RSIM8
: 1;
11550 unsigned G1RSIM9
: 1;
11551 unsigned G1RSIM10
: 1;
11552 unsigned G1RSIM11
: 1;
11553 unsigned G1RSIM12
: 1;
11554 unsigned G1RSIM13
: 1;
11555 unsigned G1RSIM14
: 1;
11556 unsigned G1RSIM15
: 1;
11558 } __COG1RSIM1bits_t
;
11560 extern __at(0x0698) volatile __COG1RSIM1bits_t COG1RSIM1bits
;
11562 #define _RSIM8 0x01
11563 #define _G1RSIM8 0x01
11564 #define _RSIM9 0x02
11565 #define _G1RSIM9 0x02
11566 #define _RSIM10 0x04
11567 #define _G1RSIM10 0x04
11568 #define _RSIM11 0x08
11569 #define _G1RSIM11 0x08
11570 #define _RSIM12 0x10
11571 #define _G1RSIM12 0x10
11572 #define _RSIM13 0x20
11573 #define _G1RSIM13 0x20
11574 #define _RSIM14 0x40
11575 #define _G1RSIM14 0x40
11576 #define _RSIM15 0x80
11577 #define _G1RSIM15 0x80
11579 //==============================================================================
11582 //==============================================================================
11585 extern __at(0x0699) __sfr COG1FIS0
;
11603 unsigned G1FIS0
: 1;
11604 unsigned G1FIS1
: 1;
11605 unsigned G1FIS2
: 1;
11606 unsigned G1FIS3
: 1;
11607 unsigned G1FIS4
: 1;
11608 unsigned G1FIS5
: 1;
11609 unsigned G1FIS6
: 1;
11610 unsigned G1FIS7
: 1;
11612 } __COG1FIS0bits_t
;
11614 extern __at(0x0699) volatile __COG1FIS0bits_t COG1FIS0bits
;
11617 #define _G1FIS0 0x01
11619 #define _G1FIS1 0x02
11621 #define _G1FIS2 0x04
11623 #define _G1FIS3 0x08
11625 #define _G1FIS4 0x10
11627 #define _G1FIS5 0x20
11629 #define _G1FIS6 0x40
11631 #define _G1FIS7 0x80
11633 //==============================================================================
11636 //==============================================================================
11639 extern __at(0x069A) __sfr COG1FIS1
;
11647 unsigned FIS10
: 1;
11648 unsigned FIS11
: 1;
11649 unsigned FIS12
: 1;
11650 unsigned FIS13
: 1;
11651 unsigned FIS14
: 1;
11652 unsigned FIS15
: 1;
11657 unsigned G1FIS8
: 1;
11658 unsigned G1FIS9
: 1;
11659 unsigned G1FIS10
: 1;
11660 unsigned G1FIS11
: 1;
11661 unsigned G1FIS12
: 1;
11662 unsigned G1FIS13
: 1;
11663 unsigned G1FIS14
: 1;
11664 unsigned G1FIS15
: 1;
11666 } __COG1FIS1bits_t
;
11668 extern __at(0x069A) volatile __COG1FIS1bits_t COG1FIS1bits
;
11671 #define _G1FIS8 0x01
11673 #define _G1FIS9 0x02
11674 #define _FIS10 0x04
11675 #define _G1FIS10 0x04
11676 #define _FIS11 0x08
11677 #define _G1FIS11 0x08
11678 #define _FIS12 0x10
11679 #define _G1FIS12 0x10
11680 #define _FIS13 0x20
11681 #define _G1FIS13 0x20
11682 #define _FIS14 0x40
11683 #define _G1FIS14 0x40
11684 #define _FIS15 0x80
11685 #define _G1FIS15 0x80
11687 //==============================================================================
11690 //==============================================================================
11693 extern __at(0x069B) __sfr COG1FSIM0
;
11699 unsigned FSIM0
: 1;
11700 unsigned FSIM1
: 1;
11701 unsigned FSIM2
: 1;
11702 unsigned FSIM3
: 1;
11703 unsigned FSIM4
: 1;
11704 unsigned FSIM5
: 1;
11705 unsigned FSIM6
: 1;
11706 unsigned FSIM7
: 1;
11711 unsigned G1FSIM0
: 1;
11712 unsigned G1FSIM1
: 1;
11713 unsigned G1FSIM2
: 1;
11714 unsigned G1FSIM3
: 1;
11715 unsigned G1FSIM4
: 1;
11716 unsigned G1FSIM5
: 1;
11717 unsigned G1FSIM6
: 1;
11718 unsigned G1FSIM7
: 1;
11720 } __COG1FSIM0bits_t
;
11722 extern __at(0x069B) volatile __COG1FSIM0bits_t COG1FSIM0bits
;
11724 #define _FSIM0 0x01
11725 #define _G1FSIM0 0x01
11726 #define _FSIM1 0x02
11727 #define _G1FSIM1 0x02
11728 #define _FSIM2 0x04
11729 #define _G1FSIM2 0x04
11730 #define _FSIM3 0x08
11731 #define _G1FSIM3 0x08
11732 #define _FSIM4 0x10
11733 #define _G1FSIM4 0x10
11734 #define _FSIM5 0x20
11735 #define _G1FSIM5 0x20
11736 #define _FSIM6 0x40
11737 #define _G1FSIM6 0x40
11738 #define _FSIM7 0x80
11739 #define _G1FSIM7 0x80
11741 //==============================================================================
11744 //==============================================================================
11747 extern __at(0x069C) __sfr COG1FSIM1
;
11753 unsigned FSIM8
: 1;
11754 unsigned FSIM9
: 1;
11755 unsigned FSIM10
: 1;
11756 unsigned FSIM11
: 1;
11757 unsigned FSIM12
: 1;
11758 unsigned FSIM13
: 1;
11759 unsigned FSIM14
: 1;
11760 unsigned FSIM15
: 1;
11765 unsigned G1FSIM8
: 1;
11766 unsigned G1FSIM9
: 1;
11767 unsigned G1FSIM10
: 1;
11768 unsigned G1FSIM11
: 1;
11769 unsigned G1FSIM12
: 1;
11770 unsigned G1FSIM13
: 1;
11771 unsigned G1FSIM14
: 1;
11772 unsigned G1FSIM15
: 1;
11774 } __COG1FSIM1bits_t
;
11776 extern __at(0x069C) volatile __COG1FSIM1bits_t COG1FSIM1bits
;
11778 #define _FSIM8 0x01
11779 #define _G1FSIM8 0x01
11780 #define _FSIM9 0x02
11781 #define _G1FSIM9 0x02
11782 #define _FSIM10 0x04
11783 #define _G1FSIM10 0x04
11784 #define _FSIM11 0x08
11785 #define _G1FSIM11 0x08
11786 #define _FSIM12 0x10
11787 #define _G1FSIM12 0x10
11788 #define _FSIM13 0x20
11789 #define _G1FSIM13 0x20
11790 #define _FSIM14 0x40
11791 #define _G1FSIM14 0x40
11792 #define _FSIM15 0x80
11793 #define _G1FSIM15 0x80
11795 //==============================================================================
11798 //==============================================================================
11801 extern __at(0x069D) __sfr COG1ASD0
;
11809 unsigned ASDAC0
: 1;
11810 unsigned ASDAC1
: 1;
11811 unsigned ASDBD0
: 1;
11812 unsigned ASDBD1
: 1;
11813 unsigned ASREN
: 1;
11821 unsigned G1ASDAC0
: 1;
11822 unsigned G1ASDAC1
: 1;
11823 unsigned G1ASDBD0
: 1;
11824 unsigned G1ASDBD1
: 1;
11825 unsigned ARSEN
: 1;
11826 unsigned G1ASE
: 1;
11837 unsigned G1ARSEN
: 1;
11849 unsigned G1ASREN
: 1;
11856 unsigned G1ASDAC
: 2;
11863 unsigned ASDAC
: 2;
11870 unsigned ASDBD
: 2;
11877 unsigned G1ASDBD
: 2;
11880 } __COG1ASD0bits_t
;
11882 extern __at(0x069D) volatile __COG1ASD0bits_t COG1ASD0bits
;
11884 #define _ASDAC0 0x04
11885 #define _G1ASDAC0 0x04
11886 #define _ASDAC1 0x08
11887 #define _G1ASDAC1 0x08
11888 #define _ASDBD0 0x10
11889 #define _G1ASDBD0 0x10
11890 #define _ASDBD1 0x20
11891 #define _G1ASDBD1 0x20
11892 #define _ASREN 0x40
11893 #define _ARSEN 0x40
11894 #define _G1ARSEN 0x40
11895 #define _G1ASREN 0x40
11897 #define _G1ASE 0x80
11899 //==============================================================================
11902 //==============================================================================
11905 extern __at(0x069E) __sfr COG1ASD1
;
11923 unsigned G1AS0E
: 1;
11924 unsigned G1AS1E
: 1;
11925 unsigned G1AS2E
: 1;
11926 unsigned G1AS3E
: 1;
11927 unsigned G1AS4E
: 1;
11928 unsigned G1AS5E
: 1;
11929 unsigned G1AS6E
: 1;
11930 unsigned G1AS7E
: 1;
11932 } __COG1ASD1bits_t
;
11934 extern __at(0x069E) volatile __COG1ASD1bits_t COG1ASD1bits
;
11937 #define _G1AS0E 0x01
11939 #define _G1AS1E 0x02
11941 #define _G1AS2E 0x04
11943 #define _G1AS3E 0x08
11945 #define _G1AS4E 0x10
11947 #define _G1AS5E 0x20
11949 #define _G1AS6E 0x40
11951 #define _G1AS7E 0x80
11953 //==============================================================================
11956 //==============================================================================
11959 extern __at(0x069F) __sfr COG1STR
;
11969 unsigned SDATA
: 1;
11970 unsigned SDATB
: 1;
11971 unsigned SDATC
: 1;
11972 unsigned SDATD
: 1;
11977 unsigned G1STRA
: 1;
11978 unsigned G1STRB
: 1;
11979 unsigned G1STRC
: 1;
11980 unsigned G1STRD
: 1;
11981 unsigned G1SDATA
: 1;
11982 unsigned G1SDATB
: 1;
11983 unsigned G1SDATC
: 1;
11984 unsigned G1SDATD
: 1;
11988 extern __at(0x069F) volatile __COG1STRbits_t COG1STRbits
;
11991 #define _G1STRA 0x01
11993 #define _G1STRB 0x02
11995 #define _G1STRC 0x04
11997 #define _G1STRD 0x08
11998 #define _SDATA 0x10
11999 #define _G1SDATA 0x10
12000 #define _SDATB 0x20
12001 #define _G1SDATB 0x20
12002 #define _SDATC 0x40
12003 #define _G1SDATC 0x40
12004 #define _SDATD 0x80
12005 #define _G1SDATD 0x80
12007 //==============================================================================
12010 //==============================================================================
12013 extern __at(0x070D) __sfr COG2PHR
;
12031 unsigned G2PHR0
: 1;
12032 unsigned G2PHR1
: 1;
12033 unsigned G2PHR2
: 1;
12034 unsigned G2PHR3
: 1;
12035 unsigned G2PHR4
: 1;
12036 unsigned G2PHR5
: 1;
12049 unsigned G2PHR
: 6;
12054 extern __at(0x070D) volatile __COG2PHRbits_t COG2PHRbits
;
12056 #define _COG2PHR_PHR0 0x01
12057 #define _COG2PHR_G2PHR0 0x01
12058 #define _COG2PHR_PHR1 0x02
12059 #define _COG2PHR_G2PHR1 0x02
12060 #define _COG2PHR_PHR2 0x04
12061 #define _COG2PHR_G2PHR2 0x04
12062 #define _COG2PHR_PHR3 0x08
12063 #define _COG2PHR_G2PHR3 0x08
12064 #define _COG2PHR_PHR4 0x10
12065 #define _COG2PHR_G2PHR4 0x10
12066 #define _COG2PHR_PHR5 0x20
12067 #define _COG2PHR_G2PHR5 0x20
12069 //==============================================================================
12072 //==============================================================================
12075 extern __at(0x070E) __sfr COG2PHF
;
12093 unsigned G2PHF0
: 1;
12094 unsigned G2PHF1
: 1;
12095 unsigned G2PHF2
: 1;
12096 unsigned G2PHF3
: 1;
12097 unsigned G2PHF4
: 1;
12098 unsigned G2PHF5
: 1;
12105 unsigned G2PHF
: 6;
12116 extern __at(0x070E) volatile __COG2PHFbits_t COG2PHFbits
;
12118 #define _COG2PHF_PHF0 0x01
12119 #define _COG2PHF_G2PHF0 0x01
12120 #define _COG2PHF_PHF1 0x02
12121 #define _COG2PHF_G2PHF1 0x02
12122 #define _COG2PHF_PHF2 0x04
12123 #define _COG2PHF_G2PHF2 0x04
12124 #define _COG2PHF_PHF3 0x08
12125 #define _COG2PHF_G2PHF3 0x08
12126 #define _COG2PHF_PHF4 0x10
12127 #define _COG2PHF_G2PHF4 0x10
12128 #define _COG2PHF_PHF5 0x20
12129 #define _COG2PHF_G2PHF5 0x20
12131 //==============================================================================
12134 //==============================================================================
12137 extern __at(0x070F) __sfr COG2BLKR
;
12143 unsigned BLKR0
: 1;
12144 unsigned BLKR1
: 1;
12145 unsigned BLKR2
: 1;
12146 unsigned BLKR3
: 1;
12147 unsigned BLKR4
: 1;
12148 unsigned BLKR5
: 1;
12155 unsigned G2BLKR0
: 1;
12156 unsigned G2BLKR1
: 1;
12157 unsigned G2BLKR2
: 1;
12158 unsigned G2BLKR3
: 1;
12159 unsigned G2BLKR4
: 1;
12160 unsigned G2BLKR5
: 1;
12173 unsigned G2BLKR
: 6;
12176 } __COG2BLKRbits_t
;
12178 extern __at(0x070F) volatile __COG2BLKRbits_t COG2BLKRbits
;
12180 #define _COG2BLKR_BLKR0 0x01
12181 #define _COG2BLKR_G2BLKR0 0x01
12182 #define _COG2BLKR_BLKR1 0x02
12183 #define _COG2BLKR_G2BLKR1 0x02
12184 #define _COG2BLKR_BLKR2 0x04
12185 #define _COG2BLKR_G2BLKR2 0x04
12186 #define _COG2BLKR_BLKR3 0x08
12187 #define _COG2BLKR_G2BLKR3 0x08
12188 #define _COG2BLKR_BLKR4 0x10
12189 #define _COG2BLKR_G2BLKR4 0x10
12190 #define _COG2BLKR_BLKR5 0x20
12191 #define _COG2BLKR_G2BLKR5 0x20
12193 //==============================================================================
12196 //==============================================================================
12199 extern __at(0x0710) __sfr COG2BLKF
;
12205 unsigned BLKF0
: 1;
12206 unsigned BLKF1
: 1;
12207 unsigned BLKF2
: 1;
12208 unsigned BLKF3
: 1;
12209 unsigned BLKF4
: 1;
12210 unsigned BLKF5
: 1;
12217 unsigned G2BLKF0
: 1;
12218 unsigned G2BLKF1
: 1;
12219 unsigned G2BLKF2
: 1;
12220 unsigned G2BLKF3
: 1;
12221 unsigned G2BLKF4
: 1;
12222 unsigned G2BLKF5
: 1;
12229 unsigned G2BLKF
: 6;
12238 } __COG2BLKFbits_t
;
12240 extern __at(0x0710) volatile __COG2BLKFbits_t COG2BLKFbits
;
12242 #define _COG2BLKF_BLKF0 0x01
12243 #define _COG2BLKF_G2BLKF0 0x01
12244 #define _COG2BLKF_BLKF1 0x02
12245 #define _COG2BLKF_G2BLKF1 0x02
12246 #define _COG2BLKF_BLKF2 0x04
12247 #define _COG2BLKF_G2BLKF2 0x04
12248 #define _COG2BLKF_BLKF3 0x08
12249 #define _COG2BLKF_G2BLKF3 0x08
12250 #define _COG2BLKF_BLKF4 0x10
12251 #define _COG2BLKF_G2BLKF4 0x10
12252 #define _COG2BLKF_BLKF5 0x20
12253 #define _COG2BLKF_G2BLKF5 0x20
12255 //==============================================================================
12258 //==============================================================================
12261 extern __at(0x0711) __sfr COG2DBR
;
12279 unsigned G2DBR0
: 1;
12280 unsigned G2DBR1
: 1;
12281 unsigned G2DBR2
: 1;
12282 unsigned G2DBR3
: 1;
12283 unsigned G2DBR4
: 1;
12284 unsigned G2DBR5
: 1;
12297 unsigned G2DBR
: 6;
12302 extern __at(0x0711) volatile __COG2DBRbits_t COG2DBRbits
;
12304 #define _COG2DBR_DBR0 0x01
12305 #define _COG2DBR_G2DBR0 0x01
12306 #define _COG2DBR_DBR1 0x02
12307 #define _COG2DBR_G2DBR1 0x02
12308 #define _COG2DBR_DBR2 0x04
12309 #define _COG2DBR_G2DBR2 0x04
12310 #define _COG2DBR_DBR3 0x08
12311 #define _COG2DBR_G2DBR3 0x08
12312 #define _COG2DBR_DBR4 0x10
12313 #define _COG2DBR_G2DBR4 0x10
12314 #define _COG2DBR_DBR5 0x20
12315 #define _COG2DBR_G2DBR5 0x20
12317 //==============================================================================
12320 //==============================================================================
12323 extern __at(0x0712) __sfr COG2DBF
;
12341 unsigned G2DBF0
: 1;
12342 unsigned G2DBF1
: 1;
12343 unsigned G2DBF2
: 1;
12344 unsigned G2DBF3
: 1;
12345 unsigned G2DBF4
: 1;
12346 unsigned G2DBF5
: 1;
12359 unsigned G2DBF
: 6;
12364 extern __at(0x0712) volatile __COG2DBFbits_t COG2DBFbits
;
12366 #define _COG2DBF_DBF0 0x01
12367 #define _COG2DBF_G2DBF0 0x01
12368 #define _COG2DBF_DBF1 0x02
12369 #define _COG2DBF_G2DBF1 0x02
12370 #define _COG2DBF_DBF2 0x04
12371 #define _COG2DBF_G2DBF2 0x04
12372 #define _COG2DBF_DBF3 0x08
12373 #define _COG2DBF_G2DBF3 0x08
12374 #define _COG2DBF_DBF4 0x10
12375 #define _COG2DBF_G2DBF4 0x10
12376 #define _COG2DBF_DBF5 0x20
12377 #define _COG2DBF_G2DBF5 0x20
12379 //==============================================================================
12382 //==============================================================================
12385 extern __at(0x0713) __sfr COG2CON0
;
12403 unsigned G2MD0
: 1;
12404 unsigned G2MD1
: 1;
12405 unsigned G2MD2
: 1;
12406 unsigned G2CS0
: 1;
12407 unsigned G2CS1
: 1;
12438 } __COG2CON0bits_t
;
12440 extern __at(0x0713) volatile __COG2CON0bits_t COG2CON0bits
;
12442 #define _COG2CON0_MD0 0x01
12443 #define _COG2CON0_G2MD0 0x01
12444 #define _COG2CON0_MD1 0x02
12445 #define _COG2CON0_G2MD1 0x02
12446 #define _COG2CON0_MD2 0x04
12447 #define _COG2CON0_G2MD2 0x04
12448 #define _COG2CON0_CS0 0x08
12449 #define _COG2CON0_G2CS0 0x08
12450 #define _COG2CON0_CS1 0x10
12451 #define _COG2CON0_G2CS1 0x10
12452 #define _COG2CON0_LD 0x40
12453 #define _COG2CON0_G2LD 0x40
12454 #define _COG2CON0_EN 0x80
12455 #define _COG2CON0_G2EN 0x80
12457 //==============================================================================
12460 //==============================================================================
12463 extern __at(0x0714) __sfr COG2CON1
;
12481 unsigned G2POLA
: 1;
12482 unsigned G2POLB
: 1;
12483 unsigned G2POLC
: 1;
12484 unsigned G2POLD
: 1;
12487 unsigned G2FDBS
: 1;
12488 unsigned G2RDBS
: 1;
12490 } __COG2CON1bits_t
;
12492 extern __at(0x0714) volatile __COG2CON1bits_t COG2CON1bits
;
12494 #define _COG2CON1_POLA 0x01
12495 #define _COG2CON1_G2POLA 0x01
12496 #define _COG2CON1_POLB 0x02
12497 #define _COG2CON1_G2POLB 0x02
12498 #define _COG2CON1_POLC 0x04
12499 #define _COG2CON1_G2POLC 0x04
12500 #define _COG2CON1_POLD 0x08
12501 #define _COG2CON1_G2POLD 0x08
12502 #define _COG2CON1_FDBS 0x40
12503 #define _COG2CON1_G2FDBS 0x40
12504 #define _COG2CON1_RDBS 0x80
12505 #define _COG2CON1_G2RDBS 0x80
12507 //==============================================================================
12510 //==============================================================================
12513 extern __at(0x0715) __sfr COG2RIS0
;
12531 unsigned G2RIS0
: 1;
12532 unsigned G2RIS1
: 1;
12533 unsigned G2RIS2
: 1;
12534 unsigned G2RIS3
: 1;
12535 unsigned G2RIS4
: 1;
12536 unsigned G2RIS5
: 1;
12537 unsigned G2RIS6
: 1;
12538 unsigned G2RIS7
: 1;
12540 } __COG2RIS0bits_t
;
12542 extern __at(0x0715) volatile __COG2RIS0bits_t COG2RIS0bits
;
12544 #define _COG2RIS0_RIS0 0x01
12545 #define _COG2RIS0_G2RIS0 0x01
12546 #define _COG2RIS0_RIS1 0x02
12547 #define _COG2RIS0_G2RIS1 0x02
12548 #define _COG2RIS0_RIS2 0x04
12549 #define _COG2RIS0_G2RIS2 0x04
12550 #define _COG2RIS0_RIS3 0x08
12551 #define _COG2RIS0_G2RIS3 0x08
12552 #define _COG2RIS0_RIS4 0x10
12553 #define _COG2RIS0_G2RIS4 0x10
12554 #define _COG2RIS0_RIS5 0x20
12555 #define _COG2RIS0_G2RIS5 0x20
12556 #define _COG2RIS0_RIS6 0x40
12557 #define _COG2RIS0_G2RIS6 0x40
12558 #define _COG2RIS0_RIS7 0x80
12559 #define _COG2RIS0_G2RIS7 0x80
12561 //==============================================================================
12564 //==============================================================================
12567 extern __at(0x0716) __sfr COG2RIS1
;
12575 unsigned RIS10
: 1;
12576 unsigned RIS11
: 1;
12577 unsigned RIS12
: 1;
12578 unsigned RIS13
: 1;
12579 unsigned RIS14
: 1;
12580 unsigned RIS15
: 1;
12585 unsigned G2RIS8
: 1;
12586 unsigned G2RIS9
: 1;
12587 unsigned G2RIS10
: 1;
12588 unsigned G2RIS11
: 1;
12589 unsigned G2RIS12
: 1;
12590 unsigned G2RIS13
: 1;
12591 unsigned G2RIS14
: 1;
12592 unsigned G2RIS15
: 1;
12594 } __COG2RIS1bits_t
;
12596 extern __at(0x0716) volatile __COG2RIS1bits_t COG2RIS1bits
;
12598 #define _COG2RIS1_RIS8 0x01
12599 #define _COG2RIS1_G2RIS8 0x01
12600 #define _COG2RIS1_RIS9 0x02
12601 #define _COG2RIS1_G2RIS9 0x02
12602 #define _COG2RIS1_RIS10 0x04
12603 #define _COG2RIS1_G2RIS10 0x04
12604 #define _COG2RIS1_RIS11 0x08
12605 #define _COG2RIS1_G2RIS11 0x08
12606 #define _COG2RIS1_RIS12 0x10
12607 #define _COG2RIS1_G2RIS12 0x10
12608 #define _COG2RIS1_RIS13 0x20
12609 #define _COG2RIS1_G2RIS13 0x20
12610 #define _COG2RIS1_RIS14 0x40
12611 #define _COG2RIS1_G2RIS14 0x40
12612 #define _COG2RIS1_RIS15 0x80
12613 #define _COG2RIS1_G2RIS15 0x80
12615 //==============================================================================
12618 //==============================================================================
12621 extern __at(0x0717) __sfr COG2RSIM0
;
12627 unsigned RSIM0
: 1;
12628 unsigned RSIM1
: 1;
12629 unsigned RSIM2
: 1;
12630 unsigned RSIM3
: 1;
12631 unsigned RSIM4
: 1;
12632 unsigned RSIM5
: 1;
12633 unsigned RSIM6
: 1;
12634 unsigned RSIM7
: 1;
12639 unsigned G2RSIM0
: 1;
12640 unsigned G2RSIM1
: 1;
12641 unsigned G2RSIM2
: 1;
12642 unsigned G2RSIM3
: 1;
12643 unsigned G2RSIM4
: 1;
12644 unsigned G2RSIM5
: 1;
12645 unsigned G2RSIM6
: 1;
12646 unsigned G2RSIM7
: 1;
12648 } __COG2RSIM0bits_t
;
12650 extern __at(0x0717) volatile __COG2RSIM0bits_t COG2RSIM0bits
;
12652 #define _COG2RSIM0_RSIM0 0x01
12653 #define _COG2RSIM0_G2RSIM0 0x01
12654 #define _COG2RSIM0_RSIM1 0x02
12655 #define _COG2RSIM0_G2RSIM1 0x02
12656 #define _COG2RSIM0_RSIM2 0x04
12657 #define _COG2RSIM0_G2RSIM2 0x04
12658 #define _COG2RSIM0_RSIM3 0x08
12659 #define _COG2RSIM0_G2RSIM3 0x08
12660 #define _COG2RSIM0_RSIM4 0x10
12661 #define _COG2RSIM0_G2RSIM4 0x10
12662 #define _COG2RSIM0_RSIM5 0x20
12663 #define _COG2RSIM0_G2RSIM5 0x20
12664 #define _COG2RSIM0_RSIM6 0x40
12665 #define _COG2RSIM0_G2RSIM6 0x40
12666 #define _COG2RSIM0_RSIM7 0x80
12667 #define _COG2RSIM0_G2RSIM7 0x80
12669 //==============================================================================
12672 //==============================================================================
12675 extern __at(0x0718) __sfr COG2RSIM1
;
12681 unsigned RSIM8
: 1;
12682 unsigned RSIM9
: 1;
12683 unsigned RSIM10
: 1;
12684 unsigned RSIM11
: 1;
12685 unsigned RSIM12
: 1;
12686 unsigned RSIM13
: 1;
12687 unsigned RSIM14
: 1;
12688 unsigned RSIM15
: 1;
12693 unsigned G2RSIM8
: 1;
12694 unsigned G2RSIM9
: 1;
12695 unsigned G2RSIM10
: 1;
12696 unsigned G2RSIM11
: 1;
12697 unsigned G2RSIM12
: 1;
12698 unsigned G2RSIM13
: 1;
12699 unsigned G2RSIM14
: 1;
12700 unsigned G2RSIM15
: 1;
12702 } __COG2RSIM1bits_t
;
12704 extern __at(0x0718) volatile __COG2RSIM1bits_t COG2RSIM1bits
;
12706 #define _COG2RSIM1_RSIM8 0x01
12707 #define _COG2RSIM1_G2RSIM8 0x01
12708 #define _COG2RSIM1_RSIM9 0x02
12709 #define _COG2RSIM1_G2RSIM9 0x02
12710 #define _COG2RSIM1_RSIM10 0x04
12711 #define _COG2RSIM1_G2RSIM10 0x04
12712 #define _COG2RSIM1_RSIM11 0x08
12713 #define _COG2RSIM1_G2RSIM11 0x08
12714 #define _COG2RSIM1_RSIM12 0x10
12715 #define _COG2RSIM1_G2RSIM12 0x10
12716 #define _COG2RSIM1_RSIM13 0x20
12717 #define _COG2RSIM1_G2RSIM13 0x20
12718 #define _COG2RSIM1_RSIM14 0x40
12719 #define _COG2RSIM1_G2RSIM14 0x40
12720 #define _COG2RSIM1_RSIM15 0x80
12721 #define _COG2RSIM1_G2RSIM15 0x80
12723 //==============================================================================
12726 //==============================================================================
12729 extern __at(0x0719) __sfr COG2FIS0
;
12747 unsigned G2FIS0
: 1;
12748 unsigned G2FIS1
: 1;
12749 unsigned G2FIS2
: 1;
12750 unsigned G2FIS3
: 1;
12751 unsigned G2FIS4
: 1;
12752 unsigned G2FIS5
: 1;
12753 unsigned G2FIS6
: 1;
12754 unsigned G2FIS7
: 1;
12756 } __COG2FIS0bits_t
;
12758 extern __at(0x0719) volatile __COG2FIS0bits_t COG2FIS0bits
;
12760 #define _COG2FIS0_FIS0 0x01
12761 #define _COG2FIS0_G2FIS0 0x01
12762 #define _COG2FIS0_FIS1 0x02
12763 #define _COG2FIS0_G2FIS1 0x02
12764 #define _COG2FIS0_FIS2 0x04
12765 #define _COG2FIS0_G2FIS2 0x04
12766 #define _COG2FIS0_FIS3 0x08
12767 #define _COG2FIS0_G2FIS3 0x08
12768 #define _COG2FIS0_FIS4 0x10
12769 #define _COG2FIS0_G2FIS4 0x10
12770 #define _COG2FIS0_FIS5 0x20
12771 #define _COG2FIS0_G2FIS5 0x20
12772 #define _COG2FIS0_FIS6 0x40
12773 #define _COG2FIS0_G2FIS6 0x40
12774 #define _COG2FIS0_FIS7 0x80
12775 #define _COG2FIS0_G2FIS7 0x80
12777 //==============================================================================
12780 //==============================================================================
12783 extern __at(0x071A) __sfr COG2FIS1
;
12791 unsigned FIS10
: 1;
12792 unsigned FIS11
: 1;
12793 unsigned FIS12
: 1;
12794 unsigned FIS13
: 1;
12795 unsigned FIS14
: 1;
12796 unsigned FIS15
: 1;
12801 unsigned G2FIS8
: 1;
12802 unsigned G2FIS9
: 1;
12803 unsigned G2FIS10
: 1;
12804 unsigned G2FIS11
: 1;
12805 unsigned G2FIS12
: 1;
12806 unsigned G2FIS13
: 1;
12807 unsigned G2FIS14
: 1;
12808 unsigned G2FIS15
: 1;
12810 } __COG2FIS1bits_t
;
12812 extern __at(0x071A) volatile __COG2FIS1bits_t COG2FIS1bits
;
12814 #define _COG2FIS1_FIS8 0x01
12815 #define _COG2FIS1_G2FIS8 0x01
12816 #define _COG2FIS1_FIS9 0x02
12817 #define _COG2FIS1_G2FIS9 0x02
12818 #define _COG2FIS1_FIS10 0x04
12819 #define _COG2FIS1_G2FIS10 0x04
12820 #define _COG2FIS1_FIS11 0x08
12821 #define _COG2FIS1_G2FIS11 0x08
12822 #define _COG2FIS1_FIS12 0x10
12823 #define _COG2FIS1_G2FIS12 0x10
12824 #define _COG2FIS1_FIS13 0x20
12825 #define _COG2FIS1_G2FIS13 0x20
12826 #define _COG2FIS1_FIS14 0x40
12827 #define _COG2FIS1_G2FIS14 0x40
12828 #define _COG2FIS1_FIS15 0x80
12829 #define _COG2FIS1_G2FIS15 0x80
12831 //==============================================================================
12834 //==============================================================================
12837 extern __at(0x071B) __sfr COG2FSIM0
;
12843 unsigned FSIM0
: 1;
12844 unsigned FSIM1
: 1;
12845 unsigned FSIM2
: 1;
12846 unsigned FSIM3
: 1;
12847 unsigned FSIM4
: 1;
12848 unsigned FSIM5
: 1;
12849 unsigned FSIM6
: 1;
12850 unsigned FSIM7
: 1;
12855 unsigned G2FSIM0
: 1;
12856 unsigned G2FSIM1
: 1;
12857 unsigned G2FSIM2
: 1;
12858 unsigned G2FSIM3
: 1;
12859 unsigned G2FSIM4
: 1;
12860 unsigned G2FSIM5
: 1;
12861 unsigned G2FSIM6
: 1;
12862 unsigned G2FSIM7
: 1;
12864 } __COG2FSIM0bits_t
;
12866 extern __at(0x071B) volatile __COG2FSIM0bits_t COG2FSIM0bits
;
12868 #define _COG2FSIM0_FSIM0 0x01
12869 #define _COG2FSIM0_G2FSIM0 0x01
12870 #define _COG2FSIM0_FSIM1 0x02
12871 #define _COG2FSIM0_G2FSIM1 0x02
12872 #define _COG2FSIM0_FSIM2 0x04
12873 #define _COG2FSIM0_G2FSIM2 0x04
12874 #define _COG2FSIM0_FSIM3 0x08
12875 #define _COG2FSIM0_G2FSIM3 0x08
12876 #define _COG2FSIM0_FSIM4 0x10
12877 #define _COG2FSIM0_G2FSIM4 0x10
12878 #define _COG2FSIM0_FSIM5 0x20
12879 #define _COG2FSIM0_G2FSIM5 0x20
12880 #define _COG2FSIM0_FSIM6 0x40
12881 #define _COG2FSIM0_G2FSIM6 0x40
12882 #define _COG2FSIM0_FSIM7 0x80
12883 #define _COG2FSIM0_G2FSIM7 0x80
12885 //==============================================================================
12888 //==============================================================================
12891 extern __at(0x071C) __sfr COG2FSIM1
;
12897 unsigned FSIM8
: 1;
12898 unsigned FSIM9
: 1;
12899 unsigned FSIM10
: 1;
12900 unsigned FSIM11
: 1;
12901 unsigned FSIM12
: 1;
12902 unsigned FSIM13
: 1;
12903 unsigned FSIM14
: 1;
12904 unsigned FSIM15
: 1;
12909 unsigned G2FSIM8
: 1;
12910 unsigned G2FSIM9
: 1;
12911 unsigned G2FSIM10
: 1;
12912 unsigned G2FSIM11
: 1;
12913 unsigned G2FSIM12
: 1;
12914 unsigned G2FSIM13
: 1;
12915 unsigned G2FSIM14
: 1;
12916 unsigned G2FSIM15
: 1;
12918 } __COG2FSIM1bits_t
;
12920 extern __at(0x071C) volatile __COG2FSIM1bits_t COG2FSIM1bits
;
12922 #define _COG2FSIM1_FSIM8 0x01
12923 #define _COG2FSIM1_G2FSIM8 0x01
12924 #define _COG2FSIM1_FSIM9 0x02
12925 #define _COG2FSIM1_G2FSIM9 0x02
12926 #define _COG2FSIM1_FSIM10 0x04
12927 #define _COG2FSIM1_G2FSIM10 0x04
12928 #define _COG2FSIM1_FSIM11 0x08
12929 #define _COG2FSIM1_G2FSIM11 0x08
12930 #define _COG2FSIM1_FSIM12 0x10
12931 #define _COG2FSIM1_G2FSIM12 0x10
12932 #define _COG2FSIM1_FSIM13 0x20
12933 #define _COG2FSIM1_G2FSIM13 0x20
12934 #define _COG2FSIM1_FSIM14 0x40
12935 #define _COG2FSIM1_G2FSIM14 0x40
12936 #define _COG2FSIM1_FSIM15 0x80
12937 #define _COG2FSIM1_G2FSIM15 0x80
12939 //==============================================================================
12942 //==============================================================================
12945 extern __at(0x071D) __sfr COG2ASD0
;
12953 unsigned ASDAC0
: 1;
12954 unsigned ASDAC1
: 1;
12955 unsigned ASDBD0
: 1;
12956 unsigned ASDBD1
: 1;
12957 unsigned ASREN
: 1;
12965 unsigned G2ASDAC0
: 1;
12966 unsigned G2ASDAC1
: 1;
12967 unsigned G2ASDBD0
: 1;
12968 unsigned G2ASDBD1
: 1;
12969 unsigned ARSEN
: 1;
12970 unsigned G2ASE
: 1;
12981 unsigned G2ARSEN
: 1;
12993 unsigned G2ASREN
: 1;
13000 unsigned ASDAC
: 2;
13007 unsigned G2ASDAC
: 2;
13014 unsigned G2ASDBD
: 2;
13021 unsigned ASDBD
: 2;
13024 } __COG2ASD0bits_t
;
13026 extern __at(0x071D) volatile __COG2ASD0bits_t COG2ASD0bits
;
13028 #define _COG2ASD0_ASDAC0 0x04
13029 #define _COG2ASD0_G2ASDAC0 0x04
13030 #define _COG2ASD0_ASDAC1 0x08
13031 #define _COG2ASD0_G2ASDAC1 0x08
13032 #define _COG2ASD0_ASDBD0 0x10
13033 #define _COG2ASD0_G2ASDBD0 0x10
13034 #define _COG2ASD0_ASDBD1 0x20
13035 #define _COG2ASD0_G2ASDBD1 0x20
13036 #define _COG2ASD0_ASREN 0x40
13037 #define _COG2ASD0_ARSEN 0x40
13038 #define _COG2ASD0_G2ARSEN 0x40
13039 #define _COG2ASD0_G2ASREN 0x40
13040 #define _COG2ASD0_ASE 0x80
13041 #define _COG2ASD0_G2ASE 0x80
13043 //==============================================================================
13046 //==============================================================================
13049 extern __at(0x071E) __sfr COG2ASD1
;
13067 unsigned G2AS0E
: 1;
13068 unsigned G2AS1E
: 1;
13069 unsigned G2AS2E
: 1;
13070 unsigned G2AS3E
: 1;
13071 unsigned G2AS4E
: 1;
13072 unsigned G2AS5E
: 1;
13073 unsigned G2AS6E
: 1;
13074 unsigned G2AS7E
: 1;
13076 } __COG2ASD1bits_t
;
13078 extern __at(0x071E) volatile __COG2ASD1bits_t COG2ASD1bits
;
13080 #define _COG2ASD1_AS0E 0x01
13081 #define _COG2ASD1_G2AS0E 0x01
13082 #define _COG2ASD1_AS1E 0x02
13083 #define _COG2ASD1_G2AS1E 0x02
13084 #define _COG2ASD1_AS2E 0x04
13085 #define _COG2ASD1_G2AS2E 0x04
13086 #define _COG2ASD1_AS3E 0x08
13087 #define _COG2ASD1_G2AS3E 0x08
13088 #define _COG2ASD1_AS4E 0x10
13089 #define _COG2ASD1_G2AS4E 0x10
13090 #define _COG2ASD1_AS5E 0x20
13091 #define _COG2ASD1_G2AS5E 0x20
13092 #define _COG2ASD1_AS6E 0x40
13093 #define _COG2ASD1_G2AS6E 0x40
13094 #define _COG2ASD1_AS7E 0x80
13095 #define _COG2ASD1_G2AS7E 0x80
13097 //==============================================================================
13100 //==============================================================================
13103 extern __at(0x071F) __sfr COG2STR
;
13113 unsigned SDATA
: 1;
13114 unsigned SDATB
: 1;
13115 unsigned SDATC
: 1;
13116 unsigned SDATD
: 1;
13121 unsigned G2STRA
: 1;
13122 unsigned G2STRB
: 1;
13123 unsigned G2STRC
: 1;
13124 unsigned G2STRD
: 1;
13125 unsigned G2SDATA
: 1;
13126 unsigned G2SDATB
: 1;
13127 unsigned G2SDATC
: 1;
13128 unsigned G2SDATD
: 1;
13132 extern __at(0x071F) volatile __COG2STRbits_t COG2STRbits
;
13134 #define _COG2STR_STRA 0x01
13135 #define _COG2STR_G2STRA 0x01
13136 #define _COG2STR_STRB 0x02
13137 #define _COG2STR_G2STRB 0x02
13138 #define _COG2STR_STRC 0x04
13139 #define _COG2STR_G2STRC 0x04
13140 #define _COG2STR_STRD 0x08
13141 #define _COG2STR_G2STRD 0x08
13142 #define _COG2STR_SDATA 0x10
13143 #define _COG2STR_G2SDATA 0x10
13144 #define _COG2STR_SDATB 0x20
13145 #define _COG2STR_G2SDATB 0x20
13146 #define _COG2STR_SDATC 0x40
13147 #define _COG2STR_G2SDATC 0x40
13148 #define _COG2STR_SDATD 0x80
13149 #define _COG2STR_G2SDATD 0x80
13151 //==============================================================================
13154 //==============================================================================
13157 extern __at(0x078E) __sfr PRG1RTSS
;
13163 unsigned RTSS0
: 1;
13164 unsigned RTSS1
: 1;
13165 unsigned RTSS2
: 1;
13166 unsigned RTSS3
: 1;
13175 unsigned RG1RTSS0
: 1;
13176 unsigned RG1RTSS1
: 1;
13177 unsigned RG1RTSS2
: 1;
13178 unsigned RG1RTSS3
: 1;
13187 unsigned RG1RTSS
: 4;
13196 } __PRG1RTSSbits_t
;
13198 extern __at(0x078E) volatile __PRG1RTSSbits_t PRG1RTSSbits
;
13200 #define _RTSS0 0x01
13201 #define _RG1RTSS0 0x01
13202 #define _RTSS1 0x02
13203 #define _RG1RTSS1 0x02
13204 #define _RTSS2 0x04
13205 #define _RG1RTSS2 0x04
13206 #define _RTSS3 0x08
13207 #define _RG1RTSS3 0x08
13209 //==============================================================================
13212 //==============================================================================
13215 extern __at(0x078F) __sfr PRG1FTSS
;
13221 unsigned FTSS0
: 1;
13222 unsigned FTSS1
: 1;
13223 unsigned FTSS2
: 1;
13224 unsigned FTSS3
: 1;
13233 unsigned RG1FTSS0
: 1;
13234 unsigned RG1FTSS1
: 1;
13235 unsigned RG1FTSS2
: 1;
13236 unsigned RG1FTSS3
: 1;
13251 unsigned RG1FTSS
: 4;
13254 } __PRG1FTSSbits_t
;
13256 extern __at(0x078F) volatile __PRG1FTSSbits_t PRG1FTSSbits
;
13258 #define _FTSS0 0x01
13259 #define _RG1FTSS0 0x01
13260 #define _FTSS1 0x02
13261 #define _RG1FTSS1 0x02
13262 #define _FTSS2 0x04
13263 #define _RG1FTSS2 0x04
13264 #define _FTSS3 0x08
13265 #define _RG1FTSS3 0x08
13267 //==============================================================================
13270 //==============================================================================
13273 extern __at(0x0790) __sfr PRG1INS
;
13291 unsigned RG1INS0
: 1;
13292 unsigned RG1INS1
: 1;
13293 unsigned RG1INS2
: 1;
13294 unsigned RG1INS3
: 1;
13309 unsigned RG1INS
: 4;
13314 extern __at(0x0790) volatile __PRG1INSbits_t PRG1INSbits
;
13317 #define _RG1INS0 0x01
13319 #define _RG1INS1 0x02
13321 #define _RG1INS2 0x04
13323 #define _RG1INS3 0x08
13325 //==============================================================================
13328 //==============================================================================
13331 extern __at(0x0791) __sfr PRG1CON0
;
13339 unsigned MODE0
: 1;
13340 unsigned MODE1
: 1;
13349 unsigned RG1GO
: 1;
13350 unsigned RG1OS
: 1;
13351 unsigned RG1MODE0
: 1;
13352 unsigned RG1MODE1
: 1;
13353 unsigned RG1REDG
: 1;
13354 unsigned RG1FEDG
: 1;
13356 unsigned RG1EN
: 1;
13369 unsigned RG1MODE
: 2;
13372 } __PRG1CON0bits_t
;
13374 extern __at(0x0791) volatile __PRG1CON0bits_t PRG1CON0bits
;
13376 #define _PRG1CON0_GO 0x01
13377 #define _PRG1CON0_RG1GO 0x01
13378 #define _PRG1CON0_OS 0x02
13379 #define _PRG1CON0_RG1OS 0x02
13380 #define _PRG1CON0_MODE0 0x04
13381 #define _PRG1CON0_RG1MODE0 0x04
13382 #define _PRG1CON0_MODE1 0x08
13383 #define _PRG1CON0_RG1MODE1 0x08
13384 #define _PRG1CON0_REDG 0x10
13385 #define _PRG1CON0_RG1REDG 0x10
13386 #define _PRG1CON0_FEDG 0x20
13387 #define _PRG1CON0_RG1FEDG 0x20
13388 #define _PRG1CON0_EN 0x80
13389 #define _PRG1CON0_RG1EN 0x80
13391 //==============================================================================
13394 //==============================================================================
13397 extern __at(0x0792) __sfr PRG1CON1
;
13415 unsigned RG1RPOL
: 1;
13416 unsigned RG1FPOL
: 1;
13417 unsigned RG1RDY
: 1;
13424 } __PRG1CON1bits_t
;
13426 extern __at(0x0792) volatile __PRG1CON1bits_t PRG1CON1bits
;
13429 #define _RG1RPOL 0x01
13431 #define _RG1FPOL 0x02
13433 #define _RG1RDY 0x04
13435 //==============================================================================
13438 //==============================================================================
13441 extern __at(0x0793) __sfr PRG1CON2
;
13447 unsigned ISET0
: 1;
13448 unsigned ISET1
: 1;
13449 unsigned ISET2
: 1;
13450 unsigned ISET3
: 1;
13451 unsigned ISET4
: 1;
13459 unsigned RG1ISET0
: 1;
13460 unsigned RG1ISET1
: 1;
13461 unsigned RG1ISET2
: 1;
13462 unsigned RG1ISET3
: 1;
13463 unsigned RG1ISET4
: 1;
13471 unsigned RG1ISET
: 5;
13480 } __PRG1CON2bits_t
;
13482 extern __at(0x0793) volatile __PRG1CON2bits_t PRG1CON2bits
;
13484 #define _ISET0 0x01
13485 #define _RG1ISET0 0x01
13486 #define _ISET1 0x02
13487 #define _RG1ISET1 0x02
13488 #define _ISET2 0x04
13489 #define _RG1ISET2 0x04
13490 #define _ISET3 0x08
13491 #define _RG1ISET3 0x08
13492 #define _ISET4 0x10
13493 #define _RG1ISET4 0x10
13495 //==============================================================================
13498 //==============================================================================
13501 extern __at(0x0794) __sfr PRG2RTSS
;
13507 unsigned RTSS0
: 1;
13508 unsigned RTSS1
: 1;
13509 unsigned RTSS2
: 1;
13510 unsigned RTSS3
: 1;
13519 unsigned RG2RTSS0
: 1;
13520 unsigned RG2RTSS1
: 1;
13521 unsigned RG2RTSS2
: 1;
13522 unsigned RG2RTSS3
: 1;
13531 unsigned RG2RTSS
: 4;
13540 } __PRG2RTSSbits_t
;
13542 extern __at(0x0794) volatile __PRG2RTSSbits_t PRG2RTSSbits
;
13544 #define _PRG2RTSS_RTSS0 0x01
13545 #define _PRG2RTSS_RG2RTSS0 0x01
13546 #define _PRG2RTSS_RTSS1 0x02
13547 #define _PRG2RTSS_RG2RTSS1 0x02
13548 #define _PRG2RTSS_RTSS2 0x04
13549 #define _PRG2RTSS_RG2RTSS2 0x04
13550 #define _PRG2RTSS_RTSS3 0x08
13551 #define _PRG2RTSS_RG2RTSS3 0x08
13553 //==============================================================================
13556 //==============================================================================
13559 extern __at(0x0795) __sfr PRG2FTSS
;
13565 unsigned FTSS0
: 1;
13566 unsigned FTSS1
: 1;
13567 unsigned FTSS2
: 1;
13568 unsigned FTSS3
: 1;
13577 unsigned RG2FTSS0
: 1;
13578 unsigned RG2FTSS1
: 1;
13579 unsigned RG2FTSS2
: 1;
13580 unsigned RG2FTSS3
: 1;
13595 unsigned RG2FTSS
: 4;
13598 } __PRG2FTSSbits_t
;
13600 extern __at(0x0795) volatile __PRG2FTSSbits_t PRG2FTSSbits
;
13602 #define _PRG2FTSS_FTSS0 0x01
13603 #define _PRG2FTSS_RG2FTSS0 0x01
13604 #define _PRG2FTSS_FTSS1 0x02
13605 #define _PRG2FTSS_RG2FTSS1 0x02
13606 #define _PRG2FTSS_FTSS2 0x04
13607 #define _PRG2FTSS_RG2FTSS2 0x04
13608 #define _PRG2FTSS_FTSS3 0x08
13609 #define _PRG2FTSS_RG2FTSS3 0x08
13611 //==============================================================================
13614 //==============================================================================
13617 extern __at(0x0796) __sfr PRG2INS
;
13635 unsigned RG2INS0
: 1;
13636 unsigned RG2INS1
: 1;
13637 unsigned RG2INS2
: 1;
13638 unsigned RG2INS3
: 1;
13647 unsigned RG2INS
: 4;
13658 extern __at(0x0796) volatile __PRG2INSbits_t PRG2INSbits
;
13660 #define _PRG2INS_INS0 0x01
13661 #define _PRG2INS_RG2INS0 0x01
13662 #define _PRG2INS_INS1 0x02
13663 #define _PRG2INS_RG2INS1 0x02
13664 #define _PRG2INS_INS2 0x04
13665 #define _PRG2INS_RG2INS2 0x04
13666 #define _PRG2INS_INS3 0x08
13667 #define _PRG2INS_RG2INS3 0x08
13669 //==============================================================================
13672 //==============================================================================
13675 extern __at(0x0797) __sfr PRG2CON0
;
13683 unsigned MODE0
: 1;
13684 unsigned MODE1
: 1;
13693 unsigned RG2GO
: 1;
13694 unsigned RG2OS
: 1;
13695 unsigned RG2MODE0
: 1;
13696 unsigned RG2MODE1
: 1;
13697 unsigned RG2REDG
: 1;
13698 unsigned RG2FEDG
: 1;
13700 unsigned RG2EN
: 1;
13713 unsigned RG2MODE
: 2;
13716 } __PRG2CON0bits_t
;
13718 extern __at(0x0797) volatile __PRG2CON0bits_t PRG2CON0bits
;
13720 #define _PRG2CON0_GO 0x01
13721 #define _PRG2CON0_RG2GO 0x01
13722 #define _PRG2CON0_OS 0x02
13723 #define _PRG2CON0_RG2OS 0x02
13724 #define _PRG2CON0_MODE0 0x04
13725 #define _PRG2CON0_RG2MODE0 0x04
13726 #define _PRG2CON0_MODE1 0x08
13727 #define _PRG2CON0_RG2MODE1 0x08
13728 #define _PRG2CON0_REDG 0x10
13729 #define _PRG2CON0_RG2REDG 0x10
13730 #define _PRG2CON0_FEDG 0x20
13731 #define _PRG2CON0_RG2FEDG 0x20
13732 #define _PRG2CON0_EN 0x80
13733 #define _PRG2CON0_RG2EN 0x80
13735 //==============================================================================
13738 //==============================================================================
13741 extern __at(0x0798) __sfr PRG2CON1
;
13759 unsigned RG2RPOL
: 1;
13760 unsigned RG2FPOL
: 1;
13761 unsigned RG2RDY
: 1;
13768 } __PRG2CON1bits_t
;
13770 extern __at(0x0798) volatile __PRG2CON1bits_t PRG2CON1bits
;
13772 #define _PRG2CON1_RPOL 0x01
13773 #define _PRG2CON1_RG2RPOL 0x01
13774 #define _PRG2CON1_FPOL 0x02
13775 #define _PRG2CON1_RG2FPOL 0x02
13776 #define _PRG2CON1_RDY 0x04
13777 #define _PRG2CON1_RG2RDY 0x04
13779 //==============================================================================
13782 //==============================================================================
13785 extern __at(0x0799) __sfr PRG2CON2
;
13791 unsigned ISET0
: 1;
13792 unsigned ISET1
: 1;
13793 unsigned ISET2
: 1;
13794 unsigned ISET3
: 1;
13795 unsigned ISET4
: 1;
13803 unsigned RG2ISET0
: 1;
13804 unsigned RG2ISET1
: 1;
13805 unsigned RG2ISET2
: 1;
13806 unsigned RG2ISET3
: 1;
13807 unsigned RG2ISET4
: 1;
13821 unsigned RG2ISET
: 5;
13824 } __PRG2CON2bits_t
;
13826 extern __at(0x0799) volatile __PRG2CON2bits_t PRG2CON2bits
;
13828 #define _PRG2CON2_ISET0 0x01
13829 #define _PRG2CON2_RG2ISET0 0x01
13830 #define _PRG2CON2_ISET1 0x02
13831 #define _PRG2CON2_RG2ISET1 0x02
13832 #define _PRG2CON2_ISET2 0x04
13833 #define _PRG2CON2_RG2ISET2 0x04
13834 #define _PRG2CON2_ISET3 0x08
13835 #define _PRG2CON2_RG2ISET3 0x08
13836 #define _PRG2CON2_ISET4 0x10
13837 #define _PRG2CON2_RG2ISET4 0x10
13839 //==============================================================================
13842 //==============================================================================
13845 extern __at(0x079A) __sfr PRG3RTSS
;
13851 unsigned RTSS0
: 1;
13852 unsigned RTSS1
: 1;
13853 unsigned RTSS2
: 1;
13854 unsigned RTSS3
: 1;
13863 unsigned RG3RTSS0
: 1;
13864 unsigned RG3RTSS1
: 1;
13865 unsigned RG3RTSS2
: 1;
13866 unsigned RG3RTSS3
: 1;
13875 unsigned RG3RTSS
: 4;
13884 } __PRG3RTSSbits_t
;
13886 extern __at(0x079A) volatile __PRG3RTSSbits_t PRG3RTSSbits
;
13888 #define _PRG3RTSS_RTSS0 0x01
13889 #define _PRG3RTSS_RG3RTSS0 0x01
13890 #define _PRG3RTSS_RTSS1 0x02
13891 #define _PRG3RTSS_RG3RTSS1 0x02
13892 #define _PRG3RTSS_RTSS2 0x04
13893 #define _PRG3RTSS_RG3RTSS2 0x04
13894 #define _PRG3RTSS_RTSS3 0x08
13895 #define _PRG3RTSS_RG3RTSS3 0x08
13897 //==============================================================================
13900 //==============================================================================
13903 extern __at(0x079B) __sfr PRG3FTSS
;
13909 unsigned FTSS0
: 1;
13910 unsigned FTSS1
: 1;
13911 unsigned FTSS2
: 1;
13912 unsigned FTSS3
: 1;
13921 unsigned RG3FTSS0
: 1;
13922 unsigned RG3FTSS1
: 1;
13923 unsigned RG3FTSS2
: 1;
13924 unsigned RG3FTSS3
: 1;
13933 unsigned RG3FTSS
: 4;
13942 } __PRG3FTSSbits_t
;
13944 extern __at(0x079B) volatile __PRG3FTSSbits_t PRG3FTSSbits
;
13946 #define _PRG3FTSS_FTSS0 0x01
13947 #define _PRG3FTSS_RG3FTSS0 0x01
13948 #define _PRG3FTSS_FTSS1 0x02
13949 #define _PRG3FTSS_RG3FTSS1 0x02
13950 #define _PRG3FTSS_FTSS2 0x04
13951 #define _PRG3FTSS_RG3FTSS2 0x04
13952 #define _PRG3FTSS_FTSS3 0x08
13953 #define _PRG3FTSS_RG3FTSS3 0x08
13955 //==============================================================================
13958 //==============================================================================
13961 extern __at(0x079C) __sfr PRG3INS
;
13979 unsigned RG3INS0
: 1;
13980 unsigned RG3INS1
: 1;
13981 unsigned RG3INS2
: 1;
13982 unsigned RG3INS3
: 1;
13997 unsigned RG3INS
: 4;
14002 extern __at(0x079C) volatile __PRG3INSbits_t PRG3INSbits
;
14004 #define _PRG3INS_INS0 0x01
14005 #define _PRG3INS_RG3INS0 0x01
14006 #define _PRG3INS_INS1 0x02
14007 #define _PRG3INS_RG3INS1 0x02
14008 #define _PRG3INS_INS2 0x04
14009 #define _PRG3INS_RG3INS2 0x04
14010 #define _PRG3INS_INS3 0x08
14011 #define _PRG3INS_RG3INS3 0x08
14013 //==============================================================================
14016 //==============================================================================
14019 extern __at(0x079D) __sfr PRG3CON0
;
14027 unsigned MODE0
: 1;
14028 unsigned MODE1
: 1;
14037 unsigned RG3GO
: 1;
14038 unsigned RG3OS
: 1;
14039 unsigned RG3MODE0
: 1;
14040 unsigned RG3MODE1
: 1;
14041 unsigned RG3REDG
: 1;
14042 unsigned RG3FEDG
: 1;
14044 unsigned RG3EN
: 1;
14050 unsigned RG3MODE
: 2;
14060 } __PRG3CON0bits_t
;
14062 extern __at(0x079D) volatile __PRG3CON0bits_t PRG3CON0bits
;
14064 #define _PRG3CON0_GO 0x01
14065 #define _PRG3CON0_RG3GO 0x01
14066 #define _PRG3CON0_OS 0x02
14067 #define _PRG3CON0_RG3OS 0x02
14068 #define _PRG3CON0_MODE0 0x04
14069 #define _PRG3CON0_RG3MODE0 0x04
14070 #define _PRG3CON0_MODE1 0x08
14071 #define _PRG3CON0_RG3MODE1 0x08
14072 #define _PRG3CON0_REDG 0x10
14073 #define _PRG3CON0_RG3REDG 0x10
14074 #define _PRG3CON0_FEDG 0x20
14075 #define _PRG3CON0_RG3FEDG 0x20
14076 #define _PRG3CON0_EN 0x80
14077 #define _PRG3CON0_RG3EN 0x80
14079 //==============================================================================
14082 //==============================================================================
14085 extern __at(0x079E) __sfr PRG3CON1
;
14103 unsigned RG3RPOL
: 1;
14104 unsigned RG3FPOL
: 1;
14105 unsigned RG3RDY
: 1;
14112 } __PRG3CON1bits_t
;
14114 extern __at(0x079E) volatile __PRG3CON1bits_t PRG3CON1bits
;
14116 #define _PRG3CON1_RPOL 0x01
14117 #define _PRG3CON1_RG3RPOL 0x01
14118 #define _PRG3CON1_FPOL 0x02
14119 #define _PRG3CON1_RG3FPOL 0x02
14120 #define _PRG3CON1_RDY 0x04
14121 #define _PRG3CON1_RG3RDY 0x04
14123 //==============================================================================
14126 //==============================================================================
14129 extern __at(0x079F) __sfr PRG3CON2
;
14135 unsigned ISET0
: 1;
14136 unsigned ISET1
: 1;
14137 unsigned ISET2
: 1;
14138 unsigned ISET3
: 1;
14139 unsigned ISET4
: 1;
14147 unsigned RG3ISET0
: 1;
14148 unsigned RG3ISET1
: 1;
14149 unsigned RG3ISET2
: 1;
14150 unsigned RG3ISET3
: 1;
14151 unsigned RG3ISET4
: 1;
14165 unsigned RG3ISET
: 5;
14168 } __PRG3CON2bits_t
;
14170 extern __at(0x079F) volatile __PRG3CON2bits_t PRG3CON2bits
;
14172 #define _PRG3CON2_ISET0 0x01
14173 #define _PRG3CON2_RG3ISET0 0x01
14174 #define _PRG3CON2_ISET1 0x02
14175 #define _PRG3CON2_RG3ISET1 0x02
14176 #define _PRG3CON2_ISET2 0x04
14177 #define _PRG3CON2_RG3ISET2 0x04
14178 #define _PRG3CON2_ISET3 0x08
14179 #define _PRG3CON2_RG3ISET3 0x08
14180 #define _PRG3CON2_ISET4 0x10
14181 #define _PRG3CON2_RG3ISET4 0x10
14183 //==============================================================================
14186 //==============================================================================
14189 extern __at(0x080D) __sfr COG3PHR
;
14207 unsigned G3PHR0
: 1;
14208 unsigned G3PHR1
: 1;
14209 unsigned G3PHR2
: 1;
14210 unsigned G3PHR3
: 1;
14211 unsigned G3PHR4
: 1;
14212 unsigned G3PHR5
: 1;
14225 unsigned G3PHR
: 6;
14230 extern __at(0x080D) volatile __COG3PHRbits_t COG3PHRbits
;
14232 #define _COG3PHR_PHR0 0x01
14233 #define _COG3PHR_G3PHR0 0x01
14234 #define _COG3PHR_PHR1 0x02
14235 #define _COG3PHR_G3PHR1 0x02
14236 #define _COG3PHR_PHR2 0x04
14237 #define _COG3PHR_G3PHR2 0x04
14238 #define _COG3PHR_PHR3 0x08
14239 #define _COG3PHR_G3PHR3 0x08
14240 #define _COG3PHR_PHR4 0x10
14241 #define _COG3PHR_G3PHR4 0x10
14242 #define _COG3PHR_PHR5 0x20
14243 #define _COG3PHR_G3PHR5 0x20
14245 //==============================================================================
14248 //==============================================================================
14251 extern __at(0x080E) __sfr COG3PHF
;
14269 unsigned G3PHF0
: 1;
14270 unsigned G3PHF1
: 1;
14271 unsigned G3PHF2
: 1;
14272 unsigned G3PHF3
: 1;
14273 unsigned G3PHF4
: 1;
14274 unsigned G3PHF5
: 1;
14287 unsigned G3PHF
: 6;
14292 extern __at(0x080E) volatile __COG3PHFbits_t COG3PHFbits
;
14294 #define _COG3PHF_PHF0 0x01
14295 #define _COG3PHF_G3PHF0 0x01
14296 #define _COG3PHF_PHF1 0x02
14297 #define _COG3PHF_G3PHF1 0x02
14298 #define _COG3PHF_PHF2 0x04
14299 #define _COG3PHF_G3PHF2 0x04
14300 #define _COG3PHF_PHF3 0x08
14301 #define _COG3PHF_G3PHF3 0x08
14302 #define _COG3PHF_PHF4 0x10
14303 #define _COG3PHF_G3PHF4 0x10
14304 #define _COG3PHF_PHF5 0x20
14305 #define _COG3PHF_G3PHF5 0x20
14307 //==============================================================================
14310 //==============================================================================
14313 extern __at(0x080F) __sfr COG3BLKR
;
14319 unsigned BLKR0
: 1;
14320 unsigned BLKR1
: 1;
14321 unsigned BLKR2
: 1;
14322 unsigned BLKR3
: 1;
14323 unsigned BLKR4
: 1;
14324 unsigned BLKR5
: 1;
14331 unsigned G3BLKR0
: 1;
14332 unsigned G3BLKR1
: 1;
14333 unsigned G3BLKR2
: 1;
14334 unsigned G3BLKR3
: 1;
14335 unsigned G3BLKR4
: 1;
14336 unsigned G3BLKR5
: 1;
14343 unsigned G3BLKR
: 6;
14352 } __COG3BLKRbits_t
;
14354 extern __at(0x080F) volatile __COG3BLKRbits_t COG3BLKRbits
;
14356 #define _COG3BLKR_BLKR0 0x01
14357 #define _COG3BLKR_G3BLKR0 0x01
14358 #define _COG3BLKR_BLKR1 0x02
14359 #define _COG3BLKR_G3BLKR1 0x02
14360 #define _COG3BLKR_BLKR2 0x04
14361 #define _COG3BLKR_G3BLKR2 0x04
14362 #define _COG3BLKR_BLKR3 0x08
14363 #define _COG3BLKR_G3BLKR3 0x08
14364 #define _COG3BLKR_BLKR4 0x10
14365 #define _COG3BLKR_G3BLKR4 0x10
14366 #define _COG3BLKR_BLKR5 0x20
14367 #define _COG3BLKR_G3BLKR5 0x20
14369 //==============================================================================
14372 //==============================================================================
14375 extern __at(0x0810) __sfr COG3BLKF
;
14381 unsigned BLKF0
: 1;
14382 unsigned BLKF1
: 1;
14383 unsigned BLKF2
: 1;
14384 unsigned BLKF3
: 1;
14385 unsigned BLKF4
: 1;
14386 unsigned BLKF5
: 1;
14393 unsigned G3BLKF0
: 1;
14394 unsigned G3BLKF1
: 1;
14395 unsigned G3BLKF2
: 1;
14396 unsigned G3BLKF3
: 1;
14397 unsigned G3BLKF4
: 1;
14398 unsigned G3BLKF5
: 1;
14405 unsigned G3BLKF
: 6;
14414 } __COG3BLKFbits_t
;
14416 extern __at(0x0810) volatile __COG3BLKFbits_t COG3BLKFbits
;
14418 #define _COG3BLKF_BLKF0 0x01
14419 #define _COG3BLKF_G3BLKF0 0x01
14420 #define _COG3BLKF_BLKF1 0x02
14421 #define _COG3BLKF_G3BLKF1 0x02
14422 #define _COG3BLKF_BLKF2 0x04
14423 #define _COG3BLKF_G3BLKF2 0x04
14424 #define _COG3BLKF_BLKF3 0x08
14425 #define _COG3BLKF_G3BLKF3 0x08
14426 #define _COG3BLKF_BLKF4 0x10
14427 #define _COG3BLKF_G3BLKF4 0x10
14428 #define _COG3BLKF_BLKF5 0x20
14429 #define _COG3BLKF_G3BLKF5 0x20
14431 //==============================================================================
14434 //==============================================================================
14437 extern __at(0x0811) __sfr COG3DBR
;
14455 unsigned G3DBR0
: 1;
14456 unsigned G3DBR1
: 1;
14457 unsigned G3DBR2
: 1;
14458 unsigned G3DBR3
: 1;
14459 unsigned G3DBR4
: 1;
14460 unsigned G3DBR5
: 1;
14473 unsigned G3DBR
: 6;
14478 extern __at(0x0811) volatile __COG3DBRbits_t COG3DBRbits
;
14480 #define _COG3DBR_DBR0 0x01
14481 #define _COG3DBR_G3DBR0 0x01
14482 #define _COG3DBR_DBR1 0x02
14483 #define _COG3DBR_G3DBR1 0x02
14484 #define _COG3DBR_DBR2 0x04
14485 #define _COG3DBR_G3DBR2 0x04
14486 #define _COG3DBR_DBR3 0x08
14487 #define _COG3DBR_G3DBR3 0x08
14488 #define _COG3DBR_DBR4 0x10
14489 #define _COG3DBR_G3DBR4 0x10
14490 #define _COG3DBR_DBR5 0x20
14491 #define _COG3DBR_G3DBR5 0x20
14493 //==============================================================================
14496 //==============================================================================
14499 extern __at(0x0812) __sfr COG3DBF
;
14517 unsigned G3DBF0
: 1;
14518 unsigned G3DBF1
: 1;
14519 unsigned G3DBF2
: 1;
14520 unsigned G3DBF3
: 1;
14521 unsigned G3DBF4
: 1;
14522 unsigned G3DBF5
: 1;
14529 unsigned G3DBF
: 6;
14540 extern __at(0x0812) volatile __COG3DBFbits_t COG3DBFbits
;
14542 #define _COG3DBF_DBF0 0x01
14543 #define _COG3DBF_G3DBF0 0x01
14544 #define _COG3DBF_DBF1 0x02
14545 #define _COG3DBF_G3DBF1 0x02
14546 #define _COG3DBF_DBF2 0x04
14547 #define _COG3DBF_G3DBF2 0x04
14548 #define _COG3DBF_DBF3 0x08
14549 #define _COG3DBF_G3DBF3 0x08
14550 #define _COG3DBF_DBF4 0x10
14551 #define _COG3DBF_G3DBF4 0x10
14552 #define _COG3DBF_DBF5 0x20
14553 #define _COG3DBF_G3DBF5 0x20
14555 //==============================================================================
14558 //==============================================================================
14561 extern __at(0x0813) __sfr COG3CON0
;
14579 unsigned G3MD0
: 1;
14580 unsigned G3MD1
: 1;
14581 unsigned G3MD2
: 1;
14582 unsigned G3CS0
: 1;
14583 unsigned G3CS1
: 1;
14614 } __COG3CON0bits_t
;
14616 extern __at(0x0813) volatile __COG3CON0bits_t COG3CON0bits
;
14618 #define _COG3CON0_MD0 0x01
14619 #define _COG3CON0_G3MD0 0x01
14620 #define _COG3CON0_MD1 0x02
14621 #define _COG3CON0_G3MD1 0x02
14622 #define _COG3CON0_MD2 0x04
14623 #define _COG3CON0_G3MD2 0x04
14624 #define _COG3CON0_CS0 0x08
14625 #define _COG3CON0_G3CS0 0x08
14626 #define _COG3CON0_CS1 0x10
14627 #define _COG3CON0_G3CS1 0x10
14628 #define _COG3CON0_LD 0x40
14629 #define _COG3CON0_G3LD 0x40
14630 #define _COG3CON0_EN 0x80
14631 #define _COG3CON0_G3EN 0x80
14633 //==============================================================================
14636 //==============================================================================
14639 extern __at(0x0814) __sfr COG3CON1
;
14657 unsigned G3POLA
: 1;
14658 unsigned G3POLB
: 1;
14659 unsigned G3POLC
: 1;
14660 unsigned G3POLD
: 1;
14663 unsigned G3FDBS
: 1;
14664 unsigned G3RDBS
: 1;
14666 } __COG3CON1bits_t
;
14668 extern __at(0x0814) volatile __COG3CON1bits_t COG3CON1bits
;
14670 #define _COG3CON1_POLA 0x01
14671 #define _COG3CON1_G3POLA 0x01
14672 #define _COG3CON1_POLB 0x02
14673 #define _COG3CON1_G3POLB 0x02
14674 #define _COG3CON1_POLC 0x04
14675 #define _COG3CON1_G3POLC 0x04
14676 #define _COG3CON1_POLD 0x08
14677 #define _COG3CON1_G3POLD 0x08
14678 #define _COG3CON1_FDBS 0x40
14679 #define _COG3CON1_G3FDBS 0x40
14680 #define _COG3CON1_RDBS 0x80
14681 #define _COG3CON1_G3RDBS 0x80
14683 //==============================================================================
14686 //==============================================================================
14689 extern __at(0x0815) __sfr COG3RIS0
;
14707 unsigned G3RIS0
: 1;
14708 unsigned G3RIS1
: 1;
14709 unsigned G3RIS2
: 1;
14710 unsigned G3RIS3
: 1;
14711 unsigned G3RIS4
: 1;
14712 unsigned G3RIS5
: 1;
14713 unsigned G3RIS6
: 1;
14714 unsigned G3RIS7
: 1;
14716 } __COG3RIS0bits_t
;
14718 extern __at(0x0815) volatile __COG3RIS0bits_t COG3RIS0bits
;
14720 #define _COG3RIS0_RIS0 0x01
14721 #define _COG3RIS0_G3RIS0 0x01
14722 #define _COG3RIS0_RIS1 0x02
14723 #define _COG3RIS0_G3RIS1 0x02
14724 #define _COG3RIS0_RIS2 0x04
14725 #define _COG3RIS0_G3RIS2 0x04
14726 #define _COG3RIS0_RIS3 0x08
14727 #define _COG3RIS0_G3RIS3 0x08
14728 #define _COG3RIS0_RIS4 0x10
14729 #define _COG3RIS0_G3RIS4 0x10
14730 #define _COG3RIS0_RIS5 0x20
14731 #define _COG3RIS0_G3RIS5 0x20
14732 #define _COG3RIS0_RIS6 0x40
14733 #define _COG3RIS0_G3RIS6 0x40
14734 #define _COG3RIS0_RIS7 0x80
14735 #define _COG3RIS0_G3RIS7 0x80
14737 //==============================================================================
14740 //==============================================================================
14743 extern __at(0x0816) __sfr COG3RIS1
;
14752 unsigned RIS11
: 1;
14753 unsigned RIS12
: 1;
14754 unsigned RIS13
: 1;
14755 unsigned RIS14
: 1;
14756 unsigned RIS15
: 1;
14762 unsigned G3RIS9
: 1;
14764 unsigned G3RIS11
: 1;
14765 unsigned G3RIS12
: 1;
14766 unsigned G3RIS13
: 1;
14767 unsigned G3RIS14
: 1;
14768 unsigned G3RIS15
: 1;
14770 } __COG3RIS1bits_t
;
14772 extern __at(0x0816) volatile __COG3RIS1bits_t COG3RIS1bits
;
14774 #define _COG3RIS1_RIS9 0x02
14775 #define _COG3RIS1_G3RIS9 0x02
14776 #define _COG3RIS1_RIS11 0x08
14777 #define _COG3RIS1_G3RIS11 0x08
14778 #define _COG3RIS1_RIS12 0x10
14779 #define _COG3RIS1_G3RIS12 0x10
14780 #define _COG3RIS1_RIS13 0x20
14781 #define _COG3RIS1_G3RIS13 0x20
14782 #define _COG3RIS1_RIS14 0x40
14783 #define _COG3RIS1_G3RIS14 0x40
14784 #define _COG3RIS1_RIS15 0x80
14785 #define _COG3RIS1_G3RIS15 0x80
14787 //==============================================================================
14790 //==============================================================================
14793 extern __at(0x0817) __sfr COG3RSIM0
;
14799 unsigned RSIM0
: 1;
14800 unsigned RSIM1
: 1;
14801 unsigned RSIM2
: 1;
14802 unsigned RSIM3
: 1;
14803 unsigned RSIM4
: 1;
14804 unsigned RSIM5
: 1;
14805 unsigned RSIM6
: 1;
14806 unsigned RSIM7
: 1;
14811 unsigned G3RSIM0
: 1;
14812 unsigned G3RSIM1
: 1;
14813 unsigned G3RSIM2
: 1;
14814 unsigned G3RSIM3
: 1;
14815 unsigned G3RSIM4
: 1;
14816 unsigned G3RSIM5
: 1;
14817 unsigned G3RSIM6
: 1;
14818 unsigned G3RSIM7
: 1;
14820 } __COG3RSIM0bits_t
;
14822 extern __at(0x0817) volatile __COG3RSIM0bits_t COG3RSIM0bits
;
14824 #define _COG3RSIM0_RSIM0 0x01
14825 #define _COG3RSIM0_G3RSIM0 0x01
14826 #define _COG3RSIM0_RSIM1 0x02
14827 #define _COG3RSIM0_G3RSIM1 0x02
14828 #define _COG3RSIM0_RSIM2 0x04
14829 #define _COG3RSIM0_G3RSIM2 0x04
14830 #define _COG3RSIM0_RSIM3 0x08
14831 #define _COG3RSIM0_G3RSIM3 0x08
14832 #define _COG3RSIM0_RSIM4 0x10
14833 #define _COG3RSIM0_G3RSIM4 0x10
14834 #define _COG3RSIM0_RSIM5 0x20
14835 #define _COG3RSIM0_G3RSIM5 0x20
14836 #define _COG3RSIM0_RSIM6 0x40
14837 #define _COG3RSIM0_G3RSIM6 0x40
14838 #define _COG3RSIM0_RSIM7 0x80
14839 #define _COG3RSIM0_G3RSIM7 0x80
14841 //==============================================================================
14844 //==============================================================================
14847 extern __at(0x0818) __sfr COG3RSIM1
;
14854 unsigned RSIM9
: 1;
14856 unsigned RSIM11
: 1;
14857 unsigned RSIM12
: 1;
14858 unsigned RSIM13
: 1;
14859 unsigned RSIM14
: 1;
14860 unsigned RSIM15
: 1;
14866 unsigned G3RSIM9
: 1;
14868 unsigned G3RSIM11
: 1;
14869 unsigned G3RSIM12
: 1;
14870 unsigned G3RSIM13
: 1;
14871 unsigned G3RSIM14
: 1;
14872 unsigned G3RSIM15
: 1;
14874 } __COG3RSIM1bits_t
;
14876 extern __at(0x0818) volatile __COG3RSIM1bits_t COG3RSIM1bits
;
14878 #define _COG3RSIM1_RSIM9 0x02
14879 #define _COG3RSIM1_G3RSIM9 0x02
14880 #define _COG3RSIM1_RSIM11 0x08
14881 #define _COG3RSIM1_G3RSIM11 0x08
14882 #define _COG3RSIM1_RSIM12 0x10
14883 #define _COG3RSIM1_G3RSIM12 0x10
14884 #define _COG3RSIM1_RSIM13 0x20
14885 #define _COG3RSIM1_G3RSIM13 0x20
14886 #define _COG3RSIM1_RSIM14 0x40
14887 #define _COG3RSIM1_G3RSIM14 0x40
14888 #define _COG3RSIM1_RSIM15 0x80
14889 #define _COG3RSIM1_G3RSIM15 0x80
14891 //==============================================================================
14894 //==============================================================================
14897 extern __at(0x0819) __sfr COG3FIS0
;
14915 unsigned G3FIS0
: 1;
14916 unsigned G3FIS1
: 1;
14917 unsigned G3FIS2
: 1;
14918 unsigned G3FIS3
: 1;
14919 unsigned G3FIS4
: 1;
14920 unsigned G3FIS5
: 1;
14921 unsigned G3FIS6
: 1;
14922 unsigned G3FIS7
: 1;
14924 } __COG3FIS0bits_t
;
14926 extern __at(0x0819) volatile __COG3FIS0bits_t COG3FIS0bits
;
14928 #define _COG3FIS0_FIS0 0x01
14929 #define _COG3FIS0_G3FIS0 0x01
14930 #define _COG3FIS0_FIS1 0x02
14931 #define _COG3FIS0_G3FIS1 0x02
14932 #define _COG3FIS0_FIS2 0x04
14933 #define _COG3FIS0_G3FIS2 0x04
14934 #define _COG3FIS0_FIS3 0x08
14935 #define _COG3FIS0_G3FIS3 0x08
14936 #define _COG3FIS0_FIS4 0x10
14937 #define _COG3FIS0_G3FIS4 0x10
14938 #define _COG3FIS0_FIS5 0x20
14939 #define _COG3FIS0_G3FIS5 0x20
14940 #define _COG3FIS0_FIS6 0x40
14941 #define _COG3FIS0_G3FIS6 0x40
14942 #define _COG3FIS0_FIS7 0x80
14943 #define _COG3FIS0_G3FIS7 0x80
14945 //==============================================================================
14948 //==============================================================================
14951 extern __at(0x081A) __sfr COG3FIS1
;
14960 unsigned FIS11
: 1;
14961 unsigned FIS12
: 1;
14962 unsigned FIS13
: 1;
14963 unsigned FIS14
: 1;
14964 unsigned FIS15
: 1;
14970 unsigned G3FIS9
: 1;
14972 unsigned G3FIS11
: 1;
14973 unsigned G3FIS12
: 1;
14974 unsigned G3FIS13
: 1;
14975 unsigned G3FIS14
: 1;
14976 unsigned G3FIS15
: 1;
14978 } __COG3FIS1bits_t
;
14980 extern __at(0x081A) volatile __COG3FIS1bits_t COG3FIS1bits
;
14982 #define _COG3FIS1_FIS9 0x02
14983 #define _COG3FIS1_G3FIS9 0x02
14984 #define _COG3FIS1_FIS11 0x08
14985 #define _COG3FIS1_G3FIS11 0x08
14986 #define _COG3FIS1_FIS12 0x10
14987 #define _COG3FIS1_G3FIS12 0x10
14988 #define _COG3FIS1_FIS13 0x20
14989 #define _COG3FIS1_G3FIS13 0x20
14990 #define _COG3FIS1_FIS14 0x40
14991 #define _COG3FIS1_G3FIS14 0x40
14992 #define _COG3FIS1_FIS15 0x80
14993 #define _COG3FIS1_G3FIS15 0x80
14995 //==============================================================================
14998 //==============================================================================
15001 extern __at(0x081B) __sfr COG3FSIM0
;
15007 unsigned FSIM0
: 1;
15008 unsigned FSIM1
: 1;
15009 unsigned FSIM2
: 1;
15010 unsigned FSIM3
: 1;
15011 unsigned FSIM4
: 1;
15012 unsigned FSIM5
: 1;
15013 unsigned FSIM6
: 1;
15014 unsigned FSIM7
: 1;
15019 unsigned G3FSIM0
: 1;
15020 unsigned G3FSIM1
: 1;
15021 unsigned G3FSIM2
: 1;
15022 unsigned G3FSIM3
: 1;
15023 unsigned G3FSIM4
: 1;
15024 unsigned G3FSIM5
: 1;
15025 unsigned G3FSIM6
: 1;
15026 unsigned G3FSIM7
: 1;
15028 } __COG3FSIM0bits_t
;
15030 extern __at(0x081B) volatile __COG3FSIM0bits_t COG3FSIM0bits
;
15032 #define _COG3FSIM0_FSIM0 0x01
15033 #define _COG3FSIM0_G3FSIM0 0x01
15034 #define _COG3FSIM0_FSIM1 0x02
15035 #define _COG3FSIM0_G3FSIM1 0x02
15036 #define _COG3FSIM0_FSIM2 0x04
15037 #define _COG3FSIM0_G3FSIM2 0x04
15038 #define _COG3FSIM0_FSIM3 0x08
15039 #define _COG3FSIM0_G3FSIM3 0x08
15040 #define _COG3FSIM0_FSIM4 0x10
15041 #define _COG3FSIM0_G3FSIM4 0x10
15042 #define _COG3FSIM0_FSIM5 0x20
15043 #define _COG3FSIM0_G3FSIM5 0x20
15044 #define _COG3FSIM0_FSIM6 0x40
15045 #define _COG3FSIM0_G3FSIM6 0x40
15046 #define _COG3FSIM0_FSIM7 0x80
15047 #define _COG3FSIM0_G3FSIM7 0x80
15049 //==============================================================================
15052 //==============================================================================
15055 extern __at(0x081C) __sfr COG3FSIM1
;
15062 unsigned FSIM9
: 1;
15064 unsigned FSIM11
: 1;
15065 unsigned FSIM12
: 1;
15066 unsigned FSIM13
: 1;
15067 unsigned FSIM14
: 1;
15068 unsigned FSIM15
: 1;
15074 unsigned G3FSIM9
: 1;
15076 unsigned G3FSIM11
: 1;
15077 unsigned G3FSIM12
: 1;
15078 unsigned G3FSIM13
: 1;
15079 unsigned G3FSIM14
: 1;
15080 unsigned G3FSIM15
: 1;
15082 } __COG3FSIM1bits_t
;
15084 extern __at(0x081C) volatile __COG3FSIM1bits_t COG3FSIM1bits
;
15086 #define _COG3FSIM1_FSIM9 0x02
15087 #define _COG3FSIM1_G3FSIM9 0x02
15088 #define _COG3FSIM1_FSIM11 0x08
15089 #define _COG3FSIM1_G3FSIM11 0x08
15090 #define _COG3FSIM1_FSIM12 0x10
15091 #define _COG3FSIM1_G3FSIM12 0x10
15092 #define _COG3FSIM1_FSIM13 0x20
15093 #define _COG3FSIM1_G3FSIM13 0x20
15094 #define _COG3FSIM1_FSIM14 0x40
15095 #define _COG3FSIM1_G3FSIM14 0x40
15096 #define _COG3FSIM1_FSIM15 0x80
15097 #define _COG3FSIM1_G3FSIM15 0x80
15099 //==============================================================================
15102 //==============================================================================
15105 extern __at(0x081D) __sfr COG3ASD0
;
15113 unsigned ASDAC0
: 1;
15114 unsigned ASDAC1
: 1;
15115 unsigned ASDBD0
: 1;
15116 unsigned ASDBD1
: 1;
15117 unsigned ASREN
: 1;
15125 unsigned G3ASDAC0
: 1;
15126 unsigned G3ASDAC1
: 1;
15127 unsigned G3ASDBD0
: 1;
15128 unsigned G3ASDBD1
: 1;
15129 unsigned ARSEN
: 1;
15130 unsigned G3ASE
: 1;
15141 unsigned G3ARSEN
: 1;
15153 unsigned G3ASREN
: 1;
15160 unsigned ASDAC
: 2;
15167 unsigned G3ASDAC
: 2;
15174 unsigned G3ASDBD
: 2;
15181 unsigned ASDBD
: 2;
15184 } __COG3ASD0bits_t
;
15186 extern __at(0x081D) volatile __COG3ASD0bits_t COG3ASD0bits
;
15188 #define _COG3ASD0_ASDAC0 0x04
15189 #define _COG3ASD0_G3ASDAC0 0x04
15190 #define _COG3ASD0_ASDAC1 0x08
15191 #define _COG3ASD0_G3ASDAC1 0x08
15192 #define _COG3ASD0_ASDBD0 0x10
15193 #define _COG3ASD0_G3ASDBD0 0x10
15194 #define _COG3ASD0_ASDBD1 0x20
15195 #define _COG3ASD0_G3ASDBD1 0x20
15196 #define _COG3ASD0_ASREN 0x40
15197 #define _COG3ASD0_ARSEN 0x40
15198 #define _COG3ASD0_G3ARSEN 0x40
15199 #define _COG3ASD0_G3ASREN 0x40
15200 #define _COG3ASD0_ASE 0x80
15201 #define _COG3ASD0_G3ASE 0x80
15203 //==============================================================================
15206 //==============================================================================
15209 extern __at(0x081E) __sfr COG3ASD1
;
15227 unsigned G3AS0E
: 1;
15228 unsigned G3AS1E
: 1;
15229 unsigned G3AS2E
: 1;
15230 unsigned G3AS3E
: 1;
15231 unsigned G3AS4E
: 1;
15232 unsigned G3AS5E
: 1;
15233 unsigned G3AS6E
: 1;
15234 unsigned G3AS7E
: 1;
15236 } __COG3ASD1bits_t
;
15238 extern __at(0x081E) volatile __COG3ASD1bits_t COG3ASD1bits
;
15240 #define _COG3ASD1_AS0E 0x01
15241 #define _COG3ASD1_G3AS0E 0x01
15242 #define _COG3ASD1_AS1E 0x02
15243 #define _COG3ASD1_G3AS1E 0x02
15244 #define _COG3ASD1_AS2E 0x04
15245 #define _COG3ASD1_G3AS2E 0x04
15246 #define _COG3ASD1_AS3E 0x08
15247 #define _COG3ASD1_G3AS3E 0x08
15248 #define _COG3ASD1_AS4E 0x10
15249 #define _COG3ASD1_G3AS4E 0x10
15250 #define _COG3ASD1_AS5E 0x20
15251 #define _COG3ASD1_G3AS5E 0x20
15252 #define _COG3ASD1_AS6E 0x40
15253 #define _COG3ASD1_G3AS6E 0x40
15254 #define _COG3ASD1_AS7E 0x80
15255 #define _COG3ASD1_G3AS7E 0x80
15257 //==============================================================================
15260 //==============================================================================
15263 extern __at(0x081F) __sfr COG3STR
;
15273 unsigned SDATA
: 1;
15274 unsigned SDATB
: 1;
15275 unsigned SDATC
: 1;
15276 unsigned SDATD
: 1;
15281 unsigned G3STRA
: 1;
15282 unsigned G3STRB
: 1;
15283 unsigned G3STRC
: 1;
15284 unsigned G3STRD
: 1;
15285 unsigned G3SDATA
: 1;
15286 unsigned G3SDATB
: 1;
15287 unsigned G3SDATC
: 1;
15288 unsigned G3SDATD
: 1;
15292 extern __at(0x081F) volatile __COG3STRbits_t COG3STRbits
;
15294 #define _COG3STR_STRA 0x01
15295 #define _COG3STR_G3STRA 0x01
15296 #define _COG3STR_STRB 0x02
15297 #define _COG3STR_G3STRB 0x02
15298 #define _COG3STR_STRC 0x04
15299 #define _COG3STR_G3STRC 0x04
15300 #define _COG3STR_STRD 0x08
15301 #define _COG3STR_G3STRD 0x08
15302 #define _COG3STR_SDATA 0x10
15303 #define _COG3STR_G3SDATA 0x10
15304 #define _COG3STR_SDATB 0x20
15305 #define _COG3STR_G3SDATB 0x20
15306 #define _COG3STR_SDATC 0x40
15307 #define _COG3STR_G3SDATC 0x40
15308 #define _COG3STR_SDATD 0x80
15309 #define _COG3STR_G3SDATD 0x80
15311 //==============================================================================
15314 //==============================================================================
15317 extern __at(0x090C) __sfr CM4CON0
;
15325 unsigned Reserved
: 1;
15335 unsigned C4SYNC
: 1;
15336 unsigned C4HYS
: 1;
15338 unsigned C4ZLF
: 1;
15339 unsigned C4POL
: 1;
15341 unsigned C4OUT
: 1;
15346 extern __at(0x090C) volatile __CM4CON0bits_t CM4CON0bits
;
15348 #define _CM4CON0_SYNC 0x01
15349 #define _CM4CON0_C4SYNC 0x01
15350 #define _CM4CON0_HYS 0x02
15351 #define _CM4CON0_C4HYS 0x02
15352 #define _CM4CON0_Reserved 0x04
15353 #define _CM4CON0_C4SP 0x04
15354 #define _CM4CON0_ZLF 0x08
15355 #define _CM4CON0_C4ZLF 0x08
15356 #define _CM4CON0_POL 0x10
15357 #define _CM4CON0_C4POL 0x10
15358 #define _CM4CON0_OUT 0x40
15359 #define _CM4CON0_C4OUT 0x40
15360 #define _CM4CON0_ON 0x80
15361 #define _CM4CON0_C4ON 0x80
15363 //==============================================================================
15366 //==============================================================================
15369 extern __at(0x090D) __sfr CM4CON1
;
15387 unsigned C4INTN
: 1;
15388 unsigned C4INTP
: 1;
15398 extern __at(0x090D) volatile __CM4CON1bits_t CM4CON1bits
;
15400 #define _CM4CON1_INTN 0x01
15401 #define _CM4CON1_C4INTN 0x01
15402 #define _CM4CON1_INTP 0x02
15403 #define _CM4CON1_C4INTP 0x02
15405 //==============================================================================
15408 //==============================================================================
15411 extern __at(0x090E) __sfr CM4NSEL
;
15417 unsigned C4NCH0
: 1;
15418 unsigned C4NCH1
: 1;
15419 unsigned C4NCH2
: 1;
15420 unsigned C4NCH3
: 1;
15429 unsigned C4NCH
: 4;
15434 extern __at(0x090E) volatile __CM4NSELbits_t CM4NSELbits
;
15436 #define _C4NCH0 0x01
15437 #define _C4NCH1 0x02
15438 #define _C4NCH2 0x04
15439 #define _C4NCH3 0x08
15441 //==============================================================================
15444 //==============================================================================
15447 extern __at(0x090F) __sfr CM4PSEL
;
15465 unsigned C4PCH0
: 1;
15466 unsigned C4PCH1
: 1;
15467 unsigned C4PCH2
: 1;
15468 unsigned C4PCH3
: 1;
15483 unsigned C4PCH
: 4;
15488 extern __at(0x090F) volatile __CM4PSELbits_t CM4PSELbits
;
15490 #define _CM4PSEL_PCH0 0x01
15491 #define _CM4PSEL_C4PCH0 0x01
15492 #define _CM4PSEL_PCH1 0x02
15493 #define _CM4PSEL_C4PCH1 0x02
15494 #define _CM4PSEL_PCH2 0x04
15495 #define _CM4PSEL_C4PCH2 0x04
15496 #define _CM4PSEL_PCH3 0x08
15497 #define _CM4PSEL_C4PCH3 0x08
15499 //==============================================================================
15502 //==============================================================================
15505 extern __at(0x0910) __sfr CM5CON0
;
15513 unsigned Reserved
: 1;
15523 unsigned C5SYNC
: 1;
15524 unsigned C5HYS
: 1;
15526 unsigned C5ZLF
: 1;
15527 unsigned C5POL
: 1;
15529 unsigned C5OUT
: 1;
15534 extern __at(0x0910) volatile __CM5CON0bits_t CM5CON0bits
;
15536 #define _CM5CON0_SYNC 0x01
15537 #define _CM5CON0_C5SYNC 0x01
15538 #define _CM5CON0_HYS 0x02
15539 #define _CM5CON0_C5HYS 0x02
15540 #define _CM5CON0_Reserved 0x04
15541 #define _CM5CON0_C5SP 0x04
15542 #define _CM5CON0_ZLF 0x08
15543 #define _CM5CON0_C5ZLF 0x08
15544 #define _CM5CON0_POL 0x10
15545 #define _CM5CON0_C5POL 0x10
15546 #define _CM5CON0_OUT 0x40
15547 #define _CM5CON0_C5OUT 0x40
15548 #define _CM5CON0_ON 0x80
15549 #define _CM5CON0_C5ON 0x80
15551 //==============================================================================
15554 //==============================================================================
15557 extern __at(0x0911) __sfr CM5CON1
;
15575 unsigned C5INTN
: 1;
15576 unsigned C5INTP
: 1;
15586 extern __at(0x0911) volatile __CM5CON1bits_t CM5CON1bits
;
15588 #define _CM5CON1_INTN 0x01
15589 #define _CM5CON1_C5INTN 0x01
15590 #define _CM5CON1_INTP 0x02
15591 #define _CM5CON1_C5INTP 0x02
15593 //==============================================================================
15596 //==============================================================================
15599 extern __at(0x0912) __sfr CM5NSEL
;
15605 unsigned C5NCH0
: 1;
15606 unsigned C5NCH1
: 1;
15607 unsigned C5NCH2
: 1;
15608 unsigned C5NCH3
: 1;
15617 unsigned C5NCH
: 4;
15622 extern __at(0x0912) volatile __CM5NSELbits_t CM5NSELbits
;
15624 #define _C5NCH0 0x01
15625 #define _C5NCH1 0x02
15626 #define _C5NCH2 0x04
15627 #define _C5NCH3 0x08
15629 //==============================================================================
15632 //==============================================================================
15635 extern __at(0x0913) __sfr CM5PSEL
;
15653 unsigned C5PCH0
: 1;
15654 unsigned C5PCH1
: 1;
15655 unsigned C5PCH2
: 1;
15656 unsigned C5PCH3
: 1;
15671 unsigned C5PCH
: 4;
15676 extern __at(0x0913) volatile __CM5PSELbits_t CM5PSELbits
;
15678 #define _CM5PSEL_PCH0 0x01
15679 #define _CM5PSEL_C5PCH0 0x01
15680 #define _CM5PSEL_PCH1 0x02
15681 #define _CM5PSEL_C5PCH1 0x02
15682 #define _CM5PSEL_PCH2 0x04
15683 #define _CM5PSEL_C5PCH2 0x04
15684 #define _CM5PSEL_PCH3 0x08
15685 #define _CM5PSEL_C5PCH3 0x08
15687 //==============================================================================
15690 //==============================================================================
15693 extern __at(0x0914) __sfr CM6CON0
;
15701 unsigned Reserved
: 1;
15711 unsigned C6SYNC
: 1;
15712 unsigned C6HYS
: 1;
15714 unsigned C6ZLF
: 1;
15715 unsigned C6POL
: 1;
15717 unsigned C6OUT
: 1;
15722 extern __at(0x0914) volatile __CM6CON0bits_t CM6CON0bits
;
15724 #define _CM6CON0_SYNC 0x01
15725 #define _CM6CON0_C6SYNC 0x01
15726 #define _CM6CON0_HYS 0x02
15727 #define _CM6CON0_C6HYS 0x02
15728 #define _CM6CON0_Reserved 0x04
15729 #define _CM6CON0_C6SP 0x04
15730 #define _CM6CON0_ZLF 0x08
15731 #define _CM6CON0_C6ZLF 0x08
15732 #define _CM6CON0_POL 0x10
15733 #define _CM6CON0_C6POL 0x10
15734 #define _CM6CON0_OUT 0x40
15735 #define _CM6CON0_C6OUT 0x40
15736 #define _CM6CON0_ON 0x80
15737 #define _CM6CON0_C6ON 0x80
15739 //==============================================================================
15742 //==============================================================================
15745 extern __at(0x0915) __sfr CM6CON1
;
15763 unsigned C6INTN
: 1;
15764 unsigned C6INTP
: 1;
15774 extern __at(0x0915) volatile __CM6CON1bits_t CM6CON1bits
;
15776 #define _CM6CON1_INTN 0x01
15777 #define _CM6CON1_C6INTN 0x01
15778 #define _CM6CON1_INTP 0x02
15779 #define _CM6CON1_C6INTP 0x02
15781 //==============================================================================
15784 //==============================================================================
15787 extern __at(0x0916) __sfr CM6NSEL
;
15793 unsigned C6NCH0
: 1;
15794 unsigned C6NCH1
: 1;
15795 unsigned C6NCH2
: 1;
15796 unsigned C6NCH3
: 1;
15805 unsigned C6NCH
: 4;
15810 extern __at(0x0916) volatile __CM6NSELbits_t CM6NSELbits
;
15812 #define _C6NCH0 0x01
15813 #define _C6NCH1 0x02
15814 #define _C6NCH2 0x04
15815 #define _C6NCH3 0x08
15817 //==============================================================================
15820 //==============================================================================
15823 extern __at(0x0917) __sfr CM6PSEL
;
15841 unsigned C6PCH0
: 1;
15842 unsigned C6PCH1
: 1;
15843 unsigned C6PCH2
: 1;
15844 unsigned C6PCH3
: 1;
15853 unsigned C6PCH
: 4;
15864 extern __at(0x0917) volatile __CM6PSELbits_t CM6PSELbits
;
15866 #define _CM6PSEL_PCH0 0x01
15867 #define _CM6PSEL_C6PCH0 0x01
15868 #define _CM6PSEL_PCH1 0x02
15869 #define _CM6PSEL_C6PCH1 0x02
15870 #define _CM6PSEL_PCH2 0x04
15871 #define _CM6PSEL_C6PCH2 0x04
15872 #define _CM6PSEL_PCH3 0x08
15873 #define _CM6PSEL_C6PCH3 0x08
15875 //==============================================================================
15878 //==============================================================================
15881 extern __at(0x0D8E) __sfr PWMEN
;
15885 unsigned MPWM5EN
: 1;
15886 unsigned MPWM6EN
: 1;
15887 unsigned MPWM11EN
: 1;
15895 extern __at(0x0D8E) volatile __PWMENbits_t PWMENbits
;
15897 #define _MPWM5EN 0x01
15898 #define _MPWM6EN 0x02
15899 #define _MPWM11EN 0x04
15901 //==============================================================================
15904 //==============================================================================
15907 extern __at(0x0D8F) __sfr PWMLD
;
15911 unsigned MPWM5LD
: 1;
15912 unsigned MPWM6LD
: 1;
15913 unsigned MPWM11LD
: 1;
15921 extern __at(0x0D8F) volatile __PWMLDbits_t PWMLDbits
;
15923 #define _MPWM5LD 0x01
15924 #define _MPWM6LD 0x02
15925 #define _MPWM11LD 0x04
15927 //==============================================================================
15930 //==============================================================================
15933 extern __at(0x0D90) __sfr PWMOUT
;
15937 unsigned MPWM5OUT
: 1;
15938 unsigned MPWM6OUT
: 1;
15939 unsigned MPWM11OUT
: 1;
15947 extern __at(0x0D90) volatile __PWMOUTbits_t PWMOUTbits
;
15949 #define _MPWM5OUT 0x01
15950 #define _MPWM6OUT 0x02
15951 #define _MPWM11OUT 0x04
15953 //==============================================================================
15955 extern __at(0x0D91) __sfr PWM5PH
;
15957 //==============================================================================
15960 extern __at(0x0D91) __sfr PWM5PHL
;
15964 unsigned PWM5PHL0
: 1;
15965 unsigned PWM5PHL1
: 1;
15966 unsigned PWM5PHL2
: 1;
15967 unsigned PWM5PHL3
: 1;
15968 unsigned PWM5PHL4
: 1;
15969 unsigned PWM5PHL5
: 1;
15970 unsigned PWM5PHL6
: 1;
15971 unsigned PWM5PHL7
: 1;
15974 extern __at(0x0D91) volatile __PWM5PHLbits_t PWM5PHLbits
;
15976 #define _PWM5PHL0 0x01
15977 #define _PWM5PHL1 0x02
15978 #define _PWM5PHL2 0x04
15979 #define _PWM5PHL3 0x08
15980 #define _PWM5PHL4 0x10
15981 #define _PWM5PHL5 0x20
15982 #define _PWM5PHL6 0x40
15983 #define _PWM5PHL7 0x80
15985 //==============================================================================
15988 //==============================================================================
15991 extern __at(0x0D92) __sfr PWM5PHH
;
15995 unsigned PWM5PHH0
: 1;
15996 unsigned PWM5PHH1
: 1;
15997 unsigned PWM5PHH2
: 1;
15998 unsigned PWM5PHH3
: 1;
15999 unsigned PWM5PHH4
: 1;
16000 unsigned PWM5PHH5
: 1;
16001 unsigned PWM5PHH6
: 1;
16002 unsigned PWM5PHH7
: 1;
16005 extern __at(0x0D92) volatile __PWM5PHHbits_t PWM5PHHbits
;
16007 #define _PWM5PHH0 0x01
16008 #define _PWM5PHH1 0x02
16009 #define _PWM5PHH2 0x04
16010 #define _PWM5PHH3 0x08
16011 #define _PWM5PHH4 0x10
16012 #define _PWM5PHH5 0x20
16013 #define _PWM5PHH6 0x40
16014 #define _PWM5PHH7 0x80
16016 //==============================================================================
16018 extern __at(0x0D93) __sfr PWM5DC
;
16020 //==============================================================================
16023 extern __at(0x0D93) __sfr PWM5DCL
;
16027 unsigned PWM5DCL0
: 1;
16028 unsigned PWM5DCL1
: 1;
16029 unsigned PWM5DCL2
: 1;
16030 unsigned PWM5DCL3
: 1;
16031 unsigned PWM5DCL4
: 1;
16032 unsigned PWM5DCL5
: 1;
16033 unsigned PWM5DCL6
: 1;
16034 unsigned PWM5DCL7
: 1;
16037 extern __at(0x0D93) volatile __PWM5DCLbits_t PWM5DCLbits
;
16039 #define _PWM5DCL0 0x01
16040 #define _PWM5DCL1 0x02
16041 #define _PWM5DCL2 0x04
16042 #define _PWM5DCL3 0x08
16043 #define _PWM5DCL4 0x10
16044 #define _PWM5DCL5 0x20
16045 #define _PWM5DCL6 0x40
16046 #define _PWM5DCL7 0x80
16048 //==============================================================================
16051 //==============================================================================
16054 extern __at(0x0D94) __sfr PWM5DCH
;
16058 unsigned PWM5DCH0
: 1;
16059 unsigned PWM5DCH1
: 1;
16060 unsigned PWM5DCH2
: 1;
16061 unsigned PWM5DCH3
: 1;
16062 unsigned PWM5DCH4
: 1;
16063 unsigned PWM5DCH5
: 1;
16064 unsigned PWM5DCH6
: 1;
16065 unsigned PWM5DCH7
: 1;
16068 extern __at(0x0D94) volatile __PWM5DCHbits_t PWM5DCHbits
;
16070 #define _PWM5DCH0 0x01
16071 #define _PWM5DCH1 0x02
16072 #define _PWM5DCH2 0x04
16073 #define _PWM5DCH3 0x08
16074 #define _PWM5DCH4 0x10
16075 #define _PWM5DCH5 0x20
16076 #define _PWM5DCH6 0x40
16077 #define _PWM5DCH7 0x80
16079 //==============================================================================
16081 extern __at(0x0D95) __sfr PWM5PR
;
16083 //==============================================================================
16086 extern __at(0x0D95) __sfr PWM5PRL
;
16090 unsigned PWM5PRL0
: 1;
16091 unsigned PWM5PRL1
: 1;
16092 unsigned PWM5PRL2
: 1;
16093 unsigned PWM5PRL3
: 1;
16094 unsigned PWM5PRL4
: 1;
16095 unsigned PWM5PRL5
: 1;
16096 unsigned PWM5PRL6
: 1;
16097 unsigned PWM5PRL7
: 1;
16100 extern __at(0x0D95) volatile __PWM5PRLbits_t PWM5PRLbits
;
16102 #define _PWM5PRL0 0x01
16103 #define _PWM5PRL1 0x02
16104 #define _PWM5PRL2 0x04
16105 #define _PWM5PRL3 0x08
16106 #define _PWM5PRL4 0x10
16107 #define _PWM5PRL5 0x20
16108 #define _PWM5PRL6 0x40
16109 #define _PWM5PRL7 0x80
16111 //==============================================================================
16114 //==============================================================================
16117 extern __at(0x0D96) __sfr PWM5PRH
;
16121 unsigned PWM5PRH0
: 1;
16122 unsigned PWM5PRH1
: 1;
16123 unsigned PWM5PRH2
: 1;
16124 unsigned PWM5PRH3
: 1;
16125 unsigned PWM5PRH4
: 1;
16126 unsigned PWM5PRH5
: 1;
16127 unsigned PWM5PRH6
: 1;
16128 unsigned PWM5PRH7
: 1;
16131 extern __at(0x0D96) volatile __PWM5PRHbits_t PWM5PRHbits
;
16133 #define _PWM5PRH0 0x01
16134 #define _PWM5PRH1 0x02
16135 #define _PWM5PRH2 0x04
16136 #define _PWM5PRH3 0x08
16137 #define _PWM5PRH4 0x10
16138 #define _PWM5PRH5 0x20
16139 #define _PWM5PRH6 0x40
16140 #define _PWM5PRH7 0x80
16142 //==============================================================================
16144 extern __at(0x0D97) __sfr PWM5OF
;
16146 //==============================================================================
16149 extern __at(0x0D97) __sfr PWM5OFL
;
16153 unsigned PWM5OFL0
: 1;
16154 unsigned PWM5OFL1
: 1;
16155 unsigned PWM5OFL2
: 1;
16156 unsigned PWM5OFL3
: 1;
16157 unsigned PWM5OFL4
: 1;
16158 unsigned PWM5OFL5
: 1;
16159 unsigned PWM5OFL6
: 1;
16160 unsigned PWM5OFL7
: 1;
16163 extern __at(0x0D97) volatile __PWM5OFLbits_t PWM5OFLbits
;
16165 #define _PWM5OFL0 0x01
16166 #define _PWM5OFL1 0x02
16167 #define _PWM5OFL2 0x04
16168 #define _PWM5OFL3 0x08
16169 #define _PWM5OFL4 0x10
16170 #define _PWM5OFL5 0x20
16171 #define _PWM5OFL6 0x40
16172 #define _PWM5OFL7 0x80
16174 //==============================================================================
16177 //==============================================================================
16180 extern __at(0x0D98) __sfr PWM5OFH
;
16184 unsigned PWM5OFH0
: 1;
16185 unsigned PWM5OFH1
: 1;
16186 unsigned PWM5OFH2
: 1;
16187 unsigned PWM5OFH3
: 1;
16188 unsigned PWM5OFH4
: 1;
16189 unsigned PWM5OFH5
: 1;
16190 unsigned PWM5OFH6
: 1;
16191 unsigned PWM5OFH7
: 1;
16194 extern __at(0x0D98) volatile __PWM5OFHbits_t PWM5OFHbits
;
16196 #define _PWM5OFH0 0x01
16197 #define _PWM5OFH1 0x02
16198 #define _PWM5OFH2 0x04
16199 #define _PWM5OFH3 0x08
16200 #define _PWM5OFH4 0x10
16201 #define _PWM5OFH5 0x20
16202 #define _PWM5OFH6 0x40
16203 #define _PWM5OFH7 0x80
16205 //==============================================================================
16207 extern __at(0x0D99) __sfr PWM5TMR
;
16209 //==============================================================================
16212 extern __at(0x0D99) __sfr PWM5TMRL
;
16216 unsigned PWM5TMRL0
: 1;
16217 unsigned PWM5TMRL1
: 1;
16218 unsigned PWM5TMRL2
: 1;
16219 unsigned PWM5TMRL3
: 1;
16220 unsigned PWM5TMRL4
: 1;
16221 unsigned PWM5TMRL5
: 1;
16222 unsigned PWM5TMRL6
: 1;
16223 unsigned PWM5TMRL7
: 1;
16224 } __PWM5TMRLbits_t
;
16226 extern __at(0x0D99) volatile __PWM5TMRLbits_t PWM5TMRLbits
;
16228 #define _PWM5TMRL0 0x01
16229 #define _PWM5TMRL1 0x02
16230 #define _PWM5TMRL2 0x04
16231 #define _PWM5TMRL3 0x08
16232 #define _PWM5TMRL4 0x10
16233 #define _PWM5TMRL5 0x20
16234 #define _PWM5TMRL6 0x40
16235 #define _PWM5TMRL7 0x80
16237 //==============================================================================
16240 //==============================================================================
16243 extern __at(0x0D9A) __sfr PWM5TMRH
;
16247 unsigned PWM5TMRH0
: 1;
16248 unsigned PWM5TMRH1
: 1;
16249 unsigned PWM5TMRH2
: 1;
16250 unsigned PWM5TMRH3
: 1;
16251 unsigned PWM5TMRH4
: 1;
16252 unsigned PWM5TMRH5
: 1;
16253 unsigned PWM5TMRH6
: 1;
16254 unsigned PWM5TMRH7
: 1;
16255 } __PWM5TMRHbits_t
;
16257 extern __at(0x0D9A) volatile __PWM5TMRHbits_t PWM5TMRHbits
;
16259 #define _PWM5TMRH0 0x01
16260 #define _PWM5TMRH1 0x02
16261 #define _PWM5TMRH2 0x04
16262 #define _PWM5TMRH3 0x08
16263 #define _PWM5TMRH4 0x10
16264 #define _PWM5TMRH5 0x20
16265 #define _PWM5TMRH6 0x40
16266 #define _PWM5TMRH7 0x80
16268 //==============================================================================
16271 //==============================================================================
16274 extern __at(0x0D9B) __sfr PWM5CON
;
16282 unsigned PWM5MODE0
: 1;
16283 unsigned PWM5MODE1
: 1;
16294 unsigned MODE0
: 1;
16295 unsigned MODE1
: 1;
16296 unsigned PWM5POL
: 1;
16297 unsigned PWM5OUT
: 1;
16299 unsigned PWM5EN
: 1;
16305 unsigned PWM5MODE
: 2;
16317 extern __at(0x0D9B) volatile __PWM5CONbits_t PWM5CONbits
;
16319 #define _PWM5CON_PWM5MODE0 0x04
16320 #define _PWM5CON_MODE0 0x04
16321 #define _PWM5CON_PWM5MODE1 0x08
16322 #define _PWM5CON_MODE1 0x08
16323 #define _PWM5CON_POL 0x10
16324 #define _PWM5CON_PWM5POL 0x10
16325 #define _PWM5CON_OUT 0x20
16326 #define _PWM5CON_PWM5OUT 0x20
16327 #define _PWM5CON_EN 0x80
16328 #define _PWM5CON_PWM5EN 0x80
16330 //==============================================================================
16333 //==============================================================================
16336 extern __at(0x0D9C) __sfr PWM5INTCON
;
16354 unsigned PWM5PRIE
: 1;
16355 unsigned PWM5DCIE
: 1;
16356 unsigned PWM5PHIE
: 1;
16357 unsigned PWM5OFIE
: 1;
16363 } __PWM5INTCONbits_t
;
16365 extern __at(0x0D9C) volatile __PWM5INTCONbits_t PWM5INTCONbits
;
16368 #define _PWM5PRIE 0x01
16370 #define _PWM5DCIE 0x02
16372 #define _PWM5PHIE 0x04
16374 #define _PWM5OFIE 0x08
16376 //==============================================================================
16379 //==============================================================================
16382 extern __at(0x0D9C) __sfr PWM5INTE
;
16400 unsigned PWM5PRIE
: 1;
16401 unsigned PWM5DCIE
: 1;
16402 unsigned PWM5PHIE
: 1;
16403 unsigned PWM5OFIE
: 1;
16409 } __PWM5INTEbits_t
;
16411 extern __at(0x0D9C) volatile __PWM5INTEbits_t PWM5INTEbits
;
16413 #define _PWM5INTE_PRIE 0x01
16414 #define _PWM5INTE_PWM5PRIE 0x01
16415 #define _PWM5INTE_DCIE 0x02
16416 #define _PWM5INTE_PWM5DCIE 0x02
16417 #define _PWM5INTE_PHIE 0x04
16418 #define _PWM5INTE_PWM5PHIE 0x04
16419 #define _PWM5INTE_OFIE 0x08
16420 #define _PWM5INTE_PWM5OFIE 0x08
16422 //==============================================================================
16425 //==============================================================================
16428 extern __at(0x0D9D) __sfr PWM5INTF
;
16446 unsigned PWM5PRIF
: 1;
16447 unsigned PWM5DCIF
: 1;
16448 unsigned PWM5PHIF
: 1;
16449 unsigned PWM5OFIF
: 1;
16455 } __PWM5INTFbits_t
;
16457 extern __at(0x0D9D) volatile __PWM5INTFbits_t PWM5INTFbits
;
16460 #define _PWM5PRIF 0x01
16462 #define _PWM5DCIF 0x02
16464 #define _PWM5PHIF 0x04
16466 #define _PWM5OFIF 0x08
16468 //==============================================================================
16471 //==============================================================================
16474 extern __at(0x0D9D) __sfr PWM5INTFLG
;
16492 unsigned PWM5PRIF
: 1;
16493 unsigned PWM5DCIF
: 1;
16494 unsigned PWM5PHIF
: 1;
16495 unsigned PWM5OFIF
: 1;
16501 } __PWM5INTFLGbits_t
;
16503 extern __at(0x0D9D) volatile __PWM5INTFLGbits_t PWM5INTFLGbits
;
16505 #define _PWM5INTFLG_PRIF 0x01
16506 #define _PWM5INTFLG_PWM5PRIF 0x01
16507 #define _PWM5INTFLG_DCIF 0x02
16508 #define _PWM5INTFLG_PWM5DCIF 0x02
16509 #define _PWM5INTFLG_PHIF 0x04
16510 #define _PWM5INTFLG_PWM5PHIF 0x04
16511 #define _PWM5INTFLG_OFIF 0x08
16512 #define _PWM5INTFLG_PWM5OFIF 0x08
16514 //==============================================================================
16517 //==============================================================================
16520 extern __at(0x0D9E) __sfr PWM5CLKCON
;
16526 unsigned PWM5CS0
: 1;
16527 unsigned PWM5CS1
: 1;
16528 unsigned PWM5CS2
: 1;
16530 unsigned PWM5PS0
: 1;
16531 unsigned PWM5PS1
: 1;
16532 unsigned PWM5PS2
: 1;
16556 unsigned PWM5CS
: 3;
16570 unsigned PWM5PS
: 3;
16573 } __PWM5CLKCONbits_t
;
16575 extern __at(0x0D9E) volatile __PWM5CLKCONbits_t PWM5CLKCONbits
;
16577 #define _PWM5CLKCON_PWM5CS0 0x01
16578 #define _PWM5CLKCON_CS0 0x01
16579 #define _PWM5CLKCON_PWM5CS1 0x02
16580 #define _PWM5CLKCON_CS1 0x02
16581 #define _PWM5CLKCON_PWM5CS2 0x04
16582 #define _PWM5CLKCON_CS2 0x04
16583 #define _PWM5CLKCON_PWM5PS0 0x10
16584 #define _PWM5CLKCON_PS0 0x10
16585 #define _PWM5CLKCON_PWM5PS1 0x20
16586 #define _PWM5CLKCON_PS1 0x20
16587 #define _PWM5CLKCON_PWM5PS2 0x40
16588 #define _PWM5CLKCON_PS2 0x40
16590 //==============================================================================
16593 //==============================================================================
16596 extern __at(0x0D9F) __sfr PWM5LDCON
;
16602 unsigned PWM5LDS0
: 1;
16603 unsigned PWM5LDS1
: 1;
16620 unsigned PWM5LDM
: 1;
16621 unsigned PWM5LD
: 1;
16632 unsigned PWM5LDS
: 2;
16635 } __PWM5LDCONbits_t
;
16637 extern __at(0x0D9F) volatile __PWM5LDCONbits_t PWM5LDCONbits
;
16639 #define _PWM5LDS0 0x01
16641 #define _PWM5LDS1 0x02
16644 #define _PWM5LDM 0x40
16646 #define _PWM5LD 0x80
16648 //==============================================================================
16651 //==============================================================================
16654 extern __at(0x0DA0) __sfr PWM5OFCON
;
16660 unsigned PWM5OFS0
: 1;
16661 unsigned PWM5OFS1
: 1;
16665 unsigned PWM5OFM0
: 1;
16666 unsigned PWM5OFM1
: 1;
16676 unsigned PWM5OFMC
: 1;
16690 unsigned PWM5OFS
: 2;
16704 unsigned PWM5OFM
: 2;
16707 } __PWM5OFCONbits_t
;
16709 extern __at(0x0DA0) volatile __PWM5OFCONbits_t PWM5OFCONbits
;
16711 #define _PWM5OFS0 0x01
16713 #define _PWM5OFS1 0x02
16716 #define _PWM5OFMC 0x10
16717 #define _PWM5OFM0 0x20
16719 #define _PWM5OFM1 0x40
16722 //==============================================================================
16724 extern __at(0x0DA1) __sfr PWM6PH
;
16726 //==============================================================================
16729 extern __at(0x0DA1) __sfr PWM6PHL
;
16733 unsigned PWM6PHL0
: 1;
16734 unsigned PWM6PHL1
: 1;
16735 unsigned PWM6PHL2
: 1;
16736 unsigned PWM6PHL3
: 1;
16737 unsigned PWM6PHL4
: 1;
16738 unsigned PWM6PHL5
: 1;
16739 unsigned PWM6PHL6
: 1;
16740 unsigned PWM6PHL7
: 1;
16743 extern __at(0x0DA1) volatile __PWM6PHLbits_t PWM6PHLbits
;
16745 #define _PWM6PHL0 0x01
16746 #define _PWM6PHL1 0x02
16747 #define _PWM6PHL2 0x04
16748 #define _PWM6PHL3 0x08
16749 #define _PWM6PHL4 0x10
16750 #define _PWM6PHL5 0x20
16751 #define _PWM6PHL6 0x40
16752 #define _PWM6PHL7 0x80
16754 //==============================================================================
16757 //==============================================================================
16760 extern __at(0x0DA2) __sfr PWM6PHH
;
16764 unsigned PWM6PHH0
: 1;
16765 unsigned PWM6PHH1
: 1;
16766 unsigned PWM6PHH2
: 1;
16767 unsigned PWM6PHH3
: 1;
16768 unsigned PWM6PHH4
: 1;
16769 unsigned PWM6PHH5
: 1;
16770 unsigned PWM6PHH6
: 1;
16771 unsigned PWM6PHH7
: 1;
16774 extern __at(0x0DA2) volatile __PWM6PHHbits_t PWM6PHHbits
;
16776 #define _PWM6PHH0 0x01
16777 #define _PWM6PHH1 0x02
16778 #define _PWM6PHH2 0x04
16779 #define _PWM6PHH3 0x08
16780 #define _PWM6PHH4 0x10
16781 #define _PWM6PHH5 0x20
16782 #define _PWM6PHH6 0x40
16783 #define _PWM6PHH7 0x80
16785 //==============================================================================
16787 extern __at(0x0DA3) __sfr PWM6DC
;
16789 //==============================================================================
16792 extern __at(0x0DA3) __sfr PWM6DCL
;
16796 unsigned PWM6DCL0
: 1;
16797 unsigned PWM6DCL1
: 1;
16798 unsigned PWM6DCL2
: 1;
16799 unsigned PWM6DCL3
: 1;
16800 unsigned PWM6DCL4
: 1;
16801 unsigned PWM6DCL5
: 1;
16802 unsigned PWM6DCL6
: 1;
16803 unsigned PWM6DCL7
: 1;
16806 extern __at(0x0DA3) volatile __PWM6DCLbits_t PWM6DCLbits
;
16808 #define _PWM6DCL0 0x01
16809 #define _PWM6DCL1 0x02
16810 #define _PWM6DCL2 0x04
16811 #define _PWM6DCL3 0x08
16812 #define _PWM6DCL4 0x10
16813 #define _PWM6DCL5 0x20
16814 #define _PWM6DCL6 0x40
16815 #define _PWM6DCL7 0x80
16817 //==============================================================================
16820 //==============================================================================
16823 extern __at(0x0DA4) __sfr PWM6DCH
;
16827 unsigned PWM6DCH0
: 1;
16828 unsigned PWM6DCH1
: 1;
16829 unsigned PWM6DCH2
: 1;
16830 unsigned PWM6DCH3
: 1;
16831 unsigned PWM6DCH4
: 1;
16832 unsigned PWM6DCH5
: 1;
16833 unsigned PWM6DCH6
: 1;
16834 unsigned PWM6DCH7
: 1;
16837 extern __at(0x0DA4) volatile __PWM6DCHbits_t PWM6DCHbits
;
16839 #define _PWM6DCH0 0x01
16840 #define _PWM6DCH1 0x02
16841 #define _PWM6DCH2 0x04
16842 #define _PWM6DCH3 0x08
16843 #define _PWM6DCH4 0x10
16844 #define _PWM6DCH5 0x20
16845 #define _PWM6DCH6 0x40
16846 #define _PWM6DCH7 0x80
16848 //==============================================================================
16850 extern __at(0x0DA5) __sfr PWM6PR
;
16852 //==============================================================================
16855 extern __at(0x0DA5) __sfr PWM6PRL
;
16859 unsigned PWM6PRL0
: 1;
16860 unsigned PWM6PRL1
: 1;
16861 unsigned PWM6PRL2
: 1;
16862 unsigned PWM6PRL3
: 1;
16863 unsigned PWM6PRL4
: 1;
16864 unsigned PWM6PRL5
: 1;
16865 unsigned PWM6PRL6
: 1;
16866 unsigned PWM6PRL7
: 1;
16869 extern __at(0x0DA5) volatile __PWM6PRLbits_t PWM6PRLbits
;
16871 #define _PWM6PRL0 0x01
16872 #define _PWM6PRL1 0x02
16873 #define _PWM6PRL2 0x04
16874 #define _PWM6PRL3 0x08
16875 #define _PWM6PRL4 0x10
16876 #define _PWM6PRL5 0x20
16877 #define _PWM6PRL6 0x40
16878 #define _PWM6PRL7 0x80
16880 //==============================================================================
16883 //==============================================================================
16886 extern __at(0x0DA6) __sfr PWM6PRH
;
16890 unsigned PWM6PRH0
: 1;
16891 unsigned PWM6PRH1
: 1;
16892 unsigned PWM6PRH2
: 1;
16893 unsigned PWM6PRH3
: 1;
16894 unsigned PWM6PRH4
: 1;
16895 unsigned PWM6PRH5
: 1;
16896 unsigned PWM6PRH6
: 1;
16897 unsigned PWM6PRH7
: 1;
16900 extern __at(0x0DA6) volatile __PWM6PRHbits_t PWM6PRHbits
;
16902 #define _PWM6PRH0 0x01
16903 #define _PWM6PRH1 0x02
16904 #define _PWM6PRH2 0x04
16905 #define _PWM6PRH3 0x08
16906 #define _PWM6PRH4 0x10
16907 #define _PWM6PRH5 0x20
16908 #define _PWM6PRH6 0x40
16909 #define _PWM6PRH7 0x80
16911 //==============================================================================
16913 extern __at(0x0DA7) __sfr PWM6OF
;
16915 //==============================================================================
16918 extern __at(0x0DA7) __sfr PWM6OFL
;
16922 unsigned PWM6OFL0
: 1;
16923 unsigned PWM6OFL1
: 1;
16924 unsigned PWM6OFL2
: 1;
16925 unsigned PWM6OFL3
: 1;
16926 unsigned PWM6OFL4
: 1;
16927 unsigned PWM6OFL5
: 1;
16928 unsigned PWM6OFL6
: 1;
16929 unsigned PWM6OFL7
: 1;
16932 extern __at(0x0DA7) volatile __PWM6OFLbits_t PWM6OFLbits
;
16934 #define _PWM6OFL0 0x01
16935 #define _PWM6OFL1 0x02
16936 #define _PWM6OFL2 0x04
16937 #define _PWM6OFL3 0x08
16938 #define _PWM6OFL4 0x10
16939 #define _PWM6OFL5 0x20
16940 #define _PWM6OFL6 0x40
16941 #define _PWM6OFL7 0x80
16943 //==============================================================================
16946 //==============================================================================
16949 extern __at(0x0DA8) __sfr PWM6OFH
;
16953 unsigned PWM6OFH0
: 1;
16954 unsigned PWM6OFH1
: 1;
16955 unsigned PWM6OFH2
: 1;
16956 unsigned PWM6OFH3
: 1;
16957 unsigned PWM6OFH4
: 1;
16958 unsigned PWM6OFH5
: 1;
16959 unsigned PWM6OFH6
: 1;
16960 unsigned PWM6OFH7
: 1;
16963 extern __at(0x0DA8) volatile __PWM6OFHbits_t PWM6OFHbits
;
16965 #define _PWM6OFH0 0x01
16966 #define _PWM6OFH1 0x02
16967 #define _PWM6OFH2 0x04
16968 #define _PWM6OFH3 0x08
16969 #define _PWM6OFH4 0x10
16970 #define _PWM6OFH5 0x20
16971 #define _PWM6OFH6 0x40
16972 #define _PWM6OFH7 0x80
16974 //==============================================================================
16976 extern __at(0x0DA9) __sfr PWM6TMR
;
16978 //==============================================================================
16981 extern __at(0x0DA9) __sfr PWM6TMRL
;
16985 unsigned PWM6TMRL0
: 1;
16986 unsigned PWM6TMRL1
: 1;
16987 unsigned PWM6TMRL2
: 1;
16988 unsigned PWM6TMRL3
: 1;
16989 unsigned PWM6TMRL4
: 1;
16990 unsigned PWM6TMRL5
: 1;
16991 unsigned PWM6TMRL6
: 1;
16992 unsigned PWM6TMRL7
: 1;
16993 } __PWM6TMRLbits_t
;
16995 extern __at(0x0DA9) volatile __PWM6TMRLbits_t PWM6TMRLbits
;
16997 #define _PWM6TMRL0 0x01
16998 #define _PWM6TMRL1 0x02
16999 #define _PWM6TMRL2 0x04
17000 #define _PWM6TMRL3 0x08
17001 #define _PWM6TMRL4 0x10
17002 #define _PWM6TMRL5 0x20
17003 #define _PWM6TMRL6 0x40
17004 #define _PWM6TMRL7 0x80
17006 //==============================================================================
17009 //==============================================================================
17012 extern __at(0x0DAA) __sfr PWM6TMRH
;
17016 unsigned PWM6TMRH0
: 1;
17017 unsigned PWM6TMRH1
: 1;
17018 unsigned PWM6TMRH2
: 1;
17019 unsigned PWM6TMRH3
: 1;
17020 unsigned PWM6TMRH4
: 1;
17021 unsigned PWM6TMRH5
: 1;
17022 unsigned PWM6TMRH6
: 1;
17023 unsigned PWM6TMRH7
: 1;
17024 } __PWM6TMRHbits_t
;
17026 extern __at(0x0DAA) volatile __PWM6TMRHbits_t PWM6TMRHbits
;
17028 #define _PWM6TMRH0 0x01
17029 #define _PWM6TMRH1 0x02
17030 #define _PWM6TMRH2 0x04
17031 #define _PWM6TMRH3 0x08
17032 #define _PWM6TMRH4 0x10
17033 #define _PWM6TMRH5 0x20
17034 #define _PWM6TMRH6 0x40
17035 #define _PWM6TMRH7 0x80
17037 //==============================================================================
17040 //==============================================================================
17043 extern __at(0x0DAB) __sfr PWM6CON
;
17051 unsigned PWM6MODE0
: 1;
17052 unsigned PWM6MODE1
: 1;
17063 unsigned MODE0
: 1;
17064 unsigned MODE1
: 1;
17065 unsigned PWM6POL
: 1;
17066 unsigned PWM6OUT
: 1;
17068 unsigned PWM6EN
: 1;
17074 unsigned PWM6MODE
: 2;
17086 extern __at(0x0DAB) volatile __PWM6CONbits_t PWM6CONbits
;
17088 #define _PWM6CON_PWM6MODE0 0x04
17089 #define _PWM6CON_MODE0 0x04
17090 #define _PWM6CON_PWM6MODE1 0x08
17091 #define _PWM6CON_MODE1 0x08
17092 #define _PWM6CON_POL 0x10
17093 #define _PWM6CON_PWM6POL 0x10
17094 #define _PWM6CON_OUT 0x20
17095 #define _PWM6CON_PWM6OUT 0x20
17096 #define _PWM6CON_EN 0x80
17097 #define _PWM6CON_PWM6EN 0x80
17099 //==============================================================================
17102 //==============================================================================
17105 extern __at(0x0DAC) __sfr PWM6INTCON
;
17123 unsigned PWM6PRIE
: 1;
17124 unsigned PWM6DCIE
: 1;
17125 unsigned PWM6PHIE
: 1;
17126 unsigned PWM6OFIE
: 1;
17132 } __PWM6INTCONbits_t
;
17134 extern __at(0x0DAC) volatile __PWM6INTCONbits_t PWM6INTCONbits
;
17136 #define _PWM6INTCON_PRIE 0x01
17137 #define _PWM6INTCON_PWM6PRIE 0x01
17138 #define _PWM6INTCON_DCIE 0x02
17139 #define _PWM6INTCON_PWM6DCIE 0x02
17140 #define _PWM6INTCON_PHIE 0x04
17141 #define _PWM6INTCON_PWM6PHIE 0x04
17142 #define _PWM6INTCON_OFIE 0x08
17143 #define _PWM6INTCON_PWM6OFIE 0x08
17145 //==============================================================================
17148 //==============================================================================
17151 extern __at(0x0DAC) __sfr PWM6INTE
;
17169 unsigned PWM6PRIE
: 1;
17170 unsigned PWM6DCIE
: 1;
17171 unsigned PWM6PHIE
: 1;
17172 unsigned PWM6OFIE
: 1;
17178 } __PWM6INTEbits_t
;
17180 extern __at(0x0DAC) volatile __PWM6INTEbits_t PWM6INTEbits
;
17182 #define _PWM6INTE_PRIE 0x01
17183 #define _PWM6INTE_PWM6PRIE 0x01
17184 #define _PWM6INTE_DCIE 0x02
17185 #define _PWM6INTE_PWM6DCIE 0x02
17186 #define _PWM6INTE_PHIE 0x04
17187 #define _PWM6INTE_PWM6PHIE 0x04
17188 #define _PWM6INTE_OFIE 0x08
17189 #define _PWM6INTE_PWM6OFIE 0x08
17191 //==============================================================================
17194 //==============================================================================
17197 extern __at(0x0DAD) __sfr PWM6INTF
;
17215 unsigned PWM6PRIF
: 1;
17216 unsigned PWM6DCIF
: 1;
17217 unsigned PWM6PHIF
: 1;
17218 unsigned PWM6OFIF
: 1;
17224 } __PWM6INTFbits_t
;
17226 extern __at(0x0DAD) volatile __PWM6INTFbits_t PWM6INTFbits
;
17228 #define _PWM6INTF_PRIF 0x01
17229 #define _PWM6INTF_PWM6PRIF 0x01
17230 #define _PWM6INTF_DCIF 0x02
17231 #define _PWM6INTF_PWM6DCIF 0x02
17232 #define _PWM6INTF_PHIF 0x04
17233 #define _PWM6INTF_PWM6PHIF 0x04
17234 #define _PWM6INTF_OFIF 0x08
17235 #define _PWM6INTF_PWM6OFIF 0x08
17237 //==============================================================================
17240 //==============================================================================
17243 extern __at(0x0DAD) __sfr PWM6INTFLG
;
17261 unsigned PWM6PRIF
: 1;
17262 unsigned PWM6DCIF
: 1;
17263 unsigned PWM6PHIF
: 1;
17264 unsigned PWM6OFIF
: 1;
17270 } __PWM6INTFLGbits_t
;
17272 extern __at(0x0DAD) volatile __PWM6INTFLGbits_t PWM6INTFLGbits
;
17274 #define _PWM6INTFLG_PRIF 0x01
17275 #define _PWM6INTFLG_PWM6PRIF 0x01
17276 #define _PWM6INTFLG_DCIF 0x02
17277 #define _PWM6INTFLG_PWM6DCIF 0x02
17278 #define _PWM6INTFLG_PHIF 0x04
17279 #define _PWM6INTFLG_PWM6PHIF 0x04
17280 #define _PWM6INTFLG_OFIF 0x08
17281 #define _PWM6INTFLG_PWM6OFIF 0x08
17283 //==============================================================================
17286 //==============================================================================
17289 extern __at(0x0DAE) __sfr PWM6CLKCON
;
17295 unsigned PWM6CS0
: 1;
17296 unsigned PWM6CS1
: 1;
17297 unsigned PWM6CS2
: 1;
17299 unsigned PWM6PS0
: 1;
17300 unsigned PWM6PS1
: 1;
17301 unsigned PWM6PS2
: 1;
17325 unsigned PWM6CS
: 3;
17332 unsigned PWM6PS
: 3;
17342 } __PWM6CLKCONbits_t
;
17344 extern __at(0x0DAE) volatile __PWM6CLKCONbits_t PWM6CLKCONbits
;
17346 #define _PWM6CLKCON_PWM6CS0 0x01
17347 #define _PWM6CLKCON_CS0 0x01
17348 #define _PWM6CLKCON_PWM6CS1 0x02
17349 #define _PWM6CLKCON_CS1 0x02
17350 #define _PWM6CLKCON_PWM6CS2 0x04
17351 #define _PWM6CLKCON_CS2 0x04
17352 #define _PWM6CLKCON_PWM6PS0 0x10
17353 #define _PWM6CLKCON_PS0 0x10
17354 #define _PWM6CLKCON_PWM6PS1 0x20
17355 #define _PWM6CLKCON_PS1 0x20
17356 #define _PWM6CLKCON_PWM6PS2 0x40
17357 #define _PWM6CLKCON_PS2 0x40
17359 //==============================================================================
17362 //==============================================================================
17365 extern __at(0x0DAF) __sfr PWM6LDCON
;
17371 unsigned PWM6LDS0
: 1;
17372 unsigned PWM6LDS1
: 1;
17389 unsigned PWM6LDM
: 1;
17390 unsigned PWM6LD
: 1;
17401 unsigned PWM6LDS
: 2;
17404 } __PWM6LDCONbits_t
;
17406 extern __at(0x0DAF) volatile __PWM6LDCONbits_t PWM6LDCONbits
;
17408 #define _PWM6LDCON_PWM6LDS0 0x01
17409 #define _PWM6LDCON_LDS0 0x01
17410 #define _PWM6LDCON_PWM6LDS1 0x02
17411 #define _PWM6LDCON_LDS1 0x02
17412 #define _PWM6LDCON_LDT 0x40
17413 #define _PWM6LDCON_PWM6LDM 0x40
17414 #define _PWM6LDCON_LDA 0x80
17415 #define _PWM6LDCON_PWM6LD 0x80
17417 //==============================================================================
17420 //==============================================================================
17423 extern __at(0x0DB0) __sfr PWM6OFCON
;
17429 unsigned PWM6OFS0
: 1;
17430 unsigned PWM6OFS1
: 1;
17434 unsigned PWM6OFM0
: 1;
17435 unsigned PWM6OFM1
: 1;
17445 unsigned PWM6OFMC
: 1;
17453 unsigned PWM6OFS
: 2;
17473 unsigned PWM6OFM
: 2;
17476 } __PWM6OFCONbits_t
;
17478 extern __at(0x0DB0) volatile __PWM6OFCONbits_t PWM6OFCONbits
;
17480 #define _PWM6OFCON_PWM6OFS0 0x01
17481 #define _PWM6OFCON_OFS0 0x01
17482 #define _PWM6OFCON_PWM6OFS1 0x02
17483 #define _PWM6OFCON_OFS1 0x02
17484 #define _PWM6OFCON_OFO 0x10
17485 #define _PWM6OFCON_PWM6OFMC 0x10
17486 #define _PWM6OFCON_PWM6OFM0 0x20
17487 #define _PWM6OFCON_OFM0 0x20
17488 #define _PWM6OFCON_PWM6OFM1 0x40
17489 #define _PWM6OFCON_OFM1 0x40
17491 //==============================================================================
17493 extern __at(0x0DB1) __sfr PWM11PH
;
17495 //==============================================================================
17498 extern __at(0x0DB1) __sfr PWM11PHL
;
17502 unsigned PWM11PHL0
: 1;
17503 unsigned PWM11PHL1
: 1;
17504 unsigned PWM11PHL2
: 1;
17505 unsigned PWM11PHL3
: 1;
17506 unsigned PWM11PHL4
: 1;
17507 unsigned PWM11PHL5
: 1;
17508 unsigned PWM11PHL6
: 1;
17509 unsigned PWM11PHL7
: 1;
17510 } __PWM11PHLbits_t
;
17512 extern __at(0x0DB1) volatile __PWM11PHLbits_t PWM11PHLbits
;
17514 #define _PWM11PHL0 0x01
17515 #define _PWM11PHL1 0x02
17516 #define _PWM11PHL2 0x04
17517 #define _PWM11PHL3 0x08
17518 #define _PWM11PHL4 0x10
17519 #define _PWM11PHL5 0x20
17520 #define _PWM11PHL6 0x40
17521 #define _PWM11PHL7 0x80
17523 //==============================================================================
17526 //==============================================================================
17529 extern __at(0x0DB2) __sfr PWM11PHH
;
17533 unsigned PWM11PHH0
: 1;
17534 unsigned PWM11PHH1
: 1;
17535 unsigned PWM11PHH2
: 1;
17536 unsigned PWM11PHH3
: 1;
17537 unsigned PWM11PHH4
: 1;
17538 unsigned PWM11PHH5
: 1;
17539 unsigned PWM11PHH6
: 1;
17540 unsigned PWM11PHH7
: 1;
17541 } __PWM11PHHbits_t
;
17543 extern __at(0x0DB2) volatile __PWM11PHHbits_t PWM11PHHbits
;
17545 #define _PWM11PHH0 0x01
17546 #define _PWM11PHH1 0x02
17547 #define _PWM11PHH2 0x04
17548 #define _PWM11PHH3 0x08
17549 #define _PWM11PHH4 0x10
17550 #define _PWM11PHH5 0x20
17551 #define _PWM11PHH6 0x40
17552 #define _PWM11PHH7 0x80
17554 //==============================================================================
17556 extern __at(0x0DB3) __sfr PWM11DC
;
17558 //==============================================================================
17561 extern __at(0x0DB3) __sfr PWM11DCL
;
17565 unsigned PWM11DCL0
: 1;
17566 unsigned PWM11DCL1
: 1;
17567 unsigned PWM11DCL2
: 1;
17568 unsigned PWM11DCL3
: 1;
17569 unsigned PWM11DCL4
: 1;
17570 unsigned PWM11DCL5
: 1;
17571 unsigned PWM11DCL6
: 1;
17572 unsigned PWM11DCL7
: 1;
17573 } __PWM11DCLbits_t
;
17575 extern __at(0x0DB3) volatile __PWM11DCLbits_t PWM11DCLbits
;
17577 #define _PWM11DCL0 0x01
17578 #define _PWM11DCL1 0x02
17579 #define _PWM11DCL2 0x04
17580 #define _PWM11DCL3 0x08
17581 #define _PWM11DCL4 0x10
17582 #define _PWM11DCL5 0x20
17583 #define _PWM11DCL6 0x40
17584 #define _PWM11DCL7 0x80
17586 //==============================================================================
17589 //==============================================================================
17592 extern __at(0x0DB4) __sfr PWM11DCH
;
17596 unsigned PWM11DCH0
: 1;
17597 unsigned PWM11DCH1
: 1;
17598 unsigned PWM11DCH2
: 1;
17599 unsigned PWM11DCH3
: 1;
17600 unsigned PWM11DCH4
: 1;
17601 unsigned PWM11DCH5
: 1;
17602 unsigned PWM11DCH6
: 1;
17603 unsigned PWM11DCH7
: 1;
17604 } __PWM11DCHbits_t
;
17606 extern __at(0x0DB4) volatile __PWM11DCHbits_t PWM11DCHbits
;
17608 #define _PWM11DCH0 0x01
17609 #define _PWM11DCH1 0x02
17610 #define _PWM11DCH2 0x04
17611 #define _PWM11DCH3 0x08
17612 #define _PWM11DCH4 0x10
17613 #define _PWM11DCH5 0x20
17614 #define _PWM11DCH6 0x40
17615 #define _PWM11DCH7 0x80
17617 //==============================================================================
17619 extern __at(0x0DB5) __sfr PWM11PR
;
17621 //==============================================================================
17624 extern __at(0x0DB5) __sfr PWM11PRL
;
17628 unsigned PWM11PRL0
: 1;
17629 unsigned PWM11PRL1
: 1;
17630 unsigned PWM11PRL2
: 1;
17631 unsigned PWM11PRL3
: 1;
17632 unsigned PWM11PRL4
: 1;
17633 unsigned PWM11PRL5
: 1;
17634 unsigned PWM11PRL6
: 1;
17635 unsigned PWM11PRL7
: 1;
17636 } __PWM11PRLbits_t
;
17638 extern __at(0x0DB5) volatile __PWM11PRLbits_t PWM11PRLbits
;
17640 #define _PWM11PRL0 0x01
17641 #define _PWM11PRL1 0x02
17642 #define _PWM11PRL2 0x04
17643 #define _PWM11PRL3 0x08
17644 #define _PWM11PRL4 0x10
17645 #define _PWM11PRL5 0x20
17646 #define _PWM11PRL6 0x40
17647 #define _PWM11PRL7 0x80
17649 //==============================================================================
17652 //==============================================================================
17655 extern __at(0x0DB6) __sfr PWM11PRH
;
17659 unsigned PWM11PRH0
: 1;
17660 unsigned PWM11PRH1
: 1;
17661 unsigned PWM11PRH2
: 1;
17662 unsigned PWM11PRH3
: 1;
17663 unsigned PWM11PRH4
: 1;
17664 unsigned PWM11PRH5
: 1;
17665 unsigned PWM11PRH6
: 1;
17666 unsigned PWM11PRH7
: 1;
17667 } __PWM11PRHbits_t
;
17669 extern __at(0x0DB6) volatile __PWM11PRHbits_t PWM11PRHbits
;
17671 #define _PWM11PRH0 0x01
17672 #define _PWM11PRH1 0x02
17673 #define _PWM11PRH2 0x04
17674 #define _PWM11PRH3 0x08
17675 #define _PWM11PRH4 0x10
17676 #define _PWM11PRH5 0x20
17677 #define _PWM11PRH6 0x40
17678 #define _PWM11PRH7 0x80
17680 //==============================================================================
17682 extern __at(0x0DB7) __sfr PWM11OF
;
17684 //==============================================================================
17687 extern __at(0x0DB7) __sfr PWM11OFL
;
17691 unsigned PWM11OFL0
: 1;
17692 unsigned PWM11OFL1
: 1;
17693 unsigned PWM11OFL2
: 1;
17694 unsigned PWM11OFL3
: 1;
17695 unsigned PWM11OFL4
: 1;
17696 unsigned PWM11OFL5
: 1;
17697 unsigned PWM11OFL6
: 1;
17698 unsigned PWM11OFL7
: 1;
17699 } __PWM11OFLbits_t
;
17701 extern __at(0x0DB7) volatile __PWM11OFLbits_t PWM11OFLbits
;
17703 #define _PWM11OFL0 0x01
17704 #define _PWM11OFL1 0x02
17705 #define _PWM11OFL2 0x04
17706 #define _PWM11OFL3 0x08
17707 #define _PWM11OFL4 0x10
17708 #define _PWM11OFL5 0x20
17709 #define _PWM11OFL6 0x40
17710 #define _PWM11OFL7 0x80
17712 //==============================================================================
17715 //==============================================================================
17718 extern __at(0x0DB8) __sfr PWM11OFH
;
17722 unsigned PWM11OFH0
: 1;
17723 unsigned PWM11OFH1
: 1;
17724 unsigned PWM11OFH2
: 1;
17725 unsigned PWM11OFH3
: 1;
17726 unsigned PWM11OFH4
: 1;
17727 unsigned PWM11OFH5
: 1;
17728 unsigned PWM11OFH6
: 1;
17729 unsigned PWM11OFH7
: 1;
17730 } __PWM11OFHbits_t
;
17732 extern __at(0x0DB8) volatile __PWM11OFHbits_t PWM11OFHbits
;
17734 #define _PWM11OFH0 0x01
17735 #define _PWM11OFH1 0x02
17736 #define _PWM11OFH2 0x04
17737 #define _PWM11OFH3 0x08
17738 #define _PWM11OFH4 0x10
17739 #define _PWM11OFH5 0x20
17740 #define _PWM11OFH6 0x40
17741 #define _PWM11OFH7 0x80
17743 //==============================================================================
17745 extern __at(0x0DB9) __sfr PWM11TMR
;
17747 //==============================================================================
17750 extern __at(0x0DB9) __sfr PWM11TMRL
;
17754 unsigned PWM11TMRL0
: 1;
17755 unsigned PWM11TMRL1
: 1;
17756 unsigned PWM11TMRL2
: 1;
17757 unsigned PWM11TMRL3
: 1;
17758 unsigned PWM11TMRL4
: 1;
17759 unsigned PWM11TMRL5
: 1;
17760 unsigned PWM11TMRL6
: 1;
17761 unsigned PWM11TMRL7
: 1;
17762 } __PWM11TMRLbits_t
;
17764 extern __at(0x0DB9) volatile __PWM11TMRLbits_t PWM11TMRLbits
;
17766 #define _PWM11TMRL0 0x01
17767 #define _PWM11TMRL1 0x02
17768 #define _PWM11TMRL2 0x04
17769 #define _PWM11TMRL3 0x08
17770 #define _PWM11TMRL4 0x10
17771 #define _PWM11TMRL5 0x20
17772 #define _PWM11TMRL6 0x40
17773 #define _PWM11TMRL7 0x80
17775 //==============================================================================
17778 //==============================================================================
17781 extern __at(0x0DBA) __sfr PWM11TMRH
;
17785 unsigned PWM11TMRH0
: 1;
17786 unsigned PWM11TMRH1
: 1;
17787 unsigned PWM11TMRH2
: 1;
17788 unsigned PWM11TMRH3
: 1;
17789 unsigned PWM11TMRH4
: 1;
17790 unsigned PWM11TMRH5
: 1;
17791 unsigned PWM11TMRH6
: 1;
17792 unsigned PWM11TMRH7
: 1;
17793 } __PWM11TMRHbits_t
;
17795 extern __at(0x0DBA) volatile __PWM11TMRHbits_t PWM11TMRHbits
;
17797 #define _PWM11TMRH0 0x01
17798 #define _PWM11TMRH1 0x02
17799 #define _PWM11TMRH2 0x04
17800 #define _PWM11TMRH3 0x08
17801 #define _PWM11TMRH4 0x10
17802 #define _PWM11TMRH5 0x20
17803 #define _PWM11TMRH6 0x40
17804 #define _PWM11TMRH7 0x80
17806 //==============================================================================
17809 //==============================================================================
17812 extern __at(0x0DBB) __sfr PWM11CON
;
17820 unsigned PWM11MODE0
: 1;
17821 unsigned PWM11MODE1
: 1;
17832 unsigned MODE0
: 1;
17833 unsigned MODE1
: 1;
17834 unsigned PWM11POL
: 1;
17835 unsigned PWM11OUT
: 1;
17837 unsigned PWM11EN
: 1;
17843 unsigned PWM11MODE
: 2;
17853 } __PWM11CONbits_t
;
17855 extern __at(0x0DBB) volatile __PWM11CONbits_t PWM11CONbits
;
17857 #define _PWM11CON_PWM11MODE0 0x04
17858 #define _PWM11CON_MODE0 0x04
17859 #define _PWM11CON_PWM11MODE1 0x08
17860 #define _PWM11CON_MODE1 0x08
17861 #define _PWM11CON_POL 0x10
17862 #define _PWM11CON_PWM11POL 0x10
17863 #define _PWM11CON_OUT 0x20
17864 #define _PWM11CON_PWM11OUT 0x20
17865 #define _PWM11CON_EN 0x80
17866 #define _PWM11CON_PWM11EN 0x80
17868 //==============================================================================
17871 //==============================================================================
17872 // PWM11INTCON Bits
17874 extern __at(0x0DBC) __sfr PWM11INTCON
;
17892 unsigned PWM11PRIE
: 1;
17893 unsigned PWM11DCIE
: 1;
17894 unsigned PWM11PHIE
: 1;
17895 unsigned PWM11OFIE
: 1;
17901 } __PWM11INTCONbits_t
;
17903 extern __at(0x0DBC) volatile __PWM11INTCONbits_t PWM11INTCONbits
;
17905 #define _PWM11INTCON_PRIE 0x01
17906 #define _PWM11INTCON_PWM11PRIE 0x01
17907 #define _PWM11INTCON_DCIE 0x02
17908 #define _PWM11INTCON_PWM11DCIE 0x02
17909 #define _PWM11INTCON_PHIE 0x04
17910 #define _PWM11INTCON_PWM11PHIE 0x04
17911 #define _PWM11INTCON_OFIE 0x08
17912 #define _PWM11INTCON_PWM11OFIE 0x08
17914 //==============================================================================
17917 //==============================================================================
17920 extern __at(0x0DBC) __sfr PWM11INTE
;
17938 unsigned PWM11PRIE
: 1;
17939 unsigned PWM11DCIE
: 1;
17940 unsigned PWM11PHIE
: 1;
17941 unsigned PWM11OFIE
: 1;
17947 } __PWM11INTEbits_t
;
17949 extern __at(0x0DBC) volatile __PWM11INTEbits_t PWM11INTEbits
;
17951 #define _PWM11INTE_PRIE 0x01
17952 #define _PWM11INTE_PWM11PRIE 0x01
17953 #define _PWM11INTE_DCIE 0x02
17954 #define _PWM11INTE_PWM11DCIE 0x02
17955 #define _PWM11INTE_PHIE 0x04
17956 #define _PWM11INTE_PWM11PHIE 0x04
17957 #define _PWM11INTE_OFIE 0x08
17958 #define _PWM11INTE_PWM11OFIE 0x08
17960 //==============================================================================
17963 //==============================================================================
17966 extern __at(0x0DBD) __sfr PWM11INTF
;
17984 unsigned PWM11PRIF
: 1;
17985 unsigned PWM11DCIF
: 1;
17986 unsigned PWM11PHIF
: 1;
17987 unsigned PWM11OFIF
: 1;
17993 } __PWM11INTFbits_t
;
17995 extern __at(0x0DBD) volatile __PWM11INTFbits_t PWM11INTFbits
;
17997 #define _PWM11INTF_PRIF 0x01
17998 #define _PWM11INTF_PWM11PRIF 0x01
17999 #define _PWM11INTF_DCIF 0x02
18000 #define _PWM11INTF_PWM11DCIF 0x02
18001 #define _PWM11INTF_PHIF 0x04
18002 #define _PWM11INTF_PWM11PHIF 0x04
18003 #define _PWM11INTF_OFIF 0x08
18004 #define _PWM11INTF_PWM11OFIF 0x08
18006 //==============================================================================
18009 //==============================================================================
18010 // PWM11INTFLG Bits
18012 extern __at(0x0DBD) __sfr PWM11INTFLG
;
18030 unsigned PWM11PRIF
: 1;
18031 unsigned PWM11DCIF
: 1;
18032 unsigned PWM11PHIF
: 1;
18033 unsigned PWM11OFIF
: 1;
18039 } __PWM11INTFLGbits_t
;
18041 extern __at(0x0DBD) volatile __PWM11INTFLGbits_t PWM11INTFLGbits
;
18043 #define _PWM11INTFLG_PRIF 0x01
18044 #define _PWM11INTFLG_PWM11PRIF 0x01
18045 #define _PWM11INTFLG_DCIF 0x02
18046 #define _PWM11INTFLG_PWM11DCIF 0x02
18047 #define _PWM11INTFLG_PHIF 0x04
18048 #define _PWM11INTFLG_PWM11PHIF 0x04
18049 #define _PWM11INTFLG_OFIF 0x08
18050 #define _PWM11INTFLG_PWM11OFIF 0x08
18052 //==============================================================================
18055 //==============================================================================
18056 // PWM11CLKCON Bits
18058 extern __at(0x0DBE) __sfr PWM11CLKCON
;
18064 unsigned PWM11CS0
: 1;
18065 unsigned PWM11CS1
: 1;
18066 unsigned PWM11CS2
: 1;
18068 unsigned PWM11PS0
: 1;
18069 unsigned PWM11PS1
: 1;
18070 unsigned PWM11PS2
: 1;
18088 unsigned PWM11CS
: 3;
18108 unsigned PWM11PS
: 3;
18111 } __PWM11CLKCONbits_t
;
18113 extern __at(0x0DBE) volatile __PWM11CLKCONbits_t PWM11CLKCONbits
;
18115 #define _PWM11CLKCON_PWM11CS0 0x01
18116 #define _PWM11CLKCON_CS0 0x01
18117 #define _PWM11CLKCON_PWM11CS1 0x02
18118 #define _PWM11CLKCON_CS1 0x02
18119 #define _PWM11CLKCON_PWM11CS2 0x04
18120 #define _PWM11CLKCON_CS2 0x04
18121 #define _PWM11CLKCON_PWM11PS0 0x10
18122 #define _PWM11CLKCON_PS0 0x10
18123 #define _PWM11CLKCON_PWM11PS1 0x20
18124 #define _PWM11CLKCON_PS1 0x20
18125 #define _PWM11CLKCON_PWM11PS2 0x40
18126 #define _PWM11CLKCON_PS2 0x40
18128 //==============================================================================
18131 //==============================================================================
18134 extern __at(0x0DBF) __sfr PWM11LDCON
;
18140 unsigned PWM11LDS0
: 1;
18141 unsigned PWM11LDS1
: 1;
18158 unsigned PWM11LDM
: 1;
18159 unsigned PWM11LD
: 1;
18164 unsigned PWM11LDS
: 2;
18173 } __PWM11LDCONbits_t
;
18175 extern __at(0x0DBF) volatile __PWM11LDCONbits_t PWM11LDCONbits
;
18177 #define _PWM11LDCON_PWM11LDS0 0x01
18178 #define _PWM11LDCON_LDS0 0x01
18179 #define _PWM11LDCON_PWM11LDS1 0x02
18180 #define _PWM11LDCON_LDS1 0x02
18181 #define _PWM11LDCON_LDT 0x40
18182 #define _PWM11LDCON_PWM11LDM 0x40
18183 #define _PWM11LDCON_LDA 0x80
18184 #define _PWM11LDCON_PWM11LD 0x80
18186 //==============================================================================
18189 //==============================================================================
18192 extern __at(0x0DC0) __sfr PWM11OFCON
;
18198 unsigned PWM11OFS0
: 1;
18199 unsigned PWM11OFS1
: 1;
18203 unsigned PWM11OFM0
: 1;
18204 unsigned PWM11OFM1
: 1;
18214 unsigned PWM11OFMC
: 1;
18228 unsigned PWM11OFS
: 2;
18235 unsigned PWM11OFM
: 2;
18245 } __PWM11OFCONbits_t
;
18247 extern __at(0x0DC0) volatile __PWM11OFCONbits_t PWM11OFCONbits
;
18249 #define _PWM11OFCON_PWM11OFS0 0x01
18250 #define _PWM11OFCON_OFS0 0x01
18251 #define _PWM11OFCON_PWM11OFS1 0x02
18252 #define _PWM11OFCON_OFS1 0x02
18253 #define _PWM11OFCON_OFO 0x10
18254 #define _PWM11OFCON_PWM11OFMC 0x10
18255 #define _PWM11OFCON_PWM11OFM0 0x20
18256 #define _PWM11OFCON_OFM0 0x20
18257 #define _PWM11OFCON_PWM11OFM1 0x40
18258 #define _PWM11OFCON_OFM1 0x40
18260 //==============================================================================
18263 //==============================================================================
18266 extern __at(0x0E0C) __sfr PPSLOCK
;
18270 unsigned PPSLOCKED
: 1;
18280 extern __at(0x0E0C) volatile __PPSLOCKbits_t PPSLOCKbits
;
18282 #define _PPSLOCKED 0x01
18284 //==============================================================================
18286 extern __at(0x0E0D) __sfr INTPPS
;
18287 extern __at(0x0E0E) __sfr T0CKIPPS
;
18288 extern __at(0x0E0F) __sfr T1CKIPPS
;
18289 extern __at(0x0E10) __sfr T1GPPS
;
18290 extern __at(0x0E11) __sfr T3CKIPPS
;
18291 extern __at(0x0E12) __sfr T3GPPS
;
18292 extern __at(0x0E13) __sfr T5CKIPPS
;
18293 extern __at(0x0E14) __sfr T5GPPS
;
18294 extern __at(0x0E15) __sfr T2CKIPPS
;
18295 extern __at(0x0E16) __sfr T4CKIPPS
;
18296 extern __at(0x0E17) __sfr T6CKIPPS
;
18297 extern __at(0x0E18) __sfr T8CKIPPS
;
18298 extern __at(0x0E19) __sfr CCP1PPS
;
18299 extern __at(0x0E1A) __sfr CCP2PPS
;
18300 extern __at(0x0E1B) __sfr CCP7PPS
;
18301 extern __at(0x0E1D) __sfr COG1INPPS
;
18302 extern __at(0x0E1E) __sfr COG2INPPS
;
18303 extern __at(0x0E1F) __sfr COG3INPPS
;
18304 extern __at(0x0E21) __sfr MD1CLPPS
;
18305 extern __at(0x0E22) __sfr MD1CHPPS
;
18306 extern __at(0x0E23) __sfr MD1MODPPS
;
18307 extern __at(0x0E24) __sfr MD2CLPPS
;
18308 extern __at(0x0E25) __sfr MD2CHPPS
;
18309 extern __at(0x0E26) __sfr MD2MODPPS
;
18310 extern __at(0x0E27) __sfr MD3CLPPS
;
18311 extern __at(0x0E28) __sfr MD3CHPPS
;
18312 extern __at(0x0E29) __sfr MD3MODPPS
;
18313 extern __at(0x0E2D) __sfr PRG1RPPS
;
18314 extern __at(0x0E2E) __sfr PRG1FPPS
;
18315 extern __at(0x0E2F) __sfr PRG2RPPS
;
18316 extern __at(0x0E30) __sfr PRG2FPPS
;
18317 extern __at(0x0E31) __sfr PRG3RPPS
;
18318 extern __at(0x0E32) __sfr PRG3FPPS
;
18319 extern __at(0x0E35) __sfr CLCIN0PPS
;
18320 extern __at(0x0E36) __sfr CLCIN1PPS
;
18321 extern __at(0x0E37) __sfr CLCIN2PPS
;
18322 extern __at(0x0E38) __sfr CLCIN3PPS
;
18323 extern __at(0x0E39) __sfr ADCACTPPS
;
18324 extern __at(0x0E3A) __sfr SSPCLKPPS
;
18325 extern __at(0x0E3B) __sfr SSPDATPPS
;
18326 extern __at(0x0E3C) __sfr SSPSSPPS
;
18327 extern __at(0x0E3D) __sfr RXPPS
;
18328 extern __at(0x0E3E) __sfr CKPPS
;
18329 extern __at(0x0E90) __sfr RA0PPS
;
18330 extern __at(0x0E91) __sfr RA1PPS
;
18331 extern __at(0x0E92) __sfr RA2PPS
;
18332 extern __at(0x0E93) __sfr RA3PPS
;
18333 extern __at(0x0E94) __sfr RA4PPS
;
18334 extern __at(0x0E95) __sfr RA5PPS
;
18335 extern __at(0x0E96) __sfr RA6PPS
;
18336 extern __at(0x0E97) __sfr RA7PPS
;
18337 extern __at(0x0E98) __sfr RB0PPS
;
18338 extern __at(0x0E99) __sfr RB1PPS
;
18339 extern __at(0x0E9A) __sfr RB2PPS
;
18340 extern __at(0x0E9B) __sfr RB3PPS
;
18341 extern __at(0x0E9C) __sfr RB4PPS
;
18342 extern __at(0x0E9D) __sfr RB5PPS
;
18343 extern __at(0x0E9E) __sfr RB6PPS
;
18344 extern __at(0x0E9F) __sfr RB7PPS
;
18345 extern __at(0x0EA0) __sfr RC0PPS
;
18346 extern __at(0x0EA1) __sfr RC1PPS
;
18347 extern __at(0x0EA2) __sfr RC2PPS
;
18348 extern __at(0x0EA3) __sfr RC3PPS
;
18349 extern __at(0x0EA4) __sfr RC4PPS
;
18350 extern __at(0x0EA5) __sfr RC5PPS
;
18351 extern __at(0x0EA6) __sfr RC6PPS
;
18352 extern __at(0x0EA7) __sfr RC7PPS
;
18354 //==============================================================================
18357 extern __at(0x0F0F) __sfr CLCDATA
;
18361 unsigned MCLC1OUT
: 1;
18362 unsigned MCLC2OUT
: 1;
18363 unsigned MCLC3OUT
: 1;
18364 unsigned MLC4OUT
: 1;
18371 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
18373 #define _MCLC1OUT 0x01
18374 #define _MCLC2OUT 0x02
18375 #define _MCLC3OUT 0x04
18376 #define _MLC4OUT 0x08
18378 //==============================================================================
18381 //==============================================================================
18384 extern __at(0x0F10) __sfr CLC1CON
;
18390 unsigned LC1MODE0
: 1;
18391 unsigned LC1MODE1
: 1;
18392 unsigned LC1MODE2
: 1;
18393 unsigned LC1INTN
: 1;
18394 unsigned LC1INTP
: 1;
18395 unsigned LC1OUT
: 1;
18397 unsigned LC1EN
: 1;
18402 unsigned MODE0
: 1;
18403 unsigned MODE1
: 1;
18404 unsigned MODE2
: 1;
18414 unsigned LC1MODE
: 3;
18425 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
18427 #define _CLC1CON_LC1MODE0 0x01
18428 #define _CLC1CON_MODE0 0x01
18429 #define _CLC1CON_LC1MODE1 0x02
18430 #define _CLC1CON_MODE1 0x02
18431 #define _CLC1CON_LC1MODE2 0x04
18432 #define _CLC1CON_MODE2 0x04
18433 #define _CLC1CON_LC1INTN 0x08
18434 #define _CLC1CON_INTN 0x08
18435 #define _CLC1CON_LC1INTP 0x10
18436 #define _CLC1CON_INTP 0x10
18437 #define _CLC1CON_LC1OUT 0x20
18438 #define _CLC1CON_OUT 0x20
18439 #define _CLC1CON_LC1EN 0x80
18440 #define _CLC1CON_EN 0x80
18442 //==============================================================================
18445 //==============================================================================
18448 extern __at(0x0F11) __sfr CLC1POL
;
18454 unsigned LC1G1POL
: 1;
18455 unsigned LC1G2POL
: 1;
18456 unsigned LC1G3POL
: 1;
18457 unsigned LC1G4POL
: 1;
18461 unsigned LC1POL
: 1;
18466 unsigned G1POL
: 1;
18467 unsigned G2POL
: 1;
18468 unsigned G3POL
: 1;
18469 unsigned G4POL
: 1;
18477 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
18479 #define _LC1G1POL 0x01
18480 #define _G1POL 0x01
18481 #define _LC1G2POL 0x02
18482 #define _G2POL 0x02
18483 #define _LC1G3POL 0x04
18484 #define _G3POL 0x04
18485 #define _LC1G4POL 0x08
18486 #define _G4POL 0x08
18487 #define _LC1POL 0x80
18490 //==============================================================================
18493 //==============================================================================
18496 extern __at(0x0F12) __sfr CLC1SEL0
;
18502 unsigned LC1D1S0
: 1;
18503 unsigned LC1D1S1
: 1;
18504 unsigned LC1D1S2
: 1;
18505 unsigned LC1D1S3
: 1;
18506 unsigned LC1D1S4
: 1;
18507 unsigned LC1D1S5
: 1;
18526 unsigned LC1D1S
: 6;
18535 } __CLC1SEL0bits_t
;
18537 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
18539 #define _LC1D1S0 0x01
18541 #define _LC1D1S1 0x02
18543 #define _LC1D1S2 0x04
18545 #define _LC1D1S3 0x08
18547 #define _LC1D1S4 0x10
18549 #define _LC1D1S5 0x20
18552 //==============================================================================
18555 //==============================================================================
18558 extern __at(0x0F13) __sfr CLC1SEL1
;
18564 unsigned LC1D2S0
: 1;
18565 unsigned LC1D2S1
: 1;
18566 unsigned LC1D2S2
: 1;
18567 unsigned LC1D2S3
: 1;
18568 unsigned LC1D2S4
: 1;
18569 unsigned LC1D2S5
: 1;
18594 unsigned LC1D2S
: 6;
18597 } __CLC1SEL1bits_t
;
18599 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
18601 #define _LC1D2S0 0x01
18603 #define _LC1D2S1 0x02
18605 #define _LC1D2S2 0x04
18607 #define _LC1D2S3 0x08
18609 #define _LC1D2S4 0x10
18611 #define _LC1D2S5 0x20
18614 //==============================================================================
18617 //==============================================================================
18620 extern __at(0x0F14) __sfr CLC1SEL2
;
18626 unsigned LC1D3S0
: 1;
18627 unsigned LC1D3S1
: 1;
18628 unsigned LC1D3S2
: 1;
18629 unsigned LC1D3S3
: 1;
18630 unsigned LC1D3S4
: 1;
18631 unsigned LC1D3S5
: 1;
18656 unsigned LC1D3S
: 6;
18659 } __CLC1SEL2bits_t
;
18661 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
18663 #define _LC1D3S0 0x01
18665 #define _LC1D3S1 0x02
18667 #define _LC1D3S2 0x04
18669 #define _LC1D3S3 0x08
18671 #define _LC1D3S4 0x10
18673 #define _LC1D3S5 0x20
18676 //==============================================================================
18679 //==============================================================================
18682 extern __at(0x0F15) __sfr CLC1SEL3
;
18688 unsigned LC1D4S0
: 1;
18689 unsigned LC1D4S1
: 1;
18690 unsigned LC1D4S2
: 1;
18691 unsigned LC1D4S3
: 1;
18692 unsigned LC1D4S4
: 1;
18693 unsigned LC1D4S5
: 1;
18712 unsigned LC1D4S
: 6;
18721 } __CLC1SEL3bits_t
;
18723 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
18725 #define _LC1D4S0 0x01
18727 #define _LC1D4S1 0x02
18729 #define _LC1D4S2 0x04
18731 #define _LC1D4S3 0x08
18733 #define _LC1D4S4 0x10
18735 #define _LC1D4S5 0x20
18738 //==============================================================================
18741 //==============================================================================
18744 extern __at(0x0F16) __sfr CLC1GLS0
;
18750 unsigned LC1G1D1N
: 1;
18751 unsigned LC1G1D1T
: 1;
18752 unsigned LC1G1D2N
: 1;
18753 unsigned LC1G1D2T
: 1;
18754 unsigned LC1G1D3N
: 1;
18755 unsigned LC1G1D3T
: 1;
18756 unsigned LC1G1D4N
: 1;
18757 unsigned LC1G1D4T
: 1;
18771 } __CLC1GLS0bits_t
;
18773 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
18775 #define _LC1G1D1N 0x01
18777 #define _LC1G1D1T 0x02
18779 #define _LC1G1D2N 0x04
18781 #define _LC1G1D2T 0x08
18783 #define _LC1G1D3N 0x10
18785 #define _LC1G1D3T 0x20
18787 #define _LC1G1D4N 0x40
18789 #define _LC1G1D4T 0x80
18792 //==============================================================================
18795 //==============================================================================
18798 extern __at(0x0F17) __sfr CLC1GLS1
;
18804 unsigned LC1G2D1N
: 1;
18805 unsigned LC1G2D1T
: 1;
18806 unsigned LC1G2D2N
: 1;
18807 unsigned LC1G2D2T
: 1;
18808 unsigned LC1G2D3N
: 1;
18809 unsigned LC1G2D3T
: 1;
18810 unsigned LC1G2D4N
: 1;
18811 unsigned LC1G2D4T
: 1;
18825 } __CLC1GLS1bits_t
;
18827 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
18829 #define _CLC1GLS1_LC1G2D1N 0x01
18830 #define _CLC1GLS1_D1N 0x01
18831 #define _CLC1GLS1_LC1G2D1T 0x02
18832 #define _CLC1GLS1_D1T 0x02
18833 #define _CLC1GLS1_LC1G2D2N 0x04
18834 #define _CLC1GLS1_D2N 0x04
18835 #define _CLC1GLS1_LC1G2D2T 0x08
18836 #define _CLC1GLS1_D2T 0x08
18837 #define _CLC1GLS1_LC1G2D3N 0x10
18838 #define _CLC1GLS1_D3N 0x10
18839 #define _CLC1GLS1_LC1G2D3T 0x20
18840 #define _CLC1GLS1_D3T 0x20
18841 #define _CLC1GLS1_LC1G2D4N 0x40
18842 #define _CLC1GLS1_D4N 0x40
18843 #define _CLC1GLS1_LC1G2D4T 0x80
18844 #define _CLC1GLS1_D4T 0x80
18846 //==============================================================================
18849 //==============================================================================
18852 extern __at(0x0F18) __sfr CLC1GLS2
;
18858 unsigned LC1G3D1N
: 1;
18859 unsigned LC1G3D1T
: 1;
18860 unsigned LC1G3D2N
: 1;
18861 unsigned LC1G3D2T
: 1;
18862 unsigned LC1G3D3N
: 1;
18863 unsigned LC1G3D3T
: 1;
18864 unsigned LC1G3D4N
: 1;
18865 unsigned LC1G3D4T
: 1;
18879 } __CLC1GLS2bits_t
;
18881 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
18883 #define _CLC1GLS2_LC1G3D1N 0x01
18884 #define _CLC1GLS2_D1N 0x01
18885 #define _CLC1GLS2_LC1G3D1T 0x02
18886 #define _CLC1GLS2_D1T 0x02
18887 #define _CLC1GLS2_LC1G3D2N 0x04
18888 #define _CLC1GLS2_D2N 0x04
18889 #define _CLC1GLS2_LC1G3D2T 0x08
18890 #define _CLC1GLS2_D2T 0x08
18891 #define _CLC1GLS2_LC1G3D3N 0x10
18892 #define _CLC1GLS2_D3N 0x10
18893 #define _CLC1GLS2_LC1G3D3T 0x20
18894 #define _CLC1GLS2_D3T 0x20
18895 #define _CLC1GLS2_LC1G3D4N 0x40
18896 #define _CLC1GLS2_D4N 0x40
18897 #define _CLC1GLS2_LC1G3D4T 0x80
18898 #define _CLC1GLS2_D4T 0x80
18900 //==============================================================================
18903 //==============================================================================
18906 extern __at(0x0F19) __sfr CLC1GLS3
;
18912 unsigned LC1G4D1N
: 1;
18913 unsigned LC1G4D1T
: 1;
18914 unsigned LC1G4D2N
: 1;
18915 unsigned LC1G4D2T
: 1;
18916 unsigned LC1G4D3N
: 1;
18917 unsigned LC1G4D3T
: 1;
18918 unsigned LC1G4D4N
: 1;
18919 unsigned LC1G4D4T
: 1;
18924 unsigned G4D1N
: 1;
18925 unsigned G4D1T
: 1;
18926 unsigned G4D2N
: 1;
18927 unsigned G4D2T
: 1;
18928 unsigned G4D3N
: 1;
18929 unsigned G4D3T
: 1;
18930 unsigned G4D4N
: 1;
18931 unsigned G4D4T
: 1;
18933 } __CLC1GLS3bits_t
;
18935 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
18937 #define _LC1G4D1N 0x01
18938 #define _G4D1N 0x01
18939 #define _LC1G4D1T 0x02
18940 #define _G4D1T 0x02
18941 #define _LC1G4D2N 0x04
18942 #define _G4D2N 0x04
18943 #define _LC1G4D2T 0x08
18944 #define _G4D2T 0x08
18945 #define _LC1G4D3N 0x10
18946 #define _G4D3N 0x10
18947 #define _LC1G4D3T 0x20
18948 #define _G4D3T 0x20
18949 #define _LC1G4D4N 0x40
18950 #define _G4D4N 0x40
18951 #define _LC1G4D4T 0x80
18952 #define _G4D4T 0x80
18954 //==============================================================================
18957 //==============================================================================
18960 extern __at(0x0F1A) __sfr CLC2CON
;
18966 unsigned LC2MODE0
: 1;
18967 unsigned LC2MODE1
: 1;
18968 unsigned LC2MODE2
: 1;
18969 unsigned LC2INTN
: 1;
18970 unsigned LC2INTP
: 1;
18971 unsigned LC2OUT
: 1;
18973 unsigned LC2EN
: 1;
18978 unsigned MODE0
: 1;
18979 unsigned MODE1
: 1;
18980 unsigned MODE2
: 1;
18996 unsigned LC2MODE
: 3;
19001 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
19003 #define _CLC2CON_LC2MODE0 0x01
19004 #define _CLC2CON_MODE0 0x01
19005 #define _CLC2CON_LC2MODE1 0x02
19006 #define _CLC2CON_MODE1 0x02
19007 #define _CLC2CON_LC2MODE2 0x04
19008 #define _CLC2CON_MODE2 0x04
19009 #define _CLC2CON_LC2INTN 0x08
19010 #define _CLC2CON_INTN 0x08
19011 #define _CLC2CON_LC2INTP 0x10
19012 #define _CLC2CON_INTP 0x10
19013 #define _CLC2CON_LC2OUT 0x20
19014 #define _CLC2CON_OUT 0x20
19015 #define _CLC2CON_LC2EN 0x80
19016 #define _CLC2CON_EN 0x80
19018 //==============================================================================
19021 //==============================================================================
19024 extern __at(0x0F1B) __sfr CLC2POL
;
19030 unsigned LC2G1POL
: 1;
19031 unsigned LC2G2POL
: 1;
19032 unsigned LC2G3POL
: 1;
19033 unsigned LC2G4POL
: 1;
19037 unsigned LC2POL
: 1;
19042 unsigned G1POL
: 1;
19043 unsigned G2POL
: 1;
19044 unsigned G3POL
: 1;
19045 unsigned G4POL
: 1;
19053 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
19055 #define _CLC2POL_LC2G1POL 0x01
19056 #define _CLC2POL_G1POL 0x01
19057 #define _CLC2POL_LC2G2POL 0x02
19058 #define _CLC2POL_G2POL 0x02
19059 #define _CLC2POL_LC2G3POL 0x04
19060 #define _CLC2POL_G3POL 0x04
19061 #define _CLC2POL_LC2G4POL 0x08
19062 #define _CLC2POL_G4POL 0x08
19063 #define _CLC2POL_LC2POL 0x80
19064 #define _CLC2POL_POL 0x80
19066 //==============================================================================
19069 //==============================================================================
19072 extern __at(0x0F1C) __sfr CLC2SEL0
;
19078 unsigned LC2D1S0
: 1;
19079 unsigned LC2D1S1
: 1;
19080 unsigned LC2D1S2
: 1;
19081 unsigned LC2D1S3
: 1;
19082 unsigned LC2D1S4
: 1;
19083 unsigned LC2D1S5
: 1;
19108 unsigned LC2D1S
: 6;
19111 } __CLC2SEL0bits_t
;
19113 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
19115 #define _CLC2SEL0_LC2D1S0 0x01
19116 #define _CLC2SEL0_D1S0 0x01
19117 #define _CLC2SEL0_LC2D1S1 0x02
19118 #define _CLC2SEL0_D1S1 0x02
19119 #define _CLC2SEL0_LC2D1S2 0x04
19120 #define _CLC2SEL0_D1S2 0x04
19121 #define _CLC2SEL0_LC2D1S3 0x08
19122 #define _CLC2SEL0_D1S3 0x08
19123 #define _CLC2SEL0_LC2D1S4 0x10
19124 #define _CLC2SEL0_D1S4 0x10
19125 #define _CLC2SEL0_LC2D1S5 0x20
19126 #define _CLC2SEL0_D1S5 0x20
19128 //==============================================================================
19131 //==============================================================================
19134 extern __at(0x0F1D) __sfr CLC2SEL1
;
19140 unsigned LC2D2S0
: 1;
19141 unsigned LC2D2S1
: 1;
19142 unsigned LC2D2S2
: 1;
19143 unsigned LC2D2S3
: 1;
19144 unsigned LC2D2S4
: 1;
19145 unsigned LC2D2S5
: 1;
19164 unsigned LC2D2S
: 6;
19173 } __CLC2SEL1bits_t
;
19175 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
19177 #define _CLC2SEL1_LC2D2S0 0x01
19178 #define _CLC2SEL1_D2S0 0x01
19179 #define _CLC2SEL1_LC2D2S1 0x02
19180 #define _CLC2SEL1_D2S1 0x02
19181 #define _CLC2SEL1_LC2D2S2 0x04
19182 #define _CLC2SEL1_D2S2 0x04
19183 #define _CLC2SEL1_LC2D2S3 0x08
19184 #define _CLC2SEL1_D2S3 0x08
19185 #define _CLC2SEL1_LC2D2S4 0x10
19186 #define _CLC2SEL1_D2S4 0x10
19187 #define _CLC2SEL1_LC2D2S5 0x20
19188 #define _CLC2SEL1_D2S5 0x20
19190 //==============================================================================
19193 //==============================================================================
19196 extern __at(0x0F1E) __sfr CLC2SEL2
;
19202 unsigned LC2D3S0
: 1;
19203 unsigned LC2D3S1
: 1;
19204 unsigned LC2D3S2
: 1;
19205 unsigned LC2D3S3
: 1;
19206 unsigned LC2D3S4
: 1;
19207 unsigned LC2D3S5
: 1;
19226 unsigned LC2D3S
: 6;
19235 } __CLC2SEL2bits_t
;
19237 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
19239 #define _CLC2SEL2_LC2D3S0 0x01
19240 #define _CLC2SEL2_D3S0 0x01
19241 #define _CLC2SEL2_LC2D3S1 0x02
19242 #define _CLC2SEL2_D3S1 0x02
19243 #define _CLC2SEL2_LC2D3S2 0x04
19244 #define _CLC2SEL2_D3S2 0x04
19245 #define _CLC2SEL2_LC2D3S3 0x08
19246 #define _CLC2SEL2_D3S3 0x08
19247 #define _CLC2SEL2_LC2D3S4 0x10
19248 #define _CLC2SEL2_D3S4 0x10
19249 #define _CLC2SEL2_LC2D3S5 0x20
19250 #define _CLC2SEL2_D3S5 0x20
19252 //==============================================================================
19255 //==============================================================================
19258 extern __at(0x0F1F) __sfr CLC2SEL3
;
19264 unsigned LC2D4S0
: 1;
19265 unsigned LC2D4S1
: 1;
19266 unsigned LC2D4S2
: 1;
19267 unsigned LC2D4S3
: 1;
19268 unsigned LC2D4S4
: 1;
19269 unsigned LC2D4S5
: 1;
19288 unsigned LC2D4S
: 6;
19297 } __CLC2SEL3bits_t
;
19299 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
19301 #define _CLC2SEL3_LC2D4S0 0x01
19302 #define _CLC2SEL3_D4S0 0x01
19303 #define _CLC2SEL3_LC2D4S1 0x02
19304 #define _CLC2SEL3_D4S1 0x02
19305 #define _CLC2SEL3_LC2D4S2 0x04
19306 #define _CLC2SEL3_D4S2 0x04
19307 #define _CLC2SEL3_LC2D4S3 0x08
19308 #define _CLC2SEL3_D4S3 0x08
19309 #define _CLC2SEL3_LC2D4S4 0x10
19310 #define _CLC2SEL3_D4S4 0x10
19311 #define _CLC2SEL3_LC2D4S5 0x20
19312 #define _CLC2SEL3_D4S5 0x20
19314 //==============================================================================
19317 //==============================================================================
19320 extern __at(0x0F20) __sfr CLC2GLS0
;
19326 unsigned LC2G1D1N
: 1;
19327 unsigned LC2G1D1T
: 1;
19328 unsigned LC2G1D2N
: 1;
19329 unsigned LC2G1D2T
: 1;
19330 unsigned LC2G1D3N
: 1;
19331 unsigned LC2G1D3T
: 1;
19332 unsigned LC2G1D4N
: 1;
19333 unsigned LC2G1D4T
: 1;
19347 } __CLC2GLS0bits_t
;
19349 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
19351 #define _CLC2GLS0_LC2G1D1N 0x01
19352 #define _CLC2GLS0_D1N 0x01
19353 #define _CLC2GLS0_LC2G1D1T 0x02
19354 #define _CLC2GLS0_D1T 0x02
19355 #define _CLC2GLS0_LC2G1D2N 0x04
19356 #define _CLC2GLS0_D2N 0x04
19357 #define _CLC2GLS0_LC2G1D2T 0x08
19358 #define _CLC2GLS0_D2T 0x08
19359 #define _CLC2GLS0_LC2G1D3N 0x10
19360 #define _CLC2GLS0_D3N 0x10
19361 #define _CLC2GLS0_LC2G1D3T 0x20
19362 #define _CLC2GLS0_D3T 0x20
19363 #define _CLC2GLS0_LC2G1D4N 0x40
19364 #define _CLC2GLS0_D4N 0x40
19365 #define _CLC2GLS0_LC2G1D4T 0x80
19366 #define _CLC2GLS0_D4T 0x80
19368 //==============================================================================
19371 //==============================================================================
19374 extern __at(0x0F21) __sfr CLC2GLS1
;
19380 unsigned LC2G2D1N
: 1;
19381 unsigned LC2G2D1T
: 1;
19382 unsigned LC2G2D2N
: 1;
19383 unsigned LC2G2D2T
: 1;
19384 unsigned LC2G2D3N
: 1;
19385 unsigned LC2G2D3T
: 1;
19386 unsigned LC2G2D4N
: 1;
19387 unsigned LC2G2D4T
: 1;
19401 } __CLC2GLS1bits_t
;
19403 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
19405 #define _CLC2GLS1_LC2G2D1N 0x01
19406 #define _CLC2GLS1_D1N 0x01
19407 #define _CLC2GLS1_LC2G2D1T 0x02
19408 #define _CLC2GLS1_D1T 0x02
19409 #define _CLC2GLS1_LC2G2D2N 0x04
19410 #define _CLC2GLS1_D2N 0x04
19411 #define _CLC2GLS1_LC2G2D2T 0x08
19412 #define _CLC2GLS1_D2T 0x08
19413 #define _CLC2GLS1_LC2G2D3N 0x10
19414 #define _CLC2GLS1_D3N 0x10
19415 #define _CLC2GLS1_LC2G2D3T 0x20
19416 #define _CLC2GLS1_D3T 0x20
19417 #define _CLC2GLS1_LC2G2D4N 0x40
19418 #define _CLC2GLS1_D4N 0x40
19419 #define _CLC2GLS1_LC2G2D4T 0x80
19420 #define _CLC2GLS1_D4T 0x80
19422 //==============================================================================
19425 //==============================================================================
19428 extern __at(0x0F22) __sfr CLC2GLS2
;
19434 unsigned LC2G3D1N
: 1;
19435 unsigned LC2G3D1T
: 1;
19436 unsigned LC2G3D2N
: 1;
19437 unsigned LC2G3D2T
: 1;
19438 unsigned LC2G3D3N
: 1;
19439 unsigned LC2G3D3T
: 1;
19440 unsigned LC2G3D4N
: 1;
19441 unsigned LC2G3D4T
: 1;
19455 } __CLC2GLS2bits_t
;
19457 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
19459 #define _CLC2GLS2_LC2G3D1N 0x01
19460 #define _CLC2GLS2_D1N 0x01
19461 #define _CLC2GLS2_LC2G3D1T 0x02
19462 #define _CLC2GLS2_D1T 0x02
19463 #define _CLC2GLS2_LC2G3D2N 0x04
19464 #define _CLC2GLS2_D2N 0x04
19465 #define _CLC2GLS2_LC2G3D2T 0x08
19466 #define _CLC2GLS2_D2T 0x08
19467 #define _CLC2GLS2_LC2G3D3N 0x10
19468 #define _CLC2GLS2_D3N 0x10
19469 #define _CLC2GLS2_LC2G3D3T 0x20
19470 #define _CLC2GLS2_D3T 0x20
19471 #define _CLC2GLS2_LC2G3D4N 0x40
19472 #define _CLC2GLS2_D4N 0x40
19473 #define _CLC2GLS2_LC2G3D4T 0x80
19474 #define _CLC2GLS2_D4T 0x80
19476 //==============================================================================
19479 //==============================================================================
19482 extern __at(0x0F23) __sfr CLC2GLS3
;
19488 unsigned LC2G4D1N
: 1;
19489 unsigned LC2G4D1T
: 1;
19490 unsigned LC2G4D2N
: 1;
19491 unsigned LC2G4D2T
: 1;
19492 unsigned LC2G4D3N
: 1;
19493 unsigned LC2G4D3T
: 1;
19494 unsigned LC2G4D4N
: 1;
19495 unsigned LC2G4D4T
: 1;
19500 unsigned G4D1N
: 1;
19501 unsigned G4D1T
: 1;
19502 unsigned G4D2N
: 1;
19503 unsigned G4D2T
: 1;
19504 unsigned G4D3N
: 1;
19505 unsigned G4D3T
: 1;
19506 unsigned G4D4N
: 1;
19507 unsigned G4D4T
: 1;
19509 } __CLC2GLS3bits_t
;
19511 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
19513 #define _CLC2GLS3_LC2G4D1N 0x01
19514 #define _CLC2GLS3_G4D1N 0x01
19515 #define _CLC2GLS3_LC2G4D1T 0x02
19516 #define _CLC2GLS3_G4D1T 0x02
19517 #define _CLC2GLS3_LC2G4D2N 0x04
19518 #define _CLC2GLS3_G4D2N 0x04
19519 #define _CLC2GLS3_LC2G4D2T 0x08
19520 #define _CLC2GLS3_G4D2T 0x08
19521 #define _CLC2GLS3_LC2G4D3N 0x10
19522 #define _CLC2GLS3_G4D3N 0x10
19523 #define _CLC2GLS3_LC2G4D3T 0x20
19524 #define _CLC2GLS3_G4D3T 0x20
19525 #define _CLC2GLS3_LC2G4D4N 0x40
19526 #define _CLC2GLS3_G4D4N 0x40
19527 #define _CLC2GLS3_LC2G4D4T 0x80
19528 #define _CLC2GLS3_G4D4T 0x80
19530 //==============================================================================
19533 //==============================================================================
19536 extern __at(0x0F24) __sfr CLC3CON
;
19542 unsigned LC3MODE0
: 1;
19543 unsigned LC3MODE1
: 1;
19544 unsigned LC3MODE2
: 1;
19545 unsigned LC3INTN
: 1;
19546 unsigned LC3INTP
: 1;
19547 unsigned LC3OUT
: 1;
19549 unsigned LC3EN
: 1;
19554 unsigned MODE0
: 1;
19555 unsigned MODE1
: 1;
19556 unsigned MODE2
: 1;
19572 unsigned LC3MODE
: 3;
19577 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
19579 #define _CLC3CON_LC3MODE0 0x01
19580 #define _CLC3CON_MODE0 0x01
19581 #define _CLC3CON_LC3MODE1 0x02
19582 #define _CLC3CON_MODE1 0x02
19583 #define _CLC3CON_LC3MODE2 0x04
19584 #define _CLC3CON_MODE2 0x04
19585 #define _CLC3CON_LC3INTN 0x08
19586 #define _CLC3CON_INTN 0x08
19587 #define _CLC3CON_LC3INTP 0x10
19588 #define _CLC3CON_INTP 0x10
19589 #define _CLC3CON_LC3OUT 0x20
19590 #define _CLC3CON_OUT 0x20
19591 #define _CLC3CON_LC3EN 0x80
19592 #define _CLC3CON_EN 0x80
19594 //==============================================================================
19597 //==============================================================================
19600 extern __at(0x0F25) __sfr CLC3POL
;
19606 unsigned LC3G1POL
: 1;
19607 unsigned LC3G2POL
: 1;
19608 unsigned LC3G3POL
: 1;
19609 unsigned LC3G4POL
: 1;
19613 unsigned LC3POL
: 1;
19618 unsigned G1POL
: 1;
19619 unsigned G2POL
: 1;
19620 unsigned G3POL
: 1;
19621 unsigned G4POL
: 1;
19629 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
19631 #define _CLC3POL_LC3G1POL 0x01
19632 #define _CLC3POL_G1POL 0x01
19633 #define _CLC3POL_LC3G2POL 0x02
19634 #define _CLC3POL_G2POL 0x02
19635 #define _CLC3POL_LC3G3POL 0x04
19636 #define _CLC3POL_G3POL 0x04
19637 #define _CLC3POL_LC3G4POL 0x08
19638 #define _CLC3POL_G4POL 0x08
19639 #define _CLC3POL_LC3POL 0x80
19640 #define _CLC3POL_POL 0x80
19642 //==============================================================================
19645 //==============================================================================
19648 extern __at(0x0F26) __sfr CLC3SEL0
;
19654 unsigned LC3D1S0
: 1;
19655 unsigned LC3D1S1
: 1;
19656 unsigned LC3D1S2
: 1;
19657 unsigned LC3D1S3
: 1;
19658 unsigned LC3D1S4
: 1;
19659 unsigned LC3D1S5
: 1;
19684 unsigned LC3D1S
: 6;
19687 } __CLC3SEL0bits_t
;
19689 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
19691 #define _CLC3SEL0_LC3D1S0 0x01
19692 #define _CLC3SEL0_D1S0 0x01
19693 #define _CLC3SEL0_LC3D1S1 0x02
19694 #define _CLC3SEL0_D1S1 0x02
19695 #define _CLC3SEL0_LC3D1S2 0x04
19696 #define _CLC3SEL0_D1S2 0x04
19697 #define _CLC3SEL0_LC3D1S3 0x08
19698 #define _CLC3SEL0_D1S3 0x08
19699 #define _CLC3SEL0_LC3D1S4 0x10
19700 #define _CLC3SEL0_D1S4 0x10
19701 #define _CLC3SEL0_LC3D1S5 0x20
19702 #define _CLC3SEL0_D1S5 0x20
19704 //==============================================================================
19707 //==============================================================================
19710 extern __at(0x0F27) __sfr CLC3SEL1
;
19716 unsigned LC3D2S0
: 1;
19717 unsigned LC3D2S1
: 1;
19718 unsigned LC3D2S2
: 1;
19719 unsigned LC3D2S3
: 1;
19720 unsigned LC3D2S4
: 1;
19721 unsigned LC3D2S5
: 1;
19740 unsigned LC3D2S
: 6;
19749 } __CLC3SEL1bits_t
;
19751 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
19753 #define _CLC3SEL1_LC3D2S0 0x01
19754 #define _CLC3SEL1_D2S0 0x01
19755 #define _CLC3SEL1_LC3D2S1 0x02
19756 #define _CLC3SEL1_D2S1 0x02
19757 #define _CLC3SEL1_LC3D2S2 0x04
19758 #define _CLC3SEL1_D2S2 0x04
19759 #define _CLC3SEL1_LC3D2S3 0x08
19760 #define _CLC3SEL1_D2S3 0x08
19761 #define _CLC3SEL1_LC3D2S4 0x10
19762 #define _CLC3SEL1_D2S4 0x10
19763 #define _CLC3SEL1_LC3D2S5 0x20
19764 #define _CLC3SEL1_D2S5 0x20
19766 //==============================================================================
19769 //==============================================================================
19772 extern __at(0x0F28) __sfr CLC3SEL2
;
19778 unsigned LC3D3S0
: 1;
19779 unsigned LC3D3S1
: 1;
19780 unsigned LC3D3S2
: 1;
19781 unsigned LC3D3S3
: 1;
19782 unsigned LC3D3S4
: 1;
19783 unsigned LC3D3S5
: 1;
19808 unsigned LC3D3S
: 6;
19811 } __CLC3SEL2bits_t
;
19813 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
19815 #define _CLC3SEL2_LC3D3S0 0x01
19816 #define _CLC3SEL2_D3S0 0x01
19817 #define _CLC3SEL2_LC3D3S1 0x02
19818 #define _CLC3SEL2_D3S1 0x02
19819 #define _CLC3SEL2_LC3D3S2 0x04
19820 #define _CLC3SEL2_D3S2 0x04
19821 #define _CLC3SEL2_LC3D3S3 0x08
19822 #define _CLC3SEL2_D3S3 0x08
19823 #define _CLC3SEL2_LC3D3S4 0x10
19824 #define _CLC3SEL2_D3S4 0x10
19825 #define _CLC3SEL2_LC3D3S5 0x20
19826 #define _CLC3SEL2_D3S5 0x20
19828 //==============================================================================
19831 //==============================================================================
19834 extern __at(0x0F29) __sfr CLC3SEL3
;
19840 unsigned LC3D4S0
: 1;
19841 unsigned LC3D4S1
: 1;
19842 unsigned LC3D4S2
: 1;
19843 unsigned LC3D4S3
: 1;
19844 unsigned LC3D4S4
: 1;
19845 unsigned LC3D4S5
: 1;
19864 unsigned LC3D4S
: 6;
19873 } __CLC3SEL3bits_t
;
19875 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
19877 #define _CLC3SEL3_LC3D4S0 0x01
19878 #define _CLC3SEL3_D4S0 0x01
19879 #define _CLC3SEL3_LC3D4S1 0x02
19880 #define _CLC3SEL3_D4S1 0x02
19881 #define _CLC3SEL3_LC3D4S2 0x04
19882 #define _CLC3SEL3_D4S2 0x04
19883 #define _CLC3SEL3_LC3D4S3 0x08
19884 #define _CLC3SEL3_D4S3 0x08
19885 #define _CLC3SEL3_LC3D4S4 0x10
19886 #define _CLC3SEL3_D4S4 0x10
19887 #define _CLC3SEL3_LC3D4S5 0x20
19888 #define _CLC3SEL3_D4S5 0x20
19890 //==============================================================================
19893 //==============================================================================
19896 extern __at(0x0F2A) __sfr CLC3GLS0
;
19902 unsigned LC3G1D1N
: 1;
19903 unsigned LC3G1D1T
: 1;
19904 unsigned LC3G1D2N
: 1;
19905 unsigned LC3G1D2T
: 1;
19906 unsigned LC3G1D3N
: 1;
19907 unsigned LC3G1D3T
: 1;
19908 unsigned LC3G1D4N
: 1;
19909 unsigned LC3G1D4T
: 1;
19923 } __CLC3GLS0bits_t
;
19925 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
19927 #define _CLC3GLS0_LC3G1D1N 0x01
19928 #define _CLC3GLS0_D1N 0x01
19929 #define _CLC3GLS0_LC3G1D1T 0x02
19930 #define _CLC3GLS0_D1T 0x02
19931 #define _CLC3GLS0_LC3G1D2N 0x04
19932 #define _CLC3GLS0_D2N 0x04
19933 #define _CLC3GLS0_LC3G1D2T 0x08
19934 #define _CLC3GLS0_D2T 0x08
19935 #define _CLC3GLS0_LC3G1D3N 0x10
19936 #define _CLC3GLS0_D3N 0x10
19937 #define _CLC3GLS0_LC3G1D3T 0x20
19938 #define _CLC3GLS0_D3T 0x20
19939 #define _CLC3GLS0_LC3G1D4N 0x40
19940 #define _CLC3GLS0_D4N 0x40
19941 #define _CLC3GLS0_LC3G1D4T 0x80
19942 #define _CLC3GLS0_D4T 0x80
19944 //==============================================================================
19947 //==============================================================================
19950 extern __at(0x0F2B) __sfr CLC3GLS1
;
19956 unsigned LC3G2D1N
: 1;
19957 unsigned LC3G2D1T
: 1;
19958 unsigned LC3G2D2N
: 1;
19959 unsigned LC3G2D2T
: 1;
19960 unsigned LC3G2D3N
: 1;
19961 unsigned LC3G2D3T
: 1;
19962 unsigned LC3G2D4N
: 1;
19963 unsigned LC3G2D4T
: 1;
19977 } __CLC3GLS1bits_t
;
19979 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
19981 #define _CLC3GLS1_LC3G2D1N 0x01
19982 #define _CLC3GLS1_D1N 0x01
19983 #define _CLC3GLS1_LC3G2D1T 0x02
19984 #define _CLC3GLS1_D1T 0x02
19985 #define _CLC3GLS1_LC3G2D2N 0x04
19986 #define _CLC3GLS1_D2N 0x04
19987 #define _CLC3GLS1_LC3G2D2T 0x08
19988 #define _CLC3GLS1_D2T 0x08
19989 #define _CLC3GLS1_LC3G2D3N 0x10
19990 #define _CLC3GLS1_D3N 0x10
19991 #define _CLC3GLS1_LC3G2D3T 0x20
19992 #define _CLC3GLS1_D3T 0x20
19993 #define _CLC3GLS1_LC3G2D4N 0x40
19994 #define _CLC3GLS1_D4N 0x40
19995 #define _CLC3GLS1_LC3G2D4T 0x80
19996 #define _CLC3GLS1_D4T 0x80
19998 //==============================================================================
20001 //==============================================================================
20004 extern __at(0x0F2C) __sfr CLC3GLS2
;
20010 unsigned LC3G3D1N
: 1;
20011 unsigned LC3G3D1T
: 1;
20012 unsigned LC3G3D2N
: 1;
20013 unsigned LC3G3D2T
: 1;
20014 unsigned LC3G3D3N
: 1;
20015 unsigned LC3G3D3T
: 1;
20016 unsigned LC3G3D4N
: 1;
20017 unsigned LC3G3D4T
: 1;
20031 } __CLC3GLS2bits_t
;
20033 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
20035 #define _CLC3GLS2_LC3G3D1N 0x01
20036 #define _CLC3GLS2_D1N 0x01
20037 #define _CLC3GLS2_LC3G3D1T 0x02
20038 #define _CLC3GLS2_D1T 0x02
20039 #define _CLC3GLS2_LC3G3D2N 0x04
20040 #define _CLC3GLS2_D2N 0x04
20041 #define _CLC3GLS2_LC3G3D2T 0x08
20042 #define _CLC3GLS2_D2T 0x08
20043 #define _CLC3GLS2_LC3G3D3N 0x10
20044 #define _CLC3GLS2_D3N 0x10
20045 #define _CLC3GLS2_LC3G3D3T 0x20
20046 #define _CLC3GLS2_D3T 0x20
20047 #define _CLC3GLS2_LC3G3D4N 0x40
20048 #define _CLC3GLS2_D4N 0x40
20049 #define _CLC3GLS2_LC3G3D4T 0x80
20050 #define _CLC3GLS2_D4T 0x80
20052 //==============================================================================
20055 //==============================================================================
20058 extern __at(0x0F2D) __sfr CLC3GLS3
;
20064 unsigned LC3G4D1N
: 1;
20065 unsigned LC3G4D1T
: 1;
20066 unsigned LC3G4D2N
: 1;
20067 unsigned LC3G4D2T
: 1;
20068 unsigned LC3G4D3N
: 1;
20069 unsigned LC3G4D3T
: 1;
20070 unsigned LC3G4D4N
: 1;
20071 unsigned LC3G4D4T
: 1;
20076 unsigned G4D1N
: 1;
20077 unsigned G4D1T
: 1;
20078 unsigned G4D2N
: 1;
20079 unsigned G4D2T
: 1;
20080 unsigned G4D3N
: 1;
20081 unsigned G4D3T
: 1;
20082 unsigned G4D4N
: 1;
20083 unsigned G4D4T
: 1;
20085 } __CLC3GLS3bits_t
;
20087 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
20089 #define _CLC3GLS3_LC3G4D1N 0x01
20090 #define _CLC3GLS3_G4D1N 0x01
20091 #define _CLC3GLS3_LC3G4D1T 0x02
20092 #define _CLC3GLS3_G4D1T 0x02
20093 #define _CLC3GLS3_LC3G4D2N 0x04
20094 #define _CLC3GLS3_G4D2N 0x04
20095 #define _CLC3GLS3_LC3G4D2T 0x08
20096 #define _CLC3GLS3_G4D2T 0x08
20097 #define _CLC3GLS3_LC3G4D3N 0x10
20098 #define _CLC3GLS3_G4D3N 0x10
20099 #define _CLC3GLS3_LC3G4D3T 0x20
20100 #define _CLC3GLS3_G4D3T 0x20
20101 #define _CLC3GLS3_LC3G4D4N 0x40
20102 #define _CLC3GLS3_G4D4N 0x40
20103 #define _CLC3GLS3_LC3G4D4T 0x80
20104 #define _CLC3GLS3_G4D4T 0x80
20106 //==============================================================================
20109 //==============================================================================
20112 extern __at(0x0F2E) __sfr CLC4CON
;
20118 unsigned LC4MODE0
: 1;
20119 unsigned LC4MODE1
: 1;
20120 unsigned LC4MODE2
: 1;
20121 unsigned LC4INTN
: 1;
20122 unsigned LC4INTP
: 1;
20123 unsigned LC4OUT
: 1;
20125 unsigned LC4EN
: 1;
20130 unsigned MODE0
: 1;
20131 unsigned MODE1
: 1;
20132 unsigned MODE2
: 1;
20142 unsigned LC4MODE
: 3;
20153 extern __at(0x0F2E) volatile __CLC4CONbits_t CLC4CONbits
;
20155 #define _CLC4CON_LC4MODE0 0x01
20156 #define _CLC4CON_MODE0 0x01
20157 #define _CLC4CON_LC4MODE1 0x02
20158 #define _CLC4CON_MODE1 0x02
20159 #define _CLC4CON_LC4MODE2 0x04
20160 #define _CLC4CON_MODE2 0x04
20161 #define _CLC4CON_LC4INTN 0x08
20162 #define _CLC4CON_INTN 0x08
20163 #define _CLC4CON_LC4INTP 0x10
20164 #define _CLC4CON_INTP 0x10
20165 #define _CLC4CON_LC4OUT 0x20
20166 #define _CLC4CON_OUT 0x20
20167 #define _CLC4CON_LC4EN 0x80
20168 #define _CLC4CON_EN 0x80
20170 //==============================================================================
20173 //==============================================================================
20176 extern __at(0x0F2F) __sfr CLC4POL
;
20182 unsigned LC4G1POL
: 1;
20183 unsigned LC4G2POL
: 1;
20184 unsigned LC4G3POL
: 1;
20185 unsigned LC4G4POL
: 1;
20189 unsigned LC4POL
: 1;
20194 unsigned G1POL
: 1;
20195 unsigned G2POL
: 1;
20196 unsigned G3POL
: 1;
20197 unsigned G4POL
: 1;
20205 extern __at(0x0F2F) volatile __CLC4POLbits_t CLC4POLbits
;
20207 #define _CLC4POL_LC4G1POL 0x01
20208 #define _CLC4POL_G1POL 0x01
20209 #define _CLC4POL_LC4G2POL 0x02
20210 #define _CLC4POL_G2POL 0x02
20211 #define _CLC4POL_LC4G3POL 0x04
20212 #define _CLC4POL_G3POL 0x04
20213 #define _CLC4POL_LC4G4POL 0x08
20214 #define _CLC4POL_G4POL 0x08
20215 #define _CLC4POL_LC4POL 0x80
20216 #define _CLC4POL_POL 0x80
20218 //==============================================================================
20221 //==============================================================================
20224 extern __at(0x0F30) __sfr CLC4SEL0
;
20230 unsigned LC4D1S0
: 1;
20231 unsigned LC4D1S1
: 1;
20232 unsigned LC4D1S2
: 1;
20233 unsigned LC4D1S3
: 1;
20234 unsigned LC4D1S4
: 1;
20235 unsigned LC4D1S5
: 1;
20260 unsigned LC4D1S
: 6;
20263 } __CLC4SEL0bits_t
;
20265 extern __at(0x0F30) volatile __CLC4SEL0bits_t CLC4SEL0bits
;
20267 #define _CLC4SEL0_LC4D1S0 0x01
20268 #define _CLC4SEL0_D1S0 0x01
20269 #define _CLC4SEL0_LC4D1S1 0x02
20270 #define _CLC4SEL0_D1S1 0x02
20271 #define _CLC4SEL0_LC4D1S2 0x04
20272 #define _CLC4SEL0_D1S2 0x04
20273 #define _CLC4SEL0_LC4D1S3 0x08
20274 #define _CLC4SEL0_D1S3 0x08
20275 #define _CLC4SEL0_LC4D1S4 0x10
20276 #define _CLC4SEL0_D1S4 0x10
20277 #define _CLC4SEL0_LC4D1S5 0x20
20278 #define _CLC4SEL0_D1S5 0x20
20280 //==============================================================================
20283 //==============================================================================
20286 extern __at(0x0F31) __sfr CLC4SEL1
;
20292 unsigned LC4D2S0
: 1;
20293 unsigned LC4D2S1
: 1;
20294 unsigned LC4D2S2
: 1;
20295 unsigned LC4D2S3
: 1;
20296 unsigned LC4D2S4
: 1;
20297 unsigned LC4D2S5
: 1;
20316 unsigned LC4D2S
: 6;
20325 } __CLC4SEL1bits_t
;
20327 extern __at(0x0F31) volatile __CLC4SEL1bits_t CLC4SEL1bits
;
20329 #define _CLC4SEL1_LC4D2S0 0x01
20330 #define _CLC4SEL1_D2S0 0x01
20331 #define _CLC4SEL1_LC4D2S1 0x02
20332 #define _CLC4SEL1_D2S1 0x02
20333 #define _CLC4SEL1_LC4D2S2 0x04
20334 #define _CLC4SEL1_D2S2 0x04
20335 #define _CLC4SEL1_LC4D2S3 0x08
20336 #define _CLC4SEL1_D2S3 0x08
20337 #define _CLC4SEL1_LC4D2S4 0x10
20338 #define _CLC4SEL1_D2S4 0x10
20339 #define _CLC4SEL1_LC4D2S5 0x20
20340 #define _CLC4SEL1_D2S5 0x20
20342 //==============================================================================
20345 //==============================================================================
20348 extern __at(0x0F32) __sfr CLC4SEL2
;
20354 unsigned LC4D3S0
: 1;
20355 unsigned LC4D3S1
: 1;
20356 unsigned LC4D3S2
: 1;
20357 unsigned LC4D3S3
: 1;
20358 unsigned LC4D3S4
: 1;
20359 unsigned LC4D3S5
: 1;
20378 unsigned LC4D3S
: 6;
20387 } __CLC4SEL2bits_t
;
20389 extern __at(0x0F32) volatile __CLC4SEL2bits_t CLC4SEL2bits
;
20391 #define _CLC4SEL2_LC4D3S0 0x01
20392 #define _CLC4SEL2_D3S0 0x01
20393 #define _CLC4SEL2_LC4D3S1 0x02
20394 #define _CLC4SEL2_D3S1 0x02
20395 #define _CLC4SEL2_LC4D3S2 0x04
20396 #define _CLC4SEL2_D3S2 0x04
20397 #define _CLC4SEL2_LC4D3S3 0x08
20398 #define _CLC4SEL2_D3S3 0x08
20399 #define _CLC4SEL2_LC4D3S4 0x10
20400 #define _CLC4SEL2_D3S4 0x10
20401 #define _CLC4SEL2_LC4D3S5 0x20
20402 #define _CLC4SEL2_D3S5 0x20
20404 //==============================================================================
20407 //==============================================================================
20410 extern __at(0x0F33) __sfr CLC4SEL3
;
20416 unsigned LC4D4S0
: 1;
20417 unsigned LC4D4S1
: 1;
20418 unsigned LC4D4S2
: 1;
20419 unsigned LC4D4S3
: 1;
20420 unsigned LC4D4S4
: 1;
20421 unsigned LC4D4S5
: 1;
20440 unsigned LC4D4S
: 6;
20449 } __CLC4SEL3bits_t
;
20451 extern __at(0x0F33) volatile __CLC4SEL3bits_t CLC4SEL3bits
;
20453 #define _CLC4SEL3_LC4D4S0 0x01
20454 #define _CLC4SEL3_D4S0 0x01
20455 #define _CLC4SEL3_LC4D4S1 0x02
20456 #define _CLC4SEL3_D4S1 0x02
20457 #define _CLC4SEL3_LC4D4S2 0x04
20458 #define _CLC4SEL3_D4S2 0x04
20459 #define _CLC4SEL3_LC4D4S3 0x08
20460 #define _CLC4SEL3_D4S3 0x08
20461 #define _CLC4SEL3_LC4D4S4 0x10
20462 #define _CLC4SEL3_D4S4 0x10
20463 #define _CLC4SEL3_LC4D4S5 0x20
20464 #define _CLC4SEL3_D4S5 0x20
20466 //==============================================================================
20469 //==============================================================================
20472 extern __at(0x0F34) __sfr CLC4GLS0
;
20478 unsigned LC4G1D1N
: 1;
20479 unsigned LC4G1D1T
: 1;
20480 unsigned LC4G1D2N
: 1;
20481 unsigned LC4G1D2T
: 1;
20482 unsigned LC4G1D3N
: 1;
20483 unsigned LC4G1D3T
: 1;
20484 unsigned LC4G1D4N
: 1;
20485 unsigned LC4G1D4T
: 1;
20499 } __CLC4GLS0bits_t
;
20501 extern __at(0x0F34) volatile __CLC4GLS0bits_t CLC4GLS0bits
;
20503 #define _CLC4GLS0_LC4G1D1N 0x01
20504 #define _CLC4GLS0_D1N 0x01
20505 #define _CLC4GLS0_LC4G1D1T 0x02
20506 #define _CLC4GLS0_D1T 0x02
20507 #define _CLC4GLS0_LC4G1D2N 0x04
20508 #define _CLC4GLS0_D2N 0x04
20509 #define _CLC4GLS0_LC4G1D2T 0x08
20510 #define _CLC4GLS0_D2T 0x08
20511 #define _CLC4GLS0_LC4G1D3N 0x10
20512 #define _CLC4GLS0_D3N 0x10
20513 #define _CLC4GLS0_LC4G1D3T 0x20
20514 #define _CLC4GLS0_D3T 0x20
20515 #define _CLC4GLS0_LC4G1D4N 0x40
20516 #define _CLC4GLS0_D4N 0x40
20517 #define _CLC4GLS0_LC4G1D4T 0x80
20518 #define _CLC4GLS0_D4T 0x80
20520 //==============================================================================
20523 //==============================================================================
20526 extern __at(0x0F35) __sfr CLC4GLS1
;
20532 unsigned LC4G2D1N
: 1;
20533 unsigned LC4G2D1T
: 1;
20534 unsigned LC4G2D2N
: 1;
20535 unsigned LC4G2D2T
: 1;
20536 unsigned LC4G2D3N
: 1;
20537 unsigned LC4G2D3T
: 1;
20538 unsigned LC4G2D4N
: 1;
20539 unsigned LC4G2D4T
: 1;
20553 } __CLC4GLS1bits_t
;
20555 extern __at(0x0F35) volatile __CLC4GLS1bits_t CLC4GLS1bits
;
20557 #define _CLC4GLS1_LC4G2D1N 0x01
20558 #define _CLC4GLS1_D1N 0x01
20559 #define _CLC4GLS1_LC4G2D1T 0x02
20560 #define _CLC4GLS1_D1T 0x02
20561 #define _CLC4GLS1_LC4G2D2N 0x04
20562 #define _CLC4GLS1_D2N 0x04
20563 #define _CLC4GLS1_LC4G2D2T 0x08
20564 #define _CLC4GLS1_D2T 0x08
20565 #define _CLC4GLS1_LC4G2D3N 0x10
20566 #define _CLC4GLS1_D3N 0x10
20567 #define _CLC4GLS1_LC4G2D3T 0x20
20568 #define _CLC4GLS1_D3T 0x20
20569 #define _CLC4GLS1_LC4G2D4N 0x40
20570 #define _CLC4GLS1_D4N 0x40
20571 #define _CLC4GLS1_LC4G2D4T 0x80
20572 #define _CLC4GLS1_D4T 0x80
20574 //==============================================================================
20577 //==============================================================================
20580 extern __at(0x0F36) __sfr CLC4GLS2
;
20586 unsigned LC4G3D1N
: 1;
20587 unsigned LC4G3D1T
: 1;
20588 unsigned LC4G3D2N
: 1;
20589 unsigned LC4G3D2T
: 1;
20590 unsigned LC4G3D3N
: 1;
20591 unsigned LC4G3D3T
: 1;
20592 unsigned LC4G3D4N
: 1;
20593 unsigned LC4G3D4T
: 1;
20607 } __CLC4GLS2bits_t
;
20609 extern __at(0x0F36) volatile __CLC4GLS2bits_t CLC4GLS2bits
;
20611 #define _CLC4GLS2_LC4G3D1N 0x01
20612 #define _CLC4GLS2_D1N 0x01
20613 #define _CLC4GLS2_LC4G3D1T 0x02
20614 #define _CLC4GLS2_D1T 0x02
20615 #define _CLC4GLS2_LC4G3D2N 0x04
20616 #define _CLC4GLS2_D2N 0x04
20617 #define _CLC4GLS2_LC4G3D2T 0x08
20618 #define _CLC4GLS2_D2T 0x08
20619 #define _CLC4GLS2_LC4G3D3N 0x10
20620 #define _CLC4GLS2_D3N 0x10
20621 #define _CLC4GLS2_LC4G3D3T 0x20
20622 #define _CLC4GLS2_D3T 0x20
20623 #define _CLC4GLS2_LC4G3D4N 0x40
20624 #define _CLC4GLS2_D4N 0x40
20625 #define _CLC4GLS2_LC4G3D4T 0x80
20626 #define _CLC4GLS2_D4T 0x80
20628 //==============================================================================
20631 //==============================================================================
20634 extern __at(0x0F37) __sfr CLC4GLS3
;
20640 unsigned LC4G4D1N
: 1;
20641 unsigned LC4G4D1T
: 1;
20642 unsigned LC4G4D2N
: 1;
20643 unsigned LC4G4D2T
: 1;
20644 unsigned LC4G4D3N
: 1;
20645 unsigned LC4G4D3T
: 1;
20646 unsigned LC4G4D4N
: 1;
20647 unsigned LC4G4D4T
: 1;
20652 unsigned G4D1N
: 1;
20653 unsigned G4D1T
: 1;
20654 unsigned G4D2N
: 1;
20655 unsigned G4D2T
: 1;
20656 unsigned G4D3N
: 1;
20657 unsigned G4D3T
: 1;
20658 unsigned G4D4N
: 1;
20659 unsigned G4D4T
: 1;
20661 } __CLC4GLS3bits_t
;
20663 extern __at(0x0F37) volatile __CLC4GLS3bits_t CLC4GLS3bits
;
20665 #define _CLC4GLS3_LC4G4D1N 0x01
20666 #define _CLC4GLS3_G4D1N 0x01
20667 #define _CLC4GLS3_LC4G4D1T 0x02
20668 #define _CLC4GLS3_G4D1T 0x02
20669 #define _CLC4GLS3_LC4G4D2N 0x04
20670 #define _CLC4GLS3_G4D2N 0x04
20671 #define _CLC4GLS3_LC4G4D2T 0x08
20672 #define _CLC4GLS3_G4D2T 0x08
20673 #define _CLC4GLS3_LC4G4D3N 0x10
20674 #define _CLC4GLS3_G4D3N 0x10
20675 #define _CLC4GLS3_LC4G4D3T 0x20
20676 #define _CLC4GLS3_G4D3T 0x20
20677 #define _CLC4GLS3_LC4G4D4N 0x40
20678 #define _CLC4GLS3_G4D4N 0x40
20679 #define _CLC4GLS3_LC4G4D4T 0x80
20680 #define _CLC4GLS3_G4D4T 0x80
20682 //==============================================================================
20685 //==============================================================================
20686 // STATUS_SHAD Bits
20688 extern __at(0x0FE4) __sfr STATUS_SHAD
;
20692 unsigned C_SHAD
: 1;
20693 unsigned DC_SHAD
: 1;
20694 unsigned Z_SHAD
: 1;
20700 } __STATUS_SHADbits_t
;
20702 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
20704 #define _C_SHAD 0x01
20705 #define _DC_SHAD 0x02
20706 #define _Z_SHAD 0x04
20708 //==============================================================================
20710 extern __at(0x0FE5) __sfr WREG_SHAD
;
20711 extern __at(0x0FE6) __sfr BSR_SHAD
;
20712 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
20713 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
20714 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
20715 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
20716 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
20717 extern __at(0x0FED) __sfr STKPTR
;
20718 extern __at(0x0FEE) __sfr TOSL
;
20719 extern __at(0x0FEF) __sfr TOSH
;
20721 //==============================================================================
20723 // Configuration Bits
20725 //==============================================================================
20727 #define _CONFIG1 0x8007
20728 #define _CONFIG2 0x8008
20730 //----------------------------- CONFIG1 Options -------------------------------
20732 #define _FOSC_LP 0x3FF8 // LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins.
20733 #define _FOSC_XT 0x3FF9 // XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins.
20734 #define _FOSC_HS 0x3FFA // HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins.
20735 #define _FOSC_EXTRC 0x3FFB // EXTRC oscillator: External RC circuit connected to CLKIN pin.
20736 #define _FOSC_INTOSC 0x3FFC // INTOSC oscillator: I/O function on CLKIN pin.
20737 #define _FOSC_ECL 0x3FFD // ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pins.
20738 #define _FOSC_ECM 0x3FFE // ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pins.
20739 #define _FOSC_ECH 0x3FFF // ECH, External Clock, High Power Mode (4-20 MHz): device clock supplied to CLKIN pins.
20740 #define _WDTE_OFF 0x3FE7 // WDT disabled.
20741 #define _WDTE_SWDTEN 0x3FEF // WDT controlled by the SWDTEN bit in the WDTCON register.
20742 #define _WDTE_NSLEEP 0x3FF7 // WDT enabled while running and disabled in Sleep.
20743 #define _WDTE_ON 0x3FFF // WDT enabled.
20744 #define _PWRTE_ON 0x3FDF // PWRT enabled.
20745 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
20746 #define _MCLRE_OFF 0x3FBF // MCLR/VPP pin function is digital input.
20747 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR.
20748 #define _CP_ON 0x3F7F // Program memory code protection is enabled.
20749 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
20750 #define _BOREN_OFF 0x39FF // Brown-out Reset disabled.
20751 #define _BOREN_SBODEN 0x3BFF // Brown-out Reset controlled by the SBOREN bit in the BORCON register.
20752 #define _BOREN_NSLEEP 0x3DFF // Brown-out Reset enabled while running and disabled in Sleep.
20753 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled.
20754 #define _CLKOUTEN_ON 0x37FF // CLKOUT function is enabled on the CLKOUT pin.
20755 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
20756 #define _IESO_OFF 0x2FFF // Internal/External Switchover Mode is disabled.
20757 #define _IESO_ON 0x3FFF // Internal/External Switchover Mode is enabled.
20758 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
20759 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
20761 //----------------------------- CONFIG2 Options -------------------------------
20763 #define _WRT_ALL 0x3FFC // 000h to 1FFFh write protected, no addresses may be modified by EECON control.
20764 #define _WRT_HALF 0x3FFD // 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control.
20765 #define _WRT_BOOT 0x3FFE // 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control.
20766 #define _WRT_OFF 0x3FFF // Write protection off.
20767 #define _PPS1WAY_OFF 0x3FFB // The PPSLOCK bit can be set and cleared repeatedly by software.
20768 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit cannot be cleared once it is set by software.
20769 #define _ZCD_ON 0x3F7F // Zero-cross detect circuit is enabled at POR.
20770 #define _ZCD_OFF 0x3FFF // Zero-cross detect circuit is disabled at POR.
20771 #define _PLLEN_OFF 0x3EFF // 4x PLL is enabled when software sets the SPLLEN bit.
20772 #define _PLLEN_ON 0x3FFF // 4x PLL is always enabled.
20773 #define _STVREN_OFF 0x3DFF // Stack Overflow or Underflow will not cause a Reset.
20774 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
20775 #define _BORV_HI 0x3BFF // Brown-out Reset Voltage (Vbor), high trip point selected.
20776 #define _BORV_LO 0x3FFF // Brown-out Reset Voltage (Vbor), low trip point selected.
20777 #define _LPBOR_ON 0x37FF // Low-Power BOR is enabled.
20778 #define _LPBOR_OFF 0x3FFF // Low-Power BOR is disabled.
20779 #define _DEBUG_ON 0x2FFF // In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger.
20780 #define _DEBUG_OFF 0x3FFF // In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins.
20781 #define _LVP_OFF 0x1FFF // High-voltage on MCLR/VPP must be used for programming.
20782 #define _LVP_ON 0x3FFF // Low-voltage programming enabled.
20784 //==============================================================================
20786 #define _DEVID1 0x8006
20788 #define _IDLOC0 0x8000
20789 #define _IDLOC1 0x8001
20790 #define _IDLOC2 0x8002
20791 #define _IDLOC3 0x8003
20793 //==============================================================================
20795 #ifndef NO_BIT_DEFINES
20797 #define ADON ADCON0bits.ADON // bit 0
20798 #define GO ADCON0bits.GO // bit 1
20800 #define ADNREF ADCON1bits.ADNREF // bit 2
20801 #define ADFM ADCON1bits.ADFM // bit 7
20803 #define ANSA0 ANSELAbits.ANSA0 // bit 0
20804 #define ANSA1 ANSELAbits.ANSA1 // bit 1
20805 #define ANSA2 ANSELAbits.ANSA2 // bit 2
20806 #define ANSA3 ANSELAbits.ANSA3 // bit 3
20807 #define ANSA4 ANSELAbits.ANSA4 // bit 4
20808 #define ANSA5 ANSELAbits.ANSA5 // bit 5
20810 #define ANSB0 ANSELBbits.ANSB0 // bit 0
20811 #define ANSB1 ANSELBbits.ANSB1 // bit 1
20812 #define ANSB2 ANSELBbits.ANSB2 // bit 2
20813 #define ANSB3 ANSELBbits.ANSB3 // bit 3
20814 #define ANSB4 ANSELBbits.ANSB4 // bit 4
20815 #define ANSB5 ANSELBbits.ANSB5 // bit 5
20817 #define ANSC2 ANSELCbits.ANSC2 // bit 2
20818 #define ANSC3 ANSELCbits.ANSC3 // bit 3
20819 #define ANSC4 ANSELCbits.ANSC4 // bit 4
20820 #define ANSC5 ANSELCbits.ANSC5 // bit 5
20821 #define ANSC6 ANSELCbits.ANSC6 // bit 6
20822 #define ANSC7 ANSELCbits.ANSC7 // bit 7
20824 #define ABDEN BAUD1CONbits.ABDEN // bit 0
20825 #define WUE BAUD1CONbits.WUE // bit 1
20826 #define BRG16 BAUD1CONbits.BRG16 // bit 3
20827 #define SCKP BAUD1CONbits.SCKP // bit 4
20828 #define RCIDL BAUD1CONbits.RCIDL // bit 6
20829 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
20831 #define BORRDY BORCONbits.BORRDY // bit 0
20832 #define BORFS BORCONbits.BORFS // bit 6
20833 #define SBOREN BORCONbits.SBOREN // bit 7
20835 #define BSR0 BSRbits.BSR0 // bit 0
20836 #define BSR1 BSRbits.BSR1 // bit 1
20837 #define BSR2 BSRbits.BSR2 // bit 2
20838 #define BSR3 BSRbits.BSR3 // bit 3
20839 #define BSR4 BSRbits.BSR4 // bit 4
20841 #define CTS0 CCP1CAPbits.CTS0 // bit 0, shadows bit in CCP1CAPbits
20842 #define CCP1CTS0 CCP1CAPbits.CCP1CTS0 // bit 0, shadows bit in CCP1CAPbits
20843 #define CTS1 CCP1CAPbits.CTS1 // bit 1, shadows bit in CCP1CAPbits
20844 #define CCP1CTS1 CCP1CAPbits.CCP1CTS1 // bit 1, shadows bit in CCP1CAPbits
20845 #define CTS2 CCP1CAPbits.CTS2 // bit 2, shadows bit in CCP1CAPbits
20846 #define CCP1CTS2 CCP1CAPbits.CCP1CTS2 // bit 2, shadows bit in CCP1CAPbits
20847 #define CTS3 CCP1CAPbits.CTS3 // bit 3, shadows bit in CCP1CAPbits
20848 #define CCP1CTS3 CCP1CAPbits.CCP1CTS3 // bit 3, shadows bit in CCP1CAPbits
20850 #define MODE0 CCP1CONbits.MODE0 // bit 0, shadows bit in CCP1CONbits
20851 #define CCP1MODE0 CCP1CONbits.CCP1MODE0 // bit 0, shadows bit in CCP1CONbits
20852 #define MODE1 CCP1CONbits.MODE1 // bit 1, shadows bit in CCP1CONbits
20853 #define CCP1MODE1 CCP1CONbits.CCP1MODE1 // bit 1, shadows bit in CCP1CONbits
20854 #define MODE2 CCP1CONbits.MODE2 // bit 2, shadows bit in CCP1CONbits
20855 #define CCP1MODE2 CCP1CONbits.CCP1MODE2 // bit 2, shadows bit in CCP1CONbits
20856 #define MODE3 CCP1CONbits.MODE3 // bit 3, shadows bit in CCP1CONbits
20857 #define CCP1MODE3 CCP1CONbits.CCP1MODE3 // bit 3, shadows bit in CCP1CONbits
20858 #define FMT CCP1CONbits.FMT // bit 4, shadows bit in CCP1CONbits
20859 #define CCP1FMT CCP1CONbits.CCP1FMT // bit 4, shadows bit in CCP1CONbits
20860 #define OUT CCP1CONbits.OUT // bit 5, shadows bit in CCP1CONbits
20861 #define CCP1OUT CCP1CONbits.CCP1OUT // bit 5, shadows bit in CCP1CONbits
20862 #define EN CCP1CONbits.EN // bit 7, shadows bit in CCP1CONbits
20863 #define CCP1EN CCP1CONbits.CCP1EN // bit 7, shadows bit in CCP1CONbits
20865 #define C1TSEL0 CCPTMRS1bits.C1TSEL0 // bit 0
20866 #define C1TSEL1 CCPTMRS1bits.C1TSEL1 // bit 1
20867 #define C2TSEL0 CCPTMRS1bits.C2TSEL0 // bit 2
20868 #define C2TSEL1 CCPTMRS1bits.C2TSEL1 // bit 3
20869 #define C7TSEL0 CCPTMRS1bits.C7TSEL0 // bit 4
20870 #define C7TSEL1 CCPTMRS1bits.C7TSEL1 // bit 5
20872 #define P3TSEL0 CCPTMRS2bits.P3TSEL0 // bit 0
20873 #define P3TSEL1 CCPTMRS2bits.P3TSEL1 // bit 1
20874 #define P4TSEL0 CCPTMRS2bits.P4TSEL0 // bit 2
20875 #define P4TSEL1 CCPTMRS2bits.P4TSEL1 // bit 3
20876 #define P9TSEL0 CCPTMRS2bits.P9TSEL0 // bit 4
20877 #define P9TSEL1 CCPTMRS2bits.P9TSEL1 // bit 5
20879 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
20880 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
20881 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
20882 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
20883 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
20884 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
20885 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
20886 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
20887 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
20888 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
20889 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
20890 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
20891 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
20892 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
20893 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
20894 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
20896 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
20897 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
20898 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
20899 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
20900 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
20901 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
20902 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
20903 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
20904 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
20905 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
20906 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
20907 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
20908 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
20909 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
20910 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
20911 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
20913 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
20914 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
20915 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
20916 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
20917 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
20918 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
20919 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
20920 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
20921 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
20922 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
20924 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
20925 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
20926 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
20927 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
20928 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
20929 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
20930 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
20931 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
20932 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
20933 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
20934 #define LC1D1S5 CLC1SEL0bits.LC1D1S5 // bit 5, shadows bit in CLC1SEL0bits
20935 #define D1S5 CLC1SEL0bits.D1S5 // bit 5, shadows bit in CLC1SEL0bits
20937 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
20938 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
20939 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
20940 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
20941 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
20942 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
20943 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
20944 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
20945 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
20946 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
20947 #define LC1D2S5 CLC1SEL1bits.LC1D2S5 // bit 5, shadows bit in CLC1SEL1bits
20948 #define D2S5 CLC1SEL1bits.D2S5 // bit 5, shadows bit in CLC1SEL1bits
20950 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
20951 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
20952 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
20953 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
20954 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
20955 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
20956 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
20957 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
20958 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
20959 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
20960 #define LC1D3S5 CLC1SEL2bits.LC1D3S5 // bit 5, shadows bit in CLC1SEL2bits
20961 #define D3S5 CLC1SEL2bits.D3S5 // bit 5, shadows bit in CLC1SEL2bits
20963 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
20964 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
20965 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
20966 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
20967 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
20968 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
20969 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
20970 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
20971 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
20972 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
20973 #define LC1D4S5 CLC1SEL3bits.LC1D4S5 // bit 5, shadows bit in CLC1SEL3bits
20974 #define D4S5 CLC1SEL3bits.D4S5 // bit 5, shadows bit in CLC1SEL3bits
20976 #define MCLC1OUT CLCDATAbits.MCLC1OUT // bit 0
20977 #define MCLC2OUT CLCDATAbits.MCLC2OUT // bit 1
20978 #define MCLC3OUT CLCDATAbits.MCLC3OUT // bit 2
20979 #define MLC4OUT CLCDATAbits.MLC4OUT // bit 3
20981 #define C1NCH0 CM1NSELbits.C1NCH0 // bit 0
20982 #define C1NCH1 CM1NSELbits.C1NCH1 // bit 1
20983 #define C1NCH2 CM1NSELbits.C1NCH2 // bit 2
20984 #define C1NCH3 CM1NSELbits.C1NCH3 // bit 3
20986 #define PCH0 CM1PSELbits.PCH0 // bit 0, shadows bit in CM1PSELbits
20987 #define C1PCH0 CM1PSELbits.C1PCH0 // bit 0, shadows bit in CM1PSELbits
20988 #define PCH1 CM1PSELbits.PCH1 // bit 1, shadows bit in CM1PSELbits
20989 #define C1PCH1 CM1PSELbits.C1PCH1 // bit 1, shadows bit in CM1PSELbits
20990 #define PCH2 CM1PSELbits.PCH2 // bit 2, shadows bit in CM1PSELbits
20991 #define C1PCH2 CM1PSELbits.C1PCH2 // bit 2, shadows bit in CM1PSELbits
20992 #define PCH3 CM1PSELbits.PCH3 // bit 3, shadows bit in CM1PSELbits
20993 #define C1PCH3 CM1PSELbits.C1PCH3 // bit 3, shadows bit in CM1PSELbits
20995 #define C2NCH0 CM2NSELbits.C2NCH0 // bit 0
20996 #define C2NCH1 CM2NSELbits.C2NCH1 // bit 1
20997 #define C2NCH2 CM2NSELbits.C2NCH2 // bit 2
20998 #define C2NCH3 CM2NSELbits.C2NCH3 // bit 3
21000 #define C3NCH0 CM3NSELbits.C3NCH0 // bit 0
21001 #define C3NCH1 CM3NSELbits.C3NCH1 // bit 1
21002 #define C3NCH2 CM3NSELbits.C3NCH2 // bit 2
21003 #define C3NCH3 CM3NSELbits.C3NCH3 // bit 3
21005 #define C4NCH0 CM4NSELbits.C4NCH0 // bit 0
21006 #define C4NCH1 CM4NSELbits.C4NCH1 // bit 1
21007 #define C4NCH2 CM4NSELbits.C4NCH2 // bit 2
21008 #define C4NCH3 CM4NSELbits.C4NCH3 // bit 3
21010 #define C5NCH0 CM5NSELbits.C5NCH0 // bit 0
21011 #define C5NCH1 CM5NSELbits.C5NCH1 // bit 1
21012 #define C5NCH2 CM5NSELbits.C5NCH2 // bit 2
21013 #define C5NCH3 CM5NSELbits.C5NCH3 // bit 3
21015 #define C6NCH0 CM6NSELbits.C6NCH0 // bit 0
21016 #define C6NCH1 CM6NSELbits.C6NCH1 // bit 1
21017 #define C6NCH2 CM6NSELbits.C6NCH2 // bit 2
21018 #define C6NCH3 CM6NSELbits.C6NCH3 // bit 3
21020 #define MC1OUT CMOUTbits.MC1OUT // bit 0
21021 #define MC2OUT CMOUTbits.MC2OUT // bit 1
21022 #define MC3OUT CMOUTbits.MC3OUT // bit 2
21023 #define MC4OUT CMOUTbits.MC4OUT // bit 3
21024 #define MC5OUT CMOUTbits.MC5OUT // bit 4
21025 #define MC6OUT CMOUTbits.MC6OUT // bit 5
21027 #define ASDAC0 COG1ASD0bits.ASDAC0 // bit 2, shadows bit in COG1ASD0bits
21028 #define G1ASDAC0 COG1ASD0bits.G1ASDAC0 // bit 2, shadows bit in COG1ASD0bits
21029 #define ASDAC1 COG1ASD0bits.ASDAC1 // bit 3, shadows bit in COG1ASD0bits
21030 #define G1ASDAC1 COG1ASD0bits.G1ASDAC1 // bit 3, shadows bit in COG1ASD0bits
21031 #define ASDBD0 COG1ASD0bits.ASDBD0 // bit 4, shadows bit in COG1ASD0bits
21032 #define G1ASDBD0 COG1ASD0bits.G1ASDBD0 // bit 4, shadows bit in COG1ASD0bits
21033 #define ASDBD1 COG1ASD0bits.ASDBD1 // bit 5, shadows bit in COG1ASD0bits
21034 #define G1ASDBD1 COG1ASD0bits.G1ASDBD1 // bit 5, shadows bit in COG1ASD0bits
21035 #define ASREN COG1ASD0bits.ASREN // bit 6, shadows bit in COG1ASD0bits
21036 #define ARSEN COG1ASD0bits.ARSEN // bit 6, shadows bit in COG1ASD0bits
21037 #define G1ARSEN COG1ASD0bits.G1ARSEN // bit 6, shadows bit in COG1ASD0bits
21038 #define G1ASREN COG1ASD0bits.G1ASREN // bit 6, shadows bit in COG1ASD0bits
21039 #define ASE COG1ASD0bits.ASE // bit 7, shadows bit in COG1ASD0bits
21040 #define G1ASE COG1ASD0bits.G1ASE // bit 7, shadows bit in COG1ASD0bits
21042 #define AS0E COG1ASD1bits.AS0E // bit 0, shadows bit in COG1ASD1bits
21043 #define G1AS0E COG1ASD1bits.G1AS0E // bit 0, shadows bit in COG1ASD1bits
21044 #define AS1E COG1ASD1bits.AS1E // bit 1, shadows bit in COG1ASD1bits
21045 #define G1AS1E COG1ASD1bits.G1AS1E // bit 1, shadows bit in COG1ASD1bits
21046 #define AS2E COG1ASD1bits.AS2E // bit 2, shadows bit in COG1ASD1bits
21047 #define G1AS2E COG1ASD1bits.G1AS2E // bit 2, shadows bit in COG1ASD1bits
21048 #define AS3E COG1ASD1bits.AS3E // bit 3, shadows bit in COG1ASD1bits
21049 #define G1AS3E COG1ASD1bits.G1AS3E // bit 3, shadows bit in COG1ASD1bits
21050 #define AS4E COG1ASD1bits.AS4E // bit 4, shadows bit in COG1ASD1bits
21051 #define G1AS4E COG1ASD1bits.G1AS4E // bit 4, shadows bit in COG1ASD1bits
21052 #define AS5E COG1ASD1bits.AS5E // bit 5, shadows bit in COG1ASD1bits
21053 #define G1AS5E COG1ASD1bits.G1AS5E // bit 5, shadows bit in COG1ASD1bits
21054 #define AS6E COG1ASD1bits.AS6E // bit 6, shadows bit in COG1ASD1bits
21055 #define G1AS6E COG1ASD1bits.G1AS6E // bit 6, shadows bit in COG1ASD1bits
21056 #define AS7E COG1ASD1bits.AS7E // bit 7, shadows bit in COG1ASD1bits
21057 #define G1AS7E COG1ASD1bits.G1AS7E // bit 7, shadows bit in COG1ASD1bits
21059 #define BLKF0 COG1BLKFbits.BLKF0 // bit 0, shadows bit in COG1BLKFbits
21060 #define G1BLKF0 COG1BLKFbits.G1BLKF0 // bit 0, shadows bit in COG1BLKFbits
21061 #define BLKF1 COG1BLKFbits.BLKF1 // bit 1, shadows bit in COG1BLKFbits
21062 #define G1BLKF1 COG1BLKFbits.G1BLKF1 // bit 1, shadows bit in COG1BLKFbits
21063 #define BLKF2 COG1BLKFbits.BLKF2 // bit 2, shadows bit in COG1BLKFbits
21064 #define G1BLKF2 COG1BLKFbits.G1BLKF2 // bit 2, shadows bit in COG1BLKFbits
21065 #define BLKF3 COG1BLKFbits.BLKF3 // bit 3, shadows bit in COG1BLKFbits
21066 #define G1BLKF3 COG1BLKFbits.G1BLKF3 // bit 3, shadows bit in COG1BLKFbits
21067 #define BLKF4 COG1BLKFbits.BLKF4 // bit 4, shadows bit in COG1BLKFbits
21068 #define G1BLKF4 COG1BLKFbits.G1BLKF4 // bit 4, shadows bit in COG1BLKFbits
21069 #define BLKF5 COG1BLKFbits.BLKF5 // bit 5, shadows bit in COG1BLKFbits
21070 #define G1BLKF5 COG1BLKFbits.G1BLKF5 // bit 5, shadows bit in COG1BLKFbits
21072 #define BLKR0 COG1BLKRbits.BLKR0 // bit 0, shadows bit in COG1BLKRbits
21073 #define G1BLKR0 COG1BLKRbits.G1BLKR0 // bit 0, shadows bit in COG1BLKRbits
21074 #define BLKR1 COG1BLKRbits.BLKR1 // bit 1, shadows bit in COG1BLKRbits
21075 #define G1BLKR1 COG1BLKRbits.G1BLKR1 // bit 1, shadows bit in COG1BLKRbits
21076 #define BLKR2 COG1BLKRbits.BLKR2 // bit 2, shadows bit in COG1BLKRbits
21077 #define G1BLKR2 COG1BLKRbits.G1BLKR2 // bit 2, shadows bit in COG1BLKRbits
21078 #define BLKR3 COG1BLKRbits.BLKR3 // bit 3, shadows bit in COG1BLKRbits
21079 #define G1BLKR3 COG1BLKRbits.G1BLKR3 // bit 3, shadows bit in COG1BLKRbits
21080 #define BLKR4 COG1BLKRbits.BLKR4 // bit 4, shadows bit in COG1BLKRbits
21081 #define G1BLKR4 COG1BLKRbits.G1BLKR4 // bit 4, shadows bit in COG1BLKRbits
21082 #define BLKR5 COG1BLKRbits.BLKR5 // bit 5, shadows bit in COG1BLKRbits
21083 #define G1BLKR5 COG1BLKRbits.G1BLKR5 // bit 5, shadows bit in COG1BLKRbits
21085 #define POLA COG1CON1bits.POLA // bit 0, shadows bit in COG1CON1bits
21086 #define G1POLA COG1CON1bits.G1POLA // bit 0, shadows bit in COG1CON1bits
21087 #define POLB COG1CON1bits.POLB // bit 1, shadows bit in COG1CON1bits
21088 #define G1POLB COG1CON1bits.G1POLB // bit 1, shadows bit in COG1CON1bits
21089 #define POLC COG1CON1bits.POLC // bit 2, shadows bit in COG1CON1bits
21090 #define G1POLC COG1CON1bits.G1POLC // bit 2, shadows bit in COG1CON1bits
21091 #define POLD COG1CON1bits.POLD // bit 3, shadows bit in COG1CON1bits
21092 #define G1POLD COG1CON1bits.G1POLD // bit 3, shadows bit in COG1CON1bits
21093 #define FDBS COG1CON1bits.FDBS // bit 6, shadows bit in COG1CON1bits
21094 #define G1FDBS COG1CON1bits.G1FDBS // bit 6, shadows bit in COG1CON1bits
21095 #define RDBS COG1CON1bits.RDBS // bit 7, shadows bit in COG1CON1bits
21096 #define G1RDBS COG1CON1bits.G1RDBS // bit 7, shadows bit in COG1CON1bits
21098 #define DBF0 COG1DBFbits.DBF0 // bit 0, shadows bit in COG1DBFbits
21099 #define G1DBF0 COG1DBFbits.G1DBF0 // bit 0, shadows bit in COG1DBFbits
21100 #define DBF1 COG1DBFbits.DBF1 // bit 1, shadows bit in COG1DBFbits
21101 #define G1DBF1 COG1DBFbits.G1DBF1 // bit 1, shadows bit in COG1DBFbits
21102 #define DBF2 COG1DBFbits.DBF2 // bit 2, shadows bit in COG1DBFbits
21103 #define G1DBF2 COG1DBFbits.G1DBF2 // bit 2, shadows bit in COG1DBFbits
21104 #define DBF3 COG1DBFbits.DBF3 // bit 3, shadows bit in COG1DBFbits
21105 #define G1DBF3 COG1DBFbits.G1DBF3 // bit 3, shadows bit in COG1DBFbits
21106 #define DBF4 COG1DBFbits.DBF4 // bit 4, shadows bit in COG1DBFbits
21107 #define G1DBF4 COG1DBFbits.G1DBF4 // bit 4, shadows bit in COG1DBFbits
21108 #define DBF5 COG1DBFbits.DBF5 // bit 5, shadows bit in COG1DBFbits
21109 #define G1DBF5 COG1DBFbits.G1DBF5 // bit 5, shadows bit in COG1DBFbits
21111 #define DBR0 COG1DBRbits.DBR0 // bit 0, shadows bit in COG1DBRbits
21112 #define G1DBR0 COG1DBRbits.G1DBR0 // bit 0, shadows bit in COG1DBRbits
21113 #define DBR1 COG1DBRbits.DBR1 // bit 1, shadows bit in COG1DBRbits
21114 #define G1DBR1 COG1DBRbits.G1DBR1 // bit 1, shadows bit in COG1DBRbits
21115 #define DBR2 COG1DBRbits.DBR2 // bit 2, shadows bit in COG1DBRbits
21116 #define G1DBR2 COG1DBRbits.G1DBR2 // bit 2, shadows bit in COG1DBRbits
21117 #define DBR3 COG1DBRbits.DBR3 // bit 3, shadows bit in COG1DBRbits
21118 #define G1DBR3 COG1DBRbits.G1DBR3 // bit 3, shadows bit in COG1DBRbits
21119 #define DBR4 COG1DBRbits.DBR4 // bit 4, shadows bit in COG1DBRbits
21120 #define G1DBR4 COG1DBRbits.G1DBR4 // bit 4, shadows bit in COG1DBRbits
21121 #define DBR5 COG1DBRbits.DBR5 // bit 5, shadows bit in COG1DBRbits
21122 #define G1DBR5 COG1DBRbits.G1DBR5 // bit 5, shadows bit in COG1DBRbits
21124 #define FIS0 COG1FIS0bits.FIS0 // bit 0, shadows bit in COG1FIS0bits
21125 #define G1FIS0 COG1FIS0bits.G1FIS0 // bit 0, shadows bit in COG1FIS0bits
21126 #define FIS1 COG1FIS0bits.FIS1 // bit 1, shadows bit in COG1FIS0bits
21127 #define G1FIS1 COG1FIS0bits.G1FIS1 // bit 1, shadows bit in COG1FIS0bits
21128 #define FIS2 COG1FIS0bits.FIS2 // bit 2, shadows bit in COG1FIS0bits
21129 #define G1FIS2 COG1FIS0bits.G1FIS2 // bit 2, shadows bit in COG1FIS0bits
21130 #define FIS3 COG1FIS0bits.FIS3 // bit 3, shadows bit in COG1FIS0bits
21131 #define G1FIS3 COG1FIS0bits.G1FIS3 // bit 3, shadows bit in COG1FIS0bits
21132 #define FIS4 COG1FIS0bits.FIS4 // bit 4, shadows bit in COG1FIS0bits
21133 #define G1FIS4 COG1FIS0bits.G1FIS4 // bit 4, shadows bit in COG1FIS0bits
21134 #define FIS5 COG1FIS0bits.FIS5 // bit 5, shadows bit in COG1FIS0bits
21135 #define G1FIS5 COG1FIS0bits.G1FIS5 // bit 5, shadows bit in COG1FIS0bits
21136 #define FIS6 COG1FIS0bits.FIS6 // bit 6, shadows bit in COG1FIS0bits
21137 #define G1FIS6 COG1FIS0bits.G1FIS6 // bit 6, shadows bit in COG1FIS0bits
21138 #define FIS7 COG1FIS0bits.FIS7 // bit 7, shadows bit in COG1FIS0bits
21139 #define G1FIS7 COG1FIS0bits.G1FIS7 // bit 7, shadows bit in COG1FIS0bits
21141 #define FIS8 COG1FIS1bits.FIS8 // bit 0, shadows bit in COG1FIS1bits
21142 #define G1FIS8 COG1FIS1bits.G1FIS8 // bit 0, shadows bit in COG1FIS1bits
21143 #define FIS9 COG1FIS1bits.FIS9 // bit 1, shadows bit in COG1FIS1bits
21144 #define G1FIS9 COG1FIS1bits.G1FIS9 // bit 1, shadows bit in COG1FIS1bits
21145 #define FIS10 COG1FIS1bits.FIS10 // bit 2, shadows bit in COG1FIS1bits
21146 #define G1FIS10 COG1FIS1bits.G1FIS10 // bit 2, shadows bit in COG1FIS1bits
21147 #define FIS11 COG1FIS1bits.FIS11 // bit 3, shadows bit in COG1FIS1bits
21148 #define G1FIS11 COG1FIS1bits.G1FIS11 // bit 3, shadows bit in COG1FIS1bits
21149 #define FIS12 COG1FIS1bits.FIS12 // bit 4, shadows bit in COG1FIS1bits
21150 #define G1FIS12 COG1FIS1bits.G1FIS12 // bit 4, shadows bit in COG1FIS1bits
21151 #define FIS13 COG1FIS1bits.FIS13 // bit 5, shadows bit in COG1FIS1bits
21152 #define G1FIS13 COG1FIS1bits.G1FIS13 // bit 5, shadows bit in COG1FIS1bits
21153 #define FIS14 COG1FIS1bits.FIS14 // bit 6, shadows bit in COG1FIS1bits
21154 #define G1FIS14 COG1FIS1bits.G1FIS14 // bit 6, shadows bit in COG1FIS1bits
21155 #define FIS15 COG1FIS1bits.FIS15 // bit 7, shadows bit in COG1FIS1bits
21156 #define G1FIS15 COG1FIS1bits.G1FIS15 // bit 7, shadows bit in COG1FIS1bits
21158 #define FSIM0 COG1FSIM0bits.FSIM0 // bit 0, shadows bit in COG1FSIM0bits
21159 #define G1FSIM0 COG1FSIM0bits.G1FSIM0 // bit 0, shadows bit in COG1FSIM0bits
21160 #define FSIM1 COG1FSIM0bits.FSIM1 // bit 1, shadows bit in COG1FSIM0bits
21161 #define G1FSIM1 COG1FSIM0bits.G1FSIM1 // bit 1, shadows bit in COG1FSIM0bits
21162 #define FSIM2 COG1FSIM0bits.FSIM2 // bit 2, shadows bit in COG1FSIM0bits
21163 #define G1FSIM2 COG1FSIM0bits.G1FSIM2 // bit 2, shadows bit in COG1FSIM0bits
21164 #define FSIM3 COG1FSIM0bits.FSIM3 // bit 3, shadows bit in COG1FSIM0bits
21165 #define G1FSIM3 COG1FSIM0bits.G1FSIM3 // bit 3, shadows bit in COG1FSIM0bits
21166 #define FSIM4 COG1FSIM0bits.FSIM4 // bit 4, shadows bit in COG1FSIM0bits
21167 #define G1FSIM4 COG1FSIM0bits.G1FSIM4 // bit 4, shadows bit in COG1FSIM0bits
21168 #define FSIM5 COG1FSIM0bits.FSIM5 // bit 5, shadows bit in COG1FSIM0bits
21169 #define G1FSIM5 COG1FSIM0bits.G1FSIM5 // bit 5, shadows bit in COG1FSIM0bits
21170 #define FSIM6 COG1FSIM0bits.FSIM6 // bit 6, shadows bit in COG1FSIM0bits
21171 #define G1FSIM6 COG1FSIM0bits.G1FSIM6 // bit 6, shadows bit in COG1FSIM0bits
21172 #define FSIM7 COG1FSIM0bits.FSIM7 // bit 7, shadows bit in COG1FSIM0bits
21173 #define G1FSIM7 COG1FSIM0bits.G1FSIM7 // bit 7, shadows bit in COG1FSIM0bits
21175 #define FSIM8 COG1FSIM1bits.FSIM8 // bit 0, shadows bit in COG1FSIM1bits
21176 #define G1FSIM8 COG1FSIM1bits.G1FSIM8 // bit 0, shadows bit in COG1FSIM1bits
21177 #define FSIM9 COG1FSIM1bits.FSIM9 // bit 1, shadows bit in COG1FSIM1bits
21178 #define G1FSIM9 COG1FSIM1bits.G1FSIM9 // bit 1, shadows bit in COG1FSIM1bits
21179 #define FSIM10 COG1FSIM1bits.FSIM10 // bit 2, shadows bit in COG1FSIM1bits
21180 #define G1FSIM10 COG1FSIM1bits.G1FSIM10 // bit 2, shadows bit in COG1FSIM1bits
21181 #define FSIM11 COG1FSIM1bits.FSIM11 // bit 3, shadows bit in COG1FSIM1bits
21182 #define G1FSIM11 COG1FSIM1bits.G1FSIM11 // bit 3, shadows bit in COG1FSIM1bits
21183 #define FSIM12 COG1FSIM1bits.FSIM12 // bit 4, shadows bit in COG1FSIM1bits
21184 #define G1FSIM12 COG1FSIM1bits.G1FSIM12 // bit 4, shadows bit in COG1FSIM1bits
21185 #define FSIM13 COG1FSIM1bits.FSIM13 // bit 5, shadows bit in COG1FSIM1bits
21186 #define G1FSIM13 COG1FSIM1bits.G1FSIM13 // bit 5, shadows bit in COG1FSIM1bits
21187 #define FSIM14 COG1FSIM1bits.FSIM14 // bit 6, shadows bit in COG1FSIM1bits
21188 #define G1FSIM14 COG1FSIM1bits.G1FSIM14 // bit 6, shadows bit in COG1FSIM1bits
21189 #define FSIM15 COG1FSIM1bits.FSIM15 // bit 7, shadows bit in COG1FSIM1bits
21190 #define G1FSIM15 COG1FSIM1bits.G1FSIM15 // bit 7, shadows bit in COG1FSIM1bits
21192 #define PHF0 COG1PHFbits.PHF0 // bit 0, shadows bit in COG1PHFbits
21193 #define G1PHF0 COG1PHFbits.G1PHF0 // bit 0, shadows bit in COG1PHFbits
21194 #define PHF1 COG1PHFbits.PHF1 // bit 1, shadows bit in COG1PHFbits
21195 #define G1PHF1 COG1PHFbits.G1PHF1 // bit 1, shadows bit in COG1PHFbits
21196 #define PHF2 COG1PHFbits.PHF2 // bit 2, shadows bit in COG1PHFbits
21197 #define G1PHF2 COG1PHFbits.G1PHF2 // bit 2, shadows bit in COG1PHFbits
21198 #define PHF3 COG1PHFbits.PHF3 // bit 3, shadows bit in COG1PHFbits
21199 #define G1PHF3 COG1PHFbits.G1PHF3 // bit 3, shadows bit in COG1PHFbits
21200 #define PHF4 COG1PHFbits.PHF4 // bit 4, shadows bit in COG1PHFbits
21201 #define G1PHF4 COG1PHFbits.G1PHF4 // bit 4, shadows bit in COG1PHFbits
21202 #define PHF5 COG1PHFbits.PHF5 // bit 5, shadows bit in COG1PHFbits
21203 #define G1PHF5 COG1PHFbits.G1PHF5 // bit 5, shadows bit in COG1PHFbits
21205 #define PHR0 COG1PHRbits.PHR0 // bit 0, shadows bit in COG1PHRbits
21206 #define G1PHR0 COG1PHRbits.G1PHR0 // bit 0, shadows bit in COG1PHRbits
21207 #define PHR1 COG1PHRbits.PHR1 // bit 1, shadows bit in COG1PHRbits
21208 #define G1PHR1 COG1PHRbits.G1PHR1 // bit 1, shadows bit in COG1PHRbits
21209 #define PHR2 COG1PHRbits.PHR2 // bit 2, shadows bit in COG1PHRbits
21210 #define G1PHR2 COG1PHRbits.G1PHR2 // bit 2, shadows bit in COG1PHRbits
21211 #define PHR3 COG1PHRbits.PHR3 // bit 3, shadows bit in COG1PHRbits
21212 #define G1PHR3 COG1PHRbits.G1PHR3 // bit 3, shadows bit in COG1PHRbits
21213 #define PHR4 COG1PHRbits.PHR4 // bit 4, shadows bit in COG1PHRbits
21214 #define G1PHR4 COG1PHRbits.G1PHR4 // bit 4, shadows bit in COG1PHRbits
21215 #define PHR5 COG1PHRbits.PHR5 // bit 5, shadows bit in COG1PHRbits
21216 #define G1PHR5 COG1PHRbits.G1PHR5 // bit 5, shadows bit in COG1PHRbits
21218 #define RIS0 COG1RIS0bits.RIS0 // bit 0, shadows bit in COG1RIS0bits
21219 #define G1RIS0 COG1RIS0bits.G1RIS0 // bit 0, shadows bit in COG1RIS0bits
21220 #define RIS1 COG1RIS0bits.RIS1 // bit 1, shadows bit in COG1RIS0bits
21221 #define G1RIS1 COG1RIS0bits.G1RIS1 // bit 1, shadows bit in COG1RIS0bits
21222 #define RIS2 COG1RIS0bits.RIS2 // bit 2, shadows bit in COG1RIS0bits
21223 #define G1RIS2 COG1RIS0bits.G1RIS2 // bit 2, shadows bit in COG1RIS0bits
21224 #define RIS3 COG1RIS0bits.RIS3 // bit 3, shadows bit in COG1RIS0bits
21225 #define G1RIS3 COG1RIS0bits.G1RIS3 // bit 3, shadows bit in COG1RIS0bits
21226 #define RIS4 COG1RIS0bits.RIS4 // bit 4, shadows bit in COG1RIS0bits
21227 #define G1RIS4 COG1RIS0bits.G1RIS4 // bit 4, shadows bit in COG1RIS0bits
21228 #define RIS5 COG1RIS0bits.RIS5 // bit 5, shadows bit in COG1RIS0bits
21229 #define G1RIS5 COG1RIS0bits.G1RIS5 // bit 5, shadows bit in COG1RIS0bits
21230 #define RIS6 COG1RIS0bits.RIS6 // bit 6, shadows bit in COG1RIS0bits
21231 #define G1RIS6 COG1RIS0bits.G1RIS6 // bit 6, shadows bit in COG1RIS0bits
21232 #define RIS7 COG1RIS0bits.RIS7 // bit 7, shadows bit in COG1RIS0bits
21233 #define G1RIS7 COG1RIS0bits.G1RIS7 // bit 7, shadows bit in COG1RIS0bits
21235 #define RIS8 COG1RIS1bits.RIS8 // bit 0, shadows bit in COG1RIS1bits
21236 #define G1RIS8 COG1RIS1bits.G1RIS8 // bit 0, shadows bit in COG1RIS1bits
21237 #define RIS9 COG1RIS1bits.RIS9 // bit 1, shadows bit in COG1RIS1bits
21238 #define G1RIS9 COG1RIS1bits.G1RIS9 // bit 1, shadows bit in COG1RIS1bits
21239 #define RIS10 COG1RIS1bits.RIS10 // bit 2, shadows bit in COG1RIS1bits
21240 #define G1RIS10 COG1RIS1bits.G1RIS10 // bit 2, shadows bit in COG1RIS1bits
21241 #define RIS11 COG1RIS1bits.RIS11 // bit 3, shadows bit in COG1RIS1bits
21242 #define G1RIS11 COG1RIS1bits.G1RIS11 // bit 3, shadows bit in COG1RIS1bits
21243 #define RIS12 COG1RIS1bits.RIS12 // bit 4, shadows bit in COG1RIS1bits
21244 #define G1RIS12 COG1RIS1bits.G1RIS12 // bit 4, shadows bit in COG1RIS1bits
21245 #define RIS13 COG1RIS1bits.RIS13 // bit 5, shadows bit in COG1RIS1bits
21246 #define G1RIS13 COG1RIS1bits.G1RIS13 // bit 5, shadows bit in COG1RIS1bits
21247 #define RIS14 COG1RIS1bits.RIS14 // bit 6, shadows bit in COG1RIS1bits
21248 #define G1RIS14 COG1RIS1bits.G1RIS14 // bit 6, shadows bit in COG1RIS1bits
21249 #define RIS15 COG1RIS1bits.RIS15 // bit 7, shadows bit in COG1RIS1bits
21250 #define G1RIS15 COG1RIS1bits.G1RIS15 // bit 7, shadows bit in COG1RIS1bits
21252 #define RSIM0 COG1RSIM0bits.RSIM0 // bit 0, shadows bit in COG1RSIM0bits
21253 #define G1RSIM0 COG1RSIM0bits.G1RSIM0 // bit 0, shadows bit in COG1RSIM0bits
21254 #define RSIM1 COG1RSIM0bits.RSIM1 // bit 1, shadows bit in COG1RSIM0bits
21255 #define G1RSIM1 COG1RSIM0bits.G1RSIM1 // bit 1, shadows bit in COG1RSIM0bits
21256 #define RSIM2 COG1RSIM0bits.RSIM2 // bit 2, shadows bit in COG1RSIM0bits
21257 #define G1RSIM2 COG1RSIM0bits.G1RSIM2 // bit 2, shadows bit in COG1RSIM0bits
21258 #define RSIM3 COG1RSIM0bits.RSIM3 // bit 3, shadows bit in COG1RSIM0bits
21259 #define G1RSIM3 COG1RSIM0bits.G1RSIM3 // bit 3, shadows bit in COG1RSIM0bits
21260 #define RSIM4 COG1RSIM0bits.RSIM4 // bit 4, shadows bit in COG1RSIM0bits
21261 #define G1RSIM4 COG1RSIM0bits.G1RSIM4 // bit 4, shadows bit in COG1RSIM0bits
21262 #define RSIM5 COG1RSIM0bits.RSIM5 // bit 5, shadows bit in COG1RSIM0bits
21263 #define G1RSIM5 COG1RSIM0bits.G1RSIM5 // bit 5, shadows bit in COG1RSIM0bits
21264 #define RSIM6 COG1RSIM0bits.RSIM6 // bit 6, shadows bit in COG1RSIM0bits
21265 #define G1RSIM6 COG1RSIM0bits.G1RSIM6 // bit 6, shadows bit in COG1RSIM0bits
21266 #define RSIM7 COG1RSIM0bits.RSIM7 // bit 7, shadows bit in COG1RSIM0bits
21267 #define G1RSIM7 COG1RSIM0bits.G1RSIM7 // bit 7, shadows bit in COG1RSIM0bits
21269 #define RSIM8 COG1RSIM1bits.RSIM8 // bit 0, shadows bit in COG1RSIM1bits
21270 #define G1RSIM8 COG1RSIM1bits.G1RSIM8 // bit 0, shadows bit in COG1RSIM1bits
21271 #define RSIM9 COG1RSIM1bits.RSIM9 // bit 1, shadows bit in COG1RSIM1bits
21272 #define G1RSIM9 COG1RSIM1bits.G1RSIM9 // bit 1, shadows bit in COG1RSIM1bits
21273 #define RSIM10 COG1RSIM1bits.RSIM10 // bit 2, shadows bit in COG1RSIM1bits
21274 #define G1RSIM10 COG1RSIM1bits.G1RSIM10 // bit 2, shadows bit in COG1RSIM1bits
21275 #define RSIM11 COG1RSIM1bits.RSIM11 // bit 3, shadows bit in COG1RSIM1bits
21276 #define G1RSIM11 COG1RSIM1bits.G1RSIM11 // bit 3, shadows bit in COG1RSIM1bits
21277 #define RSIM12 COG1RSIM1bits.RSIM12 // bit 4, shadows bit in COG1RSIM1bits
21278 #define G1RSIM12 COG1RSIM1bits.G1RSIM12 // bit 4, shadows bit in COG1RSIM1bits
21279 #define RSIM13 COG1RSIM1bits.RSIM13 // bit 5, shadows bit in COG1RSIM1bits
21280 #define G1RSIM13 COG1RSIM1bits.G1RSIM13 // bit 5, shadows bit in COG1RSIM1bits
21281 #define RSIM14 COG1RSIM1bits.RSIM14 // bit 6, shadows bit in COG1RSIM1bits
21282 #define G1RSIM14 COG1RSIM1bits.G1RSIM14 // bit 6, shadows bit in COG1RSIM1bits
21283 #define RSIM15 COG1RSIM1bits.RSIM15 // bit 7, shadows bit in COG1RSIM1bits
21284 #define G1RSIM15 COG1RSIM1bits.G1RSIM15 // bit 7, shadows bit in COG1RSIM1bits
21286 #define STRA COG1STRbits.STRA // bit 0, shadows bit in COG1STRbits
21287 #define G1STRA COG1STRbits.G1STRA // bit 0, shadows bit in COG1STRbits
21288 #define STRB COG1STRbits.STRB // bit 1, shadows bit in COG1STRbits
21289 #define G1STRB COG1STRbits.G1STRB // bit 1, shadows bit in COG1STRbits
21290 #define STRC COG1STRbits.STRC // bit 2, shadows bit in COG1STRbits
21291 #define G1STRC COG1STRbits.G1STRC // bit 2, shadows bit in COG1STRbits
21292 #define STRD COG1STRbits.STRD // bit 3, shadows bit in COG1STRbits
21293 #define G1STRD COG1STRbits.G1STRD // bit 3, shadows bit in COG1STRbits
21294 #define SDATA COG1STRbits.SDATA // bit 4, shadows bit in COG1STRbits
21295 #define G1SDATA COG1STRbits.G1SDATA // bit 4, shadows bit in COG1STRbits
21296 #define SDATB COG1STRbits.SDATB // bit 5, shadows bit in COG1STRbits
21297 #define G1SDATB COG1STRbits.G1SDATB // bit 5, shadows bit in COG1STRbits
21298 #define SDATC COG1STRbits.SDATC // bit 6, shadows bit in COG1STRbits
21299 #define G1SDATC COG1STRbits.G1SDATC // bit 6, shadows bit in COG1STRbits
21300 #define SDATD COG1STRbits.SDATD // bit 7, shadows bit in COG1STRbits
21301 #define G1SDATD COG1STRbits.G1SDATD // bit 7, shadows bit in COG1STRbits
21303 #define REF0 DAC1CON1bits.REF0 // bit 0, shadows bit in DAC1CON1bits
21304 #define DAC1REF0 DAC1CON1bits.DAC1REF0 // bit 0, shadows bit in DAC1CON1bits
21305 #define R0 DAC1CON1bits.R0 // bit 0, shadows bit in DAC1CON1bits
21306 #define DAC1R0 DAC1CON1bits.DAC1R0 // bit 0, shadows bit in DAC1CON1bits
21307 #define REF1 DAC1CON1bits.REF1 // bit 1, shadows bit in DAC1CON1bits
21308 #define DAC1REF1 DAC1CON1bits.DAC1REF1 // bit 1, shadows bit in DAC1CON1bits
21309 #define R1 DAC1CON1bits.R1 // bit 1, shadows bit in DAC1CON1bits
21310 #define DAC1R1 DAC1CON1bits.DAC1R1 // bit 1, shadows bit in DAC1CON1bits
21311 #define REF2 DAC1CON1bits.REF2 // bit 2, shadows bit in DAC1CON1bits
21312 #define DAC1REF2 DAC1CON1bits.DAC1REF2 // bit 2, shadows bit in DAC1CON1bits
21313 #define R2 DAC1CON1bits.R2 // bit 2, shadows bit in DAC1CON1bits
21314 #define DAC1R2 DAC1CON1bits.DAC1R2 // bit 2, shadows bit in DAC1CON1bits
21315 #define REF3 DAC1CON1bits.REF3 // bit 3, shadows bit in DAC1CON1bits
21316 #define DAC1REF3 DAC1CON1bits.DAC1REF3 // bit 3, shadows bit in DAC1CON1bits
21317 #define R3 DAC1CON1bits.R3 // bit 3, shadows bit in DAC1CON1bits
21318 #define DAC1R3 DAC1CON1bits.DAC1R3 // bit 3, shadows bit in DAC1CON1bits
21319 #define REF4 DAC1CON1bits.REF4 // bit 4, shadows bit in DAC1CON1bits
21320 #define DAC1REF4 DAC1CON1bits.DAC1REF4 // bit 4, shadows bit in DAC1CON1bits
21321 #define R4 DAC1CON1bits.R4 // bit 4, shadows bit in DAC1CON1bits
21322 #define DAC1R4 DAC1CON1bits.DAC1R4 // bit 4, shadows bit in DAC1CON1bits
21323 #define REF5 DAC1CON1bits.REF5 // bit 5, shadows bit in DAC1CON1bits
21324 #define DAC1REF5 DAC1CON1bits.DAC1REF5 // bit 5, shadows bit in DAC1CON1bits
21325 #define R5 DAC1CON1bits.R5 // bit 5, shadows bit in DAC1CON1bits
21326 #define DAC1R5 DAC1CON1bits.DAC1R5 // bit 5, shadows bit in DAC1CON1bits
21327 #define REF6 DAC1CON1bits.REF6 // bit 6, shadows bit in DAC1CON1bits
21328 #define DAC1REF6 DAC1CON1bits.DAC1REF6 // bit 6, shadows bit in DAC1CON1bits
21329 #define R6 DAC1CON1bits.R6 // bit 6, shadows bit in DAC1CON1bits
21330 #define DAC1R6 DAC1CON1bits.DAC1R6 // bit 6, shadows bit in DAC1CON1bits
21331 #define REF7 DAC1CON1bits.REF7 // bit 7, shadows bit in DAC1CON1bits
21332 #define DAC1REF7 DAC1CON1bits.DAC1REF7 // bit 7, shadows bit in DAC1CON1bits
21333 #define R7 DAC1CON1bits.R7 // bit 7, shadows bit in DAC1CON1bits
21334 #define DAC1R7 DAC1CON1bits.DAC1R7 // bit 7, shadows bit in DAC1CON1bits
21336 #define REF8 DAC1CON2bits.REF8 // bit 0, shadows bit in DAC1CON2bits
21337 #define DAC1REF8 DAC1CON2bits.DAC1REF8 // bit 0, shadows bit in DAC1CON2bits
21338 #define R8 DAC1CON2bits.R8 // bit 0, shadows bit in DAC1CON2bits
21339 #define DAC1R8 DAC1CON2bits.DAC1R8 // bit 0, shadows bit in DAC1CON2bits
21340 #define REF9 DAC1CON2bits.REF9 // bit 1, shadows bit in DAC1CON2bits
21341 #define DAC1REF9 DAC1CON2bits.DAC1REF9 // bit 1, shadows bit in DAC1CON2bits
21342 #define R9 DAC1CON2bits.R9 // bit 1, shadows bit in DAC1CON2bits
21343 #define DAC1R9 DAC1CON2bits.DAC1R9 // bit 1, shadows bit in DAC1CON2bits
21344 #define REF10 DAC1CON2bits.REF10 // bit 2, shadows bit in DAC1CON2bits
21345 #define DAC1REF10 DAC1CON2bits.DAC1REF10 // bit 2, shadows bit in DAC1CON2bits
21346 #define R10 DAC1CON2bits.R10 // bit 2, shadows bit in DAC1CON2bits
21347 #define DAC1R10 DAC1CON2bits.DAC1R10 // bit 2, shadows bit in DAC1CON2bits
21348 #define REF11 DAC1CON2bits.REF11 // bit 3, shadows bit in DAC1CON2bits
21349 #define DAC1REF11 DAC1CON2bits.DAC1REF11 // bit 3, shadows bit in DAC1CON2bits
21350 #define R11 DAC1CON2bits.R11 // bit 3, shadows bit in DAC1CON2bits
21351 #define DAC1R11 DAC1CON2bits.DAC1R11 // bit 3, shadows bit in DAC1CON2bits
21352 #define REF12 DAC1CON2bits.REF12 // bit 4, shadows bit in DAC1CON2bits
21353 #define DAC1REF12 DAC1CON2bits.DAC1REF12 // bit 4, shadows bit in DAC1CON2bits
21354 #define R12 DAC1CON2bits.R12 // bit 4, shadows bit in DAC1CON2bits
21355 #define DAC1R12 DAC1CON2bits.DAC1R12 // bit 4, shadows bit in DAC1CON2bits
21356 #define REF13 DAC1CON2bits.REF13 // bit 5, shadows bit in DAC1CON2bits
21357 #define DAC1REF13 DAC1CON2bits.DAC1REF13 // bit 5, shadows bit in DAC1CON2bits
21358 #define R13 DAC1CON2bits.R13 // bit 5, shadows bit in DAC1CON2bits
21359 #define DAC1R13 DAC1CON2bits.DAC1R13 // bit 5, shadows bit in DAC1CON2bits
21360 #define REF14 DAC1CON2bits.REF14 // bit 6, shadows bit in DAC1CON2bits
21361 #define DAC1REF14 DAC1CON2bits.DAC1REF14 // bit 6, shadows bit in DAC1CON2bits
21362 #define R14 DAC1CON2bits.R14 // bit 6, shadows bit in DAC1CON2bits
21363 #define DAC1R14 DAC1CON2bits.DAC1R14 // bit 6, shadows bit in DAC1CON2bits
21364 #define REF15 DAC1CON2bits.REF15 // bit 7, shadows bit in DAC1CON2bits
21365 #define DAC1REF15 DAC1CON2bits.DAC1REF15 // bit 7, shadows bit in DAC1CON2bits
21366 #define R15 DAC1CON2bits.R15 // bit 7, shadows bit in DAC1CON2bits
21367 #define DAC1R15 DAC1CON2bits.DAC1R15 // bit 7, shadows bit in DAC1CON2bits
21369 #define DAC1LD DACLDbits.DAC1LD // bit 0
21370 #define DAC2LD DACLDbits.DAC2LD // bit 1
21371 #define DAC5LD DACLDbits.DAC5LD // bit 4
21373 #define TSRNG FVRCONbits.TSRNG // bit 4
21374 #define TSEN FVRCONbits.TSEN // bit 5
21375 #define FVRRDY FVRCONbits.FVRRDY // bit 6
21376 #define FVREN FVRCONbits.FVREN // bit 7
21378 #define HIDB0 HIDRVBbits.HIDB0 // bit 0
21379 #define HIDB1 HIDRVBbits.HIDB1 // bit 1
21381 #define INLVE3 INLVEbits.INLVE3 // bit 3
21383 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
21384 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
21385 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
21386 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
21387 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
21388 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
21389 #define INLVA6 INLVLAbits.INLVA6 // bit 6
21390 #define INLVA7 INLVLAbits.INLVA7 // bit 7
21392 #define INLVB0 INLVLBbits.INLVB0 // bit 0
21393 #define INLVB1 INLVLBbits.INLVB1 // bit 1
21394 #define INLVB2 INLVLBbits.INLVB2 // bit 2
21395 #define INLVB3 INLVLBbits.INLVB3 // bit 3
21396 #define INLVLB4 INLVLBbits.INLVLB4 // bit 4
21397 #define INLVLB5 INLVLBbits.INLVLB5 // bit 5
21398 #define INLVLB6 INLVLBbits.INLVLB6 // bit 6
21399 #define INLVLB7 INLVLBbits.INLVLB7 // bit 7
21401 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
21402 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
21403 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
21404 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
21405 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
21406 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
21407 #define INLVLC6 INLVLCbits.INLVLC6 // bit 6
21408 #define INLVLC7 INLVLCbits.INLVLC7 // bit 7
21410 #define IOCIF INTCONbits.IOCIF // bit 0
21411 #define INTF INTCONbits.INTF // bit 1
21412 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
21413 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
21414 #define IOCIE INTCONbits.IOCIE // bit 3
21415 #define INTE INTCONbits.INTE // bit 4
21416 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
21417 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
21418 #define PEIE INTCONbits.PEIE // bit 6
21419 #define GIE INTCONbits.GIE // bit 7
21421 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
21422 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
21423 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
21424 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
21425 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
21426 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
21427 #define IOCAF6 IOCAFbits.IOCAF6 // bit 6
21428 #define IOCAF7 IOCAFbits.IOCAF7 // bit 7
21430 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
21431 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
21432 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
21433 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
21434 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
21435 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
21436 #define IOCAN6 IOCANbits.IOCAN6 // bit 6
21437 #define IOCAN7 IOCANbits.IOCAN7 // bit 7
21439 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
21440 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
21441 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
21442 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
21443 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
21444 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
21445 #define IOCAP6 IOCAPbits.IOCAP6 // bit 6
21446 #define IOCAP7 IOCAPbits.IOCAP7 // bit 7
21448 #define IOCBF0 IOCBFbits.IOCBF0 // bit 0
21449 #define IOCBF1 IOCBFbits.IOCBF1 // bit 1
21450 #define IOCBF2 IOCBFbits.IOCBF2 // bit 2
21451 #define IOCBF3 IOCBFbits.IOCBF3 // bit 3
21452 #define IOCBF4 IOCBFbits.IOCBF4 // bit 4
21453 #define IOCBF5 IOCBFbits.IOCBF5 // bit 5
21454 #define IOCBF6 IOCBFbits.IOCBF6 // bit 6
21455 #define IOCBF7 IOCBFbits.IOCBF7 // bit 7
21457 #define IOCBN0 IOCBNbits.IOCBN0 // bit 0
21458 #define IOCBN1 IOCBNbits.IOCBN1 // bit 1
21459 #define IOCBN2 IOCBNbits.IOCBN2 // bit 2
21460 #define IOCBN3 IOCBNbits.IOCBN3 // bit 3
21461 #define IOCBN4 IOCBNbits.IOCBN4 // bit 4
21462 #define IOCBN5 IOCBNbits.IOCBN5 // bit 5
21463 #define IOCBN6 IOCBNbits.IOCBN6 // bit 6
21464 #define IOCBN7 IOCBNbits.IOCBN7 // bit 7
21466 #define IOCBP0 IOCBPbits.IOCBP0 // bit 0
21467 #define IOCBP1 IOCBPbits.IOCBP1 // bit 1
21468 #define IOCBP2 IOCBPbits.IOCBP2 // bit 2
21469 #define IOCBP3 IOCBPbits.IOCBP3 // bit 3
21470 #define IOCBP4 IOCBPbits.IOCBP4 // bit 4
21471 #define IOCBP5 IOCBPbits.IOCBP5 // bit 5
21472 #define IOCBP6 IOCBPbits.IOCBP6 // bit 6
21473 #define IOCBP7 IOCBPbits.IOCBP7 // bit 7
21475 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
21476 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
21477 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
21478 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
21479 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
21480 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
21481 #define IOCCF6 IOCCFbits.IOCCF6 // bit 6
21482 #define IOCCF7 IOCCFbits.IOCCF7 // bit 7
21484 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
21485 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
21486 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
21487 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
21488 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
21489 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
21490 #define IOCCN6 IOCCNbits.IOCCN6 // bit 6
21491 #define IOCCN7 IOCCNbits.IOCCN7 // bit 7
21493 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
21494 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
21495 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
21496 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
21497 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
21498 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
21499 #define IOCCP6 IOCCPbits.IOCCP6 // bit 6
21500 #define IOCCP7 IOCCPbits.IOCCP7 // bit 7
21502 #define IOCEF3 IOCEFbits.IOCEF3 // bit 3
21504 #define IOCEN3 IOCENbits.IOCEN3 // bit 3
21506 #define IOCEP3 IOCEPbits.IOCEP3 // bit 3
21508 #define LATA0 LATAbits.LATA0 // bit 0
21509 #define LATA1 LATAbits.LATA1 // bit 1
21510 #define LATA2 LATAbits.LATA2 // bit 2
21511 #define LATA3 LATAbits.LATA3 // bit 3
21512 #define LATA4 LATAbits.LATA4 // bit 4
21513 #define LATA5 LATAbits.LATA5 // bit 5
21514 #define LATA6 LATAbits.LATA6 // bit 6
21515 #define LATA7 LATAbits.LATA7 // bit 7
21517 #define LATB0 LATBbits.LATB0 // bit 0
21518 #define LATB1 LATBbits.LATB1 // bit 1
21519 #define LATB2 LATBbits.LATB2 // bit 2
21520 #define LATB3 LATBbits.LATB3 // bit 3
21521 #define LATB4 LATBbits.LATB4 // bit 4
21522 #define LATB5 LATBbits.LATB5 // bit 5
21523 #define LATB6 LATBbits.LATB6 // bit 6
21524 #define LATB7 LATBbits.LATB7 // bit 7
21526 #define LATC0 LATCbits.LATC0 // bit 0
21527 #define LATC1 LATCbits.LATC1 // bit 1
21528 #define LATC2 LATCbits.LATC2 // bit 2
21529 #define LATC3 LATCbits.LATC3 // bit 3
21530 #define LATC4 LATCbits.LATC4 // bit 4
21531 #define LATC5 LATCbits.LATC5 // bit 5
21532 #define LATC6 LATCbits.LATC6 // bit 6
21533 #define LATC7 LATCbits.LATC7 // bit 7
21535 #define CH0 MD1CARHbits.CH0 // bit 0, shadows bit in MD1CARHbits
21536 #define MD1CH0 MD1CARHbits.MD1CH0 // bit 0, shadows bit in MD1CARHbits
21537 #define CH1 MD1CARHbits.CH1 // bit 1, shadows bit in MD1CARHbits
21538 #define MD1CH1 MD1CARHbits.MD1CH1 // bit 1, shadows bit in MD1CARHbits
21539 #define CH2 MD1CARHbits.CH2 // bit 2, shadows bit in MD1CARHbits
21540 #define MD1CH2 MD1CARHbits.MD1CH2 // bit 2, shadows bit in MD1CARHbits
21541 #define CH3 MD1CARHbits.CH3 // bit 3, shadows bit in MD1CARHbits
21542 #define MD1CH3 MD1CARHbits.MD1CH3 // bit 3, shadows bit in MD1CARHbits
21543 #define CH4 MD1CARHbits.CH4 // bit 4
21545 #define CL0 MD1CARLbits.CL0 // bit 0, shadows bit in MD1CARLbits
21546 #define MD1CL0 MD1CARLbits.MD1CL0 // bit 0, shadows bit in MD1CARLbits
21547 #define CL1 MD1CARLbits.CL1 // bit 1, shadows bit in MD1CARLbits
21548 #define MD1CL1 MD1CARLbits.MD1CL1 // bit 1, shadows bit in MD1CARLbits
21549 #define CL2 MD1CARLbits.CL2 // bit 2, shadows bit in MD1CARLbits
21550 #define MD1CL2 MD1CARLbits.MD1CL2 // bit 2, shadows bit in MD1CARLbits
21551 #define CL3 MD1CARLbits.CL3 // bit 3, shadows bit in MD1CARLbits
21552 #define MD1CL3 MD1CARLbits.MD1CL3 // bit 3, shadows bit in MD1CARLbits
21553 #define CL4 MD1CARLbits.CL4 // bit 4
21555 #define CLSYNC MD1CON1bits.CLSYNC // bit 0, shadows bit in MD1CON1bits
21556 #define MD1CLSYNC MD1CON1bits.MD1CLSYNC // bit 0, shadows bit in MD1CON1bits
21557 #define CLPOL MD1CON1bits.CLPOL // bit 1, shadows bit in MD1CON1bits
21558 #define MD1CLPOL MD1CON1bits.MD1CLPOL // bit 1, shadows bit in MD1CON1bits
21559 #define CHSYNC MD1CON1bits.CHSYNC // bit 4, shadows bit in MD1CON1bits
21560 #define MD1CHSYNC MD1CON1bits.MD1CHSYNC // bit 4, shadows bit in MD1CON1bits
21561 #define CHPOL MD1CON1bits.CHPOL // bit 5, shadows bit in MD1CON1bits
21562 #define MD1CHPOL MD1CON1bits.MD1CHPOL // bit 5, shadows bit in MD1CON1bits
21564 #define MS0 MD1SRCbits.MS0 // bit 0, shadows bit in MD1SRCbits
21565 #define MD1MS0 MD1SRCbits.MD1MS0 // bit 0, shadows bit in MD1SRCbits
21566 #define MS1 MD1SRCbits.MS1 // bit 1, shadows bit in MD1SRCbits
21567 #define MD1MS1 MD1SRCbits.MD1MS1 // bit 1, shadows bit in MD1SRCbits
21568 #define MS2 MD1SRCbits.MS2 // bit 2, shadows bit in MD1SRCbits
21569 #define MD1MS2 MD1SRCbits.MD1MS2 // bit 2, shadows bit in MD1SRCbits
21570 #define MS3 MD1SRCbits.MS3 // bit 3, shadows bit in MD1SRCbits
21571 #define MD1MS3 MD1SRCbits.MD1MS3 // bit 3, shadows bit in MD1SRCbits
21572 #define MS4 MD1SRCbits.MS4 // bit 4, shadows bit in MD1SRCbits
21573 #define MD1MS4 MD1SRCbits.MD1MS4 // bit 4, shadows bit in MD1SRCbits
21575 #define ODA0 ODCONAbits.ODA0 // bit 0
21576 #define ODA1 ODCONAbits.ODA1 // bit 1
21577 #define ODA2 ODCONAbits.ODA2 // bit 2
21578 #define ODA3 ODCONAbits.ODA3 // bit 3
21579 #define ODA4 ODCONAbits.ODA4 // bit 4
21580 #define ODA5 ODCONAbits.ODA5 // bit 5
21581 #define ODA6 ODCONAbits.ODA6 // bit 6
21582 #define ODA7 ODCONAbits.ODA7 // bit 7
21584 #define ODC0 ODCONCbits.ODC0 // bit 0
21585 #define ODC1 ODCONCbits.ODC1 // bit 1
21586 #define ODC2 ODCONCbits.ODC2 // bit 2
21587 #define ODC3 ODCONCbits.ODC3 // bit 3
21588 #define ODC4 ODCONCbits.ODC4 // bit 4
21589 #define ODC5 ODCONCbits.ODC5 // bit 5
21590 #define ODC6 ODCONCbits.ODC6 // bit 6
21591 #define ODC7 ODCONCbits.ODC7 // bit 7
21593 #define PS0 OPTION_REGbits.PS0 // bit 0
21594 #define PS1 OPTION_REGbits.PS1 // bit 1
21595 #define PS2 OPTION_REGbits.PS2 // bit 2
21596 #define PSA OPTION_REGbits.PSA // bit 3
21597 #define TMR0SE OPTION_REGbits.TMR0SE // bit 4, shadows bit in OPTION_REGbits
21598 #define T0SE OPTION_REGbits.T0SE // bit 4, shadows bit in OPTION_REGbits
21599 #define TMR0CS OPTION_REGbits.TMR0CS // bit 5, shadows bit in OPTION_REGbits
21600 #define T0CS OPTION_REGbits.T0CS // bit 5, shadows bit in OPTION_REGbits
21601 #define INTEDG OPTION_REGbits.INTEDG // bit 6
21602 #define NOT_WPUEN OPTION_REGbits.NOT_WPUEN // bit 7
21604 #define SCS0 OSCCONbits.SCS0 // bit 0
21605 #define SCS1 OSCCONbits.SCS1 // bit 1
21606 #define IRCF0 OSCCONbits.IRCF0 // bit 3
21607 #define IRCF1 OSCCONbits.IRCF1 // bit 4
21608 #define IRCF2 OSCCONbits.IRCF2 // bit 5
21609 #define IRCF3 OSCCONbits.IRCF3 // bit 6
21610 #define SPLLEN OSCCONbits.SPLLEN // bit 7
21612 #define HFIOFS OSCSTATbits.HFIOFS // bit 0
21613 #define LFIOFR OSCSTATbits.LFIOFR // bit 1
21614 #define MFIOFR OSCSTATbits.MFIOFR // bit 2
21615 #define HFIOFL OSCSTATbits.HFIOFL // bit 3
21616 #define HFIOFR OSCSTATbits.HFIOFR // bit 4
21617 #define OSTS OSCSTATbits.OSTS // bit 5
21618 #define PLLR OSCSTATbits.PLLR // bit 6
21619 #define SOSCR OSCSTATbits.SOSCR // bit 7
21621 #define TUN0 OSCTUNEbits.TUN0 // bit 0
21622 #define TUN1 OSCTUNEbits.TUN1 // bit 1
21623 #define TUN2 OSCTUNEbits.TUN2 // bit 2
21624 #define TUN3 OSCTUNEbits.TUN3 // bit 3
21625 #define TUN4 OSCTUNEbits.TUN4 // bit 4
21626 #define TUN5 OSCTUNEbits.TUN5 // bit 5
21628 #define NOT_BOR PCONbits.NOT_BOR // bit 0
21629 #define NOT_POR PCONbits.NOT_POR // bit 1
21630 #define NOT_RI PCONbits.NOT_RI // bit 2
21631 #define NOT_RMCLR PCONbits.NOT_RMCLR // bit 3
21632 #define NOT_RWDT PCONbits.NOT_RWDT // bit 4
21633 #define STKUNF PCONbits.STKUNF // bit 6
21634 #define STKOVF PCONbits.STKOVF // bit 7
21636 #define TMR1IE PIE1bits.TMR1IE // bit 0
21637 #define TMR2IE PIE1bits.TMR2IE // bit 1
21638 #define CCP1IE PIE1bits.CCP1IE // bit 2, shadows bit in PIE1bits
21639 #define CCPIE PIE1bits.CCPIE // bit 2, shadows bit in PIE1bits
21640 #define SSP1IE PIE1bits.SSP1IE // bit 3
21641 #define TXIE PIE1bits.TXIE // bit 4
21642 #define RCIE PIE1bits.RCIE // bit 5
21643 #define ADIE PIE1bits.ADIE // bit 6
21644 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
21646 #define CCP2IE PIE2bits.CCP2IE // bit 0
21647 #define C3IE PIE2bits.C3IE // bit 1
21648 #define C4IE PIE2bits.C4IE // bit 2
21649 #define BCL1IE PIE2bits.BCL1IE // bit 3
21650 #define COGIE PIE2bits.COGIE // bit 4
21651 #define C1IE PIE2bits.C1IE // bit 5
21652 #define C2IE PIE2bits.C2IE // bit 6
21653 #define OSFIE PIE2bits.OSFIE // bit 7
21655 #define CLC1IE PIE3bits.CLC1IE // bit 0
21656 #define CLC2IE PIE3bits.CLC2IE // bit 1
21657 #define CLC3IE PIE3bits.CLC3IE // bit 2
21658 #define CLC4IE PIE3bits.CLC4IE // bit 3
21659 #define ZCDIE PIE3bits.ZCDIE // bit 4
21660 #define COG2IE PIE3bits.COG2IE // bit 5
21662 #define TMR4IE PIE4bits.TMR4IE // bit 0
21663 #define TMR6IE PIE4bits.TMR6IE // bit 1
21664 #define TMR3IE PIE4bits.TMR3IE // bit 2
21665 #define TMR3GIE PIE4bits.TMR3GIE // bit 3
21666 #define TMR5IE PIE4bits.TMR5IE // bit 4
21667 #define TMR5GIE PIE4bits.TMR5GIE // bit 5
21668 #define TMR8IE PIE4bits.TMR8IE // bit 6
21670 #define C5IE PIE5bits.C5IE // bit 0
21671 #define C6IE PIE5bits.C6IE // bit 1
21672 #define COG3IE PIE5bits.COG3IE // bit 4
21673 #define CCP7IE PIE5bits.CCP7IE // bit 6
21675 #define PWM5IE PIE6bits.PWM5IE // bit 0
21676 #define PWM6IE PIE6bits.PWM6IE // bit 1
21677 #define PWM11IE PIE6bits.PWM11IE // bit 2
21679 #define TMR1IF PIR1bits.TMR1IF // bit 0
21680 #define TMR2IF PIR1bits.TMR2IF // bit 1
21681 #define CCP1IF PIR1bits.CCP1IF // bit 2, shadows bit in PIR1bits
21682 #define CCPIF PIR1bits.CCPIF // bit 2, shadows bit in PIR1bits
21683 #define SSP1IF PIR1bits.SSP1IF // bit 3
21684 #define TXIF PIR1bits.TXIF // bit 4
21685 #define RCIF PIR1bits.RCIF // bit 5
21686 #define ADIF PIR1bits.ADIF // bit 6
21687 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
21689 #define CCP2IF PIR2bits.CCP2IF // bit 0
21690 #define C3IF PIR2bits.C3IF // bit 1
21691 #define C4IF PIR2bits.C4IF // bit 2
21692 #define BCL1IF PIR2bits.BCL1IF // bit 3
21693 #define COG1IF PIR2bits.COG1IF // bit 4
21694 #define C1IF PIR2bits.C1IF // bit 5
21695 #define C2IF PIR2bits.C2IF // bit 6
21696 #define OSFIF PIR2bits.OSFIF // bit 7
21698 #define CLC1IF PIR3bits.CLC1IF // bit 0
21699 #define CLC2IF PIR3bits.CLC2IF // bit 1
21700 #define CLC3IF PIR3bits.CLC3IF // bit 2
21701 #define CLC4IF PIR3bits.CLC4IF // bit 3
21702 #define ZCDIF PIR3bits.ZCDIF // bit 4
21703 #define COG2IF PIR3bits.COG2IF // bit 5
21705 #define TMR4IF PIR4bits.TMR4IF // bit 0
21706 #define TMR6IF PIR4bits.TMR6IF // bit 1
21707 #define TMR3IF PIR4bits.TMR3IF // bit 2
21708 #define TMR3GIF PIR4bits.TMR3GIF // bit 3
21709 #define TMR5IF PIR4bits.TMR5IF // bit 4
21710 #define TMR5GIF PIR4bits.TMR5GIF // bit 5
21711 #define TMR8IF PIR4bits.TMR8IF // bit 6
21713 #define C5IF PIR5bits.C5IF // bit 0
21714 #define C6IF PIR5bits.C6IF // bit 1
21715 #define COG3IF PIR5bits.COG3IF // bit 4
21716 #define CCP7IF PIR5bits.CCP7IF // bit 6
21718 #define PWM5IF PIR6bits.PWM5IF // bit 0
21719 #define PWM6IF PIR6bits.PWM6IF // bit 1
21720 #define PWM11IF PIR6bits.PWM11IF // bit 2
21722 #define RD PMCON1bits.RD // bit 0
21723 #define WR PMCON1bits.WR // bit 1
21724 #define WREN PMCON1bits.WREN // bit 2
21725 #define WRERR PMCON1bits.WRERR // bit 3
21726 #define FREE PMCON1bits.FREE // bit 4
21727 #define LWLO PMCON1bits.LWLO // bit 5
21728 #define CFGS PMCON1bits.CFGS // bit 6
21730 #define RA0 PORTAbits.RA0 // bit 0
21731 #define RA1 PORTAbits.RA1 // bit 1
21732 #define RA2 PORTAbits.RA2 // bit 2
21733 #define RA3 PORTAbits.RA3 // bit 3
21734 #define RA4 PORTAbits.RA4 // bit 4
21735 #define RA5 PORTAbits.RA5 // bit 5
21736 #define RA6 PORTAbits.RA6 // bit 6
21737 #define RA7 PORTAbits.RA7 // bit 7
21739 #define RB0 PORTBbits.RB0 // bit 0
21740 #define RB1 PORTBbits.RB1 // bit 1
21741 #define RB2 PORTBbits.RB2 // bit 2
21742 #define RB3 PORTBbits.RB3 // bit 3
21743 #define RB4 PORTBbits.RB4 // bit 4
21744 #define RB5 PORTBbits.RB5 // bit 5
21745 #define RB6 PORTBbits.RB6 // bit 6
21746 #define RB7 PORTBbits.RB7 // bit 7
21748 #define RC0 PORTCbits.RC0 // bit 0
21749 #define RC1 PORTCbits.RC1 // bit 1
21750 #define RC2 PORTCbits.RC2 // bit 2
21751 #define RC3 PORTCbits.RC3 // bit 3
21752 #define RC4 PORTCbits.RC4 // bit 4
21753 #define RC5 PORTCbits.RC5 // bit 5
21754 #define RC6 PORTCbits.RC6 // bit 6
21755 #define RC7 PORTCbits.RC7 // bit 7
21757 #define RE3 PORTEbits.RE3 // bit 3
21759 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
21761 #define RPOL PRG1CON1bits.RPOL // bit 0, shadows bit in PRG1CON1bits
21762 #define RG1RPOL PRG1CON1bits.RG1RPOL // bit 0, shadows bit in PRG1CON1bits
21763 #define FPOL PRG1CON1bits.FPOL // bit 1, shadows bit in PRG1CON1bits
21764 #define RG1FPOL PRG1CON1bits.RG1FPOL // bit 1, shadows bit in PRG1CON1bits
21765 #define RDY PRG1CON1bits.RDY // bit 2, shadows bit in PRG1CON1bits
21766 #define RG1RDY PRG1CON1bits.RG1RDY // bit 2, shadows bit in PRG1CON1bits
21768 #define ISET0 PRG1CON2bits.ISET0 // bit 0, shadows bit in PRG1CON2bits
21769 #define RG1ISET0 PRG1CON2bits.RG1ISET0 // bit 0, shadows bit in PRG1CON2bits
21770 #define ISET1 PRG1CON2bits.ISET1 // bit 1, shadows bit in PRG1CON2bits
21771 #define RG1ISET1 PRG1CON2bits.RG1ISET1 // bit 1, shadows bit in PRG1CON2bits
21772 #define ISET2 PRG1CON2bits.ISET2 // bit 2, shadows bit in PRG1CON2bits
21773 #define RG1ISET2 PRG1CON2bits.RG1ISET2 // bit 2, shadows bit in PRG1CON2bits
21774 #define ISET3 PRG1CON2bits.ISET3 // bit 3, shadows bit in PRG1CON2bits
21775 #define RG1ISET3 PRG1CON2bits.RG1ISET3 // bit 3, shadows bit in PRG1CON2bits
21776 #define ISET4 PRG1CON2bits.ISET4 // bit 4, shadows bit in PRG1CON2bits
21777 #define RG1ISET4 PRG1CON2bits.RG1ISET4 // bit 4, shadows bit in PRG1CON2bits
21779 #define FTSS0 PRG1FTSSbits.FTSS0 // bit 0, shadows bit in PRG1FTSSbits
21780 #define RG1FTSS0 PRG1FTSSbits.RG1FTSS0 // bit 0, shadows bit in PRG1FTSSbits
21781 #define FTSS1 PRG1FTSSbits.FTSS1 // bit 1, shadows bit in PRG1FTSSbits
21782 #define RG1FTSS1 PRG1FTSSbits.RG1FTSS1 // bit 1, shadows bit in PRG1FTSSbits
21783 #define FTSS2 PRG1FTSSbits.FTSS2 // bit 2, shadows bit in PRG1FTSSbits
21784 #define RG1FTSS2 PRG1FTSSbits.RG1FTSS2 // bit 2, shadows bit in PRG1FTSSbits
21785 #define FTSS3 PRG1FTSSbits.FTSS3 // bit 3, shadows bit in PRG1FTSSbits
21786 #define RG1FTSS3 PRG1FTSSbits.RG1FTSS3 // bit 3, shadows bit in PRG1FTSSbits
21788 #define INS0 PRG1INSbits.INS0 // bit 0, shadows bit in PRG1INSbits
21789 #define RG1INS0 PRG1INSbits.RG1INS0 // bit 0, shadows bit in PRG1INSbits
21790 #define INS1 PRG1INSbits.INS1 // bit 1, shadows bit in PRG1INSbits
21791 #define RG1INS1 PRG1INSbits.RG1INS1 // bit 1, shadows bit in PRG1INSbits
21792 #define INS2 PRG1INSbits.INS2 // bit 2, shadows bit in PRG1INSbits
21793 #define RG1INS2 PRG1INSbits.RG1INS2 // bit 2, shadows bit in PRG1INSbits
21794 #define INS3 PRG1INSbits.INS3 // bit 3, shadows bit in PRG1INSbits
21795 #define RG1INS3 PRG1INSbits.RG1INS3 // bit 3, shadows bit in PRG1INSbits
21797 #define RTSS0 PRG1RTSSbits.RTSS0 // bit 0, shadows bit in PRG1RTSSbits
21798 #define RG1RTSS0 PRG1RTSSbits.RG1RTSS0 // bit 0, shadows bit in PRG1RTSSbits
21799 #define RTSS1 PRG1RTSSbits.RTSS1 // bit 1, shadows bit in PRG1RTSSbits
21800 #define RG1RTSS1 PRG1RTSSbits.RG1RTSS1 // bit 1, shadows bit in PRG1RTSSbits
21801 #define RTSS2 PRG1RTSSbits.RTSS2 // bit 2, shadows bit in PRG1RTSSbits
21802 #define RG1RTSS2 PRG1RTSSbits.RG1RTSS2 // bit 2, shadows bit in PRG1RTSSbits
21803 #define RTSS3 PRG1RTSSbits.RTSS3 // bit 3, shadows bit in PRG1RTSSbits
21804 #define RG1RTSS3 PRG1RTSSbits.RG1RTSS3 // bit 3, shadows bit in PRG1RTSSbits
21806 #define DC2 PWM3DCHbits.DC2 // bit 0, shadows bit in PWM3DCHbits
21807 #define PWM3DC2 PWM3DCHbits.PWM3DC2 // bit 0, shadows bit in PWM3DCHbits
21808 #define PWMPW2 PWM3DCHbits.PWMPW2 // bit 0, shadows bit in PWM3DCHbits
21809 #define DC3 PWM3DCHbits.DC3 // bit 1, shadows bit in PWM3DCHbits
21810 #define PWM3DC3 PWM3DCHbits.PWM3DC3 // bit 1, shadows bit in PWM3DCHbits
21811 #define PWMPW3 PWM3DCHbits.PWMPW3 // bit 1, shadows bit in PWM3DCHbits
21812 #define DC4 PWM3DCHbits.DC4 // bit 2, shadows bit in PWM3DCHbits
21813 #define PWM3DC4 PWM3DCHbits.PWM3DC4 // bit 2, shadows bit in PWM3DCHbits
21814 #define PWMPW4 PWM3DCHbits.PWMPW4 // bit 2, shadows bit in PWM3DCHbits
21815 #define DC5 PWM3DCHbits.DC5 // bit 3, shadows bit in PWM3DCHbits
21816 #define PWM3DC5 PWM3DCHbits.PWM3DC5 // bit 3, shadows bit in PWM3DCHbits
21817 #define PWMPW5 PWM3DCHbits.PWMPW5 // bit 3, shadows bit in PWM3DCHbits
21818 #define DC6 PWM3DCHbits.DC6 // bit 4, shadows bit in PWM3DCHbits
21819 #define PWM3DC6 PWM3DCHbits.PWM3DC6 // bit 4, shadows bit in PWM3DCHbits
21820 #define PWMPW6 PWM3DCHbits.PWMPW6 // bit 4, shadows bit in PWM3DCHbits
21821 #define DC7 PWM3DCHbits.DC7 // bit 5, shadows bit in PWM3DCHbits
21822 #define PWM3DC7 PWM3DCHbits.PWM3DC7 // bit 5, shadows bit in PWM3DCHbits
21823 #define PWMPW7 PWM3DCHbits.PWMPW7 // bit 5, shadows bit in PWM3DCHbits
21824 #define DC8 PWM3DCHbits.DC8 // bit 6, shadows bit in PWM3DCHbits
21825 #define PWM3DC8 PWM3DCHbits.PWM3DC8 // bit 6, shadows bit in PWM3DCHbits
21826 #define PWMPW8 PWM3DCHbits.PWMPW8 // bit 6, shadows bit in PWM3DCHbits
21827 #define DC9 PWM3DCHbits.DC9 // bit 7, shadows bit in PWM3DCHbits
21828 #define PWM3DC9 PWM3DCHbits.PWM3DC9 // bit 7, shadows bit in PWM3DCHbits
21829 #define PWMPW9 PWM3DCHbits.PWMPW9 // bit 7, shadows bit in PWM3DCHbits
21831 #define DC0 PWM3DCLbits.DC0 // bit 6, shadows bit in PWM3DCLbits
21832 #define PWM3DC0 PWM3DCLbits.PWM3DC0 // bit 6, shadows bit in PWM3DCLbits
21833 #define PWMPW0 PWM3DCLbits.PWMPW0 // bit 6, shadows bit in PWM3DCLbits
21834 #define DC1 PWM3DCLbits.DC1 // bit 7, shadows bit in PWM3DCLbits
21835 #define PWM3DC1 PWM3DCLbits.PWM3DC1 // bit 7, shadows bit in PWM3DCLbits
21836 #define PWMPW1 PWM3DCLbits.PWMPW1 // bit 7, shadows bit in PWM3DCLbits
21838 #define PWM5DCH0 PWM5DCHbits.PWM5DCH0 // bit 0
21839 #define PWM5DCH1 PWM5DCHbits.PWM5DCH1 // bit 1
21840 #define PWM5DCH2 PWM5DCHbits.PWM5DCH2 // bit 2
21841 #define PWM5DCH3 PWM5DCHbits.PWM5DCH3 // bit 3
21842 #define PWM5DCH4 PWM5DCHbits.PWM5DCH4 // bit 4
21843 #define PWM5DCH5 PWM5DCHbits.PWM5DCH5 // bit 5
21844 #define PWM5DCH6 PWM5DCHbits.PWM5DCH6 // bit 6
21845 #define PWM5DCH7 PWM5DCHbits.PWM5DCH7 // bit 7
21847 #define PWM5DCL0 PWM5DCLbits.PWM5DCL0 // bit 0
21848 #define PWM5DCL1 PWM5DCLbits.PWM5DCL1 // bit 1
21849 #define PWM5DCL2 PWM5DCLbits.PWM5DCL2 // bit 2
21850 #define PWM5DCL3 PWM5DCLbits.PWM5DCL3 // bit 3
21851 #define PWM5DCL4 PWM5DCLbits.PWM5DCL4 // bit 4
21852 #define PWM5DCL5 PWM5DCLbits.PWM5DCL5 // bit 5
21853 #define PWM5DCL6 PWM5DCLbits.PWM5DCL6 // bit 6
21854 #define PWM5DCL7 PWM5DCLbits.PWM5DCL7 // bit 7
21856 #define PRIE PWM5INTCONbits.PRIE // bit 0, shadows bit in PWM5INTCONbits
21857 #define PWM5PRIE PWM5INTCONbits.PWM5PRIE // bit 0, shadows bit in PWM5INTCONbits
21858 #define DCIE PWM5INTCONbits.DCIE // bit 1, shadows bit in PWM5INTCONbits
21859 #define PWM5DCIE PWM5INTCONbits.PWM5DCIE // bit 1, shadows bit in PWM5INTCONbits
21860 #define PHIE PWM5INTCONbits.PHIE // bit 2, shadows bit in PWM5INTCONbits
21861 #define PWM5PHIE PWM5INTCONbits.PWM5PHIE // bit 2, shadows bit in PWM5INTCONbits
21862 #define OFIE PWM5INTCONbits.OFIE // bit 3, shadows bit in PWM5INTCONbits
21863 #define PWM5OFIE PWM5INTCONbits.PWM5OFIE // bit 3, shadows bit in PWM5INTCONbits
21865 #define PRIF PWM5INTFbits.PRIF // bit 0, shadows bit in PWM5INTFbits
21866 #define PWM5PRIF PWM5INTFbits.PWM5PRIF // bit 0, shadows bit in PWM5INTFbits
21867 #define DCIF PWM5INTFbits.DCIF // bit 1, shadows bit in PWM5INTFbits
21868 #define PWM5DCIF PWM5INTFbits.PWM5DCIF // bit 1, shadows bit in PWM5INTFbits
21869 #define PHIF PWM5INTFbits.PHIF // bit 2, shadows bit in PWM5INTFbits
21870 #define PWM5PHIF PWM5INTFbits.PWM5PHIF // bit 2, shadows bit in PWM5INTFbits
21871 #define OFIF PWM5INTFbits.OFIF // bit 3, shadows bit in PWM5INTFbits
21872 #define PWM5OFIF PWM5INTFbits.PWM5OFIF // bit 3, shadows bit in PWM5INTFbits
21874 #define PWM5LDS0 PWM5LDCONbits.PWM5LDS0 // bit 0, shadows bit in PWM5LDCONbits
21875 #define LDS0 PWM5LDCONbits.LDS0 // bit 0, shadows bit in PWM5LDCONbits
21876 #define PWM5LDS1 PWM5LDCONbits.PWM5LDS1 // bit 1, shadows bit in PWM5LDCONbits
21877 #define LDS1 PWM5LDCONbits.LDS1 // bit 1, shadows bit in PWM5LDCONbits
21878 #define LDT PWM5LDCONbits.LDT // bit 6, shadows bit in PWM5LDCONbits
21879 #define PWM5LDM PWM5LDCONbits.PWM5LDM // bit 6, shadows bit in PWM5LDCONbits
21880 #define LDA PWM5LDCONbits.LDA // bit 7, shadows bit in PWM5LDCONbits
21881 #define PWM5LD PWM5LDCONbits.PWM5LD // bit 7, shadows bit in PWM5LDCONbits
21883 #define PWM5OFS0 PWM5OFCONbits.PWM5OFS0 // bit 0, shadows bit in PWM5OFCONbits
21884 #define OFS0 PWM5OFCONbits.OFS0 // bit 0, shadows bit in PWM5OFCONbits
21885 #define PWM5OFS1 PWM5OFCONbits.PWM5OFS1 // bit 1, shadows bit in PWM5OFCONbits
21886 #define OFS1 PWM5OFCONbits.OFS1 // bit 1, shadows bit in PWM5OFCONbits
21887 #define OFO PWM5OFCONbits.OFO // bit 4, shadows bit in PWM5OFCONbits
21888 #define PWM5OFMC PWM5OFCONbits.PWM5OFMC // bit 4, shadows bit in PWM5OFCONbits
21889 #define PWM5OFM0 PWM5OFCONbits.PWM5OFM0 // bit 5, shadows bit in PWM5OFCONbits
21890 #define OFM0 PWM5OFCONbits.OFM0 // bit 5, shadows bit in PWM5OFCONbits
21891 #define PWM5OFM1 PWM5OFCONbits.PWM5OFM1 // bit 6, shadows bit in PWM5OFCONbits
21892 #define OFM1 PWM5OFCONbits.OFM1 // bit 6, shadows bit in PWM5OFCONbits
21894 #define PWM5OFH0 PWM5OFHbits.PWM5OFH0 // bit 0
21895 #define PWM5OFH1 PWM5OFHbits.PWM5OFH1 // bit 1
21896 #define PWM5OFH2 PWM5OFHbits.PWM5OFH2 // bit 2
21897 #define PWM5OFH3 PWM5OFHbits.PWM5OFH3 // bit 3
21898 #define PWM5OFH4 PWM5OFHbits.PWM5OFH4 // bit 4
21899 #define PWM5OFH5 PWM5OFHbits.PWM5OFH5 // bit 5
21900 #define PWM5OFH6 PWM5OFHbits.PWM5OFH6 // bit 6
21901 #define PWM5OFH7 PWM5OFHbits.PWM5OFH7 // bit 7
21903 #define PWM5OFL0 PWM5OFLbits.PWM5OFL0 // bit 0
21904 #define PWM5OFL1 PWM5OFLbits.PWM5OFL1 // bit 1
21905 #define PWM5OFL2 PWM5OFLbits.PWM5OFL2 // bit 2
21906 #define PWM5OFL3 PWM5OFLbits.PWM5OFL3 // bit 3
21907 #define PWM5OFL4 PWM5OFLbits.PWM5OFL4 // bit 4
21908 #define PWM5OFL5 PWM5OFLbits.PWM5OFL5 // bit 5
21909 #define PWM5OFL6 PWM5OFLbits.PWM5OFL6 // bit 6
21910 #define PWM5OFL7 PWM5OFLbits.PWM5OFL7 // bit 7
21912 #define PWM5PHH0 PWM5PHHbits.PWM5PHH0 // bit 0
21913 #define PWM5PHH1 PWM5PHHbits.PWM5PHH1 // bit 1
21914 #define PWM5PHH2 PWM5PHHbits.PWM5PHH2 // bit 2
21915 #define PWM5PHH3 PWM5PHHbits.PWM5PHH3 // bit 3
21916 #define PWM5PHH4 PWM5PHHbits.PWM5PHH4 // bit 4
21917 #define PWM5PHH5 PWM5PHHbits.PWM5PHH5 // bit 5
21918 #define PWM5PHH6 PWM5PHHbits.PWM5PHH6 // bit 6
21919 #define PWM5PHH7 PWM5PHHbits.PWM5PHH7 // bit 7
21921 #define PWM5PHL0 PWM5PHLbits.PWM5PHL0 // bit 0
21922 #define PWM5PHL1 PWM5PHLbits.PWM5PHL1 // bit 1
21923 #define PWM5PHL2 PWM5PHLbits.PWM5PHL2 // bit 2
21924 #define PWM5PHL3 PWM5PHLbits.PWM5PHL3 // bit 3
21925 #define PWM5PHL4 PWM5PHLbits.PWM5PHL4 // bit 4
21926 #define PWM5PHL5 PWM5PHLbits.PWM5PHL5 // bit 5
21927 #define PWM5PHL6 PWM5PHLbits.PWM5PHL6 // bit 6
21928 #define PWM5PHL7 PWM5PHLbits.PWM5PHL7 // bit 7
21930 #define PWM5PRH0 PWM5PRHbits.PWM5PRH0 // bit 0
21931 #define PWM5PRH1 PWM5PRHbits.PWM5PRH1 // bit 1
21932 #define PWM5PRH2 PWM5PRHbits.PWM5PRH2 // bit 2
21933 #define PWM5PRH3 PWM5PRHbits.PWM5PRH3 // bit 3
21934 #define PWM5PRH4 PWM5PRHbits.PWM5PRH4 // bit 4
21935 #define PWM5PRH5 PWM5PRHbits.PWM5PRH5 // bit 5
21936 #define PWM5PRH6 PWM5PRHbits.PWM5PRH6 // bit 6
21937 #define PWM5PRH7 PWM5PRHbits.PWM5PRH7 // bit 7
21939 #define PWM5PRL0 PWM5PRLbits.PWM5PRL0 // bit 0
21940 #define PWM5PRL1 PWM5PRLbits.PWM5PRL1 // bit 1
21941 #define PWM5PRL2 PWM5PRLbits.PWM5PRL2 // bit 2
21942 #define PWM5PRL3 PWM5PRLbits.PWM5PRL3 // bit 3
21943 #define PWM5PRL4 PWM5PRLbits.PWM5PRL4 // bit 4
21944 #define PWM5PRL5 PWM5PRLbits.PWM5PRL5 // bit 5
21945 #define PWM5PRL6 PWM5PRLbits.PWM5PRL6 // bit 6
21946 #define PWM5PRL7 PWM5PRLbits.PWM5PRL7 // bit 7
21948 #define PWM5TMRH0 PWM5TMRHbits.PWM5TMRH0 // bit 0
21949 #define PWM5TMRH1 PWM5TMRHbits.PWM5TMRH1 // bit 1
21950 #define PWM5TMRH2 PWM5TMRHbits.PWM5TMRH2 // bit 2
21951 #define PWM5TMRH3 PWM5TMRHbits.PWM5TMRH3 // bit 3
21952 #define PWM5TMRH4 PWM5TMRHbits.PWM5TMRH4 // bit 4
21953 #define PWM5TMRH5 PWM5TMRHbits.PWM5TMRH5 // bit 5
21954 #define PWM5TMRH6 PWM5TMRHbits.PWM5TMRH6 // bit 6
21955 #define PWM5TMRH7 PWM5TMRHbits.PWM5TMRH7 // bit 7
21957 #define PWM5TMRL0 PWM5TMRLbits.PWM5TMRL0 // bit 0
21958 #define PWM5TMRL1 PWM5TMRLbits.PWM5TMRL1 // bit 1
21959 #define PWM5TMRL2 PWM5TMRLbits.PWM5TMRL2 // bit 2
21960 #define PWM5TMRL3 PWM5TMRLbits.PWM5TMRL3 // bit 3
21961 #define PWM5TMRL4 PWM5TMRLbits.PWM5TMRL4 // bit 4
21962 #define PWM5TMRL5 PWM5TMRLbits.PWM5TMRL5 // bit 5
21963 #define PWM5TMRL6 PWM5TMRLbits.PWM5TMRL6 // bit 6
21964 #define PWM5TMRL7 PWM5TMRLbits.PWM5TMRL7 // bit 7
21966 #define PWM6DCH0 PWM6DCHbits.PWM6DCH0 // bit 0
21967 #define PWM6DCH1 PWM6DCHbits.PWM6DCH1 // bit 1
21968 #define PWM6DCH2 PWM6DCHbits.PWM6DCH2 // bit 2
21969 #define PWM6DCH3 PWM6DCHbits.PWM6DCH3 // bit 3
21970 #define PWM6DCH4 PWM6DCHbits.PWM6DCH4 // bit 4
21971 #define PWM6DCH5 PWM6DCHbits.PWM6DCH5 // bit 5
21972 #define PWM6DCH6 PWM6DCHbits.PWM6DCH6 // bit 6
21973 #define PWM6DCH7 PWM6DCHbits.PWM6DCH7 // bit 7
21975 #define PWM6DCL0 PWM6DCLbits.PWM6DCL0 // bit 0
21976 #define PWM6DCL1 PWM6DCLbits.PWM6DCL1 // bit 1
21977 #define PWM6DCL2 PWM6DCLbits.PWM6DCL2 // bit 2
21978 #define PWM6DCL3 PWM6DCLbits.PWM6DCL3 // bit 3
21979 #define PWM6DCL4 PWM6DCLbits.PWM6DCL4 // bit 4
21980 #define PWM6DCL5 PWM6DCLbits.PWM6DCL5 // bit 5
21981 #define PWM6DCL6 PWM6DCLbits.PWM6DCL6 // bit 6
21982 #define PWM6DCL7 PWM6DCLbits.PWM6DCL7 // bit 7
21984 #define PWM6OFH0 PWM6OFHbits.PWM6OFH0 // bit 0
21985 #define PWM6OFH1 PWM6OFHbits.PWM6OFH1 // bit 1
21986 #define PWM6OFH2 PWM6OFHbits.PWM6OFH2 // bit 2
21987 #define PWM6OFH3 PWM6OFHbits.PWM6OFH3 // bit 3
21988 #define PWM6OFH4 PWM6OFHbits.PWM6OFH4 // bit 4
21989 #define PWM6OFH5 PWM6OFHbits.PWM6OFH5 // bit 5
21990 #define PWM6OFH6 PWM6OFHbits.PWM6OFH6 // bit 6
21991 #define PWM6OFH7 PWM6OFHbits.PWM6OFH7 // bit 7
21993 #define PWM6OFL0 PWM6OFLbits.PWM6OFL0 // bit 0
21994 #define PWM6OFL1 PWM6OFLbits.PWM6OFL1 // bit 1
21995 #define PWM6OFL2 PWM6OFLbits.PWM6OFL2 // bit 2
21996 #define PWM6OFL3 PWM6OFLbits.PWM6OFL3 // bit 3
21997 #define PWM6OFL4 PWM6OFLbits.PWM6OFL4 // bit 4
21998 #define PWM6OFL5 PWM6OFLbits.PWM6OFL5 // bit 5
21999 #define PWM6OFL6 PWM6OFLbits.PWM6OFL6 // bit 6
22000 #define PWM6OFL7 PWM6OFLbits.PWM6OFL7 // bit 7
22002 #define PWM6PHH0 PWM6PHHbits.PWM6PHH0 // bit 0
22003 #define PWM6PHH1 PWM6PHHbits.PWM6PHH1 // bit 1
22004 #define PWM6PHH2 PWM6PHHbits.PWM6PHH2 // bit 2
22005 #define PWM6PHH3 PWM6PHHbits.PWM6PHH3 // bit 3
22006 #define PWM6PHH4 PWM6PHHbits.PWM6PHH4 // bit 4
22007 #define PWM6PHH5 PWM6PHHbits.PWM6PHH5 // bit 5
22008 #define PWM6PHH6 PWM6PHHbits.PWM6PHH6 // bit 6
22009 #define PWM6PHH7 PWM6PHHbits.PWM6PHH7 // bit 7
22011 #define PWM6PHL0 PWM6PHLbits.PWM6PHL0 // bit 0
22012 #define PWM6PHL1 PWM6PHLbits.PWM6PHL1 // bit 1
22013 #define PWM6PHL2 PWM6PHLbits.PWM6PHL2 // bit 2
22014 #define PWM6PHL3 PWM6PHLbits.PWM6PHL3 // bit 3
22015 #define PWM6PHL4 PWM6PHLbits.PWM6PHL4 // bit 4
22016 #define PWM6PHL5 PWM6PHLbits.PWM6PHL5 // bit 5
22017 #define PWM6PHL6 PWM6PHLbits.PWM6PHL6 // bit 6
22018 #define PWM6PHL7 PWM6PHLbits.PWM6PHL7 // bit 7
22020 #define PWM6PRH0 PWM6PRHbits.PWM6PRH0 // bit 0
22021 #define PWM6PRH1 PWM6PRHbits.PWM6PRH1 // bit 1
22022 #define PWM6PRH2 PWM6PRHbits.PWM6PRH2 // bit 2
22023 #define PWM6PRH3 PWM6PRHbits.PWM6PRH3 // bit 3
22024 #define PWM6PRH4 PWM6PRHbits.PWM6PRH4 // bit 4
22025 #define PWM6PRH5 PWM6PRHbits.PWM6PRH5 // bit 5
22026 #define PWM6PRH6 PWM6PRHbits.PWM6PRH6 // bit 6
22027 #define PWM6PRH7 PWM6PRHbits.PWM6PRH7 // bit 7
22029 #define PWM6PRL0 PWM6PRLbits.PWM6PRL0 // bit 0
22030 #define PWM6PRL1 PWM6PRLbits.PWM6PRL1 // bit 1
22031 #define PWM6PRL2 PWM6PRLbits.PWM6PRL2 // bit 2
22032 #define PWM6PRL3 PWM6PRLbits.PWM6PRL3 // bit 3
22033 #define PWM6PRL4 PWM6PRLbits.PWM6PRL4 // bit 4
22034 #define PWM6PRL5 PWM6PRLbits.PWM6PRL5 // bit 5
22035 #define PWM6PRL6 PWM6PRLbits.PWM6PRL6 // bit 6
22036 #define PWM6PRL7 PWM6PRLbits.PWM6PRL7 // bit 7
22038 #define PWM6TMRH0 PWM6TMRHbits.PWM6TMRH0 // bit 0
22039 #define PWM6TMRH1 PWM6TMRHbits.PWM6TMRH1 // bit 1
22040 #define PWM6TMRH2 PWM6TMRHbits.PWM6TMRH2 // bit 2
22041 #define PWM6TMRH3 PWM6TMRHbits.PWM6TMRH3 // bit 3
22042 #define PWM6TMRH4 PWM6TMRHbits.PWM6TMRH4 // bit 4
22043 #define PWM6TMRH5 PWM6TMRHbits.PWM6TMRH5 // bit 5
22044 #define PWM6TMRH6 PWM6TMRHbits.PWM6TMRH6 // bit 6
22045 #define PWM6TMRH7 PWM6TMRHbits.PWM6TMRH7 // bit 7
22047 #define PWM6TMRL0 PWM6TMRLbits.PWM6TMRL0 // bit 0
22048 #define PWM6TMRL1 PWM6TMRLbits.PWM6TMRL1 // bit 1
22049 #define PWM6TMRL2 PWM6TMRLbits.PWM6TMRL2 // bit 2
22050 #define PWM6TMRL3 PWM6TMRLbits.PWM6TMRL3 // bit 3
22051 #define PWM6TMRL4 PWM6TMRLbits.PWM6TMRL4 // bit 4
22052 #define PWM6TMRL5 PWM6TMRLbits.PWM6TMRL5 // bit 5
22053 #define PWM6TMRL6 PWM6TMRLbits.PWM6TMRL6 // bit 6
22054 #define PWM6TMRL7 PWM6TMRLbits.PWM6TMRL7 // bit 7
22056 #define PWM11DCH0 PWM11DCHbits.PWM11DCH0 // bit 0
22057 #define PWM11DCH1 PWM11DCHbits.PWM11DCH1 // bit 1
22058 #define PWM11DCH2 PWM11DCHbits.PWM11DCH2 // bit 2
22059 #define PWM11DCH3 PWM11DCHbits.PWM11DCH3 // bit 3
22060 #define PWM11DCH4 PWM11DCHbits.PWM11DCH4 // bit 4
22061 #define PWM11DCH5 PWM11DCHbits.PWM11DCH5 // bit 5
22062 #define PWM11DCH6 PWM11DCHbits.PWM11DCH6 // bit 6
22063 #define PWM11DCH7 PWM11DCHbits.PWM11DCH7 // bit 7
22065 #define PWM11DCL0 PWM11DCLbits.PWM11DCL0 // bit 0
22066 #define PWM11DCL1 PWM11DCLbits.PWM11DCL1 // bit 1
22067 #define PWM11DCL2 PWM11DCLbits.PWM11DCL2 // bit 2
22068 #define PWM11DCL3 PWM11DCLbits.PWM11DCL3 // bit 3
22069 #define PWM11DCL4 PWM11DCLbits.PWM11DCL4 // bit 4
22070 #define PWM11DCL5 PWM11DCLbits.PWM11DCL5 // bit 5
22071 #define PWM11DCL6 PWM11DCLbits.PWM11DCL6 // bit 6
22072 #define PWM11DCL7 PWM11DCLbits.PWM11DCL7 // bit 7
22074 #define PWM11OFH0 PWM11OFHbits.PWM11OFH0 // bit 0
22075 #define PWM11OFH1 PWM11OFHbits.PWM11OFH1 // bit 1
22076 #define PWM11OFH2 PWM11OFHbits.PWM11OFH2 // bit 2
22077 #define PWM11OFH3 PWM11OFHbits.PWM11OFH3 // bit 3
22078 #define PWM11OFH4 PWM11OFHbits.PWM11OFH4 // bit 4
22079 #define PWM11OFH5 PWM11OFHbits.PWM11OFH5 // bit 5
22080 #define PWM11OFH6 PWM11OFHbits.PWM11OFH6 // bit 6
22081 #define PWM11OFH7 PWM11OFHbits.PWM11OFH7 // bit 7
22083 #define PWM11OFL0 PWM11OFLbits.PWM11OFL0 // bit 0
22084 #define PWM11OFL1 PWM11OFLbits.PWM11OFL1 // bit 1
22085 #define PWM11OFL2 PWM11OFLbits.PWM11OFL2 // bit 2
22086 #define PWM11OFL3 PWM11OFLbits.PWM11OFL3 // bit 3
22087 #define PWM11OFL4 PWM11OFLbits.PWM11OFL4 // bit 4
22088 #define PWM11OFL5 PWM11OFLbits.PWM11OFL5 // bit 5
22089 #define PWM11OFL6 PWM11OFLbits.PWM11OFL6 // bit 6
22090 #define PWM11OFL7 PWM11OFLbits.PWM11OFL7 // bit 7
22092 #define PWM11PHH0 PWM11PHHbits.PWM11PHH0 // bit 0
22093 #define PWM11PHH1 PWM11PHHbits.PWM11PHH1 // bit 1
22094 #define PWM11PHH2 PWM11PHHbits.PWM11PHH2 // bit 2
22095 #define PWM11PHH3 PWM11PHHbits.PWM11PHH3 // bit 3
22096 #define PWM11PHH4 PWM11PHHbits.PWM11PHH4 // bit 4
22097 #define PWM11PHH5 PWM11PHHbits.PWM11PHH5 // bit 5
22098 #define PWM11PHH6 PWM11PHHbits.PWM11PHH6 // bit 6
22099 #define PWM11PHH7 PWM11PHHbits.PWM11PHH7 // bit 7
22101 #define PWM11PHL0 PWM11PHLbits.PWM11PHL0 // bit 0
22102 #define PWM11PHL1 PWM11PHLbits.PWM11PHL1 // bit 1
22103 #define PWM11PHL2 PWM11PHLbits.PWM11PHL2 // bit 2
22104 #define PWM11PHL3 PWM11PHLbits.PWM11PHL3 // bit 3
22105 #define PWM11PHL4 PWM11PHLbits.PWM11PHL4 // bit 4
22106 #define PWM11PHL5 PWM11PHLbits.PWM11PHL5 // bit 5
22107 #define PWM11PHL6 PWM11PHLbits.PWM11PHL6 // bit 6
22108 #define PWM11PHL7 PWM11PHLbits.PWM11PHL7 // bit 7
22110 #define PWM11PRH0 PWM11PRHbits.PWM11PRH0 // bit 0
22111 #define PWM11PRH1 PWM11PRHbits.PWM11PRH1 // bit 1
22112 #define PWM11PRH2 PWM11PRHbits.PWM11PRH2 // bit 2
22113 #define PWM11PRH3 PWM11PRHbits.PWM11PRH3 // bit 3
22114 #define PWM11PRH4 PWM11PRHbits.PWM11PRH4 // bit 4
22115 #define PWM11PRH5 PWM11PRHbits.PWM11PRH5 // bit 5
22116 #define PWM11PRH6 PWM11PRHbits.PWM11PRH6 // bit 6
22117 #define PWM11PRH7 PWM11PRHbits.PWM11PRH7 // bit 7
22119 #define PWM11PRL0 PWM11PRLbits.PWM11PRL0 // bit 0
22120 #define PWM11PRL1 PWM11PRLbits.PWM11PRL1 // bit 1
22121 #define PWM11PRL2 PWM11PRLbits.PWM11PRL2 // bit 2
22122 #define PWM11PRL3 PWM11PRLbits.PWM11PRL3 // bit 3
22123 #define PWM11PRL4 PWM11PRLbits.PWM11PRL4 // bit 4
22124 #define PWM11PRL5 PWM11PRLbits.PWM11PRL5 // bit 5
22125 #define PWM11PRL6 PWM11PRLbits.PWM11PRL6 // bit 6
22126 #define PWM11PRL7 PWM11PRLbits.PWM11PRL7 // bit 7
22128 #define PWM11TMRH0 PWM11TMRHbits.PWM11TMRH0 // bit 0
22129 #define PWM11TMRH1 PWM11TMRHbits.PWM11TMRH1 // bit 1
22130 #define PWM11TMRH2 PWM11TMRHbits.PWM11TMRH2 // bit 2
22131 #define PWM11TMRH3 PWM11TMRHbits.PWM11TMRH3 // bit 3
22132 #define PWM11TMRH4 PWM11TMRHbits.PWM11TMRH4 // bit 4
22133 #define PWM11TMRH5 PWM11TMRHbits.PWM11TMRH5 // bit 5
22134 #define PWM11TMRH6 PWM11TMRHbits.PWM11TMRH6 // bit 6
22135 #define PWM11TMRH7 PWM11TMRHbits.PWM11TMRH7 // bit 7
22137 #define PWM11TMRL0 PWM11TMRLbits.PWM11TMRL0 // bit 0
22138 #define PWM11TMRL1 PWM11TMRLbits.PWM11TMRL1 // bit 1
22139 #define PWM11TMRL2 PWM11TMRLbits.PWM11TMRL2 // bit 2
22140 #define PWM11TMRL3 PWM11TMRLbits.PWM11TMRL3 // bit 3
22141 #define PWM11TMRL4 PWM11TMRLbits.PWM11TMRL4 // bit 4
22142 #define PWM11TMRL5 PWM11TMRLbits.PWM11TMRL5 // bit 5
22143 #define PWM11TMRL6 PWM11TMRLbits.PWM11TMRL6 // bit 6
22144 #define PWM11TMRL7 PWM11TMRLbits.PWM11TMRL7 // bit 7
22146 #define MPWM5EN PWMENbits.MPWM5EN // bit 0
22147 #define MPWM6EN PWMENbits.MPWM6EN // bit 1
22148 #define MPWM11EN PWMENbits.MPWM11EN // bit 2
22150 #define MPWM5LD PWMLDbits.MPWM5LD // bit 0
22151 #define MPWM6LD PWMLDbits.MPWM6LD // bit 1
22152 #define MPWM11LD PWMLDbits.MPWM11LD // bit 2
22154 #define MPWM5OUT PWMOUTbits.MPWM5OUT // bit 0
22155 #define MPWM6OUT PWMOUTbits.MPWM6OUT // bit 1
22156 #define MPWM11OUT PWMOUTbits.MPWM11OUT // bit 2
22158 #define RX9D RC1STAbits.RX9D // bit 0
22159 #define OERR RC1STAbits.OERR // bit 1
22160 #define FERR RC1STAbits.FERR // bit 2
22161 #define ADDEN RC1STAbits.ADDEN // bit 3
22162 #define CREN RC1STAbits.CREN // bit 4
22163 #define SREN RC1STAbits.SREN // bit 5
22164 #define RX9 RC1STAbits.RX9 // bit 6
22165 #define SPEN RC1STAbits.SPEN // bit 7
22167 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
22168 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
22169 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
22170 #define SLRA3 SLRCONAbits.SLRA3 // bit 3
22171 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
22172 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
22173 #define SLRA6 SLRCONAbits.SLRA6 // bit 6
22174 #define SLRA7 SLRCONAbits.SLRA7 // bit 7
22176 #define SLRB0 SLRCONBbits.SLRB0 // bit 0
22177 #define SLRB1 SLRCONBbits.SLRB1 // bit 1
22178 #define SLRB2 SLRCONBbits.SLRB2 // bit 2
22179 #define SLRB3 SLRCONBbits.SLRB3 // bit 3
22180 #define SLRB4 SLRCONBbits.SLRB4 // bit 4
22181 #define SLRB5 SLRCONBbits.SLRB5 // bit 5
22182 #define SLRB6 SLRCONBbits.SLRB6 // bit 6
22183 #define SLRB7 SLRCONBbits.SLRB7 // bit 7
22185 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
22186 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
22187 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
22188 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
22189 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
22190 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
22191 #define SLRC6 SLRCONCbits.SLRC6 // bit 6
22192 #define SLRC7 SLRCONCbits.SLRC7 // bit 7
22194 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
22195 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
22196 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
22197 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
22198 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
22199 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
22200 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
22201 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
22202 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
22203 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
22204 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
22205 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
22206 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
22207 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
22208 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
22209 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
22211 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
22212 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
22213 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
22214 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
22215 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
22216 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
22217 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
22218 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
22219 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
22220 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
22221 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
22222 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
22223 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
22224 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
22225 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
22226 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
22228 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
22229 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
22230 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
22231 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
22232 #define CKP SSP1CONbits.CKP // bit 4
22233 #define SSPEN SSP1CONbits.SSPEN // bit 5
22234 #define SSPOV SSP1CONbits.SSPOV // bit 6
22235 #define WCOL SSP1CONbits.WCOL // bit 7
22237 #define SEN SSP1CON2bits.SEN // bit 0
22238 #define RSEN SSP1CON2bits.RSEN // bit 1
22239 #define PEN SSP1CON2bits.PEN // bit 2
22240 #define RCEN SSP1CON2bits.RCEN // bit 3
22241 #define ACKEN SSP1CON2bits.ACKEN // bit 4
22242 #define ACKDT SSP1CON2bits.ACKDT // bit 5
22243 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
22244 #define GCEN SSP1CON2bits.GCEN // bit 7
22246 #define DHEN SSP1CON3bits.DHEN // bit 0
22247 #define AHEN SSP1CON3bits.AHEN // bit 1
22248 #define SBCDE SSP1CON3bits.SBCDE // bit 2
22249 #define SDAHT SSP1CON3bits.SDAHT // bit 3
22250 #define BOEN SSP1CON3bits.BOEN // bit 4
22251 #define SCIE SSP1CON3bits.SCIE // bit 5
22252 #define PCIE SSP1CON3bits.PCIE // bit 6
22253 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
22255 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
22256 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
22257 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
22258 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
22259 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
22260 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
22261 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
22262 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
22263 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
22264 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
22265 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
22266 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
22267 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
22268 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
22269 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
22270 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
22272 #define BF SSP1STATbits.BF // bit 0
22273 #define UA SSP1STATbits.UA // bit 1
22274 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
22275 #define S SSP1STATbits.S // bit 3
22276 #define P SSP1STATbits.P // bit 4
22277 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
22278 #define CKE SSP1STATbits.CKE // bit 6
22279 #define SMP SSP1STATbits.SMP // bit 7
22281 #define C STATUSbits.C // bit 0
22282 #define DC STATUSbits.DC // bit 1
22283 #define Z STATUSbits.Z // bit 2
22284 #define NOT_PD STATUSbits.NOT_PD // bit 3
22285 #define NOT_TO STATUSbits.NOT_TO // bit 4
22287 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
22288 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
22289 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
22291 #define GSS0 T1GCONbits.GSS0 // bit 0, shadows bit in T1GCONbits
22292 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0, shadows bit in T1GCONbits
22293 #define GSS1 T1GCONbits.GSS1 // bit 1, shadows bit in T1GCONbits
22294 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1, shadows bit in T1GCONbits
22295 #define GVAL T1GCONbits.GVAL // bit 2, shadows bit in T1GCONbits
22296 #define T1GVAL T1GCONbits.T1GVAL // bit 2, shadows bit in T1GCONbits
22297 #define GGO_NOT_DONE T1GCONbits.GGO_NOT_DONE // bit 3, shadows bit in T1GCONbits
22298 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3, shadows bit in T1GCONbits
22299 #define GSPM T1GCONbits.GSPM // bit 4, shadows bit in T1GCONbits
22300 #define T1GSPM T1GCONbits.T1GSPM // bit 4, shadows bit in T1GCONbits
22301 #define GTM T1GCONbits.GTM // bit 5, shadows bit in T1GCONbits
22302 #define T1GTM T1GCONbits.T1GTM // bit 5, shadows bit in T1GCONbits
22303 #define GPOL T1GCONbits.GPOL // bit 6, shadows bit in T1GCONbits
22304 #define T1GPOL T1GCONbits.T1GPOL // bit 6, shadows bit in T1GCONbits
22305 #define GE T1GCONbits.GE // bit 7, shadows bit in T1GCONbits
22306 #define T1GE T1GCONbits.T1GE // bit 7, shadows bit in T1GCONbits
22307 #define TMR1GE T1GCONbits.TMR1GE // bit 7, shadows bit in T1GCONbits
22309 #define RSEL0 T2RSTbits.RSEL0 // bit 0, shadows bit in T2RSTbits
22310 #define T2RSEL0 T2RSTbits.T2RSEL0 // bit 0, shadows bit in T2RSTbits
22311 #define RSEL1 T2RSTbits.RSEL1 // bit 1, shadows bit in T2RSTbits
22312 #define T2RSEL1 T2RSTbits.T2RSEL1 // bit 1, shadows bit in T2RSTbits
22313 #define RSEL2 T2RSTbits.RSEL2 // bit 2, shadows bit in T2RSTbits
22314 #define T2RSEL2 T2RSTbits.T2RSEL2 // bit 2, shadows bit in T2RSTbits
22315 #define RSEL3 T2RSTbits.RSEL3 // bit 3, shadows bit in T2RSTbits
22316 #define T2RSEL3 T2RSTbits.T2RSEL3 // bit 3, shadows bit in T2RSTbits
22317 #define RSEL4 T2RSTbits.RSEL4 // bit 4, shadows bit in T2RSTbits
22318 #define T2RSEL4 T2RSTbits.T2RSEL4 // bit 4, shadows bit in T2RSTbits
22320 #define TRISA0 TRISAbits.TRISA0 // bit 0
22321 #define TRISA1 TRISAbits.TRISA1 // bit 1
22322 #define TRISA2 TRISAbits.TRISA2 // bit 2
22323 #define TRISA3 TRISAbits.TRISA3 // bit 3
22324 #define TRISA4 TRISAbits.TRISA4 // bit 4
22325 #define TRISA5 TRISAbits.TRISA5 // bit 5
22326 #define TRISA6 TRISAbits.TRISA6 // bit 6
22327 #define TRISA7 TRISAbits.TRISA7 // bit 7
22329 #define TRISB0 TRISBbits.TRISB0 // bit 0
22330 #define TRISB1 TRISBbits.TRISB1 // bit 1
22331 #define TRISB2 TRISBbits.TRISB2 // bit 2
22332 #define TRISB3 TRISBbits.TRISB3 // bit 3
22333 #define TRISB4 TRISBbits.TRISB4 // bit 4
22334 #define TRISB5 TRISBbits.TRISB5 // bit 5
22335 #define TRISB6 TRISBbits.TRISB6 // bit 6
22336 #define TRISB7 TRISBbits.TRISB7 // bit 7
22338 #define TRISC0 TRISCbits.TRISC0 // bit 0
22339 #define TRISC1 TRISCbits.TRISC1 // bit 1
22340 #define TRISC2 TRISCbits.TRISC2 // bit 2
22341 #define TRISC3 TRISCbits.TRISC3 // bit 3
22342 #define TRISC4 TRISCbits.TRISC4 // bit 4
22343 #define TRISC5 TRISCbits.TRISC5 // bit 5
22344 #define TRISC6 TRISCbits.TRISC6 // bit 6
22345 #define TRISC7 TRISCbits.TRISC7 // bit 7
22347 #define TRISE3 TRISEbits.TRISE3 // bit 3
22349 #define VREGPM0 VREGCONbits.VREGPM0 // bit 0
22350 #define VREGPM1 VREGCONbits.VREGPM1 // bit 1
22352 #define SWDTEN WDTCONbits.SWDTEN // bit 0
22353 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
22354 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
22355 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
22356 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
22357 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
22359 #define WPUA0 WPUAbits.WPUA0 // bit 0
22360 #define WPUA1 WPUAbits.WPUA1 // bit 1
22361 #define WPUA2 WPUAbits.WPUA2 // bit 2
22362 #define WPUA3 WPUAbits.WPUA3 // bit 3
22363 #define WPUA4 WPUAbits.WPUA4 // bit 4
22364 #define WPUA5 WPUAbits.WPUA5 // bit 5
22365 #define WPUA6 WPUAbits.WPUA6 // bit 6
22366 #define WPUA7 WPUAbits.WPUA7 // bit 7
22368 #define WPUB0 WPUBbits.WPUB0 // bit 0
22369 #define WPUB1 WPUBbits.WPUB1 // bit 1
22370 #define WPUB2 WPUBbits.WPUB2 // bit 2
22371 #define WPUB3 WPUBbits.WPUB3 // bit 3
22372 #define WPUB4 WPUBbits.WPUB4 // bit 4
22373 #define WPUB5 WPUBbits.WPUB5 // bit 5
22374 #define WPUB6 WPUBbits.WPUB6 // bit 6
22375 #define WPUB7 WPUBbits.WPUB7 // bit 7
22377 #define WPUC0 WPUCbits.WPUC0 // bit 0
22378 #define WPUC1 WPUCbits.WPUC1 // bit 1
22379 #define WPUC2 WPUCbits.WPUC2 // bit 2
22380 #define WPUC3 WPUCbits.WPUC3 // bit 3
22381 #define WPUC4 WPUCbits.WPUC4 // bit 4
22382 #define WPUC5 WPUCbits.WPUC5 // bit 5
22383 #define WPUC6 WPUCbits.WPUC6 // bit 6
22384 #define WPUC7 WPUCbits.WPUC7 // bit 7
22386 #define WPUE3 WPUEbits.WPUE3 // bit 3
22388 #define ZCD1INTN ZCD1CONbits.ZCD1INTN // bit 0
22389 #define ZCD1INTP ZCD1CONbits.ZCD1INTP // bit 1
22390 #define ZCD1POL ZCD1CONbits.ZCD1POL // bit 4
22391 #define ZCD1OUT ZCD1CONbits.ZCD1OUT // bit 5
22392 #define ZCD1EN ZCD1CONbits.ZCD1EN // bit 7
22394 #endif // #ifndef NO_BIT_DEFINES
22396 #endif // #ifndef __PIC16F1773_H__