2 * This declarations of the PIC16F1777 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:16 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F1777_H__
26 #define __PIC16F1777_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTB_ADDR 0x000D
52 #define PORTC_ADDR 0x000E
53 #define PORTD_ADDR 0x000F
54 #define PORTE_ADDR 0x0010
55 #define PIR1_ADDR 0x0011
56 #define PIR2_ADDR 0x0012
57 #define PIR3_ADDR 0x0013
58 #define PIR4_ADDR 0x0014
59 #define PIR5_ADDR 0x0015
60 #define PIR6_ADDR 0x0016
61 #define TMR0_ADDR 0x0017
62 #define TMR1_ADDR 0x0018
63 #define TMR1L_ADDR 0x0018
64 #define TMR1H_ADDR 0x0019
65 #define T1CON_ADDR 0x001A
66 #define T1GCON_ADDR 0x001B
67 #define TMR3_ADDR 0x001C
68 #define TMR3L_ADDR 0x001C
69 #define TMR3H_ADDR 0x001D
70 #define T3CON_ADDR 0x001E
71 #define T3GCON_ADDR 0x001F
72 #define TRISA_ADDR 0x008C
73 #define TRISB_ADDR 0x008D
74 #define TRISC_ADDR 0x008E
75 #define TRISD_ADDR 0x008F
76 #define TRISE_ADDR 0x0090
77 #define PIE1_ADDR 0x0091
78 #define PIE2_ADDR 0x0092
79 #define PIE3_ADDR 0x0093
80 #define PIE4_ADDR 0x0094
81 #define PIE5_ADDR 0x0095
82 #define PIE6_ADDR 0x0096
83 #define OPTION_REG_ADDR 0x0097
84 #define PCON_ADDR 0x0098
85 #define WDTCON_ADDR 0x0099
86 #define OSCTUNE_ADDR 0x009A
87 #define OSCCON_ADDR 0x009B
88 #define OSCSTAT_ADDR 0x009C
89 #define BORCON_ADDR 0x009D
90 #define FVRCON_ADDR 0x009E
91 #define ZCD1CON_ADDR 0x009F
92 #define LATA_ADDR 0x010C
93 #define LATB_ADDR 0x010D
94 #define LATC_ADDR 0x010E
95 #define LATD_ADDR 0x010F
96 #define LATE_ADDR 0x0110
97 #define CMOUT_ADDR 0x0111
98 #define CM1CON0_ADDR 0x0112
99 #define CM1CON1_ADDR 0x0113
100 #define CM1NSEL_ADDR 0x0114
101 #define CM1PSEL_ADDR 0x0115
102 #define CM2CON0_ADDR 0x0116
103 #define CM2CON1_ADDR 0x0117
104 #define CM2NSEL_ADDR 0x0118
105 #define CM2PSEL_ADDR 0x0119
106 #define CM3CON0_ADDR 0x011A
107 #define CM3CON1_ADDR 0x011B
108 #define CM3NSEL_ADDR 0x011C
109 #define CM3PSEL_ADDR 0x011D
110 #define ANSELA_ADDR 0x018C
111 #define ANSELB_ADDR 0x018D
112 #define ANSELC_ADDR 0x018E
113 #define ANSELD_ADDR 0x018F
114 #define ANSELE_ADDR 0x0190
115 #define PMADR_ADDR 0x0191
116 #define PMADRL_ADDR 0x0191
117 #define PMADRH_ADDR 0x0192
118 #define PMDAT_ADDR 0x0193
119 #define PMDATL_ADDR 0x0193
120 #define PMDATH_ADDR 0x0194
121 #define PMCON1_ADDR 0x0195
122 #define PMCON2_ADDR 0x0196
123 #define VREGCON_ADDR 0x0197
124 #define RC1REG_ADDR 0x0199
125 #define RCREG_ADDR 0x0199
126 #define RCREG1_ADDR 0x0199
127 #define TX1REG_ADDR 0x019A
128 #define TXREG_ADDR 0x019A
129 #define TXREG1_ADDR 0x019A
130 #define SP1BRG_ADDR 0x019B
131 #define SP1BRGL_ADDR 0x019B
132 #define SPBRG_ADDR 0x019B
133 #define SPBRG1_ADDR 0x019B
134 #define SPBRGL_ADDR 0x019B
135 #define SP1BRGH_ADDR 0x019C
136 #define SPBRGH_ADDR 0x019C
137 #define SPBRGH1_ADDR 0x019C
138 #define RC1STA_ADDR 0x019D
139 #define RCSTA_ADDR 0x019D
140 #define RCSTA1_ADDR 0x019D
141 #define TX1STA_ADDR 0x019E
142 #define TXSTA_ADDR 0x019E
143 #define TXSTA1_ADDR 0x019E
144 #define BAUD1CON_ADDR 0x019F
145 #define BAUDCON_ADDR 0x019F
146 #define BAUDCON1_ADDR 0x019F
147 #define BAUDCTL_ADDR 0x019F
148 #define BAUDCTL1_ADDR 0x019F
149 #define WPUA_ADDR 0x020C
150 #define WPUB_ADDR 0x020D
151 #define WPUC_ADDR 0x020E
152 #define WPUD_ADDR 0x020F
153 #define WPUE_ADDR 0x0210
154 #define SSP1BUF_ADDR 0x0211
155 #define SSPBUF_ADDR 0x0211
156 #define SSP1ADD_ADDR 0x0212
157 #define SSPADD_ADDR 0x0212
158 #define SSP1MSK_ADDR 0x0213
159 #define SSPMSK_ADDR 0x0213
160 #define SSP1STAT_ADDR 0x0214
161 #define SSPSTAT_ADDR 0x0214
162 #define SSP1CON_ADDR 0x0215
163 #define SSP1CON1_ADDR 0x0215
164 #define SSPCON_ADDR 0x0215
165 #define SSPCON1_ADDR 0x0215
166 #define SSP1CON2_ADDR 0x0216
167 #define SSPCON2_ADDR 0x0216
168 #define SSP1CON3_ADDR 0x0217
169 #define SSPCON3_ADDR 0x0217
170 #define MD3CON0_ADDR 0x021B
171 #define MD3CON1_ADDR 0x021C
172 #define MD3SRC_ADDR 0x021D
173 #define MD3CARL_ADDR 0x021E
174 #define MD3CARH_ADDR 0x021F
175 #define ODCONA_ADDR 0x028C
176 #define ODCONB_ADDR 0x028D
177 #define ODCONC_ADDR 0x028E
178 #define ODCOND_ADDR 0x028F
179 #define ODCONE_ADDR 0x0290
180 #define CCPR1_ADDR 0x0291
181 #define CCPR1L_ADDR 0x0291
182 #define CCPR1H_ADDR 0x0292
183 #define CCP1CON_ADDR 0x0293
184 #define CCP1CAP_ADDR 0x0294
185 #define CCPR2_ADDR 0x0295
186 #define CCPR2L_ADDR 0x0295
187 #define CCPR2H_ADDR 0x0296
188 #define CCP2CON_ADDR 0x0297
189 #define CCP2CAP_ADDR 0x0298
190 #define CCPR7_ADDR 0x0299
191 #define CCPR7L_ADDR 0x0299
192 #define CCPR7H_ADDR 0x029A
193 #define CCP7CON_ADDR 0x029B
194 #define CCP7CAP_ADDR 0x029C
195 #define CCPTMRS1_ADDR 0x029E
196 #define CCPTMRS2_ADDR 0x029F
197 #define SLRCONA_ADDR 0x030C
198 #define SLRCONB_ADDR 0x030D
199 #define SLRCONC_ADDR 0x030E
200 #define SLRCOND_ADDR 0x030F
201 #define SLRCONE_ADDR 0x0310
202 #define CCPR8_ADDR 0x0311
203 #define CCPR8L_ADDR 0x0311
204 #define CCPR8H_ADDR 0x0312
205 #define CCP8CON_ADDR 0x0313
206 #define CCP8CAP_ADDR 0x0314
207 #define MD1CON0_ADDR 0x0315
208 #define MD1CON1_ADDR 0x0316
209 #define MD1SRC_ADDR 0x0317
210 #define MD1CARL_ADDR 0x0318
211 #define MD1CARH_ADDR 0x0319
212 #define MD2CON0_ADDR 0x031B
213 #define MD2CON1_ADDR 0x031C
214 #define MD2SRC_ADDR 0x031D
215 #define MD2CARL_ADDR 0x031E
216 #define MD2CARH_ADDR 0x031F
217 #define INLVLA_ADDR 0x038C
218 #define INLVLB_ADDR 0x038D
219 #define INLVLC_ADDR 0x038E
220 #define INLVLD_ADDR 0x038F
221 #define INLVE_ADDR 0x0390
222 #define IOCAP_ADDR 0x0391
223 #define IOCAN_ADDR 0x0392
224 #define IOCAF_ADDR 0x0393
225 #define IOCBP_ADDR 0x0394
226 #define IOCBN_ADDR 0x0395
227 #define IOCBF_ADDR 0x0396
228 #define IOCCP_ADDR 0x0397
229 #define IOCCN_ADDR 0x0398
230 #define IOCCF_ADDR 0x0399
231 #define IOCEP_ADDR 0x039D
232 #define IOCEN_ADDR 0x039E
233 #define IOCEF_ADDR 0x039F
234 #define HIDRVB_ADDR 0x040D
235 #define TMR5_ADDR 0x040F
236 #define TMR5L_ADDR 0x040F
237 #define TMR5H_ADDR 0x0410
238 #define T5CON_ADDR 0x0411
239 #define T5GCON_ADDR 0x0412
240 #define T4TMR_ADDR 0x0413
241 #define TMR4_ADDR 0x0413
242 #define PR4_ADDR 0x0414
243 #define T4PR_ADDR 0x0414
244 #define T4CON_ADDR 0x0415
245 #define T4HLT_ADDR 0x0416
246 #define T4CLKCON_ADDR 0x0417
247 #define T4RST_ADDR 0x0418
248 #define T6TMR_ADDR 0x041A
249 #define TMR6_ADDR 0x041A
250 #define PR6_ADDR 0x041B
251 #define T6PR_ADDR 0x041B
252 #define T6CON_ADDR 0x041C
253 #define T6HLT_ADDR 0x041D
254 #define T6CLKCON_ADDR 0x041E
255 #define T6RST_ADDR 0x041F
256 #define ADRESL_ADDR 0x048E
257 #define ADRESH_ADDR 0x048F
258 #define ADCON0_ADDR 0x0490
259 #define ADCON1_ADDR 0x0491
260 #define ADCON2_ADDR 0x0492
261 #define T2TMR_ADDR 0x0493
262 #define TMR2_ADDR 0x0493
263 #define PR2_ADDR 0x0494
264 #define T2PR_ADDR 0x0494
265 #define T2CON_ADDR 0x0495
266 #define T2HLT_ADDR 0x0496
267 #define T2CLKCON_ADDR 0x0497
268 #define T2RST_ADDR 0x0498
269 #define T8TMR_ADDR 0x049A
270 #define TMR8_ADDR 0x049A
271 #define PR8_ADDR 0x049B
272 #define T8PR_ADDR 0x049B
273 #define T8CON_ADDR 0x049C
274 #define T8HLT_ADDR 0x049D
275 #define T8CLKCON_ADDR 0x049E
276 #define T8RST_ADDR 0x049F
277 #define OPA1NCHS_ADDR 0x050F
278 #define OPA1PCHS_ADDR 0x0510
279 #define OPA1CON_ADDR 0x0511
280 #define OPA1ORS_ADDR 0x0512
281 #define OPA2NCHS_ADDR 0x0513
282 #define OPA2PCHS_ADDR 0x0514
283 #define OPA2CON_ADDR 0x0515
284 #define OPA2ORS_ADDR 0x0516
285 #define OPA3NCHS_ADDR 0x0517
286 #define OPA3PCHS_ADDR 0x0518
287 #define OPA3CON_ADDR 0x0519
288 #define OPA3ORS_ADDR 0x051A
289 #define OPA4NCHS_ADDR 0x051B
290 #define OPA4PCHS_ADDR 0x051C
291 #define OPA4CON_ADDR 0x051D
292 #define OPA4ORS_ADDR 0x051E
293 #define DACLD_ADDR 0x058D
294 #define DAC1CON0_ADDR 0x058E
295 #define DAC1CON1_ADDR 0x058F
296 #define DAC1REF_ADDR 0x058F
297 #define DAC1REFL_ADDR 0x058F
298 #define DAC1CON2_ADDR 0x0590
299 #define DAC1REFH_ADDR 0x0590
300 #define DAC2CON0_ADDR 0x0591
301 #define DAC2CON1_ADDR 0x0592
302 #define DAC2REF_ADDR 0x0592
303 #define DAC2REFL_ADDR 0x0592
304 #define DAC2CON2_ADDR 0x0593
305 #define DAC2REFH_ADDR 0x0593
306 #define DAC3CON0_ADDR 0x0594
307 #define DAC3CON1_ADDR 0x0595
308 #define DAC3REF_ADDR 0x0595
309 #define DAC4CON0_ADDR 0x0596
310 #define DAC4CON1_ADDR 0x0597
311 #define DAC4REF_ADDR 0x0597
312 #define DAC5CON0_ADDR 0x0598
313 #define DAC5CON1_ADDR 0x0599
314 #define DAC5REF_ADDR 0x0599
315 #define DAC5REFL_ADDR 0x0599
316 #define DAC5CON2_ADDR 0x059A
317 #define DAC5REFH_ADDR 0x059A
318 #define DAC6CON0_ADDR 0x059B
319 #define DAC6CON1_ADDR 0x059C
320 #define DAC6REF_ADDR 0x059C
321 #define DAC6REFL_ADDR 0x059C
322 #define DAC6CON2_ADDR 0x059D
323 #define DAC6REFH_ADDR 0x059D
324 #define DAC7CON0_ADDR 0x059E
325 #define DAC7CON1_ADDR 0x059F
326 #define DAC7REF_ADDR 0x059F
327 #define DAC8CON0_ADDR 0x060C
328 #define DAC8CON1_ADDR 0x060D
329 #define DAC8REF_ADDR 0x060D
330 #define PRG4RTSS_ADDR 0x060E
331 #define PRG4FTSS_ADDR 0x060F
332 #define PRG4INS_ADDR 0x0610
333 #define PRG4CON0_ADDR 0x0611
334 #define PRG4CON1_ADDR 0x0612
335 #define PRG4CON2_ADDR 0x0613
336 #define PWM3DCL_ADDR 0x0614
337 #define PWM3DCH_ADDR 0x0615
338 #define PWM3CON_ADDR 0x0616
339 #define PWM4DCL_ADDR 0x0617
340 #define PWM4DCH_ADDR 0x0618
341 #define PWM4CON_ADDR 0x0619
342 #define PWM9DCL_ADDR 0x061A
343 #define PWM9DCH_ADDR 0x061B
344 #define PWM9CON_ADDR 0x061C
345 #define PWM10DCL_ADDR 0x061D
346 #define PWM10DCH_ADDR 0x061E
347 #define PWM10CON_ADDR 0x061F
348 #define COG1PHR_ADDR 0x068D
349 #define COG1PHF_ADDR 0x068E
350 #define COG1BLKR_ADDR 0x068F
351 #define COG1BLKF_ADDR 0x0690
352 #define COG1DBR_ADDR 0x0691
353 #define COG1DBF_ADDR 0x0692
354 #define COG1CON0_ADDR 0x0693
355 #define COG1CON1_ADDR 0x0694
356 #define COG1RIS0_ADDR 0x0695
357 #define COG1RIS1_ADDR 0x0696
358 #define COG1RSIM0_ADDR 0x0697
359 #define COG1RSIM1_ADDR 0x0698
360 #define COG1FIS0_ADDR 0x0699
361 #define COG1FIS1_ADDR 0x069A
362 #define COG1FSIM0_ADDR 0x069B
363 #define COG1FSIM1_ADDR 0x069C
364 #define COG1ASD0_ADDR 0x069D
365 #define COG1ASD1_ADDR 0x069E
366 #define COG1STR_ADDR 0x069F
367 #define COG2PHR_ADDR 0x070D
368 #define COG2PHF_ADDR 0x070E
369 #define COG2BLKR_ADDR 0x070F
370 #define COG2BLKF_ADDR 0x0710
371 #define COG2DBR_ADDR 0x0711
372 #define COG2DBF_ADDR 0x0712
373 #define COG2CON0_ADDR 0x0713
374 #define COG2CON1_ADDR 0x0714
375 #define COG2RIS0_ADDR 0x0715
376 #define COG2RIS1_ADDR 0x0716
377 #define COG2RSIM0_ADDR 0x0717
378 #define COG2RSIM1_ADDR 0x0718
379 #define COG2FIS0_ADDR 0x0719
380 #define COG2FIS1_ADDR 0x071A
381 #define COG2FSIM0_ADDR 0x071B
382 #define COG2FSIM1_ADDR 0x071C
383 #define COG2ASD0_ADDR 0x071D
384 #define COG2ASD1_ADDR 0x071E
385 #define COG2STR_ADDR 0x071F
386 #define PRG1RTSS_ADDR 0x078E
387 #define PRG1FTSS_ADDR 0x078F
388 #define PRG1INS_ADDR 0x0790
389 #define PRG1CON0_ADDR 0x0791
390 #define PRG1CON1_ADDR 0x0792
391 #define PRG1CON2_ADDR 0x0793
392 #define PRG2RTSS_ADDR 0x0794
393 #define PRG2FTSS_ADDR 0x0795
394 #define PRG2INS_ADDR 0x0796
395 #define PRG2CON0_ADDR 0x0797
396 #define PRG2CON1_ADDR 0x0798
397 #define PRG2CON2_ADDR 0x0799
398 #define PRG3RTSS_ADDR 0x079A
399 #define PRG3FTSS_ADDR 0x079B
400 #define PRG3INS_ADDR 0x079C
401 #define PRG3CON0_ADDR 0x079D
402 #define PRG3CON1_ADDR 0x079E
403 #define PRG3CON2_ADDR 0x079F
404 #define COG3PHR_ADDR 0x080D
405 #define COG3PHF_ADDR 0x080E
406 #define COG3BLKR_ADDR 0x080F
407 #define COG3BLKF_ADDR 0x0810
408 #define COG3DBR_ADDR 0x0811
409 #define COG3DBF_ADDR 0x0812
410 #define COG3CON0_ADDR 0x0813
411 #define COG3CON1_ADDR 0x0814
412 #define COG3RIS0_ADDR 0x0815
413 #define COG3RIS1_ADDR 0x0816
414 #define COG3RSIM0_ADDR 0x0817
415 #define COG3RSIM1_ADDR 0x0818
416 #define COG3FIS0_ADDR 0x0819
417 #define COG3FIS1_ADDR 0x081A
418 #define COG3FSIM0_ADDR 0x081B
419 #define COG3FSIM1_ADDR 0x081C
420 #define COG3ASD0_ADDR 0x081D
421 #define COG3ASD1_ADDR 0x081E
422 #define COG3STR_ADDR 0x081F
423 #define COG4PHR_ADDR 0x088D
424 #define COG4PHF_ADDR 0x088E
425 #define COG4BLKR_ADDR 0x088F
426 #define COG4BLKF_ADDR 0x0890
427 #define COG4DBR_ADDR 0x0891
428 #define COG4DBF_ADDR 0x0892
429 #define COG4CON0_ADDR 0x0893
430 #define COG4CON1_ADDR 0x0894
431 #define COG4RIS0_ADDR 0x0895
432 #define COG4RIS1_ADDR 0x0896
433 #define COG4RSIM0_ADDR 0x0897
434 #define COG4RSIM1_ADDR 0x0898
435 #define COG4FIS0_ADDR 0x0899
436 #define COG4FIS1_ADDR 0x089A
437 #define COG4FSIM0_ADDR 0x089B
438 #define COG4FSIM1_ADDR 0x089C
439 #define COG4ASD0_ADDR 0x089D
440 #define COG4ASD1_ADDR 0x089E
441 #define COG4STR_ADDR 0x089F
442 #define CM4CON0_ADDR 0x090C
443 #define CM4CON1_ADDR 0x090D
444 #define CM4NSEL_ADDR 0x090E
445 #define CM4PSEL_ADDR 0x090F
446 #define CM5CON0_ADDR 0x0910
447 #define CM5CON1_ADDR 0x0911
448 #define CM5NSEL_ADDR 0x0912
449 #define CM5PSEL_ADDR 0x0913
450 #define CM6CON0_ADDR 0x0914
451 #define CM6CON1_ADDR 0x0915
452 #define CM6NSEL_ADDR 0x0916
453 #define CM6PSEL_ADDR 0x0917
454 #define CM7CON0_ADDR 0x0918
455 #define CM7CON1_ADDR 0x0919
456 #define CM7NSEL_ADDR 0x091A
457 #define CM7PSEL_ADDR 0x091B
458 #define CM8CON0_ADDR 0x091C
459 #define CM8CON1_ADDR 0x091D
460 #define CM8NSEL_ADDR 0x091E
461 #define CM8PSEL_ADDR 0x091F
462 #define MD4CON0_ADDR 0x0D1B
463 #define MD4CON1_ADDR 0x0D1C
464 #define MD4SRC_ADDR 0x0D1D
465 #define MD4CARL_ADDR 0x0D1E
466 #define MD4CARH_ADDR 0x0D1F
467 #define PWMEN_ADDR 0x0D8E
468 #define PWMLD_ADDR 0x0D8F
469 #define PWMOUT_ADDR 0x0D90
470 #define PWM5PH_ADDR 0x0D91
471 #define PWM5PHL_ADDR 0x0D91
472 #define PWM5PHH_ADDR 0x0D92
473 #define PWM5DC_ADDR 0x0D93
474 #define PWM5DCL_ADDR 0x0D93
475 #define PWM5DCH_ADDR 0x0D94
476 #define PWM5PR_ADDR 0x0D95
477 #define PWM5PRL_ADDR 0x0D95
478 #define PWM5PRH_ADDR 0x0D96
479 #define PWM5OF_ADDR 0x0D97
480 #define PWM5OFL_ADDR 0x0D97
481 #define PWM5OFH_ADDR 0x0D98
482 #define PWM5TMR_ADDR 0x0D99
483 #define PWM5TMRL_ADDR 0x0D99
484 #define PWM5TMRH_ADDR 0x0D9A
485 #define PWM5CON_ADDR 0x0D9B
486 #define PWM5INTCON_ADDR 0x0D9C
487 #define PWM5INTE_ADDR 0x0D9C
488 #define PWM5INTF_ADDR 0x0D9D
489 #define PWM5INTFLG_ADDR 0x0D9D
490 #define PWM5CLKCON_ADDR 0x0D9E
491 #define PWM5LDCON_ADDR 0x0D9F
492 #define PWM5OFCON_ADDR 0x0DA0
493 #define PWM6PH_ADDR 0x0DA1
494 #define PWM6PHL_ADDR 0x0DA1
495 #define PWM6PHH_ADDR 0x0DA2
496 #define PWM6DC_ADDR 0x0DA3
497 #define PWM6DCL_ADDR 0x0DA3
498 #define PWM6DCH_ADDR 0x0DA4
499 #define PWM6PR_ADDR 0x0DA5
500 #define PWM6PRL_ADDR 0x0DA5
501 #define PWM6PRH_ADDR 0x0DA6
502 #define PWM6OF_ADDR 0x0DA7
503 #define PWM6OFL_ADDR 0x0DA7
504 #define PWM6OFH_ADDR 0x0DA8
505 #define PWM6TMR_ADDR 0x0DA9
506 #define PWM6TMRL_ADDR 0x0DA9
507 #define PWM6TMRH_ADDR 0x0DAA
508 #define PWM6CON_ADDR 0x0DAB
509 #define PWM6INTCON_ADDR 0x0DAC
510 #define PWM6INTE_ADDR 0x0DAC
511 #define PWM6INTF_ADDR 0x0DAD
512 #define PWM6INTFLG_ADDR 0x0DAD
513 #define PWM6CLKCON_ADDR 0x0DAE
514 #define PWM6LDCON_ADDR 0x0DAF
515 #define PWM6OFCON_ADDR 0x0DB0
516 #define PWM11PH_ADDR 0x0DB1
517 #define PWM11PHL_ADDR 0x0DB1
518 #define PWM11PHH_ADDR 0x0DB2
519 #define PWM11DC_ADDR 0x0DB3
520 #define PWM11DCL_ADDR 0x0DB3
521 #define PWM11DCH_ADDR 0x0DB4
522 #define PWM11PR_ADDR 0x0DB5
523 #define PWM11PRL_ADDR 0x0DB5
524 #define PWM11PRH_ADDR 0x0DB6
525 #define PWM11OF_ADDR 0x0DB7
526 #define PWM11OFL_ADDR 0x0DB7
527 #define PWM11OFH_ADDR 0x0DB8
528 #define PWM11TMR_ADDR 0x0DB9
529 #define PWM11TMRL_ADDR 0x0DB9
530 #define PWM11TMRH_ADDR 0x0DBA
531 #define PWM11CON_ADDR 0x0DBB
532 #define PWM11INTCON_ADDR 0x0DBC
533 #define PWM11INTE_ADDR 0x0DBC
534 #define PWM11INTF_ADDR 0x0DBD
535 #define PWM11INTFLG_ADDR 0x0DBD
536 #define PWM11CLKCON_ADDR 0x0DBE
537 #define PWM11LDCON_ADDR 0x0DBF
538 #define PWM11OFCON_ADDR 0x0DC0
539 #define PWM12PH_ADDR 0x0DC1
540 #define PWM12PHL_ADDR 0x0DC1
541 #define PWM12PHH_ADDR 0x0DC2
542 #define PWM12DC_ADDR 0x0DC3
543 #define PWM12DCL_ADDR 0x0DC3
544 #define PWM12DCH_ADDR 0x0DC4
545 #define PWM12PR_ADDR 0x0DC5
546 #define PWM12PRL_ADDR 0x0DC5
547 #define PWM12PRH_ADDR 0x0DC6
548 #define PWM12OF_ADDR 0x0DC7
549 #define PWM12OFL_ADDR 0x0DC7
550 #define PWM12OFH_ADDR 0x0DC8
551 #define PWM12TMR_ADDR 0x0DC9
552 #define PWM12TMRL_ADDR 0x0DC9
553 #define PWM12TMRH_ADDR 0x0DCA
554 #define PWM12CON_ADDR 0x0DCB
555 #define PWM12INTCON_ADDR 0x0DCC
556 #define PWM12INTE_ADDR 0x0DCC
557 #define PWM12INTF_ADDR 0x0DCD
558 #define PWM12INTFLG_ADDR 0x0DCD
559 #define PWM12CLKCON_ADDR 0x0DCE
560 #define PWM12LDCON_ADDR 0x0DCF
561 #define PWM12OFCON_ADDR 0x0DD0
562 #define PPSLOCK_ADDR 0x0E0C
563 #define INTPPS_ADDR 0x0E0D
564 #define T0CKIPPS_ADDR 0x0E0E
565 #define T1CKIPPS_ADDR 0x0E0F
566 #define T1GPPS_ADDR 0x0E10
567 #define T3CKIPPS_ADDR 0x0E11
568 #define T3GPPS_ADDR 0x0E12
569 #define T5CKIPPS_ADDR 0x0E13
570 #define T5GPPS_ADDR 0x0E14
571 #define T2CKIPPS_ADDR 0x0E15
572 #define T4CKIPPS_ADDR 0x0E16
573 #define T6CKIPPS_ADDR 0x0E17
574 #define T8CKIPPS_ADDR 0x0E18
575 #define CCP1PPS_ADDR 0x0E19
576 #define CCP2PPS_ADDR 0x0E1A
577 #define CCP7PPS_ADDR 0x0E1B
578 #define CCP8PPS_ADDR 0x0E1C
579 #define COG1INPPS_ADDR 0x0E1D
580 #define COG2INPPS_ADDR 0x0E1E
581 #define COG3INPPS_ADDR 0x0E1F
582 #define COG4INPPS_ADDR 0x0E20
583 #define MD1CLPPS_ADDR 0x0E21
584 #define MD1CHPPS_ADDR 0x0E22
585 #define MD1MODPPS_ADDR 0x0E23
586 #define MD2CLPPS_ADDR 0x0E24
587 #define MD2CHPPS_ADDR 0x0E25
588 #define MD2MODPPS_ADDR 0x0E26
589 #define MD3CLPPS_ADDR 0x0E27
590 #define MD3CHPPS_ADDR 0x0E28
591 #define MD3MODPPS_ADDR 0x0E29
592 #define MD4CLPPS_ADDR 0x0E2A
593 #define MD4CHPPS_ADDR 0x0E2B
594 #define MD4MODPPS_ADDR 0x0E2C
595 #define PRG1RPPS_ADDR 0x0E2D
596 #define PRG1FPPS_ADDR 0x0E2E
597 #define PRG2RPPS_ADDR 0x0E2F
598 #define PRG2FPPS_ADDR 0x0E30
599 #define PRG3RPPS_ADDR 0x0E31
600 #define PRG3FPPS_ADDR 0x0E32
601 #define PRG4RPPS_ADDR 0x0E33
602 #define PRG4FPPS_ADDR 0x0E34
603 #define CLCIN0PPS_ADDR 0x0E35
604 #define CLCIN1PPS_ADDR 0x0E36
605 #define CLCIN2PPS_ADDR 0x0E37
606 #define CLCIN3PPS_ADDR 0x0E38
607 #define ADCACTPPS_ADDR 0x0E39
608 #define SSPCLKPPS_ADDR 0x0E3A
609 #define SSPDATPPS_ADDR 0x0E3B
610 #define SSPSSPPS_ADDR 0x0E3C
611 #define RXPPS_ADDR 0x0E3D
612 #define CKPPS_ADDR 0x0E3E
613 #define RA0PPS_ADDR 0x0E90
614 #define RA1PPS_ADDR 0x0E91
615 #define RA2PPS_ADDR 0x0E92
616 #define RA3PPS_ADDR 0x0E93
617 #define RA4PPS_ADDR 0x0E94
618 #define RA5PPS_ADDR 0x0E95
619 #define RA6PPS_ADDR 0x0E96
620 #define RA7PPS_ADDR 0x0E97
621 #define RB0PPS_ADDR 0x0E98
622 #define RB1PPS_ADDR 0x0E99
623 #define RB2PPS_ADDR 0x0E9A
624 #define RB3PPS_ADDR 0x0E9B
625 #define RB4PPS_ADDR 0x0E9C
626 #define RB5PPS_ADDR 0x0E9D
627 #define RB6PPS_ADDR 0x0E9E
628 #define RB7PPS_ADDR 0x0E9F
629 #define RC0PPS_ADDR 0x0EA0
630 #define RC1PPS_ADDR 0x0EA1
631 #define RC2PPS_ADDR 0x0EA2
632 #define RC3PPS_ADDR 0x0EA3
633 #define RC4PPS_ADDR 0x0EA4
634 #define RC5PPS_ADDR 0x0EA5
635 #define RC6PPS_ADDR 0x0EA6
636 #define RC7PPS_ADDR 0x0EA7
637 #define RD0PPS_ADDR 0x0EA8
638 #define RD1PPS_ADDR 0x0EA9
639 #define RD2PPS_ADDR 0x0EAA
640 #define RD3PPS_ADDR 0x0EAB
641 #define RD4PPS_ADDR 0x0EAC
642 #define RD5PPS_ADDR 0x0EAD
643 #define RD6PPS_ADDR 0x0EAE
644 #define RD7PPS_ADDR 0x0EAF
645 #define RE0PPS_ADDR 0x0EB0
646 #define RE1PPS_ADDR 0x0EB1
647 #define RE2PPS_ADDR 0x0EB2
648 #define CLCDATA_ADDR 0x0F0F
649 #define CLC1CON_ADDR 0x0F10
650 #define CLC1POL_ADDR 0x0F11
651 #define CLC1SEL0_ADDR 0x0F12
652 #define CLC1SEL1_ADDR 0x0F13
653 #define CLC1SEL2_ADDR 0x0F14
654 #define CLC1SEL3_ADDR 0x0F15
655 #define CLC1GLS0_ADDR 0x0F16
656 #define CLC1GLS1_ADDR 0x0F17
657 #define CLC1GLS2_ADDR 0x0F18
658 #define CLC1GLS3_ADDR 0x0F19
659 #define CLC2CON_ADDR 0x0F1A
660 #define CLC2POL_ADDR 0x0F1B
661 #define CLC2SEL0_ADDR 0x0F1C
662 #define CLC2SEL1_ADDR 0x0F1D
663 #define CLC2SEL2_ADDR 0x0F1E
664 #define CLC2SEL3_ADDR 0x0F1F
665 #define CLC2GLS0_ADDR 0x0F20
666 #define CLC2GLS1_ADDR 0x0F21
667 #define CLC2GLS2_ADDR 0x0F22
668 #define CLC2GLS3_ADDR 0x0F23
669 #define CLC3CON_ADDR 0x0F24
670 #define CLC3POL_ADDR 0x0F25
671 #define CLC3SEL0_ADDR 0x0F26
672 #define CLC3SEL1_ADDR 0x0F27
673 #define CLC3SEL2_ADDR 0x0F28
674 #define CLC3SEL3_ADDR 0x0F29
675 #define CLC3GLS0_ADDR 0x0F2A
676 #define CLC3GLS1_ADDR 0x0F2B
677 #define CLC3GLS2_ADDR 0x0F2C
678 #define CLC3GLS3_ADDR 0x0F2D
679 #define CLC4CON_ADDR 0x0F2E
680 #define CLC4POL_ADDR 0x0F2F
681 #define CLC4SEL0_ADDR 0x0F30
682 #define CLC4SEL1_ADDR 0x0F31
683 #define CLC4SEL2_ADDR 0x0F32
684 #define CLC4SEL3_ADDR 0x0F33
685 #define CLC4GLS0_ADDR 0x0F34
686 #define CLC4GLS1_ADDR 0x0F35
687 #define CLC4GLS2_ADDR 0x0F36
688 #define CLC4GLS3_ADDR 0x0F37
689 #define STATUS_SHAD_ADDR 0x0FE4
690 #define WREG_SHAD_ADDR 0x0FE5
691 #define BSR_SHAD_ADDR 0x0FE6
692 #define PCLATH_SHAD_ADDR 0x0FE7
693 #define FSR0L_SHAD_ADDR 0x0FE8
694 #define FSR0H_SHAD_ADDR 0x0FE9
695 #define FSR1L_SHAD_ADDR 0x0FEA
696 #define FSR1H_SHAD_ADDR 0x0FEB
697 #define STKPTR_ADDR 0x0FED
698 #define TOSL_ADDR 0x0FEE
699 #define TOSH_ADDR 0x0FEF
701 #endif // #ifndef NO_ADDR_DEFINES
703 //==============================================================================
705 // Register Definitions
707 //==============================================================================
709 extern __at(0x0000) __sfr INDF0
;
710 extern __at(0x0001) __sfr INDF1
;
711 extern __at(0x0002) __sfr PCL
;
713 //==============================================================================
716 extern __at(0x0003) __sfr STATUS
;
730 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
738 //==============================================================================
740 extern __at(0x0004) __sfr FSR0
;
741 extern __at(0x0004) __sfr FSR0L
;
742 extern __at(0x0005) __sfr FSR0H
;
743 extern __at(0x0006) __sfr FSR1
;
744 extern __at(0x0006) __sfr FSR1L
;
745 extern __at(0x0007) __sfr FSR1H
;
747 //==============================================================================
750 extern __at(0x0008) __sfr BSR
;
773 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
781 //==============================================================================
783 extern __at(0x0009) __sfr WREG
;
784 extern __at(0x000A) __sfr PCLATH
;
786 //==============================================================================
789 extern __at(0x000B) __sfr INTCON
;
818 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
831 //==============================================================================
834 //==============================================================================
837 extern __at(0x000C) __sfr PORTA
;
851 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
862 //==============================================================================
865 //==============================================================================
868 extern __at(0x000D) __sfr PORTB
;
882 extern __at(0x000D) volatile __PORTBbits_t PORTBbits
;
893 //==============================================================================
896 //==============================================================================
899 extern __at(0x000E) __sfr PORTC
;
913 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
924 //==============================================================================
927 //==============================================================================
930 extern __at(0x000F) __sfr PORTD
;
944 extern __at(0x000F) volatile __PORTDbits_t PORTDbits
;
955 //==============================================================================
958 //==============================================================================
961 extern __at(0x0010) __sfr PORTE
;
984 extern __at(0x0010) volatile __PORTEbits_t PORTEbits
;
991 //==============================================================================
994 //==============================================================================
997 extern __at(0x0011) __sfr PIR1
;
1003 unsigned TMR1IF
: 1;
1004 unsigned TMR2IF
: 1;
1005 unsigned CCP1IF
: 1;
1006 unsigned SSP1IF
: 1;
1010 unsigned TMR1GIF
: 1;
1026 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
1028 #define _TMR1IF 0x01
1029 #define _TMR2IF 0x02
1030 #define _CCP1IF 0x04
1032 #define _SSP1IF 0x08
1036 #define _TMR1GIF 0x80
1038 //==============================================================================
1041 //==============================================================================
1044 extern __at(0x0012) __sfr PIR2
;
1048 unsigned CCP2IF
: 1;
1051 unsigned BCL1IF
: 1;
1052 unsigned COG1IF
: 1;
1058 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
1060 #define _CCP2IF 0x01
1063 #define _BCL1IF 0x08
1064 #define _COG1IF 0x10
1069 //==============================================================================
1072 //==============================================================================
1075 extern __at(0x0013) __sfr PIR3
;
1079 unsigned CLC1IF
: 1;
1080 unsigned CLC2IF
: 1;
1081 unsigned CLC3IF
: 1;
1082 unsigned CLC4IF
: 1;
1084 unsigned COG2IF
: 1;
1089 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
1091 #define _CLC1IF 0x01
1092 #define _CLC2IF 0x02
1093 #define _CLC3IF 0x04
1094 #define _CLC4IF 0x08
1096 #define _COG2IF 0x20
1098 //==============================================================================
1101 //==============================================================================
1104 extern __at(0x0014) __sfr PIR4
;
1108 unsigned TMR4IF
: 1;
1109 unsigned TMR6IF
: 1;
1110 unsigned TMR3IF
: 1;
1111 unsigned TMR3GIF
: 1;
1112 unsigned TMR5IF
: 1;
1113 unsigned TMR5GIF
: 1;
1114 unsigned TMR8IF
: 1;
1118 extern __at(0x0014) volatile __PIR4bits_t PIR4bits
;
1120 #define _TMR4IF 0x01
1121 #define _TMR6IF 0x02
1122 #define _TMR3IF 0x04
1123 #define _TMR3GIF 0x08
1124 #define _TMR5IF 0x10
1125 #define _TMR5GIF 0x20
1126 #define _TMR8IF 0x40
1128 //==============================================================================
1131 //==============================================================================
1134 extern __at(0x0015) __sfr PIR5
;
1142 unsigned COG3IF
: 1;
1143 unsigned COG4IF
: 1;
1144 unsigned CCP7IF
: 1;
1145 unsigned CCP8IF
: 1;
1148 extern __at(0x0015) volatile __PIR5bits_t PIR5bits
;
1154 #define _COG3IF 0x10
1155 #define _COG4IF 0x20
1156 #define _CCP7IF 0x40
1157 #define _CCP8IF 0x80
1159 //==============================================================================
1162 //==============================================================================
1165 extern __at(0x0016) __sfr PIR6
;
1169 unsigned PWM5IF
: 1;
1170 unsigned PWM6IF
: 1;
1171 unsigned PWM11IF
: 1;
1172 unsigned PWM12IF
: 1;
1179 extern __at(0x0016) volatile __PIR6bits_t PIR6bits
;
1181 #define _PWM5IF 0x01
1182 #define _PWM6IF 0x02
1183 #define _PWM11IF 0x04
1184 #define _PWM12IF 0x08
1186 //==============================================================================
1188 extern __at(0x0017) __sfr TMR0
;
1189 extern __at(0x0018) __sfr TMR1
;
1190 extern __at(0x0018) __sfr TMR1L
;
1191 extern __at(0x0019) __sfr TMR1H
;
1193 //==============================================================================
1196 extern __at(0x001A) __sfr T1CON
;
1204 unsigned NOT_SYNC
: 1;
1217 unsigned SOSCEN
: 1;
1218 unsigned T1CKPS0
: 1;
1219 unsigned T1CKPS1
: 1;
1226 unsigned TMR1ON
: 1;
1228 unsigned NOT_T1SYNC
: 1;
1229 unsigned T1OSCEN
: 1;
1232 unsigned TMR1CS0
: 1;
1233 unsigned TMR1CS1
: 1;
1251 unsigned T1CKPS
: 2;
1277 unsigned TMR1CS
: 2;
1281 extern __at(0x001A) volatile __T1CONbits_t T1CONbits
;
1283 #define _T1CON_ON 0x01
1284 #define _T1CON_TMRON 0x01
1285 #define _T1CON_TMR1ON 0x01
1286 #define _T1CON_T1ON 0x01
1287 #define _T1CON_NOT_SYNC 0x04
1288 #define _T1CON_SYNC 0x04
1289 #define _T1CON_NOT_T1SYNC 0x04
1290 #define _T1CON_OSCEN 0x08
1291 #define _T1CON_SOSCEN 0x08
1292 #define _T1CON_T1OSCEN 0x08
1293 #define _T1CON_CKPS0 0x10
1294 #define _T1CON_T1CKPS0 0x10
1295 #define _T1CON_CKPS1 0x20
1296 #define _T1CON_T1CKPS1 0x20
1297 #define _T1CON_CS0 0x40
1298 #define _T1CON_T1CS0 0x40
1299 #define _T1CON_TMR1CS0 0x40
1300 #define _T1CON_CS1 0x80
1301 #define _T1CON_T1CS1 0x80
1302 #define _T1CON_TMR1CS1 0x80
1304 //==============================================================================
1307 //==============================================================================
1310 extern __at(0x001B) __sfr T1GCON
;
1319 unsigned GGO_NOT_DONE
: 1;
1328 unsigned T1GSS0
: 1;
1329 unsigned T1GSS1
: 1;
1330 unsigned T1GVAL
: 1;
1331 unsigned T1GGO_NOT_DONE
: 1;
1332 unsigned T1GSPM
: 1;
1334 unsigned T1GPOL
: 1;
1347 unsigned TMR1GE
: 1;
1363 extern __at(0x001B) volatile __T1GCONbits_t T1GCONbits
;
1366 #define _T1GSS0 0x01
1368 #define _T1GSS1 0x02
1370 #define _T1GVAL 0x04
1371 #define _GGO_NOT_DONE 0x08
1372 #define _T1GGO_NOT_DONE 0x08
1374 #define _T1GSPM 0x10
1378 #define _T1GPOL 0x40
1381 #define _TMR1GE 0x80
1383 //==============================================================================
1385 extern __at(0x001C) __sfr TMR3
;
1386 extern __at(0x001C) __sfr TMR3L
;
1387 extern __at(0x001D) __sfr TMR3H
;
1389 //==============================================================================
1392 extern __at(0x001E) __sfr T3CON
;
1400 unsigned NOT_SYNC
: 1;
1413 unsigned SOSCEN
: 1;
1414 unsigned T3CKPS0
: 1;
1415 unsigned T3CKPS1
: 1;
1422 unsigned TMR3ON
: 1;
1424 unsigned NOT_T3SYNC
: 1;
1425 unsigned T3OSCEN
: 1;
1428 unsigned TMR3CS0
: 1;
1429 unsigned TMR3CS1
: 1;
1454 unsigned T3CKPS
: 2;
1467 unsigned TMR3CS
: 2;
1477 extern __at(0x001E) volatile __T3CONbits_t T3CONbits
;
1479 #define _T3CON_ON 0x01
1480 #define _T3CON_TMRON 0x01
1481 #define _T3CON_TMR3ON 0x01
1482 #define _T3CON_T3ON 0x01
1483 #define _T3CON_NOT_SYNC 0x04
1484 #define _T3CON_SYNC 0x04
1485 #define _T3CON_NOT_T3SYNC 0x04
1486 #define _T3CON_OSCEN 0x08
1487 #define _T3CON_SOSCEN 0x08
1488 #define _T3CON_T3OSCEN 0x08
1489 #define _T3CON_CKPS0 0x10
1490 #define _T3CON_T3CKPS0 0x10
1491 #define _T3CON_CKPS1 0x20
1492 #define _T3CON_T3CKPS1 0x20
1493 #define _T3CON_CS0 0x40
1494 #define _T3CON_T3CS0 0x40
1495 #define _T3CON_TMR3CS0 0x40
1496 #define _T3CON_CS1 0x80
1497 #define _T3CON_T3CS1 0x80
1498 #define _T3CON_TMR3CS1 0x80
1500 //==============================================================================
1503 //==============================================================================
1506 extern __at(0x001F) __sfr T3GCON
;
1515 unsigned GGO_NOT_DONE
: 1;
1524 unsigned T3GSS0
: 1;
1525 unsigned T3GSS1
: 1;
1526 unsigned T3GVAL
: 1;
1527 unsigned T3GGO_NOT_DONE
: 1;
1528 unsigned T3GSPM
: 1;
1530 unsigned T3GPOL
: 1;
1543 unsigned TMR3GE
: 1;
1559 extern __at(0x001F) volatile __T3GCONbits_t T3GCONbits
;
1561 #define _T3GCON_GSS0 0x01
1562 #define _T3GCON_T3GSS0 0x01
1563 #define _T3GCON_GSS1 0x02
1564 #define _T3GCON_T3GSS1 0x02
1565 #define _T3GCON_GVAL 0x04
1566 #define _T3GCON_T3GVAL 0x04
1567 #define _T3GCON_GGO_NOT_DONE 0x08
1568 #define _T3GCON_T3GGO_NOT_DONE 0x08
1569 #define _T3GCON_GSPM 0x10
1570 #define _T3GCON_T3GSPM 0x10
1571 #define _T3GCON_GTM 0x20
1572 #define _T3GCON_T3GTM 0x20
1573 #define _T3GCON_GPOL 0x40
1574 #define _T3GCON_T3GPOL 0x40
1575 #define _T3GCON_GE 0x80
1576 #define _T3GCON_T3GE 0x80
1577 #define _T3GCON_TMR3GE 0x80
1579 //==============================================================================
1582 //==============================================================================
1585 extern __at(0x008C) __sfr TRISA
;
1589 unsigned TRISA0
: 1;
1590 unsigned TRISA1
: 1;
1591 unsigned TRISA2
: 1;
1592 unsigned TRISA3
: 1;
1593 unsigned TRISA4
: 1;
1594 unsigned TRISA5
: 1;
1595 unsigned TRISA6
: 1;
1596 unsigned TRISA7
: 1;
1599 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
1601 #define _TRISA0 0x01
1602 #define _TRISA1 0x02
1603 #define _TRISA2 0x04
1604 #define _TRISA3 0x08
1605 #define _TRISA4 0x10
1606 #define _TRISA5 0x20
1607 #define _TRISA6 0x40
1608 #define _TRISA7 0x80
1610 //==============================================================================
1613 //==============================================================================
1616 extern __at(0x008D) __sfr TRISB
;
1620 unsigned TRISB0
: 1;
1621 unsigned TRISB1
: 1;
1622 unsigned TRISB2
: 1;
1623 unsigned TRISB3
: 1;
1624 unsigned TRISB4
: 1;
1625 unsigned TRISB5
: 1;
1626 unsigned TRISB6
: 1;
1627 unsigned TRISB7
: 1;
1630 extern __at(0x008D) volatile __TRISBbits_t TRISBbits
;
1632 #define _TRISB0 0x01
1633 #define _TRISB1 0x02
1634 #define _TRISB2 0x04
1635 #define _TRISB3 0x08
1636 #define _TRISB4 0x10
1637 #define _TRISB5 0x20
1638 #define _TRISB6 0x40
1639 #define _TRISB7 0x80
1641 //==============================================================================
1644 //==============================================================================
1647 extern __at(0x008E) __sfr TRISC
;
1651 unsigned TRISC0
: 1;
1652 unsigned TRISC1
: 1;
1653 unsigned TRISC2
: 1;
1654 unsigned TRISC3
: 1;
1655 unsigned TRISC4
: 1;
1656 unsigned TRISC5
: 1;
1657 unsigned TRISC6
: 1;
1658 unsigned TRISC7
: 1;
1661 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
1663 #define _TRISC0 0x01
1664 #define _TRISC1 0x02
1665 #define _TRISC2 0x04
1666 #define _TRISC3 0x08
1667 #define _TRISC4 0x10
1668 #define _TRISC5 0x20
1669 #define _TRISC6 0x40
1670 #define _TRISC7 0x80
1672 //==============================================================================
1675 //==============================================================================
1678 extern __at(0x008F) __sfr TRISD
;
1682 unsigned TRISD0
: 1;
1683 unsigned TRISD1
: 1;
1684 unsigned TRISD2
: 1;
1685 unsigned TRISD3
: 1;
1686 unsigned TRISD4
: 1;
1687 unsigned TRISD5
: 1;
1688 unsigned TRISD6
: 1;
1689 unsigned TRISD7
: 1;
1692 extern __at(0x008F) volatile __TRISDbits_t TRISDbits
;
1694 #define _TRISD0 0x01
1695 #define _TRISD1 0x02
1696 #define _TRISD2 0x04
1697 #define _TRISD3 0x08
1698 #define _TRISD4 0x10
1699 #define _TRISD5 0x20
1700 #define _TRISD6 0x40
1701 #define _TRISD7 0x80
1703 //==============================================================================
1706 //==============================================================================
1709 extern __at(0x0090) __sfr TRISE
;
1715 unsigned TRISE0
: 1;
1716 unsigned TRISE1
: 1;
1717 unsigned TRISE2
: 1;
1718 unsigned TRISE3
: 1;
1732 extern __at(0x0090) volatile __TRISEbits_t TRISEbits
;
1734 #define _TRISE0 0x01
1735 #define _TRISE1 0x02
1736 #define _TRISE2 0x04
1737 #define _TRISE3 0x08
1739 //==============================================================================
1742 //==============================================================================
1745 extern __at(0x0091) __sfr PIE1
;
1751 unsigned TMR1IE
: 1;
1752 unsigned TMR2IE
: 1;
1753 unsigned CCP1IE
: 1;
1754 unsigned SSP1IE
: 1;
1758 unsigned TMR1GIE
: 1;
1774 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
1776 #define _TMR1IE 0x01
1777 #define _TMR2IE 0x02
1778 #define _CCP1IE 0x04
1780 #define _SSP1IE 0x08
1784 #define _TMR1GIE 0x80
1786 //==============================================================================
1789 //==============================================================================
1792 extern __at(0x0092) __sfr PIE2
;
1796 unsigned CCP2IE
: 1;
1799 unsigned BCL1IE
: 1;
1806 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
1808 #define _CCP2IE 0x01
1811 #define _BCL1IE 0x08
1817 //==============================================================================
1820 //==============================================================================
1823 extern __at(0x0093) __sfr PIE3
;
1827 unsigned CLC1IE
: 1;
1828 unsigned CLC2IE
: 1;
1829 unsigned CLC3IE
: 1;
1830 unsigned CLC4IE
: 1;
1832 unsigned COG2IE
: 1;
1837 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
1839 #define _CLC1IE 0x01
1840 #define _CLC2IE 0x02
1841 #define _CLC3IE 0x04
1842 #define _CLC4IE 0x08
1844 #define _COG2IE 0x20
1846 //==============================================================================
1849 //==============================================================================
1852 extern __at(0x0094) __sfr PIE4
;
1856 unsigned TMR4IE
: 1;
1857 unsigned TMR6IE
: 1;
1858 unsigned TMR3IE
: 1;
1859 unsigned TMR3GIE
: 1;
1860 unsigned TMR5IE
: 1;
1861 unsigned TMR5GIE
: 1;
1862 unsigned TMR8IE
: 1;
1866 extern __at(0x0094) volatile __PIE4bits_t PIE4bits
;
1868 #define _TMR4IE 0x01
1869 #define _TMR6IE 0x02
1870 #define _TMR3IE 0x04
1871 #define _TMR3GIE 0x08
1872 #define _TMR5IE 0x10
1873 #define _TMR5GIE 0x20
1874 #define _TMR8IE 0x40
1876 //==============================================================================
1879 //==============================================================================
1882 extern __at(0x0095) __sfr PIE5
;
1890 unsigned COG3IE
: 1;
1891 unsigned COG4IE
: 1;
1892 unsigned CCP7IE
: 1;
1893 unsigned CCP8IE
: 1;
1896 extern __at(0x0095) volatile __PIE5bits_t PIE5bits
;
1902 #define _COG3IE 0x10
1903 #define _COG4IE 0x20
1904 #define _CCP7IE 0x40
1905 #define _CCP8IE 0x80
1907 //==============================================================================
1910 //==============================================================================
1913 extern __at(0x0096) __sfr PIE6
;
1917 unsigned PWM5IE
: 1;
1918 unsigned PWM6IE
: 1;
1919 unsigned PWM11IE
: 1;
1920 unsigned PWM12IE
: 1;
1927 extern __at(0x0096) volatile __PIE6bits_t PIE6bits
;
1929 #define _PWM5IE 0x01
1930 #define _PWM6IE 0x02
1931 #define _PWM11IE 0x04
1932 #define _PWM12IE 0x08
1934 //==============================================================================
1937 //==============================================================================
1940 extern __at(0x0097) __sfr OPTION_REG
;
1950 unsigned TMR0SE
: 1;
1951 unsigned TMR0CS
: 1;
1952 unsigned INTEDG
: 1;
1953 unsigned NOT_WPUEN
: 1;
1973 } __OPTION_REGbits_t
;
1975 extern __at(0x0097) volatile __OPTION_REGbits_t OPTION_REGbits
;
1981 #define _TMR0SE 0x10
1983 #define _TMR0CS 0x20
1985 #define _INTEDG 0x40
1986 #define _NOT_WPUEN 0x80
1988 //==============================================================================
1991 //==============================================================================
1994 extern __at(0x0098) __sfr PCON
;
1998 unsigned NOT_BOR
: 1;
1999 unsigned NOT_POR
: 1;
2000 unsigned NOT_RI
: 1;
2001 unsigned NOT_RMCLR
: 1;
2002 unsigned NOT_RWDT
: 1;
2004 unsigned STKUNF
: 1;
2005 unsigned STKOVF
: 1;
2008 extern __at(0x0098) volatile __PCONbits_t PCONbits
;
2010 #define _NOT_BOR 0x01
2011 #define _NOT_POR 0x02
2012 #define _NOT_RI 0x04
2013 #define _NOT_RMCLR 0x08
2014 #define _NOT_RWDT 0x10
2015 #define _STKUNF 0x40
2016 #define _STKOVF 0x80
2018 //==============================================================================
2021 //==============================================================================
2024 extern __at(0x0099) __sfr WDTCON
;
2030 unsigned SWDTEN
: 1;
2031 unsigned WDTPS0
: 1;
2032 unsigned WDTPS1
: 1;
2033 unsigned WDTPS2
: 1;
2034 unsigned WDTPS3
: 1;
2035 unsigned WDTPS4
: 1;
2048 extern __at(0x0099) volatile __WDTCONbits_t WDTCONbits
;
2050 #define _SWDTEN 0x01
2051 #define _WDTPS0 0x02
2052 #define _WDTPS1 0x04
2053 #define _WDTPS2 0x08
2054 #define _WDTPS3 0x10
2055 #define _WDTPS4 0x20
2057 //==============================================================================
2060 //==============================================================================
2063 extern __at(0x009A) __sfr OSCTUNE
;
2086 extern __at(0x009A) volatile __OSCTUNEbits_t OSCTUNEbits
;
2095 //==============================================================================
2098 //==============================================================================
2101 extern __at(0x009B) __sfr OSCCON
;
2114 unsigned SPLLEN
: 1;
2131 extern __at(0x009B) volatile __OSCCONbits_t OSCCONbits
;
2139 #define _SPLLEN 0x80
2141 //==============================================================================
2144 //==============================================================================
2147 extern __at(0x009C) __sfr OSCSTAT
;
2151 unsigned HFIOFS
: 1;
2152 unsigned LFIOFR
: 1;
2153 unsigned MFIOFR
: 1;
2154 unsigned HFIOFL
: 1;
2155 unsigned HFIOFR
: 1;
2161 extern __at(0x009C) volatile __OSCSTATbits_t OSCSTATbits
;
2163 #define _HFIOFS 0x01
2164 #define _LFIOFR 0x02
2165 #define _MFIOFR 0x04
2166 #define _HFIOFL 0x08
2167 #define _HFIOFR 0x10
2172 //==============================================================================
2175 //==============================================================================
2178 extern __at(0x009D) __sfr BORCON
;
2182 unsigned BORRDY
: 1;
2189 unsigned SBOREN
: 1;
2192 extern __at(0x009D) volatile __BORCONbits_t BORCONbits
;
2194 #define _BORRDY 0x01
2196 #define _SBOREN 0x80
2198 //==============================================================================
2201 //==============================================================================
2204 extern __at(0x009E) __sfr FVRCON
;
2214 unsigned FVRRDY
: 1;
2218 extern __at(0x009E) volatile __FVRCONbits_t FVRCONbits
;
2222 #define _FVRRDY 0x40
2225 //==============================================================================
2228 //==============================================================================
2231 extern __at(0x009F) __sfr ZCD1CON
;
2235 unsigned ZCD1INTN
: 1;
2236 unsigned ZCD1INTP
: 1;
2239 unsigned ZCD1POL
: 1;
2240 unsigned ZCD1OUT
: 1;
2242 unsigned ZCD1EN
: 1;
2245 extern __at(0x009F) volatile __ZCD1CONbits_t ZCD1CONbits
;
2247 #define _ZCD1INTN 0x01
2248 #define _ZCD1INTP 0x02
2249 #define _ZCD1POL 0x10
2250 #define _ZCD1OUT 0x20
2251 #define _ZCD1EN 0x80
2253 //==============================================================================
2256 //==============================================================================
2259 extern __at(0x010C) __sfr LATA
;
2273 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
2284 //==============================================================================
2287 //==============================================================================
2290 extern __at(0x010D) __sfr LATB
;
2304 extern __at(0x010D) volatile __LATBbits_t LATBbits
;
2315 //==============================================================================
2318 //==============================================================================
2321 extern __at(0x010E) __sfr LATC
;
2335 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
2346 //==============================================================================
2349 //==============================================================================
2352 extern __at(0x010F) __sfr LATD
;
2366 extern __at(0x010F) volatile __LATDbits_t LATDbits
;
2377 //==============================================================================
2380 //==============================================================================
2383 extern __at(0x0110) __sfr LATE
;
2406 extern __at(0x0110) volatile __LATEbits_t LATEbits
;
2412 //==============================================================================
2415 //==============================================================================
2418 extern __at(0x0111) __sfr CMOUT
;
2422 unsigned MC1OUT
: 1;
2423 unsigned MC2OUT
: 1;
2424 unsigned MC3OUT
: 1;
2425 unsigned MC4OUT
: 1;
2426 unsigned MC5OUT
: 1;
2427 unsigned MC6OUT
: 1;
2428 unsigned MC7OUT
: 1;
2429 unsigned MC80UT
: 1;
2432 extern __at(0x0111) volatile __CMOUTbits_t CMOUTbits
;
2434 #define _MC1OUT 0x01
2435 #define _MC2OUT 0x02
2436 #define _MC3OUT 0x04
2437 #define _MC4OUT 0x08
2438 #define _MC5OUT 0x10
2439 #define _MC6OUT 0x20
2440 #define _MC7OUT 0x40
2441 #define _MC80UT 0x80
2443 //==============================================================================
2446 //==============================================================================
2449 extern __at(0x0112) __sfr CM1CON0
;
2457 unsigned Reserved
: 1;
2467 unsigned C1SYNC
: 1;
2478 extern __at(0x0112) volatile __CM1CON0bits_t CM1CON0bits
;
2480 #define _CM1CON0_SYNC 0x01
2481 #define _CM1CON0_C1SYNC 0x01
2482 #define _CM1CON0_HYS 0x02
2483 #define _CM1CON0_C1HYS 0x02
2484 #define _CM1CON0_Reserved 0x04
2485 #define _CM1CON0_C1SP 0x04
2486 #define _CM1CON0_ZLF 0x08
2487 #define _CM1CON0_C1ZLF 0x08
2488 #define _CM1CON0_POL 0x10
2489 #define _CM1CON0_C1POL 0x10
2490 #define _CM1CON0_OUT 0x40
2491 #define _CM1CON0_C1OUT 0x40
2492 #define _CM1CON0_ON 0x80
2493 #define _CM1CON0_C1ON 0x80
2495 //==============================================================================
2498 //==============================================================================
2501 extern __at(0x0113) __sfr CM1CON1
;
2519 unsigned C1INTN
: 1;
2520 unsigned C1INTP
: 1;
2530 extern __at(0x0113) volatile __CM1CON1bits_t CM1CON1bits
;
2532 #define _CM1CON1_INTN 0x01
2533 #define _CM1CON1_C1INTN 0x01
2534 #define _CM1CON1_INTP 0x02
2535 #define _CM1CON1_C1INTP 0x02
2537 //==============================================================================
2540 //==============================================================================
2543 extern __at(0x0114) __sfr CM1NSEL
;
2549 unsigned C1NCH0
: 1;
2550 unsigned C1NCH1
: 1;
2551 unsigned C1NCH2
: 1;
2552 unsigned C1NCH3
: 1;
2566 extern __at(0x0114) volatile __CM1NSELbits_t CM1NSELbits
;
2568 #define _C1NCH0 0x01
2569 #define _C1NCH1 0x02
2570 #define _C1NCH2 0x04
2571 #define _C1NCH3 0x08
2573 //==============================================================================
2576 //==============================================================================
2579 extern __at(0x0115) __sfr CM1PSEL
;
2597 unsigned C1PCH0
: 1;
2598 unsigned C1PCH1
: 1;
2599 unsigned C1PCH2
: 1;
2600 unsigned C1PCH3
: 1;
2620 extern __at(0x0115) volatile __CM1PSELbits_t CM1PSELbits
;
2623 #define _C1PCH0 0x01
2625 #define _C1PCH1 0x02
2627 #define _C1PCH2 0x04
2629 #define _C1PCH3 0x08
2631 //==============================================================================
2634 //==============================================================================
2637 extern __at(0x0116) __sfr CM2CON0
;
2645 unsigned Reserved
: 1;
2655 unsigned C2SYNC
: 1;
2666 extern __at(0x0116) volatile __CM2CON0bits_t CM2CON0bits
;
2668 #define _CM2CON0_SYNC 0x01
2669 #define _CM2CON0_C2SYNC 0x01
2670 #define _CM2CON0_HYS 0x02
2671 #define _CM2CON0_C2HYS 0x02
2672 #define _CM2CON0_Reserved 0x04
2673 #define _CM2CON0_C2SP 0x04
2674 #define _CM2CON0_ZLF 0x08
2675 #define _CM2CON0_C2ZLF 0x08
2676 #define _CM2CON0_POL 0x10
2677 #define _CM2CON0_C2POL 0x10
2678 #define _CM2CON0_OUT 0x40
2679 #define _CM2CON0_C2OUT 0x40
2680 #define _CM2CON0_ON 0x80
2681 #define _CM2CON0_C2ON 0x80
2683 //==============================================================================
2686 //==============================================================================
2689 extern __at(0x0117) __sfr CM2CON1
;
2707 unsigned C2INTN
: 1;
2708 unsigned C2INTP
: 1;
2718 extern __at(0x0117) volatile __CM2CON1bits_t CM2CON1bits
;
2720 #define _CM2CON1_INTN 0x01
2721 #define _CM2CON1_C2INTN 0x01
2722 #define _CM2CON1_INTP 0x02
2723 #define _CM2CON1_C2INTP 0x02
2725 //==============================================================================
2728 //==============================================================================
2731 extern __at(0x0118) __sfr CM2NSEL
;
2737 unsigned C2NCH0
: 1;
2738 unsigned C2NCH1
: 1;
2739 unsigned C2NCH2
: 1;
2740 unsigned C2NCH3
: 1;
2754 extern __at(0x0118) volatile __CM2NSELbits_t CM2NSELbits
;
2756 #define _C2NCH0 0x01
2757 #define _C2NCH1 0x02
2758 #define _C2NCH2 0x04
2759 #define _C2NCH3 0x08
2761 //==============================================================================
2764 //==============================================================================
2767 extern __at(0x0119) __sfr CM2PSEL
;
2785 unsigned C2PCH0
: 1;
2786 unsigned C2PCH1
: 1;
2787 unsigned C2PCH2
: 1;
2788 unsigned C2PCH3
: 1;
2808 extern __at(0x0119) volatile __CM2PSELbits_t CM2PSELbits
;
2810 #define _CM2PSEL_PCH0 0x01
2811 #define _CM2PSEL_C2PCH0 0x01
2812 #define _CM2PSEL_PCH1 0x02
2813 #define _CM2PSEL_C2PCH1 0x02
2814 #define _CM2PSEL_PCH2 0x04
2815 #define _CM2PSEL_C2PCH2 0x04
2816 #define _CM2PSEL_PCH3 0x08
2817 #define _CM2PSEL_C2PCH3 0x08
2819 //==============================================================================
2822 //==============================================================================
2825 extern __at(0x011A) __sfr CM3CON0
;
2833 unsigned Reserved
: 1;
2843 unsigned C3SYNC
: 1;
2854 extern __at(0x011A) volatile __CM3CON0bits_t CM3CON0bits
;
2856 #define _CM3CON0_SYNC 0x01
2857 #define _CM3CON0_C3SYNC 0x01
2858 #define _CM3CON0_HYS 0x02
2859 #define _CM3CON0_C3HYS 0x02
2860 #define _CM3CON0_Reserved 0x04
2861 #define _CM3CON0_C3SP 0x04
2862 #define _CM3CON0_ZLF 0x08
2863 #define _CM3CON0_C3ZLF 0x08
2864 #define _CM3CON0_POL 0x10
2865 #define _CM3CON0_C3POL 0x10
2866 #define _CM3CON0_OUT 0x40
2867 #define _CM3CON0_C3OUT 0x40
2868 #define _CM3CON0_ON 0x80
2869 #define _CM3CON0_C3ON 0x80
2871 //==============================================================================
2874 //==============================================================================
2877 extern __at(0x011B) __sfr CM3CON1
;
2895 unsigned C3INTN
: 1;
2896 unsigned C3INTP
: 1;
2906 extern __at(0x011B) volatile __CM3CON1bits_t CM3CON1bits
;
2908 #define _CM3CON1_INTN 0x01
2909 #define _CM3CON1_C3INTN 0x01
2910 #define _CM3CON1_INTP 0x02
2911 #define _CM3CON1_C3INTP 0x02
2913 //==============================================================================
2916 //==============================================================================
2919 extern __at(0x011C) __sfr CM3NSEL
;
2925 unsigned C3NCH0
: 1;
2926 unsigned C3NCH1
: 1;
2927 unsigned C3NCH2
: 1;
2928 unsigned C3NCH3
: 1;
2942 extern __at(0x011C) volatile __CM3NSELbits_t CM3NSELbits
;
2944 #define _C3NCH0 0x01
2945 #define _C3NCH1 0x02
2946 #define _C3NCH2 0x04
2947 #define _C3NCH3 0x08
2949 //==============================================================================
2952 //==============================================================================
2955 extern __at(0x011D) __sfr CM3PSEL
;
2973 unsigned C3PCH0
: 1;
2974 unsigned C3PCH1
: 1;
2975 unsigned C3PCH2
: 1;
2976 unsigned C3PCH3
: 1;
2996 extern __at(0x011D) volatile __CM3PSELbits_t CM3PSELbits
;
2998 #define _CM3PSEL_PCH0 0x01
2999 #define _CM3PSEL_C3PCH0 0x01
3000 #define _CM3PSEL_PCH1 0x02
3001 #define _CM3PSEL_C3PCH1 0x02
3002 #define _CM3PSEL_PCH2 0x04
3003 #define _CM3PSEL_C3PCH2 0x04
3004 #define _CM3PSEL_PCH3 0x08
3005 #define _CM3PSEL_C3PCH3 0x08
3007 //==============================================================================
3010 //==============================================================================
3013 extern __at(0x018C) __sfr ANSELA
;
3036 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
3045 //==============================================================================
3048 //==============================================================================
3051 extern __at(0x018D) __sfr ANSELB
;
3074 extern __at(0x018D) volatile __ANSELBbits_t ANSELBbits
;
3083 //==============================================================================
3086 //==============================================================================
3089 extern __at(0x018E) __sfr ANSELC
;
3103 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
3112 //==============================================================================
3115 //==============================================================================
3118 extern __at(0x018F) __sfr ANSELD
;
3132 extern __at(0x018F) volatile __ANSELDbits_t ANSELDbits
;
3143 //==============================================================================
3146 //==============================================================================
3149 extern __at(0x0190) __sfr ANSELE
;
3172 extern __at(0x0190) volatile __ANSELEbits_t ANSELEbits
;
3178 //==============================================================================
3180 extern __at(0x0191) __sfr PMADR
;
3181 extern __at(0x0191) __sfr PMADRL
;
3182 extern __at(0x0192) __sfr PMADRH
;
3183 extern __at(0x0193) __sfr PMDAT
;
3184 extern __at(0x0193) __sfr PMDATL
;
3185 extern __at(0x0194) __sfr PMDATH
;
3187 //==============================================================================
3190 extern __at(0x0195) __sfr PMCON1
;
3204 extern __at(0x0195) volatile __PMCON1bits_t PMCON1bits
;
3214 //==============================================================================
3216 extern __at(0x0196) __sfr PMCON2
;
3218 //==============================================================================
3221 extern __at(0x0197) __sfr VREGCON
;
3225 unsigned reserved
: 1;
3226 unsigned VREGPM
: 1;
3235 extern __at(0x0197) volatile __VREGCONbits_t VREGCONbits
;
3237 #define _reserved 0x01
3238 #define _VREGPM 0x02
3240 //==============================================================================
3242 extern __at(0x0199) __sfr RC1REG
;
3243 extern __at(0x0199) __sfr RCREG
;
3244 extern __at(0x0199) __sfr RCREG1
;
3245 extern __at(0x019A) __sfr TX1REG
;
3246 extern __at(0x019A) __sfr TXREG
;
3247 extern __at(0x019A) __sfr TXREG1
;
3248 extern __at(0x019B) __sfr SP1BRG
;
3249 extern __at(0x019B) __sfr SP1BRGL
;
3250 extern __at(0x019B) __sfr SPBRG
;
3251 extern __at(0x019B) __sfr SPBRG1
;
3252 extern __at(0x019B) __sfr SPBRGL
;
3253 extern __at(0x019C) __sfr SP1BRGH
;
3254 extern __at(0x019C) __sfr SPBRGH
;
3255 extern __at(0x019C) __sfr SPBRGH1
;
3257 //==============================================================================
3260 extern __at(0x019D) __sfr RC1STA
;
3274 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
3285 //==============================================================================
3288 //==============================================================================
3291 extern __at(0x019D) __sfr RCSTA
;
3305 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
3307 #define _RCSTA_RX9D 0x01
3308 #define _RCSTA_OERR 0x02
3309 #define _RCSTA_FERR 0x04
3310 #define _RCSTA_ADDEN 0x08
3311 #define _RCSTA_CREN 0x10
3312 #define _RCSTA_SREN 0x20
3313 #define _RCSTA_RX9 0x40
3314 #define _RCSTA_SPEN 0x80
3316 //==============================================================================
3319 //==============================================================================
3322 extern __at(0x019D) __sfr RCSTA1
;
3336 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
3338 #define _RCSTA1_RX9D 0x01
3339 #define _RCSTA1_OERR 0x02
3340 #define _RCSTA1_FERR 0x04
3341 #define _RCSTA1_ADDEN 0x08
3342 #define _RCSTA1_CREN 0x10
3343 #define _RCSTA1_SREN 0x20
3344 #define _RCSTA1_RX9 0x40
3345 #define _RCSTA1_SPEN 0x80
3347 //==============================================================================
3350 //==============================================================================
3353 extern __at(0x019E) __sfr TX1STA
;
3367 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
3369 #define _TX1STA_TX9D 0x01
3370 #define _TX1STA_TRMT 0x02
3371 #define _TX1STA_BRGH 0x04
3372 #define _TX1STA_SENDB 0x08
3373 #define _TX1STA_SYNC 0x10
3374 #define _TX1STA_TXEN 0x20
3375 #define _TX1STA_TX9 0x40
3376 #define _TX1STA_CSRC 0x80
3378 //==============================================================================
3381 //==============================================================================
3384 extern __at(0x019E) __sfr TXSTA
;
3398 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
3400 #define _TXSTA_TX9D 0x01
3401 #define _TXSTA_TRMT 0x02
3402 #define _TXSTA_BRGH 0x04
3403 #define _TXSTA_SENDB 0x08
3404 #define _TXSTA_SYNC 0x10
3405 #define _TXSTA_TXEN 0x20
3406 #define _TXSTA_TX9 0x40
3407 #define _TXSTA_CSRC 0x80
3409 //==============================================================================
3412 //==============================================================================
3415 extern __at(0x019E) __sfr TXSTA1
;
3429 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
3431 #define _TXSTA1_TX9D 0x01
3432 #define _TXSTA1_TRMT 0x02
3433 #define _TXSTA1_BRGH 0x04
3434 #define _TXSTA1_SENDB 0x08
3435 #define _TXSTA1_SYNC 0x10
3436 #define _TXSTA1_TXEN 0x20
3437 #define _TXSTA1_TX9 0x40
3438 #define _TXSTA1_CSRC 0x80
3440 //==============================================================================
3443 //==============================================================================
3446 extern __at(0x019F) __sfr BAUD1CON
;
3457 unsigned ABDOVF
: 1;
3460 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
3467 #define _ABDOVF 0x80
3469 //==============================================================================
3472 //==============================================================================
3475 extern __at(0x019F) __sfr BAUDCON
;
3486 unsigned ABDOVF
: 1;
3489 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
3491 #define _BAUDCON_ABDEN 0x01
3492 #define _BAUDCON_WUE 0x02
3493 #define _BAUDCON_BRG16 0x08
3494 #define _BAUDCON_SCKP 0x10
3495 #define _BAUDCON_RCIDL 0x40
3496 #define _BAUDCON_ABDOVF 0x80
3498 //==============================================================================
3501 //==============================================================================
3504 extern __at(0x019F) __sfr BAUDCON1
;
3515 unsigned ABDOVF
: 1;
3518 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
3520 #define _BAUDCON1_ABDEN 0x01
3521 #define _BAUDCON1_WUE 0x02
3522 #define _BAUDCON1_BRG16 0x08
3523 #define _BAUDCON1_SCKP 0x10
3524 #define _BAUDCON1_RCIDL 0x40
3525 #define _BAUDCON1_ABDOVF 0x80
3527 //==============================================================================
3530 //==============================================================================
3533 extern __at(0x019F) __sfr BAUDCTL
;
3544 unsigned ABDOVF
: 1;
3547 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
3549 #define _BAUDCTL_ABDEN 0x01
3550 #define _BAUDCTL_WUE 0x02
3551 #define _BAUDCTL_BRG16 0x08
3552 #define _BAUDCTL_SCKP 0x10
3553 #define _BAUDCTL_RCIDL 0x40
3554 #define _BAUDCTL_ABDOVF 0x80
3556 //==============================================================================
3559 //==============================================================================
3562 extern __at(0x019F) __sfr BAUDCTL1
;
3573 unsigned ABDOVF
: 1;
3576 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
3578 #define _BAUDCTL1_ABDEN 0x01
3579 #define _BAUDCTL1_WUE 0x02
3580 #define _BAUDCTL1_BRG16 0x08
3581 #define _BAUDCTL1_SCKP 0x10
3582 #define _BAUDCTL1_RCIDL 0x40
3583 #define _BAUDCTL1_ABDOVF 0x80
3585 //==============================================================================
3588 //==============================================================================
3591 extern __at(0x020C) __sfr WPUA
;
3605 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
3616 //==============================================================================
3619 //==============================================================================
3622 extern __at(0x020D) __sfr WPUB
;
3636 extern __at(0x020D) volatile __WPUBbits_t WPUBbits
;
3647 //==============================================================================
3650 //==============================================================================
3653 extern __at(0x020E) __sfr WPUC
;
3667 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
3678 //==============================================================================
3681 //==============================================================================
3684 extern __at(0x020F) __sfr WPUD
;
3698 extern __at(0x020F) volatile __WPUDbits_t WPUDbits
;
3709 //==============================================================================
3712 //==============================================================================
3715 extern __at(0x0210) __sfr WPUE
;
3738 extern __at(0x0210) volatile __WPUEbits_t WPUEbits
;
3745 //==============================================================================
3748 //==============================================================================
3751 extern __at(0x0211) __sfr SSP1BUF
;
3757 unsigned SSP1BUF0
: 1;
3758 unsigned SSP1BUF1
: 1;
3759 unsigned SSP1BUF2
: 1;
3760 unsigned SSP1BUF3
: 1;
3761 unsigned SSP1BUF4
: 1;
3762 unsigned SSP1BUF5
: 1;
3763 unsigned SSP1BUF6
: 1;
3764 unsigned SSP1BUF7
: 1;
3780 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
3782 #define _SSP1BUF0 0x01
3784 #define _SSP1BUF1 0x02
3786 #define _SSP1BUF2 0x04
3788 #define _SSP1BUF3 0x08
3790 #define _SSP1BUF4 0x10
3792 #define _SSP1BUF5 0x20
3794 #define _SSP1BUF6 0x40
3796 #define _SSP1BUF7 0x80
3799 //==============================================================================
3802 //==============================================================================
3805 extern __at(0x0211) __sfr SSPBUF
;
3811 unsigned SSP1BUF0
: 1;
3812 unsigned SSP1BUF1
: 1;
3813 unsigned SSP1BUF2
: 1;
3814 unsigned SSP1BUF3
: 1;
3815 unsigned SSP1BUF4
: 1;
3816 unsigned SSP1BUF5
: 1;
3817 unsigned SSP1BUF6
: 1;
3818 unsigned SSP1BUF7
: 1;
3834 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
3836 #define _SSPBUF_SSP1BUF0 0x01
3837 #define _SSPBUF_BUF0 0x01
3838 #define _SSPBUF_SSP1BUF1 0x02
3839 #define _SSPBUF_BUF1 0x02
3840 #define _SSPBUF_SSP1BUF2 0x04
3841 #define _SSPBUF_BUF2 0x04
3842 #define _SSPBUF_SSP1BUF3 0x08
3843 #define _SSPBUF_BUF3 0x08
3844 #define _SSPBUF_SSP1BUF4 0x10
3845 #define _SSPBUF_BUF4 0x10
3846 #define _SSPBUF_SSP1BUF5 0x20
3847 #define _SSPBUF_BUF5 0x20
3848 #define _SSPBUF_SSP1BUF6 0x40
3849 #define _SSPBUF_BUF6 0x40
3850 #define _SSPBUF_SSP1BUF7 0x80
3851 #define _SSPBUF_BUF7 0x80
3853 //==============================================================================
3856 //==============================================================================
3859 extern __at(0x0212) __sfr SSP1ADD
;
3865 unsigned SSP1ADD0
: 1;
3866 unsigned SSP1ADD1
: 1;
3867 unsigned SSP1ADD2
: 1;
3868 unsigned SSP1ADD3
: 1;
3869 unsigned SSP1ADD4
: 1;
3870 unsigned SSP1ADD5
: 1;
3871 unsigned SSP1ADD6
: 1;
3872 unsigned SSP1ADD7
: 1;
3888 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
3890 #define _SSP1ADD0 0x01
3892 #define _SSP1ADD1 0x02
3894 #define _SSP1ADD2 0x04
3896 #define _SSP1ADD3 0x08
3898 #define _SSP1ADD4 0x10
3900 #define _SSP1ADD5 0x20
3902 #define _SSP1ADD6 0x40
3904 #define _SSP1ADD7 0x80
3907 //==============================================================================
3910 //==============================================================================
3913 extern __at(0x0212) __sfr SSPADD
;
3919 unsigned SSP1ADD0
: 1;
3920 unsigned SSP1ADD1
: 1;
3921 unsigned SSP1ADD2
: 1;
3922 unsigned SSP1ADD3
: 1;
3923 unsigned SSP1ADD4
: 1;
3924 unsigned SSP1ADD5
: 1;
3925 unsigned SSP1ADD6
: 1;
3926 unsigned SSP1ADD7
: 1;
3942 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
3944 #define _SSPADD_SSP1ADD0 0x01
3945 #define _SSPADD_ADD0 0x01
3946 #define _SSPADD_SSP1ADD1 0x02
3947 #define _SSPADD_ADD1 0x02
3948 #define _SSPADD_SSP1ADD2 0x04
3949 #define _SSPADD_ADD2 0x04
3950 #define _SSPADD_SSP1ADD3 0x08
3951 #define _SSPADD_ADD3 0x08
3952 #define _SSPADD_SSP1ADD4 0x10
3953 #define _SSPADD_ADD4 0x10
3954 #define _SSPADD_SSP1ADD5 0x20
3955 #define _SSPADD_ADD5 0x20
3956 #define _SSPADD_SSP1ADD6 0x40
3957 #define _SSPADD_ADD6 0x40
3958 #define _SSPADD_SSP1ADD7 0x80
3959 #define _SSPADD_ADD7 0x80
3961 //==============================================================================
3964 //==============================================================================
3967 extern __at(0x0213) __sfr SSP1MSK
;
3973 unsigned SSP1MSK0
: 1;
3974 unsigned SSP1MSK1
: 1;
3975 unsigned SSP1MSK2
: 1;
3976 unsigned SSP1MSK3
: 1;
3977 unsigned SSP1MSK4
: 1;
3978 unsigned SSP1MSK5
: 1;
3979 unsigned SSP1MSK6
: 1;
3980 unsigned SSP1MSK7
: 1;
3996 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
3998 #define _SSP1MSK0 0x01
4000 #define _SSP1MSK1 0x02
4002 #define _SSP1MSK2 0x04
4004 #define _SSP1MSK3 0x08
4006 #define _SSP1MSK4 0x10
4008 #define _SSP1MSK5 0x20
4010 #define _SSP1MSK6 0x40
4012 #define _SSP1MSK7 0x80
4015 //==============================================================================
4018 //==============================================================================
4021 extern __at(0x0213) __sfr SSPMSK
;
4027 unsigned SSP1MSK0
: 1;
4028 unsigned SSP1MSK1
: 1;
4029 unsigned SSP1MSK2
: 1;
4030 unsigned SSP1MSK3
: 1;
4031 unsigned SSP1MSK4
: 1;
4032 unsigned SSP1MSK5
: 1;
4033 unsigned SSP1MSK6
: 1;
4034 unsigned SSP1MSK7
: 1;
4050 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
4052 #define _SSPMSK_SSP1MSK0 0x01
4053 #define _SSPMSK_MSK0 0x01
4054 #define _SSPMSK_SSP1MSK1 0x02
4055 #define _SSPMSK_MSK1 0x02
4056 #define _SSPMSK_SSP1MSK2 0x04
4057 #define _SSPMSK_MSK2 0x04
4058 #define _SSPMSK_SSP1MSK3 0x08
4059 #define _SSPMSK_MSK3 0x08
4060 #define _SSPMSK_SSP1MSK4 0x10
4061 #define _SSPMSK_MSK4 0x10
4062 #define _SSPMSK_SSP1MSK5 0x20
4063 #define _SSPMSK_MSK5 0x20
4064 #define _SSPMSK_SSP1MSK6 0x40
4065 #define _SSPMSK_MSK6 0x40
4066 #define _SSPMSK_SSP1MSK7 0x80
4067 #define _SSPMSK_MSK7 0x80
4069 //==============================================================================
4072 //==============================================================================
4075 extern __at(0x0214) __sfr SSP1STAT
;
4081 unsigned R_NOT_W
: 1;
4084 unsigned D_NOT_A
: 1;
4089 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
4093 #define _R_NOT_W 0x04
4096 #define _D_NOT_A 0x20
4100 //==============================================================================
4103 //==============================================================================
4106 extern __at(0x0214) __sfr SSPSTAT
;
4112 unsigned R_NOT_W
: 1;
4115 unsigned D_NOT_A
: 1;
4120 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
4122 #define _SSPSTAT_BF 0x01
4123 #define _SSPSTAT_UA 0x02
4124 #define _SSPSTAT_R_NOT_W 0x04
4125 #define _SSPSTAT_S 0x08
4126 #define _SSPSTAT_P 0x10
4127 #define _SSPSTAT_D_NOT_A 0x20
4128 #define _SSPSTAT_CKE 0x40
4129 #define _SSPSTAT_SMP 0x80
4131 //==============================================================================
4134 //==============================================================================
4137 extern __at(0x0215) __sfr SSP1CON
;
4160 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
4171 //==============================================================================
4174 //==============================================================================
4177 extern __at(0x0215) __sfr SSP1CON1
;
4200 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
4202 #define _SSP1CON1_SSPM0 0x01
4203 #define _SSP1CON1_SSPM1 0x02
4204 #define _SSP1CON1_SSPM2 0x04
4205 #define _SSP1CON1_SSPM3 0x08
4206 #define _SSP1CON1_CKP 0x10
4207 #define _SSP1CON1_SSPEN 0x20
4208 #define _SSP1CON1_SSPOV 0x40
4209 #define _SSP1CON1_WCOL 0x80
4211 //==============================================================================
4214 //==============================================================================
4217 extern __at(0x0215) __sfr SSPCON
;
4240 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
4242 #define _SSPCON_SSPM0 0x01
4243 #define _SSPCON_SSPM1 0x02
4244 #define _SSPCON_SSPM2 0x04
4245 #define _SSPCON_SSPM3 0x08
4246 #define _SSPCON_CKP 0x10
4247 #define _SSPCON_SSPEN 0x20
4248 #define _SSPCON_SSPOV 0x40
4249 #define _SSPCON_WCOL 0x80
4251 //==============================================================================
4254 //==============================================================================
4257 extern __at(0x0215) __sfr SSPCON1
;
4280 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
4282 #define _SSPCON1_SSPM0 0x01
4283 #define _SSPCON1_SSPM1 0x02
4284 #define _SSPCON1_SSPM2 0x04
4285 #define _SSPCON1_SSPM3 0x08
4286 #define _SSPCON1_CKP 0x10
4287 #define _SSPCON1_SSPEN 0x20
4288 #define _SSPCON1_SSPOV 0x40
4289 #define _SSPCON1_WCOL 0x80
4291 //==============================================================================
4294 //==============================================================================
4297 extern __at(0x0216) __sfr SSP1CON2
;
4307 unsigned ACKSTAT
: 1;
4311 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
4319 #define _ACKSTAT 0x40
4322 //==============================================================================
4325 //==============================================================================
4328 extern __at(0x0216) __sfr SSPCON2
;
4338 unsigned ACKSTAT
: 1;
4342 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
4344 #define _SSPCON2_SEN 0x01
4345 #define _SSPCON2_RSEN 0x02
4346 #define _SSPCON2_PEN 0x04
4347 #define _SSPCON2_RCEN 0x08
4348 #define _SSPCON2_ACKEN 0x10
4349 #define _SSPCON2_ACKDT 0x20
4350 #define _SSPCON2_ACKSTAT 0x40
4351 #define _SSPCON2_GCEN 0x80
4353 //==============================================================================
4356 //==============================================================================
4359 extern __at(0x0217) __sfr SSP1CON3
;
4370 unsigned ACKTIM
: 1;
4373 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
4382 #define _ACKTIM 0x80
4384 //==============================================================================
4387 //==============================================================================
4390 extern __at(0x0217) __sfr SSPCON3
;
4401 unsigned ACKTIM
: 1;
4404 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
4406 #define _SSPCON3_DHEN 0x01
4407 #define _SSPCON3_AHEN 0x02
4408 #define _SSPCON3_SBCDE 0x04
4409 #define _SSPCON3_SDAHT 0x08
4410 #define _SSPCON3_BOEN 0x10
4411 #define _SSPCON3_SCIE 0x20
4412 #define _SSPCON3_PCIE 0x40
4413 #define _SSPCON3_ACKTIM 0x80
4415 //==============================================================================
4418 //==============================================================================
4421 extern __at(0x021B) __sfr MD3CON0
;
4439 unsigned MD3BIT
: 1;
4443 unsigned MD3OPOL
: 1;
4444 unsigned MD3OUT
: 1;
4450 extern __at(0x021B) volatile __MD3CON0bits_t MD3CON0bits
;
4452 #define _MD3CON0_BIT 0x01
4453 #define _MD3CON0_MD3BIT 0x01
4454 #define _MD3CON0_OPOL 0x10
4455 #define _MD3CON0_MD3OPOL 0x10
4456 #define _MD3CON0_OUT 0x20
4457 #define _MD3CON0_MD3OUT 0x20
4458 #define _MD3CON0_EN 0x80
4459 #define _MD3CON0_MD3EN 0x80
4461 //==============================================================================
4464 //==============================================================================
4467 extern __at(0x021C) __sfr MD3CON1
;
4473 unsigned CLSYNC
: 1;
4477 unsigned CHSYNC
: 1;
4485 unsigned MD3CLSYNC
: 1;
4486 unsigned MD3CLPOL
: 1;
4489 unsigned MD3CHSYNC
: 1;
4490 unsigned MD3CHPOL
: 1;
4496 extern __at(0x021C) volatile __MD3CON1bits_t MD3CON1bits
;
4498 #define _MD3CON1_CLSYNC 0x01
4499 #define _MD3CON1_MD3CLSYNC 0x01
4500 #define _MD3CON1_CLPOL 0x02
4501 #define _MD3CON1_MD3CLPOL 0x02
4502 #define _MD3CON1_CHSYNC 0x10
4503 #define _MD3CON1_MD3CHSYNC 0x10
4504 #define _MD3CON1_CHPOL 0x20
4505 #define _MD3CON1_MD3CHPOL 0x20
4507 //==============================================================================
4510 //==============================================================================
4513 extern __at(0x021D) __sfr MD3SRC
;
4531 unsigned MD3MS0
: 1;
4532 unsigned MD3MS1
: 1;
4533 unsigned MD3MS2
: 1;
4534 unsigned MD3MS3
: 1;
4535 unsigned MD3MS4
: 1;
4554 extern __at(0x021D) volatile __MD3SRCbits_t MD3SRCbits
;
4556 #define _MD3SRC_MS0 0x01
4557 #define _MD3SRC_MD3MS0 0x01
4558 #define _MD3SRC_MS1 0x02
4559 #define _MD3SRC_MD3MS1 0x02
4560 #define _MD3SRC_MS2 0x04
4561 #define _MD3SRC_MD3MS2 0x04
4562 #define _MD3SRC_MS3 0x08
4563 #define _MD3SRC_MD3MS3 0x08
4564 #define _MD3SRC_MS4 0x10
4565 #define _MD3SRC_MD3MS4 0x10
4567 //==============================================================================
4570 //==============================================================================
4573 extern __at(0x021E) __sfr MD3CARL
;
4591 unsigned MD3CL0
: 1;
4592 unsigned MD3CL1
: 1;
4593 unsigned MD3CL2
: 1;
4594 unsigned MD3CL3
: 1;
4614 extern __at(0x021E) volatile __MD3CARLbits_t MD3CARLbits
;
4616 #define _MD3CARL_CL0 0x01
4617 #define _MD3CARL_MD3CL0 0x01
4618 #define _MD3CARL_CL1 0x02
4619 #define _MD3CARL_MD3CL1 0x02
4620 #define _MD3CARL_CL2 0x04
4621 #define _MD3CARL_MD3CL2 0x04
4622 #define _MD3CARL_CL3 0x08
4623 #define _MD3CARL_MD3CL3 0x08
4624 #define _MD3CARL_CL4 0x10
4626 //==============================================================================
4629 //==============================================================================
4632 extern __at(0x021F) __sfr MD3CARH
;
4650 unsigned MD3CH0
: 1;
4651 unsigned MD3CH1
: 1;
4652 unsigned MD3CH2
: 1;
4653 unsigned MD3CH3
: 1;
4673 extern __at(0x021F) volatile __MD3CARHbits_t MD3CARHbits
;
4675 #define _MD3CARH_CH0 0x01
4676 #define _MD3CARH_MD3CH0 0x01
4677 #define _MD3CARH_CH1 0x02
4678 #define _MD3CARH_MD3CH1 0x02
4679 #define _MD3CARH_CH2 0x04
4680 #define _MD3CARH_MD3CH2 0x04
4681 #define _MD3CARH_CH3 0x08
4682 #define _MD3CARH_MD3CH3 0x08
4683 #define _MD3CARH_CH4 0x10
4685 //==============================================================================
4688 //==============================================================================
4691 extern __at(0x028C) __sfr ODCONA
;
4705 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
4716 //==============================================================================
4719 //==============================================================================
4722 extern __at(0x028D) __sfr ODCONB
;
4736 extern __at(0x028D) volatile __ODCONBbits_t ODCONBbits
;
4747 //==============================================================================
4750 //==============================================================================
4753 extern __at(0x028E) __sfr ODCONC
;
4767 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
4778 //==============================================================================
4781 //==============================================================================
4784 extern __at(0x028F) __sfr ODCOND
;
4798 extern __at(0x028F) volatile __ODCONDbits_t ODCONDbits
;
4809 //==============================================================================
4812 //==============================================================================
4815 extern __at(0x0290) __sfr ODCONE
;
4838 extern __at(0x0290) volatile __ODCONEbits_t ODCONEbits
;
4844 //==============================================================================
4846 extern __at(0x0291) __sfr CCPR1
;
4847 extern __at(0x0291) __sfr CCPR1L
;
4848 extern __at(0x0292) __sfr CCPR1H
;
4850 //==============================================================================
4853 extern __at(0x0293) __sfr CCP1CON
;
4871 unsigned CCP1MODE0
: 1;
4872 unsigned CCP1MODE1
: 1;
4873 unsigned CCP1MODE2
: 1;
4874 unsigned CCP1MODE3
: 1;
4875 unsigned CCP1FMT
: 1;
4876 unsigned CCP1OUT
: 1;
4878 unsigned CCP1EN
: 1;
4883 unsigned CCP1MODE
: 4;
4894 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
4897 #define _CCP1MODE0 0x01
4899 #define _CCP1MODE1 0x02
4901 #define _CCP1MODE2 0x04
4903 #define _CCP1MODE3 0x08
4905 #define _CCP1FMT 0x10
4907 #define _CCP1OUT 0x20
4909 #define _CCP1EN 0x80
4911 //==============================================================================
4914 //==============================================================================
4917 extern __at(0x0294) __sfr CCP1CAP
;
4935 unsigned CCP1CTS0
: 1;
4936 unsigned CCP1CTS1
: 1;
4937 unsigned CCP1CTS2
: 1;
4938 unsigned CCP1CTS3
: 1;
4947 unsigned CCP1CTS
: 4;
4958 extern __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits
;
4961 #define _CCP1CTS0 0x01
4963 #define _CCP1CTS1 0x02
4965 #define _CCP1CTS2 0x04
4967 #define _CCP1CTS3 0x08
4969 //==============================================================================
4971 extern __at(0x0295) __sfr CCPR2
;
4972 extern __at(0x0295) __sfr CCPR2L
;
4973 extern __at(0x0296) __sfr CCPR2H
;
4975 //==============================================================================
4978 extern __at(0x0297) __sfr CCP2CON
;
4996 unsigned CCP2MODE0
: 1;
4997 unsigned CCP2MODE1
: 1;
4998 unsigned CCP2MODE2
: 1;
4999 unsigned CCP2MODE3
: 1;
5000 unsigned CCP2FMT
: 1;
5001 unsigned CCP2OUT
: 1;
5003 unsigned CCP2EN
: 1;
5014 unsigned CCP2MODE
: 4;
5019 extern __at(0x0297) volatile __CCP2CONbits_t CCP2CONbits
;
5021 #define _CCP2CON_MODE0 0x01
5022 #define _CCP2CON_CCP2MODE0 0x01
5023 #define _CCP2CON_MODE1 0x02
5024 #define _CCP2CON_CCP2MODE1 0x02
5025 #define _CCP2CON_MODE2 0x04
5026 #define _CCP2CON_CCP2MODE2 0x04
5027 #define _CCP2CON_MODE3 0x08
5028 #define _CCP2CON_CCP2MODE3 0x08
5029 #define _CCP2CON_FMT 0x10
5030 #define _CCP2CON_CCP2FMT 0x10
5031 #define _CCP2CON_OUT 0x20
5032 #define _CCP2CON_CCP2OUT 0x20
5033 #define _CCP2CON_EN 0x80
5034 #define _CCP2CON_CCP2EN 0x80
5036 //==============================================================================
5039 //==============================================================================
5042 extern __at(0x0298) __sfr CCP2CAP
;
5060 unsigned CCP2CTS0
: 1;
5061 unsigned CCP2CTS1
: 1;
5062 unsigned CCP2CTS2
: 1;
5063 unsigned CCP2CTS3
: 1;
5078 unsigned CCP2CTS
: 4;
5083 extern __at(0x0298) volatile __CCP2CAPbits_t CCP2CAPbits
;
5085 #define _CCP2CAP_CTS0 0x01
5086 #define _CCP2CAP_CCP2CTS0 0x01
5087 #define _CCP2CAP_CTS1 0x02
5088 #define _CCP2CAP_CCP2CTS1 0x02
5089 #define _CCP2CAP_CTS2 0x04
5090 #define _CCP2CAP_CCP2CTS2 0x04
5091 #define _CCP2CAP_CTS3 0x08
5092 #define _CCP2CAP_CCP2CTS3 0x08
5094 //==============================================================================
5096 extern __at(0x0299) __sfr CCPR7
;
5097 extern __at(0x0299) __sfr CCPR7L
;
5098 extern __at(0x029A) __sfr CCPR7H
;
5100 //==============================================================================
5103 extern __at(0x029B) __sfr CCP7CON
;
5121 unsigned CCP7MODE0
: 1;
5122 unsigned CCP7MODE1
: 1;
5123 unsigned CCP7MODE2
: 1;
5124 unsigned CCP7MODE3
: 1;
5125 unsigned CCP7FMT
: 1;
5126 unsigned CCP7OUT
: 1;
5128 unsigned CCP7EN
: 1;
5139 unsigned CCP7MODE
: 4;
5144 extern __at(0x029B) volatile __CCP7CONbits_t CCP7CONbits
;
5146 #define _CCP7CON_MODE0 0x01
5147 #define _CCP7CON_CCP7MODE0 0x01
5148 #define _CCP7CON_MODE1 0x02
5149 #define _CCP7CON_CCP7MODE1 0x02
5150 #define _CCP7CON_MODE2 0x04
5151 #define _CCP7CON_CCP7MODE2 0x04
5152 #define _CCP7CON_MODE3 0x08
5153 #define _CCP7CON_CCP7MODE3 0x08
5154 #define _CCP7CON_FMT 0x10
5155 #define _CCP7CON_CCP7FMT 0x10
5156 #define _CCP7CON_OUT 0x20
5157 #define _CCP7CON_CCP7OUT 0x20
5158 #define _CCP7CON_EN 0x80
5159 #define _CCP7CON_CCP7EN 0x80
5161 //==============================================================================
5164 //==============================================================================
5167 extern __at(0x029C) __sfr CCP7CAP
;
5185 unsigned CCP7CTS0
: 1;
5186 unsigned CCP7CTS1
: 1;
5187 unsigned CCP7CTS2
: 1;
5188 unsigned CCP7CTS3
: 1;
5203 unsigned CCP7CTS
: 4;
5208 extern __at(0x029C) volatile __CCP7CAPbits_t CCP7CAPbits
;
5210 #define _CCP7CAP_CTS0 0x01
5211 #define _CCP7CAP_CCP7CTS0 0x01
5212 #define _CCP7CAP_CTS1 0x02
5213 #define _CCP7CAP_CCP7CTS1 0x02
5214 #define _CCP7CAP_CTS2 0x04
5215 #define _CCP7CAP_CCP7CTS2 0x04
5216 #define _CCP7CAP_CTS3 0x08
5217 #define _CCP7CAP_CCP7CTS3 0x08
5219 //==============================================================================
5222 //==============================================================================
5225 extern __at(0x029E) __sfr CCPTMRS1
;
5231 unsigned C1TSEL0
: 1;
5232 unsigned C1TSEL1
: 1;
5233 unsigned C2TSEL0
: 1;
5234 unsigned C2TSEL1
: 1;
5235 unsigned C7TSEL0
: 1;
5236 unsigned C7TSEL1
: 1;
5243 unsigned C1TSEL
: 2;
5250 unsigned C2TSEL
: 2;
5257 unsigned C7TSEL
: 2;
5262 extern __at(0x029E) volatile __CCPTMRS1bits_t CCPTMRS1bits
;
5264 #define _C1TSEL0 0x01
5265 #define _C1TSEL1 0x02
5266 #define _C2TSEL0 0x04
5267 #define _C2TSEL1 0x08
5268 #define _C7TSEL0 0x10
5269 #define _C7TSEL1 0x20
5271 //==============================================================================
5274 //==============================================================================
5277 extern __at(0x029F) __sfr CCPTMRS2
;
5283 unsigned P3TSEL0
: 1;
5284 unsigned P3TSEL1
: 1;
5285 unsigned P4TSEL0
: 1;
5286 unsigned P4TSEL1
: 1;
5287 unsigned P9TSEL0
: 1;
5288 unsigned P9TSEL1
: 1;
5295 unsigned P3TSEL
: 2;
5302 unsigned P4TSEL
: 2;
5309 unsigned P9TSEL
: 2;
5314 extern __at(0x029F) volatile __CCPTMRS2bits_t CCPTMRS2bits
;
5316 #define _P3TSEL0 0x01
5317 #define _P3TSEL1 0x02
5318 #define _P4TSEL0 0x04
5319 #define _P4TSEL1 0x08
5320 #define _P9TSEL0 0x10
5321 #define _P9TSEL1 0x20
5323 //==============================================================================
5326 //==============================================================================
5329 extern __at(0x030C) __sfr SLRCONA
;
5343 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
5354 //==============================================================================
5357 //==============================================================================
5360 extern __at(0x030D) __sfr SLRCONB
;
5374 extern __at(0x030D) volatile __SLRCONBbits_t SLRCONBbits
;
5385 //==============================================================================
5388 //==============================================================================
5391 extern __at(0x030E) __sfr SLRCONC
;
5405 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
5416 //==============================================================================
5419 //==============================================================================
5422 extern __at(0x030F) __sfr SLRCOND
;
5436 extern __at(0x030F) volatile __SLRCONDbits_t SLRCONDbits
;
5447 //==============================================================================
5450 //==============================================================================
5453 extern __at(0x0310) __sfr SLRCONE
;
5476 extern __at(0x0310) volatile __SLRCONEbits_t SLRCONEbits
;
5482 //==============================================================================
5484 extern __at(0x0311) __sfr CCPR8
;
5485 extern __at(0x0311) __sfr CCPR8L
;
5486 extern __at(0x0312) __sfr CCPR8H
;
5488 //==============================================================================
5491 extern __at(0x0313) __sfr CCP8CON
;
5509 unsigned CCP8MODE0
: 1;
5510 unsigned CCP8MODE1
: 1;
5511 unsigned CCP8MODE2
: 1;
5512 unsigned CCP8MODE3
: 1;
5513 unsigned CCP8FMT
: 1;
5514 unsigned CCP8OUT
: 1;
5516 unsigned CCP8EN
: 1;
5527 unsigned CCP8MODE
: 4;
5532 extern __at(0x0313) volatile __CCP8CONbits_t CCP8CONbits
;
5534 #define _CCP8CON_MODE0 0x01
5535 #define _CCP8CON_CCP8MODE0 0x01
5536 #define _CCP8CON_MODE1 0x02
5537 #define _CCP8CON_CCP8MODE1 0x02
5538 #define _CCP8CON_MODE2 0x04
5539 #define _CCP8CON_CCP8MODE2 0x04
5540 #define _CCP8CON_MODE3 0x08
5541 #define _CCP8CON_CCP8MODE3 0x08
5542 #define _CCP8CON_FMT 0x10
5543 #define _CCP8CON_CCP8FMT 0x10
5544 #define _CCP8CON_OUT 0x20
5545 #define _CCP8CON_CCP8OUT 0x20
5546 #define _CCP8CON_EN 0x80
5547 #define _CCP8CON_CCP8EN 0x80
5549 //==============================================================================
5552 //==============================================================================
5555 extern __at(0x0314) __sfr CCP8CAP
;
5573 unsigned CCP8CTS0
: 1;
5574 unsigned CCP8CTS1
: 1;
5575 unsigned CCP8CTS2
: 1;
5576 unsigned CCP8CTS3
: 1;
5585 unsigned CCP8CTS
: 4;
5596 extern __at(0x0314) volatile __CCP8CAPbits_t CCP8CAPbits
;
5598 #define _CCP8CAP_CTS0 0x01
5599 #define _CCP8CAP_CCP8CTS0 0x01
5600 #define _CCP8CAP_CTS1 0x02
5601 #define _CCP8CAP_CCP8CTS1 0x02
5602 #define _CCP8CAP_CTS2 0x04
5603 #define _CCP8CAP_CCP8CTS2 0x04
5604 #define _CCP8CAP_CTS3 0x08
5605 #define _CCP8CAP_CCP8CTS3 0x08
5607 //==============================================================================
5610 //==============================================================================
5613 extern __at(0x0315) __sfr MD1CON0
;
5631 unsigned MD1BIT
: 1;
5635 unsigned MD1OPOL
: 1;
5636 unsigned MD1OUT
: 1;
5642 extern __at(0x0315) volatile __MD1CON0bits_t MD1CON0bits
;
5644 #define _MD1CON0_BIT 0x01
5645 #define _MD1CON0_MD1BIT 0x01
5646 #define _MD1CON0_OPOL 0x10
5647 #define _MD1CON0_MD1OPOL 0x10
5648 #define _MD1CON0_OUT 0x20
5649 #define _MD1CON0_MD1OUT 0x20
5650 #define _MD1CON0_EN 0x80
5651 #define _MD1CON0_MD1EN 0x80
5653 //==============================================================================
5656 //==============================================================================
5659 extern __at(0x0316) __sfr MD1CON1
;
5665 unsigned CLSYNC
: 1;
5669 unsigned CHSYNC
: 1;
5677 unsigned MD1CLSYNC
: 1;
5678 unsigned MD1CLPOL
: 1;
5681 unsigned MD1CHSYNC
: 1;
5682 unsigned MD1CHPOL
: 1;
5688 extern __at(0x0316) volatile __MD1CON1bits_t MD1CON1bits
;
5690 #define _CLSYNC 0x01
5691 #define _MD1CLSYNC 0x01
5693 #define _MD1CLPOL 0x02
5694 #define _CHSYNC 0x10
5695 #define _MD1CHSYNC 0x10
5697 #define _MD1CHPOL 0x20
5699 //==============================================================================
5702 //==============================================================================
5705 extern __at(0x0317) __sfr MD1SRC
;
5723 unsigned MD1MS0
: 1;
5724 unsigned MD1MS1
: 1;
5725 unsigned MD1MS2
: 1;
5726 unsigned MD1MS3
: 1;
5727 unsigned MD1MS4
: 1;
5746 extern __at(0x0317) volatile __MD1SRCbits_t MD1SRCbits
;
5749 #define _MD1MS0 0x01
5751 #define _MD1MS1 0x02
5753 #define _MD1MS2 0x04
5755 #define _MD1MS3 0x08
5757 #define _MD1MS4 0x10
5759 //==============================================================================
5762 //==============================================================================
5765 extern __at(0x0318) __sfr MD1CARL
;
5783 unsigned MD1CL0
: 1;
5784 unsigned MD1CL1
: 1;
5785 unsigned MD1CL2
: 1;
5786 unsigned MD1CL3
: 1;
5806 extern __at(0x0318) volatile __MD1CARLbits_t MD1CARLbits
;
5809 #define _MD1CL0 0x01
5811 #define _MD1CL1 0x02
5813 #define _MD1CL2 0x04
5815 #define _MD1CL3 0x08
5818 //==============================================================================
5821 //==============================================================================
5824 extern __at(0x0319) __sfr MD1CARH
;
5842 unsigned MD1CH0
: 1;
5843 unsigned MD1CH1
: 1;
5844 unsigned MD1CH2
: 1;
5845 unsigned MD1CH3
: 1;
5865 extern __at(0x0319) volatile __MD1CARHbits_t MD1CARHbits
;
5868 #define _MD1CH0 0x01
5870 #define _MD1CH1 0x02
5872 #define _MD1CH2 0x04
5874 #define _MD1CH3 0x08
5877 //==============================================================================
5880 //==============================================================================
5883 extern __at(0x031B) __sfr MD2CON0
;
5901 unsigned MD2BIT
: 1;
5905 unsigned MD2OPOL
: 1;
5906 unsigned MD2OUT
: 1;
5912 extern __at(0x031B) volatile __MD2CON0bits_t MD2CON0bits
;
5914 #define _MD2CON0_BIT 0x01
5915 #define _MD2CON0_MD2BIT 0x01
5916 #define _MD2CON0_OPOL 0x10
5917 #define _MD2CON0_MD2OPOL 0x10
5918 #define _MD2CON0_OUT 0x20
5919 #define _MD2CON0_MD2OUT 0x20
5920 #define _MD2CON0_EN 0x80
5921 #define _MD2CON0_MD2EN 0x80
5923 //==============================================================================
5926 //==============================================================================
5929 extern __at(0x031C) __sfr MD2CON1
;
5935 unsigned CLSYNC
: 1;
5939 unsigned CHSYNC
: 1;
5947 unsigned MD2CLSYNC
: 1;
5948 unsigned MD2CLPOL
: 1;
5951 unsigned MD2CHSYNC
: 1;
5952 unsigned MD2CHPOL
: 1;
5958 extern __at(0x031C) volatile __MD2CON1bits_t MD2CON1bits
;
5960 #define _MD2CON1_CLSYNC 0x01
5961 #define _MD2CON1_MD2CLSYNC 0x01
5962 #define _MD2CON1_CLPOL 0x02
5963 #define _MD2CON1_MD2CLPOL 0x02
5964 #define _MD2CON1_CHSYNC 0x10
5965 #define _MD2CON1_MD2CHSYNC 0x10
5966 #define _MD2CON1_CHPOL 0x20
5967 #define _MD2CON1_MD2CHPOL 0x20
5969 //==============================================================================
5972 //==============================================================================
5975 extern __at(0x031D) __sfr MD2SRC
;
5993 unsigned MD2MS0
: 1;
5994 unsigned MD2MS1
: 1;
5995 unsigned MD2MS2
: 1;
5996 unsigned MD2MS3
: 1;
5997 unsigned MD2MS4
: 1;
6016 extern __at(0x031D) volatile __MD2SRCbits_t MD2SRCbits
;
6018 #define _MD2SRC_MS0 0x01
6019 #define _MD2SRC_MD2MS0 0x01
6020 #define _MD2SRC_MS1 0x02
6021 #define _MD2SRC_MD2MS1 0x02
6022 #define _MD2SRC_MS2 0x04
6023 #define _MD2SRC_MD2MS2 0x04
6024 #define _MD2SRC_MS3 0x08
6025 #define _MD2SRC_MD2MS3 0x08
6026 #define _MD2SRC_MS4 0x10
6027 #define _MD2SRC_MD2MS4 0x10
6029 //==============================================================================
6032 //==============================================================================
6035 extern __at(0x031E) __sfr MD2CARL
;
6053 unsigned MD2CL0
: 1;
6054 unsigned MD2CL1
: 1;
6055 unsigned MD2CL2
: 1;
6056 unsigned MD2CL3
: 1;
6076 extern __at(0x031E) volatile __MD2CARLbits_t MD2CARLbits
;
6078 #define _MD2CARL_CL0 0x01
6079 #define _MD2CARL_MD2CL0 0x01
6080 #define _MD2CARL_CL1 0x02
6081 #define _MD2CARL_MD2CL1 0x02
6082 #define _MD2CARL_CL2 0x04
6083 #define _MD2CARL_MD2CL2 0x04
6084 #define _MD2CARL_CL3 0x08
6085 #define _MD2CARL_MD2CL3 0x08
6086 #define _MD2CARL_CL4 0x10
6088 //==============================================================================
6091 //==============================================================================
6094 extern __at(0x031F) __sfr MD2CARH
;
6112 unsigned MD2CH0
: 1;
6113 unsigned MD2CH1
: 1;
6114 unsigned MD2CH2
: 1;
6115 unsigned MD2CH3
: 1;
6135 extern __at(0x031F) volatile __MD2CARHbits_t MD2CARHbits
;
6137 #define _MD2CARH_CH0 0x01
6138 #define _MD2CARH_MD2CH0 0x01
6139 #define _MD2CARH_CH1 0x02
6140 #define _MD2CARH_MD2CH1 0x02
6141 #define _MD2CARH_CH2 0x04
6142 #define _MD2CARH_MD2CH2 0x04
6143 #define _MD2CARH_CH3 0x08
6144 #define _MD2CARH_MD2CH3 0x08
6145 #define _MD2CARH_CH4 0x10
6147 //==============================================================================
6150 //==============================================================================
6153 extern __at(0x038C) __sfr INLVLA
;
6159 unsigned INLVLA0
: 1;
6160 unsigned INLVLA1
: 1;
6161 unsigned INLVLA2
: 1;
6162 unsigned INLVLA3
: 1;
6163 unsigned INLVLA4
: 1;
6164 unsigned INLVLA5
: 1;
6165 unsigned INLVA6
: 1;
6166 unsigned INLVA7
: 1;
6171 unsigned INLVLA
: 6;
6176 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
6178 #define _INLVLA0 0x01
6179 #define _INLVLA1 0x02
6180 #define _INLVLA2 0x04
6181 #define _INLVLA3 0x08
6182 #define _INLVLA4 0x10
6183 #define _INLVLA5 0x20
6184 #define _INLVA6 0x40
6185 #define _INLVA7 0x80
6187 //==============================================================================
6190 //==============================================================================
6193 extern __at(0x038D) __sfr INLVLB
;
6199 unsigned INLVB0
: 1;
6200 unsigned INLVB1
: 1;
6201 unsigned INLVB2
: 1;
6202 unsigned INLVB3
: 1;
6203 unsigned INLVLB4
: 1;
6204 unsigned INLVLB5
: 1;
6205 unsigned INLVLB6
: 1;
6206 unsigned INLVLB7
: 1;
6216 extern __at(0x038D) volatile __INLVLBbits_t INLVLBbits
;
6218 #define _INLVB0 0x01
6219 #define _INLVB1 0x02
6220 #define _INLVB2 0x04
6221 #define _INLVB3 0x08
6222 #define _INLVLB4 0x10
6223 #define _INLVLB5 0x20
6224 #define _INLVLB6 0x40
6225 #define _INLVLB7 0x80
6227 //==============================================================================
6230 //==============================================================================
6233 extern __at(0x038E) __sfr INLVLC
;
6237 unsigned INLVLC0
: 1;
6238 unsigned INLVLC1
: 1;
6239 unsigned INLVLC2
: 1;
6240 unsigned INLVLC3
: 1;
6241 unsigned INLVLC4
: 1;
6242 unsigned INLVLC5
: 1;
6243 unsigned INLVLC6
: 1;
6244 unsigned INLVLC7
: 1;
6247 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
6249 #define _INLVLC0 0x01
6250 #define _INLVLC1 0x02
6251 #define _INLVLC2 0x04
6252 #define _INLVLC3 0x08
6253 #define _INLVLC4 0x10
6254 #define _INLVLC5 0x20
6255 #define _INLVLC6 0x40
6256 #define _INLVLC7 0x80
6258 //==============================================================================
6261 //==============================================================================
6264 extern __at(0x038F) __sfr INLVLD
;
6268 unsigned INLVLD0
: 1;
6269 unsigned INLVLD1
: 1;
6270 unsigned INLVLD2
: 1;
6271 unsigned INLVLD3
: 1;
6272 unsigned INLVLD4
: 1;
6273 unsigned INLVLD5
: 1;
6274 unsigned INLVLD6
: 1;
6275 unsigned INLVLD7
: 1;
6278 extern __at(0x038F) volatile __INLVLDbits_t INLVLDbits
;
6280 #define _INLVLD0 0x01
6281 #define _INLVLD1 0x02
6282 #define _INLVLD2 0x04
6283 #define _INLVLD3 0x08
6284 #define _INLVLD4 0x10
6285 #define _INLVLD5 0x20
6286 #define _INLVLD6 0x40
6287 #define _INLVLD7 0x80
6289 //==============================================================================
6292 //==============================================================================
6295 extern __at(0x0390) __sfr INLVE
;
6301 unsigned INLVE0
: 1;
6302 unsigned INLVE1
: 1;
6303 unsigned INLVE2
: 1;
6304 unsigned INLVE3
: 1;
6318 extern __at(0x0390) volatile __INLVEbits_t INLVEbits
;
6320 #define _INLVE0 0x01
6321 #define _INLVE1 0x02
6322 #define _INLVE2 0x04
6323 #define _INLVE3 0x08
6325 //==============================================================================
6328 //==============================================================================
6331 extern __at(0x0391) __sfr IOCAP
;
6335 unsigned IOCAP0
: 1;
6336 unsigned IOCAP1
: 1;
6337 unsigned IOCAP2
: 1;
6338 unsigned IOCAP3
: 1;
6339 unsigned IOCAP4
: 1;
6340 unsigned IOCAP5
: 1;
6341 unsigned IOCAP6
: 1;
6342 unsigned IOCAP7
: 1;
6345 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
6347 #define _IOCAP0 0x01
6348 #define _IOCAP1 0x02
6349 #define _IOCAP2 0x04
6350 #define _IOCAP3 0x08
6351 #define _IOCAP4 0x10
6352 #define _IOCAP5 0x20
6353 #define _IOCAP6 0x40
6354 #define _IOCAP7 0x80
6356 //==============================================================================
6359 //==============================================================================
6362 extern __at(0x0392) __sfr IOCAN
;
6366 unsigned IOCAN0
: 1;
6367 unsigned IOCAN1
: 1;
6368 unsigned IOCAN2
: 1;
6369 unsigned IOCAN3
: 1;
6370 unsigned IOCAN4
: 1;
6371 unsigned IOCAN5
: 1;
6372 unsigned IOCAN6
: 1;
6373 unsigned IOCAN7
: 1;
6376 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
6378 #define _IOCAN0 0x01
6379 #define _IOCAN1 0x02
6380 #define _IOCAN2 0x04
6381 #define _IOCAN3 0x08
6382 #define _IOCAN4 0x10
6383 #define _IOCAN5 0x20
6384 #define _IOCAN6 0x40
6385 #define _IOCAN7 0x80
6387 //==============================================================================
6390 //==============================================================================
6393 extern __at(0x0393) __sfr IOCAF
;
6397 unsigned IOCAF0
: 1;
6398 unsigned IOCAF1
: 1;
6399 unsigned IOCAF2
: 1;
6400 unsigned IOCAF3
: 1;
6401 unsigned IOCAF4
: 1;
6402 unsigned IOCAF5
: 1;
6403 unsigned IOCAF6
: 1;
6404 unsigned IOCAF7
: 1;
6407 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
6409 #define _IOCAF0 0x01
6410 #define _IOCAF1 0x02
6411 #define _IOCAF2 0x04
6412 #define _IOCAF3 0x08
6413 #define _IOCAF4 0x10
6414 #define _IOCAF5 0x20
6415 #define _IOCAF6 0x40
6416 #define _IOCAF7 0x80
6418 //==============================================================================
6421 //==============================================================================
6424 extern __at(0x0394) __sfr IOCBP
;
6428 unsigned IOCBP0
: 1;
6429 unsigned IOCBP1
: 1;
6430 unsigned IOCBP2
: 1;
6431 unsigned IOCBP3
: 1;
6432 unsigned IOCBP4
: 1;
6433 unsigned IOCBP5
: 1;
6434 unsigned IOCBP6
: 1;
6435 unsigned IOCBP7
: 1;
6438 extern __at(0x0394) volatile __IOCBPbits_t IOCBPbits
;
6440 #define _IOCBP0 0x01
6441 #define _IOCBP1 0x02
6442 #define _IOCBP2 0x04
6443 #define _IOCBP3 0x08
6444 #define _IOCBP4 0x10
6445 #define _IOCBP5 0x20
6446 #define _IOCBP6 0x40
6447 #define _IOCBP7 0x80
6449 //==============================================================================
6452 //==============================================================================
6455 extern __at(0x0395) __sfr IOCBN
;
6459 unsigned IOCBN0
: 1;
6460 unsigned IOCBN1
: 1;
6461 unsigned IOCBN2
: 1;
6462 unsigned IOCBN3
: 1;
6463 unsigned IOCBN4
: 1;
6464 unsigned IOCBN5
: 1;
6465 unsigned IOCBN6
: 1;
6466 unsigned IOCBN7
: 1;
6469 extern __at(0x0395) volatile __IOCBNbits_t IOCBNbits
;
6471 #define _IOCBN0 0x01
6472 #define _IOCBN1 0x02
6473 #define _IOCBN2 0x04
6474 #define _IOCBN3 0x08
6475 #define _IOCBN4 0x10
6476 #define _IOCBN5 0x20
6477 #define _IOCBN6 0x40
6478 #define _IOCBN7 0x80
6480 //==============================================================================
6483 //==============================================================================
6486 extern __at(0x0396) __sfr IOCBF
;
6490 unsigned IOCBF0
: 1;
6491 unsigned IOCBF1
: 1;
6492 unsigned IOCBF2
: 1;
6493 unsigned IOCBF3
: 1;
6494 unsigned IOCBF4
: 1;
6495 unsigned IOCBF5
: 1;
6496 unsigned IOCBF6
: 1;
6497 unsigned IOCBF7
: 1;
6500 extern __at(0x0396) volatile __IOCBFbits_t IOCBFbits
;
6502 #define _IOCBF0 0x01
6503 #define _IOCBF1 0x02
6504 #define _IOCBF2 0x04
6505 #define _IOCBF3 0x08
6506 #define _IOCBF4 0x10
6507 #define _IOCBF5 0x20
6508 #define _IOCBF6 0x40
6509 #define _IOCBF7 0x80
6511 //==============================================================================
6514 //==============================================================================
6517 extern __at(0x0397) __sfr IOCCP
;
6521 unsigned IOCCP0
: 1;
6522 unsigned IOCCP1
: 1;
6523 unsigned IOCCP2
: 1;
6524 unsigned IOCCP3
: 1;
6525 unsigned IOCCP4
: 1;
6526 unsigned IOCCP5
: 1;
6527 unsigned IOCCP6
: 1;
6528 unsigned IOCCP7
: 1;
6531 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
6533 #define _IOCCP0 0x01
6534 #define _IOCCP1 0x02
6535 #define _IOCCP2 0x04
6536 #define _IOCCP3 0x08
6537 #define _IOCCP4 0x10
6538 #define _IOCCP5 0x20
6539 #define _IOCCP6 0x40
6540 #define _IOCCP7 0x80
6542 //==============================================================================
6545 //==============================================================================
6548 extern __at(0x0398) __sfr IOCCN
;
6552 unsigned IOCCN0
: 1;
6553 unsigned IOCCN1
: 1;
6554 unsigned IOCCN2
: 1;
6555 unsigned IOCCN3
: 1;
6556 unsigned IOCCN4
: 1;
6557 unsigned IOCCN5
: 1;
6558 unsigned IOCCN6
: 1;
6559 unsigned IOCCN7
: 1;
6562 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
6564 #define _IOCCN0 0x01
6565 #define _IOCCN1 0x02
6566 #define _IOCCN2 0x04
6567 #define _IOCCN3 0x08
6568 #define _IOCCN4 0x10
6569 #define _IOCCN5 0x20
6570 #define _IOCCN6 0x40
6571 #define _IOCCN7 0x80
6573 //==============================================================================
6576 //==============================================================================
6579 extern __at(0x0399) __sfr IOCCF
;
6583 unsigned IOCCF0
: 1;
6584 unsigned IOCCF1
: 1;
6585 unsigned IOCCF2
: 1;
6586 unsigned IOCCF3
: 1;
6587 unsigned IOCCF4
: 1;
6588 unsigned IOCCF5
: 1;
6589 unsigned IOCCF6
: 1;
6590 unsigned IOCCF7
: 1;
6593 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
6595 #define _IOCCF0 0x01
6596 #define _IOCCF1 0x02
6597 #define _IOCCF2 0x04
6598 #define _IOCCF3 0x08
6599 #define _IOCCF4 0x10
6600 #define _IOCCF5 0x20
6601 #define _IOCCF6 0x40
6602 #define _IOCCF7 0x80
6604 //==============================================================================
6607 //==============================================================================
6610 extern __at(0x039D) __sfr IOCEP
;
6617 unsigned IOCEP3
: 1;
6624 extern __at(0x039D) volatile __IOCEPbits_t IOCEPbits
;
6626 #define _IOCEP3 0x08
6628 //==============================================================================
6631 //==============================================================================
6634 extern __at(0x039E) __sfr IOCEN
;
6641 unsigned IOCEN3
: 1;
6648 extern __at(0x039E) volatile __IOCENbits_t IOCENbits
;
6650 #define _IOCEN3 0x08
6652 //==============================================================================
6655 //==============================================================================
6658 extern __at(0x039F) __sfr IOCEF
;
6665 unsigned IOCEF3
: 1;
6672 extern __at(0x039F) volatile __IOCEFbits_t IOCEFbits
;
6674 #define _IOCEF3 0x08
6676 //==============================================================================
6679 //==============================================================================
6682 extern __at(0x040D) __sfr HIDRVB
;
6705 extern __at(0x040D) volatile __HIDRVBbits_t HIDRVBbits
;
6710 //==============================================================================
6712 extern __at(0x040F) __sfr TMR5
;
6713 extern __at(0x040F) __sfr TMR5L
;
6714 extern __at(0x0410) __sfr TMR5H
;
6716 //==============================================================================
6719 extern __at(0x0411) __sfr T5CON
;
6727 unsigned NOT_SYNC
: 1;
6740 unsigned SOSCEN
: 1;
6741 unsigned T5CKPS0
: 1;
6742 unsigned T5CKPS1
: 1;
6749 unsigned TMR5ON
: 1;
6751 unsigned NOT_T5SYNC
: 1;
6752 unsigned T5OSCEN
: 1;
6755 unsigned TMR5CS0
: 1;
6756 unsigned TMR5CS1
: 1;
6781 unsigned T5CKPS
: 2;
6794 unsigned TMR5CS
: 2;
6804 extern __at(0x0411) volatile __T5CONbits_t T5CONbits
;
6806 #define _T5CON_ON 0x01
6807 #define _T5CON_TMRON 0x01
6808 #define _T5CON_TMR5ON 0x01
6809 #define _T5CON_T5ON 0x01
6810 #define _T5CON_NOT_SYNC 0x04
6811 #define _T5CON_SYNC 0x04
6812 #define _T5CON_NOT_T5SYNC 0x04
6813 #define _T5CON_OSCEN 0x08
6814 #define _T5CON_SOSCEN 0x08
6815 #define _T5CON_T5OSCEN 0x08
6816 #define _T5CON_CKPS0 0x10
6817 #define _T5CON_T5CKPS0 0x10
6818 #define _T5CON_CKPS1 0x20
6819 #define _T5CON_T5CKPS1 0x20
6820 #define _T5CON_CS0 0x40
6821 #define _T5CON_T5CS0 0x40
6822 #define _T5CON_TMR5CS0 0x40
6823 #define _T5CON_CS1 0x80
6824 #define _T5CON_T5CS1 0x80
6825 #define _T5CON_TMR5CS1 0x80
6827 //==============================================================================
6830 //==============================================================================
6833 extern __at(0x0412) __sfr T5GCON
;
6842 unsigned GGO_NOT_DONE
: 1;
6851 unsigned T5GSS0
: 1;
6852 unsigned T5GSS1
: 1;
6853 unsigned T5GVAL
: 1;
6854 unsigned T5GGO_NOT_DONE
: 1;
6855 unsigned T5GSPM
: 1;
6857 unsigned T5GPOL
: 1;
6870 unsigned TMR5GE
: 1;
6886 extern __at(0x0412) volatile __T5GCONbits_t T5GCONbits
;
6888 #define _T5GCON_GSS0 0x01
6889 #define _T5GCON_T5GSS0 0x01
6890 #define _T5GCON_GSS1 0x02
6891 #define _T5GCON_T5GSS1 0x02
6892 #define _T5GCON_GVAL 0x04
6893 #define _T5GCON_T5GVAL 0x04
6894 #define _T5GCON_GGO_NOT_DONE 0x08
6895 #define _T5GCON_T5GGO_NOT_DONE 0x08
6896 #define _T5GCON_GSPM 0x10
6897 #define _T5GCON_T5GSPM 0x10
6898 #define _T5GCON_GTM 0x20
6899 #define _T5GCON_T5GTM 0x20
6900 #define _T5GCON_GPOL 0x40
6901 #define _T5GCON_T5GPOL 0x40
6902 #define _T5GCON_GE 0x80
6903 #define _T5GCON_T5GE 0x80
6904 #define _T5GCON_TMR5GE 0x80
6906 //==============================================================================
6908 extern __at(0x0413) __sfr T4TMR
;
6909 extern __at(0x0413) __sfr TMR4
;
6910 extern __at(0x0414) __sfr PR4
;
6911 extern __at(0x0414) __sfr T4PR
;
6913 //==============================================================================
6916 extern __at(0x0415) __sfr T4CON
;
6922 unsigned OUTPS0
: 1;
6923 unsigned OUTPS1
: 1;
6924 unsigned OUTPS2
: 1;
6925 unsigned OUTPS3
: 1;
6934 unsigned T4OUTPS0
: 1;
6935 unsigned T4OUTPS1
: 1;
6936 unsigned T4OUTPS2
: 1;
6937 unsigned T4OUTPS3
: 1;
6938 unsigned T4CKPS0
: 1;
6939 unsigned T4CKPS1
: 1;
6940 unsigned T4CKPS2
: 1;
6953 unsigned TMR4ON
: 1;
6964 unsigned T4OUTPS
: 4;
6978 unsigned T4CKPS
: 3;
6983 extern __at(0x0415) volatile __T4CONbits_t T4CONbits
;
6985 #define _T4CON_OUTPS0 0x01
6986 #define _T4CON_T4OUTPS0 0x01
6987 #define _T4CON_OUTPS1 0x02
6988 #define _T4CON_T4OUTPS1 0x02
6989 #define _T4CON_OUTPS2 0x04
6990 #define _T4CON_T4OUTPS2 0x04
6991 #define _T4CON_OUTPS3 0x08
6992 #define _T4CON_T4OUTPS3 0x08
6993 #define _T4CON_CKPS0 0x10
6994 #define _T4CON_T4CKPS0 0x10
6995 #define _T4CON_CKPS1 0x20
6996 #define _T4CON_T4CKPS1 0x20
6997 #define _T4CON_CKPS2 0x40
6998 #define _T4CON_T4CKPS2 0x40
6999 #define _T4CON_ON 0x80
7000 #define _T4CON_T4ON 0x80
7001 #define _T4CON_TMR4ON 0x80
7003 //==============================================================================
7006 //==============================================================================
7009 extern __at(0x0416) __sfr T4HLT
;
7020 unsigned CKSYNC
: 1;
7027 unsigned T4MODE0
: 1;
7028 unsigned T4MODE1
: 1;
7029 unsigned T4MODE2
: 1;
7030 unsigned T4MODE3
: 1;
7031 unsigned T4MODE4
: 1;
7032 unsigned T4CKSYNC
: 1;
7033 unsigned T4CKPOL
: 1;
7034 unsigned T4PSYNC
: 1;
7039 unsigned T4MODE
: 5;
7050 extern __at(0x0416) volatile __T4HLTbits_t T4HLTbits
;
7052 #define _T4HLT_MODE0 0x01
7053 #define _T4HLT_T4MODE0 0x01
7054 #define _T4HLT_MODE1 0x02
7055 #define _T4HLT_T4MODE1 0x02
7056 #define _T4HLT_MODE2 0x04
7057 #define _T4HLT_T4MODE2 0x04
7058 #define _T4HLT_MODE3 0x08
7059 #define _T4HLT_T4MODE3 0x08
7060 #define _T4HLT_MODE4 0x10
7061 #define _T4HLT_T4MODE4 0x10
7062 #define _T4HLT_CKSYNC 0x20
7063 #define _T4HLT_T4CKSYNC 0x20
7064 #define _T4HLT_CKPOL 0x40
7065 #define _T4HLT_T4CKPOL 0x40
7066 #define _T4HLT_PSYNC 0x80
7067 #define _T4HLT_T4PSYNC 0x80
7069 //==============================================================================
7072 //==============================================================================
7075 extern __at(0x0417) __sfr T4CLKCON
;
7116 extern __at(0x0417) volatile __T4CLKCONbits_t T4CLKCONbits
;
7118 #define _T4CLKCON_CS0 0x01
7119 #define _T4CLKCON_T4CS0 0x01
7120 #define _T4CLKCON_CS1 0x02
7121 #define _T4CLKCON_T4CS1 0x02
7122 #define _T4CLKCON_CS2 0x04
7123 #define _T4CLKCON_T4CS2 0x04
7124 #define _T4CLKCON_CS3 0x08
7125 #define _T4CLKCON_T4CS3 0x08
7127 //==============================================================================
7130 //==============================================================================
7133 extern __at(0x0418) __sfr T4RST
;
7151 unsigned T4RSEL0
: 1;
7152 unsigned T4RSEL1
: 1;
7153 unsigned T4RSEL2
: 1;
7154 unsigned T4RSEL3
: 1;
7155 unsigned T4RSEL4
: 1;
7169 unsigned T4RSEL
: 5;
7174 extern __at(0x0418) volatile __T4RSTbits_t T4RSTbits
;
7176 #define _T4RST_RSEL0 0x01
7177 #define _T4RST_T4RSEL0 0x01
7178 #define _T4RST_RSEL1 0x02
7179 #define _T4RST_T4RSEL1 0x02
7180 #define _T4RST_RSEL2 0x04
7181 #define _T4RST_T4RSEL2 0x04
7182 #define _T4RST_RSEL3 0x08
7183 #define _T4RST_T4RSEL3 0x08
7184 #define _T4RST_RSEL4 0x10
7185 #define _T4RST_T4RSEL4 0x10
7187 //==============================================================================
7189 extern __at(0x041A) __sfr T6TMR
;
7190 extern __at(0x041A) __sfr TMR6
;
7191 extern __at(0x041B) __sfr PR6
;
7192 extern __at(0x041B) __sfr T6PR
;
7194 //==============================================================================
7197 extern __at(0x041C) __sfr T6CON
;
7203 unsigned OUTPS0
: 1;
7204 unsigned OUTPS1
: 1;
7205 unsigned OUTPS2
: 1;
7206 unsigned OUTPS3
: 1;
7215 unsigned T6OUTPS0
: 1;
7216 unsigned T6OUTPS1
: 1;
7217 unsigned T6OUTPS2
: 1;
7218 unsigned T6OUTPS3
: 1;
7219 unsigned T6CKPS0
: 1;
7220 unsigned T6CKPS1
: 1;
7221 unsigned T6CKPS2
: 1;
7234 unsigned TMR6ON
: 1;
7239 unsigned T6OUTPS
: 4;
7252 unsigned T6CKPS
: 3;
7264 extern __at(0x041C) volatile __T6CONbits_t T6CONbits
;
7266 #define _T6CON_OUTPS0 0x01
7267 #define _T6CON_T6OUTPS0 0x01
7268 #define _T6CON_OUTPS1 0x02
7269 #define _T6CON_T6OUTPS1 0x02
7270 #define _T6CON_OUTPS2 0x04
7271 #define _T6CON_T6OUTPS2 0x04
7272 #define _T6CON_OUTPS3 0x08
7273 #define _T6CON_T6OUTPS3 0x08
7274 #define _T6CON_CKPS0 0x10
7275 #define _T6CON_T6CKPS0 0x10
7276 #define _T6CON_CKPS1 0x20
7277 #define _T6CON_T6CKPS1 0x20
7278 #define _T6CON_CKPS2 0x40
7279 #define _T6CON_T6CKPS2 0x40
7280 #define _T6CON_ON 0x80
7281 #define _T6CON_T6ON 0x80
7282 #define _T6CON_TMR6ON 0x80
7284 //==============================================================================
7287 //==============================================================================
7290 extern __at(0x041D) __sfr T6HLT
;
7301 unsigned CKSYNC
: 1;
7308 unsigned T6MODE0
: 1;
7309 unsigned T6MODE1
: 1;
7310 unsigned T6MODE2
: 1;
7311 unsigned T6MODE3
: 1;
7312 unsigned T6MODE4
: 1;
7313 unsigned T6CKSYNC
: 1;
7314 unsigned T6CKPOL
: 1;
7315 unsigned T6PSYNC
: 1;
7326 unsigned T6MODE
: 5;
7331 extern __at(0x041D) volatile __T6HLTbits_t T6HLTbits
;
7333 #define _T6HLT_MODE0 0x01
7334 #define _T6HLT_T6MODE0 0x01
7335 #define _T6HLT_MODE1 0x02
7336 #define _T6HLT_T6MODE1 0x02
7337 #define _T6HLT_MODE2 0x04
7338 #define _T6HLT_T6MODE2 0x04
7339 #define _T6HLT_MODE3 0x08
7340 #define _T6HLT_T6MODE3 0x08
7341 #define _T6HLT_MODE4 0x10
7342 #define _T6HLT_T6MODE4 0x10
7343 #define _T6HLT_CKSYNC 0x20
7344 #define _T6HLT_T6CKSYNC 0x20
7345 #define _T6HLT_CKPOL 0x40
7346 #define _T6HLT_T6CKPOL 0x40
7347 #define _T6HLT_PSYNC 0x80
7348 #define _T6HLT_T6PSYNC 0x80
7350 //==============================================================================
7353 //==============================================================================
7356 extern __at(0x041E) __sfr T6CLKCON
;
7397 extern __at(0x041E) volatile __T6CLKCONbits_t T6CLKCONbits
;
7399 #define _T6CLKCON_CS0 0x01
7400 #define _T6CLKCON_T6CS0 0x01
7401 #define _T6CLKCON_CS1 0x02
7402 #define _T6CLKCON_T6CS1 0x02
7403 #define _T6CLKCON_CS2 0x04
7404 #define _T6CLKCON_T6CS2 0x04
7405 #define _T6CLKCON_CS3 0x08
7406 #define _T6CLKCON_T6CS3 0x08
7408 //==============================================================================
7411 //==============================================================================
7414 extern __at(0x041F) __sfr T6RST
;
7432 unsigned T6RSEL0
: 1;
7433 unsigned T6RSEL1
: 1;
7434 unsigned T6RSEL2
: 1;
7435 unsigned T6RSEL3
: 1;
7436 unsigned T6RSEL4
: 1;
7444 unsigned T6RSEL
: 5;
7455 extern __at(0x041F) volatile __T6RSTbits_t T6RSTbits
;
7457 #define _T6RST_RSEL0 0x01
7458 #define _T6RST_T6RSEL0 0x01
7459 #define _T6RST_RSEL1 0x02
7460 #define _T6RST_T6RSEL1 0x02
7461 #define _T6RST_RSEL2 0x04
7462 #define _T6RST_T6RSEL2 0x04
7463 #define _T6RST_RSEL3 0x08
7464 #define _T6RST_T6RSEL3 0x08
7465 #define _T6RST_RSEL4 0x10
7466 #define _T6RST_T6RSEL4 0x10
7468 //==============================================================================
7470 extern __at(0x048E) __sfr ADRESL
;
7471 extern __at(0x048F) __sfr ADRESH
;
7473 //==============================================================================
7476 extern __at(0x0490) __sfr ADCON0
;
7490 extern __at(0x0490) volatile __ADCON0bits_t ADCON0bits
;
7495 //==============================================================================
7498 //==============================================================================
7501 extern __at(0x0491) __sfr ADCON1
;
7507 unsigned ADNREF
: 1;
7515 extern __at(0x0491) volatile __ADCON1bits_t ADCON1bits
;
7517 #define _ADNREF 0x04
7520 //==============================================================================
7522 extern __at(0x0492) __sfr ADCON2
;
7523 extern __at(0x0493) __sfr T2TMR
;
7524 extern __at(0x0493) __sfr TMR2
;
7525 extern __at(0x0494) __sfr PR2
;
7526 extern __at(0x0494) __sfr T2PR
;
7528 //==============================================================================
7531 extern __at(0x0495) __sfr T2CON
;
7537 unsigned OUTPS0
: 1;
7538 unsigned OUTPS1
: 1;
7539 unsigned OUTPS2
: 1;
7540 unsigned OUTPS3
: 1;
7549 unsigned T2OUTPS0
: 1;
7550 unsigned T2OUTPS1
: 1;
7551 unsigned T2OUTPS2
: 1;
7552 unsigned T2OUTPS3
: 1;
7553 unsigned T2CKPS0
: 1;
7554 unsigned T2CKPS1
: 1;
7555 unsigned T2CKPS2
: 1;
7568 unsigned TMR2ON
: 1;
7573 unsigned T2OUTPS
: 4;
7593 unsigned T2CKPS
: 3;
7598 extern __at(0x0495) volatile __T2CONbits_t T2CONbits
;
7600 #define _T2CON_OUTPS0 0x01
7601 #define _T2CON_T2OUTPS0 0x01
7602 #define _T2CON_OUTPS1 0x02
7603 #define _T2CON_T2OUTPS1 0x02
7604 #define _T2CON_OUTPS2 0x04
7605 #define _T2CON_T2OUTPS2 0x04
7606 #define _T2CON_OUTPS3 0x08
7607 #define _T2CON_T2OUTPS3 0x08
7608 #define _T2CON_CKPS0 0x10
7609 #define _T2CON_T2CKPS0 0x10
7610 #define _T2CON_CKPS1 0x20
7611 #define _T2CON_T2CKPS1 0x20
7612 #define _T2CON_CKPS2 0x40
7613 #define _T2CON_T2CKPS2 0x40
7614 #define _T2CON_ON 0x80
7615 #define _T2CON_T2ON 0x80
7616 #define _T2CON_TMR2ON 0x80
7618 //==============================================================================
7621 //==============================================================================
7624 extern __at(0x0496) __sfr T2HLT
;
7635 unsigned CKSYNC
: 1;
7642 unsigned T2MODE0
: 1;
7643 unsigned T2MODE1
: 1;
7644 unsigned T2MODE2
: 1;
7645 unsigned T2MODE3
: 1;
7646 unsigned T2MODE4
: 1;
7647 unsigned T2CKSYNC
: 1;
7648 unsigned T2CKPOL
: 1;
7649 unsigned T2PSYNC
: 1;
7654 unsigned T2MODE
: 5;
7665 extern __at(0x0496) volatile __T2HLTbits_t T2HLTbits
;
7667 #define _T2HLT_MODE0 0x01
7668 #define _T2HLT_T2MODE0 0x01
7669 #define _T2HLT_MODE1 0x02
7670 #define _T2HLT_T2MODE1 0x02
7671 #define _T2HLT_MODE2 0x04
7672 #define _T2HLT_T2MODE2 0x04
7673 #define _T2HLT_MODE3 0x08
7674 #define _T2HLT_T2MODE3 0x08
7675 #define _T2HLT_MODE4 0x10
7676 #define _T2HLT_T2MODE4 0x10
7677 #define _T2HLT_CKSYNC 0x20
7678 #define _T2HLT_T2CKSYNC 0x20
7679 #define _T2HLT_CKPOL 0x40
7680 #define _T2HLT_T2CKPOL 0x40
7681 #define _T2HLT_PSYNC 0x80
7682 #define _T2HLT_T2PSYNC 0x80
7684 //==============================================================================
7687 //==============================================================================
7690 extern __at(0x0497) __sfr T2CLKCON
;
7731 extern __at(0x0497) volatile __T2CLKCONbits_t T2CLKCONbits
;
7733 #define _T2CLKCON_CS0 0x01
7734 #define _T2CLKCON_T2CS0 0x01
7735 #define _T2CLKCON_CS1 0x02
7736 #define _T2CLKCON_T2CS1 0x02
7737 #define _T2CLKCON_CS2 0x04
7738 #define _T2CLKCON_T2CS2 0x04
7739 #define _T2CLKCON_CS3 0x08
7740 #define _T2CLKCON_T2CS3 0x08
7742 //==============================================================================
7745 //==============================================================================
7748 extern __at(0x0498) __sfr T2RST
;
7766 unsigned T2RSEL0
: 1;
7767 unsigned T2RSEL1
: 1;
7768 unsigned T2RSEL2
: 1;
7769 unsigned T2RSEL3
: 1;
7770 unsigned T2RSEL4
: 1;
7778 unsigned T2RSEL
: 5;
7789 extern __at(0x0498) volatile __T2RSTbits_t T2RSTbits
;
7792 #define _T2RSEL0 0x01
7794 #define _T2RSEL1 0x02
7796 #define _T2RSEL2 0x04
7798 #define _T2RSEL3 0x08
7800 #define _T2RSEL4 0x10
7802 //==============================================================================
7804 extern __at(0x049A) __sfr T8TMR
;
7805 extern __at(0x049A) __sfr TMR8
;
7806 extern __at(0x049B) __sfr PR8
;
7807 extern __at(0x049B) __sfr T8PR
;
7809 //==============================================================================
7812 extern __at(0x049C) __sfr T8CON
;
7818 unsigned OUTPS0
: 1;
7819 unsigned OUTPS1
: 1;
7820 unsigned OUTPS2
: 1;
7821 unsigned OUTPS3
: 1;
7830 unsigned T8OUTPS0
: 1;
7831 unsigned T8OUTPS1
: 1;
7832 unsigned T8OUTPS2
: 1;
7833 unsigned T8OUTPS3
: 1;
7834 unsigned T8CKPS0
: 1;
7835 unsigned T8CKPS1
: 1;
7836 unsigned T8CKPS2
: 1;
7849 unsigned TMR8ON
: 1;
7854 unsigned T8OUTPS
: 4;
7867 unsigned T8CKPS
: 3;
7879 extern __at(0x049C) volatile __T8CONbits_t T8CONbits
;
7881 #define _T8CON_OUTPS0 0x01
7882 #define _T8CON_T8OUTPS0 0x01
7883 #define _T8CON_OUTPS1 0x02
7884 #define _T8CON_T8OUTPS1 0x02
7885 #define _T8CON_OUTPS2 0x04
7886 #define _T8CON_T8OUTPS2 0x04
7887 #define _T8CON_OUTPS3 0x08
7888 #define _T8CON_T8OUTPS3 0x08
7889 #define _T8CON_CKPS0 0x10
7890 #define _T8CON_T8CKPS0 0x10
7891 #define _T8CON_CKPS1 0x20
7892 #define _T8CON_T8CKPS1 0x20
7893 #define _T8CON_CKPS2 0x40
7894 #define _T8CON_T8CKPS2 0x40
7895 #define _T8CON_ON 0x80
7896 #define _T8CON_T8ON 0x80
7897 #define _T8CON_TMR8ON 0x80
7899 //==============================================================================
7902 //==============================================================================
7905 extern __at(0x049D) __sfr T8HLT
;
7916 unsigned CKSYNC
: 1;
7923 unsigned T8MODE0
: 1;
7924 unsigned T8MODE1
: 1;
7925 unsigned T8MODE2
: 1;
7926 unsigned T8MODE3
: 1;
7927 unsigned T8MODE4
: 1;
7928 unsigned T8CKSYNC
: 1;
7929 unsigned T8CKPOL
: 1;
7930 unsigned T8PSYNC
: 1;
7941 unsigned T8MODE
: 5;
7946 extern __at(0x049D) volatile __T8HLTbits_t T8HLTbits
;
7948 #define _T8HLT_MODE0 0x01
7949 #define _T8HLT_T8MODE0 0x01
7950 #define _T8HLT_MODE1 0x02
7951 #define _T8HLT_T8MODE1 0x02
7952 #define _T8HLT_MODE2 0x04
7953 #define _T8HLT_T8MODE2 0x04
7954 #define _T8HLT_MODE3 0x08
7955 #define _T8HLT_T8MODE3 0x08
7956 #define _T8HLT_MODE4 0x10
7957 #define _T8HLT_T8MODE4 0x10
7958 #define _T8HLT_CKSYNC 0x20
7959 #define _T8HLT_T8CKSYNC 0x20
7960 #define _T8HLT_CKPOL 0x40
7961 #define _T8HLT_T8CKPOL 0x40
7962 #define _T8HLT_PSYNC 0x80
7963 #define _T8HLT_T8PSYNC 0x80
7965 //==============================================================================
7968 //==============================================================================
7971 extern __at(0x049E) __sfr T8CLKCON
;
8012 extern __at(0x049E) volatile __T8CLKCONbits_t T8CLKCONbits
;
8014 #define _T8CLKCON_CS0 0x01
8015 #define _T8CLKCON_T8CS0 0x01
8016 #define _T8CLKCON_CS1 0x02
8017 #define _T8CLKCON_T8CS1 0x02
8018 #define _T8CLKCON_CS2 0x04
8019 #define _T8CLKCON_T8CS2 0x04
8020 #define _T8CLKCON_CS3 0x08
8021 #define _T8CLKCON_T8CS3 0x08
8023 //==============================================================================
8026 //==============================================================================
8029 extern __at(0x049F) __sfr T8RST
;
8047 unsigned T8RSEL0
: 1;
8048 unsigned T8RSEL1
: 1;
8049 unsigned T8RSEL2
: 1;
8050 unsigned T8RSEL3
: 1;
8051 unsigned T8RSEL4
: 1;
8059 unsigned T8RSEL
: 5;
8070 extern __at(0x049F) volatile __T8RSTbits_t T8RSTbits
;
8072 #define _T8RST_RSEL0 0x01
8073 #define _T8RST_T8RSEL0 0x01
8074 #define _T8RST_RSEL1 0x02
8075 #define _T8RST_T8RSEL1 0x02
8076 #define _T8RST_RSEL2 0x04
8077 #define _T8RST_T8RSEL2 0x04
8078 #define _T8RST_RSEL3 0x08
8079 #define _T8RST_T8RSEL3 0x08
8080 #define _T8RST_RSEL4 0x10
8081 #define _T8RST_T8RSEL4 0x10
8083 //==============================================================================
8085 extern __at(0x050F) __sfr OPA1NCHS
;
8086 extern __at(0x0510) __sfr OPA1PCHS
;
8088 //==============================================================================
8091 extern __at(0x0511) __sfr OPA1CON
;
8109 unsigned OPA1ORM0
: 1;
8110 unsigned OPA1ORM1
: 1;
8111 unsigned OPA1ORPOL
: 1;
8113 unsigned OPA1UG
: 1;
8116 unsigned OPA1EN
: 1;
8127 unsigned OPA1ORM
: 2;
8132 extern __at(0x0511) volatile __OPA1CONbits_t OPA1CONbits
;
8134 #define _OPA1CON_ORM0 0x01
8135 #define _OPA1CON_OPA1ORM0 0x01
8136 #define _OPA1CON_ORM1 0x02
8137 #define _OPA1CON_OPA1ORM1 0x02
8138 #define _OPA1CON_ORPOL 0x04
8139 #define _OPA1CON_OPA1ORPOL 0x04
8140 #define _OPA1CON_UG 0x10
8141 #define _OPA1CON_OPA1UG 0x10
8142 #define _OPA1CON_EN 0x80
8143 #define _OPA1CON_OPA1EN 0x80
8145 //==============================================================================
8147 extern __at(0x0512) __sfr OPA1ORS
;
8148 extern __at(0x0513) __sfr OPA2NCHS
;
8149 extern __at(0x0514) __sfr OPA2PCHS
;
8151 //==============================================================================
8154 extern __at(0x0515) __sfr OPA2CON
;
8172 unsigned OPA2ORM0
: 1;
8173 unsigned OPA2ORM1
: 1;
8174 unsigned OPA2ORPOL
: 1;
8176 unsigned OPA2UG
: 1;
8179 unsigned OPA2EN
: 1;
8184 unsigned OPA2ORM
: 2;
8195 extern __at(0x0515) volatile __OPA2CONbits_t OPA2CONbits
;
8197 #define _OPA2CON_ORM0 0x01
8198 #define _OPA2CON_OPA2ORM0 0x01
8199 #define _OPA2CON_ORM1 0x02
8200 #define _OPA2CON_OPA2ORM1 0x02
8201 #define _OPA2CON_ORPOL 0x04
8202 #define _OPA2CON_OPA2ORPOL 0x04
8203 #define _OPA2CON_UG 0x10
8204 #define _OPA2CON_OPA2UG 0x10
8205 #define _OPA2CON_EN 0x80
8206 #define _OPA2CON_OPA2EN 0x80
8208 //==============================================================================
8210 extern __at(0x0516) __sfr OPA2ORS
;
8211 extern __at(0x0517) __sfr OPA3NCHS
;
8212 extern __at(0x0518) __sfr OPA3PCHS
;
8214 //==============================================================================
8217 extern __at(0x0519) __sfr OPA3CON
;
8235 unsigned OPA3ORM0
: 1;
8236 unsigned OPA3ORM1
: 1;
8237 unsigned OPA3ORPOL
: 1;
8239 unsigned OPA3UG
: 1;
8241 unsigned OPA3SP
: 1;
8242 unsigned OPA3EN
: 1;
8247 unsigned OPA3ORM
: 2;
8258 extern __at(0x0519) volatile __OPA3CONbits_t OPA3CONbits
;
8260 #define _OPA3CON_ORM0 0x01
8261 #define _OPA3CON_OPA3ORM0 0x01
8262 #define _OPA3CON_ORM1 0x02
8263 #define _OPA3CON_OPA3ORM1 0x02
8264 #define _OPA3CON_ORPOL 0x04
8265 #define _OPA3CON_OPA3ORPOL 0x04
8266 #define _OPA3CON_UG 0x10
8267 #define _OPA3CON_OPA3UG 0x10
8268 #define _OPA3CON_SP 0x40
8269 #define _OPA3CON_OPA3SP 0x40
8270 #define _OPA3CON_EN 0x80
8271 #define _OPA3CON_OPA3EN 0x80
8273 //==============================================================================
8275 extern __at(0x051A) __sfr OPA3ORS
;
8276 extern __at(0x051B) __sfr OPA4NCHS
;
8277 extern __at(0x051C) __sfr OPA4PCHS
;
8279 //==============================================================================
8282 extern __at(0x051D) __sfr OPA4CON
;
8300 unsigned OPA4ORM0
: 1;
8301 unsigned OPA4ORM1
: 1;
8302 unsigned OPA4ORPOL
: 1;
8304 unsigned OPA4UG
: 1;
8306 unsigned OPA4SP
: 1;
8307 unsigned OPA4EN
: 1;
8318 unsigned OPA4ORM
: 2;
8323 extern __at(0x051D) volatile __OPA4CONbits_t OPA4CONbits
;
8325 #define _OPA4CON_ORM0 0x01
8326 #define _OPA4CON_OPA4ORM0 0x01
8327 #define _OPA4CON_ORM1 0x02
8328 #define _OPA4CON_OPA4ORM1 0x02
8329 #define _OPA4CON_ORPOL 0x04
8330 #define _OPA4CON_OPA4ORPOL 0x04
8331 #define _OPA4CON_UG 0x10
8332 #define _OPA4CON_OPA4UG 0x10
8333 #define _OPA4CON_SP 0x40
8334 #define _OPA4CON_OPA4SP 0x40
8335 #define _OPA4CON_EN 0x80
8336 #define _OPA4CON_OPA4EN 0x80
8338 //==============================================================================
8340 extern __at(0x051E) __sfr OPA4ORS
;
8342 //==============================================================================
8345 extern __at(0x058D) __sfr DACLD
;
8349 unsigned DAC1LD
: 1;
8350 unsigned DAC2LD
: 1;
8353 unsigned DAC5LD
: 1;
8354 unsigned DAC6LD
: 1;
8359 extern __at(0x058D) volatile __DACLDbits_t DACLDbits
;
8361 #define _DAC1LD 0x01
8362 #define _DAC2LD 0x02
8363 #define _DAC5LD 0x10
8364 #define _DAC6LD 0x20
8366 //==============================================================================
8369 //==============================================================================
8372 extern __at(0x058E) __sfr DAC1CON0
;
8390 unsigned DACNSS0
: 1;
8391 unsigned DACNSS1
: 1;
8392 unsigned DACPSS0
: 1;
8393 unsigned DACPSS1
: 1;
8394 unsigned DACOE2
: 1;
8402 unsigned DAC1NSS0
: 1;
8403 unsigned DAC1NSS1
: 1;
8404 unsigned DAC1PSS0
: 1;
8405 unsigned DAC1PSS1
: 1;
8406 unsigned DAC1OE2
: 1;
8407 unsigned DACOE1
: 1;
8408 unsigned DAC1FM
: 1;
8409 unsigned DAC1EN
: 1;
8431 unsigned DAC1OE1
: 1;
8438 unsigned DAC1NSS
: 2;
8450 unsigned DACNSS
: 2;
8457 unsigned DACPSS
: 2;
8471 unsigned DAC1PSS
: 2;
8476 extern __at(0x058E) volatile __DAC1CON0bits_t DAC1CON0bits
;
8478 #define _DAC1CON0_NSS0 0x01
8479 #define _DAC1CON0_DACNSS0 0x01
8480 #define _DAC1CON0_DAC1NSS0 0x01
8481 #define _DAC1CON0_NSS1 0x02
8482 #define _DAC1CON0_DACNSS1 0x02
8483 #define _DAC1CON0_DAC1NSS1 0x02
8484 #define _DAC1CON0_PSS0 0x04
8485 #define _DAC1CON0_DACPSS0 0x04
8486 #define _DAC1CON0_DAC1PSS0 0x04
8487 #define _DAC1CON0_PSS1 0x08
8488 #define _DAC1CON0_DACPSS1 0x08
8489 #define _DAC1CON0_DAC1PSS1 0x08
8490 #define _DAC1CON0_OE2 0x10
8491 #define _DAC1CON0_DACOE2 0x10
8492 #define _DAC1CON0_DAC1OE2 0x10
8493 #define _DAC1CON0_OE1 0x20
8494 #define _DAC1CON0_OE 0x20
8495 #define _DAC1CON0_DACOE1 0x20
8496 #define _DAC1CON0_DACOE 0x20
8497 #define _DAC1CON0_DAC1OE1 0x20
8498 #define _DAC1CON0_FM 0x40
8499 #define _DAC1CON0_DACFM 0x40
8500 #define _DAC1CON0_DAC1FM 0x40
8501 #define _DAC1CON0_EN 0x80
8502 #define _DAC1CON0_DACEN 0x80
8503 #define _DAC1CON0_DAC1EN 0x80
8505 //==============================================================================
8508 //==============================================================================
8511 extern __at(0x058F) __sfr DAC1CON1
;
8529 unsigned DAC1REF0
: 1;
8530 unsigned DAC1REF1
: 1;
8531 unsigned DAC1REF2
: 1;
8532 unsigned DAC1REF3
: 1;
8533 unsigned DAC1REF4
: 1;
8534 unsigned DAC1REF5
: 1;
8535 unsigned DAC1REF6
: 1;
8536 unsigned DAC1REF7
: 1;
8553 unsigned DAC1R0
: 1;
8554 unsigned DAC1R1
: 1;
8555 unsigned DAC1R2
: 1;
8556 unsigned DAC1R3
: 1;
8557 unsigned DAC1R4
: 1;
8558 unsigned DAC1R5
: 1;
8559 unsigned DAC1R6
: 1;
8560 unsigned DAC1R7
: 1;
8564 extern __at(0x058F) volatile __DAC1CON1bits_t DAC1CON1bits
;
8567 #define _DAC1REF0 0x01
8569 #define _DAC1R0 0x01
8571 #define _DAC1REF1 0x02
8573 #define _DAC1R1 0x02
8575 #define _DAC1REF2 0x04
8577 #define _DAC1R2 0x04
8579 #define _DAC1REF3 0x08
8581 #define _DAC1R3 0x08
8583 #define _DAC1REF4 0x10
8585 #define _DAC1R4 0x10
8587 #define _DAC1REF5 0x20
8589 #define _DAC1R5 0x20
8591 #define _DAC1REF6 0x40
8593 #define _DAC1R6 0x40
8595 #define _DAC1REF7 0x80
8597 #define _DAC1R7 0x80
8599 //==============================================================================
8601 extern __at(0x058F) __sfr DAC1REF
;
8603 //==============================================================================
8606 extern __at(0x058F) __sfr DAC1REFL
;
8624 unsigned DAC1REF0
: 1;
8625 unsigned DAC1REF1
: 1;
8626 unsigned DAC1REF2
: 1;
8627 unsigned DAC1REF3
: 1;
8628 unsigned DAC1REF4
: 1;
8629 unsigned DAC1REF5
: 1;
8630 unsigned DAC1REF6
: 1;
8631 unsigned DAC1REF7
: 1;
8648 unsigned DAC1R0
: 1;
8649 unsigned DAC1R1
: 1;
8650 unsigned DAC1R2
: 1;
8651 unsigned DAC1R3
: 1;
8652 unsigned DAC1R4
: 1;
8653 unsigned DAC1R5
: 1;
8654 unsigned DAC1R6
: 1;
8655 unsigned DAC1R7
: 1;
8659 extern __at(0x058F) volatile __DAC1REFLbits_t DAC1REFLbits
;
8661 #define _DAC1REFL_REF0 0x01
8662 #define _DAC1REFL_DAC1REF0 0x01
8663 #define _DAC1REFL_R0 0x01
8664 #define _DAC1REFL_DAC1R0 0x01
8665 #define _DAC1REFL_REF1 0x02
8666 #define _DAC1REFL_DAC1REF1 0x02
8667 #define _DAC1REFL_R1 0x02
8668 #define _DAC1REFL_DAC1R1 0x02
8669 #define _DAC1REFL_REF2 0x04
8670 #define _DAC1REFL_DAC1REF2 0x04
8671 #define _DAC1REFL_R2 0x04
8672 #define _DAC1REFL_DAC1R2 0x04
8673 #define _DAC1REFL_REF3 0x08
8674 #define _DAC1REFL_DAC1REF3 0x08
8675 #define _DAC1REFL_R3 0x08
8676 #define _DAC1REFL_DAC1R3 0x08
8677 #define _DAC1REFL_REF4 0x10
8678 #define _DAC1REFL_DAC1REF4 0x10
8679 #define _DAC1REFL_R4 0x10
8680 #define _DAC1REFL_DAC1R4 0x10
8681 #define _DAC1REFL_REF5 0x20
8682 #define _DAC1REFL_DAC1REF5 0x20
8683 #define _DAC1REFL_R5 0x20
8684 #define _DAC1REFL_DAC1R5 0x20
8685 #define _DAC1REFL_REF6 0x40
8686 #define _DAC1REFL_DAC1REF6 0x40
8687 #define _DAC1REFL_R6 0x40
8688 #define _DAC1REFL_DAC1R6 0x40
8689 #define _DAC1REFL_REF7 0x80
8690 #define _DAC1REFL_DAC1REF7 0x80
8691 #define _DAC1REFL_R7 0x80
8692 #define _DAC1REFL_DAC1R7 0x80
8694 //==============================================================================
8697 //==============================================================================
8700 extern __at(0x0590) __sfr DAC1CON2
;
8718 unsigned DAC1REF8
: 1;
8719 unsigned DAC1REF9
: 1;
8720 unsigned DAC1REF10
: 1;
8721 unsigned DAC1REF11
: 1;
8722 unsigned DAC1REF12
: 1;
8723 unsigned DAC1REF13
: 1;
8724 unsigned DAC1REF14
: 1;
8725 unsigned DAC1REF15
: 1;
8742 unsigned DAC1R8
: 1;
8743 unsigned DAC1R9
: 1;
8744 unsigned DAC1R10
: 1;
8745 unsigned DAC1R11
: 1;
8746 unsigned DAC1R12
: 1;
8747 unsigned DAC1R13
: 1;
8748 unsigned DAC1R14
: 1;
8749 unsigned DAC1R15
: 1;
8753 extern __at(0x0590) volatile __DAC1CON2bits_t DAC1CON2bits
;
8756 #define _DAC1REF8 0x01
8758 #define _DAC1R8 0x01
8760 #define _DAC1REF9 0x02
8762 #define _DAC1R9 0x02
8764 #define _DAC1REF10 0x04
8766 #define _DAC1R10 0x04
8768 #define _DAC1REF11 0x08
8770 #define _DAC1R11 0x08
8772 #define _DAC1REF12 0x10
8774 #define _DAC1R12 0x10
8776 #define _DAC1REF13 0x20
8778 #define _DAC1R13 0x20
8780 #define _DAC1REF14 0x40
8782 #define _DAC1R14 0x40
8784 #define _DAC1REF15 0x80
8786 #define _DAC1R15 0x80
8788 //==============================================================================
8791 //==============================================================================
8794 extern __at(0x0590) __sfr DAC1REFH
;
8812 unsigned DAC1REF8
: 1;
8813 unsigned DAC1REF9
: 1;
8814 unsigned DAC1REF10
: 1;
8815 unsigned DAC1REF11
: 1;
8816 unsigned DAC1REF12
: 1;
8817 unsigned DAC1REF13
: 1;
8818 unsigned DAC1REF14
: 1;
8819 unsigned DAC1REF15
: 1;
8836 unsigned DAC1R8
: 1;
8837 unsigned DAC1R9
: 1;
8838 unsigned DAC1R10
: 1;
8839 unsigned DAC1R11
: 1;
8840 unsigned DAC1R12
: 1;
8841 unsigned DAC1R13
: 1;
8842 unsigned DAC1R14
: 1;
8843 unsigned DAC1R15
: 1;
8847 extern __at(0x0590) volatile __DAC1REFHbits_t DAC1REFHbits
;
8849 #define _DAC1REFH_REF8 0x01
8850 #define _DAC1REFH_DAC1REF8 0x01
8851 #define _DAC1REFH_R8 0x01
8852 #define _DAC1REFH_DAC1R8 0x01
8853 #define _DAC1REFH_REF9 0x02
8854 #define _DAC1REFH_DAC1REF9 0x02
8855 #define _DAC1REFH_R9 0x02
8856 #define _DAC1REFH_DAC1R9 0x02
8857 #define _DAC1REFH_REF10 0x04
8858 #define _DAC1REFH_DAC1REF10 0x04
8859 #define _DAC1REFH_R10 0x04
8860 #define _DAC1REFH_DAC1R10 0x04
8861 #define _DAC1REFH_REF11 0x08
8862 #define _DAC1REFH_DAC1REF11 0x08
8863 #define _DAC1REFH_R11 0x08
8864 #define _DAC1REFH_DAC1R11 0x08
8865 #define _DAC1REFH_REF12 0x10
8866 #define _DAC1REFH_DAC1REF12 0x10
8867 #define _DAC1REFH_R12 0x10
8868 #define _DAC1REFH_DAC1R12 0x10
8869 #define _DAC1REFH_REF13 0x20
8870 #define _DAC1REFH_DAC1REF13 0x20
8871 #define _DAC1REFH_R13 0x20
8872 #define _DAC1REFH_DAC1R13 0x20
8873 #define _DAC1REFH_REF14 0x40
8874 #define _DAC1REFH_DAC1REF14 0x40
8875 #define _DAC1REFH_R14 0x40
8876 #define _DAC1REFH_DAC1R14 0x40
8877 #define _DAC1REFH_REF15 0x80
8878 #define _DAC1REFH_DAC1REF15 0x80
8879 #define _DAC1REFH_R15 0x80
8880 #define _DAC1REFH_DAC1R15 0x80
8882 //==============================================================================
8885 //==============================================================================
8888 extern __at(0x0591) __sfr DAC2CON0
;
8906 unsigned DACNSS0
: 1;
8907 unsigned DACNSS1
: 1;
8908 unsigned DACPSS0
: 1;
8909 unsigned DACPSS1
: 1;
8910 unsigned DACOE2
: 1;
8918 unsigned DAC2NSS0
: 1;
8919 unsigned DAC2NSS1
: 1;
8920 unsigned DAC2PSS0
: 1;
8921 unsigned DAC2PSS1
: 1;
8922 unsigned DAC2OE2
: 1;
8923 unsigned DACOE1
: 1;
8924 unsigned DAC2FM
: 1;
8925 unsigned DAC2EN
: 1;
8947 unsigned DAC2OE1
: 1;
8954 unsigned DAC2NSS
: 2;
8960 unsigned DACNSS
: 2;
8980 unsigned DACPSS
: 2;
8987 unsigned DAC2PSS
: 2;
8992 extern __at(0x0591) volatile __DAC2CON0bits_t DAC2CON0bits
;
8994 #define _DAC2CON0_NSS0 0x01
8995 #define _DAC2CON0_DACNSS0 0x01
8996 #define _DAC2CON0_DAC2NSS0 0x01
8997 #define _DAC2CON0_NSS1 0x02
8998 #define _DAC2CON0_DACNSS1 0x02
8999 #define _DAC2CON0_DAC2NSS1 0x02
9000 #define _DAC2CON0_PSS0 0x04
9001 #define _DAC2CON0_DACPSS0 0x04
9002 #define _DAC2CON0_DAC2PSS0 0x04
9003 #define _DAC2CON0_PSS1 0x08
9004 #define _DAC2CON0_DACPSS1 0x08
9005 #define _DAC2CON0_DAC2PSS1 0x08
9006 #define _DAC2CON0_OE2 0x10
9007 #define _DAC2CON0_DACOE2 0x10
9008 #define _DAC2CON0_DAC2OE2 0x10
9009 #define _DAC2CON0_OE1 0x20
9010 #define _DAC2CON0_OE 0x20
9011 #define _DAC2CON0_DACOE1 0x20
9012 #define _DAC2CON0_DACOE 0x20
9013 #define _DAC2CON0_DAC2OE1 0x20
9014 #define _DAC2CON0_FM 0x40
9015 #define _DAC2CON0_DACFM 0x40
9016 #define _DAC2CON0_DAC2FM 0x40
9017 #define _DAC2CON0_EN 0x80
9018 #define _DAC2CON0_DACEN 0x80
9019 #define _DAC2CON0_DAC2EN 0x80
9021 //==============================================================================
9024 //==============================================================================
9027 extern __at(0x0592) __sfr DAC2CON1
;
9045 unsigned DAC2REF0
: 1;
9046 unsigned DAC2REF1
: 1;
9047 unsigned DAC2REF2
: 1;
9048 unsigned DAC2REF3
: 1;
9049 unsigned DAC2REF4
: 1;
9050 unsigned DAC2REF5
: 1;
9051 unsigned DAC2REF6
: 1;
9052 unsigned DAC2REF7
: 1;
9069 unsigned DAC2R0
: 1;
9070 unsigned DAC2R1
: 1;
9071 unsigned DAC2R2
: 1;
9072 unsigned DAC2R3
: 1;
9073 unsigned DAC2R4
: 1;
9074 unsigned DAC2R5
: 1;
9075 unsigned DAC2R6
: 1;
9076 unsigned DAC2R7
: 1;
9080 extern __at(0x0592) volatile __DAC2CON1bits_t DAC2CON1bits
;
9082 #define _DAC2CON1_REF0 0x01
9083 #define _DAC2CON1_DAC2REF0 0x01
9084 #define _DAC2CON1_R0 0x01
9085 #define _DAC2CON1_DAC2R0 0x01
9086 #define _DAC2CON1_REF1 0x02
9087 #define _DAC2CON1_DAC2REF1 0x02
9088 #define _DAC2CON1_R1 0x02
9089 #define _DAC2CON1_DAC2R1 0x02
9090 #define _DAC2CON1_REF2 0x04
9091 #define _DAC2CON1_DAC2REF2 0x04
9092 #define _DAC2CON1_R2 0x04
9093 #define _DAC2CON1_DAC2R2 0x04
9094 #define _DAC2CON1_REF3 0x08
9095 #define _DAC2CON1_DAC2REF3 0x08
9096 #define _DAC2CON1_R3 0x08
9097 #define _DAC2CON1_DAC2R3 0x08
9098 #define _DAC2CON1_REF4 0x10
9099 #define _DAC2CON1_DAC2REF4 0x10
9100 #define _DAC2CON1_R4 0x10
9101 #define _DAC2CON1_DAC2R4 0x10
9102 #define _DAC2CON1_REF5 0x20
9103 #define _DAC2CON1_DAC2REF5 0x20
9104 #define _DAC2CON1_R5 0x20
9105 #define _DAC2CON1_DAC2R5 0x20
9106 #define _DAC2CON1_REF6 0x40
9107 #define _DAC2CON1_DAC2REF6 0x40
9108 #define _DAC2CON1_R6 0x40
9109 #define _DAC2CON1_DAC2R6 0x40
9110 #define _DAC2CON1_REF7 0x80
9111 #define _DAC2CON1_DAC2REF7 0x80
9112 #define _DAC2CON1_R7 0x80
9113 #define _DAC2CON1_DAC2R7 0x80
9115 //==============================================================================
9117 extern __at(0x0592) __sfr DAC2REF
;
9119 //==============================================================================
9122 extern __at(0x0592) __sfr DAC2REFL
;
9140 unsigned DAC2REF0
: 1;
9141 unsigned DAC2REF1
: 1;
9142 unsigned DAC2REF2
: 1;
9143 unsigned DAC2REF3
: 1;
9144 unsigned DAC2REF4
: 1;
9145 unsigned DAC2REF5
: 1;
9146 unsigned DAC2REF6
: 1;
9147 unsigned DAC2REF7
: 1;
9164 unsigned DAC2R0
: 1;
9165 unsigned DAC2R1
: 1;
9166 unsigned DAC2R2
: 1;
9167 unsigned DAC2R3
: 1;
9168 unsigned DAC2R4
: 1;
9169 unsigned DAC2R5
: 1;
9170 unsigned DAC2R6
: 1;
9171 unsigned DAC2R7
: 1;
9175 extern __at(0x0592) volatile __DAC2REFLbits_t DAC2REFLbits
;
9177 #define _DAC2REFL_REF0 0x01
9178 #define _DAC2REFL_DAC2REF0 0x01
9179 #define _DAC2REFL_R0 0x01
9180 #define _DAC2REFL_DAC2R0 0x01
9181 #define _DAC2REFL_REF1 0x02
9182 #define _DAC2REFL_DAC2REF1 0x02
9183 #define _DAC2REFL_R1 0x02
9184 #define _DAC2REFL_DAC2R1 0x02
9185 #define _DAC2REFL_REF2 0x04
9186 #define _DAC2REFL_DAC2REF2 0x04
9187 #define _DAC2REFL_R2 0x04
9188 #define _DAC2REFL_DAC2R2 0x04
9189 #define _DAC2REFL_REF3 0x08
9190 #define _DAC2REFL_DAC2REF3 0x08
9191 #define _DAC2REFL_R3 0x08
9192 #define _DAC2REFL_DAC2R3 0x08
9193 #define _DAC2REFL_REF4 0x10
9194 #define _DAC2REFL_DAC2REF4 0x10
9195 #define _DAC2REFL_R4 0x10
9196 #define _DAC2REFL_DAC2R4 0x10
9197 #define _DAC2REFL_REF5 0x20
9198 #define _DAC2REFL_DAC2REF5 0x20
9199 #define _DAC2REFL_R5 0x20
9200 #define _DAC2REFL_DAC2R5 0x20
9201 #define _DAC2REFL_REF6 0x40
9202 #define _DAC2REFL_DAC2REF6 0x40
9203 #define _DAC2REFL_R6 0x40
9204 #define _DAC2REFL_DAC2R6 0x40
9205 #define _DAC2REFL_REF7 0x80
9206 #define _DAC2REFL_DAC2REF7 0x80
9207 #define _DAC2REFL_R7 0x80
9208 #define _DAC2REFL_DAC2R7 0x80
9210 //==============================================================================
9213 //==============================================================================
9216 extern __at(0x0593) __sfr DAC2CON2
;
9234 unsigned DAC2REF8
: 1;
9235 unsigned DAC2REF9
: 1;
9236 unsigned DAC2REF10
: 1;
9237 unsigned DAC2REF11
: 1;
9238 unsigned DAC2REF12
: 1;
9239 unsigned DAC2REF13
: 1;
9240 unsigned DAC2REF14
: 1;
9241 unsigned DAC2REF15
: 1;
9258 unsigned DAC2R8
: 1;
9259 unsigned DAC2R9
: 1;
9260 unsigned DAC2R10
: 1;
9261 unsigned DAC2R11
: 1;
9262 unsigned DAC2R12
: 1;
9263 unsigned DAC2R13
: 1;
9264 unsigned DAC2R14
: 1;
9265 unsigned DAC2R15
: 1;
9269 extern __at(0x0593) volatile __DAC2CON2bits_t DAC2CON2bits
;
9271 #define _DAC2CON2_REF8 0x01
9272 #define _DAC2CON2_DAC2REF8 0x01
9273 #define _DAC2CON2_R8 0x01
9274 #define _DAC2CON2_DAC2R8 0x01
9275 #define _DAC2CON2_REF9 0x02
9276 #define _DAC2CON2_DAC2REF9 0x02
9277 #define _DAC2CON2_R9 0x02
9278 #define _DAC2CON2_DAC2R9 0x02
9279 #define _DAC2CON2_REF10 0x04
9280 #define _DAC2CON2_DAC2REF10 0x04
9281 #define _DAC2CON2_R10 0x04
9282 #define _DAC2CON2_DAC2R10 0x04
9283 #define _DAC2CON2_REF11 0x08
9284 #define _DAC2CON2_DAC2REF11 0x08
9285 #define _DAC2CON2_R11 0x08
9286 #define _DAC2CON2_DAC2R11 0x08
9287 #define _DAC2CON2_REF12 0x10
9288 #define _DAC2CON2_DAC2REF12 0x10
9289 #define _DAC2CON2_R12 0x10
9290 #define _DAC2CON2_DAC2R12 0x10
9291 #define _DAC2CON2_REF13 0x20
9292 #define _DAC2CON2_DAC2REF13 0x20
9293 #define _DAC2CON2_R13 0x20
9294 #define _DAC2CON2_DAC2R13 0x20
9295 #define _DAC2CON2_REF14 0x40
9296 #define _DAC2CON2_DAC2REF14 0x40
9297 #define _DAC2CON2_R14 0x40
9298 #define _DAC2CON2_DAC2R14 0x40
9299 #define _DAC2CON2_REF15 0x80
9300 #define _DAC2CON2_DAC2REF15 0x80
9301 #define _DAC2CON2_R15 0x80
9302 #define _DAC2CON2_DAC2R15 0x80
9304 //==============================================================================
9307 //==============================================================================
9310 extern __at(0x0593) __sfr DAC2REFH
;
9328 unsigned DAC2REF8
: 1;
9329 unsigned DAC2REF9
: 1;
9330 unsigned DAC2REF10
: 1;
9331 unsigned DAC2REF11
: 1;
9332 unsigned DAC2REF12
: 1;
9333 unsigned DAC2REF13
: 1;
9334 unsigned DAC2REF14
: 1;
9335 unsigned DAC2REF15
: 1;
9352 unsigned DAC2R8
: 1;
9353 unsigned DAC2R9
: 1;
9354 unsigned DAC2R10
: 1;
9355 unsigned DAC2R11
: 1;
9356 unsigned DAC2R12
: 1;
9357 unsigned DAC2R13
: 1;
9358 unsigned DAC2R14
: 1;
9359 unsigned DAC2R15
: 1;
9363 extern __at(0x0593) volatile __DAC2REFHbits_t DAC2REFHbits
;
9365 #define _DAC2REFH_REF8 0x01
9366 #define _DAC2REFH_DAC2REF8 0x01
9367 #define _DAC2REFH_R8 0x01
9368 #define _DAC2REFH_DAC2R8 0x01
9369 #define _DAC2REFH_REF9 0x02
9370 #define _DAC2REFH_DAC2REF9 0x02
9371 #define _DAC2REFH_R9 0x02
9372 #define _DAC2REFH_DAC2R9 0x02
9373 #define _DAC2REFH_REF10 0x04
9374 #define _DAC2REFH_DAC2REF10 0x04
9375 #define _DAC2REFH_R10 0x04
9376 #define _DAC2REFH_DAC2R10 0x04
9377 #define _DAC2REFH_REF11 0x08
9378 #define _DAC2REFH_DAC2REF11 0x08
9379 #define _DAC2REFH_R11 0x08
9380 #define _DAC2REFH_DAC2R11 0x08
9381 #define _DAC2REFH_REF12 0x10
9382 #define _DAC2REFH_DAC2REF12 0x10
9383 #define _DAC2REFH_R12 0x10
9384 #define _DAC2REFH_DAC2R12 0x10
9385 #define _DAC2REFH_REF13 0x20
9386 #define _DAC2REFH_DAC2REF13 0x20
9387 #define _DAC2REFH_R13 0x20
9388 #define _DAC2REFH_DAC2R13 0x20
9389 #define _DAC2REFH_REF14 0x40
9390 #define _DAC2REFH_DAC2REF14 0x40
9391 #define _DAC2REFH_R14 0x40
9392 #define _DAC2REFH_DAC2R14 0x40
9393 #define _DAC2REFH_REF15 0x80
9394 #define _DAC2REFH_DAC2REF15 0x80
9395 #define _DAC2REFH_R15 0x80
9396 #define _DAC2REFH_DAC2R15 0x80
9398 //==============================================================================
9401 //==============================================================================
9404 extern __at(0x0594) __sfr DAC3CON0
;
9422 unsigned DACNSS0
: 1;
9423 unsigned DACNSS1
: 1;
9424 unsigned DACPSS0
: 1;
9425 unsigned DACPSS1
: 1;
9426 unsigned DACOE2
: 1;
9427 unsigned DACOE1
: 1;
9434 unsigned DAC3NSS0
: 1;
9435 unsigned DAC3NSS1
: 1;
9436 unsigned DAC3PSS0
: 1;
9437 unsigned DAC3PSS1
: 1;
9438 unsigned DAC3OE2
: 1;
9439 unsigned DAC3OE1
: 1;
9441 unsigned DAC3EN
: 1;
9452 unsigned DACNSS
: 2;
9458 unsigned DAC3NSS
: 2;
9465 unsigned DACPSS
: 2;
9472 unsigned DAC3PSS
: 2;
9484 extern __at(0x0594) volatile __DAC3CON0bits_t DAC3CON0bits
;
9486 #define _DAC3CON0_NSS0 0x01
9487 #define _DAC3CON0_DACNSS0 0x01
9488 #define _DAC3CON0_DAC3NSS0 0x01
9489 #define _DAC3CON0_NSS1 0x02
9490 #define _DAC3CON0_DACNSS1 0x02
9491 #define _DAC3CON0_DAC3NSS1 0x02
9492 #define _DAC3CON0_PSS0 0x04
9493 #define _DAC3CON0_DACPSS0 0x04
9494 #define _DAC3CON0_DAC3PSS0 0x04
9495 #define _DAC3CON0_PSS1 0x08
9496 #define _DAC3CON0_DACPSS1 0x08
9497 #define _DAC3CON0_DAC3PSS1 0x08
9498 #define _DAC3CON0_OE2 0x10
9499 #define _DAC3CON0_DACOE2 0x10
9500 #define _DAC3CON0_DAC3OE2 0x10
9501 #define _DAC3CON0_OE1 0x20
9502 #define _DAC3CON0_DACOE1 0x20
9503 #define _DAC3CON0_DAC3OE1 0x20
9504 #define _DAC3CON0_EN 0x80
9505 #define _DAC3CON0_DACEN 0x80
9506 #define _DAC3CON0_DAC3EN 0x80
9508 //==============================================================================
9511 //==============================================================================
9514 extern __at(0x0595) __sfr DAC3CON1
;
9544 unsigned DAC3R0
: 1;
9545 unsigned DAC3R1
: 1;
9546 unsigned DAC3R2
: 1;
9547 unsigned DAC3R3
: 1;
9548 unsigned DAC3R4
: 1;
9568 unsigned DAC3REF0
: 1;
9569 unsigned DAC3REF1
: 1;
9570 unsigned DAC3REF2
: 1;
9571 unsigned DAC3REF3
: 1;
9572 unsigned DAC3REF4
: 1;
9586 unsigned DAC3REF
: 5;
9609 extern __at(0x0595) volatile __DAC3CON1bits_t DAC3CON1bits
;
9611 #define _DAC3CON1_DACR0 0x01
9612 #define _DAC3CON1_R0 0x01
9613 #define _DAC3CON1_DAC3R0 0x01
9614 #define _DAC3CON1_REF0 0x01
9615 #define _DAC3CON1_DAC3REF0 0x01
9616 #define _DAC3CON1_DACR1 0x02
9617 #define _DAC3CON1_R1 0x02
9618 #define _DAC3CON1_DAC3R1 0x02
9619 #define _DAC3CON1_REF1 0x02
9620 #define _DAC3CON1_DAC3REF1 0x02
9621 #define _DAC3CON1_DACR2 0x04
9622 #define _DAC3CON1_R2 0x04
9623 #define _DAC3CON1_DAC3R2 0x04
9624 #define _DAC3CON1_REF2 0x04
9625 #define _DAC3CON1_DAC3REF2 0x04
9626 #define _DAC3CON1_DACR3 0x08
9627 #define _DAC3CON1_R3 0x08
9628 #define _DAC3CON1_DAC3R3 0x08
9629 #define _DAC3CON1_REF3 0x08
9630 #define _DAC3CON1_DAC3REF3 0x08
9631 #define _DAC3CON1_DACR4 0x10
9632 #define _DAC3CON1_R4 0x10
9633 #define _DAC3CON1_DAC3R4 0x10
9634 #define _DAC3CON1_REF4 0x10
9635 #define _DAC3CON1_DAC3REF4 0x10
9637 //==============================================================================
9640 //==============================================================================
9643 extern __at(0x0595) __sfr DAC3REF
;
9673 unsigned DAC3R0
: 1;
9674 unsigned DAC3R1
: 1;
9675 unsigned DAC3R2
: 1;
9676 unsigned DAC3R3
: 1;
9677 unsigned DAC3R4
: 1;
9697 unsigned DAC3REF0
: 1;
9698 unsigned DAC3REF1
: 1;
9699 unsigned DAC3REF2
: 1;
9700 unsigned DAC3REF3
: 1;
9701 unsigned DAC3REF4
: 1;
9715 unsigned DAC3REF
: 5;
9738 extern __at(0x0595) volatile __DAC3REFbits_t DAC3REFbits
;
9740 #define _DAC3REF_DACR0 0x01
9741 #define _DAC3REF_R0 0x01
9742 #define _DAC3REF_DAC3R0 0x01
9743 #define _DAC3REF_REF0 0x01
9744 #define _DAC3REF_DAC3REF0 0x01
9745 #define _DAC3REF_DACR1 0x02
9746 #define _DAC3REF_R1 0x02
9747 #define _DAC3REF_DAC3R1 0x02
9748 #define _DAC3REF_REF1 0x02
9749 #define _DAC3REF_DAC3REF1 0x02
9750 #define _DAC3REF_DACR2 0x04
9751 #define _DAC3REF_R2 0x04
9752 #define _DAC3REF_DAC3R2 0x04
9753 #define _DAC3REF_REF2 0x04
9754 #define _DAC3REF_DAC3REF2 0x04
9755 #define _DAC3REF_DACR3 0x08
9756 #define _DAC3REF_R3 0x08
9757 #define _DAC3REF_DAC3R3 0x08
9758 #define _DAC3REF_REF3 0x08
9759 #define _DAC3REF_DAC3REF3 0x08
9760 #define _DAC3REF_DACR4 0x10
9761 #define _DAC3REF_R4 0x10
9762 #define _DAC3REF_DAC3R4 0x10
9763 #define _DAC3REF_REF4 0x10
9764 #define _DAC3REF_DAC3REF4 0x10
9766 //==============================================================================
9769 //==============================================================================
9772 extern __at(0x0596) __sfr DAC4CON0
;
9790 unsigned DACNSS0
: 1;
9791 unsigned DACNSS1
: 1;
9792 unsigned DACPSS0
: 1;
9793 unsigned DACPSS1
: 1;
9794 unsigned DACOE2
: 1;
9795 unsigned DACOE1
: 1;
9802 unsigned DAC4NSS0
: 1;
9803 unsigned DAC4NSS1
: 1;
9804 unsigned DAC4PSS0
: 1;
9805 unsigned DAC4PSS1
: 1;
9806 unsigned DAC4OE2
: 1;
9807 unsigned DAC4OE1
: 1;
9809 unsigned DAC4EN
: 1;
9820 unsigned DAC4NSS
: 2;
9826 unsigned DACNSS
: 2;
9833 unsigned DACPSS
: 2;
9840 unsigned DAC4PSS
: 2;
9852 extern __at(0x0596) volatile __DAC4CON0bits_t DAC4CON0bits
;
9854 #define _DAC4CON0_NSS0 0x01
9855 #define _DAC4CON0_DACNSS0 0x01
9856 #define _DAC4CON0_DAC4NSS0 0x01
9857 #define _DAC4CON0_NSS1 0x02
9858 #define _DAC4CON0_DACNSS1 0x02
9859 #define _DAC4CON0_DAC4NSS1 0x02
9860 #define _DAC4CON0_PSS0 0x04
9861 #define _DAC4CON0_DACPSS0 0x04
9862 #define _DAC4CON0_DAC4PSS0 0x04
9863 #define _DAC4CON0_PSS1 0x08
9864 #define _DAC4CON0_DACPSS1 0x08
9865 #define _DAC4CON0_DAC4PSS1 0x08
9866 #define _DAC4CON0_OE2 0x10
9867 #define _DAC4CON0_DACOE2 0x10
9868 #define _DAC4CON0_DAC4OE2 0x10
9869 #define _DAC4CON0_OE1 0x20
9870 #define _DAC4CON0_DACOE1 0x20
9871 #define _DAC4CON0_DAC4OE1 0x20
9872 #define _DAC4CON0_EN 0x80
9873 #define _DAC4CON0_DACEN 0x80
9874 #define _DAC4CON0_DAC4EN 0x80
9876 //==============================================================================
9879 //==============================================================================
9882 extern __at(0x0597) __sfr DAC4CON1
;
9912 unsigned DAC4R0
: 1;
9913 unsigned DAC4R1
: 1;
9914 unsigned DAC4R2
: 1;
9915 unsigned DAC4R3
: 1;
9916 unsigned DAC4R4
: 1;
9936 unsigned DAC4REF0
: 1;
9937 unsigned DAC4REF1
: 1;
9938 unsigned DAC4REF2
: 1;
9939 unsigned DAC4REF3
: 1;
9940 unsigned DAC4REF4
: 1;
9960 unsigned DAC4REF
: 5;
9977 extern __at(0x0597) volatile __DAC4CON1bits_t DAC4CON1bits
;
9979 #define _DAC4CON1_DACR0 0x01
9980 #define _DAC4CON1_R0 0x01
9981 #define _DAC4CON1_DAC4R0 0x01
9982 #define _DAC4CON1_REF0 0x01
9983 #define _DAC4CON1_DAC4REF0 0x01
9984 #define _DAC4CON1_DACR1 0x02
9985 #define _DAC4CON1_R1 0x02
9986 #define _DAC4CON1_DAC4R1 0x02
9987 #define _DAC4CON1_REF1 0x02
9988 #define _DAC4CON1_DAC4REF1 0x02
9989 #define _DAC4CON1_DACR2 0x04
9990 #define _DAC4CON1_R2 0x04
9991 #define _DAC4CON1_DAC4R2 0x04
9992 #define _DAC4CON1_REF2 0x04
9993 #define _DAC4CON1_DAC4REF2 0x04
9994 #define _DAC4CON1_DACR3 0x08
9995 #define _DAC4CON1_R3 0x08
9996 #define _DAC4CON1_DAC4R3 0x08
9997 #define _DAC4CON1_REF3 0x08
9998 #define _DAC4CON1_DAC4REF3 0x08
9999 #define _DAC4CON1_DACR4 0x10
10000 #define _DAC4CON1_R4 0x10
10001 #define _DAC4CON1_DAC4R4 0x10
10002 #define _DAC4CON1_REF4 0x10
10003 #define _DAC4CON1_DAC4REF4 0x10
10005 //==============================================================================
10008 //==============================================================================
10011 extern __at(0x0597) __sfr DAC4REF
;
10017 unsigned DACR0
: 1;
10018 unsigned DACR1
: 1;
10019 unsigned DACR2
: 1;
10020 unsigned DACR3
: 1;
10021 unsigned DACR4
: 1;
10041 unsigned DAC4R0
: 1;
10042 unsigned DAC4R1
: 1;
10043 unsigned DAC4R2
: 1;
10044 unsigned DAC4R3
: 1;
10045 unsigned DAC4R4
: 1;
10065 unsigned DAC4REF0
: 1;
10066 unsigned DAC4REF1
: 1;
10067 unsigned DAC4REF2
: 1;
10068 unsigned DAC4REF3
: 1;
10069 unsigned DAC4REF4
: 1;
10077 unsigned DAC4R
: 5;
10089 unsigned DAC4REF
: 5;
10106 extern __at(0x0597) volatile __DAC4REFbits_t DAC4REFbits
;
10108 #define _DAC4REF_DACR0 0x01
10109 #define _DAC4REF_R0 0x01
10110 #define _DAC4REF_DAC4R0 0x01
10111 #define _DAC4REF_REF0 0x01
10112 #define _DAC4REF_DAC4REF0 0x01
10113 #define _DAC4REF_DACR1 0x02
10114 #define _DAC4REF_R1 0x02
10115 #define _DAC4REF_DAC4R1 0x02
10116 #define _DAC4REF_REF1 0x02
10117 #define _DAC4REF_DAC4REF1 0x02
10118 #define _DAC4REF_DACR2 0x04
10119 #define _DAC4REF_R2 0x04
10120 #define _DAC4REF_DAC4R2 0x04
10121 #define _DAC4REF_REF2 0x04
10122 #define _DAC4REF_DAC4REF2 0x04
10123 #define _DAC4REF_DACR3 0x08
10124 #define _DAC4REF_R3 0x08
10125 #define _DAC4REF_DAC4R3 0x08
10126 #define _DAC4REF_REF3 0x08
10127 #define _DAC4REF_DAC4REF3 0x08
10128 #define _DAC4REF_DACR4 0x10
10129 #define _DAC4REF_R4 0x10
10130 #define _DAC4REF_DAC4R4 0x10
10131 #define _DAC4REF_REF4 0x10
10132 #define _DAC4REF_DAC4REF4 0x10
10134 //==============================================================================
10137 //==============================================================================
10140 extern __at(0x0598) __sfr DAC5CON0
;
10158 unsigned DACNSS0
: 1;
10159 unsigned DACNSS1
: 1;
10160 unsigned DACPSS0
: 1;
10161 unsigned DACPSS1
: 1;
10162 unsigned DACOE2
: 1;
10164 unsigned DACFM
: 1;
10165 unsigned DACEN
: 1;
10170 unsigned DAC5NSS0
: 1;
10171 unsigned DAC5NSS1
: 1;
10172 unsigned DAC5PSS0
: 1;
10173 unsigned DAC5PSS1
: 1;
10174 unsigned DAC5OE2
: 1;
10175 unsigned DACOE1
: 1;
10176 unsigned DAC5FM
: 1;
10177 unsigned DAC5EN
: 1;
10187 unsigned DACOE
: 1;
10199 unsigned DAC5OE1
: 1;
10206 unsigned DAC5NSS
: 2;
10218 unsigned DACNSS
: 2;
10225 unsigned DACPSS
: 2;
10239 unsigned DAC5PSS
: 2;
10242 } __DAC5CON0bits_t
;
10244 extern __at(0x0598) volatile __DAC5CON0bits_t DAC5CON0bits
;
10246 #define _DAC5CON0_NSS0 0x01
10247 #define _DAC5CON0_DACNSS0 0x01
10248 #define _DAC5CON0_DAC5NSS0 0x01
10249 #define _DAC5CON0_NSS1 0x02
10250 #define _DAC5CON0_DACNSS1 0x02
10251 #define _DAC5CON0_DAC5NSS1 0x02
10252 #define _DAC5CON0_PSS0 0x04
10253 #define _DAC5CON0_DACPSS0 0x04
10254 #define _DAC5CON0_DAC5PSS0 0x04
10255 #define _DAC5CON0_PSS1 0x08
10256 #define _DAC5CON0_DACPSS1 0x08
10257 #define _DAC5CON0_DAC5PSS1 0x08
10258 #define _DAC5CON0_OE2 0x10
10259 #define _DAC5CON0_DACOE2 0x10
10260 #define _DAC5CON0_DAC5OE2 0x10
10261 #define _DAC5CON0_OE1 0x20
10262 #define _DAC5CON0_OE 0x20
10263 #define _DAC5CON0_DACOE1 0x20
10264 #define _DAC5CON0_DACOE 0x20
10265 #define _DAC5CON0_DAC5OE1 0x20
10266 #define _DAC5CON0_FM 0x40
10267 #define _DAC5CON0_DACFM 0x40
10268 #define _DAC5CON0_DAC5FM 0x40
10269 #define _DAC5CON0_EN 0x80
10270 #define _DAC5CON0_DACEN 0x80
10271 #define _DAC5CON0_DAC5EN 0x80
10273 //==============================================================================
10276 //==============================================================================
10279 extern __at(0x0599) __sfr DAC5CON1
;
10297 unsigned DAC5REF0
: 1;
10298 unsigned DAC5REF1
: 1;
10299 unsigned DAC5REF2
: 1;
10300 unsigned DAC5REF3
: 1;
10301 unsigned DAC5REF4
: 1;
10302 unsigned DAC5REF5
: 1;
10303 unsigned DAC5REF6
: 1;
10304 unsigned DAC5REF7
: 1;
10321 unsigned DAC5R0
: 1;
10322 unsigned DAC5R1
: 1;
10323 unsigned DAC5R2
: 1;
10324 unsigned DAC5R3
: 1;
10325 unsigned DAC5R4
: 1;
10326 unsigned DAC5R5
: 1;
10327 unsigned DAC5R6
: 1;
10328 unsigned DAC5R7
: 1;
10330 } __DAC5CON1bits_t
;
10332 extern __at(0x0599) volatile __DAC5CON1bits_t DAC5CON1bits
;
10334 #define _DAC5CON1_REF0 0x01
10335 #define _DAC5CON1_DAC5REF0 0x01
10336 #define _DAC5CON1_R0 0x01
10337 #define _DAC5CON1_DAC5R0 0x01
10338 #define _DAC5CON1_REF1 0x02
10339 #define _DAC5CON1_DAC5REF1 0x02
10340 #define _DAC5CON1_R1 0x02
10341 #define _DAC5CON1_DAC5R1 0x02
10342 #define _DAC5CON1_REF2 0x04
10343 #define _DAC5CON1_DAC5REF2 0x04
10344 #define _DAC5CON1_R2 0x04
10345 #define _DAC5CON1_DAC5R2 0x04
10346 #define _DAC5CON1_REF3 0x08
10347 #define _DAC5CON1_DAC5REF3 0x08
10348 #define _DAC5CON1_R3 0x08
10349 #define _DAC5CON1_DAC5R3 0x08
10350 #define _DAC5CON1_REF4 0x10
10351 #define _DAC5CON1_DAC5REF4 0x10
10352 #define _DAC5CON1_R4 0x10
10353 #define _DAC5CON1_DAC5R4 0x10
10354 #define _DAC5CON1_REF5 0x20
10355 #define _DAC5CON1_DAC5REF5 0x20
10356 #define _DAC5CON1_R5 0x20
10357 #define _DAC5CON1_DAC5R5 0x20
10358 #define _DAC5CON1_REF6 0x40
10359 #define _DAC5CON1_DAC5REF6 0x40
10360 #define _DAC5CON1_R6 0x40
10361 #define _DAC5CON1_DAC5R6 0x40
10362 #define _DAC5CON1_REF7 0x80
10363 #define _DAC5CON1_DAC5REF7 0x80
10364 #define _DAC5CON1_R7 0x80
10365 #define _DAC5CON1_DAC5R7 0x80
10367 //==============================================================================
10369 extern __at(0x0599) __sfr DAC5REF
;
10371 //==============================================================================
10374 extern __at(0x0599) __sfr DAC5REFL
;
10392 unsigned DAC5REF0
: 1;
10393 unsigned DAC5REF1
: 1;
10394 unsigned DAC5REF2
: 1;
10395 unsigned DAC5REF3
: 1;
10396 unsigned DAC5REF4
: 1;
10397 unsigned DAC5REF5
: 1;
10398 unsigned DAC5REF6
: 1;
10399 unsigned DAC5REF7
: 1;
10416 unsigned DAC5R0
: 1;
10417 unsigned DAC5R1
: 1;
10418 unsigned DAC5R2
: 1;
10419 unsigned DAC5R3
: 1;
10420 unsigned DAC5R4
: 1;
10421 unsigned DAC5R5
: 1;
10422 unsigned DAC5R6
: 1;
10423 unsigned DAC5R7
: 1;
10425 } __DAC5REFLbits_t
;
10427 extern __at(0x0599) volatile __DAC5REFLbits_t DAC5REFLbits
;
10429 #define _DAC5REFL_REF0 0x01
10430 #define _DAC5REFL_DAC5REF0 0x01
10431 #define _DAC5REFL_R0 0x01
10432 #define _DAC5REFL_DAC5R0 0x01
10433 #define _DAC5REFL_REF1 0x02
10434 #define _DAC5REFL_DAC5REF1 0x02
10435 #define _DAC5REFL_R1 0x02
10436 #define _DAC5REFL_DAC5R1 0x02
10437 #define _DAC5REFL_REF2 0x04
10438 #define _DAC5REFL_DAC5REF2 0x04
10439 #define _DAC5REFL_R2 0x04
10440 #define _DAC5REFL_DAC5R2 0x04
10441 #define _DAC5REFL_REF3 0x08
10442 #define _DAC5REFL_DAC5REF3 0x08
10443 #define _DAC5REFL_R3 0x08
10444 #define _DAC5REFL_DAC5R3 0x08
10445 #define _DAC5REFL_REF4 0x10
10446 #define _DAC5REFL_DAC5REF4 0x10
10447 #define _DAC5REFL_R4 0x10
10448 #define _DAC5REFL_DAC5R4 0x10
10449 #define _DAC5REFL_REF5 0x20
10450 #define _DAC5REFL_DAC5REF5 0x20
10451 #define _DAC5REFL_R5 0x20
10452 #define _DAC5REFL_DAC5R5 0x20
10453 #define _DAC5REFL_REF6 0x40
10454 #define _DAC5REFL_DAC5REF6 0x40
10455 #define _DAC5REFL_R6 0x40
10456 #define _DAC5REFL_DAC5R6 0x40
10457 #define _DAC5REFL_REF7 0x80
10458 #define _DAC5REFL_DAC5REF7 0x80
10459 #define _DAC5REFL_R7 0x80
10460 #define _DAC5REFL_DAC5R7 0x80
10462 //==============================================================================
10465 //==============================================================================
10468 extern __at(0x059A) __sfr DAC5CON2
;
10476 unsigned REF10
: 1;
10477 unsigned REF11
: 1;
10478 unsigned REF12
: 1;
10479 unsigned REF13
: 1;
10480 unsigned REF14
: 1;
10481 unsigned REF15
: 1;
10486 unsigned DAC5REF8
: 1;
10487 unsigned DAC5REF9
: 1;
10488 unsigned DAC5REF10
: 1;
10489 unsigned DAC5REF11
: 1;
10490 unsigned DAC5REF12
: 1;
10491 unsigned DAC5REF13
: 1;
10492 unsigned DAC5REF14
: 1;
10493 unsigned DAC5REF15
: 1;
10510 unsigned DAC5R8
: 1;
10511 unsigned DAC5R9
: 1;
10512 unsigned DAC5R10
: 1;
10513 unsigned DAC5R11
: 1;
10514 unsigned DAC5R12
: 1;
10515 unsigned DAC5R13
: 1;
10516 unsigned DAC5R14
: 1;
10517 unsigned DAC5R15
: 1;
10519 } __DAC5CON2bits_t
;
10521 extern __at(0x059A) volatile __DAC5CON2bits_t DAC5CON2bits
;
10523 #define _DAC5CON2_REF8 0x01
10524 #define _DAC5CON2_DAC5REF8 0x01
10525 #define _DAC5CON2_R8 0x01
10526 #define _DAC5CON2_DAC5R8 0x01
10527 #define _DAC5CON2_REF9 0x02
10528 #define _DAC5CON2_DAC5REF9 0x02
10529 #define _DAC5CON2_R9 0x02
10530 #define _DAC5CON2_DAC5R9 0x02
10531 #define _DAC5CON2_REF10 0x04
10532 #define _DAC5CON2_DAC5REF10 0x04
10533 #define _DAC5CON2_R10 0x04
10534 #define _DAC5CON2_DAC5R10 0x04
10535 #define _DAC5CON2_REF11 0x08
10536 #define _DAC5CON2_DAC5REF11 0x08
10537 #define _DAC5CON2_R11 0x08
10538 #define _DAC5CON2_DAC5R11 0x08
10539 #define _DAC5CON2_REF12 0x10
10540 #define _DAC5CON2_DAC5REF12 0x10
10541 #define _DAC5CON2_R12 0x10
10542 #define _DAC5CON2_DAC5R12 0x10
10543 #define _DAC5CON2_REF13 0x20
10544 #define _DAC5CON2_DAC5REF13 0x20
10545 #define _DAC5CON2_R13 0x20
10546 #define _DAC5CON2_DAC5R13 0x20
10547 #define _DAC5CON2_REF14 0x40
10548 #define _DAC5CON2_DAC5REF14 0x40
10549 #define _DAC5CON2_R14 0x40
10550 #define _DAC5CON2_DAC5R14 0x40
10551 #define _DAC5CON2_REF15 0x80
10552 #define _DAC5CON2_DAC5REF15 0x80
10553 #define _DAC5CON2_R15 0x80
10554 #define _DAC5CON2_DAC5R15 0x80
10556 //==============================================================================
10559 //==============================================================================
10562 extern __at(0x059A) __sfr DAC5REFH
;
10570 unsigned REF10
: 1;
10571 unsigned REF11
: 1;
10572 unsigned REF12
: 1;
10573 unsigned REF13
: 1;
10574 unsigned REF14
: 1;
10575 unsigned REF15
: 1;
10580 unsigned DAC5REF8
: 1;
10581 unsigned DAC5REF9
: 1;
10582 unsigned DAC5REF10
: 1;
10583 unsigned DAC5REF11
: 1;
10584 unsigned DAC5REF12
: 1;
10585 unsigned DAC5REF13
: 1;
10586 unsigned DAC5REF14
: 1;
10587 unsigned DAC5REF15
: 1;
10604 unsigned DAC5R8
: 1;
10605 unsigned DAC5R9
: 1;
10606 unsigned DAC5R10
: 1;
10607 unsigned DAC5R11
: 1;
10608 unsigned DAC5R12
: 1;
10609 unsigned DAC5R13
: 1;
10610 unsigned DAC5R14
: 1;
10611 unsigned DAC5R15
: 1;
10613 } __DAC5REFHbits_t
;
10615 extern __at(0x059A) volatile __DAC5REFHbits_t DAC5REFHbits
;
10617 #define _DAC5REFH_REF8 0x01
10618 #define _DAC5REFH_DAC5REF8 0x01
10619 #define _DAC5REFH_R8 0x01
10620 #define _DAC5REFH_DAC5R8 0x01
10621 #define _DAC5REFH_REF9 0x02
10622 #define _DAC5REFH_DAC5REF9 0x02
10623 #define _DAC5REFH_R9 0x02
10624 #define _DAC5REFH_DAC5R9 0x02
10625 #define _DAC5REFH_REF10 0x04
10626 #define _DAC5REFH_DAC5REF10 0x04
10627 #define _DAC5REFH_R10 0x04
10628 #define _DAC5REFH_DAC5R10 0x04
10629 #define _DAC5REFH_REF11 0x08
10630 #define _DAC5REFH_DAC5REF11 0x08
10631 #define _DAC5REFH_R11 0x08
10632 #define _DAC5REFH_DAC5R11 0x08
10633 #define _DAC5REFH_REF12 0x10
10634 #define _DAC5REFH_DAC5REF12 0x10
10635 #define _DAC5REFH_R12 0x10
10636 #define _DAC5REFH_DAC5R12 0x10
10637 #define _DAC5REFH_REF13 0x20
10638 #define _DAC5REFH_DAC5REF13 0x20
10639 #define _DAC5REFH_R13 0x20
10640 #define _DAC5REFH_DAC5R13 0x20
10641 #define _DAC5REFH_REF14 0x40
10642 #define _DAC5REFH_DAC5REF14 0x40
10643 #define _DAC5REFH_R14 0x40
10644 #define _DAC5REFH_DAC5R14 0x40
10645 #define _DAC5REFH_REF15 0x80
10646 #define _DAC5REFH_DAC5REF15 0x80
10647 #define _DAC5REFH_R15 0x80
10648 #define _DAC5REFH_DAC5R15 0x80
10650 //==============================================================================
10653 //==============================================================================
10656 extern __at(0x059B) __sfr DAC6CON0
;
10674 unsigned DACNSS0
: 1;
10675 unsigned DACNSS1
: 1;
10676 unsigned DACPSS0
: 1;
10677 unsigned DACPSS1
: 1;
10678 unsigned DACOE2
: 1;
10680 unsigned DACFM
: 1;
10681 unsigned DACEN
: 1;
10686 unsigned DAC6NSS0
: 1;
10687 unsigned DAC6NSS1
: 1;
10688 unsigned DAC6PSS0
: 1;
10689 unsigned DAC6PSS1
: 1;
10690 unsigned DAC6OE2
: 1;
10691 unsigned DACOE1
: 1;
10692 unsigned DAC6FM
: 1;
10693 unsigned DAC6EN
: 1;
10703 unsigned DACOE
: 1;
10715 unsigned DAC6OE1
: 1;
10722 unsigned DAC6NSS
: 2;
10728 unsigned DACNSS
: 2;
10741 unsigned DAC6PSS
: 2;
10755 unsigned DACPSS
: 2;
10758 } __DAC6CON0bits_t
;
10760 extern __at(0x059B) volatile __DAC6CON0bits_t DAC6CON0bits
;
10762 #define _DAC6CON0_NSS0 0x01
10763 #define _DAC6CON0_DACNSS0 0x01
10764 #define _DAC6CON0_DAC6NSS0 0x01
10765 #define _DAC6CON0_NSS1 0x02
10766 #define _DAC6CON0_DACNSS1 0x02
10767 #define _DAC6CON0_DAC6NSS1 0x02
10768 #define _DAC6CON0_PSS0 0x04
10769 #define _DAC6CON0_DACPSS0 0x04
10770 #define _DAC6CON0_DAC6PSS0 0x04
10771 #define _DAC6CON0_PSS1 0x08
10772 #define _DAC6CON0_DACPSS1 0x08
10773 #define _DAC6CON0_DAC6PSS1 0x08
10774 #define _DAC6CON0_OE2 0x10
10775 #define _DAC6CON0_DACOE2 0x10
10776 #define _DAC6CON0_DAC6OE2 0x10
10777 #define _DAC6CON0_OE1 0x20
10778 #define _DAC6CON0_OE 0x20
10779 #define _DAC6CON0_DACOE1 0x20
10780 #define _DAC6CON0_DACOE 0x20
10781 #define _DAC6CON0_DAC6OE1 0x20
10782 #define _DAC6CON0_FM 0x40
10783 #define _DAC6CON0_DACFM 0x40
10784 #define _DAC6CON0_DAC6FM 0x40
10785 #define _DAC6CON0_EN 0x80
10786 #define _DAC6CON0_DACEN 0x80
10787 #define _DAC6CON0_DAC6EN 0x80
10789 //==============================================================================
10792 //==============================================================================
10795 extern __at(0x059C) __sfr DAC6CON1
;
10813 unsigned DAC6REF0
: 1;
10814 unsigned DAC6REF1
: 1;
10815 unsigned DAC6REF2
: 1;
10816 unsigned DAC6REF3
: 1;
10817 unsigned DAC6REF4
: 1;
10818 unsigned DAC6REF5
: 1;
10819 unsigned DAC6REF6
: 1;
10820 unsigned DAC6REF7
: 1;
10837 unsigned DAC6R0
: 1;
10838 unsigned DAC6R1
: 1;
10839 unsigned DAC6R2
: 1;
10840 unsigned DAC6R3
: 1;
10841 unsigned DAC6R4
: 1;
10842 unsigned DAC6R5
: 1;
10843 unsigned DAC6R6
: 1;
10844 unsigned DAC6R7
: 1;
10846 } __DAC6CON1bits_t
;
10848 extern __at(0x059C) volatile __DAC6CON1bits_t DAC6CON1bits
;
10850 #define _DAC6CON1_REF0 0x01
10851 #define _DAC6CON1_DAC6REF0 0x01
10852 #define _DAC6CON1_R0 0x01
10853 #define _DAC6CON1_DAC6R0 0x01
10854 #define _DAC6CON1_REF1 0x02
10855 #define _DAC6CON1_DAC6REF1 0x02
10856 #define _DAC6CON1_R1 0x02
10857 #define _DAC6CON1_DAC6R1 0x02
10858 #define _DAC6CON1_REF2 0x04
10859 #define _DAC6CON1_DAC6REF2 0x04
10860 #define _DAC6CON1_R2 0x04
10861 #define _DAC6CON1_DAC6R2 0x04
10862 #define _DAC6CON1_REF3 0x08
10863 #define _DAC6CON1_DAC6REF3 0x08
10864 #define _DAC6CON1_R3 0x08
10865 #define _DAC6CON1_DAC6R3 0x08
10866 #define _DAC6CON1_REF4 0x10
10867 #define _DAC6CON1_DAC6REF4 0x10
10868 #define _DAC6CON1_R4 0x10
10869 #define _DAC6CON1_DAC6R4 0x10
10870 #define _DAC6CON1_REF5 0x20
10871 #define _DAC6CON1_DAC6REF5 0x20
10872 #define _DAC6CON1_R5 0x20
10873 #define _DAC6CON1_DAC6R5 0x20
10874 #define _DAC6CON1_REF6 0x40
10875 #define _DAC6CON1_DAC6REF6 0x40
10876 #define _DAC6CON1_R6 0x40
10877 #define _DAC6CON1_DAC6R6 0x40
10878 #define _DAC6CON1_REF7 0x80
10879 #define _DAC6CON1_DAC6REF7 0x80
10880 #define _DAC6CON1_R7 0x80
10881 #define _DAC6CON1_DAC6R7 0x80
10883 //==============================================================================
10885 extern __at(0x059C) __sfr DAC6REF
;
10887 //==============================================================================
10890 extern __at(0x059C) __sfr DAC6REFL
;
10908 unsigned DAC6REF0
: 1;
10909 unsigned DAC6REF1
: 1;
10910 unsigned DAC6REF2
: 1;
10911 unsigned DAC6REF3
: 1;
10912 unsigned DAC6REF4
: 1;
10913 unsigned DAC6REF5
: 1;
10914 unsigned DAC6REF6
: 1;
10915 unsigned DAC6REF7
: 1;
10932 unsigned DAC6R0
: 1;
10933 unsigned DAC6R1
: 1;
10934 unsigned DAC6R2
: 1;
10935 unsigned DAC6R3
: 1;
10936 unsigned DAC6R4
: 1;
10937 unsigned DAC6R5
: 1;
10938 unsigned DAC6R6
: 1;
10939 unsigned DAC6R7
: 1;
10941 } __DAC6REFLbits_t
;
10943 extern __at(0x059C) volatile __DAC6REFLbits_t DAC6REFLbits
;
10945 #define _DAC6REFL_REF0 0x01
10946 #define _DAC6REFL_DAC6REF0 0x01
10947 #define _DAC6REFL_R0 0x01
10948 #define _DAC6REFL_DAC6R0 0x01
10949 #define _DAC6REFL_REF1 0x02
10950 #define _DAC6REFL_DAC6REF1 0x02
10951 #define _DAC6REFL_R1 0x02
10952 #define _DAC6REFL_DAC6R1 0x02
10953 #define _DAC6REFL_REF2 0x04
10954 #define _DAC6REFL_DAC6REF2 0x04
10955 #define _DAC6REFL_R2 0x04
10956 #define _DAC6REFL_DAC6R2 0x04
10957 #define _DAC6REFL_REF3 0x08
10958 #define _DAC6REFL_DAC6REF3 0x08
10959 #define _DAC6REFL_R3 0x08
10960 #define _DAC6REFL_DAC6R3 0x08
10961 #define _DAC6REFL_REF4 0x10
10962 #define _DAC6REFL_DAC6REF4 0x10
10963 #define _DAC6REFL_R4 0x10
10964 #define _DAC6REFL_DAC6R4 0x10
10965 #define _DAC6REFL_REF5 0x20
10966 #define _DAC6REFL_DAC6REF5 0x20
10967 #define _DAC6REFL_R5 0x20
10968 #define _DAC6REFL_DAC6R5 0x20
10969 #define _DAC6REFL_REF6 0x40
10970 #define _DAC6REFL_DAC6REF6 0x40
10971 #define _DAC6REFL_R6 0x40
10972 #define _DAC6REFL_DAC6R6 0x40
10973 #define _DAC6REFL_REF7 0x80
10974 #define _DAC6REFL_DAC6REF7 0x80
10975 #define _DAC6REFL_R7 0x80
10976 #define _DAC6REFL_DAC6R7 0x80
10978 //==============================================================================
10981 //==============================================================================
10984 extern __at(0x059D) __sfr DAC6CON2
;
10992 unsigned REF10
: 1;
10993 unsigned REF11
: 1;
10994 unsigned REF12
: 1;
10995 unsigned REF13
: 1;
10996 unsigned REF14
: 1;
10997 unsigned REF15
: 1;
11002 unsigned DAC6REF8
: 1;
11003 unsigned DAC6REF9
: 1;
11004 unsigned DAC6REF10
: 1;
11005 unsigned DAC6REF11
: 1;
11006 unsigned DAC6REF12
: 1;
11007 unsigned DAC6REF13
: 1;
11008 unsigned DAC6REF14
: 1;
11009 unsigned DAC6REF15
: 1;
11026 unsigned DAC6R8
: 1;
11027 unsigned DAC6R9
: 1;
11028 unsigned DAC6R10
: 1;
11029 unsigned DAC6R11
: 1;
11030 unsigned DAC6R12
: 1;
11031 unsigned DAC6R13
: 1;
11032 unsigned DAC6R14
: 1;
11033 unsigned DAC6R15
: 1;
11035 } __DAC6CON2bits_t
;
11037 extern __at(0x059D) volatile __DAC6CON2bits_t DAC6CON2bits
;
11039 #define _DAC6CON2_REF8 0x01
11040 #define _DAC6CON2_DAC6REF8 0x01
11041 #define _DAC6CON2_R8 0x01
11042 #define _DAC6CON2_DAC6R8 0x01
11043 #define _DAC6CON2_REF9 0x02
11044 #define _DAC6CON2_DAC6REF9 0x02
11045 #define _DAC6CON2_R9 0x02
11046 #define _DAC6CON2_DAC6R9 0x02
11047 #define _DAC6CON2_REF10 0x04
11048 #define _DAC6CON2_DAC6REF10 0x04
11049 #define _DAC6CON2_R10 0x04
11050 #define _DAC6CON2_DAC6R10 0x04
11051 #define _DAC6CON2_REF11 0x08
11052 #define _DAC6CON2_DAC6REF11 0x08
11053 #define _DAC6CON2_R11 0x08
11054 #define _DAC6CON2_DAC6R11 0x08
11055 #define _DAC6CON2_REF12 0x10
11056 #define _DAC6CON2_DAC6REF12 0x10
11057 #define _DAC6CON2_R12 0x10
11058 #define _DAC6CON2_DAC6R12 0x10
11059 #define _DAC6CON2_REF13 0x20
11060 #define _DAC6CON2_DAC6REF13 0x20
11061 #define _DAC6CON2_R13 0x20
11062 #define _DAC6CON2_DAC6R13 0x20
11063 #define _DAC6CON2_REF14 0x40
11064 #define _DAC6CON2_DAC6REF14 0x40
11065 #define _DAC6CON2_R14 0x40
11066 #define _DAC6CON2_DAC6R14 0x40
11067 #define _DAC6CON2_REF15 0x80
11068 #define _DAC6CON2_DAC6REF15 0x80
11069 #define _DAC6CON2_R15 0x80
11070 #define _DAC6CON2_DAC6R15 0x80
11072 //==============================================================================
11075 //==============================================================================
11078 extern __at(0x059D) __sfr DAC6REFH
;
11086 unsigned REF10
: 1;
11087 unsigned REF11
: 1;
11088 unsigned REF12
: 1;
11089 unsigned REF13
: 1;
11090 unsigned REF14
: 1;
11091 unsigned REF15
: 1;
11096 unsigned DAC6REF8
: 1;
11097 unsigned DAC6REF9
: 1;
11098 unsigned DAC6REF10
: 1;
11099 unsigned DAC6REF11
: 1;
11100 unsigned DAC6REF12
: 1;
11101 unsigned DAC6REF13
: 1;
11102 unsigned DAC6REF14
: 1;
11103 unsigned DAC6REF15
: 1;
11120 unsigned DAC6R8
: 1;
11121 unsigned DAC6R9
: 1;
11122 unsigned DAC6R10
: 1;
11123 unsigned DAC6R11
: 1;
11124 unsigned DAC6R12
: 1;
11125 unsigned DAC6R13
: 1;
11126 unsigned DAC6R14
: 1;
11127 unsigned DAC6R15
: 1;
11129 } __DAC6REFHbits_t
;
11131 extern __at(0x059D) volatile __DAC6REFHbits_t DAC6REFHbits
;
11133 #define _DAC6REFH_REF8 0x01
11134 #define _DAC6REFH_DAC6REF8 0x01
11135 #define _DAC6REFH_R8 0x01
11136 #define _DAC6REFH_DAC6R8 0x01
11137 #define _DAC6REFH_REF9 0x02
11138 #define _DAC6REFH_DAC6REF9 0x02
11139 #define _DAC6REFH_R9 0x02
11140 #define _DAC6REFH_DAC6R9 0x02
11141 #define _DAC6REFH_REF10 0x04
11142 #define _DAC6REFH_DAC6REF10 0x04
11143 #define _DAC6REFH_R10 0x04
11144 #define _DAC6REFH_DAC6R10 0x04
11145 #define _DAC6REFH_REF11 0x08
11146 #define _DAC6REFH_DAC6REF11 0x08
11147 #define _DAC6REFH_R11 0x08
11148 #define _DAC6REFH_DAC6R11 0x08
11149 #define _DAC6REFH_REF12 0x10
11150 #define _DAC6REFH_DAC6REF12 0x10
11151 #define _DAC6REFH_R12 0x10
11152 #define _DAC6REFH_DAC6R12 0x10
11153 #define _DAC6REFH_REF13 0x20
11154 #define _DAC6REFH_DAC6REF13 0x20
11155 #define _DAC6REFH_R13 0x20
11156 #define _DAC6REFH_DAC6R13 0x20
11157 #define _DAC6REFH_REF14 0x40
11158 #define _DAC6REFH_DAC6REF14 0x40
11159 #define _DAC6REFH_R14 0x40
11160 #define _DAC6REFH_DAC6R14 0x40
11161 #define _DAC6REFH_REF15 0x80
11162 #define _DAC6REFH_DAC6REF15 0x80
11163 #define _DAC6REFH_R15 0x80
11164 #define _DAC6REFH_DAC6R15 0x80
11166 //==============================================================================
11169 //==============================================================================
11172 extern __at(0x059E) __sfr DAC7CON0
;
11190 unsigned DACNSS0
: 1;
11191 unsigned DACNSS1
: 1;
11192 unsigned DACPSS0
: 1;
11193 unsigned DACPSS1
: 1;
11194 unsigned DACOE2
: 1;
11195 unsigned DACOE1
: 1;
11197 unsigned DACEN
: 1;
11202 unsigned DAC7NSS0
: 1;
11203 unsigned DAC7NSS1
: 1;
11204 unsigned DAC7PSS0
: 1;
11205 unsigned DAC7PSS1
: 1;
11206 unsigned DAC7OE2
: 1;
11207 unsigned DAC7OE1
: 1;
11209 unsigned DAC7EN
: 1;
11214 unsigned DAC7NSS
: 2;
11226 unsigned DACNSS
: 2;
11233 unsigned DACPSS
: 2;
11240 unsigned DAC7PSS
: 2;
11250 } __DAC7CON0bits_t
;
11252 extern __at(0x059E) volatile __DAC7CON0bits_t DAC7CON0bits
;
11254 #define _DAC7CON0_NSS0 0x01
11255 #define _DAC7CON0_DACNSS0 0x01
11256 #define _DAC7CON0_DAC7NSS0 0x01
11257 #define _DAC7CON0_NSS1 0x02
11258 #define _DAC7CON0_DACNSS1 0x02
11259 #define _DAC7CON0_DAC7NSS1 0x02
11260 #define _DAC7CON0_PSS0 0x04
11261 #define _DAC7CON0_DACPSS0 0x04
11262 #define _DAC7CON0_DAC7PSS0 0x04
11263 #define _DAC7CON0_PSS1 0x08
11264 #define _DAC7CON0_DACPSS1 0x08
11265 #define _DAC7CON0_DAC7PSS1 0x08
11266 #define _DAC7CON0_OE2 0x10
11267 #define _DAC7CON0_DACOE2 0x10
11268 #define _DAC7CON0_DAC7OE2 0x10
11269 #define _DAC7CON0_OE1 0x20
11270 #define _DAC7CON0_DACOE1 0x20
11271 #define _DAC7CON0_DAC7OE1 0x20
11272 #define _DAC7CON0_EN 0x80
11273 #define _DAC7CON0_DACEN 0x80
11274 #define _DAC7CON0_DAC7EN 0x80
11276 //==============================================================================
11279 //==============================================================================
11282 extern __at(0x059F) __sfr DAC7CON1
;
11288 unsigned DACR0
: 1;
11289 unsigned DACR1
: 1;
11290 unsigned DACR2
: 1;
11291 unsigned DACR3
: 1;
11292 unsigned DACR4
: 1;
11312 unsigned DAC7R0
: 1;
11313 unsigned DAC7R1
: 1;
11314 unsigned DAC7R2
: 1;
11315 unsigned DAC7R3
: 1;
11316 unsigned DAC7R4
: 1;
11336 unsigned DAC7REF0
: 1;
11337 unsigned DAC7REF1
: 1;
11338 unsigned DAC7REF2
: 1;
11339 unsigned DAC7REF3
: 1;
11340 unsigned DAC7REF4
: 1;
11348 unsigned DAC7R
: 5;
11366 unsigned DAC7REF
: 5;
11375 } __DAC7CON1bits_t
;
11377 extern __at(0x059F) volatile __DAC7CON1bits_t DAC7CON1bits
;
11379 #define _DAC7CON1_DACR0 0x01
11380 #define _DAC7CON1_R0 0x01
11381 #define _DAC7CON1_DAC7R0 0x01
11382 #define _DAC7CON1_REF0 0x01
11383 #define _DAC7CON1_DAC7REF0 0x01
11384 #define _DAC7CON1_DACR1 0x02
11385 #define _DAC7CON1_R1 0x02
11386 #define _DAC7CON1_DAC7R1 0x02
11387 #define _DAC7CON1_REF1 0x02
11388 #define _DAC7CON1_DAC7REF1 0x02
11389 #define _DAC7CON1_DACR2 0x04
11390 #define _DAC7CON1_R2 0x04
11391 #define _DAC7CON1_DAC7R2 0x04
11392 #define _DAC7CON1_REF2 0x04
11393 #define _DAC7CON1_DAC7REF2 0x04
11394 #define _DAC7CON1_DACR3 0x08
11395 #define _DAC7CON1_R3 0x08
11396 #define _DAC7CON1_DAC7R3 0x08
11397 #define _DAC7CON1_REF3 0x08
11398 #define _DAC7CON1_DAC7REF3 0x08
11399 #define _DAC7CON1_DACR4 0x10
11400 #define _DAC7CON1_R4 0x10
11401 #define _DAC7CON1_DAC7R4 0x10
11402 #define _DAC7CON1_REF4 0x10
11403 #define _DAC7CON1_DAC7REF4 0x10
11405 //==============================================================================
11408 //==============================================================================
11411 extern __at(0x059F) __sfr DAC7REF
;
11417 unsigned DACR0
: 1;
11418 unsigned DACR1
: 1;
11419 unsigned DACR2
: 1;
11420 unsigned DACR3
: 1;
11421 unsigned DACR4
: 1;
11441 unsigned DAC7R0
: 1;
11442 unsigned DAC7R1
: 1;
11443 unsigned DAC7R2
: 1;
11444 unsigned DAC7R3
: 1;
11445 unsigned DAC7R4
: 1;
11465 unsigned DAC7REF0
: 1;
11466 unsigned DAC7REF1
: 1;
11467 unsigned DAC7REF2
: 1;
11468 unsigned DAC7REF3
: 1;
11469 unsigned DAC7REF4
: 1;
11477 unsigned DAC7R
: 5;
11495 unsigned DAC7REF
: 5;
11506 extern __at(0x059F) volatile __DAC7REFbits_t DAC7REFbits
;
11508 #define _DAC7REF_DACR0 0x01
11509 #define _DAC7REF_R0 0x01
11510 #define _DAC7REF_DAC7R0 0x01
11511 #define _DAC7REF_REF0 0x01
11512 #define _DAC7REF_DAC7REF0 0x01
11513 #define _DAC7REF_DACR1 0x02
11514 #define _DAC7REF_R1 0x02
11515 #define _DAC7REF_DAC7R1 0x02
11516 #define _DAC7REF_REF1 0x02
11517 #define _DAC7REF_DAC7REF1 0x02
11518 #define _DAC7REF_DACR2 0x04
11519 #define _DAC7REF_R2 0x04
11520 #define _DAC7REF_DAC7R2 0x04
11521 #define _DAC7REF_REF2 0x04
11522 #define _DAC7REF_DAC7REF2 0x04
11523 #define _DAC7REF_DACR3 0x08
11524 #define _DAC7REF_R3 0x08
11525 #define _DAC7REF_DAC7R3 0x08
11526 #define _DAC7REF_REF3 0x08
11527 #define _DAC7REF_DAC7REF3 0x08
11528 #define _DAC7REF_DACR4 0x10
11529 #define _DAC7REF_R4 0x10
11530 #define _DAC7REF_DAC7R4 0x10
11531 #define _DAC7REF_REF4 0x10
11532 #define _DAC7REF_DAC7REF4 0x10
11534 //==============================================================================
11537 //==============================================================================
11540 extern __at(0x060C) __sfr DAC8CON0
;
11558 unsigned DACNSS0
: 1;
11559 unsigned DACNSS1
: 1;
11560 unsigned DACPSS0
: 1;
11561 unsigned DACPSS1
: 1;
11562 unsigned DACOE2
: 1;
11563 unsigned DACOE1
: 1;
11565 unsigned DACEN
: 1;
11570 unsigned DAC8NSS0
: 1;
11571 unsigned DAC8NSS1
: 1;
11572 unsigned DAC8PSS0
: 1;
11573 unsigned DAC8PSS1
: 1;
11574 unsigned DAC8OE2
: 1;
11575 unsigned DAC8OE1
: 1;
11577 unsigned DAC8EN
: 1;
11588 unsigned DACNSS
: 2;
11594 unsigned DAC8NSS
: 2;
11601 unsigned DAC8PSS
: 2;
11608 unsigned DACPSS
: 2;
11618 } __DAC8CON0bits_t
;
11620 extern __at(0x060C) volatile __DAC8CON0bits_t DAC8CON0bits
;
11622 #define _DAC8CON0_NSS0 0x01
11623 #define _DAC8CON0_DACNSS0 0x01
11624 #define _DAC8CON0_DAC8NSS0 0x01
11625 #define _DAC8CON0_NSS1 0x02
11626 #define _DAC8CON0_DACNSS1 0x02
11627 #define _DAC8CON0_DAC8NSS1 0x02
11628 #define _DAC8CON0_PSS0 0x04
11629 #define _DAC8CON0_DACPSS0 0x04
11630 #define _DAC8CON0_DAC8PSS0 0x04
11631 #define _DAC8CON0_PSS1 0x08
11632 #define _DAC8CON0_DACPSS1 0x08
11633 #define _DAC8CON0_DAC8PSS1 0x08
11634 #define _DAC8CON0_OE2 0x10
11635 #define _DAC8CON0_DACOE2 0x10
11636 #define _DAC8CON0_DAC8OE2 0x10
11637 #define _DAC8CON0_OE1 0x20
11638 #define _DAC8CON0_DACOE1 0x20
11639 #define _DAC8CON0_DAC8OE1 0x20
11640 #define _DAC8CON0_EN 0x80
11641 #define _DAC8CON0_DACEN 0x80
11642 #define _DAC8CON0_DAC8EN 0x80
11644 //==============================================================================
11647 //==============================================================================
11650 extern __at(0x060D) __sfr DAC8CON1
;
11656 unsigned DACR0
: 1;
11657 unsigned DACR1
: 1;
11658 unsigned DACR2
: 1;
11659 unsigned DACR3
: 1;
11660 unsigned DACR4
: 1;
11680 unsigned DAC8R0
: 1;
11681 unsigned DAC8R1
: 1;
11682 unsigned DAC8R2
: 1;
11683 unsigned DAC8R3
: 1;
11684 unsigned DAC8R4
: 1;
11704 unsigned DAC8REF0
: 1;
11705 unsigned DAC8REF1
: 1;
11706 unsigned DAC8REF2
: 1;
11707 unsigned DAC8REF3
: 1;
11708 unsigned DAC8REF4
: 1;
11716 unsigned DAC8R
: 5;
11734 unsigned DAC8REF
: 5;
11743 } __DAC8CON1bits_t
;
11745 extern __at(0x060D) volatile __DAC8CON1bits_t DAC8CON1bits
;
11747 #define _DAC8CON1_DACR0 0x01
11748 #define _DAC8CON1_R0 0x01
11749 #define _DAC8CON1_DAC8R0 0x01
11750 #define _DAC8CON1_REF0 0x01
11751 #define _DAC8CON1_DAC8REF0 0x01
11752 #define _DAC8CON1_DACR1 0x02
11753 #define _DAC8CON1_R1 0x02
11754 #define _DAC8CON1_DAC8R1 0x02
11755 #define _DAC8CON1_REF1 0x02
11756 #define _DAC8CON1_DAC8REF1 0x02
11757 #define _DAC8CON1_DACR2 0x04
11758 #define _DAC8CON1_R2 0x04
11759 #define _DAC8CON1_DAC8R2 0x04
11760 #define _DAC8CON1_REF2 0x04
11761 #define _DAC8CON1_DAC8REF2 0x04
11762 #define _DAC8CON1_DACR3 0x08
11763 #define _DAC8CON1_R3 0x08
11764 #define _DAC8CON1_DAC8R3 0x08
11765 #define _DAC8CON1_REF3 0x08
11766 #define _DAC8CON1_DAC8REF3 0x08
11767 #define _DAC8CON1_DACR4 0x10
11768 #define _DAC8CON1_R4 0x10
11769 #define _DAC8CON1_DAC8R4 0x10
11770 #define _DAC8CON1_REF4 0x10
11771 #define _DAC8CON1_DAC8REF4 0x10
11773 //==============================================================================
11776 //==============================================================================
11779 extern __at(0x060D) __sfr DAC8REF
;
11785 unsigned DACR0
: 1;
11786 unsigned DACR1
: 1;
11787 unsigned DACR2
: 1;
11788 unsigned DACR3
: 1;
11789 unsigned DACR4
: 1;
11809 unsigned DAC8R0
: 1;
11810 unsigned DAC8R1
: 1;
11811 unsigned DAC8R2
: 1;
11812 unsigned DAC8R3
: 1;
11813 unsigned DAC8R4
: 1;
11833 unsigned DAC8REF0
: 1;
11834 unsigned DAC8REF1
: 1;
11835 unsigned DAC8REF2
: 1;
11836 unsigned DAC8REF3
: 1;
11837 unsigned DAC8REF4
: 1;
11845 unsigned DAC8REF
: 5;
11857 unsigned DAC8R
: 5;
11874 extern __at(0x060D) volatile __DAC8REFbits_t DAC8REFbits
;
11876 #define _DAC8REF_DACR0 0x01
11877 #define _DAC8REF_R0 0x01
11878 #define _DAC8REF_DAC8R0 0x01
11879 #define _DAC8REF_REF0 0x01
11880 #define _DAC8REF_DAC8REF0 0x01
11881 #define _DAC8REF_DACR1 0x02
11882 #define _DAC8REF_R1 0x02
11883 #define _DAC8REF_DAC8R1 0x02
11884 #define _DAC8REF_REF1 0x02
11885 #define _DAC8REF_DAC8REF1 0x02
11886 #define _DAC8REF_DACR2 0x04
11887 #define _DAC8REF_R2 0x04
11888 #define _DAC8REF_DAC8R2 0x04
11889 #define _DAC8REF_REF2 0x04
11890 #define _DAC8REF_DAC8REF2 0x04
11891 #define _DAC8REF_DACR3 0x08
11892 #define _DAC8REF_R3 0x08
11893 #define _DAC8REF_DAC8R3 0x08
11894 #define _DAC8REF_REF3 0x08
11895 #define _DAC8REF_DAC8REF3 0x08
11896 #define _DAC8REF_DACR4 0x10
11897 #define _DAC8REF_R4 0x10
11898 #define _DAC8REF_DAC8R4 0x10
11899 #define _DAC8REF_REF4 0x10
11900 #define _DAC8REF_DAC8REF4 0x10
11902 //==============================================================================
11905 //==============================================================================
11908 extern __at(0x060E) __sfr PRG4RTSS
;
11914 unsigned RTSS0
: 1;
11915 unsigned RTSS1
: 1;
11916 unsigned RTSS2
: 1;
11917 unsigned RTSS3
: 1;
11926 unsigned RG4RTSS0
: 1;
11927 unsigned RG4RTSS1
: 1;
11928 unsigned RG4RTSS2
: 1;
11929 unsigned RG4RTSS3
: 1;
11944 unsigned RG4RTSS
: 4;
11947 } __PRG4RTSSbits_t
;
11949 extern __at(0x060E) volatile __PRG4RTSSbits_t PRG4RTSSbits
;
11951 #define _PRG4RTSS_RTSS0 0x01
11952 #define _PRG4RTSS_RG4RTSS0 0x01
11953 #define _PRG4RTSS_RTSS1 0x02
11954 #define _PRG4RTSS_RG4RTSS1 0x02
11955 #define _PRG4RTSS_RTSS2 0x04
11956 #define _PRG4RTSS_RG4RTSS2 0x04
11957 #define _PRG4RTSS_RTSS3 0x08
11958 #define _PRG4RTSS_RG4RTSS3 0x08
11960 //==============================================================================
11963 //==============================================================================
11966 extern __at(0x060F) __sfr PRG4FTSS
;
11972 unsigned FTSS0
: 1;
11973 unsigned FTSS1
: 1;
11974 unsigned FTSS2
: 1;
11975 unsigned FTSS3
: 1;
11984 unsigned RG4FTSS0
: 1;
11985 unsigned RG4FTSS1
: 1;
11986 unsigned RG4FTSS2
: 1;
11987 unsigned RG4FTSS3
: 1;
12002 unsigned RG4FTSS
: 4;
12005 } __PRG4FTSSbits_t
;
12007 extern __at(0x060F) volatile __PRG4FTSSbits_t PRG4FTSSbits
;
12009 #define _PRG4FTSS_FTSS0 0x01
12010 #define _PRG4FTSS_RG4FTSS0 0x01
12011 #define _PRG4FTSS_FTSS1 0x02
12012 #define _PRG4FTSS_RG4FTSS1 0x02
12013 #define _PRG4FTSS_FTSS2 0x04
12014 #define _PRG4FTSS_RG4FTSS2 0x04
12015 #define _PRG4FTSS_FTSS3 0x08
12016 #define _PRG4FTSS_RG4FTSS3 0x08
12018 //==============================================================================
12021 //==============================================================================
12024 extern __at(0x0610) __sfr PRG4INS
;
12042 unsigned RG4INS0
: 1;
12043 unsigned RG4INS1
: 1;
12044 unsigned RG4INS2
: 1;
12045 unsigned RG4INS3
: 1;
12060 unsigned RG4INS
: 4;
12065 extern __at(0x0610) volatile __PRG4INSbits_t PRG4INSbits
;
12067 #define _PRG4INS_INS0 0x01
12068 #define _PRG4INS_RG4INS0 0x01
12069 #define _PRG4INS_INS1 0x02
12070 #define _PRG4INS_RG4INS1 0x02
12071 #define _PRG4INS_INS2 0x04
12072 #define _PRG4INS_RG4INS2 0x04
12073 #define _PRG4INS_INS3 0x08
12074 #define _PRG4INS_RG4INS3 0x08
12076 //==============================================================================
12079 //==============================================================================
12082 extern __at(0x0611) __sfr PRG4CON0
;
12090 unsigned MODE0
: 1;
12091 unsigned MODE1
: 1;
12100 unsigned RG4GO
: 1;
12101 unsigned RG4OS
: 1;
12102 unsigned RG4MODE0
: 1;
12103 unsigned RG4MODE1
: 1;
12104 unsigned RG4REDG
: 1;
12105 unsigned RG4FEDG
: 1;
12107 unsigned RG4EN
: 1;
12120 unsigned RG4MODE
: 2;
12123 } __PRG4CON0bits_t
;
12125 extern __at(0x0611) volatile __PRG4CON0bits_t PRG4CON0bits
;
12127 #define _PRG4CON0_GO 0x01
12128 #define _PRG4CON0_RG4GO 0x01
12129 #define _PRG4CON0_OS 0x02
12130 #define _PRG4CON0_RG4OS 0x02
12131 #define _PRG4CON0_MODE0 0x04
12132 #define _PRG4CON0_RG4MODE0 0x04
12133 #define _PRG4CON0_MODE1 0x08
12134 #define _PRG4CON0_RG4MODE1 0x08
12135 #define _PRG4CON0_REDG 0x10
12136 #define _PRG4CON0_RG4REDG 0x10
12137 #define _PRG4CON0_FEDG 0x20
12138 #define _PRG4CON0_RG4FEDG 0x20
12139 #define _PRG4CON0_EN 0x80
12140 #define _PRG4CON0_RG4EN 0x80
12142 //==============================================================================
12145 //==============================================================================
12148 extern __at(0x0612) __sfr PRG4CON1
;
12166 unsigned RG4RPOL
: 1;
12167 unsigned RG4FPOL
: 1;
12168 unsigned RG4RDY
: 1;
12175 } __PRG4CON1bits_t
;
12177 extern __at(0x0612) volatile __PRG4CON1bits_t PRG4CON1bits
;
12179 #define _PRG4CON1_RPOL 0x01
12180 #define _PRG4CON1_RG4RPOL 0x01
12181 #define _PRG4CON1_FPOL 0x02
12182 #define _PRG4CON1_RG4FPOL 0x02
12183 #define _PRG4CON1_RDY 0x04
12184 #define _PRG4CON1_RG4RDY 0x04
12186 //==============================================================================
12189 //==============================================================================
12192 extern __at(0x0613) __sfr PRG4CON2
;
12198 unsigned ISET0
: 1;
12199 unsigned ISET1
: 1;
12200 unsigned ISET2
: 1;
12201 unsigned ISET3
: 1;
12202 unsigned ISET4
: 1;
12210 unsigned RG4ISET0
: 1;
12211 unsigned RG4ISET1
: 1;
12212 unsigned RG4ISET2
: 1;
12213 unsigned RG4ISET3
: 1;
12214 unsigned RG4ISET4
: 1;
12222 unsigned RG4ISET
: 5;
12231 } __PRG4CON2bits_t
;
12233 extern __at(0x0613) volatile __PRG4CON2bits_t PRG4CON2bits
;
12235 #define _PRG4CON2_ISET0 0x01
12236 #define _PRG4CON2_RG4ISET0 0x01
12237 #define _PRG4CON2_ISET1 0x02
12238 #define _PRG4CON2_RG4ISET1 0x02
12239 #define _PRG4CON2_ISET2 0x04
12240 #define _PRG4CON2_RG4ISET2 0x04
12241 #define _PRG4CON2_ISET3 0x08
12242 #define _PRG4CON2_RG4ISET3 0x08
12243 #define _PRG4CON2_ISET4 0x10
12244 #define _PRG4CON2_RG4ISET4 0x10
12246 //==============================================================================
12249 //==============================================================================
12252 extern __at(0x0614) __sfr PWM3DCL
;
12276 unsigned PWM3DC0
: 1;
12277 unsigned PWM3DC1
: 1;
12288 unsigned PWMPW0
: 1;
12289 unsigned PWMPW1
: 1;
12301 unsigned PWM3DC
: 2;
12307 unsigned PWMPW
: 2;
12311 extern __at(0x0614) volatile __PWM3DCLbits_t PWM3DCLbits
;
12314 #define _PWM3DC0 0x40
12315 #define _PWMPW0 0x40
12317 #define _PWM3DC1 0x80
12318 #define _PWMPW1 0x80
12320 //==============================================================================
12323 //==============================================================================
12326 extern __at(0x0615) __sfr PWM3DCH
;
12344 unsigned PWM3DC2
: 1;
12345 unsigned PWM3DC3
: 1;
12346 unsigned PWM3DC4
: 1;
12347 unsigned PWM3DC5
: 1;
12348 unsigned PWM3DC6
: 1;
12349 unsigned PWM3DC7
: 1;
12350 unsigned PWM3DC8
: 1;
12351 unsigned PWM3DC9
: 1;
12356 unsigned PWMPW2
: 1;
12357 unsigned PWMPW3
: 1;
12358 unsigned PWMPW4
: 1;
12359 unsigned PWMPW5
: 1;
12360 unsigned PWMPW6
: 1;
12361 unsigned PWMPW7
: 1;
12362 unsigned PWMPW8
: 1;
12363 unsigned PWMPW9
: 1;
12367 extern __at(0x0615) volatile __PWM3DCHbits_t PWM3DCHbits
;
12370 #define _PWM3DC2 0x01
12371 #define _PWMPW2 0x01
12373 #define _PWM3DC3 0x02
12374 #define _PWMPW3 0x02
12376 #define _PWM3DC4 0x04
12377 #define _PWMPW4 0x04
12379 #define _PWM3DC5 0x08
12380 #define _PWMPW5 0x08
12382 #define _PWM3DC6 0x10
12383 #define _PWMPW6 0x10
12385 #define _PWM3DC7 0x20
12386 #define _PWMPW7 0x20
12388 #define _PWM3DC8 0x40
12389 #define _PWMPW8 0x40
12391 #define _PWM3DC9 0x80
12392 #define _PWMPW9 0x80
12394 //==============================================================================
12397 //==============================================================================
12400 extern __at(0x0616) __sfr PWM3CON
;
12422 unsigned PWM3POL
: 1;
12423 unsigned PWM3OUT
: 1;
12425 unsigned PWM3EN
: 1;
12429 extern __at(0x0616) volatile __PWM3CONbits_t PWM3CONbits
;
12431 #define _PWM3CON_POL 0x10
12432 #define _PWM3CON_PWM3POL 0x10
12433 #define _PWM3CON_OUT 0x20
12434 #define _PWM3CON_PWM3OUT 0x20
12435 #define _PWM3CON_EN 0x80
12436 #define _PWM3CON_PWM3EN 0x80
12438 //==============================================================================
12441 //==============================================================================
12444 extern __at(0x0617) __sfr PWM4DCL
;
12468 unsigned PWM4DC0
: 1;
12469 unsigned PWM4DC1
: 1;
12480 unsigned PWMPW0
: 1;
12481 unsigned PWMPW1
: 1;
12487 unsigned PWM4DC
: 2;
12499 unsigned PWMPW
: 2;
12503 extern __at(0x0617) volatile __PWM4DCLbits_t PWM4DCLbits
;
12505 #define _PWM4DCL_DC0 0x40
12506 #define _PWM4DCL_PWM4DC0 0x40
12507 #define _PWM4DCL_PWMPW0 0x40
12508 #define _PWM4DCL_DC1 0x80
12509 #define _PWM4DCL_PWM4DC1 0x80
12510 #define _PWM4DCL_PWMPW1 0x80
12512 //==============================================================================
12515 //==============================================================================
12518 extern __at(0x0618) __sfr PWM4DCH
;
12536 unsigned PWM4DC2
: 1;
12537 unsigned PWM4DC3
: 1;
12538 unsigned PWM4DC4
: 1;
12539 unsigned PWM4DC5
: 1;
12540 unsigned PWM4DC6
: 1;
12541 unsigned PWM4DC7
: 1;
12542 unsigned PWM4DC8
: 1;
12543 unsigned PWM4DC9
: 1;
12548 unsigned PWMPW2
: 1;
12549 unsigned PWMPW3
: 1;
12550 unsigned PWMPW4
: 1;
12551 unsigned PWMPW5
: 1;
12552 unsigned PWMPW6
: 1;
12553 unsigned PWMPW7
: 1;
12554 unsigned PWMPW8
: 1;
12555 unsigned PWMPW9
: 1;
12559 extern __at(0x0618) volatile __PWM4DCHbits_t PWM4DCHbits
;
12561 #define _PWM4DCH_DC2 0x01
12562 #define _PWM4DCH_PWM4DC2 0x01
12563 #define _PWM4DCH_PWMPW2 0x01
12564 #define _PWM4DCH_DC3 0x02
12565 #define _PWM4DCH_PWM4DC3 0x02
12566 #define _PWM4DCH_PWMPW3 0x02
12567 #define _PWM4DCH_DC4 0x04
12568 #define _PWM4DCH_PWM4DC4 0x04
12569 #define _PWM4DCH_PWMPW4 0x04
12570 #define _PWM4DCH_DC5 0x08
12571 #define _PWM4DCH_PWM4DC5 0x08
12572 #define _PWM4DCH_PWMPW5 0x08
12573 #define _PWM4DCH_DC6 0x10
12574 #define _PWM4DCH_PWM4DC6 0x10
12575 #define _PWM4DCH_PWMPW6 0x10
12576 #define _PWM4DCH_DC7 0x20
12577 #define _PWM4DCH_PWM4DC7 0x20
12578 #define _PWM4DCH_PWMPW7 0x20
12579 #define _PWM4DCH_DC8 0x40
12580 #define _PWM4DCH_PWM4DC8 0x40
12581 #define _PWM4DCH_PWMPW8 0x40
12582 #define _PWM4DCH_DC9 0x80
12583 #define _PWM4DCH_PWM4DC9 0x80
12584 #define _PWM4DCH_PWMPW9 0x80
12586 //==============================================================================
12589 //==============================================================================
12592 extern __at(0x0619) __sfr PWM4CON
;
12614 unsigned PWM4POL
: 1;
12615 unsigned PWM4OUT
: 1;
12617 unsigned PWM4EN
: 1;
12621 extern __at(0x0619) volatile __PWM4CONbits_t PWM4CONbits
;
12623 #define _PWM4CON_POL 0x10
12624 #define _PWM4CON_PWM4POL 0x10
12625 #define _PWM4CON_OUT 0x20
12626 #define _PWM4CON_PWM4OUT 0x20
12627 #define _PWM4CON_EN 0x80
12628 #define _PWM4CON_PWM4EN 0x80
12630 //==============================================================================
12633 //==============================================================================
12636 extern __at(0x061A) __sfr PWM9DCL
;
12660 unsigned PWM9DC0
: 1;
12661 unsigned PWM9DC1
: 1;
12672 unsigned PWMPW0
: 1;
12673 unsigned PWMPW1
: 1;
12685 unsigned PWM9DC
: 2;
12691 unsigned PWMPW
: 2;
12695 extern __at(0x061A) volatile __PWM9DCLbits_t PWM9DCLbits
;
12697 #define _PWM9DCL_DC0 0x40
12698 #define _PWM9DCL_PWM9DC0 0x40
12699 #define _PWM9DCL_PWMPW0 0x40
12700 #define _PWM9DCL_DC1 0x80
12701 #define _PWM9DCL_PWM9DC1 0x80
12702 #define _PWM9DCL_PWMPW1 0x80
12704 //==============================================================================
12707 //==============================================================================
12710 extern __at(0x061B) __sfr PWM9DCH
;
12728 unsigned PWM9DC2
: 1;
12729 unsigned PWM9DC3
: 1;
12730 unsigned PWM9DC4
: 1;
12731 unsigned PWM9DC5
: 1;
12732 unsigned PWM9DC6
: 1;
12733 unsigned PWM9DC7
: 1;
12734 unsigned PWM9DC8
: 1;
12735 unsigned PWM9DC9
: 1;
12740 unsigned PWMPW2
: 1;
12741 unsigned PWMPW3
: 1;
12742 unsigned PWMPW4
: 1;
12743 unsigned PWMPW5
: 1;
12744 unsigned PWMPW6
: 1;
12745 unsigned PWMPW7
: 1;
12746 unsigned PWMPW8
: 1;
12747 unsigned PWMPW9
: 1;
12751 extern __at(0x061B) volatile __PWM9DCHbits_t PWM9DCHbits
;
12753 #define _PWM9DCH_DC2 0x01
12754 #define _PWM9DCH_PWM9DC2 0x01
12755 #define _PWM9DCH_PWMPW2 0x01
12756 #define _PWM9DCH_DC3 0x02
12757 #define _PWM9DCH_PWM9DC3 0x02
12758 #define _PWM9DCH_PWMPW3 0x02
12759 #define _PWM9DCH_DC4 0x04
12760 #define _PWM9DCH_PWM9DC4 0x04
12761 #define _PWM9DCH_PWMPW4 0x04
12762 #define _PWM9DCH_DC5 0x08
12763 #define _PWM9DCH_PWM9DC5 0x08
12764 #define _PWM9DCH_PWMPW5 0x08
12765 #define _PWM9DCH_DC6 0x10
12766 #define _PWM9DCH_PWM9DC6 0x10
12767 #define _PWM9DCH_PWMPW6 0x10
12768 #define _PWM9DCH_DC7 0x20
12769 #define _PWM9DCH_PWM9DC7 0x20
12770 #define _PWM9DCH_PWMPW7 0x20
12771 #define _PWM9DCH_DC8 0x40
12772 #define _PWM9DCH_PWM9DC8 0x40
12773 #define _PWM9DCH_PWMPW8 0x40
12774 #define _PWM9DCH_DC9 0x80
12775 #define _PWM9DCH_PWM9DC9 0x80
12776 #define _PWM9DCH_PWMPW9 0x80
12778 //==============================================================================
12781 //==============================================================================
12784 extern __at(0x061C) __sfr PWM9CON
;
12806 unsigned PWM9POL
: 1;
12807 unsigned PWM9OUT
: 1;
12809 unsigned PWM9EN
: 1;
12813 extern __at(0x061C) volatile __PWM9CONbits_t PWM9CONbits
;
12815 #define _PWM9CON_POL 0x10
12816 #define _PWM9CON_PWM9POL 0x10
12817 #define _PWM9CON_OUT 0x20
12818 #define _PWM9CON_PWM9OUT 0x20
12819 #define _PWM9CON_EN 0x80
12820 #define _PWM9CON_PWM9EN 0x80
12822 //==============================================================================
12825 //==============================================================================
12828 extern __at(0x061D) __sfr PWM10DCL
;
12852 unsigned PWM10DC0
: 1;
12853 unsigned PWM10DC1
: 1;
12864 unsigned PWMPW0
: 1;
12865 unsigned PWMPW1
: 1;
12877 unsigned PWM10DC
: 2;
12883 unsigned PWMPW
: 2;
12885 } __PWM10DCLbits_t
;
12887 extern __at(0x061D) volatile __PWM10DCLbits_t PWM10DCLbits
;
12889 #define _PWM10DCL_DC0 0x40
12890 #define _PWM10DCL_PWM10DC0 0x40
12891 #define _PWM10DCL_PWMPW0 0x40
12892 #define _PWM10DCL_DC1 0x80
12893 #define _PWM10DCL_PWM10DC1 0x80
12894 #define _PWM10DCL_PWMPW1 0x80
12896 //==============================================================================
12899 //==============================================================================
12902 extern __at(0x061E) __sfr PWM10DCH
;
12920 unsigned PWM10DC2
: 1;
12921 unsigned PWM10DC3
: 1;
12922 unsigned PWM10DC4
: 1;
12923 unsigned PWM10DC5
: 1;
12924 unsigned PWM10DC6
: 1;
12925 unsigned PWM10DC7
: 1;
12926 unsigned PWM10DC8
: 1;
12927 unsigned PWM10DC9
: 1;
12932 unsigned PWMPW2
: 1;
12933 unsigned PWMPW3
: 1;
12934 unsigned PWMPW4
: 1;
12935 unsigned PWMPW5
: 1;
12936 unsigned PWMPW6
: 1;
12937 unsigned PWMPW7
: 1;
12938 unsigned PWMPW8
: 1;
12939 unsigned PWMPW9
: 1;
12941 } __PWM10DCHbits_t
;
12943 extern __at(0x061E) volatile __PWM10DCHbits_t PWM10DCHbits
;
12945 #define _PWM10DCH_DC2 0x01
12946 #define _PWM10DCH_PWM10DC2 0x01
12947 #define _PWM10DCH_PWMPW2 0x01
12948 #define _PWM10DCH_DC3 0x02
12949 #define _PWM10DCH_PWM10DC3 0x02
12950 #define _PWM10DCH_PWMPW3 0x02
12951 #define _PWM10DCH_DC4 0x04
12952 #define _PWM10DCH_PWM10DC4 0x04
12953 #define _PWM10DCH_PWMPW4 0x04
12954 #define _PWM10DCH_DC5 0x08
12955 #define _PWM10DCH_PWM10DC5 0x08
12956 #define _PWM10DCH_PWMPW5 0x08
12957 #define _PWM10DCH_DC6 0x10
12958 #define _PWM10DCH_PWM10DC6 0x10
12959 #define _PWM10DCH_PWMPW6 0x10
12960 #define _PWM10DCH_DC7 0x20
12961 #define _PWM10DCH_PWM10DC7 0x20
12962 #define _PWM10DCH_PWMPW7 0x20
12963 #define _PWM10DCH_DC8 0x40
12964 #define _PWM10DCH_PWM10DC8 0x40
12965 #define _PWM10DCH_PWMPW8 0x40
12966 #define _PWM10DCH_DC9 0x80
12967 #define _PWM10DCH_PWM10DC9 0x80
12968 #define _PWM10DCH_PWMPW9 0x80
12970 //==============================================================================
12973 //==============================================================================
12976 extern __at(0x061F) __sfr PWM10CON
;
12998 unsigned PWM10POL
: 1;
12999 unsigned PWM10OUT
: 1;
13001 unsigned PWM10EN
: 1;
13003 } __PWM10CONbits_t
;
13005 extern __at(0x061F) volatile __PWM10CONbits_t PWM10CONbits
;
13007 #define _PWM10CON_POL 0x10
13008 #define _PWM10CON_PWM10POL 0x10
13009 #define _PWM10CON_OUT 0x20
13010 #define _PWM10CON_PWM10OUT 0x20
13011 #define _PWM10CON_EN 0x80
13012 #define _PWM10CON_PWM10EN 0x80
13014 //==============================================================================
13017 //==============================================================================
13020 extern __at(0x068D) __sfr COG1PHR
;
13038 unsigned G1PHR0
: 1;
13039 unsigned G1PHR1
: 1;
13040 unsigned G1PHR2
: 1;
13041 unsigned G1PHR3
: 1;
13042 unsigned G1PHR4
: 1;
13043 unsigned G1PHR5
: 1;
13050 unsigned G1PHR
: 6;
13061 extern __at(0x068D) volatile __COG1PHRbits_t COG1PHRbits
;
13064 #define _G1PHR0 0x01
13066 #define _G1PHR1 0x02
13068 #define _G1PHR2 0x04
13070 #define _G1PHR3 0x08
13072 #define _G1PHR4 0x10
13074 #define _G1PHR5 0x20
13076 //==============================================================================
13079 //==============================================================================
13082 extern __at(0x068E) __sfr COG1PHF
;
13100 unsigned G1PHF0
: 1;
13101 unsigned G1PHF1
: 1;
13102 unsigned G1PHF2
: 1;
13103 unsigned G1PHF3
: 1;
13104 unsigned G1PHF4
: 1;
13105 unsigned G1PHF5
: 1;
13112 unsigned G1PHF
: 6;
13123 extern __at(0x068E) volatile __COG1PHFbits_t COG1PHFbits
;
13126 #define _G1PHF0 0x01
13128 #define _G1PHF1 0x02
13130 #define _G1PHF2 0x04
13132 #define _G1PHF3 0x08
13134 #define _G1PHF4 0x10
13136 #define _G1PHF5 0x20
13138 //==============================================================================
13141 //==============================================================================
13144 extern __at(0x068F) __sfr COG1BLKR
;
13150 unsigned BLKR0
: 1;
13151 unsigned BLKR1
: 1;
13152 unsigned BLKR2
: 1;
13153 unsigned BLKR3
: 1;
13154 unsigned BLKR4
: 1;
13155 unsigned BLKR5
: 1;
13162 unsigned G1BLKR0
: 1;
13163 unsigned G1BLKR1
: 1;
13164 unsigned G1BLKR2
: 1;
13165 unsigned G1BLKR3
: 1;
13166 unsigned G1BLKR4
: 1;
13167 unsigned G1BLKR5
: 1;
13174 unsigned G1BLKR
: 6;
13183 } __COG1BLKRbits_t
;
13185 extern __at(0x068F) volatile __COG1BLKRbits_t COG1BLKRbits
;
13187 #define _BLKR0 0x01
13188 #define _G1BLKR0 0x01
13189 #define _BLKR1 0x02
13190 #define _G1BLKR1 0x02
13191 #define _BLKR2 0x04
13192 #define _G1BLKR2 0x04
13193 #define _BLKR3 0x08
13194 #define _G1BLKR3 0x08
13195 #define _BLKR4 0x10
13196 #define _G1BLKR4 0x10
13197 #define _BLKR5 0x20
13198 #define _G1BLKR5 0x20
13200 //==============================================================================
13203 //==============================================================================
13206 extern __at(0x0690) __sfr COG1BLKF
;
13212 unsigned BLKF0
: 1;
13213 unsigned BLKF1
: 1;
13214 unsigned BLKF2
: 1;
13215 unsigned BLKF3
: 1;
13216 unsigned BLKF4
: 1;
13217 unsigned BLKF5
: 1;
13224 unsigned G1BLKF0
: 1;
13225 unsigned G1BLKF1
: 1;
13226 unsigned G1BLKF2
: 1;
13227 unsigned G1BLKF3
: 1;
13228 unsigned G1BLKF4
: 1;
13229 unsigned G1BLKF5
: 1;
13242 unsigned G1BLKF
: 6;
13245 } __COG1BLKFbits_t
;
13247 extern __at(0x0690) volatile __COG1BLKFbits_t COG1BLKFbits
;
13249 #define _BLKF0 0x01
13250 #define _G1BLKF0 0x01
13251 #define _BLKF1 0x02
13252 #define _G1BLKF1 0x02
13253 #define _BLKF2 0x04
13254 #define _G1BLKF2 0x04
13255 #define _BLKF3 0x08
13256 #define _G1BLKF3 0x08
13257 #define _BLKF4 0x10
13258 #define _G1BLKF4 0x10
13259 #define _BLKF5 0x20
13260 #define _G1BLKF5 0x20
13262 //==============================================================================
13265 //==============================================================================
13268 extern __at(0x0691) __sfr COG1DBR
;
13286 unsigned G1DBR0
: 1;
13287 unsigned G1DBR1
: 1;
13288 unsigned G1DBR2
: 1;
13289 unsigned G1DBR3
: 1;
13290 unsigned G1DBR4
: 1;
13291 unsigned G1DBR5
: 1;
13298 unsigned G1DBR
: 6;
13309 extern __at(0x0691) volatile __COG1DBRbits_t COG1DBRbits
;
13312 #define _G1DBR0 0x01
13314 #define _G1DBR1 0x02
13316 #define _G1DBR2 0x04
13318 #define _G1DBR3 0x08
13320 #define _G1DBR4 0x10
13322 #define _G1DBR5 0x20
13324 //==============================================================================
13327 //==============================================================================
13330 extern __at(0x0692) __sfr COG1DBF
;
13348 unsigned G1DBF0
: 1;
13349 unsigned G1DBF1
: 1;
13350 unsigned G1DBF2
: 1;
13351 unsigned G1DBF3
: 1;
13352 unsigned G1DBF4
: 1;
13353 unsigned G1DBF5
: 1;
13360 unsigned G1DBF
: 6;
13371 extern __at(0x0692) volatile __COG1DBFbits_t COG1DBFbits
;
13374 #define _G1DBF0 0x01
13376 #define _G1DBF1 0x02
13378 #define _G1DBF2 0x04
13380 #define _G1DBF3 0x08
13382 #define _G1DBF4 0x10
13384 #define _G1DBF5 0x20
13386 //==============================================================================
13389 //==============================================================================
13392 extern __at(0x0693) __sfr COG1CON0
;
13410 unsigned G1MD0
: 1;
13411 unsigned G1MD1
: 1;
13412 unsigned G1MD2
: 1;
13413 unsigned G1CS0
: 1;
13414 unsigned G1CS1
: 1;
13445 } __COG1CON0bits_t
;
13447 extern __at(0x0693) volatile __COG1CON0bits_t COG1CON0bits
;
13449 #define _COG1CON0_MD0 0x01
13450 #define _COG1CON0_G1MD0 0x01
13451 #define _COG1CON0_MD1 0x02
13452 #define _COG1CON0_G1MD1 0x02
13453 #define _COG1CON0_MD2 0x04
13454 #define _COG1CON0_G1MD2 0x04
13455 #define _COG1CON0_CS0 0x08
13456 #define _COG1CON0_G1CS0 0x08
13457 #define _COG1CON0_CS1 0x10
13458 #define _COG1CON0_G1CS1 0x10
13459 #define _COG1CON0_LD 0x40
13460 #define _COG1CON0_G1LD 0x40
13461 #define _COG1CON0_EN 0x80
13462 #define _COG1CON0_G1EN 0x80
13464 //==============================================================================
13467 //==============================================================================
13470 extern __at(0x0694) __sfr COG1CON1
;
13488 unsigned G1POLA
: 1;
13489 unsigned G1POLB
: 1;
13490 unsigned G1POLC
: 1;
13491 unsigned G1POLD
: 1;
13494 unsigned G1FDBS
: 1;
13495 unsigned G1RDBS
: 1;
13497 } __COG1CON1bits_t
;
13499 extern __at(0x0694) volatile __COG1CON1bits_t COG1CON1bits
;
13502 #define _G1POLA 0x01
13504 #define _G1POLB 0x02
13506 #define _G1POLC 0x04
13508 #define _G1POLD 0x08
13510 #define _G1FDBS 0x40
13512 #define _G1RDBS 0x80
13514 //==============================================================================
13517 //==============================================================================
13520 extern __at(0x0695) __sfr COG1RIS0
;
13538 unsigned G1RIS0
: 1;
13539 unsigned G1RIS1
: 1;
13540 unsigned G1RIS2
: 1;
13541 unsigned G1RIS3
: 1;
13542 unsigned G1RIS4
: 1;
13543 unsigned G1RIS5
: 1;
13544 unsigned G1RIS6
: 1;
13545 unsigned G1RIS7
: 1;
13547 } __COG1RIS0bits_t
;
13549 extern __at(0x0695) volatile __COG1RIS0bits_t COG1RIS0bits
;
13552 #define _G1RIS0 0x01
13554 #define _G1RIS1 0x02
13556 #define _G1RIS2 0x04
13558 #define _G1RIS3 0x08
13560 #define _G1RIS4 0x10
13562 #define _G1RIS5 0x20
13564 #define _G1RIS6 0x40
13566 #define _G1RIS7 0x80
13568 //==============================================================================
13571 //==============================================================================
13574 extern __at(0x0696) __sfr COG1RIS1
;
13582 unsigned RIS10
: 1;
13583 unsigned RIS11
: 1;
13584 unsigned RIS12
: 1;
13585 unsigned RIS13
: 1;
13586 unsigned RIS14
: 1;
13587 unsigned RIS15
: 1;
13592 unsigned G1RIS8
: 1;
13593 unsigned G1RIS9
: 1;
13594 unsigned G1RIS10
: 1;
13595 unsigned G1RIS11
: 1;
13596 unsigned G1RIS12
: 1;
13597 unsigned G1RIS13
: 1;
13598 unsigned G1RIS14
: 1;
13599 unsigned G1RIS15
: 1;
13601 } __COG1RIS1bits_t
;
13603 extern __at(0x0696) volatile __COG1RIS1bits_t COG1RIS1bits
;
13606 #define _G1RIS8 0x01
13608 #define _G1RIS9 0x02
13609 #define _RIS10 0x04
13610 #define _G1RIS10 0x04
13611 #define _RIS11 0x08
13612 #define _G1RIS11 0x08
13613 #define _RIS12 0x10
13614 #define _G1RIS12 0x10
13615 #define _RIS13 0x20
13616 #define _G1RIS13 0x20
13617 #define _RIS14 0x40
13618 #define _G1RIS14 0x40
13619 #define _RIS15 0x80
13620 #define _G1RIS15 0x80
13622 //==============================================================================
13625 //==============================================================================
13628 extern __at(0x0697) __sfr COG1RSIM0
;
13634 unsigned RSIM0
: 1;
13635 unsigned RSIM1
: 1;
13636 unsigned RSIM2
: 1;
13637 unsigned RSIM3
: 1;
13638 unsigned RSIM4
: 1;
13639 unsigned RSIM5
: 1;
13640 unsigned RSIM6
: 1;
13641 unsigned RSIM7
: 1;
13646 unsigned G1RSIM0
: 1;
13647 unsigned G1RSIM1
: 1;
13648 unsigned G1RSIM2
: 1;
13649 unsigned G1RSIM3
: 1;
13650 unsigned G1RSIM4
: 1;
13651 unsigned G1RSIM5
: 1;
13652 unsigned G1RSIM6
: 1;
13653 unsigned G1RSIM7
: 1;
13655 } __COG1RSIM0bits_t
;
13657 extern __at(0x0697) volatile __COG1RSIM0bits_t COG1RSIM0bits
;
13659 #define _RSIM0 0x01
13660 #define _G1RSIM0 0x01
13661 #define _RSIM1 0x02
13662 #define _G1RSIM1 0x02
13663 #define _RSIM2 0x04
13664 #define _G1RSIM2 0x04
13665 #define _RSIM3 0x08
13666 #define _G1RSIM3 0x08
13667 #define _RSIM4 0x10
13668 #define _G1RSIM4 0x10
13669 #define _RSIM5 0x20
13670 #define _G1RSIM5 0x20
13671 #define _RSIM6 0x40
13672 #define _G1RSIM6 0x40
13673 #define _RSIM7 0x80
13674 #define _G1RSIM7 0x80
13676 //==============================================================================
13679 //==============================================================================
13682 extern __at(0x0698) __sfr COG1RSIM1
;
13688 unsigned RSIM8
: 1;
13689 unsigned RSIM9
: 1;
13690 unsigned RSIM10
: 1;
13691 unsigned RSIM11
: 1;
13692 unsigned RSIM12
: 1;
13693 unsigned RSIM13
: 1;
13694 unsigned RSIM14
: 1;
13695 unsigned RSIM15
: 1;
13700 unsigned G1RSIM8
: 1;
13701 unsigned G1RSIM9
: 1;
13702 unsigned G1RSIM10
: 1;
13703 unsigned G1RSIM11
: 1;
13704 unsigned G1RSIM12
: 1;
13705 unsigned G1RSIM13
: 1;
13706 unsigned G1RSIM14
: 1;
13707 unsigned G1RSIM15
: 1;
13709 } __COG1RSIM1bits_t
;
13711 extern __at(0x0698) volatile __COG1RSIM1bits_t COG1RSIM1bits
;
13713 #define _RSIM8 0x01
13714 #define _G1RSIM8 0x01
13715 #define _RSIM9 0x02
13716 #define _G1RSIM9 0x02
13717 #define _RSIM10 0x04
13718 #define _G1RSIM10 0x04
13719 #define _RSIM11 0x08
13720 #define _G1RSIM11 0x08
13721 #define _RSIM12 0x10
13722 #define _G1RSIM12 0x10
13723 #define _RSIM13 0x20
13724 #define _G1RSIM13 0x20
13725 #define _RSIM14 0x40
13726 #define _G1RSIM14 0x40
13727 #define _RSIM15 0x80
13728 #define _G1RSIM15 0x80
13730 //==============================================================================
13733 //==============================================================================
13736 extern __at(0x0699) __sfr COG1FIS0
;
13754 unsigned G1FIS0
: 1;
13755 unsigned G1FIS1
: 1;
13756 unsigned G1FIS2
: 1;
13757 unsigned G1FIS3
: 1;
13758 unsigned G1FIS4
: 1;
13759 unsigned G1FIS5
: 1;
13760 unsigned G1FIS6
: 1;
13761 unsigned G1FIS7
: 1;
13763 } __COG1FIS0bits_t
;
13765 extern __at(0x0699) volatile __COG1FIS0bits_t COG1FIS0bits
;
13768 #define _G1FIS0 0x01
13770 #define _G1FIS1 0x02
13772 #define _G1FIS2 0x04
13774 #define _G1FIS3 0x08
13776 #define _G1FIS4 0x10
13778 #define _G1FIS5 0x20
13780 #define _G1FIS6 0x40
13782 #define _G1FIS7 0x80
13784 //==============================================================================
13787 //==============================================================================
13790 extern __at(0x069A) __sfr COG1FIS1
;
13798 unsigned FIS10
: 1;
13799 unsigned FIS11
: 1;
13800 unsigned FIS12
: 1;
13801 unsigned FIS13
: 1;
13802 unsigned FIS14
: 1;
13803 unsigned FIS15
: 1;
13808 unsigned G1FIS8
: 1;
13809 unsigned G1FIS9
: 1;
13810 unsigned G1FIS10
: 1;
13811 unsigned G1FIS11
: 1;
13812 unsigned G1FIS12
: 1;
13813 unsigned G1FIS13
: 1;
13814 unsigned G1FIS14
: 1;
13815 unsigned G1FIS15
: 1;
13817 } __COG1FIS1bits_t
;
13819 extern __at(0x069A) volatile __COG1FIS1bits_t COG1FIS1bits
;
13822 #define _G1FIS8 0x01
13824 #define _G1FIS9 0x02
13825 #define _FIS10 0x04
13826 #define _G1FIS10 0x04
13827 #define _FIS11 0x08
13828 #define _G1FIS11 0x08
13829 #define _FIS12 0x10
13830 #define _G1FIS12 0x10
13831 #define _FIS13 0x20
13832 #define _G1FIS13 0x20
13833 #define _FIS14 0x40
13834 #define _G1FIS14 0x40
13835 #define _FIS15 0x80
13836 #define _G1FIS15 0x80
13838 //==============================================================================
13841 //==============================================================================
13844 extern __at(0x069B) __sfr COG1FSIM0
;
13850 unsigned FSIM0
: 1;
13851 unsigned FSIM1
: 1;
13852 unsigned FSIM2
: 1;
13853 unsigned FSIM3
: 1;
13854 unsigned FSIM4
: 1;
13855 unsigned FSIM5
: 1;
13856 unsigned FSIM6
: 1;
13857 unsigned FSIM7
: 1;
13862 unsigned G1FSIM0
: 1;
13863 unsigned G1FSIM1
: 1;
13864 unsigned G1FSIM2
: 1;
13865 unsigned G1FSIM3
: 1;
13866 unsigned G1FSIM4
: 1;
13867 unsigned G1FSIM5
: 1;
13868 unsigned G1FSIM6
: 1;
13869 unsigned G1FSIM7
: 1;
13871 } __COG1FSIM0bits_t
;
13873 extern __at(0x069B) volatile __COG1FSIM0bits_t COG1FSIM0bits
;
13875 #define _FSIM0 0x01
13876 #define _G1FSIM0 0x01
13877 #define _FSIM1 0x02
13878 #define _G1FSIM1 0x02
13879 #define _FSIM2 0x04
13880 #define _G1FSIM2 0x04
13881 #define _FSIM3 0x08
13882 #define _G1FSIM3 0x08
13883 #define _FSIM4 0x10
13884 #define _G1FSIM4 0x10
13885 #define _FSIM5 0x20
13886 #define _G1FSIM5 0x20
13887 #define _FSIM6 0x40
13888 #define _G1FSIM6 0x40
13889 #define _FSIM7 0x80
13890 #define _G1FSIM7 0x80
13892 //==============================================================================
13895 //==============================================================================
13898 extern __at(0x069C) __sfr COG1FSIM1
;
13904 unsigned FSIM8
: 1;
13905 unsigned FSIM9
: 1;
13906 unsigned FSIM10
: 1;
13907 unsigned FSIM11
: 1;
13908 unsigned FSIM12
: 1;
13909 unsigned FSIM13
: 1;
13910 unsigned FSIM14
: 1;
13911 unsigned FSIM15
: 1;
13916 unsigned G1FSIM8
: 1;
13917 unsigned G1FSIM9
: 1;
13918 unsigned G1FSIM10
: 1;
13919 unsigned G1FSIM11
: 1;
13920 unsigned G1FSIM12
: 1;
13921 unsigned G1FSIM13
: 1;
13922 unsigned G1FSIM14
: 1;
13923 unsigned G1FSIM15
: 1;
13925 } __COG1FSIM1bits_t
;
13927 extern __at(0x069C) volatile __COG1FSIM1bits_t COG1FSIM1bits
;
13929 #define _FSIM8 0x01
13930 #define _G1FSIM8 0x01
13931 #define _FSIM9 0x02
13932 #define _G1FSIM9 0x02
13933 #define _FSIM10 0x04
13934 #define _G1FSIM10 0x04
13935 #define _FSIM11 0x08
13936 #define _G1FSIM11 0x08
13937 #define _FSIM12 0x10
13938 #define _G1FSIM12 0x10
13939 #define _FSIM13 0x20
13940 #define _G1FSIM13 0x20
13941 #define _FSIM14 0x40
13942 #define _G1FSIM14 0x40
13943 #define _FSIM15 0x80
13944 #define _G1FSIM15 0x80
13946 //==============================================================================
13949 //==============================================================================
13952 extern __at(0x069D) __sfr COG1ASD0
;
13960 unsigned ASDAC0
: 1;
13961 unsigned ASDAC1
: 1;
13962 unsigned ASDBD0
: 1;
13963 unsigned ASDBD1
: 1;
13964 unsigned ASREN
: 1;
13972 unsigned G1ASDAC0
: 1;
13973 unsigned G1ASDAC1
: 1;
13974 unsigned G1ASDBD0
: 1;
13975 unsigned G1ASDBD1
: 1;
13976 unsigned ARSEN
: 1;
13977 unsigned G1ASE
: 1;
13988 unsigned G1ARSEN
: 1;
14000 unsigned G1ASREN
: 1;
14007 unsigned ASDAC
: 2;
14014 unsigned G1ASDAC
: 2;
14021 unsigned G1ASDBD
: 2;
14028 unsigned ASDBD
: 2;
14031 } __COG1ASD0bits_t
;
14033 extern __at(0x069D) volatile __COG1ASD0bits_t COG1ASD0bits
;
14035 #define _ASDAC0 0x04
14036 #define _G1ASDAC0 0x04
14037 #define _ASDAC1 0x08
14038 #define _G1ASDAC1 0x08
14039 #define _ASDBD0 0x10
14040 #define _G1ASDBD0 0x10
14041 #define _ASDBD1 0x20
14042 #define _G1ASDBD1 0x20
14043 #define _ASREN 0x40
14044 #define _ARSEN 0x40
14045 #define _G1ARSEN 0x40
14046 #define _G1ASREN 0x40
14048 #define _G1ASE 0x80
14050 //==============================================================================
14053 //==============================================================================
14056 extern __at(0x069E) __sfr COG1ASD1
;
14074 unsigned G1AS0E
: 1;
14075 unsigned G1AS1E
: 1;
14076 unsigned G1AS2E
: 1;
14077 unsigned G1AS3E
: 1;
14078 unsigned G1AS4E
: 1;
14079 unsigned G1AS5E
: 1;
14080 unsigned G1AS6E
: 1;
14081 unsigned G1AS7E
: 1;
14083 } __COG1ASD1bits_t
;
14085 extern __at(0x069E) volatile __COG1ASD1bits_t COG1ASD1bits
;
14088 #define _G1AS0E 0x01
14090 #define _G1AS1E 0x02
14092 #define _G1AS2E 0x04
14094 #define _G1AS3E 0x08
14096 #define _G1AS4E 0x10
14098 #define _G1AS5E 0x20
14100 #define _G1AS6E 0x40
14102 #define _G1AS7E 0x80
14104 //==============================================================================
14107 //==============================================================================
14110 extern __at(0x069F) __sfr COG1STR
;
14120 unsigned SDATA
: 1;
14121 unsigned SDATB
: 1;
14122 unsigned SDATC
: 1;
14123 unsigned SDATD
: 1;
14128 unsigned G1STRA
: 1;
14129 unsigned G1STRB
: 1;
14130 unsigned G1STRC
: 1;
14131 unsigned G1STRD
: 1;
14132 unsigned G1SDATA
: 1;
14133 unsigned G1SDATB
: 1;
14134 unsigned G1SDATC
: 1;
14135 unsigned G1SDATD
: 1;
14139 extern __at(0x069F) volatile __COG1STRbits_t COG1STRbits
;
14142 #define _G1STRA 0x01
14144 #define _G1STRB 0x02
14146 #define _G1STRC 0x04
14148 #define _G1STRD 0x08
14149 #define _SDATA 0x10
14150 #define _G1SDATA 0x10
14151 #define _SDATB 0x20
14152 #define _G1SDATB 0x20
14153 #define _SDATC 0x40
14154 #define _G1SDATC 0x40
14155 #define _SDATD 0x80
14156 #define _G1SDATD 0x80
14158 //==============================================================================
14161 //==============================================================================
14164 extern __at(0x070D) __sfr COG2PHR
;
14182 unsigned G2PHR0
: 1;
14183 unsigned G2PHR1
: 1;
14184 unsigned G2PHR2
: 1;
14185 unsigned G2PHR3
: 1;
14186 unsigned G2PHR4
: 1;
14187 unsigned G2PHR5
: 1;
14194 unsigned G2PHR
: 6;
14205 extern __at(0x070D) volatile __COG2PHRbits_t COG2PHRbits
;
14207 #define _COG2PHR_PHR0 0x01
14208 #define _COG2PHR_G2PHR0 0x01
14209 #define _COG2PHR_PHR1 0x02
14210 #define _COG2PHR_G2PHR1 0x02
14211 #define _COG2PHR_PHR2 0x04
14212 #define _COG2PHR_G2PHR2 0x04
14213 #define _COG2PHR_PHR3 0x08
14214 #define _COG2PHR_G2PHR3 0x08
14215 #define _COG2PHR_PHR4 0x10
14216 #define _COG2PHR_G2PHR4 0x10
14217 #define _COG2PHR_PHR5 0x20
14218 #define _COG2PHR_G2PHR5 0x20
14220 //==============================================================================
14223 //==============================================================================
14226 extern __at(0x070E) __sfr COG2PHF
;
14244 unsigned G2PHF0
: 1;
14245 unsigned G2PHF1
: 1;
14246 unsigned G2PHF2
: 1;
14247 unsigned G2PHF3
: 1;
14248 unsigned G2PHF4
: 1;
14249 unsigned G2PHF5
: 1;
14256 unsigned G2PHF
: 6;
14267 extern __at(0x070E) volatile __COG2PHFbits_t COG2PHFbits
;
14269 #define _COG2PHF_PHF0 0x01
14270 #define _COG2PHF_G2PHF0 0x01
14271 #define _COG2PHF_PHF1 0x02
14272 #define _COG2PHF_G2PHF1 0x02
14273 #define _COG2PHF_PHF2 0x04
14274 #define _COG2PHF_G2PHF2 0x04
14275 #define _COG2PHF_PHF3 0x08
14276 #define _COG2PHF_G2PHF3 0x08
14277 #define _COG2PHF_PHF4 0x10
14278 #define _COG2PHF_G2PHF4 0x10
14279 #define _COG2PHF_PHF5 0x20
14280 #define _COG2PHF_G2PHF5 0x20
14282 //==============================================================================
14285 //==============================================================================
14288 extern __at(0x070F) __sfr COG2BLKR
;
14294 unsigned BLKR0
: 1;
14295 unsigned BLKR1
: 1;
14296 unsigned BLKR2
: 1;
14297 unsigned BLKR3
: 1;
14298 unsigned BLKR4
: 1;
14299 unsigned BLKR5
: 1;
14306 unsigned G2BLKR0
: 1;
14307 unsigned G2BLKR1
: 1;
14308 unsigned G2BLKR2
: 1;
14309 unsigned G2BLKR3
: 1;
14310 unsigned G2BLKR4
: 1;
14311 unsigned G2BLKR5
: 1;
14318 unsigned G2BLKR
: 6;
14327 } __COG2BLKRbits_t
;
14329 extern __at(0x070F) volatile __COG2BLKRbits_t COG2BLKRbits
;
14331 #define _COG2BLKR_BLKR0 0x01
14332 #define _COG2BLKR_G2BLKR0 0x01
14333 #define _COG2BLKR_BLKR1 0x02
14334 #define _COG2BLKR_G2BLKR1 0x02
14335 #define _COG2BLKR_BLKR2 0x04
14336 #define _COG2BLKR_G2BLKR2 0x04
14337 #define _COG2BLKR_BLKR3 0x08
14338 #define _COG2BLKR_G2BLKR3 0x08
14339 #define _COG2BLKR_BLKR4 0x10
14340 #define _COG2BLKR_G2BLKR4 0x10
14341 #define _COG2BLKR_BLKR5 0x20
14342 #define _COG2BLKR_G2BLKR5 0x20
14344 //==============================================================================
14347 //==============================================================================
14350 extern __at(0x0710) __sfr COG2BLKF
;
14356 unsigned BLKF0
: 1;
14357 unsigned BLKF1
: 1;
14358 unsigned BLKF2
: 1;
14359 unsigned BLKF3
: 1;
14360 unsigned BLKF4
: 1;
14361 unsigned BLKF5
: 1;
14368 unsigned G2BLKF0
: 1;
14369 unsigned G2BLKF1
: 1;
14370 unsigned G2BLKF2
: 1;
14371 unsigned G2BLKF3
: 1;
14372 unsigned G2BLKF4
: 1;
14373 unsigned G2BLKF5
: 1;
14380 unsigned G2BLKF
: 6;
14389 } __COG2BLKFbits_t
;
14391 extern __at(0x0710) volatile __COG2BLKFbits_t COG2BLKFbits
;
14393 #define _COG2BLKF_BLKF0 0x01
14394 #define _COG2BLKF_G2BLKF0 0x01
14395 #define _COG2BLKF_BLKF1 0x02
14396 #define _COG2BLKF_G2BLKF1 0x02
14397 #define _COG2BLKF_BLKF2 0x04
14398 #define _COG2BLKF_G2BLKF2 0x04
14399 #define _COG2BLKF_BLKF3 0x08
14400 #define _COG2BLKF_G2BLKF3 0x08
14401 #define _COG2BLKF_BLKF4 0x10
14402 #define _COG2BLKF_G2BLKF4 0x10
14403 #define _COG2BLKF_BLKF5 0x20
14404 #define _COG2BLKF_G2BLKF5 0x20
14406 //==============================================================================
14409 //==============================================================================
14412 extern __at(0x0711) __sfr COG2DBR
;
14430 unsigned G2DBR0
: 1;
14431 unsigned G2DBR1
: 1;
14432 unsigned G2DBR2
: 1;
14433 unsigned G2DBR3
: 1;
14434 unsigned G2DBR4
: 1;
14435 unsigned G2DBR5
: 1;
14442 unsigned G2DBR
: 6;
14453 extern __at(0x0711) volatile __COG2DBRbits_t COG2DBRbits
;
14455 #define _COG2DBR_DBR0 0x01
14456 #define _COG2DBR_G2DBR0 0x01
14457 #define _COG2DBR_DBR1 0x02
14458 #define _COG2DBR_G2DBR1 0x02
14459 #define _COG2DBR_DBR2 0x04
14460 #define _COG2DBR_G2DBR2 0x04
14461 #define _COG2DBR_DBR3 0x08
14462 #define _COG2DBR_G2DBR3 0x08
14463 #define _COG2DBR_DBR4 0x10
14464 #define _COG2DBR_G2DBR4 0x10
14465 #define _COG2DBR_DBR5 0x20
14466 #define _COG2DBR_G2DBR5 0x20
14468 //==============================================================================
14471 //==============================================================================
14474 extern __at(0x0712) __sfr COG2DBF
;
14492 unsigned G2DBF0
: 1;
14493 unsigned G2DBF1
: 1;
14494 unsigned G2DBF2
: 1;
14495 unsigned G2DBF3
: 1;
14496 unsigned G2DBF4
: 1;
14497 unsigned G2DBF5
: 1;
14504 unsigned G2DBF
: 6;
14515 extern __at(0x0712) volatile __COG2DBFbits_t COG2DBFbits
;
14517 #define _COG2DBF_DBF0 0x01
14518 #define _COG2DBF_G2DBF0 0x01
14519 #define _COG2DBF_DBF1 0x02
14520 #define _COG2DBF_G2DBF1 0x02
14521 #define _COG2DBF_DBF2 0x04
14522 #define _COG2DBF_G2DBF2 0x04
14523 #define _COG2DBF_DBF3 0x08
14524 #define _COG2DBF_G2DBF3 0x08
14525 #define _COG2DBF_DBF4 0x10
14526 #define _COG2DBF_G2DBF4 0x10
14527 #define _COG2DBF_DBF5 0x20
14528 #define _COG2DBF_G2DBF5 0x20
14530 //==============================================================================
14533 //==============================================================================
14536 extern __at(0x0713) __sfr COG2CON0
;
14554 unsigned G2MD0
: 1;
14555 unsigned G2MD1
: 1;
14556 unsigned G2MD2
: 1;
14557 unsigned G2CS0
: 1;
14558 unsigned G2CS1
: 1;
14589 } __COG2CON0bits_t
;
14591 extern __at(0x0713) volatile __COG2CON0bits_t COG2CON0bits
;
14593 #define _COG2CON0_MD0 0x01
14594 #define _COG2CON0_G2MD0 0x01
14595 #define _COG2CON0_MD1 0x02
14596 #define _COG2CON0_G2MD1 0x02
14597 #define _COG2CON0_MD2 0x04
14598 #define _COG2CON0_G2MD2 0x04
14599 #define _COG2CON0_CS0 0x08
14600 #define _COG2CON0_G2CS0 0x08
14601 #define _COG2CON0_CS1 0x10
14602 #define _COG2CON0_G2CS1 0x10
14603 #define _COG2CON0_LD 0x40
14604 #define _COG2CON0_G2LD 0x40
14605 #define _COG2CON0_EN 0x80
14606 #define _COG2CON0_G2EN 0x80
14608 //==============================================================================
14611 //==============================================================================
14614 extern __at(0x0714) __sfr COG2CON1
;
14632 unsigned G2POLA
: 1;
14633 unsigned G2POLB
: 1;
14634 unsigned G2POLC
: 1;
14635 unsigned G2POLD
: 1;
14638 unsigned G2FDBS
: 1;
14639 unsigned G2RDBS
: 1;
14641 } __COG2CON1bits_t
;
14643 extern __at(0x0714) volatile __COG2CON1bits_t COG2CON1bits
;
14645 #define _COG2CON1_POLA 0x01
14646 #define _COG2CON1_G2POLA 0x01
14647 #define _COG2CON1_POLB 0x02
14648 #define _COG2CON1_G2POLB 0x02
14649 #define _COG2CON1_POLC 0x04
14650 #define _COG2CON1_G2POLC 0x04
14651 #define _COG2CON1_POLD 0x08
14652 #define _COG2CON1_G2POLD 0x08
14653 #define _COG2CON1_FDBS 0x40
14654 #define _COG2CON1_G2FDBS 0x40
14655 #define _COG2CON1_RDBS 0x80
14656 #define _COG2CON1_G2RDBS 0x80
14658 //==============================================================================
14661 //==============================================================================
14664 extern __at(0x0715) __sfr COG2RIS0
;
14682 unsigned G2RIS0
: 1;
14683 unsigned G2RIS1
: 1;
14684 unsigned G2RIS2
: 1;
14685 unsigned G2RIS3
: 1;
14686 unsigned G2RIS4
: 1;
14687 unsigned G2RIS5
: 1;
14688 unsigned G2RIS6
: 1;
14689 unsigned G2RIS7
: 1;
14691 } __COG2RIS0bits_t
;
14693 extern __at(0x0715) volatile __COG2RIS0bits_t COG2RIS0bits
;
14695 #define _COG2RIS0_RIS0 0x01
14696 #define _COG2RIS0_G2RIS0 0x01
14697 #define _COG2RIS0_RIS1 0x02
14698 #define _COG2RIS0_G2RIS1 0x02
14699 #define _COG2RIS0_RIS2 0x04
14700 #define _COG2RIS0_G2RIS2 0x04
14701 #define _COG2RIS0_RIS3 0x08
14702 #define _COG2RIS0_G2RIS3 0x08
14703 #define _COG2RIS0_RIS4 0x10
14704 #define _COG2RIS0_G2RIS4 0x10
14705 #define _COG2RIS0_RIS5 0x20
14706 #define _COG2RIS0_G2RIS5 0x20
14707 #define _COG2RIS0_RIS6 0x40
14708 #define _COG2RIS0_G2RIS6 0x40
14709 #define _COG2RIS0_RIS7 0x80
14710 #define _COG2RIS0_G2RIS7 0x80
14712 //==============================================================================
14715 //==============================================================================
14718 extern __at(0x0716) __sfr COG2RIS1
;
14726 unsigned RIS10
: 1;
14727 unsigned RIS11
: 1;
14728 unsigned RIS12
: 1;
14729 unsigned RIS13
: 1;
14730 unsigned RIS14
: 1;
14731 unsigned RIS15
: 1;
14736 unsigned G2RIS8
: 1;
14737 unsigned G2RIS9
: 1;
14738 unsigned G2RIS10
: 1;
14739 unsigned G2RIS11
: 1;
14740 unsigned G2RIS12
: 1;
14741 unsigned G2RIS13
: 1;
14742 unsigned G2RIS14
: 1;
14743 unsigned G2RIS15
: 1;
14745 } __COG2RIS1bits_t
;
14747 extern __at(0x0716) volatile __COG2RIS1bits_t COG2RIS1bits
;
14749 #define _COG2RIS1_RIS8 0x01
14750 #define _COG2RIS1_G2RIS8 0x01
14751 #define _COG2RIS1_RIS9 0x02
14752 #define _COG2RIS1_G2RIS9 0x02
14753 #define _COG2RIS1_RIS10 0x04
14754 #define _COG2RIS1_G2RIS10 0x04
14755 #define _COG2RIS1_RIS11 0x08
14756 #define _COG2RIS1_G2RIS11 0x08
14757 #define _COG2RIS1_RIS12 0x10
14758 #define _COG2RIS1_G2RIS12 0x10
14759 #define _COG2RIS1_RIS13 0x20
14760 #define _COG2RIS1_G2RIS13 0x20
14761 #define _COG2RIS1_RIS14 0x40
14762 #define _COG2RIS1_G2RIS14 0x40
14763 #define _COG2RIS1_RIS15 0x80
14764 #define _COG2RIS1_G2RIS15 0x80
14766 //==============================================================================
14769 //==============================================================================
14772 extern __at(0x0717) __sfr COG2RSIM0
;
14778 unsigned RSIM0
: 1;
14779 unsigned RSIM1
: 1;
14780 unsigned RSIM2
: 1;
14781 unsigned RSIM3
: 1;
14782 unsigned RSIM4
: 1;
14783 unsigned RSIM5
: 1;
14784 unsigned RSIM6
: 1;
14785 unsigned RSIM7
: 1;
14790 unsigned G2RSIM0
: 1;
14791 unsigned G2RSIM1
: 1;
14792 unsigned G2RSIM2
: 1;
14793 unsigned G2RSIM3
: 1;
14794 unsigned G2RSIM4
: 1;
14795 unsigned G2RSIM5
: 1;
14796 unsigned G2RSIM6
: 1;
14797 unsigned G2RSIM7
: 1;
14799 } __COG2RSIM0bits_t
;
14801 extern __at(0x0717) volatile __COG2RSIM0bits_t COG2RSIM0bits
;
14803 #define _COG2RSIM0_RSIM0 0x01
14804 #define _COG2RSIM0_G2RSIM0 0x01
14805 #define _COG2RSIM0_RSIM1 0x02
14806 #define _COG2RSIM0_G2RSIM1 0x02
14807 #define _COG2RSIM0_RSIM2 0x04
14808 #define _COG2RSIM0_G2RSIM2 0x04
14809 #define _COG2RSIM0_RSIM3 0x08
14810 #define _COG2RSIM0_G2RSIM3 0x08
14811 #define _COG2RSIM0_RSIM4 0x10
14812 #define _COG2RSIM0_G2RSIM4 0x10
14813 #define _COG2RSIM0_RSIM5 0x20
14814 #define _COG2RSIM0_G2RSIM5 0x20
14815 #define _COG2RSIM0_RSIM6 0x40
14816 #define _COG2RSIM0_G2RSIM6 0x40
14817 #define _COG2RSIM0_RSIM7 0x80
14818 #define _COG2RSIM0_G2RSIM7 0x80
14820 //==============================================================================
14823 //==============================================================================
14826 extern __at(0x0718) __sfr COG2RSIM1
;
14832 unsigned RSIM8
: 1;
14833 unsigned RSIM9
: 1;
14834 unsigned RSIM10
: 1;
14835 unsigned RSIM11
: 1;
14836 unsigned RSIM12
: 1;
14837 unsigned RSIM13
: 1;
14838 unsigned RSIM14
: 1;
14839 unsigned RSIM15
: 1;
14844 unsigned G2RSIM8
: 1;
14845 unsigned G2RSIM9
: 1;
14846 unsigned G2RSIM10
: 1;
14847 unsigned G2RSIM11
: 1;
14848 unsigned G2RSIM12
: 1;
14849 unsigned G2RSIM13
: 1;
14850 unsigned G2RSIM14
: 1;
14851 unsigned G2RSIM15
: 1;
14853 } __COG2RSIM1bits_t
;
14855 extern __at(0x0718) volatile __COG2RSIM1bits_t COG2RSIM1bits
;
14857 #define _COG2RSIM1_RSIM8 0x01
14858 #define _COG2RSIM1_G2RSIM8 0x01
14859 #define _COG2RSIM1_RSIM9 0x02
14860 #define _COG2RSIM1_G2RSIM9 0x02
14861 #define _COG2RSIM1_RSIM10 0x04
14862 #define _COG2RSIM1_G2RSIM10 0x04
14863 #define _COG2RSIM1_RSIM11 0x08
14864 #define _COG2RSIM1_G2RSIM11 0x08
14865 #define _COG2RSIM1_RSIM12 0x10
14866 #define _COG2RSIM1_G2RSIM12 0x10
14867 #define _COG2RSIM1_RSIM13 0x20
14868 #define _COG2RSIM1_G2RSIM13 0x20
14869 #define _COG2RSIM1_RSIM14 0x40
14870 #define _COG2RSIM1_G2RSIM14 0x40
14871 #define _COG2RSIM1_RSIM15 0x80
14872 #define _COG2RSIM1_G2RSIM15 0x80
14874 //==============================================================================
14877 //==============================================================================
14880 extern __at(0x0719) __sfr COG2FIS0
;
14898 unsigned G2FIS0
: 1;
14899 unsigned G2FIS1
: 1;
14900 unsigned G2FIS2
: 1;
14901 unsigned G2FIS3
: 1;
14902 unsigned G2FIS4
: 1;
14903 unsigned G2FIS5
: 1;
14904 unsigned G2FIS6
: 1;
14905 unsigned G2FIS7
: 1;
14907 } __COG2FIS0bits_t
;
14909 extern __at(0x0719) volatile __COG2FIS0bits_t COG2FIS0bits
;
14911 #define _COG2FIS0_FIS0 0x01
14912 #define _COG2FIS0_G2FIS0 0x01
14913 #define _COG2FIS0_FIS1 0x02
14914 #define _COG2FIS0_G2FIS1 0x02
14915 #define _COG2FIS0_FIS2 0x04
14916 #define _COG2FIS0_G2FIS2 0x04
14917 #define _COG2FIS0_FIS3 0x08
14918 #define _COG2FIS0_G2FIS3 0x08
14919 #define _COG2FIS0_FIS4 0x10
14920 #define _COG2FIS0_G2FIS4 0x10
14921 #define _COG2FIS0_FIS5 0x20
14922 #define _COG2FIS0_G2FIS5 0x20
14923 #define _COG2FIS0_FIS6 0x40
14924 #define _COG2FIS0_G2FIS6 0x40
14925 #define _COG2FIS0_FIS7 0x80
14926 #define _COG2FIS0_G2FIS7 0x80
14928 //==============================================================================
14931 //==============================================================================
14934 extern __at(0x071A) __sfr COG2FIS1
;
14942 unsigned FIS10
: 1;
14943 unsigned FIS11
: 1;
14944 unsigned FIS12
: 1;
14945 unsigned FIS13
: 1;
14946 unsigned FIS14
: 1;
14947 unsigned FIS15
: 1;
14952 unsigned G2FIS8
: 1;
14953 unsigned G2FIS9
: 1;
14954 unsigned G2FIS10
: 1;
14955 unsigned G2FIS11
: 1;
14956 unsigned G2FIS12
: 1;
14957 unsigned G2FIS13
: 1;
14958 unsigned G2FIS14
: 1;
14959 unsigned G2FIS15
: 1;
14961 } __COG2FIS1bits_t
;
14963 extern __at(0x071A) volatile __COG2FIS1bits_t COG2FIS1bits
;
14965 #define _COG2FIS1_FIS8 0x01
14966 #define _COG2FIS1_G2FIS8 0x01
14967 #define _COG2FIS1_FIS9 0x02
14968 #define _COG2FIS1_G2FIS9 0x02
14969 #define _COG2FIS1_FIS10 0x04
14970 #define _COG2FIS1_G2FIS10 0x04
14971 #define _COG2FIS1_FIS11 0x08
14972 #define _COG2FIS1_G2FIS11 0x08
14973 #define _COG2FIS1_FIS12 0x10
14974 #define _COG2FIS1_G2FIS12 0x10
14975 #define _COG2FIS1_FIS13 0x20
14976 #define _COG2FIS1_G2FIS13 0x20
14977 #define _COG2FIS1_FIS14 0x40
14978 #define _COG2FIS1_G2FIS14 0x40
14979 #define _COG2FIS1_FIS15 0x80
14980 #define _COG2FIS1_G2FIS15 0x80
14982 //==============================================================================
14985 //==============================================================================
14988 extern __at(0x071B) __sfr COG2FSIM0
;
14994 unsigned FSIM0
: 1;
14995 unsigned FSIM1
: 1;
14996 unsigned FSIM2
: 1;
14997 unsigned FSIM3
: 1;
14998 unsigned FSIM4
: 1;
14999 unsigned FSIM5
: 1;
15000 unsigned FSIM6
: 1;
15001 unsigned FSIM7
: 1;
15006 unsigned G2FSIM0
: 1;
15007 unsigned G2FSIM1
: 1;
15008 unsigned G2FSIM2
: 1;
15009 unsigned G2FSIM3
: 1;
15010 unsigned G2FSIM4
: 1;
15011 unsigned G2FSIM5
: 1;
15012 unsigned G2FSIM6
: 1;
15013 unsigned G2FSIM7
: 1;
15015 } __COG2FSIM0bits_t
;
15017 extern __at(0x071B) volatile __COG2FSIM0bits_t COG2FSIM0bits
;
15019 #define _COG2FSIM0_FSIM0 0x01
15020 #define _COG2FSIM0_G2FSIM0 0x01
15021 #define _COG2FSIM0_FSIM1 0x02
15022 #define _COG2FSIM0_G2FSIM1 0x02
15023 #define _COG2FSIM0_FSIM2 0x04
15024 #define _COG2FSIM0_G2FSIM2 0x04
15025 #define _COG2FSIM0_FSIM3 0x08
15026 #define _COG2FSIM0_G2FSIM3 0x08
15027 #define _COG2FSIM0_FSIM4 0x10
15028 #define _COG2FSIM0_G2FSIM4 0x10
15029 #define _COG2FSIM0_FSIM5 0x20
15030 #define _COG2FSIM0_G2FSIM5 0x20
15031 #define _COG2FSIM0_FSIM6 0x40
15032 #define _COG2FSIM0_G2FSIM6 0x40
15033 #define _COG2FSIM0_FSIM7 0x80
15034 #define _COG2FSIM0_G2FSIM7 0x80
15036 //==============================================================================
15039 //==============================================================================
15042 extern __at(0x071C) __sfr COG2FSIM1
;
15048 unsigned FSIM8
: 1;
15049 unsigned FSIM9
: 1;
15050 unsigned FSIM10
: 1;
15051 unsigned FSIM11
: 1;
15052 unsigned FSIM12
: 1;
15053 unsigned FSIM13
: 1;
15054 unsigned FSIM14
: 1;
15055 unsigned FSIM15
: 1;
15060 unsigned G2FSIM8
: 1;
15061 unsigned G2FSIM9
: 1;
15062 unsigned G2FSIM10
: 1;
15063 unsigned G2FSIM11
: 1;
15064 unsigned G2FSIM12
: 1;
15065 unsigned G2FSIM13
: 1;
15066 unsigned G2FSIM14
: 1;
15067 unsigned G2FSIM15
: 1;
15069 } __COG2FSIM1bits_t
;
15071 extern __at(0x071C) volatile __COG2FSIM1bits_t COG2FSIM1bits
;
15073 #define _COG2FSIM1_FSIM8 0x01
15074 #define _COG2FSIM1_G2FSIM8 0x01
15075 #define _COG2FSIM1_FSIM9 0x02
15076 #define _COG2FSIM1_G2FSIM9 0x02
15077 #define _COG2FSIM1_FSIM10 0x04
15078 #define _COG2FSIM1_G2FSIM10 0x04
15079 #define _COG2FSIM1_FSIM11 0x08
15080 #define _COG2FSIM1_G2FSIM11 0x08
15081 #define _COG2FSIM1_FSIM12 0x10
15082 #define _COG2FSIM1_G2FSIM12 0x10
15083 #define _COG2FSIM1_FSIM13 0x20
15084 #define _COG2FSIM1_G2FSIM13 0x20
15085 #define _COG2FSIM1_FSIM14 0x40
15086 #define _COG2FSIM1_G2FSIM14 0x40
15087 #define _COG2FSIM1_FSIM15 0x80
15088 #define _COG2FSIM1_G2FSIM15 0x80
15090 //==============================================================================
15093 //==============================================================================
15096 extern __at(0x071D) __sfr COG2ASD0
;
15104 unsigned ASDAC0
: 1;
15105 unsigned ASDAC1
: 1;
15106 unsigned ASDBD0
: 1;
15107 unsigned ASDBD1
: 1;
15108 unsigned ASREN
: 1;
15116 unsigned G2ASDAC0
: 1;
15117 unsigned G2ASDAC1
: 1;
15118 unsigned G2ASDBD0
: 1;
15119 unsigned G2ASDBD1
: 1;
15120 unsigned ARSEN
: 1;
15121 unsigned G2ASE
: 1;
15132 unsigned G2ARSEN
: 1;
15144 unsigned G2ASREN
: 1;
15151 unsigned G2ASDAC
: 2;
15158 unsigned ASDAC
: 2;
15165 unsigned G2ASDBD
: 2;
15172 unsigned ASDBD
: 2;
15175 } __COG2ASD0bits_t
;
15177 extern __at(0x071D) volatile __COG2ASD0bits_t COG2ASD0bits
;
15179 #define _COG2ASD0_ASDAC0 0x04
15180 #define _COG2ASD0_G2ASDAC0 0x04
15181 #define _COG2ASD0_ASDAC1 0x08
15182 #define _COG2ASD0_G2ASDAC1 0x08
15183 #define _COG2ASD0_ASDBD0 0x10
15184 #define _COG2ASD0_G2ASDBD0 0x10
15185 #define _COG2ASD0_ASDBD1 0x20
15186 #define _COG2ASD0_G2ASDBD1 0x20
15187 #define _COG2ASD0_ASREN 0x40
15188 #define _COG2ASD0_ARSEN 0x40
15189 #define _COG2ASD0_G2ARSEN 0x40
15190 #define _COG2ASD0_G2ASREN 0x40
15191 #define _COG2ASD0_ASE 0x80
15192 #define _COG2ASD0_G2ASE 0x80
15194 //==============================================================================
15197 //==============================================================================
15200 extern __at(0x071E) __sfr COG2ASD1
;
15218 unsigned G2AS0E
: 1;
15219 unsigned G2AS1E
: 1;
15220 unsigned G2AS2E
: 1;
15221 unsigned G2AS3E
: 1;
15222 unsigned G2AS4E
: 1;
15223 unsigned G2AS5E
: 1;
15224 unsigned G2AS6E
: 1;
15225 unsigned G2AS7E
: 1;
15227 } __COG2ASD1bits_t
;
15229 extern __at(0x071E) volatile __COG2ASD1bits_t COG2ASD1bits
;
15231 #define _COG2ASD1_AS0E 0x01
15232 #define _COG2ASD1_G2AS0E 0x01
15233 #define _COG2ASD1_AS1E 0x02
15234 #define _COG2ASD1_G2AS1E 0x02
15235 #define _COG2ASD1_AS2E 0x04
15236 #define _COG2ASD1_G2AS2E 0x04
15237 #define _COG2ASD1_AS3E 0x08
15238 #define _COG2ASD1_G2AS3E 0x08
15239 #define _COG2ASD1_AS4E 0x10
15240 #define _COG2ASD1_G2AS4E 0x10
15241 #define _COG2ASD1_AS5E 0x20
15242 #define _COG2ASD1_G2AS5E 0x20
15243 #define _COG2ASD1_AS6E 0x40
15244 #define _COG2ASD1_G2AS6E 0x40
15245 #define _COG2ASD1_AS7E 0x80
15246 #define _COG2ASD1_G2AS7E 0x80
15248 //==============================================================================
15251 //==============================================================================
15254 extern __at(0x071F) __sfr COG2STR
;
15264 unsigned SDATA
: 1;
15265 unsigned SDATB
: 1;
15266 unsigned SDATC
: 1;
15267 unsigned SDATD
: 1;
15272 unsigned G2STRA
: 1;
15273 unsigned G2STRB
: 1;
15274 unsigned G2STRC
: 1;
15275 unsigned G2STRD
: 1;
15276 unsigned G2SDATA
: 1;
15277 unsigned G2SDATB
: 1;
15278 unsigned G2SDATC
: 1;
15279 unsigned G2SDATD
: 1;
15283 extern __at(0x071F) volatile __COG2STRbits_t COG2STRbits
;
15285 #define _COG2STR_STRA 0x01
15286 #define _COG2STR_G2STRA 0x01
15287 #define _COG2STR_STRB 0x02
15288 #define _COG2STR_G2STRB 0x02
15289 #define _COG2STR_STRC 0x04
15290 #define _COG2STR_G2STRC 0x04
15291 #define _COG2STR_STRD 0x08
15292 #define _COG2STR_G2STRD 0x08
15293 #define _COG2STR_SDATA 0x10
15294 #define _COG2STR_G2SDATA 0x10
15295 #define _COG2STR_SDATB 0x20
15296 #define _COG2STR_G2SDATB 0x20
15297 #define _COG2STR_SDATC 0x40
15298 #define _COG2STR_G2SDATC 0x40
15299 #define _COG2STR_SDATD 0x80
15300 #define _COG2STR_G2SDATD 0x80
15302 //==============================================================================
15305 //==============================================================================
15308 extern __at(0x078E) __sfr PRG1RTSS
;
15314 unsigned RTSS0
: 1;
15315 unsigned RTSS1
: 1;
15316 unsigned RTSS2
: 1;
15317 unsigned RTSS3
: 1;
15326 unsigned RG1RTSS0
: 1;
15327 unsigned RG1RTSS1
: 1;
15328 unsigned RG1RTSS2
: 1;
15329 unsigned RG1RTSS3
: 1;
15344 unsigned RG1RTSS
: 4;
15347 } __PRG1RTSSbits_t
;
15349 extern __at(0x078E) volatile __PRG1RTSSbits_t PRG1RTSSbits
;
15351 #define _RTSS0 0x01
15352 #define _RG1RTSS0 0x01
15353 #define _RTSS1 0x02
15354 #define _RG1RTSS1 0x02
15355 #define _RTSS2 0x04
15356 #define _RG1RTSS2 0x04
15357 #define _RTSS3 0x08
15358 #define _RG1RTSS3 0x08
15360 //==============================================================================
15363 //==============================================================================
15366 extern __at(0x078F) __sfr PRG1FTSS
;
15372 unsigned FTSS0
: 1;
15373 unsigned FTSS1
: 1;
15374 unsigned FTSS2
: 1;
15375 unsigned FTSS3
: 1;
15384 unsigned RG1FTSS0
: 1;
15385 unsigned RG1FTSS1
: 1;
15386 unsigned RG1FTSS2
: 1;
15387 unsigned RG1FTSS3
: 1;
15396 unsigned RG1FTSS
: 4;
15405 } __PRG1FTSSbits_t
;
15407 extern __at(0x078F) volatile __PRG1FTSSbits_t PRG1FTSSbits
;
15409 #define _FTSS0 0x01
15410 #define _RG1FTSS0 0x01
15411 #define _FTSS1 0x02
15412 #define _RG1FTSS1 0x02
15413 #define _FTSS2 0x04
15414 #define _RG1FTSS2 0x04
15415 #define _FTSS3 0x08
15416 #define _RG1FTSS3 0x08
15418 //==============================================================================
15421 //==============================================================================
15424 extern __at(0x0790) __sfr PRG1INS
;
15442 unsigned RG1INS0
: 1;
15443 unsigned RG1INS1
: 1;
15444 unsigned RG1INS2
: 1;
15445 unsigned RG1INS3
: 1;
15460 unsigned RG1INS
: 4;
15465 extern __at(0x0790) volatile __PRG1INSbits_t PRG1INSbits
;
15468 #define _RG1INS0 0x01
15470 #define _RG1INS1 0x02
15472 #define _RG1INS2 0x04
15474 #define _RG1INS3 0x08
15476 //==============================================================================
15479 //==============================================================================
15482 extern __at(0x0791) __sfr PRG1CON0
;
15490 unsigned MODE0
: 1;
15491 unsigned MODE1
: 1;
15500 unsigned RG1GO
: 1;
15501 unsigned RG1OS
: 1;
15502 unsigned RG1MODE0
: 1;
15503 unsigned RG1MODE1
: 1;
15504 unsigned RG1REDG
: 1;
15505 unsigned RG1FEDG
: 1;
15507 unsigned RG1EN
: 1;
15513 unsigned RG1MODE
: 2;
15523 } __PRG1CON0bits_t
;
15525 extern __at(0x0791) volatile __PRG1CON0bits_t PRG1CON0bits
;
15527 #define _PRG1CON0_GO 0x01
15528 #define _PRG1CON0_RG1GO 0x01
15529 #define _PRG1CON0_OS 0x02
15530 #define _PRG1CON0_RG1OS 0x02
15531 #define _PRG1CON0_MODE0 0x04
15532 #define _PRG1CON0_RG1MODE0 0x04
15533 #define _PRG1CON0_MODE1 0x08
15534 #define _PRG1CON0_RG1MODE1 0x08
15535 #define _PRG1CON0_REDG 0x10
15536 #define _PRG1CON0_RG1REDG 0x10
15537 #define _PRG1CON0_FEDG 0x20
15538 #define _PRG1CON0_RG1FEDG 0x20
15539 #define _PRG1CON0_EN 0x80
15540 #define _PRG1CON0_RG1EN 0x80
15542 //==============================================================================
15545 //==============================================================================
15548 extern __at(0x0792) __sfr PRG1CON1
;
15566 unsigned RG1RPOL
: 1;
15567 unsigned RG1FPOL
: 1;
15568 unsigned RG1RDY
: 1;
15575 } __PRG1CON1bits_t
;
15577 extern __at(0x0792) volatile __PRG1CON1bits_t PRG1CON1bits
;
15580 #define _RG1RPOL 0x01
15582 #define _RG1FPOL 0x02
15584 #define _RG1RDY 0x04
15586 //==============================================================================
15589 //==============================================================================
15592 extern __at(0x0793) __sfr PRG1CON2
;
15598 unsigned ISET0
: 1;
15599 unsigned ISET1
: 1;
15600 unsigned ISET2
: 1;
15601 unsigned ISET3
: 1;
15602 unsigned ISET4
: 1;
15610 unsigned RG1ISET0
: 1;
15611 unsigned RG1ISET1
: 1;
15612 unsigned RG1ISET2
: 1;
15613 unsigned RG1ISET3
: 1;
15614 unsigned RG1ISET4
: 1;
15622 unsigned RG1ISET
: 5;
15631 } __PRG1CON2bits_t
;
15633 extern __at(0x0793) volatile __PRG1CON2bits_t PRG1CON2bits
;
15635 #define _ISET0 0x01
15636 #define _RG1ISET0 0x01
15637 #define _ISET1 0x02
15638 #define _RG1ISET1 0x02
15639 #define _ISET2 0x04
15640 #define _RG1ISET2 0x04
15641 #define _ISET3 0x08
15642 #define _RG1ISET3 0x08
15643 #define _ISET4 0x10
15644 #define _RG1ISET4 0x10
15646 //==============================================================================
15649 //==============================================================================
15652 extern __at(0x0794) __sfr PRG2RTSS
;
15658 unsigned RTSS0
: 1;
15659 unsigned RTSS1
: 1;
15660 unsigned RTSS2
: 1;
15661 unsigned RTSS3
: 1;
15670 unsigned RG2RTSS0
: 1;
15671 unsigned RG2RTSS1
: 1;
15672 unsigned RG2RTSS2
: 1;
15673 unsigned RG2RTSS3
: 1;
15682 unsigned RG2RTSS
: 4;
15691 } __PRG2RTSSbits_t
;
15693 extern __at(0x0794) volatile __PRG2RTSSbits_t PRG2RTSSbits
;
15695 #define _PRG2RTSS_RTSS0 0x01
15696 #define _PRG2RTSS_RG2RTSS0 0x01
15697 #define _PRG2RTSS_RTSS1 0x02
15698 #define _PRG2RTSS_RG2RTSS1 0x02
15699 #define _PRG2RTSS_RTSS2 0x04
15700 #define _PRG2RTSS_RG2RTSS2 0x04
15701 #define _PRG2RTSS_RTSS3 0x08
15702 #define _PRG2RTSS_RG2RTSS3 0x08
15704 //==============================================================================
15707 //==============================================================================
15710 extern __at(0x0795) __sfr PRG2FTSS
;
15716 unsigned FTSS0
: 1;
15717 unsigned FTSS1
: 1;
15718 unsigned FTSS2
: 1;
15719 unsigned FTSS3
: 1;
15728 unsigned RG2FTSS0
: 1;
15729 unsigned RG2FTSS1
: 1;
15730 unsigned RG2FTSS2
: 1;
15731 unsigned RG2FTSS3
: 1;
15740 unsigned RG2FTSS
: 4;
15749 } __PRG2FTSSbits_t
;
15751 extern __at(0x0795) volatile __PRG2FTSSbits_t PRG2FTSSbits
;
15753 #define _PRG2FTSS_FTSS0 0x01
15754 #define _PRG2FTSS_RG2FTSS0 0x01
15755 #define _PRG2FTSS_FTSS1 0x02
15756 #define _PRG2FTSS_RG2FTSS1 0x02
15757 #define _PRG2FTSS_FTSS2 0x04
15758 #define _PRG2FTSS_RG2FTSS2 0x04
15759 #define _PRG2FTSS_FTSS3 0x08
15760 #define _PRG2FTSS_RG2FTSS3 0x08
15762 //==============================================================================
15765 //==============================================================================
15768 extern __at(0x0796) __sfr PRG2INS
;
15786 unsigned RG2INS0
: 1;
15787 unsigned RG2INS1
: 1;
15788 unsigned RG2INS2
: 1;
15789 unsigned RG2INS3
: 1;
15804 unsigned RG2INS
: 4;
15809 extern __at(0x0796) volatile __PRG2INSbits_t PRG2INSbits
;
15811 #define _PRG2INS_INS0 0x01
15812 #define _PRG2INS_RG2INS0 0x01
15813 #define _PRG2INS_INS1 0x02
15814 #define _PRG2INS_RG2INS1 0x02
15815 #define _PRG2INS_INS2 0x04
15816 #define _PRG2INS_RG2INS2 0x04
15817 #define _PRG2INS_INS3 0x08
15818 #define _PRG2INS_RG2INS3 0x08
15820 //==============================================================================
15823 //==============================================================================
15826 extern __at(0x0797) __sfr PRG2CON0
;
15834 unsigned MODE0
: 1;
15835 unsigned MODE1
: 1;
15844 unsigned RG2GO
: 1;
15845 unsigned RG2OS
: 1;
15846 unsigned RG2MODE0
: 1;
15847 unsigned RG2MODE1
: 1;
15848 unsigned RG2REDG
: 1;
15849 unsigned RG2FEDG
: 1;
15851 unsigned RG2EN
: 1;
15864 unsigned RG2MODE
: 2;
15867 } __PRG2CON0bits_t
;
15869 extern __at(0x0797) volatile __PRG2CON0bits_t PRG2CON0bits
;
15871 #define _PRG2CON0_GO 0x01
15872 #define _PRG2CON0_RG2GO 0x01
15873 #define _PRG2CON0_OS 0x02
15874 #define _PRG2CON0_RG2OS 0x02
15875 #define _PRG2CON0_MODE0 0x04
15876 #define _PRG2CON0_RG2MODE0 0x04
15877 #define _PRG2CON0_MODE1 0x08
15878 #define _PRG2CON0_RG2MODE1 0x08
15879 #define _PRG2CON0_REDG 0x10
15880 #define _PRG2CON0_RG2REDG 0x10
15881 #define _PRG2CON0_FEDG 0x20
15882 #define _PRG2CON0_RG2FEDG 0x20
15883 #define _PRG2CON0_EN 0x80
15884 #define _PRG2CON0_RG2EN 0x80
15886 //==============================================================================
15889 //==============================================================================
15892 extern __at(0x0798) __sfr PRG2CON1
;
15910 unsigned RG2RPOL
: 1;
15911 unsigned RG2FPOL
: 1;
15912 unsigned RG2RDY
: 1;
15919 } __PRG2CON1bits_t
;
15921 extern __at(0x0798) volatile __PRG2CON1bits_t PRG2CON1bits
;
15923 #define _PRG2CON1_RPOL 0x01
15924 #define _PRG2CON1_RG2RPOL 0x01
15925 #define _PRG2CON1_FPOL 0x02
15926 #define _PRG2CON1_RG2FPOL 0x02
15927 #define _PRG2CON1_RDY 0x04
15928 #define _PRG2CON1_RG2RDY 0x04
15930 //==============================================================================
15933 //==============================================================================
15936 extern __at(0x0799) __sfr PRG2CON2
;
15942 unsigned ISET0
: 1;
15943 unsigned ISET1
: 1;
15944 unsigned ISET2
: 1;
15945 unsigned ISET3
: 1;
15946 unsigned ISET4
: 1;
15954 unsigned RG2ISET0
: 1;
15955 unsigned RG2ISET1
: 1;
15956 unsigned RG2ISET2
: 1;
15957 unsigned RG2ISET3
: 1;
15958 unsigned RG2ISET4
: 1;
15966 unsigned RG2ISET
: 5;
15975 } __PRG2CON2bits_t
;
15977 extern __at(0x0799) volatile __PRG2CON2bits_t PRG2CON2bits
;
15979 #define _PRG2CON2_ISET0 0x01
15980 #define _PRG2CON2_RG2ISET0 0x01
15981 #define _PRG2CON2_ISET1 0x02
15982 #define _PRG2CON2_RG2ISET1 0x02
15983 #define _PRG2CON2_ISET2 0x04
15984 #define _PRG2CON2_RG2ISET2 0x04
15985 #define _PRG2CON2_ISET3 0x08
15986 #define _PRG2CON2_RG2ISET3 0x08
15987 #define _PRG2CON2_ISET4 0x10
15988 #define _PRG2CON2_RG2ISET4 0x10
15990 //==============================================================================
15993 //==============================================================================
15996 extern __at(0x079A) __sfr PRG3RTSS
;
16002 unsigned RTSS0
: 1;
16003 unsigned RTSS1
: 1;
16004 unsigned RTSS2
: 1;
16005 unsigned RTSS3
: 1;
16014 unsigned RG3RTSS0
: 1;
16015 unsigned RG3RTSS1
: 1;
16016 unsigned RG3RTSS2
: 1;
16017 unsigned RG3RTSS3
: 1;
16026 unsigned RG3RTSS
: 4;
16035 } __PRG3RTSSbits_t
;
16037 extern __at(0x079A) volatile __PRG3RTSSbits_t PRG3RTSSbits
;
16039 #define _PRG3RTSS_RTSS0 0x01
16040 #define _PRG3RTSS_RG3RTSS0 0x01
16041 #define _PRG3RTSS_RTSS1 0x02
16042 #define _PRG3RTSS_RG3RTSS1 0x02
16043 #define _PRG3RTSS_RTSS2 0x04
16044 #define _PRG3RTSS_RG3RTSS2 0x04
16045 #define _PRG3RTSS_RTSS3 0x08
16046 #define _PRG3RTSS_RG3RTSS3 0x08
16048 //==============================================================================
16051 //==============================================================================
16054 extern __at(0x079B) __sfr PRG3FTSS
;
16060 unsigned FTSS0
: 1;
16061 unsigned FTSS1
: 1;
16062 unsigned FTSS2
: 1;
16063 unsigned FTSS3
: 1;
16072 unsigned RG3FTSS0
: 1;
16073 unsigned RG3FTSS1
: 1;
16074 unsigned RG3FTSS2
: 1;
16075 unsigned RG3FTSS3
: 1;
16084 unsigned RG3FTSS
: 4;
16093 } __PRG3FTSSbits_t
;
16095 extern __at(0x079B) volatile __PRG3FTSSbits_t PRG3FTSSbits
;
16097 #define _PRG3FTSS_FTSS0 0x01
16098 #define _PRG3FTSS_RG3FTSS0 0x01
16099 #define _PRG3FTSS_FTSS1 0x02
16100 #define _PRG3FTSS_RG3FTSS1 0x02
16101 #define _PRG3FTSS_FTSS2 0x04
16102 #define _PRG3FTSS_RG3FTSS2 0x04
16103 #define _PRG3FTSS_FTSS3 0x08
16104 #define _PRG3FTSS_RG3FTSS3 0x08
16106 //==============================================================================
16109 //==============================================================================
16112 extern __at(0x079C) __sfr PRG3INS
;
16130 unsigned RG3INS0
: 1;
16131 unsigned RG3INS1
: 1;
16132 unsigned RG3INS2
: 1;
16133 unsigned RG3INS3
: 1;
16142 unsigned RG3INS
: 4;
16153 extern __at(0x079C) volatile __PRG3INSbits_t PRG3INSbits
;
16155 #define _PRG3INS_INS0 0x01
16156 #define _PRG3INS_RG3INS0 0x01
16157 #define _PRG3INS_INS1 0x02
16158 #define _PRG3INS_RG3INS1 0x02
16159 #define _PRG3INS_INS2 0x04
16160 #define _PRG3INS_RG3INS2 0x04
16161 #define _PRG3INS_INS3 0x08
16162 #define _PRG3INS_RG3INS3 0x08
16164 //==============================================================================
16167 //==============================================================================
16170 extern __at(0x079D) __sfr PRG3CON0
;
16178 unsigned MODE0
: 1;
16179 unsigned MODE1
: 1;
16188 unsigned RG3GO
: 1;
16189 unsigned RG3OS
: 1;
16190 unsigned RG3MODE0
: 1;
16191 unsigned RG3MODE1
: 1;
16192 unsigned RG3REDG
: 1;
16193 unsigned RG3FEDG
: 1;
16195 unsigned RG3EN
: 1;
16201 unsigned RG3MODE
: 2;
16211 } __PRG3CON0bits_t
;
16213 extern __at(0x079D) volatile __PRG3CON0bits_t PRG3CON0bits
;
16215 #define _PRG3CON0_GO 0x01
16216 #define _PRG3CON0_RG3GO 0x01
16217 #define _PRG3CON0_OS 0x02
16218 #define _PRG3CON0_RG3OS 0x02
16219 #define _PRG3CON0_MODE0 0x04
16220 #define _PRG3CON0_RG3MODE0 0x04
16221 #define _PRG3CON0_MODE1 0x08
16222 #define _PRG3CON0_RG3MODE1 0x08
16223 #define _PRG3CON0_REDG 0x10
16224 #define _PRG3CON0_RG3REDG 0x10
16225 #define _PRG3CON0_FEDG 0x20
16226 #define _PRG3CON0_RG3FEDG 0x20
16227 #define _PRG3CON0_EN 0x80
16228 #define _PRG3CON0_RG3EN 0x80
16230 //==============================================================================
16233 //==============================================================================
16236 extern __at(0x079E) __sfr PRG3CON1
;
16254 unsigned RG3RPOL
: 1;
16255 unsigned RG3FPOL
: 1;
16256 unsigned RG3RDY
: 1;
16263 } __PRG3CON1bits_t
;
16265 extern __at(0x079E) volatile __PRG3CON1bits_t PRG3CON1bits
;
16267 #define _PRG3CON1_RPOL 0x01
16268 #define _PRG3CON1_RG3RPOL 0x01
16269 #define _PRG3CON1_FPOL 0x02
16270 #define _PRG3CON1_RG3FPOL 0x02
16271 #define _PRG3CON1_RDY 0x04
16272 #define _PRG3CON1_RG3RDY 0x04
16274 //==============================================================================
16277 //==============================================================================
16280 extern __at(0x079F) __sfr PRG3CON2
;
16286 unsigned ISET0
: 1;
16287 unsigned ISET1
: 1;
16288 unsigned ISET2
: 1;
16289 unsigned ISET3
: 1;
16290 unsigned ISET4
: 1;
16298 unsigned RG3ISET0
: 1;
16299 unsigned RG3ISET1
: 1;
16300 unsigned RG3ISET2
: 1;
16301 unsigned RG3ISET3
: 1;
16302 unsigned RG3ISET4
: 1;
16310 unsigned RG3ISET
: 5;
16319 } __PRG3CON2bits_t
;
16321 extern __at(0x079F) volatile __PRG3CON2bits_t PRG3CON2bits
;
16323 #define _PRG3CON2_ISET0 0x01
16324 #define _PRG3CON2_RG3ISET0 0x01
16325 #define _PRG3CON2_ISET1 0x02
16326 #define _PRG3CON2_RG3ISET1 0x02
16327 #define _PRG3CON2_ISET2 0x04
16328 #define _PRG3CON2_RG3ISET2 0x04
16329 #define _PRG3CON2_ISET3 0x08
16330 #define _PRG3CON2_RG3ISET3 0x08
16331 #define _PRG3CON2_ISET4 0x10
16332 #define _PRG3CON2_RG3ISET4 0x10
16334 //==============================================================================
16337 //==============================================================================
16340 extern __at(0x080D) __sfr COG3PHR
;
16358 unsigned G3PHR0
: 1;
16359 unsigned G3PHR1
: 1;
16360 unsigned G3PHR2
: 1;
16361 unsigned G3PHR3
: 1;
16362 unsigned G3PHR4
: 1;
16363 unsigned G3PHR5
: 1;
16376 unsigned G3PHR
: 6;
16381 extern __at(0x080D) volatile __COG3PHRbits_t COG3PHRbits
;
16383 #define _COG3PHR_PHR0 0x01
16384 #define _COG3PHR_G3PHR0 0x01
16385 #define _COG3PHR_PHR1 0x02
16386 #define _COG3PHR_G3PHR1 0x02
16387 #define _COG3PHR_PHR2 0x04
16388 #define _COG3PHR_G3PHR2 0x04
16389 #define _COG3PHR_PHR3 0x08
16390 #define _COG3PHR_G3PHR3 0x08
16391 #define _COG3PHR_PHR4 0x10
16392 #define _COG3PHR_G3PHR4 0x10
16393 #define _COG3PHR_PHR5 0x20
16394 #define _COG3PHR_G3PHR5 0x20
16396 //==============================================================================
16399 //==============================================================================
16402 extern __at(0x080E) __sfr COG3PHF
;
16420 unsigned G3PHF0
: 1;
16421 unsigned G3PHF1
: 1;
16422 unsigned G3PHF2
: 1;
16423 unsigned G3PHF3
: 1;
16424 unsigned G3PHF4
: 1;
16425 unsigned G3PHF5
: 1;
16432 unsigned G3PHF
: 6;
16443 extern __at(0x080E) volatile __COG3PHFbits_t COG3PHFbits
;
16445 #define _COG3PHF_PHF0 0x01
16446 #define _COG3PHF_G3PHF0 0x01
16447 #define _COG3PHF_PHF1 0x02
16448 #define _COG3PHF_G3PHF1 0x02
16449 #define _COG3PHF_PHF2 0x04
16450 #define _COG3PHF_G3PHF2 0x04
16451 #define _COG3PHF_PHF3 0x08
16452 #define _COG3PHF_G3PHF3 0x08
16453 #define _COG3PHF_PHF4 0x10
16454 #define _COG3PHF_G3PHF4 0x10
16455 #define _COG3PHF_PHF5 0x20
16456 #define _COG3PHF_G3PHF5 0x20
16458 //==============================================================================
16461 //==============================================================================
16464 extern __at(0x080F) __sfr COG3BLKR
;
16470 unsigned BLKR0
: 1;
16471 unsigned BLKR1
: 1;
16472 unsigned BLKR2
: 1;
16473 unsigned BLKR3
: 1;
16474 unsigned BLKR4
: 1;
16475 unsigned BLKR5
: 1;
16482 unsigned G3BLKR0
: 1;
16483 unsigned G3BLKR1
: 1;
16484 unsigned G3BLKR2
: 1;
16485 unsigned G3BLKR3
: 1;
16486 unsigned G3BLKR4
: 1;
16487 unsigned G3BLKR5
: 1;
16500 unsigned G3BLKR
: 6;
16503 } __COG3BLKRbits_t
;
16505 extern __at(0x080F) volatile __COG3BLKRbits_t COG3BLKRbits
;
16507 #define _COG3BLKR_BLKR0 0x01
16508 #define _COG3BLKR_G3BLKR0 0x01
16509 #define _COG3BLKR_BLKR1 0x02
16510 #define _COG3BLKR_G3BLKR1 0x02
16511 #define _COG3BLKR_BLKR2 0x04
16512 #define _COG3BLKR_G3BLKR2 0x04
16513 #define _COG3BLKR_BLKR3 0x08
16514 #define _COG3BLKR_G3BLKR3 0x08
16515 #define _COG3BLKR_BLKR4 0x10
16516 #define _COG3BLKR_G3BLKR4 0x10
16517 #define _COG3BLKR_BLKR5 0x20
16518 #define _COG3BLKR_G3BLKR5 0x20
16520 //==============================================================================
16523 //==============================================================================
16526 extern __at(0x0810) __sfr COG3BLKF
;
16532 unsigned BLKF0
: 1;
16533 unsigned BLKF1
: 1;
16534 unsigned BLKF2
: 1;
16535 unsigned BLKF3
: 1;
16536 unsigned BLKF4
: 1;
16537 unsigned BLKF5
: 1;
16544 unsigned G3BLKF0
: 1;
16545 unsigned G3BLKF1
: 1;
16546 unsigned G3BLKF2
: 1;
16547 unsigned G3BLKF3
: 1;
16548 unsigned G3BLKF4
: 1;
16549 unsigned G3BLKF5
: 1;
16556 unsigned G3BLKF
: 6;
16565 } __COG3BLKFbits_t
;
16567 extern __at(0x0810) volatile __COG3BLKFbits_t COG3BLKFbits
;
16569 #define _COG3BLKF_BLKF0 0x01
16570 #define _COG3BLKF_G3BLKF0 0x01
16571 #define _COG3BLKF_BLKF1 0x02
16572 #define _COG3BLKF_G3BLKF1 0x02
16573 #define _COG3BLKF_BLKF2 0x04
16574 #define _COG3BLKF_G3BLKF2 0x04
16575 #define _COG3BLKF_BLKF3 0x08
16576 #define _COG3BLKF_G3BLKF3 0x08
16577 #define _COG3BLKF_BLKF4 0x10
16578 #define _COG3BLKF_G3BLKF4 0x10
16579 #define _COG3BLKF_BLKF5 0x20
16580 #define _COG3BLKF_G3BLKF5 0x20
16582 //==============================================================================
16585 //==============================================================================
16588 extern __at(0x0811) __sfr COG3DBR
;
16606 unsigned G3DBR0
: 1;
16607 unsigned G3DBR1
: 1;
16608 unsigned G3DBR2
: 1;
16609 unsigned G3DBR3
: 1;
16610 unsigned G3DBR4
: 1;
16611 unsigned G3DBR5
: 1;
16618 unsigned G3DBR
: 6;
16629 extern __at(0x0811) volatile __COG3DBRbits_t COG3DBRbits
;
16631 #define _COG3DBR_DBR0 0x01
16632 #define _COG3DBR_G3DBR0 0x01
16633 #define _COG3DBR_DBR1 0x02
16634 #define _COG3DBR_G3DBR1 0x02
16635 #define _COG3DBR_DBR2 0x04
16636 #define _COG3DBR_G3DBR2 0x04
16637 #define _COG3DBR_DBR3 0x08
16638 #define _COG3DBR_G3DBR3 0x08
16639 #define _COG3DBR_DBR4 0x10
16640 #define _COG3DBR_G3DBR4 0x10
16641 #define _COG3DBR_DBR5 0x20
16642 #define _COG3DBR_G3DBR5 0x20
16644 //==============================================================================
16647 //==============================================================================
16650 extern __at(0x0812) __sfr COG3DBF
;
16668 unsigned G3DBF0
: 1;
16669 unsigned G3DBF1
: 1;
16670 unsigned G3DBF2
: 1;
16671 unsigned G3DBF3
: 1;
16672 unsigned G3DBF4
: 1;
16673 unsigned G3DBF5
: 1;
16686 unsigned G3DBF
: 6;
16691 extern __at(0x0812) volatile __COG3DBFbits_t COG3DBFbits
;
16693 #define _COG3DBF_DBF0 0x01
16694 #define _COG3DBF_G3DBF0 0x01
16695 #define _COG3DBF_DBF1 0x02
16696 #define _COG3DBF_G3DBF1 0x02
16697 #define _COG3DBF_DBF2 0x04
16698 #define _COG3DBF_G3DBF2 0x04
16699 #define _COG3DBF_DBF3 0x08
16700 #define _COG3DBF_G3DBF3 0x08
16701 #define _COG3DBF_DBF4 0x10
16702 #define _COG3DBF_G3DBF4 0x10
16703 #define _COG3DBF_DBF5 0x20
16704 #define _COG3DBF_G3DBF5 0x20
16706 //==============================================================================
16709 //==============================================================================
16712 extern __at(0x0813) __sfr COG3CON0
;
16730 unsigned G3MD0
: 1;
16731 unsigned G3MD1
: 1;
16732 unsigned G3MD2
: 1;
16733 unsigned G3CS0
: 1;
16734 unsigned G3CS1
: 1;
16765 } __COG3CON0bits_t
;
16767 extern __at(0x0813) volatile __COG3CON0bits_t COG3CON0bits
;
16769 #define _COG3CON0_MD0 0x01
16770 #define _COG3CON0_G3MD0 0x01
16771 #define _COG3CON0_MD1 0x02
16772 #define _COG3CON0_G3MD1 0x02
16773 #define _COG3CON0_MD2 0x04
16774 #define _COG3CON0_G3MD2 0x04
16775 #define _COG3CON0_CS0 0x08
16776 #define _COG3CON0_G3CS0 0x08
16777 #define _COG3CON0_CS1 0x10
16778 #define _COG3CON0_G3CS1 0x10
16779 #define _COG3CON0_LD 0x40
16780 #define _COG3CON0_G3LD 0x40
16781 #define _COG3CON0_EN 0x80
16782 #define _COG3CON0_G3EN 0x80
16784 //==============================================================================
16787 //==============================================================================
16790 extern __at(0x0814) __sfr COG3CON1
;
16808 unsigned G3POLA
: 1;
16809 unsigned G3POLB
: 1;
16810 unsigned G3POLC
: 1;
16811 unsigned G3POLD
: 1;
16814 unsigned G3FDBS
: 1;
16815 unsigned G3RDBS
: 1;
16817 } __COG3CON1bits_t
;
16819 extern __at(0x0814) volatile __COG3CON1bits_t COG3CON1bits
;
16821 #define _COG3CON1_POLA 0x01
16822 #define _COG3CON1_G3POLA 0x01
16823 #define _COG3CON1_POLB 0x02
16824 #define _COG3CON1_G3POLB 0x02
16825 #define _COG3CON1_POLC 0x04
16826 #define _COG3CON1_G3POLC 0x04
16827 #define _COG3CON1_POLD 0x08
16828 #define _COG3CON1_G3POLD 0x08
16829 #define _COG3CON1_FDBS 0x40
16830 #define _COG3CON1_G3FDBS 0x40
16831 #define _COG3CON1_RDBS 0x80
16832 #define _COG3CON1_G3RDBS 0x80
16834 //==============================================================================
16837 //==============================================================================
16840 extern __at(0x0815) __sfr COG3RIS0
;
16858 unsigned G3RIS0
: 1;
16859 unsigned G3RIS1
: 1;
16860 unsigned G3RIS2
: 1;
16861 unsigned G3RIS3
: 1;
16862 unsigned G3RIS4
: 1;
16863 unsigned G3RIS5
: 1;
16864 unsigned G3RIS6
: 1;
16865 unsigned G3RIS7
: 1;
16867 } __COG3RIS0bits_t
;
16869 extern __at(0x0815) volatile __COG3RIS0bits_t COG3RIS0bits
;
16871 #define _COG3RIS0_RIS0 0x01
16872 #define _COG3RIS0_G3RIS0 0x01
16873 #define _COG3RIS0_RIS1 0x02
16874 #define _COG3RIS0_G3RIS1 0x02
16875 #define _COG3RIS0_RIS2 0x04
16876 #define _COG3RIS0_G3RIS2 0x04
16877 #define _COG3RIS0_RIS3 0x08
16878 #define _COG3RIS0_G3RIS3 0x08
16879 #define _COG3RIS0_RIS4 0x10
16880 #define _COG3RIS0_G3RIS4 0x10
16881 #define _COG3RIS0_RIS5 0x20
16882 #define _COG3RIS0_G3RIS5 0x20
16883 #define _COG3RIS0_RIS6 0x40
16884 #define _COG3RIS0_G3RIS6 0x40
16885 #define _COG3RIS0_RIS7 0x80
16886 #define _COG3RIS0_G3RIS7 0x80
16888 //==============================================================================
16891 //==============================================================================
16894 extern __at(0x0816) __sfr COG3RIS1
;
16903 unsigned RIS11
: 1;
16904 unsigned RIS12
: 1;
16905 unsigned RIS13
: 1;
16906 unsigned RIS14
: 1;
16907 unsigned RIS15
: 1;
16913 unsigned G3RIS9
: 1;
16915 unsigned G3RIS11
: 1;
16916 unsigned G3RIS12
: 1;
16917 unsigned G3RIS13
: 1;
16918 unsigned G3RIS14
: 1;
16919 unsigned G3RIS15
: 1;
16921 } __COG3RIS1bits_t
;
16923 extern __at(0x0816) volatile __COG3RIS1bits_t COG3RIS1bits
;
16925 #define _COG3RIS1_RIS9 0x02
16926 #define _COG3RIS1_G3RIS9 0x02
16927 #define _COG3RIS1_RIS11 0x08
16928 #define _COG3RIS1_G3RIS11 0x08
16929 #define _COG3RIS1_RIS12 0x10
16930 #define _COG3RIS1_G3RIS12 0x10
16931 #define _COG3RIS1_RIS13 0x20
16932 #define _COG3RIS1_G3RIS13 0x20
16933 #define _COG3RIS1_RIS14 0x40
16934 #define _COG3RIS1_G3RIS14 0x40
16935 #define _COG3RIS1_RIS15 0x80
16936 #define _COG3RIS1_G3RIS15 0x80
16938 //==============================================================================
16941 //==============================================================================
16944 extern __at(0x0817) __sfr COG3RSIM0
;
16950 unsigned RSIM0
: 1;
16951 unsigned RSIM1
: 1;
16952 unsigned RSIM2
: 1;
16953 unsigned RSIM3
: 1;
16954 unsigned RSIM4
: 1;
16955 unsigned RSIM5
: 1;
16956 unsigned RSIM6
: 1;
16957 unsigned RSIM7
: 1;
16962 unsigned G3RSIM0
: 1;
16963 unsigned G3RSIM1
: 1;
16964 unsigned G3RSIM2
: 1;
16965 unsigned G3RSIM3
: 1;
16966 unsigned G3RSIM4
: 1;
16967 unsigned G3RSIM5
: 1;
16968 unsigned G3RSIM6
: 1;
16969 unsigned G3RSIM7
: 1;
16971 } __COG3RSIM0bits_t
;
16973 extern __at(0x0817) volatile __COG3RSIM0bits_t COG3RSIM0bits
;
16975 #define _COG3RSIM0_RSIM0 0x01
16976 #define _COG3RSIM0_G3RSIM0 0x01
16977 #define _COG3RSIM0_RSIM1 0x02
16978 #define _COG3RSIM0_G3RSIM1 0x02
16979 #define _COG3RSIM0_RSIM2 0x04
16980 #define _COG3RSIM0_G3RSIM2 0x04
16981 #define _COG3RSIM0_RSIM3 0x08
16982 #define _COG3RSIM0_G3RSIM3 0x08
16983 #define _COG3RSIM0_RSIM4 0x10
16984 #define _COG3RSIM0_G3RSIM4 0x10
16985 #define _COG3RSIM0_RSIM5 0x20
16986 #define _COG3RSIM0_G3RSIM5 0x20
16987 #define _COG3RSIM0_RSIM6 0x40
16988 #define _COG3RSIM0_G3RSIM6 0x40
16989 #define _COG3RSIM0_RSIM7 0x80
16990 #define _COG3RSIM0_G3RSIM7 0x80
16992 //==============================================================================
16995 //==============================================================================
16998 extern __at(0x0818) __sfr COG3RSIM1
;
17005 unsigned RSIM9
: 1;
17007 unsigned RSIM11
: 1;
17008 unsigned RSIM12
: 1;
17009 unsigned RSIM13
: 1;
17010 unsigned RSIM14
: 1;
17011 unsigned RSIM15
: 1;
17017 unsigned G3RSIM9
: 1;
17019 unsigned G3RSIM11
: 1;
17020 unsigned G3RSIM12
: 1;
17021 unsigned G3RSIM13
: 1;
17022 unsigned G3RSIM14
: 1;
17023 unsigned G3RSIM15
: 1;
17025 } __COG3RSIM1bits_t
;
17027 extern __at(0x0818) volatile __COG3RSIM1bits_t COG3RSIM1bits
;
17029 #define _COG3RSIM1_RSIM9 0x02
17030 #define _COG3RSIM1_G3RSIM9 0x02
17031 #define _COG3RSIM1_RSIM11 0x08
17032 #define _COG3RSIM1_G3RSIM11 0x08
17033 #define _COG3RSIM1_RSIM12 0x10
17034 #define _COG3RSIM1_G3RSIM12 0x10
17035 #define _COG3RSIM1_RSIM13 0x20
17036 #define _COG3RSIM1_G3RSIM13 0x20
17037 #define _COG3RSIM1_RSIM14 0x40
17038 #define _COG3RSIM1_G3RSIM14 0x40
17039 #define _COG3RSIM1_RSIM15 0x80
17040 #define _COG3RSIM1_G3RSIM15 0x80
17042 //==============================================================================
17045 //==============================================================================
17048 extern __at(0x0819) __sfr COG3FIS0
;
17066 unsigned G3FIS0
: 1;
17067 unsigned G3FIS1
: 1;
17068 unsigned G3FIS2
: 1;
17069 unsigned G3FIS3
: 1;
17070 unsigned G3FIS4
: 1;
17071 unsigned G3FIS5
: 1;
17072 unsigned G3FIS6
: 1;
17073 unsigned G3FIS7
: 1;
17075 } __COG3FIS0bits_t
;
17077 extern __at(0x0819) volatile __COG3FIS0bits_t COG3FIS0bits
;
17079 #define _COG3FIS0_FIS0 0x01
17080 #define _COG3FIS0_G3FIS0 0x01
17081 #define _COG3FIS0_FIS1 0x02
17082 #define _COG3FIS0_G3FIS1 0x02
17083 #define _COG3FIS0_FIS2 0x04
17084 #define _COG3FIS0_G3FIS2 0x04
17085 #define _COG3FIS0_FIS3 0x08
17086 #define _COG3FIS0_G3FIS3 0x08
17087 #define _COG3FIS0_FIS4 0x10
17088 #define _COG3FIS0_G3FIS4 0x10
17089 #define _COG3FIS0_FIS5 0x20
17090 #define _COG3FIS0_G3FIS5 0x20
17091 #define _COG3FIS0_FIS6 0x40
17092 #define _COG3FIS0_G3FIS6 0x40
17093 #define _COG3FIS0_FIS7 0x80
17094 #define _COG3FIS0_G3FIS7 0x80
17096 //==============================================================================
17099 //==============================================================================
17102 extern __at(0x081A) __sfr COG3FIS1
;
17111 unsigned FIS11
: 1;
17112 unsigned FIS12
: 1;
17113 unsigned FIS13
: 1;
17114 unsigned FIS14
: 1;
17115 unsigned FIS15
: 1;
17121 unsigned G3FIS9
: 1;
17123 unsigned G3FIS11
: 1;
17124 unsigned G3FIS12
: 1;
17125 unsigned G3FIS13
: 1;
17126 unsigned G3FIS14
: 1;
17127 unsigned G3FIS15
: 1;
17129 } __COG3FIS1bits_t
;
17131 extern __at(0x081A) volatile __COG3FIS1bits_t COG3FIS1bits
;
17133 #define _COG3FIS1_FIS9 0x02
17134 #define _COG3FIS1_G3FIS9 0x02
17135 #define _COG3FIS1_FIS11 0x08
17136 #define _COG3FIS1_G3FIS11 0x08
17137 #define _COG3FIS1_FIS12 0x10
17138 #define _COG3FIS1_G3FIS12 0x10
17139 #define _COG3FIS1_FIS13 0x20
17140 #define _COG3FIS1_G3FIS13 0x20
17141 #define _COG3FIS1_FIS14 0x40
17142 #define _COG3FIS1_G3FIS14 0x40
17143 #define _COG3FIS1_FIS15 0x80
17144 #define _COG3FIS1_G3FIS15 0x80
17146 //==============================================================================
17149 //==============================================================================
17152 extern __at(0x081B) __sfr COG3FSIM0
;
17158 unsigned FSIM0
: 1;
17159 unsigned FSIM1
: 1;
17160 unsigned FSIM2
: 1;
17161 unsigned FSIM3
: 1;
17162 unsigned FSIM4
: 1;
17163 unsigned FSIM5
: 1;
17164 unsigned FSIM6
: 1;
17165 unsigned FSIM7
: 1;
17170 unsigned G3FSIM0
: 1;
17171 unsigned G3FSIM1
: 1;
17172 unsigned G3FSIM2
: 1;
17173 unsigned G3FSIM3
: 1;
17174 unsigned G3FSIM4
: 1;
17175 unsigned G3FSIM5
: 1;
17176 unsigned G3FSIM6
: 1;
17177 unsigned G3FSIM7
: 1;
17179 } __COG3FSIM0bits_t
;
17181 extern __at(0x081B) volatile __COG3FSIM0bits_t COG3FSIM0bits
;
17183 #define _COG3FSIM0_FSIM0 0x01
17184 #define _COG3FSIM0_G3FSIM0 0x01
17185 #define _COG3FSIM0_FSIM1 0x02
17186 #define _COG3FSIM0_G3FSIM1 0x02
17187 #define _COG3FSIM0_FSIM2 0x04
17188 #define _COG3FSIM0_G3FSIM2 0x04
17189 #define _COG3FSIM0_FSIM3 0x08
17190 #define _COG3FSIM0_G3FSIM3 0x08
17191 #define _COG3FSIM0_FSIM4 0x10
17192 #define _COG3FSIM0_G3FSIM4 0x10
17193 #define _COG3FSIM0_FSIM5 0x20
17194 #define _COG3FSIM0_G3FSIM5 0x20
17195 #define _COG3FSIM0_FSIM6 0x40
17196 #define _COG3FSIM0_G3FSIM6 0x40
17197 #define _COG3FSIM0_FSIM7 0x80
17198 #define _COG3FSIM0_G3FSIM7 0x80
17200 //==============================================================================
17203 //==============================================================================
17206 extern __at(0x081C) __sfr COG3FSIM1
;
17213 unsigned FSIM9
: 1;
17215 unsigned FSIM11
: 1;
17216 unsigned FSIM12
: 1;
17217 unsigned FSIM13
: 1;
17218 unsigned FSIM14
: 1;
17219 unsigned FSIM15
: 1;
17225 unsigned G3FSIM9
: 1;
17227 unsigned G3FSIM11
: 1;
17228 unsigned G3FSIM12
: 1;
17229 unsigned G3FSIM13
: 1;
17230 unsigned G3FSIM14
: 1;
17231 unsigned G3FSIM15
: 1;
17233 } __COG3FSIM1bits_t
;
17235 extern __at(0x081C) volatile __COG3FSIM1bits_t COG3FSIM1bits
;
17237 #define _COG3FSIM1_FSIM9 0x02
17238 #define _COG3FSIM1_G3FSIM9 0x02
17239 #define _COG3FSIM1_FSIM11 0x08
17240 #define _COG3FSIM1_G3FSIM11 0x08
17241 #define _COG3FSIM1_FSIM12 0x10
17242 #define _COG3FSIM1_G3FSIM12 0x10
17243 #define _COG3FSIM1_FSIM13 0x20
17244 #define _COG3FSIM1_G3FSIM13 0x20
17245 #define _COG3FSIM1_FSIM14 0x40
17246 #define _COG3FSIM1_G3FSIM14 0x40
17247 #define _COG3FSIM1_FSIM15 0x80
17248 #define _COG3FSIM1_G3FSIM15 0x80
17250 //==============================================================================
17253 //==============================================================================
17256 extern __at(0x081D) __sfr COG3ASD0
;
17264 unsigned ASDAC0
: 1;
17265 unsigned ASDAC1
: 1;
17266 unsigned ASDBD0
: 1;
17267 unsigned ASDBD1
: 1;
17268 unsigned ASREN
: 1;
17276 unsigned G3ASDAC0
: 1;
17277 unsigned G3ASDAC1
: 1;
17278 unsigned G3ASDBD0
: 1;
17279 unsigned G3ASDBD1
: 1;
17280 unsigned ARSEN
: 1;
17281 unsigned G3ASE
: 1;
17292 unsigned G3ARSEN
: 1;
17304 unsigned G3ASREN
: 1;
17311 unsigned G3ASDAC
: 2;
17318 unsigned ASDAC
: 2;
17325 unsigned G3ASDBD
: 2;
17332 unsigned ASDBD
: 2;
17335 } __COG3ASD0bits_t
;
17337 extern __at(0x081D) volatile __COG3ASD0bits_t COG3ASD0bits
;
17339 #define _COG3ASD0_ASDAC0 0x04
17340 #define _COG3ASD0_G3ASDAC0 0x04
17341 #define _COG3ASD0_ASDAC1 0x08
17342 #define _COG3ASD0_G3ASDAC1 0x08
17343 #define _COG3ASD0_ASDBD0 0x10
17344 #define _COG3ASD0_G3ASDBD0 0x10
17345 #define _COG3ASD0_ASDBD1 0x20
17346 #define _COG3ASD0_G3ASDBD1 0x20
17347 #define _COG3ASD0_ASREN 0x40
17348 #define _COG3ASD0_ARSEN 0x40
17349 #define _COG3ASD0_G3ARSEN 0x40
17350 #define _COG3ASD0_G3ASREN 0x40
17351 #define _COG3ASD0_ASE 0x80
17352 #define _COG3ASD0_G3ASE 0x80
17354 //==============================================================================
17357 //==============================================================================
17360 extern __at(0x081E) __sfr COG3ASD1
;
17378 unsigned G3AS0E
: 1;
17379 unsigned G3AS1E
: 1;
17380 unsigned G3AS2E
: 1;
17381 unsigned G3AS3E
: 1;
17382 unsigned G3AS4E
: 1;
17383 unsigned G3AS5E
: 1;
17384 unsigned G3AS6E
: 1;
17385 unsigned G3AS7E
: 1;
17387 } __COG3ASD1bits_t
;
17389 extern __at(0x081E) volatile __COG3ASD1bits_t COG3ASD1bits
;
17391 #define _COG3ASD1_AS0E 0x01
17392 #define _COG3ASD1_G3AS0E 0x01
17393 #define _COG3ASD1_AS1E 0x02
17394 #define _COG3ASD1_G3AS1E 0x02
17395 #define _COG3ASD1_AS2E 0x04
17396 #define _COG3ASD1_G3AS2E 0x04
17397 #define _COG3ASD1_AS3E 0x08
17398 #define _COG3ASD1_G3AS3E 0x08
17399 #define _COG3ASD1_AS4E 0x10
17400 #define _COG3ASD1_G3AS4E 0x10
17401 #define _COG3ASD1_AS5E 0x20
17402 #define _COG3ASD1_G3AS5E 0x20
17403 #define _COG3ASD1_AS6E 0x40
17404 #define _COG3ASD1_G3AS6E 0x40
17405 #define _COG3ASD1_AS7E 0x80
17406 #define _COG3ASD1_G3AS7E 0x80
17408 //==============================================================================
17411 //==============================================================================
17414 extern __at(0x081F) __sfr COG3STR
;
17424 unsigned SDATA
: 1;
17425 unsigned SDATB
: 1;
17426 unsigned SDATC
: 1;
17427 unsigned SDATD
: 1;
17432 unsigned G3STRA
: 1;
17433 unsigned G3STRB
: 1;
17434 unsigned G3STRC
: 1;
17435 unsigned G3STRD
: 1;
17436 unsigned G3SDATA
: 1;
17437 unsigned G3SDATB
: 1;
17438 unsigned G3SDATC
: 1;
17439 unsigned G3SDATD
: 1;
17443 extern __at(0x081F) volatile __COG3STRbits_t COG3STRbits
;
17445 #define _COG3STR_STRA 0x01
17446 #define _COG3STR_G3STRA 0x01
17447 #define _COG3STR_STRB 0x02
17448 #define _COG3STR_G3STRB 0x02
17449 #define _COG3STR_STRC 0x04
17450 #define _COG3STR_G3STRC 0x04
17451 #define _COG3STR_STRD 0x08
17452 #define _COG3STR_G3STRD 0x08
17453 #define _COG3STR_SDATA 0x10
17454 #define _COG3STR_G3SDATA 0x10
17455 #define _COG3STR_SDATB 0x20
17456 #define _COG3STR_G3SDATB 0x20
17457 #define _COG3STR_SDATC 0x40
17458 #define _COG3STR_G3SDATC 0x40
17459 #define _COG3STR_SDATD 0x80
17460 #define _COG3STR_G3SDATD 0x80
17462 //==============================================================================
17465 //==============================================================================
17468 extern __at(0x088D) __sfr COG4PHR
;
17486 unsigned G4PHR0
: 1;
17487 unsigned G4PHR1
: 1;
17488 unsigned G4PHR2
: 1;
17489 unsigned G4PHR3
: 1;
17490 unsigned G4PHR4
: 1;
17491 unsigned G4PHR5
: 1;
17498 unsigned G4PHR
: 6;
17509 extern __at(0x088D) volatile __COG4PHRbits_t COG4PHRbits
;
17511 #define _COG4PHR_PHR0 0x01
17512 #define _COG4PHR_G4PHR0 0x01
17513 #define _COG4PHR_PHR1 0x02
17514 #define _COG4PHR_G4PHR1 0x02
17515 #define _COG4PHR_PHR2 0x04
17516 #define _COG4PHR_G4PHR2 0x04
17517 #define _COG4PHR_PHR3 0x08
17518 #define _COG4PHR_G4PHR3 0x08
17519 #define _COG4PHR_PHR4 0x10
17520 #define _COG4PHR_G4PHR4 0x10
17521 #define _COG4PHR_PHR5 0x20
17522 #define _COG4PHR_G4PHR5 0x20
17524 //==============================================================================
17527 //==============================================================================
17530 extern __at(0x088E) __sfr COG4PHF
;
17548 unsigned G4PHF0
: 1;
17549 unsigned G4PHF1
: 1;
17550 unsigned G4PHF2
: 1;
17551 unsigned G4PHF3
: 1;
17552 unsigned G4PHF4
: 1;
17553 unsigned G4PHF5
: 1;
17560 unsigned G4PHF
: 6;
17571 extern __at(0x088E) volatile __COG4PHFbits_t COG4PHFbits
;
17573 #define _COG4PHF_PHF0 0x01
17574 #define _COG4PHF_G4PHF0 0x01
17575 #define _COG4PHF_PHF1 0x02
17576 #define _COG4PHF_G4PHF1 0x02
17577 #define _COG4PHF_PHF2 0x04
17578 #define _COG4PHF_G4PHF2 0x04
17579 #define _COG4PHF_PHF3 0x08
17580 #define _COG4PHF_G4PHF3 0x08
17581 #define _COG4PHF_PHF4 0x10
17582 #define _COG4PHF_G4PHF4 0x10
17583 #define _COG4PHF_PHF5 0x20
17584 #define _COG4PHF_G4PHF5 0x20
17586 //==============================================================================
17589 //==============================================================================
17592 extern __at(0x088F) __sfr COG4BLKR
;
17598 unsigned BLKR0
: 1;
17599 unsigned BLKR1
: 1;
17600 unsigned BLKR2
: 1;
17601 unsigned BLKR3
: 1;
17602 unsigned BLKR4
: 1;
17603 unsigned BLKR5
: 1;
17610 unsigned G4BLKR0
: 1;
17611 unsigned G4BLKR1
: 1;
17612 unsigned G4BLKR2
: 1;
17613 unsigned G4BLKR3
: 1;
17614 unsigned G4BLKR4
: 1;
17615 unsigned G4BLKR5
: 1;
17628 unsigned G4BLKR
: 6;
17631 } __COG4BLKRbits_t
;
17633 extern __at(0x088F) volatile __COG4BLKRbits_t COG4BLKRbits
;
17635 #define _COG4BLKR_BLKR0 0x01
17636 #define _COG4BLKR_G4BLKR0 0x01
17637 #define _COG4BLKR_BLKR1 0x02
17638 #define _COG4BLKR_G4BLKR1 0x02
17639 #define _COG4BLKR_BLKR2 0x04
17640 #define _COG4BLKR_G4BLKR2 0x04
17641 #define _COG4BLKR_BLKR3 0x08
17642 #define _COG4BLKR_G4BLKR3 0x08
17643 #define _COG4BLKR_BLKR4 0x10
17644 #define _COG4BLKR_G4BLKR4 0x10
17645 #define _COG4BLKR_BLKR5 0x20
17646 #define _COG4BLKR_G4BLKR5 0x20
17648 //==============================================================================
17651 //==============================================================================
17654 extern __at(0x0890) __sfr COG4BLKF
;
17660 unsigned BLKF0
: 1;
17661 unsigned BLKF1
: 1;
17662 unsigned BLKF2
: 1;
17663 unsigned BLKF3
: 1;
17664 unsigned BLKF4
: 1;
17665 unsigned BLKF5
: 1;
17672 unsigned G4BLKF0
: 1;
17673 unsigned G4BLKF1
: 1;
17674 unsigned G4BLKF2
: 1;
17675 unsigned G4BLKF3
: 1;
17676 unsigned G4BLKF4
: 1;
17677 unsigned G4BLKF5
: 1;
17684 unsigned G4BLKF
: 6;
17693 } __COG4BLKFbits_t
;
17695 extern __at(0x0890) volatile __COG4BLKFbits_t COG4BLKFbits
;
17697 #define _COG4BLKF_BLKF0 0x01
17698 #define _COG4BLKF_G4BLKF0 0x01
17699 #define _COG4BLKF_BLKF1 0x02
17700 #define _COG4BLKF_G4BLKF1 0x02
17701 #define _COG4BLKF_BLKF2 0x04
17702 #define _COG4BLKF_G4BLKF2 0x04
17703 #define _COG4BLKF_BLKF3 0x08
17704 #define _COG4BLKF_G4BLKF3 0x08
17705 #define _COG4BLKF_BLKF4 0x10
17706 #define _COG4BLKF_G4BLKF4 0x10
17707 #define _COG4BLKF_BLKF5 0x20
17708 #define _COG4BLKF_G4BLKF5 0x20
17710 //==============================================================================
17713 //==============================================================================
17716 extern __at(0x0891) __sfr COG4DBR
;
17734 unsigned G4DBR0
: 1;
17735 unsigned G4DBR1
: 1;
17736 unsigned G4DBR2
: 1;
17737 unsigned G4DBR3
: 1;
17738 unsigned G4DBR4
: 1;
17739 unsigned G4DBR5
: 1;
17746 unsigned G4DBR
: 6;
17757 extern __at(0x0891) volatile __COG4DBRbits_t COG4DBRbits
;
17759 #define _COG4DBR_DBR0 0x01
17760 #define _COG4DBR_G4DBR0 0x01
17761 #define _COG4DBR_DBR1 0x02
17762 #define _COG4DBR_G4DBR1 0x02
17763 #define _COG4DBR_DBR2 0x04
17764 #define _COG4DBR_G4DBR2 0x04
17765 #define _COG4DBR_DBR3 0x08
17766 #define _COG4DBR_G4DBR3 0x08
17767 #define _COG4DBR_DBR4 0x10
17768 #define _COG4DBR_G4DBR4 0x10
17769 #define _COG4DBR_DBR5 0x20
17770 #define _COG4DBR_G4DBR5 0x20
17772 //==============================================================================
17775 //==============================================================================
17778 extern __at(0x0892) __sfr COG4DBF
;
17796 unsigned G4DBF0
: 1;
17797 unsigned G4DBF1
: 1;
17798 unsigned G4DBF2
: 1;
17799 unsigned G4DBF3
: 1;
17800 unsigned G4DBF4
: 1;
17801 unsigned G4DBF5
: 1;
17814 unsigned G4DBF
: 6;
17819 extern __at(0x0892) volatile __COG4DBFbits_t COG4DBFbits
;
17821 #define _COG4DBF_DBF0 0x01
17822 #define _COG4DBF_G4DBF0 0x01
17823 #define _COG4DBF_DBF1 0x02
17824 #define _COG4DBF_G4DBF1 0x02
17825 #define _COG4DBF_DBF2 0x04
17826 #define _COG4DBF_G4DBF2 0x04
17827 #define _COG4DBF_DBF3 0x08
17828 #define _COG4DBF_G4DBF3 0x08
17829 #define _COG4DBF_DBF4 0x10
17830 #define _COG4DBF_G4DBF4 0x10
17831 #define _COG4DBF_DBF5 0x20
17832 #define _COG4DBF_G4DBF5 0x20
17834 //==============================================================================
17837 //==============================================================================
17840 extern __at(0x0893) __sfr COG4CON0
;
17858 unsigned G4MD0
: 1;
17859 unsigned G4MD1
: 1;
17860 unsigned G4MD2
: 1;
17861 unsigned G4CS0
: 1;
17862 unsigned G4CS1
: 1;
17893 } __COG4CON0bits_t
;
17895 extern __at(0x0893) volatile __COG4CON0bits_t COG4CON0bits
;
17897 #define _COG4CON0_MD0 0x01
17898 #define _COG4CON0_G4MD0 0x01
17899 #define _COG4CON0_MD1 0x02
17900 #define _COG4CON0_G4MD1 0x02
17901 #define _COG4CON0_MD2 0x04
17902 #define _COG4CON0_G4MD2 0x04
17903 #define _COG4CON0_CS0 0x08
17904 #define _COG4CON0_G4CS0 0x08
17905 #define _COG4CON0_CS1 0x10
17906 #define _COG4CON0_G4CS1 0x10
17907 #define _COG4CON0_LD 0x40
17908 #define _COG4CON0_G4LD 0x40
17909 #define _COG4CON0_EN 0x80
17910 #define _COG4CON0_G4EN 0x80
17912 //==============================================================================
17915 //==============================================================================
17918 extern __at(0x0894) __sfr COG4CON1
;
17936 unsigned G4POLA
: 1;
17937 unsigned G4POLB
: 1;
17938 unsigned G4POLC
: 1;
17939 unsigned G4POLD
: 1;
17942 unsigned G4FDBS
: 1;
17943 unsigned G4RDBS
: 1;
17945 } __COG4CON1bits_t
;
17947 extern __at(0x0894) volatile __COG4CON1bits_t COG4CON1bits
;
17949 #define _COG4CON1_POLA 0x01
17950 #define _COG4CON1_G4POLA 0x01
17951 #define _COG4CON1_POLB 0x02
17952 #define _COG4CON1_G4POLB 0x02
17953 #define _COG4CON1_POLC 0x04
17954 #define _COG4CON1_G4POLC 0x04
17955 #define _COG4CON1_POLD 0x08
17956 #define _COG4CON1_G4POLD 0x08
17957 #define _COG4CON1_FDBS 0x40
17958 #define _COG4CON1_G4FDBS 0x40
17959 #define _COG4CON1_RDBS 0x80
17960 #define _COG4CON1_G4RDBS 0x80
17962 //==============================================================================
17965 //==============================================================================
17968 extern __at(0x0895) __sfr COG4RIS0
;
17986 unsigned G4RIS0
: 1;
17987 unsigned G4RIS1
: 1;
17988 unsigned G4RIS2
: 1;
17989 unsigned G4RIS3
: 1;
17990 unsigned G4RIS4
: 1;
17991 unsigned G4RIS5
: 1;
17992 unsigned G4RIS6
: 1;
17993 unsigned G4RIS7
: 1;
17995 } __COG4RIS0bits_t
;
17997 extern __at(0x0895) volatile __COG4RIS0bits_t COG4RIS0bits
;
17999 #define _COG4RIS0_RIS0 0x01
18000 #define _COG4RIS0_G4RIS0 0x01
18001 #define _COG4RIS0_RIS1 0x02
18002 #define _COG4RIS0_G4RIS1 0x02
18003 #define _COG4RIS0_RIS2 0x04
18004 #define _COG4RIS0_G4RIS2 0x04
18005 #define _COG4RIS0_RIS3 0x08
18006 #define _COG4RIS0_G4RIS3 0x08
18007 #define _COG4RIS0_RIS4 0x10
18008 #define _COG4RIS0_G4RIS4 0x10
18009 #define _COG4RIS0_RIS5 0x20
18010 #define _COG4RIS0_G4RIS5 0x20
18011 #define _COG4RIS0_RIS6 0x40
18012 #define _COG4RIS0_G4RIS6 0x40
18013 #define _COG4RIS0_RIS7 0x80
18014 #define _COG4RIS0_G4RIS7 0x80
18016 //==============================================================================
18019 //==============================================================================
18022 extern __at(0x0896) __sfr COG4RIS1
;
18030 unsigned RIS10
: 1;
18031 unsigned RIS11
: 1;
18032 unsigned RIS12
: 1;
18033 unsigned RIS13
: 1;
18034 unsigned RIS14
: 1;
18035 unsigned RIS15
: 1;
18040 unsigned G4RIS8
: 1;
18041 unsigned G4RIS9
: 1;
18042 unsigned G4RIS10
: 1;
18043 unsigned G4RIS11
: 1;
18044 unsigned G4RIS12
: 1;
18045 unsigned G4RIS13
: 1;
18046 unsigned G4RIS14
: 1;
18047 unsigned G4RIS15
: 1;
18049 } __COG4RIS1bits_t
;
18051 extern __at(0x0896) volatile __COG4RIS1bits_t COG4RIS1bits
;
18053 #define _COG4RIS1_RIS8 0x01
18054 #define _COG4RIS1_G4RIS8 0x01
18055 #define _COG4RIS1_RIS9 0x02
18056 #define _COG4RIS1_G4RIS9 0x02
18057 #define _COG4RIS1_RIS10 0x04
18058 #define _COG4RIS1_G4RIS10 0x04
18059 #define _COG4RIS1_RIS11 0x08
18060 #define _COG4RIS1_G4RIS11 0x08
18061 #define _COG4RIS1_RIS12 0x10
18062 #define _COG4RIS1_G4RIS12 0x10
18063 #define _COG4RIS1_RIS13 0x20
18064 #define _COG4RIS1_G4RIS13 0x20
18065 #define _COG4RIS1_RIS14 0x40
18066 #define _COG4RIS1_G4RIS14 0x40
18067 #define _COG4RIS1_RIS15 0x80
18068 #define _COG4RIS1_G4RIS15 0x80
18070 //==============================================================================
18073 //==============================================================================
18076 extern __at(0x0897) __sfr COG4RSIM0
;
18082 unsigned RSIM0
: 1;
18083 unsigned RSIM1
: 1;
18084 unsigned RSIM2
: 1;
18085 unsigned RSIM3
: 1;
18086 unsigned RSIM4
: 1;
18087 unsigned RSIM5
: 1;
18088 unsigned RSIM6
: 1;
18089 unsigned RSIM7
: 1;
18094 unsigned G4RSIM0
: 1;
18095 unsigned G4RSIM1
: 1;
18096 unsigned G4RSIM2
: 1;
18097 unsigned G4RSIM3
: 1;
18098 unsigned G4RSIM4
: 1;
18099 unsigned G4RSIM5
: 1;
18100 unsigned G4RSIM6
: 1;
18101 unsigned G4RSIM7
: 1;
18103 } __COG4RSIM0bits_t
;
18105 extern __at(0x0897) volatile __COG4RSIM0bits_t COG4RSIM0bits
;
18107 #define _COG4RSIM0_RSIM0 0x01
18108 #define _COG4RSIM0_G4RSIM0 0x01
18109 #define _COG4RSIM0_RSIM1 0x02
18110 #define _COG4RSIM0_G4RSIM1 0x02
18111 #define _COG4RSIM0_RSIM2 0x04
18112 #define _COG4RSIM0_G4RSIM2 0x04
18113 #define _COG4RSIM0_RSIM3 0x08
18114 #define _COG4RSIM0_G4RSIM3 0x08
18115 #define _COG4RSIM0_RSIM4 0x10
18116 #define _COG4RSIM0_G4RSIM4 0x10
18117 #define _COG4RSIM0_RSIM5 0x20
18118 #define _COG4RSIM0_G4RSIM5 0x20
18119 #define _COG4RSIM0_RSIM6 0x40
18120 #define _COG4RSIM0_G4RSIM6 0x40
18121 #define _COG4RSIM0_RSIM7 0x80
18122 #define _COG4RSIM0_G4RSIM7 0x80
18124 //==============================================================================
18127 //==============================================================================
18130 extern __at(0x0898) __sfr COG4RSIM1
;
18136 unsigned RSIM8
: 1;
18137 unsigned RSIM9
: 1;
18138 unsigned RSIM10
: 1;
18139 unsigned RSIM11
: 1;
18140 unsigned RSIM12
: 1;
18141 unsigned RSIM13
: 1;
18142 unsigned RSIM14
: 1;
18143 unsigned RSIM15
: 1;
18148 unsigned G4RSIM8
: 1;
18149 unsigned G4RSIM9
: 1;
18150 unsigned G4RSIM10
: 1;
18151 unsigned G4RSIM11
: 1;
18152 unsigned G4RSIM12
: 1;
18153 unsigned G4RSIM13
: 1;
18154 unsigned G4RSIM14
: 1;
18155 unsigned G4RSIM15
: 1;
18157 } __COG4RSIM1bits_t
;
18159 extern __at(0x0898) volatile __COG4RSIM1bits_t COG4RSIM1bits
;
18161 #define _COG4RSIM1_RSIM8 0x01
18162 #define _COG4RSIM1_G4RSIM8 0x01
18163 #define _COG4RSIM1_RSIM9 0x02
18164 #define _COG4RSIM1_G4RSIM9 0x02
18165 #define _COG4RSIM1_RSIM10 0x04
18166 #define _COG4RSIM1_G4RSIM10 0x04
18167 #define _COG4RSIM1_RSIM11 0x08
18168 #define _COG4RSIM1_G4RSIM11 0x08
18169 #define _COG4RSIM1_RSIM12 0x10
18170 #define _COG4RSIM1_G4RSIM12 0x10
18171 #define _COG4RSIM1_RSIM13 0x20
18172 #define _COG4RSIM1_G4RSIM13 0x20
18173 #define _COG4RSIM1_RSIM14 0x40
18174 #define _COG4RSIM1_G4RSIM14 0x40
18175 #define _COG4RSIM1_RSIM15 0x80
18176 #define _COG4RSIM1_G4RSIM15 0x80
18178 //==============================================================================
18181 //==============================================================================
18184 extern __at(0x0899) __sfr COG4FIS0
;
18202 unsigned G4FIS0
: 1;
18203 unsigned G4FIS1
: 1;
18204 unsigned G4FIS2
: 1;
18205 unsigned G4FIS3
: 1;
18206 unsigned G4FIS4
: 1;
18207 unsigned G4FIS5
: 1;
18208 unsigned G4FIS6
: 1;
18209 unsigned G4FIS7
: 1;
18211 } __COG4FIS0bits_t
;
18213 extern __at(0x0899) volatile __COG4FIS0bits_t COG4FIS0bits
;
18215 #define _COG4FIS0_FIS0 0x01
18216 #define _COG4FIS0_G4FIS0 0x01
18217 #define _COG4FIS0_FIS1 0x02
18218 #define _COG4FIS0_G4FIS1 0x02
18219 #define _COG4FIS0_FIS2 0x04
18220 #define _COG4FIS0_G4FIS2 0x04
18221 #define _COG4FIS0_FIS3 0x08
18222 #define _COG4FIS0_G4FIS3 0x08
18223 #define _COG4FIS0_FIS4 0x10
18224 #define _COG4FIS0_G4FIS4 0x10
18225 #define _COG4FIS0_FIS5 0x20
18226 #define _COG4FIS0_G4FIS5 0x20
18227 #define _COG4FIS0_FIS6 0x40
18228 #define _COG4FIS0_G4FIS6 0x40
18229 #define _COG4FIS0_FIS7 0x80
18230 #define _COG4FIS0_G4FIS7 0x80
18232 //==============================================================================
18235 //==============================================================================
18238 extern __at(0x089A) __sfr COG4FIS1
;
18246 unsigned FIS10
: 1;
18247 unsigned FIS11
: 1;
18248 unsigned FIS12
: 1;
18249 unsigned FIS13
: 1;
18250 unsigned FIS14
: 1;
18251 unsigned FIS15
: 1;
18256 unsigned G4FIS8
: 1;
18257 unsigned G4FIS9
: 1;
18258 unsigned G4FIS10
: 1;
18259 unsigned G4FIS11
: 1;
18260 unsigned G4FIS12
: 1;
18261 unsigned G4FIS13
: 1;
18262 unsigned G4FIS14
: 1;
18263 unsigned G4FIS15
: 1;
18265 } __COG4FIS1bits_t
;
18267 extern __at(0x089A) volatile __COG4FIS1bits_t COG4FIS1bits
;
18269 #define _COG4FIS1_FIS8 0x01
18270 #define _COG4FIS1_G4FIS8 0x01
18271 #define _COG4FIS1_FIS9 0x02
18272 #define _COG4FIS1_G4FIS9 0x02
18273 #define _COG4FIS1_FIS10 0x04
18274 #define _COG4FIS1_G4FIS10 0x04
18275 #define _COG4FIS1_FIS11 0x08
18276 #define _COG4FIS1_G4FIS11 0x08
18277 #define _COG4FIS1_FIS12 0x10
18278 #define _COG4FIS1_G4FIS12 0x10
18279 #define _COG4FIS1_FIS13 0x20
18280 #define _COG4FIS1_G4FIS13 0x20
18281 #define _COG4FIS1_FIS14 0x40
18282 #define _COG4FIS1_G4FIS14 0x40
18283 #define _COG4FIS1_FIS15 0x80
18284 #define _COG4FIS1_G4FIS15 0x80
18286 //==============================================================================
18289 //==============================================================================
18292 extern __at(0x089B) __sfr COG4FSIM0
;
18298 unsigned FSIM0
: 1;
18299 unsigned FSIM1
: 1;
18300 unsigned FSIM2
: 1;
18301 unsigned FSIM3
: 1;
18302 unsigned FSIM4
: 1;
18303 unsigned FSIM5
: 1;
18304 unsigned FSIM6
: 1;
18305 unsigned FSIM7
: 1;
18310 unsigned G4FSIM0
: 1;
18311 unsigned G4FSIM1
: 1;
18312 unsigned G4FSIM2
: 1;
18313 unsigned G4FSIM3
: 1;
18314 unsigned G4FSIM4
: 1;
18315 unsigned G4FSIM5
: 1;
18316 unsigned G4FSIM6
: 1;
18317 unsigned G4FSIM7
: 1;
18319 } __COG4FSIM0bits_t
;
18321 extern __at(0x089B) volatile __COG4FSIM0bits_t COG4FSIM0bits
;
18323 #define _COG4FSIM0_FSIM0 0x01
18324 #define _COG4FSIM0_G4FSIM0 0x01
18325 #define _COG4FSIM0_FSIM1 0x02
18326 #define _COG4FSIM0_G4FSIM1 0x02
18327 #define _COG4FSIM0_FSIM2 0x04
18328 #define _COG4FSIM0_G4FSIM2 0x04
18329 #define _COG4FSIM0_FSIM3 0x08
18330 #define _COG4FSIM0_G4FSIM3 0x08
18331 #define _COG4FSIM0_FSIM4 0x10
18332 #define _COG4FSIM0_G4FSIM4 0x10
18333 #define _COG4FSIM0_FSIM5 0x20
18334 #define _COG4FSIM0_G4FSIM5 0x20
18335 #define _COG4FSIM0_FSIM6 0x40
18336 #define _COG4FSIM0_G4FSIM6 0x40
18337 #define _COG4FSIM0_FSIM7 0x80
18338 #define _COG4FSIM0_G4FSIM7 0x80
18340 //==============================================================================
18343 //==============================================================================
18346 extern __at(0x089C) __sfr COG4FSIM1
;
18352 unsigned FSIM8
: 1;
18353 unsigned FSIM9
: 1;
18354 unsigned FSIM10
: 1;
18355 unsigned FSIM11
: 1;
18356 unsigned FSIM12
: 1;
18357 unsigned FSIM13
: 1;
18358 unsigned FSIM14
: 1;
18359 unsigned FSIM15
: 1;
18364 unsigned G4FSIM8
: 1;
18365 unsigned G4FSIM9
: 1;
18366 unsigned G4FSIM10
: 1;
18367 unsigned G4FSIM11
: 1;
18368 unsigned G4FSIM12
: 1;
18369 unsigned G4FSIM13
: 1;
18370 unsigned G4FSIM14
: 1;
18371 unsigned G4FSIM15
: 1;
18373 } __COG4FSIM1bits_t
;
18375 extern __at(0x089C) volatile __COG4FSIM1bits_t COG4FSIM1bits
;
18377 #define _COG4FSIM1_FSIM8 0x01
18378 #define _COG4FSIM1_G4FSIM8 0x01
18379 #define _COG4FSIM1_FSIM9 0x02
18380 #define _COG4FSIM1_G4FSIM9 0x02
18381 #define _COG4FSIM1_FSIM10 0x04
18382 #define _COG4FSIM1_G4FSIM10 0x04
18383 #define _COG4FSIM1_FSIM11 0x08
18384 #define _COG4FSIM1_G4FSIM11 0x08
18385 #define _COG4FSIM1_FSIM12 0x10
18386 #define _COG4FSIM1_G4FSIM12 0x10
18387 #define _COG4FSIM1_FSIM13 0x20
18388 #define _COG4FSIM1_G4FSIM13 0x20
18389 #define _COG4FSIM1_FSIM14 0x40
18390 #define _COG4FSIM1_G4FSIM14 0x40
18391 #define _COG4FSIM1_FSIM15 0x80
18392 #define _COG4FSIM1_G4FSIM15 0x80
18394 //==============================================================================
18397 //==============================================================================
18400 extern __at(0x089D) __sfr COG4ASD0
;
18408 unsigned ASDAC0
: 1;
18409 unsigned ASDAC1
: 1;
18410 unsigned ASDBD0
: 1;
18411 unsigned ASDBD1
: 1;
18412 unsigned ASREN
: 1;
18420 unsigned G4ASDAC0
: 1;
18421 unsigned G4ASDAC1
: 1;
18422 unsigned G4ASDBD0
: 1;
18423 unsigned G4ASDBD1
: 1;
18424 unsigned ARSEN
: 1;
18425 unsigned G4ASE
: 1;
18436 unsigned G4ARSEN
: 1;
18448 unsigned G4ASREN
: 1;
18455 unsigned G4ASDAC
: 2;
18462 unsigned ASDAC
: 2;
18469 unsigned G4ASDBD
: 2;
18476 unsigned ASDBD
: 2;
18479 } __COG4ASD0bits_t
;
18481 extern __at(0x089D) volatile __COG4ASD0bits_t COG4ASD0bits
;
18483 #define _COG4ASD0_ASDAC0 0x04
18484 #define _COG4ASD0_G4ASDAC0 0x04
18485 #define _COG4ASD0_ASDAC1 0x08
18486 #define _COG4ASD0_G4ASDAC1 0x08
18487 #define _COG4ASD0_ASDBD0 0x10
18488 #define _COG4ASD0_G4ASDBD0 0x10
18489 #define _COG4ASD0_ASDBD1 0x20
18490 #define _COG4ASD0_G4ASDBD1 0x20
18491 #define _COG4ASD0_ASREN 0x40
18492 #define _COG4ASD0_ARSEN 0x40
18493 #define _COG4ASD0_G4ARSEN 0x40
18494 #define _COG4ASD0_G4ASREN 0x40
18495 #define _COG4ASD0_ASE 0x80
18496 #define _COG4ASD0_G4ASE 0x80
18498 //==============================================================================
18501 //==============================================================================
18504 extern __at(0x089E) __sfr COG4ASD1
;
18522 unsigned G4AS0E
: 1;
18523 unsigned G4AS1E
: 1;
18524 unsigned G4AS2E
: 1;
18525 unsigned G4AS3E
: 1;
18526 unsigned G4AS4E
: 1;
18527 unsigned G4AS5E
: 1;
18528 unsigned G4AS6E
: 1;
18529 unsigned G4AS7E
: 1;
18531 } __COG4ASD1bits_t
;
18533 extern __at(0x089E) volatile __COG4ASD1bits_t COG4ASD1bits
;
18535 #define _COG4ASD1_AS0E 0x01
18536 #define _COG4ASD1_G4AS0E 0x01
18537 #define _COG4ASD1_AS1E 0x02
18538 #define _COG4ASD1_G4AS1E 0x02
18539 #define _COG4ASD1_AS2E 0x04
18540 #define _COG4ASD1_G4AS2E 0x04
18541 #define _COG4ASD1_AS3E 0x08
18542 #define _COG4ASD1_G4AS3E 0x08
18543 #define _COG4ASD1_AS4E 0x10
18544 #define _COG4ASD1_G4AS4E 0x10
18545 #define _COG4ASD1_AS5E 0x20
18546 #define _COG4ASD1_G4AS5E 0x20
18547 #define _COG4ASD1_AS6E 0x40
18548 #define _COG4ASD1_G4AS6E 0x40
18549 #define _COG4ASD1_AS7E 0x80
18550 #define _COG4ASD1_G4AS7E 0x80
18552 //==============================================================================
18555 //==============================================================================
18558 extern __at(0x089F) __sfr COG4STR
;
18568 unsigned SDATA
: 1;
18569 unsigned SDATB
: 1;
18570 unsigned SDATC
: 1;
18571 unsigned SDATD
: 1;
18576 unsigned G4STRA
: 1;
18577 unsigned G4STRB
: 1;
18578 unsigned G4STRC
: 1;
18579 unsigned G4STRD
: 1;
18580 unsigned G4SDATA
: 1;
18581 unsigned G4SDATB
: 1;
18582 unsigned G4SDATC
: 1;
18583 unsigned G4SDATD
: 1;
18587 extern __at(0x089F) volatile __COG4STRbits_t COG4STRbits
;
18589 #define _COG4STR_STRA 0x01
18590 #define _COG4STR_G4STRA 0x01
18591 #define _COG4STR_STRB 0x02
18592 #define _COG4STR_G4STRB 0x02
18593 #define _COG4STR_STRC 0x04
18594 #define _COG4STR_G4STRC 0x04
18595 #define _COG4STR_STRD 0x08
18596 #define _COG4STR_G4STRD 0x08
18597 #define _COG4STR_SDATA 0x10
18598 #define _COG4STR_G4SDATA 0x10
18599 #define _COG4STR_SDATB 0x20
18600 #define _COG4STR_G4SDATB 0x20
18601 #define _COG4STR_SDATC 0x40
18602 #define _COG4STR_G4SDATC 0x40
18603 #define _COG4STR_SDATD 0x80
18604 #define _COG4STR_G4SDATD 0x80
18606 //==============================================================================
18609 //==============================================================================
18612 extern __at(0x090C) __sfr CM4CON0
;
18620 unsigned Reserved
: 1;
18630 unsigned C4SYNC
: 1;
18631 unsigned C4HYS
: 1;
18633 unsigned C4ZLF
: 1;
18634 unsigned C4POL
: 1;
18636 unsigned C4OUT
: 1;
18641 extern __at(0x090C) volatile __CM4CON0bits_t CM4CON0bits
;
18643 #define _CM4CON0_SYNC 0x01
18644 #define _CM4CON0_C4SYNC 0x01
18645 #define _CM4CON0_HYS 0x02
18646 #define _CM4CON0_C4HYS 0x02
18647 #define _CM4CON0_Reserved 0x04
18648 #define _CM4CON0_C4SP 0x04
18649 #define _CM4CON0_ZLF 0x08
18650 #define _CM4CON0_C4ZLF 0x08
18651 #define _CM4CON0_POL 0x10
18652 #define _CM4CON0_C4POL 0x10
18653 #define _CM4CON0_OUT 0x40
18654 #define _CM4CON0_C4OUT 0x40
18655 #define _CM4CON0_ON 0x80
18656 #define _CM4CON0_C4ON 0x80
18658 //==============================================================================
18661 //==============================================================================
18664 extern __at(0x090D) __sfr CM4CON1
;
18682 unsigned C4INTN
: 1;
18683 unsigned C4INTP
: 1;
18693 extern __at(0x090D) volatile __CM4CON1bits_t CM4CON1bits
;
18695 #define _CM4CON1_INTN 0x01
18696 #define _CM4CON1_C4INTN 0x01
18697 #define _CM4CON1_INTP 0x02
18698 #define _CM4CON1_C4INTP 0x02
18700 //==============================================================================
18703 //==============================================================================
18706 extern __at(0x090E) __sfr CM4NSEL
;
18712 unsigned C4NCH0
: 1;
18713 unsigned C4NCH1
: 1;
18714 unsigned C4NCH2
: 1;
18715 unsigned C4NCH3
: 1;
18724 unsigned C4NCH
: 4;
18729 extern __at(0x090E) volatile __CM4NSELbits_t CM4NSELbits
;
18731 #define _C4NCH0 0x01
18732 #define _C4NCH1 0x02
18733 #define _C4NCH2 0x04
18734 #define _C4NCH3 0x08
18736 //==============================================================================
18739 //==============================================================================
18742 extern __at(0x090F) __sfr CM4PSEL
;
18760 unsigned C4PCH0
: 1;
18761 unsigned C4PCH1
: 1;
18762 unsigned C4PCH2
: 1;
18763 unsigned C4PCH3
: 1;
18778 unsigned C4PCH
: 4;
18783 extern __at(0x090F) volatile __CM4PSELbits_t CM4PSELbits
;
18785 #define _CM4PSEL_PCH0 0x01
18786 #define _CM4PSEL_C4PCH0 0x01
18787 #define _CM4PSEL_PCH1 0x02
18788 #define _CM4PSEL_C4PCH1 0x02
18789 #define _CM4PSEL_PCH2 0x04
18790 #define _CM4PSEL_C4PCH2 0x04
18791 #define _CM4PSEL_PCH3 0x08
18792 #define _CM4PSEL_C4PCH3 0x08
18794 //==============================================================================
18797 //==============================================================================
18800 extern __at(0x0910) __sfr CM5CON0
;
18808 unsigned Reserved
: 1;
18818 unsigned C5SYNC
: 1;
18819 unsigned C5HYS
: 1;
18821 unsigned C5ZLF
: 1;
18822 unsigned C5POL
: 1;
18824 unsigned C5OUT
: 1;
18829 extern __at(0x0910) volatile __CM5CON0bits_t CM5CON0bits
;
18831 #define _CM5CON0_SYNC 0x01
18832 #define _CM5CON0_C5SYNC 0x01
18833 #define _CM5CON0_HYS 0x02
18834 #define _CM5CON0_C5HYS 0x02
18835 #define _CM5CON0_Reserved 0x04
18836 #define _CM5CON0_C5SP 0x04
18837 #define _CM5CON0_ZLF 0x08
18838 #define _CM5CON0_C5ZLF 0x08
18839 #define _CM5CON0_POL 0x10
18840 #define _CM5CON0_C5POL 0x10
18841 #define _CM5CON0_OUT 0x40
18842 #define _CM5CON0_C5OUT 0x40
18843 #define _CM5CON0_ON 0x80
18844 #define _CM5CON0_C5ON 0x80
18846 //==============================================================================
18849 //==============================================================================
18852 extern __at(0x0911) __sfr CM5CON1
;
18870 unsigned C5INTN
: 1;
18871 unsigned C5INTP
: 1;
18881 extern __at(0x0911) volatile __CM5CON1bits_t CM5CON1bits
;
18883 #define _CM5CON1_INTN 0x01
18884 #define _CM5CON1_C5INTN 0x01
18885 #define _CM5CON1_INTP 0x02
18886 #define _CM5CON1_C5INTP 0x02
18888 //==============================================================================
18891 //==============================================================================
18894 extern __at(0x0912) __sfr CM5NSEL
;
18900 unsigned C5NCH0
: 1;
18901 unsigned C5NCH1
: 1;
18902 unsigned C5NCH2
: 1;
18903 unsigned C5NCH3
: 1;
18912 unsigned C5NCH
: 4;
18917 extern __at(0x0912) volatile __CM5NSELbits_t CM5NSELbits
;
18919 #define _C5NCH0 0x01
18920 #define _C5NCH1 0x02
18921 #define _C5NCH2 0x04
18922 #define _C5NCH3 0x08
18924 //==============================================================================
18927 //==============================================================================
18930 extern __at(0x0913) __sfr CM5PSEL
;
18948 unsigned C5PCH0
: 1;
18949 unsigned C5PCH1
: 1;
18950 unsigned C5PCH2
: 1;
18951 unsigned C5PCH3
: 1;
18966 unsigned C5PCH
: 4;
18971 extern __at(0x0913) volatile __CM5PSELbits_t CM5PSELbits
;
18973 #define _CM5PSEL_PCH0 0x01
18974 #define _CM5PSEL_C5PCH0 0x01
18975 #define _CM5PSEL_PCH1 0x02
18976 #define _CM5PSEL_C5PCH1 0x02
18977 #define _CM5PSEL_PCH2 0x04
18978 #define _CM5PSEL_C5PCH2 0x04
18979 #define _CM5PSEL_PCH3 0x08
18980 #define _CM5PSEL_C5PCH3 0x08
18982 //==============================================================================
18985 //==============================================================================
18988 extern __at(0x0914) __sfr CM6CON0
;
18996 unsigned Reserved
: 1;
19006 unsigned C6SYNC
: 1;
19007 unsigned C6HYS
: 1;
19009 unsigned C6ZLF
: 1;
19010 unsigned C6POL
: 1;
19012 unsigned C6OUT
: 1;
19017 extern __at(0x0914) volatile __CM6CON0bits_t CM6CON0bits
;
19019 #define _CM6CON0_SYNC 0x01
19020 #define _CM6CON0_C6SYNC 0x01
19021 #define _CM6CON0_HYS 0x02
19022 #define _CM6CON0_C6HYS 0x02
19023 #define _CM6CON0_Reserved 0x04
19024 #define _CM6CON0_C6SP 0x04
19025 #define _CM6CON0_ZLF 0x08
19026 #define _CM6CON0_C6ZLF 0x08
19027 #define _CM6CON0_POL 0x10
19028 #define _CM6CON0_C6POL 0x10
19029 #define _CM6CON0_OUT 0x40
19030 #define _CM6CON0_C6OUT 0x40
19031 #define _CM6CON0_ON 0x80
19032 #define _CM6CON0_C6ON 0x80
19034 //==============================================================================
19037 //==============================================================================
19040 extern __at(0x0915) __sfr CM6CON1
;
19058 unsigned C6INTN
: 1;
19059 unsigned C6INTP
: 1;
19069 extern __at(0x0915) volatile __CM6CON1bits_t CM6CON1bits
;
19071 #define _CM6CON1_INTN 0x01
19072 #define _CM6CON1_C6INTN 0x01
19073 #define _CM6CON1_INTP 0x02
19074 #define _CM6CON1_C6INTP 0x02
19076 //==============================================================================
19079 //==============================================================================
19082 extern __at(0x0916) __sfr CM6NSEL
;
19088 unsigned C6NCH0
: 1;
19089 unsigned C6NCH1
: 1;
19090 unsigned C6NCH2
: 1;
19091 unsigned C6NCH3
: 1;
19100 unsigned C6NCH
: 4;
19105 extern __at(0x0916) volatile __CM6NSELbits_t CM6NSELbits
;
19107 #define _C6NCH0 0x01
19108 #define _C6NCH1 0x02
19109 #define _C6NCH2 0x04
19110 #define _C6NCH3 0x08
19112 //==============================================================================
19115 //==============================================================================
19118 extern __at(0x0917) __sfr CM6PSEL
;
19136 unsigned C6PCH0
: 1;
19137 unsigned C6PCH1
: 1;
19138 unsigned C6PCH2
: 1;
19139 unsigned C6PCH3
: 1;
19148 unsigned C6PCH
: 4;
19159 extern __at(0x0917) volatile __CM6PSELbits_t CM6PSELbits
;
19161 #define _CM6PSEL_PCH0 0x01
19162 #define _CM6PSEL_C6PCH0 0x01
19163 #define _CM6PSEL_PCH1 0x02
19164 #define _CM6PSEL_C6PCH1 0x02
19165 #define _CM6PSEL_PCH2 0x04
19166 #define _CM6PSEL_C6PCH2 0x04
19167 #define _CM6PSEL_PCH3 0x08
19168 #define _CM6PSEL_C6PCH3 0x08
19170 //==============================================================================
19173 //==============================================================================
19176 extern __at(0x0918) __sfr CM7CON0
;
19184 unsigned Reserved
: 1;
19194 unsigned C7SYNC
: 1;
19195 unsigned C7HYS
: 1;
19197 unsigned C7ZLF
: 1;
19198 unsigned C7POL
: 1;
19200 unsigned C7OUT
: 1;
19205 extern __at(0x0918) volatile __CM7CON0bits_t CM7CON0bits
;
19207 #define _CM7CON0_SYNC 0x01
19208 #define _CM7CON0_C7SYNC 0x01
19209 #define _CM7CON0_HYS 0x02
19210 #define _CM7CON0_C7HYS 0x02
19211 #define _CM7CON0_Reserved 0x04
19212 #define _CM7CON0_C7SP 0x04
19213 #define _CM7CON0_ZLF 0x08
19214 #define _CM7CON0_C7ZLF 0x08
19215 #define _CM7CON0_POL 0x10
19216 #define _CM7CON0_C7POL 0x10
19217 #define _CM7CON0_OUT 0x40
19218 #define _CM7CON0_C7OUT 0x40
19219 #define _CM7CON0_ON 0x80
19220 #define _CM7CON0_C7ON 0x80
19222 //==============================================================================
19225 //==============================================================================
19228 extern __at(0x0919) __sfr CM7CON1
;
19246 unsigned C7INTN
: 1;
19247 unsigned C7INTP
: 1;
19257 extern __at(0x0919) volatile __CM7CON1bits_t CM7CON1bits
;
19259 #define _CM7CON1_INTN 0x01
19260 #define _CM7CON1_C7INTN 0x01
19261 #define _CM7CON1_INTP 0x02
19262 #define _CM7CON1_C7INTP 0x02
19264 //==============================================================================
19267 //==============================================================================
19270 extern __at(0x091A) __sfr CM7NSEL
;
19276 unsigned C7NCH0
: 1;
19277 unsigned C7NCH1
: 1;
19278 unsigned C7NCH2
: 1;
19279 unsigned C7NCH3
: 1;
19288 unsigned C7NCH
: 4;
19293 extern __at(0x091A) volatile __CM7NSELbits_t CM7NSELbits
;
19295 #define _C7NCH0 0x01
19296 #define _C7NCH1 0x02
19297 #define _C7NCH2 0x04
19298 #define _C7NCH3 0x08
19300 //==============================================================================
19303 //==============================================================================
19306 extern __at(0x091B) __sfr CM7PSEL
;
19324 unsigned C7PCH0
: 1;
19325 unsigned C7PCH1
: 1;
19326 unsigned C7PCH2
: 1;
19327 unsigned C7PCH3
: 1;
19342 unsigned C7PCH
: 4;
19347 extern __at(0x091B) volatile __CM7PSELbits_t CM7PSELbits
;
19349 #define _CM7PSEL_PCH0 0x01
19350 #define _CM7PSEL_C7PCH0 0x01
19351 #define _CM7PSEL_PCH1 0x02
19352 #define _CM7PSEL_C7PCH1 0x02
19353 #define _CM7PSEL_PCH2 0x04
19354 #define _CM7PSEL_C7PCH2 0x04
19355 #define _CM7PSEL_PCH3 0x08
19356 #define _CM7PSEL_C7PCH3 0x08
19358 //==============================================================================
19361 //==============================================================================
19364 extern __at(0x091C) __sfr CM8CON0
;
19372 unsigned Reserved
: 1;
19382 unsigned C8SYNC
: 1;
19383 unsigned C8HYS
: 1;
19385 unsigned C8ZLF
: 1;
19386 unsigned C8POL
: 1;
19388 unsigned C8OUT
: 1;
19393 extern __at(0x091C) volatile __CM8CON0bits_t CM8CON0bits
;
19395 #define _CM8CON0_SYNC 0x01
19396 #define _CM8CON0_C8SYNC 0x01
19397 #define _CM8CON0_HYS 0x02
19398 #define _CM8CON0_C8HYS 0x02
19399 #define _CM8CON0_Reserved 0x04
19400 #define _CM8CON0_C8SP 0x04
19401 #define _CM8CON0_ZLF 0x08
19402 #define _CM8CON0_C8ZLF 0x08
19403 #define _CM8CON0_POL 0x10
19404 #define _CM8CON0_C8POL 0x10
19405 #define _CM8CON0_OUT 0x40
19406 #define _CM8CON0_C8OUT 0x40
19407 #define _CM8CON0_ON 0x80
19408 #define _CM8CON0_C8ON 0x80
19410 //==============================================================================
19413 //==============================================================================
19416 extern __at(0x091D) __sfr CM8CON1
;
19434 unsigned C8INTN
: 1;
19435 unsigned C8INTP
: 1;
19445 extern __at(0x091D) volatile __CM8CON1bits_t CM8CON1bits
;
19447 #define _CM8CON1_INTN 0x01
19448 #define _CM8CON1_C8INTN 0x01
19449 #define _CM8CON1_INTP 0x02
19450 #define _CM8CON1_C8INTP 0x02
19452 //==============================================================================
19455 //==============================================================================
19458 extern __at(0x091E) __sfr CM8NSEL
;
19464 unsigned C8NCH0
: 1;
19465 unsigned C8NCH1
: 1;
19466 unsigned C8NCH2
: 1;
19467 unsigned C8NCH3
: 1;
19476 unsigned C8NCH
: 4;
19481 extern __at(0x091E) volatile __CM8NSELbits_t CM8NSELbits
;
19483 #define _C8NCH0 0x01
19484 #define _C8NCH1 0x02
19485 #define _C8NCH2 0x04
19486 #define _C8NCH3 0x08
19488 //==============================================================================
19491 //==============================================================================
19494 extern __at(0x091F) __sfr CM8PSEL
;
19512 unsigned C8PCH0
: 1;
19513 unsigned C8PCH1
: 1;
19514 unsigned C8PCH2
: 1;
19515 unsigned C8PCH3
: 1;
19524 unsigned C8PCH
: 4;
19535 extern __at(0x091F) volatile __CM8PSELbits_t CM8PSELbits
;
19537 #define _CM8PSEL_PCH0 0x01
19538 #define _CM8PSEL_C8PCH0 0x01
19539 #define _CM8PSEL_PCH1 0x02
19540 #define _CM8PSEL_C8PCH1 0x02
19541 #define _CM8PSEL_PCH2 0x04
19542 #define _CM8PSEL_C8PCH2 0x04
19543 #define _CM8PSEL_PCH3 0x08
19544 #define _CM8PSEL_C8PCH3 0x08
19546 //==============================================================================
19549 //==============================================================================
19552 extern __at(0x0D1B) __sfr MD4CON0
;
19570 unsigned MD4BIT
: 1;
19574 unsigned MD4OPOL
: 1;
19575 unsigned MD4OUT
: 1;
19577 unsigned MD4EN
: 1;
19581 extern __at(0x0D1B) volatile __MD4CON0bits_t MD4CON0bits
;
19583 #define _MD4CON0_BIT 0x01
19584 #define _MD4CON0_MD4BIT 0x01
19585 #define _MD4CON0_OPOL 0x10
19586 #define _MD4CON0_MD4OPOL 0x10
19587 #define _MD4CON0_OUT 0x20
19588 #define _MD4CON0_MD4OUT 0x20
19589 #define _MD4CON0_EN 0x80
19590 #define _MD4CON0_MD4EN 0x80
19592 //==============================================================================
19595 //==============================================================================
19598 extern __at(0x0D1C) __sfr MD4CON1
;
19604 unsigned CLSYNC
: 1;
19605 unsigned CLPOL
: 1;
19608 unsigned CHSYNC
: 1;
19609 unsigned CHPOL
: 1;
19616 unsigned MD4CLSYNC
: 1;
19617 unsigned MD4CLPOL
: 1;
19620 unsigned MD4CHSYNC
: 1;
19621 unsigned MD4CHPOL
: 1;
19627 extern __at(0x0D1C) volatile __MD4CON1bits_t MD4CON1bits
;
19629 #define _MD4CON1_CLSYNC 0x01
19630 #define _MD4CON1_MD4CLSYNC 0x01
19631 #define _MD4CON1_CLPOL 0x02
19632 #define _MD4CON1_MD4CLPOL 0x02
19633 #define _MD4CON1_CHSYNC 0x10
19634 #define _MD4CON1_MD4CHSYNC 0x10
19635 #define _MD4CON1_CHPOL 0x20
19636 #define _MD4CON1_MD4CHPOL 0x20
19638 //==============================================================================
19641 //==============================================================================
19644 extern __at(0x0D1D) __sfr MD4SRC
;
19662 unsigned MD4MS0
: 1;
19663 unsigned MD4MS1
: 1;
19664 unsigned MD4MS2
: 1;
19665 unsigned MD4MS3
: 1;
19666 unsigned MD4MS4
: 1;
19674 unsigned MD4MS
: 5;
19685 extern __at(0x0D1D) volatile __MD4SRCbits_t MD4SRCbits
;
19687 #define _MD4SRC_MS0 0x01
19688 #define _MD4SRC_MD4MS0 0x01
19689 #define _MD4SRC_MS1 0x02
19690 #define _MD4SRC_MD4MS1 0x02
19691 #define _MD4SRC_MS2 0x04
19692 #define _MD4SRC_MD4MS2 0x04
19693 #define _MD4SRC_MS3 0x08
19694 #define _MD4SRC_MD4MS3 0x08
19695 #define _MD4SRC_MS4 0x10
19696 #define _MD4SRC_MD4MS4 0x10
19698 //==============================================================================
19701 //==============================================================================
19704 extern __at(0x0D1E) __sfr MD4CARL
;
19722 unsigned MD4CL0
: 1;
19723 unsigned MD4CL1
: 1;
19724 unsigned MD4CL2
: 1;
19725 unsigned MD4CL3
: 1;
19740 unsigned MD4CL
: 4;
19745 extern __at(0x0D1E) volatile __MD4CARLbits_t MD4CARLbits
;
19747 #define _MD4CARL_CL0 0x01
19748 #define _MD4CARL_MD4CL0 0x01
19749 #define _MD4CARL_CL1 0x02
19750 #define _MD4CARL_MD4CL1 0x02
19751 #define _MD4CARL_CL2 0x04
19752 #define _MD4CARL_MD4CL2 0x04
19753 #define _MD4CARL_CL3 0x08
19754 #define _MD4CARL_MD4CL3 0x08
19755 #define _MD4CARL_CL4 0x10
19757 //==============================================================================
19760 //==============================================================================
19763 extern __at(0x0D1F) __sfr MD4CARH
;
19781 unsigned MD4CH0
: 1;
19782 unsigned MD4CH1
: 1;
19783 unsigned MD4CH2
: 1;
19784 unsigned MD4CH3
: 1;
19793 unsigned MD4CH
: 4;
19804 extern __at(0x0D1F) volatile __MD4CARHbits_t MD4CARHbits
;
19806 #define _MD4CARH_CH0 0x01
19807 #define _MD4CARH_MD4CH0 0x01
19808 #define _MD4CARH_CH1 0x02
19809 #define _MD4CARH_MD4CH1 0x02
19810 #define _MD4CARH_CH2 0x04
19811 #define _MD4CARH_MD4CH2 0x04
19812 #define _MD4CARH_CH3 0x08
19813 #define _MD4CARH_MD4CH3 0x08
19814 #define _MD4CARH_CH4 0x10
19816 //==============================================================================
19819 //==============================================================================
19822 extern __at(0x0D8E) __sfr PWMEN
;
19826 unsigned MPWM5EN
: 1;
19827 unsigned MPWM6EN
: 1;
19828 unsigned MPWM11EN
: 1;
19829 unsigned MPWM12EN
: 1;
19836 extern __at(0x0D8E) volatile __PWMENbits_t PWMENbits
;
19838 #define _MPWM5EN 0x01
19839 #define _MPWM6EN 0x02
19840 #define _MPWM11EN 0x04
19841 #define _MPWM12EN 0x08
19843 //==============================================================================
19846 //==============================================================================
19849 extern __at(0x0D8F) __sfr PWMLD
;
19853 unsigned MPWM5LD
: 1;
19854 unsigned MPWM6LD
: 1;
19855 unsigned MPWM11LD
: 1;
19856 unsigned MPWM12LD
: 1;
19863 extern __at(0x0D8F) volatile __PWMLDbits_t PWMLDbits
;
19865 #define _MPWM5LD 0x01
19866 #define _MPWM6LD 0x02
19867 #define _MPWM11LD 0x04
19868 #define _MPWM12LD 0x08
19870 //==============================================================================
19873 //==============================================================================
19876 extern __at(0x0D90) __sfr PWMOUT
;
19880 unsigned MPWM5OUT
: 1;
19881 unsigned MPWM6OUT
: 1;
19882 unsigned MPWM11OUT
: 1;
19883 unsigned MPWM12OUT
: 1;
19890 extern __at(0x0D90) volatile __PWMOUTbits_t PWMOUTbits
;
19892 #define _MPWM5OUT 0x01
19893 #define _MPWM6OUT 0x02
19894 #define _MPWM11OUT 0x04
19895 #define _MPWM12OUT 0x08
19897 //==============================================================================
19899 extern __at(0x0D91) __sfr PWM5PH
;
19901 //==============================================================================
19904 extern __at(0x0D91) __sfr PWM5PHL
;
19908 unsigned PWM5PHL0
: 1;
19909 unsigned PWM5PHL1
: 1;
19910 unsigned PWM5PHL2
: 1;
19911 unsigned PWM5PHL3
: 1;
19912 unsigned PWM5PHL4
: 1;
19913 unsigned PWM5PHL5
: 1;
19914 unsigned PWM5PHL6
: 1;
19915 unsigned PWM5PHL7
: 1;
19918 extern __at(0x0D91) volatile __PWM5PHLbits_t PWM5PHLbits
;
19920 #define _PWM5PHL0 0x01
19921 #define _PWM5PHL1 0x02
19922 #define _PWM5PHL2 0x04
19923 #define _PWM5PHL3 0x08
19924 #define _PWM5PHL4 0x10
19925 #define _PWM5PHL5 0x20
19926 #define _PWM5PHL6 0x40
19927 #define _PWM5PHL7 0x80
19929 //==============================================================================
19932 //==============================================================================
19935 extern __at(0x0D92) __sfr PWM5PHH
;
19939 unsigned PWM5PHH0
: 1;
19940 unsigned PWM5PHH1
: 1;
19941 unsigned PWM5PHH2
: 1;
19942 unsigned PWM5PHH3
: 1;
19943 unsigned PWM5PHH4
: 1;
19944 unsigned PWM5PHH5
: 1;
19945 unsigned PWM5PHH6
: 1;
19946 unsigned PWM5PHH7
: 1;
19949 extern __at(0x0D92) volatile __PWM5PHHbits_t PWM5PHHbits
;
19951 #define _PWM5PHH0 0x01
19952 #define _PWM5PHH1 0x02
19953 #define _PWM5PHH2 0x04
19954 #define _PWM5PHH3 0x08
19955 #define _PWM5PHH4 0x10
19956 #define _PWM5PHH5 0x20
19957 #define _PWM5PHH6 0x40
19958 #define _PWM5PHH7 0x80
19960 //==============================================================================
19962 extern __at(0x0D93) __sfr PWM5DC
;
19964 //==============================================================================
19967 extern __at(0x0D93) __sfr PWM5DCL
;
19971 unsigned PWM5DCL0
: 1;
19972 unsigned PWM5DCL1
: 1;
19973 unsigned PWM5DCL2
: 1;
19974 unsigned PWM5DCL3
: 1;
19975 unsigned PWM5DCL4
: 1;
19976 unsigned PWM5DCL5
: 1;
19977 unsigned PWM5DCL6
: 1;
19978 unsigned PWM5DCL7
: 1;
19981 extern __at(0x0D93) volatile __PWM5DCLbits_t PWM5DCLbits
;
19983 #define _PWM5DCL0 0x01
19984 #define _PWM5DCL1 0x02
19985 #define _PWM5DCL2 0x04
19986 #define _PWM5DCL3 0x08
19987 #define _PWM5DCL4 0x10
19988 #define _PWM5DCL5 0x20
19989 #define _PWM5DCL6 0x40
19990 #define _PWM5DCL7 0x80
19992 //==============================================================================
19995 //==============================================================================
19998 extern __at(0x0D94) __sfr PWM5DCH
;
20002 unsigned PWM5DCH0
: 1;
20003 unsigned PWM5DCH1
: 1;
20004 unsigned PWM5DCH2
: 1;
20005 unsigned PWM5DCH3
: 1;
20006 unsigned PWM5DCH4
: 1;
20007 unsigned PWM5DCH5
: 1;
20008 unsigned PWM5DCH6
: 1;
20009 unsigned PWM5DCH7
: 1;
20012 extern __at(0x0D94) volatile __PWM5DCHbits_t PWM5DCHbits
;
20014 #define _PWM5DCH0 0x01
20015 #define _PWM5DCH1 0x02
20016 #define _PWM5DCH2 0x04
20017 #define _PWM5DCH3 0x08
20018 #define _PWM5DCH4 0x10
20019 #define _PWM5DCH5 0x20
20020 #define _PWM5DCH6 0x40
20021 #define _PWM5DCH7 0x80
20023 //==============================================================================
20025 extern __at(0x0D95) __sfr PWM5PR
;
20027 //==============================================================================
20030 extern __at(0x0D95) __sfr PWM5PRL
;
20034 unsigned PWM5PRL0
: 1;
20035 unsigned PWM5PRL1
: 1;
20036 unsigned PWM5PRL2
: 1;
20037 unsigned PWM5PRL3
: 1;
20038 unsigned PWM5PRL4
: 1;
20039 unsigned PWM5PRL5
: 1;
20040 unsigned PWM5PRL6
: 1;
20041 unsigned PWM5PRL7
: 1;
20044 extern __at(0x0D95) volatile __PWM5PRLbits_t PWM5PRLbits
;
20046 #define _PWM5PRL0 0x01
20047 #define _PWM5PRL1 0x02
20048 #define _PWM5PRL2 0x04
20049 #define _PWM5PRL3 0x08
20050 #define _PWM5PRL4 0x10
20051 #define _PWM5PRL5 0x20
20052 #define _PWM5PRL6 0x40
20053 #define _PWM5PRL7 0x80
20055 //==============================================================================
20058 //==============================================================================
20061 extern __at(0x0D96) __sfr PWM5PRH
;
20065 unsigned PWM5PRH0
: 1;
20066 unsigned PWM5PRH1
: 1;
20067 unsigned PWM5PRH2
: 1;
20068 unsigned PWM5PRH3
: 1;
20069 unsigned PWM5PRH4
: 1;
20070 unsigned PWM5PRH5
: 1;
20071 unsigned PWM5PRH6
: 1;
20072 unsigned PWM5PRH7
: 1;
20075 extern __at(0x0D96) volatile __PWM5PRHbits_t PWM5PRHbits
;
20077 #define _PWM5PRH0 0x01
20078 #define _PWM5PRH1 0x02
20079 #define _PWM5PRH2 0x04
20080 #define _PWM5PRH3 0x08
20081 #define _PWM5PRH4 0x10
20082 #define _PWM5PRH5 0x20
20083 #define _PWM5PRH6 0x40
20084 #define _PWM5PRH7 0x80
20086 //==============================================================================
20088 extern __at(0x0D97) __sfr PWM5OF
;
20090 //==============================================================================
20093 extern __at(0x0D97) __sfr PWM5OFL
;
20097 unsigned PWM5OFL0
: 1;
20098 unsigned PWM5OFL1
: 1;
20099 unsigned PWM5OFL2
: 1;
20100 unsigned PWM5OFL3
: 1;
20101 unsigned PWM5OFL4
: 1;
20102 unsigned PWM5OFL5
: 1;
20103 unsigned PWM5OFL6
: 1;
20104 unsigned PWM5OFL7
: 1;
20107 extern __at(0x0D97) volatile __PWM5OFLbits_t PWM5OFLbits
;
20109 #define _PWM5OFL0 0x01
20110 #define _PWM5OFL1 0x02
20111 #define _PWM5OFL2 0x04
20112 #define _PWM5OFL3 0x08
20113 #define _PWM5OFL4 0x10
20114 #define _PWM5OFL5 0x20
20115 #define _PWM5OFL6 0x40
20116 #define _PWM5OFL7 0x80
20118 //==============================================================================
20121 //==============================================================================
20124 extern __at(0x0D98) __sfr PWM5OFH
;
20128 unsigned PWM5OFH0
: 1;
20129 unsigned PWM5OFH1
: 1;
20130 unsigned PWM5OFH2
: 1;
20131 unsigned PWM5OFH3
: 1;
20132 unsigned PWM5OFH4
: 1;
20133 unsigned PWM5OFH5
: 1;
20134 unsigned PWM5OFH6
: 1;
20135 unsigned PWM5OFH7
: 1;
20138 extern __at(0x0D98) volatile __PWM5OFHbits_t PWM5OFHbits
;
20140 #define _PWM5OFH0 0x01
20141 #define _PWM5OFH1 0x02
20142 #define _PWM5OFH2 0x04
20143 #define _PWM5OFH3 0x08
20144 #define _PWM5OFH4 0x10
20145 #define _PWM5OFH5 0x20
20146 #define _PWM5OFH6 0x40
20147 #define _PWM5OFH7 0x80
20149 //==============================================================================
20151 extern __at(0x0D99) __sfr PWM5TMR
;
20153 //==============================================================================
20156 extern __at(0x0D99) __sfr PWM5TMRL
;
20160 unsigned PWM5TMRL0
: 1;
20161 unsigned PWM5TMRL1
: 1;
20162 unsigned PWM5TMRL2
: 1;
20163 unsigned PWM5TMRL3
: 1;
20164 unsigned PWM5TMRL4
: 1;
20165 unsigned PWM5TMRL5
: 1;
20166 unsigned PWM5TMRL6
: 1;
20167 unsigned PWM5TMRL7
: 1;
20168 } __PWM5TMRLbits_t
;
20170 extern __at(0x0D99) volatile __PWM5TMRLbits_t PWM5TMRLbits
;
20172 #define _PWM5TMRL0 0x01
20173 #define _PWM5TMRL1 0x02
20174 #define _PWM5TMRL2 0x04
20175 #define _PWM5TMRL3 0x08
20176 #define _PWM5TMRL4 0x10
20177 #define _PWM5TMRL5 0x20
20178 #define _PWM5TMRL6 0x40
20179 #define _PWM5TMRL7 0x80
20181 //==============================================================================
20184 //==============================================================================
20187 extern __at(0x0D9A) __sfr PWM5TMRH
;
20191 unsigned PWM5TMRH0
: 1;
20192 unsigned PWM5TMRH1
: 1;
20193 unsigned PWM5TMRH2
: 1;
20194 unsigned PWM5TMRH3
: 1;
20195 unsigned PWM5TMRH4
: 1;
20196 unsigned PWM5TMRH5
: 1;
20197 unsigned PWM5TMRH6
: 1;
20198 unsigned PWM5TMRH7
: 1;
20199 } __PWM5TMRHbits_t
;
20201 extern __at(0x0D9A) volatile __PWM5TMRHbits_t PWM5TMRHbits
;
20203 #define _PWM5TMRH0 0x01
20204 #define _PWM5TMRH1 0x02
20205 #define _PWM5TMRH2 0x04
20206 #define _PWM5TMRH3 0x08
20207 #define _PWM5TMRH4 0x10
20208 #define _PWM5TMRH5 0x20
20209 #define _PWM5TMRH6 0x40
20210 #define _PWM5TMRH7 0x80
20212 //==============================================================================
20215 //==============================================================================
20218 extern __at(0x0D9B) __sfr PWM5CON
;
20226 unsigned PWM5MODE0
: 1;
20227 unsigned PWM5MODE1
: 1;
20238 unsigned MODE0
: 1;
20239 unsigned MODE1
: 1;
20240 unsigned PWM5POL
: 1;
20241 unsigned PWM5OUT
: 1;
20243 unsigned PWM5EN
: 1;
20249 unsigned PWM5MODE
: 2;
20261 extern __at(0x0D9B) volatile __PWM5CONbits_t PWM5CONbits
;
20263 #define _PWM5CON_PWM5MODE0 0x04
20264 #define _PWM5CON_MODE0 0x04
20265 #define _PWM5CON_PWM5MODE1 0x08
20266 #define _PWM5CON_MODE1 0x08
20267 #define _PWM5CON_POL 0x10
20268 #define _PWM5CON_PWM5POL 0x10
20269 #define _PWM5CON_OUT 0x20
20270 #define _PWM5CON_PWM5OUT 0x20
20271 #define _PWM5CON_EN 0x80
20272 #define _PWM5CON_PWM5EN 0x80
20274 //==============================================================================
20277 //==============================================================================
20280 extern __at(0x0D9C) __sfr PWM5INTCON
;
20298 unsigned PWM5PRIE
: 1;
20299 unsigned PWM5DCIE
: 1;
20300 unsigned PWM5PHIE
: 1;
20301 unsigned PWM5OFIE
: 1;
20307 } __PWM5INTCONbits_t
;
20309 extern __at(0x0D9C) volatile __PWM5INTCONbits_t PWM5INTCONbits
;
20312 #define _PWM5PRIE 0x01
20314 #define _PWM5DCIE 0x02
20316 #define _PWM5PHIE 0x04
20318 #define _PWM5OFIE 0x08
20320 //==============================================================================
20323 //==============================================================================
20326 extern __at(0x0D9C) __sfr PWM5INTE
;
20344 unsigned PWM5PRIE
: 1;
20345 unsigned PWM5DCIE
: 1;
20346 unsigned PWM5PHIE
: 1;
20347 unsigned PWM5OFIE
: 1;
20353 } __PWM5INTEbits_t
;
20355 extern __at(0x0D9C) volatile __PWM5INTEbits_t PWM5INTEbits
;
20357 #define _PWM5INTE_PRIE 0x01
20358 #define _PWM5INTE_PWM5PRIE 0x01
20359 #define _PWM5INTE_DCIE 0x02
20360 #define _PWM5INTE_PWM5DCIE 0x02
20361 #define _PWM5INTE_PHIE 0x04
20362 #define _PWM5INTE_PWM5PHIE 0x04
20363 #define _PWM5INTE_OFIE 0x08
20364 #define _PWM5INTE_PWM5OFIE 0x08
20366 //==============================================================================
20369 //==============================================================================
20372 extern __at(0x0D9D) __sfr PWM5INTF
;
20390 unsigned PWM5PRIF
: 1;
20391 unsigned PWM5DCIF
: 1;
20392 unsigned PWM5PHIF
: 1;
20393 unsigned PWM5OFIF
: 1;
20399 } __PWM5INTFbits_t
;
20401 extern __at(0x0D9D) volatile __PWM5INTFbits_t PWM5INTFbits
;
20404 #define _PWM5PRIF 0x01
20406 #define _PWM5DCIF 0x02
20408 #define _PWM5PHIF 0x04
20410 #define _PWM5OFIF 0x08
20412 //==============================================================================
20415 //==============================================================================
20418 extern __at(0x0D9D) __sfr PWM5INTFLG
;
20436 unsigned PWM5PRIF
: 1;
20437 unsigned PWM5DCIF
: 1;
20438 unsigned PWM5PHIF
: 1;
20439 unsigned PWM5OFIF
: 1;
20445 } __PWM5INTFLGbits_t
;
20447 extern __at(0x0D9D) volatile __PWM5INTFLGbits_t PWM5INTFLGbits
;
20449 #define _PWM5INTFLG_PRIF 0x01
20450 #define _PWM5INTFLG_PWM5PRIF 0x01
20451 #define _PWM5INTFLG_DCIF 0x02
20452 #define _PWM5INTFLG_PWM5DCIF 0x02
20453 #define _PWM5INTFLG_PHIF 0x04
20454 #define _PWM5INTFLG_PWM5PHIF 0x04
20455 #define _PWM5INTFLG_OFIF 0x08
20456 #define _PWM5INTFLG_PWM5OFIF 0x08
20458 //==============================================================================
20461 //==============================================================================
20464 extern __at(0x0D9E) __sfr PWM5CLKCON
;
20470 unsigned PWM5CS0
: 1;
20471 unsigned PWM5CS1
: 1;
20472 unsigned PWM5CS2
: 1;
20474 unsigned PWM5PS0
: 1;
20475 unsigned PWM5PS1
: 1;
20476 unsigned PWM5PS2
: 1;
20500 unsigned PWM5CS
: 3;
20514 unsigned PWM5PS
: 3;
20517 } __PWM5CLKCONbits_t
;
20519 extern __at(0x0D9E) volatile __PWM5CLKCONbits_t PWM5CLKCONbits
;
20521 #define _PWM5CLKCON_PWM5CS0 0x01
20522 #define _PWM5CLKCON_CS0 0x01
20523 #define _PWM5CLKCON_PWM5CS1 0x02
20524 #define _PWM5CLKCON_CS1 0x02
20525 #define _PWM5CLKCON_PWM5CS2 0x04
20526 #define _PWM5CLKCON_CS2 0x04
20527 #define _PWM5CLKCON_PWM5PS0 0x10
20528 #define _PWM5CLKCON_PS0 0x10
20529 #define _PWM5CLKCON_PWM5PS1 0x20
20530 #define _PWM5CLKCON_PS1 0x20
20531 #define _PWM5CLKCON_PWM5PS2 0x40
20532 #define _PWM5CLKCON_PS2 0x40
20534 //==============================================================================
20537 //==============================================================================
20540 extern __at(0x0D9F) __sfr PWM5LDCON
;
20546 unsigned PWM5LDS0
: 1;
20547 unsigned PWM5LDS1
: 1;
20564 unsigned PWM5LDM
: 1;
20565 unsigned PWM5LD
: 1;
20576 unsigned PWM5LDS
: 2;
20579 } __PWM5LDCONbits_t
;
20581 extern __at(0x0D9F) volatile __PWM5LDCONbits_t PWM5LDCONbits
;
20583 #define _PWM5LDS0 0x01
20585 #define _PWM5LDS1 0x02
20588 #define _PWM5LDM 0x40
20590 #define _PWM5LD 0x80
20592 //==============================================================================
20595 //==============================================================================
20598 extern __at(0x0DA0) __sfr PWM5OFCON
;
20604 unsigned PWM5OFS0
: 1;
20605 unsigned PWM5OFS1
: 1;
20609 unsigned PWM5OFM0
: 1;
20610 unsigned PWM5OFM1
: 1;
20620 unsigned PWM5OFMC
: 1;
20634 unsigned PWM5OFS
: 2;
20648 unsigned PWM5OFM
: 2;
20651 } __PWM5OFCONbits_t
;
20653 extern __at(0x0DA0) volatile __PWM5OFCONbits_t PWM5OFCONbits
;
20655 #define _PWM5OFS0 0x01
20657 #define _PWM5OFS1 0x02
20660 #define _PWM5OFMC 0x10
20661 #define _PWM5OFM0 0x20
20663 #define _PWM5OFM1 0x40
20666 //==============================================================================
20668 extern __at(0x0DA1) __sfr PWM6PH
;
20670 //==============================================================================
20673 extern __at(0x0DA1) __sfr PWM6PHL
;
20677 unsigned PWM6PHL0
: 1;
20678 unsigned PWM6PHL1
: 1;
20679 unsigned PWM6PHL2
: 1;
20680 unsigned PWM6PHL3
: 1;
20681 unsigned PWM6PHL4
: 1;
20682 unsigned PWM6PHL5
: 1;
20683 unsigned PWM6PHL6
: 1;
20684 unsigned PWM6PHL7
: 1;
20687 extern __at(0x0DA1) volatile __PWM6PHLbits_t PWM6PHLbits
;
20689 #define _PWM6PHL0 0x01
20690 #define _PWM6PHL1 0x02
20691 #define _PWM6PHL2 0x04
20692 #define _PWM6PHL3 0x08
20693 #define _PWM6PHL4 0x10
20694 #define _PWM6PHL5 0x20
20695 #define _PWM6PHL6 0x40
20696 #define _PWM6PHL7 0x80
20698 //==============================================================================
20701 //==============================================================================
20704 extern __at(0x0DA2) __sfr PWM6PHH
;
20708 unsigned PWM6PHH0
: 1;
20709 unsigned PWM6PHH1
: 1;
20710 unsigned PWM6PHH2
: 1;
20711 unsigned PWM6PHH3
: 1;
20712 unsigned PWM6PHH4
: 1;
20713 unsigned PWM6PHH5
: 1;
20714 unsigned PWM6PHH6
: 1;
20715 unsigned PWM6PHH7
: 1;
20718 extern __at(0x0DA2) volatile __PWM6PHHbits_t PWM6PHHbits
;
20720 #define _PWM6PHH0 0x01
20721 #define _PWM6PHH1 0x02
20722 #define _PWM6PHH2 0x04
20723 #define _PWM6PHH3 0x08
20724 #define _PWM6PHH4 0x10
20725 #define _PWM6PHH5 0x20
20726 #define _PWM6PHH6 0x40
20727 #define _PWM6PHH7 0x80
20729 //==============================================================================
20731 extern __at(0x0DA3) __sfr PWM6DC
;
20733 //==============================================================================
20736 extern __at(0x0DA3) __sfr PWM6DCL
;
20740 unsigned PWM6DCL0
: 1;
20741 unsigned PWM6DCL1
: 1;
20742 unsigned PWM6DCL2
: 1;
20743 unsigned PWM6DCL3
: 1;
20744 unsigned PWM6DCL4
: 1;
20745 unsigned PWM6DCL5
: 1;
20746 unsigned PWM6DCL6
: 1;
20747 unsigned PWM6DCL7
: 1;
20750 extern __at(0x0DA3) volatile __PWM6DCLbits_t PWM6DCLbits
;
20752 #define _PWM6DCL0 0x01
20753 #define _PWM6DCL1 0x02
20754 #define _PWM6DCL2 0x04
20755 #define _PWM6DCL3 0x08
20756 #define _PWM6DCL4 0x10
20757 #define _PWM6DCL5 0x20
20758 #define _PWM6DCL6 0x40
20759 #define _PWM6DCL7 0x80
20761 //==============================================================================
20764 //==============================================================================
20767 extern __at(0x0DA4) __sfr PWM6DCH
;
20771 unsigned PWM6DCH0
: 1;
20772 unsigned PWM6DCH1
: 1;
20773 unsigned PWM6DCH2
: 1;
20774 unsigned PWM6DCH3
: 1;
20775 unsigned PWM6DCH4
: 1;
20776 unsigned PWM6DCH5
: 1;
20777 unsigned PWM6DCH6
: 1;
20778 unsigned PWM6DCH7
: 1;
20781 extern __at(0x0DA4) volatile __PWM6DCHbits_t PWM6DCHbits
;
20783 #define _PWM6DCH0 0x01
20784 #define _PWM6DCH1 0x02
20785 #define _PWM6DCH2 0x04
20786 #define _PWM6DCH3 0x08
20787 #define _PWM6DCH4 0x10
20788 #define _PWM6DCH5 0x20
20789 #define _PWM6DCH6 0x40
20790 #define _PWM6DCH7 0x80
20792 //==============================================================================
20794 extern __at(0x0DA5) __sfr PWM6PR
;
20796 //==============================================================================
20799 extern __at(0x0DA5) __sfr PWM6PRL
;
20803 unsigned PWM6PRL0
: 1;
20804 unsigned PWM6PRL1
: 1;
20805 unsigned PWM6PRL2
: 1;
20806 unsigned PWM6PRL3
: 1;
20807 unsigned PWM6PRL4
: 1;
20808 unsigned PWM6PRL5
: 1;
20809 unsigned PWM6PRL6
: 1;
20810 unsigned PWM6PRL7
: 1;
20813 extern __at(0x0DA5) volatile __PWM6PRLbits_t PWM6PRLbits
;
20815 #define _PWM6PRL0 0x01
20816 #define _PWM6PRL1 0x02
20817 #define _PWM6PRL2 0x04
20818 #define _PWM6PRL3 0x08
20819 #define _PWM6PRL4 0x10
20820 #define _PWM6PRL5 0x20
20821 #define _PWM6PRL6 0x40
20822 #define _PWM6PRL7 0x80
20824 //==============================================================================
20827 //==============================================================================
20830 extern __at(0x0DA6) __sfr PWM6PRH
;
20834 unsigned PWM6PRH0
: 1;
20835 unsigned PWM6PRH1
: 1;
20836 unsigned PWM6PRH2
: 1;
20837 unsigned PWM6PRH3
: 1;
20838 unsigned PWM6PRH4
: 1;
20839 unsigned PWM6PRH5
: 1;
20840 unsigned PWM6PRH6
: 1;
20841 unsigned PWM6PRH7
: 1;
20844 extern __at(0x0DA6) volatile __PWM6PRHbits_t PWM6PRHbits
;
20846 #define _PWM6PRH0 0x01
20847 #define _PWM6PRH1 0x02
20848 #define _PWM6PRH2 0x04
20849 #define _PWM6PRH3 0x08
20850 #define _PWM6PRH4 0x10
20851 #define _PWM6PRH5 0x20
20852 #define _PWM6PRH6 0x40
20853 #define _PWM6PRH7 0x80
20855 //==============================================================================
20857 extern __at(0x0DA7) __sfr PWM6OF
;
20859 //==============================================================================
20862 extern __at(0x0DA7) __sfr PWM6OFL
;
20866 unsigned PWM6OFL0
: 1;
20867 unsigned PWM6OFL1
: 1;
20868 unsigned PWM6OFL2
: 1;
20869 unsigned PWM6OFL3
: 1;
20870 unsigned PWM6OFL4
: 1;
20871 unsigned PWM6OFL5
: 1;
20872 unsigned PWM6OFL6
: 1;
20873 unsigned PWM6OFL7
: 1;
20876 extern __at(0x0DA7) volatile __PWM6OFLbits_t PWM6OFLbits
;
20878 #define _PWM6OFL0 0x01
20879 #define _PWM6OFL1 0x02
20880 #define _PWM6OFL2 0x04
20881 #define _PWM6OFL3 0x08
20882 #define _PWM6OFL4 0x10
20883 #define _PWM6OFL5 0x20
20884 #define _PWM6OFL6 0x40
20885 #define _PWM6OFL7 0x80
20887 //==============================================================================
20890 //==============================================================================
20893 extern __at(0x0DA8) __sfr PWM6OFH
;
20897 unsigned PWM6OFH0
: 1;
20898 unsigned PWM6OFH1
: 1;
20899 unsigned PWM6OFH2
: 1;
20900 unsigned PWM6OFH3
: 1;
20901 unsigned PWM6OFH4
: 1;
20902 unsigned PWM6OFH5
: 1;
20903 unsigned PWM6OFH6
: 1;
20904 unsigned PWM6OFH7
: 1;
20907 extern __at(0x0DA8) volatile __PWM6OFHbits_t PWM6OFHbits
;
20909 #define _PWM6OFH0 0x01
20910 #define _PWM6OFH1 0x02
20911 #define _PWM6OFH2 0x04
20912 #define _PWM6OFH3 0x08
20913 #define _PWM6OFH4 0x10
20914 #define _PWM6OFH5 0x20
20915 #define _PWM6OFH6 0x40
20916 #define _PWM6OFH7 0x80
20918 //==============================================================================
20920 extern __at(0x0DA9) __sfr PWM6TMR
;
20922 //==============================================================================
20925 extern __at(0x0DA9) __sfr PWM6TMRL
;
20929 unsigned PWM6TMRL0
: 1;
20930 unsigned PWM6TMRL1
: 1;
20931 unsigned PWM6TMRL2
: 1;
20932 unsigned PWM6TMRL3
: 1;
20933 unsigned PWM6TMRL4
: 1;
20934 unsigned PWM6TMRL5
: 1;
20935 unsigned PWM6TMRL6
: 1;
20936 unsigned PWM6TMRL7
: 1;
20937 } __PWM6TMRLbits_t
;
20939 extern __at(0x0DA9) volatile __PWM6TMRLbits_t PWM6TMRLbits
;
20941 #define _PWM6TMRL0 0x01
20942 #define _PWM6TMRL1 0x02
20943 #define _PWM6TMRL2 0x04
20944 #define _PWM6TMRL3 0x08
20945 #define _PWM6TMRL4 0x10
20946 #define _PWM6TMRL5 0x20
20947 #define _PWM6TMRL6 0x40
20948 #define _PWM6TMRL7 0x80
20950 //==============================================================================
20953 //==============================================================================
20956 extern __at(0x0DAA) __sfr PWM6TMRH
;
20960 unsigned PWM6TMRH0
: 1;
20961 unsigned PWM6TMRH1
: 1;
20962 unsigned PWM6TMRH2
: 1;
20963 unsigned PWM6TMRH3
: 1;
20964 unsigned PWM6TMRH4
: 1;
20965 unsigned PWM6TMRH5
: 1;
20966 unsigned PWM6TMRH6
: 1;
20967 unsigned PWM6TMRH7
: 1;
20968 } __PWM6TMRHbits_t
;
20970 extern __at(0x0DAA) volatile __PWM6TMRHbits_t PWM6TMRHbits
;
20972 #define _PWM6TMRH0 0x01
20973 #define _PWM6TMRH1 0x02
20974 #define _PWM6TMRH2 0x04
20975 #define _PWM6TMRH3 0x08
20976 #define _PWM6TMRH4 0x10
20977 #define _PWM6TMRH5 0x20
20978 #define _PWM6TMRH6 0x40
20979 #define _PWM6TMRH7 0x80
20981 //==============================================================================
20984 //==============================================================================
20987 extern __at(0x0DAB) __sfr PWM6CON
;
20995 unsigned PWM6MODE0
: 1;
20996 unsigned PWM6MODE1
: 1;
21007 unsigned MODE0
: 1;
21008 unsigned MODE1
: 1;
21009 unsigned PWM6POL
: 1;
21010 unsigned PWM6OUT
: 1;
21012 unsigned PWM6EN
: 1;
21018 unsigned PWM6MODE
: 2;
21030 extern __at(0x0DAB) volatile __PWM6CONbits_t PWM6CONbits
;
21032 #define _PWM6CON_PWM6MODE0 0x04
21033 #define _PWM6CON_MODE0 0x04
21034 #define _PWM6CON_PWM6MODE1 0x08
21035 #define _PWM6CON_MODE1 0x08
21036 #define _PWM6CON_POL 0x10
21037 #define _PWM6CON_PWM6POL 0x10
21038 #define _PWM6CON_OUT 0x20
21039 #define _PWM6CON_PWM6OUT 0x20
21040 #define _PWM6CON_EN 0x80
21041 #define _PWM6CON_PWM6EN 0x80
21043 //==============================================================================
21046 //==============================================================================
21049 extern __at(0x0DAC) __sfr PWM6INTCON
;
21067 unsigned PWM6PRIE
: 1;
21068 unsigned PWM6DCIE
: 1;
21069 unsigned PWM6PHIE
: 1;
21070 unsigned PWM6OFIE
: 1;
21076 } __PWM6INTCONbits_t
;
21078 extern __at(0x0DAC) volatile __PWM6INTCONbits_t PWM6INTCONbits
;
21080 #define _PWM6INTCON_PRIE 0x01
21081 #define _PWM6INTCON_PWM6PRIE 0x01
21082 #define _PWM6INTCON_DCIE 0x02
21083 #define _PWM6INTCON_PWM6DCIE 0x02
21084 #define _PWM6INTCON_PHIE 0x04
21085 #define _PWM6INTCON_PWM6PHIE 0x04
21086 #define _PWM6INTCON_OFIE 0x08
21087 #define _PWM6INTCON_PWM6OFIE 0x08
21089 //==============================================================================
21092 //==============================================================================
21095 extern __at(0x0DAC) __sfr PWM6INTE
;
21113 unsigned PWM6PRIE
: 1;
21114 unsigned PWM6DCIE
: 1;
21115 unsigned PWM6PHIE
: 1;
21116 unsigned PWM6OFIE
: 1;
21122 } __PWM6INTEbits_t
;
21124 extern __at(0x0DAC) volatile __PWM6INTEbits_t PWM6INTEbits
;
21126 #define _PWM6INTE_PRIE 0x01
21127 #define _PWM6INTE_PWM6PRIE 0x01
21128 #define _PWM6INTE_DCIE 0x02
21129 #define _PWM6INTE_PWM6DCIE 0x02
21130 #define _PWM6INTE_PHIE 0x04
21131 #define _PWM6INTE_PWM6PHIE 0x04
21132 #define _PWM6INTE_OFIE 0x08
21133 #define _PWM6INTE_PWM6OFIE 0x08
21135 //==============================================================================
21138 //==============================================================================
21141 extern __at(0x0DAD) __sfr PWM6INTF
;
21159 unsigned PWM6PRIF
: 1;
21160 unsigned PWM6DCIF
: 1;
21161 unsigned PWM6PHIF
: 1;
21162 unsigned PWM6OFIF
: 1;
21168 } __PWM6INTFbits_t
;
21170 extern __at(0x0DAD) volatile __PWM6INTFbits_t PWM6INTFbits
;
21172 #define _PWM6INTF_PRIF 0x01
21173 #define _PWM6INTF_PWM6PRIF 0x01
21174 #define _PWM6INTF_DCIF 0x02
21175 #define _PWM6INTF_PWM6DCIF 0x02
21176 #define _PWM6INTF_PHIF 0x04
21177 #define _PWM6INTF_PWM6PHIF 0x04
21178 #define _PWM6INTF_OFIF 0x08
21179 #define _PWM6INTF_PWM6OFIF 0x08
21181 //==============================================================================
21184 //==============================================================================
21187 extern __at(0x0DAD) __sfr PWM6INTFLG
;
21205 unsigned PWM6PRIF
: 1;
21206 unsigned PWM6DCIF
: 1;
21207 unsigned PWM6PHIF
: 1;
21208 unsigned PWM6OFIF
: 1;
21214 } __PWM6INTFLGbits_t
;
21216 extern __at(0x0DAD) volatile __PWM6INTFLGbits_t PWM6INTFLGbits
;
21218 #define _PWM6INTFLG_PRIF 0x01
21219 #define _PWM6INTFLG_PWM6PRIF 0x01
21220 #define _PWM6INTFLG_DCIF 0x02
21221 #define _PWM6INTFLG_PWM6DCIF 0x02
21222 #define _PWM6INTFLG_PHIF 0x04
21223 #define _PWM6INTFLG_PWM6PHIF 0x04
21224 #define _PWM6INTFLG_OFIF 0x08
21225 #define _PWM6INTFLG_PWM6OFIF 0x08
21227 //==============================================================================
21230 //==============================================================================
21233 extern __at(0x0DAE) __sfr PWM6CLKCON
;
21239 unsigned PWM6CS0
: 1;
21240 unsigned PWM6CS1
: 1;
21241 unsigned PWM6CS2
: 1;
21243 unsigned PWM6PS0
: 1;
21244 unsigned PWM6PS1
: 1;
21245 unsigned PWM6PS2
: 1;
21269 unsigned PWM6CS
: 3;
21276 unsigned PWM6PS
: 3;
21286 } __PWM6CLKCONbits_t
;
21288 extern __at(0x0DAE) volatile __PWM6CLKCONbits_t PWM6CLKCONbits
;
21290 #define _PWM6CLKCON_PWM6CS0 0x01
21291 #define _PWM6CLKCON_CS0 0x01
21292 #define _PWM6CLKCON_PWM6CS1 0x02
21293 #define _PWM6CLKCON_CS1 0x02
21294 #define _PWM6CLKCON_PWM6CS2 0x04
21295 #define _PWM6CLKCON_CS2 0x04
21296 #define _PWM6CLKCON_PWM6PS0 0x10
21297 #define _PWM6CLKCON_PS0 0x10
21298 #define _PWM6CLKCON_PWM6PS1 0x20
21299 #define _PWM6CLKCON_PS1 0x20
21300 #define _PWM6CLKCON_PWM6PS2 0x40
21301 #define _PWM6CLKCON_PS2 0x40
21303 //==============================================================================
21306 //==============================================================================
21309 extern __at(0x0DAF) __sfr PWM6LDCON
;
21315 unsigned PWM6LDS0
: 1;
21316 unsigned PWM6LDS1
: 1;
21333 unsigned PWM6LDM
: 1;
21334 unsigned PWM6LD
: 1;
21345 unsigned PWM6LDS
: 2;
21348 } __PWM6LDCONbits_t
;
21350 extern __at(0x0DAF) volatile __PWM6LDCONbits_t PWM6LDCONbits
;
21352 #define _PWM6LDCON_PWM6LDS0 0x01
21353 #define _PWM6LDCON_LDS0 0x01
21354 #define _PWM6LDCON_PWM6LDS1 0x02
21355 #define _PWM6LDCON_LDS1 0x02
21356 #define _PWM6LDCON_LDT 0x40
21357 #define _PWM6LDCON_PWM6LDM 0x40
21358 #define _PWM6LDCON_LDA 0x80
21359 #define _PWM6LDCON_PWM6LD 0x80
21361 //==============================================================================
21364 //==============================================================================
21367 extern __at(0x0DB0) __sfr PWM6OFCON
;
21373 unsigned PWM6OFS0
: 1;
21374 unsigned PWM6OFS1
: 1;
21378 unsigned PWM6OFM0
: 1;
21379 unsigned PWM6OFM1
: 1;
21389 unsigned PWM6OFMC
: 1;
21397 unsigned PWM6OFS
: 2;
21417 unsigned PWM6OFM
: 2;
21420 } __PWM6OFCONbits_t
;
21422 extern __at(0x0DB0) volatile __PWM6OFCONbits_t PWM6OFCONbits
;
21424 #define _PWM6OFCON_PWM6OFS0 0x01
21425 #define _PWM6OFCON_OFS0 0x01
21426 #define _PWM6OFCON_PWM6OFS1 0x02
21427 #define _PWM6OFCON_OFS1 0x02
21428 #define _PWM6OFCON_OFO 0x10
21429 #define _PWM6OFCON_PWM6OFMC 0x10
21430 #define _PWM6OFCON_PWM6OFM0 0x20
21431 #define _PWM6OFCON_OFM0 0x20
21432 #define _PWM6OFCON_PWM6OFM1 0x40
21433 #define _PWM6OFCON_OFM1 0x40
21435 //==============================================================================
21437 extern __at(0x0DB1) __sfr PWM11PH
;
21439 //==============================================================================
21442 extern __at(0x0DB1) __sfr PWM11PHL
;
21446 unsigned PWM11PHL0
: 1;
21447 unsigned PWM11PHL1
: 1;
21448 unsigned PWM11PHL2
: 1;
21449 unsigned PWM11PHL3
: 1;
21450 unsigned PWM11PHL4
: 1;
21451 unsigned PWM11PHL5
: 1;
21452 unsigned PWM11PHL6
: 1;
21453 unsigned PWM11PHL7
: 1;
21454 } __PWM11PHLbits_t
;
21456 extern __at(0x0DB1) volatile __PWM11PHLbits_t PWM11PHLbits
;
21458 #define _PWM11PHL0 0x01
21459 #define _PWM11PHL1 0x02
21460 #define _PWM11PHL2 0x04
21461 #define _PWM11PHL3 0x08
21462 #define _PWM11PHL4 0x10
21463 #define _PWM11PHL5 0x20
21464 #define _PWM11PHL6 0x40
21465 #define _PWM11PHL7 0x80
21467 //==============================================================================
21470 //==============================================================================
21473 extern __at(0x0DB2) __sfr PWM11PHH
;
21477 unsigned PWM11PHH0
: 1;
21478 unsigned PWM11PHH1
: 1;
21479 unsigned PWM11PHH2
: 1;
21480 unsigned PWM11PHH3
: 1;
21481 unsigned PWM11PHH4
: 1;
21482 unsigned PWM11PHH5
: 1;
21483 unsigned PWM11PHH6
: 1;
21484 unsigned PWM11PHH7
: 1;
21485 } __PWM11PHHbits_t
;
21487 extern __at(0x0DB2) volatile __PWM11PHHbits_t PWM11PHHbits
;
21489 #define _PWM11PHH0 0x01
21490 #define _PWM11PHH1 0x02
21491 #define _PWM11PHH2 0x04
21492 #define _PWM11PHH3 0x08
21493 #define _PWM11PHH4 0x10
21494 #define _PWM11PHH5 0x20
21495 #define _PWM11PHH6 0x40
21496 #define _PWM11PHH7 0x80
21498 //==============================================================================
21500 extern __at(0x0DB3) __sfr PWM11DC
;
21502 //==============================================================================
21505 extern __at(0x0DB3) __sfr PWM11DCL
;
21509 unsigned PWM11DCL0
: 1;
21510 unsigned PWM11DCL1
: 1;
21511 unsigned PWM11DCL2
: 1;
21512 unsigned PWM11DCL3
: 1;
21513 unsigned PWM11DCL4
: 1;
21514 unsigned PWM11DCL5
: 1;
21515 unsigned PWM11DCL6
: 1;
21516 unsigned PWM11DCL7
: 1;
21517 } __PWM11DCLbits_t
;
21519 extern __at(0x0DB3) volatile __PWM11DCLbits_t PWM11DCLbits
;
21521 #define _PWM11DCL0 0x01
21522 #define _PWM11DCL1 0x02
21523 #define _PWM11DCL2 0x04
21524 #define _PWM11DCL3 0x08
21525 #define _PWM11DCL4 0x10
21526 #define _PWM11DCL5 0x20
21527 #define _PWM11DCL6 0x40
21528 #define _PWM11DCL7 0x80
21530 //==============================================================================
21533 //==============================================================================
21536 extern __at(0x0DB4) __sfr PWM11DCH
;
21540 unsigned PWM11DCH0
: 1;
21541 unsigned PWM11DCH1
: 1;
21542 unsigned PWM11DCH2
: 1;
21543 unsigned PWM11DCH3
: 1;
21544 unsigned PWM11DCH4
: 1;
21545 unsigned PWM11DCH5
: 1;
21546 unsigned PWM11DCH6
: 1;
21547 unsigned PWM11DCH7
: 1;
21548 } __PWM11DCHbits_t
;
21550 extern __at(0x0DB4) volatile __PWM11DCHbits_t PWM11DCHbits
;
21552 #define _PWM11DCH0 0x01
21553 #define _PWM11DCH1 0x02
21554 #define _PWM11DCH2 0x04
21555 #define _PWM11DCH3 0x08
21556 #define _PWM11DCH4 0x10
21557 #define _PWM11DCH5 0x20
21558 #define _PWM11DCH6 0x40
21559 #define _PWM11DCH7 0x80
21561 //==============================================================================
21563 extern __at(0x0DB5) __sfr PWM11PR
;
21565 //==============================================================================
21568 extern __at(0x0DB5) __sfr PWM11PRL
;
21572 unsigned PWM11PRL0
: 1;
21573 unsigned PWM11PRL1
: 1;
21574 unsigned PWM11PRL2
: 1;
21575 unsigned PWM11PRL3
: 1;
21576 unsigned PWM11PRL4
: 1;
21577 unsigned PWM11PRL5
: 1;
21578 unsigned PWM11PRL6
: 1;
21579 unsigned PWM11PRL7
: 1;
21580 } __PWM11PRLbits_t
;
21582 extern __at(0x0DB5) volatile __PWM11PRLbits_t PWM11PRLbits
;
21584 #define _PWM11PRL0 0x01
21585 #define _PWM11PRL1 0x02
21586 #define _PWM11PRL2 0x04
21587 #define _PWM11PRL3 0x08
21588 #define _PWM11PRL4 0x10
21589 #define _PWM11PRL5 0x20
21590 #define _PWM11PRL6 0x40
21591 #define _PWM11PRL7 0x80
21593 //==============================================================================
21596 //==============================================================================
21599 extern __at(0x0DB6) __sfr PWM11PRH
;
21603 unsigned PWM11PRH0
: 1;
21604 unsigned PWM11PRH1
: 1;
21605 unsigned PWM11PRH2
: 1;
21606 unsigned PWM11PRH3
: 1;
21607 unsigned PWM11PRH4
: 1;
21608 unsigned PWM11PRH5
: 1;
21609 unsigned PWM11PRH6
: 1;
21610 unsigned PWM11PRH7
: 1;
21611 } __PWM11PRHbits_t
;
21613 extern __at(0x0DB6) volatile __PWM11PRHbits_t PWM11PRHbits
;
21615 #define _PWM11PRH0 0x01
21616 #define _PWM11PRH1 0x02
21617 #define _PWM11PRH2 0x04
21618 #define _PWM11PRH3 0x08
21619 #define _PWM11PRH4 0x10
21620 #define _PWM11PRH5 0x20
21621 #define _PWM11PRH6 0x40
21622 #define _PWM11PRH7 0x80
21624 //==============================================================================
21626 extern __at(0x0DB7) __sfr PWM11OF
;
21628 //==============================================================================
21631 extern __at(0x0DB7) __sfr PWM11OFL
;
21635 unsigned PWM11OFL0
: 1;
21636 unsigned PWM11OFL1
: 1;
21637 unsigned PWM11OFL2
: 1;
21638 unsigned PWM11OFL3
: 1;
21639 unsigned PWM11OFL4
: 1;
21640 unsigned PWM11OFL5
: 1;
21641 unsigned PWM11OFL6
: 1;
21642 unsigned PWM11OFL7
: 1;
21643 } __PWM11OFLbits_t
;
21645 extern __at(0x0DB7) volatile __PWM11OFLbits_t PWM11OFLbits
;
21647 #define _PWM11OFL0 0x01
21648 #define _PWM11OFL1 0x02
21649 #define _PWM11OFL2 0x04
21650 #define _PWM11OFL3 0x08
21651 #define _PWM11OFL4 0x10
21652 #define _PWM11OFL5 0x20
21653 #define _PWM11OFL6 0x40
21654 #define _PWM11OFL7 0x80
21656 //==============================================================================
21659 //==============================================================================
21662 extern __at(0x0DB8) __sfr PWM11OFH
;
21666 unsigned PWM11OFH0
: 1;
21667 unsigned PWM11OFH1
: 1;
21668 unsigned PWM11OFH2
: 1;
21669 unsigned PWM11OFH3
: 1;
21670 unsigned PWM11OFH4
: 1;
21671 unsigned PWM11OFH5
: 1;
21672 unsigned PWM11OFH6
: 1;
21673 unsigned PWM11OFH7
: 1;
21674 } __PWM11OFHbits_t
;
21676 extern __at(0x0DB8) volatile __PWM11OFHbits_t PWM11OFHbits
;
21678 #define _PWM11OFH0 0x01
21679 #define _PWM11OFH1 0x02
21680 #define _PWM11OFH2 0x04
21681 #define _PWM11OFH3 0x08
21682 #define _PWM11OFH4 0x10
21683 #define _PWM11OFH5 0x20
21684 #define _PWM11OFH6 0x40
21685 #define _PWM11OFH7 0x80
21687 //==============================================================================
21689 extern __at(0x0DB9) __sfr PWM11TMR
;
21691 //==============================================================================
21694 extern __at(0x0DB9) __sfr PWM11TMRL
;
21698 unsigned PWM11TMRL0
: 1;
21699 unsigned PWM11TMRL1
: 1;
21700 unsigned PWM11TMRL2
: 1;
21701 unsigned PWM11TMRL3
: 1;
21702 unsigned PWM11TMRL4
: 1;
21703 unsigned PWM11TMRL5
: 1;
21704 unsigned PWM11TMRL6
: 1;
21705 unsigned PWM11TMRL7
: 1;
21706 } __PWM11TMRLbits_t
;
21708 extern __at(0x0DB9) volatile __PWM11TMRLbits_t PWM11TMRLbits
;
21710 #define _PWM11TMRL0 0x01
21711 #define _PWM11TMRL1 0x02
21712 #define _PWM11TMRL2 0x04
21713 #define _PWM11TMRL3 0x08
21714 #define _PWM11TMRL4 0x10
21715 #define _PWM11TMRL5 0x20
21716 #define _PWM11TMRL6 0x40
21717 #define _PWM11TMRL7 0x80
21719 //==============================================================================
21722 //==============================================================================
21725 extern __at(0x0DBA) __sfr PWM11TMRH
;
21729 unsigned PWM11TMRH0
: 1;
21730 unsigned PWM11TMRH1
: 1;
21731 unsigned PWM11TMRH2
: 1;
21732 unsigned PWM11TMRH3
: 1;
21733 unsigned PWM11TMRH4
: 1;
21734 unsigned PWM11TMRH5
: 1;
21735 unsigned PWM11TMRH6
: 1;
21736 unsigned PWM11TMRH7
: 1;
21737 } __PWM11TMRHbits_t
;
21739 extern __at(0x0DBA) volatile __PWM11TMRHbits_t PWM11TMRHbits
;
21741 #define _PWM11TMRH0 0x01
21742 #define _PWM11TMRH1 0x02
21743 #define _PWM11TMRH2 0x04
21744 #define _PWM11TMRH3 0x08
21745 #define _PWM11TMRH4 0x10
21746 #define _PWM11TMRH5 0x20
21747 #define _PWM11TMRH6 0x40
21748 #define _PWM11TMRH7 0x80
21750 //==============================================================================
21753 //==============================================================================
21756 extern __at(0x0DBB) __sfr PWM11CON
;
21764 unsigned PWM11MODE0
: 1;
21765 unsigned PWM11MODE1
: 1;
21776 unsigned MODE0
: 1;
21777 unsigned MODE1
: 1;
21778 unsigned PWM11POL
: 1;
21779 unsigned PWM11OUT
: 1;
21781 unsigned PWM11EN
: 1;
21794 unsigned PWM11MODE
: 2;
21797 } __PWM11CONbits_t
;
21799 extern __at(0x0DBB) volatile __PWM11CONbits_t PWM11CONbits
;
21801 #define _PWM11CON_PWM11MODE0 0x04
21802 #define _PWM11CON_MODE0 0x04
21803 #define _PWM11CON_PWM11MODE1 0x08
21804 #define _PWM11CON_MODE1 0x08
21805 #define _PWM11CON_POL 0x10
21806 #define _PWM11CON_PWM11POL 0x10
21807 #define _PWM11CON_OUT 0x20
21808 #define _PWM11CON_PWM11OUT 0x20
21809 #define _PWM11CON_EN 0x80
21810 #define _PWM11CON_PWM11EN 0x80
21812 //==============================================================================
21815 //==============================================================================
21816 // PWM11INTCON Bits
21818 extern __at(0x0DBC) __sfr PWM11INTCON
;
21836 unsigned PWM11PRIE
: 1;
21837 unsigned PWM11DCIE
: 1;
21838 unsigned PWM11PHIE
: 1;
21839 unsigned PWM11OFIE
: 1;
21845 } __PWM11INTCONbits_t
;
21847 extern __at(0x0DBC) volatile __PWM11INTCONbits_t PWM11INTCONbits
;
21849 #define _PWM11INTCON_PRIE 0x01
21850 #define _PWM11INTCON_PWM11PRIE 0x01
21851 #define _PWM11INTCON_DCIE 0x02
21852 #define _PWM11INTCON_PWM11DCIE 0x02
21853 #define _PWM11INTCON_PHIE 0x04
21854 #define _PWM11INTCON_PWM11PHIE 0x04
21855 #define _PWM11INTCON_OFIE 0x08
21856 #define _PWM11INTCON_PWM11OFIE 0x08
21858 //==============================================================================
21861 //==============================================================================
21864 extern __at(0x0DBC) __sfr PWM11INTE
;
21882 unsigned PWM11PRIE
: 1;
21883 unsigned PWM11DCIE
: 1;
21884 unsigned PWM11PHIE
: 1;
21885 unsigned PWM11OFIE
: 1;
21891 } __PWM11INTEbits_t
;
21893 extern __at(0x0DBC) volatile __PWM11INTEbits_t PWM11INTEbits
;
21895 #define _PWM11INTE_PRIE 0x01
21896 #define _PWM11INTE_PWM11PRIE 0x01
21897 #define _PWM11INTE_DCIE 0x02
21898 #define _PWM11INTE_PWM11DCIE 0x02
21899 #define _PWM11INTE_PHIE 0x04
21900 #define _PWM11INTE_PWM11PHIE 0x04
21901 #define _PWM11INTE_OFIE 0x08
21902 #define _PWM11INTE_PWM11OFIE 0x08
21904 //==============================================================================
21907 //==============================================================================
21910 extern __at(0x0DBD) __sfr PWM11INTF
;
21928 unsigned PWM11PRIF
: 1;
21929 unsigned PWM11DCIF
: 1;
21930 unsigned PWM11PHIF
: 1;
21931 unsigned PWM11OFIF
: 1;
21937 } __PWM11INTFbits_t
;
21939 extern __at(0x0DBD) volatile __PWM11INTFbits_t PWM11INTFbits
;
21941 #define _PWM11INTF_PRIF 0x01
21942 #define _PWM11INTF_PWM11PRIF 0x01
21943 #define _PWM11INTF_DCIF 0x02
21944 #define _PWM11INTF_PWM11DCIF 0x02
21945 #define _PWM11INTF_PHIF 0x04
21946 #define _PWM11INTF_PWM11PHIF 0x04
21947 #define _PWM11INTF_OFIF 0x08
21948 #define _PWM11INTF_PWM11OFIF 0x08
21950 //==============================================================================
21953 //==============================================================================
21954 // PWM11INTFLG Bits
21956 extern __at(0x0DBD) __sfr PWM11INTFLG
;
21974 unsigned PWM11PRIF
: 1;
21975 unsigned PWM11DCIF
: 1;
21976 unsigned PWM11PHIF
: 1;
21977 unsigned PWM11OFIF
: 1;
21983 } __PWM11INTFLGbits_t
;
21985 extern __at(0x0DBD) volatile __PWM11INTFLGbits_t PWM11INTFLGbits
;
21987 #define _PWM11INTFLG_PRIF 0x01
21988 #define _PWM11INTFLG_PWM11PRIF 0x01
21989 #define _PWM11INTFLG_DCIF 0x02
21990 #define _PWM11INTFLG_PWM11DCIF 0x02
21991 #define _PWM11INTFLG_PHIF 0x04
21992 #define _PWM11INTFLG_PWM11PHIF 0x04
21993 #define _PWM11INTFLG_OFIF 0x08
21994 #define _PWM11INTFLG_PWM11OFIF 0x08
21996 //==============================================================================
21999 //==============================================================================
22000 // PWM11CLKCON Bits
22002 extern __at(0x0DBE) __sfr PWM11CLKCON
;
22008 unsigned PWM11CS0
: 1;
22009 unsigned PWM11CS1
: 1;
22010 unsigned PWM11CS2
: 1;
22012 unsigned PWM11PS0
: 1;
22013 unsigned PWM11PS1
: 1;
22014 unsigned PWM11PS2
: 1;
22038 unsigned PWM11CS
: 3;
22045 unsigned PWM11PS
: 3;
22055 } __PWM11CLKCONbits_t
;
22057 extern __at(0x0DBE) volatile __PWM11CLKCONbits_t PWM11CLKCONbits
;
22059 #define _PWM11CLKCON_PWM11CS0 0x01
22060 #define _PWM11CLKCON_CS0 0x01
22061 #define _PWM11CLKCON_PWM11CS1 0x02
22062 #define _PWM11CLKCON_CS1 0x02
22063 #define _PWM11CLKCON_PWM11CS2 0x04
22064 #define _PWM11CLKCON_CS2 0x04
22065 #define _PWM11CLKCON_PWM11PS0 0x10
22066 #define _PWM11CLKCON_PS0 0x10
22067 #define _PWM11CLKCON_PWM11PS1 0x20
22068 #define _PWM11CLKCON_PS1 0x20
22069 #define _PWM11CLKCON_PWM11PS2 0x40
22070 #define _PWM11CLKCON_PS2 0x40
22072 //==============================================================================
22075 //==============================================================================
22078 extern __at(0x0DBF) __sfr PWM11LDCON
;
22084 unsigned PWM11LDS0
: 1;
22085 unsigned PWM11LDS1
: 1;
22102 unsigned PWM11LDM
: 1;
22103 unsigned PWM11LD
: 1;
22114 unsigned PWM11LDS
: 2;
22117 } __PWM11LDCONbits_t
;
22119 extern __at(0x0DBF) volatile __PWM11LDCONbits_t PWM11LDCONbits
;
22121 #define _PWM11LDCON_PWM11LDS0 0x01
22122 #define _PWM11LDCON_LDS0 0x01
22123 #define _PWM11LDCON_PWM11LDS1 0x02
22124 #define _PWM11LDCON_LDS1 0x02
22125 #define _PWM11LDCON_LDT 0x40
22126 #define _PWM11LDCON_PWM11LDM 0x40
22127 #define _PWM11LDCON_LDA 0x80
22128 #define _PWM11LDCON_PWM11LD 0x80
22130 //==============================================================================
22133 //==============================================================================
22136 extern __at(0x0DC0) __sfr PWM11OFCON
;
22142 unsigned PWM11OFS0
: 1;
22143 unsigned PWM11OFS1
: 1;
22147 unsigned PWM11OFM0
: 1;
22148 unsigned PWM11OFM1
: 1;
22158 unsigned PWM11OFMC
: 1;
22172 unsigned PWM11OFS
: 2;
22179 unsigned PWM11OFM
: 2;
22189 } __PWM11OFCONbits_t
;
22191 extern __at(0x0DC0) volatile __PWM11OFCONbits_t PWM11OFCONbits
;
22193 #define _PWM11OFCON_PWM11OFS0 0x01
22194 #define _PWM11OFCON_OFS0 0x01
22195 #define _PWM11OFCON_PWM11OFS1 0x02
22196 #define _PWM11OFCON_OFS1 0x02
22197 #define _PWM11OFCON_OFO 0x10
22198 #define _PWM11OFCON_PWM11OFMC 0x10
22199 #define _PWM11OFCON_PWM11OFM0 0x20
22200 #define _PWM11OFCON_OFM0 0x20
22201 #define _PWM11OFCON_PWM11OFM1 0x40
22202 #define _PWM11OFCON_OFM1 0x40
22204 //==============================================================================
22206 extern __at(0x0DC1) __sfr PWM12PH
;
22208 //==============================================================================
22211 extern __at(0x0DC1) __sfr PWM12PHL
;
22215 unsigned PWM12PHL0
: 1;
22216 unsigned PWM12PHL1
: 1;
22217 unsigned PWM12PHL2
: 1;
22218 unsigned PWM12PHL3
: 1;
22219 unsigned PWM12PHL4
: 1;
22220 unsigned PWM12PHL5
: 1;
22221 unsigned PWM12PHL6
: 1;
22222 unsigned PWM12PHL7
: 1;
22223 } __PWM12PHLbits_t
;
22225 extern __at(0x0DC1) volatile __PWM12PHLbits_t PWM12PHLbits
;
22227 #define _PWM12PHL0 0x01
22228 #define _PWM12PHL1 0x02
22229 #define _PWM12PHL2 0x04
22230 #define _PWM12PHL3 0x08
22231 #define _PWM12PHL4 0x10
22232 #define _PWM12PHL5 0x20
22233 #define _PWM12PHL6 0x40
22234 #define _PWM12PHL7 0x80
22236 //==============================================================================
22239 //==============================================================================
22242 extern __at(0x0DC2) __sfr PWM12PHH
;
22246 unsigned PWM12PHH0
: 1;
22247 unsigned PWM12PHH1
: 1;
22248 unsigned PWM12PHH2
: 1;
22249 unsigned PWM12PHH3
: 1;
22250 unsigned PWM12PHH4
: 1;
22251 unsigned PWM12PHH5
: 1;
22252 unsigned PWM12PHH6
: 1;
22253 unsigned PWM12PHH7
: 1;
22254 } __PWM12PHHbits_t
;
22256 extern __at(0x0DC2) volatile __PWM12PHHbits_t PWM12PHHbits
;
22258 #define _PWM12PHH0 0x01
22259 #define _PWM12PHH1 0x02
22260 #define _PWM12PHH2 0x04
22261 #define _PWM12PHH3 0x08
22262 #define _PWM12PHH4 0x10
22263 #define _PWM12PHH5 0x20
22264 #define _PWM12PHH6 0x40
22265 #define _PWM12PHH7 0x80
22267 //==============================================================================
22269 extern __at(0x0DC3) __sfr PWM12DC
;
22271 //==============================================================================
22274 extern __at(0x0DC3) __sfr PWM12DCL
;
22278 unsigned PWM12DCL0
: 1;
22279 unsigned PWM12DCL1
: 1;
22280 unsigned PWM12DCL2
: 1;
22281 unsigned PWM12DCL3
: 1;
22282 unsigned PWM12DCL4
: 1;
22283 unsigned PWM12DCL5
: 1;
22284 unsigned PWM12DCL6
: 1;
22285 unsigned PWM12DCL7
: 1;
22286 } __PWM12DCLbits_t
;
22288 extern __at(0x0DC3) volatile __PWM12DCLbits_t PWM12DCLbits
;
22290 #define _PWM12DCL0 0x01
22291 #define _PWM12DCL1 0x02
22292 #define _PWM12DCL2 0x04
22293 #define _PWM12DCL3 0x08
22294 #define _PWM12DCL4 0x10
22295 #define _PWM12DCL5 0x20
22296 #define _PWM12DCL6 0x40
22297 #define _PWM12DCL7 0x80
22299 //==============================================================================
22302 //==============================================================================
22305 extern __at(0x0DC4) __sfr PWM12DCH
;
22309 unsigned PWM12DCH0
: 1;
22310 unsigned PWM12DCH1
: 1;
22311 unsigned PWM12DCH2
: 1;
22312 unsigned PWM12DCH3
: 1;
22313 unsigned PWM12DCH4
: 1;
22314 unsigned PWM12DCH5
: 1;
22315 unsigned PWM12DCH6
: 1;
22316 unsigned PWM12DCH7
: 1;
22317 } __PWM12DCHbits_t
;
22319 extern __at(0x0DC4) volatile __PWM12DCHbits_t PWM12DCHbits
;
22321 #define _PWM12DCH0 0x01
22322 #define _PWM12DCH1 0x02
22323 #define _PWM12DCH2 0x04
22324 #define _PWM12DCH3 0x08
22325 #define _PWM12DCH4 0x10
22326 #define _PWM12DCH5 0x20
22327 #define _PWM12DCH6 0x40
22328 #define _PWM12DCH7 0x80
22330 //==============================================================================
22332 extern __at(0x0DC5) __sfr PWM12PR
;
22334 //==============================================================================
22337 extern __at(0x0DC5) __sfr PWM12PRL
;
22341 unsigned PWM12PRL0
: 1;
22342 unsigned PWM12PRL1
: 1;
22343 unsigned PWM12PRL2
: 1;
22344 unsigned PWM12PRL3
: 1;
22345 unsigned PWM12PRL4
: 1;
22346 unsigned PWM12PRL5
: 1;
22347 unsigned PWM12PRL6
: 1;
22348 unsigned PWM12PRL7
: 1;
22349 } __PWM12PRLbits_t
;
22351 extern __at(0x0DC5) volatile __PWM12PRLbits_t PWM12PRLbits
;
22353 #define _PWM12PRL0 0x01
22354 #define _PWM12PRL1 0x02
22355 #define _PWM12PRL2 0x04
22356 #define _PWM12PRL3 0x08
22357 #define _PWM12PRL4 0x10
22358 #define _PWM12PRL5 0x20
22359 #define _PWM12PRL6 0x40
22360 #define _PWM12PRL7 0x80
22362 //==============================================================================
22365 //==============================================================================
22368 extern __at(0x0DC6) __sfr PWM12PRH
;
22372 unsigned PWM12PRH0
: 1;
22373 unsigned PWM12PRH1
: 1;
22374 unsigned PWM12PRH2
: 1;
22375 unsigned PWM12PRH3
: 1;
22376 unsigned PWM12PRH4
: 1;
22377 unsigned PWM12PRH5
: 1;
22378 unsigned PWM12PRH6
: 1;
22379 unsigned PWM12PRH7
: 1;
22380 } __PWM12PRHbits_t
;
22382 extern __at(0x0DC6) volatile __PWM12PRHbits_t PWM12PRHbits
;
22384 #define _PWM12PRH0 0x01
22385 #define _PWM12PRH1 0x02
22386 #define _PWM12PRH2 0x04
22387 #define _PWM12PRH3 0x08
22388 #define _PWM12PRH4 0x10
22389 #define _PWM12PRH5 0x20
22390 #define _PWM12PRH6 0x40
22391 #define _PWM12PRH7 0x80
22393 //==============================================================================
22395 extern __at(0x0DC7) __sfr PWM12OF
;
22397 //==============================================================================
22400 extern __at(0x0DC7) __sfr PWM12OFL
;
22404 unsigned PWM12OFL0
: 1;
22405 unsigned PWM12OFL1
: 1;
22406 unsigned PWM12OFL2
: 1;
22407 unsigned PWM12OFL3
: 1;
22408 unsigned PWM12OFL4
: 1;
22409 unsigned PWM12OFL5
: 1;
22410 unsigned PWM12OFL6
: 1;
22411 unsigned PWM12OFL7
: 1;
22412 } __PWM12OFLbits_t
;
22414 extern __at(0x0DC7) volatile __PWM12OFLbits_t PWM12OFLbits
;
22416 #define _PWM12OFL0 0x01
22417 #define _PWM12OFL1 0x02
22418 #define _PWM12OFL2 0x04
22419 #define _PWM12OFL3 0x08
22420 #define _PWM12OFL4 0x10
22421 #define _PWM12OFL5 0x20
22422 #define _PWM12OFL6 0x40
22423 #define _PWM12OFL7 0x80
22425 //==============================================================================
22428 //==============================================================================
22431 extern __at(0x0DC8) __sfr PWM12OFH
;
22435 unsigned PWM12OFH0
: 1;
22436 unsigned PWM12OFH1
: 1;
22437 unsigned PWM12OFH2
: 1;
22438 unsigned PWM12OFH3
: 1;
22439 unsigned PWM12OFH4
: 1;
22440 unsigned PWM12OFH5
: 1;
22441 unsigned PWM12OFH6
: 1;
22442 unsigned PWM12OFH7
: 1;
22443 } __PWM12OFHbits_t
;
22445 extern __at(0x0DC8) volatile __PWM12OFHbits_t PWM12OFHbits
;
22447 #define _PWM12OFH0 0x01
22448 #define _PWM12OFH1 0x02
22449 #define _PWM12OFH2 0x04
22450 #define _PWM12OFH3 0x08
22451 #define _PWM12OFH4 0x10
22452 #define _PWM12OFH5 0x20
22453 #define _PWM12OFH6 0x40
22454 #define _PWM12OFH7 0x80
22456 //==============================================================================
22458 extern __at(0x0DC9) __sfr PWM12TMR
;
22460 //==============================================================================
22463 extern __at(0x0DC9) __sfr PWM12TMRL
;
22467 unsigned PWM12TMRL0
: 1;
22468 unsigned PWM12TMRL1
: 1;
22469 unsigned PWM12TMRL2
: 1;
22470 unsigned PWM12TMRL3
: 1;
22471 unsigned PWM12TMRL4
: 1;
22472 unsigned PWM12TMRL5
: 1;
22473 unsigned PWM12TMRL6
: 1;
22474 unsigned PWM12TMRL7
: 1;
22475 } __PWM12TMRLbits_t
;
22477 extern __at(0x0DC9) volatile __PWM12TMRLbits_t PWM12TMRLbits
;
22479 #define _PWM12TMRL0 0x01
22480 #define _PWM12TMRL1 0x02
22481 #define _PWM12TMRL2 0x04
22482 #define _PWM12TMRL3 0x08
22483 #define _PWM12TMRL4 0x10
22484 #define _PWM12TMRL5 0x20
22485 #define _PWM12TMRL6 0x40
22486 #define _PWM12TMRL7 0x80
22488 //==============================================================================
22491 //==============================================================================
22494 extern __at(0x0DCA) __sfr PWM12TMRH
;
22498 unsigned PWM12TMRH0
: 1;
22499 unsigned PWM12TMRH1
: 1;
22500 unsigned PWM12TMRH2
: 1;
22501 unsigned PWM12TMRH3
: 1;
22502 unsigned PWM12TMRH4
: 1;
22503 unsigned PWM12TMRH5
: 1;
22504 unsigned PWM12TMRH6
: 1;
22505 unsigned PWM12TMRH7
: 1;
22506 } __PWM12TMRHbits_t
;
22508 extern __at(0x0DCA) volatile __PWM12TMRHbits_t PWM12TMRHbits
;
22510 #define _PWM12TMRH0 0x01
22511 #define _PWM12TMRH1 0x02
22512 #define _PWM12TMRH2 0x04
22513 #define _PWM12TMRH3 0x08
22514 #define _PWM12TMRH4 0x10
22515 #define _PWM12TMRH5 0x20
22516 #define _PWM12TMRH6 0x40
22517 #define _PWM12TMRH7 0x80
22519 //==============================================================================
22522 //==============================================================================
22525 extern __at(0x0DCB) __sfr PWM12CON
;
22533 unsigned PWM12MODE0
: 1;
22534 unsigned PWM12MODE1
: 1;
22545 unsigned MODE0
: 1;
22546 unsigned MODE1
: 1;
22547 unsigned PWM12POL
: 1;
22548 unsigned PWM12OUT
: 1;
22550 unsigned PWM12EN
: 1;
22563 unsigned PWM12MODE
: 2;
22566 } __PWM12CONbits_t
;
22568 extern __at(0x0DCB) volatile __PWM12CONbits_t PWM12CONbits
;
22570 #define _PWM12CON_PWM12MODE0 0x04
22571 #define _PWM12CON_MODE0 0x04
22572 #define _PWM12CON_PWM12MODE1 0x08
22573 #define _PWM12CON_MODE1 0x08
22574 #define _PWM12CON_POL 0x10
22575 #define _PWM12CON_PWM12POL 0x10
22576 #define _PWM12CON_OUT 0x20
22577 #define _PWM12CON_PWM12OUT 0x20
22578 #define _PWM12CON_EN 0x80
22579 #define _PWM12CON_PWM12EN 0x80
22581 //==============================================================================
22584 //==============================================================================
22585 // PWM12INTCON Bits
22587 extern __at(0x0DCC) __sfr PWM12INTCON
;
22605 unsigned PWM12PRIE
: 1;
22606 unsigned PWM12DCIE
: 1;
22607 unsigned PWM12PHIE
: 1;
22608 unsigned PWM12OFIE
: 1;
22614 } __PWM12INTCONbits_t
;
22616 extern __at(0x0DCC) volatile __PWM12INTCONbits_t PWM12INTCONbits
;
22618 #define _PWM12INTCON_PRIE 0x01
22619 #define _PWM12INTCON_PWM12PRIE 0x01
22620 #define _PWM12INTCON_DCIE 0x02
22621 #define _PWM12INTCON_PWM12DCIE 0x02
22622 #define _PWM12INTCON_PHIE 0x04
22623 #define _PWM12INTCON_PWM12PHIE 0x04
22624 #define _PWM12INTCON_OFIE 0x08
22625 #define _PWM12INTCON_PWM12OFIE 0x08
22627 //==============================================================================
22630 //==============================================================================
22633 extern __at(0x0DCC) __sfr PWM12INTE
;
22651 unsigned PWM12PRIE
: 1;
22652 unsigned PWM12DCIE
: 1;
22653 unsigned PWM12PHIE
: 1;
22654 unsigned PWM12OFIE
: 1;
22660 } __PWM12INTEbits_t
;
22662 extern __at(0x0DCC) volatile __PWM12INTEbits_t PWM12INTEbits
;
22664 #define _PWM12INTE_PRIE 0x01
22665 #define _PWM12INTE_PWM12PRIE 0x01
22666 #define _PWM12INTE_DCIE 0x02
22667 #define _PWM12INTE_PWM12DCIE 0x02
22668 #define _PWM12INTE_PHIE 0x04
22669 #define _PWM12INTE_PWM12PHIE 0x04
22670 #define _PWM12INTE_OFIE 0x08
22671 #define _PWM12INTE_PWM12OFIE 0x08
22673 //==============================================================================
22676 //==============================================================================
22679 extern __at(0x0DCD) __sfr PWM12INTF
;
22697 unsigned PWM12PRIF
: 1;
22698 unsigned PWM12DCIF
: 1;
22699 unsigned PWM12PHIF
: 1;
22700 unsigned PWM12OFIF
: 1;
22706 } __PWM12INTFbits_t
;
22708 extern __at(0x0DCD) volatile __PWM12INTFbits_t PWM12INTFbits
;
22710 #define _PWM12INTF_PRIF 0x01
22711 #define _PWM12INTF_PWM12PRIF 0x01
22712 #define _PWM12INTF_DCIF 0x02
22713 #define _PWM12INTF_PWM12DCIF 0x02
22714 #define _PWM12INTF_PHIF 0x04
22715 #define _PWM12INTF_PWM12PHIF 0x04
22716 #define _PWM12INTF_OFIF 0x08
22717 #define _PWM12INTF_PWM12OFIF 0x08
22719 //==============================================================================
22722 //==============================================================================
22723 // PWM12INTFLG Bits
22725 extern __at(0x0DCD) __sfr PWM12INTFLG
;
22743 unsigned PWM12PRIF
: 1;
22744 unsigned PWM12DCIF
: 1;
22745 unsigned PWM12PHIF
: 1;
22746 unsigned PWM12OFIF
: 1;
22752 } __PWM12INTFLGbits_t
;
22754 extern __at(0x0DCD) volatile __PWM12INTFLGbits_t PWM12INTFLGbits
;
22756 #define _PWM12INTFLG_PRIF 0x01
22757 #define _PWM12INTFLG_PWM12PRIF 0x01
22758 #define _PWM12INTFLG_DCIF 0x02
22759 #define _PWM12INTFLG_PWM12DCIF 0x02
22760 #define _PWM12INTFLG_PHIF 0x04
22761 #define _PWM12INTFLG_PWM12PHIF 0x04
22762 #define _PWM12INTFLG_OFIF 0x08
22763 #define _PWM12INTFLG_PWM12OFIF 0x08
22765 //==============================================================================
22768 //==============================================================================
22769 // PWM12CLKCON Bits
22771 extern __at(0x0DCE) __sfr PWM12CLKCON
;
22777 unsigned PWM12CS0
: 1;
22778 unsigned PWM12CS1
: 1;
22779 unsigned PWM12CS2
: 1;
22781 unsigned PWM12PS0
: 1;
22782 unsigned PWM12PS1
: 1;
22783 unsigned PWM12PS2
: 1;
22801 unsigned PWM12CS
: 3;
22821 unsigned PWM12PS
: 3;
22824 } __PWM12CLKCONbits_t
;
22826 extern __at(0x0DCE) volatile __PWM12CLKCONbits_t PWM12CLKCONbits
;
22828 #define _PWM12CLKCON_PWM12CS0 0x01
22829 #define _PWM12CLKCON_CS0 0x01
22830 #define _PWM12CLKCON_PWM12CS1 0x02
22831 #define _PWM12CLKCON_CS1 0x02
22832 #define _PWM12CLKCON_PWM12CS2 0x04
22833 #define _PWM12CLKCON_CS2 0x04
22834 #define _PWM12CLKCON_PWM12PS0 0x10
22835 #define _PWM12CLKCON_PS0 0x10
22836 #define _PWM12CLKCON_PWM12PS1 0x20
22837 #define _PWM12CLKCON_PS1 0x20
22838 #define _PWM12CLKCON_PWM12PS2 0x40
22839 #define _PWM12CLKCON_PS2 0x40
22841 //==============================================================================
22844 //==============================================================================
22847 extern __at(0x0DCF) __sfr PWM12LDCON
;
22853 unsigned PWM12LDS0
: 1;
22854 unsigned PWM12LDS1
: 1;
22871 unsigned PWM12LDM
: 1;
22872 unsigned PWM12LD
: 1;
22883 unsigned PWM12LDS
: 2;
22886 } __PWM12LDCONbits_t
;
22888 extern __at(0x0DCF) volatile __PWM12LDCONbits_t PWM12LDCONbits
;
22890 #define _PWM12LDCON_PWM12LDS0 0x01
22891 #define _PWM12LDCON_LDS0 0x01
22892 #define _PWM12LDCON_PWM12LDS1 0x02
22893 #define _PWM12LDCON_LDS1 0x02
22894 #define _PWM12LDCON_LDT 0x40
22895 #define _PWM12LDCON_PWM12LDM 0x40
22896 #define _PWM12LDCON_LDA 0x80
22897 #define _PWM12LDCON_PWM12LD 0x80
22899 //==============================================================================
22902 //==============================================================================
22905 extern __at(0x0DD0) __sfr PWM12OFCON
;
22911 unsigned PWM12OFS0
: 1;
22912 unsigned PWM12OFS1
: 1;
22916 unsigned PWM12OFM0
: 1;
22917 unsigned PWM12OFM1
: 1;
22927 unsigned PWM12OFMC
: 1;
22941 unsigned PWM12OFS
: 2;
22948 unsigned PWM12OFM
: 2;
22958 } __PWM12OFCONbits_t
;
22960 extern __at(0x0DD0) volatile __PWM12OFCONbits_t PWM12OFCONbits
;
22962 #define _PWM12OFCON_PWM12OFS0 0x01
22963 #define _PWM12OFCON_OFS0 0x01
22964 #define _PWM12OFCON_PWM12OFS1 0x02
22965 #define _PWM12OFCON_OFS1 0x02
22966 #define _PWM12OFCON_OFO 0x10
22967 #define _PWM12OFCON_PWM12OFMC 0x10
22968 #define _PWM12OFCON_PWM12OFM0 0x20
22969 #define _PWM12OFCON_OFM0 0x20
22970 #define _PWM12OFCON_PWM12OFM1 0x40
22971 #define _PWM12OFCON_OFM1 0x40
22973 //==============================================================================
22976 //==============================================================================
22979 extern __at(0x0E0C) __sfr PPSLOCK
;
22983 unsigned PPSLOCKED
: 1;
22993 extern __at(0x0E0C) volatile __PPSLOCKbits_t PPSLOCKbits
;
22995 #define _PPSLOCKED 0x01
22997 //==============================================================================
22999 extern __at(0x0E0D) __sfr INTPPS
;
23000 extern __at(0x0E0E) __sfr T0CKIPPS
;
23001 extern __at(0x0E0F) __sfr T1CKIPPS
;
23002 extern __at(0x0E10) __sfr T1GPPS
;
23003 extern __at(0x0E11) __sfr T3CKIPPS
;
23004 extern __at(0x0E12) __sfr T3GPPS
;
23005 extern __at(0x0E13) __sfr T5CKIPPS
;
23006 extern __at(0x0E14) __sfr T5GPPS
;
23007 extern __at(0x0E15) __sfr T2CKIPPS
;
23008 extern __at(0x0E16) __sfr T4CKIPPS
;
23009 extern __at(0x0E17) __sfr T6CKIPPS
;
23010 extern __at(0x0E18) __sfr T8CKIPPS
;
23011 extern __at(0x0E19) __sfr CCP1PPS
;
23012 extern __at(0x0E1A) __sfr CCP2PPS
;
23013 extern __at(0x0E1B) __sfr CCP7PPS
;
23014 extern __at(0x0E1C) __sfr CCP8PPS
;
23015 extern __at(0x0E1D) __sfr COG1INPPS
;
23016 extern __at(0x0E1E) __sfr COG2INPPS
;
23017 extern __at(0x0E1F) __sfr COG3INPPS
;
23018 extern __at(0x0E20) __sfr COG4INPPS
;
23019 extern __at(0x0E21) __sfr MD1CLPPS
;
23020 extern __at(0x0E22) __sfr MD1CHPPS
;
23021 extern __at(0x0E23) __sfr MD1MODPPS
;
23022 extern __at(0x0E24) __sfr MD2CLPPS
;
23023 extern __at(0x0E25) __sfr MD2CHPPS
;
23024 extern __at(0x0E26) __sfr MD2MODPPS
;
23025 extern __at(0x0E27) __sfr MD3CLPPS
;
23026 extern __at(0x0E28) __sfr MD3CHPPS
;
23027 extern __at(0x0E29) __sfr MD3MODPPS
;
23028 extern __at(0x0E2A) __sfr MD4CLPPS
;
23029 extern __at(0x0E2B) __sfr MD4CHPPS
;
23030 extern __at(0x0E2C) __sfr MD4MODPPS
;
23031 extern __at(0x0E2D) __sfr PRG1RPPS
;
23032 extern __at(0x0E2E) __sfr PRG1FPPS
;
23033 extern __at(0x0E2F) __sfr PRG2RPPS
;
23034 extern __at(0x0E30) __sfr PRG2FPPS
;
23035 extern __at(0x0E31) __sfr PRG3RPPS
;
23036 extern __at(0x0E32) __sfr PRG3FPPS
;
23037 extern __at(0x0E33) __sfr PRG4RPPS
;
23038 extern __at(0x0E34) __sfr PRG4FPPS
;
23039 extern __at(0x0E35) __sfr CLCIN0PPS
;
23040 extern __at(0x0E36) __sfr CLCIN1PPS
;
23041 extern __at(0x0E37) __sfr CLCIN2PPS
;
23042 extern __at(0x0E38) __sfr CLCIN3PPS
;
23043 extern __at(0x0E39) __sfr ADCACTPPS
;
23044 extern __at(0x0E3A) __sfr SSPCLKPPS
;
23045 extern __at(0x0E3B) __sfr SSPDATPPS
;
23046 extern __at(0x0E3C) __sfr SSPSSPPS
;
23047 extern __at(0x0E3D) __sfr RXPPS
;
23048 extern __at(0x0E3E) __sfr CKPPS
;
23049 extern __at(0x0E90) __sfr RA0PPS
;
23050 extern __at(0x0E91) __sfr RA1PPS
;
23051 extern __at(0x0E92) __sfr RA2PPS
;
23052 extern __at(0x0E93) __sfr RA3PPS
;
23053 extern __at(0x0E94) __sfr RA4PPS
;
23054 extern __at(0x0E95) __sfr RA5PPS
;
23055 extern __at(0x0E96) __sfr RA6PPS
;
23056 extern __at(0x0E97) __sfr RA7PPS
;
23057 extern __at(0x0E98) __sfr RB0PPS
;
23058 extern __at(0x0E99) __sfr RB1PPS
;
23059 extern __at(0x0E9A) __sfr RB2PPS
;
23060 extern __at(0x0E9B) __sfr RB3PPS
;
23061 extern __at(0x0E9C) __sfr RB4PPS
;
23062 extern __at(0x0E9D) __sfr RB5PPS
;
23063 extern __at(0x0E9E) __sfr RB6PPS
;
23064 extern __at(0x0E9F) __sfr RB7PPS
;
23065 extern __at(0x0EA0) __sfr RC0PPS
;
23066 extern __at(0x0EA1) __sfr RC1PPS
;
23067 extern __at(0x0EA2) __sfr RC2PPS
;
23068 extern __at(0x0EA3) __sfr RC3PPS
;
23069 extern __at(0x0EA4) __sfr RC4PPS
;
23070 extern __at(0x0EA5) __sfr RC5PPS
;
23071 extern __at(0x0EA6) __sfr RC6PPS
;
23072 extern __at(0x0EA7) __sfr RC7PPS
;
23073 extern __at(0x0EA8) __sfr RD0PPS
;
23074 extern __at(0x0EA9) __sfr RD1PPS
;
23075 extern __at(0x0EAA) __sfr RD2PPS
;
23076 extern __at(0x0EAB) __sfr RD3PPS
;
23077 extern __at(0x0EAC) __sfr RD4PPS
;
23078 extern __at(0x0EAD) __sfr RD5PPS
;
23079 extern __at(0x0EAE) __sfr RD6PPS
;
23080 extern __at(0x0EAF) __sfr RD7PPS
;
23081 extern __at(0x0EB0) __sfr RE0PPS
;
23082 extern __at(0x0EB1) __sfr RE1PPS
;
23083 extern __at(0x0EB2) __sfr RE2PPS
;
23085 //==============================================================================
23088 extern __at(0x0F0F) __sfr CLCDATA
;
23092 unsigned MCLC1OUT
: 1;
23093 unsigned MCLC2OUT
: 1;
23094 unsigned MCLC3OUT
: 1;
23095 unsigned MLC4OUT
: 1;
23102 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
23104 #define _MCLC1OUT 0x01
23105 #define _MCLC2OUT 0x02
23106 #define _MCLC3OUT 0x04
23107 #define _MLC4OUT 0x08
23109 //==============================================================================
23112 //==============================================================================
23115 extern __at(0x0F10) __sfr CLC1CON
;
23121 unsigned LC1MODE0
: 1;
23122 unsigned LC1MODE1
: 1;
23123 unsigned LC1MODE2
: 1;
23124 unsigned LC1INTN
: 1;
23125 unsigned LC1INTP
: 1;
23126 unsigned LC1OUT
: 1;
23128 unsigned LC1EN
: 1;
23133 unsigned MODE0
: 1;
23134 unsigned MODE1
: 1;
23135 unsigned MODE2
: 1;
23145 unsigned LC1MODE
: 3;
23156 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
23158 #define _CLC1CON_LC1MODE0 0x01
23159 #define _CLC1CON_MODE0 0x01
23160 #define _CLC1CON_LC1MODE1 0x02
23161 #define _CLC1CON_MODE1 0x02
23162 #define _CLC1CON_LC1MODE2 0x04
23163 #define _CLC1CON_MODE2 0x04
23164 #define _CLC1CON_LC1INTN 0x08
23165 #define _CLC1CON_INTN 0x08
23166 #define _CLC1CON_LC1INTP 0x10
23167 #define _CLC1CON_INTP 0x10
23168 #define _CLC1CON_LC1OUT 0x20
23169 #define _CLC1CON_OUT 0x20
23170 #define _CLC1CON_LC1EN 0x80
23171 #define _CLC1CON_EN 0x80
23173 //==============================================================================
23176 //==============================================================================
23179 extern __at(0x0F11) __sfr CLC1POL
;
23185 unsigned LC1G1POL
: 1;
23186 unsigned LC1G2POL
: 1;
23187 unsigned LC1G3POL
: 1;
23188 unsigned LC1G4POL
: 1;
23192 unsigned LC1POL
: 1;
23197 unsigned G1POL
: 1;
23198 unsigned G2POL
: 1;
23199 unsigned G3POL
: 1;
23200 unsigned G4POL
: 1;
23208 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
23210 #define _LC1G1POL 0x01
23211 #define _G1POL 0x01
23212 #define _LC1G2POL 0x02
23213 #define _G2POL 0x02
23214 #define _LC1G3POL 0x04
23215 #define _G3POL 0x04
23216 #define _LC1G4POL 0x08
23217 #define _G4POL 0x08
23218 #define _LC1POL 0x80
23221 //==============================================================================
23224 //==============================================================================
23227 extern __at(0x0F12) __sfr CLC1SEL0
;
23233 unsigned LC1D1S0
: 1;
23234 unsigned LC1D1S1
: 1;
23235 unsigned LC1D1S2
: 1;
23236 unsigned LC1D1S3
: 1;
23237 unsigned LC1D1S4
: 1;
23238 unsigned LC1D1S5
: 1;
23263 unsigned LC1D1S
: 6;
23266 } __CLC1SEL0bits_t
;
23268 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
23270 #define _LC1D1S0 0x01
23272 #define _LC1D1S1 0x02
23274 #define _LC1D1S2 0x04
23276 #define _LC1D1S3 0x08
23278 #define _LC1D1S4 0x10
23280 #define _LC1D1S5 0x20
23283 //==============================================================================
23286 //==============================================================================
23289 extern __at(0x0F13) __sfr CLC1SEL1
;
23295 unsigned LC1D2S0
: 1;
23296 unsigned LC1D2S1
: 1;
23297 unsigned LC1D2S2
: 1;
23298 unsigned LC1D2S3
: 1;
23299 unsigned LC1D2S4
: 1;
23300 unsigned LC1D2S5
: 1;
23319 unsigned LC1D2S
: 6;
23328 } __CLC1SEL1bits_t
;
23330 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
23332 #define _LC1D2S0 0x01
23334 #define _LC1D2S1 0x02
23336 #define _LC1D2S2 0x04
23338 #define _LC1D2S3 0x08
23340 #define _LC1D2S4 0x10
23342 #define _LC1D2S5 0x20
23345 //==============================================================================
23348 //==============================================================================
23351 extern __at(0x0F14) __sfr CLC1SEL2
;
23357 unsigned LC1D3S0
: 1;
23358 unsigned LC1D3S1
: 1;
23359 unsigned LC1D3S2
: 1;
23360 unsigned LC1D3S3
: 1;
23361 unsigned LC1D3S4
: 1;
23362 unsigned LC1D3S5
: 1;
23381 unsigned LC1D3S
: 6;
23390 } __CLC1SEL2bits_t
;
23392 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
23394 #define _LC1D3S0 0x01
23396 #define _LC1D3S1 0x02
23398 #define _LC1D3S2 0x04
23400 #define _LC1D3S3 0x08
23402 #define _LC1D3S4 0x10
23404 #define _LC1D3S5 0x20
23407 //==============================================================================
23410 //==============================================================================
23413 extern __at(0x0F15) __sfr CLC1SEL3
;
23419 unsigned LC1D4S0
: 1;
23420 unsigned LC1D4S1
: 1;
23421 unsigned LC1D4S2
: 1;
23422 unsigned LC1D4S3
: 1;
23423 unsigned LC1D4S4
: 1;
23424 unsigned LC1D4S5
: 1;
23443 unsigned LC1D4S
: 6;
23452 } __CLC1SEL3bits_t
;
23454 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
23456 #define _LC1D4S0 0x01
23458 #define _LC1D4S1 0x02
23460 #define _LC1D4S2 0x04
23462 #define _LC1D4S3 0x08
23464 #define _LC1D4S4 0x10
23466 #define _LC1D4S5 0x20
23469 //==============================================================================
23472 //==============================================================================
23475 extern __at(0x0F16) __sfr CLC1GLS0
;
23481 unsigned LC1G1D1N
: 1;
23482 unsigned LC1G1D1T
: 1;
23483 unsigned LC1G1D2N
: 1;
23484 unsigned LC1G1D2T
: 1;
23485 unsigned LC1G1D3N
: 1;
23486 unsigned LC1G1D3T
: 1;
23487 unsigned LC1G1D4N
: 1;
23488 unsigned LC1G1D4T
: 1;
23502 } __CLC1GLS0bits_t
;
23504 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
23506 #define _LC1G1D1N 0x01
23508 #define _LC1G1D1T 0x02
23510 #define _LC1G1D2N 0x04
23512 #define _LC1G1D2T 0x08
23514 #define _LC1G1D3N 0x10
23516 #define _LC1G1D3T 0x20
23518 #define _LC1G1D4N 0x40
23520 #define _LC1G1D4T 0x80
23523 //==============================================================================
23526 //==============================================================================
23529 extern __at(0x0F17) __sfr CLC1GLS1
;
23535 unsigned LC1G2D1N
: 1;
23536 unsigned LC1G2D1T
: 1;
23537 unsigned LC1G2D2N
: 1;
23538 unsigned LC1G2D2T
: 1;
23539 unsigned LC1G2D3N
: 1;
23540 unsigned LC1G2D3T
: 1;
23541 unsigned LC1G2D4N
: 1;
23542 unsigned LC1G2D4T
: 1;
23556 } __CLC1GLS1bits_t
;
23558 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
23560 #define _CLC1GLS1_LC1G2D1N 0x01
23561 #define _CLC1GLS1_D1N 0x01
23562 #define _CLC1GLS1_LC1G2D1T 0x02
23563 #define _CLC1GLS1_D1T 0x02
23564 #define _CLC1GLS1_LC1G2D2N 0x04
23565 #define _CLC1GLS1_D2N 0x04
23566 #define _CLC1GLS1_LC1G2D2T 0x08
23567 #define _CLC1GLS1_D2T 0x08
23568 #define _CLC1GLS1_LC1G2D3N 0x10
23569 #define _CLC1GLS1_D3N 0x10
23570 #define _CLC1GLS1_LC1G2D3T 0x20
23571 #define _CLC1GLS1_D3T 0x20
23572 #define _CLC1GLS1_LC1G2D4N 0x40
23573 #define _CLC1GLS1_D4N 0x40
23574 #define _CLC1GLS1_LC1G2D4T 0x80
23575 #define _CLC1GLS1_D4T 0x80
23577 //==============================================================================
23580 //==============================================================================
23583 extern __at(0x0F18) __sfr CLC1GLS2
;
23589 unsigned LC1G3D1N
: 1;
23590 unsigned LC1G3D1T
: 1;
23591 unsigned LC1G3D2N
: 1;
23592 unsigned LC1G3D2T
: 1;
23593 unsigned LC1G3D3N
: 1;
23594 unsigned LC1G3D3T
: 1;
23595 unsigned LC1G3D4N
: 1;
23596 unsigned LC1G3D4T
: 1;
23610 } __CLC1GLS2bits_t
;
23612 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
23614 #define _CLC1GLS2_LC1G3D1N 0x01
23615 #define _CLC1GLS2_D1N 0x01
23616 #define _CLC1GLS2_LC1G3D1T 0x02
23617 #define _CLC1GLS2_D1T 0x02
23618 #define _CLC1GLS2_LC1G3D2N 0x04
23619 #define _CLC1GLS2_D2N 0x04
23620 #define _CLC1GLS2_LC1G3D2T 0x08
23621 #define _CLC1GLS2_D2T 0x08
23622 #define _CLC1GLS2_LC1G3D3N 0x10
23623 #define _CLC1GLS2_D3N 0x10
23624 #define _CLC1GLS2_LC1G3D3T 0x20
23625 #define _CLC1GLS2_D3T 0x20
23626 #define _CLC1GLS2_LC1G3D4N 0x40
23627 #define _CLC1GLS2_D4N 0x40
23628 #define _CLC1GLS2_LC1G3D4T 0x80
23629 #define _CLC1GLS2_D4T 0x80
23631 //==============================================================================
23634 //==============================================================================
23637 extern __at(0x0F19) __sfr CLC1GLS3
;
23643 unsigned LC1G4D1N
: 1;
23644 unsigned LC1G4D1T
: 1;
23645 unsigned LC1G4D2N
: 1;
23646 unsigned LC1G4D2T
: 1;
23647 unsigned LC1G4D3N
: 1;
23648 unsigned LC1G4D3T
: 1;
23649 unsigned LC1G4D4N
: 1;
23650 unsigned LC1G4D4T
: 1;
23655 unsigned G4D1N
: 1;
23656 unsigned G4D1T
: 1;
23657 unsigned G4D2N
: 1;
23658 unsigned G4D2T
: 1;
23659 unsigned G4D3N
: 1;
23660 unsigned G4D3T
: 1;
23661 unsigned G4D4N
: 1;
23662 unsigned G4D4T
: 1;
23664 } __CLC1GLS3bits_t
;
23666 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
23668 #define _LC1G4D1N 0x01
23669 #define _G4D1N 0x01
23670 #define _LC1G4D1T 0x02
23671 #define _G4D1T 0x02
23672 #define _LC1G4D2N 0x04
23673 #define _G4D2N 0x04
23674 #define _LC1G4D2T 0x08
23675 #define _G4D2T 0x08
23676 #define _LC1G4D3N 0x10
23677 #define _G4D3N 0x10
23678 #define _LC1G4D3T 0x20
23679 #define _G4D3T 0x20
23680 #define _LC1G4D4N 0x40
23681 #define _G4D4N 0x40
23682 #define _LC1G4D4T 0x80
23683 #define _G4D4T 0x80
23685 //==============================================================================
23688 //==============================================================================
23691 extern __at(0x0F1A) __sfr CLC2CON
;
23697 unsigned LC2MODE0
: 1;
23698 unsigned LC2MODE1
: 1;
23699 unsigned LC2MODE2
: 1;
23700 unsigned LC2INTN
: 1;
23701 unsigned LC2INTP
: 1;
23702 unsigned LC2OUT
: 1;
23704 unsigned LC2EN
: 1;
23709 unsigned MODE0
: 1;
23710 unsigned MODE1
: 1;
23711 unsigned MODE2
: 1;
23721 unsigned LC2MODE
: 3;
23732 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
23734 #define _CLC2CON_LC2MODE0 0x01
23735 #define _CLC2CON_MODE0 0x01
23736 #define _CLC2CON_LC2MODE1 0x02
23737 #define _CLC2CON_MODE1 0x02
23738 #define _CLC2CON_LC2MODE2 0x04
23739 #define _CLC2CON_MODE2 0x04
23740 #define _CLC2CON_LC2INTN 0x08
23741 #define _CLC2CON_INTN 0x08
23742 #define _CLC2CON_LC2INTP 0x10
23743 #define _CLC2CON_INTP 0x10
23744 #define _CLC2CON_LC2OUT 0x20
23745 #define _CLC2CON_OUT 0x20
23746 #define _CLC2CON_LC2EN 0x80
23747 #define _CLC2CON_EN 0x80
23749 //==============================================================================
23752 //==============================================================================
23755 extern __at(0x0F1B) __sfr CLC2POL
;
23761 unsigned LC2G1POL
: 1;
23762 unsigned LC2G2POL
: 1;
23763 unsigned LC2G3POL
: 1;
23764 unsigned LC2G4POL
: 1;
23768 unsigned LC2POL
: 1;
23773 unsigned G1POL
: 1;
23774 unsigned G2POL
: 1;
23775 unsigned G3POL
: 1;
23776 unsigned G4POL
: 1;
23784 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
23786 #define _CLC2POL_LC2G1POL 0x01
23787 #define _CLC2POL_G1POL 0x01
23788 #define _CLC2POL_LC2G2POL 0x02
23789 #define _CLC2POL_G2POL 0x02
23790 #define _CLC2POL_LC2G3POL 0x04
23791 #define _CLC2POL_G3POL 0x04
23792 #define _CLC2POL_LC2G4POL 0x08
23793 #define _CLC2POL_G4POL 0x08
23794 #define _CLC2POL_LC2POL 0x80
23795 #define _CLC2POL_POL 0x80
23797 //==============================================================================
23800 //==============================================================================
23803 extern __at(0x0F1C) __sfr CLC2SEL0
;
23809 unsigned LC2D1S0
: 1;
23810 unsigned LC2D1S1
: 1;
23811 unsigned LC2D1S2
: 1;
23812 unsigned LC2D1S3
: 1;
23813 unsigned LC2D1S4
: 1;
23814 unsigned LC2D1S5
: 1;
23839 unsigned LC2D1S
: 6;
23842 } __CLC2SEL0bits_t
;
23844 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
23846 #define _CLC2SEL0_LC2D1S0 0x01
23847 #define _CLC2SEL0_D1S0 0x01
23848 #define _CLC2SEL0_LC2D1S1 0x02
23849 #define _CLC2SEL0_D1S1 0x02
23850 #define _CLC2SEL0_LC2D1S2 0x04
23851 #define _CLC2SEL0_D1S2 0x04
23852 #define _CLC2SEL0_LC2D1S3 0x08
23853 #define _CLC2SEL0_D1S3 0x08
23854 #define _CLC2SEL0_LC2D1S4 0x10
23855 #define _CLC2SEL0_D1S4 0x10
23856 #define _CLC2SEL0_LC2D1S5 0x20
23857 #define _CLC2SEL0_D1S5 0x20
23859 //==============================================================================
23862 //==============================================================================
23865 extern __at(0x0F1D) __sfr CLC2SEL1
;
23871 unsigned LC2D2S0
: 1;
23872 unsigned LC2D2S1
: 1;
23873 unsigned LC2D2S2
: 1;
23874 unsigned LC2D2S3
: 1;
23875 unsigned LC2D2S4
: 1;
23876 unsigned LC2D2S5
: 1;
23895 unsigned LC2D2S
: 6;
23904 } __CLC2SEL1bits_t
;
23906 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
23908 #define _CLC2SEL1_LC2D2S0 0x01
23909 #define _CLC2SEL1_D2S0 0x01
23910 #define _CLC2SEL1_LC2D2S1 0x02
23911 #define _CLC2SEL1_D2S1 0x02
23912 #define _CLC2SEL1_LC2D2S2 0x04
23913 #define _CLC2SEL1_D2S2 0x04
23914 #define _CLC2SEL1_LC2D2S3 0x08
23915 #define _CLC2SEL1_D2S3 0x08
23916 #define _CLC2SEL1_LC2D2S4 0x10
23917 #define _CLC2SEL1_D2S4 0x10
23918 #define _CLC2SEL1_LC2D2S5 0x20
23919 #define _CLC2SEL1_D2S5 0x20
23921 //==============================================================================
23924 //==============================================================================
23927 extern __at(0x0F1E) __sfr CLC2SEL2
;
23933 unsigned LC2D3S0
: 1;
23934 unsigned LC2D3S1
: 1;
23935 unsigned LC2D3S2
: 1;
23936 unsigned LC2D3S3
: 1;
23937 unsigned LC2D3S4
: 1;
23938 unsigned LC2D3S5
: 1;
23963 unsigned LC2D3S
: 6;
23966 } __CLC2SEL2bits_t
;
23968 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
23970 #define _CLC2SEL2_LC2D3S0 0x01
23971 #define _CLC2SEL2_D3S0 0x01
23972 #define _CLC2SEL2_LC2D3S1 0x02
23973 #define _CLC2SEL2_D3S1 0x02
23974 #define _CLC2SEL2_LC2D3S2 0x04
23975 #define _CLC2SEL2_D3S2 0x04
23976 #define _CLC2SEL2_LC2D3S3 0x08
23977 #define _CLC2SEL2_D3S3 0x08
23978 #define _CLC2SEL2_LC2D3S4 0x10
23979 #define _CLC2SEL2_D3S4 0x10
23980 #define _CLC2SEL2_LC2D3S5 0x20
23981 #define _CLC2SEL2_D3S5 0x20
23983 //==============================================================================
23986 //==============================================================================
23989 extern __at(0x0F1F) __sfr CLC2SEL3
;
23995 unsigned LC2D4S0
: 1;
23996 unsigned LC2D4S1
: 1;
23997 unsigned LC2D4S2
: 1;
23998 unsigned LC2D4S3
: 1;
23999 unsigned LC2D4S4
: 1;
24000 unsigned LC2D4S5
: 1;
24019 unsigned LC2D4S
: 6;
24028 } __CLC2SEL3bits_t
;
24030 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
24032 #define _CLC2SEL3_LC2D4S0 0x01
24033 #define _CLC2SEL3_D4S0 0x01
24034 #define _CLC2SEL3_LC2D4S1 0x02
24035 #define _CLC2SEL3_D4S1 0x02
24036 #define _CLC2SEL3_LC2D4S2 0x04
24037 #define _CLC2SEL3_D4S2 0x04
24038 #define _CLC2SEL3_LC2D4S3 0x08
24039 #define _CLC2SEL3_D4S3 0x08
24040 #define _CLC2SEL3_LC2D4S4 0x10
24041 #define _CLC2SEL3_D4S4 0x10
24042 #define _CLC2SEL3_LC2D4S5 0x20
24043 #define _CLC2SEL3_D4S5 0x20
24045 //==============================================================================
24048 //==============================================================================
24051 extern __at(0x0F20) __sfr CLC2GLS0
;
24057 unsigned LC2G1D1N
: 1;
24058 unsigned LC2G1D1T
: 1;
24059 unsigned LC2G1D2N
: 1;
24060 unsigned LC2G1D2T
: 1;
24061 unsigned LC2G1D3N
: 1;
24062 unsigned LC2G1D3T
: 1;
24063 unsigned LC2G1D4N
: 1;
24064 unsigned LC2G1D4T
: 1;
24078 } __CLC2GLS0bits_t
;
24080 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
24082 #define _CLC2GLS0_LC2G1D1N 0x01
24083 #define _CLC2GLS0_D1N 0x01
24084 #define _CLC2GLS0_LC2G1D1T 0x02
24085 #define _CLC2GLS0_D1T 0x02
24086 #define _CLC2GLS0_LC2G1D2N 0x04
24087 #define _CLC2GLS0_D2N 0x04
24088 #define _CLC2GLS0_LC2G1D2T 0x08
24089 #define _CLC2GLS0_D2T 0x08
24090 #define _CLC2GLS0_LC2G1D3N 0x10
24091 #define _CLC2GLS0_D3N 0x10
24092 #define _CLC2GLS0_LC2G1D3T 0x20
24093 #define _CLC2GLS0_D3T 0x20
24094 #define _CLC2GLS0_LC2G1D4N 0x40
24095 #define _CLC2GLS0_D4N 0x40
24096 #define _CLC2GLS0_LC2G1D4T 0x80
24097 #define _CLC2GLS0_D4T 0x80
24099 //==============================================================================
24102 //==============================================================================
24105 extern __at(0x0F21) __sfr CLC2GLS1
;
24111 unsigned LC2G2D1N
: 1;
24112 unsigned LC2G2D1T
: 1;
24113 unsigned LC2G2D2N
: 1;
24114 unsigned LC2G2D2T
: 1;
24115 unsigned LC2G2D3N
: 1;
24116 unsigned LC2G2D3T
: 1;
24117 unsigned LC2G2D4N
: 1;
24118 unsigned LC2G2D4T
: 1;
24132 } __CLC2GLS1bits_t
;
24134 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
24136 #define _CLC2GLS1_LC2G2D1N 0x01
24137 #define _CLC2GLS1_D1N 0x01
24138 #define _CLC2GLS1_LC2G2D1T 0x02
24139 #define _CLC2GLS1_D1T 0x02
24140 #define _CLC2GLS1_LC2G2D2N 0x04
24141 #define _CLC2GLS1_D2N 0x04
24142 #define _CLC2GLS1_LC2G2D2T 0x08
24143 #define _CLC2GLS1_D2T 0x08
24144 #define _CLC2GLS1_LC2G2D3N 0x10
24145 #define _CLC2GLS1_D3N 0x10
24146 #define _CLC2GLS1_LC2G2D3T 0x20
24147 #define _CLC2GLS1_D3T 0x20
24148 #define _CLC2GLS1_LC2G2D4N 0x40
24149 #define _CLC2GLS1_D4N 0x40
24150 #define _CLC2GLS1_LC2G2D4T 0x80
24151 #define _CLC2GLS1_D4T 0x80
24153 //==============================================================================
24156 //==============================================================================
24159 extern __at(0x0F22) __sfr CLC2GLS2
;
24165 unsigned LC2G3D1N
: 1;
24166 unsigned LC2G3D1T
: 1;
24167 unsigned LC2G3D2N
: 1;
24168 unsigned LC2G3D2T
: 1;
24169 unsigned LC2G3D3N
: 1;
24170 unsigned LC2G3D3T
: 1;
24171 unsigned LC2G3D4N
: 1;
24172 unsigned LC2G3D4T
: 1;
24186 } __CLC2GLS2bits_t
;
24188 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
24190 #define _CLC2GLS2_LC2G3D1N 0x01
24191 #define _CLC2GLS2_D1N 0x01
24192 #define _CLC2GLS2_LC2G3D1T 0x02
24193 #define _CLC2GLS2_D1T 0x02
24194 #define _CLC2GLS2_LC2G3D2N 0x04
24195 #define _CLC2GLS2_D2N 0x04
24196 #define _CLC2GLS2_LC2G3D2T 0x08
24197 #define _CLC2GLS2_D2T 0x08
24198 #define _CLC2GLS2_LC2G3D3N 0x10
24199 #define _CLC2GLS2_D3N 0x10
24200 #define _CLC2GLS2_LC2G3D3T 0x20
24201 #define _CLC2GLS2_D3T 0x20
24202 #define _CLC2GLS2_LC2G3D4N 0x40
24203 #define _CLC2GLS2_D4N 0x40
24204 #define _CLC2GLS2_LC2G3D4T 0x80
24205 #define _CLC2GLS2_D4T 0x80
24207 //==============================================================================
24210 //==============================================================================
24213 extern __at(0x0F23) __sfr CLC2GLS3
;
24219 unsigned LC2G4D1N
: 1;
24220 unsigned LC2G4D1T
: 1;
24221 unsigned LC2G4D2N
: 1;
24222 unsigned LC2G4D2T
: 1;
24223 unsigned LC2G4D3N
: 1;
24224 unsigned LC2G4D3T
: 1;
24225 unsigned LC2G4D4N
: 1;
24226 unsigned LC2G4D4T
: 1;
24231 unsigned G4D1N
: 1;
24232 unsigned G4D1T
: 1;
24233 unsigned G4D2N
: 1;
24234 unsigned G4D2T
: 1;
24235 unsigned G4D3N
: 1;
24236 unsigned G4D3T
: 1;
24237 unsigned G4D4N
: 1;
24238 unsigned G4D4T
: 1;
24240 } __CLC2GLS3bits_t
;
24242 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
24244 #define _CLC2GLS3_LC2G4D1N 0x01
24245 #define _CLC2GLS3_G4D1N 0x01
24246 #define _CLC2GLS3_LC2G4D1T 0x02
24247 #define _CLC2GLS3_G4D1T 0x02
24248 #define _CLC2GLS3_LC2G4D2N 0x04
24249 #define _CLC2GLS3_G4D2N 0x04
24250 #define _CLC2GLS3_LC2G4D2T 0x08
24251 #define _CLC2GLS3_G4D2T 0x08
24252 #define _CLC2GLS3_LC2G4D3N 0x10
24253 #define _CLC2GLS3_G4D3N 0x10
24254 #define _CLC2GLS3_LC2G4D3T 0x20
24255 #define _CLC2GLS3_G4D3T 0x20
24256 #define _CLC2GLS3_LC2G4D4N 0x40
24257 #define _CLC2GLS3_G4D4N 0x40
24258 #define _CLC2GLS3_LC2G4D4T 0x80
24259 #define _CLC2GLS3_G4D4T 0x80
24261 //==============================================================================
24264 //==============================================================================
24267 extern __at(0x0F24) __sfr CLC3CON
;
24273 unsigned LC3MODE0
: 1;
24274 unsigned LC3MODE1
: 1;
24275 unsigned LC3MODE2
: 1;
24276 unsigned LC3INTN
: 1;
24277 unsigned LC3INTP
: 1;
24278 unsigned LC3OUT
: 1;
24280 unsigned LC3EN
: 1;
24285 unsigned MODE0
: 1;
24286 unsigned MODE1
: 1;
24287 unsigned MODE2
: 1;
24303 unsigned LC3MODE
: 3;
24308 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
24310 #define _CLC3CON_LC3MODE0 0x01
24311 #define _CLC3CON_MODE0 0x01
24312 #define _CLC3CON_LC3MODE1 0x02
24313 #define _CLC3CON_MODE1 0x02
24314 #define _CLC3CON_LC3MODE2 0x04
24315 #define _CLC3CON_MODE2 0x04
24316 #define _CLC3CON_LC3INTN 0x08
24317 #define _CLC3CON_INTN 0x08
24318 #define _CLC3CON_LC3INTP 0x10
24319 #define _CLC3CON_INTP 0x10
24320 #define _CLC3CON_LC3OUT 0x20
24321 #define _CLC3CON_OUT 0x20
24322 #define _CLC3CON_LC3EN 0x80
24323 #define _CLC3CON_EN 0x80
24325 //==============================================================================
24328 //==============================================================================
24331 extern __at(0x0F25) __sfr CLC3POL
;
24337 unsigned LC3G1POL
: 1;
24338 unsigned LC3G2POL
: 1;
24339 unsigned LC3G3POL
: 1;
24340 unsigned LC3G4POL
: 1;
24344 unsigned LC3POL
: 1;
24349 unsigned G1POL
: 1;
24350 unsigned G2POL
: 1;
24351 unsigned G3POL
: 1;
24352 unsigned G4POL
: 1;
24360 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
24362 #define _CLC3POL_LC3G1POL 0x01
24363 #define _CLC3POL_G1POL 0x01
24364 #define _CLC3POL_LC3G2POL 0x02
24365 #define _CLC3POL_G2POL 0x02
24366 #define _CLC3POL_LC3G3POL 0x04
24367 #define _CLC3POL_G3POL 0x04
24368 #define _CLC3POL_LC3G4POL 0x08
24369 #define _CLC3POL_G4POL 0x08
24370 #define _CLC3POL_LC3POL 0x80
24371 #define _CLC3POL_POL 0x80
24373 //==============================================================================
24376 //==============================================================================
24379 extern __at(0x0F26) __sfr CLC3SEL0
;
24385 unsigned LC3D1S0
: 1;
24386 unsigned LC3D1S1
: 1;
24387 unsigned LC3D1S2
: 1;
24388 unsigned LC3D1S3
: 1;
24389 unsigned LC3D1S4
: 1;
24390 unsigned LC3D1S5
: 1;
24409 unsigned LC3D1S
: 6;
24418 } __CLC3SEL0bits_t
;
24420 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
24422 #define _CLC3SEL0_LC3D1S0 0x01
24423 #define _CLC3SEL0_D1S0 0x01
24424 #define _CLC3SEL0_LC3D1S1 0x02
24425 #define _CLC3SEL0_D1S1 0x02
24426 #define _CLC3SEL0_LC3D1S2 0x04
24427 #define _CLC3SEL0_D1S2 0x04
24428 #define _CLC3SEL0_LC3D1S3 0x08
24429 #define _CLC3SEL0_D1S3 0x08
24430 #define _CLC3SEL0_LC3D1S4 0x10
24431 #define _CLC3SEL0_D1S4 0x10
24432 #define _CLC3SEL0_LC3D1S5 0x20
24433 #define _CLC3SEL0_D1S5 0x20
24435 //==============================================================================
24438 //==============================================================================
24441 extern __at(0x0F27) __sfr CLC3SEL1
;
24447 unsigned LC3D2S0
: 1;
24448 unsigned LC3D2S1
: 1;
24449 unsigned LC3D2S2
: 1;
24450 unsigned LC3D2S3
: 1;
24451 unsigned LC3D2S4
: 1;
24452 unsigned LC3D2S5
: 1;
24471 unsigned LC3D2S
: 6;
24480 } __CLC3SEL1bits_t
;
24482 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
24484 #define _CLC3SEL1_LC3D2S0 0x01
24485 #define _CLC3SEL1_D2S0 0x01
24486 #define _CLC3SEL1_LC3D2S1 0x02
24487 #define _CLC3SEL1_D2S1 0x02
24488 #define _CLC3SEL1_LC3D2S2 0x04
24489 #define _CLC3SEL1_D2S2 0x04
24490 #define _CLC3SEL1_LC3D2S3 0x08
24491 #define _CLC3SEL1_D2S3 0x08
24492 #define _CLC3SEL1_LC3D2S4 0x10
24493 #define _CLC3SEL1_D2S4 0x10
24494 #define _CLC3SEL1_LC3D2S5 0x20
24495 #define _CLC3SEL1_D2S5 0x20
24497 //==============================================================================
24500 //==============================================================================
24503 extern __at(0x0F28) __sfr CLC3SEL2
;
24509 unsigned LC3D3S0
: 1;
24510 unsigned LC3D3S1
: 1;
24511 unsigned LC3D3S2
: 1;
24512 unsigned LC3D3S3
: 1;
24513 unsigned LC3D3S4
: 1;
24514 unsigned LC3D3S5
: 1;
24533 unsigned LC3D3S
: 6;
24542 } __CLC3SEL2bits_t
;
24544 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
24546 #define _CLC3SEL2_LC3D3S0 0x01
24547 #define _CLC3SEL2_D3S0 0x01
24548 #define _CLC3SEL2_LC3D3S1 0x02
24549 #define _CLC3SEL2_D3S1 0x02
24550 #define _CLC3SEL2_LC3D3S2 0x04
24551 #define _CLC3SEL2_D3S2 0x04
24552 #define _CLC3SEL2_LC3D3S3 0x08
24553 #define _CLC3SEL2_D3S3 0x08
24554 #define _CLC3SEL2_LC3D3S4 0x10
24555 #define _CLC3SEL2_D3S4 0x10
24556 #define _CLC3SEL2_LC3D3S5 0x20
24557 #define _CLC3SEL2_D3S5 0x20
24559 //==============================================================================
24562 //==============================================================================
24565 extern __at(0x0F29) __sfr CLC3SEL3
;
24571 unsigned LC3D4S0
: 1;
24572 unsigned LC3D4S1
: 1;
24573 unsigned LC3D4S2
: 1;
24574 unsigned LC3D4S3
: 1;
24575 unsigned LC3D4S4
: 1;
24576 unsigned LC3D4S5
: 1;
24601 unsigned LC3D4S
: 6;
24604 } __CLC3SEL3bits_t
;
24606 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
24608 #define _CLC3SEL3_LC3D4S0 0x01
24609 #define _CLC3SEL3_D4S0 0x01
24610 #define _CLC3SEL3_LC3D4S1 0x02
24611 #define _CLC3SEL3_D4S1 0x02
24612 #define _CLC3SEL3_LC3D4S2 0x04
24613 #define _CLC3SEL3_D4S2 0x04
24614 #define _CLC3SEL3_LC3D4S3 0x08
24615 #define _CLC3SEL3_D4S3 0x08
24616 #define _CLC3SEL3_LC3D4S4 0x10
24617 #define _CLC3SEL3_D4S4 0x10
24618 #define _CLC3SEL3_LC3D4S5 0x20
24619 #define _CLC3SEL3_D4S5 0x20
24621 //==============================================================================
24624 //==============================================================================
24627 extern __at(0x0F2A) __sfr CLC3GLS0
;
24633 unsigned LC3G1D1N
: 1;
24634 unsigned LC3G1D1T
: 1;
24635 unsigned LC3G1D2N
: 1;
24636 unsigned LC3G1D2T
: 1;
24637 unsigned LC3G1D3N
: 1;
24638 unsigned LC3G1D3T
: 1;
24639 unsigned LC3G1D4N
: 1;
24640 unsigned LC3G1D4T
: 1;
24654 } __CLC3GLS0bits_t
;
24656 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
24658 #define _CLC3GLS0_LC3G1D1N 0x01
24659 #define _CLC3GLS0_D1N 0x01
24660 #define _CLC3GLS0_LC3G1D1T 0x02
24661 #define _CLC3GLS0_D1T 0x02
24662 #define _CLC3GLS0_LC3G1D2N 0x04
24663 #define _CLC3GLS0_D2N 0x04
24664 #define _CLC3GLS0_LC3G1D2T 0x08
24665 #define _CLC3GLS0_D2T 0x08
24666 #define _CLC3GLS0_LC3G1D3N 0x10
24667 #define _CLC3GLS0_D3N 0x10
24668 #define _CLC3GLS0_LC3G1D3T 0x20
24669 #define _CLC3GLS0_D3T 0x20
24670 #define _CLC3GLS0_LC3G1D4N 0x40
24671 #define _CLC3GLS0_D4N 0x40
24672 #define _CLC3GLS0_LC3G1D4T 0x80
24673 #define _CLC3GLS0_D4T 0x80
24675 //==============================================================================
24678 //==============================================================================
24681 extern __at(0x0F2B) __sfr CLC3GLS1
;
24687 unsigned LC3G2D1N
: 1;
24688 unsigned LC3G2D1T
: 1;
24689 unsigned LC3G2D2N
: 1;
24690 unsigned LC3G2D2T
: 1;
24691 unsigned LC3G2D3N
: 1;
24692 unsigned LC3G2D3T
: 1;
24693 unsigned LC3G2D4N
: 1;
24694 unsigned LC3G2D4T
: 1;
24708 } __CLC3GLS1bits_t
;
24710 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
24712 #define _CLC3GLS1_LC3G2D1N 0x01
24713 #define _CLC3GLS1_D1N 0x01
24714 #define _CLC3GLS1_LC3G2D1T 0x02
24715 #define _CLC3GLS1_D1T 0x02
24716 #define _CLC3GLS1_LC3G2D2N 0x04
24717 #define _CLC3GLS1_D2N 0x04
24718 #define _CLC3GLS1_LC3G2D2T 0x08
24719 #define _CLC3GLS1_D2T 0x08
24720 #define _CLC3GLS1_LC3G2D3N 0x10
24721 #define _CLC3GLS1_D3N 0x10
24722 #define _CLC3GLS1_LC3G2D3T 0x20
24723 #define _CLC3GLS1_D3T 0x20
24724 #define _CLC3GLS1_LC3G2D4N 0x40
24725 #define _CLC3GLS1_D4N 0x40
24726 #define _CLC3GLS1_LC3G2D4T 0x80
24727 #define _CLC3GLS1_D4T 0x80
24729 //==============================================================================
24732 //==============================================================================
24735 extern __at(0x0F2C) __sfr CLC3GLS2
;
24741 unsigned LC3G3D1N
: 1;
24742 unsigned LC3G3D1T
: 1;
24743 unsigned LC3G3D2N
: 1;
24744 unsigned LC3G3D2T
: 1;
24745 unsigned LC3G3D3N
: 1;
24746 unsigned LC3G3D3T
: 1;
24747 unsigned LC3G3D4N
: 1;
24748 unsigned LC3G3D4T
: 1;
24762 } __CLC3GLS2bits_t
;
24764 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
24766 #define _CLC3GLS2_LC3G3D1N 0x01
24767 #define _CLC3GLS2_D1N 0x01
24768 #define _CLC3GLS2_LC3G3D1T 0x02
24769 #define _CLC3GLS2_D1T 0x02
24770 #define _CLC3GLS2_LC3G3D2N 0x04
24771 #define _CLC3GLS2_D2N 0x04
24772 #define _CLC3GLS2_LC3G3D2T 0x08
24773 #define _CLC3GLS2_D2T 0x08
24774 #define _CLC3GLS2_LC3G3D3N 0x10
24775 #define _CLC3GLS2_D3N 0x10
24776 #define _CLC3GLS2_LC3G3D3T 0x20
24777 #define _CLC3GLS2_D3T 0x20
24778 #define _CLC3GLS2_LC3G3D4N 0x40
24779 #define _CLC3GLS2_D4N 0x40
24780 #define _CLC3GLS2_LC3G3D4T 0x80
24781 #define _CLC3GLS2_D4T 0x80
24783 //==============================================================================
24786 //==============================================================================
24789 extern __at(0x0F2D) __sfr CLC3GLS3
;
24795 unsigned LC3G4D1N
: 1;
24796 unsigned LC3G4D1T
: 1;
24797 unsigned LC3G4D2N
: 1;
24798 unsigned LC3G4D2T
: 1;
24799 unsigned LC3G4D3N
: 1;
24800 unsigned LC3G4D3T
: 1;
24801 unsigned LC3G4D4N
: 1;
24802 unsigned LC3G4D4T
: 1;
24807 unsigned G4D1N
: 1;
24808 unsigned G4D1T
: 1;
24809 unsigned G4D2N
: 1;
24810 unsigned G4D2T
: 1;
24811 unsigned G4D3N
: 1;
24812 unsigned G4D3T
: 1;
24813 unsigned G4D4N
: 1;
24814 unsigned G4D4T
: 1;
24816 } __CLC3GLS3bits_t
;
24818 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
24820 #define _CLC3GLS3_LC3G4D1N 0x01
24821 #define _CLC3GLS3_G4D1N 0x01
24822 #define _CLC3GLS3_LC3G4D1T 0x02
24823 #define _CLC3GLS3_G4D1T 0x02
24824 #define _CLC3GLS3_LC3G4D2N 0x04
24825 #define _CLC3GLS3_G4D2N 0x04
24826 #define _CLC3GLS3_LC3G4D2T 0x08
24827 #define _CLC3GLS3_G4D2T 0x08
24828 #define _CLC3GLS3_LC3G4D3N 0x10
24829 #define _CLC3GLS3_G4D3N 0x10
24830 #define _CLC3GLS3_LC3G4D3T 0x20
24831 #define _CLC3GLS3_G4D3T 0x20
24832 #define _CLC3GLS3_LC3G4D4N 0x40
24833 #define _CLC3GLS3_G4D4N 0x40
24834 #define _CLC3GLS3_LC3G4D4T 0x80
24835 #define _CLC3GLS3_G4D4T 0x80
24837 //==============================================================================
24840 //==============================================================================
24843 extern __at(0x0F2E) __sfr CLC4CON
;
24849 unsigned LC4MODE0
: 1;
24850 unsigned LC4MODE1
: 1;
24851 unsigned LC4MODE2
: 1;
24852 unsigned LC4INTN
: 1;
24853 unsigned LC4INTP
: 1;
24854 unsigned LC4OUT
: 1;
24856 unsigned LC4EN
: 1;
24861 unsigned MODE0
: 1;
24862 unsigned MODE1
: 1;
24863 unsigned MODE2
: 1;
24879 unsigned LC4MODE
: 3;
24884 extern __at(0x0F2E) volatile __CLC4CONbits_t CLC4CONbits
;
24886 #define _CLC4CON_LC4MODE0 0x01
24887 #define _CLC4CON_MODE0 0x01
24888 #define _CLC4CON_LC4MODE1 0x02
24889 #define _CLC4CON_MODE1 0x02
24890 #define _CLC4CON_LC4MODE2 0x04
24891 #define _CLC4CON_MODE2 0x04
24892 #define _CLC4CON_LC4INTN 0x08
24893 #define _CLC4CON_INTN 0x08
24894 #define _CLC4CON_LC4INTP 0x10
24895 #define _CLC4CON_INTP 0x10
24896 #define _CLC4CON_LC4OUT 0x20
24897 #define _CLC4CON_OUT 0x20
24898 #define _CLC4CON_LC4EN 0x80
24899 #define _CLC4CON_EN 0x80
24901 //==============================================================================
24904 //==============================================================================
24907 extern __at(0x0F2F) __sfr CLC4POL
;
24913 unsigned LC4G1POL
: 1;
24914 unsigned LC4G2POL
: 1;
24915 unsigned LC4G3POL
: 1;
24916 unsigned LC4G4POL
: 1;
24920 unsigned LC4POL
: 1;
24925 unsigned G1POL
: 1;
24926 unsigned G2POL
: 1;
24927 unsigned G3POL
: 1;
24928 unsigned G4POL
: 1;
24936 extern __at(0x0F2F) volatile __CLC4POLbits_t CLC4POLbits
;
24938 #define _CLC4POL_LC4G1POL 0x01
24939 #define _CLC4POL_G1POL 0x01
24940 #define _CLC4POL_LC4G2POL 0x02
24941 #define _CLC4POL_G2POL 0x02
24942 #define _CLC4POL_LC4G3POL 0x04
24943 #define _CLC4POL_G3POL 0x04
24944 #define _CLC4POL_LC4G4POL 0x08
24945 #define _CLC4POL_G4POL 0x08
24946 #define _CLC4POL_LC4POL 0x80
24947 #define _CLC4POL_POL 0x80
24949 //==============================================================================
24952 //==============================================================================
24955 extern __at(0x0F30) __sfr CLC4SEL0
;
24961 unsigned LC4D1S0
: 1;
24962 unsigned LC4D1S1
: 1;
24963 unsigned LC4D1S2
: 1;
24964 unsigned LC4D1S3
: 1;
24965 unsigned LC4D1S4
: 1;
24966 unsigned LC4D1S5
: 1;
24991 unsigned LC4D1S
: 6;
24994 } __CLC4SEL0bits_t
;
24996 extern __at(0x0F30) volatile __CLC4SEL0bits_t CLC4SEL0bits
;
24998 #define _CLC4SEL0_LC4D1S0 0x01
24999 #define _CLC4SEL0_D1S0 0x01
25000 #define _CLC4SEL0_LC4D1S1 0x02
25001 #define _CLC4SEL0_D1S1 0x02
25002 #define _CLC4SEL0_LC4D1S2 0x04
25003 #define _CLC4SEL0_D1S2 0x04
25004 #define _CLC4SEL0_LC4D1S3 0x08
25005 #define _CLC4SEL0_D1S3 0x08
25006 #define _CLC4SEL0_LC4D1S4 0x10
25007 #define _CLC4SEL0_D1S4 0x10
25008 #define _CLC4SEL0_LC4D1S5 0x20
25009 #define _CLC4SEL0_D1S5 0x20
25011 //==============================================================================
25014 //==============================================================================
25017 extern __at(0x0F31) __sfr CLC4SEL1
;
25023 unsigned LC4D2S0
: 1;
25024 unsigned LC4D2S1
: 1;
25025 unsigned LC4D2S2
: 1;
25026 unsigned LC4D2S3
: 1;
25027 unsigned LC4D2S4
: 1;
25028 unsigned LC4D2S5
: 1;
25053 unsigned LC4D2S
: 6;
25056 } __CLC4SEL1bits_t
;
25058 extern __at(0x0F31) volatile __CLC4SEL1bits_t CLC4SEL1bits
;
25060 #define _CLC4SEL1_LC4D2S0 0x01
25061 #define _CLC4SEL1_D2S0 0x01
25062 #define _CLC4SEL1_LC4D2S1 0x02
25063 #define _CLC4SEL1_D2S1 0x02
25064 #define _CLC4SEL1_LC4D2S2 0x04
25065 #define _CLC4SEL1_D2S2 0x04
25066 #define _CLC4SEL1_LC4D2S3 0x08
25067 #define _CLC4SEL1_D2S3 0x08
25068 #define _CLC4SEL1_LC4D2S4 0x10
25069 #define _CLC4SEL1_D2S4 0x10
25070 #define _CLC4SEL1_LC4D2S5 0x20
25071 #define _CLC4SEL1_D2S5 0x20
25073 //==============================================================================
25076 //==============================================================================
25079 extern __at(0x0F32) __sfr CLC4SEL2
;
25085 unsigned LC4D3S0
: 1;
25086 unsigned LC4D3S1
: 1;
25087 unsigned LC4D3S2
: 1;
25088 unsigned LC4D3S3
: 1;
25089 unsigned LC4D3S4
: 1;
25090 unsigned LC4D3S5
: 1;
25115 unsigned LC4D3S
: 6;
25118 } __CLC4SEL2bits_t
;
25120 extern __at(0x0F32) volatile __CLC4SEL2bits_t CLC4SEL2bits
;
25122 #define _CLC4SEL2_LC4D3S0 0x01
25123 #define _CLC4SEL2_D3S0 0x01
25124 #define _CLC4SEL2_LC4D3S1 0x02
25125 #define _CLC4SEL2_D3S1 0x02
25126 #define _CLC4SEL2_LC4D3S2 0x04
25127 #define _CLC4SEL2_D3S2 0x04
25128 #define _CLC4SEL2_LC4D3S3 0x08
25129 #define _CLC4SEL2_D3S3 0x08
25130 #define _CLC4SEL2_LC4D3S4 0x10
25131 #define _CLC4SEL2_D3S4 0x10
25132 #define _CLC4SEL2_LC4D3S5 0x20
25133 #define _CLC4SEL2_D3S5 0x20
25135 //==============================================================================
25138 //==============================================================================
25141 extern __at(0x0F33) __sfr CLC4SEL3
;
25147 unsigned LC4D4S0
: 1;
25148 unsigned LC4D4S1
: 1;
25149 unsigned LC4D4S2
: 1;
25150 unsigned LC4D4S3
: 1;
25151 unsigned LC4D4S4
: 1;
25152 unsigned LC4D4S5
: 1;
25171 unsigned LC4D4S
: 6;
25180 } __CLC4SEL3bits_t
;
25182 extern __at(0x0F33) volatile __CLC4SEL3bits_t CLC4SEL3bits
;
25184 #define _CLC4SEL3_LC4D4S0 0x01
25185 #define _CLC4SEL3_D4S0 0x01
25186 #define _CLC4SEL3_LC4D4S1 0x02
25187 #define _CLC4SEL3_D4S1 0x02
25188 #define _CLC4SEL3_LC4D4S2 0x04
25189 #define _CLC4SEL3_D4S2 0x04
25190 #define _CLC4SEL3_LC4D4S3 0x08
25191 #define _CLC4SEL3_D4S3 0x08
25192 #define _CLC4SEL3_LC4D4S4 0x10
25193 #define _CLC4SEL3_D4S4 0x10
25194 #define _CLC4SEL3_LC4D4S5 0x20
25195 #define _CLC4SEL3_D4S5 0x20
25197 //==============================================================================
25200 //==============================================================================
25203 extern __at(0x0F34) __sfr CLC4GLS0
;
25209 unsigned LC4G1D1N
: 1;
25210 unsigned LC4G1D1T
: 1;
25211 unsigned LC4G1D2N
: 1;
25212 unsigned LC4G1D2T
: 1;
25213 unsigned LC4G1D3N
: 1;
25214 unsigned LC4G1D3T
: 1;
25215 unsigned LC4G1D4N
: 1;
25216 unsigned LC4G1D4T
: 1;
25230 } __CLC4GLS0bits_t
;
25232 extern __at(0x0F34) volatile __CLC4GLS0bits_t CLC4GLS0bits
;
25234 #define _CLC4GLS0_LC4G1D1N 0x01
25235 #define _CLC4GLS0_D1N 0x01
25236 #define _CLC4GLS0_LC4G1D1T 0x02
25237 #define _CLC4GLS0_D1T 0x02
25238 #define _CLC4GLS0_LC4G1D2N 0x04
25239 #define _CLC4GLS0_D2N 0x04
25240 #define _CLC4GLS0_LC4G1D2T 0x08
25241 #define _CLC4GLS0_D2T 0x08
25242 #define _CLC4GLS0_LC4G1D3N 0x10
25243 #define _CLC4GLS0_D3N 0x10
25244 #define _CLC4GLS0_LC4G1D3T 0x20
25245 #define _CLC4GLS0_D3T 0x20
25246 #define _CLC4GLS0_LC4G1D4N 0x40
25247 #define _CLC4GLS0_D4N 0x40
25248 #define _CLC4GLS0_LC4G1D4T 0x80
25249 #define _CLC4GLS0_D4T 0x80
25251 //==============================================================================
25254 //==============================================================================
25257 extern __at(0x0F35) __sfr CLC4GLS1
;
25263 unsigned LC4G2D1N
: 1;
25264 unsigned LC4G2D1T
: 1;
25265 unsigned LC4G2D2N
: 1;
25266 unsigned LC4G2D2T
: 1;
25267 unsigned LC4G2D3N
: 1;
25268 unsigned LC4G2D3T
: 1;
25269 unsigned LC4G2D4N
: 1;
25270 unsigned LC4G2D4T
: 1;
25284 } __CLC4GLS1bits_t
;
25286 extern __at(0x0F35) volatile __CLC4GLS1bits_t CLC4GLS1bits
;
25288 #define _CLC4GLS1_LC4G2D1N 0x01
25289 #define _CLC4GLS1_D1N 0x01
25290 #define _CLC4GLS1_LC4G2D1T 0x02
25291 #define _CLC4GLS1_D1T 0x02
25292 #define _CLC4GLS1_LC4G2D2N 0x04
25293 #define _CLC4GLS1_D2N 0x04
25294 #define _CLC4GLS1_LC4G2D2T 0x08
25295 #define _CLC4GLS1_D2T 0x08
25296 #define _CLC4GLS1_LC4G2D3N 0x10
25297 #define _CLC4GLS1_D3N 0x10
25298 #define _CLC4GLS1_LC4G2D3T 0x20
25299 #define _CLC4GLS1_D3T 0x20
25300 #define _CLC4GLS1_LC4G2D4N 0x40
25301 #define _CLC4GLS1_D4N 0x40
25302 #define _CLC4GLS1_LC4G2D4T 0x80
25303 #define _CLC4GLS1_D4T 0x80
25305 //==============================================================================
25308 //==============================================================================
25311 extern __at(0x0F36) __sfr CLC4GLS2
;
25317 unsigned LC4G3D1N
: 1;
25318 unsigned LC4G3D1T
: 1;
25319 unsigned LC4G3D2N
: 1;
25320 unsigned LC4G3D2T
: 1;
25321 unsigned LC4G3D3N
: 1;
25322 unsigned LC4G3D3T
: 1;
25323 unsigned LC4G3D4N
: 1;
25324 unsigned LC4G3D4T
: 1;
25338 } __CLC4GLS2bits_t
;
25340 extern __at(0x0F36) volatile __CLC4GLS2bits_t CLC4GLS2bits
;
25342 #define _CLC4GLS2_LC4G3D1N 0x01
25343 #define _CLC4GLS2_D1N 0x01
25344 #define _CLC4GLS2_LC4G3D1T 0x02
25345 #define _CLC4GLS2_D1T 0x02
25346 #define _CLC4GLS2_LC4G3D2N 0x04
25347 #define _CLC4GLS2_D2N 0x04
25348 #define _CLC4GLS2_LC4G3D2T 0x08
25349 #define _CLC4GLS2_D2T 0x08
25350 #define _CLC4GLS2_LC4G3D3N 0x10
25351 #define _CLC4GLS2_D3N 0x10
25352 #define _CLC4GLS2_LC4G3D3T 0x20
25353 #define _CLC4GLS2_D3T 0x20
25354 #define _CLC4GLS2_LC4G3D4N 0x40
25355 #define _CLC4GLS2_D4N 0x40
25356 #define _CLC4GLS2_LC4G3D4T 0x80
25357 #define _CLC4GLS2_D4T 0x80
25359 //==============================================================================
25362 //==============================================================================
25365 extern __at(0x0F37) __sfr CLC4GLS3
;
25371 unsigned LC4G4D1N
: 1;
25372 unsigned LC4G4D1T
: 1;
25373 unsigned LC4G4D2N
: 1;
25374 unsigned LC4G4D2T
: 1;
25375 unsigned LC4G4D3N
: 1;
25376 unsigned LC4G4D3T
: 1;
25377 unsigned LC4G4D4N
: 1;
25378 unsigned LC4G4D4T
: 1;
25383 unsigned G4D1N
: 1;
25384 unsigned G4D1T
: 1;
25385 unsigned G4D2N
: 1;
25386 unsigned G4D2T
: 1;
25387 unsigned G4D3N
: 1;
25388 unsigned G4D3T
: 1;
25389 unsigned G4D4N
: 1;
25390 unsigned G4D4T
: 1;
25392 } __CLC4GLS3bits_t
;
25394 extern __at(0x0F37) volatile __CLC4GLS3bits_t CLC4GLS3bits
;
25396 #define _CLC4GLS3_LC4G4D1N 0x01
25397 #define _CLC4GLS3_G4D1N 0x01
25398 #define _CLC4GLS3_LC4G4D1T 0x02
25399 #define _CLC4GLS3_G4D1T 0x02
25400 #define _CLC4GLS3_LC4G4D2N 0x04
25401 #define _CLC4GLS3_G4D2N 0x04
25402 #define _CLC4GLS3_LC4G4D2T 0x08
25403 #define _CLC4GLS3_G4D2T 0x08
25404 #define _CLC4GLS3_LC4G4D3N 0x10
25405 #define _CLC4GLS3_G4D3N 0x10
25406 #define _CLC4GLS3_LC4G4D3T 0x20
25407 #define _CLC4GLS3_G4D3T 0x20
25408 #define _CLC4GLS3_LC4G4D4N 0x40
25409 #define _CLC4GLS3_G4D4N 0x40
25410 #define _CLC4GLS3_LC4G4D4T 0x80
25411 #define _CLC4GLS3_G4D4T 0x80
25413 //==============================================================================
25416 //==============================================================================
25417 // STATUS_SHAD Bits
25419 extern __at(0x0FE4) __sfr STATUS_SHAD
;
25423 unsigned C_SHAD
: 1;
25424 unsigned DC_SHAD
: 1;
25425 unsigned Z_SHAD
: 1;
25431 } __STATUS_SHADbits_t
;
25433 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
25435 #define _C_SHAD 0x01
25436 #define _DC_SHAD 0x02
25437 #define _Z_SHAD 0x04
25439 //==============================================================================
25441 extern __at(0x0FE5) __sfr WREG_SHAD
;
25442 extern __at(0x0FE6) __sfr BSR_SHAD
;
25443 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
25444 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
25445 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
25446 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
25447 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
25448 extern __at(0x0FED) __sfr STKPTR
;
25449 extern __at(0x0FEE) __sfr TOSL
;
25450 extern __at(0x0FEF) __sfr TOSH
;
25452 //==============================================================================
25454 // Configuration Bits
25456 //==============================================================================
25458 #define _CONFIG1 0x8007
25459 #define _CONFIG2 0x8008
25461 //----------------------------- CONFIG1 Options -------------------------------
25463 #define _FOSC_LP 0x3FF8 // LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins.
25464 #define _FOSC_XT 0x3FF9 // XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins.
25465 #define _FOSC_HS 0x3FFA // HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins.
25466 #define _FOSC_EXTRC 0x3FFB // EXTRC oscillator: External RC circuit connected to CLKIN pin.
25467 #define _FOSC_INTOSC 0x3FFC // INTOSC oscillator: I/O function on CLKIN pin.
25468 #define _FOSC_ECL 0x3FFD // ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pins.
25469 #define _FOSC_ECM 0x3FFE // ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pins.
25470 #define _FOSC_ECH 0x3FFF // ECH, External Clock, High Power Mode (4-20 MHz): device clock supplied to CLKIN pins.
25471 #define _WDTE_OFF 0x3FE7 // WDT disabled.
25472 #define _WDTE_SWDTEN 0x3FEF // WDT controlled by the SWDTEN bit in the WDTCON register.
25473 #define _WDTE_NSLEEP 0x3FF7 // WDT enabled while running and disabled in Sleep.
25474 #define _WDTE_ON 0x3FFF // WDT enabled.
25475 #define _PWRTE_ON 0x3FDF // PWRT enabled.
25476 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
25477 #define _MCLRE_OFF 0x3FBF // MCLR/VPP pin function is digital input.
25478 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR.
25479 #define _CP_ON 0x3F7F // Program memory code protection is enabled.
25480 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
25481 #define _BOREN_OFF 0x39FF // Brown-out Reset disabled.
25482 #define _BOREN_SBODEN 0x3BFF // Brown-out Reset controlled by the SBOREN bit in the BORCON register.
25483 #define _BOREN_NSLEEP 0x3DFF // Brown-out Reset enabled while running and disabled in Sleep.
25484 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled.
25485 #define _CLKOUTEN_ON 0x37FF // CLKOUT function is enabled on the CLKOUT pin.
25486 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
25487 #define _IESO_OFF 0x2FFF // Internal/External Switchover Mode is disabled.
25488 #define _IESO_ON 0x3FFF // Internal/External Switchover Mode is enabled.
25489 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
25490 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
25492 //----------------------------- CONFIG2 Options -------------------------------
25494 #define _WRT_ALL 0x3FFC // 000h to 1FFFh write protected, no addresses may be modified by EECON control.
25495 #define _WRT_HALF 0x3FFD // 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control.
25496 #define _WRT_BOOT 0x3FFE // 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control.
25497 #define _WRT_OFF 0x3FFF // Write protection off.
25498 #define _PPS1WAY_OFF 0x3FFB // The PPSLOCK bit can be set and cleared repeatedly by software.
25499 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit cannot be cleared once it is set by software.
25500 #define _ZCD_ON 0x3F7F // Zero-cross detect circuit is enabled at POR.
25501 #define _ZCD_OFF 0x3FFF // Zero-cross detect circuit is disabled at POR.
25502 #define _PLLEN_OFF 0x3EFF // 4x PLL is enabled when software sets the SPLLEN bit.
25503 #define _PLLEN_ON 0x3FFF // 4x PLL is always enabled.
25504 #define _STVREN_OFF 0x3DFF // Stack Overflow or Underflow will not cause a Reset.
25505 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
25506 #define _BORV_HI 0x3BFF // Brown-out Reset Voltage (Vbor), high trip point selected.
25507 #define _BORV_LO 0x3FFF // Brown-out Reset Voltage (Vbor), low trip point selected.
25508 #define _LPBOR_ON 0x37FF // Low-Power BOR is enabled.
25509 #define _LPBOR_OFF 0x3FFF // Low-Power BOR is disabled.
25510 #define _DEBUG_ON 0x2FFF // In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger.
25511 #define _DEBUG_OFF 0x3FFF // In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins.
25512 #define _LVP_OFF 0x1FFF // High-voltage on MCLR/VPP must be used for programming.
25513 #define _LVP_ON 0x3FFF // Low-voltage programming enabled.
25515 //==============================================================================
25517 #define _DEVID1 0x8006
25519 #define _IDLOC0 0x8000
25520 #define _IDLOC1 0x8001
25521 #define _IDLOC2 0x8002
25522 #define _IDLOC3 0x8003
25524 //==============================================================================
25526 #ifndef NO_BIT_DEFINES
25528 #define ADON ADCON0bits.ADON // bit 0
25529 #define GO ADCON0bits.GO // bit 1
25531 #define ADNREF ADCON1bits.ADNREF // bit 2
25532 #define ADFM ADCON1bits.ADFM // bit 7
25534 #define ANSA0 ANSELAbits.ANSA0 // bit 0
25535 #define ANSA1 ANSELAbits.ANSA1 // bit 1
25536 #define ANSA2 ANSELAbits.ANSA2 // bit 2
25537 #define ANSA3 ANSELAbits.ANSA3 // bit 3
25538 #define ANSA4 ANSELAbits.ANSA4 // bit 4
25539 #define ANSA5 ANSELAbits.ANSA5 // bit 5
25541 #define ANSB0 ANSELBbits.ANSB0 // bit 0
25542 #define ANSB1 ANSELBbits.ANSB1 // bit 1
25543 #define ANSB2 ANSELBbits.ANSB2 // bit 2
25544 #define ANSB3 ANSELBbits.ANSB3 // bit 3
25545 #define ANSB4 ANSELBbits.ANSB4 // bit 4
25546 #define ANSB5 ANSELBbits.ANSB5 // bit 5
25548 #define ANSC2 ANSELCbits.ANSC2 // bit 2
25549 #define ANSC3 ANSELCbits.ANSC3 // bit 3
25550 #define ANSC4 ANSELCbits.ANSC4 // bit 4
25551 #define ANSC5 ANSELCbits.ANSC5 // bit 5
25552 #define ANSC6 ANSELCbits.ANSC6 // bit 6
25553 #define ANSC7 ANSELCbits.ANSC7 // bit 7
25555 #define ANSD0 ANSELDbits.ANSD0 // bit 0
25556 #define ANSD1 ANSELDbits.ANSD1 // bit 1
25557 #define ANSD2 ANSELDbits.ANSD2 // bit 2
25558 #define ANSD3 ANSELDbits.ANSD3 // bit 3
25559 #define ANSD4 ANSELDbits.ANSD4 // bit 4
25560 #define ANSD5 ANSELDbits.ANSD5 // bit 5
25561 #define ANSD6 ANSELDbits.ANSD6 // bit 6
25562 #define ANSD7 ANSELDbits.ANSD7 // bit 7
25564 #define ANSE0 ANSELEbits.ANSE0 // bit 0
25565 #define ANSE1 ANSELEbits.ANSE1 // bit 1
25566 #define ANSE2 ANSELEbits.ANSE2 // bit 2
25568 #define ABDEN BAUD1CONbits.ABDEN // bit 0
25569 #define WUE BAUD1CONbits.WUE // bit 1
25570 #define BRG16 BAUD1CONbits.BRG16 // bit 3
25571 #define SCKP BAUD1CONbits.SCKP // bit 4
25572 #define RCIDL BAUD1CONbits.RCIDL // bit 6
25573 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
25575 #define BORRDY BORCONbits.BORRDY // bit 0
25576 #define BORFS BORCONbits.BORFS // bit 6
25577 #define SBOREN BORCONbits.SBOREN // bit 7
25579 #define BSR0 BSRbits.BSR0 // bit 0
25580 #define BSR1 BSRbits.BSR1 // bit 1
25581 #define BSR2 BSRbits.BSR2 // bit 2
25582 #define BSR3 BSRbits.BSR3 // bit 3
25583 #define BSR4 BSRbits.BSR4 // bit 4
25585 #define CTS0 CCP1CAPbits.CTS0 // bit 0, shadows bit in CCP1CAPbits
25586 #define CCP1CTS0 CCP1CAPbits.CCP1CTS0 // bit 0, shadows bit in CCP1CAPbits
25587 #define CTS1 CCP1CAPbits.CTS1 // bit 1, shadows bit in CCP1CAPbits
25588 #define CCP1CTS1 CCP1CAPbits.CCP1CTS1 // bit 1, shadows bit in CCP1CAPbits
25589 #define CTS2 CCP1CAPbits.CTS2 // bit 2, shadows bit in CCP1CAPbits
25590 #define CCP1CTS2 CCP1CAPbits.CCP1CTS2 // bit 2, shadows bit in CCP1CAPbits
25591 #define CTS3 CCP1CAPbits.CTS3 // bit 3, shadows bit in CCP1CAPbits
25592 #define CCP1CTS3 CCP1CAPbits.CCP1CTS3 // bit 3, shadows bit in CCP1CAPbits
25594 #define MODE0 CCP1CONbits.MODE0 // bit 0, shadows bit in CCP1CONbits
25595 #define CCP1MODE0 CCP1CONbits.CCP1MODE0 // bit 0, shadows bit in CCP1CONbits
25596 #define MODE1 CCP1CONbits.MODE1 // bit 1, shadows bit in CCP1CONbits
25597 #define CCP1MODE1 CCP1CONbits.CCP1MODE1 // bit 1, shadows bit in CCP1CONbits
25598 #define MODE2 CCP1CONbits.MODE2 // bit 2, shadows bit in CCP1CONbits
25599 #define CCP1MODE2 CCP1CONbits.CCP1MODE2 // bit 2, shadows bit in CCP1CONbits
25600 #define MODE3 CCP1CONbits.MODE3 // bit 3, shadows bit in CCP1CONbits
25601 #define CCP1MODE3 CCP1CONbits.CCP1MODE3 // bit 3, shadows bit in CCP1CONbits
25602 #define FMT CCP1CONbits.FMT // bit 4, shadows bit in CCP1CONbits
25603 #define CCP1FMT CCP1CONbits.CCP1FMT // bit 4, shadows bit in CCP1CONbits
25604 #define OUT CCP1CONbits.OUT // bit 5, shadows bit in CCP1CONbits
25605 #define CCP1OUT CCP1CONbits.CCP1OUT // bit 5, shadows bit in CCP1CONbits
25606 #define EN CCP1CONbits.EN // bit 7, shadows bit in CCP1CONbits
25607 #define CCP1EN CCP1CONbits.CCP1EN // bit 7, shadows bit in CCP1CONbits
25609 #define C1TSEL0 CCPTMRS1bits.C1TSEL0 // bit 0
25610 #define C1TSEL1 CCPTMRS1bits.C1TSEL1 // bit 1
25611 #define C2TSEL0 CCPTMRS1bits.C2TSEL0 // bit 2
25612 #define C2TSEL1 CCPTMRS1bits.C2TSEL1 // bit 3
25613 #define C7TSEL0 CCPTMRS1bits.C7TSEL0 // bit 4
25614 #define C7TSEL1 CCPTMRS1bits.C7TSEL1 // bit 5
25616 #define P3TSEL0 CCPTMRS2bits.P3TSEL0 // bit 0
25617 #define P3TSEL1 CCPTMRS2bits.P3TSEL1 // bit 1
25618 #define P4TSEL0 CCPTMRS2bits.P4TSEL0 // bit 2
25619 #define P4TSEL1 CCPTMRS2bits.P4TSEL1 // bit 3
25620 #define P9TSEL0 CCPTMRS2bits.P9TSEL0 // bit 4
25621 #define P9TSEL1 CCPTMRS2bits.P9TSEL1 // bit 5
25623 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
25624 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
25625 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
25626 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
25627 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
25628 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
25629 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
25630 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
25631 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
25632 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
25633 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
25634 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
25635 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
25636 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
25637 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
25638 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
25640 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
25641 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
25642 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
25643 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
25644 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
25645 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
25646 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
25647 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
25648 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
25649 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
25650 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
25651 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
25652 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
25653 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
25654 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
25655 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
25657 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
25658 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
25659 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
25660 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
25661 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
25662 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
25663 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
25664 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
25665 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
25666 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
25668 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
25669 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
25670 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
25671 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
25672 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
25673 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
25674 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
25675 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
25676 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
25677 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
25678 #define LC1D1S5 CLC1SEL0bits.LC1D1S5 // bit 5, shadows bit in CLC1SEL0bits
25679 #define D1S5 CLC1SEL0bits.D1S5 // bit 5, shadows bit in CLC1SEL0bits
25681 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
25682 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
25683 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
25684 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
25685 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
25686 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
25687 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
25688 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
25689 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
25690 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
25691 #define LC1D2S5 CLC1SEL1bits.LC1D2S5 // bit 5, shadows bit in CLC1SEL1bits
25692 #define D2S5 CLC1SEL1bits.D2S5 // bit 5, shadows bit in CLC1SEL1bits
25694 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
25695 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
25696 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
25697 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
25698 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
25699 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
25700 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
25701 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
25702 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
25703 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
25704 #define LC1D3S5 CLC1SEL2bits.LC1D3S5 // bit 5, shadows bit in CLC1SEL2bits
25705 #define D3S5 CLC1SEL2bits.D3S5 // bit 5, shadows bit in CLC1SEL2bits
25707 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
25708 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
25709 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
25710 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
25711 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
25712 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
25713 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
25714 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
25715 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
25716 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
25717 #define LC1D4S5 CLC1SEL3bits.LC1D4S5 // bit 5, shadows bit in CLC1SEL3bits
25718 #define D4S5 CLC1SEL3bits.D4S5 // bit 5, shadows bit in CLC1SEL3bits
25720 #define MCLC1OUT CLCDATAbits.MCLC1OUT // bit 0
25721 #define MCLC2OUT CLCDATAbits.MCLC2OUT // bit 1
25722 #define MCLC3OUT CLCDATAbits.MCLC3OUT // bit 2
25723 #define MLC4OUT CLCDATAbits.MLC4OUT // bit 3
25725 #define C1NCH0 CM1NSELbits.C1NCH0 // bit 0
25726 #define C1NCH1 CM1NSELbits.C1NCH1 // bit 1
25727 #define C1NCH2 CM1NSELbits.C1NCH2 // bit 2
25728 #define C1NCH3 CM1NSELbits.C1NCH3 // bit 3
25730 #define PCH0 CM1PSELbits.PCH0 // bit 0, shadows bit in CM1PSELbits
25731 #define C1PCH0 CM1PSELbits.C1PCH0 // bit 0, shadows bit in CM1PSELbits
25732 #define PCH1 CM1PSELbits.PCH1 // bit 1, shadows bit in CM1PSELbits
25733 #define C1PCH1 CM1PSELbits.C1PCH1 // bit 1, shadows bit in CM1PSELbits
25734 #define PCH2 CM1PSELbits.PCH2 // bit 2, shadows bit in CM1PSELbits
25735 #define C1PCH2 CM1PSELbits.C1PCH2 // bit 2, shadows bit in CM1PSELbits
25736 #define PCH3 CM1PSELbits.PCH3 // bit 3, shadows bit in CM1PSELbits
25737 #define C1PCH3 CM1PSELbits.C1PCH3 // bit 3, shadows bit in CM1PSELbits
25739 #define C2NCH0 CM2NSELbits.C2NCH0 // bit 0
25740 #define C2NCH1 CM2NSELbits.C2NCH1 // bit 1
25741 #define C2NCH2 CM2NSELbits.C2NCH2 // bit 2
25742 #define C2NCH3 CM2NSELbits.C2NCH3 // bit 3
25744 #define C3NCH0 CM3NSELbits.C3NCH0 // bit 0
25745 #define C3NCH1 CM3NSELbits.C3NCH1 // bit 1
25746 #define C3NCH2 CM3NSELbits.C3NCH2 // bit 2
25747 #define C3NCH3 CM3NSELbits.C3NCH3 // bit 3
25749 #define C4NCH0 CM4NSELbits.C4NCH0 // bit 0
25750 #define C4NCH1 CM4NSELbits.C4NCH1 // bit 1
25751 #define C4NCH2 CM4NSELbits.C4NCH2 // bit 2
25752 #define C4NCH3 CM4NSELbits.C4NCH3 // bit 3
25754 #define C5NCH0 CM5NSELbits.C5NCH0 // bit 0
25755 #define C5NCH1 CM5NSELbits.C5NCH1 // bit 1
25756 #define C5NCH2 CM5NSELbits.C5NCH2 // bit 2
25757 #define C5NCH3 CM5NSELbits.C5NCH3 // bit 3
25759 #define C6NCH0 CM6NSELbits.C6NCH0 // bit 0
25760 #define C6NCH1 CM6NSELbits.C6NCH1 // bit 1
25761 #define C6NCH2 CM6NSELbits.C6NCH2 // bit 2
25762 #define C6NCH3 CM6NSELbits.C6NCH3 // bit 3
25764 #define C7NCH0 CM7NSELbits.C7NCH0 // bit 0
25765 #define C7NCH1 CM7NSELbits.C7NCH1 // bit 1
25766 #define C7NCH2 CM7NSELbits.C7NCH2 // bit 2
25767 #define C7NCH3 CM7NSELbits.C7NCH3 // bit 3
25769 #define C8NCH0 CM8NSELbits.C8NCH0 // bit 0
25770 #define C8NCH1 CM8NSELbits.C8NCH1 // bit 1
25771 #define C8NCH2 CM8NSELbits.C8NCH2 // bit 2
25772 #define C8NCH3 CM8NSELbits.C8NCH3 // bit 3
25774 #define MC1OUT CMOUTbits.MC1OUT // bit 0
25775 #define MC2OUT CMOUTbits.MC2OUT // bit 1
25776 #define MC3OUT CMOUTbits.MC3OUT // bit 2
25777 #define MC4OUT CMOUTbits.MC4OUT // bit 3
25778 #define MC5OUT CMOUTbits.MC5OUT // bit 4
25779 #define MC6OUT CMOUTbits.MC6OUT // bit 5
25780 #define MC7OUT CMOUTbits.MC7OUT // bit 6
25781 #define MC80UT CMOUTbits.MC80UT // bit 7
25783 #define ASDAC0 COG1ASD0bits.ASDAC0 // bit 2, shadows bit in COG1ASD0bits
25784 #define G1ASDAC0 COG1ASD0bits.G1ASDAC0 // bit 2, shadows bit in COG1ASD0bits
25785 #define ASDAC1 COG1ASD0bits.ASDAC1 // bit 3, shadows bit in COG1ASD0bits
25786 #define G1ASDAC1 COG1ASD0bits.G1ASDAC1 // bit 3, shadows bit in COG1ASD0bits
25787 #define ASDBD0 COG1ASD0bits.ASDBD0 // bit 4, shadows bit in COG1ASD0bits
25788 #define G1ASDBD0 COG1ASD0bits.G1ASDBD0 // bit 4, shadows bit in COG1ASD0bits
25789 #define ASDBD1 COG1ASD0bits.ASDBD1 // bit 5, shadows bit in COG1ASD0bits
25790 #define G1ASDBD1 COG1ASD0bits.G1ASDBD1 // bit 5, shadows bit in COG1ASD0bits
25791 #define ASREN COG1ASD0bits.ASREN // bit 6, shadows bit in COG1ASD0bits
25792 #define ARSEN COG1ASD0bits.ARSEN // bit 6, shadows bit in COG1ASD0bits
25793 #define G1ARSEN COG1ASD0bits.G1ARSEN // bit 6, shadows bit in COG1ASD0bits
25794 #define G1ASREN COG1ASD0bits.G1ASREN // bit 6, shadows bit in COG1ASD0bits
25795 #define ASE COG1ASD0bits.ASE // bit 7, shadows bit in COG1ASD0bits
25796 #define G1ASE COG1ASD0bits.G1ASE // bit 7, shadows bit in COG1ASD0bits
25798 #define AS0E COG1ASD1bits.AS0E // bit 0, shadows bit in COG1ASD1bits
25799 #define G1AS0E COG1ASD1bits.G1AS0E // bit 0, shadows bit in COG1ASD1bits
25800 #define AS1E COG1ASD1bits.AS1E // bit 1, shadows bit in COG1ASD1bits
25801 #define G1AS1E COG1ASD1bits.G1AS1E // bit 1, shadows bit in COG1ASD1bits
25802 #define AS2E COG1ASD1bits.AS2E // bit 2, shadows bit in COG1ASD1bits
25803 #define G1AS2E COG1ASD1bits.G1AS2E // bit 2, shadows bit in COG1ASD1bits
25804 #define AS3E COG1ASD1bits.AS3E // bit 3, shadows bit in COG1ASD1bits
25805 #define G1AS3E COG1ASD1bits.G1AS3E // bit 3, shadows bit in COG1ASD1bits
25806 #define AS4E COG1ASD1bits.AS4E // bit 4, shadows bit in COG1ASD1bits
25807 #define G1AS4E COG1ASD1bits.G1AS4E // bit 4, shadows bit in COG1ASD1bits
25808 #define AS5E COG1ASD1bits.AS5E // bit 5, shadows bit in COG1ASD1bits
25809 #define G1AS5E COG1ASD1bits.G1AS5E // bit 5, shadows bit in COG1ASD1bits
25810 #define AS6E COG1ASD1bits.AS6E // bit 6, shadows bit in COG1ASD1bits
25811 #define G1AS6E COG1ASD1bits.G1AS6E // bit 6, shadows bit in COG1ASD1bits
25812 #define AS7E COG1ASD1bits.AS7E // bit 7, shadows bit in COG1ASD1bits
25813 #define G1AS7E COG1ASD1bits.G1AS7E // bit 7, shadows bit in COG1ASD1bits
25815 #define BLKF0 COG1BLKFbits.BLKF0 // bit 0, shadows bit in COG1BLKFbits
25816 #define G1BLKF0 COG1BLKFbits.G1BLKF0 // bit 0, shadows bit in COG1BLKFbits
25817 #define BLKF1 COG1BLKFbits.BLKF1 // bit 1, shadows bit in COG1BLKFbits
25818 #define G1BLKF1 COG1BLKFbits.G1BLKF1 // bit 1, shadows bit in COG1BLKFbits
25819 #define BLKF2 COG1BLKFbits.BLKF2 // bit 2, shadows bit in COG1BLKFbits
25820 #define G1BLKF2 COG1BLKFbits.G1BLKF2 // bit 2, shadows bit in COG1BLKFbits
25821 #define BLKF3 COG1BLKFbits.BLKF3 // bit 3, shadows bit in COG1BLKFbits
25822 #define G1BLKF3 COG1BLKFbits.G1BLKF3 // bit 3, shadows bit in COG1BLKFbits
25823 #define BLKF4 COG1BLKFbits.BLKF4 // bit 4, shadows bit in COG1BLKFbits
25824 #define G1BLKF4 COG1BLKFbits.G1BLKF4 // bit 4, shadows bit in COG1BLKFbits
25825 #define BLKF5 COG1BLKFbits.BLKF5 // bit 5, shadows bit in COG1BLKFbits
25826 #define G1BLKF5 COG1BLKFbits.G1BLKF5 // bit 5, shadows bit in COG1BLKFbits
25828 #define BLKR0 COG1BLKRbits.BLKR0 // bit 0, shadows bit in COG1BLKRbits
25829 #define G1BLKR0 COG1BLKRbits.G1BLKR0 // bit 0, shadows bit in COG1BLKRbits
25830 #define BLKR1 COG1BLKRbits.BLKR1 // bit 1, shadows bit in COG1BLKRbits
25831 #define G1BLKR1 COG1BLKRbits.G1BLKR1 // bit 1, shadows bit in COG1BLKRbits
25832 #define BLKR2 COG1BLKRbits.BLKR2 // bit 2, shadows bit in COG1BLKRbits
25833 #define G1BLKR2 COG1BLKRbits.G1BLKR2 // bit 2, shadows bit in COG1BLKRbits
25834 #define BLKR3 COG1BLKRbits.BLKR3 // bit 3, shadows bit in COG1BLKRbits
25835 #define G1BLKR3 COG1BLKRbits.G1BLKR3 // bit 3, shadows bit in COG1BLKRbits
25836 #define BLKR4 COG1BLKRbits.BLKR4 // bit 4, shadows bit in COG1BLKRbits
25837 #define G1BLKR4 COG1BLKRbits.G1BLKR4 // bit 4, shadows bit in COG1BLKRbits
25838 #define BLKR5 COG1BLKRbits.BLKR5 // bit 5, shadows bit in COG1BLKRbits
25839 #define G1BLKR5 COG1BLKRbits.G1BLKR5 // bit 5, shadows bit in COG1BLKRbits
25841 #define POLA COG1CON1bits.POLA // bit 0, shadows bit in COG1CON1bits
25842 #define G1POLA COG1CON1bits.G1POLA // bit 0, shadows bit in COG1CON1bits
25843 #define POLB COG1CON1bits.POLB // bit 1, shadows bit in COG1CON1bits
25844 #define G1POLB COG1CON1bits.G1POLB // bit 1, shadows bit in COG1CON1bits
25845 #define POLC COG1CON1bits.POLC // bit 2, shadows bit in COG1CON1bits
25846 #define G1POLC COG1CON1bits.G1POLC // bit 2, shadows bit in COG1CON1bits
25847 #define POLD COG1CON1bits.POLD // bit 3, shadows bit in COG1CON1bits
25848 #define G1POLD COG1CON1bits.G1POLD // bit 3, shadows bit in COG1CON1bits
25849 #define FDBS COG1CON1bits.FDBS // bit 6, shadows bit in COG1CON1bits
25850 #define G1FDBS COG1CON1bits.G1FDBS // bit 6, shadows bit in COG1CON1bits
25851 #define RDBS COG1CON1bits.RDBS // bit 7, shadows bit in COG1CON1bits
25852 #define G1RDBS COG1CON1bits.G1RDBS // bit 7, shadows bit in COG1CON1bits
25854 #define DBF0 COG1DBFbits.DBF0 // bit 0, shadows bit in COG1DBFbits
25855 #define G1DBF0 COG1DBFbits.G1DBF0 // bit 0, shadows bit in COG1DBFbits
25856 #define DBF1 COG1DBFbits.DBF1 // bit 1, shadows bit in COG1DBFbits
25857 #define G1DBF1 COG1DBFbits.G1DBF1 // bit 1, shadows bit in COG1DBFbits
25858 #define DBF2 COG1DBFbits.DBF2 // bit 2, shadows bit in COG1DBFbits
25859 #define G1DBF2 COG1DBFbits.G1DBF2 // bit 2, shadows bit in COG1DBFbits
25860 #define DBF3 COG1DBFbits.DBF3 // bit 3, shadows bit in COG1DBFbits
25861 #define G1DBF3 COG1DBFbits.G1DBF3 // bit 3, shadows bit in COG1DBFbits
25862 #define DBF4 COG1DBFbits.DBF4 // bit 4, shadows bit in COG1DBFbits
25863 #define G1DBF4 COG1DBFbits.G1DBF4 // bit 4, shadows bit in COG1DBFbits
25864 #define DBF5 COG1DBFbits.DBF5 // bit 5, shadows bit in COG1DBFbits
25865 #define G1DBF5 COG1DBFbits.G1DBF5 // bit 5, shadows bit in COG1DBFbits
25867 #define DBR0 COG1DBRbits.DBR0 // bit 0, shadows bit in COG1DBRbits
25868 #define G1DBR0 COG1DBRbits.G1DBR0 // bit 0, shadows bit in COG1DBRbits
25869 #define DBR1 COG1DBRbits.DBR1 // bit 1, shadows bit in COG1DBRbits
25870 #define G1DBR1 COG1DBRbits.G1DBR1 // bit 1, shadows bit in COG1DBRbits
25871 #define DBR2 COG1DBRbits.DBR2 // bit 2, shadows bit in COG1DBRbits
25872 #define G1DBR2 COG1DBRbits.G1DBR2 // bit 2, shadows bit in COG1DBRbits
25873 #define DBR3 COG1DBRbits.DBR3 // bit 3, shadows bit in COG1DBRbits
25874 #define G1DBR3 COG1DBRbits.G1DBR3 // bit 3, shadows bit in COG1DBRbits
25875 #define DBR4 COG1DBRbits.DBR4 // bit 4, shadows bit in COG1DBRbits
25876 #define G1DBR4 COG1DBRbits.G1DBR4 // bit 4, shadows bit in COG1DBRbits
25877 #define DBR5 COG1DBRbits.DBR5 // bit 5, shadows bit in COG1DBRbits
25878 #define G1DBR5 COG1DBRbits.G1DBR5 // bit 5, shadows bit in COG1DBRbits
25880 #define FIS0 COG1FIS0bits.FIS0 // bit 0, shadows bit in COG1FIS0bits
25881 #define G1FIS0 COG1FIS0bits.G1FIS0 // bit 0, shadows bit in COG1FIS0bits
25882 #define FIS1 COG1FIS0bits.FIS1 // bit 1, shadows bit in COG1FIS0bits
25883 #define G1FIS1 COG1FIS0bits.G1FIS1 // bit 1, shadows bit in COG1FIS0bits
25884 #define FIS2 COG1FIS0bits.FIS2 // bit 2, shadows bit in COG1FIS0bits
25885 #define G1FIS2 COG1FIS0bits.G1FIS2 // bit 2, shadows bit in COG1FIS0bits
25886 #define FIS3 COG1FIS0bits.FIS3 // bit 3, shadows bit in COG1FIS0bits
25887 #define G1FIS3 COG1FIS0bits.G1FIS3 // bit 3, shadows bit in COG1FIS0bits
25888 #define FIS4 COG1FIS0bits.FIS4 // bit 4, shadows bit in COG1FIS0bits
25889 #define G1FIS4 COG1FIS0bits.G1FIS4 // bit 4, shadows bit in COG1FIS0bits
25890 #define FIS5 COG1FIS0bits.FIS5 // bit 5, shadows bit in COG1FIS0bits
25891 #define G1FIS5 COG1FIS0bits.G1FIS5 // bit 5, shadows bit in COG1FIS0bits
25892 #define FIS6 COG1FIS0bits.FIS6 // bit 6, shadows bit in COG1FIS0bits
25893 #define G1FIS6 COG1FIS0bits.G1FIS6 // bit 6, shadows bit in COG1FIS0bits
25894 #define FIS7 COG1FIS0bits.FIS7 // bit 7, shadows bit in COG1FIS0bits
25895 #define G1FIS7 COG1FIS0bits.G1FIS7 // bit 7, shadows bit in COG1FIS0bits
25897 #define FIS8 COG1FIS1bits.FIS8 // bit 0, shadows bit in COG1FIS1bits
25898 #define G1FIS8 COG1FIS1bits.G1FIS8 // bit 0, shadows bit in COG1FIS1bits
25899 #define FIS9 COG1FIS1bits.FIS9 // bit 1, shadows bit in COG1FIS1bits
25900 #define G1FIS9 COG1FIS1bits.G1FIS9 // bit 1, shadows bit in COG1FIS1bits
25901 #define FIS10 COG1FIS1bits.FIS10 // bit 2, shadows bit in COG1FIS1bits
25902 #define G1FIS10 COG1FIS1bits.G1FIS10 // bit 2, shadows bit in COG1FIS1bits
25903 #define FIS11 COG1FIS1bits.FIS11 // bit 3, shadows bit in COG1FIS1bits
25904 #define G1FIS11 COG1FIS1bits.G1FIS11 // bit 3, shadows bit in COG1FIS1bits
25905 #define FIS12 COG1FIS1bits.FIS12 // bit 4, shadows bit in COG1FIS1bits
25906 #define G1FIS12 COG1FIS1bits.G1FIS12 // bit 4, shadows bit in COG1FIS1bits
25907 #define FIS13 COG1FIS1bits.FIS13 // bit 5, shadows bit in COG1FIS1bits
25908 #define G1FIS13 COG1FIS1bits.G1FIS13 // bit 5, shadows bit in COG1FIS1bits
25909 #define FIS14 COG1FIS1bits.FIS14 // bit 6, shadows bit in COG1FIS1bits
25910 #define G1FIS14 COG1FIS1bits.G1FIS14 // bit 6, shadows bit in COG1FIS1bits
25911 #define FIS15 COG1FIS1bits.FIS15 // bit 7, shadows bit in COG1FIS1bits
25912 #define G1FIS15 COG1FIS1bits.G1FIS15 // bit 7, shadows bit in COG1FIS1bits
25914 #define FSIM0 COG1FSIM0bits.FSIM0 // bit 0, shadows bit in COG1FSIM0bits
25915 #define G1FSIM0 COG1FSIM0bits.G1FSIM0 // bit 0, shadows bit in COG1FSIM0bits
25916 #define FSIM1 COG1FSIM0bits.FSIM1 // bit 1, shadows bit in COG1FSIM0bits
25917 #define G1FSIM1 COG1FSIM0bits.G1FSIM1 // bit 1, shadows bit in COG1FSIM0bits
25918 #define FSIM2 COG1FSIM0bits.FSIM2 // bit 2, shadows bit in COG1FSIM0bits
25919 #define G1FSIM2 COG1FSIM0bits.G1FSIM2 // bit 2, shadows bit in COG1FSIM0bits
25920 #define FSIM3 COG1FSIM0bits.FSIM3 // bit 3, shadows bit in COG1FSIM0bits
25921 #define G1FSIM3 COG1FSIM0bits.G1FSIM3 // bit 3, shadows bit in COG1FSIM0bits
25922 #define FSIM4 COG1FSIM0bits.FSIM4 // bit 4, shadows bit in COG1FSIM0bits
25923 #define G1FSIM4 COG1FSIM0bits.G1FSIM4 // bit 4, shadows bit in COG1FSIM0bits
25924 #define FSIM5 COG1FSIM0bits.FSIM5 // bit 5, shadows bit in COG1FSIM0bits
25925 #define G1FSIM5 COG1FSIM0bits.G1FSIM5 // bit 5, shadows bit in COG1FSIM0bits
25926 #define FSIM6 COG1FSIM0bits.FSIM6 // bit 6, shadows bit in COG1FSIM0bits
25927 #define G1FSIM6 COG1FSIM0bits.G1FSIM6 // bit 6, shadows bit in COG1FSIM0bits
25928 #define FSIM7 COG1FSIM0bits.FSIM7 // bit 7, shadows bit in COG1FSIM0bits
25929 #define G1FSIM7 COG1FSIM0bits.G1FSIM7 // bit 7, shadows bit in COG1FSIM0bits
25931 #define FSIM8 COG1FSIM1bits.FSIM8 // bit 0, shadows bit in COG1FSIM1bits
25932 #define G1FSIM8 COG1FSIM1bits.G1FSIM8 // bit 0, shadows bit in COG1FSIM1bits
25933 #define FSIM9 COG1FSIM1bits.FSIM9 // bit 1, shadows bit in COG1FSIM1bits
25934 #define G1FSIM9 COG1FSIM1bits.G1FSIM9 // bit 1, shadows bit in COG1FSIM1bits
25935 #define FSIM10 COG1FSIM1bits.FSIM10 // bit 2, shadows bit in COG1FSIM1bits
25936 #define G1FSIM10 COG1FSIM1bits.G1FSIM10 // bit 2, shadows bit in COG1FSIM1bits
25937 #define FSIM11 COG1FSIM1bits.FSIM11 // bit 3, shadows bit in COG1FSIM1bits
25938 #define G1FSIM11 COG1FSIM1bits.G1FSIM11 // bit 3, shadows bit in COG1FSIM1bits
25939 #define FSIM12 COG1FSIM1bits.FSIM12 // bit 4, shadows bit in COG1FSIM1bits
25940 #define G1FSIM12 COG1FSIM1bits.G1FSIM12 // bit 4, shadows bit in COG1FSIM1bits
25941 #define FSIM13 COG1FSIM1bits.FSIM13 // bit 5, shadows bit in COG1FSIM1bits
25942 #define G1FSIM13 COG1FSIM1bits.G1FSIM13 // bit 5, shadows bit in COG1FSIM1bits
25943 #define FSIM14 COG1FSIM1bits.FSIM14 // bit 6, shadows bit in COG1FSIM1bits
25944 #define G1FSIM14 COG1FSIM1bits.G1FSIM14 // bit 6, shadows bit in COG1FSIM1bits
25945 #define FSIM15 COG1FSIM1bits.FSIM15 // bit 7, shadows bit in COG1FSIM1bits
25946 #define G1FSIM15 COG1FSIM1bits.G1FSIM15 // bit 7, shadows bit in COG1FSIM1bits
25948 #define PHF0 COG1PHFbits.PHF0 // bit 0, shadows bit in COG1PHFbits
25949 #define G1PHF0 COG1PHFbits.G1PHF0 // bit 0, shadows bit in COG1PHFbits
25950 #define PHF1 COG1PHFbits.PHF1 // bit 1, shadows bit in COG1PHFbits
25951 #define G1PHF1 COG1PHFbits.G1PHF1 // bit 1, shadows bit in COG1PHFbits
25952 #define PHF2 COG1PHFbits.PHF2 // bit 2, shadows bit in COG1PHFbits
25953 #define G1PHF2 COG1PHFbits.G1PHF2 // bit 2, shadows bit in COG1PHFbits
25954 #define PHF3 COG1PHFbits.PHF3 // bit 3, shadows bit in COG1PHFbits
25955 #define G1PHF3 COG1PHFbits.G1PHF3 // bit 3, shadows bit in COG1PHFbits
25956 #define PHF4 COG1PHFbits.PHF4 // bit 4, shadows bit in COG1PHFbits
25957 #define G1PHF4 COG1PHFbits.G1PHF4 // bit 4, shadows bit in COG1PHFbits
25958 #define PHF5 COG1PHFbits.PHF5 // bit 5, shadows bit in COG1PHFbits
25959 #define G1PHF5 COG1PHFbits.G1PHF5 // bit 5, shadows bit in COG1PHFbits
25961 #define PHR0 COG1PHRbits.PHR0 // bit 0, shadows bit in COG1PHRbits
25962 #define G1PHR0 COG1PHRbits.G1PHR0 // bit 0, shadows bit in COG1PHRbits
25963 #define PHR1 COG1PHRbits.PHR1 // bit 1, shadows bit in COG1PHRbits
25964 #define G1PHR1 COG1PHRbits.G1PHR1 // bit 1, shadows bit in COG1PHRbits
25965 #define PHR2 COG1PHRbits.PHR2 // bit 2, shadows bit in COG1PHRbits
25966 #define G1PHR2 COG1PHRbits.G1PHR2 // bit 2, shadows bit in COG1PHRbits
25967 #define PHR3 COG1PHRbits.PHR3 // bit 3, shadows bit in COG1PHRbits
25968 #define G1PHR3 COG1PHRbits.G1PHR3 // bit 3, shadows bit in COG1PHRbits
25969 #define PHR4 COG1PHRbits.PHR4 // bit 4, shadows bit in COG1PHRbits
25970 #define G1PHR4 COG1PHRbits.G1PHR4 // bit 4, shadows bit in COG1PHRbits
25971 #define PHR5 COG1PHRbits.PHR5 // bit 5, shadows bit in COG1PHRbits
25972 #define G1PHR5 COG1PHRbits.G1PHR5 // bit 5, shadows bit in COG1PHRbits
25974 #define RIS0 COG1RIS0bits.RIS0 // bit 0, shadows bit in COG1RIS0bits
25975 #define G1RIS0 COG1RIS0bits.G1RIS0 // bit 0, shadows bit in COG1RIS0bits
25976 #define RIS1 COG1RIS0bits.RIS1 // bit 1, shadows bit in COG1RIS0bits
25977 #define G1RIS1 COG1RIS0bits.G1RIS1 // bit 1, shadows bit in COG1RIS0bits
25978 #define RIS2 COG1RIS0bits.RIS2 // bit 2, shadows bit in COG1RIS0bits
25979 #define G1RIS2 COG1RIS0bits.G1RIS2 // bit 2, shadows bit in COG1RIS0bits
25980 #define RIS3 COG1RIS0bits.RIS3 // bit 3, shadows bit in COG1RIS0bits
25981 #define G1RIS3 COG1RIS0bits.G1RIS3 // bit 3, shadows bit in COG1RIS0bits
25982 #define RIS4 COG1RIS0bits.RIS4 // bit 4, shadows bit in COG1RIS0bits
25983 #define G1RIS4 COG1RIS0bits.G1RIS4 // bit 4, shadows bit in COG1RIS0bits
25984 #define RIS5 COG1RIS0bits.RIS5 // bit 5, shadows bit in COG1RIS0bits
25985 #define G1RIS5 COG1RIS0bits.G1RIS5 // bit 5, shadows bit in COG1RIS0bits
25986 #define RIS6 COG1RIS0bits.RIS6 // bit 6, shadows bit in COG1RIS0bits
25987 #define G1RIS6 COG1RIS0bits.G1RIS6 // bit 6, shadows bit in COG1RIS0bits
25988 #define RIS7 COG1RIS0bits.RIS7 // bit 7, shadows bit in COG1RIS0bits
25989 #define G1RIS7 COG1RIS0bits.G1RIS7 // bit 7, shadows bit in COG1RIS0bits
25991 #define RIS8 COG1RIS1bits.RIS8 // bit 0, shadows bit in COG1RIS1bits
25992 #define G1RIS8 COG1RIS1bits.G1RIS8 // bit 0, shadows bit in COG1RIS1bits
25993 #define RIS9 COG1RIS1bits.RIS9 // bit 1, shadows bit in COG1RIS1bits
25994 #define G1RIS9 COG1RIS1bits.G1RIS9 // bit 1, shadows bit in COG1RIS1bits
25995 #define RIS10 COG1RIS1bits.RIS10 // bit 2, shadows bit in COG1RIS1bits
25996 #define G1RIS10 COG1RIS1bits.G1RIS10 // bit 2, shadows bit in COG1RIS1bits
25997 #define RIS11 COG1RIS1bits.RIS11 // bit 3, shadows bit in COG1RIS1bits
25998 #define G1RIS11 COG1RIS1bits.G1RIS11 // bit 3, shadows bit in COG1RIS1bits
25999 #define RIS12 COG1RIS1bits.RIS12 // bit 4, shadows bit in COG1RIS1bits
26000 #define G1RIS12 COG1RIS1bits.G1RIS12 // bit 4, shadows bit in COG1RIS1bits
26001 #define RIS13 COG1RIS1bits.RIS13 // bit 5, shadows bit in COG1RIS1bits
26002 #define G1RIS13 COG1RIS1bits.G1RIS13 // bit 5, shadows bit in COG1RIS1bits
26003 #define RIS14 COG1RIS1bits.RIS14 // bit 6, shadows bit in COG1RIS1bits
26004 #define G1RIS14 COG1RIS1bits.G1RIS14 // bit 6, shadows bit in COG1RIS1bits
26005 #define RIS15 COG1RIS1bits.RIS15 // bit 7, shadows bit in COG1RIS1bits
26006 #define G1RIS15 COG1RIS1bits.G1RIS15 // bit 7, shadows bit in COG1RIS1bits
26008 #define RSIM0 COG1RSIM0bits.RSIM0 // bit 0, shadows bit in COG1RSIM0bits
26009 #define G1RSIM0 COG1RSIM0bits.G1RSIM0 // bit 0, shadows bit in COG1RSIM0bits
26010 #define RSIM1 COG1RSIM0bits.RSIM1 // bit 1, shadows bit in COG1RSIM0bits
26011 #define G1RSIM1 COG1RSIM0bits.G1RSIM1 // bit 1, shadows bit in COG1RSIM0bits
26012 #define RSIM2 COG1RSIM0bits.RSIM2 // bit 2, shadows bit in COG1RSIM0bits
26013 #define G1RSIM2 COG1RSIM0bits.G1RSIM2 // bit 2, shadows bit in COG1RSIM0bits
26014 #define RSIM3 COG1RSIM0bits.RSIM3 // bit 3, shadows bit in COG1RSIM0bits
26015 #define G1RSIM3 COG1RSIM0bits.G1RSIM3 // bit 3, shadows bit in COG1RSIM0bits
26016 #define RSIM4 COG1RSIM0bits.RSIM4 // bit 4, shadows bit in COG1RSIM0bits
26017 #define G1RSIM4 COG1RSIM0bits.G1RSIM4 // bit 4, shadows bit in COG1RSIM0bits
26018 #define RSIM5 COG1RSIM0bits.RSIM5 // bit 5, shadows bit in COG1RSIM0bits
26019 #define G1RSIM5 COG1RSIM0bits.G1RSIM5 // bit 5, shadows bit in COG1RSIM0bits
26020 #define RSIM6 COG1RSIM0bits.RSIM6 // bit 6, shadows bit in COG1RSIM0bits
26021 #define G1RSIM6 COG1RSIM0bits.G1RSIM6 // bit 6, shadows bit in COG1RSIM0bits
26022 #define RSIM7 COG1RSIM0bits.RSIM7 // bit 7, shadows bit in COG1RSIM0bits
26023 #define G1RSIM7 COG1RSIM0bits.G1RSIM7 // bit 7, shadows bit in COG1RSIM0bits
26025 #define RSIM8 COG1RSIM1bits.RSIM8 // bit 0, shadows bit in COG1RSIM1bits
26026 #define G1RSIM8 COG1RSIM1bits.G1RSIM8 // bit 0, shadows bit in COG1RSIM1bits
26027 #define RSIM9 COG1RSIM1bits.RSIM9 // bit 1, shadows bit in COG1RSIM1bits
26028 #define G1RSIM9 COG1RSIM1bits.G1RSIM9 // bit 1, shadows bit in COG1RSIM1bits
26029 #define RSIM10 COG1RSIM1bits.RSIM10 // bit 2, shadows bit in COG1RSIM1bits
26030 #define G1RSIM10 COG1RSIM1bits.G1RSIM10 // bit 2, shadows bit in COG1RSIM1bits
26031 #define RSIM11 COG1RSIM1bits.RSIM11 // bit 3, shadows bit in COG1RSIM1bits
26032 #define G1RSIM11 COG1RSIM1bits.G1RSIM11 // bit 3, shadows bit in COG1RSIM1bits
26033 #define RSIM12 COG1RSIM1bits.RSIM12 // bit 4, shadows bit in COG1RSIM1bits
26034 #define G1RSIM12 COG1RSIM1bits.G1RSIM12 // bit 4, shadows bit in COG1RSIM1bits
26035 #define RSIM13 COG1RSIM1bits.RSIM13 // bit 5, shadows bit in COG1RSIM1bits
26036 #define G1RSIM13 COG1RSIM1bits.G1RSIM13 // bit 5, shadows bit in COG1RSIM1bits
26037 #define RSIM14 COG1RSIM1bits.RSIM14 // bit 6, shadows bit in COG1RSIM1bits
26038 #define G1RSIM14 COG1RSIM1bits.G1RSIM14 // bit 6, shadows bit in COG1RSIM1bits
26039 #define RSIM15 COG1RSIM1bits.RSIM15 // bit 7, shadows bit in COG1RSIM1bits
26040 #define G1RSIM15 COG1RSIM1bits.G1RSIM15 // bit 7, shadows bit in COG1RSIM1bits
26042 #define STRA COG1STRbits.STRA // bit 0, shadows bit in COG1STRbits
26043 #define G1STRA COG1STRbits.G1STRA // bit 0, shadows bit in COG1STRbits
26044 #define STRB COG1STRbits.STRB // bit 1, shadows bit in COG1STRbits
26045 #define G1STRB COG1STRbits.G1STRB // bit 1, shadows bit in COG1STRbits
26046 #define STRC COG1STRbits.STRC // bit 2, shadows bit in COG1STRbits
26047 #define G1STRC COG1STRbits.G1STRC // bit 2, shadows bit in COG1STRbits
26048 #define STRD COG1STRbits.STRD // bit 3, shadows bit in COG1STRbits
26049 #define G1STRD COG1STRbits.G1STRD // bit 3, shadows bit in COG1STRbits
26050 #define SDATA COG1STRbits.SDATA // bit 4, shadows bit in COG1STRbits
26051 #define G1SDATA COG1STRbits.G1SDATA // bit 4, shadows bit in COG1STRbits
26052 #define SDATB COG1STRbits.SDATB // bit 5, shadows bit in COG1STRbits
26053 #define G1SDATB COG1STRbits.G1SDATB // bit 5, shadows bit in COG1STRbits
26054 #define SDATC COG1STRbits.SDATC // bit 6, shadows bit in COG1STRbits
26055 #define G1SDATC COG1STRbits.G1SDATC // bit 6, shadows bit in COG1STRbits
26056 #define SDATD COG1STRbits.SDATD // bit 7, shadows bit in COG1STRbits
26057 #define G1SDATD COG1STRbits.G1SDATD // bit 7, shadows bit in COG1STRbits
26059 #define REF0 DAC1CON1bits.REF0 // bit 0, shadows bit in DAC1CON1bits
26060 #define DAC1REF0 DAC1CON1bits.DAC1REF0 // bit 0, shadows bit in DAC1CON1bits
26061 #define R0 DAC1CON1bits.R0 // bit 0, shadows bit in DAC1CON1bits
26062 #define DAC1R0 DAC1CON1bits.DAC1R0 // bit 0, shadows bit in DAC1CON1bits
26063 #define REF1 DAC1CON1bits.REF1 // bit 1, shadows bit in DAC1CON1bits
26064 #define DAC1REF1 DAC1CON1bits.DAC1REF1 // bit 1, shadows bit in DAC1CON1bits
26065 #define R1 DAC1CON1bits.R1 // bit 1, shadows bit in DAC1CON1bits
26066 #define DAC1R1 DAC1CON1bits.DAC1R1 // bit 1, shadows bit in DAC1CON1bits
26067 #define REF2 DAC1CON1bits.REF2 // bit 2, shadows bit in DAC1CON1bits
26068 #define DAC1REF2 DAC1CON1bits.DAC1REF2 // bit 2, shadows bit in DAC1CON1bits
26069 #define R2 DAC1CON1bits.R2 // bit 2, shadows bit in DAC1CON1bits
26070 #define DAC1R2 DAC1CON1bits.DAC1R2 // bit 2, shadows bit in DAC1CON1bits
26071 #define REF3 DAC1CON1bits.REF3 // bit 3, shadows bit in DAC1CON1bits
26072 #define DAC1REF3 DAC1CON1bits.DAC1REF3 // bit 3, shadows bit in DAC1CON1bits
26073 #define R3 DAC1CON1bits.R3 // bit 3, shadows bit in DAC1CON1bits
26074 #define DAC1R3 DAC1CON1bits.DAC1R3 // bit 3, shadows bit in DAC1CON1bits
26075 #define REF4 DAC1CON1bits.REF4 // bit 4, shadows bit in DAC1CON1bits
26076 #define DAC1REF4 DAC1CON1bits.DAC1REF4 // bit 4, shadows bit in DAC1CON1bits
26077 #define R4 DAC1CON1bits.R4 // bit 4, shadows bit in DAC1CON1bits
26078 #define DAC1R4 DAC1CON1bits.DAC1R4 // bit 4, shadows bit in DAC1CON1bits
26079 #define REF5 DAC1CON1bits.REF5 // bit 5, shadows bit in DAC1CON1bits
26080 #define DAC1REF5 DAC1CON1bits.DAC1REF5 // bit 5, shadows bit in DAC1CON1bits
26081 #define R5 DAC1CON1bits.R5 // bit 5, shadows bit in DAC1CON1bits
26082 #define DAC1R5 DAC1CON1bits.DAC1R5 // bit 5, shadows bit in DAC1CON1bits
26083 #define REF6 DAC1CON1bits.REF6 // bit 6, shadows bit in DAC1CON1bits
26084 #define DAC1REF6 DAC1CON1bits.DAC1REF6 // bit 6, shadows bit in DAC1CON1bits
26085 #define R6 DAC1CON1bits.R6 // bit 6, shadows bit in DAC1CON1bits
26086 #define DAC1R6 DAC1CON1bits.DAC1R6 // bit 6, shadows bit in DAC1CON1bits
26087 #define REF7 DAC1CON1bits.REF7 // bit 7, shadows bit in DAC1CON1bits
26088 #define DAC1REF7 DAC1CON1bits.DAC1REF7 // bit 7, shadows bit in DAC1CON1bits
26089 #define R7 DAC1CON1bits.R7 // bit 7, shadows bit in DAC1CON1bits
26090 #define DAC1R7 DAC1CON1bits.DAC1R7 // bit 7, shadows bit in DAC1CON1bits
26092 #define REF8 DAC1CON2bits.REF8 // bit 0, shadows bit in DAC1CON2bits
26093 #define DAC1REF8 DAC1CON2bits.DAC1REF8 // bit 0, shadows bit in DAC1CON2bits
26094 #define R8 DAC1CON2bits.R8 // bit 0, shadows bit in DAC1CON2bits
26095 #define DAC1R8 DAC1CON2bits.DAC1R8 // bit 0, shadows bit in DAC1CON2bits
26096 #define REF9 DAC1CON2bits.REF9 // bit 1, shadows bit in DAC1CON2bits
26097 #define DAC1REF9 DAC1CON2bits.DAC1REF9 // bit 1, shadows bit in DAC1CON2bits
26098 #define R9 DAC1CON2bits.R9 // bit 1, shadows bit in DAC1CON2bits
26099 #define DAC1R9 DAC1CON2bits.DAC1R9 // bit 1, shadows bit in DAC1CON2bits
26100 #define REF10 DAC1CON2bits.REF10 // bit 2, shadows bit in DAC1CON2bits
26101 #define DAC1REF10 DAC1CON2bits.DAC1REF10 // bit 2, shadows bit in DAC1CON2bits
26102 #define R10 DAC1CON2bits.R10 // bit 2, shadows bit in DAC1CON2bits
26103 #define DAC1R10 DAC1CON2bits.DAC1R10 // bit 2, shadows bit in DAC1CON2bits
26104 #define REF11 DAC1CON2bits.REF11 // bit 3, shadows bit in DAC1CON2bits
26105 #define DAC1REF11 DAC1CON2bits.DAC1REF11 // bit 3, shadows bit in DAC1CON2bits
26106 #define R11 DAC1CON2bits.R11 // bit 3, shadows bit in DAC1CON2bits
26107 #define DAC1R11 DAC1CON2bits.DAC1R11 // bit 3, shadows bit in DAC1CON2bits
26108 #define REF12 DAC1CON2bits.REF12 // bit 4, shadows bit in DAC1CON2bits
26109 #define DAC1REF12 DAC1CON2bits.DAC1REF12 // bit 4, shadows bit in DAC1CON2bits
26110 #define R12 DAC1CON2bits.R12 // bit 4, shadows bit in DAC1CON2bits
26111 #define DAC1R12 DAC1CON2bits.DAC1R12 // bit 4, shadows bit in DAC1CON2bits
26112 #define REF13 DAC1CON2bits.REF13 // bit 5, shadows bit in DAC1CON2bits
26113 #define DAC1REF13 DAC1CON2bits.DAC1REF13 // bit 5, shadows bit in DAC1CON2bits
26114 #define R13 DAC1CON2bits.R13 // bit 5, shadows bit in DAC1CON2bits
26115 #define DAC1R13 DAC1CON2bits.DAC1R13 // bit 5, shadows bit in DAC1CON2bits
26116 #define REF14 DAC1CON2bits.REF14 // bit 6, shadows bit in DAC1CON2bits
26117 #define DAC1REF14 DAC1CON2bits.DAC1REF14 // bit 6, shadows bit in DAC1CON2bits
26118 #define R14 DAC1CON2bits.R14 // bit 6, shadows bit in DAC1CON2bits
26119 #define DAC1R14 DAC1CON2bits.DAC1R14 // bit 6, shadows bit in DAC1CON2bits
26120 #define REF15 DAC1CON2bits.REF15 // bit 7, shadows bit in DAC1CON2bits
26121 #define DAC1REF15 DAC1CON2bits.DAC1REF15 // bit 7, shadows bit in DAC1CON2bits
26122 #define R15 DAC1CON2bits.R15 // bit 7, shadows bit in DAC1CON2bits
26123 #define DAC1R15 DAC1CON2bits.DAC1R15 // bit 7, shadows bit in DAC1CON2bits
26125 #define DAC1LD DACLDbits.DAC1LD // bit 0
26126 #define DAC2LD DACLDbits.DAC2LD // bit 1
26127 #define DAC5LD DACLDbits.DAC5LD // bit 4
26128 #define DAC6LD DACLDbits.DAC6LD // bit 5
26130 #define TSRNG FVRCONbits.TSRNG // bit 4
26131 #define TSEN FVRCONbits.TSEN // bit 5
26132 #define FVRRDY FVRCONbits.FVRRDY // bit 6
26133 #define FVREN FVRCONbits.FVREN // bit 7
26135 #define HIDB0 HIDRVBbits.HIDB0 // bit 0
26136 #define HIDB1 HIDRVBbits.HIDB1 // bit 1
26138 #define INLVE0 INLVEbits.INLVE0 // bit 0
26139 #define INLVE1 INLVEbits.INLVE1 // bit 1
26140 #define INLVE2 INLVEbits.INLVE2 // bit 2
26141 #define INLVE3 INLVEbits.INLVE3 // bit 3
26143 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
26144 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
26145 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
26146 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
26147 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
26148 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
26149 #define INLVA6 INLVLAbits.INLVA6 // bit 6
26150 #define INLVA7 INLVLAbits.INLVA7 // bit 7
26152 #define INLVB0 INLVLBbits.INLVB0 // bit 0
26153 #define INLVB1 INLVLBbits.INLVB1 // bit 1
26154 #define INLVB2 INLVLBbits.INLVB2 // bit 2
26155 #define INLVB3 INLVLBbits.INLVB3 // bit 3
26156 #define INLVLB4 INLVLBbits.INLVLB4 // bit 4
26157 #define INLVLB5 INLVLBbits.INLVLB5 // bit 5
26158 #define INLVLB6 INLVLBbits.INLVLB6 // bit 6
26159 #define INLVLB7 INLVLBbits.INLVLB7 // bit 7
26161 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
26162 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
26163 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
26164 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
26165 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
26166 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
26167 #define INLVLC6 INLVLCbits.INLVLC6 // bit 6
26168 #define INLVLC7 INLVLCbits.INLVLC7 // bit 7
26170 #define INLVLD0 INLVLDbits.INLVLD0 // bit 0
26171 #define INLVLD1 INLVLDbits.INLVLD1 // bit 1
26172 #define INLVLD2 INLVLDbits.INLVLD2 // bit 2
26173 #define INLVLD3 INLVLDbits.INLVLD3 // bit 3
26174 #define INLVLD4 INLVLDbits.INLVLD4 // bit 4
26175 #define INLVLD5 INLVLDbits.INLVLD5 // bit 5
26176 #define INLVLD6 INLVLDbits.INLVLD6 // bit 6
26177 #define INLVLD7 INLVLDbits.INLVLD7 // bit 7
26179 #define IOCIF INTCONbits.IOCIF // bit 0
26180 #define INTF INTCONbits.INTF // bit 1
26181 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
26182 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
26183 #define IOCIE INTCONbits.IOCIE // bit 3
26184 #define INTE INTCONbits.INTE // bit 4
26185 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
26186 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
26187 #define PEIE INTCONbits.PEIE // bit 6
26188 #define GIE INTCONbits.GIE // bit 7
26190 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
26191 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
26192 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
26193 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
26194 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
26195 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
26196 #define IOCAF6 IOCAFbits.IOCAF6 // bit 6
26197 #define IOCAF7 IOCAFbits.IOCAF7 // bit 7
26199 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
26200 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
26201 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
26202 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
26203 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
26204 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
26205 #define IOCAN6 IOCANbits.IOCAN6 // bit 6
26206 #define IOCAN7 IOCANbits.IOCAN7 // bit 7
26208 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
26209 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
26210 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
26211 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
26212 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
26213 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
26214 #define IOCAP6 IOCAPbits.IOCAP6 // bit 6
26215 #define IOCAP7 IOCAPbits.IOCAP7 // bit 7
26217 #define IOCBF0 IOCBFbits.IOCBF0 // bit 0
26218 #define IOCBF1 IOCBFbits.IOCBF1 // bit 1
26219 #define IOCBF2 IOCBFbits.IOCBF2 // bit 2
26220 #define IOCBF3 IOCBFbits.IOCBF3 // bit 3
26221 #define IOCBF4 IOCBFbits.IOCBF4 // bit 4
26222 #define IOCBF5 IOCBFbits.IOCBF5 // bit 5
26223 #define IOCBF6 IOCBFbits.IOCBF6 // bit 6
26224 #define IOCBF7 IOCBFbits.IOCBF7 // bit 7
26226 #define IOCBN0 IOCBNbits.IOCBN0 // bit 0
26227 #define IOCBN1 IOCBNbits.IOCBN1 // bit 1
26228 #define IOCBN2 IOCBNbits.IOCBN2 // bit 2
26229 #define IOCBN3 IOCBNbits.IOCBN3 // bit 3
26230 #define IOCBN4 IOCBNbits.IOCBN4 // bit 4
26231 #define IOCBN5 IOCBNbits.IOCBN5 // bit 5
26232 #define IOCBN6 IOCBNbits.IOCBN6 // bit 6
26233 #define IOCBN7 IOCBNbits.IOCBN7 // bit 7
26235 #define IOCBP0 IOCBPbits.IOCBP0 // bit 0
26236 #define IOCBP1 IOCBPbits.IOCBP1 // bit 1
26237 #define IOCBP2 IOCBPbits.IOCBP2 // bit 2
26238 #define IOCBP3 IOCBPbits.IOCBP3 // bit 3
26239 #define IOCBP4 IOCBPbits.IOCBP4 // bit 4
26240 #define IOCBP5 IOCBPbits.IOCBP5 // bit 5
26241 #define IOCBP6 IOCBPbits.IOCBP6 // bit 6
26242 #define IOCBP7 IOCBPbits.IOCBP7 // bit 7
26244 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
26245 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
26246 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
26247 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
26248 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
26249 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
26250 #define IOCCF6 IOCCFbits.IOCCF6 // bit 6
26251 #define IOCCF7 IOCCFbits.IOCCF7 // bit 7
26253 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
26254 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
26255 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
26256 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
26257 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
26258 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
26259 #define IOCCN6 IOCCNbits.IOCCN6 // bit 6
26260 #define IOCCN7 IOCCNbits.IOCCN7 // bit 7
26262 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
26263 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
26264 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
26265 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
26266 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
26267 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
26268 #define IOCCP6 IOCCPbits.IOCCP6 // bit 6
26269 #define IOCCP7 IOCCPbits.IOCCP7 // bit 7
26271 #define IOCEF3 IOCEFbits.IOCEF3 // bit 3
26273 #define IOCEN3 IOCENbits.IOCEN3 // bit 3
26275 #define IOCEP3 IOCEPbits.IOCEP3 // bit 3
26277 #define LATA0 LATAbits.LATA0 // bit 0
26278 #define LATA1 LATAbits.LATA1 // bit 1
26279 #define LATA2 LATAbits.LATA2 // bit 2
26280 #define LATA3 LATAbits.LATA3 // bit 3
26281 #define LATA4 LATAbits.LATA4 // bit 4
26282 #define LATA5 LATAbits.LATA5 // bit 5
26283 #define LATA6 LATAbits.LATA6 // bit 6
26284 #define LATA7 LATAbits.LATA7 // bit 7
26286 #define LATB0 LATBbits.LATB0 // bit 0
26287 #define LATB1 LATBbits.LATB1 // bit 1
26288 #define LATB2 LATBbits.LATB2 // bit 2
26289 #define LATB3 LATBbits.LATB3 // bit 3
26290 #define LATB4 LATBbits.LATB4 // bit 4
26291 #define LATB5 LATBbits.LATB5 // bit 5
26292 #define LATB6 LATBbits.LATB6 // bit 6
26293 #define LATB7 LATBbits.LATB7 // bit 7
26295 #define LATC0 LATCbits.LATC0 // bit 0
26296 #define LATC1 LATCbits.LATC1 // bit 1
26297 #define LATC2 LATCbits.LATC2 // bit 2
26298 #define LATC3 LATCbits.LATC3 // bit 3
26299 #define LATC4 LATCbits.LATC4 // bit 4
26300 #define LATC5 LATCbits.LATC5 // bit 5
26301 #define LATC6 LATCbits.LATC6 // bit 6
26302 #define LATC7 LATCbits.LATC7 // bit 7
26304 #define LATD0 LATDbits.LATD0 // bit 0
26305 #define LATD1 LATDbits.LATD1 // bit 1
26306 #define LATD2 LATDbits.LATD2 // bit 2
26307 #define LATD3 LATDbits.LATD3 // bit 3
26308 #define LATD4 LATDbits.LATD4 // bit 4
26309 #define LATD5 LATDbits.LATD5 // bit 5
26310 #define LATD6 LATDbits.LATD6 // bit 6
26311 #define LATD7 LATDbits.LATD7 // bit 7
26313 #define LATE0 LATEbits.LATE0 // bit 0
26314 #define LATE1 LATEbits.LATE1 // bit 1
26315 #define LATE2 LATEbits.LATE2 // bit 2
26317 #define CH0 MD1CARHbits.CH0 // bit 0, shadows bit in MD1CARHbits
26318 #define MD1CH0 MD1CARHbits.MD1CH0 // bit 0, shadows bit in MD1CARHbits
26319 #define CH1 MD1CARHbits.CH1 // bit 1, shadows bit in MD1CARHbits
26320 #define MD1CH1 MD1CARHbits.MD1CH1 // bit 1, shadows bit in MD1CARHbits
26321 #define CH2 MD1CARHbits.CH2 // bit 2, shadows bit in MD1CARHbits
26322 #define MD1CH2 MD1CARHbits.MD1CH2 // bit 2, shadows bit in MD1CARHbits
26323 #define CH3 MD1CARHbits.CH3 // bit 3, shadows bit in MD1CARHbits
26324 #define MD1CH3 MD1CARHbits.MD1CH3 // bit 3, shadows bit in MD1CARHbits
26325 #define CH4 MD1CARHbits.CH4 // bit 4
26327 #define CL0 MD1CARLbits.CL0 // bit 0, shadows bit in MD1CARLbits
26328 #define MD1CL0 MD1CARLbits.MD1CL0 // bit 0, shadows bit in MD1CARLbits
26329 #define CL1 MD1CARLbits.CL1 // bit 1, shadows bit in MD1CARLbits
26330 #define MD1CL1 MD1CARLbits.MD1CL1 // bit 1, shadows bit in MD1CARLbits
26331 #define CL2 MD1CARLbits.CL2 // bit 2, shadows bit in MD1CARLbits
26332 #define MD1CL2 MD1CARLbits.MD1CL2 // bit 2, shadows bit in MD1CARLbits
26333 #define CL3 MD1CARLbits.CL3 // bit 3, shadows bit in MD1CARLbits
26334 #define MD1CL3 MD1CARLbits.MD1CL3 // bit 3, shadows bit in MD1CARLbits
26335 #define CL4 MD1CARLbits.CL4 // bit 4
26337 #define CLSYNC MD1CON1bits.CLSYNC // bit 0, shadows bit in MD1CON1bits
26338 #define MD1CLSYNC MD1CON1bits.MD1CLSYNC // bit 0, shadows bit in MD1CON1bits
26339 #define CLPOL MD1CON1bits.CLPOL // bit 1, shadows bit in MD1CON1bits
26340 #define MD1CLPOL MD1CON1bits.MD1CLPOL // bit 1, shadows bit in MD1CON1bits
26341 #define CHSYNC MD1CON1bits.CHSYNC // bit 4, shadows bit in MD1CON1bits
26342 #define MD1CHSYNC MD1CON1bits.MD1CHSYNC // bit 4, shadows bit in MD1CON1bits
26343 #define CHPOL MD1CON1bits.CHPOL // bit 5, shadows bit in MD1CON1bits
26344 #define MD1CHPOL MD1CON1bits.MD1CHPOL // bit 5, shadows bit in MD1CON1bits
26346 #define MS0 MD1SRCbits.MS0 // bit 0, shadows bit in MD1SRCbits
26347 #define MD1MS0 MD1SRCbits.MD1MS0 // bit 0, shadows bit in MD1SRCbits
26348 #define MS1 MD1SRCbits.MS1 // bit 1, shadows bit in MD1SRCbits
26349 #define MD1MS1 MD1SRCbits.MD1MS1 // bit 1, shadows bit in MD1SRCbits
26350 #define MS2 MD1SRCbits.MS2 // bit 2, shadows bit in MD1SRCbits
26351 #define MD1MS2 MD1SRCbits.MD1MS2 // bit 2, shadows bit in MD1SRCbits
26352 #define MS3 MD1SRCbits.MS3 // bit 3, shadows bit in MD1SRCbits
26353 #define MD1MS3 MD1SRCbits.MD1MS3 // bit 3, shadows bit in MD1SRCbits
26354 #define MS4 MD1SRCbits.MS4 // bit 4, shadows bit in MD1SRCbits
26355 #define MD1MS4 MD1SRCbits.MD1MS4 // bit 4, shadows bit in MD1SRCbits
26357 #define ODA0 ODCONAbits.ODA0 // bit 0
26358 #define ODA1 ODCONAbits.ODA1 // bit 1
26359 #define ODA2 ODCONAbits.ODA2 // bit 2
26360 #define ODA3 ODCONAbits.ODA3 // bit 3
26361 #define ODA4 ODCONAbits.ODA4 // bit 4
26362 #define ODA5 ODCONAbits.ODA5 // bit 5
26363 #define ODA6 ODCONAbits.ODA6 // bit 6
26364 #define ODA7 ODCONAbits.ODA7 // bit 7
26366 #define ODB0 ODCONBbits.ODB0 // bit 0
26367 #define ODB1 ODCONBbits.ODB1 // bit 1
26368 #define ODB2 ODCONBbits.ODB2 // bit 2
26369 #define ODB3 ODCONBbits.ODB3 // bit 3
26370 #define ODB4 ODCONBbits.ODB4 // bit 4
26371 #define ODB5 ODCONBbits.ODB5 // bit 5
26372 #define ODB6 ODCONBbits.ODB6 // bit 6
26373 #define ODB7 ODCONBbits.ODB7 // bit 7
26375 #define ODC0 ODCONCbits.ODC0 // bit 0
26376 #define ODC1 ODCONCbits.ODC1 // bit 1
26377 #define ODC2 ODCONCbits.ODC2 // bit 2
26378 #define ODC3 ODCONCbits.ODC3 // bit 3
26379 #define ODC4 ODCONCbits.ODC4 // bit 4
26380 #define ODC5 ODCONCbits.ODC5 // bit 5
26381 #define ODC6 ODCONCbits.ODC6 // bit 6
26382 #define ODC7 ODCONCbits.ODC7 // bit 7
26384 #define ODD0 ODCONDbits.ODD0 // bit 0
26385 #define ODD1 ODCONDbits.ODD1 // bit 1
26386 #define ODD2 ODCONDbits.ODD2 // bit 2
26387 #define ODD3 ODCONDbits.ODD3 // bit 3
26388 #define ODD4 ODCONDbits.ODD4 // bit 4
26389 #define ODD5 ODCONDbits.ODD5 // bit 5
26390 #define ODD6 ODCONDbits.ODD6 // bit 6
26391 #define ODD7 ODCONDbits.ODD7 // bit 7
26393 #define ODE0 ODCONEbits.ODE0 // bit 0
26394 #define ODE1 ODCONEbits.ODE1 // bit 1
26395 #define ODE2 ODCONEbits.ODE2 // bit 2
26397 #define PS0 OPTION_REGbits.PS0 // bit 0
26398 #define PS1 OPTION_REGbits.PS1 // bit 1
26399 #define PS2 OPTION_REGbits.PS2 // bit 2
26400 #define PSA OPTION_REGbits.PSA // bit 3
26401 #define TMR0SE OPTION_REGbits.TMR0SE // bit 4, shadows bit in OPTION_REGbits
26402 #define T0SE OPTION_REGbits.T0SE // bit 4, shadows bit in OPTION_REGbits
26403 #define TMR0CS OPTION_REGbits.TMR0CS // bit 5, shadows bit in OPTION_REGbits
26404 #define T0CS OPTION_REGbits.T0CS // bit 5, shadows bit in OPTION_REGbits
26405 #define INTEDG OPTION_REGbits.INTEDG // bit 6
26406 #define NOT_WPUEN OPTION_REGbits.NOT_WPUEN // bit 7
26408 #define SCS0 OSCCONbits.SCS0 // bit 0
26409 #define SCS1 OSCCONbits.SCS1 // bit 1
26410 #define IRCF0 OSCCONbits.IRCF0 // bit 3
26411 #define IRCF1 OSCCONbits.IRCF1 // bit 4
26412 #define IRCF2 OSCCONbits.IRCF2 // bit 5
26413 #define IRCF3 OSCCONbits.IRCF3 // bit 6
26414 #define SPLLEN OSCCONbits.SPLLEN // bit 7
26416 #define HFIOFS OSCSTATbits.HFIOFS // bit 0
26417 #define LFIOFR OSCSTATbits.LFIOFR // bit 1
26418 #define MFIOFR OSCSTATbits.MFIOFR // bit 2
26419 #define HFIOFL OSCSTATbits.HFIOFL // bit 3
26420 #define HFIOFR OSCSTATbits.HFIOFR // bit 4
26421 #define OSTS OSCSTATbits.OSTS // bit 5
26422 #define PLLR OSCSTATbits.PLLR // bit 6
26423 #define SOSCR OSCSTATbits.SOSCR // bit 7
26425 #define TUN0 OSCTUNEbits.TUN0 // bit 0
26426 #define TUN1 OSCTUNEbits.TUN1 // bit 1
26427 #define TUN2 OSCTUNEbits.TUN2 // bit 2
26428 #define TUN3 OSCTUNEbits.TUN3 // bit 3
26429 #define TUN4 OSCTUNEbits.TUN4 // bit 4
26430 #define TUN5 OSCTUNEbits.TUN5 // bit 5
26432 #define NOT_BOR PCONbits.NOT_BOR // bit 0
26433 #define NOT_POR PCONbits.NOT_POR // bit 1
26434 #define NOT_RI PCONbits.NOT_RI // bit 2
26435 #define NOT_RMCLR PCONbits.NOT_RMCLR // bit 3
26436 #define NOT_RWDT PCONbits.NOT_RWDT // bit 4
26437 #define STKUNF PCONbits.STKUNF // bit 6
26438 #define STKOVF PCONbits.STKOVF // bit 7
26440 #define TMR1IE PIE1bits.TMR1IE // bit 0
26441 #define TMR2IE PIE1bits.TMR2IE // bit 1
26442 #define CCP1IE PIE1bits.CCP1IE // bit 2, shadows bit in PIE1bits
26443 #define CCPIE PIE1bits.CCPIE // bit 2, shadows bit in PIE1bits
26444 #define SSP1IE PIE1bits.SSP1IE // bit 3
26445 #define TXIE PIE1bits.TXIE // bit 4
26446 #define RCIE PIE1bits.RCIE // bit 5
26447 #define ADIE PIE1bits.ADIE // bit 6
26448 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
26450 #define CCP2IE PIE2bits.CCP2IE // bit 0
26451 #define C3IE PIE2bits.C3IE // bit 1
26452 #define C4IE PIE2bits.C4IE // bit 2
26453 #define BCL1IE PIE2bits.BCL1IE // bit 3
26454 #define COGIE PIE2bits.COGIE // bit 4
26455 #define C1IE PIE2bits.C1IE // bit 5
26456 #define C2IE PIE2bits.C2IE // bit 6
26457 #define OSFIE PIE2bits.OSFIE // bit 7
26459 #define CLC1IE PIE3bits.CLC1IE // bit 0
26460 #define CLC2IE PIE3bits.CLC2IE // bit 1
26461 #define CLC3IE PIE3bits.CLC3IE // bit 2
26462 #define CLC4IE PIE3bits.CLC4IE // bit 3
26463 #define ZCDIE PIE3bits.ZCDIE // bit 4
26464 #define COG2IE PIE3bits.COG2IE // bit 5
26466 #define TMR4IE PIE4bits.TMR4IE // bit 0
26467 #define TMR6IE PIE4bits.TMR6IE // bit 1
26468 #define TMR3IE PIE4bits.TMR3IE // bit 2
26469 #define TMR3GIE PIE4bits.TMR3GIE // bit 3
26470 #define TMR5IE PIE4bits.TMR5IE // bit 4
26471 #define TMR5GIE PIE4bits.TMR5GIE // bit 5
26472 #define TMR8IE PIE4bits.TMR8IE // bit 6
26474 #define C5IE PIE5bits.C5IE // bit 0
26475 #define C6IE PIE5bits.C6IE // bit 1
26476 #define C7IE PIE5bits.C7IE // bit 2
26477 #define C8IE PIE5bits.C8IE // bit 3
26478 #define COG3IE PIE5bits.COG3IE // bit 4
26479 #define COG4IE PIE5bits.COG4IE // bit 5
26480 #define CCP7IE PIE5bits.CCP7IE // bit 6
26481 #define CCP8IE PIE5bits.CCP8IE // bit 7
26483 #define PWM5IE PIE6bits.PWM5IE // bit 0
26484 #define PWM6IE PIE6bits.PWM6IE // bit 1
26485 #define PWM11IE PIE6bits.PWM11IE // bit 2
26486 #define PWM12IE PIE6bits.PWM12IE // bit 3
26488 #define TMR1IF PIR1bits.TMR1IF // bit 0
26489 #define TMR2IF PIR1bits.TMR2IF // bit 1
26490 #define CCP1IF PIR1bits.CCP1IF // bit 2, shadows bit in PIR1bits
26491 #define CCPIF PIR1bits.CCPIF // bit 2, shadows bit in PIR1bits
26492 #define SSP1IF PIR1bits.SSP1IF // bit 3
26493 #define TXIF PIR1bits.TXIF // bit 4
26494 #define RCIF PIR1bits.RCIF // bit 5
26495 #define ADIF PIR1bits.ADIF // bit 6
26496 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
26498 #define CCP2IF PIR2bits.CCP2IF // bit 0
26499 #define C3IF PIR2bits.C3IF // bit 1
26500 #define C4IF PIR2bits.C4IF // bit 2
26501 #define BCL1IF PIR2bits.BCL1IF // bit 3
26502 #define COG1IF PIR2bits.COG1IF // bit 4
26503 #define C1IF PIR2bits.C1IF // bit 5
26504 #define C2IF PIR2bits.C2IF // bit 6
26505 #define OSFIF PIR2bits.OSFIF // bit 7
26507 #define CLC1IF PIR3bits.CLC1IF // bit 0
26508 #define CLC2IF PIR3bits.CLC2IF // bit 1
26509 #define CLC3IF PIR3bits.CLC3IF // bit 2
26510 #define CLC4IF PIR3bits.CLC4IF // bit 3
26511 #define ZCDIF PIR3bits.ZCDIF // bit 4
26512 #define COG2IF PIR3bits.COG2IF // bit 5
26514 #define TMR4IF PIR4bits.TMR4IF // bit 0
26515 #define TMR6IF PIR4bits.TMR6IF // bit 1
26516 #define TMR3IF PIR4bits.TMR3IF // bit 2
26517 #define TMR3GIF PIR4bits.TMR3GIF // bit 3
26518 #define TMR5IF PIR4bits.TMR5IF // bit 4
26519 #define TMR5GIF PIR4bits.TMR5GIF // bit 5
26520 #define TMR8IF PIR4bits.TMR8IF // bit 6
26522 #define C5IF PIR5bits.C5IF // bit 0
26523 #define C6IF PIR5bits.C6IF // bit 1
26524 #define C7IF PIR5bits.C7IF // bit 2
26525 #define C8IF PIR5bits.C8IF // bit 3
26526 #define COG3IF PIR5bits.COG3IF // bit 4
26527 #define COG4IF PIR5bits.COG4IF // bit 5
26528 #define CCP7IF PIR5bits.CCP7IF // bit 6
26529 #define CCP8IF PIR5bits.CCP8IF // bit 7
26531 #define PWM5IF PIR6bits.PWM5IF // bit 0
26532 #define PWM6IF PIR6bits.PWM6IF // bit 1
26533 #define PWM11IF PIR6bits.PWM11IF // bit 2
26534 #define PWM12IF PIR6bits.PWM12IF // bit 3
26536 #define RD PMCON1bits.RD // bit 0
26537 #define WR PMCON1bits.WR // bit 1
26538 #define WREN PMCON1bits.WREN // bit 2
26539 #define WRERR PMCON1bits.WRERR // bit 3
26540 #define FREE PMCON1bits.FREE // bit 4
26541 #define LWLO PMCON1bits.LWLO // bit 5
26542 #define CFGS PMCON1bits.CFGS // bit 6
26544 #define RA0 PORTAbits.RA0 // bit 0
26545 #define RA1 PORTAbits.RA1 // bit 1
26546 #define RA2 PORTAbits.RA2 // bit 2
26547 #define RA3 PORTAbits.RA3 // bit 3
26548 #define RA4 PORTAbits.RA4 // bit 4
26549 #define RA5 PORTAbits.RA5 // bit 5
26550 #define RA6 PORTAbits.RA6 // bit 6
26551 #define RA7 PORTAbits.RA7 // bit 7
26553 #define RB0 PORTBbits.RB0 // bit 0
26554 #define RB1 PORTBbits.RB1 // bit 1
26555 #define RB2 PORTBbits.RB2 // bit 2
26556 #define RB3 PORTBbits.RB3 // bit 3
26557 #define RB4 PORTBbits.RB4 // bit 4
26558 #define RB5 PORTBbits.RB5 // bit 5
26559 #define RB6 PORTBbits.RB6 // bit 6
26560 #define RB7 PORTBbits.RB7 // bit 7
26562 #define RC0 PORTCbits.RC0 // bit 0
26563 #define RC1 PORTCbits.RC1 // bit 1
26564 #define RC2 PORTCbits.RC2 // bit 2
26565 #define RC3 PORTCbits.RC3 // bit 3
26566 #define RC4 PORTCbits.RC4 // bit 4
26567 #define RC5 PORTCbits.RC5 // bit 5
26568 #define RC6 PORTCbits.RC6 // bit 6
26569 #define RC7 PORTCbits.RC7 // bit 7
26571 #define RD0 PORTDbits.RD0 // bit 0
26572 #define RD1 PORTDbits.RD1 // bit 1
26573 #define RD2 PORTDbits.RD2 // bit 2
26574 #define RD3 PORTDbits.RD3 // bit 3
26575 #define RD4 PORTDbits.RD4 // bit 4
26576 #define RD5 PORTDbits.RD5 // bit 5
26577 #define RD6 PORTDbits.RD6 // bit 6
26578 #define RD7 PORTDbits.RD7 // bit 7
26580 #define RE0 PORTEbits.RE0 // bit 0
26581 #define RE1 PORTEbits.RE1 // bit 1
26582 #define RE2 PORTEbits.RE2 // bit 2
26583 #define RE3 PORTEbits.RE3 // bit 3
26585 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
26587 #define RPOL PRG1CON1bits.RPOL // bit 0, shadows bit in PRG1CON1bits
26588 #define RG1RPOL PRG1CON1bits.RG1RPOL // bit 0, shadows bit in PRG1CON1bits
26589 #define FPOL PRG1CON1bits.FPOL // bit 1, shadows bit in PRG1CON1bits
26590 #define RG1FPOL PRG1CON1bits.RG1FPOL // bit 1, shadows bit in PRG1CON1bits
26591 #define RDY PRG1CON1bits.RDY // bit 2, shadows bit in PRG1CON1bits
26592 #define RG1RDY PRG1CON1bits.RG1RDY // bit 2, shadows bit in PRG1CON1bits
26594 #define ISET0 PRG1CON2bits.ISET0 // bit 0, shadows bit in PRG1CON2bits
26595 #define RG1ISET0 PRG1CON2bits.RG1ISET0 // bit 0, shadows bit in PRG1CON2bits
26596 #define ISET1 PRG1CON2bits.ISET1 // bit 1, shadows bit in PRG1CON2bits
26597 #define RG1ISET1 PRG1CON2bits.RG1ISET1 // bit 1, shadows bit in PRG1CON2bits
26598 #define ISET2 PRG1CON2bits.ISET2 // bit 2, shadows bit in PRG1CON2bits
26599 #define RG1ISET2 PRG1CON2bits.RG1ISET2 // bit 2, shadows bit in PRG1CON2bits
26600 #define ISET3 PRG1CON2bits.ISET3 // bit 3, shadows bit in PRG1CON2bits
26601 #define RG1ISET3 PRG1CON2bits.RG1ISET3 // bit 3, shadows bit in PRG1CON2bits
26602 #define ISET4 PRG1CON2bits.ISET4 // bit 4, shadows bit in PRG1CON2bits
26603 #define RG1ISET4 PRG1CON2bits.RG1ISET4 // bit 4, shadows bit in PRG1CON2bits
26605 #define FTSS0 PRG1FTSSbits.FTSS0 // bit 0, shadows bit in PRG1FTSSbits
26606 #define RG1FTSS0 PRG1FTSSbits.RG1FTSS0 // bit 0, shadows bit in PRG1FTSSbits
26607 #define FTSS1 PRG1FTSSbits.FTSS1 // bit 1, shadows bit in PRG1FTSSbits
26608 #define RG1FTSS1 PRG1FTSSbits.RG1FTSS1 // bit 1, shadows bit in PRG1FTSSbits
26609 #define FTSS2 PRG1FTSSbits.FTSS2 // bit 2, shadows bit in PRG1FTSSbits
26610 #define RG1FTSS2 PRG1FTSSbits.RG1FTSS2 // bit 2, shadows bit in PRG1FTSSbits
26611 #define FTSS3 PRG1FTSSbits.FTSS3 // bit 3, shadows bit in PRG1FTSSbits
26612 #define RG1FTSS3 PRG1FTSSbits.RG1FTSS3 // bit 3, shadows bit in PRG1FTSSbits
26614 #define INS0 PRG1INSbits.INS0 // bit 0, shadows bit in PRG1INSbits
26615 #define RG1INS0 PRG1INSbits.RG1INS0 // bit 0, shadows bit in PRG1INSbits
26616 #define INS1 PRG1INSbits.INS1 // bit 1, shadows bit in PRG1INSbits
26617 #define RG1INS1 PRG1INSbits.RG1INS1 // bit 1, shadows bit in PRG1INSbits
26618 #define INS2 PRG1INSbits.INS2 // bit 2, shadows bit in PRG1INSbits
26619 #define RG1INS2 PRG1INSbits.RG1INS2 // bit 2, shadows bit in PRG1INSbits
26620 #define INS3 PRG1INSbits.INS3 // bit 3, shadows bit in PRG1INSbits
26621 #define RG1INS3 PRG1INSbits.RG1INS3 // bit 3, shadows bit in PRG1INSbits
26623 #define RTSS0 PRG1RTSSbits.RTSS0 // bit 0, shadows bit in PRG1RTSSbits
26624 #define RG1RTSS0 PRG1RTSSbits.RG1RTSS0 // bit 0, shadows bit in PRG1RTSSbits
26625 #define RTSS1 PRG1RTSSbits.RTSS1 // bit 1, shadows bit in PRG1RTSSbits
26626 #define RG1RTSS1 PRG1RTSSbits.RG1RTSS1 // bit 1, shadows bit in PRG1RTSSbits
26627 #define RTSS2 PRG1RTSSbits.RTSS2 // bit 2, shadows bit in PRG1RTSSbits
26628 #define RG1RTSS2 PRG1RTSSbits.RG1RTSS2 // bit 2, shadows bit in PRG1RTSSbits
26629 #define RTSS3 PRG1RTSSbits.RTSS3 // bit 3, shadows bit in PRG1RTSSbits
26630 #define RG1RTSS3 PRG1RTSSbits.RG1RTSS3 // bit 3, shadows bit in PRG1RTSSbits
26632 #define DC2 PWM3DCHbits.DC2 // bit 0, shadows bit in PWM3DCHbits
26633 #define PWM3DC2 PWM3DCHbits.PWM3DC2 // bit 0, shadows bit in PWM3DCHbits
26634 #define PWMPW2 PWM3DCHbits.PWMPW2 // bit 0, shadows bit in PWM3DCHbits
26635 #define DC3 PWM3DCHbits.DC3 // bit 1, shadows bit in PWM3DCHbits
26636 #define PWM3DC3 PWM3DCHbits.PWM3DC3 // bit 1, shadows bit in PWM3DCHbits
26637 #define PWMPW3 PWM3DCHbits.PWMPW3 // bit 1, shadows bit in PWM3DCHbits
26638 #define DC4 PWM3DCHbits.DC4 // bit 2, shadows bit in PWM3DCHbits
26639 #define PWM3DC4 PWM3DCHbits.PWM3DC4 // bit 2, shadows bit in PWM3DCHbits
26640 #define PWMPW4 PWM3DCHbits.PWMPW4 // bit 2, shadows bit in PWM3DCHbits
26641 #define DC5 PWM3DCHbits.DC5 // bit 3, shadows bit in PWM3DCHbits
26642 #define PWM3DC5 PWM3DCHbits.PWM3DC5 // bit 3, shadows bit in PWM3DCHbits
26643 #define PWMPW5 PWM3DCHbits.PWMPW5 // bit 3, shadows bit in PWM3DCHbits
26644 #define DC6 PWM3DCHbits.DC6 // bit 4, shadows bit in PWM3DCHbits
26645 #define PWM3DC6 PWM3DCHbits.PWM3DC6 // bit 4, shadows bit in PWM3DCHbits
26646 #define PWMPW6 PWM3DCHbits.PWMPW6 // bit 4, shadows bit in PWM3DCHbits
26647 #define DC7 PWM3DCHbits.DC7 // bit 5, shadows bit in PWM3DCHbits
26648 #define PWM3DC7 PWM3DCHbits.PWM3DC7 // bit 5, shadows bit in PWM3DCHbits
26649 #define PWMPW7 PWM3DCHbits.PWMPW7 // bit 5, shadows bit in PWM3DCHbits
26650 #define DC8 PWM3DCHbits.DC8 // bit 6, shadows bit in PWM3DCHbits
26651 #define PWM3DC8 PWM3DCHbits.PWM3DC8 // bit 6, shadows bit in PWM3DCHbits
26652 #define PWMPW8 PWM3DCHbits.PWMPW8 // bit 6, shadows bit in PWM3DCHbits
26653 #define DC9 PWM3DCHbits.DC9 // bit 7, shadows bit in PWM3DCHbits
26654 #define PWM3DC9 PWM3DCHbits.PWM3DC9 // bit 7, shadows bit in PWM3DCHbits
26655 #define PWMPW9 PWM3DCHbits.PWMPW9 // bit 7, shadows bit in PWM3DCHbits
26657 #define DC0 PWM3DCLbits.DC0 // bit 6, shadows bit in PWM3DCLbits
26658 #define PWM3DC0 PWM3DCLbits.PWM3DC0 // bit 6, shadows bit in PWM3DCLbits
26659 #define PWMPW0 PWM3DCLbits.PWMPW0 // bit 6, shadows bit in PWM3DCLbits
26660 #define DC1 PWM3DCLbits.DC1 // bit 7, shadows bit in PWM3DCLbits
26661 #define PWM3DC1 PWM3DCLbits.PWM3DC1 // bit 7, shadows bit in PWM3DCLbits
26662 #define PWMPW1 PWM3DCLbits.PWMPW1 // bit 7, shadows bit in PWM3DCLbits
26664 #define PWM5DCH0 PWM5DCHbits.PWM5DCH0 // bit 0
26665 #define PWM5DCH1 PWM5DCHbits.PWM5DCH1 // bit 1
26666 #define PWM5DCH2 PWM5DCHbits.PWM5DCH2 // bit 2
26667 #define PWM5DCH3 PWM5DCHbits.PWM5DCH3 // bit 3
26668 #define PWM5DCH4 PWM5DCHbits.PWM5DCH4 // bit 4
26669 #define PWM5DCH5 PWM5DCHbits.PWM5DCH5 // bit 5
26670 #define PWM5DCH6 PWM5DCHbits.PWM5DCH6 // bit 6
26671 #define PWM5DCH7 PWM5DCHbits.PWM5DCH7 // bit 7
26673 #define PWM5DCL0 PWM5DCLbits.PWM5DCL0 // bit 0
26674 #define PWM5DCL1 PWM5DCLbits.PWM5DCL1 // bit 1
26675 #define PWM5DCL2 PWM5DCLbits.PWM5DCL2 // bit 2
26676 #define PWM5DCL3 PWM5DCLbits.PWM5DCL3 // bit 3
26677 #define PWM5DCL4 PWM5DCLbits.PWM5DCL4 // bit 4
26678 #define PWM5DCL5 PWM5DCLbits.PWM5DCL5 // bit 5
26679 #define PWM5DCL6 PWM5DCLbits.PWM5DCL6 // bit 6
26680 #define PWM5DCL7 PWM5DCLbits.PWM5DCL7 // bit 7
26682 #define PRIE PWM5INTCONbits.PRIE // bit 0, shadows bit in PWM5INTCONbits
26683 #define PWM5PRIE PWM5INTCONbits.PWM5PRIE // bit 0, shadows bit in PWM5INTCONbits
26684 #define DCIE PWM5INTCONbits.DCIE // bit 1, shadows bit in PWM5INTCONbits
26685 #define PWM5DCIE PWM5INTCONbits.PWM5DCIE // bit 1, shadows bit in PWM5INTCONbits
26686 #define PHIE PWM5INTCONbits.PHIE // bit 2, shadows bit in PWM5INTCONbits
26687 #define PWM5PHIE PWM5INTCONbits.PWM5PHIE // bit 2, shadows bit in PWM5INTCONbits
26688 #define OFIE PWM5INTCONbits.OFIE // bit 3, shadows bit in PWM5INTCONbits
26689 #define PWM5OFIE PWM5INTCONbits.PWM5OFIE // bit 3, shadows bit in PWM5INTCONbits
26691 #define PRIF PWM5INTFbits.PRIF // bit 0, shadows bit in PWM5INTFbits
26692 #define PWM5PRIF PWM5INTFbits.PWM5PRIF // bit 0, shadows bit in PWM5INTFbits
26693 #define DCIF PWM5INTFbits.DCIF // bit 1, shadows bit in PWM5INTFbits
26694 #define PWM5DCIF PWM5INTFbits.PWM5DCIF // bit 1, shadows bit in PWM5INTFbits
26695 #define PHIF PWM5INTFbits.PHIF // bit 2, shadows bit in PWM5INTFbits
26696 #define PWM5PHIF PWM5INTFbits.PWM5PHIF // bit 2, shadows bit in PWM5INTFbits
26697 #define OFIF PWM5INTFbits.OFIF // bit 3, shadows bit in PWM5INTFbits
26698 #define PWM5OFIF PWM5INTFbits.PWM5OFIF // bit 3, shadows bit in PWM5INTFbits
26700 #define PWM5LDS0 PWM5LDCONbits.PWM5LDS0 // bit 0, shadows bit in PWM5LDCONbits
26701 #define LDS0 PWM5LDCONbits.LDS0 // bit 0, shadows bit in PWM5LDCONbits
26702 #define PWM5LDS1 PWM5LDCONbits.PWM5LDS1 // bit 1, shadows bit in PWM5LDCONbits
26703 #define LDS1 PWM5LDCONbits.LDS1 // bit 1, shadows bit in PWM5LDCONbits
26704 #define LDT PWM5LDCONbits.LDT // bit 6, shadows bit in PWM5LDCONbits
26705 #define PWM5LDM PWM5LDCONbits.PWM5LDM // bit 6, shadows bit in PWM5LDCONbits
26706 #define LDA PWM5LDCONbits.LDA // bit 7, shadows bit in PWM5LDCONbits
26707 #define PWM5LD PWM5LDCONbits.PWM5LD // bit 7, shadows bit in PWM5LDCONbits
26709 #define PWM5OFS0 PWM5OFCONbits.PWM5OFS0 // bit 0, shadows bit in PWM5OFCONbits
26710 #define OFS0 PWM5OFCONbits.OFS0 // bit 0, shadows bit in PWM5OFCONbits
26711 #define PWM5OFS1 PWM5OFCONbits.PWM5OFS1 // bit 1, shadows bit in PWM5OFCONbits
26712 #define OFS1 PWM5OFCONbits.OFS1 // bit 1, shadows bit in PWM5OFCONbits
26713 #define OFO PWM5OFCONbits.OFO // bit 4, shadows bit in PWM5OFCONbits
26714 #define PWM5OFMC PWM5OFCONbits.PWM5OFMC // bit 4, shadows bit in PWM5OFCONbits
26715 #define PWM5OFM0 PWM5OFCONbits.PWM5OFM0 // bit 5, shadows bit in PWM5OFCONbits
26716 #define OFM0 PWM5OFCONbits.OFM0 // bit 5, shadows bit in PWM5OFCONbits
26717 #define PWM5OFM1 PWM5OFCONbits.PWM5OFM1 // bit 6, shadows bit in PWM5OFCONbits
26718 #define OFM1 PWM5OFCONbits.OFM1 // bit 6, shadows bit in PWM5OFCONbits
26720 #define PWM5OFH0 PWM5OFHbits.PWM5OFH0 // bit 0
26721 #define PWM5OFH1 PWM5OFHbits.PWM5OFH1 // bit 1
26722 #define PWM5OFH2 PWM5OFHbits.PWM5OFH2 // bit 2
26723 #define PWM5OFH3 PWM5OFHbits.PWM5OFH3 // bit 3
26724 #define PWM5OFH4 PWM5OFHbits.PWM5OFH4 // bit 4
26725 #define PWM5OFH5 PWM5OFHbits.PWM5OFH5 // bit 5
26726 #define PWM5OFH6 PWM5OFHbits.PWM5OFH6 // bit 6
26727 #define PWM5OFH7 PWM5OFHbits.PWM5OFH7 // bit 7
26729 #define PWM5OFL0 PWM5OFLbits.PWM5OFL0 // bit 0
26730 #define PWM5OFL1 PWM5OFLbits.PWM5OFL1 // bit 1
26731 #define PWM5OFL2 PWM5OFLbits.PWM5OFL2 // bit 2
26732 #define PWM5OFL3 PWM5OFLbits.PWM5OFL3 // bit 3
26733 #define PWM5OFL4 PWM5OFLbits.PWM5OFL4 // bit 4
26734 #define PWM5OFL5 PWM5OFLbits.PWM5OFL5 // bit 5
26735 #define PWM5OFL6 PWM5OFLbits.PWM5OFL6 // bit 6
26736 #define PWM5OFL7 PWM5OFLbits.PWM5OFL7 // bit 7
26738 #define PWM5PHH0 PWM5PHHbits.PWM5PHH0 // bit 0
26739 #define PWM5PHH1 PWM5PHHbits.PWM5PHH1 // bit 1
26740 #define PWM5PHH2 PWM5PHHbits.PWM5PHH2 // bit 2
26741 #define PWM5PHH3 PWM5PHHbits.PWM5PHH3 // bit 3
26742 #define PWM5PHH4 PWM5PHHbits.PWM5PHH4 // bit 4
26743 #define PWM5PHH5 PWM5PHHbits.PWM5PHH5 // bit 5
26744 #define PWM5PHH6 PWM5PHHbits.PWM5PHH6 // bit 6
26745 #define PWM5PHH7 PWM5PHHbits.PWM5PHH7 // bit 7
26747 #define PWM5PHL0 PWM5PHLbits.PWM5PHL0 // bit 0
26748 #define PWM5PHL1 PWM5PHLbits.PWM5PHL1 // bit 1
26749 #define PWM5PHL2 PWM5PHLbits.PWM5PHL2 // bit 2
26750 #define PWM5PHL3 PWM5PHLbits.PWM5PHL3 // bit 3
26751 #define PWM5PHL4 PWM5PHLbits.PWM5PHL4 // bit 4
26752 #define PWM5PHL5 PWM5PHLbits.PWM5PHL5 // bit 5
26753 #define PWM5PHL6 PWM5PHLbits.PWM5PHL6 // bit 6
26754 #define PWM5PHL7 PWM5PHLbits.PWM5PHL7 // bit 7
26756 #define PWM5PRH0 PWM5PRHbits.PWM5PRH0 // bit 0
26757 #define PWM5PRH1 PWM5PRHbits.PWM5PRH1 // bit 1
26758 #define PWM5PRH2 PWM5PRHbits.PWM5PRH2 // bit 2
26759 #define PWM5PRH3 PWM5PRHbits.PWM5PRH3 // bit 3
26760 #define PWM5PRH4 PWM5PRHbits.PWM5PRH4 // bit 4
26761 #define PWM5PRH5 PWM5PRHbits.PWM5PRH5 // bit 5
26762 #define PWM5PRH6 PWM5PRHbits.PWM5PRH6 // bit 6
26763 #define PWM5PRH7 PWM5PRHbits.PWM5PRH7 // bit 7
26765 #define PWM5PRL0 PWM5PRLbits.PWM5PRL0 // bit 0
26766 #define PWM5PRL1 PWM5PRLbits.PWM5PRL1 // bit 1
26767 #define PWM5PRL2 PWM5PRLbits.PWM5PRL2 // bit 2
26768 #define PWM5PRL3 PWM5PRLbits.PWM5PRL3 // bit 3
26769 #define PWM5PRL4 PWM5PRLbits.PWM5PRL4 // bit 4
26770 #define PWM5PRL5 PWM5PRLbits.PWM5PRL5 // bit 5
26771 #define PWM5PRL6 PWM5PRLbits.PWM5PRL6 // bit 6
26772 #define PWM5PRL7 PWM5PRLbits.PWM5PRL7 // bit 7
26774 #define PWM5TMRH0 PWM5TMRHbits.PWM5TMRH0 // bit 0
26775 #define PWM5TMRH1 PWM5TMRHbits.PWM5TMRH1 // bit 1
26776 #define PWM5TMRH2 PWM5TMRHbits.PWM5TMRH2 // bit 2
26777 #define PWM5TMRH3 PWM5TMRHbits.PWM5TMRH3 // bit 3
26778 #define PWM5TMRH4 PWM5TMRHbits.PWM5TMRH4 // bit 4
26779 #define PWM5TMRH5 PWM5TMRHbits.PWM5TMRH5 // bit 5
26780 #define PWM5TMRH6 PWM5TMRHbits.PWM5TMRH6 // bit 6
26781 #define PWM5TMRH7 PWM5TMRHbits.PWM5TMRH7 // bit 7
26783 #define PWM5TMRL0 PWM5TMRLbits.PWM5TMRL0 // bit 0
26784 #define PWM5TMRL1 PWM5TMRLbits.PWM5TMRL1 // bit 1
26785 #define PWM5TMRL2 PWM5TMRLbits.PWM5TMRL2 // bit 2
26786 #define PWM5TMRL3 PWM5TMRLbits.PWM5TMRL3 // bit 3
26787 #define PWM5TMRL4 PWM5TMRLbits.PWM5TMRL4 // bit 4
26788 #define PWM5TMRL5 PWM5TMRLbits.PWM5TMRL5 // bit 5
26789 #define PWM5TMRL6 PWM5TMRLbits.PWM5TMRL6 // bit 6
26790 #define PWM5TMRL7 PWM5TMRLbits.PWM5TMRL7 // bit 7
26792 #define PWM6DCH0 PWM6DCHbits.PWM6DCH0 // bit 0
26793 #define PWM6DCH1 PWM6DCHbits.PWM6DCH1 // bit 1
26794 #define PWM6DCH2 PWM6DCHbits.PWM6DCH2 // bit 2
26795 #define PWM6DCH3 PWM6DCHbits.PWM6DCH3 // bit 3
26796 #define PWM6DCH4 PWM6DCHbits.PWM6DCH4 // bit 4
26797 #define PWM6DCH5 PWM6DCHbits.PWM6DCH5 // bit 5
26798 #define PWM6DCH6 PWM6DCHbits.PWM6DCH6 // bit 6
26799 #define PWM6DCH7 PWM6DCHbits.PWM6DCH7 // bit 7
26801 #define PWM6DCL0 PWM6DCLbits.PWM6DCL0 // bit 0
26802 #define PWM6DCL1 PWM6DCLbits.PWM6DCL1 // bit 1
26803 #define PWM6DCL2 PWM6DCLbits.PWM6DCL2 // bit 2
26804 #define PWM6DCL3 PWM6DCLbits.PWM6DCL3 // bit 3
26805 #define PWM6DCL4 PWM6DCLbits.PWM6DCL4 // bit 4
26806 #define PWM6DCL5 PWM6DCLbits.PWM6DCL5 // bit 5
26807 #define PWM6DCL6 PWM6DCLbits.PWM6DCL6 // bit 6
26808 #define PWM6DCL7 PWM6DCLbits.PWM6DCL7 // bit 7
26810 #define PWM6OFH0 PWM6OFHbits.PWM6OFH0 // bit 0
26811 #define PWM6OFH1 PWM6OFHbits.PWM6OFH1 // bit 1
26812 #define PWM6OFH2 PWM6OFHbits.PWM6OFH2 // bit 2
26813 #define PWM6OFH3 PWM6OFHbits.PWM6OFH3 // bit 3
26814 #define PWM6OFH4 PWM6OFHbits.PWM6OFH4 // bit 4
26815 #define PWM6OFH5 PWM6OFHbits.PWM6OFH5 // bit 5
26816 #define PWM6OFH6 PWM6OFHbits.PWM6OFH6 // bit 6
26817 #define PWM6OFH7 PWM6OFHbits.PWM6OFH7 // bit 7
26819 #define PWM6OFL0 PWM6OFLbits.PWM6OFL0 // bit 0
26820 #define PWM6OFL1 PWM6OFLbits.PWM6OFL1 // bit 1
26821 #define PWM6OFL2 PWM6OFLbits.PWM6OFL2 // bit 2
26822 #define PWM6OFL3 PWM6OFLbits.PWM6OFL3 // bit 3
26823 #define PWM6OFL4 PWM6OFLbits.PWM6OFL4 // bit 4
26824 #define PWM6OFL5 PWM6OFLbits.PWM6OFL5 // bit 5
26825 #define PWM6OFL6 PWM6OFLbits.PWM6OFL6 // bit 6
26826 #define PWM6OFL7 PWM6OFLbits.PWM6OFL7 // bit 7
26828 #define PWM6PHH0 PWM6PHHbits.PWM6PHH0 // bit 0
26829 #define PWM6PHH1 PWM6PHHbits.PWM6PHH1 // bit 1
26830 #define PWM6PHH2 PWM6PHHbits.PWM6PHH2 // bit 2
26831 #define PWM6PHH3 PWM6PHHbits.PWM6PHH3 // bit 3
26832 #define PWM6PHH4 PWM6PHHbits.PWM6PHH4 // bit 4
26833 #define PWM6PHH5 PWM6PHHbits.PWM6PHH5 // bit 5
26834 #define PWM6PHH6 PWM6PHHbits.PWM6PHH6 // bit 6
26835 #define PWM6PHH7 PWM6PHHbits.PWM6PHH7 // bit 7
26837 #define PWM6PHL0 PWM6PHLbits.PWM6PHL0 // bit 0
26838 #define PWM6PHL1 PWM6PHLbits.PWM6PHL1 // bit 1
26839 #define PWM6PHL2 PWM6PHLbits.PWM6PHL2 // bit 2
26840 #define PWM6PHL3 PWM6PHLbits.PWM6PHL3 // bit 3
26841 #define PWM6PHL4 PWM6PHLbits.PWM6PHL4 // bit 4
26842 #define PWM6PHL5 PWM6PHLbits.PWM6PHL5 // bit 5
26843 #define PWM6PHL6 PWM6PHLbits.PWM6PHL6 // bit 6
26844 #define PWM6PHL7 PWM6PHLbits.PWM6PHL7 // bit 7
26846 #define PWM6PRH0 PWM6PRHbits.PWM6PRH0 // bit 0
26847 #define PWM6PRH1 PWM6PRHbits.PWM6PRH1 // bit 1
26848 #define PWM6PRH2 PWM6PRHbits.PWM6PRH2 // bit 2
26849 #define PWM6PRH3 PWM6PRHbits.PWM6PRH3 // bit 3
26850 #define PWM6PRH4 PWM6PRHbits.PWM6PRH4 // bit 4
26851 #define PWM6PRH5 PWM6PRHbits.PWM6PRH5 // bit 5
26852 #define PWM6PRH6 PWM6PRHbits.PWM6PRH6 // bit 6
26853 #define PWM6PRH7 PWM6PRHbits.PWM6PRH7 // bit 7
26855 #define PWM6PRL0 PWM6PRLbits.PWM6PRL0 // bit 0
26856 #define PWM6PRL1 PWM6PRLbits.PWM6PRL1 // bit 1
26857 #define PWM6PRL2 PWM6PRLbits.PWM6PRL2 // bit 2
26858 #define PWM6PRL3 PWM6PRLbits.PWM6PRL3 // bit 3
26859 #define PWM6PRL4 PWM6PRLbits.PWM6PRL4 // bit 4
26860 #define PWM6PRL5 PWM6PRLbits.PWM6PRL5 // bit 5
26861 #define PWM6PRL6 PWM6PRLbits.PWM6PRL6 // bit 6
26862 #define PWM6PRL7 PWM6PRLbits.PWM6PRL7 // bit 7
26864 #define PWM6TMRH0 PWM6TMRHbits.PWM6TMRH0 // bit 0
26865 #define PWM6TMRH1 PWM6TMRHbits.PWM6TMRH1 // bit 1
26866 #define PWM6TMRH2 PWM6TMRHbits.PWM6TMRH2 // bit 2
26867 #define PWM6TMRH3 PWM6TMRHbits.PWM6TMRH3 // bit 3
26868 #define PWM6TMRH4 PWM6TMRHbits.PWM6TMRH4 // bit 4
26869 #define PWM6TMRH5 PWM6TMRHbits.PWM6TMRH5 // bit 5
26870 #define PWM6TMRH6 PWM6TMRHbits.PWM6TMRH6 // bit 6
26871 #define PWM6TMRH7 PWM6TMRHbits.PWM6TMRH7 // bit 7
26873 #define PWM6TMRL0 PWM6TMRLbits.PWM6TMRL0 // bit 0
26874 #define PWM6TMRL1 PWM6TMRLbits.PWM6TMRL1 // bit 1
26875 #define PWM6TMRL2 PWM6TMRLbits.PWM6TMRL2 // bit 2
26876 #define PWM6TMRL3 PWM6TMRLbits.PWM6TMRL3 // bit 3
26877 #define PWM6TMRL4 PWM6TMRLbits.PWM6TMRL4 // bit 4
26878 #define PWM6TMRL5 PWM6TMRLbits.PWM6TMRL5 // bit 5
26879 #define PWM6TMRL6 PWM6TMRLbits.PWM6TMRL6 // bit 6
26880 #define PWM6TMRL7 PWM6TMRLbits.PWM6TMRL7 // bit 7
26882 #define PWM11DCH0 PWM11DCHbits.PWM11DCH0 // bit 0
26883 #define PWM11DCH1 PWM11DCHbits.PWM11DCH1 // bit 1
26884 #define PWM11DCH2 PWM11DCHbits.PWM11DCH2 // bit 2
26885 #define PWM11DCH3 PWM11DCHbits.PWM11DCH3 // bit 3
26886 #define PWM11DCH4 PWM11DCHbits.PWM11DCH4 // bit 4
26887 #define PWM11DCH5 PWM11DCHbits.PWM11DCH5 // bit 5
26888 #define PWM11DCH6 PWM11DCHbits.PWM11DCH6 // bit 6
26889 #define PWM11DCH7 PWM11DCHbits.PWM11DCH7 // bit 7
26891 #define PWM11DCL0 PWM11DCLbits.PWM11DCL0 // bit 0
26892 #define PWM11DCL1 PWM11DCLbits.PWM11DCL1 // bit 1
26893 #define PWM11DCL2 PWM11DCLbits.PWM11DCL2 // bit 2
26894 #define PWM11DCL3 PWM11DCLbits.PWM11DCL3 // bit 3
26895 #define PWM11DCL4 PWM11DCLbits.PWM11DCL4 // bit 4
26896 #define PWM11DCL5 PWM11DCLbits.PWM11DCL5 // bit 5
26897 #define PWM11DCL6 PWM11DCLbits.PWM11DCL6 // bit 6
26898 #define PWM11DCL7 PWM11DCLbits.PWM11DCL7 // bit 7
26900 #define PWM11OFH0 PWM11OFHbits.PWM11OFH0 // bit 0
26901 #define PWM11OFH1 PWM11OFHbits.PWM11OFH1 // bit 1
26902 #define PWM11OFH2 PWM11OFHbits.PWM11OFH2 // bit 2
26903 #define PWM11OFH3 PWM11OFHbits.PWM11OFH3 // bit 3
26904 #define PWM11OFH4 PWM11OFHbits.PWM11OFH4 // bit 4
26905 #define PWM11OFH5 PWM11OFHbits.PWM11OFH5 // bit 5
26906 #define PWM11OFH6 PWM11OFHbits.PWM11OFH6 // bit 6
26907 #define PWM11OFH7 PWM11OFHbits.PWM11OFH7 // bit 7
26909 #define PWM11OFL0 PWM11OFLbits.PWM11OFL0 // bit 0
26910 #define PWM11OFL1 PWM11OFLbits.PWM11OFL1 // bit 1
26911 #define PWM11OFL2 PWM11OFLbits.PWM11OFL2 // bit 2
26912 #define PWM11OFL3 PWM11OFLbits.PWM11OFL3 // bit 3
26913 #define PWM11OFL4 PWM11OFLbits.PWM11OFL4 // bit 4
26914 #define PWM11OFL5 PWM11OFLbits.PWM11OFL5 // bit 5
26915 #define PWM11OFL6 PWM11OFLbits.PWM11OFL6 // bit 6
26916 #define PWM11OFL7 PWM11OFLbits.PWM11OFL7 // bit 7
26918 #define PWM11PHH0 PWM11PHHbits.PWM11PHH0 // bit 0
26919 #define PWM11PHH1 PWM11PHHbits.PWM11PHH1 // bit 1
26920 #define PWM11PHH2 PWM11PHHbits.PWM11PHH2 // bit 2
26921 #define PWM11PHH3 PWM11PHHbits.PWM11PHH3 // bit 3
26922 #define PWM11PHH4 PWM11PHHbits.PWM11PHH4 // bit 4
26923 #define PWM11PHH5 PWM11PHHbits.PWM11PHH5 // bit 5
26924 #define PWM11PHH6 PWM11PHHbits.PWM11PHH6 // bit 6
26925 #define PWM11PHH7 PWM11PHHbits.PWM11PHH7 // bit 7
26927 #define PWM11PHL0 PWM11PHLbits.PWM11PHL0 // bit 0
26928 #define PWM11PHL1 PWM11PHLbits.PWM11PHL1 // bit 1
26929 #define PWM11PHL2 PWM11PHLbits.PWM11PHL2 // bit 2
26930 #define PWM11PHL3 PWM11PHLbits.PWM11PHL3 // bit 3
26931 #define PWM11PHL4 PWM11PHLbits.PWM11PHL4 // bit 4
26932 #define PWM11PHL5 PWM11PHLbits.PWM11PHL5 // bit 5
26933 #define PWM11PHL6 PWM11PHLbits.PWM11PHL6 // bit 6
26934 #define PWM11PHL7 PWM11PHLbits.PWM11PHL7 // bit 7
26936 #define PWM11PRH0 PWM11PRHbits.PWM11PRH0 // bit 0
26937 #define PWM11PRH1 PWM11PRHbits.PWM11PRH1 // bit 1
26938 #define PWM11PRH2 PWM11PRHbits.PWM11PRH2 // bit 2
26939 #define PWM11PRH3 PWM11PRHbits.PWM11PRH3 // bit 3
26940 #define PWM11PRH4 PWM11PRHbits.PWM11PRH4 // bit 4
26941 #define PWM11PRH5 PWM11PRHbits.PWM11PRH5 // bit 5
26942 #define PWM11PRH6 PWM11PRHbits.PWM11PRH6 // bit 6
26943 #define PWM11PRH7 PWM11PRHbits.PWM11PRH7 // bit 7
26945 #define PWM11PRL0 PWM11PRLbits.PWM11PRL0 // bit 0
26946 #define PWM11PRL1 PWM11PRLbits.PWM11PRL1 // bit 1
26947 #define PWM11PRL2 PWM11PRLbits.PWM11PRL2 // bit 2
26948 #define PWM11PRL3 PWM11PRLbits.PWM11PRL3 // bit 3
26949 #define PWM11PRL4 PWM11PRLbits.PWM11PRL4 // bit 4
26950 #define PWM11PRL5 PWM11PRLbits.PWM11PRL5 // bit 5
26951 #define PWM11PRL6 PWM11PRLbits.PWM11PRL6 // bit 6
26952 #define PWM11PRL7 PWM11PRLbits.PWM11PRL7 // bit 7
26954 #define PWM11TMRH0 PWM11TMRHbits.PWM11TMRH0 // bit 0
26955 #define PWM11TMRH1 PWM11TMRHbits.PWM11TMRH1 // bit 1
26956 #define PWM11TMRH2 PWM11TMRHbits.PWM11TMRH2 // bit 2
26957 #define PWM11TMRH3 PWM11TMRHbits.PWM11TMRH3 // bit 3
26958 #define PWM11TMRH4 PWM11TMRHbits.PWM11TMRH4 // bit 4
26959 #define PWM11TMRH5 PWM11TMRHbits.PWM11TMRH5 // bit 5
26960 #define PWM11TMRH6 PWM11TMRHbits.PWM11TMRH6 // bit 6
26961 #define PWM11TMRH7 PWM11TMRHbits.PWM11TMRH7 // bit 7
26963 #define PWM11TMRL0 PWM11TMRLbits.PWM11TMRL0 // bit 0
26964 #define PWM11TMRL1 PWM11TMRLbits.PWM11TMRL1 // bit 1
26965 #define PWM11TMRL2 PWM11TMRLbits.PWM11TMRL2 // bit 2
26966 #define PWM11TMRL3 PWM11TMRLbits.PWM11TMRL3 // bit 3
26967 #define PWM11TMRL4 PWM11TMRLbits.PWM11TMRL4 // bit 4
26968 #define PWM11TMRL5 PWM11TMRLbits.PWM11TMRL5 // bit 5
26969 #define PWM11TMRL6 PWM11TMRLbits.PWM11TMRL6 // bit 6
26970 #define PWM11TMRL7 PWM11TMRLbits.PWM11TMRL7 // bit 7
26972 #define PWM12DCH0 PWM12DCHbits.PWM12DCH0 // bit 0
26973 #define PWM12DCH1 PWM12DCHbits.PWM12DCH1 // bit 1
26974 #define PWM12DCH2 PWM12DCHbits.PWM12DCH2 // bit 2
26975 #define PWM12DCH3 PWM12DCHbits.PWM12DCH3 // bit 3
26976 #define PWM12DCH4 PWM12DCHbits.PWM12DCH4 // bit 4
26977 #define PWM12DCH5 PWM12DCHbits.PWM12DCH5 // bit 5
26978 #define PWM12DCH6 PWM12DCHbits.PWM12DCH6 // bit 6
26979 #define PWM12DCH7 PWM12DCHbits.PWM12DCH7 // bit 7
26981 #define PWM12DCL0 PWM12DCLbits.PWM12DCL0 // bit 0
26982 #define PWM12DCL1 PWM12DCLbits.PWM12DCL1 // bit 1
26983 #define PWM12DCL2 PWM12DCLbits.PWM12DCL2 // bit 2
26984 #define PWM12DCL3 PWM12DCLbits.PWM12DCL3 // bit 3
26985 #define PWM12DCL4 PWM12DCLbits.PWM12DCL4 // bit 4
26986 #define PWM12DCL5 PWM12DCLbits.PWM12DCL5 // bit 5
26987 #define PWM12DCL6 PWM12DCLbits.PWM12DCL6 // bit 6
26988 #define PWM12DCL7 PWM12DCLbits.PWM12DCL7 // bit 7
26990 #define PWM12OFH0 PWM12OFHbits.PWM12OFH0 // bit 0
26991 #define PWM12OFH1 PWM12OFHbits.PWM12OFH1 // bit 1
26992 #define PWM12OFH2 PWM12OFHbits.PWM12OFH2 // bit 2
26993 #define PWM12OFH3 PWM12OFHbits.PWM12OFH3 // bit 3
26994 #define PWM12OFH4 PWM12OFHbits.PWM12OFH4 // bit 4
26995 #define PWM12OFH5 PWM12OFHbits.PWM12OFH5 // bit 5
26996 #define PWM12OFH6 PWM12OFHbits.PWM12OFH6 // bit 6
26997 #define PWM12OFH7 PWM12OFHbits.PWM12OFH7 // bit 7
26999 #define PWM12OFL0 PWM12OFLbits.PWM12OFL0 // bit 0
27000 #define PWM12OFL1 PWM12OFLbits.PWM12OFL1 // bit 1
27001 #define PWM12OFL2 PWM12OFLbits.PWM12OFL2 // bit 2
27002 #define PWM12OFL3 PWM12OFLbits.PWM12OFL3 // bit 3
27003 #define PWM12OFL4 PWM12OFLbits.PWM12OFL4 // bit 4
27004 #define PWM12OFL5 PWM12OFLbits.PWM12OFL5 // bit 5
27005 #define PWM12OFL6 PWM12OFLbits.PWM12OFL6 // bit 6
27006 #define PWM12OFL7 PWM12OFLbits.PWM12OFL7 // bit 7
27008 #define PWM12PHH0 PWM12PHHbits.PWM12PHH0 // bit 0
27009 #define PWM12PHH1 PWM12PHHbits.PWM12PHH1 // bit 1
27010 #define PWM12PHH2 PWM12PHHbits.PWM12PHH2 // bit 2
27011 #define PWM12PHH3 PWM12PHHbits.PWM12PHH3 // bit 3
27012 #define PWM12PHH4 PWM12PHHbits.PWM12PHH4 // bit 4
27013 #define PWM12PHH5 PWM12PHHbits.PWM12PHH5 // bit 5
27014 #define PWM12PHH6 PWM12PHHbits.PWM12PHH6 // bit 6
27015 #define PWM12PHH7 PWM12PHHbits.PWM12PHH7 // bit 7
27017 #define PWM12PHL0 PWM12PHLbits.PWM12PHL0 // bit 0
27018 #define PWM12PHL1 PWM12PHLbits.PWM12PHL1 // bit 1
27019 #define PWM12PHL2 PWM12PHLbits.PWM12PHL2 // bit 2
27020 #define PWM12PHL3 PWM12PHLbits.PWM12PHL3 // bit 3
27021 #define PWM12PHL4 PWM12PHLbits.PWM12PHL4 // bit 4
27022 #define PWM12PHL5 PWM12PHLbits.PWM12PHL5 // bit 5
27023 #define PWM12PHL6 PWM12PHLbits.PWM12PHL6 // bit 6
27024 #define PWM12PHL7 PWM12PHLbits.PWM12PHL7 // bit 7
27026 #define PWM12PRH0 PWM12PRHbits.PWM12PRH0 // bit 0
27027 #define PWM12PRH1 PWM12PRHbits.PWM12PRH1 // bit 1
27028 #define PWM12PRH2 PWM12PRHbits.PWM12PRH2 // bit 2
27029 #define PWM12PRH3 PWM12PRHbits.PWM12PRH3 // bit 3
27030 #define PWM12PRH4 PWM12PRHbits.PWM12PRH4 // bit 4
27031 #define PWM12PRH5 PWM12PRHbits.PWM12PRH5 // bit 5
27032 #define PWM12PRH6 PWM12PRHbits.PWM12PRH6 // bit 6
27033 #define PWM12PRH7 PWM12PRHbits.PWM12PRH7 // bit 7
27035 #define PWM12PRL0 PWM12PRLbits.PWM12PRL0 // bit 0
27036 #define PWM12PRL1 PWM12PRLbits.PWM12PRL1 // bit 1
27037 #define PWM12PRL2 PWM12PRLbits.PWM12PRL2 // bit 2
27038 #define PWM12PRL3 PWM12PRLbits.PWM12PRL3 // bit 3
27039 #define PWM12PRL4 PWM12PRLbits.PWM12PRL4 // bit 4
27040 #define PWM12PRL5 PWM12PRLbits.PWM12PRL5 // bit 5
27041 #define PWM12PRL6 PWM12PRLbits.PWM12PRL6 // bit 6
27042 #define PWM12PRL7 PWM12PRLbits.PWM12PRL7 // bit 7
27044 #define PWM12TMRH0 PWM12TMRHbits.PWM12TMRH0 // bit 0
27045 #define PWM12TMRH1 PWM12TMRHbits.PWM12TMRH1 // bit 1
27046 #define PWM12TMRH2 PWM12TMRHbits.PWM12TMRH2 // bit 2
27047 #define PWM12TMRH3 PWM12TMRHbits.PWM12TMRH3 // bit 3
27048 #define PWM12TMRH4 PWM12TMRHbits.PWM12TMRH4 // bit 4
27049 #define PWM12TMRH5 PWM12TMRHbits.PWM12TMRH5 // bit 5
27050 #define PWM12TMRH6 PWM12TMRHbits.PWM12TMRH6 // bit 6
27051 #define PWM12TMRH7 PWM12TMRHbits.PWM12TMRH7 // bit 7
27053 #define PWM12TMRL0 PWM12TMRLbits.PWM12TMRL0 // bit 0
27054 #define PWM12TMRL1 PWM12TMRLbits.PWM12TMRL1 // bit 1
27055 #define PWM12TMRL2 PWM12TMRLbits.PWM12TMRL2 // bit 2
27056 #define PWM12TMRL3 PWM12TMRLbits.PWM12TMRL3 // bit 3
27057 #define PWM12TMRL4 PWM12TMRLbits.PWM12TMRL4 // bit 4
27058 #define PWM12TMRL5 PWM12TMRLbits.PWM12TMRL5 // bit 5
27059 #define PWM12TMRL6 PWM12TMRLbits.PWM12TMRL6 // bit 6
27060 #define PWM12TMRL7 PWM12TMRLbits.PWM12TMRL7 // bit 7
27062 #define MPWM5EN PWMENbits.MPWM5EN // bit 0
27063 #define MPWM6EN PWMENbits.MPWM6EN // bit 1
27064 #define MPWM11EN PWMENbits.MPWM11EN // bit 2
27065 #define MPWM12EN PWMENbits.MPWM12EN // bit 3
27067 #define MPWM5LD PWMLDbits.MPWM5LD // bit 0
27068 #define MPWM6LD PWMLDbits.MPWM6LD // bit 1
27069 #define MPWM11LD PWMLDbits.MPWM11LD // bit 2
27070 #define MPWM12LD PWMLDbits.MPWM12LD // bit 3
27072 #define MPWM5OUT PWMOUTbits.MPWM5OUT // bit 0
27073 #define MPWM6OUT PWMOUTbits.MPWM6OUT // bit 1
27074 #define MPWM11OUT PWMOUTbits.MPWM11OUT // bit 2
27075 #define MPWM12OUT PWMOUTbits.MPWM12OUT // bit 3
27077 #define RX9D RC1STAbits.RX9D // bit 0
27078 #define OERR RC1STAbits.OERR // bit 1
27079 #define FERR RC1STAbits.FERR // bit 2
27080 #define ADDEN RC1STAbits.ADDEN // bit 3
27081 #define CREN RC1STAbits.CREN // bit 4
27082 #define SREN RC1STAbits.SREN // bit 5
27083 #define RX9 RC1STAbits.RX9 // bit 6
27084 #define SPEN RC1STAbits.SPEN // bit 7
27086 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
27087 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
27088 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
27089 #define SLRA3 SLRCONAbits.SLRA3 // bit 3
27090 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
27091 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
27092 #define SLRA6 SLRCONAbits.SLRA6 // bit 6
27093 #define SLRA7 SLRCONAbits.SLRA7 // bit 7
27095 #define SLRB0 SLRCONBbits.SLRB0 // bit 0
27096 #define SLRB1 SLRCONBbits.SLRB1 // bit 1
27097 #define SLRB2 SLRCONBbits.SLRB2 // bit 2
27098 #define SLRB3 SLRCONBbits.SLRB3 // bit 3
27099 #define SLRB4 SLRCONBbits.SLRB4 // bit 4
27100 #define SLRB5 SLRCONBbits.SLRB5 // bit 5
27101 #define SLRB6 SLRCONBbits.SLRB6 // bit 6
27102 #define SLRB7 SLRCONBbits.SLRB7 // bit 7
27104 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
27105 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
27106 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
27107 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
27108 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
27109 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
27110 #define SLRC6 SLRCONCbits.SLRC6 // bit 6
27111 #define SLRC7 SLRCONCbits.SLRC7 // bit 7
27113 #define SLRD0 SLRCONDbits.SLRD0 // bit 0
27114 #define SLRD1 SLRCONDbits.SLRD1 // bit 1
27115 #define SLRD2 SLRCONDbits.SLRD2 // bit 2
27116 #define SLRD3 SLRCONDbits.SLRD3 // bit 3
27117 #define SLRD4 SLRCONDbits.SLRD4 // bit 4
27118 #define SLRD5 SLRCONDbits.SLRD5 // bit 5
27119 #define SLRD6 SLRCONDbits.SLRD6 // bit 6
27120 #define SLRD7 SLRCONDbits.SLRD7 // bit 7
27122 #define SLRE0 SLRCONEbits.SLRE0 // bit 0
27123 #define SLRE1 SLRCONEbits.SLRE1 // bit 1
27124 #define SLRE2 SLRCONEbits.SLRE2 // bit 2
27126 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
27127 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
27128 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
27129 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
27130 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
27131 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
27132 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
27133 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
27134 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
27135 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
27136 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
27137 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
27138 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
27139 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
27140 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
27141 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
27143 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
27144 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
27145 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
27146 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
27147 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
27148 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
27149 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
27150 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
27151 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
27152 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
27153 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
27154 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
27155 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
27156 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
27157 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
27158 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
27160 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
27161 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
27162 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
27163 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
27164 #define CKP SSP1CONbits.CKP // bit 4
27165 #define SSPEN SSP1CONbits.SSPEN // bit 5
27166 #define SSPOV SSP1CONbits.SSPOV // bit 6
27167 #define WCOL SSP1CONbits.WCOL // bit 7
27169 #define SEN SSP1CON2bits.SEN // bit 0
27170 #define RSEN SSP1CON2bits.RSEN // bit 1
27171 #define PEN SSP1CON2bits.PEN // bit 2
27172 #define RCEN SSP1CON2bits.RCEN // bit 3
27173 #define ACKEN SSP1CON2bits.ACKEN // bit 4
27174 #define ACKDT SSP1CON2bits.ACKDT // bit 5
27175 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
27176 #define GCEN SSP1CON2bits.GCEN // bit 7
27178 #define DHEN SSP1CON3bits.DHEN // bit 0
27179 #define AHEN SSP1CON3bits.AHEN // bit 1
27180 #define SBCDE SSP1CON3bits.SBCDE // bit 2
27181 #define SDAHT SSP1CON3bits.SDAHT // bit 3
27182 #define BOEN SSP1CON3bits.BOEN // bit 4
27183 #define SCIE SSP1CON3bits.SCIE // bit 5
27184 #define PCIE SSP1CON3bits.PCIE // bit 6
27185 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
27187 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
27188 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
27189 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
27190 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
27191 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
27192 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
27193 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
27194 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
27195 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
27196 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
27197 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
27198 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
27199 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
27200 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
27201 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
27202 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
27204 #define BF SSP1STATbits.BF // bit 0
27205 #define UA SSP1STATbits.UA // bit 1
27206 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
27207 #define S SSP1STATbits.S // bit 3
27208 #define P SSP1STATbits.P // bit 4
27209 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
27210 #define CKE SSP1STATbits.CKE // bit 6
27211 #define SMP SSP1STATbits.SMP // bit 7
27213 #define C STATUSbits.C // bit 0
27214 #define DC STATUSbits.DC // bit 1
27215 #define Z STATUSbits.Z // bit 2
27216 #define NOT_PD STATUSbits.NOT_PD // bit 3
27217 #define NOT_TO STATUSbits.NOT_TO // bit 4
27219 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
27220 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
27221 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
27223 #define GSS0 T1GCONbits.GSS0 // bit 0, shadows bit in T1GCONbits
27224 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0, shadows bit in T1GCONbits
27225 #define GSS1 T1GCONbits.GSS1 // bit 1, shadows bit in T1GCONbits
27226 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1, shadows bit in T1GCONbits
27227 #define GVAL T1GCONbits.GVAL // bit 2, shadows bit in T1GCONbits
27228 #define T1GVAL T1GCONbits.T1GVAL // bit 2, shadows bit in T1GCONbits
27229 #define GGO_NOT_DONE T1GCONbits.GGO_NOT_DONE // bit 3, shadows bit in T1GCONbits
27230 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3, shadows bit in T1GCONbits
27231 #define GSPM T1GCONbits.GSPM // bit 4, shadows bit in T1GCONbits
27232 #define T1GSPM T1GCONbits.T1GSPM // bit 4, shadows bit in T1GCONbits
27233 #define GTM T1GCONbits.GTM // bit 5, shadows bit in T1GCONbits
27234 #define T1GTM T1GCONbits.T1GTM // bit 5, shadows bit in T1GCONbits
27235 #define GPOL T1GCONbits.GPOL // bit 6, shadows bit in T1GCONbits
27236 #define T1GPOL T1GCONbits.T1GPOL // bit 6, shadows bit in T1GCONbits
27237 #define GE T1GCONbits.GE // bit 7, shadows bit in T1GCONbits
27238 #define T1GE T1GCONbits.T1GE // bit 7, shadows bit in T1GCONbits
27239 #define TMR1GE T1GCONbits.TMR1GE // bit 7, shadows bit in T1GCONbits
27241 #define RSEL0 T2RSTbits.RSEL0 // bit 0, shadows bit in T2RSTbits
27242 #define T2RSEL0 T2RSTbits.T2RSEL0 // bit 0, shadows bit in T2RSTbits
27243 #define RSEL1 T2RSTbits.RSEL1 // bit 1, shadows bit in T2RSTbits
27244 #define T2RSEL1 T2RSTbits.T2RSEL1 // bit 1, shadows bit in T2RSTbits
27245 #define RSEL2 T2RSTbits.RSEL2 // bit 2, shadows bit in T2RSTbits
27246 #define T2RSEL2 T2RSTbits.T2RSEL2 // bit 2, shadows bit in T2RSTbits
27247 #define RSEL3 T2RSTbits.RSEL3 // bit 3, shadows bit in T2RSTbits
27248 #define T2RSEL3 T2RSTbits.T2RSEL3 // bit 3, shadows bit in T2RSTbits
27249 #define RSEL4 T2RSTbits.RSEL4 // bit 4, shadows bit in T2RSTbits
27250 #define T2RSEL4 T2RSTbits.T2RSEL4 // bit 4, shadows bit in T2RSTbits
27252 #define TRISA0 TRISAbits.TRISA0 // bit 0
27253 #define TRISA1 TRISAbits.TRISA1 // bit 1
27254 #define TRISA2 TRISAbits.TRISA2 // bit 2
27255 #define TRISA3 TRISAbits.TRISA3 // bit 3
27256 #define TRISA4 TRISAbits.TRISA4 // bit 4
27257 #define TRISA5 TRISAbits.TRISA5 // bit 5
27258 #define TRISA6 TRISAbits.TRISA6 // bit 6
27259 #define TRISA7 TRISAbits.TRISA7 // bit 7
27261 #define TRISB0 TRISBbits.TRISB0 // bit 0
27262 #define TRISB1 TRISBbits.TRISB1 // bit 1
27263 #define TRISB2 TRISBbits.TRISB2 // bit 2
27264 #define TRISB3 TRISBbits.TRISB3 // bit 3
27265 #define TRISB4 TRISBbits.TRISB4 // bit 4
27266 #define TRISB5 TRISBbits.TRISB5 // bit 5
27267 #define TRISB6 TRISBbits.TRISB6 // bit 6
27268 #define TRISB7 TRISBbits.TRISB7 // bit 7
27270 #define TRISC0 TRISCbits.TRISC0 // bit 0
27271 #define TRISC1 TRISCbits.TRISC1 // bit 1
27272 #define TRISC2 TRISCbits.TRISC2 // bit 2
27273 #define TRISC3 TRISCbits.TRISC3 // bit 3
27274 #define TRISC4 TRISCbits.TRISC4 // bit 4
27275 #define TRISC5 TRISCbits.TRISC5 // bit 5
27276 #define TRISC6 TRISCbits.TRISC6 // bit 6
27277 #define TRISC7 TRISCbits.TRISC7 // bit 7
27279 #define TRISD0 TRISDbits.TRISD0 // bit 0
27280 #define TRISD1 TRISDbits.TRISD1 // bit 1
27281 #define TRISD2 TRISDbits.TRISD2 // bit 2
27282 #define TRISD3 TRISDbits.TRISD3 // bit 3
27283 #define TRISD4 TRISDbits.TRISD4 // bit 4
27284 #define TRISD5 TRISDbits.TRISD5 // bit 5
27285 #define TRISD6 TRISDbits.TRISD6 // bit 6
27286 #define TRISD7 TRISDbits.TRISD7 // bit 7
27288 #define TRISE0 TRISEbits.TRISE0 // bit 0
27289 #define TRISE1 TRISEbits.TRISE1 // bit 1
27290 #define TRISE2 TRISEbits.TRISE2 // bit 2
27291 #define TRISE3 TRISEbits.TRISE3 // bit 3
27293 #define reserved VREGCONbits.reserved // bit 0
27294 #define VREGPM VREGCONbits.VREGPM // bit 1
27296 #define SWDTEN WDTCONbits.SWDTEN // bit 0
27297 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
27298 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
27299 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
27300 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
27301 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
27303 #define WPUA0 WPUAbits.WPUA0 // bit 0
27304 #define WPUA1 WPUAbits.WPUA1 // bit 1
27305 #define WPUA2 WPUAbits.WPUA2 // bit 2
27306 #define WPUA3 WPUAbits.WPUA3 // bit 3
27307 #define WPUA4 WPUAbits.WPUA4 // bit 4
27308 #define WPUA5 WPUAbits.WPUA5 // bit 5
27309 #define WPUA6 WPUAbits.WPUA6 // bit 6
27310 #define WPUA7 WPUAbits.WPUA7 // bit 7
27312 #define WPUB0 WPUBbits.WPUB0 // bit 0
27313 #define WPUB1 WPUBbits.WPUB1 // bit 1
27314 #define WPUB2 WPUBbits.WPUB2 // bit 2
27315 #define WPUB3 WPUBbits.WPUB3 // bit 3
27316 #define WPUB4 WPUBbits.WPUB4 // bit 4
27317 #define WPUB5 WPUBbits.WPUB5 // bit 5
27318 #define WPUB6 WPUBbits.WPUB6 // bit 6
27319 #define WPUB7 WPUBbits.WPUB7 // bit 7
27321 #define WPUC0 WPUCbits.WPUC0 // bit 0
27322 #define WPUC1 WPUCbits.WPUC1 // bit 1
27323 #define WPUC2 WPUCbits.WPUC2 // bit 2
27324 #define WPUC3 WPUCbits.WPUC3 // bit 3
27325 #define WPUC4 WPUCbits.WPUC4 // bit 4
27326 #define WPUC5 WPUCbits.WPUC5 // bit 5
27327 #define WPUC6 WPUCbits.WPUC6 // bit 6
27328 #define WPUC7 WPUCbits.WPUC7 // bit 7
27330 #define WPUD0 WPUDbits.WPUD0 // bit 0
27331 #define WPUD1 WPUDbits.WPUD1 // bit 1
27332 #define WPUD2 WPUDbits.WPUD2 // bit 2
27333 #define WPUD3 WPUDbits.WPUD3 // bit 3
27334 #define WPUD4 WPUDbits.WPUD4 // bit 4
27335 #define WPUD5 WPUDbits.WPUD5 // bit 5
27336 #define WPUD6 WPUDbits.WPUD6 // bit 6
27337 #define WPUD7 WPUDbits.WPUD7 // bit 7
27339 #define WPUE0 WPUEbits.WPUE0 // bit 0
27340 #define WPUE1 WPUEbits.WPUE1 // bit 1
27341 #define WPUE2 WPUEbits.WPUE2 // bit 2
27342 #define WPUE3 WPUEbits.WPUE3 // bit 3
27344 #define ZCD1INTN ZCD1CONbits.ZCD1INTN // bit 0
27345 #define ZCD1INTP ZCD1CONbits.ZCD1INTP // bit 1
27346 #define ZCD1POL ZCD1CONbits.ZCD1POL // bit 4
27347 #define ZCD1OUT ZCD1CONbits.ZCD1OUT // bit 5
27348 #define ZCD1EN ZCD1CONbits.ZCD1EN // bit 7
27350 #endif // #ifndef NO_BIT_DEFINES
27352 #endif // #ifndef __PIC16F1777_H__