2 * This declarations of the PIC16F1778 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:16 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F1778_H__
26 #define __PIC16F1778_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTB_ADDR 0x000D
52 #define PORTC_ADDR 0x000E
53 #define PORTE_ADDR 0x0010
54 #define PIR1_ADDR 0x0011
55 #define PIR2_ADDR 0x0012
56 #define PIR3_ADDR 0x0013
57 #define PIR4_ADDR 0x0014
58 #define PIR5_ADDR 0x0015
59 #define PIR6_ADDR 0x0016
60 #define TMR0_ADDR 0x0017
61 #define TMR1_ADDR 0x0018
62 #define TMR1L_ADDR 0x0018
63 #define TMR1H_ADDR 0x0019
64 #define T1CON_ADDR 0x001A
65 #define T1GCON_ADDR 0x001B
66 #define TMR3_ADDR 0x001C
67 #define TMR3L_ADDR 0x001C
68 #define TMR3H_ADDR 0x001D
69 #define T3CON_ADDR 0x001E
70 #define T3GCON_ADDR 0x001F
71 #define TRISA_ADDR 0x008C
72 #define TRISB_ADDR 0x008D
73 #define TRISC_ADDR 0x008E
74 #define TRISE_ADDR 0x0090
75 #define PIE1_ADDR 0x0091
76 #define PIE2_ADDR 0x0092
77 #define PIE3_ADDR 0x0093
78 #define PIE4_ADDR 0x0094
79 #define PIE5_ADDR 0x0095
80 #define PIE6_ADDR 0x0096
81 #define OPTION_REG_ADDR 0x0097
82 #define PCON_ADDR 0x0098
83 #define WDTCON_ADDR 0x0099
84 #define OSCTUNE_ADDR 0x009A
85 #define OSCCON_ADDR 0x009B
86 #define OSCSTAT_ADDR 0x009C
87 #define BORCON_ADDR 0x009D
88 #define FVRCON_ADDR 0x009E
89 #define ZCD1CON_ADDR 0x009F
90 #define LATA_ADDR 0x010C
91 #define LATB_ADDR 0x010D
92 #define LATC_ADDR 0x010E
93 #define CMOUT_ADDR 0x0111
94 #define CM1CON0_ADDR 0x0112
95 #define CM1CON1_ADDR 0x0113
96 #define CM1NSEL_ADDR 0x0114
97 #define CM1PSEL_ADDR 0x0115
98 #define CM2CON0_ADDR 0x0116
99 #define CM2CON1_ADDR 0x0117
100 #define CM2NSEL_ADDR 0x0118
101 #define CM2PSEL_ADDR 0x0119
102 #define CM3CON0_ADDR 0x011A
103 #define CM3CON1_ADDR 0x011B
104 #define CM3NSEL_ADDR 0x011C
105 #define CM3PSEL_ADDR 0x011D
106 #define ANSELA_ADDR 0x018C
107 #define ANSELB_ADDR 0x018D
108 #define ANSELC_ADDR 0x018E
109 #define PMADR_ADDR 0x0191
110 #define PMADRL_ADDR 0x0191
111 #define PMADRH_ADDR 0x0192
112 #define PMDAT_ADDR 0x0193
113 #define PMDATL_ADDR 0x0193
114 #define PMDATH_ADDR 0x0194
115 #define PMCON1_ADDR 0x0195
116 #define PMCON2_ADDR 0x0196
117 #define VREGCON_ADDR 0x0197
118 #define RC1REG_ADDR 0x0199
119 #define RCREG_ADDR 0x0199
120 #define RCREG1_ADDR 0x0199
121 #define TX1REG_ADDR 0x019A
122 #define TXREG_ADDR 0x019A
123 #define TXREG1_ADDR 0x019A
124 #define SP1BRG_ADDR 0x019B
125 #define SP1BRGL_ADDR 0x019B
126 #define SPBRG_ADDR 0x019B
127 #define SPBRG1_ADDR 0x019B
128 #define SPBRGL_ADDR 0x019B
129 #define SP1BRGH_ADDR 0x019C
130 #define SPBRGH_ADDR 0x019C
131 #define SPBRGH1_ADDR 0x019C
132 #define RC1STA_ADDR 0x019D
133 #define RCSTA_ADDR 0x019D
134 #define RCSTA1_ADDR 0x019D
135 #define TX1STA_ADDR 0x019E
136 #define TXSTA_ADDR 0x019E
137 #define TXSTA1_ADDR 0x019E
138 #define BAUD1CON_ADDR 0x019F
139 #define BAUDCON_ADDR 0x019F
140 #define BAUDCON1_ADDR 0x019F
141 #define BAUDCTL_ADDR 0x019F
142 #define BAUDCTL1_ADDR 0x019F
143 #define WPUA_ADDR 0x020C
144 #define WPUB_ADDR 0x020D
145 #define WPUC_ADDR 0x020E
146 #define WPUE_ADDR 0x0210
147 #define SSP1BUF_ADDR 0x0211
148 #define SSPBUF_ADDR 0x0211
149 #define SSP1ADD_ADDR 0x0212
150 #define SSPADD_ADDR 0x0212
151 #define SSP1MSK_ADDR 0x0213
152 #define SSPMSK_ADDR 0x0213
153 #define SSP1STAT_ADDR 0x0214
154 #define SSPSTAT_ADDR 0x0214
155 #define SSP1CON_ADDR 0x0215
156 #define SSP1CON1_ADDR 0x0215
157 #define SSPCON_ADDR 0x0215
158 #define SSPCON1_ADDR 0x0215
159 #define SSP1CON2_ADDR 0x0216
160 #define SSPCON2_ADDR 0x0216
161 #define SSP1CON3_ADDR 0x0217
162 #define SSPCON3_ADDR 0x0217
163 #define MD3CON0_ADDR 0x021B
164 #define MD3CON1_ADDR 0x021C
165 #define MD3SRC_ADDR 0x021D
166 #define MD3CARL_ADDR 0x021E
167 #define MD3CARH_ADDR 0x021F
168 #define ODCONA_ADDR 0x028C
169 #define ODCONB_ADDR 0x028D
170 #define ODCONC_ADDR 0x028E
171 #define CCPR1_ADDR 0x0291
172 #define CCPR1L_ADDR 0x0291
173 #define CCPR1H_ADDR 0x0292
174 #define CCP1CON_ADDR 0x0293
175 #define CCP1CAP_ADDR 0x0294
176 #define CCPR2_ADDR 0x0295
177 #define CCPR2L_ADDR 0x0295
178 #define CCPR2H_ADDR 0x0296
179 #define CCP2CON_ADDR 0x0297
180 #define CCP2CAP_ADDR 0x0298
181 #define CCPR7_ADDR 0x0299
182 #define CCPR7L_ADDR 0x0299
183 #define CCPR7H_ADDR 0x029A
184 #define CCP7CON_ADDR 0x029B
185 #define CCP7CAP_ADDR 0x029C
186 #define CCPTMRS1_ADDR 0x029E
187 #define CCPTMRS2_ADDR 0x029F
188 #define SLRCONA_ADDR 0x030C
189 #define SLRCONB_ADDR 0x030D
190 #define SLRCONC_ADDR 0x030E
191 #define MD1CON0_ADDR 0x0315
192 #define MD1CON1_ADDR 0x0316
193 #define MD1SRC_ADDR 0x0317
194 #define MD1CARL_ADDR 0x0318
195 #define MD1CARH_ADDR 0x0319
196 #define MD2CON0_ADDR 0x031B
197 #define MD2CON1_ADDR 0x031C
198 #define MD2SRC_ADDR 0x031D
199 #define MD2CARL_ADDR 0x031E
200 #define MD2CARH_ADDR 0x031F
201 #define INLVLA_ADDR 0x038C
202 #define INLVLB_ADDR 0x038D
203 #define INLVLC_ADDR 0x038E
204 #define INLVE_ADDR 0x0390
205 #define IOCAP_ADDR 0x0391
206 #define IOCAN_ADDR 0x0392
207 #define IOCAF_ADDR 0x0393
208 #define IOCBP_ADDR 0x0394
209 #define IOCBN_ADDR 0x0395
210 #define IOCBF_ADDR 0x0396
211 #define IOCCP_ADDR 0x0397
212 #define IOCCN_ADDR 0x0398
213 #define IOCCF_ADDR 0x0399
214 #define IOCEP_ADDR 0x039D
215 #define IOCEN_ADDR 0x039E
216 #define IOCEF_ADDR 0x039F
217 #define HIDRVB_ADDR 0x040D
218 #define TMR5_ADDR 0x040F
219 #define TMR5L_ADDR 0x040F
220 #define TMR5H_ADDR 0x0410
221 #define T5CON_ADDR 0x0411
222 #define T5GCON_ADDR 0x0412
223 #define T4TMR_ADDR 0x0413
224 #define TMR4_ADDR 0x0413
225 #define PR4_ADDR 0x0414
226 #define T4PR_ADDR 0x0414
227 #define T4CON_ADDR 0x0415
228 #define T4HLT_ADDR 0x0416
229 #define T4CLKCON_ADDR 0x0417
230 #define T4RST_ADDR 0x0418
231 #define T6TMR_ADDR 0x041A
232 #define TMR6_ADDR 0x041A
233 #define PR6_ADDR 0x041B
234 #define T6PR_ADDR 0x041B
235 #define T6CON_ADDR 0x041C
236 #define T6HLT_ADDR 0x041D
237 #define T6CLKCON_ADDR 0x041E
238 #define T6RST_ADDR 0x041F
239 #define ADRESL_ADDR 0x048E
240 #define ADRESH_ADDR 0x048F
241 #define ADCON0_ADDR 0x0490
242 #define ADCON1_ADDR 0x0491
243 #define ADCON2_ADDR 0x0492
244 #define T2TMR_ADDR 0x0493
245 #define TMR2_ADDR 0x0493
246 #define PR2_ADDR 0x0494
247 #define T2PR_ADDR 0x0494
248 #define T2CON_ADDR 0x0495
249 #define T2HLT_ADDR 0x0496
250 #define T2CLKCON_ADDR 0x0497
251 #define T2RST_ADDR 0x0498
252 #define T8TMR_ADDR 0x049A
253 #define TMR8_ADDR 0x049A
254 #define PR8_ADDR 0x049B
255 #define T8PR_ADDR 0x049B
256 #define T8CON_ADDR 0x049C
257 #define T8HLT_ADDR 0x049D
258 #define T8CLKCON_ADDR 0x049E
259 #define T8RST_ADDR 0x049F
260 #define OPA1NCHS_ADDR 0x050F
261 #define OPA1PCHS_ADDR 0x0510
262 #define OPA1CON_ADDR 0x0511
263 #define OPA1ORS_ADDR 0x0512
264 #define OPA2NCHS_ADDR 0x0513
265 #define OPA2PCHS_ADDR 0x0514
266 #define OPA2CON_ADDR 0x0515
267 #define OPA2ORS_ADDR 0x0516
268 #define OPA3NCHS_ADDR 0x0517
269 #define OPA3PCHS_ADDR 0x0518
270 #define OPA3CON_ADDR 0x0519
271 #define OPA3ORS_ADDR 0x051A
272 #define DACLD_ADDR 0x058D
273 #define DAC1CON0_ADDR 0x058E
274 #define DAC1CON1_ADDR 0x058F
275 #define DAC1REF_ADDR 0x058F
276 #define DAC1REFL_ADDR 0x058F
277 #define DAC1CON2_ADDR 0x0590
278 #define DAC1REFH_ADDR 0x0590
279 #define DAC2CON0_ADDR 0x0591
280 #define DAC2CON1_ADDR 0x0592
281 #define DAC2REF_ADDR 0x0592
282 #define DAC2REFL_ADDR 0x0592
283 #define DAC2CON2_ADDR 0x0593
284 #define DAC2REFH_ADDR 0x0593
285 #define DAC3CON0_ADDR 0x0594
286 #define DAC3CON1_ADDR 0x0595
287 #define DAC3REF_ADDR 0x0595
288 #define DAC4CON0_ADDR 0x0596
289 #define DAC4CON1_ADDR 0x0597
290 #define DAC4REF_ADDR 0x0597
291 #define DAC5CON0_ADDR 0x0598
292 #define DAC5CON1_ADDR 0x0599
293 #define DAC5REF_ADDR 0x0599
294 #define DAC5REFL_ADDR 0x0599
295 #define DAC5CON2_ADDR 0x059A
296 #define DAC5REFH_ADDR 0x059A
297 #define DAC7CON0_ADDR 0x059E
298 #define DAC7CON1_ADDR 0x059F
299 #define DAC7REF_ADDR 0x059F
300 #define PWM3DCL_ADDR 0x0614
301 #define PWM3DCH_ADDR 0x0615
302 #define PWM3CON_ADDR 0x0616
303 #define PWM4DCL_ADDR 0x0617
304 #define PWM4DCH_ADDR 0x0618
305 #define PWM4CON_ADDR 0x0619
306 #define PWM9DCL_ADDR 0x061A
307 #define PWM9DCH_ADDR 0x061B
308 #define PWM9CON_ADDR 0x061C
309 #define COG1PHR_ADDR 0x068D
310 #define COG1PHF_ADDR 0x068E
311 #define COG1BLKR_ADDR 0x068F
312 #define COG1BLKF_ADDR 0x0690
313 #define COG1DBR_ADDR 0x0691
314 #define COG1DBF_ADDR 0x0692
315 #define COG1CON0_ADDR 0x0693
316 #define COG1CON1_ADDR 0x0694
317 #define COG1RIS0_ADDR 0x0695
318 #define COG1RIS1_ADDR 0x0696
319 #define COG1RSIM0_ADDR 0x0697
320 #define COG1RSIM1_ADDR 0x0698
321 #define COG1FIS0_ADDR 0x0699
322 #define COG1FIS1_ADDR 0x069A
323 #define COG1FSIM0_ADDR 0x069B
324 #define COG1FSIM1_ADDR 0x069C
325 #define COG1ASD0_ADDR 0x069D
326 #define COG1ASD1_ADDR 0x069E
327 #define COG1STR_ADDR 0x069F
328 #define COG2PHR_ADDR 0x070D
329 #define COG2PHF_ADDR 0x070E
330 #define COG2BLKR_ADDR 0x070F
331 #define COG2BLKF_ADDR 0x0710
332 #define COG2DBR_ADDR 0x0711
333 #define COG2DBF_ADDR 0x0712
334 #define COG2CON0_ADDR 0x0713
335 #define COG2CON1_ADDR 0x0714
336 #define COG2RIS0_ADDR 0x0715
337 #define COG2RIS1_ADDR 0x0716
338 #define COG2RSIM0_ADDR 0x0717
339 #define COG2RSIM1_ADDR 0x0718
340 #define COG2FIS0_ADDR 0x0719
341 #define COG2FIS1_ADDR 0x071A
342 #define COG2FSIM0_ADDR 0x071B
343 #define COG2FSIM1_ADDR 0x071C
344 #define COG2ASD0_ADDR 0x071D
345 #define COG2ASD1_ADDR 0x071E
346 #define COG2STR_ADDR 0x071F
347 #define PRG1RTSS_ADDR 0x078E
348 #define PRG1FTSS_ADDR 0x078F
349 #define PRG1INS_ADDR 0x0790
350 #define PRG1CON0_ADDR 0x0791
351 #define PRG1CON1_ADDR 0x0792
352 #define PRG1CON2_ADDR 0x0793
353 #define PRG2RTSS_ADDR 0x0794
354 #define PRG2FTSS_ADDR 0x0795
355 #define PRG2INS_ADDR 0x0796
356 #define PRG2CON0_ADDR 0x0797
357 #define PRG2CON1_ADDR 0x0798
358 #define PRG2CON2_ADDR 0x0799
359 #define PRG3RTSS_ADDR 0x079A
360 #define PRG3FTSS_ADDR 0x079B
361 #define PRG3INS_ADDR 0x079C
362 #define PRG3CON0_ADDR 0x079D
363 #define PRG3CON1_ADDR 0x079E
364 #define PRG3CON2_ADDR 0x079F
365 #define COG3PHR_ADDR 0x080D
366 #define COG3PHF_ADDR 0x080E
367 #define COG3BLKR_ADDR 0x080F
368 #define COG3BLKF_ADDR 0x0810
369 #define COG3DBR_ADDR 0x0811
370 #define COG3DBF_ADDR 0x0812
371 #define COG3CON0_ADDR 0x0813
372 #define COG3CON1_ADDR 0x0814
373 #define COG3RIS0_ADDR 0x0815
374 #define COG3RIS1_ADDR 0x0816
375 #define COG3RSIM0_ADDR 0x0817
376 #define COG3RSIM1_ADDR 0x0818
377 #define COG3FIS0_ADDR 0x0819
378 #define COG3FIS1_ADDR 0x081A
379 #define COG3FSIM0_ADDR 0x081B
380 #define COG3FSIM1_ADDR 0x081C
381 #define COG3ASD0_ADDR 0x081D
382 #define COG3ASD1_ADDR 0x081E
383 #define COG3STR_ADDR 0x081F
384 #define CM4CON0_ADDR 0x090C
385 #define CM4CON1_ADDR 0x090D
386 #define CM4NSEL_ADDR 0x090E
387 #define CM4PSEL_ADDR 0x090F
388 #define CM5CON0_ADDR 0x0910
389 #define CM5CON1_ADDR 0x0911
390 #define CM5NSEL_ADDR 0x0912
391 #define CM5PSEL_ADDR 0x0913
392 #define CM6CON0_ADDR 0x0914
393 #define CM6CON1_ADDR 0x0915
394 #define CM6NSEL_ADDR 0x0916
395 #define CM6PSEL_ADDR 0x0917
396 #define PWMEN_ADDR 0x0D8E
397 #define PWMLD_ADDR 0x0D8F
398 #define PWMOUT_ADDR 0x0D90
399 #define PWM5PH_ADDR 0x0D91
400 #define PWM5PHL_ADDR 0x0D91
401 #define PWM5PHH_ADDR 0x0D92
402 #define PWM5DC_ADDR 0x0D93
403 #define PWM5DCL_ADDR 0x0D93
404 #define PWM5DCH_ADDR 0x0D94
405 #define PWM5PR_ADDR 0x0D95
406 #define PWM5PRL_ADDR 0x0D95
407 #define PWM5PRH_ADDR 0x0D96
408 #define PWM5OF_ADDR 0x0D97
409 #define PWM5OFL_ADDR 0x0D97
410 #define PWM5OFH_ADDR 0x0D98
411 #define PWM5TMR_ADDR 0x0D99
412 #define PWM5TMRL_ADDR 0x0D99
413 #define PWM5TMRH_ADDR 0x0D9A
414 #define PWM5CON_ADDR 0x0D9B
415 #define PWM5INTCON_ADDR 0x0D9C
416 #define PWM5INTE_ADDR 0x0D9C
417 #define PWM5INTF_ADDR 0x0D9D
418 #define PWM5INTFLG_ADDR 0x0D9D
419 #define PWM5CLKCON_ADDR 0x0D9E
420 #define PWM5LDCON_ADDR 0x0D9F
421 #define PWM5OFCON_ADDR 0x0DA0
422 #define PWM6PH_ADDR 0x0DA1
423 #define PWM6PHL_ADDR 0x0DA1
424 #define PWM6PHH_ADDR 0x0DA2
425 #define PWM6DC_ADDR 0x0DA3
426 #define PWM6DCL_ADDR 0x0DA3
427 #define PWM6DCH_ADDR 0x0DA4
428 #define PWM6PR_ADDR 0x0DA5
429 #define PWM6PRL_ADDR 0x0DA5
430 #define PWM6PRH_ADDR 0x0DA6
431 #define PWM6OF_ADDR 0x0DA7
432 #define PWM6OFL_ADDR 0x0DA7
433 #define PWM6OFH_ADDR 0x0DA8
434 #define PWM6TMR_ADDR 0x0DA9
435 #define PWM6TMRL_ADDR 0x0DA9
436 #define PWM6TMRH_ADDR 0x0DAA
437 #define PWM6CON_ADDR 0x0DAB
438 #define PWM6INTCON_ADDR 0x0DAC
439 #define PWM6INTE_ADDR 0x0DAC
440 #define PWM6INTF_ADDR 0x0DAD
441 #define PWM6INTFLG_ADDR 0x0DAD
442 #define PWM6CLKCON_ADDR 0x0DAE
443 #define PWM6LDCON_ADDR 0x0DAF
444 #define PWM6OFCON_ADDR 0x0DB0
445 #define PWM11PH_ADDR 0x0DB1
446 #define PWM11PHL_ADDR 0x0DB1
447 #define PWM11PHH_ADDR 0x0DB2
448 #define PWM11DC_ADDR 0x0DB3
449 #define PWM11DCL_ADDR 0x0DB3
450 #define PWM11DCH_ADDR 0x0DB4
451 #define PWM11PR_ADDR 0x0DB5
452 #define PWM11PRL_ADDR 0x0DB5
453 #define PWM11PRH_ADDR 0x0DB6
454 #define PWM11OF_ADDR 0x0DB7
455 #define PWM11OFL_ADDR 0x0DB7
456 #define PWM11OFH_ADDR 0x0DB8
457 #define PWM11TMR_ADDR 0x0DB9
458 #define PWM11TMRL_ADDR 0x0DB9
459 #define PWM11TMRH_ADDR 0x0DBA
460 #define PWM11CON_ADDR 0x0DBB
461 #define PWM11INTCON_ADDR 0x0DBC
462 #define PWM11INTE_ADDR 0x0DBC
463 #define PWM11INTF_ADDR 0x0DBD
464 #define PWM11INTFLG_ADDR 0x0DBD
465 #define PWM11CLKCON_ADDR 0x0DBE
466 #define PWM11LDCON_ADDR 0x0DBF
467 #define PWM11OFCON_ADDR 0x0DC0
468 #define PPSLOCK_ADDR 0x0E0C
469 #define INTPPS_ADDR 0x0E0D
470 #define T0CKIPPS_ADDR 0x0E0E
471 #define T1CKIPPS_ADDR 0x0E0F
472 #define T1GPPS_ADDR 0x0E10
473 #define T3CKIPPS_ADDR 0x0E11
474 #define T3GPPS_ADDR 0x0E12
475 #define T5CKIPPS_ADDR 0x0E13
476 #define T5GPPS_ADDR 0x0E14
477 #define T2CKIPPS_ADDR 0x0E15
478 #define T4CKIPPS_ADDR 0x0E16
479 #define T6CKIPPS_ADDR 0x0E17
480 #define T8CKIPPS_ADDR 0x0E18
481 #define CCP1PPS_ADDR 0x0E19
482 #define CCP2PPS_ADDR 0x0E1A
483 #define CCP7PPS_ADDR 0x0E1B
484 #define COG1INPPS_ADDR 0x0E1D
485 #define COG2INPPS_ADDR 0x0E1E
486 #define COG3INPPS_ADDR 0x0E1F
487 #define MD1CLPPS_ADDR 0x0E21
488 #define MD1CHPPS_ADDR 0x0E22
489 #define MD1MODPPS_ADDR 0x0E23
490 #define MD2CLPPS_ADDR 0x0E24
491 #define MD2CHPPS_ADDR 0x0E25
492 #define MD2MODPPS_ADDR 0x0E26
493 #define MD3CLPPS_ADDR 0x0E27
494 #define MD3CHPPS_ADDR 0x0E28
495 #define MD3MODPPS_ADDR 0x0E29
496 #define PRG1RPPS_ADDR 0x0E2D
497 #define PRG1FPPS_ADDR 0x0E2E
498 #define PRG2RPPS_ADDR 0x0E2F
499 #define PRG2FPPS_ADDR 0x0E30
500 #define PRG3RPPS_ADDR 0x0E31
501 #define PRG3FPPS_ADDR 0x0E32
502 #define CLCIN0PPS_ADDR 0x0E35
503 #define CLCIN1PPS_ADDR 0x0E36
504 #define CLCIN2PPS_ADDR 0x0E37
505 #define CLCIN3PPS_ADDR 0x0E38
506 #define ADCACTPPS_ADDR 0x0E39
507 #define SSPCLKPPS_ADDR 0x0E3A
508 #define SSPDATPPS_ADDR 0x0E3B
509 #define SSPSSPPS_ADDR 0x0E3C
510 #define RXPPS_ADDR 0x0E3D
511 #define CKPPS_ADDR 0x0E3E
512 #define RA0PPS_ADDR 0x0E90
513 #define RA1PPS_ADDR 0x0E91
514 #define RA2PPS_ADDR 0x0E92
515 #define RA3PPS_ADDR 0x0E93
516 #define RA4PPS_ADDR 0x0E94
517 #define RA5PPS_ADDR 0x0E95
518 #define RA6PPS_ADDR 0x0E96
519 #define RA7PPS_ADDR 0x0E97
520 #define RB0PPS_ADDR 0x0E98
521 #define RB1PPS_ADDR 0x0E99
522 #define RB2PPS_ADDR 0x0E9A
523 #define RB3PPS_ADDR 0x0E9B
524 #define RB4PPS_ADDR 0x0E9C
525 #define RB5PPS_ADDR 0x0E9D
526 #define RB6PPS_ADDR 0x0E9E
527 #define RB7PPS_ADDR 0x0E9F
528 #define RC0PPS_ADDR 0x0EA0
529 #define RC1PPS_ADDR 0x0EA1
530 #define RC2PPS_ADDR 0x0EA2
531 #define RC3PPS_ADDR 0x0EA3
532 #define RC4PPS_ADDR 0x0EA4
533 #define RC5PPS_ADDR 0x0EA5
534 #define RC6PPS_ADDR 0x0EA6
535 #define RC7PPS_ADDR 0x0EA7
536 #define CLCDATA_ADDR 0x0F0F
537 #define CLC1CON_ADDR 0x0F10
538 #define CLC1POL_ADDR 0x0F11
539 #define CLC1SEL0_ADDR 0x0F12
540 #define CLC1SEL1_ADDR 0x0F13
541 #define CLC1SEL2_ADDR 0x0F14
542 #define CLC1SEL3_ADDR 0x0F15
543 #define CLC1GLS0_ADDR 0x0F16
544 #define CLC1GLS1_ADDR 0x0F17
545 #define CLC1GLS2_ADDR 0x0F18
546 #define CLC1GLS3_ADDR 0x0F19
547 #define CLC2CON_ADDR 0x0F1A
548 #define CLC2POL_ADDR 0x0F1B
549 #define CLC2SEL0_ADDR 0x0F1C
550 #define CLC2SEL1_ADDR 0x0F1D
551 #define CLC2SEL2_ADDR 0x0F1E
552 #define CLC2SEL3_ADDR 0x0F1F
553 #define CLC2GLS0_ADDR 0x0F20
554 #define CLC2GLS1_ADDR 0x0F21
555 #define CLC2GLS2_ADDR 0x0F22
556 #define CLC2GLS3_ADDR 0x0F23
557 #define CLC3CON_ADDR 0x0F24
558 #define CLC3POL_ADDR 0x0F25
559 #define CLC3SEL0_ADDR 0x0F26
560 #define CLC3SEL1_ADDR 0x0F27
561 #define CLC3SEL2_ADDR 0x0F28
562 #define CLC3SEL3_ADDR 0x0F29
563 #define CLC3GLS0_ADDR 0x0F2A
564 #define CLC3GLS1_ADDR 0x0F2B
565 #define CLC3GLS2_ADDR 0x0F2C
566 #define CLC3GLS3_ADDR 0x0F2D
567 #define CLC4CON_ADDR 0x0F2E
568 #define CLC4POL_ADDR 0x0F2F
569 #define CLC4SEL0_ADDR 0x0F30
570 #define CLC4SEL1_ADDR 0x0F31
571 #define CLC4SEL2_ADDR 0x0F32
572 #define CLC4SEL3_ADDR 0x0F33
573 #define CLC4GLS0_ADDR 0x0F34
574 #define CLC4GLS1_ADDR 0x0F35
575 #define CLC4GLS2_ADDR 0x0F36
576 #define CLC4GLS3_ADDR 0x0F37
577 #define STATUS_SHAD_ADDR 0x0FE4
578 #define WREG_SHAD_ADDR 0x0FE5
579 #define BSR_SHAD_ADDR 0x0FE6
580 #define PCLATH_SHAD_ADDR 0x0FE7
581 #define FSR0L_SHAD_ADDR 0x0FE8
582 #define FSR0H_SHAD_ADDR 0x0FE9
583 #define FSR1L_SHAD_ADDR 0x0FEA
584 #define FSR1H_SHAD_ADDR 0x0FEB
585 #define STKPTR_ADDR 0x0FED
586 #define TOSL_ADDR 0x0FEE
587 #define TOSH_ADDR 0x0FEF
589 #endif // #ifndef NO_ADDR_DEFINES
591 //==============================================================================
593 // Register Definitions
595 //==============================================================================
597 extern __at(0x0000) __sfr INDF0
;
598 extern __at(0x0001) __sfr INDF1
;
599 extern __at(0x0002) __sfr PCL
;
601 //==============================================================================
604 extern __at(0x0003) __sfr STATUS
;
618 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
626 //==============================================================================
628 extern __at(0x0004) __sfr FSR0
;
629 extern __at(0x0004) __sfr FSR0L
;
630 extern __at(0x0005) __sfr FSR0H
;
631 extern __at(0x0006) __sfr FSR1
;
632 extern __at(0x0006) __sfr FSR1L
;
633 extern __at(0x0007) __sfr FSR1H
;
635 //==============================================================================
638 extern __at(0x0008) __sfr BSR
;
661 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
669 //==============================================================================
671 extern __at(0x0009) __sfr WREG
;
672 extern __at(0x000A) __sfr PCLATH
;
674 //==============================================================================
677 extern __at(0x000B) __sfr INTCON
;
706 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
719 //==============================================================================
722 //==============================================================================
725 extern __at(0x000C) __sfr PORTA
;
739 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
750 //==============================================================================
753 //==============================================================================
756 extern __at(0x000D) __sfr PORTB
;
770 extern __at(0x000D) volatile __PORTBbits_t PORTBbits
;
781 //==============================================================================
784 //==============================================================================
787 extern __at(0x000E) __sfr PORTC
;
801 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
812 //==============================================================================
815 //==============================================================================
818 extern __at(0x0010) __sfr PORTE
;
832 extern __at(0x0010) volatile __PORTEbits_t PORTEbits
;
836 //==============================================================================
839 //==============================================================================
842 extern __at(0x0011) __sfr PIR1
;
855 unsigned TMR1GIF
: 1;
871 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
881 #define _TMR1GIF 0x80
883 //==============================================================================
886 //==============================================================================
889 extern __at(0x0012) __sfr PIR2
;
903 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
914 //==============================================================================
917 //==============================================================================
920 extern __at(0x0013) __sfr PIR3
;
934 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
943 //==============================================================================
946 //==============================================================================
949 extern __at(0x0014) __sfr PIR4
;
956 unsigned TMR3GIF
: 1;
958 unsigned TMR5GIF
: 1;
963 extern __at(0x0014) volatile __PIR4bits_t PIR4bits
;
968 #define _TMR3GIF 0x08
970 #define _TMR5GIF 0x20
973 //==============================================================================
976 //==============================================================================
979 extern __at(0x0015) __sfr PIR5
;
993 extern __at(0x0015) volatile __PIR5bits_t PIR5bits
;
1000 //==============================================================================
1003 //==============================================================================
1006 extern __at(0x0016) __sfr PIR6
;
1010 unsigned PWM5IF
: 1;
1011 unsigned PWM6IF
: 1;
1012 unsigned PWM11IF
: 1;
1020 extern __at(0x0016) volatile __PIR6bits_t PIR6bits
;
1022 #define _PWM5IF 0x01
1023 #define _PWM6IF 0x02
1024 #define _PWM11IF 0x04
1026 //==============================================================================
1028 extern __at(0x0017) __sfr TMR0
;
1029 extern __at(0x0018) __sfr TMR1
;
1030 extern __at(0x0018) __sfr TMR1L
;
1031 extern __at(0x0019) __sfr TMR1H
;
1033 //==============================================================================
1036 extern __at(0x001A) __sfr T1CON
;
1044 unsigned NOT_SYNC
: 1;
1057 unsigned SOSCEN
: 1;
1058 unsigned T1CKPS0
: 1;
1059 unsigned T1CKPS1
: 1;
1066 unsigned TMR1ON
: 1;
1068 unsigned NOT_T1SYNC
: 1;
1069 unsigned T1OSCEN
: 1;
1072 unsigned TMR1CS0
: 1;
1073 unsigned TMR1CS1
: 1;
1091 unsigned T1CKPS
: 2;
1105 unsigned TMR1CS
: 2;
1121 extern __at(0x001A) volatile __T1CONbits_t T1CONbits
;
1123 #define _T1CON_ON 0x01
1124 #define _T1CON_TMRON 0x01
1125 #define _T1CON_TMR1ON 0x01
1126 #define _T1CON_T1ON 0x01
1127 #define _T1CON_NOT_SYNC 0x04
1128 #define _T1CON_SYNC 0x04
1129 #define _T1CON_NOT_T1SYNC 0x04
1130 #define _T1CON_OSCEN 0x08
1131 #define _T1CON_SOSCEN 0x08
1132 #define _T1CON_T1OSCEN 0x08
1133 #define _T1CON_CKPS0 0x10
1134 #define _T1CON_T1CKPS0 0x10
1135 #define _T1CON_CKPS1 0x20
1136 #define _T1CON_T1CKPS1 0x20
1137 #define _T1CON_CS0 0x40
1138 #define _T1CON_T1CS0 0x40
1139 #define _T1CON_TMR1CS0 0x40
1140 #define _T1CON_CS1 0x80
1141 #define _T1CON_T1CS1 0x80
1142 #define _T1CON_TMR1CS1 0x80
1144 //==============================================================================
1147 //==============================================================================
1150 extern __at(0x001B) __sfr T1GCON
;
1159 unsigned GGO_NOT_DONE
: 1;
1168 unsigned T1GSS0
: 1;
1169 unsigned T1GSS1
: 1;
1170 unsigned T1GVAL
: 1;
1171 unsigned T1GGO_NOT_DONE
: 1;
1172 unsigned T1GSPM
: 1;
1174 unsigned T1GPOL
: 1;
1187 unsigned TMR1GE
: 1;
1203 extern __at(0x001B) volatile __T1GCONbits_t T1GCONbits
;
1206 #define _T1GSS0 0x01
1208 #define _T1GSS1 0x02
1210 #define _T1GVAL 0x04
1211 #define _GGO_NOT_DONE 0x08
1212 #define _T1GGO_NOT_DONE 0x08
1214 #define _T1GSPM 0x10
1218 #define _T1GPOL 0x40
1221 #define _TMR1GE 0x80
1223 //==============================================================================
1225 extern __at(0x001C) __sfr TMR3
;
1226 extern __at(0x001C) __sfr TMR3L
;
1227 extern __at(0x001D) __sfr TMR3H
;
1229 //==============================================================================
1232 extern __at(0x001E) __sfr T3CON
;
1240 unsigned NOT_SYNC
: 1;
1253 unsigned SOSCEN
: 1;
1254 unsigned T3CKPS0
: 1;
1255 unsigned T3CKPS1
: 1;
1262 unsigned TMR3ON
: 1;
1264 unsigned NOT_T3SYNC
: 1;
1265 unsigned T3OSCEN
: 1;
1268 unsigned TMR3CS0
: 1;
1269 unsigned TMR3CS1
: 1;
1287 unsigned T3CKPS
: 2;
1301 unsigned TMR3CS
: 2;
1317 extern __at(0x001E) volatile __T3CONbits_t T3CONbits
;
1319 #define _T3CON_ON 0x01
1320 #define _T3CON_TMRON 0x01
1321 #define _T3CON_TMR3ON 0x01
1322 #define _T3CON_T3ON 0x01
1323 #define _T3CON_NOT_SYNC 0x04
1324 #define _T3CON_SYNC 0x04
1325 #define _T3CON_NOT_T3SYNC 0x04
1326 #define _T3CON_OSCEN 0x08
1327 #define _T3CON_SOSCEN 0x08
1328 #define _T3CON_T3OSCEN 0x08
1329 #define _T3CON_CKPS0 0x10
1330 #define _T3CON_T3CKPS0 0x10
1331 #define _T3CON_CKPS1 0x20
1332 #define _T3CON_T3CKPS1 0x20
1333 #define _T3CON_CS0 0x40
1334 #define _T3CON_T3CS0 0x40
1335 #define _T3CON_TMR3CS0 0x40
1336 #define _T3CON_CS1 0x80
1337 #define _T3CON_T3CS1 0x80
1338 #define _T3CON_TMR3CS1 0x80
1340 //==============================================================================
1343 //==============================================================================
1346 extern __at(0x001F) __sfr T3GCON
;
1355 unsigned GGO_NOT_DONE
: 1;
1364 unsigned T3GSS0
: 1;
1365 unsigned T3GSS1
: 1;
1366 unsigned T3GVAL
: 1;
1367 unsigned T3GGO_NOT_DONE
: 1;
1368 unsigned T3GSPM
: 1;
1370 unsigned T3GPOL
: 1;
1383 unsigned TMR3GE
: 1;
1399 extern __at(0x001F) volatile __T3GCONbits_t T3GCONbits
;
1401 #define _T3GCON_GSS0 0x01
1402 #define _T3GCON_T3GSS0 0x01
1403 #define _T3GCON_GSS1 0x02
1404 #define _T3GCON_T3GSS1 0x02
1405 #define _T3GCON_GVAL 0x04
1406 #define _T3GCON_T3GVAL 0x04
1407 #define _T3GCON_GGO_NOT_DONE 0x08
1408 #define _T3GCON_T3GGO_NOT_DONE 0x08
1409 #define _T3GCON_GSPM 0x10
1410 #define _T3GCON_T3GSPM 0x10
1411 #define _T3GCON_GTM 0x20
1412 #define _T3GCON_T3GTM 0x20
1413 #define _T3GCON_GPOL 0x40
1414 #define _T3GCON_T3GPOL 0x40
1415 #define _T3GCON_GE 0x80
1416 #define _T3GCON_T3GE 0x80
1417 #define _T3GCON_TMR3GE 0x80
1419 //==============================================================================
1422 //==============================================================================
1425 extern __at(0x008C) __sfr TRISA
;
1429 unsigned TRISA0
: 1;
1430 unsigned TRISA1
: 1;
1431 unsigned TRISA2
: 1;
1432 unsigned TRISA3
: 1;
1433 unsigned TRISA4
: 1;
1434 unsigned TRISA5
: 1;
1435 unsigned TRISA6
: 1;
1436 unsigned TRISA7
: 1;
1439 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
1441 #define _TRISA0 0x01
1442 #define _TRISA1 0x02
1443 #define _TRISA2 0x04
1444 #define _TRISA3 0x08
1445 #define _TRISA4 0x10
1446 #define _TRISA5 0x20
1447 #define _TRISA6 0x40
1448 #define _TRISA7 0x80
1450 //==============================================================================
1453 //==============================================================================
1456 extern __at(0x008D) __sfr TRISB
;
1460 unsigned TRISB0
: 1;
1461 unsigned TRISB1
: 1;
1462 unsigned TRISB2
: 1;
1463 unsigned TRISB3
: 1;
1464 unsigned TRISB4
: 1;
1465 unsigned TRISB5
: 1;
1466 unsigned TRISB6
: 1;
1467 unsigned TRISB7
: 1;
1470 extern __at(0x008D) volatile __TRISBbits_t TRISBbits
;
1472 #define _TRISB0 0x01
1473 #define _TRISB1 0x02
1474 #define _TRISB2 0x04
1475 #define _TRISB3 0x08
1476 #define _TRISB4 0x10
1477 #define _TRISB5 0x20
1478 #define _TRISB6 0x40
1479 #define _TRISB7 0x80
1481 //==============================================================================
1484 //==============================================================================
1487 extern __at(0x008E) __sfr TRISC
;
1491 unsigned TRISC0
: 1;
1492 unsigned TRISC1
: 1;
1493 unsigned TRISC2
: 1;
1494 unsigned TRISC3
: 1;
1495 unsigned TRISC4
: 1;
1496 unsigned TRISC5
: 1;
1497 unsigned TRISC6
: 1;
1498 unsigned TRISC7
: 1;
1501 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
1503 #define _TRISC0 0x01
1504 #define _TRISC1 0x02
1505 #define _TRISC2 0x04
1506 #define _TRISC3 0x08
1507 #define _TRISC4 0x10
1508 #define _TRISC5 0x20
1509 #define _TRISC6 0x40
1510 #define _TRISC7 0x80
1512 //==============================================================================
1515 //==============================================================================
1518 extern __at(0x0090) __sfr TRISE
;
1525 unsigned TRISE3
: 1;
1532 extern __at(0x0090) volatile __TRISEbits_t TRISEbits
;
1534 #define _TRISE3 0x08
1536 //==============================================================================
1539 //==============================================================================
1542 extern __at(0x0091) __sfr PIE1
;
1548 unsigned TMR1IE
: 1;
1549 unsigned TMR2IE
: 1;
1550 unsigned CCP1IE
: 1;
1551 unsigned SSP1IE
: 1;
1555 unsigned TMR1GIE
: 1;
1571 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
1573 #define _TMR1IE 0x01
1574 #define _TMR2IE 0x02
1575 #define _CCP1IE 0x04
1577 #define _SSP1IE 0x08
1581 #define _TMR1GIE 0x80
1583 //==============================================================================
1586 //==============================================================================
1589 extern __at(0x0092) __sfr PIE2
;
1593 unsigned CCP2IE
: 1;
1596 unsigned BCL1IE
: 1;
1603 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
1605 #define _CCP2IE 0x01
1608 #define _BCL1IE 0x08
1614 //==============================================================================
1617 //==============================================================================
1620 extern __at(0x0093) __sfr PIE3
;
1624 unsigned CLC1IE
: 1;
1625 unsigned CLC2IE
: 1;
1626 unsigned CLC3IE
: 1;
1627 unsigned CLC4IE
: 1;
1629 unsigned COG2IE
: 1;
1634 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
1636 #define _CLC1IE 0x01
1637 #define _CLC2IE 0x02
1638 #define _CLC3IE 0x04
1639 #define _CLC4IE 0x08
1641 #define _COG2IE 0x20
1643 //==============================================================================
1646 //==============================================================================
1649 extern __at(0x0094) __sfr PIE4
;
1653 unsigned TMR4IE
: 1;
1654 unsigned TMR6IE
: 1;
1655 unsigned TMR3IE
: 1;
1656 unsigned TMR3GIE
: 1;
1657 unsigned TMR5IE
: 1;
1658 unsigned TMR5GIE
: 1;
1659 unsigned TMR8IE
: 1;
1663 extern __at(0x0094) volatile __PIE4bits_t PIE4bits
;
1665 #define _TMR4IE 0x01
1666 #define _TMR6IE 0x02
1667 #define _TMR3IE 0x04
1668 #define _TMR3GIE 0x08
1669 #define _TMR5IE 0x10
1670 #define _TMR5GIE 0x20
1671 #define _TMR8IE 0x40
1673 //==============================================================================
1676 //==============================================================================
1679 extern __at(0x0095) __sfr PIE5
;
1687 unsigned COG3IE
: 1;
1689 unsigned CCP7IE
: 1;
1693 extern __at(0x0095) volatile __PIE5bits_t PIE5bits
;
1697 #define _COG3IE 0x10
1698 #define _CCP7IE 0x40
1700 //==============================================================================
1703 //==============================================================================
1706 extern __at(0x0096) __sfr PIE6
;
1710 unsigned PWM5IE
: 1;
1711 unsigned PWM6IE
: 1;
1712 unsigned PWM11IE
: 1;
1720 extern __at(0x0096) volatile __PIE6bits_t PIE6bits
;
1722 #define _PWM5IE 0x01
1723 #define _PWM6IE 0x02
1724 #define _PWM11IE 0x04
1726 //==============================================================================
1729 //==============================================================================
1732 extern __at(0x0097) __sfr OPTION_REG
;
1742 unsigned TMR0SE
: 1;
1743 unsigned TMR0CS
: 1;
1744 unsigned INTEDG
: 1;
1745 unsigned NOT_WPUEN
: 1;
1765 } __OPTION_REGbits_t
;
1767 extern __at(0x0097) volatile __OPTION_REGbits_t OPTION_REGbits
;
1773 #define _TMR0SE 0x10
1775 #define _TMR0CS 0x20
1777 #define _INTEDG 0x40
1778 #define _NOT_WPUEN 0x80
1780 //==============================================================================
1783 //==============================================================================
1786 extern __at(0x0098) __sfr PCON
;
1790 unsigned NOT_BOR
: 1;
1791 unsigned NOT_POR
: 1;
1792 unsigned NOT_RI
: 1;
1793 unsigned NOT_RMCLR
: 1;
1794 unsigned NOT_RWDT
: 1;
1796 unsigned STKUNF
: 1;
1797 unsigned STKOVF
: 1;
1800 extern __at(0x0098) volatile __PCONbits_t PCONbits
;
1802 #define _NOT_BOR 0x01
1803 #define _NOT_POR 0x02
1804 #define _NOT_RI 0x04
1805 #define _NOT_RMCLR 0x08
1806 #define _NOT_RWDT 0x10
1807 #define _STKUNF 0x40
1808 #define _STKOVF 0x80
1810 //==============================================================================
1813 //==============================================================================
1816 extern __at(0x0099) __sfr WDTCON
;
1822 unsigned SWDTEN
: 1;
1823 unsigned WDTPS0
: 1;
1824 unsigned WDTPS1
: 1;
1825 unsigned WDTPS2
: 1;
1826 unsigned WDTPS3
: 1;
1827 unsigned WDTPS4
: 1;
1840 extern __at(0x0099) volatile __WDTCONbits_t WDTCONbits
;
1842 #define _SWDTEN 0x01
1843 #define _WDTPS0 0x02
1844 #define _WDTPS1 0x04
1845 #define _WDTPS2 0x08
1846 #define _WDTPS3 0x10
1847 #define _WDTPS4 0x20
1849 //==============================================================================
1852 //==============================================================================
1855 extern __at(0x009A) __sfr OSCTUNE
;
1878 extern __at(0x009A) volatile __OSCTUNEbits_t OSCTUNEbits
;
1887 //==============================================================================
1890 //==============================================================================
1893 extern __at(0x009B) __sfr OSCCON
;
1906 unsigned SPLLEN
: 1;
1923 extern __at(0x009B) volatile __OSCCONbits_t OSCCONbits
;
1931 #define _SPLLEN 0x80
1933 //==============================================================================
1936 //==============================================================================
1939 extern __at(0x009C) __sfr OSCSTAT
;
1943 unsigned HFIOFS
: 1;
1944 unsigned LFIOFR
: 1;
1945 unsigned MFIOFR
: 1;
1946 unsigned HFIOFL
: 1;
1947 unsigned HFIOFR
: 1;
1953 extern __at(0x009C) volatile __OSCSTATbits_t OSCSTATbits
;
1955 #define _HFIOFS 0x01
1956 #define _LFIOFR 0x02
1957 #define _MFIOFR 0x04
1958 #define _HFIOFL 0x08
1959 #define _HFIOFR 0x10
1964 //==============================================================================
1967 //==============================================================================
1970 extern __at(0x009D) __sfr BORCON
;
1974 unsigned BORRDY
: 1;
1981 unsigned SBOREN
: 1;
1984 extern __at(0x009D) volatile __BORCONbits_t BORCONbits
;
1986 #define _BORRDY 0x01
1988 #define _SBOREN 0x80
1990 //==============================================================================
1993 //==============================================================================
1996 extern __at(0x009E) __sfr FVRCON
;
2006 unsigned FVRRDY
: 1;
2010 extern __at(0x009E) volatile __FVRCONbits_t FVRCONbits
;
2014 #define _FVRRDY 0x40
2017 //==============================================================================
2020 //==============================================================================
2023 extern __at(0x009F) __sfr ZCD1CON
;
2027 unsigned ZCD1INTN
: 1;
2028 unsigned ZCD1INTP
: 1;
2031 unsigned ZCD1POL
: 1;
2032 unsigned ZCD1OUT
: 1;
2034 unsigned ZCD1EN
: 1;
2037 extern __at(0x009F) volatile __ZCD1CONbits_t ZCD1CONbits
;
2039 #define _ZCD1INTN 0x01
2040 #define _ZCD1INTP 0x02
2041 #define _ZCD1POL 0x10
2042 #define _ZCD1OUT 0x20
2043 #define _ZCD1EN 0x80
2045 //==============================================================================
2048 //==============================================================================
2051 extern __at(0x010C) __sfr LATA
;
2065 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
2076 //==============================================================================
2079 //==============================================================================
2082 extern __at(0x010D) __sfr LATB
;
2096 extern __at(0x010D) volatile __LATBbits_t LATBbits
;
2107 //==============================================================================
2110 //==============================================================================
2113 extern __at(0x010E) __sfr LATC
;
2127 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
2138 //==============================================================================
2141 //==============================================================================
2144 extern __at(0x0111) __sfr CMOUT
;
2148 unsigned MC1OUT
: 1;
2149 unsigned MC2OUT
: 1;
2150 unsigned MC3OUT
: 1;
2151 unsigned MC4OUT
: 1;
2152 unsigned MC5OUT
: 1;
2153 unsigned MC6OUT
: 1;
2158 extern __at(0x0111) volatile __CMOUTbits_t CMOUTbits
;
2160 #define _MC1OUT 0x01
2161 #define _MC2OUT 0x02
2162 #define _MC3OUT 0x04
2163 #define _MC4OUT 0x08
2164 #define _MC5OUT 0x10
2165 #define _MC6OUT 0x20
2167 //==============================================================================
2170 //==============================================================================
2173 extern __at(0x0112) __sfr CM1CON0
;
2181 unsigned Reserved
: 1;
2191 unsigned C1SYNC
: 1;
2202 extern __at(0x0112) volatile __CM1CON0bits_t CM1CON0bits
;
2204 #define _CM1CON0_SYNC 0x01
2205 #define _CM1CON0_C1SYNC 0x01
2206 #define _CM1CON0_HYS 0x02
2207 #define _CM1CON0_C1HYS 0x02
2208 #define _CM1CON0_Reserved 0x04
2209 #define _CM1CON0_C1SP 0x04
2210 #define _CM1CON0_ZLF 0x08
2211 #define _CM1CON0_C1ZLF 0x08
2212 #define _CM1CON0_POL 0x10
2213 #define _CM1CON0_C1POL 0x10
2214 #define _CM1CON0_OUT 0x40
2215 #define _CM1CON0_C1OUT 0x40
2216 #define _CM1CON0_ON 0x80
2217 #define _CM1CON0_C1ON 0x80
2219 //==============================================================================
2222 //==============================================================================
2225 extern __at(0x0113) __sfr CM1CON1
;
2243 unsigned C1INTN
: 1;
2244 unsigned C1INTP
: 1;
2254 extern __at(0x0113) volatile __CM1CON1bits_t CM1CON1bits
;
2256 #define _CM1CON1_INTN 0x01
2257 #define _CM1CON1_C1INTN 0x01
2258 #define _CM1CON1_INTP 0x02
2259 #define _CM1CON1_C1INTP 0x02
2261 //==============================================================================
2264 //==============================================================================
2267 extern __at(0x0114) __sfr CM1NSEL
;
2273 unsigned C1NCH0
: 1;
2274 unsigned C1NCH1
: 1;
2275 unsigned C1NCH2
: 1;
2276 unsigned C1NCH3
: 1;
2290 extern __at(0x0114) volatile __CM1NSELbits_t CM1NSELbits
;
2292 #define _C1NCH0 0x01
2293 #define _C1NCH1 0x02
2294 #define _C1NCH2 0x04
2295 #define _C1NCH3 0x08
2297 //==============================================================================
2300 //==============================================================================
2303 extern __at(0x0115) __sfr CM1PSEL
;
2321 unsigned C1PCH0
: 1;
2322 unsigned C1PCH1
: 1;
2323 unsigned C1PCH2
: 1;
2324 unsigned C1PCH3
: 1;
2344 extern __at(0x0115) volatile __CM1PSELbits_t CM1PSELbits
;
2347 #define _C1PCH0 0x01
2349 #define _C1PCH1 0x02
2351 #define _C1PCH2 0x04
2353 #define _C1PCH3 0x08
2355 //==============================================================================
2358 //==============================================================================
2361 extern __at(0x0116) __sfr CM2CON0
;
2369 unsigned Reserved
: 1;
2379 unsigned C2SYNC
: 1;
2390 extern __at(0x0116) volatile __CM2CON0bits_t CM2CON0bits
;
2392 #define _CM2CON0_SYNC 0x01
2393 #define _CM2CON0_C2SYNC 0x01
2394 #define _CM2CON0_HYS 0x02
2395 #define _CM2CON0_C2HYS 0x02
2396 #define _CM2CON0_Reserved 0x04
2397 #define _CM2CON0_C2SP 0x04
2398 #define _CM2CON0_ZLF 0x08
2399 #define _CM2CON0_C2ZLF 0x08
2400 #define _CM2CON0_POL 0x10
2401 #define _CM2CON0_C2POL 0x10
2402 #define _CM2CON0_OUT 0x40
2403 #define _CM2CON0_C2OUT 0x40
2404 #define _CM2CON0_ON 0x80
2405 #define _CM2CON0_C2ON 0x80
2407 //==============================================================================
2410 //==============================================================================
2413 extern __at(0x0117) __sfr CM2CON1
;
2431 unsigned C2INTN
: 1;
2432 unsigned C2INTP
: 1;
2442 extern __at(0x0117) volatile __CM2CON1bits_t CM2CON1bits
;
2444 #define _CM2CON1_INTN 0x01
2445 #define _CM2CON1_C2INTN 0x01
2446 #define _CM2CON1_INTP 0x02
2447 #define _CM2CON1_C2INTP 0x02
2449 //==============================================================================
2452 //==============================================================================
2455 extern __at(0x0118) __sfr CM2NSEL
;
2461 unsigned C2NCH0
: 1;
2462 unsigned C2NCH1
: 1;
2463 unsigned C2NCH2
: 1;
2464 unsigned C2NCH3
: 1;
2478 extern __at(0x0118) volatile __CM2NSELbits_t CM2NSELbits
;
2480 #define _C2NCH0 0x01
2481 #define _C2NCH1 0x02
2482 #define _C2NCH2 0x04
2483 #define _C2NCH3 0x08
2485 //==============================================================================
2488 //==============================================================================
2491 extern __at(0x0119) __sfr CM2PSEL
;
2509 unsigned C2PCH0
: 1;
2510 unsigned C2PCH1
: 1;
2511 unsigned C2PCH2
: 1;
2512 unsigned C2PCH3
: 1;
2532 extern __at(0x0119) volatile __CM2PSELbits_t CM2PSELbits
;
2534 #define _CM2PSEL_PCH0 0x01
2535 #define _CM2PSEL_C2PCH0 0x01
2536 #define _CM2PSEL_PCH1 0x02
2537 #define _CM2PSEL_C2PCH1 0x02
2538 #define _CM2PSEL_PCH2 0x04
2539 #define _CM2PSEL_C2PCH2 0x04
2540 #define _CM2PSEL_PCH3 0x08
2541 #define _CM2PSEL_C2PCH3 0x08
2543 //==============================================================================
2546 //==============================================================================
2549 extern __at(0x011A) __sfr CM3CON0
;
2557 unsigned Reserved
: 1;
2567 unsigned C3SYNC
: 1;
2578 extern __at(0x011A) volatile __CM3CON0bits_t CM3CON0bits
;
2580 #define _CM3CON0_SYNC 0x01
2581 #define _CM3CON0_C3SYNC 0x01
2582 #define _CM3CON0_HYS 0x02
2583 #define _CM3CON0_C3HYS 0x02
2584 #define _CM3CON0_Reserved 0x04
2585 #define _CM3CON0_C3SP 0x04
2586 #define _CM3CON0_ZLF 0x08
2587 #define _CM3CON0_C3ZLF 0x08
2588 #define _CM3CON0_POL 0x10
2589 #define _CM3CON0_C3POL 0x10
2590 #define _CM3CON0_OUT 0x40
2591 #define _CM3CON0_C3OUT 0x40
2592 #define _CM3CON0_ON 0x80
2593 #define _CM3CON0_C3ON 0x80
2595 //==============================================================================
2598 //==============================================================================
2601 extern __at(0x011B) __sfr CM3CON1
;
2619 unsigned C3INTN
: 1;
2620 unsigned C3INTP
: 1;
2630 extern __at(0x011B) volatile __CM3CON1bits_t CM3CON1bits
;
2632 #define _CM3CON1_INTN 0x01
2633 #define _CM3CON1_C3INTN 0x01
2634 #define _CM3CON1_INTP 0x02
2635 #define _CM3CON1_C3INTP 0x02
2637 //==============================================================================
2640 //==============================================================================
2643 extern __at(0x011C) __sfr CM3NSEL
;
2649 unsigned C3NCH0
: 1;
2650 unsigned C3NCH1
: 1;
2651 unsigned C3NCH2
: 1;
2652 unsigned C3NCH3
: 1;
2666 extern __at(0x011C) volatile __CM3NSELbits_t CM3NSELbits
;
2668 #define _C3NCH0 0x01
2669 #define _C3NCH1 0x02
2670 #define _C3NCH2 0x04
2671 #define _C3NCH3 0x08
2673 //==============================================================================
2676 //==============================================================================
2679 extern __at(0x011D) __sfr CM3PSEL
;
2697 unsigned C3PCH0
: 1;
2698 unsigned C3PCH1
: 1;
2699 unsigned C3PCH2
: 1;
2700 unsigned C3PCH3
: 1;
2720 extern __at(0x011D) volatile __CM3PSELbits_t CM3PSELbits
;
2722 #define _CM3PSEL_PCH0 0x01
2723 #define _CM3PSEL_C3PCH0 0x01
2724 #define _CM3PSEL_PCH1 0x02
2725 #define _CM3PSEL_C3PCH1 0x02
2726 #define _CM3PSEL_PCH2 0x04
2727 #define _CM3PSEL_C3PCH2 0x04
2728 #define _CM3PSEL_PCH3 0x08
2729 #define _CM3PSEL_C3PCH3 0x08
2731 //==============================================================================
2734 //==============================================================================
2737 extern __at(0x018C) __sfr ANSELA
;
2760 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
2769 //==============================================================================
2772 //==============================================================================
2775 extern __at(0x018D) __sfr ANSELB
;
2798 extern __at(0x018D) volatile __ANSELBbits_t ANSELBbits
;
2807 //==============================================================================
2810 //==============================================================================
2813 extern __at(0x018E) __sfr ANSELC
;
2827 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
2836 //==============================================================================
2838 extern __at(0x0191) __sfr PMADR
;
2839 extern __at(0x0191) __sfr PMADRL
;
2840 extern __at(0x0192) __sfr PMADRH
;
2841 extern __at(0x0193) __sfr PMDAT
;
2842 extern __at(0x0193) __sfr PMDATL
;
2843 extern __at(0x0194) __sfr PMDATH
;
2845 //==============================================================================
2848 extern __at(0x0195) __sfr PMCON1
;
2862 extern __at(0x0195) volatile __PMCON1bits_t PMCON1bits
;
2872 //==============================================================================
2874 extern __at(0x0196) __sfr PMCON2
;
2876 //==============================================================================
2879 extern __at(0x0197) __sfr VREGCON
;
2883 unsigned Reserved
: 1;
2884 unsigned VREGPM
: 1;
2893 extern __at(0x0197) volatile __VREGCONbits_t VREGCONbits
;
2895 #define _VREGCON_Reserved 0x01
2896 #define _VREGCON_VREGPM 0x02
2898 //==============================================================================
2900 extern __at(0x0199) __sfr RC1REG
;
2901 extern __at(0x0199) __sfr RCREG
;
2902 extern __at(0x0199) __sfr RCREG1
;
2903 extern __at(0x019A) __sfr TX1REG
;
2904 extern __at(0x019A) __sfr TXREG
;
2905 extern __at(0x019A) __sfr TXREG1
;
2906 extern __at(0x019B) __sfr SP1BRG
;
2907 extern __at(0x019B) __sfr SP1BRGL
;
2908 extern __at(0x019B) __sfr SPBRG
;
2909 extern __at(0x019B) __sfr SPBRG1
;
2910 extern __at(0x019B) __sfr SPBRGL
;
2911 extern __at(0x019C) __sfr SP1BRGH
;
2912 extern __at(0x019C) __sfr SPBRGH
;
2913 extern __at(0x019C) __sfr SPBRGH1
;
2915 //==============================================================================
2918 extern __at(0x019D) __sfr RC1STA
;
2932 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
2943 //==============================================================================
2946 //==============================================================================
2949 extern __at(0x019D) __sfr RCSTA
;
2963 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
2965 #define _RCSTA_RX9D 0x01
2966 #define _RCSTA_OERR 0x02
2967 #define _RCSTA_FERR 0x04
2968 #define _RCSTA_ADDEN 0x08
2969 #define _RCSTA_CREN 0x10
2970 #define _RCSTA_SREN 0x20
2971 #define _RCSTA_RX9 0x40
2972 #define _RCSTA_SPEN 0x80
2974 //==============================================================================
2977 //==============================================================================
2980 extern __at(0x019D) __sfr RCSTA1
;
2994 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
2996 #define _RCSTA1_RX9D 0x01
2997 #define _RCSTA1_OERR 0x02
2998 #define _RCSTA1_FERR 0x04
2999 #define _RCSTA1_ADDEN 0x08
3000 #define _RCSTA1_CREN 0x10
3001 #define _RCSTA1_SREN 0x20
3002 #define _RCSTA1_RX9 0x40
3003 #define _RCSTA1_SPEN 0x80
3005 //==============================================================================
3008 //==============================================================================
3011 extern __at(0x019E) __sfr TX1STA
;
3025 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
3027 #define _TX1STA_TX9D 0x01
3028 #define _TX1STA_TRMT 0x02
3029 #define _TX1STA_BRGH 0x04
3030 #define _TX1STA_SENDB 0x08
3031 #define _TX1STA_SYNC 0x10
3032 #define _TX1STA_TXEN 0x20
3033 #define _TX1STA_TX9 0x40
3034 #define _TX1STA_CSRC 0x80
3036 //==============================================================================
3039 //==============================================================================
3042 extern __at(0x019E) __sfr TXSTA
;
3056 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
3058 #define _TXSTA_TX9D 0x01
3059 #define _TXSTA_TRMT 0x02
3060 #define _TXSTA_BRGH 0x04
3061 #define _TXSTA_SENDB 0x08
3062 #define _TXSTA_SYNC 0x10
3063 #define _TXSTA_TXEN 0x20
3064 #define _TXSTA_TX9 0x40
3065 #define _TXSTA_CSRC 0x80
3067 //==============================================================================
3070 //==============================================================================
3073 extern __at(0x019E) __sfr TXSTA1
;
3087 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
3089 #define _TXSTA1_TX9D 0x01
3090 #define _TXSTA1_TRMT 0x02
3091 #define _TXSTA1_BRGH 0x04
3092 #define _TXSTA1_SENDB 0x08
3093 #define _TXSTA1_SYNC 0x10
3094 #define _TXSTA1_TXEN 0x20
3095 #define _TXSTA1_TX9 0x40
3096 #define _TXSTA1_CSRC 0x80
3098 //==============================================================================
3101 //==============================================================================
3104 extern __at(0x019F) __sfr BAUD1CON
;
3115 unsigned ABDOVF
: 1;
3118 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
3125 #define _ABDOVF 0x80
3127 //==============================================================================
3130 //==============================================================================
3133 extern __at(0x019F) __sfr BAUDCON
;
3144 unsigned ABDOVF
: 1;
3147 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
3149 #define _BAUDCON_ABDEN 0x01
3150 #define _BAUDCON_WUE 0x02
3151 #define _BAUDCON_BRG16 0x08
3152 #define _BAUDCON_SCKP 0x10
3153 #define _BAUDCON_RCIDL 0x40
3154 #define _BAUDCON_ABDOVF 0x80
3156 //==============================================================================
3159 //==============================================================================
3162 extern __at(0x019F) __sfr BAUDCON1
;
3173 unsigned ABDOVF
: 1;
3176 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
3178 #define _BAUDCON1_ABDEN 0x01
3179 #define _BAUDCON1_WUE 0x02
3180 #define _BAUDCON1_BRG16 0x08
3181 #define _BAUDCON1_SCKP 0x10
3182 #define _BAUDCON1_RCIDL 0x40
3183 #define _BAUDCON1_ABDOVF 0x80
3185 //==============================================================================
3188 //==============================================================================
3191 extern __at(0x019F) __sfr BAUDCTL
;
3202 unsigned ABDOVF
: 1;
3205 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
3207 #define _BAUDCTL_ABDEN 0x01
3208 #define _BAUDCTL_WUE 0x02
3209 #define _BAUDCTL_BRG16 0x08
3210 #define _BAUDCTL_SCKP 0x10
3211 #define _BAUDCTL_RCIDL 0x40
3212 #define _BAUDCTL_ABDOVF 0x80
3214 //==============================================================================
3217 //==============================================================================
3220 extern __at(0x019F) __sfr BAUDCTL1
;
3231 unsigned ABDOVF
: 1;
3234 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
3236 #define _BAUDCTL1_ABDEN 0x01
3237 #define _BAUDCTL1_WUE 0x02
3238 #define _BAUDCTL1_BRG16 0x08
3239 #define _BAUDCTL1_SCKP 0x10
3240 #define _BAUDCTL1_RCIDL 0x40
3241 #define _BAUDCTL1_ABDOVF 0x80
3243 //==============================================================================
3246 //==============================================================================
3249 extern __at(0x020C) __sfr WPUA
;
3263 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
3274 //==============================================================================
3277 //==============================================================================
3280 extern __at(0x020D) __sfr WPUB
;
3294 extern __at(0x020D) volatile __WPUBbits_t WPUBbits
;
3305 //==============================================================================
3308 //==============================================================================
3311 extern __at(0x020E) __sfr WPUC
;
3325 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
3336 //==============================================================================
3339 //==============================================================================
3342 extern __at(0x0210) __sfr WPUE
;
3356 extern __at(0x0210) volatile __WPUEbits_t WPUEbits
;
3360 //==============================================================================
3363 //==============================================================================
3366 extern __at(0x0211) __sfr SSP1BUF
;
3372 unsigned SSP1BUF0
: 1;
3373 unsigned SSP1BUF1
: 1;
3374 unsigned SSP1BUF2
: 1;
3375 unsigned SSP1BUF3
: 1;
3376 unsigned SSP1BUF4
: 1;
3377 unsigned SSP1BUF5
: 1;
3378 unsigned SSP1BUF6
: 1;
3379 unsigned SSP1BUF7
: 1;
3395 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
3397 #define _SSP1BUF0 0x01
3399 #define _SSP1BUF1 0x02
3401 #define _SSP1BUF2 0x04
3403 #define _SSP1BUF3 0x08
3405 #define _SSP1BUF4 0x10
3407 #define _SSP1BUF5 0x20
3409 #define _SSP1BUF6 0x40
3411 #define _SSP1BUF7 0x80
3414 //==============================================================================
3417 //==============================================================================
3420 extern __at(0x0211) __sfr SSPBUF
;
3426 unsigned SSP1BUF0
: 1;
3427 unsigned SSP1BUF1
: 1;
3428 unsigned SSP1BUF2
: 1;
3429 unsigned SSP1BUF3
: 1;
3430 unsigned SSP1BUF4
: 1;
3431 unsigned SSP1BUF5
: 1;
3432 unsigned SSP1BUF6
: 1;
3433 unsigned SSP1BUF7
: 1;
3449 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
3451 #define _SSPBUF_SSP1BUF0 0x01
3452 #define _SSPBUF_BUF0 0x01
3453 #define _SSPBUF_SSP1BUF1 0x02
3454 #define _SSPBUF_BUF1 0x02
3455 #define _SSPBUF_SSP1BUF2 0x04
3456 #define _SSPBUF_BUF2 0x04
3457 #define _SSPBUF_SSP1BUF3 0x08
3458 #define _SSPBUF_BUF3 0x08
3459 #define _SSPBUF_SSP1BUF4 0x10
3460 #define _SSPBUF_BUF4 0x10
3461 #define _SSPBUF_SSP1BUF5 0x20
3462 #define _SSPBUF_BUF5 0x20
3463 #define _SSPBUF_SSP1BUF6 0x40
3464 #define _SSPBUF_BUF6 0x40
3465 #define _SSPBUF_SSP1BUF7 0x80
3466 #define _SSPBUF_BUF7 0x80
3468 //==============================================================================
3471 //==============================================================================
3474 extern __at(0x0212) __sfr SSP1ADD
;
3480 unsigned SSP1ADD0
: 1;
3481 unsigned SSP1ADD1
: 1;
3482 unsigned SSP1ADD2
: 1;
3483 unsigned SSP1ADD3
: 1;
3484 unsigned SSP1ADD4
: 1;
3485 unsigned SSP1ADD5
: 1;
3486 unsigned SSP1ADD6
: 1;
3487 unsigned SSP1ADD7
: 1;
3503 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
3505 #define _SSP1ADD0 0x01
3507 #define _SSP1ADD1 0x02
3509 #define _SSP1ADD2 0x04
3511 #define _SSP1ADD3 0x08
3513 #define _SSP1ADD4 0x10
3515 #define _SSP1ADD5 0x20
3517 #define _SSP1ADD6 0x40
3519 #define _SSP1ADD7 0x80
3522 //==============================================================================
3525 //==============================================================================
3528 extern __at(0x0212) __sfr SSPADD
;
3534 unsigned SSP1ADD0
: 1;
3535 unsigned SSP1ADD1
: 1;
3536 unsigned SSP1ADD2
: 1;
3537 unsigned SSP1ADD3
: 1;
3538 unsigned SSP1ADD4
: 1;
3539 unsigned SSP1ADD5
: 1;
3540 unsigned SSP1ADD6
: 1;
3541 unsigned SSP1ADD7
: 1;
3557 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
3559 #define _SSPADD_SSP1ADD0 0x01
3560 #define _SSPADD_ADD0 0x01
3561 #define _SSPADD_SSP1ADD1 0x02
3562 #define _SSPADD_ADD1 0x02
3563 #define _SSPADD_SSP1ADD2 0x04
3564 #define _SSPADD_ADD2 0x04
3565 #define _SSPADD_SSP1ADD3 0x08
3566 #define _SSPADD_ADD3 0x08
3567 #define _SSPADD_SSP1ADD4 0x10
3568 #define _SSPADD_ADD4 0x10
3569 #define _SSPADD_SSP1ADD5 0x20
3570 #define _SSPADD_ADD5 0x20
3571 #define _SSPADD_SSP1ADD6 0x40
3572 #define _SSPADD_ADD6 0x40
3573 #define _SSPADD_SSP1ADD7 0x80
3574 #define _SSPADD_ADD7 0x80
3576 //==============================================================================
3579 //==============================================================================
3582 extern __at(0x0213) __sfr SSP1MSK
;
3588 unsigned SSP1MSK0
: 1;
3589 unsigned SSP1MSK1
: 1;
3590 unsigned SSP1MSK2
: 1;
3591 unsigned SSP1MSK3
: 1;
3592 unsigned SSP1MSK4
: 1;
3593 unsigned SSP1MSK5
: 1;
3594 unsigned SSP1MSK6
: 1;
3595 unsigned SSP1MSK7
: 1;
3611 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
3613 #define _SSP1MSK0 0x01
3615 #define _SSP1MSK1 0x02
3617 #define _SSP1MSK2 0x04
3619 #define _SSP1MSK3 0x08
3621 #define _SSP1MSK4 0x10
3623 #define _SSP1MSK5 0x20
3625 #define _SSP1MSK6 0x40
3627 #define _SSP1MSK7 0x80
3630 //==============================================================================
3633 //==============================================================================
3636 extern __at(0x0213) __sfr SSPMSK
;
3642 unsigned SSP1MSK0
: 1;
3643 unsigned SSP1MSK1
: 1;
3644 unsigned SSP1MSK2
: 1;
3645 unsigned SSP1MSK3
: 1;
3646 unsigned SSP1MSK4
: 1;
3647 unsigned SSP1MSK5
: 1;
3648 unsigned SSP1MSK6
: 1;
3649 unsigned SSP1MSK7
: 1;
3665 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
3667 #define _SSPMSK_SSP1MSK0 0x01
3668 #define _SSPMSK_MSK0 0x01
3669 #define _SSPMSK_SSP1MSK1 0x02
3670 #define _SSPMSK_MSK1 0x02
3671 #define _SSPMSK_SSP1MSK2 0x04
3672 #define _SSPMSK_MSK2 0x04
3673 #define _SSPMSK_SSP1MSK3 0x08
3674 #define _SSPMSK_MSK3 0x08
3675 #define _SSPMSK_SSP1MSK4 0x10
3676 #define _SSPMSK_MSK4 0x10
3677 #define _SSPMSK_SSP1MSK5 0x20
3678 #define _SSPMSK_MSK5 0x20
3679 #define _SSPMSK_SSP1MSK6 0x40
3680 #define _SSPMSK_MSK6 0x40
3681 #define _SSPMSK_SSP1MSK7 0x80
3682 #define _SSPMSK_MSK7 0x80
3684 //==============================================================================
3687 //==============================================================================
3690 extern __at(0x0214) __sfr SSP1STAT
;
3696 unsigned R_NOT_W
: 1;
3699 unsigned D_NOT_A
: 1;
3704 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
3708 #define _R_NOT_W 0x04
3711 #define _D_NOT_A 0x20
3715 //==============================================================================
3718 //==============================================================================
3721 extern __at(0x0214) __sfr SSPSTAT
;
3727 unsigned R_NOT_W
: 1;
3730 unsigned D_NOT_A
: 1;
3735 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
3737 #define _SSPSTAT_BF 0x01
3738 #define _SSPSTAT_UA 0x02
3739 #define _SSPSTAT_R_NOT_W 0x04
3740 #define _SSPSTAT_S 0x08
3741 #define _SSPSTAT_P 0x10
3742 #define _SSPSTAT_D_NOT_A 0x20
3743 #define _SSPSTAT_CKE 0x40
3744 #define _SSPSTAT_SMP 0x80
3746 //==============================================================================
3749 //==============================================================================
3752 extern __at(0x0215) __sfr SSP1CON
;
3775 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
3786 //==============================================================================
3789 //==============================================================================
3792 extern __at(0x0215) __sfr SSP1CON1
;
3815 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
3817 #define _SSP1CON1_SSPM0 0x01
3818 #define _SSP1CON1_SSPM1 0x02
3819 #define _SSP1CON1_SSPM2 0x04
3820 #define _SSP1CON1_SSPM3 0x08
3821 #define _SSP1CON1_CKP 0x10
3822 #define _SSP1CON1_SSPEN 0x20
3823 #define _SSP1CON1_SSPOV 0x40
3824 #define _SSP1CON1_WCOL 0x80
3826 //==============================================================================
3829 //==============================================================================
3832 extern __at(0x0215) __sfr SSPCON
;
3855 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
3857 #define _SSPCON_SSPM0 0x01
3858 #define _SSPCON_SSPM1 0x02
3859 #define _SSPCON_SSPM2 0x04
3860 #define _SSPCON_SSPM3 0x08
3861 #define _SSPCON_CKP 0x10
3862 #define _SSPCON_SSPEN 0x20
3863 #define _SSPCON_SSPOV 0x40
3864 #define _SSPCON_WCOL 0x80
3866 //==============================================================================
3869 //==============================================================================
3872 extern __at(0x0215) __sfr SSPCON1
;
3895 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
3897 #define _SSPCON1_SSPM0 0x01
3898 #define _SSPCON1_SSPM1 0x02
3899 #define _SSPCON1_SSPM2 0x04
3900 #define _SSPCON1_SSPM3 0x08
3901 #define _SSPCON1_CKP 0x10
3902 #define _SSPCON1_SSPEN 0x20
3903 #define _SSPCON1_SSPOV 0x40
3904 #define _SSPCON1_WCOL 0x80
3906 //==============================================================================
3909 //==============================================================================
3912 extern __at(0x0216) __sfr SSP1CON2
;
3922 unsigned ACKSTAT
: 1;
3926 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
3934 #define _ACKSTAT 0x40
3937 //==============================================================================
3940 //==============================================================================
3943 extern __at(0x0216) __sfr SSPCON2
;
3953 unsigned ACKSTAT
: 1;
3957 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
3959 #define _SSPCON2_SEN 0x01
3960 #define _SSPCON2_RSEN 0x02
3961 #define _SSPCON2_PEN 0x04
3962 #define _SSPCON2_RCEN 0x08
3963 #define _SSPCON2_ACKEN 0x10
3964 #define _SSPCON2_ACKDT 0x20
3965 #define _SSPCON2_ACKSTAT 0x40
3966 #define _SSPCON2_GCEN 0x80
3968 //==============================================================================
3971 //==============================================================================
3974 extern __at(0x0217) __sfr SSP1CON3
;
3985 unsigned ACKTIM
: 1;
3988 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
3997 #define _ACKTIM 0x80
3999 //==============================================================================
4002 //==============================================================================
4005 extern __at(0x0217) __sfr SSPCON3
;
4016 unsigned ACKTIM
: 1;
4019 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
4021 #define _SSPCON3_DHEN 0x01
4022 #define _SSPCON3_AHEN 0x02
4023 #define _SSPCON3_SBCDE 0x04
4024 #define _SSPCON3_SDAHT 0x08
4025 #define _SSPCON3_BOEN 0x10
4026 #define _SSPCON3_SCIE 0x20
4027 #define _SSPCON3_PCIE 0x40
4028 #define _SSPCON3_ACKTIM 0x80
4030 //==============================================================================
4033 //==============================================================================
4036 extern __at(0x021B) __sfr MD3CON0
;
4054 unsigned MD3BIT
: 1;
4058 unsigned MD3OPOL
: 1;
4059 unsigned MD3OUT
: 1;
4065 extern __at(0x021B) volatile __MD3CON0bits_t MD3CON0bits
;
4067 #define _MD3CON0_BIT 0x01
4068 #define _MD3CON0_MD3BIT 0x01
4069 #define _MD3CON0_OPOL 0x10
4070 #define _MD3CON0_MD3OPOL 0x10
4071 #define _MD3CON0_OUT 0x20
4072 #define _MD3CON0_MD3OUT 0x20
4073 #define _MD3CON0_EN 0x80
4074 #define _MD3CON0_MD3EN 0x80
4076 //==============================================================================
4079 //==============================================================================
4082 extern __at(0x021C) __sfr MD3CON1
;
4088 unsigned CLSYNC
: 1;
4092 unsigned CHSYNC
: 1;
4100 unsigned MD3CLSYNC
: 1;
4101 unsigned MD3CLPOL
: 1;
4104 unsigned MD3CHSYNC
: 1;
4105 unsigned MD3CHPOL
: 1;
4111 extern __at(0x021C) volatile __MD3CON1bits_t MD3CON1bits
;
4113 #define _MD3CON1_CLSYNC 0x01
4114 #define _MD3CON1_MD3CLSYNC 0x01
4115 #define _MD3CON1_CLPOL 0x02
4116 #define _MD3CON1_MD3CLPOL 0x02
4117 #define _MD3CON1_CHSYNC 0x10
4118 #define _MD3CON1_MD3CHSYNC 0x10
4119 #define _MD3CON1_CHPOL 0x20
4120 #define _MD3CON1_MD3CHPOL 0x20
4122 //==============================================================================
4125 //==============================================================================
4128 extern __at(0x021D) __sfr MD3SRC
;
4146 unsigned MD3MS0
: 1;
4147 unsigned MD3MS1
: 1;
4148 unsigned MD3MS2
: 1;
4149 unsigned MD3MS3
: 1;
4150 unsigned MD3MS4
: 1;
4169 extern __at(0x021D) volatile __MD3SRCbits_t MD3SRCbits
;
4171 #define _MD3SRC_MS0 0x01
4172 #define _MD3SRC_MD3MS0 0x01
4173 #define _MD3SRC_MS1 0x02
4174 #define _MD3SRC_MD3MS1 0x02
4175 #define _MD3SRC_MS2 0x04
4176 #define _MD3SRC_MD3MS2 0x04
4177 #define _MD3SRC_MS3 0x08
4178 #define _MD3SRC_MD3MS3 0x08
4179 #define _MD3SRC_MS4 0x10
4180 #define _MD3SRC_MD3MS4 0x10
4182 //==============================================================================
4185 //==============================================================================
4188 extern __at(0x021E) __sfr MD3CARL
;
4206 unsigned MD3CL0
: 1;
4207 unsigned MD3CL1
: 1;
4208 unsigned MD3CL2
: 1;
4209 unsigned MD3CL3
: 1;
4229 extern __at(0x021E) volatile __MD3CARLbits_t MD3CARLbits
;
4231 #define _MD3CARL_CL0 0x01
4232 #define _MD3CARL_MD3CL0 0x01
4233 #define _MD3CARL_CL1 0x02
4234 #define _MD3CARL_MD3CL1 0x02
4235 #define _MD3CARL_CL2 0x04
4236 #define _MD3CARL_MD3CL2 0x04
4237 #define _MD3CARL_CL3 0x08
4238 #define _MD3CARL_MD3CL3 0x08
4239 #define _MD3CARL_CL4 0x10
4241 //==============================================================================
4244 //==============================================================================
4247 extern __at(0x021F) __sfr MD3CARH
;
4265 unsigned MD3CH0
: 1;
4266 unsigned MD3CH1
: 1;
4267 unsigned MD3CH2
: 1;
4268 unsigned MD3CH3
: 1;
4288 extern __at(0x021F) volatile __MD3CARHbits_t MD3CARHbits
;
4290 #define _MD3CARH_CH0 0x01
4291 #define _MD3CARH_MD3CH0 0x01
4292 #define _MD3CARH_CH1 0x02
4293 #define _MD3CARH_MD3CH1 0x02
4294 #define _MD3CARH_CH2 0x04
4295 #define _MD3CARH_MD3CH2 0x04
4296 #define _MD3CARH_CH3 0x08
4297 #define _MD3CARH_MD3CH3 0x08
4298 #define _MD3CARH_CH4 0x10
4300 //==============================================================================
4303 //==============================================================================
4306 extern __at(0x028C) __sfr ODCONA
;
4320 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
4331 //==============================================================================
4334 //==============================================================================
4337 extern __at(0x028D) __sfr ODCONB
;
4360 extern __at(0x028D) volatile __ODCONBbits_t ODCONBbits
;
4362 #define _ODCONB_ODA0 0x01
4363 #define _ODCONB_ODA1 0x02
4364 #define _ODCONB_ODA2 0x04
4365 #define _ODCONB_ODA3 0x08
4366 #define _ODCONB_ODB4 0x10
4367 #define _ODCONB_ODB5 0x20
4368 #define _ODCONB_ODB6 0x40
4369 #define _ODCONB_ODB7 0x80
4371 //==============================================================================
4374 //==============================================================================
4377 extern __at(0x028E) __sfr ODCONC
;
4391 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
4402 //==============================================================================
4404 extern __at(0x0291) __sfr CCPR1
;
4405 extern __at(0x0291) __sfr CCPR1L
;
4406 extern __at(0x0292) __sfr CCPR1H
;
4408 //==============================================================================
4411 extern __at(0x0293) __sfr CCP1CON
;
4429 unsigned CCP1MODE0
: 1;
4430 unsigned CCP1MODE1
: 1;
4431 unsigned CCP1MODE2
: 1;
4432 unsigned CCP1MODE3
: 1;
4433 unsigned CCP1FMT
: 1;
4434 unsigned CCP1OUT
: 1;
4436 unsigned CCP1EN
: 1;
4441 unsigned CCP1MODE
: 4;
4452 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
4455 #define _CCP1MODE0 0x01
4457 #define _CCP1MODE1 0x02
4459 #define _CCP1MODE2 0x04
4461 #define _CCP1MODE3 0x08
4463 #define _CCP1FMT 0x10
4465 #define _CCP1OUT 0x20
4467 #define _CCP1EN 0x80
4469 //==============================================================================
4472 //==============================================================================
4475 extern __at(0x0294) __sfr CCP1CAP
;
4493 unsigned CCP1CTS0
: 1;
4494 unsigned CCP1CTS1
: 1;
4495 unsigned CCP1CTS2
: 1;
4496 unsigned CCP1CTS3
: 1;
4505 unsigned CCP1CTS
: 4;
4516 extern __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits
;
4519 #define _CCP1CTS0 0x01
4521 #define _CCP1CTS1 0x02
4523 #define _CCP1CTS2 0x04
4525 #define _CCP1CTS3 0x08
4527 //==============================================================================
4529 extern __at(0x0295) __sfr CCPR2
;
4530 extern __at(0x0295) __sfr CCPR2L
;
4531 extern __at(0x0296) __sfr CCPR2H
;
4533 //==============================================================================
4536 extern __at(0x0297) __sfr CCP2CON
;
4554 unsigned CCP2MODE0
: 1;
4555 unsigned CCP2MODE1
: 1;
4556 unsigned CCP2MODE2
: 1;
4557 unsigned CCP2MODE3
: 1;
4558 unsigned CCP2FMT
: 1;
4559 unsigned CCP2OUT
: 1;
4561 unsigned CCP2EN
: 1;
4566 unsigned CCP2MODE
: 4;
4577 extern __at(0x0297) volatile __CCP2CONbits_t CCP2CONbits
;
4579 #define _CCP2CON_MODE0 0x01
4580 #define _CCP2CON_CCP2MODE0 0x01
4581 #define _CCP2CON_MODE1 0x02
4582 #define _CCP2CON_CCP2MODE1 0x02
4583 #define _CCP2CON_MODE2 0x04
4584 #define _CCP2CON_CCP2MODE2 0x04
4585 #define _CCP2CON_MODE3 0x08
4586 #define _CCP2CON_CCP2MODE3 0x08
4587 #define _CCP2CON_FMT 0x10
4588 #define _CCP2CON_CCP2FMT 0x10
4589 #define _CCP2CON_OUT 0x20
4590 #define _CCP2CON_CCP2OUT 0x20
4591 #define _CCP2CON_EN 0x80
4592 #define _CCP2CON_CCP2EN 0x80
4594 //==============================================================================
4597 //==============================================================================
4600 extern __at(0x0298) __sfr CCP2CAP
;
4618 unsigned CCP2CTS0
: 1;
4619 unsigned CCP2CTS1
: 1;
4620 unsigned CCP2CTS2
: 1;
4621 unsigned CCP2CTS3
: 1;
4630 unsigned CCP2CTS
: 4;
4641 extern __at(0x0298) volatile __CCP2CAPbits_t CCP2CAPbits
;
4643 #define _CCP2CAP_CTS0 0x01
4644 #define _CCP2CAP_CCP2CTS0 0x01
4645 #define _CCP2CAP_CTS1 0x02
4646 #define _CCP2CAP_CCP2CTS1 0x02
4647 #define _CCP2CAP_CTS2 0x04
4648 #define _CCP2CAP_CCP2CTS2 0x04
4649 #define _CCP2CAP_CTS3 0x08
4650 #define _CCP2CAP_CCP2CTS3 0x08
4652 //==============================================================================
4654 extern __at(0x0299) __sfr CCPR7
;
4655 extern __at(0x0299) __sfr CCPR7L
;
4656 extern __at(0x029A) __sfr CCPR7H
;
4658 //==============================================================================
4661 extern __at(0x029B) __sfr CCP7CON
;
4679 unsigned CCP7MODE0
: 1;
4680 unsigned CCP7MODE1
: 1;
4681 unsigned CCP7MODE2
: 1;
4682 unsigned CCP7MODE3
: 1;
4683 unsigned CCP7FMT
: 1;
4684 unsigned CCP7OUT
: 1;
4686 unsigned CCP7EN
: 1;
4691 unsigned CCP7MODE
: 4;
4702 extern __at(0x029B) volatile __CCP7CONbits_t CCP7CONbits
;
4704 #define _CCP7CON_MODE0 0x01
4705 #define _CCP7CON_CCP7MODE0 0x01
4706 #define _CCP7CON_MODE1 0x02
4707 #define _CCP7CON_CCP7MODE1 0x02
4708 #define _CCP7CON_MODE2 0x04
4709 #define _CCP7CON_CCP7MODE2 0x04
4710 #define _CCP7CON_MODE3 0x08
4711 #define _CCP7CON_CCP7MODE3 0x08
4712 #define _CCP7CON_FMT 0x10
4713 #define _CCP7CON_CCP7FMT 0x10
4714 #define _CCP7CON_OUT 0x20
4715 #define _CCP7CON_CCP7OUT 0x20
4716 #define _CCP7CON_EN 0x80
4717 #define _CCP7CON_CCP7EN 0x80
4719 //==============================================================================
4722 //==============================================================================
4725 extern __at(0x029C) __sfr CCP7CAP
;
4743 unsigned CCP7CTS0
: 1;
4744 unsigned CCP7CTS1
: 1;
4745 unsigned CCP7CTS2
: 1;
4746 unsigned CCP7CTS3
: 1;
4755 unsigned CCP7CTS
: 4;
4766 extern __at(0x029C) volatile __CCP7CAPbits_t CCP7CAPbits
;
4768 #define _CCP7CAP_CTS0 0x01
4769 #define _CCP7CAP_CCP7CTS0 0x01
4770 #define _CCP7CAP_CTS1 0x02
4771 #define _CCP7CAP_CCP7CTS1 0x02
4772 #define _CCP7CAP_CTS2 0x04
4773 #define _CCP7CAP_CCP7CTS2 0x04
4774 #define _CCP7CAP_CTS3 0x08
4775 #define _CCP7CAP_CCP7CTS3 0x08
4777 //==============================================================================
4780 //==============================================================================
4783 extern __at(0x029E) __sfr CCPTMRS1
;
4789 unsigned C1TSEL0
: 1;
4790 unsigned C1TSEL1
: 1;
4791 unsigned C2TSEL0
: 1;
4792 unsigned C2TSEL1
: 1;
4793 unsigned C7TSEL0
: 1;
4794 unsigned C7TSEL1
: 1;
4801 unsigned C1TSEL
: 2;
4808 unsigned C2TSEL
: 2;
4815 unsigned C7TSEL
: 2;
4820 extern __at(0x029E) volatile __CCPTMRS1bits_t CCPTMRS1bits
;
4822 #define _C1TSEL0 0x01
4823 #define _C1TSEL1 0x02
4824 #define _C2TSEL0 0x04
4825 #define _C2TSEL1 0x08
4826 #define _C7TSEL0 0x10
4827 #define _C7TSEL1 0x20
4829 //==============================================================================
4832 //==============================================================================
4835 extern __at(0x029F) __sfr CCPTMRS2
;
4841 unsigned P3TSEL0
: 1;
4842 unsigned P3TSEL1
: 1;
4843 unsigned P4TSEL0
: 1;
4844 unsigned P4TSEL1
: 1;
4845 unsigned P9TSEL0
: 1;
4846 unsigned P9TSEL1
: 1;
4853 unsigned P3TSEL
: 2;
4860 unsigned P4TSEL
: 2;
4867 unsigned P9TSEL
: 2;
4872 extern __at(0x029F) volatile __CCPTMRS2bits_t CCPTMRS2bits
;
4874 #define _P3TSEL0 0x01
4875 #define _P3TSEL1 0x02
4876 #define _P4TSEL0 0x04
4877 #define _P4TSEL1 0x08
4878 #define _P9TSEL0 0x10
4879 #define _P9TSEL1 0x20
4881 //==============================================================================
4884 //==============================================================================
4887 extern __at(0x030C) __sfr SLRCONA
;
4901 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
4912 //==============================================================================
4915 //==============================================================================
4918 extern __at(0x030D) __sfr SLRCONB
;
4932 extern __at(0x030D) volatile __SLRCONBbits_t SLRCONBbits
;
4943 //==============================================================================
4946 //==============================================================================
4949 extern __at(0x030E) __sfr SLRCONC
;
4963 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
4974 //==============================================================================
4977 //==============================================================================
4980 extern __at(0x0315) __sfr MD1CON0
;
4998 unsigned MD1BIT
: 1;
5002 unsigned MD1OPOL
: 1;
5003 unsigned MD1OUT
: 1;
5009 extern __at(0x0315) volatile __MD1CON0bits_t MD1CON0bits
;
5011 #define _MD1CON0_BIT 0x01
5012 #define _MD1CON0_MD1BIT 0x01
5013 #define _MD1CON0_OPOL 0x10
5014 #define _MD1CON0_MD1OPOL 0x10
5015 #define _MD1CON0_OUT 0x20
5016 #define _MD1CON0_MD1OUT 0x20
5017 #define _MD1CON0_EN 0x80
5018 #define _MD1CON0_MD1EN 0x80
5020 //==============================================================================
5023 //==============================================================================
5026 extern __at(0x0316) __sfr MD1CON1
;
5032 unsigned CLSYNC
: 1;
5036 unsigned CHSYNC
: 1;
5044 unsigned MD1CLSYNC
: 1;
5045 unsigned MD1CLPOL
: 1;
5048 unsigned MD1CHSYNC
: 1;
5049 unsigned MD1CHPOL
: 1;
5055 extern __at(0x0316) volatile __MD1CON1bits_t MD1CON1bits
;
5057 #define _CLSYNC 0x01
5058 #define _MD1CLSYNC 0x01
5060 #define _MD1CLPOL 0x02
5061 #define _CHSYNC 0x10
5062 #define _MD1CHSYNC 0x10
5064 #define _MD1CHPOL 0x20
5066 //==============================================================================
5069 //==============================================================================
5072 extern __at(0x0317) __sfr MD1SRC
;
5090 unsigned MD1MS0
: 1;
5091 unsigned MD1MS1
: 1;
5092 unsigned MD1MS2
: 1;
5093 unsigned MD1MS3
: 1;
5094 unsigned MD1MS4
: 1;
5113 extern __at(0x0317) volatile __MD1SRCbits_t MD1SRCbits
;
5116 #define _MD1MS0 0x01
5118 #define _MD1MS1 0x02
5120 #define _MD1MS2 0x04
5122 #define _MD1MS3 0x08
5124 #define _MD1MS4 0x10
5126 //==============================================================================
5129 //==============================================================================
5132 extern __at(0x0318) __sfr MD1CARL
;
5150 unsigned MD1CL0
: 1;
5151 unsigned MD1CL1
: 1;
5152 unsigned MD1CL2
: 1;
5153 unsigned MD1CL3
: 1;
5173 extern __at(0x0318) volatile __MD1CARLbits_t MD1CARLbits
;
5176 #define _MD1CL0 0x01
5178 #define _MD1CL1 0x02
5180 #define _MD1CL2 0x04
5182 #define _MD1CL3 0x08
5185 //==============================================================================
5188 //==============================================================================
5191 extern __at(0x0319) __sfr MD1CARH
;
5209 unsigned MD1CH0
: 1;
5210 unsigned MD1CH1
: 1;
5211 unsigned MD1CH2
: 1;
5212 unsigned MD1CH3
: 1;
5232 extern __at(0x0319) volatile __MD1CARHbits_t MD1CARHbits
;
5235 #define _MD1CH0 0x01
5237 #define _MD1CH1 0x02
5239 #define _MD1CH2 0x04
5241 #define _MD1CH3 0x08
5244 //==============================================================================
5247 //==============================================================================
5250 extern __at(0x031B) __sfr MD2CON0
;
5268 unsigned MD2BIT
: 1;
5272 unsigned MD2OPOL
: 1;
5273 unsigned MD2OUT
: 1;
5279 extern __at(0x031B) volatile __MD2CON0bits_t MD2CON0bits
;
5281 #define _MD2CON0_BIT 0x01
5282 #define _MD2CON0_MD2BIT 0x01
5283 #define _MD2CON0_OPOL 0x10
5284 #define _MD2CON0_MD2OPOL 0x10
5285 #define _MD2CON0_OUT 0x20
5286 #define _MD2CON0_MD2OUT 0x20
5287 #define _MD2CON0_EN 0x80
5288 #define _MD2CON0_MD2EN 0x80
5290 //==============================================================================
5293 //==============================================================================
5296 extern __at(0x031C) __sfr MD2CON1
;
5302 unsigned CLSYNC
: 1;
5306 unsigned CHSYNC
: 1;
5314 unsigned MD2CLSYNC
: 1;
5315 unsigned MD2CLPOL
: 1;
5318 unsigned MD2CHSYNC
: 1;
5319 unsigned MD2CHPOL
: 1;
5325 extern __at(0x031C) volatile __MD2CON1bits_t MD2CON1bits
;
5327 #define _MD2CON1_CLSYNC 0x01
5328 #define _MD2CON1_MD2CLSYNC 0x01
5329 #define _MD2CON1_CLPOL 0x02
5330 #define _MD2CON1_MD2CLPOL 0x02
5331 #define _MD2CON1_CHSYNC 0x10
5332 #define _MD2CON1_MD2CHSYNC 0x10
5333 #define _MD2CON1_CHPOL 0x20
5334 #define _MD2CON1_MD2CHPOL 0x20
5336 //==============================================================================
5339 //==============================================================================
5342 extern __at(0x031D) __sfr MD2SRC
;
5360 unsigned MD2MS0
: 1;
5361 unsigned MD2MS1
: 1;
5362 unsigned MD2MS2
: 1;
5363 unsigned MD2MS3
: 1;
5364 unsigned MD2MS4
: 1;
5383 extern __at(0x031D) volatile __MD2SRCbits_t MD2SRCbits
;
5385 #define _MD2SRC_MS0 0x01
5386 #define _MD2SRC_MD2MS0 0x01
5387 #define _MD2SRC_MS1 0x02
5388 #define _MD2SRC_MD2MS1 0x02
5389 #define _MD2SRC_MS2 0x04
5390 #define _MD2SRC_MD2MS2 0x04
5391 #define _MD2SRC_MS3 0x08
5392 #define _MD2SRC_MD2MS3 0x08
5393 #define _MD2SRC_MS4 0x10
5394 #define _MD2SRC_MD2MS4 0x10
5396 //==============================================================================
5399 //==============================================================================
5402 extern __at(0x031E) __sfr MD2CARL
;
5420 unsigned MD2CL0
: 1;
5421 unsigned MD2CL1
: 1;
5422 unsigned MD2CL2
: 1;
5423 unsigned MD2CL3
: 1;
5443 extern __at(0x031E) volatile __MD2CARLbits_t MD2CARLbits
;
5445 #define _MD2CARL_CL0 0x01
5446 #define _MD2CARL_MD2CL0 0x01
5447 #define _MD2CARL_CL1 0x02
5448 #define _MD2CARL_MD2CL1 0x02
5449 #define _MD2CARL_CL2 0x04
5450 #define _MD2CARL_MD2CL2 0x04
5451 #define _MD2CARL_CL3 0x08
5452 #define _MD2CARL_MD2CL3 0x08
5453 #define _MD2CARL_CL4 0x10
5455 //==============================================================================
5458 //==============================================================================
5461 extern __at(0x031F) __sfr MD2CARH
;
5479 unsigned MD2CH0
: 1;
5480 unsigned MD2CH1
: 1;
5481 unsigned MD2CH2
: 1;
5482 unsigned MD2CH3
: 1;
5502 extern __at(0x031F) volatile __MD2CARHbits_t MD2CARHbits
;
5504 #define _MD2CARH_CH0 0x01
5505 #define _MD2CARH_MD2CH0 0x01
5506 #define _MD2CARH_CH1 0x02
5507 #define _MD2CARH_MD2CH1 0x02
5508 #define _MD2CARH_CH2 0x04
5509 #define _MD2CARH_MD2CH2 0x04
5510 #define _MD2CARH_CH3 0x08
5511 #define _MD2CARH_MD2CH3 0x08
5512 #define _MD2CARH_CH4 0x10
5514 //==============================================================================
5517 //==============================================================================
5520 extern __at(0x038C) __sfr INLVLA
;
5526 unsigned INLVLA0
: 1;
5527 unsigned INLVLA1
: 1;
5528 unsigned INLVLA2
: 1;
5529 unsigned INLVLA3
: 1;
5530 unsigned INLVLA4
: 1;
5531 unsigned INLVLA5
: 1;
5532 unsigned INLVA6
: 1;
5533 unsigned INLVA7
: 1;
5538 unsigned INLVLA
: 6;
5543 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
5545 #define _INLVLA0 0x01
5546 #define _INLVLA1 0x02
5547 #define _INLVLA2 0x04
5548 #define _INLVLA3 0x08
5549 #define _INLVLA4 0x10
5550 #define _INLVLA5 0x20
5551 #define _INLVA6 0x40
5552 #define _INLVA7 0x80
5554 //==============================================================================
5557 //==============================================================================
5560 extern __at(0x038D) __sfr INLVLB
;
5566 unsigned INLVB0
: 1;
5567 unsigned INLVB1
: 1;
5568 unsigned INLVB2
: 1;
5569 unsigned INLVB3
: 1;
5570 unsigned INLVLB4
: 1;
5571 unsigned INLVLB5
: 1;
5572 unsigned INLVLB6
: 1;
5573 unsigned INLVLB7
: 1;
5583 extern __at(0x038D) volatile __INLVLBbits_t INLVLBbits
;
5585 #define _INLVB0 0x01
5586 #define _INLVB1 0x02
5587 #define _INLVB2 0x04
5588 #define _INLVB3 0x08
5589 #define _INLVLB4 0x10
5590 #define _INLVLB5 0x20
5591 #define _INLVLB6 0x40
5592 #define _INLVLB7 0x80
5594 //==============================================================================
5597 //==============================================================================
5600 extern __at(0x038E) __sfr INLVLC
;
5604 unsigned INLVLC0
: 1;
5605 unsigned INLVLC1
: 1;
5606 unsigned INLVLC2
: 1;
5607 unsigned INLVLC3
: 1;
5608 unsigned INLVLC4
: 1;
5609 unsigned INLVLC5
: 1;
5610 unsigned INLVLC6
: 1;
5611 unsigned INLVLC7
: 1;
5614 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
5616 #define _INLVLC0 0x01
5617 #define _INLVLC1 0x02
5618 #define _INLVLC2 0x04
5619 #define _INLVLC3 0x08
5620 #define _INLVLC4 0x10
5621 #define _INLVLC5 0x20
5622 #define _INLVLC6 0x40
5623 #define _INLVLC7 0x80
5625 //==============================================================================
5628 //==============================================================================
5631 extern __at(0x0390) __sfr INLVE
;
5638 unsigned INLVE3
: 1;
5645 extern __at(0x0390) volatile __INLVEbits_t INLVEbits
;
5647 #define _INLVE3 0x08
5649 //==============================================================================
5652 //==============================================================================
5655 extern __at(0x0391) __sfr IOCAP
;
5659 unsigned IOCAP0
: 1;
5660 unsigned IOCAP1
: 1;
5661 unsigned IOCAP2
: 1;
5662 unsigned IOCAP3
: 1;
5663 unsigned IOCAP4
: 1;
5664 unsigned IOCAP5
: 1;
5665 unsigned IOCAP6
: 1;
5666 unsigned IOCAP7
: 1;
5669 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
5671 #define _IOCAP0 0x01
5672 #define _IOCAP1 0x02
5673 #define _IOCAP2 0x04
5674 #define _IOCAP3 0x08
5675 #define _IOCAP4 0x10
5676 #define _IOCAP5 0x20
5677 #define _IOCAP6 0x40
5678 #define _IOCAP7 0x80
5680 //==============================================================================
5683 //==============================================================================
5686 extern __at(0x0392) __sfr IOCAN
;
5690 unsigned IOCAN0
: 1;
5691 unsigned IOCAN1
: 1;
5692 unsigned IOCAN2
: 1;
5693 unsigned IOCAN3
: 1;
5694 unsigned IOCAN4
: 1;
5695 unsigned IOCAN5
: 1;
5696 unsigned IOCAN6
: 1;
5697 unsigned IOCAN7
: 1;
5700 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
5702 #define _IOCAN0 0x01
5703 #define _IOCAN1 0x02
5704 #define _IOCAN2 0x04
5705 #define _IOCAN3 0x08
5706 #define _IOCAN4 0x10
5707 #define _IOCAN5 0x20
5708 #define _IOCAN6 0x40
5709 #define _IOCAN7 0x80
5711 //==============================================================================
5714 //==============================================================================
5717 extern __at(0x0393) __sfr IOCAF
;
5721 unsigned IOCAF0
: 1;
5722 unsigned IOCAF1
: 1;
5723 unsigned IOCAF2
: 1;
5724 unsigned IOCAF3
: 1;
5725 unsigned IOCAF4
: 1;
5726 unsigned IOCAF5
: 1;
5727 unsigned IOCAF6
: 1;
5728 unsigned IOCAF7
: 1;
5731 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
5733 #define _IOCAF0 0x01
5734 #define _IOCAF1 0x02
5735 #define _IOCAF2 0x04
5736 #define _IOCAF3 0x08
5737 #define _IOCAF4 0x10
5738 #define _IOCAF5 0x20
5739 #define _IOCAF6 0x40
5740 #define _IOCAF7 0x80
5742 //==============================================================================
5745 //==============================================================================
5748 extern __at(0x0394) __sfr IOCBP
;
5752 unsigned IOCBP0
: 1;
5753 unsigned IOCBP1
: 1;
5754 unsigned IOCBP2
: 1;
5755 unsigned IOCBP3
: 1;
5756 unsigned IOCBP4
: 1;
5757 unsigned IOCBP5
: 1;
5758 unsigned IOCBP6
: 1;
5759 unsigned IOCBP7
: 1;
5762 extern __at(0x0394) volatile __IOCBPbits_t IOCBPbits
;
5764 #define _IOCBP0 0x01
5765 #define _IOCBP1 0x02
5766 #define _IOCBP2 0x04
5767 #define _IOCBP3 0x08
5768 #define _IOCBP4 0x10
5769 #define _IOCBP5 0x20
5770 #define _IOCBP6 0x40
5771 #define _IOCBP7 0x80
5773 //==============================================================================
5776 //==============================================================================
5779 extern __at(0x0395) __sfr IOCBN
;
5783 unsigned IOCBN0
: 1;
5784 unsigned IOCBN1
: 1;
5785 unsigned IOCBN2
: 1;
5786 unsigned IOCBN3
: 1;
5787 unsigned IOCBN4
: 1;
5788 unsigned IOCBN5
: 1;
5789 unsigned IOCBN6
: 1;
5790 unsigned IOCBN7
: 1;
5793 extern __at(0x0395) volatile __IOCBNbits_t IOCBNbits
;
5795 #define _IOCBN0 0x01
5796 #define _IOCBN1 0x02
5797 #define _IOCBN2 0x04
5798 #define _IOCBN3 0x08
5799 #define _IOCBN4 0x10
5800 #define _IOCBN5 0x20
5801 #define _IOCBN6 0x40
5802 #define _IOCBN7 0x80
5804 //==============================================================================
5807 //==============================================================================
5810 extern __at(0x0396) __sfr IOCBF
;
5814 unsigned IOCBF0
: 1;
5815 unsigned IOCBF1
: 1;
5816 unsigned IOCBF2
: 1;
5817 unsigned IOCBF3
: 1;
5818 unsigned IOCBF4
: 1;
5819 unsigned IOCBF5
: 1;
5820 unsigned IOCBF6
: 1;
5821 unsigned IOCBF7
: 1;
5824 extern __at(0x0396) volatile __IOCBFbits_t IOCBFbits
;
5826 #define _IOCBF0 0x01
5827 #define _IOCBF1 0x02
5828 #define _IOCBF2 0x04
5829 #define _IOCBF3 0x08
5830 #define _IOCBF4 0x10
5831 #define _IOCBF5 0x20
5832 #define _IOCBF6 0x40
5833 #define _IOCBF7 0x80
5835 //==============================================================================
5838 //==============================================================================
5841 extern __at(0x0397) __sfr IOCCP
;
5845 unsigned IOCCP0
: 1;
5846 unsigned IOCCP1
: 1;
5847 unsigned IOCCP2
: 1;
5848 unsigned IOCCP3
: 1;
5849 unsigned IOCCP4
: 1;
5850 unsigned IOCCP5
: 1;
5851 unsigned IOCCP6
: 1;
5852 unsigned IOCCP7
: 1;
5855 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
5857 #define _IOCCP0 0x01
5858 #define _IOCCP1 0x02
5859 #define _IOCCP2 0x04
5860 #define _IOCCP3 0x08
5861 #define _IOCCP4 0x10
5862 #define _IOCCP5 0x20
5863 #define _IOCCP6 0x40
5864 #define _IOCCP7 0x80
5866 //==============================================================================
5869 //==============================================================================
5872 extern __at(0x0398) __sfr IOCCN
;
5876 unsigned IOCCN0
: 1;
5877 unsigned IOCCN1
: 1;
5878 unsigned IOCCN2
: 1;
5879 unsigned IOCCN3
: 1;
5880 unsigned IOCCN4
: 1;
5881 unsigned IOCCN5
: 1;
5882 unsigned IOCCN6
: 1;
5883 unsigned IOCCN7
: 1;
5886 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
5888 #define _IOCCN0 0x01
5889 #define _IOCCN1 0x02
5890 #define _IOCCN2 0x04
5891 #define _IOCCN3 0x08
5892 #define _IOCCN4 0x10
5893 #define _IOCCN5 0x20
5894 #define _IOCCN6 0x40
5895 #define _IOCCN7 0x80
5897 //==============================================================================
5900 //==============================================================================
5903 extern __at(0x0399) __sfr IOCCF
;
5907 unsigned IOCCF0
: 1;
5908 unsigned IOCCF1
: 1;
5909 unsigned IOCCF2
: 1;
5910 unsigned IOCCF3
: 1;
5911 unsigned IOCCF4
: 1;
5912 unsigned IOCCF5
: 1;
5913 unsigned IOCCF6
: 1;
5914 unsigned IOCCF7
: 1;
5917 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
5919 #define _IOCCF0 0x01
5920 #define _IOCCF1 0x02
5921 #define _IOCCF2 0x04
5922 #define _IOCCF3 0x08
5923 #define _IOCCF4 0x10
5924 #define _IOCCF5 0x20
5925 #define _IOCCF6 0x40
5926 #define _IOCCF7 0x80
5928 //==============================================================================
5931 //==============================================================================
5934 extern __at(0x039D) __sfr IOCEP
;
5941 unsigned IOCEP3
: 1;
5948 extern __at(0x039D) volatile __IOCEPbits_t IOCEPbits
;
5950 #define _IOCEP3 0x08
5952 //==============================================================================
5955 //==============================================================================
5958 extern __at(0x039E) __sfr IOCEN
;
5965 unsigned IOCEN3
: 1;
5972 extern __at(0x039E) volatile __IOCENbits_t IOCENbits
;
5974 #define _IOCEN3 0x08
5976 //==============================================================================
5979 //==============================================================================
5982 extern __at(0x039F) __sfr IOCEF
;
5989 unsigned IOCEF3
: 1;
5996 extern __at(0x039F) volatile __IOCEFbits_t IOCEFbits
;
5998 #define _IOCEF3 0x08
6000 //==============================================================================
6003 //==============================================================================
6006 extern __at(0x040D) __sfr HIDRVB
;
6029 extern __at(0x040D) volatile __HIDRVBbits_t HIDRVBbits
;
6034 //==============================================================================
6036 extern __at(0x040F) __sfr TMR5
;
6037 extern __at(0x040F) __sfr TMR5L
;
6038 extern __at(0x0410) __sfr TMR5H
;
6040 //==============================================================================
6043 extern __at(0x0411) __sfr T5CON
;
6051 unsigned NOT_SYNC
: 1;
6064 unsigned SOSCEN
: 1;
6065 unsigned T5CKPS0
: 1;
6066 unsigned T5CKPS1
: 1;
6073 unsigned TMR5ON
: 1;
6075 unsigned NOT_T5SYNC
: 1;
6076 unsigned T5OSCEN
: 1;
6079 unsigned TMR5CS0
: 1;
6080 unsigned TMR5CS1
: 1;
6098 unsigned T5CKPS
: 2;
6118 unsigned TMR5CS
: 2;
6128 extern __at(0x0411) volatile __T5CONbits_t T5CONbits
;
6130 #define _T5CON_ON 0x01
6131 #define _T5CON_TMRON 0x01
6132 #define _T5CON_TMR5ON 0x01
6133 #define _T5CON_T5ON 0x01
6134 #define _T5CON_NOT_SYNC 0x04
6135 #define _T5CON_SYNC 0x04
6136 #define _T5CON_NOT_T5SYNC 0x04
6137 #define _T5CON_OSCEN 0x08
6138 #define _T5CON_SOSCEN 0x08
6139 #define _T5CON_T5OSCEN 0x08
6140 #define _T5CON_CKPS0 0x10
6141 #define _T5CON_T5CKPS0 0x10
6142 #define _T5CON_CKPS1 0x20
6143 #define _T5CON_T5CKPS1 0x20
6144 #define _T5CON_CS0 0x40
6145 #define _T5CON_T5CS0 0x40
6146 #define _T5CON_TMR5CS0 0x40
6147 #define _T5CON_CS1 0x80
6148 #define _T5CON_T5CS1 0x80
6149 #define _T5CON_TMR5CS1 0x80
6151 //==============================================================================
6154 //==============================================================================
6157 extern __at(0x0412) __sfr T5GCON
;
6166 unsigned GGO_NOT_DONE
: 1;
6175 unsigned T5GSS0
: 1;
6176 unsigned T5GSS1
: 1;
6177 unsigned T5GVAL
: 1;
6178 unsigned T5GGO_NOT_DONE
: 1;
6179 unsigned T5GSPM
: 1;
6181 unsigned T5GPOL
: 1;
6194 unsigned TMR5GE
: 1;
6210 extern __at(0x0412) volatile __T5GCONbits_t T5GCONbits
;
6212 #define _T5GCON_GSS0 0x01
6213 #define _T5GCON_T5GSS0 0x01
6214 #define _T5GCON_GSS1 0x02
6215 #define _T5GCON_T5GSS1 0x02
6216 #define _T5GCON_GVAL 0x04
6217 #define _T5GCON_T5GVAL 0x04
6218 #define _T5GCON_GGO_NOT_DONE 0x08
6219 #define _T5GCON_T5GGO_NOT_DONE 0x08
6220 #define _T5GCON_GSPM 0x10
6221 #define _T5GCON_T5GSPM 0x10
6222 #define _T5GCON_GTM 0x20
6223 #define _T5GCON_T5GTM 0x20
6224 #define _T5GCON_GPOL 0x40
6225 #define _T5GCON_T5GPOL 0x40
6226 #define _T5GCON_GE 0x80
6227 #define _T5GCON_T5GE 0x80
6228 #define _T5GCON_TMR5GE 0x80
6230 //==============================================================================
6232 extern __at(0x0413) __sfr T4TMR
;
6233 extern __at(0x0413) __sfr TMR4
;
6234 extern __at(0x0414) __sfr PR4
;
6235 extern __at(0x0414) __sfr T4PR
;
6237 //==============================================================================
6240 extern __at(0x0415) __sfr T4CON
;
6246 unsigned OUTPS0
: 1;
6247 unsigned OUTPS1
: 1;
6248 unsigned OUTPS2
: 1;
6249 unsigned OUTPS3
: 1;
6258 unsigned T4OUTPS0
: 1;
6259 unsigned T4OUTPS1
: 1;
6260 unsigned T4OUTPS2
: 1;
6261 unsigned T4OUTPS3
: 1;
6262 unsigned T4CKPS0
: 1;
6263 unsigned T4CKPS1
: 1;
6264 unsigned T4CKPS2
: 1;
6277 unsigned TMR4ON
: 1;
6282 unsigned T4OUTPS
: 4;
6295 unsigned T4CKPS
: 3;
6307 extern __at(0x0415) volatile __T4CONbits_t T4CONbits
;
6309 #define _T4CON_OUTPS0 0x01
6310 #define _T4CON_T4OUTPS0 0x01
6311 #define _T4CON_OUTPS1 0x02
6312 #define _T4CON_T4OUTPS1 0x02
6313 #define _T4CON_OUTPS2 0x04
6314 #define _T4CON_T4OUTPS2 0x04
6315 #define _T4CON_OUTPS3 0x08
6316 #define _T4CON_T4OUTPS3 0x08
6317 #define _T4CON_CKPS0 0x10
6318 #define _T4CON_T4CKPS0 0x10
6319 #define _T4CON_CKPS1 0x20
6320 #define _T4CON_T4CKPS1 0x20
6321 #define _T4CON_CKPS2 0x40
6322 #define _T4CON_T4CKPS2 0x40
6323 #define _T4CON_ON 0x80
6324 #define _T4CON_T4ON 0x80
6325 #define _T4CON_TMR4ON 0x80
6327 //==============================================================================
6330 //==============================================================================
6333 extern __at(0x0416) __sfr T4HLT
;
6344 unsigned CKSYNC
: 1;
6351 unsigned T4MODE0
: 1;
6352 unsigned T4MODE1
: 1;
6353 unsigned T4MODE2
: 1;
6354 unsigned T4MODE3
: 1;
6355 unsigned T4MODE4
: 1;
6356 unsigned T4CKSYNC
: 1;
6357 unsigned T4CKPOL
: 1;
6358 unsigned T4PSYNC
: 1;
6363 unsigned T4MODE
: 5;
6374 extern __at(0x0416) volatile __T4HLTbits_t T4HLTbits
;
6376 #define _T4HLT_MODE0 0x01
6377 #define _T4HLT_T4MODE0 0x01
6378 #define _T4HLT_MODE1 0x02
6379 #define _T4HLT_T4MODE1 0x02
6380 #define _T4HLT_MODE2 0x04
6381 #define _T4HLT_T4MODE2 0x04
6382 #define _T4HLT_MODE3 0x08
6383 #define _T4HLT_T4MODE3 0x08
6384 #define _T4HLT_MODE4 0x10
6385 #define _T4HLT_T4MODE4 0x10
6386 #define _T4HLT_CKSYNC 0x20
6387 #define _T4HLT_T4CKSYNC 0x20
6388 #define _T4HLT_CKPOL 0x40
6389 #define _T4HLT_T4CKPOL 0x40
6390 #define _T4HLT_PSYNC 0x80
6391 #define _T4HLT_T4PSYNC 0x80
6393 //==============================================================================
6396 //==============================================================================
6399 extern __at(0x0417) __sfr T4CLKCON
;
6440 extern __at(0x0417) volatile __T4CLKCONbits_t T4CLKCONbits
;
6442 #define _T4CLKCON_CS0 0x01
6443 #define _T4CLKCON_T4CS0 0x01
6444 #define _T4CLKCON_CS1 0x02
6445 #define _T4CLKCON_T4CS1 0x02
6446 #define _T4CLKCON_CS2 0x04
6447 #define _T4CLKCON_T4CS2 0x04
6448 #define _T4CLKCON_CS3 0x08
6449 #define _T4CLKCON_T4CS3 0x08
6451 //==============================================================================
6454 //==============================================================================
6457 extern __at(0x0418) __sfr T4RST
;
6475 unsigned T4RSEL0
: 1;
6476 unsigned T4RSEL1
: 1;
6477 unsigned T4RSEL2
: 1;
6478 unsigned T4RSEL3
: 1;
6479 unsigned T4RSEL4
: 1;
6493 unsigned T4RSEL
: 5;
6498 extern __at(0x0418) volatile __T4RSTbits_t T4RSTbits
;
6500 #define _T4RST_RSEL0 0x01
6501 #define _T4RST_T4RSEL0 0x01
6502 #define _T4RST_RSEL1 0x02
6503 #define _T4RST_T4RSEL1 0x02
6504 #define _T4RST_RSEL2 0x04
6505 #define _T4RST_T4RSEL2 0x04
6506 #define _T4RST_RSEL3 0x08
6507 #define _T4RST_T4RSEL3 0x08
6508 #define _T4RST_RSEL4 0x10
6509 #define _T4RST_T4RSEL4 0x10
6511 //==============================================================================
6513 extern __at(0x041A) __sfr T6TMR
;
6514 extern __at(0x041A) __sfr TMR6
;
6515 extern __at(0x041B) __sfr PR6
;
6516 extern __at(0x041B) __sfr T6PR
;
6518 //==============================================================================
6521 extern __at(0x041C) __sfr T6CON
;
6527 unsigned OUTPS0
: 1;
6528 unsigned OUTPS1
: 1;
6529 unsigned OUTPS2
: 1;
6530 unsigned OUTPS3
: 1;
6539 unsigned T6OUTPS0
: 1;
6540 unsigned T6OUTPS1
: 1;
6541 unsigned T6OUTPS2
: 1;
6542 unsigned T6OUTPS3
: 1;
6543 unsigned T6CKPS0
: 1;
6544 unsigned T6CKPS1
: 1;
6545 unsigned T6CKPS2
: 1;
6558 unsigned TMR6ON
: 1;
6563 unsigned T6OUTPS
: 4;
6583 unsigned T6CKPS
: 3;
6588 extern __at(0x041C) volatile __T6CONbits_t T6CONbits
;
6590 #define _T6CON_OUTPS0 0x01
6591 #define _T6CON_T6OUTPS0 0x01
6592 #define _T6CON_OUTPS1 0x02
6593 #define _T6CON_T6OUTPS1 0x02
6594 #define _T6CON_OUTPS2 0x04
6595 #define _T6CON_T6OUTPS2 0x04
6596 #define _T6CON_OUTPS3 0x08
6597 #define _T6CON_T6OUTPS3 0x08
6598 #define _T6CON_CKPS0 0x10
6599 #define _T6CON_T6CKPS0 0x10
6600 #define _T6CON_CKPS1 0x20
6601 #define _T6CON_T6CKPS1 0x20
6602 #define _T6CON_CKPS2 0x40
6603 #define _T6CON_T6CKPS2 0x40
6604 #define _T6CON_ON 0x80
6605 #define _T6CON_T6ON 0x80
6606 #define _T6CON_TMR6ON 0x80
6608 //==============================================================================
6611 //==============================================================================
6614 extern __at(0x041D) __sfr T6HLT
;
6625 unsigned CKSYNC
: 1;
6632 unsigned T6MODE0
: 1;
6633 unsigned T6MODE1
: 1;
6634 unsigned T6MODE2
: 1;
6635 unsigned T6MODE3
: 1;
6636 unsigned T6MODE4
: 1;
6637 unsigned T6CKSYNC
: 1;
6638 unsigned T6CKPOL
: 1;
6639 unsigned T6PSYNC
: 1;
6650 unsigned T6MODE
: 5;
6655 extern __at(0x041D) volatile __T6HLTbits_t T6HLTbits
;
6657 #define _T6HLT_MODE0 0x01
6658 #define _T6HLT_T6MODE0 0x01
6659 #define _T6HLT_MODE1 0x02
6660 #define _T6HLT_T6MODE1 0x02
6661 #define _T6HLT_MODE2 0x04
6662 #define _T6HLT_T6MODE2 0x04
6663 #define _T6HLT_MODE3 0x08
6664 #define _T6HLT_T6MODE3 0x08
6665 #define _T6HLT_MODE4 0x10
6666 #define _T6HLT_T6MODE4 0x10
6667 #define _T6HLT_CKSYNC 0x20
6668 #define _T6HLT_T6CKSYNC 0x20
6669 #define _T6HLT_CKPOL 0x40
6670 #define _T6HLT_T6CKPOL 0x40
6671 #define _T6HLT_PSYNC 0x80
6672 #define _T6HLT_T6PSYNC 0x80
6674 //==============================================================================
6677 //==============================================================================
6680 extern __at(0x041E) __sfr T6CLKCON
;
6721 extern __at(0x041E) volatile __T6CLKCONbits_t T6CLKCONbits
;
6723 #define _T6CLKCON_CS0 0x01
6724 #define _T6CLKCON_T6CS0 0x01
6725 #define _T6CLKCON_CS1 0x02
6726 #define _T6CLKCON_T6CS1 0x02
6727 #define _T6CLKCON_CS2 0x04
6728 #define _T6CLKCON_T6CS2 0x04
6729 #define _T6CLKCON_CS3 0x08
6730 #define _T6CLKCON_T6CS3 0x08
6732 //==============================================================================
6735 //==============================================================================
6738 extern __at(0x041F) __sfr T6RST
;
6756 unsigned T6RSEL0
: 1;
6757 unsigned T6RSEL1
: 1;
6758 unsigned T6RSEL2
: 1;
6759 unsigned T6RSEL3
: 1;
6760 unsigned T6RSEL4
: 1;
6768 unsigned T6RSEL
: 5;
6779 extern __at(0x041F) volatile __T6RSTbits_t T6RSTbits
;
6781 #define _T6RST_RSEL0 0x01
6782 #define _T6RST_T6RSEL0 0x01
6783 #define _T6RST_RSEL1 0x02
6784 #define _T6RST_T6RSEL1 0x02
6785 #define _T6RST_RSEL2 0x04
6786 #define _T6RST_T6RSEL2 0x04
6787 #define _T6RST_RSEL3 0x08
6788 #define _T6RST_T6RSEL3 0x08
6789 #define _T6RST_RSEL4 0x10
6790 #define _T6RST_T6RSEL4 0x10
6792 //==============================================================================
6794 extern __at(0x048E) __sfr ADRESL
;
6795 extern __at(0x048F) __sfr ADRESH
;
6797 //==============================================================================
6800 extern __at(0x0490) __sfr ADCON0
;
6814 extern __at(0x0490) volatile __ADCON0bits_t ADCON0bits
;
6819 //==============================================================================
6822 //==============================================================================
6825 extern __at(0x0491) __sfr ADCON1
;
6831 unsigned ADNREF
: 1;
6839 extern __at(0x0491) volatile __ADCON1bits_t ADCON1bits
;
6841 #define _ADNREF 0x04
6844 //==============================================================================
6846 extern __at(0x0492) __sfr ADCON2
;
6847 extern __at(0x0493) __sfr T2TMR
;
6848 extern __at(0x0493) __sfr TMR2
;
6849 extern __at(0x0494) __sfr PR2
;
6850 extern __at(0x0494) __sfr T2PR
;
6852 //==============================================================================
6855 extern __at(0x0495) __sfr T2CON
;
6861 unsigned OUTPS0
: 1;
6862 unsigned OUTPS1
: 1;
6863 unsigned OUTPS2
: 1;
6864 unsigned OUTPS3
: 1;
6873 unsigned T2OUTPS0
: 1;
6874 unsigned T2OUTPS1
: 1;
6875 unsigned T2OUTPS2
: 1;
6876 unsigned T2OUTPS3
: 1;
6877 unsigned T2CKPS0
: 1;
6878 unsigned T2CKPS1
: 1;
6879 unsigned T2CKPS2
: 1;
6892 unsigned TMR2ON
: 1;
6903 unsigned T2OUTPS
: 4;
6910 unsigned T2CKPS
: 3;
6922 extern __at(0x0495) volatile __T2CONbits_t T2CONbits
;
6924 #define _T2CON_OUTPS0 0x01
6925 #define _T2CON_T2OUTPS0 0x01
6926 #define _T2CON_OUTPS1 0x02
6927 #define _T2CON_T2OUTPS1 0x02
6928 #define _T2CON_OUTPS2 0x04
6929 #define _T2CON_T2OUTPS2 0x04
6930 #define _T2CON_OUTPS3 0x08
6931 #define _T2CON_T2OUTPS3 0x08
6932 #define _T2CON_CKPS0 0x10
6933 #define _T2CON_T2CKPS0 0x10
6934 #define _T2CON_CKPS1 0x20
6935 #define _T2CON_T2CKPS1 0x20
6936 #define _T2CON_CKPS2 0x40
6937 #define _T2CON_T2CKPS2 0x40
6938 #define _T2CON_ON 0x80
6939 #define _T2CON_T2ON 0x80
6940 #define _T2CON_TMR2ON 0x80
6942 //==============================================================================
6945 //==============================================================================
6948 extern __at(0x0496) __sfr T2HLT
;
6959 unsigned CKSYNC
: 1;
6966 unsigned T2MODE0
: 1;
6967 unsigned T2MODE1
: 1;
6968 unsigned T2MODE2
: 1;
6969 unsigned T2MODE3
: 1;
6970 unsigned T2MODE4
: 1;
6971 unsigned T2CKSYNC
: 1;
6972 unsigned T2CKPOL
: 1;
6973 unsigned T2PSYNC
: 1;
6978 unsigned T2MODE
: 5;
6989 extern __at(0x0496) volatile __T2HLTbits_t T2HLTbits
;
6991 #define _T2HLT_MODE0 0x01
6992 #define _T2HLT_T2MODE0 0x01
6993 #define _T2HLT_MODE1 0x02
6994 #define _T2HLT_T2MODE1 0x02
6995 #define _T2HLT_MODE2 0x04
6996 #define _T2HLT_T2MODE2 0x04
6997 #define _T2HLT_MODE3 0x08
6998 #define _T2HLT_T2MODE3 0x08
6999 #define _T2HLT_MODE4 0x10
7000 #define _T2HLT_T2MODE4 0x10
7001 #define _T2HLT_CKSYNC 0x20
7002 #define _T2HLT_T2CKSYNC 0x20
7003 #define _T2HLT_CKPOL 0x40
7004 #define _T2HLT_T2CKPOL 0x40
7005 #define _T2HLT_PSYNC 0x80
7006 #define _T2HLT_T2PSYNC 0x80
7008 //==============================================================================
7011 //==============================================================================
7014 extern __at(0x0497) __sfr T2CLKCON
;
7055 extern __at(0x0497) volatile __T2CLKCONbits_t T2CLKCONbits
;
7057 #define _T2CLKCON_CS0 0x01
7058 #define _T2CLKCON_T2CS0 0x01
7059 #define _T2CLKCON_CS1 0x02
7060 #define _T2CLKCON_T2CS1 0x02
7061 #define _T2CLKCON_CS2 0x04
7062 #define _T2CLKCON_T2CS2 0x04
7063 #define _T2CLKCON_CS3 0x08
7064 #define _T2CLKCON_T2CS3 0x08
7066 //==============================================================================
7069 //==============================================================================
7072 extern __at(0x0498) __sfr T2RST
;
7090 unsigned T2RSEL0
: 1;
7091 unsigned T2RSEL1
: 1;
7092 unsigned T2RSEL2
: 1;
7093 unsigned T2RSEL3
: 1;
7094 unsigned T2RSEL4
: 1;
7102 unsigned T2RSEL
: 5;
7113 extern __at(0x0498) volatile __T2RSTbits_t T2RSTbits
;
7116 #define _T2RSEL0 0x01
7118 #define _T2RSEL1 0x02
7120 #define _T2RSEL2 0x04
7122 #define _T2RSEL3 0x08
7124 #define _T2RSEL4 0x10
7126 //==============================================================================
7128 extern __at(0x049A) __sfr T8TMR
;
7129 extern __at(0x049A) __sfr TMR8
;
7130 extern __at(0x049B) __sfr PR8
;
7131 extern __at(0x049B) __sfr T8PR
;
7133 //==============================================================================
7136 extern __at(0x049C) __sfr T8CON
;
7142 unsigned OUTPS0
: 1;
7143 unsigned OUTPS1
: 1;
7144 unsigned OUTPS2
: 1;
7145 unsigned OUTPS3
: 1;
7154 unsigned T8OUTPS0
: 1;
7155 unsigned T8OUTPS1
: 1;
7156 unsigned T8OUTPS2
: 1;
7157 unsigned T8OUTPS3
: 1;
7158 unsigned T8CKPS0
: 1;
7159 unsigned T8CKPS1
: 1;
7160 unsigned T8CKPS2
: 1;
7173 unsigned TMR8ON
: 1;
7178 unsigned T8OUTPS
: 4;
7191 unsigned T8CKPS
: 3;
7203 extern __at(0x049C) volatile __T8CONbits_t T8CONbits
;
7205 #define _T8CON_OUTPS0 0x01
7206 #define _T8CON_T8OUTPS0 0x01
7207 #define _T8CON_OUTPS1 0x02
7208 #define _T8CON_T8OUTPS1 0x02
7209 #define _T8CON_OUTPS2 0x04
7210 #define _T8CON_T8OUTPS2 0x04
7211 #define _T8CON_OUTPS3 0x08
7212 #define _T8CON_T8OUTPS3 0x08
7213 #define _T8CON_CKPS0 0x10
7214 #define _T8CON_T8CKPS0 0x10
7215 #define _T8CON_CKPS1 0x20
7216 #define _T8CON_T8CKPS1 0x20
7217 #define _T8CON_CKPS2 0x40
7218 #define _T8CON_T8CKPS2 0x40
7219 #define _T8CON_ON 0x80
7220 #define _T8CON_T8ON 0x80
7221 #define _T8CON_TMR8ON 0x80
7223 //==============================================================================
7226 //==============================================================================
7229 extern __at(0x049D) __sfr T8HLT
;
7240 unsigned CKSYNC
: 1;
7247 unsigned T8MODE0
: 1;
7248 unsigned T8MODE1
: 1;
7249 unsigned T8MODE2
: 1;
7250 unsigned T8MODE3
: 1;
7251 unsigned T8MODE4
: 1;
7252 unsigned T8CKSYNC
: 1;
7253 unsigned T8CKPOL
: 1;
7254 unsigned T8PSYNC
: 1;
7265 unsigned T8MODE
: 5;
7270 extern __at(0x049D) volatile __T8HLTbits_t T8HLTbits
;
7272 #define _T8HLT_MODE0 0x01
7273 #define _T8HLT_T8MODE0 0x01
7274 #define _T8HLT_MODE1 0x02
7275 #define _T8HLT_T8MODE1 0x02
7276 #define _T8HLT_MODE2 0x04
7277 #define _T8HLT_T8MODE2 0x04
7278 #define _T8HLT_MODE3 0x08
7279 #define _T8HLT_T8MODE3 0x08
7280 #define _T8HLT_MODE4 0x10
7281 #define _T8HLT_T8MODE4 0x10
7282 #define _T8HLT_CKSYNC 0x20
7283 #define _T8HLT_T8CKSYNC 0x20
7284 #define _T8HLT_CKPOL 0x40
7285 #define _T8HLT_T8CKPOL 0x40
7286 #define _T8HLT_PSYNC 0x80
7287 #define _T8HLT_T8PSYNC 0x80
7289 //==============================================================================
7292 //==============================================================================
7295 extern __at(0x049E) __sfr T8CLKCON
;
7336 extern __at(0x049E) volatile __T8CLKCONbits_t T8CLKCONbits
;
7338 #define _T8CLKCON_CS0 0x01
7339 #define _T8CLKCON_T8CS0 0x01
7340 #define _T8CLKCON_CS1 0x02
7341 #define _T8CLKCON_T8CS1 0x02
7342 #define _T8CLKCON_CS2 0x04
7343 #define _T8CLKCON_T8CS2 0x04
7344 #define _T8CLKCON_CS3 0x08
7345 #define _T8CLKCON_T8CS3 0x08
7347 //==============================================================================
7350 //==============================================================================
7353 extern __at(0x049F) __sfr T8RST
;
7371 unsigned T8RSEL0
: 1;
7372 unsigned T8RSEL1
: 1;
7373 unsigned T8RSEL2
: 1;
7374 unsigned T8RSEL3
: 1;
7375 unsigned T8RSEL4
: 1;
7383 unsigned T8RSEL
: 5;
7394 extern __at(0x049F) volatile __T8RSTbits_t T8RSTbits
;
7396 #define _T8RST_RSEL0 0x01
7397 #define _T8RST_T8RSEL0 0x01
7398 #define _T8RST_RSEL1 0x02
7399 #define _T8RST_T8RSEL1 0x02
7400 #define _T8RST_RSEL2 0x04
7401 #define _T8RST_T8RSEL2 0x04
7402 #define _T8RST_RSEL3 0x08
7403 #define _T8RST_T8RSEL3 0x08
7404 #define _T8RST_RSEL4 0x10
7405 #define _T8RST_T8RSEL4 0x10
7407 //==============================================================================
7409 extern __at(0x050F) __sfr OPA1NCHS
;
7410 extern __at(0x0510) __sfr OPA1PCHS
;
7412 //==============================================================================
7415 extern __at(0x0511) __sfr OPA1CON
;
7433 unsigned OPA1ORM0
: 1;
7434 unsigned OPA1ORM1
: 1;
7435 unsigned OPA1ORPOL
: 1;
7437 unsigned OPA1UG
: 1;
7440 unsigned OPA1EN
: 1;
7451 unsigned OPA1ORM
: 2;
7456 extern __at(0x0511) volatile __OPA1CONbits_t OPA1CONbits
;
7458 #define _OPA1CON_ORM0 0x01
7459 #define _OPA1CON_OPA1ORM0 0x01
7460 #define _OPA1CON_ORM1 0x02
7461 #define _OPA1CON_OPA1ORM1 0x02
7462 #define _OPA1CON_ORPOL 0x04
7463 #define _OPA1CON_OPA1ORPOL 0x04
7464 #define _OPA1CON_UG 0x10
7465 #define _OPA1CON_OPA1UG 0x10
7466 #define _OPA1CON_EN 0x80
7467 #define _OPA1CON_OPA1EN 0x80
7469 //==============================================================================
7471 extern __at(0x0512) __sfr OPA1ORS
;
7472 extern __at(0x0513) __sfr OPA2NCHS
;
7473 extern __at(0x0514) __sfr OPA2PCHS
;
7475 //==============================================================================
7478 extern __at(0x0515) __sfr OPA2CON
;
7496 unsigned OPA2ORM0
: 1;
7497 unsigned OPA2ORM1
: 1;
7498 unsigned OPA2ORPOL
: 1;
7500 unsigned OPA2UG
: 1;
7503 unsigned OPA2EN
: 1;
7514 unsigned OPA2ORM
: 2;
7519 extern __at(0x0515) volatile __OPA2CONbits_t OPA2CONbits
;
7521 #define _OPA2CON_ORM0 0x01
7522 #define _OPA2CON_OPA2ORM0 0x01
7523 #define _OPA2CON_ORM1 0x02
7524 #define _OPA2CON_OPA2ORM1 0x02
7525 #define _OPA2CON_ORPOL 0x04
7526 #define _OPA2CON_OPA2ORPOL 0x04
7527 #define _OPA2CON_UG 0x10
7528 #define _OPA2CON_OPA2UG 0x10
7529 #define _OPA2CON_EN 0x80
7530 #define _OPA2CON_OPA2EN 0x80
7532 //==============================================================================
7534 extern __at(0x0516) __sfr OPA2ORS
;
7535 extern __at(0x0517) __sfr OPA3NCHS
;
7536 extern __at(0x0518) __sfr OPA3PCHS
;
7538 //==============================================================================
7541 extern __at(0x0519) __sfr OPA3CON
;
7559 unsigned OPA3ORM0
: 1;
7560 unsigned OPA3ORM1
: 1;
7561 unsigned OPA3ORPOL
: 1;
7563 unsigned OPA3UG
: 1;
7565 unsigned OPA3SP
: 1;
7566 unsigned OPA3EN
: 1;
7571 unsigned OPA3ORM
: 2;
7582 extern __at(0x0519) volatile __OPA3CONbits_t OPA3CONbits
;
7584 #define _OPA3CON_ORM0 0x01
7585 #define _OPA3CON_OPA3ORM0 0x01
7586 #define _OPA3CON_ORM1 0x02
7587 #define _OPA3CON_OPA3ORM1 0x02
7588 #define _OPA3CON_ORPOL 0x04
7589 #define _OPA3CON_OPA3ORPOL 0x04
7590 #define _OPA3CON_UG 0x10
7591 #define _OPA3CON_OPA3UG 0x10
7592 #define _OPA3CON_SP 0x40
7593 #define _OPA3CON_OPA3SP 0x40
7594 #define _OPA3CON_EN 0x80
7595 #define _OPA3CON_OPA3EN 0x80
7597 //==============================================================================
7599 extern __at(0x051A) __sfr OPA3ORS
;
7601 //==============================================================================
7604 extern __at(0x058D) __sfr DACLD
;
7608 unsigned DAC1LD
: 1;
7609 unsigned DAC2LD
: 1;
7612 unsigned DAC5LD
: 1;
7618 extern __at(0x058D) volatile __DACLDbits_t DACLDbits
;
7620 #define _DAC1LD 0x01
7621 #define _DAC2LD 0x02
7622 #define _DAC5LD 0x10
7624 //==============================================================================
7627 //==============================================================================
7630 extern __at(0x058E) __sfr DAC1CON0
;
7648 unsigned DACNSS0
: 1;
7649 unsigned DACNSS1
: 1;
7650 unsigned DACPSS0
: 1;
7651 unsigned DACPSS1
: 1;
7652 unsigned DACOE2
: 1;
7660 unsigned DAC1NSS0
: 1;
7661 unsigned DAC1NSS1
: 1;
7662 unsigned DAC1PSS0
: 1;
7663 unsigned DAC1PSS1
: 1;
7664 unsigned DAC1OE2
: 1;
7665 unsigned DACOE1
: 1;
7666 unsigned DAC1FM
: 1;
7667 unsigned DAC1EN
: 1;
7689 unsigned DAC1OE1
: 1;
7696 unsigned DAC1NSS
: 2;
7702 unsigned DACNSS
: 2;
7722 unsigned DAC1PSS
: 2;
7729 unsigned DACPSS
: 2;
7734 extern __at(0x058E) volatile __DAC1CON0bits_t DAC1CON0bits
;
7736 #define _DAC1CON0_NSS0 0x01
7737 #define _DAC1CON0_DACNSS0 0x01
7738 #define _DAC1CON0_DAC1NSS0 0x01
7739 #define _DAC1CON0_NSS1 0x02
7740 #define _DAC1CON0_DACNSS1 0x02
7741 #define _DAC1CON0_DAC1NSS1 0x02
7742 #define _DAC1CON0_PSS0 0x04
7743 #define _DAC1CON0_DACPSS0 0x04
7744 #define _DAC1CON0_DAC1PSS0 0x04
7745 #define _DAC1CON0_PSS1 0x08
7746 #define _DAC1CON0_DACPSS1 0x08
7747 #define _DAC1CON0_DAC1PSS1 0x08
7748 #define _DAC1CON0_OE2 0x10
7749 #define _DAC1CON0_DACOE2 0x10
7750 #define _DAC1CON0_DAC1OE2 0x10
7751 #define _DAC1CON0_OE1 0x20
7752 #define _DAC1CON0_OE 0x20
7753 #define _DAC1CON0_DACOE1 0x20
7754 #define _DAC1CON0_DACOE 0x20
7755 #define _DAC1CON0_DAC1OE1 0x20
7756 #define _DAC1CON0_FM 0x40
7757 #define _DAC1CON0_DACFM 0x40
7758 #define _DAC1CON0_DAC1FM 0x40
7759 #define _DAC1CON0_EN 0x80
7760 #define _DAC1CON0_DACEN 0x80
7761 #define _DAC1CON0_DAC1EN 0x80
7763 //==============================================================================
7766 //==============================================================================
7769 extern __at(0x058F) __sfr DAC1CON1
;
7787 unsigned DAC1REF0
: 1;
7788 unsigned DAC1REF1
: 1;
7789 unsigned DAC1REF2
: 1;
7790 unsigned DAC1REF3
: 1;
7791 unsigned DAC1REF4
: 1;
7792 unsigned DAC1REF5
: 1;
7793 unsigned DAC1REF6
: 1;
7794 unsigned DAC1REF7
: 1;
7811 unsigned DAC1R0
: 1;
7812 unsigned DAC1R1
: 1;
7813 unsigned DAC1R2
: 1;
7814 unsigned DAC1R3
: 1;
7815 unsigned DAC1R4
: 1;
7816 unsigned DAC1R5
: 1;
7817 unsigned DAC1R6
: 1;
7818 unsigned DAC1R7
: 1;
7822 extern __at(0x058F) volatile __DAC1CON1bits_t DAC1CON1bits
;
7825 #define _DAC1REF0 0x01
7827 #define _DAC1R0 0x01
7829 #define _DAC1REF1 0x02
7831 #define _DAC1R1 0x02
7833 #define _DAC1REF2 0x04
7835 #define _DAC1R2 0x04
7837 #define _DAC1REF3 0x08
7839 #define _DAC1R3 0x08
7841 #define _DAC1REF4 0x10
7843 #define _DAC1R4 0x10
7845 #define _DAC1REF5 0x20
7847 #define _DAC1R5 0x20
7849 #define _DAC1REF6 0x40
7851 #define _DAC1R6 0x40
7853 #define _DAC1REF7 0x80
7855 #define _DAC1R7 0x80
7857 //==============================================================================
7859 extern __at(0x058F) __sfr DAC1REF
;
7861 //==============================================================================
7864 extern __at(0x058F) __sfr DAC1REFL
;
7882 unsigned DAC1REF0
: 1;
7883 unsigned DAC1REF1
: 1;
7884 unsigned DAC1REF2
: 1;
7885 unsigned DAC1REF3
: 1;
7886 unsigned DAC1REF4
: 1;
7887 unsigned DAC1REF5
: 1;
7888 unsigned DAC1REF6
: 1;
7889 unsigned DAC1REF7
: 1;
7906 unsigned DAC1R0
: 1;
7907 unsigned DAC1R1
: 1;
7908 unsigned DAC1R2
: 1;
7909 unsigned DAC1R3
: 1;
7910 unsigned DAC1R4
: 1;
7911 unsigned DAC1R5
: 1;
7912 unsigned DAC1R6
: 1;
7913 unsigned DAC1R7
: 1;
7917 extern __at(0x058F) volatile __DAC1REFLbits_t DAC1REFLbits
;
7919 #define _DAC1REFL_REF0 0x01
7920 #define _DAC1REFL_DAC1REF0 0x01
7921 #define _DAC1REFL_R0 0x01
7922 #define _DAC1REFL_DAC1R0 0x01
7923 #define _DAC1REFL_REF1 0x02
7924 #define _DAC1REFL_DAC1REF1 0x02
7925 #define _DAC1REFL_R1 0x02
7926 #define _DAC1REFL_DAC1R1 0x02
7927 #define _DAC1REFL_REF2 0x04
7928 #define _DAC1REFL_DAC1REF2 0x04
7929 #define _DAC1REFL_R2 0x04
7930 #define _DAC1REFL_DAC1R2 0x04
7931 #define _DAC1REFL_REF3 0x08
7932 #define _DAC1REFL_DAC1REF3 0x08
7933 #define _DAC1REFL_R3 0x08
7934 #define _DAC1REFL_DAC1R3 0x08
7935 #define _DAC1REFL_REF4 0x10
7936 #define _DAC1REFL_DAC1REF4 0x10
7937 #define _DAC1REFL_R4 0x10
7938 #define _DAC1REFL_DAC1R4 0x10
7939 #define _DAC1REFL_REF5 0x20
7940 #define _DAC1REFL_DAC1REF5 0x20
7941 #define _DAC1REFL_R5 0x20
7942 #define _DAC1REFL_DAC1R5 0x20
7943 #define _DAC1REFL_REF6 0x40
7944 #define _DAC1REFL_DAC1REF6 0x40
7945 #define _DAC1REFL_R6 0x40
7946 #define _DAC1REFL_DAC1R6 0x40
7947 #define _DAC1REFL_REF7 0x80
7948 #define _DAC1REFL_DAC1REF7 0x80
7949 #define _DAC1REFL_R7 0x80
7950 #define _DAC1REFL_DAC1R7 0x80
7952 //==============================================================================
7955 //==============================================================================
7958 extern __at(0x0590) __sfr DAC1CON2
;
7976 unsigned DAC1REF8
: 1;
7977 unsigned DAC1REF9
: 1;
7978 unsigned DAC1REF10
: 1;
7979 unsigned DAC1REF11
: 1;
7980 unsigned DAC1REF12
: 1;
7981 unsigned DAC1REF13
: 1;
7982 unsigned DAC1REF14
: 1;
7983 unsigned DAC1REF15
: 1;
8000 unsigned DAC1R8
: 1;
8001 unsigned DAC1R9
: 1;
8002 unsigned DAC1R10
: 1;
8003 unsigned DAC1R11
: 1;
8004 unsigned DAC1R12
: 1;
8005 unsigned DAC1R13
: 1;
8006 unsigned DAC1R14
: 1;
8007 unsigned DAC1R15
: 1;
8011 extern __at(0x0590) volatile __DAC1CON2bits_t DAC1CON2bits
;
8014 #define _DAC1REF8 0x01
8016 #define _DAC1R8 0x01
8018 #define _DAC1REF9 0x02
8020 #define _DAC1R9 0x02
8022 #define _DAC1REF10 0x04
8024 #define _DAC1R10 0x04
8026 #define _DAC1REF11 0x08
8028 #define _DAC1R11 0x08
8030 #define _DAC1REF12 0x10
8032 #define _DAC1R12 0x10
8034 #define _DAC1REF13 0x20
8036 #define _DAC1R13 0x20
8038 #define _DAC1REF14 0x40
8040 #define _DAC1R14 0x40
8042 #define _DAC1REF15 0x80
8044 #define _DAC1R15 0x80
8046 //==============================================================================
8049 //==============================================================================
8052 extern __at(0x0590) __sfr DAC1REFH
;
8070 unsigned DAC1REF8
: 1;
8071 unsigned DAC1REF9
: 1;
8072 unsigned DAC1REF10
: 1;
8073 unsigned DAC1REF11
: 1;
8074 unsigned DAC1REF12
: 1;
8075 unsigned DAC1REF13
: 1;
8076 unsigned DAC1REF14
: 1;
8077 unsigned DAC1REF15
: 1;
8094 unsigned DAC1R8
: 1;
8095 unsigned DAC1R9
: 1;
8096 unsigned DAC1R10
: 1;
8097 unsigned DAC1R11
: 1;
8098 unsigned DAC1R12
: 1;
8099 unsigned DAC1R13
: 1;
8100 unsigned DAC1R14
: 1;
8101 unsigned DAC1R15
: 1;
8105 extern __at(0x0590) volatile __DAC1REFHbits_t DAC1REFHbits
;
8107 #define _DAC1REFH_REF8 0x01
8108 #define _DAC1REFH_DAC1REF8 0x01
8109 #define _DAC1REFH_R8 0x01
8110 #define _DAC1REFH_DAC1R8 0x01
8111 #define _DAC1REFH_REF9 0x02
8112 #define _DAC1REFH_DAC1REF9 0x02
8113 #define _DAC1REFH_R9 0x02
8114 #define _DAC1REFH_DAC1R9 0x02
8115 #define _DAC1REFH_REF10 0x04
8116 #define _DAC1REFH_DAC1REF10 0x04
8117 #define _DAC1REFH_R10 0x04
8118 #define _DAC1REFH_DAC1R10 0x04
8119 #define _DAC1REFH_REF11 0x08
8120 #define _DAC1REFH_DAC1REF11 0x08
8121 #define _DAC1REFH_R11 0x08
8122 #define _DAC1REFH_DAC1R11 0x08
8123 #define _DAC1REFH_REF12 0x10
8124 #define _DAC1REFH_DAC1REF12 0x10
8125 #define _DAC1REFH_R12 0x10
8126 #define _DAC1REFH_DAC1R12 0x10
8127 #define _DAC1REFH_REF13 0x20
8128 #define _DAC1REFH_DAC1REF13 0x20
8129 #define _DAC1REFH_R13 0x20
8130 #define _DAC1REFH_DAC1R13 0x20
8131 #define _DAC1REFH_REF14 0x40
8132 #define _DAC1REFH_DAC1REF14 0x40
8133 #define _DAC1REFH_R14 0x40
8134 #define _DAC1REFH_DAC1R14 0x40
8135 #define _DAC1REFH_REF15 0x80
8136 #define _DAC1REFH_DAC1REF15 0x80
8137 #define _DAC1REFH_R15 0x80
8138 #define _DAC1REFH_DAC1R15 0x80
8140 //==============================================================================
8143 //==============================================================================
8146 extern __at(0x0591) __sfr DAC2CON0
;
8164 unsigned DACNSS0
: 1;
8165 unsigned DACNSS1
: 1;
8166 unsigned DACPSS0
: 1;
8167 unsigned DACPSS1
: 1;
8168 unsigned DACOE2
: 1;
8176 unsigned DAC2NSS0
: 1;
8177 unsigned DAC2NSS1
: 1;
8178 unsigned DAC2PSS0
: 1;
8179 unsigned DAC2PSS1
: 1;
8180 unsigned DAC2OE2
: 1;
8181 unsigned DACOE1
: 1;
8182 unsigned DAC2FM
: 1;
8183 unsigned DAC2EN
: 1;
8205 unsigned DAC2OE1
: 1;
8212 unsigned DAC2NSS
: 2;
8218 unsigned DACNSS
: 2;
8238 unsigned DAC2PSS
: 2;
8245 unsigned DACPSS
: 2;
8250 extern __at(0x0591) volatile __DAC2CON0bits_t DAC2CON0bits
;
8252 #define _DAC2CON0_NSS0 0x01
8253 #define _DAC2CON0_DACNSS0 0x01
8254 #define _DAC2CON0_DAC2NSS0 0x01
8255 #define _DAC2CON0_NSS1 0x02
8256 #define _DAC2CON0_DACNSS1 0x02
8257 #define _DAC2CON0_DAC2NSS1 0x02
8258 #define _DAC2CON0_PSS0 0x04
8259 #define _DAC2CON0_DACPSS0 0x04
8260 #define _DAC2CON0_DAC2PSS0 0x04
8261 #define _DAC2CON0_PSS1 0x08
8262 #define _DAC2CON0_DACPSS1 0x08
8263 #define _DAC2CON0_DAC2PSS1 0x08
8264 #define _DAC2CON0_OE2 0x10
8265 #define _DAC2CON0_DACOE2 0x10
8266 #define _DAC2CON0_DAC2OE2 0x10
8267 #define _DAC2CON0_OE1 0x20
8268 #define _DAC2CON0_OE 0x20
8269 #define _DAC2CON0_DACOE1 0x20
8270 #define _DAC2CON0_DACOE 0x20
8271 #define _DAC2CON0_DAC2OE1 0x20
8272 #define _DAC2CON0_FM 0x40
8273 #define _DAC2CON0_DACFM 0x40
8274 #define _DAC2CON0_DAC2FM 0x40
8275 #define _DAC2CON0_EN 0x80
8276 #define _DAC2CON0_DACEN 0x80
8277 #define _DAC2CON0_DAC2EN 0x80
8279 //==============================================================================
8282 //==============================================================================
8285 extern __at(0x0592) __sfr DAC2CON1
;
8303 unsigned DAC2REF0
: 1;
8304 unsigned DAC2REF1
: 1;
8305 unsigned DAC2REF2
: 1;
8306 unsigned DAC2REF3
: 1;
8307 unsigned DAC2REF4
: 1;
8308 unsigned DAC2REF5
: 1;
8309 unsigned DAC2REF6
: 1;
8310 unsigned DAC2REF7
: 1;
8327 unsigned DAC2R0
: 1;
8328 unsigned DAC2R1
: 1;
8329 unsigned DAC2R2
: 1;
8330 unsigned DAC2R3
: 1;
8331 unsigned DAC2R4
: 1;
8332 unsigned DAC2R5
: 1;
8333 unsigned DAC2R6
: 1;
8334 unsigned DAC2R7
: 1;
8338 extern __at(0x0592) volatile __DAC2CON1bits_t DAC2CON1bits
;
8340 #define _DAC2CON1_REF0 0x01
8341 #define _DAC2CON1_DAC2REF0 0x01
8342 #define _DAC2CON1_R0 0x01
8343 #define _DAC2CON1_DAC2R0 0x01
8344 #define _DAC2CON1_REF1 0x02
8345 #define _DAC2CON1_DAC2REF1 0x02
8346 #define _DAC2CON1_R1 0x02
8347 #define _DAC2CON1_DAC2R1 0x02
8348 #define _DAC2CON1_REF2 0x04
8349 #define _DAC2CON1_DAC2REF2 0x04
8350 #define _DAC2CON1_R2 0x04
8351 #define _DAC2CON1_DAC2R2 0x04
8352 #define _DAC2CON1_REF3 0x08
8353 #define _DAC2CON1_DAC2REF3 0x08
8354 #define _DAC2CON1_R3 0x08
8355 #define _DAC2CON1_DAC2R3 0x08
8356 #define _DAC2CON1_REF4 0x10
8357 #define _DAC2CON1_DAC2REF4 0x10
8358 #define _DAC2CON1_R4 0x10
8359 #define _DAC2CON1_DAC2R4 0x10
8360 #define _DAC2CON1_REF5 0x20
8361 #define _DAC2CON1_DAC2REF5 0x20
8362 #define _DAC2CON1_R5 0x20
8363 #define _DAC2CON1_DAC2R5 0x20
8364 #define _DAC2CON1_REF6 0x40
8365 #define _DAC2CON1_DAC2REF6 0x40
8366 #define _DAC2CON1_R6 0x40
8367 #define _DAC2CON1_DAC2R6 0x40
8368 #define _DAC2CON1_REF7 0x80
8369 #define _DAC2CON1_DAC2REF7 0x80
8370 #define _DAC2CON1_R7 0x80
8371 #define _DAC2CON1_DAC2R7 0x80
8373 //==============================================================================
8375 extern __at(0x0592) __sfr DAC2REF
;
8377 //==============================================================================
8380 extern __at(0x0592) __sfr DAC2REFL
;
8398 unsigned DAC2REF0
: 1;
8399 unsigned DAC2REF1
: 1;
8400 unsigned DAC2REF2
: 1;
8401 unsigned DAC2REF3
: 1;
8402 unsigned DAC2REF4
: 1;
8403 unsigned DAC2REF5
: 1;
8404 unsigned DAC2REF6
: 1;
8405 unsigned DAC2REF7
: 1;
8422 unsigned DAC2R0
: 1;
8423 unsigned DAC2R1
: 1;
8424 unsigned DAC2R2
: 1;
8425 unsigned DAC2R3
: 1;
8426 unsigned DAC2R4
: 1;
8427 unsigned DAC2R5
: 1;
8428 unsigned DAC2R6
: 1;
8429 unsigned DAC2R7
: 1;
8433 extern __at(0x0592) volatile __DAC2REFLbits_t DAC2REFLbits
;
8435 #define _DAC2REFL_REF0 0x01
8436 #define _DAC2REFL_DAC2REF0 0x01
8437 #define _DAC2REFL_R0 0x01
8438 #define _DAC2REFL_DAC2R0 0x01
8439 #define _DAC2REFL_REF1 0x02
8440 #define _DAC2REFL_DAC2REF1 0x02
8441 #define _DAC2REFL_R1 0x02
8442 #define _DAC2REFL_DAC2R1 0x02
8443 #define _DAC2REFL_REF2 0x04
8444 #define _DAC2REFL_DAC2REF2 0x04
8445 #define _DAC2REFL_R2 0x04
8446 #define _DAC2REFL_DAC2R2 0x04
8447 #define _DAC2REFL_REF3 0x08
8448 #define _DAC2REFL_DAC2REF3 0x08
8449 #define _DAC2REFL_R3 0x08
8450 #define _DAC2REFL_DAC2R3 0x08
8451 #define _DAC2REFL_REF4 0x10
8452 #define _DAC2REFL_DAC2REF4 0x10
8453 #define _DAC2REFL_R4 0x10
8454 #define _DAC2REFL_DAC2R4 0x10
8455 #define _DAC2REFL_REF5 0x20
8456 #define _DAC2REFL_DAC2REF5 0x20
8457 #define _DAC2REFL_R5 0x20
8458 #define _DAC2REFL_DAC2R5 0x20
8459 #define _DAC2REFL_REF6 0x40
8460 #define _DAC2REFL_DAC2REF6 0x40
8461 #define _DAC2REFL_R6 0x40
8462 #define _DAC2REFL_DAC2R6 0x40
8463 #define _DAC2REFL_REF7 0x80
8464 #define _DAC2REFL_DAC2REF7 0x80
8465 #define _DAC2REFL_R7 0x80
8466 #define _DAC2REFL_DAC2R7 0x80
8468 //==============================================================================
8471 //==============================================================================
8474 extern __at(0x0593) __sfr DAC2CON2
;
8492 unsigned DAC2REF8
: 1;
8493 unsigned DAC2REF9
: 1;
8494 unsigned DAC2REF10
: 1;
8495 unsigned DAC2REF11
: 1;
8496 unsigned DAC2REF12
: 1;
8497 unsigned DAC2REF13
: 1;
8498 unsigned DAC2REF14
: 1;
8499 unsigned DAC2REF15
: 1;
8516 unsigned DAC2R8
: 1;
8517 unsigned DAC2R9
: 1;
8518 unsigned DAC2R10
: 1;
8519 unsigned DAC2R11
: 1;
8520 unsigned DAC2R12
: 1;
8521 unsigned DAC2R13
: 1;
8522 unsigned DAC2R14
: 1;
8523 unsigned DAC2R15
: 1;
8527 extern __at(0x0593) volatile __DAC2CON2bits_t DAC2CON2bits
;
8529 #define _DAC2CON2_REF8 0x01
8530 #define _DAC2CON2_DAC2REF8 0x01
8531 #define _DAC2CON2_R8 0x01
8532 #define _DAC2CON2_DAC2R8 0x01
8533 #define _DAC2CON2_REF9 0x02
8534 #define _DAC2CON2_DAC2REF9 0x02
8535 #define _DAC2CON2_R9 0x02
8536 #define _DAC2CON2_DAC2R9 0x02
8537 #define _DAC2CON2_REF10 0x04
8538 #define _DAC2CON2_DAC2REF10 0x04
8539 #define _DAC2CON2_R10 0x04
8540 #define _DAC2CON2_DAC2R10 0x04
8541 #define _DAC2CON2_REF11 0x08
8542 #define _DAC2CON2_DAC2REF11 0x08
8543 #define _DAC2CON2_R11 0x08
8544 #define _DAC2CON2_DAC2R11 0x08
8545 #define _DAC2CON2_REF12 0x10
8546 #define _DAC2CON2_DAC2REF12 0x10
8547 #define _DAC2CON2_R12 0x10
8548 #define _DAC2CON2_DAC2R12 0x10
8549 #define _DAC2CON2_REF13 0x20
8550 #define _DAC2CON2_DAC2REF13 0x20
8551 #define _DAC2CON2_R13 0x20
8552 #define _DAC2CON2_DAC2R13 0x20
8553 #define _DAC2CON2_REF14 0x40
8554 #define _DAC2CON2_DAC2REF14 0x40
8555 #define _DAC2CON2_R14 0x40
8556 #define _DAC2CON2_DAC2R14 0x40
8557 #define _DAC2CON2_REF15 0x80
8558 #define _DAC2CON2_DAC2REF15 0x80
8559 #define _DAC2CON2_R15 0x80
8560 #define _DAC2CON2_DAC2R15 0x80
8562 //==============================================================================
8565 //==============================================================================
8568 extern __at(0x0593) __sfr DAC2REFH
;
8586 unsigned DAC2REF8
: 1;
8587 unsigned DAC2REF9
: 1;
8588 unsigned DAC2REF10
: 1;
8589 unsigned DAC2REF11
: 1;
8590 unsigned DAC2REF12
: 1;
8591 unsigned DAC2REF13
: 1;
8592 unsigned DAC2REF14
: 1;
8593 unsigned DAC2REF15
: 1;
8610 unsigned DAC2R8
: 1;
8611 unsigned DAC2R9
: 1;
8612 unsigned DAC2R10
: 1;
8613 unsigned DAC2R11
: 1;
8614 unsigned DAC2R12
: 1;
8615 unsigned DAC2R13
: 1;
8616 unsigned DAC2R14
: 1;
8617 unsigned DAC2R15
: 1;
8621 extern __at(0x0593) volatile __DAC2REFHbits_t DAC2REFHbits
;
8623 #define _DAC2REFH_REF8 0x01
8624 #define _DAC2REFH_DAC2REF8 0x01
8625 #define _DAC2REFH_R8 0x01
8626 #define _DAC2REFH_DAC2R8 0x01
8627 #define _DAC2REFH_REF9 0x02
8628 #define _DAC2REFH_DAC2REF9 0x02
8629 #define _DAC2REFH_R9 0x02
8630 #define _DAC2REFH_DAC2R9 0x02
8631 #define _DAC2REFH_REF10 0x04
8632 #define _DAC2REFH_DAC2REF10 0x04
8633 #define _DAC2REFH_R10 0x04
8634 #define _DAC2REFH_DAC2R10 0x04
8635 #define _DAC2REFH_REF11 0x08
8636 #define _DAC2REFH_DAC2REF11 0x08
8637 #define _DAC2REFH_R11 0x08
8638 #define _DAC2REFH_DAC2R11 0x08
8639 #define _DAC2REFH_REF12 0x10
8640 #define _DAC2REFH_DAC2REF12 0x10
8641 #define _DAC2REFH_R12 0x10
8642 #define _DAC2REFH_DAC2R12 0x10
8643 #define _DAC2REFH_REF13 0x20
8644 #define _DAC2REFH_DAC2REF13 0x20
8645 #define _DAC2REFH_R13 0x20
8646 #define _DAC2REFH_DAC2R13 0x20
8647 #define _DAC2REFH_REF14 0x40
8648 #define _DAC2REFH_DAC2REF14 0x40
8649 #define _DAC2REFH_R14 0x40
8650 #define _DAC2REFH_DAC2R14 0x40
8651 #define _DAC2REFH_REF15 0x80
8652 #define _DAC2REFH_DAC2REF15 0x80
8653 #define _DAC2REFH_R15 0x80
8654 #define _DAC2REFH_DAC2R15 0x80
8656 //==============================================================================
8659 //==============================================================================
8662 extern __at(0x0594) __sfr DAC3CON0
;
8680 unsigned DACNSS0
: 1;
8681 unsigned DACNSS1
: 1;
8682 unsigned DACPSS0
: 1;
8683 unsigned DACPSS1
: 1;
8684 unsigned DACOE2
: 1;
8685 unsigned DACOE1
: 1;
8692 unsigned DAC3NSS0
: 1;
8693 unsigned DAC3NSS1
: 1;
8694 unsigned DAC3PSS0
: 1;
8695 unsigned DAC3PSS1
: 1;
8696 unsigned DAC3OE2
: 1;
8697 unsigned DAC3OE1
: 1;
8699 unsigned DAC3EN
: 1;
8704 unsigned DAC3NSS
: 2;
8710 unsigned DACNSS
: 2;
8730 unsigned DACPSS
: 2;
8737 unsigned DAC3PSS
: 2;
8742 extern __at(0x0594) volatile __DAC3CON0bits_t DAC3CON0bits
;
8744 #define _DAC3CON0_NSS0 0x01
8745 #define _DAC3CON0_DACNSS0 0x01
8746 #define _DAC3CON0_DAC3NSS0 0x01
8747 #define _DAC3CON0_NSS1 0x02
8748 #define _DAC3CON0_DACNSS1 0x02
8749 #define _DAC3CON0_DAC3NSS1 0x02
8750 #define _DAC3CON0_PSS0 0x04
8751 #define _DAC3CON0_DACPSS0 0x04
8752 #define _DAC3CON0_DAC3PSS0 0x04
8753 #define _DAC3CON0_PSS1 0x08
8754 #define _DAC3CON0_DACPSS1 0x08
8755 #define _DAC3CON0_DAC3PSS1 0x08
8756 #define _DAC3CON0_OE2 0x10
8757 #define _DAC3CON0_DACOE2 0x10
8758 #define _DAC3CON0_DAC3OE2 0x10
8759 #define _DAC3CON0_OE1 0x20
8760 #define _DAC3CON0_DACOE1 0x20
8761 #define _DAC3CON0_DAC3OE1 0x20
8762 #define _DAC3CON0_EN 0x80
8763 #define _DAC3CON0_DACEN 0x80
8764 #define _DAC3CON0_DAC3EN 0x80
8766 //==============================================================================
8769 //==============================================================================
8772 extern __at(0x0595) __sfr DAC3CON1
;
8802 unsigned DAC3R0
: 1;
8803 unsigned DAC3R1
: 1;
8804 unsigned DAC3R2
: 1;
8805 unsigned DAC3R3
: 1;
8806 unsigned DAC3R4
: 1;
8826 unsigned DAC3REF0
: 1;
8827 unsigned DAC3REF1
: 1;
8828 unsigned DAC3REF2
: 1;
8829 unsigned DAC3REF3
: 1;
8830 unsigned DAC3REF4
: 1;
8844 unsigned DAC3REF
: 5;
8867 extern __at(0x0595) volatile __DAC3CON1bits_t DAC3CON1bits
;
8869 #define _DAC3CON1_DACR0 0x01
8870 #define _DAC3CON1_R0 0x01
8871 #define _DAC3CON1_DAC3R0 0x01
8872 #define _DAC3CON1_REF0 0x01
8873 #define _DAC3CON1_DAC3REF0 0x01
8874 #define _DAC3CON1_DACR1 0x02
8875 #define _DAC3CON1_R1 0x02
8876 #define _DAC3CON1_DAC3R1 0x02
8877 #define _DAC3CON1_REF1 0x02
8878 #define _DAC3CON1_DAC3REF1 0x02
8879 #define _DAC3CON1_DACR2 0x04
8880 #define _DAC3CON1_R2 0x04
8881 #define _DAC3CON1_DAC3R2 0x04
8882 #define _DAC3CON1_REF2 0x04
8883 #define _DAC3CON1_DAC3REF2 0x04
8884 #define _DAC3CON1_DACR3 0x08
8885 #define _DAC3CON1_R3 0x08
8886 #define _DAC3CON1_DAC3R3 0x08
8887 #define _DAC3CON1_REF3 0x08
8888 #define _DAC3CON1_DAC3REF3 0x08
8889 #define _DAC3CON1_DACR4 0x10
8890 #define _DAC3CON1_R4 0x10
8891 #define _DAC3CON1_DAC3R4 0x10
8892 #define _DAC3CON1_REF4 0x10
8893 #define _DAC3CON1_DAC3REF4 0x10
8895 //==============================================================================
8898 //==============================================================================
8901 extern __at(0x0595) __sfr DAC3REF
;
8931 unsigned DAC3R0
: 1;
8932 unsigned DAC3R1
: 1;
8933 unsigned DAC3R2
: 1;
8934 unsigned DAC3R3
: 1;
8935 unsigned DAC3R4
: 1;
8955 unsigned DAC3REF0
: 1;
8956 unsigned DAC3REF1
: 1;
8957 unsigned DAC3REF2
: 1;
8958 unsigned DAC3REF3
: 1;
8959 unsigned DAC3REF4
: 1;
8973 unsigned DAC3REF
: 5;
8996 extern __at(0x0595) volatile __DAC3REFbits_t DAC3REFbits
;
8998 #define _DAC3REF_DACR0 0x01
8999 #define _DAC3REF_R0 0x01
9000 #define _DAC3REF_DAC3R0 0x01
9001 #define _DAC3REF_REF0 0x01
9002 #define _DAC3REF_DAC3REF0 0x01
9003 #define _DAC3REF_DACR1 0x02
9004 #define _DAC3REF_R1 0x02
9005 #define _DAC3REF_DAC3R1 0x02
9006 #define _DAC3REF_REF1 0x02
9007 #define _DAC3REF_DAC3REF1 0x02
9008 #define _DAC3REF_DACR2 0x04
9009 #define _DAC3REF_R2 0x04
9010 #define _DAC3REF_DAC3R2 0x04
9011 #define _DAC3REF_REF2 0x04
9012 #define _DAC3REF_DAC3REF2 0x04
9013 #define _DAC3REF_DACR3 0x08
9014 #define _DAC3REF_R3 0x08
9015 #define _DAC3REF_DAC3R3 0x08
9016 #define _DAC3REF_REF3 0x08
9017 #define _DAC3REF_DAC3REF3 0x08
9018 #define _DAC3REF_DACR4 0x10
9019 #define _DAC3REF_R4 0x10
9020 #define _DAC3REF_DAC3R4 0x10
9021 #define _DAC3REF_REF4 0x10
9022 #define _DAC3REF_DAC3REF4 0x10
9024 //==============================================================================
9027 //==============================================================================
9030 extern __at(0x0596) __sfr DAC4CON0
;
9048 unsigned DACNSS0
: 1;
9049 unsigned DACNSS1
: 1;
9050 unsigned DACPSS0
: 1;
9051 unsigned DACPSS1
: 1;
9052 unsigned DACOE2
: 1;
9053 unsigned DACOE1
: 1;
9060 unsigned DAC4NSS0
: 1;
9061 unsigned DAC4NSS1
: 1;
9062 unsigned DAC4PSS0
: 1;
9063 unsigned DAC4PSS1
: 1;
9064 unsigned DAC4OE2
: 1;
9065 unsigned DAC4OE1
: 1;
9067 unsigned DAC4EN
: 1;
9072 unsigned DACNSS
: 2;
9084 unsigned DAC4NSS
: 2;
9091 unsigned DAC4PSS
: 2;
9098 unsigned DACPSS
: 2;
9110 extern __at(0x0596) volatile __DAC4CON0bits_t DAC4CON0bits
;
9112 #define _DAC4CON0_NSS0 0x01
9113 #define _DAC4CON0_DACNSS0 0x01
9114 #define _DAC4CON0_DAC4NSS0 0x01
9115 #define _DAC4CON0_NSS1 0x02
9116 #define _DAC4CON0_DACNSS1 0x02
9117 #define _DAC4CON0_DAC4NSS1 0x02
9118 #define _DAC4CON0_PSS0 0x04
9119 #define _DAC4CON0_DACPSS0 0x04
9120 #define _DAC4CON0_DAC4PSS0 0x04
9121 #define _DAC4CON0_PSS1 0x08
9122 #define _DAC4CON0_DACPSS1 0x08
9123 #define _DAC4CON0_DAC4PSS1 0x08
9124 #define _DAC4CON0_OE2 0x10
9125 #define _DAC4CON0_DACOE2 0x10
9126 #define _DAC4CON0_DAC4OE2 0x10
9127 #define _DAC4CON0_OE1 0x20
9128 #define _DAC4CON0_DACOE1 0x20
9129 #define _DAC4CON0_DAC4OE1 0x20
9130 #define _DAC4CON0_EN 0x80
9131 #define _DAC4CON0_DACEN 0x80
9132 #define _DAC4CON0_DAC4EN 0x80
9134 //==============================================================================
9137 //==============================================================================
9140 extern __at(0x0597) __sfr DAC4CON1
;
9170 unsigned DAC4R0
: 1;
9171 unsigned DAC4R1
: 1;
9172 unsigned DAC4R2
: 1;
9173 unsigned DAC4R3
: 1;
9174 unsigned DAC4R4
: 1;
9194 unsigned DAC4REF0
: 1;
9195 unsigned DAC4REF1
: 1;
9196 unsigned DAC4REF2
: 1;
9197 unsigned DAC4REF3
: 1;
9198 unsigned DAC4REF4
: 1;
9206 unsigned DAC4REF
: 5;
9235 extern __at(0x0597) volatile __DAC4CON1bits_t DAC4CON1bits
;
9237 #define _DAC4CON1_DACR0 0x01
9238 #define _DAC4CON1_R0 0x01
9239 #define _DAC4CON1_DAC4R0 0x01
9240 #define _DAC4CON1_REF0 0x01
9241 #define _DAC4CON1_DAC4REF0 0x01
9242 #define _DAC4CON1_DACR1 0x02
9243 #define _DAC4CON1_R1 0x02
9244 #define _DAC4CON1_DAC4R1 0x02
9245 #define _DAC4CON1_REF1 0x02
9246 #define _DAC4CON1_DAC4REF1 0x02
9247 #define _DAC4CON1_DACR2 0x04
9248 #define _DAC4CON1_R2 0x04
9249 #define _DAC4CON1_DAC4R2 0x04
9250 #define _DAC4CON1_REF2 0x04
9251 #define _DAC4CON1_DAC4REF2 0x04
9252 #define _DAC4CON1_DACR3 0x08
9253 #define _DAC4CON1_R3 0x08
9254 #define _DAC4CON1_DAC4R3 0x08
9255 #define _DAC4CON1_REF3 0x08
9256 #define _DAC4CON1_DAC4REF3 0x08
9257 #define _DAC4CON1_DACR4 0x10
9258 #define _DAC4CON1_R4 0x10
9259 #define _DAC4CON1_DAC4R4 0x10
9260 #define _DAC4CON1_REF4 0x10
9261 #define _DAC4CON1_DAC4REF4 0x10
9263 //==============================================================================
9266 //==============================================================================
9269 extern __at(0x0597) __sfr DAC4REF
;
9299 unsigned DAC4R0
: 1;
9300 unsigned DAC4R1
: 1;
9301 unsigned DAC4R2
: 1;
9302 unsigned DAC4R3
: 1;
9303 unsigned DAC4R4
: 1;
9323 unsigned DAC4REF0
: 1;
9324 unsigned DAC4REF1
: 1;
9325 unsigned DAC4REF2
: 1;
9326 unsigned DAC4REF3
: 1;
9327 unsigned DAC4REF4
: 1;
9347 unsigned DAC4REF
: 5;
9364 extern __at(0x0597) volatile __DAC4REFbits_t DAC4REFbits
;
9366 #define _DAC4REF_DACR0 0x01
9367 #define _DAC4REF_R0 0x01
9368 #define _DAC4REF_DAC4R0 0x01
9369 #define _DAC4REF_REF0 0x01
9370 #define _DAC4REF_DAC4REF0 0x01
9371 #define _DAC4REF_DACR1 0x02
9372 #define _DAC4REF_R1 0x02
9373 #define _DAC4REF_DAC4R1 0x02
9374 #define _DAC4REF_REF1 0x02
9375 #define _DAC4REF_DAC4REF1 0x02
9376 #define _DAC4REF_DACR2 0x04
9377 #define _DAC4REF_R2 0x04
9378 #define _DAC4REF_DAC4R2 0x04
9379 #define _DAC4REF_REF2 0x04
9380 #define _DAC4REF_DAC4REF2 0x04
9381 #define _DAC4REF_DACR3 0x08
9382 #define _DAC4REF_R3 0x08
9383 #define _DAC4REF_DAC4R3 0x08
9384 #define _DAC4REF_REF3 0x08
9385 #define _DAC4REF_DAC4REF3 0x08
9386 #define _DAC4REF_DACR4 0x10
9387 #define _DAC4REF_R4 0x10
9388 #define _DAC4REF_DAC4R4 0x10
9389 #define _DAC4REF_REF4 0x10
9390 #define _DAC4REF_DAC4REF4 0x10
9392 //==============================================================================
9395 //==============================================================================
9398 extern __at(0x0598) __sfr DAC5CON0
;
9416 unsigned DACNSS0
: 1;
9417 unsigned DACNSS1
: 1;
9418 unsigned DACPSS0
: 1;
9419 unsigned DACPSS1
: 1;
9420 unsigned DACOE2
: 1;
9428 unsigned DAC5NSS0
: 1;
9429 unsigned DAC5NSS1
: 1;
9430 unsigned DAC5PSS0
: 1;
9431 unsigned DAC5PSS1
: 1;
9432 unsigned DAC5OE2
: 1;
9433 unsigned DACOE1
: 1;
9434 unsigned DAC5FM
: 1;
9435 unsigned DAC5EN
: 1;
9457 unsigned DAC5OE1
: 1;
9470 unsigned DACNSS
: 2;
9476 unsigned DAC5NSS
: 2;
9483 unsigned DACPSS
: 2;
9490 unsigned DAC5PSS
: 2;
9502 extern __at(0x0598) volatile __DAC5CON0bits_t DAC5CON0bits
;
9504 #define _DAC5CON0_NSS0 0x01
9505 #define _DAC5CON0_DACNSS0 0x01
9506 #define _DAC5CON0_DAC5NSS0 0x01
9507 #define _DAC5CON0_NSS1 0x02
9508 #define _DAC5CON0_DACNSS1 0x02
9509 #define _DAC5CON0_DAC5NSS1 0x02
9510 #define _DAC5CON0_PSS0 0x04
9511 #define _DAC5CON0_DACPSS0 0x04
9512 #define _DAC5CON0_DAC5PSS0 0x04
9513 #define _DAC5CON0_PSS1 0x08
9514 #define _DAC5CON0_DACPSS1 0x08
9515 #define _DAC5CON0_DAC5PSS1 0x08
9516 #define _DAC5CON0_OE2 0x10
9517 #define _DAC5CON0_DACOE2 0x10
9518 #define _DAC5CON0_DAC5OE2 0x10
9519 #define _DAC5CON0_OE1 0x20
9520 #define _DAC5CON0_OE 0x20
9521 #define _DAC5CON0_DACOE1 0x20
9522 #define _DAC5CON0_DACOE 0x20
9523 #define _DAC5CON0_DAC5OE1 0x20
9524 #define _DAC5CON0_FM 0x40
9525 #define _DAC5CON0_DACFM 0x40
9526 #define _DAC5CON0_DAC5FM 0x40
9527 #define _DAC5CON0_EN 0x80
9528 #define _DAC5CON0_DACEN 0x80
9529 #define _DAC5CON0_DAC5EN 0x80
9531 //==============================================================================
9534 //==============================================================================
9537 extern __at(0x0599) __sfr DAC5CON1
;
9555 unsigned DAC5REF0
: 1;
9556 unsigned DAC5REF1
: 1;
9557 unsigned DAC5REF2
: 1;
9558 unsigned DAC5REF3
: 1;
9559 unsigned DAC5REF4
: 1;
9560 unsigned DAC5REF5
: 1;
9561 unsigned DAC5REF6
: 1;
9562 unsigned DAC5REF7
: 1;
9579 unsigned DAC5R0
: 1;
9580 unsigned DAC5R1
: 1;
9581 unsigned DAC5R2
: 1;
9582 unsigned DAC5R3
: 1;
9583 unsigned DAC5R4
: 1;
9584 unsigned DAC5R5
: 1;
9585 unsigned DAC5R6
: 1;
9586 unsigned DAC5R7
: 1;
9590 extern __at(0x0599) volatile __DAC5CON1bits_t DAC5CON1bits
;
9592 #define _DAC5CON1_REF0 0x01
9593 #define _DAC5CON1_DAC5REF0 0x01
9594 #define _DAC5CON1_R0 0x01
9595 #define _DAC5CON1_DAC5R0 0x01
9596 #define _DAC5CON1_REF1 0x02
9597 #define _DAC5CON1_DAC5REF1 0x02
9598 #define _DAC5CON1_R1 0x02
9599 #define _DAC5CON1_DAC5R1 0x02
9600 #define _DAC5CON1_REF2 0x04
9601 #define _DAC5CON1_DAC5REF2 0x04
9602 #define _DAC5CON1_R2 0x04
9603 #define _DAC5CON1_DAC5R2 0x04
9604 #define _DAC5CON1_REF3 0x08
9605 #define _DAC5CON1_DAC5REF3 0x08
9606 #define _DAC5CON1_R3 0x08
9607 #define _DAC5CON1_DAC5R3 0x08
9608 #define _DAC5CON1_REF4 0x10
9609 #define _DAC5CON1_DAC5REF4 0x10
9610 #define _DAC5CON1_R4 0x10
9611 #define _DAC5CON1_DAC5R4 0x10
9612 #define _DAC5CON1_REF5 0x20
9613 #define _DAC5CON1_DAC5REF5 0x20
9614 #define _DAC5CON1_R5 0x20
9615 #define _DAC5CON1_DAC5R5 0x20
9616 #define _DAC5CON1_REF6 0x40
9617 #define _DAC5CON1_DAC5REF6 0x40
9618 #define _DAC5CON1_R6 0x40
9619 #define _DAC5CON1_DAC5R6 0x40
9620 #define _DAC5CON1_REF7 0x80
9621 #define _DAC5CON1_DAC5REF7 0x80
9622 #define _DAC5CON1_R7 0x80
9623 #define _DAC5CON1_DAC5R7 0x80
9625 //==============================================================================
9627 extern __at(0x0599) __sfr DAC5REF
;
9629 //==============================================================================
9632 extern __at(0x0599) __sfr DAC5REFL
;
9650 unsigned DAC5REF0
: 1;
9651 unsigned DAC5REF1
: 1;
9652 unsigned DAC5REF2
: 1;
9653 unsigned DAC5REF3
: 1;
9654 unsigned DAC5REF4
: 1;
9655 unsigned DAC5REF5
: 1;
9656 unsigned DAC5REF6
: 1;
9657 unsigned DAC5REF7
: 1;
9674 unsigned DAC5R0
: 1;
9675 unsigned DAC5R1
: 1;
9676 unsigned DAC5R2
: 1;
9677 unsigned DAC5R3
: 1;
9678 unsigned DAC5R4
: 1;
9679 unsigned DAC5R5
: 1;
9680 unsigned DAC5R6
: 1;
9681 unsigned DAC5R7
: 1;
9685 extern __at(0x0599) volatile __DAC5REFLbits_t DAC5REFLbits
;
9687 #define _DAC5REFL_REF0 0x01
9688 #define _DAC5REFL_DAC5REF0 0x01
9689 #define _DAC5REFL_R0 0x01
9690 #define _DAC5REFL_DAC5R0 0x01
9691 #define _DAC5REFL_REF1 0x02
9692 #define _DAC5REFL_DAC5REF1 0x02
9693 #define _DAC5REFL_R1 0x02
9694 #define _DAC5REFL_DAC5R1 0x02
9695 #define _DAC5REFL_REF2 0x04
9696 #define _DAC5REFL_DAC5REF2 0x04
9697 #define _DAC5REFL_R2 0x04
9698 #define _DAC5REFL_DAC5R2 0x04
9699 #define _DAC5REFL_REF3 0x08
9700 #define _DAC5REFL_DAC5REF3 0x08
9701 #define _DAC5REFL_R3 0x08
9702 #define _DAC5REFL_DAC5R3 0x08
9703 #define _DAC5REFL_REF4 0x10
9704 #define _DAC5REFL_DAC5REF4 0x10
9705 #define _DAC5REFL_R4 0x10
9706 #define _DAC5REFL_DAC5R4 0x10
9707 #define _DAC5REFL_REF5 0x20
9708 #define _DAC5REFL_DAC5REF5 0x20
9709 #define _DAC5REFL_R5 0x20
9710 #define _DAC5REFL_DAC5R5 0x20
9711 #define _DAC5REFL_REF6 0x40
9712 #define _DAC5REFL_DAC5REF6 0x40
9713 #define _DAC5REFL_R6 0x40
9714 #define _DAC5REFL_DAC5R6 0x40
9715 #define _DAC5REFL_REF7 0x80
9716 #define _DAC5REFL_DAC5REF7 0x80
9717 #define _DAC5REFL_R7 0x80
9718 #define _DAC5REFL_DAC5R7 0x80
9720 //==============================================================================
9723 //==============================================================================
9726 extern __at(0x059A) __sfr DAC5CON2
;
9744 unsigned DAC5REF8
: 1;
9745 unsigned DAC5REF9
: 1;
9746 unsigned DAC5REF10
: 1;
9747 unsigned DAC5REF11
: 1;
9748 unsigned DAC5REF12
: 1;
9749 unsigned DAC5REF13
: 1;
9750 unsigned DAC5REF14
: 1;
9751 unsigned DAC5REF15
: 1;
9768 unsigned DAC5R8
: 1;
9769 unsigned DAC5R9
: 1;
9770 unsigned DAC5R10
: 1;
9771 unsigned DAC5R11
: 1;
9772 unsigned DAC5R12
: 1;
9773 unsigned DAC5R13
: 1;
9774 unsigned DAC5R14
: 1;
9775 unsigned DAC5R15
: 1;
9779 extern __at(0x059A) volatile __DAC5CON2bits_t DAC5CON2bits
;
9781 #define _DAC5CON2_REF8 0x01
9782 #define _DAC5CON2_DAC5REF8 0x01
9783 #define _DAC5CON2_R8 0x01
9784 #define _DAC5CON2_DAC5R8 0x01
9785 #define _DAC5CON2_REF9 0x02
9786 #define _DAC5CON2_DAC5REF9 0x02
9787 #define _DAC5CON2_R9 0x02
9788 #define _DAC5CON2_DAC5R9 0x02
9789 #define _DAC5CON2_REF10 0x04
9790 #define _DAC5CON2_DAC5REF10 0x04
9791 #define _DAC5CON2_R10 0x04
9792 #define _DAC5CON2_DAC5R10 0x04
9793 #define _DAC5CON2_REF11 0x08
9794 #define _DAC5CON2_DAC5REF11 0x08
9795 #define _DAC5CON2_R11 0x08
9796 #define _DAC5CON2_DAC5R11 0x08
9797 #define _DAC5CON2_REF12 0x10
9798 #define _DAC5CON2_DAC5REF12 0x10
9799 #define _DAC5CON2_R12 0x10
9800 #define _DAC5CON2_DAC5R12 0x10
9801 #define _DAC5CON2_REF13 0x20
9802 #define _DAC5CON2_DAC5REF13 0x20
9803 #define _DAC5CON2_R13 0x20
9804 #define _DAC5CON2_DAC5R13 0x20
9805 #define _DAC5CON2_REF14 0x40
9806 #define _DAC5CON2_DAC5REF14 0x40
9807 #define _DAC5CON2_R14 0x40
9808 #define _DAC5CON2_DAC5R14 0x40
9809 #define _DAC5CON2_REF15 0x80
9810 #define _DAC5CON2_DAC5REF15 0x80
9811 #define _DAC5CON2_R15 0x80
9812 #define _DAC5CON2_DAC5R15 0x80
9814 //==============================================================================
9817 //==============================================================================
9820 extern __at(0x059A) __sfr DAC5REFH
;
9838 unsigned DAC5REF8
: 1;
9839 unsigned DAC5REF9
: 1;
9840 unsigned DAC5REF10
: 1;
9841 unsigned DAC5REF11
: 1;
9842 unsigned DAC5REF12
: 1;
9843 unsigned DAC5REF13
: 1;
9844 unsigned DAC5REF14
: 1;
9845 unsigned DAC5REF15
: 1;
9862 unsigned DAC5R8
: 1;
9863 unsigned DAC5R9
: 1;
9864 unsigned DAC5R10
: 1;
9865 unsigned DAC5R11
: 1;
9866 unsigned DAC5R12
: 1;
9867 unsigned DAC5R13
: 1;
9868 unsigned DAC5R14
: 1;
9869 unsigned DAC5R15
: 1;
9873 extern __at(0x059A) volatile __DAC5REFHbits_t DAC5REFHbits
;
9875 #define _DAC5REFH_REF8 0x01
9876 #define _DAC5REFH_DAC5REF8 0x01
9877 #define _DAC5REFH_R8 0x01
9878 #define _DAC5REFH_DAC5R8 0x01
9879 #define _DAC5REFH_REF9 0x02
9880 #define _DAC5REFH_DAC5REF9 0x02
9881 #define _DAC5REFH_R9 0x02
9882 #define _DAC5REFH_DAC5R9 0x02
9883 #define _DAC5REFH_REF10 0x04
9884 #define _DAC5REFH_DAC5REF10 0x04
9885 #define _DAC5REFH_R10 0x04
9886 #define _DAC5REFH_DAC5R10 0x04
9887 #define _DAC5REFH_REF11 0x08
9888 #define _DAC5REFH_DAC5REF11 0x08
9889 #define _DAC5REFH_R11 0x08
9890 #define _DAC5REFH_DAC5R11 0x08
9891 #define _DAC5REFH_REF12 0x10
9892 #define _DAC5REFH_DAC5REF12 0x10
9893 #define _DAC5REFH_R12 0x10
9894 #define _DAC5REFH_DAC5R12 0x10
9895 #define _DAC5REFH_REF13 0x20
9896 #define _DAC5REFH_DAC5REF13 0x20
9897 #define _DAC5REFH_R13 0x20
9898 #define _DAC5REFH_DAC5R13 0x20
9899 #define _DAC5REFH_REF14 0x40
9900 #define _DAC5REFH_DAC5REF14 0x40
9901 #define _DAC5REFH_R14 0x40
9902 #define _DAC5REFH_DAC5R14 0x40
9903 #define _DAC5REFH_REF15 0x80
9904 #define _DAC5REFH_DAC5REF15 0x80
9905 #define _DAC5REFH_R15 0x80
9906 #define _DAC5REFH_DAC5R15 0x80
9908 //==============================================================================
9911 //==============================================================================
9914 extern __at(0x059E) __sfr DAC7CON0
;
9932 unsigned DACNSS0
: 1;
9933 unsigned DACNSS1
: 1;
9934 unsigned DACPSS0
: 1;
9935 unsigned DACPSS1
: 1;
9936 unsigned DACOE2
: 1;
9937 unsigned DACOE1
: 1;
9944 unsigned DAC7NSS0
: 1;
9945 unsigned DAC7NSS1
: 1;
9946 unsigned DAC7PSS0
: 1;
9947 unsigned DAC7PSS1
: 1;
9948 unsigned DAC7OE2
: 1;
9949 unsigned DAC7OE1
: 1;
9951 unsigned DAC7EN
: 1;
9956 unsigned DAC7NSS
: 2;
9962 unsigned DACNSS
: 2;
9982 unsigned DACPSS
: 2;
9989 unsigned DAC7PSS
: 2;
9994 extern __at(0x059E) volatile __DAC7CON0bits_t DAC7CON0bits
;
9996 #define _DAC7CON0_NSS0 0x01
9997 #define _DAC7CON0_DACNSS0 0x01
9998 #define _DAC7CON0_DAC7NSS0 0x01
9999 #define _DAC7CON0_NSS1 0x02
10000 #define _DAC7CON0_DACNSS1 0x02
10001 #define _DAC7CON0_DAC7NSS1 0x02
10002 #define _DAC7CON0_PSS0 0x04
10003 #define _DAC7CON0_DACPSS0 0x04
10004 #define _DAC7CON0_DAC7PSS0 0x04
10005 #define _DAC7CON0_PSS1 0x08
10006 #define _DAC7CON0_DACPSS1 0x08
10007 #define _DAC7CON0_DAC7PSS1 0x08
10008 #define _DAC7CON0_OE2 0x10
10009 #define _DAC7CON0_DACOE2 0x10
10010 #define _DAC7CON0_DAC7OE2 0x10
10011 #define _DAC7CON0_OE1 0x20
10012 #define _DAC7CON0_DACOE1 0x20
10013 #define _DAC7CON0_DAC7OE1 0x20
10014 #define _DAC7CON0_EN 0x80
10015 #define _DAC7CON0_DACEN 0x80
10016 #define _DAC7CON0_DAC7EN 0x80
10018 //==============================================================================
10021 //==============================================================================
10024 extern __at(0x059F) __sfr DAC7CON1
;
10030 unsigned DACR0
: 1;
10031 unsigned DACR1
: 1;
10032 unsigned DACR2
: 1;
10033 unsigned DACR3
: 1;
10034 unsigned DACR4
: 1;
10054 unsigned DAC7R0
: 1;
10055 unsigned DAC7R1
: 1;
10056 unsigned DAC7R2
: 1;
10057 unsigned DAC7R3
: 1;
10058 unsigned DAC7R4
: 1;
10078 unsigned DAC7REF0
: 1;
10079 unsigned DAC7REF1
: 1;
10080 unsigned DAC7REF2
: 1;
10081 unsigned DAC7REF3
: 1;
10082 unsigned DAC7REF4
: 1;
10090 unsigned DAC7R
: 5;
10108 unsigned DAC7REF
: 5;
10117 } __DAC7CON1bits_t
;
10119 extern __at(0x059F) volatile __DAC7CON1bits_t DAC7CON1bits
;
10121 #define _DAC7CON1_DACR0 0x01
10122 #define _DAC7CON1_R0 0x01
10123 #define _DAC7CON1_DAC7R0 0x01
10124 #define _DAC7CON1_REF0 0x01
10125 #define _DAC7CON1_DAC7REF0 0x01
10126 #define _DAC7CON1_DACR1 0x02
10127 #define _DAC7CON1_R1 0x02
10128 #define _DAC7CON1_DAC7R1 0x02
10129 #define _DAC7CON1_REF1 0x02
10130 #define _DAC7CON1_DAC7REF1 0x02
10131 #define _DAC7CON1_DACR2 0x04
10132 #define _DAC7CON1_R2 0x04
10133 #define _DAC7CON1_DAC7R2 0x04
10134 #define _DAC7CON1_REF2 0x04
10135 #define _DAC7CON1_DAC7REF2 0x04
10136 #define _DAC7CON1_DACR3 0x08
10137 #define _DAC7CON1_R3 0x08
10138 #define _DAC7CON1_DAC7R3 0x08
10139 #define _DAC7CON1_REF3 0x08
10140 #define _DAC7CON1_DAC7REF3 0x08
10141 #define _DAC7CON1_DACR4 0x10
10142 #define _DAC7CON1_R4 0x10
10143 #define _DAC7CON1_DAC7R4 0x10
10144 #define _DAC7CON1_REF4 0x10
10145 #define _DAC7CON1_DAC7REF4 0x10
10147 //==============================================================================
10150 //==============================================================================
10153 extern __at(0x059F) __sfr DAC7REF
;
10159 unsigned DACR0
: 1;
10160 unsigned DACR1
: 1;
10161 unsigned DACR2
: 1;
10162 unsigned DACR3
: 1;
10163 unsigned DACR4
: 1;
10183 unsigned DAC7R0
: 1;
10184 unsigned DAC7R1
: 1;
10185 unsigned DAC7R2
: 1;
10186 unsigned DAC7R3
: 1;
10187 unsigned DAC7R4
: 1;
10207 unsigned DAC7REF0
: 1;
10208 unsigned DAC7REF1
: 1;
10209 unsigned DAC7REF2
: 1;
10210 unsigned DAC7REF3
: 1;
10211 unsigned DAC7REF4
: 1;
10219 unsigned DAC7REF
: 5;
10231 unsigned DAC7R
: 5;
10248 extern __at(0x059F) volatile __DAC7REFbits_t DAC7REFbits
;
10250 #define _DAC7REF_DACR0 0x01
10251 #define _DAC7REF_R0 0x01
10252 #define _DAC7REF_DAC7R0 0x01
10253 #define _DAC7REF_REF0 0x01
10254 #define _DAC7REF_DAC7REF0 0x01
10255 #define _DAC7REF_DACR1 0x02
10256 #define _DAC7REF_R1 0x02
10257 #define _DAC7REF_DAC7R1 0x02
10258 #define _DAC7REF_REF1 0x02
10259 #define _DAC7REF_DAC7REF1 0x02
10260 #define _DAC7REF_DACR2 0x04
10261 #define _DAC7REF_R2 0x04
10262 #define _DAC7REF_DAC7R2 0x04
10263 #define _DAC7REF_REF2 0x04
10264 #define _DAC7REF_DAC7REF2 0x04
10265 #define _DAC7REF_DACR3 0x08
10266 #define _DAC7REF_R3 0x08
10267 #define _DAC7REF_DAC7R3 0x08
10268 #define _DAC7REF_REF3 0x08
10269 #define _DAC7REF_DAC7REF3 0x08
10270 #define _DAC7REF_DACR4 0x10
10271 #define _DAC7REF_R4 0x10
10272 #define _DAC7REF_DAC7R4 0x10
10273 #define _DAC7REF_REF4 0x10
10274 #define _DAC7REF_DAC7REF4 0x10
10276 //==============================================================================
10279 //==============================================================================
10282 extern __at(0x0614) __sfr PWM3DCL
;
10306 unsigned PWM3DC0
: 1;
10307 unsigned PWM3DC1
: 1;
10318 unsigned PWMPW0
: 1;
10319 unsigned PWMPW1
: 1;
10325 unsigned PWMPW
: 2;
10331 unsigned PWM3DC
: 2;
10341 extern __at(0x0614) volatile __PWM3DCLbits_t PWM3DCLbits
;
10344 #define _PWM3DC0 0x40
10345 #define _PWMPW0 0x40
10347 #define _PWM3DC1 0x80
10348 #define _PWMPW1 0x80
10350 //==============================================================================
10353 //==============================================================================
10356 extern __at(0x0615) __sfr PWM3DCH
;
10374 unsigned PWM3DC2
: 1;
10375 unsigned PWM3DC3
: 1;
10376 unsigned PWM3DC4
: 1;
10377 unsigned PWM3DC5
: 1;
10378 unsigned PWM3DC6
: 1;
10379 unsigned PWM3DC7
: 1;
10380 unsigned PWM3DC8
: 1;
10381 unsigned PWM3DC9
: 1;
10386 unsigned PWMPW2
: 1;
10387 unsigned PWMPW3
: 1;
10388 unsigned PWMPW4
: 1;
10389 unsigned PWMPW5
: 1;
10390 unsigned PWMPW6
: 1;
10391 unsigned PWMPW7
: 1;
10392 unsigned PWMPW8
: 1;
10393 unsigned PWMPW9
: 1;
10397 extern __at(0x0615) volatile __PWM3DCHbits_t PWM3DCHbits
;
10400 #define _PWM3DC2 0x01
10401 #define _PWMPW2 0x01
10403 #define _PWM3DC3 0x02
10404 #define _PWMPW3 0x02
10406 #define _PWM3DC4 0x04
10407 #define _PWMPW4 0x04
10409 #define _PWM3DC5 0x08
10410 #define _PWMPW5 0x08
10412 #define _PWM3DC6 0x10
10413 #define _PWMPW6 0x10
10415 #define _PWM3DC7 0x20
10416 #define _PWMPW7 0x20
10418 #define _PWM3DC8 0x40
10419 #define _PWMPW8 0x40
10421 #define _PWM3DC9 0x80
10422 #define _PWMPW9 0x80
10424 //==============================================================================
10427 //==============================================================================
10430 extern __at(0x0616) __sfr PWM3CON
;
10452 unsigned PWM3POL
: 1;
10453 unsigned PWM3OUT
: 1;
10455 unsigned PWM3EN
: 1;
10459 extern __at(0x0616) volatile __PWM3CONbits_t PWM3CONbits
;
10461 #define _PWM3CON_POL 0x10
10462 #define _PWM3CON_PWM3POL 0x10
10463 #define _PWM3CON_OUT 0x20
10464 #define _PWM3CON_PWM3OUT 0x20
10465 #define _PWM3CON_EN 0x80
10466 #define _PWM3CON_PWM3EN 0x80
10468 //==============================================================================
10471 //==============================================================================
10474 extern __at(0x0617) __sfr PWM4DCL
;
10498 unsigned PWM4DC0
: 1;
10499 unsigned PWM4DC1
: 1;
10510 unsigned PWMPW0
: 1;
10511 unsigned PWMPW1
: 1;
10517 unsigned PWMPW
: 2;
10529 unsigned PWM4DC
: 2;
10533 extern __at(0x0617) volatile __PWM4DCLbits_t PWM4DCLbits
;
10535 #define _PWM4DCL_DC0 0x40
10536 #define _PWM4DCL_PWM4DC0 0x40
10537 #define _PWM4DCL_PWMPW0 0x40
10538 #define _PWM4DCL_DC1 0x80
10539 #define _PWM4DCL_PWM4DC1 0x80
10540 #define _PWM4DCL_PWMPW1 0x80
10542 //==============================================================================
10545 //==============================================================================
10548 extern __at(0x0618) __sfr PWM4DCH
;
10566 unsigned PWM4DC2
: 1;
10567 unsigned PWM4DC3
: 1;
10568 unsigned PWM4DC4
: 1;
10569 unsigned PWM4DC5
: 1;
10570 unsigned PWM4DC6
: 1;
10571 unsigned PWM4DC7
: 1;
10572 unsigned PWM4DC8
: 1;
10573 unsigned PWM4DC9
: 1;
10578 unsigned PWMPW2
: 1;
10579 unsigned PWMPW3
: 1;
10580 unsigned PWMPW4
: 1;
10581 unsigned PWMPW5
: 1;
10582 unsigned PWMPW6
: 1;
10583 unsigned PWMPW7
: 1;
10584 unsigned PWMPW8
: 1;
10585 unsigned PWMPW9
: 1;
10589 extern __at(0x0618) volatile __PWM4DCHbits_t PWM4DCHbits
;
10591 #define _PWM4DCH_DC2 0x01
10592 #define _PWM4DCH_PWM4DC2 0x01
10593 #define _PWM4DCH_PWMPW2 0x01
10594 #define _PWM4DCH_DC3 0x02
10595 #define _PWM4DCH_PWM4DC3 0x02
10596 #define _PWM4DCH_PWMPW3 0x02
10597 #define _PWM4DCH_DC4 0x04
10598 #define _PWM4DCH_PWM4DC4 0x04
10599 #define _PWM4DCH_PWMPW4 0x04
10600 #define _PWM4DCH_DC5 0x08
10601 #define _PWM4DCH_PWM4DC5 0x08
10602 #define _PWM4DCH_PWMPW5 0x08
10603 #define _PWM4DCH_DC6 0x10
10604 #define _PWM4DCH_PWM4DC6 0x10
10605 #define _PWM4DCH_PWMPW6 0x10
10606 #define _PWM4DCH_DC7 0x20
10607 #define _PWM4DCH_PWM4DC7 0x20
10608 #define _PWM4DCH_PWMPW7 0x20
10609 #define _PWM4DCH_DC8 0x40
10610 #define _PWM4DCH_PWM4DC8 0x40
10611 #define _PWM4DCH_PWMPW8 0x40
10612 #define _PWM4DCH_DC9 0x80
10613 #define _PWM4DCH_PWM4DC9 0x80
10614 #define _PWM4DCH_PWMPW9 0x80
10616 //==============================================================================
10619 //==============================================================================
10622 extern __at(0x0619) __sfr PWM4CON
;
10644 unsigned PWM4POL
: 1;
10645 unsigned PWM4OUT
: 1;
10647 unsigned PWM4EN
: 1;
10651 extern __at(0x0619) volatile __PWM4CONbits_t PWM4CONbits
;
10653 #define _PWM4CON_POL 0x10
10654 #define _PWM4CON_PWM4POL 0x10
10655 #define _PWM4CON_OUT 0x20
10656 #define _PWM4CON_PWM4OUT 0x20
10657 #define _PWM4CON_EN 0x80
10658 #define _PWM4CON_PWM4EN 0x80
10660 //==============================================================================
10663 //==============================================================================
10666 extern __at(0x061A) __sfr PWM9DCL
;
10690 unsigned PWM9DC0
: 1;
10691 unsigned PWM9DC1
: 1;
10702 unsigned PWMPW0
: 1;
10703 unsigned PWMPW1
: 1;
10709 unsigned PWMPW
: 2;
10721 unsigned PWM9DC
: 2;
10725 extern __at(0x061A) volatile __PWM9DCLbits_t PWM9DCLbits
;
10727 #define _PWM9DCL_DC0 0x40
10728 #define _PWM9DCL_PWM9DC0 0x40
10729 #define _PWM9DCL_PWMPW0 0x40
10730 #define _PWM9DCL_DC1 0x80
10731 #define _PWM9DCL_PWM9DC1 0x80
10732 #define _PWM9DCL_PWMPW1 0x80
10734 //==============================================================================
10737 //==============================================================================
10740 extern __at(0x061B) __sfr PWM9DCH
;
10758 unsigned PWM9DC2
: 1;
10759 unsigned PWM9DC3
: 1;
10760 unsigned PWM9DC4
: 1;
10761 unsigned PWM9DC5
: 1;
10762 unsigned PWM9DC6
: 1;
10763 unsigned PWM9DC7
: 1;
10764 unsigned PWM9DC8
: 1;
10765 unsigned PWM9DC9
: 1;
10770 unsigned PWMPW2
: 1;
10771 unsigned PWMPW3
: 1;
10772 unsigned PWMPW4
: 1;
10773 unsigned PWMPW5
: 1;
10774 unsigned PWMPW6
: 1;
10775 unsigned PWMPW7
: 1;
10776 unsigned PWMPW8
: 1;
10777 unsigned PWMPW9
: 1;
10781 extern __at(0x061B) volatile __PWM9DCHbits_t PWM9DCHbits
;
10783 #define _PWM9DCH_DC2 0x01
10784 #define _PWM9DCH_PWM9DC2 0x01
10785 #define _PWM9DCH_PWMPW2 0x01
10786 #define _PWM9DCH_DC3 0x02
10787 #define _PWM9DCH_PWM9DC3 0x02
10788 #define _PWM9DCH_PWMPW3 0x02
10789 #define _PWM9DCH_DC4 0x04
10790 #define _PWM9DCH_PWM9DC4 0x04
10791 #define _PWM9DCH_PWMPW4 0x04
10792 #define _PWM9DCH_DC5 0x08
10793 #define _PWM9DCH_PWM9DC5 0x08
10794 #define _PWM9DCH_PWMPW5 0x08
10795 #define _PWM9DCH_DC6 0x10
10796 #define _PWM9DCH_PWM9DC6 0x10
10797 #define _PWM9DCH_PWMPW6 0x10
10798 #define _PWM9DCH_DC7 0x20
10799 #define _PWM9DCH_PWM9DC7 0x20
10800 #define _PWM9DCH_PWMPW7 0x20
10801 #define _PWM9DCH_DC8 0x40
10802 #define _PWM9DCH_PWM9DC8 0x40
10803 #define _PWM9DCH_PWMPW8 0x40
10804 #define _PWM9DCH_DC9 0x80
10805 #define _PWM9DCH_PWM9DC9 0x80
10806 #define _PWM9DCH_PWMPW9 0x80
10808 //==============================================================================
10811 //==============================================================================
10814 extern __at(0x061C) __sfr PWM9CON
;
10836 unsigned PWM9POL
: 1;
10837 unsigned PWM9OUT
: 1;
10839 unsigned PWM9EN
: 1;
10843 extern __at(0x061C) volatile __PWM9CONbits_t PWM9CONbits
;
10845 #define _PWM9CON_POL 0x10
10846 #define _PWM9CON_PWM9POL 0x10
10847 #define _PWM9CON_OUT 0x20
10848 #define _PWM9CON_PWM9OUT 0x20
10849 #define _PWM9CON_EN 0x80
10850 #define _PWM9CON_PWM9EN 0x80
10852 //==============================================================================
10855 //==============================================================================
10858 extern __at(0x068D) __sfr COG1PHR
;
10876 unsigned G1PHR0
: 1;
10877 unsigned G1PHR1
: 1;
10878 unsigned G1PHR2
: 1;
10879 unsigned G1PHR3
: 1;
10880 unsigned G1PHR4
: 1;
10881 unsigned G1PHR5
: 1;
10888 unsigned G1PHR
: 6;
10899 extern __at(0x068D) volatile __COG1PHRbits_t COG1PHRbits
;
10902 #define _G1PHR0 0x01
10904 #define _G1PHR1 0x02
10906 #define _G1PHR2 0x04
10908 #define _G1PHR3 0x08
10910 #define _G1PHR4 0x10
10912 #define _G1PHR5 0x20
10914 //==============================================================================
10917 //==============================================================================
10920 extern __at(0x068E) __sfr COG1PHF
;
10938 unsigned G1PHF0
: 1;
10939 unsigned G1PHF1
: 1;
10940 unsigned G1PHF2
: 1;
10941 unsigned G1PHF3
: 1;
10942 unsigned G1PHF4
: 1;
10943 unsigned G1PHF5
: 1;
10950 unsigned G1PHF
: 6;
10961 extern __at(0x068E) volatile __COG1PHFbits_t COG1PHFbits
;
10964 #define _G1PHF0 0x01
10966 #define _G1PHF1 0x02
10968 #define _G1PHF2 0x04
10970 #define _G1PHF3 0x08
10972 #define _G1PHF4 0x10
10974 #define _G1PHF5 0x20
10976 //==============================================================================
10979 //==============================================================================
10982 extern __at(0x068F) __sfr COG1BLKR
;
10988 unsigned BLKR0
: 1;
10989 unsigned BLKR1
: 1;
10990 unsigned BLKR2
: 1;
10991 unsigned BLKR3
: 1;
10992 unsigned BLKR4
: 1;
10993 unsigned BLKR5
: 1;
11000 unsigned G1BLKR0
: 1;
11001 unsigned G1BLKR1
: 1;
11002 unsigned G1BLKR2
: 1;
11003 unsigned G1BLKR3
: 1;
11004 unsigned G1BLKR4
: 1;
11005 unsigned G1BLKR5
: 1;
11012 unsigned G1BLKR
: 6;
11021 } __COG1BLKRbits_t
;
11023 extern __at(0x068F) volatile __COG1BLKRbits_t COG1BLKRbits
;
11025 #define _BLKR0 0x01
11026 #define _G1BLKR0 0x01
11027 #define _BLKR1 0x02
11028 #define _G1BLKR1 0x02
11029 #define _BLKR2 0x04
11030 #define _G1BLKR2 0x04
11031 #define _BLKR3 0x08
11032 #define _G1BLKR3 0x08
11033 #define _BLKR4 0x10
11034 #define _G1BLKR4 0x10
11035 #define _BLKR5 0x20
11036 #define _G1BLKR5 0x20
11038 //==============================================================================
11041 //==============================================================================
11044 extern __at(0x0690) __sfr COG1BLKF
;
11050 unsigned BLKF0
: 1;
11051 unsigned BLKF1
: 1;
11052 unsigned BLKF2
: 1;
11053 unsigned BLKF3
: 1;
11054 unsigned BLKF4
: 1;
11055 unsigned BLKF5
: 1;
11062 unsigned G1BLKF0
: 1;
11063 unsigned G1BLKF1
: 1;
11064 unsigned G1BLKF2
: 1;
11065 unsigned G1BLKF3
: 1;
11066 unsigned G1BLKF4
: 1;
11067 unsigned G1BLKF5
: 1;
11080 unsigned G1BLKF
: 6;
11083 } __COG1BLKFbits_t
;
11085 extern __at(0x0690) volatile __COG1BLKFbits_t COG1BLKFbits
;
11087 #define _BLKF0 0x01
11088 #define _G1BLKF0 0x01
11089 #define _BLKF1 0x02
11090 #define _G1BLKF1 0x02
11091 #define _BLKF2 0x04
11092 #define _G1BLKF2 0x04
11093 #define _BLKF3 0x08
11094 #define _G1BLKF3 0x08
11095 #define _BLKF4 0x10
11096 #define _G1BLKF4 0x10
11097 #define _BLKF5 0x20
11098 #define _G1BLKF5 0x20
11100 //==============================================================================
11103 //==============================================================================
11106 extern __at(0x0691) __sfr COG1DBR
;
11124 unsigned G1DBR0
: 1;
11125 unsigned G1DBR1
: 1;
11126 unsigned G1DBR2
: 1;
11127 unsigned G1DBR3
: 1;
11128 unsigned G1DBR4
: 1;
11129 unsigned G1DBR5
: 1;
11136 unsigned G1DBR
: 6;
11147 extern __at(0x0691) volatile __COG1DBRbits_t COG1DBRbits
;
11150 #define _G1DBR0 0x01
11152 #define _G1DBR1 0x02
11154 #define _G1DBR2 0x04
11156 #define _G1DBR3 0x08
11158 #define _G1DBR4 0x10
11160 #define _G1DBR5 0x20
11162 //==============================================================================
11165 //==============================================================================
11168 extern __at(0x0692) __sfr COG1DBF
;
11186 unsigned G1DBF0
: 1;
11187 unsigned G1DBF1
: 1;
11188 unsigned G1DBF2
: 1;
11189 unsigned G1DBF3
: 1;
11190 unsigned G1DBF4
: 1;
11191 unsigned G1DBF5
: 1;
11198 unsigned G1DBF
: 6;
11209 extern __at(0x0692) volatile __COG1DBFbits_t COG1DBFbits
;
11212 #define _G1DBF0 0x01
11214 #define _G1DBF1 0x02
11216 #define _G1DBF2 0x04
11218 #define _G1DBF3 0x08
11220 #define _G1DBF4 0x10
11222 #define _G1DBF5 0x20
11224 //==============================================================================
11227 //==============================================================================
11230 extern __at(0x0693) __sfr COG1CON0
;
11248 unsigned G1MD0
: 1;
11249 unsigned G1MD1
: 1;
11250 unsigned G1MD2
: 1;
11251 unsigned G1CS0
: 1;
11252 unsigned G1CS1
: 1;
11283 } __COG1CON0bits_t
;
11285 extern __at(0x0693) volatile __COG1CON0bits_t COG1CON0bits
;
11287 #define _COG1CON0_MD0 0x01
11288 #define _COG1CON0_G1MD0 0x01
11289 #define _COG1CON0_MD1 0x02
11290 #define _COG1CON0_G1MD1 0x02
11291 #define _COG1CON0_MD2 0x04
11292 #define _COG1CON0_G1MD2 0x04
11293 #define _COG1CON0_CS0 0x08
11294 #define _COG1CON0_G1CS0 0x08
11295 #define _COG1CON0_CS1 0x10
11296 #define _COG1CON0_G1CS1 0x10
11297 #define _COG1CON0_LD 0x40
11298 #define _COG1CON0_G1LD 0x40
11299 #define _COG1CON0_EN 0x80
11300 #define _COG1CON0_G1EN 0x80
11302 //==============================================================================
11305 //==============================================================================
11308 extern __at(0x0694) __sfr COG1CON1
;
11326 unsigned G1POLA
: 1;
11327 unsigned G1POLB
: 1;
11328 unsigned G1POLC
: 1;
11329 unsigned G1POLD
: 1;
11332 unsigned G1FDBS
: 1;
11333 unsigned G1RDBS
: 1;
11335 } __COG1CON1bits_t
;
11337 extern __at(0x0694) volatile __COG1CON1bits_t COG1CON1bits
;
11340 #define _G1POLA 0x01
11342 #define _G1POLB 0x02
11344 #define _G1POLC 0x04
11346 #define _G1POLD 0x08
11348 #define _G1FDBS 0x40
11350 #define _G1RDBS 0x80
11352 //==============================================================================
11355 //==============================================================================
11358 extern __at(0x0695) __sfr COG1RIS0
;
11376 unsigned G1RIS0
: 1;
11377 unsigned G1RIS1
: 1;
11378 unsigned G1RIS2
: 1;
11379 unsigned G1RIS3
: 1;
11380 unsigned G1RIS4
: 1;
11381 unsigned G1RIS5
: 1;
11382 unsigned G1RIS6
: 1;
11383 unsigned G1RIS7
: 1;
11385 } __COG1RIS0bits_t
;
11387 extern __at(0x0695) volatile __COG1RIS0bits_t COG1RIS0bits
;
11390 #define _G1RIS0 0x01
11392 #define _G1RIS1 0x02
11394 #define _G1RIS2 0x04
11396 #define _G1RIS3 0x08
11398 #define _G1RIS4 0x10
11400 #define _G1RIS5 0x20
11402 #define _G1RIS6 0x40
11404 #define _G1RIS7 0x80
11406 //==============================================================================
11409 //==============================================================================
11412 extern __at(0x0696) __sfr COG1RIS1
;
11420 unsigned RIS10
: 1;
11421 unsigned RIS11
: 1;
11422 unsigned RIS12
: 1;
11423 unsigned RIS13
: 1;
11424 unsigned RIS14
: 1;
11425 unsigned RIS15
: 1;
11430 unsigned G1RIS8
: 1;
11431 unsigned G1RIS9
: 1;
11432 unsigned G1RIS10
: 1;
11433 unsigned G1RIS11
: 1;
11434 unsigned G1RIS12
: 1;
11435 unsigned G1RIS13
: 1;
11436 unsigned G1RIS14
: 1;
11437 unsigned G1RIS15
: 1;
11439 } __COG1RIS1bits_t
;
11441 extern __at(0x0696) volatile __COG1RIS1bits_t COG1RIS1bits
;
11444 #define _G1RIS8 0x01
11446 #define _G1RIS9 0x02
11447 #define _RIS10 0x04
11448 #define _G1RIS10 0x04
11449 #define _RIS11 0x08
11450 #define _G1RIS11 0x08
11451 #define _RIS12 0x10
11452 #define _G1RIS12 0x10
11453 #define _RIS13 0x20
11454 #define _G1RIS13 0x20
11455 #define _RIS14 0x40
11456 #define _G1RIS14 0x40
11457 #define _RIS15 0x80
11458 #define _G1RIS15 0x80
11460 //==============================================================================
11463 //==============================================================================
11466 extern __at(0x0697) __sfr COG1RSIM0
;
11472 unsigned RSIM0
: 1;
11473 unsigned RSIM1
: 1;
11474 unsigned RSIM2
: 1;
11475 unsigned RSIM3
: 1;
11476 unsigned RSIM4
: 1;
11477 unsigned RSIM5
: 1;
11478 unsigned RSIM6
: 1;
11479 unsigned RSIM7
: 1;
11484 unsigned G1RSIM0
: 1;
11485 unsigned G1RSIM1
: 1;
11486 unsigned G1RSIM2
: 1;
11487 unsigned G1RSIM3
: 1;
11488 unsigned G1RSIM4
: 1;
11489 unsigned G1RSIM5
: 1;
11490 unsigned G1RSIM6
: 1;
11491 unsigned G1RSIM7
: 1;
11493 } __COG1RSIM0bits_t
;
11495 extern __at(0x0697) volatile __COG1RSIM0bits_t COG1RSIM0bits
;
11497 #define _RSIM0 0x01
11498 #define _G1RSIM0 0x01
11499 #define _RSIM1 0x02
11500 #define _G1RSIM1 0x02
11501 #define _RSIM2 0x04
11502 #define _G1RSIM2 0x04
11503 #define _RSIM3 0x08
11504 #define _G1RSIM3 0x08
11505 #define _RSIM4 0x10
11506 #define _G1RSIM4 0x10
11507 #define _RSIM5 0x20
11508 #define _G1RSIM5 0x20
11509 #define _RSIM6 0x40
11510 #define _G1RSIM6 0x40
11511 #define _RSIM7 0x80
11512 #define _G1RSIM7 0x80
11514 //==============================================================================
11517 //==============================================================================
11520 extern __at(0x0698) __sfr COG1RSIM1
;
11526 unsigned RSIM8
: 1;
11527 unsigned RSIM9
: 1;
11528 unsigned RSIM10
: 1;
11529 unsigned RSIM11
: 1;
11530 unsigned RSIM12
: 1;
11531 unsigned RSIM13
: 1;
11532 unsigned RSIM14
: 1;
11533 unsigned RSIM15
: 1;
11538 unsigned G1RSIM8
: 1;
11539 unsigned G1RSIM9
: 1;
11540 unsigned G1RSIM10
: 1;
11541 unsigned G1RSIM11
: 1;
11542 unsigned G1RSIM12
: 1;
11543 unsigned G1RSIM13
: 1;
11544 unsigned G1RSIM14
: 1;
11545 unsigned G1RSIM15
: 1;
11547 } __COG1RSIM1bits_t
;
11549 extern __at(0x0698) volatile __COG1RSIM1bits_t COG1RSIM1bits
;
11551 #define _RSIM8 0x01
11552 #define _G1RSIM8 0x01
11553 #define _RSIM9 0x02
11554 #define _G1RSIM9 0x02
11555 #define _RSIM10 0x04
11556 #define _G1RSIM10 0x04
11557 #define _RSIM11 0x08
11558 #define _G1RSIM11 0x08
11559 #define _RSIM12 0x10
11560 #define _G1RSIM12 0x10
11561 #define _RSIM13 0x20
11562 #define _G1RSIM13 0x20
11563 #define _RSIM14 0x40
11564 #define _G1RSIM14 0x40
11565 #define _RSIM15 0x80
11566 #define _G1RSIM15 0x80
11568 //==============================================================================
11571 //==============================================================================
11574 extern __at(0x0699) __sfr COG1FIS0
;
11592 unsigned G1FIS0
: 1;
11593 unsigned G1FIS1
: 1;
11594 unsigned G1FIS2
: 1;
11595 unsigned G1FIS3
: 1;
11596 unsigned G1FIS4
: 1;
11597 unsigned G1FIS5
: 1;
11598 unsigned G1FIS6
: 1;
11599 unsigned G1FIS7
: 1;
11601 } __COG1FIS0bits_t
;
11603 extern __at(0x0699) volatile __COG1FIS0bits_t COG1FIS0bits
;
11606 #define _G1FIS0 0x01
11608 #define _G1FIS1 0x02
11610 #define _G1FIS2 0x04
11612 #define _G1FIS3 0x08
11614 #define _G1FIS4 0x10
11616 #define _G1FIS5 0x20
11618 #define _G1FIS6 0x40
11620 #define _G1FIS7 0x80
11622 //==============================================================================
11625 //==============================================================================
11628 extern __at(0x069A) __sfr COG1FIS1
;
11636 unsigned FIS10
: 1;
11637 unsigned FIS11
: 1;
11638 unsigned FIS12
: 1;
11639 unsigned FIS13
: 1;
11640 unsigned FIS14
: 1;
11641 unsigned FIS15
: 1;
11646 unsigned G1FIS8
: 1;
11647 unsigned G1FIS9
: 1;
11648 unsigned G1FIS10
: 1;
11649 unsigned G1FIS11
: 1;
11650 unsigned G1FIS12
: 1;
11651 unsigned G1FIS13
: 1;
11652 unsigned G1FIS14
: 1;
11653 unsigned G1FIS15
: 1;
11655 } __COG1FIS1bits_t
;
11657 extern __at(0x069A) volatile __COG1FIS1bits_t COG1FIS1bits
;
11660 #define _G1FIS8 0x01
11662 #define _G1FIS9 0x02
11663 #define _FIS10 0x04
11664 #define _G1FIS10 0x04
11665 #define _FIS11 0x08
11666 #define _G1FIS11 0x08
11667 #define _FIS12 0x10
11668 #define _G1FIS12 0x10
11669 #define _FIS13 0x20
11670 #define _G1FIS13 0x20
11671 #define _FIS14 0x40
11672 #define _G1FIS14 0x40
11673 #define _FIS15 0x80
11674 #define _G1FIS15 0x80
11676 //==============================================================================
11679 //==============================================================================
11682 extern __at(0x069B) __sfr COG1FSIM0
;
11688 unsigned FSIM0
: 1;
11689 unsigned FSIM1
: 1;
11690 unsigned FSIM2
: 1;
11691 unsigned FSIM3
: 1;
11692 unsigned FSIM4
: 1;
11693 unsigned FSIM5
: 1;
11694 unsigned FSIM6
: 1;
11695 unsigned FSIM7
: 1;
11700 unsigned G1FSIM0
: 1;
11701 unsigned G1FSIM1
: 1;
11702 unsigned G1FSIM2
: 1;
11703 unsigned G1FSIM3
: 1;
11704 unsigned G1FSIM4
: 1;
11705 unsigned G1FSIM5
: 1;
11706 unsigned G1FSIM6
: 1;
11707 unsigned G1FSIM7
: 1;
11709 } __COG1FSIM0bits_t
;
11711 extern __at(0x069B) volatile __COG1FSIM0bits_t COG1FSIM0bits
;
11713 #define _FSIM0 0x01
11714 #define _G1FSIM0 0x01
11715 #define _FSIM1 0x02
11716 #define _G1FSIM1 0x02
11717 #define _FSIM2 0x04
11718 #define _G1FSIM2 0x04
11719 #define _FSIM3 0x08
11720 #define _G1FSIM3 0x08
11721 #define _FSIM4 0x10
11722 #define _G1FSIM4 0x10
11723 #define _FSIM5 0x20
11724 #define _G1FSIM5 0x20
11725 #define _FSIM6 0x40
11726 #define _G1FSIM6 0x40
11727 #define _FSIM7 0x80
11728 #define _G1FSIM7 0x80
11730 //==============================================================================
11733 //==============================================================================
11736 extern __at(0x069C) __sfr COG1FSIM1
;
11742 unsigned FSIM8
: 1;
11743 unsigned FSIM9
: 1;
11744 unsigned FSIM10
: 1;
11745 unsigned FSIM11
: 1;
11746 unsigned FSIM12
: 1;
11747 unsigned FSIM13
: 1;
11748 unsigned FSIM14
: 1;
11749 unsigned FSIM15
: 1;
11754 unsigned G1FSIM8
: 1;
11755 unsigned G1FSIM9
: 1;
11756 unsigned G1FSIM10
: 1;
11757 unsigned G1FSIM11
: 1;
11758 unsigned G1FSIM12
: 1;
11759 unsigned G1FSIM13
: 1;
11760 unsigned G1FSIM14
: 1;
11761 unsigned G1FSIM15
: 1;
11763 } __COG1FSIM1bits_t
;
11765 extern __at(0x069C) volatile __COG1FSIM1bits_t COG1FSIM1bits
;
11767 #define _FSIM8 0x01
11768 #define _G1FSIM8 0x01
11769 #define _FSIM9 0x02
11770 #define _G1FSIM9 0x02
11771 #define _FSIM10 0x04
11772 #define _G1FSIM10 0x04
11773 #define _FSIM11 0x08
11774 #define _G1FSIM11 0x08
11775 #define _FSIM12 0x10
11776 #define _G1FSIM12 0x10
11777 #define _FSIM13 0x20
11778 #define _G1FSIM13 0x20
11779 #define _FSIM14 0x40
11780 #define _G1FSIM14 0x40
11781 #define _FSIM15 0x80
11782 #define _G1FSIM15 0x80
11784 //==============================================================================
11787 //==============================================================================
11790 extern __at(0x069D) __sfr COG1ASD0
;
11798 unsigned ASDAC0
: 1;
11799 unsigned ASDAC1
: 1;
11800 unsigned ASDBD0
: 1;
11801 unsigned ASDBD1
: 1;
11802 unsigned ASREN
: 1;
11810 unsigned G1ASDAC0
: 1;
11811 unsigned G1ASDAC1
: 1;
11812 unsigned G1ASDBD0
: 1;
11813 unsigned G1ASDBD1
: 1;
11814 unsigned ARSEN
: 1;
11815 unsigned G1ASE
: 1;
11826 unsigned G1ARSEN
: 1;
11838 unsigned G1ASREN
: 1;
11845 unsigned G1ASDAC
: 2;
11852 unsigned ASDAC
: 2;
11859 unsigned ASDBD
: 2;
11866 unsigned G1ASDBD
: 2;
11869 } __COG1ASD0bits_t
;
11871 extern __at(0x069D) volatile __COG1ASD0bits_t COG1ASD0bits
;
11873 #define _ASDAC0 0x04
11874 #define _G1ASDAC0 0x04
11875 #define _ASDAC1 0x08
11876 #define _G1ASDAC1 0x08
11877 #define _ASDBD0 0x10
11878 #define _G1ASDBD0 0x10
11879 #define _ASDBD1 0x20
11880 #define _G1ASDBD1 0x20
11881 #define _ASREN 0x40
11882 #define _ARSEN 0x40
11883 #define _G1ARSEN 0x40
11884 #define _G1ASREN 0x40
11886 #define _G1ASE 0x80
11888 //==============================================================================
11891 //==============================================================================
11894 extern __at(0x069E) __sfr COG1ASD1
;
11912 unsigned G1AS0E
: 1;
11913 unsigned G1AS1E
: 1;
11914 unsigned G1AS2E
: 1;
11915 unsigned G1AS3E
: 1;
11916 unsigned G1AS4E
: 1;
11917 unsigned G1AS5E
: 1;
11918 unsigned G1AS6E
: 1;
11919 unsigned G1AS7E
: 1;
11921 } __COG1ASD1bits_t
;
11923 extern __at(0x069E) volatile __COG1ASD1bits_t COG1ASD1bits
;
11926 #define _G1AS0E 0x01
11928 #define _G1AS1E 0x02
11930 #define _G1AS2E 0x04
11932 #define _G1AS3E 0x08
11934 #define _G1AS4E 0x10
11936 #define _G1AS5E 0x20
11938 #define _G1AS6E 0x40
11940 #define _G1AS7E 0x80
11942 //==============================================================================
11945 //==============================================================================
11948 extern __at(0x069F) __sfr COG1STR
;
11958 unsigned SDATA
: 1;
11959 unsigned SDATB
: 1;
11960 unsigned SDATC
: 1;
11961 unsigned SDATD
: 1;
11966 unsigned G1STRA
: 1;
11967 unsigned G1STRB
: 1;
11968 unsigned G1STRC
: 1;
11969 unsigned G1STRD
: 1;
11970 unsigned G1SDATA
: 1;
11971 unsigned G1SDATB
: 1;
11972 unsigned G1SDATC
: 1;
11973 unsigned G1SDATD
: 1;
11977 extern __at(0x069F) volatile __COG1STRbits_t COG1STRbits
;
11980 #define _G1STRA 0x01
11982 #define _G1STRB 0x02
11984 #define _G1STRC 0x04
11986 #define _G1STRD 0x08
11987 #define _SDATA 0x10
11988 #define _G1SDATA 0x10
11989 #define _SDATB 0x20
11990 #define _G1SDATB 0x20
11991 #define _SDATC 0x40
11992 #define _G1SDATC 0x40
11993 #define _SDATD 0x80
11994 #define _G1SDATD 0x80
11996 //==============================================================================
11999 //==============================================================================
12002 extern __at(0x070D) __sfr COG2PHR
;
12020 unsigned G2PHR0
: 1;
12021 unsigned G2PHR1
: 1;
12022 unsigned G2PHR2
: 1;
12023 unsigned G2PHR3
: 1;
12024 unsigned G2PHR4
: 1;
12025 unsigned G2PHR5
: 1;
12038 unsigned G2PHR
: 6;
12043 extern __at(0x070D) volatile __COG2PHRbits_t COG2PHRbits
;
12045 #define _COG2PHR_PHR0 0x01
12046 #define _COG2PHR_G2PHR0 0x01
12047 #define _COG2PHR_PHR1 0x02
12048 #define _COG2PHR_G2PHR1 0x02
12049 #define _COG2PHR_PHR2 0x04
12050 #define _COG2PHR_G2PHR2 0x04
12051 #define _COG2PHR_PHR3 0x08
12052 #define _COG2PHR_G2PHR3 0x08
12053 #define _COG2PHR_PHR4 0x10
12054 #define _COG2PHR_G2PHR4 0x10
12055 #define _COG2PHR_PHR5 0x20
12056 #define _COG2PHR_G2PHR5 0x20
12058 //==============================================================================
12061 //==============================================================================
12064 extern __at(0x070E) __sfr COG2PHF
;
12082 unsigned G2PHF0
: 1;
12083 unsigned G2PHF1
: 1;
12084 unsigned G2PHF2
: 1;
12085 unsigned G2PHF3
: 1;
12086 unsigned G2PHF4
: 1;
12087 unsigned G2PHF5
: 1;
12100 unsigned G2PHF
: 6;
12105 extern __at(0x070E) volatile __COG2PHFbits_t COG2PHFbits
;
12107 #define _COG2PHF_PHF0 0x01
12108 #define _COG2PHF_G2PHF0 0x01
12109 #define _COG2PHF_PHF1 0x02
12110 #define _COG2PHF_G2PHF1 0x02
12111 #define _COG2PHF_PHF2 0x04
12112 #define _COG2PHF_G2PHF2 0x04
12113 #define _COG2PHF_PHF3 0x08
12114 #define _COG2PHF_G2PHF3 0x08
12115 #define _COG2PHF_PHF4 0x10
12116 #define _COG2PHF_G2PHF4 0x10
12117 #define _COG2PHF_PHF5 0x20
12118 #define _COG2PHF_G2PHF5 0x20
12120 //==============================================================================
12123 //==============================================================================
12126 extern __at(0x070F) __sfr COG2BLKR
;
12132 unsigned BLKR0
: 1;
12133 unsigned BLKR1
: 1;
12134 unsigned BLKR2
: 1;
12135 unsigned BLKR3
: 1;
12136 unsigned BLKR4
: 1;
12137 unsigned BLKR5
: 1;
12144 unsigned G2BLKR0
: 1;
12145 unsigned G2BLKR1
: 1;
12146 unsigned G2BLKR2
: 1;
12147 unsigned G2BLKR3
: 1;
12148 unsigned G2BLKR4
: 1;
12149 unsigned G2BLKR5
: 1;
12162 unsigned G2BLKR
: 6;
12165 } __COG2BLKRbits_t
;
12167 extern __at(0x070F) volatile __COG2BLKRbits_t COG2BLKRbits
;
12169 #define _COG2BLKR_BLKR0 0x01
12170 #define _COG2BLKR_G2BLKR0 0x01
12171 #define _COG2BLKR_BLKR1 0x02
12172 #define _COG2BLKR_G2BLKR1 0x02
12173 #define _COG2BLKR_BLKR2 0x04
12174 #define _COG2BLKR_G2BLKR2 0x04
12175 #define _COG2BLKR_BLKR3 0x08
12176 #define _COG2BLKR_G2BLKR3 0x08
12177 #define _COG2BLKR_BLKR4 0x10
12178 #define _COG2BLKR_G2BLKR4 0x10
12179 #define _COG2BLKR_BLKR5 0x20
12180 #define _COG2BLKR_G2BLKR5 0x20
12182 //==============================================================================
12185 //==============================================================================
12188 extern __at(0x0710) __sfr COG2BLKF
;
12194 unsigned BLKF0
: 1;
12195 unsigned BLKF1
: 1;
12196 unsigned BLKF2
: 1;
12197 unsigned BLKF3
: 1;
12198 unsigned BLKF4
: 1;
12199 unsigned BLKF5
: 1;
12206 unsigned G2BLKF0
: 1;
12207 unsigned G2BLKF1
: 1;
12208 unsigned G2BLKF2
: 1;
12209 unsigned G2BLKF3
: 1;
12210 unsigned G2BLKF4
: 1;
12211 unsigned G2BLKF5
: 1;
12224 unsigned G2BLKF
: 6;
12227 } __COG2BLKFbits_t
;
12229 extern __at(0x0710) volatile __COG2BLKFbits_t COG2BLKFbits
;
12231 #define _COG2BLKF_BLKF0 0x01
12232 #define _COG2BLKF_G2BLKF0 0x01
12233 #define _COG2BLKF_BLKF1 0x02
12234 #define _COG2BLKF_G2BLKF1 0x02
12235 #define _COG2BLKF_BLKF2 0x04
12236 #define _COG2BLKF_G2BLKF2 0x04
12237 #define _COG2BLKF_BLKF3 0x08
12238 #define _COG2BLKF_G2BLKF3 0x08
12239 #define _COG2BLKF_BLKF4 0x10
12240 #define _COG2BLKF_G2BLKF4 0x10
12241 #define _COG2BLKF_BLKF5 0x20
12242 #define _COG2BLKF_G2BLKF5 0x20
12244 //==============================================================================
12247 //==============================================================================
12250 extern __at(0x0711) __sfr COG2DBR
;
12268 unsigned G2DBR0
: 1;
12269 unsigned G2DBR1
: 1;
12270 unsigned G2DBR2
: 1;
12271 unsigned G2DBR3
: 1;
12272 unsigned G2DBR4
: 1;
12273 unsigned G2DBR5
: 1;
12280 unsigned G2DBR
: 6;
12291 extern __at(0x0711) volatile __COG2DBRbits_t COG2DBRbits
;
12293 #define _COG2DBR_DBR0 0x01
12294 #define _COG2DBR_G2DBR0 0x01
12295 #define _COG2DBR_DBR1 0x02
12296 #define _COG2DBR_G2DBR1 0x02
12297 #define _COG2DBR_DBR2 0x04
12298 #define _COG2DBR_G2DBR2 0x04
12299 #define _COG2DBR_DBR3 0x08
12300 #define _COG2DBR_G2DBR3 0x08
12301 #define _COG2DBR_DBR4 0x10
12302 #define _COG2DBR_G2DBR4 0x10
12303 #define _COG2DBR_DBR5 0x20
12304 #define _COG2DBR_G2DBR5 0x20
12306 //==============================================================================
12309 //==============================================================================
12312 extern __at(0x0712) __sfr COG2DBF
;
12330 unsigned G2DBF0
: 1;
12331 unsigned G2DBF1
: 1;
12332 unsigned G2DBF2
: 1;
12333 unsigned G2DBF3
: 1;
12334 unsigned G2DBF4
: 1;
12335 unsigned G2DBF5
: 1;
12348 unsigned G2DBF
: 6;
12353 extern __at(0x0712) volatile __COG2DBFbits_t COG2DBFbits
;
12355 #define _COG2DBF_DBF0 0x01
12356 #define _COG2DBF_G2DBF0 0x01
12357 #define _COG2DBF_DBF1 0x02
12358 #define _COG2DBF_G2DBF1 0x02
12359 #define _COG2DBF_DBF2 0x04
12360 #define _COG2DBF_G2DBF2 0x04
12361 #define _COG2DBF_DBF3 0x08
12362 #define _COG2DBF_G2DBF3 0x08
12363 #define _COG2DBF_DBF4 0x10
12364 #define _COG2DBF_G2DBF4 0x10
12365 #define _COG2DBF_DBF5 0x20
12366 #define _COG2DBF_G2DBF5 0x20
12368 //==============================================================================
12371 //==============================================================================
12374 extern __at(0x0713) __sfr COG2CON0
;
12392 unsigned G2MD0
: 1;
12393 unsigned G2MD1
: 1;
12394 unsigned G2MD2
: 1;
12395 unsigned G2CS0
: 1;
12396 unsigned G2CS1
: 1;
12427 } __COG2CON0bits_t
;
12429 extern __at(0x0713) volatile __COG2CON0bits_t COG2CON0bits
;
12431 #define _COG2CON0_MD0 0x01
12432 #define _COG2CON0_G2MD0 0x01
12433 #define _COG2CON0_MD1 0x02
12434 #define _COG2CON0_G2MD1 0x02
12435 #define _COG2CON0_MD2 0x04
12436 #define _COG2CON0_G2MD2 0x04
12437 #define _COG2CON0_CS0 0x08
12438 #define _COG2CON0_G2CS0 0x08
12439 #define _COG2CON0_CS1 0x10
12440 #define _COG2CON0_G2CS1 0x10
12441 #define _COG2CON0_LD 0x40
12442 #define _COG2CON0_G2LD 0x40
12443 #define _COG2CON0_EN 0x80
12444 #define _COG2CON0_G2EN 0x80
12446 //==============================================================================
12449 //==============================================================================
12452 extern __at(0x0714) __sfr COG2CON1
;
12470 unsigned G2POLA
: 1;
12471 unsigned G2POLB
: 1;
12472 unsigned G2POLC
: 1;
12473 unsigned G2POLD
: 1;
12476 unsigned G2FDBS
: 1;
12477 unsigned G2RDBS
: 1;
12479 } __COG2CON1bits_t
;
12481 extern __at(0x0714) volatile __COG2CON1bits_t COG2CON1bits
;
12483 #define _COG2CON1_POLA 0x01
12484 #define _COG2CON1_G2POLA 0x01
12485 #define _COG2CON1_POLB 0x02
12486 #define _COG2CON1_G2POLB 0x02
12487 #define _COG2CON1_POLC 0x04
12488 #define _COG2CON1_G2POLC 0x04
12489 #define _COG2CON1_POLD 0x08
12490 #define _COG2CON1_G2POLD 0x08
12491 #define _COG2CON1_FDBS 0x40
12492 #define _COG2CON1_G2FDBS 0x40
12493 #define _COG2CON1_RDBS 0x80
12494 #define _COG2CON1_G2RDBS 0x80
12496 //==============================================================================
12499 //==============================================================================
12502 extern __at(0x0715) __sfr COG2RIS0
;
12520 unsigned G2RIS0
: 1;
12521 unsigned G2RIS1
: 1;
12522 unsigned G2RIS2
: 1;
12523 unsigned G2RIS3
: 1;
12524 unsigned G2RIS4
: 1;
12525 unsigned G2RIS5
: 1;
12526 unsigned G2RIS6
: 1;
12527 unsigned G2RIS7
: 1;
12529 } __COG2RIS0bits_t
;
12531 extern __at(0x0715) volatile __COG2RIS0bits_t COG2RIS0bits
;
12533 #define _COG2RIS0_RIS0 0x01
12534 #define _COG2RIS0_G2RIS0 0x01
12535 #define _COG2RIS0_RIS1 0x02
12536 #define _COG2RIS0_G2RIS1 0x02
12537 #define _COG2RIS0_RIS2 0x04
12538 #define _COG2RIS0_G2RIS2 0x04
12539 #define _COG2RIS0_RIS3 0x08
12540 #define _COG2RIS0_G2RIS3 0x08
12541 #define _COG2RIS0_RIS4 0x10
12542 #define _COG2RIS0_G2RIS4 0x10
12543 #define _COG2RIS0_RIS5 0x20
12544 #define _COG2RIS0_G2RIS5 0x20
12545 #define _COG2RIS0_RIS6 0x40
12546 #define _COG2RIS0_G2RIS6 0x40
12547 #define _COG2RIS0_RIS7 0x80
12548 #define _COG2RIS0_G2RIS7 0x80
12550 //==============================================================================
12553 //==============================================================================
12556 extern __at(0x0716) __sfr COG2RIS1
;
12564 unsigned RIS10
: 1;
12565 unsigned RIS11
: 1;
12566 unsigned RIS12
: 1;
12567 unsigned RIS13
: 1;
12568 unsigned RIS14
: 1;
12569 unsigned RIS15
: 1;
12574 unsigned G2RIS8
: 1;
12575 unsigned G2RIS9
: 1;
12576 unsigned G2RIS10
: 1;
12577 unsigned G2RIS11
: 1;
12578 unsigned G2RIS12
: 1;
12579 unsigned G2RIS13
: 1;
12580 unsigned G2RIS14
: 1;
12581 unsigned G2RIS15
: 1;
12583 } __COG2RIS1bits_t
;
12585 extern __at(0x0716) volatile __COG2RIS1bits_t COG2RIS1bits
;
12587 #define _COG2RIS1_RIS8 0x01
12588 #define _COG2RIS1_G2RIS8 0x01
12589 #define _COG2RIS1_RIS9 0x02
12590 #define _COG2RIS1_G2RIS9 0x02
12591 #define _COG2RIS1_RIS10 0x04
12592 #define _COG2RIS1_G2RIS10 0x04
12593 #define _COG2RIS1_RIS11 0x08
12594 #define _COG2RIS1_G2RIS11 0x08
12595 #define _COG2RIS1_RIS12 0x10
12596 #define _COG2RIS1_G2RIS12 0x10
12597 #define _COG2RIS1_RIS13 0x20
12598 #define _COG2RIS1_G2RIS13 0x20
12599 #define _COG2RIS1_RIS14 0x40
12600 #define _COG2RIS1_G2RIS14 0x40
12601 #define _COG2RIS1_RIS15 0x80
12602 #define _COG2RIS1_G2RIS15 0x80
12604 //==============================================================================
12607 //==============================================================================
12610 extern __at(0x0717) __sfr COG2RSIM0
;
12616 unsigned RSIM0
: 1;
12617 unsigned RSIM1
: 1;
12618 unsigned RSIM2
: 1;
12619 unsigned RSIM3
: 1;
12620 unsigned RSIM4
: 1;
12621 unsigned RSIM5
: 1;
12622 unsigned RSIM6
: 1;
12623 unsigned RSIM7
: 1;
12628 unsigned G2RSIM0
: 1;
12629 unsigned G2RSIM1
: 1;
12630 unsigned G2RSIM2
: 1;
12631 unsigned G2RSIM3
: 1;
12632 unsigned G2RSIM4
: 1;
12633 unsigned G2RSIM5
: 1;
12634 unsigned G2RSIM6
: 1;
12635 unsigned G2RSIM7
: 1;
12637 } __COG2RSIM0bits_t
;
12639 extern __at(0x0717) volatile __COG2RSIM0bits_t COG2RSIM0bits
;
12641 #define _COG2RSIM0_RSIM0 0x01
12642 #define _COG2RSIM0_G2RSIM0 0x01
12643 #define _COG2RSIM0_RSIM1 0x02
12644 #define _COG2RSIM0_G2RSIM1 0x02
12645 #define _COG2RSIM0_RSIM2 0x04
12646 #define _COG2RSIM0_G2RSIM2 0x04
12647 #define _COG2RSIM0_RSIM3 0x08
12648 #define _COG2RSIM0_G2RSIM3 0x08
12649 #define _COG2RSIM0_RSIM4 0x10
12650 #define _COG2RSIM0_G2RSIM4 0x10
12651 #define _COG2RSIM0_RSIM5 0x20
12652 #define _COG2RSIM0_G2RSIM5 0x20
12653 #define _COG2RSIM0_RSIM6 0x40
12654 #define _COG2RSIM0_G2RSIM6 0x40
12655 #define _COG2RSIM0_RSIM7 0x80
12656 #define _COG2RSIM0_G2RSIM7 0x80
12658 //==============================================================================
12661 //==============================================================================
12664 extern __at(0x0718) __sfr COG2RSIM1
;
12670 unsigned RSIM8
: 1;
12671 unsigned RSIM9
: 1;
12672 unsigned RSIM10
: 1;
12673 unsigned RSIM11
: 1;
12674 unsigned RSIM12
: 1;
12675 unsigned RSIM13
: 1;
12676 unsigned RSIM14
: 1;
12677 unsigned RSIM15
: 1;
12682 unsigned G2RSIM8
: 1;
12683 unsigned G2RSIM9
: 1;
12684 unsigned G2RSIM10
: 1;
12685 unsigned G2RSIM11
: 1;
12686 unsigned G2RSIM12
: 1;
12687 unsigned G2RSIM13
: 1;
12688 unsigned G2RSIM14
: 1;
12689 unsigned G2RSIM15
: 1;
12691 } __COG2RSIM1bits_t
;
12693 extern __at(0x0718) volatile __COG2RSIM1bits_t COG2RSIM1bits
;
12695 #define _COG2RSIM1_RSIM8 0x01
12696 #define _COG2RSIM1_G2RSIM8 0x01
12697 #define _COG2RSIM1_RSIM9 0x02
12698 #define _COG2RSIM1_G2RSIM9 0x02
12699 #define _COG2RSIM1_RSIM10 0x04
12700 #define _COG2RSIM1_G2RSIM10 0x04
12701 #define _COG2RSIM1_RSIM11 0x08
12702 #define _COG2RSIM1_G2RSIM11 0x08
12703 #define _COG2RSIM1_RSIM12 0x10
12704 #define _COG2RSIM1_G2RSIM12 0x10
12705 #define _COG2RSIM1_RSIM13 0x20
12706 #define _COG2RSIM1_G2RSIM13 0x20
12707 #define _COG2RSIM1_RSIM14 0x40
12708 #define _COG2RSIM1_G2RSIM14 0x40
12709 #define _COG2RSIM1_RSIM15 0x80
12710 #define _COG2RSIM1_G2RSIM15 0x80
12712 //==============================================================================
12715 //==============================================================================
12718 extern __at(0x0719) __sfr COG2FIS0
;
12736 unsigned G2FIS0
: 1;
12737 unsigned G2FIS1
: 1;
12738 unsigned G2FIS2
: 1;
12739 unsigned G2FIS3
: 1;
12740 unsigned G2FIS4
: 1;
12741 unsigned G2FIS5
: 1;
12742 unsigned G2FIS6
: 1;
12743 unsigned G2FIS7
: 1;
12745 } __COG2FIS0bits_t
;
12747 extern __at(0x0719) volatile __COG2FIS0bits_t COG2FIS0bits
;
12749 #define _COG2FIS0_FIS0 0x01
12750 #define _COG2FIS0_G2FIS0 0x01
12751 #define _COG2FIS0_FIS1 0x02
12752 #define _COG2FIS0_G2FIS1 0x02
12753 #define _COG2FIS0_FIS2 0x04
12754 #define _COG2FIS0_G2FIS2 0x04
12755 #define _COG2FIS0_FIS3 0x08
12756 #define _COG2FIS0_G2FIS3 0x08
12757 #define _COG2FIS0_FIS4 0x10
12758 #define _COG2FIS0_G2FIS4 0x10
12759 #define _COG2FIS0_FIS5 0x20
12760 #define _COG2FIS0_G2FIS5 0x20
12761 #define _COG2FIS0_FIS6 0x40
12762 #define _COG2FIS0_G2FIS6 0x40
12763 #define _COG2FIS0_FIS7 0x80
12764 #define _COG2FIS0_G2FIS7 0x80
12766 //==============================================================================
12769 //==============================================================================
12772 extern __at(0x071A) __sfr COG2FIS1
;
12780 unsigned FIS10
: 1;
12781 unsigned FIS11
: 1;
12782 unsigned FIS12
: 1;
12783 unsigned FIS13
: 1;
12784 unsigned FIS14
: 1;
12785 unsigned FIS15
: 1;
12790 unsigned G2FIS8
: 1;
12791 unsigned G2FIS9
: 1;
12792 unsigned G2FIS10
: 1;
12793 unsigned G2FIS11
: 1;
12794 unsigned G2FIS12
: 1;
12795 unsigned G2FIS13
: 1;
12796 unsigned G2FIS14
: 1;
12797 unsigned G2FIS15
: 1;
12799 } __COG2FIS1bits_t
;
12801 extern __at(0x071A) volatile __COG2FIS1bits_t COG2FIS1bits
;
12803 #define _COG2FIS1_FIS8 0x01
12804 #define _COG2FIS1_G2FIS8 0x01
12805 #define _COG2FIS1_FIS9 0x02
12806 #define _COG2FIS1_G2FIS9 0x02
12807 #define _COG2FIS1_FIS10 0x04
12808 #define _COG2FIS1_G2FIS10 0x04
12809 #define _COG2FIS1_FIS11 0x08
12810 #define _COG2FIS1_G2FIS11 0x08
12811 #define _COG2FIS1_FIS12 0x10
12812 #define _COG2FIS1_G2FIS12 0x10
12813 #define _COG2FIS1_FIS13 0x20
12814 #define _COG2FIS1_G2FIS13 0x20
12815 #define _COG2FIS1_FIS14 0x40
12816 #define _COG2FIS1_G2FIS14 0x40
12817 #define _COG2FIS1_FIS15 0x80
12818 #define _COG2FIS1_G2FIS15 0x80
12820 //==============================================================================
12823 //==============================================================================
12826 extern __at(0x071B) __sfr COG2FSIM0
;
12832 unsigned FSIM0
: 1;
12833 unsigned FSIM1
: 1;
12834 unsigned FSIM2
: 1;
12835 unsigned FSIM3
: 1;
12836 unsigned FSIM4
: 1;
12837 unsigned FSIM5
: 1;
12838 unsigned FSIM6
: 1;
12839 unsigned FSIM7
: 1;
12844 unsigned G2FSIM0
: 1;
12845 unsigned G2FSIM1
: 1;
12846 unsigned G2FSIM2
: 1;
12847 unsigned G2FSIM3
: 1;
12848 unsigned G2FSIM4
: 1;
12849 unsigned G2FSIM5
: 1;
12850 unsigned G2FSIM6
: 1;
12851 unsigned G2FSIM7
: 1;
12853 } __COG2FSIM0bits_t
;
12855 extern __at(0x071B) volatile __COG2FSIM0bits_t COG2FSIM0bits
;
12857 #define _COG2FSIM0_FSIM0 0x01
12858 #define _COG2FSIM0_G2FSIM0 0x01
12859 #define _COG2FSIM0_FSIM1 0x02
12860 #define _COG2FSIM0_G2FSIM1 0x02
12861 #define _COG2FSIM0_FSIM2 0x04
12862 #define _COG2FSIM0_G2FSIM2 0x04
12863 #define _COG2FSIM0_FSIM3 0x08
12864 #define _COG2FSIM0_G2FSIM3 0x08
12865 #define _COG2FSIM0_FSIM4 0x10
12866 #define _COG2FSIM0_G2FSIM4 0x10
12867 #define _COG2FSIM0_FSIM5 0x20
12868 #define _COG2FSIM0_G2FSIM5 0x20
12869 #define _COG2FSIM0_FSIM6 0x40
12870 #define _COG2FSIM0_G2FSIM6 0x40
12871 #define _COG2FSIM0_FSIM7 0x80
12872 #define _COG2FSIM0_G2FSIM7 0x80
12874 //==============================================================================
12877 //==============================================================================
12880 extern __at(0x071C) __sfr COG2FSIM1
;
12886 unsigned FSIM8
: 1;
12887 unsigned FSIM9
: 1;
12888 unsigned FSIM10
: 1;
12889 unsigned FSIM11
: 1;
12890 unsigned FSIM12
: 1;
12891 unsigned FSIM13
: 1;
12892 unsigned FSIM14
: 1;
12893 unsigned FSIM15
: 1;
12898 unsigned G2FSIM8
: 1;
12899 unsigned G2FSIM9
: 1;
12900 unsigned G2FSIM10
: 1;
12901 unsigned G2FSIM11
: 1;
12902 unsigned G2FSIM12
: 1;
12903 unsigned G2FSIM13
: 1;
12904 unsigned G2FSIM14
: 1;
12905 unsigned G2FSIM15
: 1;
12907 } __COG2FSIM1bits_t
;
12909 extern __at(0x071C) volatile __COG2FSIM1bits_t COG2FSIM1bits
;
12911 #define _COG2FSIM1_FSIM8 0x01
12912 #define _COG2FSIM1_G2FSIM8 0x01
12913 #define _COG2FSIM1_FSIM9 0x02
12914 #define _COG2FSIM1_G2FSIM9 0x02
12915 #define _COG2FSIM1_FSIM10 0x04
12916 #define _COG2FSIM1_G2FSIM10 0x04
12917 #define _COG2FSIM1_FSIM11 0x08
12918 #define _COG2FSIM1_G2FSIM11 0x08
12919 #define _COG2FSIM1_FSIM12 0x10
12920 #define _COG2FSIM1_G2FSIM12 0x10
12921 #define _COG2FSIM1_FSIM13 0x20
12922 #define _COG2FSIM1_G2FSIM13 0x20
12923 #define _COG2FSIM1_FSIM14 0x40
12924 #define _COG2FSIM1_G2FSIM14 0x40
12925 #define _COG2FSIM1_FSIM15 0x80
12926 #define _COG2FSIM1_G2FSIM15 0x80
12928 //==============================================================================
12931 //==============================================================================
12934 extern __at(0x071D) __sfr COG2ASD0
;
12942 unsigned ASDAC0
: 1;
12943 unsigned ASDAC1
: 1;
12944 unsigned ASDBD0
: 1;
12945 unsigned ASDBD1
: 1;
12946 unsigned ASREN
: 1;
12954 unsigned G2ASDAC0
: 1;
12955 unsigned G2ASDAC1
: 1;
12956 unsigned G2ASDBD0
: 1;
12957 unsigned G2ASDBD1
: 1;
12958 unsigned ARSEN
: 1;
12959 unsigned G2ASE
: 1;
12970 unsigned G2ARSEN
: 1;
12982 unsigned G2ASREN
: 1;
12989 unsigned G2ASDAC
: 2;
12996 unsigned ASDAC
: 2;
13003 unsigned G2ASDBD
: 2;
13010 unsigned ASDBD
: 2;
13013 } __COG2ASD0bits_t
;
13015 extern __at(0x071D) volatile __COG2ASD0bits_t COG2ASD0bits
;
13017 #define _COG2ASD0_ASDAC0 0x04
13018 #define _COG2ASD0_G2ASDAC0 0x04
13019 #define _COG2ASD0_ASDAC1 0x08
13020 #define _COG2ASD0_G2ASDAC1 0x08
13021 #define _COG2ASD0_ASDBD0 0x10
13022 #define _COG2ASD0_G2ASDBD0 0x10
13023 #define _COG2ASD0_ASDBD1 0x20
13024 #define _COG2ASD0_G2ASDBD1 0x20
13025 #define _COG2ASD0_ASREN 0x40
13026 #define _COG2ASD0_ARSEN 0x40
13027 #define _COG2ASD0_G2ARSEN 0x40
13028 #define _COG2ASD0_G2ASREN 0x40
13029 #define _COG2ASD0_ASE 0x80
13030 #define _COG2ASD0_G2ASE 0x80
13032 //==============================================================================
13035 //==============================================================================
13038 extern __at(0x071E) __sfr COG2ASD1
;
13056 unsigned G2AS0E
: 1;
13057 unsigned G2AS1E
: 1;
13058 unsigned G2AS2E
: 1;
13059 unsigned G2AS3E
: 1;
13060 unsigned G2AS4E
: 1;
13061 unsigned G2AS5E
: 1;
13062 unsigned G2AS6E
: 1;
13063 unsigned G2AS7E
: 1;
13065 } __COG2ASD1bits_t
;
13067 extern __at(0x071E) volatile __COG2ASD1bits_t COG2ASD1bits
;
13069 #define _COG2ASD1_AS0E 0x01
13070 #define _COG2ASD1_G2AS0E 0x01
13071 #define _COG2ASD1_AS1E 0x02
13072 #define _COG2ASD1_G2AS1E 0x02
13073 #define _COG2ASD1_AS2E 0x04
13074 #define _COG2ASD1_G2AS2E 0x04
13075 #define _COG2ASD1_AS3E 0x08
13076 #define _COG2ASD1_G2AS3E 0x08
13077 #define _COG2ASD1_AS4E 0x10
13078 #define _COG2ASD1_G2AS4E 0x10
13079 #define _COG2ASD1_AS5E 0x20
13080 #define _COG2ASD1_G2AS5E 0x20
13081 #define _COG2ASD1_AS6E 0x40
13082 #define _COG2ASD1_G2AS6E 0x40
13083 #define _COG2ASD1_AS7E 0x80
13084 #define _COG2ASD1_G2AS7E 0x80
13086 //==============================================================================
13089 //==============================================================================
13092 extern __at(0x071F) __sfr COG2STR
;
13102 unsigned SDATA
: 1;
13103 unsigned SDATB
: 1;
13104 unsigned SDATC
: 1;
13105 unsigned SDATD
: 1;
13110 unsigned G2STRA
: 1;
13111 unsigned G2STRB
: 1;
13112 unsigned G2STRC
: 1;
13113 unsigned G2STRD
: 1;
13114 unsigned G2SDATA
: 1;
13115 unsigned G2SDATB
: 1;
13116 unsigned G2SDATC
: 1;
13117 unsigned G2SDATD
: 1;
13121 extern __at(0x071F) volatile __COG2STRbits_t COG2STRbits
;
13123 #define _COG2STR_STRA 0x01
13124 #define _COG2STR_G2STRA 0x01
13125 #define _COG2STR_STRB 0x02
13126 #define _COG2STR_G2STRB 0x02
13127 #define _COG2STR_STRC 0x04
13128 #define _COG2STR_G2STRC 0x04
13129 #define _COG2STR_STRD 0x08
13130 #define _COG2STR_G2STRD 0x08
13131 #define _COG2STR_SDATA 0x10
13132 #define _COG2STR_G2SDATA 0x10
13133 #define _COG2STR_SDATB 0x20
13134 #define _COG2STR_G2SDATB 0x20
13135 #define _COG2STR_SDATC 0x40
13136 #define _COG2STR_G2SDATC 0x40
13137 #define _COG2STR_SDATD 0x80
13138 #define _COG2STR_G2SDATD 0x80
13140 //==============================================================================
13143 //==============================================================================
13146 extern __at(0x078E) __sfr PRG1RTSS
;
13152 unsigned RTSS0
: 1;
13153 unsigned RTSS1
: 1;
13154 unsigned RTSS2
: 1;
13155 unsigned RTSS3
: 1;
13164 unsigned RG1RTSS0
: 1;
13165 unsigned RG1RTSS1
: 1;
13166 unsigned RG1RTSS2
: 1;
13167 unsigned RG1RTSS3
: 1;
13176 unsigned RG1RTSS
: 4;
13185 } __PRG1RTSSbits_t
;
13187 extern __at(0x078E) volatile __PRG1RTSSbits_t PRG1RTSSbits
;
13189 #define _RTSS0 0x01
13190 #define _RG1RTSS0 0x01
13191 #define _RTSS1 0x02
13192 #define _RG1RTSS1 0x02
13193 #define _RTSS2 0x04
13194 #define _RG1RTSS2 0x04
13195 #define _RTSS3 0x08
13196 #define _RG1RTSS3 0x08
13198 //==============================================================================
13201 //==============================================================================
13204 extern __at(0x078F) __sfr PRG1FTSS
;
13210 unsigned FTSS0
: 1;
13211 unsigned FTSS1
: 1;
13212 unsigned FTSS2
: 1;
13213 unsigned FTSS3
: 1;
13222 unsigned RG1FTSS0
: 1;
13223 unsigned RG1FTSS1
: 1;
13224 unsigned RG1FTSS2
: 1;
13225 unsigned RG1FTSS3
: 1;
13234 unsigned RG1FTSS
: 4;
13243 } __PRG1FTSSbits_t
;
13245 extern __at(0x078F) volatile __PRG1FTSSbits_t PRG1FTSSbits
;
13247 #define _FTSS0 0x01
13248 #define _RG1FTSS0 0x01
13249 #define _FTSS1 0x02
13250 #define _RG1FTSS1 0x02
13251 #define _FTSS2 0x04
13252 #define _RG1FTSS2 0x04
13253 #define _FTSS3 0x08
13254 #define _RG1FTSS3 0x08
13256 //==============================================================================
13259 //==============================================================================
13262 extern __at(0x0790) __sfr PRG1INS
;
13280 unsigned RG1INS0
: 1;
13281 unsigned RG1INS1
: 1;
13282 unsigned RG1INS2
: 1;
13283 unsigned RG1INS3
: 1;
13292 unsigned RG1INS
: 4;
13303 extern __at(0x0790) volatile __PRG1INSbits_t PRG1INSbits
;
13306 #define _RG1INS0 0x01
13308 #define _RG1INS1 0x02
13310 #define _RG1INS2 0x04
13312 #define _RG1INS3 0x08
13314 //==============================================================================
13317 //==============================================================================
13320 extern __at(0x0791) __sfr PRG1CON0
;
13328 unsigned MODE0
: 1;
13329 unsigned MODE1
: 1;
13338 unsigned RG1GO
: 1;
13339 unsigned RG1OS
: 1;
13340 unsigned RG1MODE0
: 1;
13341 unsigned RG1MODE1
: 1;
13342 unsigned RG1REDG
: 1;
13343 unsigned RG1FEDG
: 1;
13345 unsigned RG1EN
: 1;
13358 unsigned RG1MODE
: 2;
13361 } __PRG1CON0bits_t
;
13363 extern __at(0x0791) volatile __PRG1CON0bits_t PRG1CON0bits
;
13365 #define _PRG1CON0_GO 0x01
13366 #define _PRG1CON0_RG1GO 0x01
13367 #define _PRG1CON0_OS 0x02
13368 #define _PRG1CON0_RG1OS 0x02
13369 #define _PRG1CON0_MODE0 0x04
13370 #define _PRG1CON0_RG1MODE0 0x04
13371 #define _PRG1CON0_MODE1 0x08
13372 #define _PRG1CON0_RG1MODE1 0x08
13373 #define _PRG1CON0_REDG 0x10
13374 #define _PRG1CON0_RG1REDG 0x10
13375 #define _PRG1CON0_FEDG 0x20
13376 #define _PRG1CON0_RG1FEDG 0x20
13377 #define _PRG1CON0_EN 0x80
13378 #define _PRG1CON0_RG1EN 0x80
13380 //==============================================================================
13383 //==============================================================================
13386 extern __at(0x0792) __sfr PRG1CON1
;
13404 unsigned RG1RPOL
: 1;
13405 unsigned RG1FPOL
: 1;
13406 unsigned RG1RDY
: 1;
13413 } __PRG1CON1bits_t
;
13415 extern __at(0x0792) volatile __PRG1CON1bits_t PRG1CON1bits
;
13418 #define _RG1RPOL 0x01
13420 #define _RG1FPOL 0x02
13422 #define _RG1RDY 0x04
13424 //==============================================================================
13427 //==============================================================================
13430 extern __at(0x0793) __sfr PRG1CON2
;
13436 unsigned ISET0
: 1;
13437 unsigned ISET1
: 1;
13438 unsigned ISET2
: 1;
13439 unsigned ISET3
: 1;
13440 unsigned ISET4
: 1;
13448 unsigned RG1ISET0
: 1;
13449 unsigned RG1ISET1
: 1;
13450 unsigned RG1ISET2
: 1;
13451 unsigned RG1ISET3
: 1;
13452 unsigned RG1ISET4
: 1;
13466 unsigned RG1ISET
: 5;
13469 } __PRG1CON2bits_t
;
13471 extern __at(0x0793) volatile __PRG1CON2bits_t PRG1CON2bits
;
13473 #define _ISET0 0x01
13474 #define _RG1ISET0 0x01
13475 #define _ISET1 0x02
13476 #define _RG1ISET1 0x02
13477 #define _ISET2 0x04
13478 #define _RG1ISET2 0x04
13479 #define _ISET3 0x08
13480 #define _RG1ISET3 0x08
13481 #define _ISET4 0x10
13482 #define _RG1ISET4 0x10
13484 //==============================================================================
13487 //==============================================================================
13490 extern __at(0x0794) __sfr PRG2RTSS
;
13496 unsigned RTSS0
: 1;
13497 unsigned RTSS1
: 1;
13498 unsigned RTSS2
: 1;
13499 unsigned RTSS3
: 1;
13508 unsigned RG2RTSS0
: 1;
13509 unsigned RG2RTSS1
: 1;
13510 unsigned RG2RTSS2
: 1;
13511 unsigned RG2RTSS3
: 1;
13520 unsigned RG2RTSS
: 4;
13529 } __PRG2RTSSbits_t
;
13531 extern __at(0x0794) volatile __PRG2RTSSbits_t PRG2RTSSbits
;
13533 #define _PRG2RTSS_RTSS0 0x01
13534 #define _PRG2RTSS_RG2RTSS0 0x01
13535 #define _PRG2RTSS_RTSS1 0x02
13536 #define _PRG2RTSS_RG2RTSS1 0x02
13537 #define _PRG2RTSS_RTSS2 0x04
13538 #define _PRG2RTSS_RG2RTSS2 0x04
13539 #define _PRG2RTSS_RTSS3 0x08
13540 #define _PRG2RTSS_RG2RTSS3 0x08
13542 //==============================================================================
13545 //==============================================================================
13548 extern __at(0x0795) __sfr PRG2FTSS
;
13554 unsigned FTSS0
: 1;
13555 unsigned FTSS1
: 1;
13556 unsigned FTSS2
: 1;
13557 unsigned FTSS3
: 1;
13566 unsigned RG2FTSS0
: 1;
13567 unsigned RG2FTSS1
: 1;
13568 unsigned RG2FTSS2
: 1;
13569 unsigned RG2FTSS3
: 1;
13584 unsigned RG2FTSS
: 4;
13587 } __PRG2FTSSbits_t
;
13589 extern __at(0x0795) volatile __PRG2FTSSbits_t PRG2FTSSbits
;
13591 #define _PRG2FTSS_FTSS0 0x01
13592 #define _PRG2FTSS_RG2FTSS0 0x01
13593 #define _PRG2FTSS_FTSS1 0x02
13594 #define _PRG2FTSS_RG2FTSS1 0x02
13595 #define _PRG2FTSS_FTSS2 0x04
13596 #define _PRG2FTSS_RG2FTSS2 0x04
13597 #define _PRG2FTSS_FTSS3 0x08
13598 #define _PRG2FTSS_RG2FTSS3 0x08
13600 //==============================================================================
13603 //==============================================================================
13606 extern __at(0x0796) __sfr PRG2INS
;
13624 unsigned RG2INS0
: 1;
13625 unsigned RG2INS1
: 1;
13626 unsigned RG2INS2
: 1;
13627 unsigned RG2INS3
: 1;
13636 unsigned RG2INS
: 4;
13647 extern __at(0x0796) volatile __PRG2INSbits_t PRG2INSbits
;
13649 #define _PRG2INS_INS0 0x01
13650 #define _PRG2INS_RG2INS0 0x01
13651 #define _PRG2INS_INS1 0x02
13652 #define _PRG2INS_RG2INS1 0x02
13653 #define _PRG2INS_INS2 0x04
13654 #define _PRG2INS_RG2INS2 0x04
13655 #define _PRG2INS_INS3 0x08
13656 #define _PRG2INS_RG2INS3 0x08
13658 //==============================================================================
13661 //==============================================================================
13664 extern __at(0x0797) __sfr PRG2CON0
;
13672 unsigned MODE0
: 1;
13673 unsigned MODE1
: 1;
13682 unsigned RG2GO
: 1;
13683 unsigned RG2OS
: 1;
13684 unsigned RG2MODE0
: 1;
13685 unsigned RG2MODE1
: 1;
13686 unsigned RG2REDG
: 1;
13687 unsigned RG2FEDG
: 1;
13689 unsigned RG2EN
: 1;
13702 unsigned RG2MODE
: 2;
13705 } __PRG2CON0bits_t
;
13707 extern __at(0x0797) volatile __PRG2CON0bits_t PRG2CON0bits
;
13709 #define _PRG2CON0_GO 0x01
13710 #define _PRG2CON0_RG2GO 0x01
13711 #define _PRG2CON0_OS 0x02
13712 #define _PRG2CON0_RG2OS 0x02
13713 #define _PRG2CON0_MODE0 0x04
13714 #define _PRG2CON0_RG2MODE0 0x04
13715 #define _PRG2CON0_MODE1 0x08
13716 #define _PRG2CON0_RG2MODE1 0x08
13717 #define _PRG2CON0_REDG 0x10
13718 #define _PRG2CON0_RG2REDG 0x10
13719 #define _PRG2CON0_FEDG 0x20
13720 #define _PRG2CON0_RG2FEDG 0x20
13721 #define _PRG2CON0_EN 0x80
13722 #define _PRG2CON0_RG2EN 0x80
13724 //==============================================================================
13727 //==============================================================================
13730 extern __at(0x0798) __sfr PRG2CON1
;
13748 unsigned RG2RPOL
: 1;
13749 unsigned RG2FPOL
: 1;
13750 unsigned RG2RDY
: 1;
13757 } __PRG2CON1bits_t
;
13759 extern __at(0x0798) volatile __PRG2CON1bits_t PRG2CON1bits
;
13761 #define _PRG2CON1_RPOL 0x01
13762 #define _PRG2CON1_RG2RPOL 0x01
13763 #define _PRG2CON1_FPOL 0x02
13764 #define _PRG2CON1_RG2FPOL 0x02
13765 #define _PRG2CON1_RDY 0x04
13766 #define _PRG2CON1_RG2RDY 0x04
13768 //==============================================================================
13771 //==============================================================================
13774 extern __at(0x0799) __sfr PRG2CON2
;
13780 unsigned ISET0
: 1;
13781 unsigned ISET1
: 1;
13782 unsigned ISET2
: 1;
13783 unsigned ISET3
: 1;
13784 unsigned ISET4
: 1;
13792 unsigned RG2ISET0
: 1;
13793 unsigned RG2ISET1
: 1;
13794 unsigned RG2ISET2
: 1;
13795 unsigned RG2ISET3
: 1;
13796 unsigned RG2ISET4
: 1;
13810 unsigned RG2ISET
: 5;
13813 } __PRG2CON2bits_t
;
13815 extern __at(0x0799) volatile __PRG2CON2bits_t PRG2CON2bits
;
13817 #define _PRG2CON2_ISET0 0x01
13818 #define _PRG2CON2_RG2ISET0 0x01
13819 #define _PRG2CON2_ISET1 0x02
13820 #define _PRG2CON2_RG2ISET1 0x02
13821 #define _PRG2CON2_ISET2 0x04
13822 #define _PRG2CON2_RG2ISET2 0x04
13823 #define _PRG2CON2_ISET3 0x08
13824 #define _PRG2CON2_RG2ISET3 0x08
13825 #define _PRG2CON2_ISET4 0x10
13826 #define _PRG2CON2_RG2ISET4 0x10
13828 //==============================================================================
13831 //==============================================================================
13834 extern __at(0x079A) __sfr PRG3RTSS
;
13840 unsigned RTSS0
: 1;
13841 unsigned RTSS1
: 1;
13842 unsigned RTSS2
: 1;
13843 unsigned RTSS3
: 1;
13852 unsigned RG3RTSS0
: 1;
13853 unsigned RG3RTSS1
: 1;
13854 unsigned RG3RTSS2
: 1;
13855 unsigned RG3RTSS3
: 1;
13870 unsigned RG3RTSS
: 4;
13873 } __PRG3RTSSbits_t
;
13875 extern __at(0x079A) volatile __PRG3RTSSbits_t PRG3RTSSbits
;
13877 #define _PRG3RTSS_RTSS0 0x01
13878 #define _PRG3RTSS_RG3RTSS0 0x01
13879 #define _PRG3RTSS_RTSS1 0x02
13880 #define _PRG3RTSS_RG3RTSS1 0x02
13881 #define _PRG3RTSS_RTSS2 0x04
13882 #define _PRG3RTSS_RG3RTSS2 0x04
13883 #define _PRG3RTSS_RTSS3 0x08
13884 #define _PRG3RTSS_RG3RTSS3 0x08
13886 //==============================================================================
13889 //==============================================================================
13892 extern __at(0x079B) __sfr PRG3FTSS
;
13898 unsigned FTSS0
: 1;
13899 unsigned FTSS1
: 1;
13900 unsigned FTSS2
: 1;
13901 unsigned FTSS3
: 1;
13910 unsigned RG3FTSS0
: 1;
13911 unsigned RG3FTSS1
: 1;
13912 unsigned RG3FTSS2
: 1;
13913 unsigned RG3FTSS3
: 1;
13922 unsigned RG3FTSS
: 4;
13931 } __PRG3FTSSbits_t
;
13933 extern __at(0x079B) volatile __PRG3FTSSbits_t PRG3FTSSbits
;
13935 #define _PRG3FTSS_FTSS0 0x01
13936 #define _PRG3FTSS_RG3FTSS0 0x01
13937 #define _PRG3FTSS_FTSS1 0x02
13938 #define _PRG3FTSS_RG3FTSS1 0x02
13939 #define _PRG3FTSS_FTSS2 0x04
13940 #define _PRG3FTSS_RG3FTSS2 0x04
13941 #define _PRG3FTSS_FTSS3 0x08
13942 #define _PRG3FTSS_RG3FTSS3 0x08
13944 //==============================================================================
13947 //==============================================================================
13950 extern __at(0x079C) __sfr PRG3INS
;
13968 unsigned RG3INS0
: 1;
13969 unsigned RG3INS1
: 1;
13970 unsigned RG3INS2
: 1;
13971 unsigned RG3INS3
: 1;
13980 unsigned RG3INS
: 4;
13991 extern __at(0x079C) volatile __PRG3INSbits_t PRG3INSbits
;
13993 #define _PRG3INS_INS0 0x01
13994 #define _PRG3INS_RG3INS0 0x01
13995 #define _PRG3INS_INS1 0x02
13996 #define _PRG3INS_RG3INS1 0x02
13997 #define _PRG3INS_INS2 0x04
13998 #define _PRG3INS_RG3INS2 0x04
13999 #define _PRG3INS_INS3 0x08
14000 #define _PRG3INS_RG3INS3 0x08
14002 //==============================================================================
14005 //==============================================================================
14008 extern __at(0x079D) __sfr PRG3CON0
;
14016 unsigned MODE0
: 1;
14017 unsigned MODE1
: 1;
14026 unsigned RG3GO
: 1;
14027 unsigned RG3OS
: 1;
14028 unsigned RG3MODE0
: 1;
14029 unsigned RG3MODE1
: 1;
14030 unsigned RG3REDG
: 1;
14031 unsigned RG3FEDG
: 1;
14033 unsigned RG3EN
: 1;
14039 unsigned RG3MODE
: 2;
14049 } __PRG3CON0bits_t
;
14051 extern __at(0x079D) volatile __PRG3CON0bits_t PRG3CON0bits
;
14053 #define _PRG3CON0_GO 0x01
14054 #define _PRG3CON0_RG3GO 0x01
14055 #define _PRG3CON0_OS 0x02
14056 #define _PRG3CON0_RG3OS 0x02
14057 #define _PRG3CON0_MODE0 0x04
14058 #define _PRG3CON0_RG3MODE0 0x04
14059 #define _PRG3CON0_MODE1 0x08
14060 #define _PRG3CON0_RG3MODE1 0x08
14061 #define _PRG3CON0_REDG 0x10
14062 #define _PRG3CON0_RG3REDG 0x10
14063 #define _PRG3CON0_FEDG 0x20
14064 #define _PRG3CON0_RG3FEDG 0x20
14065 #define _PRG3CON0_EN 0x80
14066 #define _PRG3CON0_RG3EN 0x80
14068 //==============================================================================
14071 //==============================================================================
14074 extern __at(0x079E) __sfr PRG3CON1
;
14092 unsigned RG3RPOL
: 1;
14093 unsigned RG3FPOL
: 1;
14094 unsigned RG3RDY
: 1;
14101 } __PRG3CON1bits_t
;
14103 extern __at(0x079E) volatile __PRG3CON1bits_t PRG3CON1bits
;
14105 #define _PRG3CON1_RPOL 0x01
14106 #define _PRG3CON1_RG3RPOL 0x01
14107 #define _PRG3CON1_FPOL 0x02
14108 #define _PRG3CON1_RG3FPOL 0x02
14109 #define _PRG3CON1_RDY 0x04
14110 #define _PRG3CON1_RG3RDY 0x04
14112 //==============================================================================
14115 //==============================================================================
14118 extern __at(0x079F) __sfr PRG3CON2
;
14124 unsigned ISET0
: 1;
14125 unsigned ISET1
: 1;
14126 unsigned ISET2
: 1;
14127 unsigned ISET3
: 1;
14128 unsigned ISET4
: 1;
14136 unsigned RG3ISET0
: 1;
14137 unsigned RG3ISET1
: 1;
14138 unsigned RG3ISET2
: 1;
14139 unsigned RG3ISET3
: 1;
14140 unsigned RG3ISET4
: 1;
14154 unsigned RG3ISET
: 5;
14157 } __PRG3CON2bits_t
;
14159 extern __at(0x079F) volatile __PRG3CON2bits_t PRG3CON2bits
;
14161 #define _PRG3CON2_ISET0 0x01
14162 #define _PRG3CON2_RG3ISET0 0x01
14163 #define _PRG3CON2_ISET1 0x02
14164 #define _PRG3CON2_RG3ISET1 0x02
14165 #define _PRG3CON2_ISET2 0x04
14166 #define _PRG3CON2_RG3ISET2 0x04
14167 #define _PRG3CON2_ISET3 0x08
14168 #define _PRG3CON2_RG3ISET3 0x08
14169 #define _PRG3CON2_ISET4 0x10
14170 #define _PRG3CON2_RG3ISET4 0x10
14172 //==============================================================================
14175 //==============================================================================
14178 extern __at(0x080D) __sfr COG3PHR
;
14196 unsigned G3PHR0
: 1;
14197 unsigned G3PHR1
: 1;
14198 unsigned G3PHR2
: 1;
14199 unsigned G3PHR3
: 1;
14200 unsigned G3PHR4
: 1;
14201 unsigned G3PHR5
: 1;
14214 unsigned G3PHR
: 6;
14219 extern __at(0x080D) volatile __COG3PHRbits_t COG3PHRbits
;
14221 #define _COG3PHR_PHR0 0x01
14222 #define _COG3PHR_G3PHR0 0x01
14223 #define _COG3PHR_PHR1 0x02
14224 #define _COG3PHR_G3PHR1 0x02
14225 #define _COG3PHR_PHR2 0x04
14226 #define _COG3PHR_G3PHR2 0x04
14227 #define _COG3PHR_PHR3 0x08
14228 #define _COG3PHR_G3PHR3 0x08
14229 #define _COG3PHR_PHR4 0x10
14230 #define _COG3PHR_G3PHR4 0x10
14231 #define _COG3PHR_PHR5 0x20
14232 #define _COG3PHR_G3PHR5 0x20
14234 //==============================================================================
14237 //==============================================================================
14240 extern __at(0x080E) __sfr COG3PHF
;
14258 unsigned G3PHF0
: 1;
14259 unsigned G3PHF1
: 1;
14260 unsigned G3PHF2
: 1;
14261 unsigned G3PHF3
: 1;
14262 unsigned G3PHF4
: 1;
14263 unsigned G3PHF5
: 1;
14270 unsigned G3PHF
: 6;
14281 extern __at(0x080E) volatile __COG3PHFbits_t COG3PHFbits
;
14283 #define _COG3PHF_PHF0 0x01
14284 #define _COG3PHF_G3PHF0 0x01
14285 #define _COG3PHF_PHF1 0x02
14286 #define _COG3PHF_G3PHF1 0x02
14287 #define _COG3PHF_PHF2 0x04
14288 #define _COG3PHF_G3PHF2 0x04
14289 #define _COG3PHF_PHF3 0x08
14290 #define _COG3PHF_G3PHF3 0x08
14291 #define _COG3PHF_PHF4 0x10
14292 #define _COG3PHF_G3PHF4 0x10
14293 #define _COG3PHF_PHF5 0x20
14294 #define _COG3PHF_G3PHF5 0x20
14296 //==============================================================================
14299 //==============================================================================
14302 extern __at(0x080F) __sfr COG3BLKR
;
14308 unsigned BLKR0
: 1;
14309 unsigned BLKR1
: 1;
14310 unsigned BLKR2
: 1;
14311 unsigned BLKR3
: 1;
14312 unsigned BLKR4
: 1;
14313 unsigned BLKR5
: 1;
14320 unsigned G3BLKR0
: 1;
14321 unsigned G3BLKR1
: 1;
14322 unsigned G3BLKR2
: 1;
14323 unsigned G3BLKR3
: 1;
14324 unsigned G3BLKR4
: 1;
14325 unsigned G3BLKR5
: 1;
14338 unsigned G3BLKR
: 6;
14341 } __COG3BLKRbits_t
;
14343 extern __at(0x080F) volatile __COG3BLKRbits_t COG3BLKRbits
;
14345 #define _COG3BLKR_BLKR0 0x01
14346 #define _COG3BLKR_G3BLKR0 0x01
14347 #define _COG3BLKR_BLKR1 0x02
14348 #define _COG3BLKR_G3BLKR1 0x02
14349 #define _COG3BLKR_BLKR2 0x04
14350 #define _COG3BLKR_G3BLKR2 0x04
14351 #define _COG3BLKR_BLKR3 0x08
14352 #define _COG3BLKR_G3BLKR3 0x08
14353 #define _COG3BLKR_BLKR4 0x10
14354 #define _COG3BLKR_G3BLKR4 0x10
14355 #define _COG3BLKR_BLKR5 0x20
14356 #define _COG3BLKR_G3BLKR5 0x20
14358 //==============================================================================
14361 //==============================================================================
14364 extern __at(0x0810) __sfr COG3BLKF
;
14370 unsigned BLKF0
: 1;
14371 unsigned BLKF1
: 1;
14372 unsigned BLKF2
: 1;
14373 unsigned BLKF3
: 1;
14374 unsigned BLKF4
: 1;
14375 unsigned BLKF5
: 1;
14382 unsigned G3BLKF0
: 1;
14383 unsigned G3BLKF1
: 1;
14384 unsigned G3BLKF2
: 1;
14385 unsigned G3BLKF3
: 1;
14386 unsigned G3BLKF4
: 1;
14387 unsigned G3BLKF5
: 1;
14394 unsigned G3BLKF
: 6;
14403 } __COG3BLKFbits_t
;
14405 extern __at(0x0810) volatile __COG3BLKFbits_t COG3BLKFbits
;
14407 #define _COG3BLKF_BLKF0 0x01
14408 #define _COG3BLKF_G3BLKF0 0x01
14409 #define _COG3BLKF_BLKF1 0x02
14410 #define _COG3BLKF_G3BLKF1 0x02
14411 #define _COG3BLKF_BLKF2 0x04
14412 #define _COG3BLKF_G3BLKF2 0x04
14413 #define _COG3BLKF_BLKF3 0x08
14414 #define _COG3BLKF_G3BLKF3 0x08
14415 #define _COG3BLKF_BLKF4 0x10
14416 #define _COG3BLKF_G3BLKF4 0x10
14417 #define _COG3BLKF_BLKF5 0x20
14418 #define _COG3BLKF_G3BLKF5 0x20
14420 //==============================================================================
14423 //==============================================================================
14426 extern __at(0x0811) __sfr COG3DBR
;
14444 unsigned G3DBR0
: 1;
14445 unsigned G3DBR1
: 1;
14446 unsigned G3DBR2
: 1;
14447 unsigned G3DBR3
: 1;
14448 unsigned G3DBR4
: 1;
14449 unsigned G3DBR5
: 1;
14462 unsigned G3DBR
: 6;
14467 extern __at(0x0811) volatile __COG3DBRbits_t COG3DBRbits
;
14469 #define _COG3DBR_DBR0 0x01
14470 #define _COG3DBR_G3DBR0 0x01
14471 #define _COG3DBR_DBR1 0x02
14472 #define _COG3DBR_G3DBR1 0x02
14473 #define _COG3DBR_DBR2 0x04
14474 #define _COG3DBR_G3DBR2 0x04
14475 #define _COG3DBR_DBR3 0x08
14476 #define _COG3DBR_G3DBR3 0x08
14477 #define _COG3DBR_DBR4 0x10
14478 #define _COG3DBR_G3DBR4 0x10
14479 #define _COG3DBR_DBR5 0x20
14480 #define _COG3DBR_G3DBR5 0x20
14482 //==============================================================================
14485 //==============================================================================
14488 extern __at(0x0812) __sfr COG3DBF
;
14506 unsigned G3DBF0
: 1;
14507 unsigned G3DBF1
: 1;
14508 unsigned G3DBF2
: 1;
14509 unsigned G3DBF3
: 1;
14510 unsigned G3DBF4
: 1;
14511 unsigned G3DBF5
: 1;
14524 unsigned G3DBF
: 6;
14529 extern __at(0x0812) volatile __COG3DBFbits_t COG3DBFbits
;
14531 #define _COG3DBF_DBF0 0x01
14532 #define _COG3DBF_G3DBF0 0x01
14533 #define _COG3DBF_DBF1 0x02
14534 #define _COG3DBF_G3DBF1 0x02
14535 #define _COG3DBF_DBF2 0x04
14536 #define _COG3DBF_G3DBF2 0x04
14537 #define _COG3DBF_DBF3 0x08
14538 #define _COG3DBF_G3DBF3 0x08
14539 #define _COG3DBF_DBF4 0x10
14540 #define _COG3DBF_G3DBF4 0x10
14541 #define _COG3DBF_DBF5 0x20
14542 #define _COG3DBF_G3DBF5 0x20
14544 //==============================================================================
14547 //==============================================================================
14550 extern __at(0x0813) __sfr COG3CON0
;
14568 unsigned G3MD0
: 1;
14569 unsigned G3MD1
: 1;
14570 unsigned G3MD2
: 1;
14571 unsigned G3CS0
: 1;
14572 unsigned G3CS1
: 1;
14603 } __COG3CON0bits_t
;
14605 extern __at(0x0813) volatile __COG3CON0bits_t COG3CON0bits
;
14607 #define _COG3CON0_MD0 0x01
14608 #define _COG3CON0_G3MD0 0x01
14609 #define _COG3CON0_MD1 0x02
14610 #define _COG3CON0_G3MD1 0x02
14611 #define _COG3CON0_MD2 0x04
14612 #define _COG3CON0_G3MD2 0x04
14613 #define _COG3CON0_CS0 0x08
14614 #define _COG3CON0_G3CS0 0x08
14615 #define _COG3CON0_CS1 0x10
14616 #define _COG3CON0_G3CS1 0x10
14617 #define _COG3CON0_LD 0x40
14618 #define _COG3CON0_G3LD 0x40
14619 #define _COG3CON0_EN 0x80
14620 #define _COG3CON0_G3EN 0x80
14622 //==============================================================================
14625 //==============================================================================
14628 extern __at(0x0814) __sfr COG3CON1
;
14646 unsigned G3POLA
: 1;
14647 unsigned G3POLB
: 1;
14648 unsigned G3POLC
: 1;
14649 unsigned G3POLD
: 1;
14652 unsigned G3FDBS
: 1;
14653 unsigned G3RDBS
: 1;
14655 } __COG3CON1bits_t
;
14657 extern __at(0x0814) volatile __COG3CON1bits_t COG3CON1bits
;
14659 #define _COG3CON1_POLA 0x01
14660 #define _COG3CON1_G3POLA 0x01
14661 #define _COG3CON1_POLB 0x02
14662 #define _COG3CON1_G3POLB 0x02
14663 #define _COG3CON1_POLC 0x04
14664 #define _COG3CON1_G3POLC 0x04
14665 #define _COG3CON1_POLD 0x08
14666 #define _COG3CON1_G3POLD 0x08
14667 #define _COG3CON1_FDBS 0x40
14668 #define _COG3CON1_G3FDBS 0x40
14669 #define _COG3CON1_RDBS 0x80
14670 #define _COG3CON1_G3RDBS 0x80
14672 //==============================================================================
14675 //==============================================================================
14678 extern __at(0x0815) __sfr COG3RIS0
;
14696 unsigned G3RIS0
: 1;
14697 unsigned G3RIS1
: 1;
14698 unsigned G3RIS2
: 1;
14699 unsigned G3RIS3
: 1;
14700 unsigned G3RIS4
: 1;
14701 unsigned G3RIS5
: 1;
14702 unsigned G3RIS6
: 1;
14703 unsigned G3RIS7
: 1;
14705 } __COG3RIS0bits_t
;
14707 extern __at(0x0815) volatile __COG3RIS0bits_t COG3RIS0bits
;
14709 #define _COG3RIS0_RIS0 0x01
14710 #define _COG3RIS0_G3RIS0 0x01
14711 #define _COG3RIS0_RIS1 0x02
14712 #define _COG3RIS0_G3RIS1 0x02
14713 #define _COG3RIS0_RIS2 0x04
14714 #define _COG3RIS0_G3RIS2 0x04
14715 #define _COG3RIS0_RIS3 0x08
14716 #define _COG3RIS0_G3RIS3 0x08
14717 #define _COG3RIS0_RIS4 0x10
14718 #define _COG3RIS0_G3RIS4 0x10
14719 #define _COG3RIS0_RIS5 0x20
14720 #define _COG3RIS0_G3RIS5 0x20
14721 #define _COG3RIS0_RIS6 0x40
14722 #define _COG3RIS0_G3RIS6 0x40
14723 #define _COG3RIS0_RIS7 0x80
14724 #define _COG3RIS0_G3RIS7 0x80
14726 //==============================================================================
14729 //==============================================================================
14732 extern __at(0x0816) __sfr COG3RIS1
;
14741 unsigned RIS11
: 1;
14742 unsigned RIS12
: 1;
14743 unsigned RIS13
: 1;
14744 unsigned RIS14
: 1;
14745 unsigned RIS15
: 1;
14751 unsigned G3RIS9
: 1;
14753 unsigned G3RIS11
: 1;
14754 unsigned G3RIS12
: 1;
14755 unsigned G3RIS13
: 1;
14756 unsigned G3RIS14
: 1;
14757 unsigned G3RIS15
: 1;
14759 } __COG3RIS1bits_t
;
14761 extern __at(0x0816) volatile __COG3RIS1bits_t COG3RIS1bits
;
14763 #define _COG3RIS1_RIS9 0x02
14764 #define _COG3RIS1_G3RIS9 0x02
14765 #define _COG3RIS1_RIS11 0x08
14766 #define _COG3RIS1_G3RIS11 0x08
14767 #define _COG3RIS1_RIS12 0x10
14768 #define _COG3RIS1_G3RIS12 0x10
14769 #define _COG3RIS1_RIS13 0x20
14770 #define _COG3RIS1_G3RIS13 0x20
14771 #define _COG3RIS1_RIS14 0x40
14772 #define _COG3RIS1_G3RIS14 0x40
14773 #define _COG3RIS1_RIS15 0x80
14774 #define _COG3RIS1_G3RIS15 0x80
14776 //==============================================================================
14779 //==============================================================================
14782 extern __at(0x0817) __sfr COG3RSIM0
;
14788 unsigned RSIM0
: 1;
14789 unsigned RSIM1
: 1;
14790 unsigned RSIM2
: 1;
14791 unsigned RSIM3
: 1;
14792 unsigned RSIM4
: 1;
14793 unsigned RSIM5
: 1;
14794 unsigned RSIM6
: 1;
14795 unsigned RSIM7
: 1;
14800 unsigned G3RSIM0
: 1;
14801 unsigned G3RSIM1
: 1;
14802 unsigned G3RSIM2
: 1;
14803 unsigned G3RSIM3
: 1;
14804 unsigned G3RSIM4
: 1;
14805 unsigned G3RSIM5
: 1;
14806 unsigned G3RSIM6
: 1;
14807 unsigned G3RSIM7
: 1;
14809 } __COG3RSIM0bits_t
;
14811 extern __at(0x0817) volatile __COG3RSIM0bits_t COG3RSIM0bits
;
14813 #define _COG3RSIM0_RSIM0 0x01
14814 #define _COG3RSIM0_G3RSIM0 0x01
14815 #define _COG3RSIM0_RSIM1 0x02
14816 #define _COG3RSIM0_G3RSIM1 0x02
14817 #define _COG3RSIM0_RSIM2 0x04
14818 #define _COG3RSIM0_G3RSIM2 0x04
14819 #define _COG3RSIM0_RSIM3 0x08
14820 #define _COG3RSIM0_G3RSIM3 0x08
14821 #define _COG3RSIM0_RSIM4 0x10
14822 #define _COG3RSIM0_G3RSIM4 0x10
14823 #define _COG3RSIM0_RSIM5 0x20
14824 #define _COG3RSIM0_G3RSIM5 0x20
14825 #define _COG3RSIM0_RSIM6 0x40
14826 #define _COG3RSIM0_G3RSIM6 0x40
14827 #define _COG3RSIM0_RSIM7 0x80
14828 #define _COG3RSIM0_G3RSIM7 0x80
14830 //==============================================================================
14833 //==============================================================================
14836 extern __at(0x0818) __sfr COG3RSIM1
;
14843 unsigned RSIM9
: 1;
14845 unsigned RSIM11
: 1;
14846 unsigned RSIM12
: 1;
14847 unsigned RSIM13
: 1;
14848 unsigned RSIM14
: 1;
14849 unsigned RSIM15
: 1;
14855 unsigned G3RSIM9
: 1;
14857 unsigned G3RSIM11
: 1;
14858 unsigned G3RSIM12
: 1;
14859 unsigned G3RSIM13
: 1;
14860 unsigned G3RSIM14
: 1;
14861 unsigned G3RSIM15
: 1;
14863 } __COG3RSIM1bits_t
;
14865 extern __at(0x0818) volatile __COG3RSIM1bits_t COG3RSIM1bits
;
14867 #define _COG3RSIM1_RSIM9 0x02
14868 #define _COG3RSIM1_G3RSIM9 0x02
14869 #define _COG3RSIM1_RSIM11 0x08
14870 #define _COG3RSIM1_G3RSIM11 0x08
14871 #define _COG3RSIM1_RSIM12 0x10
14872 #define _COG3RSIM1_G3RSIM12 0x10
14873 #define _COG3RSIM1_RSIM13 0x20
14874 #define _COG3RSIM1_G3RSIM13 0x20
14875 #define _COG3RSIM1_RSIM14 0x40
14876 #define _COG3RSIM1_G3RSIM14 0x40
14877 #define _COG3RSIM1_RSIM15 0x80
14878 #define _COG3RSIM1_G3RSIM15 0x80
14880 //==============================================================================
14883 //==============================================================================
14886 extern __at(0x0819) __sfr COG3FIS0
;
14904 unsigned G3FIS0
: 1;
14905 unsigned G3FIS1
: 1;
14906 unsigned G3FIS2
: 1;
14907 unsigned G3FIS3
: 1;
14908 unsigned G3FIS4
: 1;
14909 unsigned G3FIS5
: 1;
14910 unsigned G3FIS6
: 1;
14911 unsigned G3FIS7
: 1;
14913 } __COG3FIS0bits_t
;
14915 extern __at(0x0819) volatile __COG3FIS0bits_t COG3FIS0bits
;
14917 #define _COG3FIS0_FIS0 0x01
14918 #define _COG3FIS0_G3FIS0 0x01
14919 #define _COG3FIS0_FIS1 0x02
14920 #define _COG3FIS0_G3FIS1 0x02
14921 #define _COG3FIS0_FIS2 0x04
14922 #define _COG3FIS0_G3FIS2 0x04
14923 #define _COG3FIS0_FIS3 0x08
14924 #define _COG3FIS0_G3FIS3 0x08
14925 #define _COG3FIS0_FIS4 0x10
14926 #define _COG3FIS0_G3FIS4 0x10
14927 #define _COG3FIS0_FIS5 0x20
14928 #define _COG3FIS0_G3FIS5 0x20
14929 #define _COG3FIS0_FIS6 0x40
14930 #define _COG3FIS0_G3FIS6 0x40
14931 #define _COG3FIS0_FIS7 0x80
14932 #define _COG3FIS0_G3FIS7 0x80
14934 //==============================================================================
14937 //==============================================================================
14940 extern __at(0x081A) __sfr COG3FIS1
;
14949 unsigned FIS11
: 1;
14950 unsigned FIS12
: 1;
14951 unsigned FIS13
: 1;
14952 unsigned FIS14
: 1;
14953 unsigned FIS15
: 1;
14959 unsigned G3FIS9
: 1;
14961 unsigned G3FIS11
: 1;
14962 unsigned G3FIS12
: 1;
14963 unsigned G3FIS13
: 1;
14964 unsigned G3FIS14
: 1;
14965 unsigned G3FIS15
: 1;
14967 } __COG3FIS1bits_t
;
14969 extern __at(0x081A) volatile __COG3FIS1bits_t COG3FIS1bits
;
14971 #define _COG3FIS1_FIS9 0x02
14972 #define _COG3FIS1_G3FIS9 0x02
14973 #define _COG3FIS1_FIS11 0x08
14974 #define _COG3FIS1_G3FIS11 0x08
14975 #define _COG3FIS1_FIS12 0x10
14976 #define _COG3FIS1_G3FIS12 0x10
14977 #define _COG3FIS1_FIS13 0x20
14978 #define _COG3FIS1_G3FIS13 0x20
14979 #define _COG3FIS1_FIS14 0x40
14980 #define _COG3FIS1_G3FIS14 0x40
14981 #define _COG3FIS1_FIS15 0x80
14982 #define _COG3FIS1_G3FIS15 0x80
14984 //==============================================================================
14987 //==============================================================================
14990 extern __at(0x081B) __sfr COG3FSIM0
;
14996 unsigned FSIM0
: 1;
14997 unsigned FSIM1
: 1;
14998 unsigned FSIM2
: 1;
14999 unsigned FSIM3
: 1;
15000 unsigned FSIM4
: 1;
15001 unsigned FSIM5
: 1;
15002 unsigned FSIM6
: 1;
15003 unsigned FSIM7
: 1;
15008 unsigned G3FSIM0
: 1;
15009 unsigned G3FSIM1
: 1;
15010 unsigned G3FSIM2
: 1;
15011 unsigned G3FSIM3
: 1;
15012 unsigned G3FSIM4
: 1;
15013 unsigned G3FSIM5
: 1;
15014 unsigned G3FSIM6
: 1;
15015 unsigned G3FSIM7
: 1;
15017 } __COG3FSIM0bits_t
;
15019 extern __at(0x081B) volatile __COG3FSIM0bits_t COG3FSIM0bits
;
15021 #define _COG3FSIM0_FSIM0 0x01
15022 #define _COG3FSIM0_G3FSIM0 0x01
15023 #define _COG3FSIM0_FSIM1 0x02
15024 #define _COG3FSIM0_G3FSIM1 0x02
15025 #define _COG3FSIM0_FSIM2 0x04
15026 #define _COG3FSIM0_G3FSIM2 0x04
15027 #define _COG3FSIM0_FSIM3 0x08
15028 #define _COG3FSIM0_G3FSIM3 0x08
15029 #define _COG3FSIM0_FSIM4 0x10
15030 #define _COG3FSIM0_G3FSIM4 0x10
15031 #define _COG3FSIM0_FSIM5 0x20
15032 #define _COG3FSIM0_G3FSIM5 0x20
15033 #define _COG3FSIM0_FSIM6 0x40
15034 #define _COG3FSIM0_G3FSIM6 0x40
15035 #define _COG3FSIM0_FSIM7 0x80
15036 #define _COG3FSIM0_G3FSIM7 0x80
15038 //==============================================================================
15041 //==============================================================================
15044 extern __at(0x081C) __sfr COG3FSIM1
;
15051 unsigned FSIM9
: 1;
15053 unsigned FSIM11
: 1;
15054 unsigned FSIM12
: 1;
15055 unsigned FSIM13
: 1;
15056 unsigned FSIM14
: 1;
15057 unsigned FSIM15
: 1;
15063 unsigned G3FSIM9
: 1;
15065 unsigned G3FSIM11
: 1;
15066 unsigned G3FSIM12
: 1;
15067 unsigned G3FSIM13
: 1;
15068 unsigned G3FSIM14
: 1;
15069 unsigned G3FSIM15
: 1;
15071 } __COG3FSIM1bits_t
;
15073 extern __at(0x081C) volatile __COG3FSIM1bits_t COG3FSIM1bits
;
15075 #define _COG3FSIM1_FSIM9 0x02
15076 #define _COG3FSIM1_G3FSIM9 0x02
15077 #define _COG3FSIM1_FSIM11 0x08
15078 #define _COG3FSIM1_G3FSIM11 0x08
15079 #define _COG3FSIM1_FSIM12 0x10
15080 #define _COG3FSIM1_G3FSIM12 0x10
15081 #define _COG3FSIM1_FSIM13 0x20
15082 #define _COG3FSIM1_G3FSIM13 0x20
15083 #define _COG3FSIM1_FSIM14 0x40
15084 #define _COG3FSIM1_G3FSIM14 0x40
15085 #define _COG3FSIM1_FSIM15 0x80
15086 #define _COG3FSIM1_G3FSIM15 0x80
15088 //==============================================================================
15091 //==============================================================================
15094 extern __at(0x081D) __sfr COG3ASD0
;
15102 unsigned ASDAC0
: 1;
15103 unsigned ASDAC1
: 1;
15104 unsigned ASDBD0
: 1;
15105 unsigned ASDBD1
: 1;
15106 unsigned ASREN
: 1;
15114 unsigned G3ASDAC0
: 1;
15115 unsigned G3ASDAC1
: 1;
15116 unsigned G3ASDBD0
: 1;
15117 unsigned G3ASDBD1
: 1;
15118 unsigned ARSEN
: 1;
15119 unsigned G3ASE
: 1;
15130 unsigned G3ARSEN
: 1;
15142 unsigned G3ASREN
: 1;
15149 unsigned ASDAC
: 2;
15156 unsigned G3ASDAC
: 2;
15163 unsigned ASDBD
: 2;
15170 unsigned G3ASDBD
: 2;
15173 } __COG3ASD0bits_t
;
15175 extern __at(0x081D) volatile __COG3ASD0bits_t COG3ASD0bits
;
15177 #define _COG3ASD0_ASDAC0 0x04
15178 #define _COG3ASD0_G3ASDAC0 0x04
15179 #define _COG3ASD0_ASDAC1 0x08
15180 #define _COG3ASD0_G3ASDAC1 0x08
15181 #define _COG3ASD0_ASDBD0 0x10
15182 #define _COG3ASD0_G3ASDBD0 0x10
15183 #define _COG3ASD0_ASDBD1 0x20
15184 #define _COG3ASD0_G3ASDBD1 0x20
15185 #define _COG3ASD0_ASREN 0x40
15186 #define _COG3ASD0_ARSEN 0x40
15187 #define _COG3ASD0_G3ARSEN 0x40
15188 #define _COG3ASD0_G3ASREN 0x40
15189 #define _COG3ASD0_ASE 0x80
15190 #define _COG3ASD0_G3ASE 0x80
15192 //==============================================================================
15195 //==============================================================================
15198 extern __at(0x081E) __sfr COG3ASD1
;
15216 unsigned G3AS0E
: 1;
15217 unsigned G3AS1E
: 1;
15218 unsigned G3AS2E
: 1;
15219 unsigned G3AS3E
: 1;
15220 unsigned G3AS4E
: 1;
15221 unsigned G3AS5E
: 1;
15222 unsigned G3AS6E
: 1;
15223 unsigned G3AS7E
: 1;
15225 } __COG3ASD1bits_t
;
15227 extern __at(0x081E) volatile __COG3ASD1bits_t COG3ASD1bits
;
15229 #define _COG3ASD1_AS0E 0x01
15230 #define _COG3ASD1_G3AS0E 0x01
15231 #define _COG3ASD1_AS1E 0x02
15232 #define _COG3ASD1_G3AS1E 0x02
15233 #define _COG3ASD1_AS2E 0x04
15234 #define _COG3ASD1_G3AS2E 0x04
15235 #define _COG3ASD1_AS3E 0x08
15236 #define _COG3ASD1_G3AS3E 0x08
15237 #define _COG3ASD1_AS4E 0x10
15238 #define _COG3ASD1_G3AS4E 0x10
15239 #define _COG3ASD1_AS5E 0x20
15240 #define _COG3ASD1_G3AS5E 0x20
15241 #define _COG3ASD1_AS6E 0x40
15242 #define _COG3ASD1_G3AS6E 0x40
15243 #define _COG3ASD1_AS7E 0x80
15244 #define _COG3ASD1_G3AS7E 0x80
15246 //==============================================================================
15249 //==============================================================================
15252 extern __at(0x081F) __sfr COG3STR
;
15262 unsigned SDATA
: 1;
15263 unsigned SDATB
: 1;
15264 unsigned SDATC
: 1;
15265 unsigned SDATD
: 1;
15270 unsigned G3STRA
: 1;
15271 unsigned G3STRB
: 1;
15272 unsigned G3STRC
: 1;
15273 unsigned G3STRD
: 1;
15274 unsigned G3SDATA
: 1;
15275 unsigned G3SDATB
: 1;
15276 unsigned G3SDATC
: 1;
15277 unsigned G3SDATD
: 1;
15281 extern __at(0x081F) volatile __COG3STRbits_t COG3STRbits
;
15283 #define _COG3STR_STRA 0x01
15284 #define _COG3STR_G3STRA 0x01
15285 #define _COG3STR_STRB 0x02
15286 #define _COG3STR_G3STRB 0x02
15287 #define _COG3STR_STRC 0x04
15288 #define _COG3STR_G3STRC 0x04
15289 #define _COG3STR_STRD 0x08
15290 #define _COG3STR_G3STRD 0x08
15291 #define _COG3STR_SDATA 0x10
15292 #define _COG3STR_G3SDATA 0x10
15293 #define _COG3STR_SDATB 0x20
15294 #define _COG3STR_G3SDATB 0x20
15295 #define _COG3STR_SDATC 0x40
15296 #define _COG3STR_G3SDATC 0x40
15297 #define _COG3STR_SDATD 0x80
15298 #define _COG3STR_G3SDATD 0x80
15300 //==============================================================================
15303 //==============================================================================
15306 extern __at(0x090C) __sfr CM4CON0
;
15314 unsigned Reserved
: 1;
15324 unsigned C4SYNC
: 1;
15325 unsigned C4HYS
: 1;
15327 unsigned C4ZLF
: 1;
15328 unsigned C4POL
: 1;
15330 unsigned C4OUT
: 1;
15335 extern __at(0x090C) volatile __CM4CON0bits_t CM4CON0bits
;
15337 #define _CM4CON0_SYNC 0x01
15338 #define _CM4CON0_C4SYNC 0x01
15339 #define _CM4CON0_HYS 0x02
15340 #define _CM4CON0_C4HYS 0x02
15341 #define _CM4CON0_Reserved 0x04
15342 #define _CM4CON0_C4SP 0x04
15343 #define _CM4CON0_ZLF 0x08
15344 #define _CM4CON0_C4ZLF 0x08
15345 #define _CM4CON0_POL 0x10
15346 #define _CM4CON0_C4POL 0x10
15347 #define _CM4CON0_OUT 0x40
15348 #define _CM4CON0_C4OUT 0x40
15349 #define _CM4CON0_ON 0x80
15350 #define _CM4CON0_C4ON 0x80
15352 //==============================================================================
15355 //==============================================================================
15358 extern __at(0x090D) __sfr CM4CON1
;
15376 unsigned C4INTN
: 1;
15377 unsigned C4INTP
: 1;
15387 extern __at(0x090D) volatile __CM4CON1bits_t CM4CON1bits
;
15389 #define _CM4CON1_INTN 0x01
15390 #define _CM4CON1_C4INTN 0x01
15391 #define _CM4CON1_INTP 0x02
15392 #define _CM4CON1_C4INTP 0x02
15394 //==============================================================================
15397 //==============================================================================
15400 extern __at(0x090E) __sfr CM4NSEL
;
15406 unsigned C4NCH0
: 1;
15407 unsigned C4NCH1
: 1;
15408 unsigned C4NCH2
: 1;
15409 unsigned C4NCH3
: 1;
15418 unsigned C4NCH
: 4;
15423 extern __at(0x090E) volatile __CM4NSELbits_t CM4NSELbits
;
15425 #define _C4NCH0 0x01
15426 #define _C4NCH1 0x02
15427 #define _C4NCH2 0x04
15428 #define _C4NCH3 0x08
15430 //==============================================================================
15433 //==============================================================================
15436 extern __at(0x090F) __sfr CM4PSEL
;
15454 unsigned C4PCH0
: 1;
15455 unsigned C4PCH1
: 1;
15456 unsigned C4PCH2
: 1;
15457 unsigned C4PCH3
: 1;
15472 unsigned C4PCH
: 4;
15477 extern __at(0x090F) volatile __CM4PSELbits_t CM4PSELbits
;
15479 #define _CM4PSEL_PCH0 0x01
15480 #define _CM4PSEL_C4PCH0 0x01
15481 #define _CM4PSEL_PCH1 0x02
15482 #define _CM4PSEL_C4PCH1 0x02
15483 #define _CM4PSEL_PCH2 0x04
15484 #define _CM4PSEL_C4PCH2 0x04
15485 #define _CM4PSEL_PCH3 0x08
15486 #define _CM4PSEL_C4PCH3 0x08
15488 //==============================================================================
15491 //==============================================================================
15494 extern __at(0x0910) __sfr CM5CON0
;
15502 unsigned Reserved
: 1;
15512 unsigned C5SYNC
: 1;
15513 unsigned C5HYS
: 1;
15515 unsigned C5ZLF
: 1;
15516 unsigned C5POL
: 1;
15518 unsigned C5OUT
: 1;
15523 extern __at(0x0910) volatile __CM5CON0bits_t CM5CON0bits
;
15525 #define _CM5CON0_SYNC 0x01
15526 #define _CM5CON0_C5SYNC 0x01
15527 #define _CM5CON0_HYS 0x02
15528 #define _CM5CON0_C5HYS 0x02
15529 #define _CM5CON0_Reserved 0x04
15530 #define _CM5CON0_C5SP 0x04
15531 #define _CM5CON0_ZLF 0x08
15532 #define _CM5CON0_C5ZLF 0x08
15533 #define _CM5CON0_POL 0x10
15534 #define _CM5CON0_C5POL 0x10
15535 #define _CM5CON0_OUT 0x40
15536 #define _CM5CON0_C5OUT 0x40
15537 #define _CM5CON0_ON 0x80
15538 #define _CM5CON0_C5ON 0x80
15540 //==============================================================================
15543 //==============================================================================
15546 extern __at(0x0911) __sfr CM5CON1
;
15564 unsigned C5INTN
: 1;
15565 unsigned C5INTP
: 1;
15575 extern __at(0x0911) volatile __CM5CON1bits_t CM5CON1bits
;
15577 #define _CM5CON1_INTN 0x01
15578 #define _CM5CON1_C5INTN 0x01
15579 #define _CM5CON1_INTP 0x02
15580 #define _CM5CON1_C5INTP 0x02
15582 //==============================================================================
15585 //==============================================================================
15588 extern __at(0x0912) __sfr CM5NSEL
;
15594 unsigned C5NCH0
: 1;
15595 unsigned C5NCH1
: 1;
15596 unsigned C5NCH2
: 1;
15597 unsigned C5NCH3
: 1;
15606 unsigned C5NCH
: 4;
15611 extern __at(0x0912) volatile __CM5NSELbits_t CM5NSELbits
;
15613 #define _C5NCH0 0x01
15614 #define _C5NCH1 0x02
15615 #define _C5NCH2 0x04
15616 #define _C5NCH3 0x08
15618 //==============================================================================
15621 //==============================================================================
15624 extern __at(0x0913) __sfr CM5PSEL
;
15642 unsigned C5PCH0
: 1;
15643 unsigned C5PCH1
: 1;
15644 unsigned C5PCH2
: 1;
15645 unsigned C5PCH3
: 1;
15654 unsigned C5PCH
: 4;
15665 extern __at(0x0913) volatile __CM5PSELbits_t CM5PSELbits
;
15667 #define _CM5PSEL_PCH0 0x01
15668 #define _CM5PSEL_C5PCH0 0x01
15669 #define _CM5PSEL_PCH1 0x02
15670 #define _CM5PSEL_C5PCH1 0x02
15671 #define _CM5PSEL_PCH2 0x04
15672 #define _CM5PSEL_C5PCH2 0x04
15673 #define _CM5PSEL_PCH3 0x08
15674 #define _CM5PSEL_C5PCH3 0x08
15676 //==============================================================================
15679 //==============================================================================
15682 extern __at(0x0914) __sfr CM6CON0
;
15690 unsigned Reserved
: 1;
15700 unsigned C6SYNC
: 1;
15701 unsigned C6HYS
: 1;
15703 unsigned C6ZLF
: 1;
15704 unsigned C6POL
: 1;
15706 unsigned C6OUT
: 1;
15711 extern __at(0x0914) volatile __CM6CON0bits_t CM6CON0bits
;
15713 #define _CM6CON0_SYNC 0x01
15714 #define _CM6CON0_C6SYNC 0x01
15715 #define _CM6CON0_HYS 0x02
15716 #define _CM6CON0_C6HYS 0x02
15717 #define _CM6CON0_Reserved 0x04
15718 #define _CM6CON0_C6SP 0x04
15719 #define _CM6CON0_ZLF 0x08
15720 #define _CM6CON0_C6ZLF 0x08
15721 #define _CM6CON0_POL 0x10
15722 #define _CM6CON0_C6POL 0x10
15723 #define _CM6CON0_OUT 0x40
15724 #define _CM6CON0_C6OUT 0x40
15725 #define _CM6CON0_ON 0x80
15726 #define _CM6CON0_C6ON 0x80
15728 //==============================================================================
15731 //==============================================================================
15734 extern __at(0x0915) __sfr CM6CON1
;
15752 unsigned C6INTN
: 1;
15753 unsigned C6INTP
: 1;
15763 extern __at(0x0915) volatile __CM6CON1bits_t CM6CON1bits
;
15765 #define _CM6CON1_INTN 0x01
15766 #define _CM6CON1_C6INTN 0x01
15767 #define _CM6CON1_INTP 0x02
15768 #define _CM6CON1_C6INTP 0x02
15770 //==============================================================================
15773 //==============================================================================
15776 extern __at(0x0916) __sfr CM6NSEL
;
15782 unsigned C6NCH0
: 1;
15783 unsigned C6NCH1
: 1;
15784 unsigned C6NCH2
: 1;
15785 unsigned C6NCH3
: 1;
15794 unsigned C6NCH
: 4;
15799 extern __at(0x0916) volatile __CM6NSELbits_t CM6NSELbits
;
15801 #define _C6NCH0 0x01
15802 #define _C6NCH1 0x02
15803 #define _C6NCH2 0x04
15804 #define _C6NCH3 0x08
15806 //==============================================================================
15809 //==============================================================================
15812 extern __at(0x0917) __sfr CM6PSEL
;
15830 unsigned C6PCH0
: 1;
15831 unsigned C6PCH1
: 1;
15832 unsigned C6PCH2
: 1;
15833 unsigned C6PCH3
: 1;
15848 unsigned C6PCH
: 4;
15853 extern __at(0x0917) volatile __CM6PSELbits_t CM6PSELbits
;
15855 #define _CM6PSEL_PCH0 0x01
15856 #define _CM6PSEL_C6PCH0 0x01
15857 #define _CM6PSEL_PCH1 0x02
15858 #define _CM6PSEL_C6PCH1 0x02
15859 #define _CM6PSEL_PCH2 0x04
15860 #define _CM6PSEL_C6PCH2 0x04
15861 #define _CM6PSEL_PCH3 0x08
15862 #define _CM6PSEL_C6PCH3 0x08
15864 //==============================================================================
15867 //==============================================================================
15870 extern __at(0x0D8E) __sfr PWMEN
;
15874 unsigned MPWM5EN
: 1;
15875 unsigned MPWM6EN
: 1;
15876 unsigned MPWM11EN
: 1;
15884 extern __at(0x0D8E) volatile __PWMENbits_t PWMENbits
;
15886 #define _MPWM5EN 0x01
15887 #define _MPWM6EN 0x02
15888 #define _MPWM11EN 0x04
15890 //==============================================================================
15893 //==============================================================================
15896 extern __at(0x0D8F) __sfr PWMLD
;
15900 unsigned MPWM5LD
: 1;
15901 unsigned MPWM6LD
: 1;
15902 unsigned MPWM11LD
: 1;
15910 extern __at(0x0D8F) volatile __PWMLDbits_t PWMLDbits
;
15912 #define _MPWM5LD 0x01
15913 #define _MPWM6LD 0x02
15914 #define _MPWM11LD 0x04
15916 //==============================================================================
15919 //==============================================================================
15922 extern __at(0x0D90) __sfr PWMOUT
;
15926 unsigned MPWM5OUT
: 1;
15927 unsigned MPWM6OUT
: 1;
15928 unsigned MPWM11OUT
: 1;
15936 extern __at(0x0D90) volatile __PWMOUTbits_t PWMOUTbits
;
15938 #define _MPWM5OUT 0x01
15939 #define _MPWM6OUT 0x02
15940 #define _MPWM11OUT 0x04
15942 //==============================================================================
15944 extern __at(0x0D91) __sfr PWM5PH
;
15946 //==============================================================================
15949 extern __at(0x0D91) __sfr PWM5PHL
;
15953 unsigned PWM5PHL0
: 1;
15954 unsigned PWM5PHL1
: 1;
15955 unsigned PWM5PHL2
: 1;
15956 unsigned PWM5PHL3
: 1;
15957 unsigned PWM5PHL4
: 1;
15958 unsigned PWM5PHL5
: 1;
15959 unsigned PWM5PHL6
: 1;
15960 unsigned PWM5PHL7
: 1;
15963 extern __at(0x0D91) volatile __PWM5PHLbits_t PWM5PHLbits
;
15965 #define _PWM5PHL0 0x01
15966 #define _PWM5PHL1 0x02
15967 #define _PWM5PHL2 0x04
15968 #define _PWM5PHL3 0x08
15969 #define _PWM5PHL4 0x10
15970 #define _PWM5PHL5 0x20
15971 #define _PWM5PHL6 0x40
15972 #define _PWM5PHL7 0x80
15974 //==============================================================================
15977 //==============================================================================
15980 extern __at(0x0D92) __sfr PWM5PHH
;
15984 unsigned PWM5PHH0
: 1;
15985 unsigned PWM5PHH1
: 1;
15986 unsigned PWM5PHH2
: 1;
15987 unsigned PWM5PHH3
: 1;
15988 unsigned PWM5PHH4
: 1;
15989 unsigned PWM5PHH5
: 1;
15990 unsigned PWM5PHH6
: 1;
15991 unsigned PWM5PHH7
: 1;
15994 extern __at(0x0D92) volatile __PWM5PHHbits_t PWM5PHHbits
;
15996 #define _PWM5PHH0 0x01
15997 #define _PWM5PHH1 0x02
15998 #define _PWM5PHH2 0x04
15999 #define _PWM5PHH3 0x08
16000 #define _PWM5PHH4 0x10
16001 #define _PWM5PHH5 0x20
16002 #define _PWM5PHH6 0x40
16003 #define _PWM5PHH7 0x80
16005 //==============================================================================
16007 extern __at(0x0D93) __sfr PWM5DC
;
16009 //==============================================================================
16012 extern __at(0x0D93) __sfr PWM5DCL
;
16016 unsigned PWM5DCL0
: 1;
16017 unsigned PWM5DCL1
: 1;
16018 unsigned PWM5DCL2
: 1;
16019 unsigned PWM5DCL3
: 1;
16020 unsigned PWM5DCL4
: 1;
16021 unsigned PWM5DCL5
: 1;
16022 unsigned PWM5DCL6
: 1;
16023 unsigned PWM5DCL7
: 1;
16026 extern __at(0x0D93) volatile __PWM5DCLbits_t PWM5DCLbits
;
16028 #define _PWM5DCL0 0x01
16029 #define _PWM5DCL1 0x02
16030 #define _PWM5DCL2 0x04
16031 #define _PWM5DCL3 0x08
16032 #define _PWM5DCL4 0x10
16033 #define _PWM5DCL5 0x20
16034 #define _PWM5DCL6 0x40
16035 #define _PWM5DCL7 0x80
16037 //==============================================================================
16040 //==============================================================================
16043 extern __at(0x0D94) __sfr PWM5DCH
;
16047 unsigned PWM5DCH0
: 1;
16048 unsigned PWM5DCH1
: 1;
16049 unsigned PWM5DCH2
: 1;
16050 unsigned PWM5DCH3
: 1;
16051 unsigned PWM5DCH4
: 1;
16052 unsigned PWM5DCH5
: 1;
16053 unsigned PWM5DCH6
: 1;
16054 unsigned PWM5DCH7
: 1;
16057 extern __at(0x0D94) volatile __PWM5DCHbits_t PWM5DCHbits
;
16059 #define _PWM5DCH0 0x01
16060 #define _PWM5DCH1 0x02
16061 #define _PWM5DCH2 0x04
16062 #define _PWM5DCH3 0x08
16063 #define _PWM5DCH4 0x10
16064 #define _PWM5DCH5 0x20
16065 #define _PWM5DCH6 0x40
16066 #define _PWM5DCH7 0x80
16068 //==============================================================================
16070 extern __at(0x0D95) __sfr PWM5PR
;
16072 //==============================================================================
16075 extern __at(0x0D95) __sfr PWM5PRL
;
16079 unsigned PWM5PRL0
: 1;
16080 unsigned PWM5PRL1
: 1;
16081 unsigned PWM5PRL2
: 1;
16082 unsigned PWM5PRL3
: 1;
16083 unsigned PWM5PRL4
: 1;
16084 unsigned PWM5PRL5
: 1;
16085 unsigned PWM5PRL6
: 1;
16086 unsigned PWM5PRL7
: 1;
16089 extern __at(0x0D95) volatile __PWM5PRLbits_t PWM5PRLbits
;
16091 #define _PWM5PRL0 0x01
16092 #define _PWM5PRL1 0x02
16093 #define _PWM5PRL2 0x04
16094 #define _PWM5PRL3 0x08
16095 #define _PWM5PRL4 0x10
16096 #define _PWM5PRL5 0x20
16097 #define _PWM5PRL6 0x40
16098 #define _PWM5PRL7 0x80
16100 //==============================================================================
16103 //==============================================================================
16106 extern __at(0x0D96) __sfr PWM5PRH
;
16110 unsigned PWM5PRH0
: 1;
16111 unsigned PWM5PRH1
: 1;
16112 unsigned PWM5PRH2
: 1;
16113 unsigned PWM5PRH3
: 1;
16114 unsigned PWM5PRH4
: 1;
16115 unsigned PWM5PRH5
: 1;
16116 unsigned PWM5PRH6
: 1;
16117 unsigned PWM5PRH7
: 1;
16120 extern __at(0x0D96) volatile __PWM5PRHbits_t PWM5PRHbits
;
16122 #define _PWM5PRH0 0x01
16123 #define _PWM5PRH1 0x02
16124 #define _PWM5PRH2 0x04
16125 #define _PWM5PRH3 0x08
16126 #define _PWM5PRH4 0x10
16127 #define _PWM5PRH5 0x20
16128 #define _PWM5PRH6 0x40
16129 #define _PWM5PRH7 0x80
16131 //==============================================================================
16133 extern __at(0x0D97) __sfr PWM5OF
;
16135 //==============================================================================
16138 extern __at(0x0D97) __sfr PWM5OFL
;
16142 unsigned PWM5OFL0
: 1;
16143 unsigned PWM5OFL1
: 1;
16144 unsigned PWM5OFL2
: 1;
16145 unsigned PWM5OFL3
: 1;
16146 unsigned PWM5OFL4
: 1;
16147 unsigned PWM5OFL5
: 1;
16148 unsigned PWM5OFL6
: 1;
16149 unsigned PWM5OFL7
: 1;
16152 extern __at(0x0D97) volatile __PWM5OFLbits_t PWM5OFLbits
;
16154 #define _PWM5OFL0 0x01
16155 #define _PWM5OFL1 0x02
16156 #define _PWM5OFL2 0x04
16157 #define _PWM5OFL3 0x08
16158 #define _PWM5OFL4 0x10
16159 #define _PWM5OFL5 0x20
16160 #define _PWM5OFL6 0x40
16161 #define _PWM5OFL7 0x80
16163 //==============================================================================
16166 //==============================================================================
16169 extern __at(0x0D98) __sfr PWM5OFH
;
16173 unsigned PWM5OFH0
: 1;
16174 unsigned PWM5OFH1
: 1;
16175 unsigned PWM5OFH2
: 1;
16176 unsigned PWM5OFH3
: 1;
16177 unsigned PWM5OFH4
: 1;
16178 unsigned PWM5OFH5
: 1;
16179 unsigned PWM5OFH6
: 1;
16180 unsigned PWM5OFH7
: 1;
16183 extern __at(0x0D98) volatile __PWM5OFHbits_t PWM5OFHbits
;
16185 #define _PWM5OFH0 0x01
16186 #define _PWM5OFH1 0x02
16187 #define _PWM5OFH2 0x04
16188 #define _PWM5OFH3 0x08
16189 #define _PWM5OFH4 0x10
16190 #define _PWM5OFH5 0x20
16191 #define _PWM5OFH6 0x40
16192 #define _PWM5OFH7 0x80
16194 //==============================================================================
16196 extern __at(0x0D99) __sfr PWM5TMR
;
16198 //==============================================================================
16201 extern __at(0x0D99) __sfr PWM5TMRL
;
16205 unsigned PWM5TMRL0
: 1;
16206 unsigned PWM5TMRL1
: 1;
16207 unsigned PWM5TMRL2
: 1;
16208 unsigned PWM5TMRL3
: 1;
16209 unsigned PWM5TMRL4
: 1;
16210 unsigned PWM5TMRL5
: 1;
16211 unsigned PWM5TMRL6
: 1;
16212 unsigned PWM5TMRL7
: 1;
16213 } __PWM5TMRLbits_t
;
16215 extern __at(0x0D99) volatile __PWM5TMRLbits_t PWM5TMRLbits
;
16217 #define _PWM5TMRL0 0x01
16218 #define _PWM5TMRL1 0x02
16219 #define _PWM5TMRL2 0x04
16220 #define _PWM5TMRL3 0x08
16221 #define _PWM5TMRL4 0x10
16222 #define _PWM5TMRL5 0x20
16223 #define _PWM5TMRL6 0x40
16224 #define _PWM5TMRL7 0x80
16226 //==============================================================================
16229 //==============================================================================
16232 extern __at(0x0D9A) __sfr PWM5TMRH
;
16236 unsigned PWM5TMRH0
: 1;
16237 unsigned PWM5TMRH1
: 1;
16238 unsigned PWM5TMRH2
: 1;
16239 unsigned PWM5TMRH3
: 1;
16240 unsigned PWM5TMRH4
: 1;
16241 unsigned PWM5TMRH5
: 1;
16242 unsigned PWM5TMRH6
: 1;
16243 unsigned PWM5TMRH7
: 1;
16244 } __PWM5TMRHbits_t
;
16246 extern __at(0x0D9A) volatile __PWM5TMRHbits_t PWM5TMRHbits
;
16248 #define _PWM5TMRH0 0x01
16249 #define _PWM5TMRH1 0x02
16250 #define _PWM5TMRH2 0x04
16251 #define _PWM5TMRH3 0x08
16252 #define _PWM5TMRH4 0x10
16253 #define _PWM5TMRH5 0x20
16254 #define _PWM5TMRH6 0x40
16255 #define _PWM5TMRH7 0x80
16257 //==============================================================================
16260 //==============================================================================
16263 extern __at(0x0D9B) __sfr PWM5CON
;
16271 unsigned PWM5MODE0
: 1;
16272 unsigned PWM5MODE1
: 1;
16283 unsigned MODE0
: 1;
16284 unsigned MODE1
: 1;
16285 unsigned PWM5POL
: 1;
16286 unsigned PWM5OUT
: 1;
16288 unsigned PWM5EN
: 1;
16301 unsigned PWM5MODE
: 2;
16306 extern __at(0x0D9B) volatile __PWM5CONbits_t PWM5CONbits
;
16308 #define _PWM5CON_PWM5MODE0 0x04
16309 #define _PWM5CON_MODE0 0x04
16310 #define _PWM5CON_PWM5MODE1 0x08
16311 #define _PWM5CON_MODE1 0x08
16312 #define _PWM5CON_POL 0x10
16313 #define _PWM5CON_PWM5POL 0x10
16314 #define _PWM5CON_OUT 0x20
16315 #define _PWM5CON_PWM5OUT 0x20
16316 #define _PWM5CON_EN 0x80
16317 #define _PWM5CON_PWM5EN 0x80
16319 //==============================================================================
16322 //==============================================================================
16325 extern __at(0x0D9C) __sfr PWM5INTCON
;
16343 unsigned PWM5PRIE
: 1;
16344 unsigned PWM5DCIE
: 1;
16345 unsigned PWM5PHIE
: 1;
16346 unsigned PWM5OFIE
: 1;
16352 } __PWM5INTCONbits_t
;
16354 extern __at(0x0D9C) volatile __PWM5INTCONbits_t PWM5INTCONbits
;
16357 #define _PWM5PRIE 0x01
16359 #define _PWM5DCIE 0x02
16361 #define _PWM5PHIE 0x04
16363 #define _PWM5OFIE 0x08
16365 //==============================================================================
16368 //==============================================================================
16371 extern __at(0x0D9C) __sfr PWM5INTE
;
16389 unsigned PWM5PRIE
: 1;
16390 unsigned PWM5DCIE
: 1;
16391 unsigned PWM5PHIE
: 1;
16392 unsigned PWM5OFIE
: 1;
16398 } __PWM5INTEbits_t
;
16400 extern __at(0x0D9C) volatile __PWM5INTEbits_t PWM5INTEbits
;
16402 #define _PWM5INTE_PRIE 0x01
16403 #define _PWM5INTE_PWM5PRIE 0x01
16404 #define _PWM5INTE_DCIE 0x02
16405 #define _PWM5INTE_PWM5DCIE 0x02
16406 #define _PWM5INTE_PHIE 0x04
16407 #define _PWM5INTE_PWM5PHIE 0x04
16408 #define _PWM5INTE_OFIE 0x08
16409 #define _PWM5INTE_PWM5OFIE 0x08
16411 //==============================================================================
16414 //==============================================================================
16417 extern __at(0x0D9D) __sfr PWM5INTF
;
16435 unsigned PWM5PRIF
: 1;
16436 unsigned PWM5DCIF
: 1;
16437 unsigned PWM5PHIF
: 1;
16438 unsigned PWM5OFIF
: 1;
16444 } __PWM5INTFbits_t
;
16446 extern __at(0x0D9D) volatile __PWM5INTFbits_t PWM5INTFbits
;
16449 #define _PWM5PRIF 0x01
16451 #define _PWM5DCIF 0x02
16453 #define _PWM5PHIF 0x04
16455 #define _PWM5OFIF 0x08
16457 //==============================================================================
16460 //==============================================================================
16463 extern __at(0x0D9D) __sfr PWM5INTFLG
;
16481 unsigned PWM5PRIF
: 1;
16482 unsigned PWM5DCIF
: 1;
16483 unsigned PWM5PHIF
: 1;
16484 unsigned PWM5OFIF
: 1;
16490 } __PWM5INTFLGbits_t
;
16492 extern __at(0x0D9D) volatile __PWM5INTFLGbits_t PWM5INTFLGbits
;
16494 #define _PWM5INTFLG_PRIF 0x01
16495 #define _PWM5INTFLG_PWM5PRIF 0x01
16496 #define _PWM5INTFLG_DCIF 0x02
16497 #define _PWM5INTFLG_PWM5DCIF 0x02
16498 #define _PWM5INTFLG_PHIF 0x04
16499 #define _PWM5INTFLG_PWM5PHIF 0x04
16500 #define _PWM5INTFLG_OFIF 0x08
16501 #define _PWM5INTFLG_PWM5OFIF 0x08
16503 //==============================================================================
16506 //==============================================================================
16509 extern __at(0x0D9E) __sfr PWM5CLKCON
;
16515 unsigned PWM5CS0
: 1;
16516 unsigned PWM5CS1
: 1;
16517 unsigned PWM5CS2
: 1;
16519 unsigned PWM5PS0
: 1;
16520 unsigned PWM5PS1
: 1;
16521 unsigned PWM5PS2
: 1;
16539 unsigned PWM5CS
: 3;
16559 unsigned PWM5PS
: 3;
16562 } __PWM5CLKCONbits_t
;
16564 extern __at(0x0D9E) volatile __PWM5CLKCONbits_t PWM5CLKCONbits
;
16566 #define _PWM5CLKCON_PWM5CS0 0x01
16567 #define _PWM5CLKCON_CS0 0x01
16568 #define _PWM5CLKCON_PWM5CS1 0x02
16569 #define _PWM5CLKCON_CS1 0x02
16570 #define _PWM5CLKCON_PWM5CS2 0x04
16571 #define _PWM5CLKCON_CS2 0x04
16572 #define _PWM5CLKCON_PWM5PS0 0x10
16573 #define _PWM5CLKCON_PS0 0x10
16574 #define _PWM5CLKCON_PWM5PS1 0x20
16575 #define _PWM5CLKCON_PS1 0x20
16576 #define _PWM5CLKCON_PWM5PS2 0x40
16577 #define _PWM5CLKCON_PS2 0x40
16579 //==============================================================================
16582 //==============================================================================
16585 extern __at(0x0D9F) __sfr PWM5LDCON
;
16591 unsigned PWM5LDS0
: 1;
16592 unsigned PWM5LDS1
: 1;
16609 unsigned PWM5LDM
: 1;
16610 unsigned PWM5LD
: 1;
16615 unsigned PWM5LDS
: 2;
16624 } __PWM5LDCONbits_t
;
16626 extern __at(0x0D9F) volatile __PWM5LDCONbits_t PWM5LDCONbits
;
16628 #define _PWM5LDS0 0x01
16630 #define _PWM5LDS1 0x02
16633 #define _PWM5LDM 0x40
16635 #define _PWM5LD 0x80
16637 //==============================================================================
16640 //==============================================================================
16643 extern __at(0x0DA0) __sfr PWM5OFCON
;
16649 unsigned PWM5OFS0
: 1;
16650 unsigned PWM5OFS1
: 1;
16654 unsigned PWM5OFM0
: 1;
16655 unsigned PWM5OFM1
: 1;
16665 unsigned PWM5OFMC
: 1;
16673 unsigned PWM5OFS
: 2;
16693 unsigned PWM5OFM
: 2;
16696 } __PWM5OFCONbits_t
;
16698 extern __at(0x0DA0) volatile __PWM5OFCONbits_t PWM5OFCONbits
;
16700 #define _PWM5OFS0 0x01
16702 #define _PWM5OFS1 0x02
16705 #define _PWM5OFMC 0x10
16706 #define _PWM5OFM0 0x20
16708 #define _PWM5OFM1 0x40
16711 //==============================================================================
16713 extern __at(0x0DA1) __sfr PWM6PH
;
16715 //==============================================================================
16718 extern __at(0x0DA1) __sfr PWM6PHL
;
16722 unsigned PWM6PHL0
: 1;
16723 unsigned PWM6PHL1
: 1;
16724 unsigned PWM6PHL2
: 1;
16725 unsigned PWM6PHL3
: 1;
16726 unsigned PWM6PHL4
: 1;
16727 unsigned PWM6PHL5
: 1;
16728 unsigned PWM6PHL6
: 1;
16729 unsigned PWM6PHL7
: 1;
16732 extern __at(0x0DA1) volatile __PWM6PHLbits_t PWM6PHLbits
;
16734 #define _PWM6PHL0 0x01
16735 #define _PWM6PHL1 0x02
16736 #define _PWM6PHL2 0x04
16737 #define _PWM6PHL3 0x08
16738 #define _PWM6PHL4 0x10
16739 #define _PWM6PHL5 0x20
16740 #define _PWM6PHL6 0x40
16741 #define _PWM6PHL7 0x80
16743 //==============================================================================
16746 //==============================================================================
16749 extern __at(0x0DA2) __sfr PWM6PHH
;
16753 unsigned PWM6PHH0
: 1;
16754 unsigned PWM6PHH1
: 1;
16755 unsigned PWM6PHH2
: 1;
16756 unsigned PWM6PHH3
: 1;
16757 unsigned PWM6PHH4
: 1;
16758 unsigned PWM6PHH5
: 1;
16759 unsigned PWM6PHH6
: 1;
16760 unsigned PWM6PHH7
: 1;
16763 extern __at(0x0DA2) volatile __PWM6PHHbits_t PWM6PHHbits
;
16765 #define _PWM6PHH0 0x01
16766 #define _PWM6PHH1 0x02
16767 #define _PWM6PHH2 0x04
16768 #define _PWM6PHH3 0x08
16769 #define _PWM6PHH4 0x10
16770 #define _PWM6PHH5 0x20
16771 #define _PWM6PHH6 0x40
16772 #define _PWM6PHH7 0x80
16774 //==============================================================================
16776 extern __at(0x0DA3) __sfr PWM6DC
;
16778 //==============================================================================
16781 extern __at(0x0DA3) __sfr PWM6DCL
;
16785 unsigned PWM6DCL0
: 1;
16786 unsigned PWM6DCL1
: 1;
16787 unsigned PWM6DCL2
: 1;
16788 unsigned PWM6DCL3
: 1;
16789 unsigned PWM6DCL4
: 1;
16790 unsigned PWM6DCL5
: 1;
16791 unsigned PWM6DCL6
: 1;
16792 unsigned PWM6DCL7
: 1;
16795 extern __at(0x0DA3) volatile __PWM6DCLbits_t PWM6DCLbits
;
16797 #define _PWM6DCL0 0x01
16798 #define _PWM6DCL1 0x02
16799 #define _PWM6DCL2 0x04
16800 #define _PWM6DCL3 0x08
16801 #define _PWM6DCL4 0x10
16802 #define _PWM6DCL5 0x20
16803 #define _PWM6DCL6 0x40
16804 #define _PWM6DCL7 0x80
16806 //==============================================================================
16809 //==============================================================================
16812 extern __at(0x0DA4) __sfr PWM6DCH
;
16816 unsigned PWM6DCH0
: 1;
16817 unsigned PWM6DCH1
: 1;
16818 unsigned PWM6DCH2
: 1;
16819 unsigned PWM6DCH3
: 1;
16820 unsigned PWM6DCH4
: 1;
16821 unsigned PWM6DCH5
: 1;
16822 unsigned PWM6DCH6
: 1;
16823 unsigned PWM6DCH7
: 1;
16826 extern __at(0x0DA4) volatile __PWM6DCHbits_t PWM6DCHbits
;
16828 #define _PWM6DCH0 0x01
16829 #define _PWM6DCH1 0x02
16830 #define _PWM6DCH2 0x04
16831 #define _PWM6DCH3 0x08
16832 #define _PWM6DCH4 0x10
16833 #define _PWM6DCH5 0x20
16834 #define _PWM6DCH6 0x40
16835 #define _PWM6DCH7 0x80
16837 //==============================================================================
16839 extern __at(0x0DA5) __sfr PWM6PR
;
16841 //==============================================================================
16844 extern __at(0x0DA5) __sfr PWM6PRL
;
16848 unsigned PWM6PRL0
: 1;
16849 unsigned PWM6PRL1
: 1;
16850 unsigned PWM6PRL2
: 1;
16851 unsigned PWM6PRL3
: 1;
16852 unsigned PWM6PRL4
: 1;
16853 unsigned PWM6PRL5
: 1;
16854 unsigned PWM6PRL6
: 1;
16855 unsigned PWM6PRL7
: 1;
16858 extern __at(0x0DA5) volatile __PWM6PRLbits_t PWM6PRLbits
;
16860 #define _PWM6PRL0 0x01
16861 #define _PWM6PRL1 0x02
16862 #define _PWM6PRL2 0x04
16863 #define _PWM6PRL3 0x08
16864 #define _PWM6PRL4 0x10
16865 #define _PWM6PRL5 0x20
16866 #define _PWM6PRL6 0x40
16867 #define _PWM6PRL7 0x80
16869 //==============================================================================
16872 //==============================================================================
16875 extern __at(0x0DA6) __sfr PWM6PRH
;
16879 unsigned PWM6PRH0
: 1;
16880 unsigned PWM6PRH1
: 1;
16881 unsigned PWM6PRH2
: 1;
16882 unsigned PWM6PRH3
: 1;
16883 unsigned PWM6PRH4
: 1;
16884 unsigned PWM6PRH5
: 1;
16885 unsigned PWM6PRH6
: 1;
16886 unsigned PWM6PRH7
: 1;
16889 extern __at(0x0DA6) volatile __PWM6PRHbits_t PWM6PRHbits
;
16891 #define _PWM6PRH0 0x01
16892 #define _PWM6PRH1 0x02
16893 #define _PWM6PRH2 0x04
16894 #define _PWM6PRH3 0x08
16895 #define _PWM6PRH4 0x10
16896 #define _PWM6PRH5 0x20
16897 #define _PWM6PRH6 0x40
16898 #define _PWM6PRH7 0x80
16900 //==============================================================================
16902 extern __at(0x0DA7) __sfr PWM6OF
;
16904 //==============================================================================
16907 extern __at(0x0DA7) __sfr PWM6OFL
;
16911 unsigned PWM6OFL0
: 1;
16912 unsigned PWM6OFL1
: 1;
16913 unsigned PWM6OFL2
: 1;
16914 unsigned PWM6OFL3
: 1;
16915 unsigned PWM6OFL4
: 1;
16916 unsigned PWM6OFL5
: 1;
16917 unsigned PWM6OFL6
: 1;
16918 unsigned PWM6OFL7
: 1;
16921 extern __at(0x0DA7) volatile __PWM6OFLbits_t PWM6OFLbits
;
16923 #define _PWM6OFL0 0x01
16924 #define _PWM6OFL1 0x02
16925 #define _PWM6OFL2 0x04
16926 #define _PWM6OFL3 0x08
16927 #define _PWM6OFL4 0x10
16928 #define _PWM6OFL5 0x20
16929 #define _PWM6OFL6 0x40
16930 #define _PWM6OFL7 0x80
16932 //==============================================================================
16935 //==============================================================================
16938 extern __at(0x0DA8) __sfr PWM6OFH
;
16942 unsigned PWM6OFH0
: 1;
16943 unsigned PWM6OFH1
: 1;
16944 unsigned PWM6OFH2
: 1;
16945 unsigned PWM6OFH3
: 1;
16946 unsigned PWM6OFH4
: 1;
16947 unsigned PWM6OFH5
: 1;
16948 unsigned PWM6OFH6
: 1;
16949 unsigned PWM6OFH7
: 1;
16952 extern __at(0x0DA8) volatile __PWM6OFHbits_t PWM6OFHbits
;
16954 #define _PWM6OFH0 0x01
16955 #define _PWM6OFH1 0x02
16956 #define _PWM6OFH2 0x04
16957 #define _PWM6OFH3 0x08
16958 #define _PWM6OFH4 0x10
16959 #define _PWM6OFH5 0x20
16960 #define _PWM6OFH6 0x40
16961 #define _PWM6OFH7 0x80
16963 //==============================================================================
16965 extern __at(0x0DA9) __sfr PWM6TMR
;
16967 //==============================================================================
16970 extern __at(0x0DA9) __sfr PWM6TMRL
;
16974 unsigned PWM6TMRL0
: 1;
16975 unsigned PWM6TMRL1
: 1;
16976 unsigned PWM6TMRL2
: 1;
16977 unsigned PWM6TMRL3
: 1;
16978 unsigned PWM6TMRL4
: 1;
16979 unsigned PWM6TMRL5
: 1;
16980 unsigned PWM6TMRL6
: 1;
16981 unsigned PWM6TMRL7
: 1;
16982 } __PWM6TMRLbits_t
;
16984 extern __at(0x0DA9) volatile __PWM6TMRLbits_t PWM6TMRLbits
;
16986 #define _PWM6TMRL0 0x01
16987 #define _PWM6TMRL1 0x02
16988 #define _PWM6TMRL2 0x04
16989 #define _PWM6TMRL3 0x08
16990 #define _PWM6TMRL4 0x10
16991 #define _PWM6TMRL5 0x20
16992 #define _PWM6TMRL6 0x40
16993 #define _PWM6TMRL7 0x80
16995 //==============================================================================
16998 //==============================================================================
17001 extern __at(0x0DAA) __sfr PWM6TMRH
;
17005 unsigned PWM6TMRH0
: 1;
17006 unsigned PWM6TMRH1
: 1;
17007 unsigned PWM6TMRH2
: 1;
17008 unsigned PWM6TMRH3
: 1;
17009 unsigned PWM6TMRH4
: 1;
17010 unsigned PWM6TMRH5
: 1;
17011 unsigned PWM6TMRH6
: 1;
17012 unsigned PWM6TMRH7
: 1;
17013 } __PWM6TMRHbits_t
;
17015 extern __at(0x0DAA) volatile __PWM6TMRHbits_t PWM6TMRHbits
;
17017 #define _PWM6TMRH0 0x01
17018 #define _PWM6TMRH1 0x02
17019 #define _PWM6TMRH2 0x04
17020 #define _PWM6TMRH3 0x08
17021 #define _PWM6TMRH4 0x10
17022 #define _PWM6TMRH5 0x20
17023 #define _PWM6TMRH6 0x40
17024 #define _PWM6TMRH7 0x80
17026 //==============================================================================
17029 //==============================================================================
17032 extern __at(0x0DAB) __sfr PWM6CON
;
17040 unsigned PWM6MODE0
: 1;
17041 unsigned PWM6MODE1
: 1;
17052 unsigned MODE0
: 1;
17053 unsigned MODE1
: 1;
17054 unsigned PWM6POL
: 1;
17055 unsigned PWM6OUT
: 1;
17057 unsigned PWM6EN
: 1;
17070 unsigned PWM6MODE
: 2;
17075 extern __at(0x0DAB) volatile __PWM6CONbits_t PWM6CONbits
;
17077 #define _PWM6CON_PWM6MODE0 0x04
17078 #define _PWM6CON_MODE0 0x04
17079 #define _PWM6CON_PWM6MODE1 0x08
17080 #define _PWM6CON_MODE1 0x08
17081 #define _PWM6CON_POL 0x10
17082 #define _PWM6CON_PWM6POL 0x10
17083 #define _PWM6CON_OUT 0x20
17084 #define _PWM6CON_PWM6OUT 0x20
17085 #define _PWM6CON_EN 0x80
17086 #define _PWM6CON_PWM6EN 0x80
17088 //==============================================================================
17091 //==============================================================================
17094 extern __at(0x0DAC) __sfr PWM6INTCON
;
17112 unsigned PWM6PRIE
: 1;
17113 unsigned PWM6DCIE
: 1;
17114 unsigned PWM6PHIE
: 1;
17115 unsigned PWM6OFIE
: 1;
17121 } __PWM6INTCONbits_t
;
17123 extern __at(0x0DAC) volatile __PWM6INTCONbits_t PWM6INTCONbits
;
17125 #define _PWM6INTCON_PRIE 0x01
17126 #define _PWM6INTCON_PWM6PRIE 0x01
17127 #define _PWM6INTCON_DCIE 0x02
17128 #define _PWM6INTCON_PWM6DCIE 0x02
17129 #define _PWM6INTCON_PHIE 0x04
17130 #define _PWM6INTCON_PWM6PHIE 0x04
17131 #define _PWM6INTCON_OFIE 0x08
17132 #define _PWM6INTCON_PWM6OFIE 0x08
17134 //==============================================================================
17137 //==============================================================================
17140 extern __at(0x0DAC) __sfr PWM6INTE
;
17158 unsigned PWM6PRIE
: 1;
17159 unsigned PWM6DCIE
: 1;
17160 unsigned PWM6PHIE
: 1;
17161 unsigned PWM6OFIE
: 1;
17167 } __PWM6INTEbits_t
;
17169 extern __at(0x0DAC) volatile __PWM6INTEbits_t PWM6INTEbits
;
17171 #define _PWM6INTE_PRIE 0x01
17172 #define _PWM6INTE_PWM6PRIE 0x01
17173 #define _PWM6INTE_DCIE 0x02
17174 #define _PWM6INTE_PWM6DCIE 0x02
17175 #define _PWM6INTE_PHIE 0x04
17176 #define _PWM6INTE_PWM6PHIE 0x04
17177 #define _PWM6INTE_OFIE 0x08
17178 #define _PWM6INTE_PWM6OFIE 0x08
17180 //==============================================================================
17183 //==============================================================================
17186 extern __at(0x0DAD) __sfr PWM6INTF
;
17204 unsigned PWM6PRIF
: 1;
17205 unsigned PWM6DCIF
: 1;
17206 unsigned PWM6PHIF
: 1;
17207 unsigned PWM6OFIF
: 1;
17213 } __PWM6INTFbits_t
;
17215 extern __at(0x0DAD) volatile __PWM6INTFbits_t PWM6INTFbits
;
17217 #define _PWM6INTF_PRIF 0x01
17218 #define _PWM6INTF_PWM6PRIF 0x01
17219 #define _PWM6INTF_DCIF 0x02
17220 #define _PWM6INTF_PWM6DCIF 0x02
17221 #define _PWM6INTF_PHIF 0x04
17222 #define _PWM6INTF_PWM6PHIF 0x04
17223 #define _PWM6INTF_OFIF 0x08
17224 #define _PWM6INTF_PWM6OFIF 0x08
17226 //==============================================================================
17229 //==============================================================================
17232 extern __at(0x0DAD) __sfr PWM6INTFLG
;
17250 unsigned PWM6PRIF
: 1;
17251 unsigned PWM6DCIF
: 1;
17252 unsigned PWM6PHIF
: 1;
17253 unsigned PWM6OFIF
: 1;
17259 } __PWM6INTFLGbits_t
;
17261 extern __at(0x0DAD) volatile __PWM6INTFLGbits_t PWM6INTFLGbits
;
17263 #define _PWM6INTFLG_PRIF 0x01
17264 #define _PWM6INTFLG_PWM6PRIF 0x01
17265 #define _PWM6INTFLG_DCIF 0x02
17266 #define _PWM6INTFLG_PWM6DCIF 0x02
17267 #define _PWM6INTFLG_PHIF 0x04
17268 #define _PWM6INTFLG_PWM6PHIF 0x04
17269 #define _PWM6INTFLG_OFIF 0x08
17270 #define _PWM6INTFLG_PWM6OFIF 0x08
17272 //==============================================================================
17275 //==============================================================================
17278 extern __at(0x0DAE) __sfr PWM6CLKCON
;
17284 unsigned PWM6CS0
: 1;
17285 unsigned PWM6CS1
: 1;
17286 unsigned PWM6CS2
: 1;
17288 unsigned PWM6PS0
: 1;
17289 unsigned PWM6PS1
: 1;
17290 unsigned PWM6PS2
: 1;
17308 unsigned PWM6CS
: 3;
17321 unsigned PWM6PS
: 3;
17331 } __PWM6CLKCONbits_t
;
17333 extern __at(0x0DAE) volatile __PWM6CLKCONbits_t PWM6CLKCONbits
;
17335 #define _PWM6CLKCON_PWM6CS0 0x01
17336 #define _PWM6CLKCON_CS0 0x01
17337 #define _PWM6CLKCON_PWM6CS1 0x02
17338 #define _PWM6CLKCON_CS1 0x02
17339 #define _PWM6CLKCON_PWM6CS2 0x04
17340 #define _PWM6CLKCON_CS2 0x04
17341 #define _PWM6CLKCON_PWM6PS0 0x10
17342 #define _PWM6CLKCON_PS0 0x10
17343 #define _PWM6CLKCON_PWM6PS1 0x20
17344 #define _PWM6CLKCON_PS1 0x20
17345 #define _PWM6CLKCON_PWM6PS2 0x40
17346 #define _PWM6CLKCON_PS2 0x40
17348 //==============================================================================
17351 //==============================================================================
17354 extern __at(0x0DAF) __sfr PWM6LDCON
;
17360 unsigned PWM6LDS0
: 1;
17361 unsigned PWM6LDS1
: 1;
17378 unsigned PWM6LDM
: 1;
17379 unsigned PWM6LD
: 1;
17390 unsigned PWM6LDS
: 2;
17393 } __PWM6LDCONbits_t
;
17395 extern __at(0x0DAF) volatile __PWM6LDCONbits_t PWM6LDCONbits
;
17397 #define _PWM6LDCON_PWM6LDS0 0x01
17398 #define _PWM6LDCON_LDS0 0x01
17399 #define _PWM6LDCON_PWM6LDS1 0x02
17400 #define _PWM6LDCON_LDS1 0x02
17401 #define _PWM6LDCON_LDT 0x40
17402 #define _PWM6LDCON_PWM6LDM 0x40
17403 #define _PWM6LDCON_LDA 0x80
17404 #define _PWM6LDCON_PWM6LD 0x80
17406 //==============================================================================
17409 //==============================================================================
17412 extern __at(0x0DB0) __sfr PWM6OFCON
;
17418 unsigned PWM6OFS0
: 1;
17419 unsigned PWM6OFS1
: 1;
17423 unsigned PWM6OFM0
: 1;
17424 unsigned PWM6OFM1
: 1;
17434 unsigned PWM6OFMC
: 1;
17442 unsigned PWM6OFS
: 2;
17462 unsigned PWM6OFM
: 2;
17465 } __PWM6OFCONbits_t
;
17467 extern __at(0x0DB0) volatile __PWM6OFCONbits_t PWM6OFCONbits
;
17469 #define _PWM6OFCON_PWM6OFS0 0x01
17470 #define _PWM6OFCON_OFS0 0x01
17471 #define _PWM6OFCON_PWM6OFS1 0x02
17472 #define _PWM6OFCON_OFS1 0x02
17473 #define _PWM6OFCON_OFO 0x10
17474 #define _PWM6OFCON_PWM6OFMC 0x10
17475 #define _PWM6OFCON_PWM6OFM0 0x20
17476 #define _PWM6OFCON_OFM0 0x20
17477 #define _PWM6OFCON_PWM6OFM1 0x40
17478 #define _PWM6OFCON_OFM1 0x40
17480 //==============================================================================
17482 extern __at(0x0DB1) __sfr PWM11PH
;
17484 //==============================================================================
17487 extern __at(0x0DB1) __sfr PWM11PHL
;
17491 unsigned PWM11PHL0
: 1;
17492 unsigned PWM11PHL1
: 1;
17493 unsigned PWM11PHL2
: 1;
17494 unsigned PWM11PHL3
: 1;
17495 unsigned PWM11PHL4
: 1;
17496 unsigned PWM11PHL5
: 1;
17497 unsigned PWM11PHL6
: 1;
17498 unsigned PWM11PHL7
: 1;
17499 } __PWM11PHLbits_t
;
17501 extern __at(0x0DB1) volatile __PWM11PHLbits_t PWM11PHLbits
;
17503 #define _PWM11PHL0 0x01
17504 #define _PWM11PHL1 0x02
17505 #define _PWM11PHL2 0x04
17506 #define _PWM11PHL3 0x08
17507 #define _PWM11PHL4 0x10
17508 #define _PWM11PHL5 0x20
17509 #define _PWM11PHL6 0x40
17510 #define _PWM11PHL7 0x80
17512 //==============================================================================
17515 //==============================================================================
17518 extern __at(0x0DB2) __sfr PWM11PHH
;
17522 unsigned PWM11PHH0
: 1;
17523 unsigned PWM11PHH1
: 1;
17524 unsigned PWM11PHH2
: 1;
17525 unsigned PWM11PHH3
: 1;
17526 unsigned PWM11PHH4
: 1;
17527 unsigned PWM11PHH5
: 1;
17528 unsigned PWM11PHH6
: 1;
17529 unsigned PWM11PHH7
: 1;
17530 } __PWM11PHHbits_t
;
17532 extern __at(0x0DB2) volatile __PWM11PHHbits_t PWM11PHHbits
;
17534 #define _PWM11PHH0 0x01
17535 #define _PWM11PHH1 0x02
17536 #define _PWM11PHH2 0x04
17537 #define _PWM11PHH3 0x08
17538 #define _PWM11PHH4 0x10
17539 #define _PWM11PHH5 0x20
17540 #define _PWM11PHH6 0x40
17541 #define _PWM11PHH7 0x80
17543 //==============================================================================
17545 extern __at(0x0DB3) __sfr PWM11DC
;
17547 //==============================================================================
17550 extern __at(0x0DB3) __sfr PWM11DCL
;
17554 unsigned PWM11DCL0
: 1;
17555 unsigned PWM11DCL1
: 1;
17556 unsigned PWM11DCL2
: 1;
17557 unsigned PWM11DCL3
: 1;
17558 unsigned PWM11DCL4
: 1;
17559 unsigned PWM11DCL5
: 1;
17560 unsigned PWM11DCL6
: 1;
17561 unsigned PWM11DCL7
: 1;
17562 } __PWM11DCLbits_t
;
17564 extern __at(0x0DB3) volatile __PWM11DCLbits_t PWM11DCLbits
;
17566 #define _PWM11DCL0 0x01
17567 #define _PWM11DCL1 0x02
17568 #define _PWM11DCL2 0x04
17569 #define _PWM11DCL3 0x08
17570 #define _PWM11DCL4 0x10
17571 #define _PWM11DCL5 0x20
17572 #define _PWM11DCL6 0x40
17573 #define _PWM11DCL7 0x80
17575 //==============================================================================
17578 //==============================================================================
17581 extern __at(0x0DB4) __sfr PWM11DCH
;
17585 unsigned PWM11DCH0
: 1;
17586 unsigned PWM11DCH1
: 1;
17587 unsigned PWM11DCH2
: 1;
17588 unsigned PWM11DCH3
: 1;
17589 unsigned PWM11DCH4
: 1;
17590 unsigned PWM11DCH5
: 1;
17591 unsigned PWM11DCH6
: 1;
17592 unsigned PWM11DCH7
: 1;
17593 } __PWM11DCHbits_t
;
17595 extern __at(0x0DB4) volatile __PWM11DCHbits_t PWM11DCHbits
;
17597 #define _PWM11DCH0 0x01
17598 #define _PWM11DCH1 0x02
17599 #define _PWM11DCH2 0x04
17600 #define _PWM11DCH3 0x08
17601 #define _PWM11DCH4 0x10
17602 #define _PWM11DCH5 0x20
17603 #define _PWM11DCH6 0x40
17604 #define _PWM11DCH7 0x80
17606 //==============================================================================
17608 extern __at(0x0DB5) __sfr PWM11PR
;
17610 //==============================================================================
17613 extern __at(0x0DB5) __sfr PWM11PRL
;
17617 unsigned PWM11PRL0
: 1;
17618 unsigned PWM11PRL1
: 1;
17619 unsigned PWM11PRL2
: 1;
17620 unsigned PWM11PRL3
: 1;
17621 unsigned PWM11PRL4
: 1;
17622 unsigned PWM11PRL5
: 1;
17623 unsigned PWM11PRL6
: 1;
17624 unsigned PWM11PRL7
: 1;
17625 } __PWM11PRLbits_t
;
17627 extern __at(0x0DB5) volatile __PWM11PRLbits_t PWM11PRLbits
;
17629 #define _PWM11PRL0 0x01
17630 #define _PWM11PRL1 0x02
17631 #define _PWM11PRL2 0x04
17632 #define _PWM11PRL3 0x08
17633 #define _PWM11PRL4 0x10
17634 #define _PWM11PRL5 0x20
17635 #define _PWM11PRL6 0x40
17636 #define _PWM11PRL7 0x80
17638 //==============================================================================
17641 //==============================================================================
17644 extern __at(0x0DB6) __sfr PWM11PRH
;
17648 unsigned PWM11PRH0
: 1;
17649 unsigned PWM11PRH1
: 1;
17650 unsigned PWM11PRH2
: 1;
17651 unsigned PWM11PRH3
: 1;
17652 unsigned PWM11PRH4
: 1;
17653 unsigned PWM11PRH5
: 1;
17654 unsigned PWM11PRH6
: 1;
17655 unsigned PWM11PRH7
: 1;
17656 } __PWM11PRHbits_t
;
17658 extern __at(0x0DB6) volatile __PWM11PRHbits_t PWM11PRHbits
;
17660 #define _PWM11PRH0 0x01
17661 #define _PWM11PRH1 0x02
17662 #define _PWM11PRH2 0x04
17663 #define _PWM11PRH3 0x08
17664 #define _PWM11PRH4 0x10
17665 #define _PWM11PRH5 0x20
17666 #define _PWM11PRH6 0x40
17667 #define _PWM11PRH7 0x80
17669 //==============================================================================
17671 extern __at(0x0DB7) __sfr PWM11OF
;
17673 //==============================================================================
17676 extern __at(0x0DB7) __sfr PWM11OFL
;
17680 unsigned PWM11OFL0
: 1;
17681 unsigned PWM11OFL1
: 1;
17682 unsigned PWM11OFL2
: 1;
17683 unsigned PWM11OFL3
: 1;
17684 unsigned PWM11OFL4
: 1;
17685 unsigned PWM11OFL5
: 1;
17686 unsigned PWM11OFL6
: 1;
17687 unsigned PWM11OFL7
: 1;
17688 } __PWM11OFLbits_t
;
17690 extern __at(0x0DB7) volatile __PWM11OFLbits_t PWM11OFLbits
;
17692 #define _PWM11OFL0 0x01
17693 #define _PWM11OFL1 0x02
17694 #define _PWM11OFL2 0x04
17695 #define _PWM11OFL3 0x08
17696 #define _PWM11OFL4 0x10
17697 #define _PWM11OFL5 0x20
17698 #define _PWM11OFL6 0x40
17699 #define _PWM11OFL7 0x80
17701 //==============================================================================
17704 //==============================================================================
17707 extern __at(0x0DB8) __sfr PWM11OFH
;
17711 unsigned PWM11OFH0
: 1;
17712 unsigned PWM11OFH1
: 1;
17713 unsigned PWM11OFH2
: 1;
17714 unsigned PWM11OFH3
: 1;
17715 unsigned PWM11OFH4
: 1;
17716 unsigned PWM11OFH5
: 1;
17717 unsigned PWM11OFH6
: 1;
17718 unsigned PWM11OFH7
: 1;
17719 } __PWM11OFHbits_t
;
17721 extern __at(0x0DB8) volatile __PWM11OFHbits_t PWM11OFHbits
;
17723 #define _PWM11OFH0 0x01
17724 #define _PWM11OFH1 0x02
17725 #define _PWM11OFH2 0x04
17726 #define _PWM11OFH3 0x08
17727 #define _PWM11OFH4 0x10
17728 #define _PWM11OFH5 0x20
17729 #define _PWM11OFH6 0x40
17730 #define _PWM11OFH7 0x80
17732 //==============================================================================
17734 extern __at(0x0DB9) __sfr PWM11TMR
;
17736 //==============================================================================
17739 extern __at(0x0DB9) __sfr PWM11TMRL
;
17743 unsigned PWM11TMRL0
: 1;
17744 unsigned PWM11TMRL1
: 1;
17745 unsigned PWM11TMRL2
: 1;
17746 unsigned PWM11TMRL3
: 1;
17747 unsigned PWM11TMRL4
: 1;
17748 unsigned PWM11TMRL5
: 1;
17749 unsigned PWM11TMRL6
: 1;
17750 unsigned PWM11TMRL7
: 1;
17751 } __PWM11TMRLbits_t
;
17753 extern __at(0x0DB9) volatile __PWM11TMRLbits_t PWM11TMRLbits
;
17755 #define _PWM11TMRL0 0x01
17756 #define _PWM11TMRL1 0x02
17757 #define _PWM11TMRL2 0x04
17758 #define _PWM11TMRL3 0x08
17759 #define _PWM11TMRL4 0x10
17760 #define _PWM11TMRL5 0x20
17761 #define _PWM11TMRL6 0x40
17762 #define _PWM11TMRL7 0x80
17764 //==============================================================================
17767 //==============================================================================
17770 extern __at(0x0DBA) __sfr PWM11TMRH
;
17774 unsigned PWM11TMRH0
: 1;
17775 unsigned PWM11TMRH1
: 1;
17776 unsigned PWM11TMRH2
: 1;
17777 unsigned PWM11TMRH3
: 1;
17778 unsigned PWM11TMRH4
: 1;
17779 unsigned PWM11TMRH5
: 1;
17780 unsigned PWM11TMRH6
: 1;
17781 unsigned PWM11TMRH7
: 1;
17782 } __PWM11TMRHbits_t
;
17784 extern __at(0x0DBA) volatile __PWM11TMRHbits_t PWM11TMRHbits
;
17786 #define _PWM11TMRH0 0x01
17787 #define _PWM11TMRH1 0x02
17788 #define _PWM11TMRH2 0x04
17789 #define _PWM11TMRH3 0x08
17790 #define _PWM11TMRH4 0x10
17791 #define _PWM11TMRH5 0x20
17792 #define _PWM11TMRH6 0x40
17793 #define _PWM11TMRH7 0x80
17795 //==============================================================================
17798 //==============================================================================
17801 extern __at(0x0DBB) __sfr PWM11CON
;
17809 unsigned PWM11MODE0
: 1;
17810 unsigned PWM11MODE1
: 1;
17821 unsigned MODE0
: 1;
17822 unsigned MODE1
: 1;
17823 unsigned PWM11POL
: 1;
17824 unsigned PWM11OUT
: 1;
17826 unsigned PWM11EN
: 1;
17832 unsigned PWM11MODE
: 2;
17842 } __PWM11CONbits_t
;
17844 extern __at(0x0DBB) volatile __PWM11CONbits_t PWM11CONbits
;
17846 #define _PWM11CON_PWM11MODE0 0x04
17847 #define _PWM11CON_MODE0 0x04
17848 #define _PWM11CON_PWM11MODE1 0x08
17849 #define _PWM11CON_MODE1 0x08
17850 #define _PWM11CON_POL 0x10
17851 #define _PWM11CON_PWM11POL 0x10
17852 #define _PWM11CON_OUT 0x20
17853 #define _PWM11CON_PWM11OUT 0x20
17854 #define _PWM11CON_EN 0x80
17855 #define _PWM11CON_PWM11EN 0x80
17857 //==============================================================================
17860 //==============================================================================
17861 // PWM11INTCON Bits
17863 extern __at(0x0DBC) __sfr PWM11INTCON
;
17881 unsigned PWM11PRIE
: 1;
17882 unsigned PWM11DCIE
: 1;
17883 unsigned PWM11PHIE
: 1;
17884 unsigned PWM11OFIE
: 1;
17890 } __PWM11INTCONbits_t
;
17892 extern __at(0x0DBC) volatile __PWM11INTCONbits_t PWM11INTCONbits
;
17894 #define _PWM11INTCON_PRIE 0x01
17895 #define _PWM11INTCON_PWM11PRIE 0x01
17896 #define _PWM11INTCON_DCIE 0x02
17897 #define _PWM11INTCON_PWM11DCIE 0x02
17898 #define _PWM11INTCON_PHIE 0x04
17899 #define _PWM11INTCON_PWM11PHIE 0x04
17900 #define _PWM11INTCON_OFIE 0x08
17901 #define _PWM11INTCON_PWM11OFIE 0x08
17903 //==============================================================================
17906 //==============================================================================
17909 extern __at(0x0DBC) __sfr PWM11INTE
;
17927 unsigned PWM11PRIE
: 1;
17928 unsigned PWM11DCIE
: 1;
17929 unsigned PWM11PHIE
: 1;
17930 unsigned PWM11OFIE
: 1;
17936 } __PWM11INTEbits_t
;
17938 extern __at(0x0DBC) volatile __PWM11INTEbits_t PWM11INTEbits
;
17940 #define _PWM11INTE_PRIE 0x01
17941 #define _PWM11INTE_PWM11PRIE 0x01
17942 #define _PWM11INTE_DCIE 0x02
17943 #define _PWM11INTE_PWM11DCIE 0x02
17944 #define _PWM11INTE_PHIE 0x04
17945 #define _PWM11INTE_PWM11PHIE 0x04
17946 #define _PWM11INTE_OFIE 0x08
17947 #define _PWM11INTE_PWM11OFIE 0x08
17949 //==============================================================================
17952 //==============================================================================
17955 extern __at(0x0DBD) __sfr PWM11INTF
;
17973 unsigned PWM11PRIF
: 1;
17974 unsigned PWM11DCIF
: 1;
17975 unsigned PWM11PHIF
: 1;
17976 unsigned PWM11OFIF
: 1;
17982 } __PWM11INTFbits_t
;
17984 extern __at(0x0DBD) volatile __PWM11INTFbits_t PWM11INTFbits
;
17986 #define _PWM11INTF_PRIF 0x01
17987 #define _PWM11INTF_PWM11PRIF 0x01
17988 #define _PWM11INTF_DCIF 0x02
17989 #define _PWM11INTF_PWM11DCIF 0x02
17990 #define _PWM11INTF_PHIF 0x04
17991 #define _PWM11INTF_PWM11PHIF 0x04
17992 #define _PWM11INTF_OFIF 0x08
17993 #define _PWM11INTF_PWM11OFIF 0x08
17995 //==============================================================================
17998 //==============================================================================
17999 // PWM11INTFLG Bits
18001 extern __at(0x0DBD) __sfr PWM11INTFLG
;
18019 unsigned PWM11PRIF
: 1;
18020 unsigned PWM11DCIF
: 1;
18021 unsigned PWM11PHIF
: 1;
18022 unsigned PWM11OFIF
: 1;
18028 } __PWM11INTFLGbits_t
;
18030 extern __at(0x0DBD) volatile __PWM11INTFLGbits_t PWM11INTFLGbits
;
18032 #define _PWM11INTFLG_PRIF 0x01
18033 #define _PWM11INTFLG_PWM11PRIF 0x01
18034 #define _PWM11INTFLG_DCIF 0x02
18035 #define _PWM11INTFLG_PWM11DCIF 0x02
18036 #define _PWM11INTFLG_PHIF 0x04
18037 #define _PWM11INTFLG_PWM11PHIF 0x04
18038 #define _PWM11INTFLG_OFIF 0x08
18039 #define _PWM11INTFLG_PWM11OFIF 0x08
18041 //==============================================================================
18044 //==============================================================================
18045 // PWM11CLKCON Bits
18047 extern __at(0x0DBE) __sfr PWM11CLKCON
;
18053 unsigned PWM11CS0
: 1;
18054 unsigned PWM11CS1
: 1;
18055 unsigned PWM11CS2
: 1;
18057 unsigned PWM11PS0
: 1;
18058 unsigned PWM11PS1
: 1;
18059 unsigned PWM11PS2
: 1;
18083 unsigned PWM11CS
: 3;
18090 unsigned PWM11PS
: 3;
18100 } __PWM11CLKCONbits_t
;
18102 extern __at(0x0DBE) volatile __PWM11CLKCONbits_t PWM11CLKCONbits
;
18104 #define _PWM11CLKCON_PWM11CS0 0x01
18105 #define _PWM11CLKCON_CS0 0x01
18106 #define _PWM11CLKCON_PWM11CS1 0x02
18107 #define _PWM11CLKCON_CS1 0x02
18108 #define _PWM11CLKCON_PWM11CS2 0x04
18109 #define _PWM11CLKCON_CS2 0x04
18110 #define _PWM11CLKCON_PWM11PS0 0x10
18111 #define _PWM11CLKCON_PS0 0x10
18112 #define _PWM11CLKCON_PWM11PS1 0x20
18113 #define _PWM11CLKCON_PS1 0x20
18114 #define _PWM11CLKCON_PWM11PS2 0x40
18115 #define _PWM11CLKCON_PS2 0x40
18117 //==============================================================================
18120 //==============================================================================
18123 extern __at(0x0DBF) __sfr PWM11LDCON
;
18129 unsigned PWM11LDS0
: 1;
18130 unsigned PWM11LDS1
: 1;
18147 unsigned PWM11LDM
: 1;
18148 unsigned PWM11LD
: 1;
18153 unsigned PWM11LDS
: 2;
18162 } __PWM11LDCONbits_t
;
18164 extern __at(0x0DBF) volatile __PWM11LDCONbits_t PWM11LDCONbits
;
18166 #define _PWM11LDCON_PWM11LDS0 0x01
18167 #define _PWM11LDCON_LDS0 0x01
18168 #define _PWM11LDCON_PWM11LDS1 0x02
18169 #define _PWM11LDCON_LDS1 0x02
18170 #define _PWM11LDCON_LDT 0x40
18171 #define _PWM11LDCON_PWM11LDM 0x40
18172 #define _PWM11LDCON_LDA 0x80
18173 #define _PWM11LDCON_PWM11LD 0x80
18175 //==============================================================================
18178 //==============================================================================
18181 extern __at(0x0DC0) __sfr PWM11OFCON
;
18187 unsigned PWM11OFS0
: 1;
18188 unsigned PWM11OFS1
: 1;
18192 unsigned PWM11OFM0
: 1;
18193 unsigned PWM11OFM1
: 1;
18203 unsigned PWM11OFMC
: 1;
18211 unsigned PWM11OFS
: 2;
18224 unsigned PWM11OFM
: 2;
18234 } __PWM11OFCONbits_t
;
18236 extern __at(0x0DC0) volatile __PWM11OFCONbits_t PWM11OFCONbits
;
18238 #define _PWM11OFCON_PWM11OFS0 0x01
18239 #define _PWM11OFCON_OFS0 0x01
18240 #define _PWM11OFCON_PWM11OFS1 0x02
18241 #define _PWM11OFCON_OFS1 0x02
18242 #define _PWM11OFCON_OFO 0x10
18243 #define _PWM11OFCON_PWM11OFMC 0x10
18244 #define _PWM11OFCON_PWM11OFM0 0x20
18245 #define _PWM11OFCON_OFM0 0x20
18246 #define _PWM11OFCON_PWM11OFM1 0x40
18247 #define _PWM11OFCON_OFM1 0x40
18249 //==============================================================================
18252 //==============================================================================
18255 extern __at(0x0E0C) __sfr PPSLOCK
;
18259 unsigned PPSLOCKED
: 1;
18269 extern __at(0x0E0C) volatile __PPSLOCKbits_t PPSLOCKbits
;
18271 #define _PPSLOCKED 0x01
18273 //==============================================================================
18275 extern __at(0x0E0D) __sfr INTPPS
;
18276 extern __at(0x0E0E) __sfr T0CKIPPS
;
18277 extern __at(0x0E0F) __sfr T1CKIPPS
;
18278 extern __at(0x0E10) __sfr T1GPPS
;
18279 extern __at(0x0E11) __sfr T3CKIPPS
;
18280 extern __at(0x0E12) __sfr T3GPPS
;
18281 extern __at(0x0E13) __sfr T5CKIPPS
;
18282 extern __at(0x0E14) __sfr T5GPPS
;
18283 extern __at(0x0E15) __sfr T2CKIPPS
;
18284 extern __at(0x0E16) __sfr T4CKIPPS
;
18285 extern __at(0x0E17) __sfr T6CKIPPS
;
18286 extern __at(0x0E18) __sfr T8CKIPPS
;
18287 extern __at(0x0E19) __sfr CCP1PPS
;
18288 extern __at(0x0E1A) __sfr CCP2PPS
;
18289 extern __at(0x0E1B) __sfr CCP7PPS
;
18290 extern __at(0x0E1D) __sfr COG1INPPS
;
18291 extern __at(0x0E1E) __sfr COG2INPPS
;
18292 extern __at(0x0E1F) __sfr COG3INPPS
;
18293 extern __at(0x0E21) __sfr MD1CLPPS
;
18294 extern __at(0x0E22) __sfr MD1CHPPS
;
18295 extern __at(0x0E23) __sfr MD1MODPPS
;
18296 extern __at(0x0E24) __sfr MD2CLPPS
;
18297 extern __at(0x0E25) __sfr MD2CHPPS
;
18298 extern __at(0x0E26) __sfr MD2MODPPS
;
18299 extern __at(0x0E27) __sfr MD3CLPPS
;
18300 extern __at(0x0E28) __sfr MD3CHPPS
;
18301 extern __at(0x0E29) __sfr MD3MODPPS
;
18302 extern __at(0x0E2D) __sfr PRG1RPPS
;
18303 extern __at(0x0E2E) __sfr PRG1FPPS
;
18304 extern __at(0x0E2F) __sfr PRG2RPPS
;
18305 extern __at(0x0E30) __sfr PRG2FPPS
;
18306 extern __at(0x0E31) __sfr PRG3RPPS
;
18307 extern __at(0x0E32) __sfr PRG3FPPS
;
18308 extern __at(0x0E35) __sfr CLCIN0PPS
;
18309 extern __at(0x0E36) __sfr CLCIN1PPS
;
18310 extern __at(0x0E37) __sfr CLCIN2PPS
;
18311 extern __at(0x0E38) __sfr CLCIN3PPS
;
18312 extern __at(0x0E39) __sfr ADCACTPPS
;
18313 extern __at(0x0E3A) __sfr SSPCLKPPS
;
18314 extern __at(0x0E3B) __sfr SSPDATPPS
;
18315 extern __at(0x0E3C) __sfr SSPSSPPS
;
18316 extern __at(0x0E3D) __sfr RXPPS
;
18317 extern __at(0x0E3E) __sfr CKPPS
;
18318 extern __at(0x0E90) __sfr RA0PPS
;
18319 extern __at(0x0E91) __sfr RA1PPS
;
18320 extern __at(0x0E92) __sfr RA2PPS
;
18321 extern __at(0x0E93) __sfr RA3PPS
;
18322 extern __at(0x0E94) __sfr RA4PPS
;
18323 extern __at(0x0E95) __sfr RA5PPS
;
18324 extern __at(0x0E96) __sfr RA6PPS
;
18325 extern __at(0x0E97) __sfr RA7PPS
;
18326 extern __at(0x0E98) __sfr RB0PPS
;
18327 extern __at(0x0E99) __sfr RB1PPS
;
18328 extern __at(0x0E9A) __sfr RB2PPS
;
18329 extern __at(0x0E9B) __sfr RB3PPS
;
18330 extern __at(0x0E9C) __sfr RB4PPS
;
18331 extern __at(0x0E9D) __sfr RB5PPS
;
18332 extern __at(0x0E9E) __sfr RB6PPS
;
18333 extern __at(0x0E9F) __sfr RB7PPS
;
18334 extern __at(0x0EA0) __sfr RC0PPS
;
18335 extern __at(0x0EA1) __sfr RC1PPS
;
18336 extern __at(0x0EA2) __sfr RC2PPS
;
18337 extern __at(0x0EA3) __sfr RC3PPS
;
18338 extern __at(0x0EA4) __sfr RC4PPS
;
18339 extern __at(0x0EA5) __sfr RC5PPS
;
18340 extern __at(0x0EA6) __sfr RC6PPS
;
18341 extern __at(0x0EA7) __sfr RC7PPS
;
18343 //==============================================================================
18346 extern __at(0x0F0F) __sfr CLCDATA
;
18350 unsigned MCLC1OUT
: 1;
18351 unsigned MCLC2OUT
: 1;
18352 unsigned MCLC3OUT
: 1;
18353 unsigned MLC4OUT
: 1;
18360 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
18362 #define _MCLC1OUT 0x01
18363 #define _MCLC2OUT 0x02
18364 #define _MCLC3OUT 0x04
18365 #define _MLC4OUT 0x08
18367 //==============================================================================
18370 //==============================================================================
18373 extern __at(0x0F10) __sfr CLC1CON
;
18379 unsigned LC1MODE0
: 1;
18380 unsigned LC1MODE1
: 1;
18381 unsigned LC1MODE2
: 1;
18382 unsigned LC1INTN
: 1;
18383 unsigned LC1INTP
: 1;
18384 unsigned LC1OUT
: 1;
18386 unsigned LC1EN
: 1;
18391 unsigned MODE0
: 1;
18392 unsigned MODE1
: 1;
18393 unsigned MODE2
: 1;
18409 unsigned LC1MODE
: 3;
18414 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
18416 #define _CLC1CON_LC1MODE0 0x01
18417 #define _CLC1CON_MODE0 0x01
18418 #define _CLC1CON_LC1MODE1 0x02
18419 #define _CLC1CON_MODE1 0x02
18420 #define _CLC1CON_LC1MODE2 0x04
18421 #define _CLC1CON_MODE2 0x04
18422 #define _CLC1CON_LC1INTN 0x08
18423 #define _CLC1CON_INTN 0x08
18424 #define _CLC1CON_LC1INTP 0x10
18425 #define _CLC1CON_INTP 0x10
18426 #define _CLC1CON_LC1OUT 0x20
18427 #define _CLC1CON_OUT 0x20
18428 #define _CLC1CON_LC1EN 0x80
18429 #define _CLC1CON_EN 0x80
18431 //==============================================================================
18434 //==============================================================================
18437 extern __at(0x0F11) __sfr CLC1POL
;
18443 unsigned LC1G1POL
: 1;
18444 unsigned LC1G2POL
: 1;
18445 unsigned LC1G3POL
: 1;
18446 unsigned LC1G4POL
: 1;
18450 unsigned LC1POL
: 1;
18455 unsigned G1POL
: 1;
18456 unsigned G2POL
: 1;
18457 unsigned G3POL
: 1;
18458 unsigned G4POL
: 1;
18466 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
18468 #define _LC1G1POL 0x01
18469 #define _G1POL 0x01
18470 #define _LC1G2POL 0x02
18471 #define _G2POL 0x02
18472 #define _LC1G3POL 0x04
18473 #define _G3POL 0x04
18474 #define _LC1G4POL 0x08
18475 #define _G4POL 0x08
18476 #define _LC1POL 0x80
18479 //==============================================================================
18482 //==============================================================================
18485 extern __at(0x0F12) __sfr CLC1SEL0
;
18491 unsigned LC1D1S0
: 1;
18492 unsigned LC1D1S1
: 1;
18493 unsigned LC1D1S2
: 1;
18494 unsigned LC1D1S3
: 1;
18495 unsigned LC1D1S4
: 1;
18496 unsigned LC1D1S5
: 1;
18521 unsigned LC1D1S
: 6;
18524 } __CLC1SEL0bits_t
;
18526 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
18528 #define _LC1D1S0 0x01
18530 #define _LC1D1S1 0x02
18532 #define _LC1D1S2 0x04
18534 #define _LC1D1S3 0x08
18536 #define _LC1D1S4 0x10
18538 #define _LC1D1S5 0x20
18541 //==============================================================================
18544 //==============================================================================
18547 extern __at(0x0F13) __sfr CLC1SEL1
;
18553 unsigned LC1D2S0
: 1;
18554 unsigned LC1D2S1
: 1;
18555 unsigned LC1D2S2
: 1;
18556 unsigned LC1D2S3
: 1;
18557 unsigned LC1D2S4
: 1;
18558 unsigned LC1D2S5
: 1;
18577 unsigned LC1D2S
: 6;
18586 } __CLC1SEL1bits_t
;
18588 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
18590 #define _LC1D2S0 0x01
18592 #define _LC1D2S1 0x02
18594 #define _LC1D2S2 0x04
18596 #define _LC1D2S3 0x08
18598 #define _LC1D2S4 0x10
18600 #define _LC1D2S5 0x20
18603 //==============================================================================
18606 //==============================================================================
18609 extern __at(0x0F14) __sfr CLC1SEL2
;
18615 unsigned LC1D3S0
: 1;
18616 unsigned LC1D3S1
: 1;
18617 unsigned LC1D3S2
: 1;
18618 unsigned LC1D3S3
: 1;
18619 unsigned LC1D3S4
: 1;
18620 unsigned LC1D3S5
: 1;
18639 unsigned LC1D3S
: 6;
18648 } __CLC1SEL2bits_t
;
18650 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
18652 #define _LC1D3S0 0x01
18654 #define _LC1D3S1 0x02
18656 #define _LC1D3S2 0x04
18658 #define _LC1D3S3 0x08
18660 #define _LC1D3S4 0x10
18662 #define _LC1D3S5 0x20
18665 //==============================================================================
18668 //==============================================================================
18671 extern __at(0x0F15) __sfr CLC1SEL3
;
18677 unsigned LC1D4S0
: 1;
18678 unsigned LC1D4S1
: 1;
18679 unsigned LC1D4S2
: 1;
18680 unsigned LC1D4S3
: 1;
18681 unsigned LC1D4S4
: 1;
18682 unsigned LC1D4S5
: 1;
18701 unsigned LC1D4S
: 6;
18710 } __CLC1SEL3bits_t
;
18712 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
18714 #define _LC1D4S0 0x01
18716 #define _LC1D4S1 0x02
18718 #define _LC1D4S2 0x04
18720 #define _LC1D4S3 0x08
18722 #define _LC1D4S4 0x10
18724 #define _LC1D4S5 0x20
18727 //==============================================================================
18730 //==============================================================================
18733 extern __at(0x0F16) __sfr CLC1GLS0
;
18739 unsigned LC1G1D1N
: 1;
18740 unsigned LC1G1D1T
: 1;
18741 unsigned LC1G1D2N
: 1;
18742 unsigned LC1G1D2T
: 1;
18743 unsigned LC1G1D3N
: 1;
18744 unsigned LC1G1D3T
: 1;
18745 unsigned LC1G1D4N
: 1;
18746 unsigned LC1G1D4T
: 1;
18760 } __CLC1GLS0bits_t
;
18762 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
18764 #define _LC1G1D1N 0x01
18766 #define _LC1G1D1T 0x02
18768 #define _LC1G1D2N 0x04
18770 #define _LC1G1D2T 0x08
18772 #define _LC1G1D3N 0x10
18774 #define _LC1G1D3T 0x20
18776 #define _LC1G1D4N 0x40
18778 #define _LC1G1D4T 0x80
18781 //==============================================================================
18784 //==============================================================================
18787 extern __at(0x0F17) __sfr CLC1GLS1
;
18793 unsigned LC1G2D1N
: 1;
18794 unsigned LC1G2D1T
: 1;
18795 unsigned LC1G2D2N
: 1;
18796 unsigned LC1G2D2T
: 1;
18797 unsigned LC1G2D3N
: 1;
18798 unsigned LC1G2D3T
: 1;
18799 unsigned LC1G2D4N
: 1;
18800 unsigned LC1G2D4T
: 1;
18814 } __CLC1GLS1bits_t
;
18816 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
18818 #define _CLC1GLS1_LC1G2D1N 0x01
18819 #define _CLC1GLS1_D1N 0x01
18820 #define _CLC1GLS1_LC1G2D1T 0x02
18821 #define _CLC1GLS1_D1T 0x02
18822 #define _CLC1GLS1_LC1G2D2N 0x04
18823 #define _CLC1GLS1_D2N 0x04
18824 #define _CLC1GLS1_LC1G2D2T 0x08
18825 #define _CLC1GLS1_D2T 0x08
18826 #define _CLC1GLS1_LC1G2D3N 0x10
18827 #define _CLC1GLS1_D3N 0x10
18828 #define _CLC1GLS1_LC1G2D3T 0x20
18829 #define _CLC1GLS1_D3T 0x20
18830 #define _CLC1GLS1_LC1G2D4N 0x40
18831 #define _CLC1GLS1_D4N 0x40
18832 #define _CLC1GLS1_LC1G2D4T 0x80
18833 #define _CLC1GLS1_D4T 0x80
18835 //==============================================================================
18838 //==============================================================================
18841 extern __at(0x0F18) __sfr CLC1GLS2
;
18847 unsigned LC1G3D1N
: 1;
18848 unsigned LC1G3D1T
: 1;
18849 unsigned LC1G3D2N
: 1;
18850 unsigned LC1G3D2T
: 1;
18851 unsigned LC1G3D3N
: 1;
18852 unsigned LC1G3D3T
: 1;
18853 unsigned LC1G3D4N
: 1;
18854 unsigned LC1G3D4T
: 1;
18868 } __CLC1GLS2bits_t
;
18870 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
18872 #define _CLC1GLS2_LC1G3D1N 0x01
18873 #define _CLC1GLS2_D1N 0x01
18874 #define _CLC1GLS2_LC1G3D1T 0x02
18875 #define _CLC1GLS2_D1T 0x02
18876 #define _CLC1GLS2_LC1G3D2N 0x04
18877 #define _CLC1GLS2_D2N 0x04
18878 #define _CLC1GLS2_LC1G3D2T 0x08
18879 #define _CLC1GLS2_D2T 0x08
18880 #define _CLC1GLS2_LC1G3D3N 0x10
18881 #define _CLC1GLS2_D3N 0x10
18882 #define _CLC1GLS2_LC1G3D3T 0x20
18883 #define _CLC1GLS2_D3T 0x20
18884 #define _CLC1GLS2_LC1G3D4N 0x40
18885 #define _CLC1GLS2_D4N 0x40
18886 #define _CLC1GLS2_LC1G3D4T 0x80
18887 #define _CLC1GLS2_D4T 0x80
18889 //==============================================================================
18892 //==============================================================================
18895 extern __at(0x0F19) __sfr CLC1GLS3
;
18901 unsigned LC1G4D1N
: 1;
18902 unsigned LC1G4D1T
: 1;
18903 unsigned LC1G4D2N
: 1;
18904 unsigned LC1G4D2T
: 1;
18905 unsigned LC1G4D3N
: 1;
18906 unsigned LC1G4D3T
: 1;
18907 unsigned LC1G4D4N
: 1;
18908 unsigned LC1G4D4T
: 1;
18913 unsigned G4D1N
: 1;
18914 unsigned G4D1T
: 1;
18915 unsigned G4D2N
: 1;
18916 unsigned G4D2T
: 1;
18917 unsigned G4D3N
: 1;
18918 unsigned G4D3T
: 1;
18919 unsigned G4D4N
: 1;
18920 unsigned G4D4T
: 1;
18922 } __CLC1GLS3bits_t
;
18924 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
18926 #define _LC1G4D1N 0x01
18927 #define _G4D1N 0x01
18928 #define _LC1G4D1T 0x02
18929 #define _G4D1T 0x02
18930 #define _LC1G4D2N 0x04
18931 #define _G4D2N 0x04
18932 #define _LC1G4D2T 0x08
18933 #define _G4D2T 0x08
18934 #define _LC1G4D3N 0x10
18935 #define _G4D3N 0x10
18936 #define _LC1G4D3T 0x20
18937 #define _G4D3T 0x20
18938 #define _LC1G4D4N 0x40
18939 #define _G4D4N 0x40
18940 #define _LC1G4D4T 0x80
18941 #define _G4D4T 0x80
18943 //==============================================================================
18946 //==============================================================================
18949 extern __at(0x0F1A) __sfr CLC2CON
;
18955 unsigned LC2MODE0
: 1;
18956 unsigned LC2MODE1
: 1;
18957 unsigned LC2MODE2
: 1;
18958 unsigned LC2INTN
: 1;
18959 unsigned LC2INTP
: 1;
18960 unsigned LC2OUT
: 1;
18962 unsigned LC2EN
: 1;
18967 unsigned MODE0
: 1;
18968 unsigned MODE1
: 1;
18969 unsigned MODE2
: 1;
18979 unsigned LC2MODE
: 3;
18990 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
18992 #define _CLC2CON_LC2MODE0 0x01
18993 #define _CLC2CON_MODE0 0x01
18994 #define _CLC2CON_LC2MODE1 0x02
18995 #define _CLC2CON_MODE1 0x02
18996 #define _CLC2CON_LC2MODE2 0x04
18997 #define _CLC2CON_MODE2 0x04
18998 #define _CLC2CON_LC2INTN 0x08
18999 #define _CLC2CON_INTN 0x08
19000 #define _CLC2CON_LC2INTP 0x10
19001 #define _CLC2CON_INTP 0x10
19002 #define _CLC2CON_LC2OUT 0x20
19003 #define _CLC2CON_OUT 0x20
19004 #define _CLC2CON_LC2EN 0x80
19005 #define _CLC2CON_EN 0x80
19007 //==============================================================================
19010 //==============================================================================
19013 extern __at(0x0F1B) __sfr CLC2POL
;
19019 unsigned LC2G1POL
: 1;
19020 unsigned LC2G2POL
: 1;
19021 unsigned LC2G3POL
: 1;
19022 unsigned LC2G4POL
: 1;
19026 unsigned LC2POL
: 1;
19031 unsigned G1POL
: 1;
19032 unsigned G2POL
: 1;
19033 unsigned G3POL
: 1;
19034 unsigned G4POL
: 1;
19042 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
19044 #define _CLC2POL_LC2G1POL 0x01
19045 #define _CLC2POL_G1POL 0x01
19046 #define _CLC2POL_LC2G2POL 0x02
19047 #define _CLC2POL_G2POL 0x02
19048 #define _CLC2POL_LC2G3POL 0x04
19049 #define _CLC2POL_G3POL 0x04
19050 #define _CLC2POL_LC2G4POL 0x08
19051 #define _CLC2POL_G4POL 0x08
19052 #define _CLC2POL_LC2POL 0x80
19053 #define _CLC2POL_POL 0x80
19055 //==============================================================================
19058 //==============================================================================
19061 extern __at(0x0F1C) __sfr CLC2SEL0
;
19067 unsigned LC2D1S0
: 1;
19068 unsigned LC2D1S1
: 1;
19069 unsigned LC2D1S2
: 1;
19070 unsigned LC2D1S3
: 1;
19071 unsigned LC2D1S4
: 1;
19072 unsigned LC2D1S5
: 1;
19091 unsigned LC2D1S
: 6;
19100 } __CLC2SEL0bits_t
;
19102 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
19104 #define _CLC2SEL0_LC2D1S0 0x01
19105 #define _CLC2SEL0_D1S0 0x01
19106 #define _CLC2SEL0_LC2D1S1 0x02
19107 #define _CLC2SEL0_D1S1 0x02
19108 #define _CLC2SEL0_LC2D1S2 0x04
19109 #define _CLC2SEL0_D1S2 0x04
19110 #define _CLC2SEL0_LC2D1S3 0x08
19111 #define _CLC2SEL0_D1S3 0x08
19112 #define _CLC2SEL0_LC2D1S4 0x10
19113 #define _CLC2SEL0_D1S4 0x10
19114 #define _CLC2SEL0_LC2D1S5 0x20
19115 #define _CLC2SEL0_D1S5 0x20
19117 //==============================================================================
19120 //==============================================================================
19123 extern __at(0x0F1D) __sfr CLC2SEL1
;
19129 unsigned LC2D2S0
: 1;
19130 unsigned LC2D2S1
: 1;
19131 unsigned LC2D2S2
: 1;
19132 unsigned LC2D2S3
: 1;
19133 unsigned LC2D2S4
: 1;
19134 unsigned LC2D2S5
: 1;
19153 unsigned LC2D2S
: 6;
19162 } __CLC2SEL1bits_t
;
19164 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
19166 #define _CLC2SEL1_LC2D2S0 0x01
19167 #define _CLC2SEL1_D2S0 0x01
19168 #define _CLC2SEL1_LC2D2S1 0x02
19169 #define _CLC2SEL1_D2S1 0x02
19170 #define _CLC2SEL1_LC2D2S2 0x04
19171 #define _CLC2SEL1_D2S2 0x04
19172 #define _CLC2SEL1_LC2D2S3 0x08
19173 #define _CLC2SEL1_D2S3 0x08
19174 #define _CLC2SEL1_LC2D2S4 0x10
19175 #define _CLC2SEL1_D2S4 0x10
19176 #define _CLC2SEL1_LC2D2S5 0x20
19177 #define _CLC2SEL1_D2S5 0x20
19179 //==============================================================================
19182 //==============================================================================
19185 extern __at(0x0F1E) __sfr CLC2SEL2
;
19191 unsigned LC2D3S0
: 1;
19192 unsigned LC2D3S1
: 1;
19193 unsigned LC2D3S2
: 1;
19194 unsigned LC2D3S3
: 1;
19195 unsigned LC2D3S4
: 1;
19196 unsigned LC2D3S5
: 1;
19215 unsigned LC2D3S
: 6;
19224 } __CLC2SEL2bits_t
;
19226 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
19228 #define _CLC2SEL2_LC2D3S0 0x01
19229 #define _CLC2SEL2_D3S0 0x01
19230 #define _CLC2SEL2_LC2D3S1 0x02
19231 #define _CLC2SEL2_D3S1 0x02
19232 #define _CLC2SEL2_LC2D3S2 0x04
19233 #define _CLC2SEL2_D3S2 0x04
19234 #define _CLC2SEL2_LC2D3S3 0x08
19235 #define _CLC2SEL2_D3S3 0x08
19236 #define _CLC2SEL2_LC2D3S4 0x10
19237 #define _CLC2SEL2_D3S4 0x10
19238 #define _CLC2SEL2_LC2D3S5 0x20
19239 #define _CLC2SEL2_D3S5 0x20
19241 //==============================================================================
19244 //==============================================================================
19247 extern __at(0x0F1F) __sfr CLC2SEL3
;
19253 unsigned LC2D4S0
: 1;
19254 unsigned LC2D4S1
: 1;
19255 unsigned LC2D4S2
: 1;
19256 unsigned LC2D4S3
: 1;
19257 unsigned LC2D4S4
: 1;
19258 unsigned LC2D4S5
: 1;
19277 unsigned LC2D4S
: 6;
19286 } __CLC2SEL3bits_t
;
19288 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
19290 #define _CLC2SEL3_LC2D4S0 0x01
19291 #define _CLC2SEL3_D4S0 0x01
19292 #define _CLC2SEL3_LC2D4S1 0x02
19293 #define _CLC2SEL3_D4S1 0x02
19294 #define _CLC2SEL3_LC2D4S2 0x04
19295 #define _CLC2SEL3_D4S2 0x04
19296 #define _CLC2SEL3_LC2D4S3 0x08
19297 #define _CLC2SEL3_D4S3 0x08
19298 #define _CLC2SEL3_LC2D4S4 0x10
19299 #define _CLC2SEL3_D4S4 0x10
19300 #define _CLC2SEL3_LC2D4S5 0x20
19301 #define _CLC2SEL3_D4S5 0x20
19303 //==============================================================================
19306 //==============================================================================
19309 extern __at(0x0F20) __sfr CLC2GLS0
;
19315 unsigned LC2G1D1N
: 1;
19316 unsigned LC2G1D1T
: 1;
19317 unsigned LC2G1D2N
: 1;
19318 unsigned LC2G1D2T
: 1;
19319 unsigned LC2G1D3N
: 1;
19320 unsigned LC2G1D3T
: 1;
19321 unsigned LC2G1D4N
: 1;
19322 unsigned LC2G1D4T
: 1;
19336 } __CLC2GLS0bits_t
;
19338 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
19340 #define _CLC2GLS0_LC2G1D1N 0x01
19341 #define _CLC2GLS0_D1N 0x01
19342 #define _CLC2GLS0_LC2G1D1T 0x02
19343 #define _CLC2GLS0_D1T 0x02
19344 #define _CLC2GLS0_LC2G1D2N 0x04
19345 #define _CLC2GLS0_D2N 0x04
19346 #define _CLC2GLS0_LC2G1D2T 0x08
19347 #define _CLC2GLS0_D2T 0x08
19348 #define _CLC2GLS0_LC2G1D3N 0x10
19349 #define _CLC2GLS0_D3N 0x10
19350 #define _CLC2GLS0_LC2G1D3T 0x20
19351 #define _CLC2GLS0_D3T 0x20
19352 #define _CLC2GLS0_LC2G1D4N 0x40
19353 #define _CLC2GLS0_D4N 0x40
19354 #define _CLC2GLS0_LC2G1D4T 0x80
19355 #define _CLC2GLS0_D4T 0x80
19357 //==============================================================================
19360 //==============================================================================
19363 extern __at(0x0F21) __sfr CLC2GLS1
;
19369 unsigned LC2G2D1N
: 1;
19370 unsigned LC2G2D1T
: 1;
19371 unsigned LC2G2D2N
: 1;
19372 unsigned LC2G2D2T
: 1;
19373 unsigned LC2G2D3N
: 1;
19374 unsigned LC2G2D3T
: 1;
19375 unsigned LC2G2D4N
: 1;
19376 unsigned LC2G2D4T
: 1;
19390 } __CLC2GLS1bits_t
;
19392 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
19394 #define _CLC2GLS1_LC2G2D1N 0x01
19395 #define _CLC2GLS1_D1N 0x01
19396 #define _CLC2GLS1_LC2G2D1T 0x02
19397 #define _CLC2GLS1_D1T 0x02
19398 #define _CLC2GLS1_LC2G2D2N 0x04
19399 #define _CLC2GLS1_D2N 0x04
19400 #define _CLC2GLS1_LC2G2D2T 0x08
19401 #define _CLC2GLS1_D2T 0x08
19402 #define _CLC2GLS1_LC2G2D3N 0x10
19403 #define _CLC2GLS1_D3N 0x10
19404 #define _CLC2GLS1_LC2G2D3T 0x20
19405 #define _CLC2GLS1_D3T 0x20
19406 #define _CLC2GLS1_LC2G2D4N 0x40
19407 #define _CLC2GLS1_D4N 0x40
19408 #define _CLC2GLS1_LC2G2D4T 0x80
19409 #define _CLC2GLS1_D4T 0x80
19411 //==============================================================================
19414 //==============================================================================
19417 extern __at(0x0F22) __sfr CLC2GLS2
;
19423 unsigned LC2G3D1N
: 1;
19424 unsigned LC2G3D1T
: 1;
19425 unsigned LC2G3D2N
: 1;
19426 unsigned LC2G3D2T
: 1;
19427 unsigned LC2G3D3N
: 1;
19428 unsigned LC2G3D3T
: 1;
19429 unsigned LC2G3D4N
: 1;
19430 unsigned LC2G3D4T
: 1;
19444 } __CLC2GLS2bits_t
;
19446 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
19448 #define _CLC2GLS2_LC2G3D1N 0x01
19449 #define _CLC2GLS2_D1N 0x01
19450 #define _CLC2GLS2_LC2G3D1T 0x02
19451 #define _CLC2GLS2_D1T 0x02
19452 #define _CLC2GLS2_LC2G3D2N 0x04
19453 #define _CLC2GLS2_D2N 0x04
19454 #define _CLC2GLS2_LC2G3D2T 0x08
19455 #define _CLC2GLS2_D2T 0x08
19456 #define _CLC2GLS2_LC2G3D3N 0x10
19457 #define _CLC2GLS2_D3N 0x10
19458 #define _CLC2GLS2_LC2G3D3T 0x20
19459 #define _CLC2GLS2_D3T 0x20
19460 #define _CLC2GLS2_LC2G3D4N 0x40
19461 #define _CLC2GLS2_D4N 0x40
19462 #define _CLC2GLS2_LC2G3D4T 0x80
19463 #define _CLC2GLS2_D4T 0x80
19465 //==============================================================================
19468 //==============================================================================
19471 extern __at(0x0F23) __sfr CLC2GLS3
;
19477 unsigned LC2G4D1N
: 1;
19478 unsigned LC2G4D1T
: 1;
19479 unsigned LC2G4D2N
: 1;
19480 unsigned LC2G4D2T
: 1;
19481 unsigned LC2G4D3N
: 1;
19482 unsigned LC2G4D3T
: 1;
19483 unsigned LC2G4D4N
: 1;
19484 unsigned LC2G4D4T
: 1;
19489 unsigned G4D1N
: 1;
19490 unsigned G4D1T
: 1;
19491 unsigned G4D2N
: 1;
19492 unsigned G4D2T
: 1;
19493 unsigned G4D3N
: 1;
19494 unsigned G4D3T
: 1;
19495 unsigned G4D4N
: 1;
19496 unsigned G4D4T
: 1;
19498 } __CLC2GLS3bits_t
;
19500 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
19502 #define _CLC2GLS3_LC2G4D1N 0x01
19503 #define _CLC2GLS3_G4D1N 0x01
19504 #define _CLC2GLS3_LC2G4D1T 0x02
19505 #define _CLC2GLS3_G4D1T 0x02
19506 #define _CLC2GLS3_LC2G4D2N 0x04
19507 #define _CLC2GLS3_G4D2N 0x04
19508 #define _CLC2GLS3_LC2G4D2T 0x08
19509 #define _CLC2GLS3_G4D2T 0x08
19510 #define _CLC2GLS3_LC2G4D3N 0x10
19511 #define _CLC2GLS3_G4D3N 0x10
19512 #define _CLC2GLS3_LC2G4D3T 0x20
19513 #define _CLC2GLS3_G4D3T 0x20
19514 #define _CLC2GLS3_LC2G4D4N 0x40
19515 #define _CLC2GLS3_G4D4N 0x40
19516 #define _CLC2GLS3_LC2G4D4T 0x80
19517 #define _CLC2GLS3_G4D4T 0x80
19519 //==============================================================================
19522 //==============================================================================
19525 extern __at(0x0F24) __sfr CLC3CON
;
19531 unsigned LC3MODE0
: 1;
19532 unsigned LC3MODE1
: 1;
19533 unsigned LC3MODE2
: 1;
19534 unsigned LC3INTN
: 1;
19535 unsigned LC3INTP
: 1;
19536 unsigned LC3OUT
: 1;
19538 unsigned LC3EN
: 1;
19543 unsigned MODE0
: 1;
19544 unsigned MODE1
: 1;
19545 unsigned MODE2
: 1;
19555 unsigned LC3MODE
: 3;
19566 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
19568 #define _CLC3CON_LC3MODE0 0x01
19569 #define _CLC3CON_MODE0 0x01
19570 #define _CLC3CON_LC3MODE1 0x02
19571 #define _CLC3CON_MODE1 0x02
19572 #define _CLC3CON_LC3MODE2 0x04
19573 #define _CLC3CON_MODE2 0x04
19574 #define _CLC3CON_LC3INTN 0x08
19575 #define _CLC3CON_INTN 0x08
19576 #define _CLC3CON_LC3INTP 0x10
19577 #define _CLC3CON_INTP 0x10
19578 #define _CLC3CON_LC3OUT 0x20
19579 #define _CLC3CON_OUT 0x20
19580 #define _CLC3CON_LC3EN 0x80
19581 #define _CLC3CON_EN 0x80
19583 //==============================================================================
19586 //==============================================================================
19589 extern __at(0x0F25) __sfr CLC3POL
;
19595 unsigned LC3G1POL
: 1;
19596 unsigned LC3G2POL
: 1;
19597 unsigned LC3G3POL
: 1;
19598 unsigned LC3G4POL
: 1;
19602 unsigned LC3POL
: 1;
19607 unsigned G1POL
: 1;
19608 unsigned G2POL
: 1;
19609 unsigned G3POL
: 1;
19610 unsigned G4POL
: 1;
19618 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
19620 #define _CLC3POL_LC3G1POL 0x01
19621 #define _CLC3POL_G1POL 0x01
19622 #define _CLC3POL_LC3G2POL 0x02
19623 #define _CLC3POL_G2POL 0x02
19624 #define _CLC3POL_LC3G3POL 0x04
19625 #define _CLC3POL_G3POL 0x04
19626 #define _CLC3POL_LC3G4POL 0x08
19627 #define _CLC3POL_G4POL 0x08
19628 #define _CLC3POL_LC3POL 0x80
19629 #define _CLC3POL_POL 0x80
19631 //==============================================================================
19634 //==============================================================================
19637 extern __at(0x0F26) __sfr CLC3SEL0
;
19643 unsigned LC3D1S0
: 1;
19644 unsigned LC3D1S1
: 1;
19645 unsigned LC3D1S2
: 1;
19646 unsigned LC3D1S3
: 1;
19647 unsigned LC3D1S4
: 1;
19648 unsigned LC3D1S5
: 1;
19673 unsigned LC3D1S
: 6;
19676 } __CLC3SEL0bits_t
;
19678 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
19680 #define _CLC3SEL0_LC3D1S0 0x01
19681 #define _CLC3SEL0_D1S0 0x01
19682 #define _CLC3SEL0_LC3D1S1 0x02
19683 #define _CLC3SEL0_D1S1 0x02
19684 #define _CLC3SEL0_LC3D1S2 0x04
19685 #define _CLC3SEL0_D1S2 0x04
19686 #define _CLC3SEL0_LC3D1S3 0x08
19687 #define _CLC3SEL0_D1S3 0x08
19688 #define _CLC3SEL0_LC3D1S4 0x10
19689 #define _CLC3SEL0_D1S4 0x10
19690 #define _CLC3SEL0_LC3D1S5 0x20
19691 #define _CLC3SEL0_D1S5 0x20
19693 //==============================================================================
19696 //==============================================================================
19699 extern __at(0x0F27) __sfr CLC3SEL1
;
19705 unsigned LC3D2S0
: 1;
19706 unsigned LC3D2S1
: 1;
19707 unsigned LC3D2S2
: 1;
19708 unsigned LC3D2S3
: 1;
19709 unsigned LC3D2S4
: 1;
19710 unsigned LC3D2S5
: 1;
19729 unsigned LC3D2S
: 6;
19738 } __CLC3SEL1bits_t
;
19740 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
19742 #define _CLC3SEL1_LC3D2S0 0x01
19743 #define _CLC3SEL1_D2S0 0x01
19744 #define _CLC3SEL1_LC3D2S1 0x02
19745 #define _CLC3SEL1_D2S1 0x02
19746 #define _CLC3SEL1_LC3D2S2 0x04
19747 #define _CLC3SEL1_D2S2 0x04
19748 #define _CLC3SEL1_LC3D2S3 0x08
19749 #define _CLC3SEL1_D2S3 0x08
19750 #define _CLC3SEL1_LC3D2S4 0x10
19751 #define _CLC3SEL1_D2S4 0x10
19752 #define _CLC3SEL1_LC3D2S5 0x20
19753 #define _CLC3SEL1_D2S5 0x20
19755 //==============================================================================
19758 //==============================================================================
19761 extern __at(0x0F28) __sfr CLC3SEL2
;
19767 unsigned LC3D3S0
: 1;
19768 unsigned LC3D3S1
: 1;
19769 unsigned LC3D3S2
: 1;
19770 unsigned LC3D3S3
: 1;
19771 unsigned LC3D3S4
: 1;
19772 unsigned LC3D3S5
: 1;
19797 unsigned LC3D3S
: 6;
19800 } __CLC3SEL2bits_t
;
19802 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
19804 #define _CLC3SEL2_LC3D3S0 0x01
19805 #define _CLC3SEL2_D3S0 0x01
19806 #define _CLC3SEL2_LC3D3S1 0x02
19807 #define _CLC3SEL2_D3S1 0x02
19808 #define _CLC3SEL2_LC3D3S2 0x04
19809 #define _CLC3SEL2_D3S2 0x04
19810 #define _CLC3SEL2_LC3D3S3 0x08
19811 #define _CLC3SEL2_D3S3 0x08
19812 #define _CLC3SEL2_LC3D3S4 0x10
19813 #define _CLC3SEL2_D3S4 0x10
19814 #define _CLC3SEL2_LC3D3S5 0x20
19815 #define _CLC3SEL2_D3S5 0x20
19817 //==============================================================================
19820 //==============================================================================
19823 extern __at(0x0F29) __sfr CLC3SEL3
;
19829 unsigned LC3D4S0
: 1;
19830 unsigned LC3D4S1
: 1;
19831 unsigned LC3D4S2
: 1;
19832 unsigned LC3D4S3
: 1;
19833 unsigned LC3D4S4
: 1;
19834 unsigned LC3D4S5
: 1;
19859 unsigned LC3D4S
: 6;
19862 } __CLC3SEL3bits_t
;
19864 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
19866 #define _CLC3SEL3_LC3D4S0 0x01
19867 #define _CLC3SEL3_D4S0 0x01
19868 #define _CLC3SEL3_LC3D4S1 0x02
19869 #define _CLC3SEL3_D4S1 0x02
19870 #define _CLC3SEL3_LC3D4S2 0x04
19871 #define _CLC3SEL3_D4S2 0x04
19872 #define _CLC3SEL3_LC3D4S3 0x08
19873 #define _CLC3SEL3_D4S3 0x08
19874 #define _CLC3SEL3_LC3D4S4 0x10
19875 #define _CLC3SEL3_D4S4 0x10
19876 #define _CLC3SEL3_LC3D4S5 0x20
19877 #define _CLC3SEL3_D4S5 0x20
19879 //==============================================================================
19882 //==============================================================================
19885 extern __at(0x0F2A) __sfr CLC3GLS0
;
19891 unsigned LC3G1D1N
: 1;
19892 unsigned LC3G1D1T
: 1;
19893 unsigned LC3G1D2N
: 1;
19894 unsigned LC3G1D2T
: 1;
19895 unsigned LC3G1D3N
: 1;
19896 unsigned LC3G1D3T
: 1;
19897 unsigned LC3G1D4N
: 1;
19898 unsigned LC3G1D4T
: 1;
19912 } __CLC3GLS0bits_t
;
19914 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
19916 #define _CLC3GLS0_LC3G1D1N 0x01
19917 #define _CLC3GLS0_D1N 0x01
19918 #define _CLC3GLS0_LC3G1D1T 0x02
19919 #define _CLC3GLS0_D1T 0x02
19920 #define _CLC3GLS0_LC3G1D2N 0x04
19921 #define _CLC3GLS0_D2N 0x04
19922 #define _CLC3GLS0_LC3G1D2T 0x08
19923 #define _CLC3GLS0_D2T 0x08
19924 #define _CLC3GLS0_LC3G1D3N 0x10
19925 #define _CLC3GLS0_D3N 0x10
19926 #define _CLC3GLS0_LC3G1D3T 0x20
19927 #define _CLC3GLS0_D3T 0x20
19928 #define _CLC3GLS0_LC3G1D4N 0x40
19929 #define _CLC3GLS0_D4N 0x40
19930 #define _CLC3GLS0_LC3G1D4T 0x80
19931 #define _CLC3GLS0_D4T 0x80
19933 //==============================================================================
19936 //==============================================================================
19939 extern __at(0x0F2B) __sfr CLC3GLS1
;
19945 unsigned LC3G2D1N
: 1;
19946 unsigned LC3G2D1T
: 1;
19947 unsigned LC3G2D2N
: 1;
19948 unsigned LC3G2D2T
: 1;
19949 unsigned LC3G2D3N
: 1;
19950 unsigned LC3G2D3T
: 1;
19951 unsigned LC3G2D4N
: 1;
19952 unsigned LC3G2D4T
: 1;
19966 } __CLC3GLS1bits_t
;
19968 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
19970 #define _CLC3GLS1_LC3G2D1N 0x01
19971 #define _CLC3GLS1_D1N 0x01
19972 #define _CLC3GLS1_LC3G2D1T 0x02
19973 #define _CLC3GLS1_D1T 0x02
19974 #define _CLC3GLS1_LC3G2D2N 0x04
19975 #define _CLC3GLS1_D2N 0x04
19976 #define _CLC3GLS1_LC3G2D2T 0x08
19977 #define _CLC3GLS1_D2T 0x08
19978 #define _CLC3GLS1_LC3G2D3N 0x10
19979 #define _CLC3GLS1_D3N 0x10
19980 #define _CLC3GLS1_LC3G2D3T 0x20
19981 #define _CLC3GLS1_D3T 0x20
19982 #define _CLC3GLS1_LC3G2D4N 0x40
19983 #define _CLC3GLS1_D4N 0x40
19984 #define _CLC3GLS1_LC3G2D4T 0x80
19985 #define _CLC3GLS1_D4T 0x80
19987 //==============================================================================
19990 //==============================================================================
19993 extern __at(0x0F2C) __sfr CLC3GLS2
;
19999 unsigned LC3G3D1N
: 1;
20000 unsigned LC3G3D1T
: 1;
20001 unsigned LC3G3D2N
: 1;
20002 unsigned LC3G3D2T
: 1;
20003 unsigned LC3G3D3N
: 1;
20004 unsigned LC3G3D3T
: 1;
20005 unsigned LC3G3D4N
: 1;
20006 unsigned LC3G3D4T
: 1;
20020 } __CLC3GLS2bits_t
;
20022 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
20024 #define _CLC3GLS2_LC3G3D1N 0x01
20025 #define _CLC3GLS2_D1N 0x01
20026 #define _CLC3GLS2_LC3G3D1T 0x02
20027 #define _CLC3GLS2_D1T 0x02
20028 #define _CLC3GLS2_LC3G3D2N 0x04
20029 #define _CLC3GLS2_D2N 0x04
20030 #define _CLC3GLS2_LC3G3D2T 0x08
20031 #define _CLC3GLS2_D2T 0x08
20032 #define _CLC3GLS2_LC3G3D3N 0x10
20033 #define _CLC3GLS2_D3N 0x10
20034 #define _CLC3GLS2_LC3G3D3T 0x20
20035 #define _CLC3GLS2_D3T 0x20
20036 #define _CLC3GLS2_LC3G3D4N 0x40
20037 #define _CLC3GLS2_D4N 0x40
20038 #define _CLC3GLS2_LC3G3D4T 0x80
20039 #define _CLC3GLS2_D4T 0x80
20041 //==============================================================================
20044 //==============================================================================
20047 extern __at(0x0F2D) __sfr CLC3GLS3
;
20053 unsigned LC3G4D1N
: 1;
20054 unsigned LC3G4D1T
: 1;
20055 unsigned LC3G4D2N
: 1;
20056 unsigned LC3G4D2T
: 1;
20057 unsigned LC3G4D3N
: 1;
20058 unsigned LC3G4D3T
: 1;
20059 unsigned LC3G4D4N
: 1;
20060 unsigned LC3G4D4T
: 1;
20065 unsigned G4D1N
: 1;
20066 unsigned G4D1T
: 1;
20067 unsigned G4D2N
: 1;
20068 unsigned G4D2T
: 1;
20069 unsigned G4D3N
: 1;
20070 unsigned G4D3T
: 1;
20071 unsigned G4D4N
: 1;
20072 unsigned G4D4T
: 1;
20074 } __CLC3GLS3bits_t
;
20076 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
20078 #define _CLC3GLS3_LC3G4D1N 0x01
20079 #define _CLC3GLS3_G4D1N 0x01
20080 #define _CLC3GLS3_LC3G4D1T 0x02
20081 #define _CLC3GLS3_G4D1T 0x02
20082 #define _CLC3GLS3_LC3G4D2N 0x04
20083 #define _CLC3GLS3_G4D2N 0x04
20084 #define _CLC3GLS3_LC3G4D2T 0x08
20085 #define _CLC3GLS3_G4D2T 0x08
20086 #define _CLC3GLS3_LC3G4D3N 0x10
20087 #define _CLC3GLS3_G4D3N 0x10
20088 #define _CLC3GLS3_LC3G4D3T 0x20
20089 #define _CLC3GLS3_G4D3T 0x20
20090 #define _CLC3GLS3_LC3G4D4N 0x40
20091 #define _CLC3GLS3_G4D4N 0x40
20092 #define _CLC3GLS3_LC3G4D4T 0x80
20093 #define _CLC3GLS3_G4D4T 0x80
20095 //==============================================================================
20098 //==============================================================================
20101 extern __at(0x0F2E) __sfr CLC4CON
;
20107 unsigned LC4MODE0
: 1;
20108 unsigned LC4MODE1
: 1;
20109 unsigned LC4MODE2
: 1;
20110 unsigned LC4INTN
: 1;
20111 unsigned LC4INTP
: 1;
20112 unsigned LC4OUT
: 1;
20114 unsigned LC4EN
: 1;
20119 unsigned MODE0
: 1;
20120 unsigned MODE1
: 1;
20121 unsigned MODE2
: 1;
20137 unsigned LC4MODE
: 3;
20142 extern __at(0x0F2E) volatile __CLC4CONbits_t CLC4CONbits
;
20144 #define _CLC4CON_LC4MODE0 0x01
20145 #define _CLC4CON_MODE0 0x01
20146 #define _CLC4CON_LC4MODE1 0x02
20147 #define _CLC4CON_MODE1 0x02
20148 #define _CLC4CON_LC4MODE2 0x04
20149 #define _CLC4CON_MODE2 0x04
20150 #define _CLC4CON_LC4INTN 0x08
20151 #define _CLC4CON_INTN 0x08
20152 #define _CLC4CON_LC4INTP 0x10
20153 #define _CLC4CON_INTP 0x10
20154 #define _CLC4CON_LC4OUT 0x20
20155 #define _CLC4CON_OUT 0x20
20156 #define _CLC4CON_LC4EN 0x80
20157 #define _CLC4CON_EN 0x80
20159 //==============================================================================
20162 //==============================================================================
20165 extern __at(0x0F2F) __sfr CLC4POL
;
20171 unsigned LC4G1POL
: 1;
20172 unsigned LC4G2POL
: 1;
20173 unsigned LC4G3POL
: 1;
20174 unsigned LC4G4POL
: 1;
20178 unsigned LC4POL
: 1;
20183 unsigned G1POL
: 1;
20184 unsigned G2POL
: 1;
20185 unsigned G3POL
: 1;
20186 unsigned G4POL
: 1;
20194 extern __at(0x0F2F) volatile __CLC4POLbits_t CLC4POLbits
;
20196 #define _CLC4POL_LC4G1POL 0x01
20197 #define _CLC4POL_G1POL 0x01
20198 #define _CLC4POL_LC4G2POL 0x02
20199 #define _CLC4POL_G2POL 0x02
20200 #define _CLC4POL_LC4G3POL 0x04
20201 #define _CLC4POL_G3POL 0x04
20202 #define _CLC4POL_LC4G4POL 0x08
20203 #define _CLC4POL_G4POL 0x08
20204 #define _CLC4POL_LC4POL 0x80
20205 #define _CLC4POL_POL 0x80
20207 //==============================================================================
20210 //==============================================================================
20213 extern __at(0x0F30) __sfr CLC4SEL0
;
20219 unsigned LC4D1S0
: 1;
20220 unsigned LC4D1S1
: 1;
20221 unsigned LC4D1S2
: 1;
20222 unsigned LC4D1S3
: 1;
20223 unsigned LC4D1S4
: 1;
20224 unsigned LC4D1S5
: 1;
20243 unsigned LC4D1S
: 6;
20252 } __CLC4SEL0bits_t
;
20254 extern __at(0x0F30) volatile __CLC4SEL0bits_t CLC4SEL0bits
;
20256 #define _CLC4SEL0_LC4D1S0 0x01
20257 #define _CLC4SEL0_D1S0 0x01
20258 #define _CLC4SEL0_LC4D1S1 0x02
20259 #define _CLC4SEL0_D1S1 0x02
20260 #define _CLC4SEL0_LC4D1S2 0x04
20261 #define _CLC4SEL0_D1S2 0x04
20262 #define _CLC4SEL0_LC4D1S3 0x08
20263 #define _CLC4SEL0_D1S3 0x08
20264 #define _CLC4SEL0_LC4D1S4 0x10
20265 #define _CLC4SEL0_D1S4 0x10
20266 #define _CLC4SEL0_LC4D1S5 0x20
20267 #define _CLC4SEL0_D1S5 0x20
20269 //==============================================================================
20272 //==============================================================================
20275 extern __at(0x0F31) __sfr CLC4SEL1
;
20281 unsigned LC4D2S0
: 1;
20282 unsigned LC4D2S1
: 1;
20283 unsigned LC4D2S2
: 1;
20284 unsigned LC4D2S3
: 1;
20285 unsigned LC4D2S4
: 1;
20286 unsigned LC4D2S5
: 1;
20305 unsigned LC4D2S
: 6;
20314 } __CLC4SEL1bits_t
;
20316 extern __at(0x0F31) volatile __CLC4SEL1bits_t CLC4SEL1bits
;
20318 #define _CLC4SEL1_LC4D2S0 0x01
20319 #define _CLC4SEL1_D2S0 0x01
20320 #define _CLC4SEL1_LC4D2S1 0x02
20321 #define _CLC4SEL1_D2S1 0x02
20322 #define _CLC4SEL1_LC4D2S2 0x04
20323 #define _CLC4SEL1_D2S2 0x04
20324 #define _CLC4SEL1_LC4D2S3 0x08
20325 #define _CLC4SEL1_D2S3 0x08
20326 #define _CLC4SEL1_LC4D2S4 0x10
20327 #define _CLC4SEL1_D2S4 0x10
20328 #define _CLC4SEL1_LC4D2S5 0x20
20329 #define _CLC4SEL1_D2S5 0x20
20331 //==============================================================================
20334 //==============================================================================
20337 extern __at(0x0F32) __sfr CLC4SEL2
;
20343 unsigned LC4D3S0
: 1;
20344 unsigned LC4D3S1
: 1;
20345 unsigned LC4D3S2
: 1;
20346 unsigned LC4D3S3
: 1;
20347 unsigned LC4D3S4
: 1;
20348 unsigned LC4D3S5
: 1;
20373 unsigned LC4D3S
: 6;
20376 } __CLC4SEL2bits_t
;
20378 extern __at(0x0F32) volatile __CLC4SEL2bits_t CLC4SEL2bits
;
20380 #define _CLC4SEL2_LC4D3S0 0x01
20381 #define _CLC4SEL2_D3S0 0x01
20382 #define _CLC4SEL2_LC4D3S1 0x02
20383 #define _CLC4SEL2_D3S1 0x02
20384 #define _CLC4SEL2_LC4D3S2 0x04
20385 #define _CLC4SEL2_D3S2 0x04
20386 #define _CLC4SEL2_LC4D3S3 0x08
20387 #define _CLC4SEL2_D3S3 0x08
20388 #define _CLC4SEL2_LC4D3S4 0x10
20389 #define _CLC4SEL2_D3S4 0x10
20390 #define _CLC4SEL2_LC4D3S5 0x20
20391 #define _CLC4SEL2_D3S5 0x20
20393 //==============================================================================
20396 //==============================================================================
20399 extern __at(0x0F33) __sfr CLC4SEL3
;
20405 unsigned LC4D4S0
: 1;
20406 unsigned LC4D4S1
: 1;
20407 unsigned LC4D4S2
: 1;
20408 unsigned LC4D4S3
: 1;
20409 unsigned LC4D4S4
: 1;
20410 unsigned LC4D4S5
: 1;
20435 unsigned LC4D4S
: 6;
20438 } __CLC4SEL3bits_t
;
20440 extern __at(0x0F33) volatile __CLC4SEL3bits_t CLC4SEL3bits
;
20442 #define _CLC4SEL3_LC4D4S0 0x01
20443 #define _CLC4SEL3_D4S0 0x01
20444 #define _CLC4SEL3_LC4D4S1 0x02
20445 #define _CLC4SEL3_D4S1 0x02
20446 #define _CLC4SEL3_LC4D4S2 0x04
20447 #define _CLC4SEL3_D4S2 0x04
20448 #define _CLC4SEL3_LC4D4S3 0x08
20449 #define _CLC4SEL3_D4S3 0x08
20450 #define _CLC4SEL3_LC4D4S4 0x10
20451 #define _CLC4SEL3_D4S4 0x10
20452 #define _CLC4SEL3_LC4D4S5 0x20
20453 #define _CLC4SEL3_D4S5 0x20
20455 //==============================================================================
20458 //==============================================================================
20461 extern __at(0x0F34) __sfr CLC4GLS0
;
20467 unsigned LC4G1D1N
: 1;
20468 unsigned LC4G1D1T
: 1;
20469 unsigned LC4G1D2N
: 1;
20470 unsigned LC4G1D2T
: 1;
20471 unsigned LC4G1D3N
: 1;
20472 unsigned LC4G1D3T
: 1;
20473 unsigned LC4G1D4N
: 1;
20474 unsigned LC4G1D4T
: 1;
20488 } __CLC4GLS0bits_t
;
20490 extern __at(0x0F34) volatile __CLC4GLS0bits_t CLC4GLS0bits
;
20492 #define _CLC4GLS0_LC4G1D1N 0x01
20493 #define _CLC4GLS0_D1N 0x01
20494 #define _CLC4GLS0_LC4G1D1T 0x02
20495 #define _CLC4GLS0_D1T 0x02
20496 #define _CLC4GLS0_LC4G1D2N 0x04
20497 #define _CLC4GLS0_D2N 0x04
20498 #define _CLC4GLS0_LC4G1D2T 0x08
20499 #define _CLC4GLS0_D2T 0x08
20500 #define _CLC4GLS0_LC4G1D3N 0x10
20501 #define _CLC4GLS0_D3N 0x10
20502 #define _CLC4GLS0_LC4G1D3T 0x20
20503 #define _CLC4GLS0_D3T 0x20
20504 #define _CLC4GLS0_LC4G1D4N 0x40
20505 #define _CLC4GLS0_D4N 0x40
20506 #define _CLC4GLS0_LC4G1D4T 0x80
20507 #define _CLC4GLS0_D4T 0x80
20509 //==============================================================================
20512 //==============================================================================
20515 extern __at(0x0F35) __sfr CLC4GLS1
;
20521 unsigned LC4G2D1N
: 1;
20522 unsigned LC4G2D1T
: 1;
20523 unsigned LC4G2D2N
: 1;
20524 unsigned LC4G2D2T
: 1;
20525 unsigned LC4G2D3N
: 1;
20526 unsigned LC4G2D3T
: 1;
20527 unsigned LC4G2D4N
: 1;
20528 unsigned LC4G2D4T
: 1;
20542 } __CLC4GLS1bits_t
;
20544 extern __at(0x0F35) volatile __CLC4GLS1bits_t CLC4GLS1bits
;
20546 #define _CLC4GLS1_LC4G2D1N 0x01
20547 #define _CLC4GLS1_D1N 0x01
20548 #define _CLC4GLS1_LC4G2D1T 0x02
20549 #define _CLC4GLS1_D1T 0x02
20550 #define _CLC4GLS1_LC4G2D2N 0x04
20551 #define _CLC4GLS1_D2N 0x04
20552 #define _CLC4GLS1_LC4G2D2T 0x08
20553 #define _CLC4GLS1_D2T 0x08
20554 #define _CLC4GLS1_LC4G2D3N 0x10
20555 #define _CLC4GLS1_D3N 0x10
20556 #define _CLC4GLS1_LC4G2D3T 0x20
20557 #define _CLC4GLS1_D3T 0x20
20558 #define _CLC4GLS1_LC4G2D4N 0x40
20559 #define _CLC4GLS1_D4N 0x40
20560 #define _CLC4GLS1_LC4G2D4T 0x80
20561 #define _CLC4GLS1_D4T 0x80
20563 //==============================================================================
20566 //==============================================================================
20569 extern __at(0x0F36) __sfr CLC4GLS2
;
20575 unsigned LC4G3D1N
: 1;
20576 unsigned LC4G3D1T
: 1;
20577 unsigned LC4G3D2N
: 1;
20578 unsigned LC4G3D2T
: 1;
20579 unsigned LC4G3D3N
: 1;
20580 unsigned LC4G3D3T
: 1;
20581 unsigned LC4G3D4N
: 1;
20582 unsigned LC4G3D4T
: 1;
20596 } __CLC4GLS2bits_t
;
20598 extern __at(0x0F36) volatile __CLC4GLS2bits_t CLC4GLS2bits
;
20600 #define _CLC4GLS2_LC4G3D1N 0x01
20601 #define _CLC4GLS2_D1N 0x01
20602 #define _CLC4GLS2_LC4G3D1T 0x02
20603 #define _CLC4GLS2_D1T 0x02
20604 #define _CLC4GLS2_LC4G3D2N 0x04
20605 #define _CLC4GLS2_D2N 0x04
20606 #define _CLC4GLS2_LC4G3D2T 0x08
20607 #define _CLC4GLS2_D2T 0x08
20608 #define _CLC4GLS2_LC4G3D3N 0x10
20609 #define _CLC4GLS2_D3N 0x10
20610 #define _CLC4GLS2_LC4G3D3T 0x20
20611 #define _CLC4GLS2_D3T 0x20
20612 #define _CLC4GLS2_LC4G3D4N 0x40
20613 #define _CLC4GLS2_D4N 0x40
20614 #define _CLC4GLS2_LC4G3D4T 0x80
20615 #define _CLC4GLS2_D4T 0x80
20617 //==============================================================================
20620 //==============================================================================
20623 extern __at(0x0F37) __sfr CLC4GLS3
;
20629 unsigned LC4G4D1N
: 1;
20630 unsigned LC4G4D1T
: 1;
20631 unsigned LC4G4D2N
: 1;
20632 unsigned LC4G4D2T
: 1;
20633 unsigned LC4G4D3N
: 1;
20634 unsigned LC4G4D3T
: 1;
20635 unsigned LC4G4D4N
: 1;
20636 unsigned LC4G4D4T
: 1;
20641 unsigned G4D1N
: 1;
20642 unsigned G4D1T
: 1;
20643 unsigned G4D2N
: 1;
20644 unsigned G4D2T
: 1;
20645 unsigned G4D3N
: 1;
20646 unsigned G4D3T
: 1;
20647 unsigned G4D4N
: 1;
20648 unsigned G4D4T
: 1;
20650 } __CLC4GLS3bits_t
;
20652 extern __at(0x0F37) volatile __CLC4GLS3bits_t CLC4GLS3bits
;
20654 #define _CLC4GLS3_LC4G4D1N 0x01
20655 #define _CLC4GLS3_G4D1N 0x01
20656 #define _CLC4GLS3_LC4G4D1T 0x02
20657 #define _CLC4GLS3_G4D1T 0x02
20658 #define _CLC4GLS3_LC4G4D2N 0x04
20659 #define _CLC4GLS3_G4D2N 0x04
20660 #define _CLC4GLS3_LC4G4D2T 0x08
20661 #define _CLC4GLS3_G4D2T 0x08
20662 #define _CLC4GLS3_LC4G4D3N 0x10
20663 #define _CLC4GLS3_G4D3N 0x10
20664 #define _CLC4GLS3_LC4G4D3T 0x20
20665 #define _CLC4GLS3_G4D3T 0x20
20666 #define _CLC4GLS3_LC4G4D4N 0x40
20667 #define _CLC4GLS3_G4D4N 0x40
20668 #define _CLC4GLS3_LC4G4D4T 0x80
20669 #define _CLC4GLS3_G4D4T 0x80
20671 //==============================================================================
20674 //==============================================================================
20675 // STATUS_SHAD Bits
20677 extern __at(0x0FE4) __sfr STATUS_SHAD
;
20681 unsigned C_SHAD
: 1;
20682 unsigned DC_SHAD
: 1;
20683 unsigned Z_SHAD
: 1;
20689 } __STATUS_SHADbits_t
;
20691 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
20693 #define _C_SHAD 0x01
20694 #define _DC_SHAD 0x02
20695 #define _Z_SHAD 0x04
20697 //==============================================================================
20699 extern __at(0x0FE5) __sfr WREG_SHAD
;
20700 extern __at(0x0FE6) __sfr BSR_SHAD
;
20701 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
20702 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
20703 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
20704 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
20705 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
20706 extern __at(0x0FED) __sfr STKPTR
;
20707 extern __at(0x0FEE) __sfr TOSL
;
20708 extern __at(0x0FEF) __sfr TOSH
;
20710 //==============================================================================
20712 // Configuration Bits
20714 //==============================================================================
20716 #define _CONFIG1 0x8007
20717 #define _CONFIG2 0x8008
20719 //----------------------------- CONFIG1 Options -------------------------------
20721 #define _FOSC_LP 0x3FF8 // LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins.
20722 #define _FOSC_XT 0x3FF9 // XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins.
20723 #define _FOSC_HS 0x3FFA // HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins.
20724 #define _FOSC_EXTRC 0x3FFB // EXTRC oscillator: External RC circuit connected to CLKIN pin.
20725 #define _FOSC_INTOSC 0x3FFC // INTOSC oscillator: I/O function on CLKIN pin.
20726 #define _FOSC_ECL 0x3FFD // ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pins.
20727 #define _FOSC_ECM 0x3FFE // ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pins.
20728 #define _FOSC_ECH 0x3FFF // ECH, External Clock, High Power Mode (4-20 MHz): device clock supplied to CLKIN pins.
20729 #define _WDTE_OFF 0x3FE7 // WDT disabled.
20730 #define _WDTE_SWDTEN 0x3FEF // WDT controlled by the SWDTEN bit in the WDTCON register.
20731 #define _WDTE_NSLEEP 0x3FF7 // WDT enabled while running and disabled in Sleep.
20732 #define _WDTE_ON 0x3FFF // WDT enabled.
20733 #define _PWRTE_ON 0x3FDF // PWRT enabled.
20734 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
20735 #define _MCLRE_OFF 0x3FBF // MCLR/VPP pin function is digital input.
20736 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR.
20737 #define _CP_ON 0x3F7F // Program memory code protection is enabled.
20738 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
20739 #define _BOREN_OFF 0x39FF // Brown-out Reset disabled.
20740 #define _BOREN_SBODEN 0x3BFF // Brown-out Reset controlled by the SBOREN bit in the BORCON register.
20741 #define _BOREN_NSLEEP 0x3DFF // Brown-out Reset enabled while running and disabled in Sleep.
20742 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled.
20743 #define _CLKOUTEN_ON 0x37FF // CLKOUT function is enabled on the CLKOUT pin.
20744 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
20745 #define _IESO_OFF 0x2FFF // Internal/External Switchover Mode is disabled.
20746 #define _IESO_ON 0x3FFF // Internal/External Switchover Mode is enabled.
20747 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
20748 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
20750 //----------------------------- CONFIG2 Options -------------------------------
20752 #define _WRT_ALL 0x3FFC // 000h to 1FFFh write protected, no addresses may be modified by EECON control.
20753 #define _WRT_HALF 0x3FFD // 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control.
20754 #define _WRT_BOOT 0x3FFE // 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control.
20755 #define _WRT_OFF 0x3FFF // Write protection off.
20756 #define _PPS1WAY_OFF 0x3FFB // The PPSLOCK bit can be set and cleared repeatedly by software.
20757 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit cannot be cleared once it is set by software.
20758 #define _ZCD_ON 0x3F7F // Zero-cross detect circuit is enabled at POR.
20759 #define _ZCD_OFF 0x3FFF // Zero-cross detect circuit is disabled at POR.
20760 #define _PLLEN_OFF 0x3EFF // 4x PLL is enabled when software sets the SPLLEN bit.
20761 #define _PLLEN_ON 0x3FFF // 4x PLL is always enabled.
20762 #define _STVREN_OFF 0x3DFF // Stack Overflow or Underflow will not cause a Reset.
20763 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
20764 #define _BORV_HI 0x3BFF // Brown-out Reset Voltage (Vbor), high trip point selected.
20765 #define _BORV_LO 0x3FFF // Brown-out Reset Voltage (Vbor), low trip point selected.
20766 #define _LPBOR_ON 0x37FF // Low-Power BOR is enabled.
20767 #define _LPBOR_OFF 0x3FFF // Low-Power BOR is disabled.
20768 #define _DEBUG_ON 0x2FFF // In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger.
20769 #define _DEBUG_OFF 0x3FFF // In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins.
20770 #define _LVP_OFF 0x1FFF // High-voltage on MCLR/VPP must be used for programming.
20771 #define _LVP_ON 0x3FFF // Low-voltage programming enabled.
20773 //==============================================================================
20775 #define _DEVID1 0x8006
20777 #define _IDLOC0 0x8000
20778 #define _IDLOC1 0x8001
20779 #define _IDLOC2 0x8002
20780 #define _IDLOC3 0x8003
20782 //==============================================================================
20784 #ifndef NO_BIT_DEFINES
20786 #define ADON ADCON0bits.ADON // bit 0
20787 #define GO ADCON0bits.GO // bit 1
20789 #define ADNREF ADCON1bits.ADNREF // bit 2
20790 #define ADFM ADCON1bits.ADFM // bit 7
20792 #define ANSA0 ANSELAbits.ANSA0 // bit 0
20793 #define ANSA1 ANSELAbits.ANSA1 // bit 1
20794 #define ANSA2 ANSELAbits.ANSA2 // bit 2
20795 #define ANSA3 ANSELAbits.ANSA3 // bit 3
20796 #define ANSA4 ANSELAbits.ANSA4 // bit 4
20797 #define ANSA5 ANSELAbits.ANSA5 // bit 5
20799 #define ANSB0 ANSELBbits.ANSB0 // bit 0
20800 #define ANSB1 ANSELBbits.ANSB1 // bit 1
20801 #define ANSB2 ANSELBbits.ANSB2 // bit 2
20802 #define ANSB3 ANSELBbits.ANSB3 // bit 3
20803 #define ANSB4 ANSELBbits.ANSB4 // bit 4
20804 #define ANSB5 ANSELBbits.ANSB5 // bit 5
20806 #define ANSC2 ANSELCbits.ANSC2 // bit 2
20807 #define ANSC3 ANSELCbits.ANSC3 // bit 3
20808 #define ANSC4 ANSELCbits.ANSC4 // bit 4
20809 #define ANSC5 ANSELCbits.ANSC5 // bit 5
20810 #define ANSC6 ANSELCbits.ANSC6 // bit 6
20811 #define ANSC7 ANSELCbits.ANSC7 // bit 7
20813 #define ABDEN BAUD1CONbits.ABDEN // bit 0
20814 #define WUE BAUD1CONbits.WUE // bit 1
20815 #define BRG16 BAUD1CONbits.BRG16 // bit 3
20816 #define SCKP BAUD1CONbits.SCKP // bit 4
20817 #define RCIDL BAUD1CONbits.RCIDL // bit 6
20818 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
20820 #define BORRDY BORCONbits.BORRDY // bit 0
20821 #define BORFS BORCONbits.BORFS // bit 6
20822 #define SBOREN BORCONbits.SBOREN // bit 7
20824 #define BSR0 BSRbits.BSR0 // bit 0
20825 #define BSR1 BSRbits.BSR1 // bit 1
20826 #define BSR2 BSRbits.BSR2 // bit 2
20827 #define BSR3 BSRbits.BSR3 // bit 3
20828 #define BSR4 BSRbits.BSR4 // bit 4
20830 #define CTS0 CCP1CAPbits.CTS0 // bit 0, shadows bit in CCP1CAPbits
20831 #define CCP1CTS0 CCP1CAPbits.CCP1CTS0 // bit 0, shadows bit in CCP1CAPbits
20832 #define CTS1 CCP1CAPbits.CTS1 // bit 1, shadows bit in CCP1CAPbits
20833 #define CCP1CTS1 CCP1CAPbits.CCP1CTS1 // bit 1, shadows bit in CCP1CAPbits
20834 #define CTS2 CCP1CAPbits.CTS2 // bit 2, shadows bit in CCP1CAPbits
20835 #define CCP1CTS2 CCP1CAPbits.CCP1CTS2 // bit 2, shadows bit in CCP1CAPbits
20836 #define CTS3 CCP1CAPbits.CTS3 // bit 3, shadows bit in CCP1CAPbits
20837 #define CCP1CTS3 CCP1CAPbits.CCP1CTS3 // bit 3, shadows bit in CCP1CAPbits
20839 #define MODE0 CCP1CONbits.MODE0 // bit 0, shadows bit in CCP1CONbits
20840 #define CCP1MODE0 CCP1CONbits.CCP1MODE0 // bit 0, shadows bit in CCP1CONbits
20841 #define MODE1 CCP1CONbits.MODE1 // bit 1, shadows bit in CCP1CONbits
20842 #define CCP1MODE1 CCP1CONbits.CCP1MODE1 // bit 1, shadows bit in CCP1CONbits
20843 #define MODE2 CCP1CONbits.MODE2 // bit 2, shadows bit in CCP1CONbits
20844 #define CCP1MODE2 CCP1CONbits.CCP1MODE2 // bit 2, shadows bit in CCP1CONbits
20845 #define MODE3 CCP1CONbits.MODE3 // bit 3, shadows bit in CCP1CONbits
20846 #define CCP1MODE3 CCP1CONbits.CCP1MODE3 // bit 3, shadows bit in CCP1CONbits
20847 #define FMT CCP1CONbits.FMT // bit 4, shadows bit in CCP1CONbits
20848 #define CCP1FMT CCP1CONbits.CCP1FMT // bit 4, shadows bit in CCP1CONbits
20849 #define OUT CCP1CONbits.OUT // bit 5, shadows bit in CCP1CONbits
20850 #define CCP1OUT CCP1CONbits.CCP1OUT // bit 5, shadows bit in CCP1CONbits
20851 #define EN CCP1CONbits.EN // bit 7, shadows bit in CCP1CONbits
20852 #define CCP1EN CCP1CONbits.CCP1EN // bit 7, shadows bit in CCP1CONbits
20854 #define C1TSEL0 CCPTMRS1bits.C1TSEL0 // bit 0
20855 #define C1TSEL1 CCPTMRS1bits.C1TSEL1 // bit 1
20856 #define C2TSEL0 CCPTMRS1bits.C2TSEL0 // bit 2
20857 #define C2TSEL1 CCPTMRS1bits.C2TSEL1 // bit 3
20858 #define C7TSEL0 CCPTMRS1bits.C7TSEL0 // bit 4
20859 #define C7TSEL1 CCPTMRS1bits.C7TSEL1 // bit 5
20861 #define P3TSEL0 CCPTMRS2bits.P3TSEL0 // bit 0
20862 #define P3TSEL1 CCPTMRS2bits.P3TSEL1 // bit 1
20863 #define P4TSEL0 CCPTMRS2bits.P4TSEL0 // bit 2
20864 #define P4TSEL1 CCPTMRS2bits.P4TSEL1 // bit 3
20865 #define P9TSEL0 CCPTMRS2bits.P9TSEL0 // bit 4
20866 #define P9TSEL1 CCPTMRS2bits.P9TSEL1 // bit 5
20868 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
20869 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
20870 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
20871 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
20872 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
20873 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
20874 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
20875 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
20876 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
20877 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
20878 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
20879 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
20880 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
20881 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
20882 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
20883 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
20885 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
20886 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
20887 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
20888 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
20889 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
20890 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
20891 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
20892 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
20893 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
20894 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
20895 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
20896 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
20897 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
20898 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
20899 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
20900 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
20902 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
20903 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
20904 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
20905 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
20906 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
20907 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
20908 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
20909 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
20910 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
20911 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
20913 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
20914 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
20915 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
20916 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
20917 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
20918 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
20919 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
20920 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
20921 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
20922 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
20923 #define LC1D1S5 CLC1SEL0bits.LC1D1S5 // bit 5, shadows bit in CLC1SEL0bits
20924 #define D1S5 CLC1SEL0bits.D1S5 // bit 5, shadows bit in CLC1SEL0bits
20926 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
20927 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
20928 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
20929 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
20930 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
20931 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
20932 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
20933 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
20934 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
20935 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
20936 #define LC1D2S5 CLC1SEL1bits.LC1D2S5 // bit 5, shadows bit in CLC1SEL1bits
20937 #define D2S5 CLC1SEL1bits.D2S5 // bit 5, shadows bit in CLC1SEL1bits
20939 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
20940 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
20941 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
20942 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
20943 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
20944 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
20945 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
20946 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
20947 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
20948 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
20949 #define LC1D3S5 CLC1SEL2bits.LC1D3S5 // bit 5, shadows bit in CLC1SEL2bits
20950 #define D3S5 CLC1SEL2bits.D3S5 // bit 5, shadows bit in CLC1SEL2bits
20952 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
20953 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
20954 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
20955 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
20956 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
20957 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
20958 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
20959 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
20960 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
20961 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
20962 #define LC1D4S5 CLC1SEL3bits.LC1D4S5 // bit 5, shadows bit in CLC1SEL3bits
20963 #define D4S5 CLC1SEL3bits.D4S5 // bit 5, shadows bit in CLC1SEL3bits
20965 #define MCLC1OUT CLCDATAbits.MCLC1OUT // bit 0
20966 #define MCLC2OUT CLCDATAbits.MCLC2OUT // bit 1
20967 #define MCLC3OUT CLCDATAbits.MCLC3OUT // bit 2
20968 #define MLC4OUT CLCDATAbits.MLC4OUT // bit 3
20970 #define C1NCH0 CM1NSELbits.C1NCH0 // bit 0
20971 #define C1NCH1 CM1NSELbits.C1NCH1 // bit 1
20972 #define C1NCH2 CM1NSELbits.C1NCH2 // bit 2
20973 #define C1NCH3 CM1NSELbits.C1NCH3 // bit 3
20975 #define PCH0 CM1PSELbits.PCH0 // bit 0, shadows bit in CM1PSELbits
20976 #define C1PCH0 CM1PSELbits.C1PCH0 // bit 0, shadows bit in CM1PSELbits
20977 #define PCH1 CM1PSELbits.PCH1 // bit 1, shadows bit in CM1PSELbits
20978 #define C1PCH1 CM1PSELbits.C1PCH1 // bit 1, shadows bit in CM1PSELbits
20979 #define PCH2 CM1PSELbits.PCH2 // bit 2, shadows bit in CM1PSELbits
20980 #define C1PCH2 CM1PSELbits.C1PCH2 // bit 2, shadows bit in CM1PSELbits
20981 #define PCH3 CM1PSELbits.PCH3 // bit 3, shadows bit in CM1PSELbits
20982 #define C1PCH3 CM1PSELbits.C1PCH3 // bit 3, shadows bit in CM1PSELbits
20984 #define C2NCH0 CM2NSELbits.C2NCH0 // bit 0
20985 #define C2NCH1 CM2NSELbits.C2NCH1 // bit 1
20986 #define C2NCH2 CM2NSELbits.C2NCH2 // bit 2
20987 #define C2NCH3 CM2NSELbits.C2NCH3 // bit 3
20989 #define C3NCH0 CM3NSELbits.C3NCH0 // bit 0
20990 #define C3NCH1 CM3NSELbits.C3NCH1 // bit 1
20991 #define C3NCH2 CM3NSELbits.C3NCH2 // bit 2
20992 #define C3NCH3 CM3NSELbits.C3NCH3 // bit 3
20994 #define C4NCH0 CM4NSELbits.C4NCH0 // bit 0
20995 #define C4NCH1 CM4NSELbits.C4NCH1 // bit 1
20996 #define C4NCH2 CM4NSELbits.C4NCH2 // bit 2
20997 #define C4NCH3 CM4NSELbits.C4NCH3 // bit 3
20999 #define C5NCH0 CM5NSELbits.C5NCH0 // bit 0
21000 #define C5NCH1 CM5NSELbits.C5NCH1 // bit 1
21001 #define C5NCH2 CM5NSELbits.C5NCH2 // bit 2
21002 #define C5NCH3 CM5NSELbits.C5NCH3 // bit 3
21004 #define C6NCH0 CM6NSELbits.C6NCH0 // bit 0
21005 #define C6NCH1 CM6NSELbits.C6NCH1 // bit 1
21006 #define C6NCH2 CM6NSELbits.C6NCH2 // bit 2
21007 #define C6NCH3 CM6NSELbits.C6NCH3 // bit 3
21009 #define MC1OUT CMOUTbits.MC1OUT // bit 0
21010 #define MC2OUT CMOUTbits.MC2OUT // bit 1
21011 #define MC3OUT CMOUTbits.MC3OUT // bit 2
21012 #define MC4OUT CMOUTbits.MC4OUT // bit 3
21013 #define MC5OUT CMOUTbits.MC5OUT // bit 4
21014 #define MC6OUT CMOUTbits.MC6OUT // bit 5
21016 #define ASDAC0 COG1ASD0bits.ASDAC0 // bit 2, shadows bit in COG1ASD0bits
21017 #define G1ASDAC0 COG1ASD0bits.G1ASDAC0 // bit 2, shadows bit in COG1ASD0bits
21018 #define ASDAC1 COG1ASD0bits.ASDAC1 // bit 3, shadows bit in COG1ASD0bits
21019 #define G1ASDAC1 COG1ASD0bits.G1ASDAC1 // bit 3, shadows bit in COG1ASD0bits
21020 #define ASDBD0 COG1ASD0bits.ASDBD0 // bit 4, shadows bit in COG1ASD0bits
21021 #define G1ASDBD0 COG1ASD0bits.G1ASDBD0 // bit 4, shadows bit in COG1ASD0bits
21022 #define ASDBD1 COG1ASD0bits.ASDBD1 // bit 5, shadows bit in COG1ASD0bits
21023 #define G1ASDBD1 COG1ASD0bits.G1ASDBD1 // bit 5, shadows bit in COG1ASD0bits
21024 #define ASREN COG1ASD0bits.ASREN // bit 6, shadows bit in COG1ASD0bits
21025 #define ARSEN COG1ASD0bits.ARSEN // bit 6, shadows bit in COG1ASD0bits
21026 #define G1ARSEN COG1ASD0bits.G1ARSEN // bit 6, shadows bit in COG1ASD0bits
21027 #define G1ASREN COG1ASD0bits.G1ASREN // bit 6, shadows bit in COG1ASD0bits
21028 #define ASE COG1ASD0bits.ASE // bit 7, shadows bit in COG1ASD0bits
21029 #define G1ASE COG1ASD0bits.G1ASE // bit 7, shadows bit in COG1ASD0bits
21031 #define AS0E COG1ASD1bits.AS0E // bit 0, shadows bit in COG1ASD1bits
21032 #define G1AS0E COG1ASD1bits.G1AS0E // bit 0, shadows bit in COG1ASD1bits
21033 #define AS1E COG1ASD1bits.AS1E // bit 1, shadows bit in COG1ASD1bits
21034 #define G1AS1E COG1ASD1bits.G1AS1E // bit 1, shadows bit in COG1ASD1bits
21035 #define AS2E COG1ASD1bits.AS2E // bit 2, shadows bit in COG1ASD1bits
21036 #define G1AS2E COG1ASD1bits.G1AS2E // bit 2, shadows bit in COG1ASD1bits
21037 #define AS3E COG1ASD1bits.AS3E // bit 3, shadows bit in COG1ASD1bits
21038 #define G1AS3E COG1ASD1bits.G1AS3E // bit 3, shadows bit in COG1ASD1bits
21039 #define AS4E COG1ASD1bits.AS4E // bit 4, shadows bit in COG1ASD1bits
21040 #define G1AS4E COG1ASD1bits.G1AS4E // bit 4, shadows bit in COG1ASD1bits
21041 #define AS5E COG1ASD1bits.AS5E // bit 5, shadows bit in COG1ASD1bits
21042 #define G1AS5E COG1ASD1bits.G1AS5E // bit 5, shadows bit in COG1ASD1bits
21043 #define AS6E COG1ASD1bits.AS6E // bit 6, shadows bit in COG1ASD1bits
21044 #define G1AS6E COG1ASD1bits.G1AS6E // bit 6, shadows bit in COG1ASD1bits
21045 #define AS7E COG1ASD1bits.AS7E // bit 7, shadows bit in COG1ASD1bits
21046 #define G1AS7E COG1ASD1bits.G1AS7E // bit 7, shadows bit in COG1ASD1bits
21048 #define BLKF0 COG1BLKFbits.BLKF0 // bit 0, shadows bit in COG1BLKFbits
21049 #define G1BLKF0 COG1BLKFbits.G1BLKF0 // bit 0, shadows bit in COG1BLKFbits
21050 #define BLKF1 COG1BLKFbits.BLKF1 // bit 1, shadows bit in COG1BLKFbits
21051 #define G1BLKF1 COG1BLKFbits.G1BLKF1 // bit 1, shadows bit in COG1BLKFbits
21052 #define BLKF2 COG1BLKFbits.BLKF2 // bit 2, shadows bit in COG1BLKFbits
21053 #define G1BLKF2 COG1BLKFbits.G1BLKF2 // bit 2, shadows bit in COG1BLKFbits
21054 #define BLKF3 COG1BLKFbits.BLKF3 // bit 3, shadows bit in COG1BLKFbits
21055 #define G1BLKF3 COG1BLKFbits.G1BLKF3 // bit 3, shadows bit in COG1BLKFbits
21056 #define BLKF4 COG1BLKFbits.BLKF4 // bit 4, shadows bit in COG1BLKFbits
21057 #define G1BLKF4 COG1BLKFbits.G1BLKF4 // bit 4, shadows bit in COG1BLKFbits
21058 #define BLKF5 COG1BLKFbits.BLKF5 // bit 5, shadows bit in COG1BLKFbits
21059 #define G1BLKF5 COG1BLKFbits.G1BLKF5 // bit 5, shadows bit in COG1BLKFbits
21061 #define BLKR0 COG1BLKRbits.BLKR0 // bit 0, shadows bit in COG1BLKRbits
21062 #define G1BLKR0 COG1BLKRbits.G1BLKR0 // bit 0, shadows bit in COG1BLKRbits
21063 #define BLKR1 COG1BLKRbits.BLKR1 // bit 1, shadows bit in COG1BLKRbits
21064 #define G1BLKR1 COG1BLKRbits.G1BLKR1 // bit 1, shadows bit in COG1BLKRbits
21065 #define BLKR2 COG1BLKRbits.BLKR2 // bit 2, shadows bit in COG1BLKRbits
21066 #define G1BLKR2 COG1BLKRbits.G1BLKR2 // bit 2, shadows bit in COG1BLKRbits
21067 #define BLKR3 COG1BLKRbits.BLKR3 // bit 3, shadows bit in COG1BLKRbits
21068 #define G1BLKR3 COG1BLKRbits.G1BLKR3 // bit 3, shadows bit in COG1BLKRbits
21069 #define BLKR4 COG1BLKRbits.BLKR4 // bit 4, shadows bit in COG1BLKRbits
21070 #define G1BLKR4 COG1BLKRbits.G1BLKR4 // bit 4, shadows bit in COG1BLKRbits
21071 #define BLKR5 COG1BLKRbits.BLKR5 // bit 5, shadows bit in COG1BLKRbits
21072 #define G1BLKR5 COG1BLKRbits.G1BLKR5 // bit 5, shadows bit in COG1BLKRbits
21074 #define POLA COG1CON1bits.POLA // bit 0, shadows bit in COG1CON1bits
21075 #define G1POLA COG1CON1bits.G1POLA // bit 0, shadows bit in COG1CON1bits
21076 #define POLB COG1CON1bits.POLB // bit 1, shadows bit in COG1CON1bits
21077 #define G1POLB COG1CON1bits.G1POLB // bit 1, shadows bit in COG1CON1bits
21078 #define POLC COG1CON1bits.POLC // bit 2, shadows bit in COG1CON1bits
21079 #define G1POLC COG1CON1bits.G1POLC // bit 2, shadows bit in COG1CON1bits
21080 #define POLD COG1CON1bits.POLD // bit 3, shadows bit in COG1CON1bits
21081 #define G1POLD COG1CON1bits.G1POLD // bit 3, shadows bit in COG1CON1bits
21082 #define FDBS COG1CON1bits.FDBS // bit 6, shadows bit in COG1CON1bits
21083 #define G1FDBS COG1CON1bits.G1FDBS // bit 6, shadows bit in COG1CON1bits
21084 #define RDBS COG1CON1bits.RDBS // bit 7, shadows bit in COG1CON1bits
21085 #define G1RDBS COG1CON1bits.G1RDBS // bit 7, shadows bit in COG1CON1bits
21087 #define DBF0 COG1DBFbits.DBF0 // bit 0, shadows bit in COG1DBFbits
21088 #define G1DBF0 COG1DBFbits.G1DBF0 // bit 0, shadows bit in COG1DBFbits
21089 #define DBF1 COG1DBFbits.DBF1 // bit 1, shadows bit in COG1DBFbits
21090 #define G1DBF1 COG1DBFbits.G1DBF1 // bit 1, shadows bit in COG1DBFbits
21091 #define DBF2 COG1DBFbits.DBF2 // bit 2, shadows bit in COG1DBFbits
21092 #define G1DBF2 COG1DBFbits.G1DBF2 // bit 2, shadows bit in COG1DBFbits
21093 #define DBF3 COG1DBFbits.DBF3 // bit 3, shadows bit in COG1DBFbits
21094 #define G1DBF3 COG1DBFbits.G1DBF3 // bit 3, shadows bit in COG1DBFbits
21095 #define DBF4 COG1DBFbits.DBF4 // bit 4, shadows bit in COG1DBFbits
21096 #define G1DBF4 COG1DBFbits.G1DBF4 // bit 4, shadows bit in COG1DBFbits
21097 #define DBF5 COG1DBFbits.DBF5 // bit 5, shadows bit in COG1DBFbits
21098 #define G1DBF5 COG1DBFbits.G1DBF5 // bit 5, shadows bit in COG1DBFbits
21100 #define DBR0 COG1DBRbits.DBR0 // bit 0, shadows bit in COG1DBRbits
21101 #define G1DBR0 COG1DBRbits.G1DBR0 // bit 0, shadows bit in COG1DBRbits
21102 #define DBR1 COG1DBRbits.DBR1 // bit 1, shadows bit in COG1DBRbits
21103 #define G1DBR1 COG1DBRbits.G1DBR1 // bit 1, shadows bit in COG1DBRbits
21104 #define DBR2 COG1DBRbits.DBR2 // bit 2, shadows bit in COG1DBRbits
21105 #define G1DBR2 COG1DBRbits.G1DBR2 // bit 2, shadows bit in COG1DBRbits
21106 #define DBR3 COG1DBRbits.DBR3 // bit 3, shadows bit in COG1DBRbits
21107 #define G1DBR3 COG1DBRbits.G1DBR3 // bit 3, shadows bit in COG1DBRbits
21108 #define DBR4 COG1DBRbits.DBR4 // bit 4, shadows bit in COG1DBRbits
21109 #define G1DBR4 COG1DBRbits.G1DBR4 // bit 4, shadows bit in COG1DBRbits
21110 #define DBR5 COG1DBRbits.DBR5 // bit 5, shadows bit in COG1DBRbits
21111 #define G1DBR5 COG1DBRbits.G1DBR5 // bit 5, shadows bit in COG1DBRbits
21113 #define FIS0 COG1FIS0bits.FIS0 // bit 0, shadows bit in COG1FIS0bits
21114 #define G1FIS0 COG1FIS0bits.G1FIS0 // bit 0, shadows bit in COG1FIS0bits
21115 #define FIS1 COG1FIS0bits.FIS1 // bit 1, shadows bit in COG1FIS0bits
21116 #define G1FIS1 COG1FIS0bits.G1FIS1 // bit 1, shadows bit in COG1FIS0bits
21117 #define FIS2 COG1FIS0bits.FIS2 // bit 2, shadows bit in COG1FIS0bits
21118 #define G1FIS2 COG1FIS0bits.G1FIS2 // bit 2, shadows bit in COG1FIS0bits
21119 #define FIS3 COG1FIS0bits.FIS3 // bit 3, shadows bit in COG1FIS0bits
21120 #define G1FIS3 COG1FIS0bits.G1FIS3 // bit 3, shadows bit in COG1FIS0bits
21121 #define FIS4 COG1FIS0bits.FIS4 // bit 4, shadows bit in COG1FIS0bits
21122 #define G1FIS4 COG1FIS0bits.G1FIS4 // bit 4, shadows bit in COG1FIS0bits
21123 #define FIS5 COG1FIS0bits.FIS5 // bit 5, shadows bit in COG1FIS0bits
21124 #define G1FIS5 COG1FIS0bits.G1FIS5 // bit 5, shadows bit in COG1FIS0bits
21125 #define FIS6 COG1FIS0bits.FIS6 // bit 6, shadows bit in COG1FIS0bits
21126 #define G1FIS6 COG1FIS0bits.G1FIS6 // bit 6, shadows bit in COG1FIS0bits
21127 #define FIS7 COG1FIS0bits.FIS7 // bit 7, shadows bit in COG1FIS0bits
21128 #define G1FIS7 COG1FIS0bits.G1FIS7 // bit 7, shadows bit in COG1FIS0bits
21130 #define FIS8 COG1FIS1bits.FIS8 // bit 0, shadows bit in COG1FIS1bits
21131 #define G1FIS8 COG1FIS1bits.G1FIS8 // bit 0, shadows bit in COG1FIS1bits
21132 #define FIS9 COG1FIS1bits.FIS9 // bit 1, shadows bit in COG1FIS1bits
21133 #define G1FIS9 COG1FIS1bits.G1FIS9 // bit 1, shadows bit in COG1FIS1bits
21134 #define FIS10 COG1FIS1bits.FIS10 // bit 2, shadows bit in COG1FIS1bits
21135 #define G1FIS10 COG1FIS1bits.G1FIS10 // bit 2, shadows bit in COG1FIS1bits
21136 #define FIS11 COG1FIS1bits.FIS11 // bit 3, shadows bit in COG1FIS1bits
21137 #define G1FIS11 COG1FIS1bits.G1FIS11 // bit 3, shadows bit in COG1FIS1bits
21138 #define FIS12 COG1FIS1bits.FIS12 // bit 4, shadows bit in COG1FIS1bits
21139 #define G1FIS12 COG1FIS1bits.G1FIS12 // bit 4, shadows bit in COG1FIS1bits
21140 #define FIS13 COG1FIS1bits.FIS13 // bit 5, shadows bit in COG1FIS1bits
21141 #define G1FIS13 COG1FIS1bits.G1FIS13 // bit 5, shadows bit in COG1FIS1bits
21142 #define FIS14 COG1FIS1bits.FIS14 // bit 6, shadows bit in COG1FIS1bits
21143 #define G1FIS14 COG1FIS1bits.G1FIS14 // bit 6, shadows bit in COG1FIS1bits
21144 #define FIS15 COG1FIS1bits.FIS15 // bit 7, shadows bit in COG1FIS1bits
21145 #define G1FIS15 COG1FIS1bits.G1FIS15 // bit 7, shadows bit in COG1FIS1bits
21147 #define FSIM0 COG1FSIM0bits.FSIM0 // bit 0, shadows bit in COG1FSIM0bits
21148 #define G1FSIM0 COG1FSIM0bits.G1FSIM0 // bit 0, shadows bit in COG1FSIM0bits
21149 #define FSIM1 COG1FSIM0bits.FSIM1 // bit 1, shadows bit in COG1FSIM0bits
21150 #define G1FSIM1 COG1FSIM0bits.G1FSIM1 // bit 1, shadows bit in COG1FSIM0bits
21151 #define FSIM2 COG1FSIM0bits.FSIM2 // bit 2, shadows bit in COG1FSIM0bits
21152 #define G1FSIM2 COG1FSIM0bits.G1FSIM2 // bit 2, shadows bit in COG1FSIM0bits
21153 #define FSIM3 COG1FSIM0bits.FSIM3 // bit 3, shadows bit in COG1FSIM0bits
21154 #define G1FSIM3 COG1FSIM0bits.G1FSIM3 // bit 3, shadows bit in COG1FSIM0bits
21155 #define FSIM4 COG1FSIM0bits.FSIM4 // bit 4, shadows bit in COG1FSIM0bits
21156 #define G1FSIM4 COG1FSIM0bits.G1FSIM4 // bit 4, shadows bit in COG1FSIM0bits
21157 #define FSIM5 COG1FSIM0bits.FSIM5 // bit 5, shadows bit in COG1FSIM0bits
21158 #define G1FSIM5 COG1FSIM0bits.G1FSIM5 // bit 5, shadows bit in COG1FSIM0bits
21159 #define FSIM6 COG1FSIM0bits.FSIM6 // bit 6, shadows bit in COG1FSIM0bits
21160 #define G1FSIM6 COG1FSIM0bits.G1FSIM6 // bit 6, shadows bit in COG1FSIM0bits
21161 #define FSIM7 COG1FSIM0bits.FSIM7 // bit 7, shadows bit in COG1FSIM0bits
21162 #define G1FSIM7 COG1FSIM0bits.G1FSIM7 // bit 7, shadows bit in COG1FSIM0bits
21164 #define FSIM8 COG1FSIM1bits.FSIM8 // bit 0, shadows bit in COG1FSIM1bits
21165 #define G1FSIM8 COG1FSIM1bits.G1FSIM8 // bit 0, shadows bit in COG1FSIM1bits
21166 #define FSIM9 COG1FSIM1bits.FSIM9 // bit 1, shadows bit in COG1FSIM1bits
21167 #define G1FSIM9 COG1FSIM1bits.G1FSIM9 // bit 1, shadows bit in COG1FSIM1bits
21168 #define FSIM10 COG1FSIM1bits.FSIM10 // bit 2, shadows bit in COG1FSIM1bits
21169 #define G1FSIM10 COG1FSIM1bits.G1FSIM10 // bit 2, shadows bit in COG1FSIM1bits
21170 #define FSIM11 COG1FSIM1bits.FSIM11 // bit 3, shadows bit in COG1FSIM1bits
21171 #define G1FSIM11 COG1FSIM1bits.G1FSIM11 // bit 3, shadows bit in COG1FSIM1bits
21172 #define FSIM12 COG1FSIM1bits.FSIM12 // bit 4, shadows bit in COG1FSIM1bits
21173 #define G1FSIM12 COG1FSIM1bits.G1FSIM12 // bit 4, shadows bit in COG1FSIM1bits
21174 #define FSIM13 COG1FSIM1bits.FSIM13 // bit 5, shadows bit in COG1FSIM1bits
21175 #define G1FSIM13 COG1FSIM1bits.G1FSIM13 // bit 5, shadows bit in COG1FSIM1bits
21176 #define FSIM14 COG1FSIM1bits.FSIM14 // bit 6, shadows bit in COG1FSIM1bits
21177 #define G1FSIM14 COG1FSIM1bits.G1FSIM14 // bit 6, shadows bit in COG1FSIM1bits
21178 #define FSIM15 COG1FSIM1bits.FSIM15 // bit 7, shadows bit in COG1FSIM1bits
21179 #define G1FSIM15 COG1FSIM1bits.G1FSIM15 // bit 7, shadows bit in COG1FSIM1bits
21181 #define PHF0 COG1PHFbits.PHF0 // bit 0, shadows bit in COG1PHFbits
21182 #define G1PHF0 COG1PHFbits.G1PHF0 // bit 0, shadows bit in COG1PHFbits
21183 #define PHF1 COG1PHFbits.PHF1 // bit 1, shadows bit in COG1PHFbits
21184 #define G1PHF1 COG1PHFbits.G1PHF1 // bit 1, shadows bit in COG1PHFbits
21185 #define PHF2 COG1PHFbits.PHF2 // bit 2, shadows bit in COG1PHFbits
21186 #define G1PHF2 COG1PHFbits.G1PHF2 // bit 2, shadows bit in COG1PHFbits
21187 #define PHF3 COG1PHFbits.PHF3 // bit 3, shadows bit in COG1PHFbits
21188 #define G1PHF3 COG1PHFbits.G1PHF3 // bit 3, shadows bit in COG1PHFbits
21189 #define PHF4 COG1PHFbits.PHF4 // bit 4, shadows bit in COG1PHFbits
21190 #define G1PHF4 COG1PHFbits.G1PHF4 // bit 4, shadows bit in COG1PHFbits
21191 #define PHF5 COG1PHFbits.PHF5 // bit 5, shadows bit in COG1PHFbits
21192 #define G1PHF5 COG1PHFbits.G1PHF5 // bit 5, shadows bit in COG1PHFbits
21194 #define PHR0 COG1PHRbits.PHR0 // bit 0, shadows bit in COG1PHRbits
21195 #define G1PHR0 COG1PHRbits.G1PHR0 // bit 0, shadows bit in COG1PHRbits
21196 #define PHR1 COG1PHRbits.PHR1 // bit 1, shadows bit in COG1PHRbits
21197 #define G1PHR1 COG1PHRbits.G1PHR1 // bit 1, shadows bit in COG1PHRbits
21198 #define PHR2 COG1PHRbits.PHR2 // bit 2, shadows bit in COG1PHRbits
21199 #define G1PHR2 COG1PHRbits.G1PHR2 // bit 2, shadows bit in COG1PHRbits
21200 #define PHR3 COG1PHRbits.PHR3 // bit 3, shadows bit in COG1PHRbits
21201 #define G1PHR3 COG1PHRbits.G1PHR3 // bit 3, shadows bit in COG1PHRbits
21202 #define PHR4 COG1PHRbits.PHR4 // bit 4, shadows bit in COG1PHRbits
21203 #define G1PHR4 COG1PHRbits.G1PHR4 // bit 4, shadows bit in COG1PHRbits
21204 #define PHR5 COG1PHRbits.PHR5 // bit 5, shadows bit in COG1PHRbits
21205 #define G1PHR5 COG1PHRbits.G1PHR5 // bit 5, shadows bit in COG1PHRbits
21207 #define RIS0 COG1RIS0bits.RIS0 // bit 0, shadows bit in COG1RIS0bits
21208 #define G1RIS0 COG1RIS0bits.G1RIS0 // bit 0, shadows bit in COG1RIS0bits
21209 #define RIS1 COG1RIS0bits.RIS1 // bit 1, shadows bit in COG1RIS0bits
21210 #define G1RIS1 COG1RIS0bits.G1RIS1 // bit 1, shadows bit in COG1RIS0bits
21211 #define RIS2 COG1RIS0bits.RIS2 // bit 2, shadows bit in COG1RIS0bits
21212 #define G1RIS2 COG1RIS0bits.G1RIS2 // bit 2, shadows bit in COG1RIS0bits
21213 #define RIS3 COG1RIS0bits.RIS3 // bit 3, shadows bit in COG1RIS0bits
21214 #define G1RIS3 COG1RIS0bits.G1RIS3 // bit 3, shadows bit in COG1RIS0bits
21215 #define RIS4 COG1RIS0bits.RIS4 // bit 4, shadows bit in COG1RIS0bits
21216 #define G1RIS4 COG1RIS0bits.G1RIS4 // bit 4, shadows bit in COG1RIS0bits
21217 #define RIS5 COG1RIS0bits.RIS5 // bit 5, shadows bit in COG1RIS0bits
21218 #define G1RIS5 COG1RIS0bits.G1RIS5 // bit 5, shadows bit in COG1RIS0bits
21219 #define RIS6 COG1RIS0bits.RIS6 // bit 6, shadows bit in COG1RIS0bits
21220 #define G1RIS6 COG1RIS0bits.G1RIS6 // bit 6, shadows bit in COG1RIS0bits
21221 #define RIS7 COG1RIS0bits.RIS7 // bit 7, shadows bit in COG1RIS0bits
21222 #define G1RIS7 COG1RIS0bits.G1RIS7 // bit 7, shadows bit in COG1RIS0bits
21224 #define RIS8 COG1RIS1bits.RIS8 // bit 0, shadows bit in COG1RIS1bits
21225 #define G1RIS8 COG1RIS1bits.G1RIS8 // bit 0, shadows bit in COG1RIS1bits
21226 #define RIS9 COG1RIS1bits.RIS9 // bit 1, shadows bit in COG1RIS1bits
21227 #define G1RIS9 COG1RIS1bits.G1RIS9 // bit 1, shadows bit in COG1RIS1bits
21228 #define RIS10 COG1RIS1bits.RIS10 // bit 2, shadows bit in COG1RIS1bits
21229 #define G1RIS10 COG1RIS1bits.G1RIS10 // bit 2, shadows bit in COG1RIS1bits
21230 #define RIS11 COG1RIS1bits.RIS11 // bit 3, shadows bit in COG1RIS1bits
21231 #define G1RIS11 COG1RIS1bits.G1RIS11 // bit 3, shadows bit in COG1RIS1bits
21232 #define RIS12 COG1RIS1bits.RIS12 // bit 4, shadows bit in COG1RIS1bits
21233 #define G1RIS12 COG1RIS1bits.G1RIS12 // bit 4, shadows bit in COG1RIS1bits
21234 #define RIS13 COG1RIS1bits.RIS13 // bit 5, shadows bit in COG1RIS1bits
21235 #define G1RIS13 COG1RIS1bits.G1RIS13 // bit 5, shadows bit in COG1RIS1bits
21236 #define RIS14 COG1RIS1bits.RIS14 // bit 6, shadows bit in COG1RIS1bits
21237 #define G1RIS14 COG1RIS1bits.G1RIS14 // bit 6, shadows bit in COG1RIS1bits
21238 #define RIS15 COG1RIS1bits.RIS15 // bit 7, shadows bit in COG1RIS1bits
21239 #define G1RIS15 COG1RIS1bits.G1RIS15 // bit 7, shadows bit in COG1RIS1bits
21241 #define RSIM0 COG1RSIM0bits.RSIM0 // bit 0, shadows bit in COG1RSIM0bits
21242 #define G1RSIM0 COG1RSIM0bits.G1RSIM0 // bit 0, shadows bit in COG1RSIM0bits
21243 #define RSIM1 COG1RSIM0bits.RSIM1 // bit 1, shadows bit in COG1RSIM0bits
21244 #define G1RSIM1 COG1RSIM0bits.G1RSIM1 // bit 1, shadows bit in COG1RSIM0bits
21245 #define RSIM2 COG1RSIM0bits.RSIM2 // bit 2, shadows bit in COG1RSIM0bits
21246 #define G1RSIM2 COG1RSIM0bits.G1RSIM2 // bit 2, shadows bit in COG1RSIM0bits
21247 #define RSIM3 COG1RSIM0bits.RSIM3 // bit 3, shadows bit in COG1RSIM0bits
21248 #define G1RSIM3 COG1RSIM0bits.G1RSIM3 // bit 3, shadows bit in COG1RSIM0bits
21249 #define RSIM4 COG1RSIM0bits.RSIM4 // bit 4, shadows bit in COG1RSIM0bits
21250 #define G1RSIM4 COG1RSIM0bits.G1RSIM4 // bit 4, shadows bit in COG1RSIM0bits
21251 #define RSIM5 COG1RSIM0bits.RSIM5 // bit 5, shadows bit in COG1RSIM0bits
21252 #define G1RSIM5 COG1RSIM0bits.G1RSIM5 // bit 5, shadows bit in COG1RSIM0bits
21253 #define RSIM6 COG1RSIM0bits.RSIM6 // bit 6, shadows bit in COG1RSIM0bits
21254 #define G1RSIM6 COG1RSIM0bits.G1RSIM6 // bit 6, shadows bit in COG1RSIM0bits
21255 #define RSIM7 COG1RSIM0bits.RSIM7 // bit 7, shadows bit in COG1RSIM0bits
21256 #define G1RSIM7 COG1RSIM0bits.G1RSIM7 // bit 7, shadows bit in COG1RSIM0bits
21258 #define RSIM8 COG1RSIM1bits.RSIM8 // bit 0, shadows bit in COG1RSIM1bits
21259 #define G1RSIM8 COG1RSIM1bits.G1RSIM8 // bit 0, shadows bit in COG1RSIM1bits
21260 #define RSIM9 COG1RSIM1bits.RSIM9 // bit 1, shadows bit in COG1RSIM1bits
21261 #define G1RSIM9 COG1RSIM1bits.G1RSIM9 // bit 1, shadows bit in COG1RSIM1bits
21262 #define RSIM10 COG1RSIM1bits.RSIM10 // bit 2, shadows bit in COG1RSIM1bits
21263 #define G1RSIM10 COG1RSIM1bits.G1RSIM10 // bit 2, shadows bit in COG1RSIM1bits
21264 #define RSIM11 COG1RSIM1bits.RSIM11 // bit 3, shadows bit in COG1RSIM1bits
21265 #define G1RSIM11 COG1RSIM1bits.G1RSIM11 // bit 3, shadows bit in COG1RSIM1bits
21266 #define RSIM12 COG1RSIM1bits.RSIM12 // bit 4, shadows bit in COG1RSIM1bits
21267 #define G1RSIM12 COG1RSIM1bits.G1RSIM12 // bit 4, shadows bit in COG1RSIM1bits
21268 #define RSIM13 COG1RSIM1bits.RSIM13 // bit 5, shadows bit in COG1RSIM1bits
21269 #define G1RSIM13 COG1RSIM1bits.G1RSIM13 // bit 5, shadows bit in COG1RSIM1bits
21270 #define RSIM14 COG1RSIM1bits.RSIM14 // bit 6, shadows bit in COG1RSIM1bits
21271 #define G1RSIM14 COG1RSIM1bits.G1RSIM14 // bit 6, shadows bit in COG1RSIM1bits
21272 #define RSIM15 COG1RSIM1bits.RSIM15 // bit 7, shadows bit in COG1RSIM1bits
21273 #define G1RSIM15 COG1RSIM1bits.G1RSIM15 // bit 7, shadows bit in COG1RSIM1bits
21275 #define STRA COG1STRbits.STRA // bit 0, shadows bit in COG1STRbits
21276 #define G1STRA COG1STRbits.G1STRA // bit 0, shadows bit in COG1STRbits
21277 #define STRB COG1STRbits.STRB // bit 1, shadows bit in COG1STRbits
21278 #define G1STRB COG1STRbits.G1STRB // bit 1, shadows bit in COG1STRbits
21279 #define STRC COG1STRbits.STRC // bit 2, shadows bit in COG1STRbits
21280 #define G1STRC COG1STRbits.G1STRC // bit 2, shadows bit in COG1STRbits
21281 #define STRD COG1STRbits.STRD // bit 3, shadows bit in COG1STRbits
21282 #define G1STRD COG1STRbits.G1STRD // bit 3, shadows bit in COG1STRbits
21283 #define SDATA COG1STRbits.SDATA // bit 4, shadows bit in COG1STRbits
21284 #define G1SDATA COG1STRbits.G1SDATA // bit 4, shadows bit in COG1STRbits
21285 #define SDATB COG1STRbits.SDATB // bit 5, shadows bit in COG1STRbits
21286 #define G1SDATB COG1STRbits.G1SDATB // bit 5, shadows bit in COG1STRbits
21287 #define SDATC COG1STRbits.SDATC // bit 6, shadows bit in COG1STRbits
21288 #define G1SDATC COG1STRbits.G1SDATC // bit 6, shadows bit in COG1STRbits
21289 #define SDATD COG1STRbits.SDATD // bit 7, shadows bit in COG1STRbits
21290 #define G1SDATD COG1STRbits.G1SDATD // bit 7, shadows bit in COG1STRbits
21292 #define REF0 DAC1CON1bits.REF0 // bit 0, shadows bit in DAC1CON1bits
21293 #define DAC1REF0 DAC1CON1bits.DAC1REF0 // bit 0, shadows bit in DAC1CON1bits
21294 #define R0 DAC1CON1bits.R0 // bit 0, shadows bit in DAC1CON1bits
21295 #define DAC1R0 DAC1CON1bits.DAC1R0 // bit 0, shadows bit in DAC1CON1bits
21296 #define REF1 DAC1CON1bits.REF1 // bit 1, shadows bit in DAC1CON1bits
21297 #define DAC1REF1 DAC1CON1bits.DAC1REF1 // bit 1, shadows bit in DAC1CON1bits
21298 #define R1 DAC1CON1bits.R1 // bit 1, shadows bit in DAC1CON1bits
21299 #define DAC1R1 DAC1CON1bits.DAC1R1 // bit 1, shadows bit in DAC1CON1bits
21300 #define REF2 DAC1CON1bits.REF2 // bit 2, shadows bit in DAC1CON1bits
21301 #define DAC1REF2 DAC1CON1bits.DAC1REF2 // bit 2, shadows bit in DAC1CON1bits
21302 #define R2 DAC1CON1bits.R2 // bit 2, shadows bit in DAC1CON1bits
21303 #define DAC1R2 DAC1CON1bits.DAC1R2 // bit 2, shadows bit in DAC1CON1bits
21304 #define REF3 DAC1CON1bits.REF3 // bit 3, shadows bit in DAC1CON1bits
21305 #define DAC1REF3 DAC1CON1bits.DAC1REF3 // bit 3, shadows bit in DAC1CON1bits
21306 #define R3 DAC1CON1bits.R3 // bit 3, shadows bit in DAC1CON1bits
21307 #define DAC1R3 DAC1CON1bits.DAC1R3 // bit 3, shadows bit in DAC1CON1bits
21308 #define REF4 DAC1CON1bits.REF4 // bit 4, shadows bit in DAC1CON1bits
21309 #define DAC1REF4 DAC1CON1bits.DAC1REF4 // bit 4, shadows bit in DAC1CON1bits
21310 #define R4 DAC1CON1bits.R4 // bit 4, shadows bit in DAC1CON1bits
21311 #define DAC1R4 DAC1CON1bits.DAC1R4 // bit 4, shadows bit in DAC1CON1bits
21312 #define REF5 DAC1CON1bits.REF5 // bit 5, shadows bit in DAC1CON1bits
21313 #define DAC1REF5 DAC1CON1bits.DAC1REF5 // bit 5, shadows bit in DAC1CON1bits
21314 #define R5 DAC1CON1bits.R5 // bit 5, shadows bit in DAC1CON1bits
21315 #define DAC1R5 DAC1CON1bits.DAC1R5 // bit 5, shadows bit in DAC1CON1bits
21316 #define REF6 DAC1CON1bits.REF6 // bit 6, shadows bit in DAC1CON1bits
21317 #define DAC1REF6 DAC1CON1bits.DAC1REF6 // bit 6, shadows bit in DAC1CON1bits
21318 #define R6 DAC1CON1bits.R6 // bit 6, shadows bit in DAC1CON1bits
21319 #define DAC1R6 DAC1CON1bits.DAC1R6 // bit 6, shadows bit in DAC1CON1bits
21320 #define REF7 DAC1CON1bits.REF7 // bit 7, shadows bit in DAC1CON1bits
21321 #define DAC1REF7 DAC1CON1bits.DAC1REF7 // bit 7, shadows bit in DAC1CON1bits
21322 #define R7 DAC1CON1bits.R7 // bit 7, shadows bit in DAC1CON1bits
21323 #define DAC1R7 DAC1CON1bits.DAC1R7 // bit 7, shadows bit in DAC1CON1bits
21325 #define REF8 DAC1CON2bits.REF8 // bit 0, shadows bit in DAC1CON2bits
21326 #define DAC1REF8 DAC1CON2bits.DAC1REF8 // bit 0, shadows bit in DAC1CON2bits
21327 #define R8 DAC1CON2bits.R8 // bit 0, shadows bit in DAC1CON2bits
21328 #define DAC1R8 DAC1CON2bits.DAC1R8 // bit 0, shadows bit in DAC1CON2bits
21329 #define REF9 DAC1CON2bits.REF9 // bit 1, shadows bit in DAC1CON2bits
21330 #define DAC1REF9 DAC1CON2bits.DAC1REF9 // bit 1, shadows bit in DAC1CON2bits
21331 #define R9 DAC1CON2bits.R9 // bit 1, shadows bit in DAC1CON2bits
21332 #define DAC1R9 DAC1CON2bits.DAC1R9 // bit 1, shadows bit in DAC1CON2bits
21333 #define REF10 DAC1CON2bits.REF10 // bit 2, shadows bit in DAC1CON2bits
21334 #define DAC1REF10 DAC1CON2bits.DAC1REF10 // bit 2, shadows bit in DAC1CON2bits
21335 #define R10 DAC1CON2bits.R10 // bit 2, shadows bit in DAC1CON2bits
21336 #define DAC1R10 DAC1CON2bits.DAC1R10 // bit 2, shadows bit in DAC1CON2bits
21337 #define REF11 DAC1CON2bits.REF11 // bit 3, shadows bit in DAC1CON2bits
21338 #define DAC1REF11 DAC1CON2bits.DAC1REF11 // bit 3, shadows bit in DAC1CON2bits
21339 #define R11 DAC1CON2bits.R11 // bit 3, shadows bit in DAC1CON2bits
21340 #define DAC1R11 DAC1CON2bits.DAC1R11 // bit 3, shadows bit in DAC1CON2bits
21341 #define REF12 DAC1CON2bits.REF12 // bit 4, shadows bit in DAC1CON2bits
21342 #define DAC1REF12 DAC1CON2bits.DAC1REF12 // bit 4, shadows bit in DAC1CON2bits
21343 #define R12 DAC1CON2bits.R12 // bit 4, shadows bit in DAC1CON2bits
21344 #define DAC1R12 DAC1CON2bits.DAC1R12 // bit 4, shadows bit in DAC1CON2bits
21345 #define REF13 DAC1CON2bits.REF13 // bit 5, shadows bit in DAC1CON2bits
21346 #define DAC1REF13 DAC1CON2bits.DAC1REF13 // bit 5, shadows bit in DAC1CON2bits
21347 #define R13 DAC1CON2bits.R13 // bit 5, shadows bit in DAC1CON2bits
21348 #define DAC1R13 DAC1CON2bits.DAC1R13 // bit 5, shadows bit in DAC1CON2bits
21349 #define REF14 DAC1CON2bits.REF14 // bit 6, shadows bit in DAC1CON2bits
21350 #define DAC1REF14 DAC1CON2bits.DAC1REF14 // bit 6, shadows bit in DAC1CON2bits
21351 #define R14 DAC1CON2bits.R14 // bit 6, shadows bit in DAC1CON2bits
21352 #define DAC1R14 DAC1CON2bits.DAC1R14 // bit 6, shadows bit in DAC1CON2bits
21353 #define REF15 DAC1CON2bits.REF15 // bit 7, shadows bit in DAC1CON2bits
21354 #define DAC1REF15 DAC1CON2bits.DAC1REF15 // bit 7, shadows bit in DAC1CON2bits
21355 #define R15 DAC1CON2bits.R15 // bit 7, shadows bit in DAC1CON2bits
21356 #define DAC1R15 DAC1CON2bits.DAC1R15 // bit 7, shadows bit in DAC1CON2bits
21358 #define DAC1LD DACLDbits.DAC1LD // bit 0
21359 #define DAC2LD DACLDbits.DAC2LD // bit 1
21360 #define DAC5LD DACLDbits.DAC5LD // bit 4
21362 #define TSRNG FVRCONbits.TSRNG // bit 4
21363 #define TSEN FVRCONbits.TSEN // bit 5
21364 #define FVRRDY FVRCONbits.FVRRDY // bit 6
21365 #define FVREN FVRCONbits.FVREN // bit 7
21367 #define HIDB0 HIDRVBbits.HIDB0 // bit 0
21368 #define HIDB1 HIDRVBbits.HIDB1 // bit 1
21370 #define INLVE3 INLVEbits.INLVE3 // bit 3
21372 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
21373 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
21374 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
21375 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
21376 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
21377 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
21378 #define INLVA6 INLVLAbits.INLVA6 // bit 6
21379 #define INLVA7 INLVLAbits.INLVA7 // bit 7
21381 #define INLVB0 INLVLBbits.INLVB0 // bit 0
21382 #define INLVB1 INLVLBbits.INLVB1 // bit 1
21383 #define INLVB2 INLVLBbits.INLVB2 // bit 2
21384 #define INLVB3 INLVLBbits.INLVB3 // bit 3
21385 #define INLVLB4 INLVLBbits.INLVLB4 // bit 4
21386 #define INLVLB5 INLVLBbits.INLVLB5 // bit 5
21387 #define INLVLB6 INLVLBbits.INLVLB6 // bit 6
21388 #define INLVLB7 INLVLBbits.INLVLB7 // bit 7
21390 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
21391 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
21392 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
21393 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
21394 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
21395 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
21396 #define INLVLC6 INLVLCbits.INLVLC6 // bit 6
21397 #define INLVLC7 INLVLCbits.INLVLC7 // bit 7
21399 #define IOCIF INTCONbits.IOCIF // bit 0
21400 #define INTF INTCONbits.INTF // bit 1
21401 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
21402 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
21403 #define IOCIE INTCONbits.IOCIE // bit 3
21404 #define INTE INTCONbits.INTE // bit 4
21405 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
21406 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
21407 #define PEIE INTCONbits.PEIE // bit 6
21408 #define GIE INTCONbits.GIE // bit 7
21410 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
21411 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
21412 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
21413 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
21414 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
21415 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
21416 #define IOCAF6 IOCAFbits.IOCAF6 // bit 6
21417 #define IOCAF7 IOCAFbits.IOCAF7 // bit 7
21419 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
21420 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
21421 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
21422 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
21423 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
21424 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
21425 #define IOCAN6 IOCANbits.IOCAN6 // bit 6
21426 #define IOCAN7 IOCANbits.IOCAN7 // bit 7
21428 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
21429 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
21430 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
21431 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
21432 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
21433 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
21434 #define IOCAP6 IOCAPbits.IOCAP6 // bit 6
21435 #define IOCAP7 IOCAPbits.IOCAP7 // bit 7
21437 #define IOCBF0 IOCBFbits.IOCBF0 // bit 0
21438 #define IOCBF1 IOCBFbits.IOCBF1 // bit 1
21439 #define IOCBF2 IOCBFbits.IOCBF2 // bit 2
21440 #define IOCBF3 IOCBFbits.IOCBF3 // bit 3
21441 #define IOCBF4 IOCBFbits.IOCBF4 // bit 4
21442 #define IOCBF5 IOCBFbits.IOCBF5 // bit 5
21443 #define IOCBF6 IOCBFbits.IOCBF6 // bit 6
21444 #define IOCBF7 IOCBFbits.IOCBF7 // bit 7
21446 #define IOCBN0 IOCBNbits.IOCBN0 // bit 0
21447 #define IOCBN1 IOCBNbits.IOCBN1 // bit 1
21448 #define IOCBN2 IOCBNbits.IOCBN2 // bit 2
21449 #define IOCBN3 IOCBNbits.IOCBN3 // bit 3
21450 #define IOCBN4 IOCBNbits.IOCBN4 // bit 4
21451 #define IOCBN5 IOCBNbits.IOCBN5 // bit 5
21452 #define IOCBN6 IOCBNbits.IOCBN6 // bit 6
21453 #define IOCBN7 IOCBNbits.IOCBN7 // bit 7
21455 #define IOCBP0 IOCBPbits.IOCBP0 // bit 0
21456 #define IOCBP1 IOCBPbits.IOCBP1 // bit 1
21457 #define IOCBP2 IOCBPbits.IOCBP2 // bit 2
21458 #define IOCBP3 IOCBPbits.IOCBP3 // bit 3
21459 #define IOCBP4 IOCBPbits.IOCBP4 // bit 4
21460 #define IOCBP5 IOCBPbits.IOCBP5 // bit 5
21461 #define IOCBP6 IOCBPbits.IOCBP6 // bit 6
21462 #define IOCBP7 IOCBPbits.IOCBP7 // bit 7
21464 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
21465 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
21466 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
21467 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
21468 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
21469 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
21470 #define IOCCF6 IOCCFbits.IOCCF6 // bit 6
21471 #define IOCCF7 IOCCFbits.IOCCF7 // bit 7
21473 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
21474 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
21475 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
21476 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
21477 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
21478 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
21479 #define IOCCN6 IOCCNbits.IOCCN6 // bit 6
21480 #define IOCCN7 IOCCNbits.IOCCN7 // bit 7
21482 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
21483 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
21484 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
21485 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
21486 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
21487 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
21488 #define IOCCP6 IOCCPbits.IOCCP6 // bit 6
21489 #define IOCCP7 IOCCPbits.IOCCP7 // bit 7
21491 #define IOCEF3 IOCEFbits.IOCEF3 // bit 3
21493 #define IOCEN3 IOCENbits.IOCEN3 // bit 3
21495 #define IOCEP3 IOCEPbits.IOCEP3 // bit 3
21497 #define LATA0 LATAbits.LATA0 // bit 0
21498 #define LATA1 LATAbits.LATA1 // bit 1
21499 #define LATA2 LATAbits.LATA2 // bit 2
21500 #define LATA3 LATAbits.LATA3 // bit 3
21501 #define LATA4 LATAbits.LATA4 // bit 4
21502 #define LATA5 LATAbits.LATA5 // bit 5
21503 #define LATA6 LATAbits.LATA6 // bit 6
21504 #define LATA7 LATAbits.LATA7 // bit 7
21506 #define LATB0 LATBbits.LATB0 // bit 0
21507 #define LATB1 LATBbits.LATB1 // bit 1
21508 #define LATB2 LATBbits.LATB2 // bit 2
21509 #define LATB3 LATBbits.LATB3 // bit 3
21510 #define LATB4 LATBbits.LATB4 // bit 4
21511 #define LATB5 LATBbits.LATB5 // bit 5
21512 #define LATB6 LATBbits.LATB6 // bit 6
21513 #define LATB7 LATBbits.LATB7 // bit 7
21515 #define LATC0 LATCbits.LATC0 // bit 0
21516 #define LATC1 LATCbits.LATC1 // bit 1
21517 #define LATC2 LATCbits.LATC2 // bit 2
21518 #define LATC3 LATCbits.LATC3 // bit 3
21519 #define LATC4 LATCbits.LATC4 // bit 4
21520 #define LATC5 LATCbits.LATC5 // bit 5
21521 #define LATC6 LATCbits.LATC6 // bit 6
21522 #define LATC7 LATCbits.LATC7 // bit 7
21524 #define CH0 MD1CARHbits.CH0 // bit 0, shadows bit in MD1CARHbits
21525 #define MD1CH0 MD1CARHbits.MD1CH0 // bit 0, shadows bit in MD1CARHbits
21526 #define CH1 MD1CARHbits.CH1 // bit 1, shadows bit in MD1CARHbits
21527 #define MD1CH1 MD1CARHbits.MD1CH1 // bit 1, shadows bit in MD1CARHbits
21528 #define CH2 MD1CARHbits.CH2 // bit 2, shadows bit in MD1CARHbits
21529 #define MD1CH2 MD1CARHbits.MD1CH2 // bit 2, shadows bit in MD1CARHbits
21530 #define CH3 MD1CARHbits.CH3 // bit 3, shadows bit in MD1CARHbits
21531 #define MD1CH3 MD1CARHbits.MD1CH3 // bit 3, shadows bit in MD1CARHbits
21532 #define CH4 MD1CARHbits.CH4 // bit 4
21534 #define CL0 MD1CARLbits.CL0 // bit 0, shadows bit in MD1CARLbits
21535 #define MD1CL0 MD1CARLbits.MD1CL0 // bit 0, shadows bit in MD1CARLbits
21536 #define CL1 MD1CARLbits.CL1 // bit 1, shadows bit in MD1CARLbits
21537 #define MD1CL1 MD1CARLbits.MD1CL1 // bit 1, shadows bit in MD1CARLbits
21538 #define CL2 MD1CARLbits.CL2 // bit 2, shadows bit in MD1CARLbits
21539 #define MD1CL2 MD1CARLbits.MD1CL2 // bit 2, shadows bit in MD1CARLbits
21540 #define CL3 MD1CARLbits.CL3 // bit 3, shadows bit in MD1CARLbits
21541 #define MD1CL3 MD1CARLbits.MD1CL3 // bit 3, shadows bit in MD1CARLbits
21542 #define CL4 MD1CARLbits.CL4 // bit 4
21544 #define CLSYNC MD1CON1bits.CLSYNC // bit 0, shadows bit in MD1CON1bits
21545 #define MD1CLSYNC MD1CON1bits.MD1CLSYNC // bit 0, shadows bit in MD1CON1bits
21546 #define CLPOL MD1CON1bits.CLPOL // bit 1, shadows bit in MD1CON1bits
21547 #define MD1CLPOL MD1CON1bits.MD1CLPOL // bit 1, shadows bit in MD1CON1bits
21548 #define CHSYNC MD1CON1bits.CHSYNC // bit 4, shadows bit in MD1CON1bits
21549 #define MD1CHSYNC MD1CON1bits.MD1CHSYNC // bit 4, shadows bit in MD1CON1bits
21550 #define CHPOL MD1CON1bits.CHPOL // bit 5, shadows bit in MD1CON1bits
21551 #define MD1CHPOL MD1CON1bits.MD1CHPOL // bit 5, shadows bit in MD1CON1bits
21553 #define MS0 MD1SRCbits.MS0 // bit 0, shadows bit in MD1SRCbits
21554 #define MD1MS0 MD1SRCbits.MD1MS0 // bit 0, shadows bit in MD1SRCbits
21555 #define MS1 MD1SRCbits.MS1 // bit 1, shadows bit in MD1SRCbits
21556 #define MD1MS1 MD1SRCbits.MD1MS1 // bit 1, shadows bit in MD1SRCbits
21557 #define MS2 MD1SRCbits.MS2 // bit 2, shadows bit in MD1SRCbits
21558 #define MD1MS2 MD1SRCbits.MD1MS2 // bit 2, shadows bit in MD1SRCbits
21559 #define MS3 MD1SRCbits.MS3 // bit 3, shadows bit in MD1SRCbits
21560 #define MD1MS3 MD1SRCbits.MD1MS3 // bit 3, shadows bit in MD1SRCbits
21561 #define MS4 MD1SRCbits.MS4 // bit 4, shadows bit in MD1SRCbits
21562 #define MD1MS4 MD1SRCbits.MD1MS4 // bit 4, shadows bit in MD1SRCbits
21564 #define ODA0 ODCONAbits.ODA0 // bit 0
21565 #define ODA1 ODCONAbits.ODA1 // bit 1
21566 #define ODA2 ODCONAbits.ODA2 // bit 2
21567 #define ODA3 ODCONAbits.ODA3 // bit 3
21568 #define ODA4 ODCONAbits.ODA4 // bit 4
21569 #define ODA5 ODCONAbits.ODA5 // bit 5
21570 #define ODA6 ODCONAbits.ODA6 // bit 6
21571 #define ODA7 ODCONAbits.ODA7 // bit 7
21573 #define ODC0 ODCONCbits.ODC0 // bit 0
21574 #define ODC1 ODCONCbits.ODC1 // bit 1
21575 #define ODC2 ODCONCbits.ODC2 // bit 2
21576 #define ODC3 ODCONCbits.ODC3 // bit 3
21577 #define ODC4 ODCONCbits.ODC4 // bit 4
21578 #define ODC5 ODCONCbits.ODC5 // bit 5
21579 #define ODC6 ODCONCbits.ODC6 // bit 6
21580 #define ODC7 ODCONCbits.ODC7 // bit 7
21582 #define PS0 OPTION_REGbits.PS0 // bit 0
21583 #define PS1 OPTION_REGbits.PS1 // bit 1
21584 #define PS2 OPTION_REGbits.PS2 // bit 2
21585 #define PSA OPTION_REGbits.PSA // bit 3
21586 #define TMR0SE OPTION_REGbits.TMR0SE // bit 4, shadows bit in OPTION_REGbits
21587 #define T0SE OPTION_REGbits.T0SE // bit 4, shadows bit in OPTION_REGbits
21588 #define TMR0CS OPTION_REGbits.TMR0CS // bit 5, shadows bit in OPTION_REGbits
21589 #define T0CS OPTION_REGbits.T0CS // bit 5, shadows bit in OPTION_REGbits
21590 #define INTEDG OPTION_REGbits.INTEDG // bit 6
21591 #define NOT_WPUEN OPTION_REGbits.NOT_WPUEN // bit 7
21593 #define SCS0 OSCCONbits.SCS0 // bit 0
21594 #define SCS1 OSCCONbits.SCS1 // bit 1
21595 #define IRCF0 OSCCONbits.IRCF0 // bit 3
21596 #define IRCF1 OSCCONbits.IRCF1 // bit 4
21597 #define IRCF2 OSCCONbits.IRCF2 // bit 5
21598 #define IRCF3 OSCCONbits.IRCF3 // bit 6
21599 #define SPLLEN OSCCONbits.SPLLEN // bit 7
21601 #define HFIOFS OSCSTATbits.HFIOFS // bit 0
21602 #define LFIOFR OSCSTATbits.LFIOFR // bit 1
21603 #define MFIOFR OSCSTATbits.MFIOFR // bit 2
21604 #define HFIOFL OSCSTATbits.HFIOFL // bit 3
21605 #define HFIOFR OSCSTATbits.HFIOFR // bit 4
21606 #define OSTS OSCSTATbits.OSTS // bit 5
21607 #define PLLR OSCSTATbits.PLLR // bit 6
21608 #define SOSCR OSCSTATbits.SOSCR // bit 7
21610 #define TUN0 OSCTUNEbits.TUN0 // bit 0
21611 #define TUN1 OSCTUNEbits.TUN1 // bit 1
21612 #define TUN2 OSCTUNEbits.TUN2 // bit 2
21613 #define TUN3 OSCTUNEbits.TUN3 // bit 3
21614 #define TUN4 OSCTUNEbits.TUN4 // bit 4
21615 #define TUN5 OSCTUNEbits.TUN5 // bit 5
21617 #define NOT_BOR PCONbits.NOT_BOR // bit 0
21618 #define NOT_POR PCONbits.NOT_POR // bit 1
21619 #define NOT_RI PCONbits.NOT_RI // bit 2
21620 #define NOT_RMCLR PCONbits.NOT_RMCLR // bit 3
21621 #define NOT_RWDT PCONbits.NOT_RWDT // bit 4
21622 #define STKUNF PCONbits.STKUNF // bit 6
21623 #define STKOVF PCONbits.STKOVF // bit 7
21625 #define TMR1IE PIE1bits.TMR1IE // bit 0
21626 #define TMR2IE PIE1bits.TMR2IE // bit 1
21627 #define CCP1IE PIE1bits.CCP1IE // bit 2, shadows bit in PIE1bits
21628 #define CCPIE PIE1bits.CCPIE // bit 2, shadows bit in PIE1bits
21629 #define SSP1IE PIE1bits.SSP1IE // bit 3
21630 #define TXIE PIE1bits.TXIE // bit 4
21631 #define RCIE PIE1bits.RCIE // bit 5
21632 #define ADIE PIE1bits.ADIE // bit 6
21633 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
21635 #define CCP2IE PIE2bits.CCP2IE // bit 0
21636 #define C3IE PIE2bits.C3IE // bit 1
21637 #define C4IE PIE2bits.C4IE // bit 2
21638 #define BCL1IE PIE2bits.BCL1IE // bit 3
21639 #define COGIE PIE2bits.COGIE // bit 4
21640 #define C1IE PIE2bits.C1IE // bit 5
21641 #define C2IE PIE2bits.C2IE // bit 6
21642 #define OSFIE PIE2bits.OSFIE // bit 7
21644 #define CLC1IE PIE3bits.CLC1IE // bit 0
21645 #define CLC2IE PIE3bits.CLC2IE // bit 1
21646 #define CLC3IE PIE3bits.CLC3IE // bit 2
21647 #define CLC4IE PIE3bits.CLC4IE // bit 3
21648 #define ZCDIE PIE3bits.ZCDIE // bit 4
21649 #define COG2IE PIE3bits.COG2IE // bit 5
21651 #define TMR4IE PIE4bits.TMR4IE // bit 0
21652 #define TMR6IE PIE4bits.TMR6IE // bit 1
21653 #define TMR3IE PIE4bits.TMR3IE // bit 2
21654 #define TMR3GIE PIE4bits.TMR3GIE // bit 3
21655 #define TMR5IE PIE4bits.TMR5IE // bit 4
21656 #define TMR5GIE PIE4bits.TMR5GIE // bit 5
21657 #define TMR8IE PIE4bits.TMR8IE // bit 6
21659 #define C5IE PIE5bits.C5IE // bit 0
21660 #define C6IE PIE5bits.C6IE // bit 1
21661 #define COG3IE PIE5bits.COG3IE // bit 4
21662 #define CCP7IE PIE5bits.CCP7IE // bit 6
21664 #define PWM5IE PIE6bits.PWM5IE // bit 0
21665 #define PWM6IE PIE6bits.PWM6IE // bit 1
21666 #define PWM11IE PIE6bits.PWM11IE // bit 2
21668 #define TMR1IF PIR1bits.TMR1IF // bit 0
21669 #define TMR2IF PIR1bits.TMR2IF // bit 1
21670 #define CCP1IF PIR1bits.CCP1IF // bit 2, shadows bit in PIR1bits
21671 #define CCPIF PIR1bits.CCPIF // bit 2, shadows bit in PIR1bits
21672 #define SSP1IF PIR1bits.SSP1IF // bit 3
21673 #define TXIF PIR1bits.TXIF // bit 4
21674 #define RCIF PIR1bits.RCIF // bit 5
21675 #define ADIF PIR1bits.ADIF // bit 6
21676 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
21678 #define CCP2IF PIR2bits.CCP2IF // bit 0
21679 #define C3IF PIR2bits.C3IF // bit 1
21680 #define C4IF PIR2bits.C4IF // bit 2
21681 #define BCL1IF PIR2bits.BCL1IF // bit 3
21682 #define COG1IF PIR2bits.COG1IF // bit 4
21683 #define C1IF PIR2bits.C1IF // bit 5
21684 #define C2IF PIR2bits.C2IF // bit 6
21685 #define OSFIF PIR2bits.OSFIF // bit 7
21687 #define CLC1IF PIR3bits.CLC1IF // bit 0
21688 #define CLC2IF PIR3bits.CLC2IF // bit 1
21689 #define CLC3IF PIR3bits.CLC3IF // bit 2
21690 #define CLC4IF PIR3bits.CLC4IF // bit 3
21691 #define ZCDIF PIR3bits.ZCDIF // bit 4
21692 #define COG2IF PIR3bits.COG2IF // bit 5
21694 #define TMR4IF PIR4bits.TMR4IF // bit 0
21695 #define TMR6IF PIR4bits.TMR6IF // bit 1
21696 #define TMR3IF PIR4bits.TMR3IF // bit 2
21697 #define TMR3GIF PIR4bits.TMR3GIF // bit 3
21698 #define TMR5IF PIR4bits.TMR5IF // bit 4
21699 #define TMR5GIF PIR4bits.TMR5GIF // bit 5
21700 #define TMR8IF PIR4bits.TMR8IF // bit 6
21702 #define C5IF PIR5bits.C5IF // bit 0
21703 #define C6IF PIR5bits.C6IF // bit 1
21704 #define COG3IF PIR5bits.COG3IF // bit 4
21705 #define CCP7IF PIR5bits.CCP7IF // bit 6
21707 #define PWM5IF PIR6bits.PWM5IF // bit 0
21708 #define PWM6IF PIR6bits.PWM6IF // bit 1
21709 #define PWM11IF PIR6bits.PWM11IF // bit 2
21711 #define RD PMCON1bits.RD // bit 0
21712 #define WR PMCON1bits.WR // bit 1
21713 #define WREN PMCON1bits.WREN // bit 2
21714 #define WRERR PMCON1bits.WRERR // bit 3
21715 #define FREE PMCON1bits.FREE // bit 4
21716 #define LWLO PMCON1bits.LWLO // bit 5
21717 #define CFGS PMCON1bits.CFGS // bit 6
21719 #define RA0 PORTAbits.RA0 // bit 0
21720 #define RA1 PORTAbits.RA1 // bit 1
21721 #define RA2 PORTAbits.RA2 // bit 2
21722 #define RA3 PORTAbits.RA3 // bit 3
21723 #define RA4 PORTAbits.RA4 // bit 4
21724 #define RA5 PORTAbits.RA5 // bit 5
21725 #define RA6 PORTAbits.RA6 // bit 6
21726 #define RA7 PORTAbits.RA7 // bit 7
21728 #define RB0 PORTBbits.RB0 // bit 0
21729 #define RB1 PORTBbits.RB1 // bit 1
21730 #define RB2 PORTBbits.RB2 // bit 2
21731 #define RB3 PORTBbits.RB3 // bit 3
21732 #define RB4 PORTBbits.RB4 // bit 4
21733 #define RB5 PORTBbits.RB5 // bit 5
21734 #define RB6 PORTBbits.RB6 // bit 6
21735 #define RB7 PORTBbits.RB7 // bit 7
21737 #define RC0 PORTCbits.RC0 // bit 0
21738 #define RC1 PORTCbits.RC1 // bit 1
21739 #define RC2 PORTCbits.RC2 // bit 2
21740 #define RC3 PORTCbits.RC3 // bit 3
21741 #define RC4 PORTCbits.RC4 // bit 4
21742 #define RC5 PORTCbits.RC5 // bit 5
21743 #define RC6 PORTCbits.RC6 // bit 6
21744 #define RC7 PORTCbits.RC7 // bit 7
21746 #define RE3 PORTEbits.RE3 // bit 3
21748 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
21750 #define RPOL PRG1CON1bits.RPOL // bit 0, shadows bit in PRG1CON1bits
21751 #define RG1RPOL PRG1CON1bits.RG1RPOL // bit 0, shadows bit in PRG1CON1bits
21752 #define FPOL PRG1CON1bits.FPOL // bit 1, shadows bit in PRG1CON1bits
21753 #define RG1FPOL PRG1CON1bits.RG1FPOL // bit 1, shadows bit in PRG1CON1bits
21754 #define RDY PRG1CON1bits.RDY // bit 2, shadows bit in PRG1CON1bits
21755 #define RG1RDY PRG1CON1bits.RG1RDY // bit 2, shadows bit in PRG1CON1bits
21757 #define ISET0 PRG1CON2bits.ISET0 // bit 0, shadows bit in PRG1CON2bits
21758 #define RG1ISET0 PRG1CON2bits.RG1ISET0 // bit 0, shadows bit in PRG1CON2bits
21759 #define ISET1 PRG1CON2bits.ISET1 // bit 1, shadows bit in PRG1CON2bits
21760 #define RG1ISET1 PRG1CON2bits.RG1ISET1 // bit 1, shadows bit in PRG1CON2bits
21761 #define ISET2 PRG1CON2bits.ISET2 // bit 2, shadows bit in PRG1CON2bits
21762 #define RG1ISET2 PRG1CON2bits.RG1ISET2 // bit 2, shadows bit in PRG1CON2bits
21763 #define ISET3 PRG1CON2bits.ISET3 // bit 3, shadows bit in PRG1CON2bits
21764 #define RG1ISET3 PRG1CON2bits.RG1ISET3 // bit 3, shadows bit in PRG1CON2bits
21765 #define ISET4 PRG1CON2bits.ISET4 // bit 4, shadows bit in PRG1CON2bits
21766 #define RG1ISET4 PRG1CON2bits.RG1ISET4 // bit 4, shadows bit in PRG1CON2bits
21768 #define FTSS0 PRG1FTSSbits.FTSS0 // bit 0, shadows bit in PRG1FTSSbits
21769 #define RG1FTSS0 PRG1FTSSbits.RG1FTSS0 // bit 0, shadows bit in PRG1FTSSbits
21770 #define FTSS1 PRG1FTSSbits.FTSS1 // bit 1, shadows bit in PRG1FTSSbits
21771 #define RG1FTSS1 PRG1FTSSbits.RG1FTSS1 // bit 1, shadows bit in PRG1FTSSbits
21772 #define FTSS2 PRG1FTSSbits.FTSS2 // bit 2, shadows bit in PRG1FTSSbits
21773 #define RG1FTSS2 PRG1FTSSbits.RG1FTSS2 // bit 2, shadows bit in PRG1FTSSbits
21774 #define FTSS3 PRG1FTSSbits.FTSS3 // bit 3, shadows bit in PRG1FTSSbits
21775 #define RG1FTSS3 PRG1FTSSbits.RG1FTSS3 // bit 3, shadows bit in PRG1FTSSbits
21777 #define INS0 PRG1INSbits.INS0 // bit 0, shadows bit in PRG1INSbits
21778 #define RG1INS0 PRG1INSbits.RG1INS0 // bit 0, shadows bit in PRG1INSbits
21779 #define INS1 PRG1INSbits.INS1 // bit 1, shadows bit in PRG1INSbits
21780 #define RG1INS1 PRG1INSbits.RG1INS1 // bit 1, shadows bit in PRG1INSbits
21781 #define INS2 PRG1INSbits.INS2 // bit 2, shadows bit in PRG1INSbits
21782 #define RG1INS2 PRG1INSbits.RG1INS2 // bit 2, shadows bit in PRG1INSbits
21783 #define INS3 PRG1INSbits.INS3 // bit 3, shadows bit in PRG1INSbits
21784 #define RG1INS3 PRG1INSbits.RG1INS3 // bit 3, shadows bit in PRG1INSbits
21786 #define RTSS0 PRG1RTSSbits.RTSS0 // bit 0, shadows bit in PRG1RTSSbits
21787 #define RG1RTSS0 PRG1RTSSbits.RG1RTSS0 // bit 0, shadows bit in PRG1RTSSbits
21788 #define RTSS1 PRG1RTSSbits.RTSS1 // bit 1, shadows bit in PRG1RTSSbits
21789 #define RG1RTSS1 PRG1RTSSbits.RG1RTSS1 // bit 1, shadows bit in PRG1RTSSbits
21790 #define RTSS2 PRG1RTSSbits.RTSS2 // bit 2, shadows bit in PRG1RTSSbits
21791 #define RG1RTSS2 PRG1RTSSbits.RG1RTSS2 // bit 2, shadows bit in PRG1RTSSbits
21792 #define RTSS3 PRG1RTSSbits.RTSS3 // bit 3, shadows bit in PRG1RTSSbits
21793 #define RG1RTSS3 PRG1RTSSbits.RG1RTSS3 // bit 3, shadows bit in PRG1RTSSbits
21795 #define DC2 PWM3DCHbits.DC2 // bit 0, shadows bit in PWM3DCHbits
21796 #define PWM3DC2 PWM3DCHbits.PWM3DC2 // bit 0, shadows bit in PWM3DCHbits
21797 #define PWMPW2 PWM3DCHbits.PWMPW2 // bit 0, shadows bit in PWM3DCHbits
21798 #define DC3 PWM3DCHbits.DC3 // bit 1, shadows bit in PWM3DCHbits
21799 #define PWM3DC3 PWM3DCHbits.PWM3DC3 // bit 1, shadows bit in PWM3DCHbits
21800 #define PWMPW3 PWM3DCHbits.PWMPW3 // bit 1, shadows bit in PWM3DCHbits
21801 #define DC4 PWM3DCHbits.DC4 // bit 2, shadows bit in PWM3DCHbits
21802 #define PWM3DC4 PWM3DCHbits.PWM3DC4 // bit 2, shadows bit in PWM3DCHbits
21803 #define PWMPW4 PWM3DCHbits.PWMPW4 // bit 2, shadows bit in PWM3DCHbits
21804 #define DC5 PWM3DCHbits.DC5 // bit 3, shadows bit in PWM3DCHbits
21805 #define PWM3DC5 PWM3DCHbits.PWM3DC5 // bit 3, shadows bit in PWM3DCHbits
21806 #define PWMPW5 PWM3DCHbits.PWMPW5 // bit 3, shadows bit in PWM3DCHbits
21807 #define DC6 PWM3DCHbits.DC6 // bit 4, shadows bit in PWM3DCHbits
21808 #define PWM3DC6 PWM3DCHbits.PWM3DC6 // bit 4, shadows bit in PWM3DCHbits
21809 #define PWMPW6 PWM3DCHbits.PWMPW6 // bit 4, shadows bit in PWM3DCHbits
21810 #define DC7 PWM3DCHbits.DC7 // bit 5, shadows bit in PWM3DCHbits
21811 #define PWM3DC7 PWM3DCHbits.PWM3DC7 // bit 5, shadows bit in PWM3DCHbits
21812 #define PWMPW7 PWM3DCHbits.PWMPW7 // bit 5, shadows bit in PWM3DCHbits
21813 #define DC8 PWM3DCHbits.DC8 // bit 6, shadows bit in PWM3DCHbits
21814 #define PWM3DC8 PWM3DCHbits.PWM3DC8 // bit 6, shadows bit in PWM3DCHbits
21815 #define PWMPW8 PWM3DCHbits.PWMPW8 // bit 6, shadows bit in PWM3DCHbits
21816 #define DC9 PWM3DCHbits.DC9 // bit 7, shadows bit in PWM3DCHbits
21817 #define PWM3DC9 PWM3DCHbits.PWM3DC9 // bit 7, shadows bit in PWM3DCHbits
21818 #define PWMPW9 PWM3DCHbits.PWMPW9 // bit 7, shadows bit in PWM3DCHbits
21820 #define DC0 PWM3DCLbits.DC0 // bit 6, shadows bit in PWM3DCLbits
21821 #define PWM3DC0 PWM3DCLbits.PWM3DC0 // bit 6, shadows bit in PWM3DCLbits
21822 #define PWMPW0 PWM3DCLbits.PWMPW0 // bit 6, shadows bit in PWM3DCLbits
21823 #define DC1 PWM3DCLbits.DC1 // bit 7, shadows bit in PWM3DCLbits
21824 #define PWM3DC1 PWM3DCLbits.PWM3DC1 // bit 7, shadows bit in PWM3DCLbits
21825 #define PWMPW1 PWM3DCLbits.PWMPW1 // bit 7, shadows bit in PWM3DCLbits
21827 #define PWM5DCH0 PWM5DCHbits.PWM5DCH0 // bit 0
21828 #define PWM5DCH1 PWM5DCHbits.PWM5DCH1 // bit 1
21829 #define PWM5DCH2 PWM5DCHbits.PWM5DCH2 // bit 2
21830 #define PWM5DCH3 PWM5DCHbits.PWM5DCH3 // bit 3
21831 #define PWM5DCH4 PWM5DCHbits.PWM5DCH4 // bit 4
21832 #define PWM5DCH5 PWM5DCHbits.PWM5DCH5 // bit 5
21833 #define PWM5DCH6 PWM5DCHbits.PWM5DCH6 // bit 6
21834 #define PWM5DCH7 PWM5DCHbits.PWM5DCH7 // bit 7
21836 #define PWM5DCL0 PWM5DCLbits.PWM5DCL0 // bit 0
21837 #define PWM5DCL1 PWM5DCLbits.PWM5DCL1 // bit 1
21838 #define PWM5DCL2 PWM5DCLbits.PWM5DCL2 // bit 2
21839 #define PWM5DCL3 PWM5DCLbits.PWM5DCL3 // bit 3
21840 #define PWM5DCL4 PWM5DCLbits.PWM5DCL4 // bit 4
21841 #define PWM5DCL5 PWM5DCLbits.PWM5DCL5 // bit 5
21842 #define PWM5DCL6 PWM5DCLbits.PWM5DCL6 // bit 6
21843 #define PWM5DCL7 PWM5DCLbits.PWM5DCL7 // bit 7
21845 #define PRIE PWM5INTCONbits.PRIE // bit 0, shadows bit in PWM5INTCONbits
21846 #define PWM5PRIE PWM5INTCONbits.PWM5PRIE // bit 0, shadows bit in PWM5INTCONbits
21847 #define DCIE PWM5INTCONbits.DCIE // bit 1, shadows bit in PWM5INTCONbits
21848 #define PWM5DCIE PWM5INTCONbits.PWM5DCIE // bit 1, shadows bit in PWM5INTCONbits
21849 #define PHIE PWM5INTCONbits.PHIE // bit 2, shadows bit in PWM5INTCONbits
21850 #define PWM5PHIE PWM5INTCONbits.PWM5PHIE // bit 2, shadows bit in PWM5INTCONbits
21851 #define OFIE PWM5INTCONbits.OFIE // bit 3, shadows bit in PWM5INTCONbits
21852 #define PWM5OFIE PWM5INTCONbits.PWM5OFIE // bit 3, shadows bit in PWM5INTCONbits
21854 #define PRIF PWM5INTFbits.PRIF // bit 0, shadows bit in PWM5INTFbits
21855 #define PWM5PRIF PWM5INTFbits.PWM5PRIF // bit 0, shadows bit in PWM5INTFbits
21856 #define DCIF PWM5INTFbits.DCIF // bit 1, shadows bit in PWM5INTFbits
21857 #define PWM5DCIF PWM5INTFbits.PWM5DCIF // bit 1, shadows bit in PWM5INTFbits
21858 #define PHIF PWM5INTFbits.PHIF // bit 2, shadows bit in PWM5INTFbits
21859 #define PWM5PHIF PWM5INTFbits.PWM5PHIF // bit 2, shadows bit in PWM5INTFbits
21860 #define OFIF PWM5INTFbits.OFIF // bit 3, shadows bit in PWM5INTFbits
21861 #define PWM5OFIF PWM5INTFbits.PWM5OFIF // bit 3, shadows bit in PWM5INTFbits
21863 #define PWM5LDS0 PWM5LDCONbits.PWM5LDS0 // bit 0, shadows bit in PWM5LDCONbits
21864 #define LDS0 PWM5LDCONbits.LDS0 // bit 0, shadows bit in PWM5LDCONbits
21865 #define PWM5LDS1 PWM5LDCONbits.PWM5LDS1 // bit 1, shadows bit in PWM5LDCONbits
21866 #define LDS1 PWM5LDCONbits.LDS1 // bit 1, shadows bit in PWM5LDCONbits
21867 #define LDT PWM5LDCONbits.LDT // bit 6, shadows bit in PWM5LDCONbits
21868 #define PWM5LDM PWM5LDCONbits.PWM5LDM // bit 6, shadows bit in PWM5LDCONbits
21869 #define LDA PWM5LDCONbits.LDA // bit 7, shadows bit in PWM5LDCONbits
21870 #define PWM5LD PWM5LDCONbits.PWM5LD // bit 7, shadows bit in PWM5LDCONbits
21872 #define PWM5OFS0 PWM5OFCONbits.PWM5OFS0 // bit 0, shadows bit in PWM5OFCONbits
21873 #define OFS0 PWM5OFCONbits.OFS0 // bit 0, shadows bit in PWM5OFCONbits
21874 #define PWM5OFS1 PWM5OFCONbits.PWM5OFS1 // bit 1, shadows bit in PWM5OFCONbits
21875 #define OFS1 PWM5OFCONbits.OFS1 // bit 1, shadows bit in PWM5OFCONbits
21876 #define OFO PWM5OFCONbits.OFO // bit 4, shadows bit in PWM5OFCONbits
21877 #define PWM5OFMC PWM5OFCONbits.PWM5OFMC // bit 4, shadows bit in PWM5OFCONbits
21878 #define PWM5OFM0 PWM5OFCONbits.PWM5OFM0 // bit 5, shadows bit in PWM5OFCONbits
21879 #define OFM0 PWM5OFCONbits.OFM0 // bit 5, shadows bit in PWM5OFCONbits
21880 #define PWM5OFM1 PWM5OFCONbits.PWM5OFM1 // bit 6, shadows bit in PWM5OFCONbits
21881 #define OFM1 PWM5OFCONbits.OFM1 // bit 6, shadows bit in PWM5OFCONbits
21883 #define PWM5OFH0 PWM5OFHbits.PWM5OFH0 // bit 0
21884 #define PWM5OFH1 PWM5OFHbits.PWM5OFH1 // bit 1
21885 #define PWM5OFH2 PWM5OFHbits.PWM5OFH2 // bit 2
21886 #define PWM5OFH3 PWM5OFHbits.PWM5OFH3 // bit 3
21887 #define PWM5OFH4 PWM5OFHbits.PWM5OFH4 // bit 4
21888 #define PWM5OFH5 PWM5OFHbits.PWM5OFH5 // bit 5
21889 #define PWM5OFH6 PWM5OFHbits.PWM5OFH6 // bit 6
21890 #define PWM5OFH7 PWM5OFHbits.PWM5OFH7 // bit 7
21892 #define PWM5OFL0 PWM5OFLbits.PWM5OFL0 // bit 0
21893 #define PWM5OFL1 PWM5OFLbits.PWM5OFL1 // bit 1
21894 #define PWM5OFL2 PWM5OFLbits.PWM5OFL2 // bit 2
21895 #define PWM5OFL3 PWM5OFLbits.PWM5OFL3 // bit 3
21896 #define PWM5OFL4 PWM5OFLbits.PWM5OFL4 // bit 4
21897 #define PWM5OFL5 PWM5OFLbits.PWM5OFL5 // bit 5
21898 #define PWM5OFL6 PWM5OFLbits.PWM5OFL6 // bit 6
21899 #define PWM5OFL7 PWM5OFLbits.PWM5OFL7 // bit 7
21901 #define PWM5PHH0 PWM5PHHbits.PWM5PHH0 // bit 0
21902 #define PWM5PHH1 PWM5PHHbits.PWM5PHH1 // bit 1
21903 #define PWM5PHH2 PWM5PHHbits.PWM5PHH2 // bit 2
21904 #define PWM5PHH3 PWM5PHHbits.PWM5PHH3 // bit 3
21905 #define PWM5PHH4 PWM5PHHbits.PWM5PHH4 // bit 4
21906 #define PWM5PHH5 PWM5PHHbits.PWM5PHH5 // bit 5
21907 #define PWM5PHH6 PWM5PHHbits.PWM5PHH6 // bit 6
21908 #define PWM5PHH7 PWM5PHHbits.PWM5PHH7 // bit 7
21910 #define PWM5PHL0 PWM5PHLbits.PWM5PHL0 // bit 0
21911 #define PWM5PHL1 PWM5PHLbits.PWM5PHL1 // bit 1
21912 #define PWM5PHL2 PWM5PHLbits.PWM5PHL2 // bit 2
21913 #define PWM5PHL3 PWM5PHLbits.PWM5PHL3 // bit 3
21914 #define PWM5PHL4 PWM5PHLbits.PWM5PHL4 // bit 4
21915 #define PWM5PHL5 PWM5PHLbits.PWM5PHL5 // bit 5
21916 #define PWM5PHL6 PWM5PHLbits.PWM5PHL6 // bit 6
21917 #define PWM5PHL7 PWM5PHLbits.PWM5PHL7 // bit 7
21919 #define PWM5PRH0 PWM5PRHbits.PWM5PRH0 // bit 0
21920 #define PWM5PRH1 PWM5PRHbits.PWM5PRH1 // bit 1
21921 #define PWM5PRH2 PWM5PRHbits.PWM5PRH2 // bit 2
21922 #define PWM5PRH3 PWM5PRHbits.PWM5PRH3 // bit 3
21923 #define PWM5PRH4 PWM5PRHbits.PWM5PRH4 // bit 4
21924 #define PWM5PRH5 PWM5PRHbits.PWM5PRH5 // bit 5
21925 #define PWM5PRH6 PWM5PRHbits.PWM5PRH6 // bit 6
21926 #define PWM5PRH7 PWM5PRHbits.PWM5PRH7 // bit 7
21928 #define PWM5PRL0 PWM5PRLbits.PWM5PRL0 // bit 0
21929 #define PWM5PRL1 PWM5PRLbits.PWM5PRL1 // bit 1
21930 #define PWM5PRL2 PWM5PRLbits.PWM5PRL2 // bit 2
21931 #define PWM5PRL3 PWM5PRLbits.PWM5PRL3 // bit 3
21932 #define PWM5PRL4 PWM5PRLbits.PWM5PRL4 // bit 4
21933 #define PWM5PRL5 PWM5PRLbits.PWM5PRL5 // bit 5
21934 #define PWM5PRL6 PWM5PRLbits.PWM5PRL6 // bit 6
21935 #define PWM5PRL7 PWM5PRLbits.PWM5PRL7 // bit 7
21937 #define PWM5TMRH0 PWM5TMRHbits.PWM5TMRH0 // bit 0
21938 #define PWM5TMRH1 PWM5TMRHbits.PWM5TMRH1 // bit 1
21939 #define PWM5TMRH2 PWM5TMRHbits.PWM5TMRH2 // bit 2
21940 #define PWM5TMRH3 PWM5TMRHbits.PWM5TMRH3 // bit 3
21941 #define PWM5TMRH4 PWM5TMRHbits.PWM5TMRH4 // bit 4
21942 #define PWM5TMRH5 PWM5TMRHbits.PWM5TMRH5 // bit 5
21943 #define PWM5TMRH6 PWM5TMRHbits.PWM5TMRH6 // bit 6
21944 #define PWM5TMRH7 PWM5TMRHbits.PWM5TMRH7 // bit 7
21946 #define PWM5TMRL0 PWM5TMRLbits.PWM5TMRL0 // bit 0
21947 #define PWM5TMRL1 PWM5TMRLbits.PWM5TMRL1 // bit 1
21948 #define PWM5TMRL2 PWM5TMRLbits.PWM5TMRL2 // bit 2
21949 #define PWM5TMRL3 PWM5TMRLbits.PWM5TMRL3 // bit 3
21950 #define PWM5TMRL4 PWM5TMRLbits.PWM5TMRL4 // bit 4
21951 #define PWM5TMRL5 PWM5TMRLbits.PWM5TMRL5 // bit 5
21952 #define PWM5TMRL6 PWM5TMRLbits.PWM5TMRL6 // bit 6
21953 #define PWM5TMRL7 PWM5TMRLbits.PWM5TMRL7 // bit 7
21955 #define PWM6DCH0 PWM6DCHbits.PWM6DCH0 // bit 0
21956 #define PWM6DCH1 PWM6DCHbits.PWM6DCH1 // bit 1
21957 #define PWM6DCH2 PWM6DCHbits.PWM6DCH2 // bit 2
21958 #define PWM6DCH3 PWM6DCHbits.PWM6DCH3 // bit 3
21959 #define PWM6DCH4 PWM6DCHbits.PWM6DCH4 // bit 4
21960 #define PWM6DCH5 PWM6DCHbits.PWM6DCH5 // bit 5
21961 #define PWM6DCH6 PWM6DCHbits.PWM6DCH6 // bit 6
21962 #define PWM6DCH7 PWM6DCHbits.PWM6DCH7 // bit 7
21964 #define PWM6DCL0 PWM6DCLbits.PWM6DCL0 // bit 0
21965 #define PWM6DCL1 PWM6DCLbits.PWM6DCL1 // bit 1
21966 #define PWM6DCL2 PWM6DCLbits.PWM6DCL2 // bit 2
21967 #define PWM6DCL3 PWM6DCLbits.PWM6DCL3 // bit 3
21968 #define PWM6DCL4 PWM6DCLbits.PWM6DCL4 // bit 4
21969 #define PWM6DCL5 PWM6DCLbits.PWM6DCL5 // bit 5
21970 #define PWM6DCL6 PWM6DCLbits.PWM6DCL6 // bit 6
21971 #define PWM6DCL7 PWM6DCLbits.PWM6DCL7 // bit 7
21973 #define PWM6OFH0 PWM6OFHbits.PWM6OFH0 // bit 0
21974 #define PWM6OFH1 PWM6OFHbits.PWM6OFH1 // bit 1
21975 #define PWM6OFH2 PWM6OFHbits.PWM6OFH2 // bit 2
21976 #define PWM6OFH3 PWM6OFHbits.PWM6OFH3 // bit 3
21977 #define PWM6OFH4 PWM6OFHbits.PWM6OFH4 // bit 4
21978 #define PWM6OFH5 PWM6OFHbits.PWM6OFH5 // bit 5
21979 #define PWM6OFH6 PWM6OFHbits.PWM6OFH6 // bit 6
21980 #define PWM6OFH7 PWM6OFHbits.PWM6OFH7 // bit 7
21982 #define PWM6OFL0 PWM6OFLbits.PWM6OFL0 // bit 0
21983 #define PWM6OFL1 PWM6OFLbits.PWM6OFL1 // bit 1
21984 #define PWM6OFL2 PWM6OFLbits.PWM6OFL2 // bit 2
21985 #define PWM6OFL3 PWM6OFLbits.PWM6OFL3 // bit 3
21986 #define PWM6OFL4 PWM6OFLbits.PWM6OFL4 // bit 4
21987 #define PWM6OFL5 PWM6OFLbits.PWM6OFL5 // bit 5
21988 #define PWM6OFL6 PWM6OFLbits.PWM6OFL6 // bit 6
21989 #define PWM6OFL7 PWM6OFLbits.PWM6OFL7 // bit 7
21991 #define PWM6PHH0 PWM6PHHbits.PWM6PHH0 // bit 0
21992 #define PWM6PHH1 PWM6PHHbits.PWM6PHH1 // bit 1
21993 #define PWM6PHH2 PWM6PHHbits.PWM6PHH2 // bit 2
21994 #define PWM6PHH3 PWM6PHHbits.PWM6PHH3 // bit 3
21995 #define PWM6PHH4 PWM6PHHbits.PWM6PHH4 // bit 4
21996 #define PWM6PHH5 PWM6PHHbits.PWM6PHH5 // bit 5
21997 #define PWM6PHH6 PWM6PHHbits.PWM6PHH6 // bit 6
21998 #define PWM6PHH7 PWM6PHHbits.PWM6PHH7 // bit 7
22000 #define PWM6PHL0 PWM6PHLbits.PWM6PHL0 // bit 0
22001 #define PWM6PHL1 PWM6PHLbits.PWM6PHL1 // bit 1
22002 #define PWM6PHL2 PWM6PHLbits.PWM6PHL2 // bit 2
22003 #define PWM6PHL3 PWM6PHLbits.PWM6PHL3 // bit 3
22004 #define PWM6PHL4 PWM6PHLbits.PWM6PHL4 // bit 4
22005 #define PWM6PHL5 PWM6PHLbits.PWM6PHL5 // bit 5
22006 #define PWM6PHL6 PWM6PHLbits.PWM6PHL6 // bit 6
22007 #define PWM6PHL7 PWM6PHLbits.PWM6PHL7 // bit 7
22009 #define PWM6PRH0 PWM6PRHbits.PWM6PRH0 // bit 0
22010 #define PWM6PRH1 PWM6PRHbits.PWM6PRH1 // bit 1
22011 #define PWM6PRH2 PWM6PRHbits.PWM6PRH2 // bit 2
22012 #define PWM6PRH3 PWM6PRHbits.PWM6PRH3 // bit 3
22013 #define PWM6PRH4 PWM6PRHbits.PWM6PRH4 // bit 4
22014 #define PWM6PRH5 PWM6PRHbits.PWM6PRH5 // bit 5
22015 #define PWM6PRH6 PWM6PRHbits.PWM6PRH6 // bit 6
22016 #define PWM6PRH7 PWM6PRHbits.PWM6PRH7 // bit 7
22018 #define PWM6PRL0 PWM6PRLbits.PWM6PRL0 // bit 0
22019 #define PWM6PRL1 PWM6PRLbits.PWM6PRL1 // bit 1
22020 #define PWM6PRL2 PWM6PRLbits.PWM6PRL2 // bit 2
22021 #define PWM6PRL3 PWM6PRLbits.PWM6PRL3 // bit 3
22022 #define PWM6PRL4 PWM6PRLbits.PWM6PRL4 // bit 4
22023 #define PWM6PRL5 PWM6PRLbits.PWM6PRL5 // bit 5
22024 #define PWM6PRL6 PWM6PRLbits.PWM6PRL6 // bit 6
22025 #define PWM6PRL7 PWM6PRLbits.PWM6PRL7 // bit 7
22027 #define PWM6TMRH0 PWM6TMRHbits.PWM6TMRH0 // bit 0
22028 #define PWM6TMRH1 PWM6TMRHbits.PWM6TMRH1 // bit 1
22029 #define PWM6TMRH2 PWM6TMRHbits.PWM6TMRH2 // bit 2
22030 #define PWM6TMRH3 PWM6TMRHbits.PWM6TMRH3 // bit 3
22031 #define PWM6TMRH4 PWM6TMRHbits.PWM6TMRH4 // bit 4
22032 #define PWM6TMRH5 PWM6TMRHbits.PWM6TMRH5 // bit 5
22033 #define PWM6TMRH6 PWM6TMRHbits.PWM6TMRH6 // bit 6
22034 #define PWM6TMRH7 PWM6TMRHbits.PWM6TMRH7 // bit 7
22036 #define PWM6TMRL0 PWM6TMRLbits.PWM6TMRL0 // bit 0
22037 #define PWM6TMRL1 PWM6TMRLbits.PWM6TMRL1 // bit 1
22038 #define PWM6TMRL2 PWM6TMRLbits.PWM6TMRL2 // bit 2
22039 #define PWM6TMRL3 PWM6TMRLbits.PWM6TMRL3 // bit 3
22040 #define PWM6TMRL4 PWM6TMRLbits.PWM6TMRL4 // bit 4
22041 #define PWM6TMRL5 PWM6TMRLbits.PWM6TMRL5 // bit 5
22042 #define PWM6TMRL6 PWM6TMRLbits.PWM6TMRL6 // bit 6
22043 #define PWM6TMRL7 PWM6TMRLbits.PWM6TMRL7 // bit 7
22045 #define PWM11DCH0 PWM11DCHbits.PWM11DCH0 // bit 0
22046 #define PWM11DCH1 PWM11DCHbits.PWM11DCH1 // bit 1
22047 #define PWM11DCH2 PWM11DCHbits.PWM11DCH2 // bit 2
22048 #define PWM11DCH3 PWM11DCHbits.PWM11DCH3 // bit 3
22049 #define PWM11DCH4 PWM11DCHbits.PWM11DCH4 // bit 4
22050 #define PWM11DCH5 PWM11DCHbits.PWM11DCH5 // bit 5
22051 #define PWM11DCH6 PWM11DCHbits.PWM11DCH6 // bit 6
22052 #define PWM11DCH7 PWM11DCHbits.PWM11DCH7 // bit 7
22054 #define PWM11DCL0 PWM11DCLbits.PWM11DCL0 // bit 0
22055 #define PWM11DCL1 PWM11DCLbits.PWM11DCL1 // bit 1
22056 #define PWM11DCL2 PWM11DCLbits.PWM11DCL2 // bit 2
22057 #define PWM11DCL3 PWM11DCLbits.PWM11DCL3 // bit 3
22058 #define PWM11DCL4 PWM11DCLbits.PWM11DCL4 // bit 4
22059 #define PWM11DCL5 PWM11DCLbits.PWM11DCL5 // bit 5
22060 #define PWM11DCL6 PWM11DCLbits.PWM11DCL6 // bit 6
22061 #define PWM11DCL7 PWM11DCLbits.PWM11DCL7 // bit 7
22063 #define PWM11OFH0 PWM11OFHbits.PWM11OFH0 // bit 0
22064 #define PWM11OFH1 PWM11OFHbits.PWM11OFH1 // bit 1
22065 #define PWM11OFH2 PWM11OFHbits.PWM11OFH2 // bit 2
22066 #define PWM11OFH3 PWM11OFHbits.PWM11OFH3 // bit 3
22067 #define PWM11OFH4 PWM11OFHbits.PWM11OFH4 // bit 4
22068 #define PWM11OFH5 PWM11OFHbits.PWM11OFH5 // bit 5
22069 #define PWM11OFH6 PWM11OFHbits.PWM11OFH6 // bit 6
22070 #define PWM11OFH7 PWM11OFHbits.PWM11OFH7 // bit 7
22072 #define PWM11OFL0 PWM11OFLbits.PWM11OFL0 // bit 0
22073 #define PWM11OFL1 PWM11OFLbits.PWM11OFL1 // bit 1
22074 #define PWM11OFL2 PWM11OFLbits.PWM11OFL2 // bit 2
22075 #define PWM11OFL3 PWM11OFLbits.PWM11OFL3 // bit 3
22076 #define PWM11OFL4 PWM11OFLbits.PWM11OFL4 // bit 4
22077 #define PWM11OFL5 PWM11OFLbits.PWM11OFL5 // bit 5
22078 #define PWM11OFL6 PWM11OFLbits.PWM11OFL6 // bit 6
22079 #define PWM11OFL7 PWM11OFLbits.PWM11OFL7 // bit 7
22081 #define PWM11PHH0 PWM11PHHbits.PWM11PHH0 // bit 0
22082 #define PWM11PHH1 PWM11PHHbits.PWM11PHH1 // bit 1
22083 #define PWM11PHH2 PWM11PHHbits.PWM11PHH2 // bit 2
22084 #define PWM11PHH3 PWM11PHHbits.PWM11PHH3 // bit 3
22085 #define PWM11PHH4 PWM11PHHbits.PWM11PHH4 // bit 4
22086 #define PWM11PHH5 PWM11PHHbits.PWM11PHH5 // bit 5
22087 #define PWM11PHH6 PWM11PHHbits.PWM11PHH6 // bit 6
22088 #define PWM11PHH7 PWM11PHHbits.PWM11PHH7 // bit 7
22090 #define PWM11PHL0 PWM11PHLbits.PWM11PHL0 // bit 0
22091 #define PWM11PHL1 PWM11PHLbits.PWM11PHL1 // bit 1
22092 #define PWM11PHL2 PWM11PHLbits.PWM11PHL2 // bit 2
22093 #define PWM11PHL3 PWM11PHLbits.PWM11PHL3 // bit 3
22094 #define PWM11PHL4 PWM11PHLbits.PWM11PHL4 // bit 4
22095 #define PWM11PHL5 PWM11PHLbits.PWM11PHL5 // bit 5
22096 #define PWM11PHL6 PWM11PHLbits.PWM11PHL6 // bit 6
22097 #define PWM11PHL7 PWM11PHLbits.PWM11PHL7 // bit 7
22099 #define PWM11PRH0 PWM11PRHbits.PWM11PRH0 // bit 0
22100 #define PWM11PRH1 PWM11PRHbits.PWM11PRH1 // bit 1
22101 #define PWM11PRH2 PWM11PRHbits.PWM11PRH2 // bit 2
22102 #define PWM11PRH3 PWM11PRHbits.PWM11PRH3 // bit 3
22103 #define PWM11PRH4 PWM11PRHbits.PWM11PRH4 // bit 4
22104 #define PWM11PRH5 PWM11PRHbits.PWM11PRH5 // bit 5
22105 #define PWM11PRH6 PWM11PRHbits.PWM11PRH6 // bit 6
22106 #define PWM11PRH7 PWM11PRHbits.PWM11PRH7 // bit 7
22108 #define PWM11PRL0 PWM11PRLbits.PWM11PRL0 // bit 0
22109 #define PWM11PRL1 PWM11PRLbits.PWM11PRL1 // bit 1
22110 #define PWM11PRL2 PWM11PRLbits.PWM11PRL2 // bit 2
22111 #define PWM11PRL3 PWM11PRLbits.PWM11PRL3 // bit 3
22112 #define PWM11PRL4 PWM11PRLbits.PWM11PRL4 // bit 4
22113 #define PWM11PRL5 PWM11PRLbits.PWM11PRL5 // bit 5
22114 #define PWM11PRL6 PWM11PRLbits.PWM11PRL6 // bit 6
22115 #define PWM11PRL7 PWM11PRLbits.PWM11PRL7 // bit 7
22117 #define PWM11TMRH0 PWM11TMRHbits.PWM11TMRH0 // bit 0
22118 #define PWM11TMRH1 PWM11TMRHbits.PWM11TMRH1 // bit 1
22119 #define PWM11TMRH2 PWM11TMRHbits.PWM11TMRH2 // bit 2
22120 #define PWM11TMRH3 PWM11TMRHbits.PWM11TMRH3 // bit 3
22121 #define PWM11TMRH4 PWM11TMRHbits.PWM11TMRH4 // bit 4
22122 #define PWM11TMRH5 PWM11TMRHbits.PWM11TMRH5 // bit 5
22123 #define PWM11TMRH6 PWM11TMRHbits.PWM11TMRH6 // bit 6
22124 #define PWM11TMRH7 PWM11TMRHbits.PWM11TMRH7 // bit 7
22126 #define PWM11TMRL0 PWM11TMRLbits.PWM11TMRL0 // bit 0
22127 #define PWM11TMRL1 PWM11TMRLbits.PWM11TMRL1 // bit 1
22128 #define PWM11TMRL2 PWM11TMRLbits.PWM11TMRL2 // bit 2
22129 #define PWM11TMRL3 PWM11TMRLbits.PWM11TMRL3 // bit 3
22130 #define PWM11TMRL4 PWM11TMRLbits.PWM11TMRL4 // bit 4
22131 #define PWM11TMRL5 PWM11TMRLbits.PWM11TMRL5 // bit 5
22132 #define PWM11TMRL6 PWM11TMRLbits.PWM11TMRL6 // bit 6
22133 #define PWM11TMRL7 PWM11TMRLbits.PWM11TMRL7 // bit 7
22135 #define MPWM5EN PWMENbits.MPWM5EN // bit 0
22136 #define MPWM6EN PWMENbits.MPWM6EN // bit 1
22137 #define MPWM11EN PWMENbits.MPWM11EN // bit 2
22139 #define MPWM5LD PWMLDbits.MPWM5LD // bit 0
22140 #define MPWM6LD PWMLDbits.MPWM6LD // bit 1
22141 #define MPWM11LD PWMLDbits.MPWM11LD // bit 2
22143 #define MPWM5OUT PWMOUTbits.MPWM5OUT // bit 0
22144 #define MPWM6OUT PWMOUTbits.MPWM6OUT // bit 1
22145 #define MPWM11OUT PWMOUTbits.MPWM11OUT // bit 2
22147 #define RX9D RC1STAbits.RX9D // bit 0
22148 #define OERR RC1STAbits.OERR // bit 1
22149 #define FERR RC1STAbits.FERR // bit 2
22150 #define ADDEN RC1STAbits.ADDEN // bit 3
22151 #define CREN RC1STAbits.CREN // bit 4
22152 #define SREN RC1STAbits.SREN // bit 5
22153 #define RX9 RC1STAbits.RX9 // bit 6
22154 #define SPEN RC1STAbits.SPEN // bit 7
22156 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
22157 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
22158 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
22159 #define SLRA3 SLRCONAbits.SLRA3 // bit 3
22160 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
22161 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
22162 #define SLRA6 SLRCONAbits.SLRA6 // bit 6
22163 #define SLRA7 SLRCONAbits.SLRA7 // bit 7
22165 #define SLRB0 SLRCONBbits.SLRB0 // bit 0
22166 #define SLRB1 SLRCONBbits.SLRB1 // bit 1
22167 #define SLRB2 SLRCONBbits.SLRB2 // bit 2
22168 #define SLRB3 SLRCONBbits.SLRB3 // bit 3
22169 #define SLRB4 SLRCONBbits.SLRB4 // bit 4
22170 #define SLRB5 SLRCONBbits.SLRB5 // bit 5
22171 #define SLRB6 SLRCONBbits.SLRB6 // bit 6
22172 #define SLRB7 SLRCONBbits.SLRB7 // bit 7
22174 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
22175 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
22176 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
22177 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
22178 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
22179 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
22180 #define SLRC6 SLRCONCbits.SLRC6 // bit 6
22181 #define SLRC7 SLRCONCbits.SLRC7 // bit 7
22183 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
22184 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
22185 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
22186 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
22187 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
22188 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
22189 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
22190 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
22191 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
22192 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
22193 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
22194 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
22195 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
22196 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
22197 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
22198 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
22200 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
22201 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
22202 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
22203 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
22204 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
22205 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
22206 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
22207 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
22208 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
22209 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
22210 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
22211 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
22212 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
22213 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
22214 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
22215 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
22217 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
22218 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
22219 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
22220 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
22221 #define CKP SSP1CONbits.CKP // bit 4
22222 #define SSPEN SSP1CONbits.SSPEN // bit 5
22223 #define SSPOV SSP1CONbits.SSPOV // bit 6
22224 #define WCOL SSP1CONbits.WCOL // bit 7
22226 #define SEN SSP1CON2bits.SEN // bit 0
22227 #define RSEN SSP1CON2bits.RSEN // bit 1
22228 #define PEN SSP1CON2bits.PEN // bit 2
22229 #define RCEN SSP1CON2bits.RCEN // bit 3
22230 #define ACKEN SSP1CON2bits.ACKEN // bit 4
22231 #define ACKDT SSP1CON2bits.ACKDT // bit 5
22232 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
22233 #define GCEN SSP1CON2bits.GCEN // bit 7
22235 #define DHEN SSP1CON3bits.DHEN // bit 0
22236 #define AHEN SSP1CON3bits.AHEN // bit 1
22237 #define SBCDE SSP1CON3bits.SBCDE // bit 2
22238 #define SDAHT SSP1CON3bits.SDAHT // bit 3
22239 #define BOEN SSP1CON3bits.BOEN // bit 4
22240 #define SCIE SSP1CON3bits.SCIE // bit 5
22241 #define PCIE SSP1CON3bits.PCIE // bit 6
22242 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
22244 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
22245 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
22246 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
22247 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
22248 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
22249 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
22250 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
22251 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
22252 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
22253 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
22254 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
22255 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
22256 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
22257 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
22258 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
22259 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
22261 #define BF SSP1STATbits.BF // bit 0
22262 #define UA SSP1STATbits.UA // bit 1
22263 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
22264 #define S SSP1STATbits.S // bit 3
22265 #define P SSP1STATbits.P // bit 4
22266 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
22267 #define CKE SSP1STATbits.CKE // bit 6
22268 #define SMP SSP1STATbits.SMP // bit 7
22270 #define C STATUSbits.C // bit 0
22271 #define DC STATUSbits.DC // bit 1
22272 #define Z STATUSbits.Z // bit 2
22273 #define NOT_PD STATUSbits.NOT_PD // bit 3
22274 #define NOT_TO STATUSbits.NOT_TO // bit 4
22276 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
22277 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
22278 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
22280 #define GSS0 T1GCONbits.GSS0 // bit 0, shadows bit in T1GCONbits
22281 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0, shadows bit in T1GCONbits
22282 #define GSS1 T1GCONbits.GSS1 // bit 1, shadows bit in T1GCONbits
22283 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1, shadows bit in T1GCONbits
22284 #define GVAL T1GCONbits.GVAL // bit 2, shadows bit in T1GCONbits
22285 #define T1GVAL T1GCONbits.T1GVAL // bit 2, shadows bit in T1GCONbits
22286 #define GGO_NOT_DONE T1GCONbits.GGO_NOT_DONE // bit 3, shadows bit in T1GCONbits
22287 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3, shadows bit in T1GCONbits
22288 #define GSPM T1GCONbits.GSPM // bit 4, shadows bit in T1GCONbits
22289 #define T1GSPM T1GCONbits.T1GSPM // bit 4, shadows bit in T1GCONbits
22290 #define GTM T1GCONbits.GTM // bit 5, shadows bit in T1GCONbits
22291 #define T1GTM T1GCONbits.T1GTM // bit 5, shadows bit in T1GCONbits
22292 #define GPOL T1GCONbits.GPOL // bit 6, shadows bit in T1GCONbits
22293 #define T1GPOL T1GCONbits.T1GPOL // bit 6, shadows bit in T1GCONbits
22294 #define GE T1GCONbits.GE // bit 7, shadows bit in T1GCONbits
22295 #define T1GE T1GCONbits.T1GE // bit 7, shadows bit in T1GCONbits
22296 #define TMR1GE T1GCONbits.TMR1GE // bit 7, shadows bit in T1GCONbits
22298 #define RSEL0 T2RSTbits.RSEL0 // bit 0, shadows bit in T2RSTbits
22299 #define T2RSEL0 T2RSTbits.T2RSEL0 // bit 0, shadows bit in T2RSTbits
22300 #define RSEL1 T2RSTbits.RSEL1 // bit 1, shadows bit in T2RSTbits
22301 #define T2RSEL1 T2RSTbits.T2RSEL1 // bit 1, shadows bit in T2RSTbits
22302 #define RSEL2 T2RSTbits.RSEL2 // bit 2, shadows bit in T2RSTbits
22303 #define T2RSEL2 T2RSTbits.T2RSEL2 // bit 2, shadows bit in T2RSTbits
22304 #define RSEL3 T2RSTbits.RSEL3 // bit 3, shadows bit in T2RSTbits
22305 #define T2RSEL3 T2RSTbits.T2RSEL3 // bit 3, shadows bit in T2RSTbits
22306 #define RSEL4 T2RSTbits.RSEL4 // bit 4, shadows bit in T2RSTbits
22307 #define T2RSEL4 T2RSTbits.T2RSEL4 // bit 4, shadows bit in T2RSTbits
22309 #define TRISA0 TRISAbits.TRISA0 // bit 0
22310 #define TRISA1 TRISAbits.TRISA1 // bit 1
22311 #define TRISA2 TRISAbits.TRISA2 // bit 2
22312 #define TRISA3 TRISAbits.TRISA3 // bit 3
22313 #define TRISA4 TRISAbits.TRISA4 // bit 4
22314 #define TRISA5 TRISAbits.TRISA5 // bit 5
22315 #define TRISA6 TRISAbits.TRISA6 // bit 6
22316 #define TRISA7 TRISAbits.TRISA7 // bit 7
22318 #define TRISB0 TRISBbits.TRISB0 // bit 0
22319 #define TRISB1 TRISBbits.TRISB1 // bit 1
22320 #define TRISB2 TRISBbits.TRISB2 // bit 2
22321 #define TRISB3 TRISBbits.TRISB3 // bit 3
22322 #define TRISB4 TRISBbits.TRISB4 // bit 4
22323 #define TRISB5 TRISBbits.TRISB5 // bit 5
22324 #define TRISB6 TRISBbits.TRISB6 // bit 6
22325 #define TRISB7 TRISBbits.TRISB7 // bit 7
22327 #define TRISC0 TRISCbits.TRISC0 // bit 0
22328 #define TRISC1 TRISCbits.TRISC1 // bit 1
22329 #define TRISC2 TRISCbits.TRISC2 // bit 2
22330 #define TRISC3 TRISCbits.TRISC3 // bit 3
22331 #define TRISC4 TRISCbits.TRISC4 // bit 4
22332 #define TRISC5 TRISCbits.TRISC5 // bit 5
22333 #define TRISC6 TRISCbits.TRISC6 // bit 6
22334 #define TRISC7 TRISCbits.TRISC7 // bit 7
22336 #define TRISE3 TRISEbits.TRISE3 // bit 3
22338 #define SWDTEN WDTCONbits.SWDTEN // bit 0
22339 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
22340 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
22341 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
22342 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
22343 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
22345 #define WPUA0 WPUAbits.WPUA0 // bit 0
22346 #define WPUA1 WPUAbits.WPUA1 // bit 1
22347 #define WPUA2 WPUAbits.WPUA2 // bit 2
22348 #define WPUA3 WPUAbits.WPUA3 // bit 3
22349 #define WPUA4 WPUAbits.WPUA4 // bit 4
22350 #define WPUA5 WPUAbits.WPUA5 // bit 5
22351 #define WPUA6 WPUAbits.WPUA6 // bit 6
22352 #define WPUA7 WPUAbits.WPUA7 // bit 7
22354 #define WPUB0 WPUBbits.WPUB0 // bit 0
22355 #define WPUB1 WPUBbits.WPUB1 // bit 1
22356 #define WPUB2 WPUBbits.WPUB2 // bit 2
22357 #define WPUB3 WPUBbits.WPUB3 // bit 3
22358 #define WPUB4 WPUBbits.WPUB4 // bit 4
22359 #define WPUB5 WPUBbits.WPUB5 // bit 5
22360 #define WPUB6 WPUBbits.WPUB6 // bit 6
22361 #define WPUB7 WPUBbits.WPUB7 // bit 7
22363 #define WPUC0 WPUCbits.WPUC0 // bit 0
22364 #define WPUC1 WPUCbits.WPUC1 // bit 1
22365 #define WPUC2 WPUCbits.WPUC2 // bit 2
22366 #define WPUC3 WPUCbits.WPUC3 // bit 3
22367 #define WPUC4 WPUCbits.WPUC4 // bit 4
22368 #define WPUC5 WPUCbits.WPUC5 // bit 5
22369 #define WPUC6 WPUCbits.WPUC6 // bit 6
22370 #define WPUC7 WPUCbits.WPUC7 // bit 7
22372 #define WPUE3 WPUEbits.WPUE3 // bit 3
22374 #define ZCD1INTN ZCD1CONbits.ZCD1INTN // bit 0
22375 #define ZCD1INTP ZCD1CONbits.ZCD1INTP // bit 1
22376 #define ZCD1POL ZCD1CONbits.ZCD1POL // bit 4
22377 #define ZCD1OUT ZCD1CONbits.ZCD1OUT // bit 5
22378 #define ZCD1EN ZCD1CONbits.ZCD1EN // bit 7
22380 #endif // #ifndef NO_BIT_DEFINES
22382 #endif // #ifndef __PIC16F1778_H__