2 * This declarations of the PIC16F18313 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:23 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F18313_H__
26 #define __PIC16F18313_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PIR0_ADDR 0x0010
52 #define PIR1_ADDR 0x0011
53 #define PIR2_ADDR 0x0012
54 #define PIR3_ADDR 0x0013
55 #define PIR4_ADDR 0x0014
56 #define TMR0L_ADDR 0x0015
57 #define TMR0H_ADDR 0x0016
58 #define T0CON0_ADDR 0x0017
59 #define T0CON1_ADDR 0x0018
60 #define TMR1_ADDR 0x0019
61 #define TMR1L_ADDR 0x0019
62 #define TMR1H_ADDR 0x001A
63 #define T1CON_ADDR 0x001B
64 #define T1GCON_ADDR 0x001C
65 #define TMR2_ADDR 0x001D
66 #define PR2_ADDR 0x001E
67 #define T2CON_ADDR 0x001F
68 #define TRISA_ADDR 0x008C
69 #define PIE0_ADDR 0x0090
70 #define PIE1_ADDR 0x0091
71 #define PIE2_ADDR 0x0092
72 #define PIE3_ADDR 0x0093
73 #define PIE4_ADDR 0x0094
74 #define WDTCON_ADDR 0x0097
75 #define ADRES_ADDR 0x009B
76 #define ADRESL_ADDR 0x009B
77 #define ADRESH_ADDR 0x009C
78 #define ADCON0_ADDR 0x009D
79 #define ADCON1_ADDR 0x009E
80 #define ADACT_ADDR 0x009F
81 #define LATA_ADDR 0x010C
82 #define CM1CON0_ADDR 0x0111
83 #define CM1CON1_ADDR 0x0112
84 #define CMOUT_ADDR 0x0115
85 #define BORCON_ADDR 0x0116
86 #define FVRCON_ADDR 0x0117
87 #define DACCON0_ADDR 0x0118
88 #define DACCON1_ADDR 0x0119
89 #define ANSELA_ADDR 0x018C
90 #define VREGCON_ADDR 0x0197
91 #define RC1REG_ADDR 0x0199
92 #define RCREG_ADDR 0x0199
93 #define RCREG1_ADDR 0x0199
94 #define TX1REG_ADDR 0x019A
95 #define TXREG_ADDR 0x019A
96 #define TXREG1_ADDR 0x019A
97 #define SP1BRG_ADDR 0x019B
98 #define SP1BRGL_ADDR 0x019B
99 #define SPBRG_ADDR 0x019B
100 #define SPBRG1_ADDR 0x019B
101 #define SPBRGL_ADDR 0x019B
102 #define SP1BRGH_ADDR 0x019C
103 #define SPBRGH_ADDR 0x019C
104 #define SPBRGH1_ADDR 0x019C
105 #define RC1STA_ADDR 0x019D
106 #define RCSTA_ADDR 0x019D
107 #define RCSTA1_ADDR 0x019D
108 #define TX1STA_ADDR 0x019E
109 #define TXSTA_ADDR 0x019E
110 #define TXSTA1_ADDR 0x019E
111 #define BAUD1CON_ADDR 0x019F
112 #define BAUDCON_ADDR 0x019F
113 #define BAUDCON1_ADDR 0x019F
114 #define BAUDCTL_ADDR 0x019F
115 #define BAUDCTL1_ADDR 0x019F
116 #define WPUA_ADDR 0x020C
117 #define SSP1BUF_ADDR 0x0211
118 #define SSPBUF_ADDR 0x0211
119 #define SSP1ADD_ADDR 0x0212
120 #define SSPADD_ADDR 0x0212
121 #define SSP1MSK_ADDR 0x0213
122 #define SSPMSK_ADDR 0x0213
123 #define SSP1STAT_ADDR 0x0214
124 #define SSPSTAT_ADDR 0x0214
125 #define SSP1CON_ADDR 0x0215
126 #define SSP1CON1_ADDR 0x0215
127 #define SSPCON_ADDR 0x0215
128 #define SSPCON1_ADDR 0x0215
129 #define SSP1CON2_ADDR 0x0216
130 #define SSPCON2_ADDR 0x0216
131 #define SSP1CON3_ADDR 0x0217
132 #define SSPCON3_ADDR 0x0217
133 #define ODCONA_ADDR 0x028C
134 #define CCPR1_ADDR 0x0291
135 #define CCPR1L_ADDR 0x0291
136 #define CCPR1H_ADDR 0x0292
137 #define CCP1CON_ADDR 0x0293
138 #define CCP1CAP_ADDR 0x0294
139 #define CCPR2_ADDR 0x0295
140 #define CCPR2L_ADDR 0x0295
141 #define CCPR2H_ADDR 0x0296
142 #define CCP2CON_ADDR 0x0297
143 #define CCP2CAP_ADDR 0x0298
144 #define CCPTMRS_ADDR 0x029F
145 #define SLRCONA_ADDR 0x030C
146 #define INLVLA_ADDR 0x038C
147 #define IOCAP_ADDR 0x0391
148 #define IOCAN_ADDR 0x0392
149 #define IOCAF_ADDR 0x0393
150 #define CLKRCON_ADDR 0x039A
151 #define MDCON_ADDR 0x039C
152 #define MDSRC_ADDR 0x039D
153 #define MDCARH_ADDR 0x039E
154 #define MDCARL_ADDR 0x039F
155 #define CCDNA_ADDR 0x040C
156 #define CCDCON_ADDR 0x041F
157 #define CCDPA_ADDR 0x048C
158 #define NCO1ACC_ADDR 0x0498
159 #define NCO1ACCL_ADDR 0x0498
160 #define NCO1ACCH_ADDR 0x0499
161 #define NCO1ACCU_ADDR 0x049A
162 #define NCO1INC_ADDR 0x049B
163 #define NCO1INCL_ADDR 0x049B
164 #define NCO1INCH_ADDR 0x049C
165 #define NCO1INCU_ADDR 0x049D
166 #define NCO1CON_ADDR 0x049E
167 #define NCO1CLK_ADDR 0x049F
168 #define PWM5DCL_ADDR 0x0617
169 #define PWM5DCH_ADDR 0x0618
170 #define PWM5CON_ADDR 0x0619
171 #define PWM5CON0_ADDR 0x0619
172 #define PWM6DCL_ADDR 0x061A
173 #define PWM6DCH_ADDR 0x061B
174 #define PWM6CON_ADDR 0x061C
175 #define PWM6CON0_ADDR 0x061C
176 #define CWG1CLKCON_ADDR 0x0691
177 #define CWG1DAT_ADDR 0x0692
178 #define CWG1DBR_ADDR 0x0693
179 #define CWG1DBF_ADDR 0x0694
180 #define CWG1CON0_ADDR 0x0695
181 #define CWG1CON1_ADDR 0x0696
182 #define CWG1AS0_ADDR 0x0697
183 #define CWG1AS1_ADDR 0x0698
184 #define CWG1STR_ADDR 0x0699
185 #define NVMADR_ADDR 0x0891
186 #define NVMADRL_ADDR 0x0891
187 #define NVMADRH_ADDR 0x0892
188 #define NVMDAT_ADDR 0x0893
189 #define NVMDATL_ADDR 0x0893
190 #define NVMDATH_ADDR 0x0894
191 #define NVMCON1_ADDR 0x0895
192 #define NVMCON2_ADDR 0x0896
193 #define PCON0_ADDR 0x089B
194 #define PMD0_ADDR 0x0911
195 #define PMD1_ADDR 0x0912
196 #define PMD2_ADDR 0x0913
197 #define PMD3_ADDR 0x0914
198 #define PMD4_ADDR 0x0915
199 #define PMD5_ADDR 0x0916
200 #define CPUDOZE_ADDR 0x0918
201 #define OSCCON1_ADDR 0x0919
202 #define OSCCON2_ADDR 0x091A
203 #define OSCCON3_ADDR 0x091B
204 #define OSCSTAT1_ADDR 0x091C
205 #define OSCEN_ADDR 0x091D
206 #define OSCTUNE_ADDR 0x091E
207 #define OSCFRQ_ADDR 0x091F
208 #define PPSLOCK_ADDR 0x0E0F
209 #define INTPPS_ADDR 0x0E10
210 #define T0CKIPPS_ADDR 0x0E11
211 #define T1CKIPPS_ADDR 0x0E12
212 #define T1GPPS_ADDR 0x0E13
213 #define CCP1PPS_ADDR 0x0E14
214 #define CCP2PPS_ADDR 0x0E15
215 #define CWG1PPS_ADDR 0x0E18
216 #define MDCIN1PPS_ADDR 0x0E1A
217 #define MDCIN2PPS_ADDR 0x0E1B
218 #define MDMINPPS_ADDR 0x0E1C
219 #define SSP1CLKPPS_ADDR 0x0E20
220 #define SSP1DATPPS_ADDR 0x0E21
221 #define SSP1SSPPS_ADDR 0x0E22
222 #define RXPPS_ADDR 0x0E24
223 #define TXPPS_ADDR 0x0E25
224 #define CLCIN0PPS_ADDR 0x0E28
225 #define CLCIN1PPS_ADDR 0x0E29
226 #define CLCIN2PPS_ADDR 0x0E2A
227 #define CLCIN3PPS_ADDR 0x0E2B
228 #define RA0PPS_ADDR 0x0E90
229 #define RA1PPS_ADDR 0x0E91
230 #define RA2PPS_ADDR 0x0E92
231 #define RA4PPS_ADDR 0x0E94
232 #define RA5PPS_ADDR 0x0E95
233 #define CLCDATA_ADDR 0x0F0F
234 #define CLC1CON_ADDR 0x0F10
235 #define CLC1POL_ADDR 0x0F11
236 #define CLC1SEL0_ADDR 0x0F12
237 #define CLC1SEL1_ADDR 0x0F13
238 #define CLC1SEL2_ADDR 0x0F14
239 #define CLC1SEL3_ADDR 0x0F15
240 #define CLC1GLS0_ADDR 0x0F16
241 #define CLC1GLS1_ADDR 0x0F17
242 #define CLC1GLS2_ADDR 0x0F18
243 #define CLC1GLS3_ADDR 0x0F19
244 #define CLC2CON_ADDR 0x0F1A
245 #define CLC2POL_ADDR 0x0F1B
246 #define CLC2SEL0_ADDR 0x0F1C
247 #define CLC2SEL1_ADDR 0x0F1D
248 #define CLC2SEL2_ADDR 0x0F1E
249 #define CLC2SEL3_ADDR 0x0F1F
250 #define CLC2GLS0_ADDR 0x0F20
251 #define CLC2GLS1_ADDR 0x0F21
252 #define CLC2GLS2_ADDR 0x0F22
253 #define CLC2GLS3_ADDR 0x0F23
254 #define STATUS_SHAD_ADDR 0x0FE4
255 #define WREG_SHAD_ADDR 0x0FE5
256 #define BSR_SHAD_ADDR 0x0FE6
257 #define PCLATH_SHAD_ADDR 0x0FE7
258 #define FSR0L_SHAD_ADDR 0x0FE8
259 #define FSR0H_SHAD_ADDR 0x0FE9
260 #define FSR1L_SHAD_ADDR 0x0FEA
261 #define FSR1H_SHAD_ADDR 0x0FEB
262 #define STKPTR_ADDR 0x0FED
263 #define TOSL_ADDR 0x0FEE
264 #define TOSH_ADDR 0x0FEF
266 #endif // #ifndef NO_ADDR_DEFINES
268 //==============================================================================
270 // Register Definitions
272 //==============================================================================
274 extern __at(0x0000) __sfr INDF0
;
275 extern __at(0x0001) __sfr INDF1
;
276 extern __at(0x0002) __sfr PCL
;
278 //==============================================================================
281 extern __at(0x0003) __sfr STATUS
;
295 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
303 //==============================================================================
305 extern __at(0x0004) __sfr FSR0
;
306 extern __at(0x0004) __sfr FSR0L
;
307 extern __at(0x0005) __sfr FSR0H
;
308 extern __at(0x0006) __sfr FSR1
;
309 extern __at(0x0006) __sfr FSR1L
;
310 extern __at(0x0007) __sfr FSR1H
;
312 //==============================================================================
315 extern __at(0x0008) __sfr BSR
;
338 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
346 //==============================================================================
348 extern __at(0x0009) __sfr WREG
;
349 extern __at(0x000A) __sfr PCLATH
;
351 //==============================================================================
354 extern __at(0x000B) __sfr INTCON
;
368 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
374 //==============================================================================
377 //==============================================================================
380 extern __at(0x000C) __sfr PORTA
;
403 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
412 //==============================================================================
415 //==============================================================================
418 extern __at(0x0010) __sfr PIR0
;
432 extern __at(0x0010) volatile __PIR0bits_t PIR0bits
;
438 //==============================================================================
441 //==============================================================================
444 extern __at(0x0011) __sfr PIR1
;
455 unsigned TMR1GIF
: 1;
458 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
467 #define _TMR1GIF 0x80
469 //==============================================================================
472 //==============================================================================
475 extern __at(0x0012) __sfr PIR2
;
489 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
495 //==============================================================================
498 //==============================================================================
501 extern __at(0x0013) __sfr PIR3
;
515 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
522 //==============================================================================
525 //==============================================================================
528 extern __at(0x0014) __sfr PIR4
;
542 extern __at(0x0014) volatile __PIR4bits_t PIR4bits
;
548 //==============================================================================
551 //==============================================================================
554 extern __at(0x0015) __sfr TMR0L
;
568 extern __at(0x0015) volatile __TMR0Lbits_t TMR0Lbits
;
579 //==============================================================================
582 //==============================================================================
585 extern __at(0x0016) __sfr TMR0H
;
599 extern __at(0x0016) volatile __TMR0Hbits_t TMR0Hbits
;
610 //==============================================================================
613 //==============================================================================
616 extern __at(0x0017) __sfr T0CON0
;
622 unsigned T0OUTPS0
: 1;
623 unsigned T0OUTPS1
: 1;
624 unsigned T0OUTPS2
: 1;
625 unsigned T0OUTPS3
: 1;
626 unsigned T016BIT
: 1;
634 unsigned T0OUTPS
: 4;
639 extern __at(0x0017) volatile __T0CON0bits_t T0CON0bits
;
641 #define _T0OUTPS0 0x01
642 #define _T0OUTPS1 0x02
643 #define _T0OUTPS2 0x04
644 #define _T0OUTPS3 0x08
645 #define _T016BIT 0x10
649 //==============================================================================
652 //==============================================================================
655 extern __at(0x0018) __sfr T0CON1
;
661 unsigned T0CKPS0
: 1;
662 unsigned T0CKPS1
: 1;
663 unsigned T0CKPS2
: 1;
664 unsigned T0CKPS3
: 1;
665 unsigned T0ASYNC
: 1;
684 extern __at(0x0018) volatile __T0CON1bits_t T0CON1bits
;
686 #define _T0CKPS0 0x01
687 #define _T0CKPS1 0x02
688 #define _T0CKPS2 0x04
689 #define _T0CKPS3 0x08
690 #define _T0ASYNC 0x10
695 //==============================================================================
697 extern __at(0x0019) __sfr TMR1
;
698 extern __at(0x0019) __sfr TMR1L
;
699 extern __at(0x001A) __sfr TMR1H
;
701 //==============================================================================
704 extern __at(0x001B) __sfr T1CON
;
714 unsigned T1CKPS0
: 1;
715 unsigned T1CKPS1
: 1;
716 unsigned TMR1CS0
: 1;
717 unsigned TMR1CS1
: 1;
734 extern __at(0x001B) volatile __T1CONbits_t T1CONbits
;
739 #define _T1CKPS0 0x10
740 #define _T1CKPS1 0x20
741 #define _TMR1CS0 0x40
742 #define _TMR1CS1 0x80
744 //==============================================================================
747 //==============================================================================
750 extern __at(0x001C) __sfr T1GCON
;
759 unsigned T1GGO_NOT_DONE
: 1;
773 extern __at(0x001C) volatile __T1GCONbits_t T1GCONbits
;
778 #define _T1GGO_NOT_DONE 0x08
784 //==============================================================================
786 extern __at(0x001D) __sfr TMR2
;
787 extern __at(0x001E) __sfr PR2
;
789 //==============================================================================
792 extern __at(0x001F) __sfr T2CON
;
798 unsigned T2CKPS0
: 1;
799 unsigned T2CKPS1
: 1;
801 unsigned T2OUTPS0
: 1;
802 unsigned T2OUTPS1
: 1;
803 unsigned T2OUTPS2
: 1;
804 unsigned T2OUTPS3
: 1;
817 unsigned T2OUTPS
: 4;
822 extern __at(0x001F) volatile __T2CONbits_t T2CONbits
;
824 #define _T2CKPS0 0x01
825 #define _T2CKPS1 0x02
827 #define _T2OUTPS0 0x08
828 #define _T2OUTPS1 0x10
829 #define _T2OUTPS2 0x20
830 #define _T2OUTPS3 0x40
832 //==============================================================================
835 //==============================================================================
838 extern __at(0x008C) __sfr TRISA
;
852 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
860 //==============================================================================
863 //==============================================================================
866 extern __at(0x0090) __sfr PIE0
;
880 extern __at(0x0090) volatile __PIE0bits_t PIE0bits
;
886 //==============================================================================
889 //==============================================================================
892 extern __at(0x0091) __sfr PIE1
;
903 unsigned TMR1GIE
: 1;
906 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
915 #define _TMR1GIE 0x80
917 //==============================================================================
920 //==============================================================================
923 extern __at(0x0092) __sfr PIE2
;
937 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
943 //==============================================================================
946 //==============================================================================
949 extern __at(0x0093) __sfr PIE3
;
963 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
970 //==============================================================================
973 //==============================================================================
976 extern __at(0x0094) __sfr PIE4
;
990 extern __at(0x0094) volatile __PIE4bits_t PIE4bits
;
996 //==============================================================================
999 //==============================================================================
1002 extern __at(0x0097) __sfr WDTCON
;
1008 unsigned SWDTEN
: 1;
1009 unsigned WDTPS0
: 1;
1010 unsigned WDTPS1
: 1;
1011 unsigned WDTPS2
: 1;
1012 unsigned WDTPS3
: 1;
1013 unsigned WDTPS4
: 1;
1026 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1028 #define _SWDTEN 0x01
1029 #define _WDTPS0 0x02
1030 #define _WDTPS1 0x04
1031 #define _WDTPS2 0x08
1032 #define _WDTPS3 0x10
1033 #define _WDTPS4 0x20
1035 //==============================================================================
1037 extern __at(0x009B) __sfr ADRES
;
1038 extern __at(0x009B) __sfr ADRESL
;
1039 extern __at(0x009C) __sfr ADRESH
;
1041 //==============================================================================
1044 extern __at(0x009D) __sfr ADCON0
;
1051 unsigned GO_NOT_DONE
: 1;
1091 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1094 #define _GO_NOT_DONE 0x02
1104 //==============================================================================
1107 //==============================================================================
1110 extern __at(0x009E) __sfr ADCON1
;
1116 unsigned ADPREF0
: 1;
1117 unsigned ADPREF1
: 1;
1118 unsigned ADNREF
: 1;
1128 unsigned ADPREF
: 2;
1140 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1142 #define _ADPREF0 0x01
1143 #define _ADPREF1 0x02
1144 #define _ADNREF 0x04
1150 //==============================================================================
1153 //==============================================================================
1156 extern __at(0x009F) __sfr ADACT
;
1162 unsigned ADACT0
: 1;
1163 unsigned ADACT1
: 1;
1164 unsigned ADACT2
: 1;
1165 unsigned ADACT3
: 1;
1179 extern __at(0x009F) volatile __ADACTbits_t ADACTbits
;
1181 #define _ADACT0 0x01
1182 #define _ADACT1 0x02
1183 #define _ADACT2 0x04
1184 #define _ADACT3 0x08
1186 //==============================================================================
1189 //==============================================================================
1192 extern __at(0x010C) __sfr LATA
;
1206 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1214 //==============================================================================
1217 //==============================================================================
1220 extern __at(0x0111) __sfr CM1CON0
;
1224 unsigned C1SYNC
: 1;
1234 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1236 #define _C1SYNC 0x01
1243 //==============================================================================
1246 //==============================================================================
1249 extern __at(0x0112) __sfr CM1CON1
;
1255 unsigned C1NCH0
: 1;
1256 unsigned C1NCH1
: 1;
1257 unsigned C1NCH2
: 1;
1258 unsigned C1PCH0
: 1;
1259 unsigned C1PCH1
: 1;
1260 unsigned C1PCH2
: 1;
1261 unsigned C1INTN
: 1;
1262 unsigned C1INTP
: 1;
1279 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1281 #define _C1NCH0 0x01
1282 #define _C1NCH1 0x02
1283 #define _C1NCH2 0x04
1284 #define _C1PCH0 0x08
1285 #define _C1PCH1 0x10
1286 #define _C1PCH2 0x20
1287 #define _C1INTN 0x40
1288 #define _C1INTP 0x80
1290 //==============================================================================
1293 //==============================================================================
1296 extern __at(0x0115) __sfr CMOUT
;
1300 unsigned MC1OUT
: 1;
1310 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1312 #define _MC1OUT 0x01
1314 //==============================================================================
1317 //==============================================================================
1320 extern __at(0x0116) __sfr BORCON
;
1324 unsigned BORRDY
: 1;
1331 unsigned SBOREN
: 1;
1334 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1336 #define _BORRDY 0x01
1337 #define _SBOREN 0x80
1339 //==============================================================================
1342 //==============================================================================
1345 extern __at(0x0117) __sfr FVRCON
;
1351 unsigned ADFVR0
: 1;
1352 unsigned ADFVR1
: 1;
1353 unsigned CDAFVR0
: 1;
1354 unsigned CDAFVR1
: 1;
1357 unsigned FVRRDY
: 1;
1370 unsigned CDAFVR
: 2;
1375 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1377 #define _ADFVR0 0x01
1378 #define _ADFVR1 0x02
1379 #define _CDAFVR0 0x04
1380 #define _CDAFVR1 0x08
1383 #define _FVRRDY 0x40
1386 //==============================================================================
1389 //==============================================================================
1392 extern __at(0x0118) __sfr DACCON0
;
1398 unsigned DAC1NSS
: 1;
1400 unsigned DAC1PSS0
: 1;
1401 unsigned DAC1PSS1
: 1;
1403 unsigned DAC1OE
: 1;
1405 unsigned DAC1EN
: 1;
1411 unsigned DAC1PSS
: 2;
1416 extern __at(0x0118) volatile __DACCON0bits_t DACCON0bits
;
1418 #define _DAC1NSS 0x01
1419 #define _DAC1PSS0 0x04
1420 #define _DAC1PSS1 0x08
1421 #define _DAC1OE 0x20
1422 #define _DAC1EN 0x80
1424 //==============================================================================
1427 //==============================================================================
1430 extern __at(0x0119) __sfr DACCON1
;
1436 unsigned DAC1R0
: 1;
1437 unsigned DAC1R1
: 1;
1438 unsigned DAC1R2
: 1;
1439 unsigned DAC1R3
: 1;
1440 unsigned DAC1R4
: 1;
1453 extern __at(0x0119) volatile __DACCON1bits_t DACCON1bits
;
1455 #define _DAC1R0 0x01
1456 #define _DAC1R1 0x02
1457 #define _DAC1R2 0x04
1458 #define _DAC1R3 0x08
1459 #define _DAC1R4 0x10
1461 //==============================================================================
1464 //==============================================================================
1467 extern __at(0x018C) __sfr ANSELA
;
1481 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1489 //==============================================================================
1492 //==============================================================================
1495 extern __at(0x0197) __sfr VREGCON
;
1500 unsigned VREGPM
: 1;
1509 extern __at(0x0197) volatile __VREGCONbits_t VREGCONbits
;
1511 #define _VREGPM 0x02
1513 //==============================================================================
1515 extern __at(0x0199) __sfr RC1REG
;
1516 extern __at(0x0199) __sfr RCREG
;
1517 extern __at(0x0199) __sfr RCREG1
;
1518 extern __at(0x019A) __sfr TX1REG
;
1519 extern __at(0x019A) __sfr TXREG
;
1520 extern __at(0x019A) __sfr TXREG1
;
1521 extern __at(0x019B) __sfr SP1BRG
;
1522 extern __at(0x019B) __sfr SP1BRGL
;
1523 extern __at(0x019B) __sfr SPBRG
;
1524 extern __at(0x019B) __sfr SPBRG1
;
1525 extern __at(0x019B) __sfr SPBRGL
;
1526 extern __at(0x019C) __sfr SP1BRGH
;
1527 extern __at(0x019C) __sfr SPBRGH
;
1528 extern __at(0x019C) __sfr SPBRGH1
;
1530 //==============================================================================
1533 extern __at(0x019D) __sfr RC1STA
;
1547 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
1558 //==============================================================================
1561 //==============================================================================
1564 extern __at(0x019D) __sfr RCSTA
;
1578 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
1580 #define _RCSTA_RX9D 0x01
1581 #define _RCSTA_OERR 0x02
1582 #define _RCSTA_FERR 0x04
1583 #define _RCSTA_ADDEN 0x08
1584 #define _RCSTA_CREN 0x10
1585 #define _RCSTA_SREN 0x20
1586 #define _RCSTA_RX9 0x40
1587 #define _RCSTA_SPEN 0x80
1589 //==============================================================================
1592 //==============================================================================
1595 extern __at(0x019D) __sfr RCSTA1
;
1609 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
1611 #define _RCSTA1_RX9D 0x01
1612 #define _RCSTA1_OERR 0x02
1613 #define _RCSTA1_FERR 0x04
1614 #define _RCSTA1_ADDEN 0x08
1615 #define _RCSTA1_CREN 0x10
1616 #define _RCSTA1_SREN 0x20
1617 #define _RCSTA1_RX9 0x40
1618 #define _RCSTA1_SPEN 0x80
1620 //==============================================================================
1623 //==============================================================================
1626 extern __at(0x019E) __sfr TX1STA
;
1640 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
1651 //==============================================================================
1654 //==============================================================================
1657 extern __at(0x019E) __sfr TXSTA
;
1671 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
1673 #define _TXSTA_TX9D 0x01
1674 #define _TXSTA_TRMT 0x02
1675 #define _TXSTA_BRGH 0x04
1676 #define _TXSTA_SENDB 0x08
1677 #define _TXSTA_SYNC 0x10
1678 #define _TXSTA_TXEN 0x20
1679 #define _TXSTA_TX9 0x40
1680 #define _TXSTA_CSRC 0x80
1682 //==============================================================================
1685 //==============================================================================
1688 extern __at(0x019E) __sfr TXSTA1
;
1702 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
1704 #define _TXSTA1_TX9D 0x01
1705 #define _TXSTA1_TRMT 0x02
1706 #define _TXSTA1_BRGH 0x04
1707 #define _TXSTA1_SENDB 0x08
1708 #define _TXSTA1_SYNC 0x10
1709 #define _TXSTA1_TXEN 0x20
1710 #define _TXSTA1_TX9 0x40
1711 #define _TXSTA1_CSRC 0x80
1713 //==============================================================================
1716 //==============================================================================
1719 extern __at(0x019F) __sfr BAUD1CON
;
1730 unsigned ABDOVF
: 1;
1733 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
1740 #define _ABDOVF 0x80
1742 //==============================================================================
1745 //==============================================================================
1748 extern __at(0x019F) __sfr BAUDCON
;
1759 unsigned ABDOVF
: 1;
1762 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
1764 #define _BAUDCON_ABDEN 0x01
1765 #define _BAUDCON_WUE 0x02
1766 #define _BAUDCON_BRG16 0x08
1767 #define _BAUDCON_SCKP 0x10
1768 #define _BAUDCON_RCIDL 0x40
1769 #define _BAUDCON_ABDOVF 0x80
1771 //==============================================================================
1774 //==============================================================================
1777 extern __at(0x019F) __sfr BAUDCON1
;
1788 unsigned ABDOVF
: 1;
1791 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
1793 #define _BAUDCON1_ABDEN 0x01
1794 #define _BAUDCON1_WUE 0x02
1795 #define _BAUDCON1_BRG16 0x08
1796 #define _BAUDCON1_SCKP 0x10
1797 #define _BAUDCON1_RCIDL 0x40
1798 #define _BAUDCON1_ABDOVF 0x80
1800 //==============================================================================
1803 //==============================================================================
1806 extern __at(0x019F) __sfr BAUDCTL
;
1817 unsigned ABDOVF
: 1;
1820 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
1822 #define _BAUDCTL_ABDEN 0x01
1823 #define _BAUDCTL_WUE 0x02
1824 #define _BAUDCTL_BRG16 0x08
1825 #define _BAUDCTL_SCKP 0x10
1826 #define _BAUDCTL_RCIDL 0x40
1827 #define _BAUDCTL_ABDOVF 0x80
1829 //==============================================================================
1832 //==============================================================================
1835 extern __at(0x019F) __sfr BAUDCTL1
;
1846 unsigned ABDOVF
: 1;
1849 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
1851 #define _BAUDCTL1_ABDEN 0x01
1852 #define _BAUDCTL1_WUE 0x02
1853 #define _BAUDCTL1_BRG16 0x08
1854 #define _BAUDCTL1_SCKP 0x10
1855 #define _BAUDCTL1_RCIDL 0x40
1856 #define _BAUDCTL1_ABDOVF 0x80
1858 //==============================================================================
1861 //==============================================================================
1864 extern __at(0x020C) __sfr WPUA
;
1887 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
1896 //==============================================================================
1899 //==============================================================================
1902 extern __at(0x0211) __sfr SSP1BUF
;
1908 unsigned SSP1BUF0
: 1;
1909 unsigned SSP1BUF1
: 1;
1910 unsigned SSP1BUF2
: 1;
1911 unsigned SSP1BUF3
: 1;
1912 unsigned SSP1BUF4
: 1;
1913 unsigned SSP1BUF5
: 1;
1914 unsigned SSP1BUF6
: 1;
1915 unsigned SSP1BUF7
: 1;
1931 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
1933 #define _SSP1BUF0 0x01
1935 #define _SSP1BUF1 0x02
1937 #define _SSP1BUF2 0x04
1939 #define _SSP1BUF3 0x08
1941 #define _SSP1BUF4 0x10
1943 #define _SSP1BUF5 0x20
1945 #define _SSP1BUF6 0x40
1947 #define _SSP1BUF7 0x80
1950 //==============================================================================
1953 //==============================================================================
1956 extern __at(0x0211) __sfr SSPBUF
;
1962 unsigned SSP1BUF0
: 1;
1963 unsigned SSP1BUF1
: 1;
1964 unsigned SSP1BUF2
: 1;
1965 unsigned SSP1BUF3
: 1;
1966 unsigned SSP1BUF4
: 1;
1967 unsigned SSP1BUF5
: 1;
1968 unsigned SSP1BUF6
: 1;
1969 unsigned SSP1BUF7
: 1;
1985 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
1987 #define _SSPBUF_SSP1BUF0 0x01
1988 #define _SSPBUF_BUF0 0x01
1989 #define _SSPBUF_SSP1BUF1 0x02
1990 #define _SSPBUF_BUF1 0x02
1991 #define _SSPBUF_SSP1BUF2 0x04
1992 #define _SSPBUF_BUF2 0x04
1993 #define _SSPBUF_SSP1BUF3 0x08
1994 #define _SSPBUF_BUF3 0x08
1995 #define _SSPBUF_SSP1BUF4 0x10
1996 #define _SSPBUF_BUF4 0x10
1997 #define _SSPBUF_SSP1BUF5 0x20
1998 #define _SSPBUF_BUF5 0x20
1999 #define _SSPBUF_SSP1BUF6 0x40
2000 #define _SSPBUF_BUF6 0x40
2001 #define _SSPBUF_SSP1BUF7 0x80
2002 #define _SSPBUF_BUF7 0x80
2004 //==============================================================================
2007 //==============================================================================
2010 extern __at(0x0212) __sfr SSP1ADD
;
2016 unsigned SSP1ADD0
: 1;
2017 unsigned SSP1ADD1
: 1;
2018 unsigned SSP1ADD2
: 1;
2019 unsigned SSP1ADD3
: 1;
2020 unsigned SSP1ADD4
: 1;
2021 unsigned SSP1ADD5
: 1;
2022 unsigned SSP1ADD6
: 1;
2023 unsigned SSP1ADD7
: 1;
2039 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
2041 #define _SSP1ADD0 0x01
2043 #define _SSP1ADD1 0x02
2045 #define _SSP1ADD2 0x04
2047 #define _SSP1ADD3 0x08
2049 #define _SSP1ADD4 0x10
2051 #define _SSP1ADD5 0x20
2053 #define _SSP1ADD6 0x40
2055 #define _SSP1ADD7 0x80
2058 //==============================================================================
2061 //==============================================================================
2064 extern __at(0x0212) __sfr SSPADD
;
2070 unsigned SSP1ADD0
: 1;
2071 unsigned SSP1ADD1
: 1;
2072 unsigned SSP1ADD2
: 1;
2073 unsigned SSP1ADD3
: 1;
2074 unsigned SSP1ADD4
: 1;
2075 unsigned SSP1ADD5
: 1;
2076 unsigned SSP1ADD6
: 1;
2077 unsigned SSP1ADD7
: 1;
2093 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
2095 #define _SSPADD_SSP1ADD0 0x01
2096 #define _SSPADD_ADD0 0x01
2097 #define _SSPADD_SSP1ADD1 0x02
2098 #define _SSPADD_ADD1 0x02
2099 #define _SSPADD_SSP1ADD2 0x04
2100 #define _SSPADD_ADD2 0x04
2101 #define _SSPADD_SSP1ADD3 0x08
2102 #define _SSPADD_ADD3 0x08
2103 #define _SSPADD_SSP1ADD4 0x10
2104 #define _SSPADD_ADD4 0x10
2105 #define _SSPADD_SSP1ADD5 0x20
2106 #define _SSPADD_ADD5 0x20
2107 #define _SSPADD_SSP1ADD6 0x40
2108 #define _SSPADD_ADD6 0x40
2109 #define _SSPADD_SSP1ADD7 0x80
2110 #define _SSPADD_ADD7 0x80
2112 //==============================================================================
2115 //==============================================================================
2118 extern __at(0x0213) __sfr SSP1MSK
;
2124 unsigned SSP1MSK0
: 1;
2125 unsigned SSP1MSK1
: 1;
2126 unsigned SSP1MSK2
: 1;
2127 unsigned SSP1MSK3
: 1;
2128 unsigned SSP1MSK4
: 1;
2129 unsigned SSP1MSK5
: 1;
2130 unsigned SSP1MSK6
: 1;
2131 unsigned SSP1MSK7
: 1;
2147 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
2149 #define _SSP1MSK0 0x01
2151 #define _SSP1MSK1 0x02
2153 #define _SSP1MSK2 0x04
2155 #define _SSP1MSK3 0x08
2157 #define _SSP1MSK4 0x10
2159 #define _SSP1MSK5 0x20
2161 #define _SSP1MSK6 0x40
2163 #define _SSP1MSK7 0x80
2166 //==============================================================================
2169 //==============================================================================
2172 extern __at(0x0213) __sfr SSPMSK
;
2178 unsigned SSP1MSK0
: 1;
2179 unsigned SSP1MSK1
: 1;
2180 unsigned SSP1MSK2
: 1;
2181 unsigned SSP1MSK3
: 1;
2182 unsigned SSP1MSK4
: 1;
2183 unsigned SSP1MSK5
: 1;
2184 unsigned SSP1MSK6
: 1;
2185 unsigned SSP1MSK7
: 1;
2201 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
2203 #define _SSPMSK_SSP1MSK0 0x01
2204 #define _SSPMSK_MSK0 0x01
2205 #define _SSPMSK_SSP1MSK1 0x02
2206 #define _SSPMSK_MSK1 0x02
2207 #define _SSPMSK_SSP1MSK2 0x04
2208 #define _SSPMSK_MSK2 0x04
2209 #define _SSPMSK_SSP1MSK3 0x08
2210 #define _SSPMSK_MSK3 0x08
2211 #define _SSPMSK_SSP1MSK4 0x10
2212 #define _SSPMSK_MSK4 0x10
2213 #define _SSPMSK_SSP1MSK5 0x20
2214 #define _SSPMSK_MSK5 0x20
2215 #define _SSPMSK_SSP1MSK6 0x40
2216 #define _SSPMSK_MSK6 0x40
2217 #define _SSPMSK_SSP1MSK7 0x80
2218 #define _SSPMSK_MSK7 0x80
2220 //==============================================================================
2223 //==============================================================================
2226 extern __at(0x0214) __sfr SSP1STAT
;
2232 unsigned R_NOT_W
: 1;
2235 unsigned D_NOT_A
: 1;
2240 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
2244 #define _R_NOT_W 0x04
2247 #define _D_NOT_A 0x20
2251 //==============================================================================
2254 //==============================================================================
2257 extern __at(0x0214) __sfr SSPSTAT
;
2263 unsigned R_NOT_W
: 1;
2266 unsigned D_NOT_A
: 1;
2271 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
2273 #define _SSPSTAT_BF 0x01
2274 #define _SSPSTAT_UA 0x02
2275 #define _SSPSTAT_R_NOT_W 0x04
2276 #define _SSPSTAT_S 0x08
2277 #define _SSPSTAT_P 0x10
2278 #define _SSPSTAT_D_NOT_A 0x20
2279 #define _SSPSTAT_CKE 0x40
2280 #define _SSPSTAT_SMP 0x80
2282 //==============================================================================
2285 //==============================================================================
2288 extern __at(0x0215) __sfr SSP1CON
;
2311 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
2322 //==============================================================================
2325 //==============================================================================
2328 extern __at(0x0215) __sfr SSP1CON1
;
2351 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
2353 #define _SSP1CON1_SSPM0 0x01
2354 #define _SSP1CON1_SSPM1 0x02
2355 #define _SSP1CON1_SSPM2 0x04
2356 #define _SSP1CON1_SSPM3 0x08
2357 #define _SSP1CON1_CKP 0x10
2358 #define _SSP1CON1_SSPEN 0x20
2359 #define _SSP1CON1_SSPOV 0x40
2360 #define _SSP1CON1_WCOL 0x80
2362 //==============================================================================
2365 //==============================================================================
2368 extern __at(0x0215) __sfr SSPCON
;
2391 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2393 #define _SSPCON_SSPM0 0x01
2394 #define _SSPCON_SSPM1 0x02
2395 #define _SSPCON_SSPM2 0x04
2396 #define _SSPCON_SSPM3 0x08
2397 #define _SSPCON_CKP 0x10
2398 #define _SSPCON_SSPEN 0x20
2399 #define _SSPCON_SSPOV 0x40
2400 #define _SSPCON_WCOL 0x80
2402 //==============================================================================
2405 //==============================================================================
2408 extern __at(0x0215) __sfr SSPCON1
;
2431 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2433 #define _SSPCON1_SSPM0 0x01
2434 #define _SSPCON1_SSPM1 0x02
2435 #define _SSPCON1_SSPM2 0x04
2436 #define _SSPCON1_SSPM3 0x08
2437 #define _SSPCON1_CKP 0x10
2438 #define _SSPCON1_SSPEN 0x20
2439 #define _SSPCON1_SSPOV 0x40
2440 #define _SSPCON1_WCOL 0x80
2442 //==============================================================================
2445 //==============================================================================
2448 extern __at(0x0216) __sfr SSP1CON2
;
2458 unsigned ACKSTAT
: 1;
2462 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
2470 #define _ACKSTAT 0x40
2473 //==============================================================================
2476 //==============================================================================
2479 extern __at(0x0216) __sfr SSPCON2
;
2489 unsigned ACKSTAT
: 1;
2493 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
2495 #define _SSPCON2_SEN 0x01
2496 #define _SSPCON2_RSEN 0x02
2497 #define _SSPCON2_PEN 0x04
2498 #define _SSPCON2_RCEN 0x08
2499 #define _SSPCON2_ACKEN 0x10
2500 #define _SSPCON2_ACKDT 0x20
2501 #define _SSPCON2_ACKSTAT 0x40
2502 #define _SSPCON2_GCEN 0x80
2504 //==============================================================================
2507 //==============================================================================
2510 extern __at(0x0217) __sfr SSP1CON3
;
2521 unsigned ACKTIM
: 1;
2524 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
2533 #define _ACKTIM 0x80
2535 //==============================================================================
2538 //==============================================================================
2541 extern __at(0x0217) __sfr SSPCON3
;
2552 unsigned ACKTIM
: 1;
2555 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
2557 #define _SSPCON3_DHEN 0x01
2558 #define _SSPCON3_AHEN 0x02
2559 #define _SSPCON3_SBCDE 0x04
2560 #define _SSPCON3_SDAHT 0x08
2561 #define _SSPCON3_BOEN 0x10
2562 #define _SSPCON3_SCIE 0x20
2563 #define _SSPCON3_PCIE 0x40
2564 #define _SSPCON3_ACKTIM 0x80
2566 //==============================================================================
2569 //==============================================================================
2572 extern __at(0x028C) __sfr ODCONA
;
2586 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
2594 //==============================================================================
2596 extern __at(0x0291) __sfr CCPR1
;
2597 extern __at(0x0291) __sfr CCPR1L
;
2598 extern __at(0x0292) __sfr CCPR1H
;
2600 //==============================================================================
2603 extern __at(0x0293) __sfr CCP1CON
;
2609 unsigned CCP1MODE0
: 1;
2610 unsigned CCP1MODE1
: 1;
2611 unsigned CCP1MODE2
: 1;
2612 unsigned CCP1MODE3
: 1;
2613 unsigned CCP1FMT
: 1;
2614 unsigned CCP1OUT
: 1;
2616 unsigned CCP1EN
: 1;
2621 unsigned CCP1MODE
: 4;
2626 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
2628 #define _CCP1MODE0 0x01
2629 #define _CCP1MODE1 0x02
2630 #define _CCP1MODE2 0x04
2631 #define _CCP1MODE3 0x08
2632 #define _CCP1FMT 0x10
2633 #define _CCP1OUT 0x20
2634 #define _CCP1EN 0x80
2636 //==============================================================================
2639 //==============================================================================
2642 extern __at(0x0294) __sfr CCP1CAP
;
2648 unsigned CCP1CTS0
: 1;
2649 unsigned CCP1CTS1
: 1;
2650 unsigned CCP1CTS2
: 1;
2660 unsigned CCP1CTS
: 3;
2665 extern __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits
;
2667 #define _CCP1CTS0 0x01
2668 #define _CCP1CTS1 0x02
2669 #define _CCP1CTS2 0x04
2671 //==============================================================================
2673 extern __at(0x0295) __sfr CCPR2
;
2674 extern __at(0x0295) __sfr CCPR2L
;
2675 extern __at(0x0296) __sfr CCPR2H
;
2677 //==============================================================================
2680 extern __at(0x0297) __sfr CCP2CON
;
2686 unsigned CCP2MODE0
: 1;
2687 unsigned CCP2MODE1
: 1;
2688 unsigned CCP2MODE2
: 1;
2689 unsigned CCP2MODE3
: 1;
2690 unsigned CCP2FMT
: 1;
2691 unsigned CCP2OUT
: 1;
2693 unsigned CCP2EN
: 1;
2698 unsigned CCP2MODE
: 4;
2703 extern __at(0x0297) volatile __CCP2CONbits_t CCP2CONbits
;
2705 #define _CCP2MODE0 0x01
2706 #define _CCP2MODE1 0x02
2707 #define _CCP2MODE2 0x04
2708 #define _CCP2MODE3 0x08
2709 #define _CCP2FMT 0x10
2710 #define _CCP2OUT 0x20
2711 #define _CCP2EN 0x80
2713 //==============================================================================
2716 //==============================================================================
2719 extern __at(0x0298) __sfr CCP2CAP
;
2725 unsigned CCP2CTS0
: 1;
2726 unsigned CCP2CTS1
: 1;
2727 unsigned CCP2CTS2
: 1;
2737 unsigned CCP2CTS
: 3;
2742 extern __at(0x0298) volatile __CCP2CAPbits_t CCP2CAPbits
;
2744 #define _CCP2CTS0 0x01
2745 #define _CCP2CTS1 0x02
2746 #define _CCP2CTS2 0x04
2748 //==============================================================================
2751 //==============================================================================
2754 extern __at(0x029F) __sfr CCPTMRS
;
2758 unsigned C1TSEL
: 1;
2760 unsigned C2TSEL
: 1;
2768 extern __at(0x029F) volatile __CCPTMRSbits_t CCPTMRSbits
;
2770 #define _C1TSEL 0x01
2771 #define _C2TSEL 0x04
2773 //==============================================================================
2776 //==============================================================================
2779 extern __at(0x030C) __sfr SLRCONA
;
2793 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
2801 //==============================================================================
2804 //==============================================================================
2807 extern __at(0x038C) __sfr INLVLA
;
2813 unsigned INLVLA0
: 1;
2814 unsigned INLVLA1
: 1;
2815 unsigned INLVLA2
: 1;
2816 unsigned INLVLA3
: 1;
2817 unsigned INLVLA4
: 1;
2818 unsigned INLVLA5
: 1;
2825 unsigned INLVLA
: 6;
2830 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
2832 #define _INLVLA0 0x01
2833 #define _INLVLA1 0x02
2834 #define _INLVLA2 0x04
2835 #define _INLVLA3 0x08
2836 #define _INLVLA4 0x10
2837 #define _INLVLA5 0x20
2839 //==============================================================================
2842 //==============================================================================
2845 extern __at(0x0391) __sfr IOCAP
;
2851 unsigned IOCAP0
: 1;
2852 unsigned IOCAP1
: 1;
2853 unsigned IOCAP2
: 1;
2854 unsigned IOCAP3
: 1;
2855 unsigned IOCAP4
: 1;
2856 unsigned IOCAP5
: 1;
2868 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
2870 #define _IOCAP0 0x01
2871 #define _IOCAP1 0x02
2872 #define _IOCAP2 0x04
2873 #define _IOCAP3 0x08
2874 #define _IOCAP4 0x10
2875 #define _IOCAP5 0x20
2877 //==============================================================================
2880 //==============================================================================
2883 extern __at(0x0392) __sfr IOCAN
;
2889 unsigned IOCAN0
: 1;
2890 unsigned IOCAN1
: 1;
2891 unsigned IOCAN2
: 1;
2892 unsigned IOCAN3
: 1;
2893 unsigned IOCAN4
: 1;
2894 unsigned IOCAN5
: 1;
2906 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
2908 #define _IOCAN0 0x01
2909 #define _IOCAN1 0x02
2910 #define _IOCAN2 0x04
2911 #define _IOCAN3 0x08
2912 #define _IOCAN4 0x10
2913 #define _IOCAN5 0x20
2915 //==============================================================================
2918 //==============================================================================
2921 extern __at(0x0393) __sfr IOCAF
;
2927 unsigned IOCAF0
: 1;
2928 unsigned IOCAF1
: 1;
2929 unsigned IOCAF2
: 1;
2930 unsigned IOCAF3
: 1;
2931 unsigned IOCAF4
: 1;
2932 unsigned IOCAF5
: 1;
2944 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
2946 #define _IOCAF0 0x01
2947 #define _IOCAF1 0x02
2948 #define _IOCAF2 0x04
2949 #define _IOCAF3 0x08
2950 #define _IOCAF4 0x10
2951 #define _IOCAF5 0x20
2953 //==============================================================================
2956 //==============================================================================
2959 extern __at(0x039A) __sfr CLKRCON
;
2965 unsigned CLKRDIV0
: 1;
2966 unsigned CLKRDIV1
: 1;
2967 unsigned CLKRDIV2
: 1;
2968 unsigned CLKRDC0
: 1;
2969 unsigned CLKRDC1
: 1;
2972 unsigned CLKREN
: 1;
2977 unsigned CLKRDIV
: 3;
2984 unsigned CLKRDC
: 2;
2989 extern __at(0x039A) volatile __CLKRCONbits_t CLKRCONbits
;
2991 #define _CLKRDIV0 0x01
2992 #define _CLKRDIV1 0x02
2993 #define _CLKRDIV2 0x04
2994 #define _CLKRDC0 0x08
2995 #define _CLKRDC1 0x10
2996 #define _CLKREN 0x80
2998 //==============================================================================
3001 //==============================================================================
3004 extern __at(0x039C) __sfr MDCON
;
3012 unsigned MDOPOL
: 1;
3018 extern __at(0x039C) volatile __MDCONbits_t MDCONbits
;
3022 #define _MDOPOL 0x10
3025 //==============================================================================
3028 //==============================================================================
3031 extern __at(0x039D) __sfr MDSRC
;
3054 extern __at(0x039D) volatile __MDSRCbits_t MDSRCbits
;
3061 //==============================================================================
3064 //==============================================================================
3067 extern __at(0x039E) __sfr MDCARH
;
3078 unsigned MDCHSYNC
: 1;
3079 unsigned MDCHPOL
: 1;
3090 extern __at(0x039E) volatile __MDCARHbits_t MDCARHbits
;
3096 #define _MDCHSYNC 0x20
3097 #define _MDCHPOL 0x40
3099 //==============================================================================
3102 //==============================================================================
3105 extern __at(0x039F) __sfr MDCARL
;
3116 unsigned MDCLSYNC
: 1;
3117 unsigned MDCLPOL
: 1;
3128 extern __at(0x039F) volatile __MDCARLbits_t MDCARLbits
;
3134 #define _MDCLSYNC 0x20
3135 #define _MDCLPOL 0x40
3137 //==============================================================================
3140 //==============================================================================
3143 extern __at(0x040C) __sfr CCDNA
;
3147 unsigned CCDNA0
: 1;
3148 unsigned CCDNA1
: 1;
3149 unsigned CCDNA2
: 1;
3151 unsigned CCDNA4
: 1;
3152 unsigned CCDNA5
: 1;
3157 extern __at(0x040C) volatile __CCDNAbits_t CCDNAbits
;
3159 #define _CCDNA0 0x01
3160 #define _CCDNA1 0x02
3161 #define _CCDNA2 0x04
3162 #define _CCDNA4 0x10
3163 #define _CCDNA5 0x20
3165 //==============================================================================
3168 //==============================================================================
3171 extern __at(0x041F) __sfr CCDCON
;
3194 extern __at(0x041F) volatile __CCDCONbits_t CCDCONbits
;
3200 //==============================================================================
3203 //==============================================================================
3206 extern __at(0x048C) __sfr CCDPA
;
3210 unsigned CCDPA0
: 1;
3211 unsigned CCDPA1
: 1;
3212 unsigned CCDPA2
: 1;
3214 unsigned CCDPA4
: 1;
3215 unsigned CCDPA5
: 1;
3220 extern __at(0x048C) volatile __CCDPAbits_t CCDPAbits
;
3222 #define _CCDPA0 0x01
3223 #define _CCDPA1 0x02
3224 #define _CCDPA2 0x04
3225 #define _CCDPA4 0x10
3226 #define _CCDPA5 0x20
3228 //==============================================================================
3230 extern __at(0x0498) __sfr NCO1ACC
;
3231 extern __at(0x0498) __sfr NCO1ACCL
;
3232 extern __at(0x0499) __sfr NCO1ACCH
;
3233 extern __at(0x049A) __sfr NCO1ACCU
;
3234 extern __at(0x049B) __sfr NCO1INC
;
3235 extern __at(0x049B) __sfr NCO1INCL
;
3236 extern __at(0x049C) __sfr NCO1INCH
;
3237 extern __at(0x049D) __sfr NCO1INCU
;
3239 //==============================================================================
3242 extern __at(0x049E) __sfr NCO1CON
;
3256 extern __at(0x049E) volatile __NCO1CONbits_t NCO1CONbits
;
3263 //==============================================================================
3265 extern __at(0x049F) __sfr NCO1CLK
;
3267 //==============================================================================
3270 extern __at(0x0617) __sfr PWM5DCL
;
3282 unsigned PWM5DCL0
: 1;
3283 unsigned PWM5DCL1
: 1;
3289 unsigned PWM5DCL
: 2;
3293 extern __at(0x0617) volatile __PWM5DCLbits_t PWM5DCLbits
;
3295 #define _PWM5DCL0 0x40
3296 #define _PWM5DCL1 0x80
3298 //==============================================================================
3301 //==============================================================================
3304 extern __at(0x0618) __sfr PWM5DCH
;
3308 unsigned PWM5DCH0
: 1;
3309 unsigned PWM5DCH1
: 1;
3310 unsigned PWM5DCH2
: 1;
3311 unsigned PWM5DCH3
: 1;
3312 unsigned PWM5DCH4
: 1;
3313 unsigned PWM5DCH5
: 1;
3314 unsigned PWM5DCH6
: 1;
3315 unsigned PWM5DCH7
: 1;
3318 extern __at(0x0618) volatile __PWM5DCHbits_t PWM5DCHbits
;
3320 #define _PWM5DCH0 0x01
3321 #define _PWM5DCH1 0x02
3322 #define _PWM5DCH2 0x04
3323 #define _PWM5DCH3 0x08
3324 #define _PWM5DCH4 0x10
3325 #define _PWM5DCH5 0x20
3326 #define _PWM5DCH6 0x40
3327 #define _PWM5DCH7 0x80
3329 //==============================================================================
3332 //==============================================================================
3335 extern __at(0x0619) __sfr PWM5CON
;
3343 unsigned PWM5POL
: 1;
3344 unsigned PWM5OUT
: 1;
3346 unsigned PWM5EN
: 1;
3349 extern __at(0x0619) volatile __PWM5CONbits_t PWM5CONbits
;
3351 #define _PWM5POL 0x10
3352 #define _PWM5OUT 0x20
3353 #define _PWM5EN 0x80
3355 //==============================================================================
3358 //==============================================================================
3361 extern __at(0x0619) __sfr PWM5CON0
;
3369 unsigned PWM5POL
: 1;
3370 unsigned PWM5OUT
: 1;
3372 unsigned PWM5EN
: 1;
3375 extern __at(0x0619) volatile __PWM5CON0bits_t PWM5CON0bits
;
3377 #define _PWM5CON0_PWM5POL 0x10
3378 #define _PWM5CON0_PWM5OUT 0x20
3379 #define _PWM5CON0_PWM5EN 0x80
3381 //==============================================================================
3384 //==============================================================================
3387 extern __at(0x061A) __sfr PWM6DCL
;
3399 unsigned PWM6DCL0
: 1;
3400 unsigned PWM6DCL1
: 1;
3406 unsigned PWM6DCL
: 2;
3410 extern __at(0x061A) volatile __PWM6DCLbits_t PWM6DCLbits
;
3412 #define _PWM6DCL0 0x40
3413 #define _PWM6DCL1 0x80
3415 //==============================================================================
3418 //==============================================================================
3421 extern __at(0x061B) __sfr PWM6DCH
;
3425 unsigned PWM6DCH0
: 1;
3426 unsigned PWM6DCH1
: 1;
3427 unsigned PWM6DCH2
: 1;
3428 unsigned PWM6DCH3
: 1;
3429 unsigned PWM6DCH4
: 1;
3430 unsigned PWM6DCH5
: 1;
3431 unsigned PWM6DCH6
: 1;
3432 unsigned PWM6DCH7
: 1;
3435 extern __at(0x061B) volatile __PWM6DCHbits_t PWM6DCHbits
;
3437 #define _PWM6DCH0 0x01
3438 #define _PWM6DCH1 0x02
3439 #define _PWM6DCH2 0x04
3440 #define _PWM6DCH3 0x08
3441 #define _PWM6DCH4 0x10
3442 #define _PWM6DCH5 0x20
3443 #define _PWM6DCH6 0x40
3444 #define _PWM6DCH7 0x80
3446 //==============================================================================
3449 //==============================================================================
3452 extern __at(0x061C) __sfr PWM6CON
;
3460 unsigned PWM6POL
: 1;
3461 unsigned PWM6OUT
: 1;
3463 unsigned PWM6EN
: 1;
3466 extern __at(0x061C) volatile __PWM6CONbits_t PWM6CONbits
;
3468 #define _PWM6POL 0x10
3469 #define _PWM6OUT 0x20
3470 #define _PWM6EN 0x80
3472 //==============================================================================
3475 //==============================================================================
3478 extern __at(0x061C) __sfr PWM6CON0
;
3486 unsigned PWM6POL
: 1;
3487 unsigned PWM6OUT
: 1;
3489 unsigned PWM6EN
: 1;
3492 extern __at(0x061C) volatile __PWM6CON0bits_t PWM6CON0bits
;
3494 #define _PWM6CON0_PWM6POL 0x10
3495 #define _PWM6CON0_PWM6OUT 0x20
3496 #define _PWM6CON0_PWM6EN 0x80
3498 //==============================================================================
3501 //==============================================================================
3504 extern __at(0x0691) __sfr CWG1CLKCON
;
3522 unsigned CWG1CS
: 1;
3531 } __CWG1CLKCONbits_t
;
3533 extern __at(0x0691) volatile __CWG1CLKCONbits_t CWG1CLKCONbits
;
3536 #define _CWG1CS 0x01
3538 //==============================================================================
3541 //==============================================================================
3544 extern __at(0x0692) __sfr CWG1DAT
;
3550 unsigned CWG1DAT0
: 1;
3551 unsigned CWG1DAT1
: 1;
3552 unsigned CWG1DAT2
: 1;
3553 unsigned CWG1DAT3
: 1;
3562 unsigned CWG1DAT
: 4;
3567 extern __at(0x0692) volatile __CWG1DATbits_t CWG1DATbits
;
3569 #define _CWG1DAT0 0x01
3570 #define _CWG1DAT1 0x02
3571 #define _CWG1DAT2 0x04
3572 #define _CWG1DAT3 0x08
3574 //==============================================================================
3577 //==============================================================================
3580 extern __at(0x0693) __sfr CWG1DBR
;
3598 unsigned CWG1DBR0
: 1;
3599 unsigned CWG1DBR1
: 1;
3600 unsigned CWG1DBR2
: 1;
3601 unsigned CWG1DBR3
: 1;
3602 unsigned CWG1DBR4
: 1;
3603 unsigned CWG1DBR5
: 1;
3616 unsigned CWG1DBR
: 6;
3621 extern __at(0x0693) volatile __CWG1DBRbits_t CWG1DBRbits
;
3624 #define _CWG1DBR0 0x01
3626 #define _CWG1DBR1 0x02
3628 #define _CWG1DBR2 0x04
3630 #define _CWG1DBR3 0x08
3632 #define _CWG1DBR4 0x10
3634 #define _CWG1DBR5 0x20
3636 //==============================================================================
3639 //==============================================================================
3642 extern __at(0x0694) __sfr CWG1DBF
;
3660 unsigned CWG1DBF0
: 1;
3661 unsigned CWG1DBF1
: 1;
3662 unsigned CWG1DBF2
: 1;
3663 unsigned CWG1DBF3
: 1;
3664 unsigned CWG1DBF4
: 1;
3665 unsigned CWG1DBF5
: 1;
3678 unsigned CWG1DBF
: 6;
3683 extern __at(0x0694) volatile __CWG1DBFbits_t CWG1DBFbits
;
3686 #define _CWG1DBF0 0x01
3688 #define _CWG1DBF1 0x02
3690 #define _CWG1DBF2 0x04
3692 #define _CWG1DBF3 0x08
3694 #define _CWG1DBF4 0x10
3696 #define _CWG1DBF5 0x20
3698 //==============================================================================
3701 //==============================================================================
3704 extern __at(0x0695) __sfr CWG1CON0
;
3722 unsigned CWG1MODE0
: 1;
3723 unsigned CWG1MODE1
: 1;
3724 unsigned CWG1MODE2
: 1;
3728 unsigned CWG1LD
: 1;
3741 unsigned CWG1EN
: 1;
3746 unsigned CWG1MODE
: 3;
3757 extern __at(0x0695) volatile __CWG1CON0bits_t CWG1CON0bits
;
3759 #define _CWG1CON0_MODE0 0x01
3760 #define _CWG1CON0_CWG1MODE0 0x01
3761 #define _CWG1CON0_MODE1 0x02
3762 #define _CWG1CON0_CWG1MODE1 0x02
3763 #define _CWG1CON0_MODE2 0x04
3764 #define _CWG1CON0_CWG1MODE2 0x04
3765 #define _CWG1CON0_LD 0x40
3766 #define _CWG1CON0_CWG1LD 0x40
3767 #define _CWG1CON0_EN 0x80
3768 #define _CWG1CON0_G1EN 0x80
3769 #define _CWG1CON0_CWG1EN 0x80
3771 //==============================================================================
3774 //==============================================================================
3777 extern __at(0x0696) __sfr CWG1CON1
;
3795 unsigned CWG1POLA
: 1;
3796 unsigned CWG1POLB
: 1;
3797 unsigned CWG1POLC
: 1;
3798 unsigned CWG1POLD
: 1;
3800 unsigned CWG1IN
: 1;
3806 extern __at(0x0696) volatile __CWG1CON1bits_t CWG1CON1bits
;
3809 #define _CWG1POLA 0x01
3811 #define _CWG1POLB 0x02
3813 #define _CWG1POLC 0x04
3815 #define _CWG1POLD 0x08
3817 #define _CWG1IN 0x20
3819 //==============================================================================
3822 //==============================================================================
3825 extern __at(0x0697) __sfr CWG1AS0
;
3838 unsigned SHUTDOWN
: 1;
3845 unsigned CWG1LSAC0
: 1;
3846 unsigned CWG1LSAC1
: 1;
3847 unsigned CWG1LSBD0
: 1;
3848 unsigned CWG1LSBD1
: 1;
3849 unsigned CWG1REN
: 1;
3850 unsigned CWG1SHUTDOWN
: 1;
3856 unsigned CWG1LSAC
: 2;
3870 unsigned CWG1LSBD
: 2;
3882 extern __at(0x0697) volatile __CWG1AS0bits_t CWG1AS0bits
;
3885 #define _CWG1LSAC0 0x04
3887 #define _CWG1LSAC1 0x08
3889 #define _CWG1LSBD0 0x10
3891 #define _CWG1LSBD1 0x20
3893 #define _CWG1REN 0x40
3894 #define _SHUTDOWN 0x80
3895 #define _CWG1SHUTDOWN 0x80
3897 //==============================================================================
3900 //==============================================================================
3903 extern __at(0x0698) __sfr CWG1AS1
;
3917 extern __at(0x0698) volatile __CWG1AS1bits_t CWG1AS1bits
;
3923 //==============================================================================
3926 //==============================================================================
3929 extern __at(0x0699) __sfr CWG1STR
;
3947 unsigned CWG1STRA
: 1;
3948 unsigned CWG1STRB
: 1;
3949 unsigned CWG1STRC
: 1;
3950 unsigned CWG1STRD
: 1;
3951 unsigned CWG1OVRA
: 1;
3952 unsigned CWG1OVRB
: 1;
3953 unsigned CWG1OVRC
: 1;
3954 unsigned CWG1OVRD
: 1;
3958 extern __at(0x0699) volatile __CWG1STRbits_t CWG1STRbits
;
3961 #define _CWG1STRA 0x01
3963 #define _CWG1STRB 0x02
3965 #define _CWG1STRC 0x04
3967 #define _CWG1STRD 0x08
3969 #define _CWG1OVRA 0x10
3971 #define _CWG1OVRB 0x20
3973 #define _CWG1OVRC 0x40
3975 #define _CWG1OVRD 0x80
3977 //==============================================================================
3979 extern __at(0x0891) __sfr NVMADR
;
3981 //==============================================================================
3984 extern __at(0x0891) __sfr NVMADRL
;
3988 unsigned NVMADR0
: 1;
3989 unsigned NVMADR1
: 1;
3990 unsigned NVMADR2
: 1;
3991 unsigned NVMADR3
: 1;
3992 unsigned NVMADR4
: 1;
3993 unsigned NVMADR5
: 1;
3994 unsigned NVMADR6
: 1;
3995 unsigned NVMADR7
: 1;
3998 extern __at(0x0891) volatile __NVMADRLbits_t NVMADRLbits
;
4000 #define _NVMADR0 0x01
4001 #define _NVMADR1 0x02
4002 #define _NVMADR2 0x04
4003 #define _NVMADR3 0x08
4004 #define _NVMADR4 0x10
4005 #define _NVMADR5 0x20
4006 #define _NVMADR6 0x40
4007 #define _NVMADR7 0x80
4009 //==============================================================================
4012 //==============================================================================
4015 extern __at(0x0892) __sfr NVMADRH
;
4019 unsigned NVMADR8
: 1;
4020 unsigned NVMADR9
: 1;
4021 unsigned NVMADR10
: 1;
4022 unsigned NVMADR11
: 1;
4023 unsigned NVMADR12
: 1;
4024 unsigned NVMADR13
: 1;
4025 unsigned NVMADR14
: 1;
4029 extern __at(0x0892) volatile __NVMADRHbits_t NVMADRHbits
;
4031 #define _NVMADR8 0x01
4032 #define _NVMADR9 0x02
4033 #define _NVMADR10 0x04
4034 #define _NVMADR11 0x08
4035 #define _NVMADR12 0x10
4036 #define _NVMADR13 0x20
4037 #define _NVMADR14 0x40
4039 //==============================================================================
4041 extern __at(0x0893) __sfr NVMDAT
;
4043 //==============================================================================
4046 extern __at(0x0893) __sfr NVMDATL
;
4050 unsigned NVMDAT0
: 1;
4051 unsigned NVMDAT1
: 1;
4052 unsigned NVMDAT2
: 1;
4053 unsigned NVMDAT3
: 1;
4054 unsigned NVMDAT4
: 1;
4055 unsigned NVMDAT5
: 1;
4056 unsigned NVMDAT6
: 1;
4057 unsigned NVMDAT7
: 1;
4060 extern __at(0x0893) volatile __NVMDATLbits_t NVMDATLbits
;
4062 #define _NVMDAT0 0x01
4063 #define _NVMDAT1 0x02
4064 #define _NVMDAT2 0x04
4065 #define _NVMDAT3 0x08
4066 #define _NVMDAT4 0x10
4067 #define _NVMDAT5 0x20
4068 #define _NVMDAT6 0x40
4069 #define _NVMDAT7 0x80
4071 //==============================================================================
4074 //==============================================================================
4077 extern __at(0x0894) __sfr NVMDATH
;
4081 unsigned NVMDAT8
: 1;
4082 unsigned NVMDAT9
: 1;
4083 unsigned NVMDAT10
: 1;
4084 unsigned NVMDAT11
: 1;
4085 unsigned NVMDAT12
: 1;
4086 unsigned NVMDAT13
: 1;
4091 extern __at(0x0894) volatile __NVMDATHbits_t NVMDATHbits
;
4093 #define _NVMDAT8 0x01
4094 #define _NVMDAT9 0x02
4095 #define _NVMDAT10 0x04
4096 #define _NVMDAT11 0x08
4097 #define _NVMDAT12 0x10
4098 #define _NVMDAT13 0x20
4100 //==============================================================================
4103 //==============================================================================
4106 extern __at(0x0895) __sfr NVMCON1
;
4116 unsigned NVMREGS
: 1;
4120 extern __at(0x0895) volatile __NVMCON1bits_t NVMCON1bits
;
4128 #define _NVMREGS 0x40
4130 //==============================================================================
4132 extern __at(0x0896) __sfr NVMCON2
;
4134 //==============================================================================
4137 extern __at(0x089B) __sfr PCON0
;
4141 unsigned NOT_BOR
: 1;
4142 unsigned NOT_POR
: 1;
4143 unsigned NOT_RI
: 1;
4144 unsigned NOT_RMCLR
: 1;
4145 unsigned NOT_RWDT
: 1;
4147 unsigned STKUNF
: 1;
4148 unsigned STKOVF
: 1;
4151 extern __at(0x089B) volatile __PCON0bits_t PCON0bits
;
4153 #define _NOT_BOR 0x01
4154 #define _NOT_POR 0x02
4155 #define _NOT_RI 0x04
4156 #define _NOT_RMCLR 0x08
4157 #define _NOT_RWDT 0x10
4158 #define _STKUNF 0x40
4159 #define _STKOVF 0x80
4161 //==============================================================================
4164 //==============================================================================
4167 extern __at(0x0911) __sfr PMD0
;
4172 unsigned CLKRMD
: 1;
4178 unsigned SYSCMD
: 1;
4181 extern __at(0x0911) volatile __PMD0bits_t PMD0bits
;
4184 #define _CLKRMD 0x02
4187 #define _SYSCMD 0x80
4189 //==============================================================================
4192 //==============================================================================
4195 extern __at(0x0912) __sfr PMD1
;
4199 unsigned TMR0MD
: 1;
4200 unsigned TMR1MD
: 1;
4201 unsigned TMR2MD
: 1;
4209 extern __at(0x0912) volatile __PMD1bits_t PMD1bits
;
4211 #define _TMR0MD 0x01
4212 #define _TMR1MD 0x02
4213 #define _TMR2MD 0x04
4216 //==============================================================================
4219 //==============================================================================
4222 extern __at(0x0913) __sfr PMD2
;
4227 unsigned CMP1MD
: 1;
4236 extern __at(0x0913) volatile __PMD2bits_t PMD2bits
;
4238 #define _CMP1MD 0x02
4242 //==============================================================================
4245 //==============================================================================
4248 extern __at(0x0914) __sfr PMD3
;
4252 unsigned CCP1MD
: 1;
4253 unsigned CCP2MD
: 1;
4256 unsigned PWM5MD
: 1;
4257 unsigned PWM6MD
: 1;
4258 unsigned CWG1MD
: 1;
4262 extern __at(0x0914) volatile __PMD3bits_t PMD3bits
;
4264 #define _CCP1MD 0x01
4265 #define _CCP2MD 0x02
4266 #define _PWM5MD 0x10
4267 #define _PWM6MD 0x20
4268 #define _CWG1MD 0x40
4270 //==============================================================================
4273 //==============================================================================
4276 extern __at(0x0915) __sfr PMD4
;
4281 unsigned MSSP1MD
: 1;
4285 unsigned UART1MD
: 1;
4290 extern __at(0x0915) volatile __PMD4bits_t PMD4bits
;
4292 #define _MSSP1MD 0x02
4293 #define _UART1MD 0x20
4295 //==============================================================================
4298 //==============================================================================
4301 extern __at(0x0916) __sfr PMD5
;
4306 unsigned CLC1MD
: 1;
4307 unsigned CLC2MD
: 1;
4315 extern __at(0x0916) volatile __PMD5bits_t PMD5bits
;
4318 #define _CLC1MD 0x02
4319 #define _CLC2MD 0x04
4321 //==============================================================================
4324 //==============================================================================
4327 extern __at(0x0918) __sfr CPUDOZE
;
4350 extern __at(0x0918) volatile __CPUDOZEbits_t CPUDOZEbits
;
4360 //==============================================================================
4363 //==============================================================================
4366 extern __at(0x0919) __sfr OSCCON1
;
4396 extern __at(0x0919) volatile __OSCCON1bits_t OSCCON1bits
;
4406 //==============================================================================
4409 //==============================================================================
4412 extern __at(0x091A) __sfr OSCCON2
;
4442 extern __at(0x091A) volatile __OSCCON2bits_t OSCCON2bits
;
4452 //==============================================================================
4455 //==============================================================================
4458 extern __at(0x091B) __sfr OSCCON3
;
4467 unsigned SOSCBE
: 1;
4468 unsigned SOSCPWR
: 1;
4469 unsigned CSWHOLD
: 1;
4472 extern __at(0x091B) volatile __OSCCON3bits_t OSCCON3bits
;
4476 #define _SOSCBE 0x20
4477 #define _SOSCPWR 0x40
4478 #define _CSWHOLD 0x80
4480 //==============================================================================
4483 //==============================================================================
4486 extern __at(0x091C) __sfr OSCSTAT1
;
4500 extern __at(0x091C) volatile __OSCSTAT1bits_t OSCSTAT1bits
;
4509 //==============================================================================
4512 //==============================================================================
4515 extern __at(0x091D) __sfr OSCEN
;
4522 unsigned SOSCEN
: 1;
4526 unsigned EXTOEN
: 1;
4529 extern __at(0x091D) volatile __OSCENbits_t OSCENbits
;
4532 #define _SOSCEN 0x08
4535 #define _EXTOEN 0x80
4537 //==============================================================================
4540 //==============================================================================
4543 extern __at(0x091E) __sfr OSCTUNE
;
4549 unsigned HFTUN0
: 1;
4550 unsigned HFTUN1
: 1;
4551 unsigned HFTUN2
: 1;
4552 unsigned HFTUN3
: 1;
4553 unsigned HFTUN4
: 1;
4554 unsigned HFTUN5
: 1;
4566 extern __at(0x091E) volatile __OSCTUNEbits_t OSCTUNEbits
;
4568 #define _HFTUN0 0x01
4569 #define _HFTUN1 0x02
4570 #define _HFTUN2 0x04
4571 #define _HFTUN3 0x08
4572 #define _HFTUN4 0x10
4573 #define _HFTUN5 0x20
4575 //==============================================================================
4578 //==============================================================================
4581 extern __at(0x091F) __sfr OSCFRQ
;
4587 unsigned HFFRQ0
: 1;
4588 unsigned HFFRQ1
: 1;
4589 unsigned HFFRQ2
: 1;
4590 unsigned HFFRQ3
: 1;
4604 extern __at(0x091F) volatile __OSCFRQbits_t OSCFRQbits
;
4606 #define _HFFRQ0 0x01
4607 #define _HFFRQ1 0x02
4608 #define _HFFRQ2 0x04
4609 #define _HFFRQ3 0x08
4611 //==============================================================================
4614 //==============================================================================
4617 extern __at(0x0E0F) __sfr PPSLOCK
;
4621 unsigned PPSLOCKED
: 1;
4631 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
4633 #define _PPSLOCKED 0x01
4635 //==============================================================================
4638 //==============================================================================
4641 extern __at(0x0E10) __sfr INTPPS
;
4647 unsigned INTPPS0
: 1;
4648 unsigned INTPPS1
: 1;
4649 unsigned INTPPS2
: 1;
4650 unsigned INTPPS3
: 1;
4651 unsigned INTPPS4
: 1;
4659 unsigned INTPPS
: 5;
4664 extern __at(0x0E10) volatile __INTPPSbits_t INTPPSbits
;
4666 #define _INTPPS0 0x01
4667 #define _INTPPS1 0x02
4668 #define _INTPPS2 0x04
4669 #define _INTPPS3 0x08
4670 #define _INTPPS4 0x10
4672 //==============================================================================
4675 //==============================================================================
4678 extern __at(0x0E11) __sfr T0CKIPPS
;
4684 unsigned T0CKIPPS0
: 1;
4685 unsigned T0CKIPPS1
: 1;
4686 unsigned T0CKIPPS2
: 1;
4687 unsigned T0CKIPPS3
: 1;
4688 unsigned T0CKIPPS4
: 1;
4696 unsigned T0CKIPPS
: 5;
4701 extern __at(0x0E11) volatile __T0CKIPPSbits_t T0CKIPPSbits
;
4703 #define _T0CKIPPS0 0x01
4704 #define _T0CKIPPS1 0x02
4705 #define _T0CKIPPS2 0x04
4706 #define _T0CKIPPS3 0x08
4707 #define _T0CKIPPS4 0x10
4709 //==============================================================================
4712 //==============================================================================
4715 extern __at(0x0E12) __sfr T1CKIPPS
;
4721 unsigned T1CKIPPS0
: 1;
4722 unsigned T1CKIPPS1
: 1;
4723 unsigned T1CKIPPS2
: 1;
4724 unsigned T1CKIPPS3
: 1;
4725 unsigned T1CKIPPS4
: 1;
4733 unsigned T1CKIPPS
: 5;
4738 extern __at(0x0E12) volatile __T1CKIPPSbits_t T1CKIPPSbits
;
4740 #define _T1CKIPPS0 0x01
4741 #define _T1CKIPPS1 0x02
4742 #define _T1CKIPPS2 0x04
4743 #define _T1CKIPPS3 0x08
4744 #define _T1CKIPPS4 0x10
4746 //==============================================================================
4749 //==============================================================================
4752 extern __at(0x0E13) __sfr T1GPPS
;
4758 unsigned T1GPPS0
: 1;
4759 unsigned T1GPPS1
: 1;
4760 unsigned T1GPPS2
: 1;
4761 unsigned T1GPPS3
: 1;
4762 unsigned T1GPPS4
: 1;
4770 unsigned T1GPPS
: 5;
4775 extern __at(0x0E13) volatile __T1GPPSbits_t T1GPPSbits
;
4777 #define _T1GPPS0 0x01
4778 #define _T1GPPS1 0x02
4779 #define _T1GPPS2 0x04
4780 #define _T1GPPS3 0x08
4781 #define _T1GPPS4 0x10
4783 //==============================================================================
4786 //==============================================================================
4789 extern __at(0x0E14) __sfr CCP1PPS
;
4795 unsigned CCP1PPS0
: 1;
4796 unsigned CCP1PPS1
: 1;
4797 unsigned CCP1PPS2
: 1;
4798 unsigned CCP1PPS3
: 1;
4799 unsigned CCP1PPS4
: 1;
4807 unsigned CCP1PPS
: 5;
4812 extern __at(0x0E14) volatile __CCP1PPSbits_t CCP1PPSbits
;
4814 #define _CCP1PPS0 0x01
4815 #define _CCP1PPS1 0x02
4816 #define _CCP1PPS2 0x04
4817 #define _CCP1PPS3 0x08
4818 #define _CCP1PPS4 0x10
4820 //==============================================================================
4823 //==============================================================================
4826 extern __at(0x0E15) __sfr CCP2PPS
;
4832 unsigned CCP2PPS0
: 1;
4833 unsigned CCP2PPS1
: 1;
4834 unsigned CCP2PPS2
: 1;
4835 unsigned CCP2PPS3
: 1;
4836 unsigned CCP2PPS4
: 1;
4844 unsigned CCP2PPS
: 5;
4849 extern __at(0x0E15) volatile __CCP2PPSbits_t CCP2PPSbits
;
4851 #define _CCP2PPS0 0x01
4852 #define _CCP2PPS1 0x02
4853 #define _CCP2PPS2 0x04
4854 #define _CCP2PPS3 0x08
4855 #define _CCP2PPS4 0x10
4857 //==============================================================================
4860 //==============================================================================
4863 extern __at(0x0E18) __sfr CWG1PPS
;
4869 unsigned CWG1PPS0
: 1;
4870 unsigned CWG1PPS1
: 1;
4871 unsigned CWG1PPS2
: 1;
4872 unsigned CWG1PPS3
: 1;
4873 unsigned CWG1PPS4
: 1;
4881 unsigned CWG1PPS
: 5;
4886 extern __at(0x0E18) volatile __CWG1PPSbits_t CWG1PPSbits
;
4888 #define _CWG1PPS0 0x01
4889 #define _CWG1PPS1 0x02
4890 #define _CWG1PPS2 0x04
4891 #define _CWG1PPS3 0x08
4892 #define _CWG1PPS4 0x10
4894 //==============================================================================
4897 //==============================================================================
4900 extern __at(0x0E1A) __sfr MDCIN1PPS
;
4906 unsigned MDCIN1PPS0
: 1;
4907 unsigned MDCIN1PPS1
: 1;
4908 unsigned MDCIN1PPS2
: 1;
4909 unsigned MDCIN1PPS3
: 1;
4910 unsigned MDCIN1PPS4
: 1;
4918 unsigned MDCIN1PPS
: 5;
4921 } __MDCIN1PPSbits_t
;
4923 extern __at(0x0E1A) volatile __MDCIN1PPSbits_t MDCIN1PPSbits
;
4925 #define _MDCIN1PPS0 0x01
4926 #define _MDCIN1PPS1 0x02
4927 #define _MDCIN1PPS2 0x04
4928 #define _MDCIN1PPS3 0x08
4929 #define _MDCIN1PPS4 0x10
4931 //==============================================================================
4934 //==============================================================================
4937 extern __at(0x0E1B) __sfr MDCIN2PPS
;
4943 unsigned MDCIN2PPS0
: 1;
4944 unsigned MDCIN2PPS1
: 1;
4945 unsigned MDCIN2PPS2
: 1;
4946 unsigned MDCIN2PPS3
: 1;
4947 unsigned MDCIN2PPS4
: 1;
4955 unsigned MDCIN2PPS
: 5;
4958 } __MDCIN2PPSbits_t
;
4960 extern __at(0x0E1B) volatile __MDCIN2PPSbits_t MDCIN2PPSbits
;
4962 #define _MDCIN2PPS0 0x01
4963 #define _MDCIN2PPS1 0x02
4964 #define _MDCIN2PPS2 0x04
4965 #define _MDCIN2PPS3 0x08
4966 #define _MDCIN2PPS4 0x10
4968 //==============================================================================
4971 //==============================================================================
4974 extern __at(0x0E1C) __sfr MDMINPPS
;
4980 unsigned MDMINPPS0
: 1;
4981 unsigned MDMINPPS1
: 1;
4982 unsigned MDMINPPS2
: 1;
4983 unsigned MDMINPPS3
: 1;
4984 unsigned MDMINPPS4
: 1;
4992 unsigned MDMINPPS
: 5;
4997 extern __at(0x0E1C) volatile __MDMINPPSbits_t MDMINPPSbits
;
4999 #define _MDMINPPS0 0x01
5000 #define _MDMINPPS1 0x02
5001 #define _MDMINPPS2 0x04
5002 #define _MDMINPPS3 0x08
5003 #define _MDMINPPS4 0x10
5005 //==============================================================================
5008 //==============================================================================
5011 extern __at(0x0E20) __sfr SSP1CLKPPS
;
5017 unsigned SSP1CLKPPS0
: 1;
5018 unsigned SSP1CLKPPS1
: 1;
5019 unsigned SSP1CLKPPS2
: 1;
5020 unsigned SSP1CLKPPS3
: 1;
5021 unsigned SSP1CLKPPS4
: 1;
5029 unsigned SSP1CLKPPS
: 5;
5032 } __SSP1CLKPPSbits_t
;
5034 extern __at(0x0E20) volatile __SSP1CLKPPSbits_t SSP1CLKPPSbits
;
5036 #define _SSP1CLKPPS0 0x01
5037 #define _SSP1CLKPPS1 0x02
5038 #define _SSP1CLKPPS2 0x04
5039 #define _SSP1CLKPPS3 0x08
5040 #define _SSP1CLKPPS4 0x10
5042 //==============================================================================
5045 //==============================================================================
5048 extern __at(0x0E21) __sfr SSP1DATPPS
;
5054 unsigned SSP1DATPPS0
: 1;
5055 unsigned SSP1DATPPS1
: 1;
5056 unsigned SSP1DATPPS2
: 1;
5057 unsigned SSP1DATPPS3
: 1;
5058 unsigned SSP1DATPPS4
: 1;
5066 unsigned SSP1DATPPS
: 5;
5069 } __SSP1DATPPSbits_t
;
5071 extern __at(0x0E21) volatile __SSP1DATPPSbits_t SSP1DATPPSbits
;
5073 #define _SSP1DATPPS0 0x01
5074 #define _SSP1DATPPS1 0x02
5075 #define _SSP1DATPPS2 0x04
5076 #define _SSP1DATPPS3 0x08
5077 #define _SSP1DATPPS4 0x10
5079 //==============================================================================
5082 //==============================================================================
5085 extern __at(0x0E22) __sfr SSP1SSPPS
;
5091 unsigned SSP1SSPPS0
: 1;
5092 unsigned SSP1SSPPS1
: 1;
5093 unsigned SSP1SSPPS2
: 1;
5094 unsigned SSP1SSPPS3
: 1;
5095 unsigned SSP1SSPPS4
: 1;
5103 unsigned SSP1SSPPS
: 5;
5106 } __SSP1SSPPSbits_t
;
5108 extern __at(0x0E22) volatile __SSP1SSPPSbits_t SSP1SSPPSbits
;
5110 #define _SSP1SSPPS0 0x01
5111 #define _SSP1SSPPS1 0x02
5112 #define _SSP1SSPPS2 0x04
5113 #define _SSP1SSPPS3 0x08
5114 #define _SSP1SSPPS4 0x10
5116 //==============================================================================
5119 //==============================================================================
5122 extern __at(0x0E24) __sfr RXPPS
;
5128 unsigned RXPPS0
: 1;
5129 unsigned RXPPS1
: 1;
5130 unsigned RXPPS2
: 1;
5131 unsigned RXPPS3
: 1;
5132 unsigned RXPPS4
: 1;
5145 extern __at(0x0E24) volatile __RXPPSbits_t RXPPSbits
;
5147 #define _RXPPS0 0x01
5148 #define _RXPPS1 0x02
5149 #define _RXPPS2 0x04
5150 #define _RXPPS3 0x08
5151 #define _RXPPS4 0x10
5153 //==============================================================================
5156 //==============================================================================
5159 extern __at(0x0E25) __sfr TXPPS
;
5165 unsigned TXPPS0
: 1;
5166 unsigned TXPPS1
: 1;
5167 unsigned TXPPS2
: 1;
5168 unsigned TXPPS3
: 1;
5169 unsigned TXPPS4
: 1;
5182 extern __at(0x0E25) volatile __TXPPSbits_t TXPPSbits
;
5184 #define _TXPPS0 0x01
5185 #define _TXPPS1 0x02
5186 #define _TXPPS2 0x04
5187 #define _TXPPS3 0x08
5188 #define _TXPPS4 0x10
5190 //==============================================================================
5193 //==============================================================================
5196 extern __at(0x0E28) __sfr CLCIN0PPS
;
5202 unsigned CLCIN0PPS0
: 1;
5203 unsigned CLCIN0PPS1
: 1;
5204 unsigned CLCIN0PPS2
: 1;
5205 unsigned CLCIN0PPS3
: 1;
5206 unsigned CLCIN0PPS4
: 1;
5214 unsigned CLCIN0PPS
: 5;
5217 } __CLCIN0PPSbits_t
;
5219 extern __at(0x0E28) volatile __CLCIN0PPSbits_t CLCIN0PPSbits
;
5221 #define _CLCIN0PPS0 0x01
5222 #define _CLCIN0PPS1 0x02
5223 #define _CLCIN0PPS2 0x04
5224 #define _CLCIN0PPS3 0x08
5225 #define _CLCIN0PPS4 0x10
5227 //==============================================================================
5230 //==============================================================================
5233 extern __at(0x0E29) __sfr CLCIN1PPS
;
5239 unsigned CLCIN1PPS0
: 1;
5240 unsigned CLCIN1PPS1
: 1;
5241 unsigned CLCIN1PPS2
: 1;
5242 unsigned CLCIN1PPS3
: 1;
5243 unsigned CLCIN1PPS4
: 1;
5251 unsigned CLCIN1PPS
: 5;
5254 } __CLCIN1PPSbits_t
;
5256 extern __at(0x0E29) volatile __CLCIN1PPSbits_t CLCIN1PPSbits
;
5258 #define _CLCIN1PPS0 0x01
5259 #define _CLCIN1PPS1 0x02
5260 #define _CLCIN1PPS2 0x04
5261 #define _CLCIN1PPS3 0x08
5262 #define _CLCIN1PPS4 0x10
5264 //==============================================================================
5267 //==============================================================================
5270 extern __at(0x0E2A) __sfr CLCIN2PPS
;
5276 unsigned CLCIN2PPS0
: 1;
5277 unsigned CLCIN2PPS1
: 1;
5278 unsigned CLCIN2PPS2
: 1;
5279 unsigned CLCIN2PPS3
: 1;
5280 unsigned CLCIN2PPS4
: 1;
5288 unsigned CLCIN2PPS
: 5;
5291 } __CLCIN2PPSbits_t
;
5293 extern __at(0x0E2A) volatile __CLCIN2PPSbits_t CLCIN2PPSbits
;
5295 #define _CLCIN2PPS0 0x01
5296 #define _CLCIN2PPS1 0x02
5297 #define _CLCIN2PPS2 0x04
5298 #define _CLCIN2PPS3 0x08
5299 #define _CLCIN2PPS4 0x10
5301 //==============================================================================
5304 //==============================================================================
5307 extern __at(0x0E2B) __sfr CLCIN3PPS
;
5313 unsigned CLCIN3PPS0
: 1;
5314 unsigned CLCIN3PPS1
: 1;
5315 unsigned CLCIN3PPS2
: 1;
5316 unsigned CLCIN3PPS3
: 1;
5317 unsigned CLCIN3PPS4
: 1;
5325 unsigned CLCIN3PPS
: 5;
5328 } __CLCIN3PPSbits_t
;
5330 extern __at(0x0E2B) volatile __CLCIN3PPSbits_t CLCIN3PPSbits
;
5332 #define _CLCIN3PPS0 0x01
5333 #define _CLCIN3PPS1 0x02
5334 #define _CLCIN3PPS2 0x04
5335 #define _CLCIN3PPS3 0x08
5336 #define _CLCIN3PPS4 0x10
5338 //==============================================================================
5341 //==============================================================================
5344 extern __at(0x0E90) __sfr RA0PPS
;
5350 unsigned RA0PPS0
: 1;
5351 unsigned RA0PPS1
: 1;
5352 unsigned RA0PPS2
: 1;
5353 unsigned RA0PPS3
: 1;
5354 unsigned RA0PPS4
: 1;
5362 unsigned RA0PPS
: 5;
5367 extern __at(0x0E90) volatile __RA0PPSbits_t RA0PPSbits
;
5369 #define _RA0PPS0 0x01
5370 #define _RA0PPS1 0x02
5371 #define _RA0PPS2 0x04
5372 #define _RA0PPS3 0x08
5373 #define _RA0PPS4 0x10
5375 //==============================================================================
5378 //==============================================================================
5381 extern __at(0x0E91) __sfr RA1PPS
;
5387 unsigned RA1PPS0
: 1;
5388 unsigned RA1PPS1
: 1;
5389 unsigned RA1PPS2
: 1;
5390 unsigned RA1PPS3
: 1;
5391 unsigned RA1PPS4
: 1;
5399 unsigned RA1PPS
: 5;
5404 extern __at(0x0E91) volatile __RA1PPSbits_t RA1PPSbits
;
5406 #define _RA1PPS0 0x01
5407 #define _RA1PPS1 0x02
5408 #define _RA1PPS2 0x04
5409 #define _RA1PPS3 0x08
5410 #define _RA1PPS4 0x10
5412 //==============================================================================
5415 //==============================================================================
5418 extern __at(0x0E92) __sfr RA2PPS
;
5424 unsigned RA2PPS0
: 1;
5425 unsigned RA2PPS1
: 1;
5426 unsigned RA2PPS2
: 1;
5427 unsigned RA2PPS3
: 1;
5428 unsigned RA2PPS4
: 1;
5436 unsigned RA2PPS
: 5;
5441 extern __at(0x0E92) volatile __RA2PPSbits_t RA2PPSbits
;
5443 #define _RA2PPS0 0x01
5444 #define _RA2PPS1 0x02
5445 #define _RA2PPS2 0x04
5446 #define _RA2PPS3 0x08
5447 #define _RA2PPS4 0x10
5449 //==============================================================================
5452 //==============================================================================
5455 extern __at(0x0E94) __sfr RA4PPS
;
5461 unsigned RA4PPS0
: 1;
5462 unsigned RA4PPS1
: 1;
5463 unsigned RA4PPS2
: 1;
5464 unsigned RA4PPS3
: 1;
5465 unsigned RA4PPS4
: 1;
5473 unsigned RA4PPS
: 5;
5478 extern __at(0x0E94) volatile __RA4PPSbits_t RA4PPSbits
;
5480 #define _RA4PPS0 0x01
5481 #define _RA4PPS1 0x02
5482 #define _RA4PPS2 0x04
5483 #define _RA4PPS3 0x08
5484 #define _RA4PPS4 0x10
5486 //==============================================================================
5489 //==============================================================================
5492 extern __at(0x0E95) __sfr RA5PPS
;
5498 unsigned RA5PPS0
: 1;
5499 unsigned RA5PPS1
: 1;
5500 unsigned RA5PPS2
: 1;
5501 unsigned RA5PPS3
: 1;
5502 unsigned RA5PPS4
: 1;
5510 unsigned RA5PPS
: 5;
5515 extern __at(0x0E95) volatile __RA5PPSbits_t RA5PPSbits
;
5517 #define _RA5PPS0 0x01
5518 #define _RA5PPS1 0x02
5519 #define _RA5PPS2 0x04
5520 #define _RA5PPS3 0x08
5521 #define _RA5PPS4 0x10
5523 //==============================================================================
5526 //==============================================================================
5529 extern __at(0x0F0F) __sfr CLCDATA
;
5533 unsigned MLC1OUT
: 1;
5534 unsigned MLC2OUT
: 1;
5543 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
5545 #define _MLC1OUT 0x01
5546 #define _MLC2OUT 0x02
5548 //==============================================================================
5551 //==============================================================================
5554 extern __at(0x0F10) __sfr CLC1CON
;
5560 unsigned LC1MODE0
: 1;
5561 unsigned LC1MODE1
: 1;
5562 unsigned LC1MODE2
: 1;
5563 unsigned LC1INTN
: 1;
5564 unsigned LC1INTP
: 1;
5565 unsigned LC1OUT
: 1;
5590 unsigned LC1MODE
: 3;
5595 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
5597 #define _LC1MODE0 0x01
5599 #define _LC1MODE1 0x02
5601 #define _LC1MODE2 0x04
5603 #define _LC1INTN 0x08
5605 #define _LC1INTP 0x10
5607 #define _LC1OUT 0x20
5612 //==============================================================================
5615 //==============================================================================
5618 extern __at(0x0F11) __sfr CLC1POL
;
5624 unsigned LC1G1POL
: 1;
5625 unsigned LC1G2POL
: 1;
5626 unsigned LC1G3POL
: 1;
5627 unsigned LC1G4POL
: 1;
5631 unsigned LC1POL
: 1;
5647 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
5649 #define _LC1G1POL 0x01
5651 #define _LC1G2POL 0x02
5653 #define _LC1G3POL 0x04
5655 #define _LC1G4POL 0x08
5657 #define _LC1POL 0x80
5660 //==============================================================================
5663 //==============================================================================
5666 extern __at(0x0F12) __sfr CLC1SEL0
;
5672 unsigned LC1D1S0
: 1;
5673 unsigned LC1D1S1
: 1;
5674 unsigned LC1D1S2
: 1;
5675 unsigned LC1D1S3
: 1;
5676 unsigned LC1D1S4
: 1;
5696 unsigned LC1D1S
: 5;
5707 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
5709 #define _LC1D1S0 0x01
5711 #define _LC1D1S1 0x02
5713 #define _LC1D1S2 0x04
5715 #define _LC1D1S3 0x08
5717 #define _LC1D1S4 0x10
5720 //==============================================================================
5723 //==============================================================================
5726 extern __at(0x0F13) __sfr CLC1SEL1
;
5732 unsigned LC1D2S0
: 1;
5733 unsigned LC1D2S1
: 1;
5734 unsigned LC1D2S2
: 1;
5735 unsigned LC1D2S3
: 1;
5736 unsigned LC1D2S4
: 1;
5762 unsigned LC1D2S
: 5;
5767 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
5769 #define _LC1D2S0 0x01
5771 #define _LC1D2S1 0x02
5773 #define _LC1D2S2 0x04
5775 #define _LC1D2S3 0x08
5777 #define _LC1D2S4 0x10
5780 //==============================================================================
5783 //==============================================================================
5786 extern __at(0x0F14) __sfr CLC1SEL2
;
5792 unsigned LC1D3S0
: 1;
5793 unsigned LC1D3S1
: 1;
5794 unsigned LC1D3S2
: 1;
5795 unsigned LC1D3S3
: 1;
5796 unsigned LC1D3S4
: 1;
5816 unsigned LC1D3S
: 5;
5827 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
5829 #define _LC1D3S0 0x01
5831 #define _LC1D3S1 0x02
5833 #define _LC1D3S2 0x04
5835 #define _LC1D3S3 0x08
5837 #define _LC1D3S4 0x10
5840 //==============================================================================
5843 //==============================================================================
5846 extern __at(0x0F15) __sfr CLC1SEL3
;
5852 unsigned LC1D4S0
: 1;
5853 unsigned LC1D4S1
: 1;
5854 unsigned LC1D4S2
: 1;
5855 unsigned LC1D4S3
: 1;
5856 unsigned LC1D4S4
: 1;
5882 unsigned LC1D4S
: 5;
5887 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
5889 #define _LC1D4S0 0x01
5891 #define _LC1D4S1 0x02
5893 #define _LC1D4S2 0x04
5895 #define _LC1D4S3 0x08
5897 #define _LC1D4S4 0x10
5900 //==============================================================================
5903 //==============================================================================
5906 extern __at(0x0F16) __sfr CLC1GLS0
;
5912 unsigned LC1G1D1N
: 1;
5913 unsigned LC1G1D1T
: 1;
5914 unsigned LC1G1D2N
: 1;
5915 unsigned LC1G1D2T
: 1;
5916 unsigned LC1G1D3N
: 1;
5917 unsigned LC1G1D3T
: 1;
5918 unsigned LC1G1D4N
: 1;
5919 unsigned LC1G1D4T
: 1;
5935 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
5937 #define _LC1G1D1N 0x01
5939 #define _LC1G1D1T 0x02
5941 #define _LC1G1D2N 0x04
5943 #define _LC1G1D2T 0x08
5945 #define _LC1G1D3N 0x10
5947 #define _LC1G1D3T 0x20
5949 #define _LC1G1D4N 0x40
5951 #define _LC1G1D4T 0x80
5954 //==============================================================================
5957 //==============================================================================
5960 extern __at(0x0F17) __sfr CLC1GLS1
;
5966 unsigned LC1G2D1N
: 1;
5967 unsigned LC1G2D1T
: 1;
5968 unsigned LC1G2D2N
: 1;
5969 unsigned LC1G2D2T
: 1;
5970 unsigned LC1G2D3N
: 1;
5971 unsigned LC1G2D3T
: 1;
5972 unsigned LC1G2D4N
: 1;
5973 unsigned LC1G2D4T
: 1;
5989 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
5991 #define _CLC1GLS1_LC1G2D1N 0x01
5992 #define _CLC1GLS1_D1N 0x01
5993 #define _CLC1GLS1_LC1G2D1T 0x02
5994 #define _CLC1GLS1_D1T 0x02
5995 #define _CLC1GLS1_LC1G2D2N 0x04
5996 #define _CLC1GLS1_D2N 0x04
5997 #define _CLC1GLS1_LC1G2D2T 0x08
5998 #define _CLC1GLS1_D2T 0x08
5999 #define _CLC1GLS1_LC1G2D3N 0x10
6000 #define _CLC1GLS1_D3N 0x10
6001 #define _CLC1GLS1_LC1G2D3T 0x20
6002 #define _CLC1GLS1_D3T 0x20
6003 #define _CLC1GLS1_LC1G2D4N 0x40
6004 #define _CLC1GLS1_D4N 0x40
6005 #define _CLC1GLS1_LC1G2D4T 0x80
6006 #define _CLC1GLS1_D4T 0x80
6008 //==============================================================================
6011 //==============================================================================
6014 extern __at(0x0F18) __sfr CLC1GLS2
;
6020 unsigned LC1G3D1N
: 1;
6021 unsigned LC1G3D1T
: 1;
6022 unsigned LC1G3D2N
: 1;
6023 unsigned LC1G3D2T
: 1;
6024 unsigned LC1G3D3N
: 1;
6025 unsigned LC1G3D3T
: 1;
6026 unsigned LC1G3D4N
: 1;
6027 unsigned LC1G3D4T
: 1;
6043 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
6045 #define _CLC1GLS2_LC1G3D1N 0x01
6046 #define _CLC1GLS2_D1N 0x01
6047 #define _CLC1GLS2_LC1G3D1T 0x02
6048 #define _CLC1GLS2_D1T 0x02
6049 #define _CLC1GLS2_LC1G3D2N 0x04
6050 #define _CLC1GLS2_D2N 0x04
6051 #define _CLC1GLS2_LC1G3D2T 0x08
6052 #define _CLC1GLS2_D2T 0x08
6053 #define _CLC1GLS2_LC1G3D3N 0x10
6054 #define _CLC1GLS2_D3N 0x10
6055 #define _CLC1GLS2_LC1G3D3T 0x20
6056 #define _CLC1GLS2_D3T 0x20
6057 #define _CLC1GLS2_LC1G3D4N 0x40
6058 #define _CLC1GLS2_D4N 0x40
6059 #define _CLC1GLS2_LC1G3D4T 0x80
6060 #define _CLC1GLS2_D4T 0x80
6062 //==============================================================================
6065 //==============================================================================
6068 extern __at(0x0F19) __sfr CLC1GLS3
;
6074 unsigned LC1G4D1N
: 1;
6075 unsigned LC1G4D1T
: 1;
6076 unsigned LC1G4D2N
: 1;
6077 unsigned LC1G4D2T
: 1;
6078 unsigned LC1G4D3N
: 1;
6079 unsigned LC1G4D3T
: 1;
6080 unsigned LC1G4D4N
: 1;
6081 unsigned LC1G4D4T
: 1;
6097 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
6099 #define _LC1G4D1N 0x01
6101 #define _LC1G4D1T 0x02
6103 #define _LC1G4D2N 0x04
6105 #define _LC1G4D2T 0x08
6107 #define _LC1G4D3N 0x10
6109 #define _LC1G4D3T 0x20
6111 #define _LC1G4D4N 0x40
6113 #define _LC1G4D4T 0x80
6116 //==============================================================================
6119 //==============================================================================
6122 extern __at(0x0F1A) __sfr CLC2CON
;
6128 unsigned LC2MODE0
: 1;
6129 unsigned LC2MODE1
: 1;
6130 unsigned LC2MODE2
: 1;
6131 unsigned LC2INTN
: 1;
6132 unsigned LC2INTP
: 1;
6133 unsigned LC2OUT
: 1;
6152 unsigned LC2MODE
: 3;
6163 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
6165 #define _CLC2CON_LC2MODE0 0x01
6166 #define _CLC2CON_MODE0 0x01
6167 #define _CLC2CON_LC2MODE1 0x02
6168 #define _CLC2CON_MODE1 0x02
6169 #define _CLC2CON_LC2MODE2 0x04
6170 #define _CLC2CON_MODE2 0x04
6171 #define _CLC2CON_LC2INTN 0x08
6172 #define _CLC2CON_INTN 0x08
6173 #define _CLC2CON_LC2INTP 0x10
6174 #define _CLC2CON_INTP 0x10
6175 #define _CLC2CON_LC2OUT 0x20
6176 #define _CLC2CON_OUT 0x20
6177 #define _CLC2CON_LC2EN 0x80
6178 #define _CLC2CON_EN 0x80
6180 //==============================================================================
6183 //==============================================================================
6186 extern __at(0x0F1B) __sfr CLC2POL
;
6192 unsigned LC2G1POL
: 1;
6193 unsigned LC2G2POL
: 1;
6194 unsigned LC2G3POL
: 1;
6195 unsigned LC2G4POL
: 1;
6199 unsigned LC2POL
: 1;
6215 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
6217 #define _CLC2POL_LC2G1POL 0x01
6218 #define _CLC2POL_G1POL 0x01
6219 #define _CLC2POL_LC2G2POL 0x02
6220 #define _CLC2POL_G2POL 0x02
6221 #define _CLC2POL_LC2G3POL 0x04
6222 #define _CLC2POL_G3POL 0x04
6223 #define _CLC2POL_LC2G4POL 0x08
6224 #define _CLC2POL_G4POL 0x08
6225 #define _CLC2POL_LC2POL 0x80
6226 #define _CLC2POL_POL 0x80
6228 //==============================================================================
6231 //==============================================================================
6234 extern __at(0x0F1C) __sfr CLC2SEL0
;
6240 unsigned LC2D1S0
: 1;
6241 unsigned LC2D1S1
: 1;
6242 unsigned LC2D1S2
: 1;
6243 unsigned LC2D1S3
: 1;
6244 unsigned LC2D1S4
: 1;
6270 unsigned LC2D1S
: 5;
6275 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
6277 #define _CLC2SEL0_LC2D1S0 0x01
6278 #define _CLC2SEL0_D1S0 0x01
6279 #define _CLC2SEL0_LC2D1S1 0x02
6280 #define _CLC2SEL0_D1S1 0x02
6281 #define _CLC2SEL0_LC2D1S2 0x04
6282 #define _CLC2SEL0_D1S2 0x04
6283 #define _CLC2SEL0_LC2D1S3 0x08
6284 #define _CLC2SEL0_D1S3 0x08
6285 #define _CLC2SEL0_LC2D1S4 0x10
6286 #define _CLC2SEL0_D1S4 0x10
6288 //==============================================================================
6291 //==============================================================================
6294 extern __at(0x0F1D) __sfr CLC2SEL1
;
6300 unsigned LC2D2S0
: 1;
6301 unsigned LC2D2S1
: 1;
6302 unsigned LC2D2S2
: 1;
6303 unsigned LC2D2S3
: 1;
6304 unsigned LC2D2S4
: 1;
6324 unsigned LC2D2S
: 5;
6335 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
6337 #define _CLC2SEL1_LC2D2S0 0x01
6338 #define _CLC2SEL1_D2S0 0x01
6339 #define _CLC2SEL1_LC2D2S1 0x02
6340 #define _CLC2SEL1_D2S1 0x02
6341 #define _CLC2SEL1_LC2D2S2 0x04
6342 #define _CLC2SEL1_D2S2 0x04
6343 #define _CLC2SEL1_LC2D2S3 0x08
6344 #define _CLC2SEL1_D2S3 0x08
6345 #define _CLC2SEL1_LC2D2S4 0x10
6346 #define _CLC2SEL1_D2S4 0x10
6348 //==============================================================================
6351 //==============================================================================
6354 extern __at(0x0F1E) __sfr CLC2SEL2
;
6360 unsigned LC2D3S0
: 1;
6361 unsigned LC2D3S1
: 1;
6362 unsigned LC2D3S2
: 1;
6363 unsigned LC2D3S3
: 1;
6364 unsigned LC2D3S4
: 1;
6384 unsigned LC2D3S
: 5;
6395 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
6397 #define _CLC2SEL2_LC2D3S0 0x01
6398 #define _CLC2SEL2_D3S0 0x01
6399 #define _CLC2SEL2_LC2D3S1 0x02
6400 #define _CLC2SEL2_D3S1 0x02
6401 #define _CLC2SEL2_LC2D3S2 0x04
6402 #define _CLC2SEL2_D3S2 0x04
6403 #define _CLC2SEL2_LC2D3S3 0x08
6404 #define _CLC2SEL2_D3S3 0x08
6405 #define _CLC2SEL2_LC2D3S4 0x10
6406 #define _CLC2SEL2_D3S4 0x10
6408 //==============================================================================
6411 //==============================================================================
6414 extern __at(0x0F1F) __sfr CLC2SEL3
;
6420 unsigned LC2D4S0
: 1;
6421 unsigned LC2D4S1
: 1;
6422 unsigned LC2D4S2
: 1;
6423 unsigned LC2D4S3
: 1;
6424 unsigned LC2D4S4
: 1;
6444 unsigned LC2D4S
: 5;
6455 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
6457 #define _CLC2SEL3_LC2D4S0 0x01
6458 #define _CLC2SEL3_D4S0 0x01
6459 #define _CLC2SEL3_LC2D4S1 0x02
6460 #define _CLC2SEL3_D4S1 0x02
6461 #define _CLC2SEL3_LC2D4S2 0x04
6462 #define _CLC2SEL3_D4S2 0x04
6463 #define _CLC2SEL3_LC2D4S3 0x08
6464 #define _CLC2SEL3_D4S3 0x08
6465 #define _CLC2SEL3_LC2D4S4 0x10
6466 #define _CLC2SEL3_D4S4 0x10
6468 //==============================================================================
6471 //==============================================================================
6474 extern __at(0x0F20) __sfr CLC2GLS0
;
6480 unsigned LC2G1D1N
: 1;
6481 unsigned LC2G1D1T
: 1;
6482 unsigned LC2G1D2N
: 1;
6483 unsigned LC2G1D2T
: 1;
6484 unsigned LC2G1D3N
: 1;
6485 unsigned LC2G1D3T
: 1;
6486 unsigned LC2G1D4N
: 1;
6487 unsigned LC2G1D4T
: 1;
6503 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
6505 #define _CLC2GLS0_LC2G1D1N 0x01
6506 #define _CLC2GLS0_D1N 0x01
6507 #define _CLC2GLS0_LC2G1D1T 0x02
6508 #define _CLC2GLS0_D1T 0x02
6509 #define _CLC2GLS0_LC2G1D2N 0x04
6510 #define _CLC2GLS0_D2N 0x04
6511 #define _CLC2GLS0_LC2G1D2T 0x08
6512 #define _CLC2GLS0_D2T 0x08
6513 #define _CLC2GLS0_LC2G1D3N 0x10
6514 #define _CLC2GLS0_D3N 0x10
6515 #define _CLC2GLS0_LC2G1D3T 0x20
6516 #define _CLC2GLS0_D3T 0x20
6517 #define _CLC2GLS0_LC2G1D4N 0x40
6518 #define _CLC2GLS0_D4N 0x40
6519 #define _CLC2GLS0_LC2G1D4T 0x80
6520 #define _CLC2GLS0_D4T 0x80
6522 //==============================================================================
6525 //==============================================================================
6528 extern __at(0x0F21) __sfr CLC2GLS1
;
6534 unsigned LC2G2D1N
: 1;
6535 unsigned LC2G2D1T
: 1;
6536 unsigned LC2G2D2N
: 1;
6537 unsigned LC2G2D2T
: 1;
6538 unsigned LC2G2D3N
: 1;
6539 unsigned LC2G2D3T
: 1;
6540 unsigned LC2G2D4N
: 1;
6541 unsigned LC2G2D4T
: 1;
6557 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
6559 #define _CLC2GLS1_LC2G2D1N 0x01
6560 #define _CLC2GLS1_D1N 0x01
6561 #define _CLC2GLS1_LC2G2D1T 0x02
6562 #define _CLC2GLS1_D1T 0x02
6563 #define _CLC2GLS1_LC2G2D2N 0x04
6564 #define _CLC2GLS1_D2N 0x04
6565 #define _CLC2GLS1_LC2G2D2T 0x08
6566 #define _CLC2GLS1_D2T 0x08
6567 #define _CLC2GLS1_LC2G2D3N 0x10
6568 #define _CLC2GLS1_D3N 0x10
6569 #define _CLC2GLS1_LC2G2D3T 0x20
6570 #define _CLC2GLS1_D3T 0x20
6571 #define _CLC2GLS1_LC2G2D4N 0x40
6572 #define _CLC2GLS1_D4N 0x40
6573 #define _CLC2GLS1_LC2G2D4T 0x80
6574 #define _CLC2GLS1_D4T 0x80
6576 //==============================================================================
6579 //==============================================================================
6582 extern __at(0x0F22) __sfr CLC2GLS2
;
6588 unsigned LC2G3D1N
: 1;
6589 unsigned LC2G3D1T
: 1;
6590 unsigned LC2G3D2N
: 1;
6591 unsigned LC2G3D2T
: 1;
6592 unsigned LC2G3D3N
: 1;
6593 unsigned LC2G3D3T
: 1;
6594 unsigned LC2G3D4N
: 1;
6595 unsigned LC2G3D4T
: 1;
6611 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
6613 #define _CLC2GLS2_LC2G3D1N 0x01
6614 #define _CLC2GLS2_D1N 0x01
6615 #define _CLC2GLS2_LC2G3D1T 0x02
6616 #define _CLC2GLS2_D1T 0x02
6617 #define _CLC2GLS2_LC2G3D2N 0x04
6618 #define _CLC2GLS2_D2N 0x04
6619 #define _CLC2GLS2_LC2G3D2T 0x08
6620 #define _CLC2GLS2_D2T 0x08
6621 #define _CLC2GLS2_LC2G3D3N 0x10
6622 #define _CLC2GLS2_D3N 0x10
6623 #define _CLC2GLS2_LC2G3D3T 0x20
6624 #define _CLC2GLS2_D3T 0x20
6625 #define _CLC2GLS2_LC2G3D4N 0x40
6626 #define _CLC2GLS2_D4N 0x40
6627 #define _CLC2GLS2_LC2G3D4T 0x80
6628 #define _CLC2GLS2_D4T 0x80
6630 //==============================================================================
6633 //==============================================================================
6636 extern __at(0x0F23) __sfr CLC2GLS3
;
6642 unsigned LC2G4D1N
: 1;
6643 unsigned LC2G4D1T
: 1;
6644 unsigned LC2G4D2N
: 1;
6645 unsigned LC2G4D2T
: 1;
6646 unsigned LC2G4D3N
: 1;
6647 unsigned LC2G4D3T
: 1;
6648 unsigned LC2G4D4N
: 1;
6649 unsigned LC2G4D4T
: 1;
6665 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
6667 #define _CLC2GLS3_LC2G4D1N 0x01
6668 #define _CLC2GLS3_G4D1N 0x01
6669 #define _CLC2GLS3_LC2G4D1T 0x02
6670 #define _CLC2GLS3_G4D1T 0x02
6671 #define _CLC2GLS3_LC2G4D2N 0x04
6672 #define _CLC2GLS3_G4D2N 0x04
6673 #define _CLC2GLS3_LC2G4D2T 0x08
6674 #define _CLC2GLS3_G4D2T 0x08
6675 #define _CLC2GLS3_LC2G4D3N 0x10
6676 #define _CLC2GLS3_G4D3N 0x10
6677 #define _CLC2GLS3_LC2G4D3T 0x20
6678 #define _CLC2GLS3_G4D3T 0x20
6679 #define _CLC2GLS3_LC2G4D4N 0x40
6680 #define _CLC2GLS3_G4D4N 0x40
6681 #define _CLC2GLS3_LC2G4D4T 0x80
6682 #define _CLC2GLS3_G4D4T 0x80
6684 //==============================================================================
6687 //==============================================================================
6690 extern __at(0x0FE4) __sfr STATUS_SHAD
;
6694 unsigned C_SHAD
: 1;
6695 unsigned DC_SHAD
: 1;
6696 unsigned Z_SHAD
: 1;
6702 } __STATUS_SHADbits_t
;
6704 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
6706 #define _C_SHAD 0x01
6707 #define _DC_SHAD 0x02
6708 #define _Z_SHAD 0x04
6710 //==============================================================================
6712 extern __at(0x0FE5) __sfr WREG_SHAD
;
6713 extern __at(0x0FE6) __sfr BSR_SHAD
;
6714 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
6715 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
6716 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
6717 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
6718 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
6719 extern __at(0x0FED) __sfr STKPTR
;
6720 extern __at(0x0FEE) __sfr TOSL
;
6721 extern __at(0x0FEF) __sfr TOSH
;
6723 //==============================================================================
6725 // Configuration Bits
6727 //==============================================================================
6729 #define _CONFIG1 0x8007
6730 #define _CONFIG2 0x8008
6731 #define _CONFIG3 0x8009
6732 #define _CONFIG4 0x800A
6734 //----------------------------- CONFIG1 Options -------------------------------
6736 #define _FEXTOSC_LP 0x3FF8 // LP (crystal oscillator) optimized for 32.768 kHz.
6737 #define _FEXTOSC_XT 0x3FF9 // XT (crystal oscillator) from 100 kHz to 4 MHz.
6738 #define _FEXTOSC_HS 0x3FFA // HS (crystal oscillator) above 4 MHz.
6739 #define _FEXTOSC_OFF 0x3FFC // Oscillator not enabled.
6740 #define _FEXTOSC_ECL 0x3FFD // EC (external clock) below 100 kHz.
6741 #define _FEXTOSC_ECM 0x3FFE // EC (external clock) for 100 kHz to 8 MHz.
6742 #define _FEXTOSC_ECH 0x3FFF // EC (external clock) above 8 MHz.
6743 #define _RSTOSC_HFINT32 0x3F8F // HFINTOSC with 2x PLL (32MHz).
6744 #define _RSTOSC_EXT4X 0x3F9F // EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits.
6745 #define _RSTOSC_SOSC 0x3FBF // SOSC (31kHz).
6746 #define _RSTOSC_LFINT 0x3FCF // LFINTOSC (31kHz).
6747 #define _RSTOSC_HFINT1 0x3FEF // HFINTOSC (1MHz).
6748 #define _RSTOSC_EXT1X 0x3FFF // EXTOSC operating per FEXTOSC bits.
6749 #define _CLKOUTEN_ON 0x3EFF // CLKOUT function is enabled; FOSC/4 clock appears at OSC2.
6750 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled; I/O or oscillator function on OSC2.
6751 #define _CSWEN_OFF 0x37FF // The NOSC and NDIV bits cannot be changed by user software.
6752 #define _CSWEN_ON 0x3FFF // Writing to NOSC and NDIV is allowed.
6753 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
6754 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
6756 //----------------------------- CONFIG2 Options -------------------------------
6758 #define _MCLRE_OFF 0x3FFE // MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of port pin's WPU control bit.
6759 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR; Weak pull-up enabled.
6760 #define _PWRTE_ON 0x3FFD // PWRT enabled.
6761 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
6762 #define _WDTE_OFF 0x3FF3 // WDT disabled; SWDTEN is ignored.
6763 #define _WDTE_SWDTEN 0x3FF7 // WDT controlled by the SWDTEN bit in the WDTCON register.
6764 #define _WDTE_SLEEP 0x3FFB // WDT enabled while running and disabled while in SLEEP/IDLE; SWDTEN is ignored.
6765 #define _WDTE_ON 0x3FFF // WDT enabled, SWDTEN is ignored.
6766 #define _LPBOREN_ON 0x3FDF // ULPBOR enabled.
6767 #define _LPBOREN_OFF 0x3FFF // ULPBOR disabled.
6768 #define _BOREN_OFF 0x3F3F // Brown-out Reset disabled.
6769 #define _BOREN_SBOREN 0x3F7F // Brown-out Reset enabled according to SBOREN.
6770 #define _BOREN_SLEEP 0x3FBF // Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored.
6771 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled, SBOREN bit ignored.
6772 #define _BORV_HIGH 0x3DFF // Brown-out voltage (Vbor) set to 2.7V.
6773 #define _BORV_LOW 0x3FFF // Brown-out voltage (Vbor) set to 2.45V.
6774 #define _PPS1WAY_OFF 0x37FF // The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence).
6775 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle.
6776 #define _STVREN_OFF 0x2FFF // Stack Overflow or Underflow will not cause a Reset.
6777 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
6778 #define _DEBUG_ON 0x1FFF // Background debugger enabled.
6779 #define _DEBUG_OFF 0x3FFF // Background debugger disabled.
6781 //----------------------------- CONFIG3 Options -------------------------------
6783 #define _WRT_ALL 0x3FFC // 0000h to 07FFh write protected, no addresses may be modified.
6784 #define _WRT_HALF 0x3FFD // 0000h to 03FFh write-protected, 0400h to 07FFh may be modified.
6785 #define _WRT_BOOT 0x3FFE // 0000h to 01FFh write-protected, 0200h to 07FFh may be modified.
6786 #define _WRT_OFF 0x3FFF // Write protection off.
6787 #define _LVP_OFF 0x1FFF // HV on MCLR/VPP must be used for programming.
6788 #define _LVP_ON 0x3FFF // Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.
6790 //----------------------------- CONFIG4 Options -------------------------------
6792 #define _CP_ON 0x3FFE // User NVM code protection enabled.
6793 #define _CP_OFF 0x3FFF // User NVM code protection disabled.
6794 #define _CPD_ON 0x3FFD // Data NVM code protection enabled.
6795 #define _CPD_OFF 0x3FFF // Data NVM code protection disabled.
6797 //==============================================================================
6799 #define _DEVID1 0x8006
6801 #define _IDLOC0 0x8000
6802 #define _IDLOC1 0x8001
6803 #define _IDLOC2 0x8002
6804 #define _IDLOC3 0x8003
6806 //==============================================================================
6808 #ifndef NO_BIT_DEFINES
6810 #define ADACT0 ADACTbits.ADACT0 // bit 0
6811 #define ADACT1 ADACTbits.ADACT1 // bit 1
6812 #define ADACT2 ADACTbits.ADACT2 // bit 2
6813 #define ADACT3 ADACTbits.ADACT3 // bit 3
6815 #define ADON ADCON0bits.ADON // bit 0
6816 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
6817 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
6818 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
6819 #define CHS0 ADCON0bits.CHS0 // bit 2
6820 #define CHS1 ADCON0bits.CHS1 // bit 3
6821 #define CHS2 ADCON0bits.CHS2 // bit 4
6822 #define CHS3 ADCON0bits.CHS3 // bit 5
6823 #define CHS4 ADCON0bits.CHS4 // bit 6
6824 #define CHS5 ADCON0bits.CHS5 // bit 7
6826 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
6827 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
6828 #define ADNREF ADCON1bits.ADNREF // bit 2
6829 #define ADCS0 ADCON1bits.ADCS0 // bit 4
6830 #define ADCS1 ADCON1bits.ADCS1 // bit 5
6831 #define ADCS2 ADCON1bits.ADCS2 // bit 6
6832 #define ADFM ADCON1bits.ADFM // bit 7
6834 #define ANSA0 ANSELAbits.ANSA0 // bit 0
6835 #define ANSA1 ANSELAbits.ANSA1 // bit 1
6836 #define ANSA2 ANSELAbits.ANSA2 // bit 2
6837 #define ANSA4 ANSELAbits.ANSA4 // bit 4
6838 #define ANSA5 ANSELAbits.ANSA5 // bit 5
6840 #define ABDEN BAUD1CONbits.ABDEN // bit 0
6841 #define WUE BAUD1CONbits.WUE // bit 1
6842 #define BRG16 BAUD1CONbits.BRG16 // bit 3
6843 #define SCKP BAUD1CONbits.SCKP // bit 4
6844 #define RCIDL BAUD1CONbits.RCIDL // bit 6
6845 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
6847 #define BORRDY BORCONbits.BORRDY // bit 0
6848 #define SBOREN BORCONbits.SBOREN // bit 7
6850 #define BSR0 BSRbits.BSR0 // bit 0
6851 #define BSR1 BSRbits.BSR1 // bit 1
6852 #define BSR2 BSRbits.BSR2 // bit 2
6853 #define BSR3 BSRbits.BSR3 // bit 3
6854 #define BSR4 BSRbits.BSR4 // bit 4
6856 #define CCDS0 CCDCONbits.CCDS0 // bit 0
6857 #define CCDS1 CCDCONbits.CCDS1 // bit 1
6858 #define CCDEN CCDCONbits.CCDEN // bit 7
6860 #define CCDNA0 CCDNAbits.CCDNA0 // bit 0
6861 #define CCDNA1 CCDNAbits.CCDNA1 // bit 1
6862 #define CCDNA2 CCDNAbits.CCDNA2 // bit 2
6863 #define CCDNA4 CCDNAbits.CCDNA4 // bit 4
6864 #define CCDNA5 CCDNAbits.CCDNA5 // bit 5
6866 #define CCDPA0 CCDPAbits.CCDPA0 // bit 0
6867 #define CCDPA1 CCDPAbits.CCDPA1 // bit 1
6868 #define CCDPA2 CCDPAbits.CCDPA2 // bit 2
6869 #define CCDPA4 CCDPAbits.CCDPA4 // bit 4
6870 #define CCDPA5 CCDPAbits.CCDPA5 // bit 5
6872 #define CCP1CTS0 CCP1CAPbits.CCP1CTS0 // bit 0
6873 #define CCP1CTS1 CCP1CAPbits.CCP1CTS1 // bit 1
6874 #define CCP1CTS2 CCP1CAPbits.CCP1CTS2 // bit 2
6876 #define CCP1MODE0 CCP1CONbits.CCP1MODE0 // bit 0
6877 #define CCP1MODE1 CCP1CONbits.CCP1MODE1 // bit 1
6878 #define CCP1MODE2 CCP1CONbits.CCP1MODE2 // bit 2
6879 #define CCP1MODE3 CCP1CONbits.CCP1MODE3 // bit 3
6880 #define CCP1FMT CCP1CONbits.CCP1FMT // bit 4
6881 #define CCP1OUT CCP1CONbits.CCP1OUT // bit 5
6882 #define CCP1EN CCP1CONbits.CCP1EN // bit 7
6884 #define CCP1PPS0 CCP1PPSbits.CCP1PPS0 // bit 0
6885 #define CCP1PPS1 CCP1PPSbits.CCP1PPS1 // bit 1
6886 #define CCP1PPS2 CCP1PPSbits.CCP1PPS2 // bit 2
6887 #define CCP1PPS3 CCP1PPSbits.CCP1PPS3 // bit 3
6888 #define CCP1PPS4 CCP1PPSbits.CCP1PPS4 // bit 4
6890 #define CCP2CTS0 CCP2CAPbits.CCP2CTS0 // bit 0
6891 #define CCP2CTS1 CCP2CAPbits.CCP2CTS1 // bit 1
6892 #define CCP2CTS2 CCP2CAPbits.CCP2CTS2 // bit 2
6894 #define CCP2MODE0 CCP2CONbits.CCP2MODE0 // bit 0
6895 #define CCP2MODE1 CCP2CONbits.CCP2MODE1 // bit 1
6896 #define CCP2MODE2 CCP2CONbits.CCP2MODE2 // bit 2
6897 #define CCP2MODE3 CCP2CONbits.CCP2MODE3 // bit 3
6898 #define CCP2FMT CCP2CONbits.CCP2FMT // bit 4
6899 #define CCP2OUT CCP2CONbits.CCP2OUT // bit 5
6900 #define CCP2EN CCP2CONbits.CCP2EN // bit 7
6902 #define CCP2PPS0 CCP2PPSbits.CCP2PPS0 // bit 0
6903 #define CCP2PPS1 CCP2PPSbits.CCP2PPS1 // bit 1
6904 #define CCP2PPS2 CCP2PPSbits.CCP2PPS2 // bit 2
6905 #define CCP2PPS3 CCP2PPSbits.CCP2PPS3 // bit 3
6906 #define CCP2PPS4 CCP2PPSbits.CCP2PPS4 // bit 4
6908 #define C1TSEL CCPTMRSbits.C1TSEL // bit 0
6909 #define C2TSEL CCPTMRSbits.C2TSEL // bit 2
6911 #define LC1MODE0 CLC1CONbits.LC1MODE0 // bit 0, shadows bit in CLC1CONbits
6912 #define MODE0 CLC1CONbits.MODE0 // bit 0, shadows bit in CLC1CONbits
6913 #define LC1MODE1 CLC1CONbits.LC1MODE1 // bit 1, shadows bit in CLC1CONbits
6914 #define MODE1 CLC1CONbits.MODE1 // bit 1, shadows bit in CLC1CONbits
6915 #define LC1MODE2 CLC1CONbits.LC1MODE2 // bit 2, shadows bit in CLC1CONbits
6916 #define MODE2 CLC1CONbits.MODE2 // bit 2, shadows bit in CLC1CONbits
6917 #define LC1INTN CLC1CONbits.LC1INTN // bit 3, shadows bit in CLC1CONbits
6918 #define INTN CLC1CONbits.INTN // bit 3, shadows bit in CLC1CONbits
6919 #define LC1INTP CLC1CONbits.LC1INTP // bit 4, shadows bit in CLC1CONbits
6920 #define INTP CLC1CONbits.INTP // bit 4, shadows bit in CLC1CONbits
6921 #define LC1OUT CLC1CONbits.LC1OUT // bit 5, shadows bit in CLC1CONbits
6922 #define OUT CLC1CONbits.OUT // bit 5, shadows bit in CLC1CONbits
6923 #define LC1EN CLC1CONbits.LC1EN // bit 7, shadows bit in CLC1CONbits
6924 #define EN CLC1CONbits.EN // bit 7, shadows bit in CLC1CONbits
6926 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
6927 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
6928 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
6929 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
6930 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
6931 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
6932 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
6933 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
6934 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
6935 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
6936 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
6937 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
6938 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
6939 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
6940 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
6941 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
6943 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
6944 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
6945 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
6946 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
6947 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
6948 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
6949 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
6950 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
6951 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
6952 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
6953 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
6954 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
6955 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
6956 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
6957 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
6958 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
6960 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
6961 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
6962 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
6963 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
6964 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
6965 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
6966 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
6967 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
6968 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
6969 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
6971 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
6972 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
6973 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
6974 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
6975 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
6976 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
6977 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
6978 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
6979 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
6980 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
6982 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
6983 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
6984 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
6985 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
6986 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
6987 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
6988 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
6989 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
6990 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
6991 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
6993 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
6994 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
6995 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
6996 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
6997 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
6998 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
6999 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
7000 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
7001 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
7002 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
7004 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
7005 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
7006 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
7007 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
7008 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
7009 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
7010 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
7011 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
7012 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
7013 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
7015 #define MLC1OUT CLCDATAbits.MLC1OUT // bit 0
7016 #define MLC2OUT CLCDATAbits.MLC2OUT // bit 1
7018 #define CLCIN0PPS0 CLCIN0PPSbits.CLCIN0PPS0 // bit 0
7019 #define CLCIN0PPS1 CLCIN0PPSbits.CLCIN0PPS1 // bit 1
7020 #define CLCIN0PPS2 CLCIN0PPSbits.CLCIN0PPS2 // bit 2
7021 #define CLCIN0PPS3 CLCIN0PPSbits.CLCIN0PPS3 // bit 3
7022 #define CLCIN0PPS4 CLCIN0PPSbits.CLCIN0PPS4 // bit 4
7024 #define CLCIN1PPS0 CLCIN1PPSbits.CLCIN1PPS0 // bit 0
7025 #define CLCIN1PPS1 CLCIN1PPSbits.CLCIN1PPS1 // bit 1
7026 #define CLCIN1PPS2 CLCIN1PPSbits.CLCIN1PPS2 // bit 2
7027 #define CLCIN1PPS3 CLCIN1PPSbits.CLCIN1PPS3 // bit 3
7028 #define CLCIN1PPS4 CLCIN1PPSbits.CLCIN1PPS4 // bit 4
7030 #define CLCIN2PPS0 CLCIN2PPSbits.CLCIN2PPS0 // bit 0
7031 #define CLCIN2PPS1 CLCIN2PPSbits.CLCIN2PPS1 // bit 1
7032 #define CLCIN2PPS2 CLCIN2PPSbits.CLCIN2PPS2 // bit 2
7033 #define CLCIN2PPS3 CLCIN2PPSbits.CLCIN2PPS3 // bit 3
7034 #define CLCIN2PPS4 CLCIN2PPSbits.CLCIN2PPS4 // bit 4
7036 #define CLCIN3PPS0 CLCIN3PPSbits.CLCIN3PPS0 // bit 0
7037 #define CLCIN3PPS1 CLCIN3PPSbits.CLCIN3PPS1 // bit 1
7038 #define CLCIN3PPS2 CLCIN3PPSbits.CLCIN3PPS2 // bit 2
7039 #define CLCIN3PPS3 CLCIN3PPSbits.CLCIN3PPS3 // bit 3
7040 #define CLCIN3PPS4 CLCIN3PPSbits.CLCIN3PPS4 // bit 4
7042 #define CLKRDIV0 CLKRCONbits.CLKRDIV0 // bit 0
7043 #define CLKRDIV1 CLKRCONbits.CLKRDIV1 // bit 1
7044 #define CLKRDIV2 CLKRCONbits.CLKRDIV2 // bit 2
7045 #define CLKRDC0 CLKRCONbits.CLKRDC0 // bit 3
7046 #define CLKRDC1 CLKRCONbits.CLKRDC1 // bit 4
7047 #define CLKREN CLKRCONbits.CLKREN // bit 7
7049 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
7050 #define C1HYS CM1CON0bits.C1HYS // bit 1
7051 #define C1SP CM1CON0bits.C1SP // bit 2
7052 #define C1POL CM1CON0bits.C1POL // bit 4
7053 #define C1OUT CM1CON0bits.C1OUT // bit 6
7054 #define C1ON CM1CON0bits.C1ON // bit 7
7056 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
7057 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
7058 #define C1NCH2 CM1CON1bits.C1NCH2 // bit 2
7059 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 3
7060 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 4
7061 #define C1PCH2 CM1CON1bits.C1PCH2 // bit 5
7062 #define C1INTN CM1CON1bits.C1INTN // bit 6
7063 #define C1INTP CM1CON1bits.C1INTP // bit 7
7065 #define MC1OUT CMOUTbits.MC1OUT // bit 0
7067 #define DOZE0 CPUDOZEbits.DOZE0 // bit 0
7068 #define DOZE1 CPUDOZEbits.DOZE1 // bit 1
7069 #define DOZE2 CPUDOZEbits.DOZE2 // bit 2
7070 #define DOE CPUDOZEbits.DOE // bit 4
7071 #define ROI CPUDOZEbits.ROI // bit 5
7072 #define DOZEN CPUDOZEbits.DOZEN // bit 6
7073 #define IDLEN CPUDOZEbits.IDLEN // bit 7
7075 #define LSAC0 CWG1AS0bits.LSAC0 // bit 2, shadows bit in CWG1AS0bits
7076 #define CWG1LSAC0 CWG1AS0bits.CWG1LSAC0 // bit 2, shadows bit in CWG1AS0bits
7077 #define LSAC1 CWG1AS0bits.LSAC1 // bit 3, shadows bit in CWG1AS0bits
7078 #define CWG1LSAC1 CWG1AS0bits.CWG1LSAC1 // bit 3, shadows bit in CWG1AS0bits
7079 #define LSBD0 CWG1AS0bits.LSBD0 // bit 4, shadows bit in CWG1AS0bits
7080 #define CWG1LSBD0 CWG1AS0bits.CWG1LSBD0 // bit 4, shadows bit in CWG1AS0bits
7081 #define LSBD1 CWG1AS0bits.LSBD1 // bit 5, shadows bit in CWG1AS0bits
7082 #define CWG1LSBD1 CWG1AS0bits.CWG1LSBD1 // bit 5, shadows bit in CWG1AS0bits
7083 #define REN CWG1AS0bits.REN // bit 6, shadows bit in CWG1AS0bits
7084 #define CWG1REN CWG1AS0bits.CWG1REN // bit 6, shadows bit in CWG1AS0bits
7085 #define SHUTDOWN CWG1AS0bits.SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
7086 #define CWG1SHUTDOWN CWG1AS0bits.CWG1SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
7088 #define AS0E CWG1AS1bits.AS0E // bit 0
7089 #define AS1E CWG1AS1bits.AS1E // bit 1
7090 #define AS3E CWG1AS1bits.AS3E // bit 3
7092 #define CS CWG1CLKCONbits.CS // bit 0, shadows bit in CWG1CLKCONbits
7093 #define CWG1CS CWG1CLKCONbits.CWG1CS // bit 0, shadows bit in CWG1CLKCONbits
7095 #define POLA CWG1CON1bits.POLA // bit 0, shadows bit in CWG1CON1bits
7096 #define CWG1POLA CWG1CON1bits.CWG1POLA // bit 0, shadows bit in CWG1CON1bits
7097 #define POLB CWG1CON1bits.POLB // bit 1, shadows bit in CWG1CON1bits
7098 #define CWG1POLB CWG1CON1bits.CWG1POLB // bit 1, shadows bit in CWG1CON1bits
7099 #define POLC CWG1CON1bits.POLC // bit 2, shadows bit in CWG1CON1bits
7100 #define CWG1POLC CWG1CON1bits.CWG1POLC // bit 2, shadows bit in CWG1CON1bits
7101 #define POLD CWG1CON1bits.POLD // bit 3, shadows bit in CWG1CON1bits
7102 #define CWG1POLD CWG1CON1bits.CWG1POLD // bit 3, shadows bit in CWG1CON1bits
7103 #define IN CWG1CON1bits.IN // bit 5, shadows bit in CWG1CON1bits
7104 #define CWG1IN CWG1CON1bits.CWG1IN // bit 5, shadows bit in CWG1CON1bits
7106 #define CWG1DAT0 CWG1DATbits.CWG1DAT0 // bit 0
7107 #define CWG1DAT1 CWG1DATbits.CWG1DAT1 // bit 1
7108 #define CWG1DAT2 CWG1DATbits.CWG1DAT2 // bit 2
7109 #define CWG1DAT3 CWG1DATbits.CWG1DAT3 // bit 3
7111 #define DBF0 CWG1DBFbits.DBF0 // bit 0, shadows bit in CWG1DBFbits
7112 #define CWG1DBF0 CWG1DBFbits.CWG1DBF0 // bit 0, shadows bit in CWG1DBFbits
7113 #define DBF1 CWG1DBFbits.DBF1 // bit 1, shadows bit in CWG1DBFbits
7114 #define CWG1DBF1 CWG1DBFbits.CWG1DBF1 // bit 1, shadows bit in CWG1DBFbits
7115 #define DBF2 CWG1DBFbits.DBF2 // bit 2, shadows bit in CWG1DBFbits
7116 #define CWG1DBF2 CWG1DBFbits.CWG1DBF2 // bit 2, shadows bit in CWG1DBFbits
7117 #define DBF3 CWG1DBFbits.DBF3 // bit 3, shadows bit in CWG1DBFbits
7118 #define CWG1DBF3 CWG1DBFbits.CWG1DBF3 // bit 3, shadows bit in CWG1DBFbits
7119 #define DBF4 CWG1DBFbits.DBF4 // bit 4, shadows bit in CWG1DBFbits
7120 #define CWG1DBF4 CWG1DBFbits.CWG1DBF4 // bit 4, shadows bit in CWG1DBFbits
7121 #define DBF5 CWG1DBFbits.DBF5 // bit 5, shadows bit in CWG1DBFbits
7122 #define CWG1DBF5 CWG1DBFbits.CWG1DBF5 // bit 5, shadows bit in CWG1DBFbits
7124 #define DBR0 CWG1DBRbits.DBR0 // bit 0, shadows bit in CWG1DBRbits
7125 #define CWG1DBR0 CWG1DBRbits.CWG1DBR0 // bit 0, shadows bit in CWG1DBRbits
7126 #define DBR1 CWG1DBRbits.DBR1 // bit 1, shadows bit in CWG1DBRbits
7127 #define CWG1DBR1 CWG1DBRbits.CWG1DBR1 // bit 1, shadows bit in CWG1DBRbits
7128 #define DBR2 CWG1DBRbits.DBR2 // bit 2, shadows bit in CWG1DBRbits
7129 #define CWG1DBR2 CWG1DBRbits.CWG1DBR2 // bit 2, shadows bit in CWG1DBRbits
7130 #define DBR3 CWG1DBRbits.DBR3 // bit 3, shadows bit in CWG1DBRbits
7131 #define CWG1DBR3 CWG1DBRbits.CWG1DBR3 // bit 3, shadows bit in CWG1DBRbits
7132 #define DBR4 CWG1DBRbits.DBR4 // bit 4, shadows bit in CWG1DBRbits
7133 #define CWG1DBR4 CWG1DBRbits.CWG1DBR4 // bit 4, shadows bit in CWG1DBRbits
7134 #define DBR5 CWG1DBRbits.DBR5 // bit 5, shadows bit in CWG1DBRbits
7135 #define CWG1DBR5 CWG1DBRbits.CWG1DBR5 // bit 5, shadows bit in CWG1DBRbits
7137 #define CWG1PPS0 CWG1PPSbits.CWG1PPS0 // bit 0
7138 #define CWG1PPS1 CWG1PPSbits.CWG1PPS1 // bit 1
7139 #define CWG1PPS2 CWG1PPSbits.CWG1PPS2 // bit 2
7140 #define CWG1PPS3 CWG1PPSbits.CWG1PPS3 // bit 3
7141 #define CWG1PPS4 CWG1PPSbits.CWG1PPS4 // bit 4
7143 #define STRA CWG1STRbits.STRA // bit 0, shadows bit in CWG1STRbits
7144 #define CWG1STRA CWG1STRbits.CWG1STRA // bit 0, shadows bit in CWG1STRbits
7145 #define STRB CWG1STRbits.STRB // bit 1, shadows bit in CWG1STRbits
7146 #define CWG1STRB CWG1STRbits.CWG1STRB // bit 1, shadows bit in CWG1STRbits
7147 #define STRC CWG1STRbits.STRC // bit 2, shadows bit in CWG1STRbits
7148 #define CWG1STRC CWG1STRbits.CWG1STRC // bit 2, shadows bit in CWG1STRbits
7149 #define STRD CWG1STRbits.STRD // bit 3, shadows bit in CWG1STRbits
7150 #define CWG1STRD CWG1STRbits.CWG1STRD // bit 3, shadows bit in CWG1STRbits
7151 #define OVRA CWG1STRbits.OVRA // bit 4, shadows bit in CWG1STRbits
7152 #define CWG1OVRA CWG1STRbits.CWG1OVRA // bit 4, shadows bit in CWG1STRbits
7153 #define OVRB CWG1STRbits.OVRB // bit 5, shadows bit in CWG1STRbits
7154 #define CWG1OVRB CWG1STRbits.CWG1OVRB // bit 5, shadows bit in CWG1STRbits
7155 #define OVRC CWG1STRbits.OVRC // bit 6, shadows bit in CWG1STRbits
7156 #define CWG1OVRC CWG1STRbits.CWG1OVRC // bit 6, shadows bit in CWG1STRbits
7157 #define OVRD CWG1STRbits.OVRD // bit 7, shadows bit in CWG1STRbits
7158 #define CWG1OVRD CWG1STRbits.CWG1OVRD // bit 7, shadows bit in CWG1STRbits
7160 #define DAC1NSS DACCON0bits.DAC1NSS // bit 0
7161 #define DAC1PSS0 DACCON0bits.DAC1PSS0 // bit 2
7162 #define DAC1PSS1 DACCON0bits.DAC1PSS1 // bit 3
7163 #define DAC1OE DACCON0bits.DAC1OE // bit 5
7164 #define DAC1EN DACCON0bits.DAC1EN // bit 7
7166 #define DAC1R0 DACCON1bits.DAC1R0 // bit 0
7167 #define DAC1R1 DACCON1bits.DAC1R1 // bit 1
7168 #define DAC1R2 DACCON1bits.DAC1R2 // bit 2
7169 #define DAC1R3 DACCON1bits.DAC1R3 // bit 3
7170 #define DAC1R4 DACCON1bits.DAC1R4 // bit 4
7172 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
7173 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
7174 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
7175 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
7176 #define TSRNG FVRCONbits.TSRNG // bit 4
7177 #define TSEN FVRCONbits.TSEN // bit 5
7178 #define FVRRDY FVRCONbits.FVRRDY // bit 6
7179 #define FVREN FVRCONbits.FVREN // bit 7
7181 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
7182 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
7183 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
7184 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
7185 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
7186 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
7188 #define INTEDG INTCONbits.INTEDG // bit 0
7189 #define PEIE INTCONbits.PEIE // bit 6
7190 #define GIE INTCONbits.GIE // bit 7
7192 #define INTPPS0 INTPPSbits.INTPPS0 // bit 0
7193 #define INTPPS1 INTPPSbits.INTPPS1 // bit 1
7194 #define INTPPS2 INTPPSbits.INTPPS2 // bit 2
7195 #define INTPPS3 INTPPSbits.INTPPS3 // bit 3
7196 #define INTPPS4 INTPPSbits.INTPPS4 // bit 4
7198 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
7199 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
7200 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
7201 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
7202 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
7203 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
7205 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
7206 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
7207 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
7208 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
7209 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
7210 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
7212 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
7213 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
7214 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
7215 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
7216 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
7217 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
7219 #define LATA0 LATAbits.LATA0 // bit 0
7220 #define LATA1 LATAbits.LATA1 // bit 1
7221 #define LATA2 LATAbits.LATA2 // bit 2
7222 #define LATA4 LATAbits.LATA4 // bit 4
7223 #define LATA5 LATAbits.LATA5 // bit 5
7225 #define MDCH0 MDCARHbits.MDCH0 // bit 0
7226 #define MDCH1 MDCARHbits.MDCH1 // bit 1
7227 #define MDCH2 MDCARHbits.MDCH2 // bit 2
7228 #define MDCH3 MDCARHbits.MDCH3 // bit 3
7229 #define MDCHSYNC MDCARHbits.MDCHSYNC // bit 5
7230 #define MDCHPOL MDCARHbits.MDCHPOL // bit 6
7232 #define MDCL0 MDCARLbits.MDCL0 // bit 0
7233 #define MDCL1 MDCARLbits.MDCL1 // bit 1
7234 #define MDCL2 MDCARLbits.MDCL2 // bit 2
7235 #define MDCL3 MDCARLbits.MDCL3 // bit 3
7236 #define MDCLSYNC MDCARLbits.MDCLSYNC // bit 5
7237 #define MDCLPOL MDCARLbits.MDCLPOL // bit 6
7239 #define MDCIN1PPS0 MDCIN1PPSbits.MDCIN1PPS0 // bit 0
7240 #define MDCIN1PPS1 MDCIN1PPSbits.MDCIN1PPS1 // bit 1
7241 #define MDCIN1PPS2 MDCIN1PPSbits.MDCIN1PPS2 // bit 2
7242 #define MDCIN1PPS3 MDCIN1PPSbits.MDCIN1PPS3 // bit 3
7243 #define MDCIN1PPS4 MDCIN1PPSbits.MDCIN1PPS4 // bit 4
7245 #define MDCIN2PPS0 MDCIN2PPSbits.MDCIN2PPS0 // bit 0
7246 #define MDCIN2PPS1 MDCIN2PPSbits.MDCIN2PPS1 // bit 1
7247 #define MDCIN2PPS2 MDCIN2PPSbits.MDCIN2PPS2 // bit 2
7248 #define MDCIN2PPS3 MDCIN2PPSbits.MDCIN2PPS3 // bit 3
7249 #define MDCIN2PPS4 MDCIN2PPSbits.MDCIN2PPS4 // bit 4
7251 #define MDBIT MDCONbits.MDBIT // bit 0
7252 #define MDOUT MDCONbits.MDOUT // bit 3
7253 #define MDOPOL MDCONbits.MDOPOL // bit 4
7254 #define MDEN MDCONbits.MDEN // bit 7
7256 #define MDMINPPS0 MDMINPPSbits.MDMINPPS0 // bit 0
7257 #define MDMINPPS1 MDMINPPSbits.MDMINPPS1 // bit 1
7258 #define MDMINPPS2 MDMINPPSbits.MDMINPPS2 // bit 2
7259 #define MDMINPPS3 MDMINPPSbits.MDMINPPS3 // bit 3
7260 #define MDMINPPS4 MDMINPPSbits.MDMINPPS4 // bit 4
7262 #define MDMS0 MDSRCbits.MDMS0 // bit 0
7263 #define MDMS1 MDSRCbits.MDMS1 // bit 1
7264 #define MDMS2 MDSRCbits.MDMS2 // bit 2
7265 #define MDMS3 MDSRCbits.MDMS3 // bit 3
7267 #define N1PFM NCO1CONbits.N1PFM // bit 0
7268 #define N1POL NCO1CONbits.N1POL // bit 4
7269 #define N1OUT NCO1CONbits.N1OUT // bit 5
7270 #define N1EN NCO1CONbits.N1EN // bit 7
7272 #define NVMADR8 NVMADRHbits.NVMADR8 // bit 0
7273 #define NVMADR9 NVMADRHbits.NVMADR9 // bit 1
7274 #define NVMADR10 NVMADRHbits.NVMADR10 // bit 2
7275 #define NVMADR11 NVMADRHbits.NVMADR11 // bit 3
7276 #define NVMADR12 NVMADRHbits.NVMADR12 // bit 4
7277 #define NVMADR13 NVMADRHbits.NVMADR13 // bit 5
7278 #define NVMADR14 NVMADRHbits.NVMADR14 // bit 6
7280 #define NVMADR0 NVMADRLbits.NVMADR0 // bit 0
7281 #define NVMADR1 NVMADRLbits.NVMADR1 // bit 1
7282 #define NVMADR2 NVMADRLbits.NVMADR2 // bit 2
7283 #define NVMADR3 NVMADRLbits.NVMADR3 // bit 3
7284 #define NVMADR4 NVMADRLbits.NVMADR4 // bit 4
7285 #define NVMADR5 NVMADRLbits.NVMADR5 // bit 5
7286 #define NVMADR6 NVMADRLbits.NVMADR6 // bit 6
7287 #define NVMADR7 NVMADRLbits.NVMADR7 // bit 7
7289 #define RD NVMCON1bits.RD // bit 0
7290 #define WR NVMCON1bits.WR // bit 1
7291 #define WREN NVMCON1bits.WREN // bit 2
7292 #define WRERR NVMCON1bits.WRERR // bit 3
7293 #define FREE NVMCON1bits.FREE // bit 4
7294 #define LWLO NVMCON1bits.LWLO // bit 5
7295 #define NVMREGS NVMCON1bits.NVMREGS // bit 6
7297 #define NVMDAT8 NVMDATHbits.NVMDAT8 // bit 0
7298 #define NVMDAT9 NVMDATHbits.NVMDAT9 // bit 1
7299 #define NVMDAT10 NVMDATHbits.NVMDAT10 // bit 2
7300 #define NVMDAT11 NVMDATHbits.NVMDAT11 // bit 3
7301 #define NVMDAT12 NVMDATHbits.NVMDAT12 // bit 4
7302 #define NVMDAT13 NVMDATHbits.NVMDAT13 // bit 5
7304 #define NVMDAT0 NVMDATLbits.NVMDAT0 // bit 0
7305 #define NVMDAT1 NVMDATLbits.NVMDAT1 // bit 1
7306 #define NVMDAT2 NVMDATLbits.NVMDAT2 // bit 2
7307 #define NVMDAT3 NVMDATLbits.NVMDAT3 // bit 3
7308 #define NVMDAT4 NVMDATLbits.NVMDAT4 // bit 4
7309 #define NVMDAT5 NVMDATLbits.NVMDAT5 // bit 5
7310 #define NVMDAT6 NVMDATLbits.NVMDAT6 // bit 6
7311 #define NVMDAT7 NVMDATLbits.NVMDAT7 // bit 7
7313 #define ODCA0 ODCONAbits.ODCA0 // bit 0
7314 #define ODCA1 ODCONAbits.ODCA1 // bit 1
7315 #define ODCA2 ODCONAbits.ODCA2 // bit 2
7316 #define ODCA4 ODCONAbits.ODCA4 // bit 4
7317 #define ODCA5 ODCONAbits.ODCA5 // bit 5
7319 #define NDIV0 OSCCON1bits.NDIV0 // bit 0
7320 #define NDIV1 OSCCON1bits.NDIV1 // bit 1
7321 #define NDIV2 OSCCON1bits.NDIV2 // bit 2
7322 #define NDIV3 OSCCON1bits.NDIV3 // bit 3
7323 #define NOSC0 OSCCON1bits.NOSC0 // bit 4
7324 #define NOSC1 OSCCON1bits.NOSC1 // bit 5
7325 #define NOSC2 OSCCON1bits.NOSC2 // bit 6
7327 #define CDIV0 OSCCON2bits.CDIV0 // bit 0
7328 #define CDIV1 OSCCON2bits.CDIV1 // bit 1
7329 #define CDIV2 OSCCON2bits.CDIV2 // bit 2
7330 #define CDIV3 OSCCON2bits.CDIV3 // bit 3
7331 #define COSC0 OSCCON2bits.COSC0 // bit 4
7332 #define COSC1 OSCCON2bits.COSC1 // bit 5
7333 #define COSC2 OSCCON2bits.COSC2 // bit 6
7335 #define NOSCR OSCCON3bits.NOSCR // bit 3
7336 #define ORDY OSCCON3bits.ORDY // bit 4
7337 #define SOSCBE OSCCON3bits.SOSCBE // bit 5
7338 #define SOSCPWR OSCCON3bits.SOSCPWR // bit 6
7339 #define CSWHOLD OSCCON3bits.CSWHOLD // bit 7
7341 #define ADOEN OSCENbits.ADOEN // bit 2
7342 #define SOSCEN OSCENbits.SOSCEN // bit 3
7343 #define LFOEN OSCENbits.LFOEN // bit 4
7344 #define HFOEN OSCENbits.HFOEN // bit 6
7345 #define EXTOEN OSCENbits.EXTOEN // bit 7
7347 #define HFFRQ0 OSCFRQbits.HFFRQ0 // bit 0
7348 #define HFFRQ1 OSCFRQbits.HFFRQ1 // bit 1
7349 #define HFFRQ2 OSCFRQbits.HFFRQ2 // bit 2
7350 #define HFFRQ3 OSCFRQbits.HFFRQ3 // bit 3
7352 #define PLLR OSCSTAT1bits.PLLR // bit 0
7353 #define ADOR OSCSTAT1bits.ADOR // bit 2
7354 #define SOR OSCSTAT1bits.SOR // bit 3
7355 #define LFOR OSCSTAT1bits.LFOR // bit 4
7356 #define HFOR OSCSTAT1bits.HFOR // bit 6
7357 #define EXTOR OSCSTAT1bits.EXTOR // bit 7
7359 #define HFTUN0 OSCTUNEbits.HFTUN0 // bit 0
7360 #define HFTUN1 OSCTUNEbits.HFTUN1 // bit 1
7361 #define HFTUN2 OSCTUNEbits.HFTUN2 // bit 2
7362 #define HFTUN3 OSCTUNEbits.HFTUN3 // bit 3
7363 #define HFTUN4 OSCTUNEbits.HFTUN4 // bit 4
7364 #define HFTUN5 OSCTUNEbits.HFTUN5 // bit 5
7366 #define NOT_BOR PCON0bits.NOT_BOR // bit 0
7367 #define NOT_POR PCON0bits.NOT_POR // bit 1
7368 #define NOT_RI PCON0bits.NOT_RI // bit 2
7369 #define NOT_RMCLR PCON0bits.NOT_RMCLR // bit 3
7370 #define NOT_RWDT PCON0bits.NOT_RWDT // bit 4
7371 #define STKUNF PCON0bits.STKUNF // bit 6
7372 #define STKOVF PCON0bits.STKOVF // bit 7
7374 #define INTE PIE0bits.INTE // bit 0
7375 #define IOCIE PIE0bits.IOCIE // bit 4
7376 #define TMR0IE PIE0bits.TMR0IE // bit 5
7378 #define TMR1IE PIE1bits.TMR1IE // bit 0
7379 #define TMR2IE PIE1bits.TMR2IE // bit 1
7380 #define BCL1IE PIE1bits.BCL1IE // bit 2
7381 #define SSP1IE PIE1bits.SSP1IE // bit 3
7382 #define TXIE PIE1bits.TXIE // bit 4
7383 #define RCIE PIE1bits.RCIE // bit 5
7384 #define ADIE PIE1bits.ADIE // bit 6
7385 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
7387 #define NCO1IE PIE2bits.NCO1IE // bit 0
7388 #define NVMIE PIE2bits.NVMIE // bit 4
7389 #define C1IE PIE2bits.C1IE // bit 5
7391 #define CLC1IE PIE3bits.CLC1IE // bit 0
7392 #define CLC2IE PIE3bits.CLC2IE // bit 1
7393 #define CSWIE PIE3bits.CSWIE // bit 6
7394 #define OSFIE PIE3bits.OSFIE // bit 7
7396 #define CCP1IE PIE4bits.CCP1IE // bit 0
7397 #define CCP2IE PIE4bits.CCP2IE // bit 1
7398 #define CWG1IE PIE4bits.CWG1IE // bit 6
7400 #define INTF PIR0bits.INTF // bit 0
7401 #define IOCIF PIR0bits.IOCIF // bit 4
7402 #define TMR0IF PIR0bits.TMR0IF // bit 5
7404 #define TMR1IF PIR1bits.TMR1IF // bit 0
7405 #define TMR2IF PIR1bits.TMR2IF // bit 1
7406 #define BCL1IF PIR1bits.BCL1IF // bit 2
7407 #define SSP1IF PIR1bits.SSP1IF // bit 3
7408 #define TXIF PIR1bits.TXIF // bit 4
7409 #define RCIF PIR1bits.RCIF // bit 5
7410 #define ADIF PIR1bits.ADIF // bit 6
7411 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
7413 #define NCO1IF PIR2bits.NCO1IF // bit 0
7414 #define NVMIF PIR2bits.NVMIF // bit 4
7415 #define C1IF PIR2bits.C1IF // bit 5
7417 #define CLC1IF PIR3bits.CLC1IF // bit 0
7418 #define CLC2IF PIR3bits.CLC2IF // bit 1
7419 #define CSWIF PIR3bits.CSWIF // bit 6
7420 #define OSFIF PIR3bits.OSFIF // bit 7
7422 #define CCP1IF PIR4bits.CCP1IF // bit 0
7423 #define CCP2IF PIR4bits.CCP2IF // bit 1
7424 #define CWG1IF PIR4bits.CWG1IF // bit 6
7426 #define IOCMD PMD0bits.IOCMD // bit 0
7427 #define CLKRMD PMD0bits.CLKRMD // bit 1
7428 #define NVMMD PMD0bits.NVMMD // bit 2
7429 #define FVRMD PMD0bits.FVRMD // bit 6
7430 #define SYSCMD PMD0bits.SYSCMD // bit 7
7432 #define TMR0MD PMD1bits.TMR0MD // bit 0
7433 #define TMR1MD PMD1bits.TMR1MD // bit 1
7434 #define TMR2MD PMD1bits.TMR2MD // bit 2
7435 #define NCOMD PMD1bits.NCOMD // bit 7
7437 #define CMP1MD PMD2bits.CMP1MD // bit 1
7438 #define ADCMD PMD2bits.ADCMD // bit 5
7439 #define DACMD PMD2bits.DACMD // bit 6
7441 #define CCP1MD PMD3bits.CCP1MD // bit 0
7442 #define CCP2MD PMD3bits.CCP2MD // bit 1
7443 #define PWM5MD PMD3bits.PWM5MD // bit 4
7444 #define PWM6MD PMD3bits.PWM6MD // bit 5
7445 #define CWG1MD PMD3bits.CWG1MD // bit 6
7447 #define MSSP1MD PMD4bits.MSSP1MD // bit 1
7448 #define UART1MD PMD4bits.UART1MD // bit 5
7450 #define DSMMD PMD5bits.DSMMD // bit 0
7451 #define CLC1MD PMD5bits.CLC1MD // bit 1
7452 #define CLC2MD PMD5bits.CLC2MD // bit 2
7454 #define RA0 PORTAbits.RA0 // bit 0
7455 #define RA1 PORTAbits.RA1 // bit 1
7456 #define RA2 PORTAbits.RA2 // bit 2
7457 #define RA3 PORTAbits.RA3 // bit 3
7458 #define RA4 PORTAbits.RA4 // bit 4
7459 #define RA5 PORTAbits.RA5 // bit 5
7461 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
7463 #define PWM5POL PWM5CONbits.PWM5POL // bit 4
7464 #define PWM5OUT PWM5CONbits.PWM5OUT // bit 5
7465 #define PWM5EN PWM5CONbits.PWM5EN // bit 7
7467 #define PWM5DCH0 PWM5DCHbits.PWM5DCH0 // bit 0
7468 #define PWM5DCH1 PWM5DCHbits.PWM5DCH1 // bit 1
7469 #define PWM5DCH2 PWM5DCHbits.PWM5DCH2 // bit 2
7470 #define PWM5DCH3 PWM5DCHbits.PWM5DCH3 // bit 3
7471 #define PWM5DCH4 PWM5DCHbits.PWM5DCH4 // bit 4
7472 #define PWM5DCH5 PWM5DCHbits.PWM5DCH5 // bit 5
7473 #define PWM5DCH6 PWM5DCHbits.PWM5DCH6 // bit 6
7474 #define PWM5DCH7 PWM5DCHbits.PWM5DCH7 // bit 7
7476 #define PWM5DCL0 PWM5DCLbits.PWM5DCL0 // bit 6
7477 #define PWM5DCL1 PWM5DCLbits.PWM5DCL1 // bit 7
7479 #define PWM6POL PWM6CONbits.PWM6POL // bit 4
7480 #define PWM6OUT PWM6CONbits.PWM6OUT // bit 5
7481 #define PWM6EN PWM6CONbits.PWM6EN // bit 7
7483 #define PWM6DCH0 PWM6DCHbits.PWM6DCH0 // bit 0
7484 #define PWM6DCH1 PWM6DCHbits.PWM6DCH1 // bit 1
7485 #define PWM6DCH2 PWM6DCHbits.PWM6DCH2 // bit 2
7486 #define PWM6DCH3 PWM6DCHbits.PWM6DCH3 // bit 3
7487 #define PWM6DCH4 PWM6DCHbits.PWM6DCH4 // bit 4
7488 #define PWM6DCH5 PWM6DCHbits.PWM6DCH5 // bit 5
7489 #define PWM6DCH6 PWM6DCHbits.PWM6DCH6 // bit 6
7490 #define PWM6DCH7 PWM6DCHbits.PWM6DCH7 // bit 7
7492 #define PWM6DCL0 PWM6DCLbits.PWM6DCL0 // bit 6
7493 #define PWM6DCL1 PWM6DCLbits.PWM6DCL1 // bit 7
7495 #define RA0PPS0 RA0PPSbits.RA0PPS0 // bit 0
7496 #define RA0PPS1 RA0PPSbits.RA0PPS1 // bit 1
7497 #define RA0PPS2 RA0PPSbits.RA0PPS2 // bit 2
7498 #define RA0PPS3 RA0PPSbits.RA0PPS3 // bit 3
7499 #define RA0PPS4 RA0PPSbits.RA0PPS4 // bit 4
7501 #define RA1PPS0 RA1PPSbits.RA1PPS0 // bit 0
7502 #define RA1PPS1 RA1PPSbits.RA1PPS1 // bit 1
7503 #define RA1PPS2 RA1PPSbits.RA1PPS2 // bit 2
7504 #define RA1PPS3 RA1PPSbits.RA1PPS3 // bit 3
7505 #define RA1PPS4 RA1PPSbits.RA1PPS4 // bit 4
7507 #define RA2PPS0 RA2PPSbits.RA2PPS0 // bit 0
7508 #define RA2PPS1 RA2PPSbits.RA2PPS1 // bit 1
7509 #define RA2PPS2 RA2PPSbits.RA2PPS2 // bit 2
7510 #define RA2PPS3 RA2PPSbits.RA2PPS3 // bit 3
7511 #define RA2PPS4 RA2PPSbits.RA2PPS4 // bit 4
7513 #define RA4PPS0 RA4PPSbits.RA4PPS0 // bit 0
7514 #define RA4PPS1 RA4PPSbits.RA4PPS1 // bit 1
7515 #define RA4PPS2 RA4PPSbits.RA4PPS2 // bit 2
7516 #define RA4PPS3 RA4PPSbits.RA4PPS3 // bit 3
7517 #define RA4PPS4 RA4PPSbits.RA4PPS4 // bit 4
7519 #define RA5PPS0 RA5PPSbits.RA5PPS0 // bit 0
7520 #define RA5PPS1 RA5PPSbits.RA5PPS1 // bit 1
7521 #define RA5PPS2 RA5PPSbits.RA5PPS2 // bit 2
7522 #define RA5PPS3 RA5PPSbits.RA5PPS3 // bit 3
7523 #define RA5PPS4 RA5PPSbits.RA5PPS4 // bit 4
7525 #define RX9D RC1STAbits.RX9D // bit 0
7526 #define OERR RC1STAbits.OERR // bit 1
7527 #define FERR RC1STAbits.FERR // bit 2
7528 #define ADDEN RC1STAbits.ADDEN // bit 3
7529 #define CREN RC1STAbits.CREN // bit 4
7530 #define SREN RC1STAbits.SREN // bit 5
7531 #define RX9 RC1STAbits.RX9 // bit 6
7532 #define SPEN RC1STAbits.SPEN // bit 7
7534 #define RXPPS0 RXPPSbits.RXPPS0 // bit 0
7535 #define RXPPS1 RXPPSbits.RXPPS1 // bit 1
7536 #define RXPPS2 RXPPSbits.RXPPS2 // bit 2
7537 #define RXPPS3 RXPPSbits.RXPPS3 // bit 3
7538 #define RXPPS4 RXPPSbits.RXPPS4 // bit 4
7540 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
7541 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
7542 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
7543 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
7544 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
7546 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
7547 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
7548 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
7549 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
7550 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
7551 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
7552 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
7553 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
7554 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
7555 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
7556 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
7557 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
7558 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
7559 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
7560 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
7561 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
7563 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
7564 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
7565 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
7566 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
7567 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
7568 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
7569 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
7570 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
7571 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
7572 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
7573 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
7574 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
7575 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
7576 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
7577 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
7578 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
7580 #define SSP1CLKPPS0 SSP1CLKPPSbits.SSP1CLKPPS0 // bit 0
7581 #define SSP1CLKPPS1 SSP1CLKPPSbits.SSP1CLKPPS1 // bit 1
7582 #define SSP1CLKPPS2 SSP1CLKPPSbits.SSP1CLKPPS2 // bit 2
7583 #define SSP1CLKPPS3 SSP1CLKPPSbits.SSP1CLKPPS3 // bit 3
7584 #define SSP1CLKPPS4 SSP1CLKPPSbits.SSP1CLKPPS4 // bit 4
7586 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
7587 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
7588 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
7589 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
7590 #define CKP SSP1CONbits.CKP // bit 4
7591 #define SSPEN SSP1CONbits.SSPEN // bit 5
7592 #define SSPOV SSP1CONbits.SSPOV // bit 6
7593 #define WCOL SSP1CONbits.WCOL // bit 7
7595 #define SEN SSP1CON2bits.SEN // bit 0
7596 #define RSEN SSP1CON2bits.RSEN // bit 1
7597 #define PEN SSP1CON2bits.PEN // bit 2
7598 #define RCEN SSP1CON2bits.RCEN // bit 3
7599 #define ACKEN SSP1CON2bits.ACKEN // bit 4
7600 #define ACKDT SSP1CON2bits.ACKDT // bit 5
7601 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
7602 #define GCEN SSP1CON2bits.GCEN // bit 7
7604 #define DHEN SSP1CON3bits.DHEN // bit 0
7605 #define AHEN SSP1CON3bits.AHEN // bit 1
7606 #define SBCDE SSP1CON3bits.SBCDE // bit 2
7607 #define SDAHT SSP1CON3bits.SDAHT // bit 3
7608 #define BOEN SSP1CON3bits.BOEN // bit 4
7609 #define SCIE SSP1CON3bits.SCIE // bit 5
7610 #define PCIE SSP1CON3bits.PCIE // bit 6
7611 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
7613 #define SSP1DATPPS0 SSP1DATPPSbits.SSP1DATPPS0 // bit 0
7614 #define SSP1DATPPS1 SSP1DATPPSbits.SSP1DATPPS1 // bit 1
7615 #define SSP1DATPPS2 SSP1DATPPSbits.SSP1DATPPS2 // bit 2
7616 #define SSP1DATPPS3 SSP1DATPPSbits.SSP1DATPPS3 // bit 3
7617 #define SSP1DATPPS4 SSP1DATPPSbits.SSP1DATPPS4 // bit 4
7619 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
7620 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
7621 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
7622 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
7623 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
7624 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
7625 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
7626 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
7627 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
7628 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
7629 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
7630 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
7631 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
7632 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
7633 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
7634 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
7636 #define SSP1SSPPS0 SSP1SSPPSbits.SSP1SSPPS0 // bit 0
7637 #define SSP1SSPPS1 SSP1SSPPSbits.SSP1SSPPS1 // bit 1
7638 #define SSP1SSPPS2 SSP1SSPPSbits.SSP1SSPPS2 // bit 2
7639 #define SSP1SSPPS3 SSP1SSPPSbits.SSP1SSPPS3 // bit 3
7640 #define SSP1SSPPS4 SSP1SSPPSbits.SSP1SSPPS4 // bit 4
7642 #define BF SSP1STATbits.BF // bit 0
7643 #define UA SSP1STATbits.UA // bit 1
7644 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
7645 #define S SSP1STATbits.S // bit 3
7646 #define P SSP1STATbits.P // bit 4
7647 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
7648 #define CKE SSP1STATbits.CKE // bit 6
7649 #define SMP SSP1STATbits.SMP // bit 7
7651 #define C STATUSbits.C // bit 0
7652 #define DC STATUSbits.DC // bit 1
7653 #define Z STATUSbits.Z // bit 2
7654 #define NOT_PD STATUSbits.NOT_PD // bit 3
7655 #define NOT_TO STATUSbits.NOT_TO // bit 4
7657 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
7658 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
7659 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
7661 #define T0CKIPPS0 T0CKIPPSbits.T0CKIPPS0 // bit 0
7662 #define T0CKIPPS1 T0CKIPPSbits.T0CKIPPS1 // bit 1
7663 #define T0CKIPPS2 T0CKIPPSbits.T0CKIPPS2 // bit 2
7664 #define T0CKIPPS3 T0CKIPPSbits.T0CKIPPS3 // bit 3
7665 #define T0CKIPPS4 T0CKIPPSbits.T0CKIPPS4 // bit 4
7667 #define T0OUTPS0 T0CON0bits.T0OUTPS0 // bit 0
7668 #define T0OUTPS1 T0CON0bits.T0OUTPS1 // bit 1
7669 #define T0OUTPS2 T0CON0bits.T0OUTPS2 // bit 2
7670 #define T0OUTPS3 T0CON0bits.T0OUTPS3 // bit 3
7671 #define T016BIT T0CON0bits.T016BIT // bit 4
7672 #define T0OUT T0CON0bits.T0OUT // bit 5
7673 #define T0EN T0CON0bits.T0EN // bit 7
7675 #define T0CKPS0 T0CON1bits.T0CKPS0 // bit 0
7676 #define T0CKPS1 T0CON1bits.T0CKPS1 // bit 1
7677 #define T0CKPS2 T0CON1bits.T0CKPS2 // bit 2
7678 #define T0CKPS3 T0CON1bits.T0CKPS3 // bit 3
7679 #define T0ASYNC T0CON1bits.T0ASYNC // bit 4
7680 #define T0CS0 T0CON1bits.T0CS0 // bit 5
7681 #define T0CS1 T0CON1bits.T0CS1 // bit 6
7682 #define T0CS2 T0CON1bits.T0CS2 // bit 7
7684 #define T1CKIPPS0 T1CKIPPSbits.T1CKIPPS0 // bit 0
7685 #define T1CKIPPS1 T1CKIPPSbits.T1CKIPPS1 // bit 1
7686 #define T1CKIPPS2 T1CKIPPSbits.T1CKIPPS2 // bit 2
7687 #define T1CKIPPS3 T1CKIPPSbits.T1CKIPPS3 // bit 3
7688 #define T1CKIPPS4 T1CKIPPSbits.T1CKIPPS4 // bit 4
7690 #define TMR1ON T1CONbits.TMR1ON // bit 0
7691 #define T1SYNC T1CONbits.T1SYNC // bit 2
7692 #define T1SOSC T1CONbits.T1SOSC // bit 3
7693 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
7694 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
7695 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
7696 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
7698 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
7699 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
7700 #define T1GVAL T1GCONbits.T1GVAL // bit 2
7701 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3
7702 #define T1GSPM T1GCONbits.T1GSPM // bit 4
7703 #define T1GTM T1GCONbits.T1GTM // bit 5
7704 #define T1GPOL T1GCONbits.T1GPOL // bit 6
7705 #define TMR1GE T1GCONbits.TMR1GE // bit 7
7707 #define T1GPPS0 T1GPPSbits.T1GPPS0 // bit 0
7708 #define T1GPPS1 T1GPPSbits.T1GPPS1 // bit 1
7709 #define T1GPPS2 T1GPPSbits.T1GPPS2 // bit 2
7710 #define T1GPPS3 T1GPPSbits.T1GPPS3 // bit 3
7711 #define T1GPPS4 T1GPPSbits.T1GPPS4 // bit 4
7713 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
7714 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
7715 #define TMR2ON T2CONbits.TMR2ON // bit 2
7716 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
7717 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
7718 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
7719 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
7721 #define TMR08 TMR0Hbits.TMR08 // bit 0
7722 #define TMR09 TMR0Hbits.TMR09 // bit 1
7723 #define TMR010 TMR0Hbits.TMR010 // bit 2
7724 #define TMR011 TMR0Hbits.TMR011 // bit 3
7725 #define TMR012 TMR0Hbits.TMR012 // bit 4
7726 #define TMR013 TMR0Hbits.TMR013 // bit 5
7727 #define TMR014 TMR0Hbits.TMR014 // bit 6
7728 #define TMR015 TMR0Hbits.TMR015 // bit 7
7730 #define TMR00 TMR0Lbits.TMR00 // bit 0
7731 #define TMR01 TMR0Lbits.TMR01 // bit 1
7732 #define TMR02 TMR0Lbits.TMR02 // bit 2
7733 #define TMR03 TMR0Lbits.TMR03 // bit 3
7734 #define TMR04 TMR0Lbits.TMR04 // bit 4
7735 #define TMR05 TMR0Lbits.TMR05 // bit 5
7736 #define TMR06 TMR0Lbits.TMR06 // bit 6
7737 #define TMR07 TMR0Lbits.TMR07 // bit 7
7739 #define TRISA0 TRISAbits.TRISA0 // bit 0
7740 #define TRISA1 TRISAbits.TRISA1 // bit 1
7741 #define TRISA2 TRISAbits.TRISA2 // bit 2
7742 #define TRISA4 TRISAbits.TRISA4 // bit 4
7743 #define TRISA5 TRISAbits.TRISA5 // bit 5
7745 #define TX9D TX1STAbits.TX9D // bit 0
7746 #define TRMT TX1STAbits.TRMT // bit 1
7747 #define BRGH TX1STAbits.BRGH // bit 2
7748 #define SENDB TX1STAbits.SENDB // bit 3
7749 #define SYNC TX1STAbits.SYNC // bit 4
7750 #define TXEN TX1STAbits.TXEN // bit 5
7751 #define TX9 TX1STAbits.TX9 // bit 6
7752 #define CSRC TX1STAbits.CSRC // bit 7
7754 #define TXPPS0 TXPPSbits.TXPPS0 // bit 0
7755 #define TXPPS1 TXPPSbits.TXPPS1 // bit 1
7756 #define TXPPS2 TXPPSbits.TXPPS2 // bit 2
7757 #define TXPPS3 TXPPSbits.TXPPS3 // bit 3
7758 #define TXPPS4 TXPPSbits.TXPPS4 // bit 4
7760 #define VREGPM VREGCONbits.VREGPM // bit 1
7762 #define SWDTEN WDTCONbits.SWDTEN // bit 0
7763 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
7764 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
7765 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
7766 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
7767 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
7769 #define WPUA0 WPUAbits.WPUA0 // bit 0
7770 #define WPUA1 WPUAbits.WPUA1 // bit 1
7771 #define WPUA2 WPUAbits.WPUA2 // bit 2
7772 #define WPUA3 WPUAbits.WPUA3 // bit 3
7773 #define WPUA4 WPUAbits.WPUA4 // bit 4
7774 #define WPUA5 WPUAbits.WPUA5 // bit 5
7776 #endif // #ifndef NO_BIT_DEFINES
7778 #endif // #ifndef __PIC16F18313_H__