2 * This declarations of the PIC16F18323 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:23 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F18323_H__
26 #define __PIC16F18323_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTC_ADDR 0x000E
52 #define PIR0_ADDR 0x0010
53 #define PIR1_ADDR 0x0011
54 #define PIR2_ADDR 0x0012
55 #define PIR3_ADDR 0x0013
56 #define PIR4_ADDR 0x0014
57 #define TMR0L_ADDR 0x0015
58 #define TMR0H_ADDR 0x0016
59 #define T0CON0_ADDR 0x0017
60 #define T0CON1_ADDR 0x0018
61 #define TMR1_ADDR 0x0019
62 #define TMR1L_ADDR 0x0019
63 #define TMR1H_ADDR 0x001A
64 #define T1CON_ADDR 0x001B
65 #define T1GCON_ADDR 0x001C
66 #define TMR2_ADDR 0x001D
67 #define PR2_ADDR 0x001E
68 #define T2CON_ADDR 0x001F
69 #define TRISA_ADDR 0x008C
70 #define TRISC_ADDR 0x008E
71 #define PIE0_ADDR 0x0090
72 #define PIE1_ADDR 0x0091
73 #define PIE2_ADDR 0x0092
74 #define PIE3_ADDR 0x0093
75 #define PIE4_ADDR 0x0094
76 #define WDTCON_ADDR 0x0097
77 #define ADRES_ADDR 0x009B
78 #define ADRESL_ADDR 0x009B
79 #define ADRESH_ADDR 0x009C
80 #define ADCON0_ADDR 0x009D
81 #define ADCON1_ADDR 0x009E
82 #define ADACT_ADDR 0x009F
83 #define LATA_ADDR 0x010C
84 #define LATC_ADDR 0x010E
85 #define CM1CON0_ADDR 0x0111
86 #define CM1CON1_ADDR 0x0112
87 #define CM2CON0_ADDR 0x0113
88 #define CM2CON1_ADDR 0x0114
89 #define CMOUT_ADDR 0x0115
90 #define BORCON_ADDR 0x0116
91 #define FVRCON_ADDR 0x0117
92 #define DACCON0_ADDR 0x0118
93 #define DACCON1_ADDR 0x0119
94 #define ANSELA_ADDR 0x018C
95 #define ANSELC_ADDR 0x018E
96 #define VREGCON_ADDR 0x0197
97 #define RC1REG_ADDR 0x0199
98 #define RCREG_ADDR 0x0199
99 #define RCREG1_ADDR 0x0199
100 #define TX1REG_ADDR 0x019A
101 #define TXREG_ADDR 0x019A
102 #define TXREG1_ADDR 0x019A
103 #define SP1BRG_ADDR 0x019B
104 #define SP1BRGL_ADDR 0x019B
105 #define SPBRG_ADDR 0x019B
106 #define SPBRG1_ADDR 0x019B
107 #define SPBRGL_ADDR 0x019B
108 #define SP1BRGH_ADDR 0x019C
109 #define SPBRGH_ADDR 0x019C
110 #define SPBRGH1_ADDR 0x019C
111 #define RC1STA_ADDR 0x019D
112 #define RCSTA_ADDR 0x019D
113 #define RCSTA1_ADDR 0x019D
114 #define TX1STA_ADDR 0x019E
115 #define TXSTA_ADDR 0x019E
116 #define TXSTA1_ADDR 0x019E
117 #define BAUD1CON_ADDR 0x019F
118 #define BAUDCON_ADDR 0x019F
119 #define BAUDCON1_ADDR 0x019F
120 #define BAUDCTL_ADDR 0x019F
121 #define BAUDCTL1_ADDR 0x019F
122 #define WPUA_ADDR 0x020C
123 #define WPUC_ADDR 0x020E
124 #define SSP1BUF_ADDR 0x0211
125 #define SSPBUF_ADDR 0x0211
126 #define SSP1ADD_ADDR 0x0212
127 #define SSPADD_ADDR 0x0212
128 #define SSP1MSK_ADDR 0x0213
129 #define SSPMSK_ADDR 0x0213
130 #define SSP1STAT_ADDR 0x0214
131 #define SSPSTAT_ADDR 0x0214
132 #define SSP1CON_ADDR 0x0215
133 #define SSP1CON1_ADDR 0x0215
134 #define SSPCON_ADDR 0x0215
135 #define SSPCON1_ADDR 0x0215
136 #define SSP1CON2_ADDR 0x0216
137 #define SSPCON2_ADDR 0x0216
138 #define SSP1CON3_ADDR 0x0217
139 #define SSPCON3_ADDR 0x0217
140 #define ODCONA_ADDR 0x028C
141 #define ODCONC_ADDR 0x028E
142 #define CCPR1_ADDR 0x0291
143 #define CCPR1L_ADDR 0x0291
144 #define CCPR1H_ADDR 0x0292
145 #define CCP1CON_ADDR 0x0293
146 #define CCP1CAP_ADDR 0x0294
147 #define CCPR2_ADDR 0x0295
148 #define CCPR2L_ADDR 0x0295
149 #define CCPR2H_ADDR 0x0296
150 #define CCP2CON_ADDR 0x0297
151 #define CCP2CAP_ADDR 0x0298
152 #define CCPTMRS_ADDR 0x029F
153 #define SLRCONA_ADDR 0x030C
154 #define SLRCONC_ADDR 0x030E
155 #define INLVLA_ADDR 0x038C
156 #define INLVLC_ADDR 0x038E
157 #define IOCAP_ADDR 0x0391
158 #define IOCAN_ADDR 0x0392
159 #define IOCAF_ADDR 0x0393
160 #define IOCCP_ADDR 0x0397
161 #define IOCCN_ADDR 0x0398
162 #define IOCCF_ADDR 0x0399
163 #define CLKRCON_ADDR 0x039A
164 #define MDCON_ADDR 0x039C
165 #define MDSRC_ADDR 0x039D
166 #define MDCARH_ADDR 0x039E
167 #define MDCARL_ADDR 0x039F
168 #define CCDNA_ADDR 0x040C
169 #define CCDNC_ADDR 0x040E
170 #define CCDCON_ADDR 0x041F
171 #define CCDPA_ADDR 0x048C
172 #define CCDPC_ADDR 0x048E
173 #define NCO1ACC_ADDR 0x0498
174 #define NCO1ACCL_ADDR 0x0498
175 #define NCO1ACCH_ADDR 0x0499
176 #define NCO1ACCU_ADDR 0x049A
177 #define NCO1INC_ADDR 0x049B
178 #define NCO1INCL_ADDR 0x049B
179 #define NCO1INCH_ADDR 0x049C
180 #define NCO1INCU_ADDR 0x049D
181 #define NCO1CON_ADDR 0x049E
182 #define NCO1CLK_ADDR 0x049F
183 #define PWM5DCL_ADDR 0x0617
184 #define PWM5DCH_ADDR 0x0618
185 #define PWM5CON_ADDR 0x0619
186 #define PWM5CON0_ADDR 0x0619
187 #define PWM6DCL_ADDR 0x061A
188 #define PWM6DCH_ADDR 0x061B
189 #define PWM6CON_ADDR 0x061C
190 #define PWM6CON0_ADDR 0x061C
191 #define CWG1CLKCON_ADDR 0x0691
192 #define CWG1DAT_ADDR 0x0692
193 #define CWG1DBR_ADDR 0x0693
194 #define CWG1DBF_ADDR 0x0694
195 #define CWG1CON0_ADDR 0x0695
196 #define CWG1CON1_ADDR 0x0696
197 #define CWG1AS0_ADDR 0x0697
198 #define CWG1AS1_ADDR 0x0698
199 #define CWG1STR_ADDR 0x0699
200 #define NVMADR_ADDR 0x0891
201 #define NVMADRL_ADDR 0x0891
202 #define NVMADRH_ADDR 0x0892
203 #define NVMDAT_ADDR 0x0893
204 #define NVMDATL_ADDR 0x0893
205 #define NVMDATH_ADDR 0x0894
206 #define NVMCON1_ADDR 0x0895
207 #define NVMCON2_ADDR 0x0896
208 #define PCON0_ADDR 0x089B
209 #define PMD0_ADDR 0x0911
210 #define PMD1_ADDR 0x0912
211 #define PMD2_ADDR 0x0913
212 #define PMD3_ADDR 0x0914
213 #define PMD4_ADDR 0x0915
214 #define PMD5_ADDR 0x0916
215 #define CPUDOZE_ADDR 0x0918
216 #define OSCCON1_ADDR 0x0919
217 #define OSCCON2_ADDR 0x091A
218 #define OSCCON3_ADDR 0x091B
219 #define OSCSTAT1_ADDR 0x091C
220 #define OSCEN_ADDR 0x091D
221 #define OSCTUNE_ADDR 0x091E
222 #define OSCFRQ_ADDR 0x091F
223 #define PPSLOCK_ADDR 0x0E0F
224 #define INTPPS_ADDR 0x0E10
225 #define T0CKIPPS_ADDR 0x0E11
226 #define T1CKIPPS_ADDR 0x0E12
227 #define T1GPPS_ADDR 0x0E13
228 #define CCP1PPS_ADDR 0x0E14
229 #define CCP2PPS_ADDR 0x0E15
230 #define CWG1PPS_ADDR 0x0E18
231 #define MDCIN1PPS_ADDR 0x0E1A
232 #define MDCIN2PPS_ADDR 0x0E1B
233 #define MDMINPPS_ADDR 0x0E1C
234 #define SSP1CLKPPS_ADDR 0x0E20
235 #define SSP1DATPPS_ADDR 0x0E21
236 #define SSP1SSPPS_ADDR 0x0E22
237 #define RXPPS_ADDR 0x0E24
238 #define TXPPS_ADDR 0x0E25
239 #define CLCIN0PPS_ADDR 0x0E28
240 #define CLCIN1PPS_ADDR 0x0E29
241 #define CLCIN2PPS_ADDR 0x0E2A
242 #define CLCIN3PPS_ADDR 0x0E2B
243 #define RA0PPS_ADDR 0x0E90
244 #define RA1PPS_ADDR 0x0E91
245 #define RA2PPS_ADDR 0x0E92
246 #define RA4PPS_ADDR 0x0E94
247 #define RA5PPS_ADDR 0x0E95
248 #define RC0PPS_ADDR 0x0EA0
249 #define RC1PPS_ADDR 0x0EA1
250 #define RC2PPS_ADDR 0x0EA2
251 #define RC3PPS_ADDR 0x0EA3
252 #define RC4PPS_ADDR 0x0EA4
253 #define RC5PPS_ADDR 0x0EA5
254 #define CLCDATA_ADDR 0x0F0F
255 #define CLC1CON_ADDR 0x0F10
256 #define CLC1POL_ADDR 0x0F11
257 #define CLC1SEL0_ADDR 0x0F12
258 #define CLC1SEL1_ADDR 0x0F13
259 #define CLC1SEL2_ADDR 0x0F14
260 #define CLC1SEL3_ADDR 0x0F15
261 #define CLC1GLS0_ADDR 0x0F16
262 #define CLC1GLS1_ADDR 0x0F17
263 #define CLC1GLS2_ADDR 0x0F18
264 #define CLC1GLS3_ADDR 0x0F19
265 #define CLC2CON_ADDR 0x0F1A
266 #define CLC2POL_ADDR 0x0F1B
267 #define CLC2SEL0_ADDR 0x0F1C
268 #define CLC2SEL1_ADDR 0x0F1D
269 #define CLC2SEL2_ADDR 0x0F1E
270 #define CLC2SEL3_ADDR 0x0F1F
271 #define CLC2GLS0_ADDR 0x0F20
272 #define CLC2GLS1_ADDR 0x0F21
273 #define CLC2GLS2_ADDR 0x0F22
274 #define CLC2GLS3_ADDR 0x0F23
275 #define STATUS_SHAD_ADDR 0x0FE4
276 #define WREG_SHAD_ADDR 0x0FE5
277 #define BSR_SHAD_ADDR 0x0FE6
278 #define PCLATH_SHAD_ADDR 0x0FE7
279 #define FSR0L_SHAD_ADDR 0x0FE8
280 #define FSR0H_SHAD_ADDR 0x0FE9
281 #define FSR1L_SHAD_ADDR 0x0FEA
282 #define FSR1H_SHAD_ADDR 0x0FEB
283 #define STKPTR_ADDR 0x0FED
284 #define TOSL_ADDR 0x0FEE
285 #define TOSH_ADDR 0x0FEF
287 #endif // #ifndef NO_ADDR_DEFINES
289 //==============================================================================
291 // Register Definitions
293 //==============================================================================
295 extern __at(0x0000) __sfr INDF0
;
296 extern __at(0x0001) __sfr INDF1
;
297 extern __at(0x0002) __sfr PCL
;
299 //==============================================================================
302 extern __at(0x0003) __sfr STATUS
;
316 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
324 //==============================================================================
326 extern __at(0x0004) __sfr FSR0
;
327 extern __at(0x0004) __sfr FSR0L
;
328 extern __at(0x0005) __sfr FSR0H
;
329 extern __at(0x0006) __sfr FSR1
;
330 extern __at(0x0006) __sfr FSR1L
;
331 extern __at(0x0007) __sfr FSR1H
;
333 //==============================================================================
336 extern __at(0x0008) __sfr BSR
;
359 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
367 //==============================================================================
369 extern __at(0x0009) __sfr WREG
;
370 extern __at(0x000A) __sfr PCLATH
;
372 //==============================================================================
375 extern __at(0x000B) __sfr INTCON
;
389 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
395 //==============================================================================
398 //==============================================================================
401 extern __at(0x000C) __sfr PORTA
;
424 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
433 //==============================================================================
436 //==============================================================================
439 extern __at(0x000E) __sfr PORTC
;
462 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
471 //==============================================================================
474 //==============================================================================
477 extern __at(0x0010) __sfr PIR0
;
491 extern __at(0x0010) volatile __PIR0bits_t PIR0bits
;
497 //==============================================================================
500 //==============================================================================
503 extern __at(0x0011) __sfr PIR1
;
514 unsigned TMR1GIF
: 1;
517 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
526 #define _TMR1GIF 0x80
528 //==============================================================================
531 //==============================================================================
534 extern __at(0x0012) __sfr PIR2
;
548 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
555 //==============================================================================
558 //==============================================================================
561 extern __at(0x0013) __sfr PIR3
;
575 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
582 //==============================================================================
585 //==============================================================================
588 extern __at(0x0014) __sfr PIR4
;
602 extern __at(0x0014) volatile __PIR4bits_t PIR4bits
;
608 //==============================================================================
611 //==============================================================================
614 extern __at(0x0015) __sfr TMR0L
;
628 extern __at(0x0015) volatile __TMR0Lbits_t TMR0Lbits
;
639 //==============================================================================
642 //==============================================================================
645 extern __at(0x0016) __sfr TMR0H
;
659 extern __at(0x0016) volatile __TMR0Hbits_t TMR0Hbits
;
670 //==============================================================================
673 //==============================================================================
676 extern __at(0x0017) __sfr T0CON0
;
682 unsigned T0OUTPS0
: 1;
683 unsigned T0OUTPS1
: 1;
684 unsigned T0OUTPS2
: 1;
685 unsigned T0OUTPS3
: 1;
686 unsigned T016BIT
: 1;
694 unsigned T0OUTPS
: 4;
699 extern __at(0x0017) volatile __T0CON0bits_t T0CON0bits
;
701 #define _T0OUTPS0 0x01
702 #define _T0OUTPS1 0x02
703 #define _T0OUTPS2 0x04
704 #define _T0OUTPS3 0x08
705 #define _T016BIT 0x10
709 //==============================================================================
712 //==============================================================================
715 extern __at(0x0018) __sfr T0CON1
;
721 unsigned T0CKPS0
: 1;
722 unsigned T0CKPS1
: 1;
723 unsigned T0CKPS2
: 1;
724 unsigned T0CKPS3
: 1;
725 unsigned T0ASYNC
: 1;
744 extern __at(0x0018) volatile __T0CON1bits_t T0CON1bits
;
746 #define _T0CKPS0 0x01
747 #define _T0CKPS1 0x02
748 #define _T0CKPS2 0x04
749 #define _T0CKPS3 0x08
750 #define _T0ASYNC 0x10
755 //==============================================================================
757 extern __at(0x0019) __sfr TMR1
;
758 extern __at(0x0019) __sfr TMR1L
;
759 extern __at(0x001A) __sfr TMR1H
;
761 //==============================================================================
764 extern __at(0x001B) __sfr T1CON
;
774 unsigned T1CKPS0
: 1;
775 unsigned T1CKPS1
: 1;
776 unsigned TMR1CS0
: 1;
777 unsigned TMR1CS1
: 1;
794 extern __at(0x001B) volatile __T1CONbits_t T1CONbits
;
799 #define _T1CKPS0 0x10
800 #define _T1CKPS1 0x20
801 #define _TMR1CS0 0x40
802 #define _TMR1CS1 0x80
804 //==============================================================================
807 //==============================================================================
810 extern __at(0x001C) __sfr T1GCON
;
819 unsigned T1GGO_NOT_DONE
: 1;
833 extern __at(0x001C) volatile __T1GCONbits_t T1GCONbits
;
838 #define _T1GGO_NOT_DONE 0x08
844 //==============================================================================
846 extern __at(0x001D) __sfr TMR2
;
847 extern __at(0x001E) __sfr PR2
;
849 //==============================================================================
852 extern __at(0x001F) __sfr T2CON
;
858 unsigned T2CKPS0
: 1;
859 unsigned T2CKPS1
: 1;
861 unsigned T2OUTPS0
: 1;
862 unsigned T2OUTPS1
: 1;
863 unsigned T2OUTPS2
: 1;
864 unsigned T2OUTPS3
: 1;
877 unsigned T2OUTPS
: 4;
882 extern __at(0x001F) volatile __T2CONbits_t T2CONbits
;
884 #define _T2CKPS0 0x01
885 #define _T2CKPS1 0x02
887 #define _T2OUTPS0 0x08
888 #define _T2OUTPS1 0x10
889 #define _T2OUTPS2 0x20
890 #define _T2OUTPS3 0x40
892 //==============================================================================
895 //==============================================================================
898 extern __at(0x008C) __sfr TRISA
;
912 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
920 //==============================================================================
923 //==============================================================================
926 extern __at(0x008E) __sfr TRISC
;
949 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
958 //==============================================================================
961 //==============================================================================
964 extern __at(0x0090) __sfr PIE0
;
978 extern __at(0x0090) volatile __PIE0bits_t PIE0bits
;
984 //==============================================================================
987 //==============================================================================
990 extern __at(0x0091) __sfr PIE1
;
1001 unsigned TMR1GIE
: 1;
1004 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
1006 #define _TMR1IE 0x01
1007 #define _TMR2IE 0x02
1008 #define _BCL1IE 0x04
1009 #define _SSP1IE 0x08
1013 #define _TMR1GIE 0x80
1015 //==============================================================================
1018 //==============================================================================
1021 extern __at(0x0092) __sfr PIE2
;
1025 unsigned NCO1IE
: 1;
1035 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
1037 #define _NCO1IE 0x01
1042 //==============================================================================
1045 //==============================================================================
1048 extern __at(0x0093) __sfr PIE3
;
1052 unsigned CLC1IE
: 1;
1053 unsigned CLC2IE
: 1;
1062 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
1064 #define _CLC1IE 0x01
1065 #define _CLC2IE 0x02
1069 //==============================================================================
1072 //==============================================================================
1075 extern __at(0x0094) __sfr PIE4
;
1079 unsigned CCP1IE
: 1;
1080 unsigned CCP2IE
: 1;
1085 unsigned CWG1IE
: 1;
1089 extern __at(0x0094) volatile __PIE4bits_t PIE4bits
;
1091 #define _CCP1IE 0x01
1092 #define _CCP2IE 0x02
1093 #define _CWG1IE 0x40
1095 //==============================================================================
1098 //==============================================================================
1101 extern __at(0x0097) __sfr WDTCON
;
1107 unsigned SWDTEN
: 1;
1108 unsigned WDTPS0
: 1;
1109 unsigned WDTPS1
: 1;
1110 unsigned WDTPS2
: 1;
1111 unsigned WDTPS3
: 1;
1112 unsigned WDTPS4
: 1;
1125 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1127 #define _SWDTEN 0x01
1128 #define _WDTPS0 0x02
1129 #define _WDTPS1 0x04
1130 #define _WDTPS2 0x08
1131 #define _WDTPS3 0x10
1132 #define _WDTPS4 0x20
1134 //==============================================================================
1136 extern __at(0x009B) __sfr ADRES
;
1137 extern __at(0x009B) __sfr ADRESL
;
1138 extern __at(0x009C) __sfr ADRESH
;
1140 //==============================================================================
1143 extern __at(0x009D) __sfr ADCON0
;
1150 unsigned GO_NOT_DONE
: 1;
1190 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1193 #define _GO_NOT_DONE 0x02
1203 //==============================================================================
1206 //==============================================================================
1209 extern __at(0x009E) __sfr ADCON1
;
1215 unsigned ADPREF0
: 1;
1216 unsigned ADPREF1
: 1;
1217 unsigned ADNREF
: 1;
1227 unsigned ADPREF
: 2;
1239 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1241 #define _ADPREF0 0x01
1242 #define _ADPREF1 0x02
1243 #define _ADNREF 0x04
1249 //==============================================================================
1252 //==============================================================================
1255 extern __at(0x009F) __sfr ADACT
;
1261 unsigned ADACT0
: 1;
1262 unsigned ADACT1
: 1;
1263 unsigned ADACT2
: 1;
1264 unsigned ADACT3
: 1;
1278 extern __at(0x009F) volatile __ADACTbits_t ADACTbits
;
1280 #define _ADACT0 0x01
1281 #define _ADACT1 0x02
1282 #define _ADACT2 0x04
1283 #define _ADACT3 0x08
1285 //==============================================================================
1288 //==============================================================================
1291 extern __at(0x010C) __sfr LATA
;
1305 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1313 //==============================================================================
1316 //==============================================================================
1319 extern __at(0x010E) __sfr LATC
;
1342 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1351 //==============================================================================
1354 //==============================================================================
1357 extern __at(0x0111) __sfr CM1CON0
;
1361 unsigned C1SYNC
: 1;
1371 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1373 #define _C1SYNC 0x01
1380 //==============================================================================
1383 //==============================================================================
1386 extern __at(0x0112) __sfr CM1CON1
;
1392 unsigned C1NCH0
: 1;
1393 unsigned C1NCH1
: 1;
1394 unsigned C1NCH2
: 1;
1395 unsigned C1PCH0
: 1;
1396 unsigned C1PCH1
: 1;
1397 unsigned C1PCH2
: 1;
1398 unsigned C1INTN
: 1;
1399 unsigned C1INTP
: 1;
1416 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1418 #define _C1NCH0 0x01
1419 #define _C1NCH1 0x02
1420 #define _C1NCH2 0x04
1421 #define _C1PCH0 0x08
1422 #define _C1PCH1 0x10
1423 #define _C1PCH2 0x20
1424 #define _C1INTN 0x40
1425 #define _C1INTP 0x80
1427 //==============================================================================
1430 //==============================================================================
1433 extern __at(0x0113) __sfr CM2CON0
;
1437 unsigned C2SYNC
: 1;
1447 extern __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits
;
1449 #define _C2SYNC 0x01
1456 //==============================================================================
1459 //==============================================================================
1462 extern __at(0x0114) __sfr CM2CON1
;
1468 unsigned C2NCH0
: 1;
1469 unsigned C2NCH1
: 1;
1470 unsigned C2NCH2
: 1;
1471 unsigned C2PCH0
: 1;
1472 unsigned C2PCH1
: 1;
1473 unsigned C2PCH2
: 1;
1474 unsigned C2INTN
: 1;
1475 unsigned C2INTP
: 1;
1492 extern __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits
;
1494 #define _C2NCH0 0x01
1495 #define _C2NCH1 0x02
1496 #define _C2NCH2 0x04
1497 #define _C2PCH0 0x08
1498 #define _C2PCH1 0x10
1499 #define _C2PCH2 0x20
1500 #define _C2INTN 0x40
1501 #define _C2INTP 0x80
1503 //==============================================================================
1506 //==============================================================================
1509 extern __at(0x0115) __sfr CMOUT
;
1513 unsigned MC1OUT
: 1;
1514 unsigned MC2OUT
: 1;
1523 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1525 #define _MC1OUT 0x01
1526 #define _MC2OUT 0x02
1528 //==============================================================================
1531 //==============================================================================
1534 extern __at(0x0116) __sfr BORCON
;
1538 unsigned BORRDY
: 1;
1545 unsigned SBOREN
: 1;
1548 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1550 #define _BORRDY 0x01
1551 #define _SBOREN 0x80
1553 //==============================================================================
1556 //==============================================================================
1559 extern __at(0x0117) __sfr FVRCON
;
1565 unsigned ADFVR0
: 1;
1566 unsigned ADFVR1
: 1;
1567 unsigned CDAFVR0
: 1;
1568 unsigned CDAFVR1
: 1;
1571 unsigned FVRRDY
: 1;
1584 unsigned CDAFVR
: 2;
1589 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1591 #define _ADFVR0 0x01
1592 #define _ADFVR1 0x02
1593 #define _CDAFVR0 0x04
1594 #define _CDAFVR1 0x08
1597 #define _FVRRDY 0x40
1600 //==============================================================================
1603 //==============================================================================
1606 extern __at(0x0118) __sfr DACCON0
;
1612 unsigned DAC1NSS
: 1;
1614 unsigned DAC1PSS0
: 1;
1615 unsigned DAC1PSS1
: 1;
1617 unsigned DAC1OE
: 1;
1619 unsigned DAC1EN
: 1;
1625 unsigned DAC1PSS
: 2;
1630 extern __at(0x0118) volatile __DACCON0bits_t DACCON0bits
;
1632 #define _DAC1NSS 0x01
1633 #define _DAC1PSS0 0x04
1634 #define _DAC1PSS1 0x08
1635 #define _DAC1OE 0x20
1636 #define _DAC1EN 0x80
1638 //==============================================================================
1641 //==============================================================================
1644 extern __at(0x0119) __sfr DACCON1
;
1650 unsigned DAC1R0
: 1;
1651 unsigned DAC1R1
: 1;
1652 unsigned DAC1R2
: 1;
1653 unsigned DAC1R3
: 1;
1654 unsigned DAC1R4
: 1;
1667 extern __at(0x0119) volatile __DACCON1bits_t DACCON1bits
;
1669 #define _DAC1R0 0x01
1670 #define _DAC1R1 0x02
1671 #define _DAC1R2 0x04
1672 #define _DAC1R3 0x08
1673 #define _DAC1R4 0x10
1675 //==============================================================================
1678 //==============================================================================
1681 extern __at(0x018C) __sfr ANSELA
;
1695 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1703 //==============================================================================
1706 //==============================================================================
1709 extern __at(0x018E) __sfr ANSELC
;
1732 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
1741 //==============================================================================
1744 //==============================================================================
1747 extern __at(0x0197) __sfr VREGCON
;
1752 unsigned VREGPM
: 1;
1761 extern __at(0x0197) volatile __VREGCONbits_t VREGCONbits
;
1763 #define _VREGPM 0x02
1765 //==============================================================================
1767 extern __at(0x0199) __sfr RC1REG
;
1768 extern __at(0x0199) __sfr RCREG
;
1769 extern __at(0x0199) __sfr RCREG1
;
1770 extern __at(0x019A) __sfr TX1REG
;
1771 extern __at(0x019A) __sfr TXREG
;
1772 extern __at(0x019A) __sfr TXREG1
;
1773 extern __at(0x019B) __sfr SP1BRG
;
1774 extern __at(0x019B) __sfr SP1BRGL
;
1775 extern __at(0x019B) __sfr SPBRG
;
1776 extern __at(0x019B) __sfr SPBRG1
;
1777 extern __at(0x019B) __sfr SPBRGL
;
1778 extern __at(0x019C) __sfr SP1BRGH
;
1779 extern __at(0x019C) __sfr SPBRGH
;
1780 extern __at(0x019C) __sfr SPBRGH1
;
1782 //==============================================================================
1785 extern __at(0x019D) __sfr RC1STA
;
1799 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
1810 //==============================================================================
1813 //==============================================================================
1816 extern __at(0x019D) __sfr RCSTA
;
1830 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
1832 #define _RCSTA_RX9D 0x01
1833 #define _RCSTA_OERR 0x02
1834 #define _RCSTA_FERR 0x04
1835 #define _RCSTA_ADDEN 0x08
1836 #define _RCSTA_CREN 0x10
1837 #define _RCSTA_SREN 0x20
1838 #define _RCSTA_RX9 0x40
1839 #define _RCSTA_SPEN 0x80
1841 //==============================================================================
1844 //==============================================================================
1847 extern __at(0x019D) __sfr RCSTA1
;
1861 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
1863 #define _RCSTA1_RX9D 0x01
1864 #define _RCSTA1_OERR 0x02
1865 #define _RCSTA1_FERR 0x04
1866 #define _RCSTA1_ADDEN 0x08
1867 #define _RCSTA1_CREN 0x10
1868 #define _RCSTA1_SREN 0x20
1869 #define _RCSTA1_RX9 0x40
1870 #define _RCSTA1_SPEN 0x80
1872 //==============================================================================
1875 //==============================================================================
1878 extern __at(0x019E) __sfr TX1STA
;
1892 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
1903 //==============================================================================
1906 //==============================================================================
1909 extern __at(0x019E) __sfr TXSTA
;
1923 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
1925 #define _TXSTA_TX9D 0x01
1926 #define _TXSTA_TRMT 0x02
1927 #define _TXSTA_BRGH 0x04
1928 #define _TXSTA_SENDB 0x08
1929 #define _TXSTA_SYNC 0x10
1930 #define _TXSTA_TXEN 0x20
1931 #define _TXSTA_TX9 0x40
1932 #define _TXSTA_CSRC 0x80
1934 //==============================================================================
1937 //==============================================================================
1940 extern __at(0x019E) __sfr TXSTA1
;
1954 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
1956 #define _TXSTA1_TX9D 0x01
1957 #define _TXSTA1_TRMT 0x02
1958 #define _TXSTA1_BRGH 0x04
1959 #define _TXSTA1_SENDB 0x08
1960 #define _TXSTA1_SYNC 0x10
1961 #define _TXSTA1_TXEN 0x20
1962 #define _TXSTA1_TX9 0x40
1963 #define _TXSTA1_CSRC 0x80
1965 //==============================================================================
1968 //==============================================================================
1971 extern __at(0x019F) __sfr BAUD1CON
;
1982 unsigned ABDOVF
: 1;
1985 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
1992 #define _ABDOVF 0x80
1994 //==============================================================================
1997 //==============================================================================
2000 extern __at(0x019F) __sfr BAUDCON
;
2011 unsigned ABDOVF
: 1;
2014 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
2016 #define _BAUDCON_ABDEN 0x01
2017 #define _BAUDCON_WUE 0x02
2018 #define _BAUDCON_BRG16 0x08
2019 #define _BAUDCON_SCKP 0x10
2020 #define _BAUDCON_RCIDL 0x40
2021 #define _BAUDCON_ABDOVF 0x80
2023 //==============================================================================
2026 //==============================================================================
2029 extern __at(0x019F) __sfr BAUDCON1
;
2040 unsigned ABDOVF
: 1;
2043 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
2045 #define _BAUDCON1_ABDEN 0x01
2046 #define _BAUDCON1_WUE 0x02
2047 #define _BAUDCON1_BRG16 0x08
2048 #define _BAUDCON1_SCKP 0x10
2049 #define _BAUDCON1_RCIDL 0x40
2050 #define _BAUDCON1_ABDOVF 0x80
2052 //==============================================================================
2055 //==============================================================================
2058 extern __at(0x019F) __sfr BAUDCTL
;
2069 unsigned ABDOVF
: 1;
2072 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
2074 #define _BAUDCTL_ABDEN 0x01
2075 #define _BAUDCTL_WUE 0x02
2076 #define _BAUDCTL_BRG16 0x08
2077 #define _BAUDCTL_SCKP 0x10
2078 #define _BAUDCTL_RCIDL 0x40
2079 #define _BAUDCTL_ABDOVF 0x80
2081 //==============================================================================
2084 //==============================================================================
2087 extern __at(0x019F) __sfr BAUDCTL1
;
2098 unsigned ABDOVF
: 1;
2101 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
2103 #define _BAUDCTL1_ABDEN 0x01
2104 #define _BAUDCTL1_WUE 0x02
2105 #define _BAUDCTL1_BRG16 0x08
2106 #define _BAUDCTL1_SCKP 0x10
2107 #define _BAUDCTL1_RCIDL 0x40
2108 #define _BAUDCTL1_ABDOVF 0x80
2110 //==============================================================================
2113 //==============================================================================
2116 extern __at(0x020C) __sfr WPUA
;
2139 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
2148 //==============================================================================
2151 //==============================================================================
2154 extern __at(0x020E) __sfr WPUC
;
2177 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
2186 //==============================================================================
2189 //==============================================================================
2192 extern __at(0x0211) __sfr SSP1BUF
;
2198 unsigned SSP1BUF0
: 1;
2199 unsigned SSP1BUF1
: 1;
2200 unsigned SSP1BUF2
: 1;
2201 unsigned SSP1BUF3
: 1;
2202 unsigned SSP1BUF4
: 1;
2203 unsigned SSP1BUF5
: 1;
2204 unsigned SSP1BUF6
: 1;
2205 unsigned SSP1BUF7
: 1;
2221 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
2223 #define _SSP1BUF0 0x01
2225 #define _SSP1BUF1 0x02
2227 #define _SSP1BUF2 0x04
2229 #define _SSP1BUF3 0x08
2231 #define _SSP1BUF4 0x10
2233 #define _SSP1BUF5 0x20
2235 #define _SSP1BUF6 0x40
2237 #define _SSP1BUF7 0x80
2240 //==============================================================================
2243 //==============================================================================
2246 extern __at(0x0211) __sfr SSPBUF
;
2252 unsigned SSP1BUF0
: 1;
2253 unsigned SSP1BUF1
: 1;
2254 unsigned SSP1BUF2
: 1;
2255 unsigned SSP1BUF3
: 1;
2256 unsigned SSP1BUF4
: 1;
2257 unsigned SSP1BUF5
: 1;
2258 unsigned SSP1BUF6
: 1;
2259 unsigned SSP1BUF7
: 1;
2275 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
2277 #define _SSPBUF_SSP1BUF0 0x01
2278 #define _SSPBUF_BUF0 0x01
2279 #define _SSPBUF_SSP1BUF1 0x02
2280 #define _SSPBUF_BUF1 0x02
2281 #define _SSPBUF_SSP1BUF2 0x04
2282 #define _SSPBUF_BUF2 0x04
2283 #define _SSPBUF_SSP1BUF3 0x08
2284 #define _SSPBUF_BUF3 0x08
2285 #define _SSPBUF_SSP1BUF4 0x10
2286 #define _SSPBUF_BUF4 0x10
2287 #define _SSPBUF_SSP1BUF5 0x20
2288 #define _SSPBUF_BUF5 0x20
2289 #define _SSPBUF_SSP1BUF6 0x40
2290 #define _SSPBUF_BUF6 0x40
2291 #define _SSPBUF_SSP1BUF7 0x80
2292 #define _SSPBUF_BUF7 0x80
2294 //==============================================================================
2297 //==============================================================================
2300 extern __at(0x0212) __sfr SSP1ADD
;
2306 unsigned SSP1ADD0
: 1;
2307 unsigned SSP1ADD1
: 1;
2308 unsigned SSP1ADD2
: 1;
2309 unsigned SSP1ADD3
: 1;
2310 unsigned SSP1ADD4
: 1;
2311 unsigned SSP1ADD5
: 1;
2312 unsigned SSP1ADD6
: 1;
2313 unsigned SSP1ADD7
: 1;
2329 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
2331 #define _SSP1ADD0 0x01
2333 #define _SSP1ADD1 0x02
2335 #define _SSP1ADD2 0x04
2337 #define _SSP1ADD3 0x08
2339 #define _SSP1ADD4 0x10
2341 #define _SSP1ADD5 0x20
2343 #define _SSP1ADD6 0x40
2345 #define _SSP1ADD7 0x80
2348 //==============================================================================
2351 //==============================================================================
2354 extern __at(0x0212) __sfr SSPADD
;
2360 unsigned SSP1ADD0
: 1;
2361 unsigned SSP1ADD1
: 1;
2362 unsigned SSP1ADD2
: 1;
2363 unsigned SSP1ADD3
: 1;
2364 unsigned SSP1ADD4
: 1;
2365 unsigned SSP1ADD5
: 1;
2366 unsigned SSP1ADD6
: 1;
2367 unsigned SSP1ADD7
: 1;
2383 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
2385 #define _SSPADD_SSP1ADD0 0x01
2386 #define _SSPADD_ADD0 0x01
2387 #define _SSPADD_SSP1ADD1 0x02
2388 #define _SSPADD_ADD1 0x02
2389 #define _SSPADD_SSP1ADD2 0x04
2390 #define _SSPADD_ADD2 0x04
2391 #define _SSPADD_SSP1ADD3 0x08
2392 #define _SSPADD_ADD3 0x08
2393 #define _SSPADD_SSP1ADD4 0x10
2394 #define _SSPADD_ADD4 0x10
2395 #define _SSPADD_SSP1ADD5 0x20
2396 #define _SSPADD_ADD5 0x20
2397 #define _SSPADD_SSP1ADD6 0x40
2398 #define _SSPADD_ADD6 0x40
2399 #define _SSPADD_SSP1ADD7 0x80
2400 #define _SSPADD_ADD7 0x80
2402 //==============================================================================
2405 //==============================================================================
2408 extern __at(0x0213) __sfr SSP1MSK
;
2414 unsigned SSP1MSK0
: 1;
2415 unsigned SSP1MSK1
: 1;
2416 unsigned SSP1MSK2
: 1;
2417 unsigned SSP1MSK3
: 1;
2418 unsigned SSP1MSK4
: 1;
2419 unsigned SSP1MSK5
: 1;
2420 unsigned SSP1MSK6
: 1;
2421 unsigned SSP1MSK7
: 1;
2437 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
2439 #define _SSP1MSK0 0x01
2441 #define _SSP1MSK1 0x02
2443 #define _SSP1MSK2 0x04
2445 #define _SSP1MSK3 0x08
2447 #define _SSP1MSK4 0x10
2449 #define _SSP1MSK5 0x20
2451 #define _SSP1MSK6 0x40
2453 #define _SSP1MSK7 0x80
2456 //==============================================================================
2459 //==============================================================================
2462 extern __at(0x0213) __sfr SSPMSK
;
2468 unsigned SSP1MSK0
: 1;
2469 unsigned SSP1MSK1
: 1;
2470 unsigned SSP1MSK2
: 1;
2471 unsigned SSP1MSK3
: 1;
2472 unsigned SSP1MSK4
: 1;
2473 unsigned SSP1MSK5
: 1;
2474 unsigned SSP1MSK6
: 1;
2475 unsigned SSP1MSK7
: 1;
2491 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
2493 #define _SSPMSK_SSP1MSK0 0x01
2494 #define _SSPMSK_MSK0 0x01
2495 #define _SSPMSK_SSP1MSK1 0x02
2496 #define _SSPMSK_MSK1 0x02
2497 #define _SSPMSK_SSP1MSK2 0x04
2498 #define _SSPMSK_MSK2 0x04
2499 #define _SSPMSK_SSP1MSK3 0x08
2500 #define _SSPMSK_MSK3 0x08
2501 #define _SSPMSK_SSP1MSK4 0x10
2502 #define _SSPMSK_MSK4 0x10
2503 #define _SSPMSK_SSP1MSK5 0x20
2504 #define _SSPMSK_MSK5 0x20
2505 #define _SSPMSK_SSP1MSK6 0x40
2506 #define _SSPMSK_MSK6 0x40
2507 #define _SSPMSK_SSP1MSK7 0x80
2508 #define _SSPMSK_MSK7 0x80
2510 //==============================================================================
2513 //==============================================================================
2516 extern __at(0x0214) __sfr SSP1STAT
;
2522 unsigned R_NOT_W
: 1;
2525 unsigned D_NOT_A
: 1;
2530 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
2534 #define _R_NOT_W 0x04
2537 #define _D_NOT_A 0x20
2541 //==============================================================================
2544 //==============================================================================
2547 extern __at(0x0214) __sfr SSPSTAT
;
2553 unsigned R_NOT_W
: 1;
2556 unsigned D_NOT_A
: 1;
2561 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
2563 #define _SSPSTAT_BF 0x01
2564 #define _SSPSTAT_UA 0x02
2565 #define _SSPSTAT_R_NOT_W 0x04
2566 #define _SSPSTAT_S 0x08
2567 #define _SSPSTAT_P 0x10
2568 #define _SSPSTAT_D_NOT_A 0x20
2569 #define _SSPSTAT_CKE 0x40
2570 #define _SSPSTAT_SMP 0x80
2572 //==============================================================================
2575 //==============================================================================
2578 extern __at(0x0215) __sfr SSP1CON
;
2601 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
2612 //==============================================================================
2615 //==============================================================================
2618 extern __at(0x0215) __sfr SSP1CON1
;
2641 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
2643 #define _SSP1CON1_SSPM0 0x01
2644 #define _SSP1CON1_SSPM1 0x02
2645 #define _SSP1CON1_SSPM2 0x04
2646 #define _SSP1CON1_SSPM3 0x08
2647 #define _SSP1CON1_CKP 0x10
2648 #define _SSP1CON1_SSPEN 0x20
2649 #define _SSP1CON1_SSPOV 0x40
2650 #define _SSP1CON1_WCOL 0x80
2652 //==============================================================================
2655 //==============================================================================
2658 extern __at(0x0215) __sfr SSPCON
;
2681 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2683 #define _SSPCON_SSPM0 0x01
2684 #define _SSPCON_SSPM1 0x02
2685 #define _SSPCON_SSPM2 0x04
2686 #define _SSPCON_SSPM3 0x08
2687 #define _SSPCON_CKP 0x10
2688 #define _SSPCON_SSPEN 0x20
2689 #define _SSPCON_SSPOV 0x40
2690 #define _SSPCON_WCOL 0x80
2692 //==============================================================================
2695 //==============================================================================
2698 extern __at(0x0215) __sfr SSPCON1
;
2721 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2723 #define _SSPCON1_SSPM0 0x01
2724 #define _SSPCON1_SSPM1 0x02
2725 #define _SSPCON1_SSPM2 0x04
2726 #define _SSPCON1_SSPM3 0x08
2727 #define _SSPCON1_CKP 0x10
2728 #define _SSPCON1_SSPEN 0x20
2729 #define _SSPCON1_SSPOV 0x40
2730 #define _SSPCON1_WCOL 0x80
2732 //==============================================================================
2735 //==============================================================================
2738 extern __at(0x0216) __sfr SSP1CON2
;
2748 unsigned ACKSTAT
: 1;
2752 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
2760 #define _ACKSTAT 0x40
2763 //==============================================================================
2766 //==============================================================================
2769 extern __at(0x0216) __sfr SSPCON2
;
2779 unsigned ACKSTAT
: 1;
2783 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
2785 #define _SSPCON2_SEN 0x01
2786 #define _SSPCON2_RSEN 0x02
2787 #define _SSPCON2_PEN 0x04
2788 #define _SSPCON2_RCEN 0x08
2789 #define _SSPCON2_ACKEN 0x10
2790 #define _SSPCON2_ACKDT 0x20
2791 #define _SSPCON2_ACKSTAT 0x40
2792 #define _SSPCON2_GCEN 0x80
2794 //==============================================================================
2797 //==============================================================================
2800 extern __at(0x0217) __sfr SSP1CON3
;
2811 unsigned ACKTIM
: 1;
2814 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
2823 #define _ACKTIM 0x80
2825 //==============================================================================
2828 //==============================================================================
2831 extern __at(0x0217) __sfr SSPCON3
;
2842 unsigned ACKTIM
: 1;
2845 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
2847 #define _SSPCON3_DHEN 0x01
2848 #define _SSPCON3_AHEN 0x02
2849 #define _SSPCON3_SBCDE 0x04
2850 #define _SSPCON3_SDAHT 0x08
2851 #define _SSPCON3_BOEN 0x10
2852 #define _SSPCON3_SCIE 0x20
2853 #define _SSPCON3_PCIE 0x40
2854 #define _SSPCON3_ACKTIM 0x80
2856 //==============================================================================
2859 //==============================================================================
2862 extern __at(0x028C) __sfr ODCONA
;
2876 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
2884 //==============================================================================
2887 //==============================================================================
2890 extern __at(0x028E) __sfr ODCONC
;
2913 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
2922 //==============================================================================
2924 extern __at(0x0291) __sfr CCPR1
;
2925 extern __at(0x0291) __sfr CCPR1L
;
2926 extern __at(0x0292) __sfr CCPR1H
;
2928 //==============================================================================
2931 extern __at(0x0293) __sfr CCP1CON
;
2937 unsigned CCP1MODE0
: 1;
2938 unsigned CCP1MODE1
: 1;
2939 unsigned CCP1MODE2
: 1;
2940 unsigned CCP1MODE3
: 1;
2941 unsigned CCP1FMT
: 1;
2942 unsigned CCP1OUT
: 1;
2944 unsigned CCP1EN
: 1;
2949 unsigned CCP1MODE
: 4;
2954 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
2956 #define _CCP1MODE0 0x01
2957 #define _CCP1MODE1 0x02
2958 #define _CCP1MODE2 0x04
2959 #define _CCP1MODE3 0x08
2960 #define _CCP1FMT 0x10
2961 #define _CCP1OUT 0x20
2962 #define _CCP1EN 0x80
2964 //==============================================================================
2967 //==============================================================================
2970 extern __at(0x0294) __sfr CCP1CAP
;
2976 unsigned CCP1CTS0
: 1;
2977 unsigned CCP1CTS1
: 1;
2978 unsigned CCP1CTS2
: 1;
2988 unsigned CCP1CTS
: 3;
2993 extern __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits
;
2995 #define _CCP1CTS0 0x01
2996 #define _CCP1CTS1 0x02
2997 #define _CCP1CTS2 0x04
2999 //==============================================================================
3001 extern __at(0x0295) __sfr CCPR2
;
3002 extern __at(0x0295) __sfr CCPR2L
;
3003 extern __at(0x0296) __sfr CCPR2H
;
3005 //==============================================================================
3008 extern __at(0x0297) __sfr CCP2CON
;
3014 unsigned CCP2MODE0
: 1;
3015 unsigned CCP2MODE1
: 1;
3016 unsigned CCP2MODE2
: 1;
3017 unsigned CCP2MODE3
: 1;
3018 unsigned CCP2FMT
: 1;
3019 unsigned CCP2OUT
: 1;
3021 unsigned CCP2EN
: 1;
3026 unsigned CCP2MODE
: 4;
3031 extern __at(0x0297) volatile __CCP2CONbits_t CCP2CONbits
;
3033 #define _CCP2MODE0 0x01
3034 #define _CCP2MODE1 0x02
3035 #define _CCP2MODE2 0x04
3036 #define _CCP2MODE3 0x08
3037 #define _CCP2FMT 0x10
3038 #define _CCP2OUT 0x20
3039 #define _CCP2EN 0x80
3041 //==============================================================================
3044 //==============================================================================
3047 extern __at(0x0298) __sfr CCP2CAP
;
3053 unsigned CCP2CTS0
: 1;
3054 unsigned CCP2CTS1
: 1;
3055 unsigned CCP2CTS2
: 1;
3065 unsigned CCP2CTS
: 3;
3070 extern __at(0x0298) volatile __CCP2CAPbits_t CCP2CAPbits
;
3072 #define _CCP2CTS0 0x01
3073 #define _CCP2CTS1 0x02
3074 #define _CCP2CTS2 0x04
3076 //==============================================================================
3079 //==============================================================================
3082 extern __at(0x029F) __sfr CCPTMRS
;
3086 unsigned C1TSEL
: 1;
3088 unsigned C2TSEL
: 1;
3096 extern __at(0x029F) volatile __CCPTMRSbits_t CCPTMRSbits
;
3098 #define _C1TSEL 0x01
3099 #define _C2TSEL 0x04
3101 //==============================================================================
3104 //==============================================================================
3107 extern __at(0x030C) __sfr SLRCONA
;
3121 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
3129 //==============================================================================
3132 //==============================================================================
3135 extern __at(0x030E) __sfr SLRCONC
;
3158 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
3167 //==============================================================================
3170 //==============================================================================
3173 extern __at(0x038C) __sfr INLVLA
;
3179 unsigned INLVLA0
: 1;
3180 unsigned INLVLA1
: 1;
3181 unsigned INLVLA2
: 1;
3182 unsigned INLVLA3
: 1;
3183 unsigned INLVLA4
: 1;
3184 unsigned INLVLA5
: 1;
3191 unsigned INLVLA
: 6;
3196 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
3198 #define _INLVLA0 0x01
3199 #define _INLVLA1 0x02
3200 #define _INLVLA2 0x04
3201 #define _INLVLA3 0x08
3202 #define _INLVLA4 0x10
3203 #define _INLVLA5 0x20
3205 //==============================================================================
3208 //==============================================================================
3211 extern __at(0x038E) __sfr INLVLC
;
3217 unsigned INLVLC0
: 1;
3218 unsigned INLVLC1
: 1;
3219 unsigned INLVLC2
: 1;
3220 unsigned INLVLC3
: 1;
3221 unsigned INLVLC4
: 1;
3222 unsigned INLVLC5
: 1;
3229 unsigned INLVLC
: 6;
3234 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
3236 #define _INLVLC0 0x01
3237 #define _INLVLC1 0x02
3238 #define _INLVLC2 0x04
3239 #define _INLVLC3 0x08
3240 #define _INLVLC4 0x10
3241 #define _INLVLC5 0x20
3243 //==============================================================================
3246 //==============================================================================
3249 extern __at(0x0391) __sfr IOCAP
;
3255 unsigned IOCAP0
: 1;
3256 unsigned IOCAP1
: 1;
3257 unsigned IOCAP2
: 1;
3258 unsigned IOCAP3
: 1;
3259 unsigned IOCAP4
: 1;
3260 unsigned IOCAP5
: 1;
3272 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
3274 #define _IOCAP0 0x01
3275 #define _IOCAP1 0x02
3276 #define _IOCAP2 0x04
3277 #define _IOCAP3 0x08
3278 #define _IOCAP4 0x10
3279 #define _IOCAP5 0x20
3281 //==============================================================================
3284 //==============================================================================
3287 extern __at(0x0392) __sfr IOCAN
;
3293 unsigned IOCAN0
: 1;
3294 unsigned IOCAN1
: 1;
3295 unsigned IOCAN2
: 1;
3296 unsigned IOCAN3
: 1;
3297 unsigned IOCAN4
: 1;
3298 unsigned IOCAN5
: 1;
3310 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
3312 #define _IOCAN0 0x01
3313 #define _IOCAN1 0x02
3314 #define _IOCAN2 0x04
3315 #define _IOCAN3 0x08
3316 #define _IOCAN4 0x10
3317 #define _IOCAN5 0x20
3319 //==============================================================================
3322 //==============================================================================
3325 extern __at(0x0393) __sfr IOCAF
;
3331 unsigned IOCAF0
: 1;
3332 unsigned IOCAF1
: 1;
3333 unsigned IOCAF2
: 1;
3334 unsigned IOCAF3
: 1;
3335 unsigned IOCAF4
: 1;
3336 unsigned IOCAF5
: 1;
3348 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
3350 #define _IOCAF0 0x01
3351 #define _IOCAF1 0x02
3352 #define _IOCAF2 0x04
3353 #define _IOCAF3 0x08
3354 #define _IOCAF4 0x10
3355 #define _IOCAF5 0x20
3357 //==============================================================================
3360 //==============================================================================
3363 extern __at(0x0397) __sfr IOCCP
;
3369 unsigned IOCCP0
: 1;
3370 unsigned IOCCP1
: 1;
3371 unsigned IOCCP2
: 1;
3372 unsigned IOCCP3
: 1;
3373 unsigned IOCCP4
: 1;
3374 unsigned IOCCP5
: 1;
3386 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
3388 #define _IOCCP0 0x01
3389 #define _IOCCP1 0x02
3390 #define _IOCCP2 0x04
3391 #define _IOCCP3 0x08
3392 #define _IOCCP4 0x10
3393 #define _IOCCP5 0x20
3395 //==============================================================================
3398 //==============================================================================
3401 extern __at(0x0398) __sfr IOCCN
;
3407 unsigned IOCCN0
: 1;
3408 unsigned IOCCN1
: 1;
3409 unsigned IOCCN2
: 1;
3410 unsigned IOCCN3
: 1;
3411 unsigned IOCCN4
: 1;
3412 unsigned IOCCN5
: 1;
3424 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
3426 #define _IOCCN0 0x01
3427 #define _IOCCN1 0x02
3428 #define _IOCCN2 0x04
3429 #define _IOCCN3 0x08
3430 #define _IOCCN4 0x10
3431 #define _IOCCN5 0x20
3433 //==============================================================================
3436 //==============================================================================
3439 extern __at(0x0399) __sfr IOCCF
;
3445 unsigned IOCCF0
: 1;
3446 unsigned IOCCF1
: 1;
3447 unsigned IOCCF2
: 1;
3448 unsigned IOCCF3
: 1;
3449 unsigned IOCCF4
: 1;
3450 unsigned IOCCF5
: 1;
3462 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
3464 #define _IOCCF0 0x01
3465 #define _IOCCF1 0x02
3466 #define _IOCCF2 0x04
3467 #define _IOCCF3 0x08
3468 #define _IOCCF4 0x10
3469 #define _IOCCF5 0x20
3471 //==============================================================================
3474 //==============================================================================
3477 extern __at(0x039A) __sfr CLKRCON
;
3483 unsigned CLKRDIV0
: 1;
3484 unsigned CLKRDIV1
: 1;
3485 unsigned CLKRDIV2
: 1;
3486 unsigned CLKRDC0
: 1;
3487 unsigned CLKRDC1
: 1;
3490 unsigned CLKREN
: 1;
3495 unsigned CLKRDIV
: 3;
3502 unsigned CLKRDC
: 2;
3507 extern __at(0x039A) volatile __CLKRCONbits_t CLKRCONbits
;
3509 #define _CLKRDIV0 0x01
3510 #define _CLKRDIV1 0x02
3511 #define _CLKRDIV2 0x04
3512 #define _CLKRDC0 0x08
3513 #define _CLKRDC1 0x10
3514 #define _CLKREN 0x80
3516 //==============================================================================
3519 //==============================================================================
3522 extern __at(0x039C) __sfr MDCON
;
3530 unsigned MDOPOL
: 1;
3536 extern __at(0x039C) volatile __MDCONbits_t MDCONbits
;
3540 #define _MDOPOL 0x10
3543 //==============================================================================
3546 //==============================================================================
3549 extern __at(0x039D) __sfr MDSRC
;
3572 extern __at(0x039D) volatile __MDSRCbits_t MDSRCbits
;
3579 //==============================================================================
3582 //==============================================================================
3585 extern __at(0x039E) __sfr MDCARH
;
3596 unsigned MDCHSYNC
: 1;
3597 unsigned MDCHPOL
: 1;
3608 extern __at(0x039E) volatile __MDCARHbits_t MDCARHbits
;
3614 #define _MDCHSYNC 0x20
3615 #define _MDCHPOL 0x40
3617 //==============================================================================
3620 //==============================================================================
3623 extern __at(0x039F) __sfr MDCARL
;
3634 unsigned MDCLSYNC
: 1;
3635 unsigned MDCLPOL
: 1;
3646 extern __at(0x039F) volatile __MDCARLbits_t MDCARLbits
;
3652 #define _MDCLSYNC 0x20
3653 #define _MDCLPOL 0x40
3655 //==============================================================================
3658 //==============================================================================
3661 extern __at(0x040C) __sfr CCDNA
;
3665 unsigned CCDNA0
: 1;
3666 unsigned CCDNA1
: 1;
3667 unsigned CCDNA2
: 1;
3669 unsigned CCDNA4
: 1;
3670 unsigned CCDNA5
: 1;
3675 extern __at(0x040C) volatile __CCDNAbits_t CCDNAbits
;
3677 #define _CCDNA0 0x01
3678 #define _CCDNA1 0x02
3679 #define _CCDNA2 0x04
3680 #define _CCDNA4 0x10
3681 #define _CCDNA5 0x20
3683 //==============================================================================
3686 //==============================================================================
3689 extern __at(0x040E) __sfr CCDNC
;
3695 unsigned CCDNC0
: 1;
3696 unsigned CCDNC1
: 1;
3697 unsigned CCDNC2
: 1;
3698 unsigned CCDNC3
: 1;
3699 unsigned CCDNC4
: 1;
3700 unsigned CCDNC5
: 1;
3712 extern __at(0x040E) volatile __CCDNCbits_t CCDNCbits
;
3714 #define _CCDNC0 0x01
3715 #define _CCDNC1 0x02
3716 #define _CCDNC2 0x04
3717 #define _CCDNC3 0x08
3718 #define _CCDNC4 0x10
3719 #define _CCDNC5 0x20
3721 //==============================================================================
3724 //==============================================================================
3727 extern __at(0x041F) __sfr CCDCON
;
3750 extern __at(0x041F) volatile __CCDCONbits_t CCDCONbits
;
3756 //==============================================================================
3759 //==============================================================================
3762 extern __at(0x048C) __sfr CCDPA
;
3766 unsigned CCDPA0
: 1;
3767 unsigned CCDPA1
: 1;
3768 unsigned CCDPA2
: 1;
3770 unsigned CCDPA4
: 1;
3771 unsigned CCDPA5
: 1;
3776 extern __at(0x048C) volatile __CCDPAbits_t CCDPAbits
;
3778 #define _CCDPA0 0x01
3779 #define _CCDPA1 0x02
3780 #define _CCDPA2 0x04
3781 #define _CCDPA4 0x10
3782 #define _CCDPA5 0x20
3784 //==============================================================================
3787 //==============================================================================
3790 extern __at(0x048E) __sfr CCDPC
;
3796 unsigned CCDPC0
: 1;
3797 unsigned CCDPC1
: 1;
3798 unsigned CCDPC2
: 1;
3799 unsigned CCDPC3
: 1;
3800 unsigned CCDPC4
: 1;
3801 unsigned CCDPC5
: 1;
3813 extern __at(0x048E) volatile __CCDPCbits_t CCDPCbits
;
3815 #define _CCDPC0 0x01
3816 #define _CCDPC1 0x02
3817 #define _CCDPC2 0x04
3818 #define _CCDPC3 0x08
3819 #define _CCDPC4 0x10
3820 #define _CCDPC5 0x20
3822 //==============================================================================
3824 extern __at(0x0498) __sfr NCO1ACC
;
3825 extern __at(0x0498) __sfr NCO1ACCL
;
3826 extern __at(0x0499) __sfr NCO1ACCH
;
3827 extern __at(0x049A) __sfr NCO1ACCU
;
3828 extern __at(0x049B) __sfr NCO1INC
;
3829 extern __at(0x049B) __sfr NCO1INCL
;
3830 extern __at(0x049C) __sfr NCO1INCH
;
3831 extern __at(0x049D) __sfr NCO1INCU
;
3833 //==============================================================================
3836 extern __at(0x049E) __sfr NCO1CON
;
3850 extern __at(0x049E) volatile __NCO1CONbits_t NCO1CONbits
;
3857 //==============================================================================
3859 extern __at(0x049F) __sfr NCO1CLK
;
3861 //==============================================================================
3864 extern __at(0x0617) __sfr PWM5DCL
;
3876 unsigned PWM5DCL0
: 1;
3877 unsigned PWM5DCL1
: 1;
3883 unsigned PWM5DCL
: 2;
3887 extern __at(0x0617) volatile __PWM5DCLbits_t PWM5DCLbits
;
3889 #define _PWM5DCL0 0x40
3890 #define _PWM5DCL1 0x80
3892 //==============================================================================
3895 //==============================================================================
3898 extern __at(0x0618) __sfr PWM5DCH
;
3902 unsigned PWM5DCH0
: 1;
3903 unsigned PWM5DCH1
: 1;
3904 unsigned PWM5DCH2
: 1;
3905 unsigned PWM5DCH3
: 1;
3906 unsigned PWM5DCH4
: 1;
3907 unsigned PWM5DCH5
: 1;
3908 unsigned PWM5DCH6
: 1;
3909 unsigned PWM5DCH7
: 1;
3912 extern __at(0x0618) volatile __PWM5DCHbits_t PWM5DCHbits
;
3914 #define _PWM5DCH0 0x01
3915 #define _PWM5DCH1 0x02
3916 #define _PWM5DCH2 0x04
3917 #define _PWM5DCH3 0x08
3918 #define _PWM5DCH4 0x10
3919 #define _PWM5DCH5 0x20
3920 #define _PWM5DCH6 0x40
3921 #define _PWM5DCH7 0x80
3923 //==============================================================================
3926 //==============================================================================
3929 extern __at(0x0619) __sfr PWM5CON
;
3937 unsigned PWM5POL
: 1;
3938 unsigned PWM5OUT
: 1;
3940 unsigned PWM5EN
: 1;
3943 extern __at(0x0619) volatile __PWM5CONbits_t PWM5CONbits
;
3945 #define _PWM5POL 0x10
3946 #define _PWM5OUT 0x20
3947 #define _PWM5EN 0x80
3949 //==============================================================================
3952 //==============================================================================
3955 extern __at(0x0619) __sfr PWM5CON0
;
3963 unsigned PWM5POL
: 1;
3964 unsigned PWM5OUT
: 1;
3966 unsigned PWM5EN
: 1;
3969 extern __at(0x0619) volatile __PWM5CON0bits_t PWM5CON0bits
;
3971 #define _PWM5CON0_PWM5POL 0x10
3972 #define _PWM5CON0_PWM5OUT 0x20
3973 #define _PWM5CON0_PWM5EN 0x80
3975 //==============================================================================
3978 //==============================================================================
3981 extern __at(0x061A) __sfr PWM6DCL
;
3993 unsigned PWM6DCL0
: 1;
3994 unsigned PWM6DCL1
: 1;
4000 unsigned PWM6DCL
: 2;
4004 extern __at(0x061A) volatile __PWM6DCLbits_t PWM6DCLbits
;
4006 #define _PWM6DCL0 0x40
4007 #define _PWM6DCL1 0x80
4009 //==============================================================================
4012 //==============================================================================
4015 extern __at(0x061B) __sfr PWM6DCH
;
4019 unsigned PWM6DCH0
: 1;
4020 unsigned PWM6DCH1
: 1;
4021 unsigned PWM6DCH2
: 1;
4022 unsigned PWM6DCH3
: 1;
4023 unsigned PWM6DCH4
: 1;
4024 unsigned PWM6DCH5
: 1;
4025 unsigned PWM6DCH6
: 1;
4026 unsigned PWM6DCH7
: 1;
4029 extern __at(0x061B) volatile __PWM6DCHbits_t PWM6DCHbits
;
4031 #define _PWM6DCH0 0x01
4032 #define _PWM6DCH1 0x02
4033 #define _PWM6DCH2 0x04
4034 #define _PWM6DCH3 0x08
4035 #define _PWM6DCH4 0x10
4036 #define _PWM6DCH5 0x20
4037 #define _PWM6DCH6 0x40
4038 #define _PWM6DCH7 0x80
4040 //==============================================================================
4043 //==============================================================================
4046 extern __at(0x061C) __sfr PWM6CON
;
4054 unsigned PWM6POL
: 1;
4055 unsigned PWM6OUT
: 1;
4057 unsigned PWM6EN
: 1;
4060 extern __at(0x061C) volatile __PWM6CONbits_t PWM6CONbits
;
4062 #define _PWM6POL 0x10
4063 #define _PWM6OUT 0x20
4064 #define _PWM6EN 0x80
4066 //==============================================================================
4069 //==============================================================================
4072 extern __at(0x061C) __sfr PWM6CON0
;
4080 unsigned PWM6POL
: 1;
4081 unsigned PWM6OUT
: 1;
4083 unsigned PWM6EN
: 1;
4086 extern __at(0x061C) volatile __PWM6CON0bits_t PWM6CON0bits
;
4088 #define _PWM6CON0_PWM6POL 0x10
4089 #define _PWM6CON0_PWM6OUT 0x20
4090 #define _PWM6CON0_PWM6EN 0x80
4092 //==============================================================================
4095 //==============================================================================
4098 extern __at(0x0691) __sfr CWG1CLKCON
;
4116 unsigned CWG1CS
: 1;
4125 } __CWG1CLKCONbits_t
;
4127 extern __at(0x0691) volatile __CWG1CLKCONbits_t CWG1CLKCONbits
;
4130 #define _CWG1CS 0x01
4132 //==============================================================================
4135 //==============================================================================
4138 extern __at(0x0692) __sfr CWG1DAT
;
4144 unsigned CWG1DAT0
: 1;
4145 unsigned CWG1DAT1
: 1;
4146 unsigned CWG1DAT2
: 1;
4147 unsigned CWG1DAT3
: 1;
4156 unsigned CWG1DAT
: 4;
4161 extern __at(0x0692) volatile __CWG1DATbits_t CWG1DATbits
;
4163 #define _CWG1DAT0 0x01
4164 #define _CWG1DAT1 0x02
4165 #define _CWG1DAT2 0x04
4166 #define _CWG1DAT3 0x08
4168 //==============================================================================
4171 //==============================================================================
4174 extern __at(0x0693) __sfr CWG1DBR
;
4192 unsigned CWG1DBR0
: 1;
4193 unsigned CWG1DBR1
: 1;
4194 unsigned CWG1DBR2
: 1;
4195 unsigned CWG1DBR3
: 1;
4196 unsigned CWG1DBR4
: 1;
4197 unsigned CWG1DBR5
: 1;
4204 unsigned CWG1DBR
: 6;
4215 extern __at(0x0693) volatile __CWG1DBRbits_t CWG1DBRbits
;
4218 #define _CWG1DBR0 0x01
4220 #define _CWG1DBR1 0x02
4222 #define _CWG1DBR2 0x04
4224 #define _CWG1DBR3 0x08
4226 #define _CWG1DBR4 0x10
4228 #define _CWG1DBR5 0x20
4230 //==============================================================================
4233 //==============================================================================
4236 extern __at(0x0694) __sfr CWG1DBF
;
4254 unsigned CWG1DBF0
: 1;
4255 unsigned CWG1DBF1
: 1;
4256 unsigned CWG1DBF2
: 1;
4257 unsigned CWG1DBF3
: 1;
4258 unsigned CWG1DBF4
: 1;
4259 unsigned CWG1DBF5
: 1;
4272 unsigned CWG1DBF
: 6;
4277 extern __at(0x0694) volatile __CWG1DBFbits_t CWG1DBFbits
;
4280 #define _CWG1DBF0 0x01
4282 #define _CWG1DBF1 0x02
4284 #define _CWG1DBF2 0x04
4286 #define _CWG1DBF3 0x08
4288 #define _CWG1DBF4 0x10
4290 #define _CWG1DBF5 0x20
4292 //==============================================================================
4295 //==============================================================================
4298 extern __at(0x0695) __sfr CWG1CON0
;
4316 unsigned CWG1MODE0
: 1;
4317 unsigned CWG1MODE1
: 1;
4318 unsigned CWG1MODE2
: 1;
4322 unsigned CWG1LD
: 1;
4335 unsigned CWG1EN
: 1;
4340 unsigned CWG1MODE
: 3;
4351 extern __at(0x0695) volatile __CWG1CON0bits_t CWG1CON0bits
;
4353 #define _CWG1CON0_MODE0 0x01
4354 #define _CWG1CON0_CWG1MODE0 0x01
4355 #define _CWG1CON0_MODE1 0x02
4356 #define _CWG1CON0_CWG1MODE1 0x02
4357 #define _CWG1CON0_MODE2 0x04
4358 #define _CWG1CON0_CWG1MODE2 0x04
4359 #define _CWG1CON0_LD 0x40
4360 #define _CWG1CON0_CWG1LD 0x40
4361 #define _CWG1CON0_EN 0x80
4362 #define _CWG1CON0_G1EN 0x80
4363 #define _CWG1CON0_CWG1EN 0x80
4365 //==============================================================================
4368 //==============================================================================
4371 extern __at(0x0696) __sfr CWG1CON1
;
4389 unsigned CWG1POLA
: 1;
4390 unsigned CWG1POLB
: 1;
4391 unsigned CWG1POLC
: 1;
4392 unsigned CWG1POLD
: 1;
4394 unsigned CWG1IN
: 1;
4400 extern __at(0x0696) volatile __CWG1CON1bits_t CWG1CON1bits
;
4403 #define _CWG1POLA 0x01
4405 #define _CWG1POLB 0x02
4407 #define _CWG1POLC 0x04
4409 #define _CWG1POLD 0x08
4411 #define _CWG1IN 0x20
4413 //==============================================================================
4416 //==============================================================================
4419 extern __at(0x0697) __sfr CWG1AS0
;
4432 unsigned SHUTDOWN
: 1;
4439 unsigned CWG1LSAC0
: 1;
4440 unsigned CWG1LSAC1
: 1;
4441 unsigned CWG1LSBD0
: 1;
4442 unsigned CWG1LSBD1
: 1;
4443 unsigned CWG1REN
: 1;
4444 unsigned CWG1SHUTDOWN
: 1;
4450 unsigned CWG1LSAC
: 2;
4471 unsigned CWG1LSBD
: 2;
4476 extern __at(0x0697) volatile __CWG1AS0bits_t CWG1AS0bits
;
4479 #define _CWG1LSAC0 0x04
4481 #define _CWG1LSAC1 0x08
4483 #define _CWG1LSBD0 0x10
4485 #define _CWG1LSBD1 0x20
4487 #define _CWG1REN 0x40
4488 #define _SHUTDOWN 0x80
4489 #define _CWG1SHUTDOWN 0x80
4491 //==============================================================================
4494 //==============================================================================
4497 extern __at(0x0698) __sfr CWG1AS1
;
4511 extern __at(0x0698) volatile __CWG1AS1bits_t CWG1AS1bits
;
4518 //==============================================================================
4521 //==============================================================================
4524 extern __at(0x0699) __sfr CWG1STR
;
4542 unsigned CWG1STRA
: 1;
4543 unsigned CWG1STRB
: 1;
4544 unsigned CWG1STRC
: 1;
4545 unsigned CWG1STRD
: 1;
4546 unsigned CWG1OVRA
: 1;
4547 unsigned CWG1OVRB
: 1;
4548 unsigned CWG1OVRC
: 1;
4549 unsigned CWG1OVRD
: 1;
4553 extern __at(0x0699) volatile __CWG1STRbits_t CWG1STRbits
;
4556 #define _CWG1STRA 0x01
4558 #define _CWG1STRB 0x02
4560 #define _CWG1STRC 0x04
4562 #define _CWG1STRD 0x08
4564 #define _CWG1OVRA 0x10
4566 #define _CWG1OVRB 0x20
4568 #define _CWG1OVRC 0x40
4570 #define _CWG1OVRD 0x80
4572 //==============================================================================
4574 extern __at(0x0891) __sfr NVMADR
;
4576 //==============================================================================
4579 extern __at(0x0891) __sfr NVMADRL
;
4583 unsigned NVMADR0
: 1;
4584 unsigned NVMADR1
: 1;
4585 unsigned NVMADR2
: 1;
4586 unsigned NVMADR3
: 1;
4587 unsigned NVMADR4
: 1;
4588 unsigned NVMADR5
: 1;
4589 unsigned NVMADR6
: 1;
4590 unsigned NVMADR7
: 1;
4593 extern __at(0x0891) volatile __NVMADRLbits_t NVMADRLbits
;
4595 #define _NVMADR0 0x01
4596 #define _NVMADR1 0x02
4597 #define _NVMADR2 0x04
4598 #define _NVMADR3 0x08
4599 #define _NVMADR4 0x10
4600 #define _NVMADR5 0x20
4601 #define _NVMADR6 0x40
4602 #define _NVMADR7 0x80
4604 //==============================================================================
4607 //==============================================================================
4610 extern __at(0x0892) __sfr NVMADRH
;
4614 unsigned NVMADR8
: 1;
4615 unsigned NVMADR9
: 1;
4616 unsigned NVMADR10
: 1;
4617 unsigned NVMADR11
: 1;
4618 unsigned NVMADR12
: 1;
4619 unsigned NVMADR13
: 1;
4620 unsigned NVMADR14
: 1;
4624 extern __at(0x0892) volatile __NVMADRHbits_t NVMADRHbits
;
4626 #define _NVMADR8 0x01
4627 #define _NVMADR9 0x02
4628 #define _NVMADR10 0x04
4629 #define _NVMADR11 0x08
4630 #define _NVMADR12 0x10
4631 #define _NVMADR13 0x20
4632 #define _NVMADR14 0x40
4634 //==============================================================================
4636 extern __at(0x0893) __sfr NVMDAT
;
4638 //==============================================================================
4641 extern __at(0x0893) __sfr NVMDATL
;
4645 unsigned NVMDAT0
: 1;
4646 unsigned NVMDAT1
: 1;
4647 unsigned NVMDAT2
: 1;
4648 unsigned NVMDAT3
: 1;
4649 unsigned NVMDAT4
: 1;
4650 unsigned NVMDAT5
: 1;
4651 unsigned NVMDAT6
: 1;
4652 unsigned NVMDAT7
: 1;
4655 extern __at(0x0893) volatile __NVMDATLbits_t NVMDATLbits
;
4657 #define _NVMDAT0 0x01
4658 #define _NVMDAT1 0x02
4659 #define _NVMDAT2 0x04
4660 #define _NVMDAT3 0x08
4661 #define _NVMDAT4 0x10
4662 #define _NVMDAT5 0x20
4663 #define _NVMDAT6 0x40
4664 #define _NVMDAT7 0x80
4666 //==============================================================================
4669 //==============================================================================
4672 extern __at(0x0894) __sfr NVMDATH
;
4676 unsigned NVMDAT8
: 1;
4677 unsigned NVMDAT9
: 1;
4678 unsigned NVMDAT10
: 1;
4679 unsigned NVMDAT11
: 1;
4680 unsigned NVMDAT12
: 1;
4681 unsigned NVMDAT13
: 1;
4686 extern __at(0x0894) volatile __NVMDATHbits_t NVMDATHbits
;
4688 #define _NVMDAT8 0x01
4689 #define _NVMDAT9 0x02
4690 #define _NVMDAT10 0x04
4691 #define _NVMDAT11 0x08
4692 #define _NVMDAT12 0x10
4693 #define _NVMDAT13 0x20
4695 //==============================================================================
4698 //==============================================================================
4701 extern __at(0x0895) __sfr NVMCON1
;
4711 unsigned NVMREGS
: 1;
4715 extern __at(0x0895) volatile __NVMCON1bits_t NVMCON1bits
;
4723 #define _NVMREGS 0x40
4725 //==============================================================================
4727 extern __at(0x0896) __sfr NVMCON2
;
4729 //==============================================================================
4732 extern __at(0x089B) __sfr PCON0
;
4736 unsigned NOT_BOR
: 1;
4737 unsigned NOT_POR
: 1;
4738 unsigned NOT_RI
: 1;
4739 unsigned NOT_RMCLR
: 1;
4740 unsigned NOT_RWDT
: 1;
4742 unsigned STKUNF
: 1;
4743 unsigned STKOVF
: 1;
4746 extern __at(0x089B) volatile __PCON0bits_t PCON0bits
;
4748 #define _NOT_BOR 0x01
4749 #define _NOT_POR 0x02
4750 #define _NOT_RI 0x04
4751 #define _NOT_RMCLR 0x08
4752 #define _NOT_RWDT 0x10
4753 #define _STKUNF 0x40
4754 #define _STKOVF 0x80
4756 //==============================================================================
4759 //==============================================================================
4762 extern __at(0x0911) __sfr PMD0
;
4767 unsigned CLKRMD
: 1;
4773 unsigned SYSCMD
: 1;
4776 extern __at(0x0911) volatile __PMD0bits_t PMD0bits
;
4779 #define _CLKRMD 0x02
4782 #define _SYSCMD 0x80
4784 //==============================================================================
4787 //==============================================================================
4790 extern __at(0x0912) __sfr PMD1
;
4794 unsigned TMR0MD
: 1;
4795 unsigned TMR1MD
: 1;
4796 unsigned TMR2MD
: 1;
4804 extern __at(0x0912) volatile __PMD1bits_t PMD1bits
;
4806 #define _TMR0MD 0x01
4807 #define _TMR1MD 0x02
4808 #define _TMR2MD 0x04
4811 //==============================================================================
4814 //==============================================================================
4817 extern __at(0x0913) __sfr PMD2
;
4822 unsigned CMP1MD
: 1;
4823 unsigned CMP2MD
: 1;
4831 extern __at(0x0913) volatile __PMD2bits_t PMD2bits
;
4833 #define _CMP1MD 0x02
4834 #define _CMP2MD 0x04
4838 //==============================================================================
4841 //==============================================================================
4844 extern __at(0x0914) __sfr PMD3
;
4848 unsigned CCP1MD
: 1;
4849 unsigned CCP2MD
: 1;
4852 unsigned PWM5MD
: 1;
4853 unsigned PWM6MD
: 1;
4854 unsigned CWG1MD
: 1;
4858 extern __at(0x0914) volatile __PMD3bits_t PMD3bits
;
4860 #define _CCP1MD 0x01
4861 #define _CCP2MD 0x02
4862 #define _PWM5MD 0x10
4863 #define _PWM6MD 0x20
4864 #define _CWG1MD 0x40
4866 //==============================================================================
4869 //==============================================================================
4872 extern __at(0x0915) __sfr PMD4
;
4877 unsigned MSSP1MD
: 1;
4881 unsigned UART1MD
: 1;
4886 extern __at(0x0915) volatile __PMD4bits_t PMD4bits
;
4888 #define _MSSP1MD 0x02
4889 #define _UART1MD 0x20
4891 //==============================================================================
4894 //==============================================================================
4897 extern __at(0x0916) __sfr PMD5
;
4902 unsigned CLC1MD
: 1;
4903 unsigned CLC2MD
: 1;
4911 extern __at(0x0916) volatile __PMD5bits_t PMD5bits
;
4914 #define _CLC1MD 0x02
4915 #define _CLC2MD 0x04
4917 //==============================================================================
4920 //==============================================================================
4923 extern __at(0x0918) __sfr CPUDOZE
;
4946 extern __at(0x0918) volatile __CPUDOZEbits_t CPUDOZEbits
;
4956 //==============================================================================
4959 //==============================================================================
4962 extern __at(0x0919) __sfr OSCCON1
;
4992 extern __at(0x0919) volatile __OSCCON1bits_t OSCCON1bits
;
5002 //==============================================================================
5005 //==============================================================================
5008 extern __at(0x091A) __sfr OSCCON2
;
5038 extern __at(0x091A) volatile __OSCCON2bits_t OSCCON2bits
;
5048 //==============================================================================
5051 //==============================================================================
5054 extern __at(0x091B) __sfr OSCCON3
;
5063 unsigned SOSCBE
: 1;
5064 unsigned SOSCPWR
: 1;
5065 unsigned CSWHOLD
: 1;
5068 extern __at(0x091B) volatile __OSCCON3bits_t OSCCON3bits
;
5072 #define _SOSCBE 0x20
5073 #define _SOSCPWR 0x40
5074 #define _CSWHOLD 0x80
5076 //==============================================================================
5079 //==============================================================================
5082 extern __at(0x091C) __sfr OSCSTAT1
;
5096 extern __at(0x091C) volatile __OSCSTAT1bits_t OSCSTAT1bits
;
5105 //==============================================================================
5108 //==============================================================================
5111 extern __at(0x091D) __sfr OSCEN
;
5118 unsigned SOSCEN
: 1;
5122 unsigned EXTOEN
: 1;
5125 extern __at(0x091D) volatile __OSCENbits_t OSCENbits
;
5128 #define _SOSCEN 0x08
5131 #define _EXTOEN 0x80
5133 //==============================================================================
5136 //==============================================================================
5139 extern __at(0x091E) __sfr OSCTUNE
;
5145 unsigned HFTUN0
: 1;
5146 unsigned HFTUN1
: 1;
5147 unsigned HFTUN2
: 1;
5148 unsigned HFTUN3
: 1;
5149 unsigned HFTUN4
: 1;
5150 unsigned HFTUN5
: 1;
5162 extern __at(0x091E) volatile __OSCTUNEbits_t OSCTUNEbits
;
5164 #define _HFTUN0 0x01
5165 #define _HFTUN1 0x02
5166 #define _HFTUN2 0x04
5167 #define _HFTUN3 0x08
5168 #define _HFTUN4 0x10
5169 #define _HFTUN5 0x20
5171 //==============================================================================
5174 //==============================================================================
5177 extern __at(0x091F) __sfr OSCFRQ
;
5183 unsigned HFFRQ0
: 1;
5184 unsigned HFFRQ1
: 1;
5185 unsigned HFFRQ2
: 1;
5186 unsigned HFFRQ3
: 1;
5200 extern __at(0x091F) volatile __OSCFRQbits_t OSCFRQbits
;
5202 #define _HFFRQ0 0x01
5203 #define _HFFRQ1 0x02
5204 #define _HFFRQ2 0x04
5205 #define _HFFRQ3 0x08
5207 //==============================================================================
5210 //==============================================================================
5213 extern __at(0x0E0F) __sfr PPSLOCK
;
5217 unsigned PPSLOCKED
: 1;
5227 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
5229 #define _PPSLOCKED 0x01
5231 //==============================================================================
5234 //==============================================================================
5237 extern __at(0x0E10) __sfr INTPPS
;
5243 unsigned INTPPS0
: 1;
5244 unsigned INTPPS1
: 1;
5245 unsigned INTPPS2
: 1;
5246 unsigned INTPPS3
: 1;
5247 unsigned INTPPS4
: 1;
5255 unsigned INTPPS
: 5;
5260 extern __at(0x0E10) volatile __INTPPSbits_t INTPPSbits
;
5262 #define _INTPPS0 0x01
5263 #define _INTPPS1 0x02
5264 #define _INTPPS2 0x04
5265 #define _INTPPS3 0x08
5266 #define _INTPPS4 0x10
5268 //==============================================================================
5271 //==============================================================================
5274 extern __at(0x0E11) __sfr T0CKIPPS
;
5280 unsigned T0CKIPPS0
: 1;
5281 unsigned T0CKIPPS1
: 1;
5282 unsigned T0CKIPPS2
: 1;
5283 unsigned T0CKIPPS3
: 1;
5284 unsigned T0CKIPPS4
: 1;
5292 unsigned T0CKIPPS
: 5;
5297 extern __at(0x0E11) volatile __T0CKIPPSbits_t T0CKIPPSbits
;
5299 #define _T0CKIPPS0 0x01
5300 #define _T0CKIPPS1 0x02
5301 #define _T0CKIPPS2 0x04
5302 #define _T0CKIPPS3 0x08
5303 #define _T0CKIPPS4 0x10
5305 //==============================================================================
5308 //==============================================================================
5311 extern __at(0x0E12) __sfr T1CKIPPS
;
5317 unsigned T1CKIPPS0
: 1;
5318 unsigned T1CKIPPS1
: 1;
5319 unsigned T1CKIPPS2
: 1;
5320 unsigned T1CKIPPS3
: 1;
5321 unsigned T1CKIPPS4
: 1;
5329 unsigned T1CKIPPS
: 5;
5334 extern __at(0x0E12) volatile __T1CKIPPSbits_t T1CKIPPSbits
;
5336 #define _T1CKIPPS0 0x01
5337 #define _T1CKIPPS1 0x02
5338 #define _T1CKIPPS2 0x04
5339 #define _T1CKIPPS3 0x08
5340 #define _T1CKIPPS4 0x10
5342 //==============================================================================
5345 //==============================================================================
5348 extern __at(0x0E13) __sfr T1GPPS
;
5354 unsigned T1GPPS0
: 1;
5355 unsigned T1GPPS1
: 1;
5356 unsigned T1GPPS2
: 1;
5357 unsigned T1GPPS3
: 1;
5358 unsigned T1GPPS4
: 1;
5366 unsigned T1GPPS
: 5;
5371 extern __at(0x0E13) volatile __T1GPPSbits_t T1GPPSbits
;
5373 #define _T1GPPS0 0x01
5374 #define _T1GPPS1 0x02
5375 #define _T1GPPS2 0x04
5376 #define _T1GPPS3 0x08
5377 #define _T1GPPS4 0x10
5379 //==============================================================================
5382 //==============================================================================
5385 extern __at(0x0E14) __sfr CCP1PPS
;
5391 unsigned CCP1PPS0
: 1;
5392 unsigned CCP1PPS1
: 1;
5393 unsigned CCP1PPS2
: 1;
5394 unsigned CCP1PPS3
: 1;
5395 unsigned CCP1PPS4
: 1;
5403 unsigned CCP1PPS
: 5;
5408 extern __at(0x0E14) volatile __CCP1PPSbits_t CCP1PPSbits
;
5410 #define _CCP1PPS0 0x01
5411 #define _CCP1PPS1 0x02
5412 #define _CCP1PPS2 0x04
5413 #define _CCP1PPS3 0x08
5414 #define _CCP1PPS4 0x10
5416 //==============================================================================
5419 //==============================================================================
5422 extern __at(0x0E15) __sfr CCP2PPS
;
5428 unsigned CCP2PPS0
: 1;
5429 unsigned CCP2PPS1
: 1;
5430 unsigned CCP2PPS2
: 1;
5431 unsigned CCP2PPS3
: 1;
5432 unsigned CCP2PPS4
: 1;
5440 unsigned CCP2PPS
: 5;
5445 extern __at(0x0E15) volatile __CCP2PPSbits_t CCP2PPSbits
;
5447 #define _CCP2PPS0 0x01
5448 #define _CCP2PPS1 0x02
5449 #define _CCP2PPS2 0x04
5450 #define _CCP2PPS3 0x08
5451 #define _CCP2PPS4 0x10
5453 //==============================================================================
5456 //==============================================================================
5459 extern __at(0x0E18) __sfr CWG1PPS
;
5465 unsigned CWG1PPS0
: 1;
5466 unsigned CWG1PPS1
: 1;
5467 unsigned CWG1PPS2
: 1;
5468 unsigned CWG1PPS3
: 1;
5469 unsigned CWG1PPS4
: 1;
5477 unsigned CWG1PPS
: 5;
5482 extern __at(0x0E18) volatile __CWG1PPSbits_t CWG1PPSbits
;
5484 #define _CWG1PPS0 0x01
5485 #define _CWG1PPS1 0x02
5486 #define _CWG1PPS2 0x04
5487 #define _CWG1PPS3 0x08
5488 #define _CWG1PPS4 0x10
5490 //==============================================================================
5493 //==============================================================================
5496 extern __at(0x0E1A) __sfr MDCIN1PPS
;
5502 unsigned MDCIN1PPS0
: 1;
5503 unsigned MDCIN1PPS1
: 1;
5504 unsigned MDCIN1PPS2
: 1;
5505 unsigned MDCIN1PPS3
: 1;
5506 unsigned MDCIN1PPS4
: 1;
5514 unsigned MDCIN1PPS
: 5;
5517 } __MDCIN1PPSbits_t
;
5519 extern __at(0x0E1A) volatile __MDCIN1PPSbits_t MDCIN1PPSbits
;
5521 #define _MDCIN1PPS0 0x01
5522 #define _MDCIN1PPS1 0x02
5523 #define _MDCIN1PPS2 0x04
5524 #define _MDCIN1PPS3 0x08
5525 #define _MDCIN1PPS4 0x10
5527 //==============================================================================
5530 //==============================================================================
5533 extern __at(0x0E1B) __sfr MDCIN2PPS
;
5539 unsigned MDCIN2PPS0
: 1;
5540 unsigned MDCIN2PPS1
: 1;
5541 unsigned MDCIN2PPS2
: 1;
5542 unsigned MDCIN2PPS3
: 1;
5543 unsigned MDCIN2PPS4
: 1;
5551 unsigned MDCIN2PPS
: 5;
5554 } __MDCIN2PPSbits_t
;
5556 extern __at(0x0E1B) volatile __MDCIN2PPSbits_t MDCIN2PPSbits
;
5558 #define _MDCIN2PPS0 0x01
5559 #define _MDCIN2PPS1 0x02
5560 #define _MDCIN2PPS2 0x04
5561 #define _MDCIN2PPS3 0x08
5562 #define _MDCIN2PPS4 0x10
5564 //==============================================================================
5567 //==============================================================================
5570 extern __at(0x0E1C) __sfr MDMINPPS
;
5576 unsigned MDMINPPS0
: 1;
5577 unsigned MDMINPPS1
: 1;
5578 unsigned MDMINPPS2
: 1;
5579 unsigned MDMINPPS3
: 1;
5580 unsigned MDMINPPS4
: 1;
5588 unsigned MDMINPPS
: 5;
5593 extern __at(0x0E1C) volatile __MDMINPPSbits_t MDMINPPSbits
;
5595 #define _MDMINPPS0 0x01
5596 #define _MDMINPPS1 0x02
5597 #define _MDMINPPS2 0x04
5598 #define _MDMINPPS3 0x08
5599 #define _MDMINPPS4 0x10
5601 //==============================================================================
5604 //==============================================================================
5607 extern __at(0x0E20) __sfr SSP1CLKPPS
;
5613 unsigned SSP1CLKPPS0
: 1;
5614 unsigned SSP1CLKPPS1
: 1;
5615 unsigned SSP1CLKPPS2
: 1;
5616 unsigned SSP1CLKPPS3
: 1;
5617 unsigned SSP1CLKPPS4
: 1;
5625 unsigned SSP1CLKPPS
: 5;
5628 } __SSP1CLKPPSbits_t
;
5630 extern __at(0x0E20) volatile __SSP1CLKPPSbits_t SSP1CLKPPSbits
;
5632 #define _SSP1CLKPPS0 0x01
5633 #define _SSP1CLKPPS1 0x02
5634 #define _SSP1CLKPPS2 0x04
5635 #define _SSP1CLKPPS3 0x08
5636 #define _SSP1CLKPPS4 0x10
5638 //==============================================================================
5641 //==============================================================================
5644 extern __at(0x0E21) __sfr SSP1DATPPS
;
5650 unsigned SSP1DATPPS0
: 1;
5651 unsigned SSP1DATPPS1
: 1;
5652 unsigned SSP1DATPPS2
: 1;
5653 unsigned SSP1DATPPS3
: 1;
5654 unsigned SSP1DATPPS4
: 1;
5662 unsigned SSP1DATPPS
: 5;
5665 } __SSP1DATPPSbits_t
;
5667 extern __at(0x0E21) volatile __SSP1DATPPSbits_t SSP1DATPPSbits
;
5669 #define _SSP1DATPPS0 0x01
5670 #define _SSP1DATPPS1 0x02
5671 #define _SSP1DATPPS2 0x04
5672 #define _SSP1DATPPS3 0x08
5673 #define _SSP1DATPPS4 0x10
5675 //==============================================================================
5678 //==============================================================================
5681 extern __at(0x0E22) __sfr SSP1SSPPS
;
5687 unsigned SSP1SSPPS0
: 1;
5688 unsigned SSP1SSPPS1
: 1;
5689 unsigned SSP1SSPPS2
: 1;
5690 unsigned SSP1SSPPS3
: 1;
5691 unsigned SSP1SSPPS4
: 1;
5699 unsigned SSP1SSPPS
: 5;
5702 } __SSP1SSPPSbits_t
;
5704 extern __at(0x0E22) volatile __SSP1SSPPSbits_t SSP1SSPPSbits
;
5706 #define _SSP1SSPPS0 0x01
5707 #define _SSP1SSPPS1 0x02
5708 #define _SSP1SSPPS2 0x04
5709 #define _SSP1SSPPS3 0x08
5710 #define _SSP1SSPPS4 0x10
5712 //==============================================================================
5715 //==============================================================================
5718 extern __at(0x0E24) __sfr RXPPS
;
5724 unsigned RXPPS0
: 1;
5725 unsigned RXPPS1
: 1;
5726 unsigned RXPPS2
: 1;
5727 unsigned RXPPS3
: 1;
5728 unsigned RXPPS4
: 1;
5741 extern __at(0x0E24) volatile __RXPPSbits_t RXPPSbits
;
5743 #define _RXPPS0 0x01
5744 #define _RXPPS1 0x02
5745 #define _RXPPS2 0x04
5746 #define _RXPPS3 0x08
5747 #define _RXPPS4 0x10
5749 //==============================================================================
5752 //==============================================================================
5755 extern __at(0x0E25) __sfr TXPPS
;
5761 unsigned TXPPS0
: 1;
5762 unsigned TXPPS1
: 1;
5763 unsigned TXPPS2
: 1;
5764 unsigned TXPPS3
: 1;
5765 unsigned TXPPS4
: 1;
5778 extern __at(0x0E25) volatile __TXPPSbits_t TXPPSbits
;
5780 #define _TXPPS0 0x01
5781 #define _TXPPS1 0x02
5782 #define _TXPPS2 0x04
5783 #define _TXPPS3 0x08
5784 #define _TXPPS4 0x10
5786 //==============================================================================
5789 //==============================================================================
5792 extern __at(0x0E28) __sfr CLCIN0PPS
;
5798 unsigned CLCIN0PPS0
: 1;
5799 unsigned CLCIN0PPS1
: 1;
5800 unsigned CLCIN0PPS2
: 1;
5801 unsigned CLCIN0PPS3
: 1;
5802 unsigned CLCIN0PPS4
: 1;
5810 unsigned CLCIN0PPS
: 5;
5813 } __CLCIN0PPSbits_t
;
5815 extern __at(0x0E28) volatile __CLCIN0PPSbits_t CLCIN0PPSbits
;
5817 #define _CLCIN0PPS0 0x01
5818 #define _CLCIN0PPS1 0x02
5819 #define _CLCIN0PPS2 0x04
5820 #define _CLCIN0PPS3 0x08
5821 #define _CLCIN0PPS4 0x10
5823 //==============================================================================
5826 //==============================================================================
5829 extern __at(0x0E29) __sfr CLCIN1PPS
;
5835 unsigned CLCIN1PPS0
: 1;
5836 unsigned CLCIN1PPS1
: 1;
5837 unsigned CLCIN1PPS2
: 1;
5838 unsigned CLCIN1PPS3
: 1;
5839 unsigned CLCIN1PPS4
: 1;
5847 unsigned CLCIN1PPS
: 5;
5850 } __CLCIN1PPSbits_t
;
5852 extern __at(0x0E29) volatile __CLCIN1PPSbits_t CLCIN1PPSbits
;
5854 #define _CLCIN1PPS0 0x01
5855 #define _CLCIN1PPS1 0x02
5856 #define _CLCIN1PPS2 0x04
5857 #define _CLCIN1PPS3 0x08
5858 #define _CLCIN1PPS4 0x10
5860 //==============================================================================
5863 //==============================================================================
5866 extern __at(0x0E2A) __sfr CLCIN2PPS
;
5872 unsigned CLCIN2PPS0
: 1;
5873 unsigned CLCIN2PPS1
: 1;
5874 unsigned CLCIN2PPS2
: 1;
5875 unsigned CLCIN2PPS3
: 1;
5876 unsigned CLCIN2PPS4
: 1;
5884 unsigned CLCIN2PPS
: 5;
5887 } __CLCIN2PPSbits_t
;
5889 extern __at(0x0E2A) volatile __CLCIN2PPSbits_t CLCIN2PPSbits
;
5891 #define _CLCIN2PPS0 0x01
5892 #define _CLCIN2PPS1 0x02
5893 #define _CLCIN2PPS2 0x04
5894 #define _CLCIN2PPS3 0x08
5895 #define _CLCIN2PPS4 0x10
5897 //==============================================================================
5900 //==============================================================================
5903 extern __at(0x0E2B) __sfr CLCIN3PPS
;
5909 unsigned CLCIN3PPS0
: 1;
5910 unsigned CLCIN3PPS1
: 1;
5911 unsigned CLCIN3PPS2
: 1;
5912 unsigned CLCIN3PPS3
: 1;
5913 unsigned CLCIN3PPS4
: 1;
5921 unsigned CLCIN3PPS
: 5;
5924 } __CLCIN3PPSbits_t
;
5926 extern __at(0x0E2B) volatile __CLCIN3PPSbits_t CLCIN3PPSbits
;
5928 #define _CLCIN3PPS0 0x01
5929 #define _CLCIN3PPS1 0x02
5930 #define _CLCIN3PPS2 0x04
5931 #define _CLCIN3PPS3 0x08
5932 #define _CLCIN3PPS4 0x10
5934 //==============================================================================
5937 //==============================================================================
5940 extern __at(0x0E90) __sfr RA0PPS
;
5946 unsigned RA0PPS0
: 1;
5947 unsigned RA0PPS1
: 1;
5948 unsigned RA0PPS2
: 1;
5949 unsigned RA0PPS3
: 1;
5950 unsigned RA0PPS4
: 1;
5958 unsigned RA0PPS
: 5;
5963 extern __at(0x0E90) volatile __RA0PPSbits_t RA0PPSbits
;
5965 #define _RA0PPS0 0x01
5966 #define _RA0PPS1 0x02
5967 #define _RA0PPS2 0x04
5968 #define _RA0PPS3 0x08
5969 #define _RA0PPS4 0x10
5971 //==============================================================================
5974 //==============================================================================
5977 extern __at(0x0E91) __sfr RA1PPS
;
5983 unsigned RA1PPS0
: 1;
5984 unsigned RA1PPS1
: 1;
5985 unsigned RA1PPS2
: 1;
5986 unsigned RA1PPS3
: 1;
5987 unsigned RA1PPS4
: 1;
5995 unsigned RA1PPS
: 5;
6000 extern __at(0x0E91) volatile __RA1PPSbits_t RA1PPSbits
;
6002 #define _RA1PPS0 0x01
6003 #define _RA1PPS1 0x02
6004 #define _RA1PPS2 0x04
6005 #define _RA1PPS3 0x08
6006 #define _RA1PPS4 0x10
6008 //==============================================================================
6011 //==============================================================================
6014 extern __at(0x0E92) __sfr RA2PPS
;
6020 unsigned RA2PPS0
: 1;
6021 unsigned RA2PPS1
: 1;
6022 unsigned RA2PPS2
: 1;
6023 unsigned RA2PPS3
: 1;
6024 unsigned RA2PPS4
: 1;
6032 unsigned RA2PPS
: 5;
6037 extern __at(0x0E92) volatile __RA2PPSbits_t RA2PPSbits
;
6039 #define _RA2PPS0 0x01
6040 #define _RA2PPS1 0x02
6041 #define _RA2PPS2 0x04
6042 #define _RA2PPS3 0x08
6043 #define _RA2PPS4 0x10
6045 //==============================================================================
6048 //==============================================================================
6051 extern __at(0x0E94) __sfr RA4PPS
;
6057 unsigned RA4PPS0
: 1;
6058 unsigned RA4PPS1
: 1;
6059 unsigned RA4PPS2
: 1;
6060 unsigned RA4PPS3
: 1;
6061 unsigned RA4PPS4
: 1;
6069 unsigned RA4PPS
: 5;
6074 extern __at(0x0E94) volatile __RA4PPSbits_t RA4PPSbits
;
6076 #define _RA4PPS0 0x01
6077 #define _RA4PPS1 0x02
6078 #define _RA4PPS2 0x04
6079 #define _RA4PPS3 0x08
6080 #define _RA4PPS4 0x10
6082 //==============================================================================
6085 //==============================================================================
6088 extern __at(0x0E95) __sfr RA5PPS
;
6094 unsigned RA5PPS0
: 1;
6095 unsigned RA5PPS1
: 1;
6096 unsigned RA5PPS2
: 1;
6097 unsigned RA5PPS3
: 1;
6098 unsigned RA5PPS4
: 1;
6106 unsigned RA5PPS
: 5;
6111 extern __at(0x0E95) volatile __RA5PPSbits_t RA5PPSbits
;
6113 #define _RA5PPS0 0x01
6114 #define _RA5PPS1 0x02
6115 #define _RA5PPS2 0x04
6116 #define _RA5PPS3 0x08
6117 #define _RA5PPS4 0x10
6119 //==============================================================================
6122 //==============================================================================
6125 extern __at(0x0EA0) __sfr RC0PPS
;
6131 unsigned RC0PPS0
: 1;
6132 unsigned RC0PPS1
: 1;
6133 unsigned RC0PPS2
: 1;
6134 unsigned RC0PPS3
: 1;
6135 unsigned RC0PPS4
: 1;
6143 unsigned RC0PPS
: 5;
6148 extern __at(0x0EA0) volatile __RC0PPSbits_t RC0PPSbits
;
6150 #define _RC0PPS0 0x01
6151 #define _RC0PPS1 0x02
6152 #define _RC0PPS2 0x04
6153 #define _RC0PPS3 0x08
6154 #define _RC0PPS4 0x10
6156 //==============================================================================
6159 //==============================================================================
6162 extern __at(0x0EA1) __sfr RC1PPS
;
6168 unsigned RC1PPS0
: 1;
6169 unsigned RC1PPS1
: 1;
6170 unsigned RC1PPS2
: 1;
6171 unsigned RC1PPS3
: 1;
6172 unsigned RC1PPS4
: 1;
6180 unsigned RC1PPS
: 5;
6185 extern __at(0x0EA1) volatile __RC1PPSbits_t RC1PPSbits
;
6187 #define _RC1PPS0 0x01
6188 #define _RC1PPS1 0x02
6189 #define _RC1PPS2 0x04
6190 #define _RC1PPS3 0x08
6191 #define _RC1PPS4 0x10
6193 //==============================================================================
6196 //==============================================================================
6199 extern __at(0x0EA2) __sfr RC2PPS
;
6205 unsigned RC2PPS0
: 1;
6206 unsigned RC2PPS1
: 1;
6207 unsigned RC2PPS2
: 1;
6208 unsigned RC2PPS3
: 1;
6209 unsigned RC2PPS4
: 1;
6217 unsigned RC2PPS
: 5;
6222 extern __at(0x0EA2) volatile __RC2PPSbits_t RC2PPSbits
;
6224 #define _RC2PPS0 0x01
6225 #define _RC2PPS1 0x02
6226 #define _RC2PPS2 0x04
6227 #define _RC2PPS3 0x08
6228 #define _RC2PPS4 0x10
6230 //==============================================================================
6233 //==============================================================================
6236 extern __at(0x0EA3) __sfr RC3PPS
;
6242 unsigned RC3PPS0
: 1;
6243 unsigned RC3PPS1
: 1;
6244 unsigned RC3PPS2
: 1;
6245 unsigned RC3PPS3
: 1;
6246 unsigned RC3PPS4
: 1;
6254 unsigned RC3PPS
: 5;
6259 extern __at(0x0EA3) volatile __RC3PPSbits_t RC3PPSbits
;
6261 #define _RC3PPS0 0x01
6262 #define _RC3PPS1 0x02
6263 #define _RC3PPS2 0x04
6264 #define _RC3PPS3 0x08
6265 #define _RC3PPS4 0x10
6267 //==============================================================================
6270 //==============================================================================
6273 extern __at(0x0EA4) __sfr RC4PPS
;
6279 unsigned RC4PPS0
: 1;
6280 unsigned RC4PPS1
: 1;
6281 unsigned RC4PPS2
: 1;
6282 unsigned RC4PPS3
: 1;
6283 unsigned RC4PPS4
: 1;
6291 unsigned RC4PPS
: 5;
6296 extern __at(0x0EA4) volatile __RC4PPSbits_t RC4PPSbits
;
6298 #define _RC4PPS0 0x01
6299 #define _RC4PPS1 0x02
6300 #define _RC4PPS2 0x04
6301 #define _RC4PPS3 0x08
6302 #define _RC4PPS4 0x10
6304 //==============================================================================
6307 //==============================================================================
6310 extern __at(0x0EA5) __sfr RC5PPS
;
6316 unsigned RC5PPS0
: 1;
6317 unsigned RC5PPS1
: 1;
6318 unsigned RC5PPS2
: 1;
6319 unsigned RC5PPS3
: 1;
6320 unsigned RC5PPS4
: 1;
6328 unsigned RC5PPS
: 5;
6333 extern __at(0x0EA5) volatile __RC5PPSbits_t RC5PPSbits
;
6335 #define _RC5PPS0 0x01
6336 #define _RC5PPS1 0x02
6337 #define _RC5PPS2 0x04
6338 #define _RC5PPS3 0x08
6339 #define _RC5PPS4 0x10
6341 //==============================================================================
6344 //==============================================================================
6347 extern __at(0x0F0F) __sfr CLCDATA
;
6351 unsigned MLC1OUT
: 1;
6352 unsigned MLC2OUT
: 1;
6361 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
6363 #define _MLC1OUT 0x01
6364 #define _MLC2OUT 0x02
6366 //==============================================================================
6369 //==============================================================================
6372 extern __at(0x0F10) __sfr CLC1CON
;
6378 unsigned LC1MODE0
: 1;
6379 unsigned LC1MODE1
: 1;
6380 unsigned LC1MODE2
: 1;
6381 unsigned LC1INTN
: 1;
6382 unsigned LC1INTP
: 1;
6383 unsigned LC1OUT
: 1;
6402 unsigned LC1MODE
: 3;
6413 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
6415 #define _LC1MODE0 0x01
6417 #define _LC1MODE1 0x02
6419 #define _LC1MODE2 0x04
6421 #define _LC1INTN 0x08
6423 #define _LC1INTP 0x10
6425 #define _LC1OUT 0x20
6430 //==============================================================================
6433 //==============================================================================
6436 extern __at(0x0F11) __sfr CLC1POL
;
6442 unsigned LC1G1POL
: 1;
6443 unsigned LC1G2POL
: 1;
6444 unsigned LC1G3POL
: 1;
6445 unsigned LC1G4POL
: 1;
6449 unsigned LC1POL
: 1;
6465 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
6467 #define _LC1G1POL 0x01
6469 #define _LC1G2POL 0x02
6471 #define _LC1G3POL 0x04
6473 #define _LC1G4POL 0x08
6475 #define _LC1POL 0x80
6478 //==============================================================================
6481 //==============================================================================
6484 extern __at(0x0F12) __sfr CLC1SEL0
;
6490 unsigned LC1D1S0
: 1;
6491 unsigned LC1D1S1
: 1;
6492 unsigned LC1D1S2
: 1;
6493 unsigned LC1D1S3
: 1;
6494 unsigned LC1D1S4
: 1;
6520 unsigned LC1D1S
: 5;
6525 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
6527 #define _LC1D1S0 0x01
6529 #define _LC1D1S1 0x02
6531 #define _LC1D1S2 0x04
6533 #define _LC1D1S3 0x08
6535 #define _LC1D1S4 0x10
6538 //==============================================================================
6541 //==============================================================================
6544 extern __at(0x0F13) __sfr CLC1SEL1
;
6550 unsigned LC1D2S0
: 1;
6551 unsigned LC1D2S1
: 1;
6552 unsigned LC1D2S2
: 1;
6553 unsigned LC1D2S3
: 1;
6554 unsigned LC1D2S4
: 1;
6574 unsigned LC1D2S
: 5;
6585 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
6587 #define _LC1D2S0 0x01
6589 #define _LC1D2S1 0x02
6591 #define _LC1D2S2 0x04
6593 #define _LC1D2S3 0x08
6595 #define _LC1D2S4 0x10
6598 //==============================================================================
6601 //==============================================================================
6604 extern __at(0x0F14) __sfr CLC1SEL2
;
6610 unsigned LC1D3S0
: 1;
6611 unsigned LC1D3S1
: 1;
6612 unsigned LC1D3S2
: 1;
6613 unsigned LC1D3S3
: 1;
6614 unsigned LC1D3S4
: 1;
6640 unsigned LC1D3S
: 5;
6645 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
6647 #define _LC1D3S0 0x01
6649 #define _LC1D3S1 0x02
6651 #define _LC1D3S2 0x04
6653 #define _LC1D3S3 0x08
6655 #define _LC1D3S4 0x10
6658 //==============================================================================
6661 //==============================================================================
6664 extern __at(0x0F15) __sfr CLC1SEL3
;
6670 unsigned LC1D4S0
: 1;
6671 unsigned LC1D4S1
: 1;
6672 unsigned LC1D4S2
: 1;
6673 unsigned LC1D4S3
: 1;
6674 unsigned LC1D4S4
: 1;
6700 unsigned LC1D4S
: 5;
6705 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
6707 #define _LC1D4S0 0x01
6709 #define _LC1D4S1 0x02
6711 #define _LC1D4S2 0x04
6713 #define _LC1D4S3 0x08
6715 #define _LC1D4S4 0x10
6718 //==============================================================================
6721 //==============================================================================
6724 extern __at(0x0F16) __sfr CLC1GLS0
;
6730 unsigned LC1G1D1N
: 1;
6731 unsigned LC1G1D1T
: 1;
6732 unsigned LC1G1D2N
: 1;
6733 unsigned LC1G1D2T
: 1;
6734 unsigned LC1G1D3N
: 1;
6735 unsigned LC1G1D3T
: 1;
6736 unsigned LC1G1D4N
: 1;
6737 unsigned LC1G1D4T
: 1;
6753 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
6755 #define _LC1G1D1N 0x01
6757 #define _LC1G1D1T 0x02
6759 #define _LC1G1D2N 0x04
6761 #define _LC1G1D2T 0x08
6763 #define _LC1G1D3N 0x10
6765 #define _LC1G1D3T 0x20
6767 #define _LC1G1D4N 0x40
6769 #define _LC1G1D4T 0x80
6772 //==============================================================================
6775 //==============================================================================
6778 extern __at(0x0F17) __sfr CLC1GLS1
;
6784 unsigned LC1G2D1N
: 1;
6785 unsigned LC1G2D1T
: 1;
6786 unsigned LC1G2D2N
: 1;
6787 unsigned LC1G2D2T
: 1;
6788 unsigned LC1G2D3N
: 1;
6789 unsigned LC1G2D3T
: 1;
6790 unsigned LC1G2D4N
: 1;
6791 unsigned LC1G2D4T
: 1;
6807 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
6809 #define _CLC1GLS1_LC1G2D1N 0x01
6810 #define _CLC1GLS1_D1N 0x01
6811 #define _CLC1GLS1_LC1G2D1T 0x02
6812 #define _CLC1GLS1_D1T 0x02
6813 #define _CLC1GLS1_LC1G2D2N 0x04
6814 #define _CLC1GLS1_D2N 0x04
6815 #define _CLC1GLS1_LC1G2D2T 0x08
6816 #define _CLC1GLS1_D2T 0x08
6817 #define _CLC1GLS1_LC1G2D3N 0x10
6818 #define _CLC1GLS1_D3N 0x10
6819 #define _CLC1GLS1_LC1G2D3T 0x20
6820 #define _CLC1GLS1_D3T 0x20
6821 #define _CLC1GLS1_LC1G2D4N 0x40
6822 #define _CLC1GLS1_D4N 0x40
6823 #define _CLC1GLS1_LC1G2D4T 0x80
6824 #define _CLC1GLS1_D4T 0x80
6826 //==============================================================================
6829 //==============================================================================
6832 extern __at(0x0F18) __sfr CLC1GLS2
;
6838 unsigned LC1G3D1N
: 1;
6839 unsigned LC1G3D1T
: 1;
6840 unsigned LC1G3D2N
: 1;
6841 unsigned LC1G3D2T
: 1;
6842 unsigned LC1G3D3N
: 1;
6843 unsigned LC1G3D3T
: 1;
6844 unsigned LC1G3D4N
: 1;
6845 unsigned LC1G3D4T
: 1;
6861 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
6863 #define _CLC1GLS2_LC1G3D1N 0x01
6864 #define _CLC1GLS2_D1N 0x01
6865 #define _CLC1GLS2_LC1G3D1T 0x02
6866 #define _CLC1GLS2_D1T 0x02
6867 #define _CLC1GLS2_LC1G3D2N 0x04
6868 #define _CLC1GLS2_D2N 0x04
6869 #define _CLC1GLS2_LC1G3D2T 0x08
6870 #define _CLC1GLS2_D2T 0x08
6871 #define _CLC1GLS2_LC1G3D3N 0x10
6872 #define _CLC1GLS2_D3N 0x10
6873 #define _CLC1GLS2_LC1G3D3T 0x20
6874 #define _CLC1GLS2_D3T 0x20
6875 #define _CLC1GLS2_LC1G3D4N 0x40
6876 #define _CLC1GLS2_D4N 0x40
6877 #define _CLC1GLS2_LC1G3D4T 0x80
6878 #define _CLC1GLS2_D4T 0x80
6880 //==============================================================================
6883 //==============================================================================
6886 extern __at(0x0F19) __sfr CLC1GLS3
;
6892 unsigned LC1G4D1N
: 1;
6893 unsigned LC1G4D1T
: 1;
6894 unsigned LC1G4D2N
: 1;
6895 unsigned LC1G4D2T
: 1;
6896 unsigned LC1G4D3N
: 1;
6897 unsigned LC1G4D3T
: 1;
6898 unsigned LC1G4D4N
: 1;
6899 unsigned LC1G4D4T
: 1;
6915 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
6917 #define _LC1G4D1N 0x01
6919 #define _LC1G4D1T 0x02
6921 #define _LC1G4D2N 0x04
6923 #define _LC1G4D2T 0x08
6925 #define _LC1G4D3N 0x10
6927 #define _LC1G4D3T 0x20
6929 #define _LC1G4D4N 0x40
6931 #define _LC1G4D4T 0x80
6934 //==============================================================================
6937 //==============================================================================
6940 extern __at(0x0F1A) __sfr CLC2CON
;
6946 unsigned LC2MODE0
: 1;
6947 unsigned LC2MODE1
: 1;
6948 unsigned LC2MODE2
: 1;
6949 unsigned LC2INTN
: 1;
6950 unsigned LC2INTP
: 1;
6951 unsigned LC2OUT
: 1;
6970 unsigned LC2MODE
: 3;
6981 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
6983 #define _CLC2CON_LC2MODE0 0x01
6984 #define _CLC2CON_MODE0 0x01
6985 #define _CLC2CON_LC2MODE1 0x02
6986 #define _CLC2CON_MODE1 0x02
6987 #define _CLC2CON_LC2MODE2 0x04
6988 #define _CLC2CON_MODE2 0x04
6989 #define _CLC2CON_LC2INTN 0x08
6990 #define _CLC2CON_INTN 0x08
6991 #define _CLC2CON_LC2INTP 0x10
6992 #define _CLC2CON_INTP 0x10
6993 #define _CLC2CON_LC2OUT 0x20
6994 #define _CLC2CON_OUT 0x20
6995 #define _CLC2CON_LC2EN 0x80
6996 #define _CLC2CON_EN 0x80
6998 //==============================================================================
7001 //==============================================================================
7004 extern __at(0x0F1B) __sfr CLC2POL
;
7010 unsigned LC2G1POL
: 1;
7011 unsigned LC2G2POL
: 1;
7012 unsigned LC2G3POL
: 1;
7013 unsigned LC2G4POL
: 1;
7017 unsigned LC2POL
: 1;
7033 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
7035 #define _CLC2POL_LC2G1POL 0x01
7036 #define _CLC2POL_G1POL 0x01
7037 #define _CLC2POL_LC2G2POL 0x02
7038 #define _CLC2POL_G2POL 0x02
7039 #define _CLC2POL_LC2G3POL 0x04
7040 #define _CLC2POL_G3POL 0x04
7041 #define _CLC2POL_LC2G4POL 0x08
7042 #define _CLC2POL_G4POL 0x08
7043 #define _CLC2POL_LC2POL 0x80
7044 #define _CLC2POL_POL 0x80
7046 //==============================================================================
7049 //==============================================================================
7052 extern __at(0x0F1C) __sfr CLC2SEL0
;
7058 unsigned LC2D1S0
: 1;
7059 unsigned LC2D1S1
: 1;
7060 unsigned LC2D1S2
: 1;
7061 unsigned LC2D1S3
: 1;
7062 unsigned LC2D1S4
: 1;
7088 unsigned LC2D1S
: 5;
7093 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
7095 #define _CLC2SEL0_LC2D1S0 0x01
7096 #define _CLC2SEL0_D1S0 0x01
7097 #define _CLC2SEL0_LC2D1S1 0x02
7098 #define _CLC2SEL0_D1S1 0x02
7099 #define _CLC2SEL0_LC2D1S2 0x04
7100 #define _CLC2SEL0_D1S2 0x04
7101 #define _CLC2SEL0_LC2D1S3 0x08
7102 #define _CLC2SEL0_D1S3 0x08
7103 #define _CLC2SEL0_LC2D1S4 0x10
7104 #define _CLC2SEL0_D1S4 0x10
7106 //==============================================================================
7109 //==============================================================================
7112 extern __at(0x0F1D) __sfr CLC2SEL1
;
7118 unsigned LC2D2S0
: 1;
7119 unsigned LC2D2S1
: 1;
7120 unsigned LC2D2S2
: 1;
7121 unsigned LC2D2S3
: 1;
7122 unsigned LC2D2S4
: 1;
7148 unsigned LC2D2S
: 5;
7153 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
7155 #define _CLC2SEL1_LC2D2S0 0x01
7156 #define _CLC2SEL1_D2S0 0x01
7157 #define _CLC2SEL1_LC2D2S1 0x02
7158 #define _CLC2SEL1_D2S1 0x02
7159 #define _CLC2SEL1_LC2D2S2 0x04
7160 #define _CLC2SEL1_D2S2 0x04
7161 #define _CLC2SEL1_LC2D2S3 0x08
7162 #define _CLC2SEL1_D2S3 0x08
7163 #define _CLC2SEL1_LC2D2S4 0x10
7164 #define _CLC2SEL1_D2S4 0x10
7166 //==============================================================================
7169 //==============================================================================
7172 extern __at(0x0F1E) __sfr CLC2SEL2
;
7178 unsigned LC2D3S0
: 1;
7179 unsigned LC2D3S1
: 1;
7180 unsigned LC2D3S2
: 1;
7181 unsigned LC2D3S3
: 1;
7182 unsigned LC2D3S4
: 1;
7202 unsigned LC2D3S
: 5;
7213 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
7215 #define _CLC2SEL2_LC2D3S0 0x01
7216 #define _CLC2SEL2_D3S0 0x01
7217 #define _CLC2SEL2_LC2D3S1 0x02
7218 #define _CLC2SEL2_D3S1 0x02
7219 #define _CLC2SEL2_LC2D3S2 0x04
7220 #define _CLC2SEL2_D3S2 0x04
7221 #define _CLC2SEL2_LC2D3S3 0x08
7222 #define _CLC2SEL2_D3S3 0x08
7223 #define _CLC2SEL2_LC2D3S4 0x10
7224 #define _CLC2SEL2_D3S4 0x10
7226 //==============================================================================
7229 //==============================================================================
7232 extern __at(0x0F1F) __sfr CLC2SEL3
;
7238 unsigned LC2D4S0
: 1;
7239 unsigned LC2D4S1
: 1;
7240 unsigned LC2D4S2
: 1;
7241 unsigned LC2D4S3
: 1;
7242 unsigned LC2D4S4
: 1;
7262 unsigned LC2D4S
: 5;
7273 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
7275 #define _CLC2SEL3_LC2D4S0 0x01
7276 #define _CLC2SEL3_D4S0 0x01
7277 #define _CLC2SEL3_LC2D4S1 0x02
7278 #define _CLC2SEL3_D4S1 0x02
7279 #define _CLC2SEL3_LC2D4S2 0x04
7280 #define _CLC2SEL3_D4S2 0x04
7281 #define _CLC2SEL3_LC2D4S3 0x08
7282 #define _CLC2SEL3_D4S3 0x08
7283 #define _CLC2SEL3_LC2D4S4 0x10
7284 #define _CLC2SEL3_D4S4 0x10
7286 //==============================================================================
7289 //==============================================================================
7292 extern __at(0x0F20) __sfr CLC2GLS0
;
7298 unsigned LC2G1D1N
: 1;
7299 unsigned LC2G1D1T
: 1;
7300 unsigned LC2G1D2N
: 1;
7301 unsigned LC2G1D2T
: 1;
7302 unsigned LC2G1D3N
: 1;
7303 unsigned LC2G1D3T
: 1;
7304 unsigned LC2G1D4N
: 1;
7305 unsigned LC2G1D4T
: 1;
7321 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
7323 #define _CLC2GLS0_LC2G1D1N 0x01
7324 #define _CLC2GLS0_D1N 0x01
7325 #define _CLC2GLS0_LC2G1D1T 0x02
7326 #define _CLC2GLS0_D1T 0x02
7327 #define _CLC2GLS0_LC2G1D2N 0x04
7328 #define _CLC2GLS0_D2N 0x04
7329 #define _CLC2GLS0_LC2G1D2T 0x08
7330 #define _CLC2GLS0_D2T 0x08
7331 #define _CLC2GLS0_LC2G1D3N 0x10
7332 #define _CLC2GLS0_D3N 0x10
7333 #define _CLC2GLS0_LC2G1D3T 0x20
7334 #define _CLC2GLS0_D3T 0x20
7335 #define _CLC2GLS0_LC2G1D4N 0x40
7336 #define _CLC2GLS0_D4N 0x40
7337 #define _CLC2GLS0_LC2G1D4T 0x80
7338 #define _CLC2GLS0_D4T 0x80
7340 //==============================================================================
7343 //==============================================================================
7346 extern __at(0x0F21) __sfr CLC2GLS1
;
7352 unsigned LC2G2D1N
: 1;
7353 unsigned LC2G2D1T
: 1;
7354 unsigned LC2G2D2N
: 1;
7355 unsigned LC2G2D2T
: 1;
7356 unsigned LC2G2D3N
: 1;
7357 unsigned LC2G2D3T
: 1;
7358 unsigned LC2G2D4N
: 1;
7359 unsigned LC2G2D4T
: 1;
7375 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
7377 #define _CLC2GLS1_LC2G2D1N 0x01
7378 #define _CLC2GLS1_D1N 0x01
7379 #define _CLC2GLS1_LC2G2D1T 0x02
7380 #define _CLC2GLS1_D1T 0x02
7381 #define _CLC2GLS1_LC2G2D2N 0x04
7382 #define _CLC2GLS1_D2N 0x04
7383 #define _CLC2GLS1_LC2G2D2T 0x08
7384 #define _CLC2GLS1_D2T 0x08
7385 #define _CLC2GLS1_LC2G2D3N 0x10
7386 #define _CLC2GLS1_D3N 0x10
7387 #define _CLC2GLS1_LC2G2D3T 0x20
7388 #define _CLC2GLS1_D3T 0x20
7389 #define _CLC2GLS1_LC2G2D4N 0x40
7390 #define _CLC2GLS1_D4N 0x40
7391 #define _CLC2GLS1_LC2G2D4T 0x80
7392 #define _CLC2GLS1_D4T 0x80
7394 //==============================================================================
7397 //==============================================================================
7400 extern __at(0x0F22) __sfr CLC2GLS2
;
7406 unsigned LC2G3D1N
: 1;
7407 unsigned LC2G3D1T
: 1;
7408 unsigned LC2G3D2N
: 1;
7409 unsigned LC2G3D2T
: 1;
7410 unsigned LC2G3D3N
: 1;
7411 unsigned LC2G3D3T
: 1;
7412 unsigned LC2G3D4N
: 1;
7413 unsigned LC2G3D4T
: 1;
7429 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
7431 #define _CLC2GLS2_LC2G3D1N 0x01
7432 #define _CLC2GLS2_D1N 0x01
7433 #define _CLC2GLS2_LC2G3D1T 0x02
7434 #define _CLC2GLS2_D1T 0x02
7435 #define _CLC2GLS2_LC2G3D2N 0x04
7436 #define _CLC2GLS2_D2N 0x04
7437 #define _CLC2GLS2_LC2G3D2T 0x08
7438 #define _CLC2GLS2_D2T 0x08
7439 #define _CLC2GLS2_LC2G3D3N 0x10
7440 #define _CLC2GLS2_D3N 0x10
7441 #define _CLC2GLS2_LC2G3D3T 0x20
7442 #define _CLC2GLS2_D3T 0x20
7443 #define _CLC2GLS2_LC2G3D4N 0x40
7444 #define _CLC2GLS2_D4N 0x40
7445 #define _CLC2GLS2_LC2G3D4T 0x80
7446 #define _CLC2GLS2_D4T 0x80
7448 //==============================================================================
7451 //==============================================================================
7454 extern __at(0x0F23) __sfr CLC2GLS3
;
7460 unsigned LC2G4D1N
: 1;
7461 unsigned LC2G4D1T
: 1;
7462 unsigned LC2G4D2N
: 1;
7463 unsigned LC2G4D2T
: 1;
7464 unsigned LC2G4D3N
: 1;
7465 unsigned LC2G4D3T
: 1;
7466 unsigned LC2G4D4N
: 1;
7467 unsigned LC2G4D4T
: 1;
7483 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
7485 #define _CLC2GLS3_LC2G4D1N 0x01
7486 #define _CLC2GLS3_G4D1N 0x01
7487 #define _CLC2GLS3_LC2G4D1T 0x02
7488 #define _CLC2GLS3_G4D1T 0x02
7489 #define _CLC2GLS3_LC2G4D2N 0x04
7490 #define _CLC2GLS3_G4D2N 0x04
7491 #define _CLC2GLS3_LC2G4D2T 0x08
7492 #define _CLC2GLS3_G4D2T 0x08
7493 #define _CLC2GLS3_LC2G4D3N 0x10
7494 #define _CLC2GLS3_G4D3N 0x10
7495 #define _CLC2GLS3_LC2G4D3T 0x20
7496 #define _CLC2GLS3_G4D3T 0x20
7497 #define _CLC2GLS3_LC2G4D4N 0x40
7498 #define _CLC2GLS3_G4D4N 0x40
7499 #define _CLC2GLS3_LC2G4D4T 0x80
7500 #define _CLC2GLS3_G4D4T 0x80
7502 //==============================================================================
7505 //==============================================================================
7508 extern __at(0x0FE4) __sfr STATUS_SHAD
;
7512 unsigned C_SHAD
: 1;
7513 unsigned DC_SHAD
: 1;
7514 unsigned Z_SHAD
: 1;
7520 } __STATUS_SHADbits_t
;
7522 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
7524 #define _C_SHAD 0x01
7525 #define _DC_SHAD 0x02
7526 #define _Z_SHAD 0x04
7528 //==============================================================================
7530 extern __at(0x0FE5) __sfr WREG_SHAD
;
7531 extern __at(0x0FE6) __sfr BSR_SHAD
;
7532 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
7533 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
7534 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
7535 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
7536 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
7537 extern __at(0x0FED) __sfr STKPTR
;
7538 extern __at(0x0FEE) __sfr TOSL
;
7539 extern __at(0x0FEF) __sfr TOSH
;
7541 //==============================================================================
7543 // Configuration Bits
7545 //==============================================================================
7547 #define _CONFIG1 0x8007
7548 #define _CONFIG2 0x8008
7549 #define _CONFIG3 0x8009
7550 #define _CONFIG4 0x800A
7552 //----------------------------- CONFIG1 Options -------------------------------
7554 #define _FEXTOSC_LP 0x3FF8 // LP (crystal oscillator) optimized for 32.768 kHz.
7555 #define _FEXTOSC_XT 0x3FF9 // XT (crystal oscillator) from 100 kHz to 4 MHz.
7556 #define _FEXTOSC_HS 0x3FFA // HS (crystal oscillator) above 4 MHz.
7557 #define _FEXTOSC_OFF 0x3FFC // Oscillator not enabled.
7558 #define _FEXTOSC_ECL 0x3FFD // EC (external clock) below 100 kHz.
7559 #define _FEXTOSC_ECM 0x3FFE // EC (external clock) for 100 kHz to 8 MHz.
7560 #define _FEXTOSC_ECH 0x3FFF // EC (external clock) above 8 MHz.
7561 #define _RSTOSC_HFINT32 0x3F8F // HFINTOSC with 2x PLL (32MHz).
7562 #define _RSTOSC_EXT4X 0x3F9F // EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits.
7563 #define _RSTOSC_SOSC 0x3FBF // SOSC (31kHz).
7564 #define _RSTOSC_LFINT 0x3FCF // LFINTOSC (31kHz).
7565 #define _RSTOSC_HFINT1 0x3FEF // HFINTOSC (1MHz).
7566 #define _RSTOSC_EXT1X 0x3FFF // EXTOSC operating per FEXTOSC bits.
7567 #define _CLKOUTEN_ON 0x3EFF // CLKOUT function is enabled; FOSC/4 clock appears at OSC2.
7568 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled; I/O or oscillator function on OSC2.
7569 #define _CSWEN_OFF 0x37FF // The NOSC and NDIV bits cannot be changed by user software.
7570 #define _CSWEN_ON 0x3FFF // Writing to NOSC and NDIV is allowed.
7571 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
7572 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
7574 //----------------------------- CONFIG2 Options -------------------------------
7576 #define _MCLRE_OFF 0x3FFE // MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of port pin's WPU control bit.
7577 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR; Weak pull-up enabled.
7578 #define _PWRTE_ON 0x3FFD // PWRT enabled.
7579 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
7580 #define _WDTE_OFF 0x3FF3 // WDT disabled; SWDTEN is ignored.
7581 #define _WDTE_SWDTEN 0x3FF7 // WDT controlled by the SWDTEN bit in the WDTCON register.
7582 #define _WDTE_SLEEP 0x3FFB // WDT enabled while running and disabled in SLEEP/IDLE; SWDTEN is ignored.
7583 #define _WDTE_ON 0x3FFF // WDT enabled, SWDTEN is ignored.
7584 #define _LPBOREN_ON 0x3FDF // ULPBOR enabled.
7585 #define _LPBOREN_OFF 0x3FFF // ULPBOR disabled.
7586 #define _BOREN_OFF 0x3F3F // Brown-out Reset disabled.
7587 #define _BOREN_SBOREN 0x3F7F // Brown-out Reset enabled according to SBOREN.
7588 #define _BOREN_SLEEP 0x3FBF // Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored.
7589 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled, SBOREN bit ignored.
7590 #define _BORV_HIGH 0x3DFF // Brown-out voltage (Vbor) set to 2.7V.
7591 #define _BORV_LOW 0x3FFF // Brown-out voltage (Vbor) set to 2.45V.
7592 #define _PPS1WAY_OFF 0x37FF // The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence).
7593 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle.
7594 #define _STVREN_OFF 0x2FFF // Stack Overflow or Underflow will not cause a Reset.
7595 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
7596 #define _DEBUG_ON 0x1FFF // Background debugger enabled.
7597 #define _DEBUG_OFF 0x3FFF // Background debugger disabled.
7599 //----------------------------- CONFIG3 Options -------------------------------
7601 #define _WRT_ALL 0x3FFC // 0000h to 07FFh write protected, no addresses may be modified.
7602 #define _WRT_HALF 0x3FFD // 0000h to 03FFh write-protected, 0400h to 07FFh may be modified.
7603 #define _WRT_BOOT 0x3FFE // 0000h to 01FFh write-protected, 0200h to 07FFh may be modified.
7604 #define _WRT_OFF 0x3FFF // Write protection off.
7605 #define _LVP_OFF 0x1FFF // High Voltage on MCLR/VPP must be used for programming.
7606 #define _LVP_ON 0x3FFF // Low Voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.
7608 //----------------------------- CONFIG4 Options -------------------------------
7610 #define _CP_ON 0x3FFE // User NVM code protection enabled.
7611 #define _CP_OFF 0x3FFF // User NVM code protection disabled.
7612 #define _CPD_ON 0x3FFD // Data NVM code protection enabled.
7613 #define _CPD_OFF 0x3FFF // Data NVM code protection disabled.
7615 //==============================================================================
7617 #define _DEVID1 0x8006
7619 #define _IDLOC0 0x8000
7620 #define _IDLOC1 0x8001
7621 #define _IDLOC2 0x8002
7622 #define _IDLOC3 0x8003
7624 //==============================================================================
7626 #ifndef NO_BIT_DEFINES
7628 #define ADACT0 ADACTbits.ADACT0 // bit 0
7629 #define ADACT1 ADACTbits.ADACT1 // bit 1
7630 #define ADACT2 ADACTbits.ADACT2 // bit 2
7631 #define ADACT3 ADACTbits.ADACT3 // bit 3
7633 #define ADON ADCON0bits.ADON // bit 0
7634 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
7635 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
7636 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
7637 #define CHS0 ADCON0bits.CHS0 // bit 2
7638 #define CHS1 ADCON0bits.CHS1 // bit 3
7639 #define CHS2 ADCON0bits.CHS2 // bit 4
7640 #define CHS3 ADCON0bits.CHS3 // bit 5
7641 #define CHS4 ADCON0bits.CHS4 // bit 6
7642 #define CHS5 ADCON0bits.CHS5 // bit 7
7644 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
7645 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
7646 #define ADNREF ADCON1bits.ADNREF // bit 2
7647 #define ADCS0 ADCON1bits.ADCS0 // bit 4
7648 #define ADCS1 ADCON1bits.ADCS1 // bit 5
7649 #define ADCS2 ADCON1bits.ADCS2 // bit 6
7650 #define ADFM ADCON1bits.ADFM // bit 7
7652 #define ANSA0 ANSELAbits.ANSA0 // bit 0
7653 #define ANSA1 ANSELAbits.ANSA1 // bit 1
7654 #define ANSA2 ANSELAbits.ANSA2 // bit 2
7655 #define ANSA4 ANSELAbits.ANSA4 // bit 4
7656 #define ANSA5 ANSELAbits.ANSA5 // bit 5
7658 #define ANSC0 ANSELCbits.ANSC0 // bit 0
7659 #define ANSC1 ANSELCbits.ANSC1 // bit 1
7660 #define ANSC2 ANSELCbits.ANSC2 // bit 2
7661 #define ANSC3 ANSELCbits.ANSC3 // bit 3
7662 #define ANSC4 ANSELCbits.ANSC4 // bit 4
7663 #define ANSC5 ANSELCbits.ANSC5 // bit 5
7665 #define ABDEN BAUD1CONbits.ABDEN // bit 0
7666 #define WUE BAUD1CONbits.WUE // bit 1
7667 #define BRG16 BAUD1CONbits.BRG16 // bit 3
7668 #define SCKP BAUD1CONbits.SCKP // bit 4
7669 #define RCIDL BAUD1CONbits.RCIDL // bit 6
7670 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
7672 #define BORRDY BORCONbits.BORRDY // bit 0
7673 #define SBOREN BORCONbits.SBOREN // bit 7
7675 #define BSR0 BSRbits.BSR0 // bit 0
7676 #define BSR1 BSRbits.BSR1 // bit 1
7677 #define BSR2 BSRbits.BSR2 // bit 2
7678 #define BSR3 BSRbits.BSR3 // bit 3
7679 #define BSR4 BSRbits.BSR4 // bit 4
7681 #define CCDS0 CCDCONbits.CCDS0 // bit 0
7682 #define CCDS1 CCDCONbits.CCDS1 // bit 1
7683 #define CCDEN CCDCONbits.CCDEN // bit 7
7685 #define CCDNA0 CCDNAbits.CCDNA0 // bit 0
7686 #define CCDNA1 CCDNAbits.CCDNA1 // bit 1
7687 #define CCDNA2 CCDNAbits.CCDNA2 // bit 2
7688 #define CCDNA4 CCDNAbits.CCDNA4 // bit 4
7689 #define CCDNA5 CCDNAbits.CCDNA5 // bit 5
7691 #define CCDNC0 CCDNCbits.CCDNC0 // bit 0
7692 #define CCDNC1 CCDNCbits.CCDNC1 // bit 1
7693 #define CCDNC2 CCDNCbits.CCDNC2 // bit 2
7694 #define CCDNC3 CCDNCbits.CCDNC3 // bit 3
7695 #define CCDNC4 CCDNCbits.CCDNC4 // bit 4
7696 #define CCDNC5 CCDNCbits.CCDNC5 // bit 5
7698 #define CCDPA0 CCDPAbits.CCDPA0 // bit 0
7699 #define CCDPA1 CCDPAbits.CCDPA1 // bit 1
7700 #define CCDPA2 CCDPAbits.CCDPA2 // bit 2
7701 #define CCDPA4 CCDPAbits.CCDPA4 // bit 4
7702 #define CCDPA5 CCDPAbits.CCDPA5 // bit 5
7704 #define CCDPC0 CCDPCbits.CCDPC0 // bit 0
7705 #define CCDPC1 CCDPCbits.CCDPC1 // bit 1
7706 #define CCDPC2 CCDPCbits.CCDPC2 // bit 2
7707 #define CCDPC3 CCDPCbits.CCDPC3 // bit 3
7708 #define CCDPC4 CCDPCbits.CCDPC4 // bit 4
7709 #define CCDPC5 CCDPCbits.CCDPC5 // bit 5
7711 #define CCP1CTS0 CCP1CAPbits.CCP1CTS0 // bit 0
7712 #define CCP1CTS1 CCP1CAPbits.CCP1CTS1 // bit 1
7713 #define CCP1CTS2 CCP1CAPbits.CCP1CTS2 // bit 2
7715 #define CCP1MODE0 CCP1CONbits.CCP1MODE0 // bit 0
7716 #define CCP1MODE1 CCP1CONbits.CCP1MODE1 // bit 1
7717 #define CCP1MODE2 CCP1CONbits.CCP1MODE2 // bit 2
7718 #define CCP1MODE3 CCP1CONbits.CCP1MODE3 // bit 3
7719 #define CCP1FMT CCP1CONbits.CCP1FMT // bit 4
7720 #define CCP1OUT CCP1CONbits.CCP1OUT // bit 5
7721 #define CCP1EN CCP1CONbits.CCP1EN // bit 7
7723 #define CCP1PPS0 CCP1PPSbits.CCP1PPS0 // bit 0
7724 #define CCP1PPS1 CCP1PPSbits.CCP1PPS1 // bit 1
7725 #define CCP1PPS2 CCP1PPSbits.CCP1PPS2 // bit 2
7726 #define CCP1PPS3 CCP1PPSbits.CCP1PPS3 // bit 3
7727 #define CCP1PPS4 CCP1PPSbits.CCP1PPS4 // bit 4
7729 #define CCP2CTS0 CCP2CAPbits.CCP2CTS0 // bit 0
7730 #define CCP2CTS1 CCP2CAPbits.CCP2CTS1 // bit 1
7731 #define CCP2CTS2 CCP2CAPbits.CCP2CTS2 // bit 2
7733 #define CCP2MODE0 CCP2CONbits.CCP2MODE0 // bit 0
7734 #define CCP2MODE1 CCP2CONbits.CCP2MODE1 // bit 1
7735 #define CCP2MODE2 CCP2CONbits.CCP2MODE2 // bit 2
7736 #define CCP2MODE3 CCP2CONbits.CCP2MODE3 // bit 3
7737 #define CCP2FMT CCP2CONbits.CCP2FMT // bit 4
7738 #define CCP2OUT CCP2CONbits.CCP2OUT // bit 5
7739 #define CCP2EN CCP2CONbits.CCP2EN // bit 7
7741 #define CCP2PPS0 CCP2PPSbits.CCP2PPS0 // bit 0
7742 #define CCP2PPS1 CCP2PPSbits.CCP2PPS1 // bit 1
7743 #define CCP2PPS2 CCP2PPSbits.CCP2PPS2 // bit 2
7744 #define CCP2PPS3 CCP2PPSbits.CCP2PPS3 // bit 3
7745 #define CCP2PPS4 CCP2PPSbits.CCP2PPS4 // bit 4
7747 #define C1TSEL CCPTMRSbits.C1TSEL // bit 0
7748 #define C2TSEL CCPTMRSbits.C2TSEL // bit 2
7750 #define LC1MODE0 CLC1CONbits.LC1MODE0 // bit 0, shadows bit in CLC1CONbits
7751 #define MODE0 CLC1CONbits.MODE0 // bit 0, shadows bit in CLC1CONbits
7752 #define LC1MODE1 CLC1CONbits.LC1MODE1 // bit 1, shadows bit in CLC1CONbits
7753 #define MODE1 CLC1CONbits.MODE1 // bit 1, shadows bit in CLC1CONbits
7754 #define LC1MODE2 CLC1CONbits.LC1MODE2 // bit 2, shadows bit in CLC1CONbits
7755 #define MODE2 CLC1CONbits.MODE2 // bit 2, shadows bit in CLC1CONbits
7756 #define LC1INTN CLC1CONbits.LC1INTN // bit 3, shadows bit in CLC1CONbits
7757 #define INTN CLC1CONbits.INTN // bit 3, shadows bit in CLC1CONbits
7758 #define LC1INTP CLC1CONbits.LC1INTP // bit 4, shadows bit in CLC1CONbits
7759 #define INTP CLC1CONbits.INTP // bit 4, shadows bit in CLC1CONbits
7760 #define LC1OUT CLC1CONbits.LC1OUT // bit 5, shadows bit in CLC1CONbits
7761 #define OUT CLC1CONbits.OUT // bit 5, shadows bit in CLC1CONbits
7762 #define LC1EN CLC1CONbits.LC1EN // bit 7, shadows bit in CLC1CONbits
7763 #define EN CLC1CONbits.EN // bit 7, shadows bit in CLC1CONbits
7765 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
7766 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
7767 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
7768 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
7769 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
7770 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
7771 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
7772 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
7773 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
7774 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
7775 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
7776 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
7777 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
7778 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
7779 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
7780 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
7782 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
7783 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
7784 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
7785 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
7786 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
7787 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
7788 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
7789 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
7790 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
7791 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
7792 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
7793 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
7794 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
7795 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
7796 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
7797 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
7799 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
7800 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
7801 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
7802 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
7803 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
7804 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
7805 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
7806 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
7807 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
7808 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
7810 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
7811 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
7812 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
7813 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
7814 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
7815 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
7816 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
7817 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
7818 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
7819 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
7821 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
7822 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
7823 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
7824 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
7825 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
7826 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
7827 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
7828 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
7829 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
7830 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
7832 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
7833 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
7834 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
7835 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
7836 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
7837 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
7838 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
7839 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
7840 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
7841 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
7843 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
7844 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
7845 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
7846 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
7847 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
7848 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
7849 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
7850 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
7851 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
7852 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
7854 #define MLC1OUT CLCDATAbits.MLC1OUT // bit 0
7855 #define MLC2OUT CLCDATAbits.MLC2OUT // bit 1
7857 #define CLCIN0PPS0 CLCIN0PPSbits.CLCIN0PPS0 // bit 0
7858 #define CLCIN0PPS1 CLCIN0PPSbits.CLCIN0PPS1 // bit 1
7859 #define CLCIN0PPS2 CLCIN0PPSbits.CLCIN0PPS2 // bit 2
7860 #define CLCIN0PPS3 CLCIN0PPSbits.CLCIN0PPS3 // bit 3
7861 #define CLCIN0PPS4 CLCIN0PPSbits.CLCIN0PPS4 // bit 4
7863 #define CLCIN1PPS0 CLCIN1PPSbits.CLCIN1PPS0 // bit 0
7864 #define CLCIN1PPS1 CLCIN1PPSbits.CLCIN1PPS1 // bit 1
7865 #define CLCIN1PPS2 CLCIN1PPSbits.CLCIN1PPS2 // bit 2
7866 #define CLCIN1PPS3 CLCIN1PPSbits.CLCIN1PPS3 // bit 3
7867 #define CLCIN1PPS4 CLCIN1PPSbits.CLCIN1PPS4 // bit 4
7869 #define CLCIN2PPS0 CLCIN2PPSbits.CLCIN2PPS0 // bit 0
7870 #define CLCIN2PPS1 CLCIN2PPSbits.CLCIN2PPS1 // bit 1
7871 #define CLCIN2PPS2 CLCIN2PPSbits.CLCIN2PPS2 // bit 2
7872 #define CLCIN2PPS3 CLCIN2PPSbits.CLCIN2PPS3 // bit 3
7873 #define CLCIN2PPS4 CLCIN2PPSbits.CLCIN2PPS4 // bit 4
7875 #define CLCIN3PPS0 CLCIN3PPSbits.CLCIN3PPS0 // bit 0
7876 #define CLCIN3PPS1 CLCIN3PPSbits.CLCIN3PPS1 // bit 1
7877 #define CLCIN3PPS2 CLCIN3PPSbits.CLCIN3PPS2 // bit 2
7878 #define CLCIN3PPS3 CLCIN3PPSbits.CLCIN3PPS3 // bit 3
7879 #define CLCIN3PPS4 CLCIN3PPSbits.CLCIN3PPS4 // bit 4
7881 #define CLKRDIV0 CLKRCONbits.CLKRDIV0 // bit 0
7882 #define CLKRDIV1 CLKRCONbits.CLKRDIV1 // bit 1
7883 #define CLKRDIV2 CLKRCONbits.CLKRDIV2 // bit 2
7884 #define CLKRDC0 CLKRCONbits.CLKRDC0 // bit 3
7885 #define CLKRDC1 CLKRCONbits.CLKRDC1 // bit 4
7886 #define CLKREN CLKRCONbits.CLKREN // bit 7
7888 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
7889 #define C1HYS CM1CON0bits.C1HYS // bit 1
7890 #define C1SP CM1CON0bits.C1SP // bit 2
7891 #define C1POL CM1CON0bits.C1POL // bit 4
7892 #define C1OUT CM1CON0bits.C1OUT // bit 6
7893 #define C1ON CM1CON0bits.C1ON // bit 7
7895 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
7896 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
7897 #define C1NCH2 CM1CON1bits.C1NCH2 // bit 2
7898 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 3
7899 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 4
7900 #define C1PCH2 CM1CON1bits.C1PCH2 // bit 5
7901 #define C1INTN CM1CON1bits.C1INTN // bit 6
7902 #define C1INTP CM1CON1bits.C1INTP // bit 7
7904 #define C2SYNC CM2CON0bits.C2SYNC // bit 0
7905 #define C2HYS CM2CON0bits.C2HYS // bit 1
7906 #define C2SP CM2CON0bits.C2SP // bit 2
7907 #define C2POL CM2CON0bits.C2POL // bit 4
7908 #define C2OUT CM2CON0bits.C2OUT // bit 6
7909 #define C2ON CM2CON0bits.C2ON // bit 7
7911 #define C2NCH0 CM2CON1bits.C2NCH0 // bit 0
7912 #define C2NCH1 CM2CON1bits.C2NCH1 // bit 1
7913 #define C2NCH2 CM2CON1bits.C2NCH2 // bit 2
7914 #define C2PCH0 CM2CON1bits.C2PCH0 // bit 3
7915 #define C2PCH1 CM2CON1bits.C2PCH1 // bit 4
7916 #define C2PCH2 CM2CON1bits.C2PCH2 // bit 5
7917 #define C2INTN CM2CON1bits.C2INTN // bit 6
7918 #define C2INTP CM2CON1bits.C2INTP // bit 7
7920 #define MC1OUT CMOUTbits.MC1OUT // bit 0
7921 #define MC2OUT CMOUTbits.MC2OUT // bit 1
7923 #define DOZE0 CPUDOZEbits.DOZE0 // bit 0
7924 #define DOZE1 CPUDOZEbits.DOZE1 // bit 1
7925 #define DOZE2 CPUDOZEbits.DOZE2 // bit 2
7926 #define DOE CPUDOZEbits.DOE // bit 4
7927 #define ROI CPUDOZEbits.ROI // bit 5
7928 #define DOZEN CPUDOZEbits.DOZEN // bit 6
7929 #define IDLEN CPUDOZEbits.IDLEN // bit 7
7931 #define LSAC0 CWG1AS0bits.LSAC0 // bit 2, shadows bit in CWG1AS0bits
7932 #define CWG1LSAC0 CWG1AS0bits.CWG1LSAC0 // bit 2, shadows bit in CWG1AS0bits
7933 #define LSAC1 CWG1AS0bits.LSAC1 // bit 3, shadows bit in CWG1AS0bits
7934 #define CWG1LSAC1 CWG1AS0bits.CWG1LSAC1 // bit 3, shadows bit in CWG1AS0bits
7935 #define LSBD0 CWG1AS0bits.LSBD0 // bit 4, shadows bit in CWG1AS0bits
7936 #define CWG1LSBD0 CWG1AS0bits.CWG1LSBD0 // bit 4, shadows bit in CWG1AS0bits
7937 #define LSBD1 CWG1AS0bits.LSBD1 // bit 5, shadows bit in CWG1AS0bits
7938 #define CWG1LSBD1 CWG1AS0bits.CWG1LSBD1 // bit 5, shadows bit in CWG1AS0bits
7939 #define REN CWG1AS0bits.REN // bit 6, shadows bit in CWG1AS0bits
7940 #define CWG1REN CWG1AS0bits.CWG1REN // bit 6, shadows bit in CWG1AS0bits
7941 #define SHUTDOWN CWG1AS0bits.SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
7942 #define CWG1SHUTDOWN CWG1AS0bits.CWG1SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
7944 #define AS0E CWG1AS1bits.AS0E // bit 0
7945 #define AS1E CWG1AS1bits.AS1E // bit 1
7946 #define AS2E CWG1AS1bits.AS2E // bit 2
7947 #define AS3E CWG1AS1bits.AS3E // bit 3
7949 #define CS CWG1CLKCONbits.CS // bit 0, shadows bit in CWG1CLKCONbits
7950 #define CWG1CS CWG1CLKCONbits.CWG1CS // bit 0, shadows bit in CWG1CLKCONbits
7952 #define POLA CWG1CON1bits.POLA // bit 0, shadows bit in CWG1CON1bits
7953 #define CWG1POLA CWG1CON1bits.CWG1POLA // bit 0, shadows bit in CWG1CON1bits
7954 #define POLB CWG1CON1bits.POLB // bit 1, shadows bit in CWG1CON1bits
7955 #define CWG1POLB CWG1CON1bits.CWG1POLB // bit 1, shadows bit in CWG1CON1bits
7956 #define POLC CWG1CON1bits.POLC // bit 2, shadows bit in CWG1CON1bits
7957 #define CWG1POLC CWG1CON1bits.CWG1POLC // bit 2, shadows bit in CWG1CON1bits
7958 #define POLD CWG1CON1bits.POLD // bit 3, shadows bit in CWG1CON1bits
7959 #define CWG1POLD CWG1CON1bits.CWG1POLD // bit 3, shadows bit in CWG1CON1bits
7960 #define IN CWG1CON1bits.IN // bit 5, shadows bit in CWG1CON1bits
7961 #define CWG1IN CWG1CON1bits.CWG1IN // bit 5, shadows bit in CWG1CON1bits
7963 #define CWG1DAT0 CWG1DATbits.CWG1DAT0 // bit 0
7964 #define CWG1DAT1 CWG1DATbits.CWG1DAT1 // bit 1
7965 #define CWG1DAT2 CWG1DATbits.CWG1DAT2 // bit 2
7966 #define CWG1DAT3 CWG1DATbits.CWG1DAT3 // bit 3
7968 #define DBF0 CWG1DBFbits.DBF0 // bit 0, shadows bit in CWG1DBFbits
7969 #define CWG1DBF0 CWG1DBFbits.CWG1DBF0 // bit 0, shadows bit in CWG1DBFbits
7970 #define DBF1 CWG1DBFbits.DBF1 // bit 1, shadows bit in CWG1DBFbits
7971 #define CWG1DBF1 CWG1DBFbits.CWG1DBF1 // bit 1, shadows bit in CWG1DBFbits
7972 #define DBF2 CWG1DBFbits.DBF2 // bit 2, shadows bit in CWG1DBFbits
7973 #define CWG1DBF2 CWG1DBFbits.CWG1DBF2 // bit 2, shadows bit in CWG1DBFbits
7974 #define DBF3 CWG1DBFbits.DBF3 // bit 3, shadows bit in CWG1DBFbits
7975 #define CWG1DBF3 CWG1DBFbits.CWG1DBF3 // bit 3, shadows bit in CWG1DBFbits
7976 #define DBF4 CWG1DBFbits.DBF4 // bit 4, shadows bit in CWG1DBFbits
7977 #define CWG1DBF4 CWG1DBFbits.CWG1DBF4 // bit 4, shadows bit in CWG1DBFbits
7978 #define DBF5 CWG1DBFbits.DBF5 // bit 5, shadows bit in CWG1DBFbits
7979 #define CWG1DBF5 CWG1DBFbits.CWG1DBF5 // bit 5, shadows bit in CWG1DBFbits
7981 #define DBR0 CWG1DBRbits.DBR0 // bit 0, shadows bit in CWG1DBRbits
7982 #define CWG1DBR0 CWG1DBRbits.CWG1DBR0 // bit 0, shadows bit in CWG1DBRbits
7983 #define DBR1 CWG1DBRbits.DBR1 // bit 1, shadows bit in CWG1DBRbits
7984 #define CWG1DBR1 CWG1DBRbits.CWG1DBR1 // bit 1, shadows bit in CWG1DBRbits
7985 #define DBR2 CWG1DBRbits.DBR2 // bit 2, shadows bit in CWG1DBRbits
7986 #define CWG1DBR2 CWG1DBRbits.CWG1DBR2 // bit 2, shadows bit in CWG1DBRbits
7987 #define DBR3 CWG1DBRbits.DBR3 // bit 3, shadows bit in CWG1DBRbits
7988 #define CWG1DBR3 CWG1DBRbits.CWG1DBR3 // bit 3, shadows bit in CWG1DBRbits
7989 #define DBR4 CWG1DBRbits.DBR4 // bit 4, shadows bit in CWG1DBRbits
7990 #define CWG1DBR4 CWG1DBRbits.CWG1DBR4 // bit 4, shadows bit in CWG1DBRbits
7991 #define DBR5 CWG1DBRbits.DBR5 // bit 5, shadows bit in CWG1DBRbits
7992 #define CWG1DBR5 CWG1DBRbits.CWG1DBR5 // bit 5, shadows bit in CWG1DBRbits
7994 #define CWG1PPS0 CWG1PPSbits.CWG1PPS0 // bit 0
7995 #define CWG1PPS1 CWG1PPSbits.CWG1PPS1 // bit 1
7996 #define CWG1PPS2 CWG1PPSbits.CWG1PPS2 // bit 2
7997 #define CWG1PPS3 CWG1PPSbits.CWG1PPS3 // bit 3
7998 #define CWG1PPS4 CWG1PPSbits.CWG1PPS4 // bit 4
8000 #define STRA CWG1STRbits.STRA // bit 0, shadows bit in CWG1STRbits
8001 #define CWG1STRA CWG1STRbits.CWG1STRA // bit 0, shadows bit in CWG1STRbits
8002 #define STRB CWG1STRbits.STRB // bit 1, shadows bit in CWG1STRbits
8003 #define CWG1STRB CWG1STRbits.CWG1STRB // bit 1, shadows bit in CWG1STRbits
8004 #define STRC CWG1STRbits.STRC // bit 2, shadows bit in CWG1STRbits
8005 #define CWG1STRC CWG1STRbits.CWG1STRC // bit 2, shadows bit in CWG1STRbits
8006 #define STRD CWG1STRbits.STRD // bit 3, shadows bit in CWG1STRbits
8007 #define CWG1STRD CWG1STRbits.CWG1STRD // bit 3, shadows bit in CWG1STRbits
8008 #define OVRA CWG1STRbits.OVRA // bit 4, shadows bit in CWG1STRbits
8009 #define CWG1OVRA CWG1STRbits.CWG1OVRA // bit 4, shadows bit in CWG1STRbits
8010 #define OVRB CWG1STRbits.OVRB // bit 5, shadows bit in CWG1STRbits
8011 #define CWG1OVRB CWG1STRbits.CWG1OVRB // bit 5, shadows bit in CWG1STRbits
8012 #define OVRC CWG1STRbits.OVRC // bit 6, shadows bit in CWG1STRbits
8013 #define CWG1OVRC CWG1STRbits.CWG1OVRC // bit 6, shadows bit in CWG1STRbits
8014 #define OVRD CWG1STRbits.OVRD // bit 7, shadows bit in CWG1STRbits
8015 #define CWG1OVRD CWG1STRbits.CWG1OVRD // bit 7, shadows bit in CWG1STRbits
8017 #define DAC1NSS DACCON0bits.DAC1NSS // bit 0
8018 #define DAC1PSS0 DACCON0bits.DAC1PSS0 // bit 2
8019 #define DAC1PSS1 DACCON0bits.DAC1PSS1 // bit 3
8020 #define DAC1OE DACCON0bits.DAC1OE // bit 5
8021 #define DAC1EN DACCON0bits.DAC1EN // bit 7
8023 #define DAC1R0 DACCON1bits.DAC1R0 // bit 0
8024 #define DAC1R1 DACCON1bits.DAC1R1 // bit 1
8025 #define DAC1R2 DACCON1bits.DAC1R2 // bit 2
8026 #define DAC1R3 DACCON1bits.DAC1R3 // bit 3
8027 #define DAC1R4 DACCON1bits.DAC1R4 // bit 4
8029 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
8030 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
8031 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
8032 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
8033 #define TSRNG FVRCONbits.TSRNG // bit 4
8034 #define TSEN FVRCONbits.TSEN // bit 5
8035 #define FVRRDY FVRCONbits.FVRRDY // bit 6
8036 #define FVREN FVRCONbits.FVREN // bit 7
8038 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
8039 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
8040 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
8041 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
8042 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
8043 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
8045 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
8046 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
8047 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
8048 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
8049 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
8050 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
8052 #define INTEDG INTCONbits.INTEDG // bit 0
8053 #define PEIE INTCONbits.PEIE // bit 6
8054 #define GIE INTCONbits.GIE // bit 7
8056 #define INTPPS0 INTPPSbits.INTPPS0 // bit 0
8057 #define INTPPS1 INTPPSbits.INTPPS1 // bit 1
8058 #define INTPPS2 INTPPSbits.INTPPS2 // bit 2
8059 #define INTPPS3 INTPPSbits.INTPPS3 // bit 3
8060 #define INTPPS4 INTPPSbits.INTPPS4 // bit 4
8062 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
8063 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
8064 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
8065 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
8066 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
8067 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
8069 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
8070 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
8071 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
8072 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
8073 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
8074 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
8076 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
8077 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
8078 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
8079 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
8080 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
8081 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
8083 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
8084 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
8085 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
8086 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
8087 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
8088 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
8090 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
8091 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
8092 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
8093 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
8094 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
8095 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
8097 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
8098 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
8099 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
8100 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
8101 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
8102 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
8104 #define LATA0 LATAbits.LATA0 // bit 0
8105 #define LATA1 LATAbits.LATA1 // bit 1
8106 #define LATA2 LATAbits.LATA2 // bit 2
8107 #define LATA4 LATAbits.LATA4 // bit 4
8108 #define LATA5 LATAbits.LATA5 // bit 5
8110 #define LATC0 LATCbits.LATC0 // bit 0
8111 #define LATC1 LATCbits.LATC1 // bit 1
8112 #define LATC2 LATCbits.LATC2 // bit 2
8113 #define LATC3 LATCbits.LATC3 // bit 3
8114 #define LATC4 LATCbits.LATC4 // bit 4
8115 #define LATC5 LATCbits.LATC5 // bit 5
8117 #define MDCH0 MDCARHbits.MDCH0 // bit 0
8118 #define MDCH1 MDCARHbits.MDCH1 // bit 1
8119 #define MDCH2 MDCARHbits.MDCH2 // bit 2
8120 #define MDCH3 MDCARHbits.MDCH3 // bit 3
8121 #define MDCHSYNC MDCARHbits.MDCHSYNC // bit 5
8122 #define MDCHPOL MDCARHbits.MDCHPOL // bit 6
8124 #define MDCL0 MDCARLbits.MDCL0 // bit 0
8125 #define MDCL1 MDCARLbits.MDCL1 // bit 1
8126 #define MDCL2 MDCARLbits.MDCL2 // bit 2
8127 #define MDCL3 MDCARLbits.MDCL3 // bit 3
8128 #define MDCLSYNC MDCARLbits.MDCLSYNC // bit 5
8129 #define MDCLPOL MDCARLbits.MDCLPOL // bit 6
8131 #define MDCIN1PPS0 MDCIN1PPSbits.MDCIN1PPS0 // bit 0
8132 #define MDCIN1PPS1 MDCIN1PPSbits.MDCIN1PPS1 // bit 1
8133 #define MDCIN1PPS2 MDCIN1PPSbits.MDCIN1PPS2 // bit 2
8134 #define MDCIN1PPS3 MDCIN1PPSbits.MDCIN1PPS3 // bit 3
8135 #define MDCIN1PPS4 MDCIN1PPSbits.MDCIN1PPS4 // bit 4
8137 #define MDCIN2PPS0 MDCIN2PPSbits.MDCIN2PPS0 // bit 0
8138 #define MDCIN2PPS1 MDCIN2PPSbits.MDCIN2PPS1 // bit 1
8139 #define MDCIN2PPS2 MDCIN2PPSbits.MDCIN2PPS2 // bit 2
8140 #define MDCIN2PPS3 MDCIN2PPSbits.MDCIN2PPS3 // bit 3
8141 #define MDCIN2PPS4 MDCIN2PPSbits.MDCIN2PPS4 // bit 4
8143 #define MDBIT MDCONbits.MDBIT // bit 0
8144 #define MDOUT MDCONbits.MDOUT // bit 3
8145 #define MDOPOL MDCONbits.MDOPOL // bit 4
8146 #define MDEN MDCONbits.MDEN // bit 7
8148 #define MDMINPPS0 MDMINPPSbits.MDMINPPS0 // bit 0
8149 #define MDMINPPS1 MDMINPPSbits.MDMINPPS1 // bit 1
8150 #define MDMINPPS2 MDMINPPSbits.MDMINPPS2 // bit 2
8151 #define MDMINPPS3 MDMINPPSbits.MDMINPPS3 // bit 3
8152 #define MDMINPPS4 MDMINPPSbits.MDMINPPS4 // bit 4
8154 #define MDMS0 MDSRCbits.MDMS0 // bit 0
8155 #define MDMS1 MDSRCbits.MDMS1 // bit 1
8156 #define MDMS2 MDSRCbits.MDMS2 // bit 2
8157 #define MDMS3 MDSRCbits.MDMS3 // bit 3
8159 #define N1PFM NCO1CONbits.N1PFM // bit 0
8160 #define N1POL NCO1CONbits.N1POL // bit 4
8161 #define N1OUT NCO1CONbits.N1OUT // bit 5
8162 #define N1EN NCO1CONbits.N1EN // bit 7
8164 #define NVMADR8 NVMADRHbits.NVMADR8 // bit 0
8165 #define NVMADR9 NVMADRHbits.NVMADR9 // bit 1
8166 #define NVMADR10 NVMADRHbits.NVMADR10 // bit 2
8167 #define NVMADR11 NVMADRHbits.NVMADR11 // bit 3
8168 #define NVMADR12 NVMADRHbits.NVMADR12 // bit 4
8169 #define NVMADR13 NVMADRHbits.NVMADR13 // bit 5
8170 #define NVMADR14 NVMADRHbits.NVMADR14 // bit 6
8172 #define NVMADR0 NVMADRLbits.NVMADR0 // bit 0
8173 #define NVMADR1 NVMADRLbits.NVMADR1 // bit 1
8174 #define NVMADR2 NVMADRLbits.NVMADR2 // bit 2
8175 #define NVMADR3 NVMADRLbits.NVMADR3 // bit 3
8176 #define NVMADR4 NVMADRLbits.NVMADR4 // bit 4
8177 #define NVMADR5 NVMADRLbits.NVMADR5 // bit 5
8178 #define NVMADR6 NVMADRLbits.NVMADR6 // bit 6
8179 #define NVMADR7 NVMADRLbits.NVMADR7 // bit 7
8181 #define RD NVMCON1bits.RD // bit 0
8182 #define WR NVMCON1bits.WR // bit 1
8183 #define WREN NVMCON1bits.WREN // bit 2
8184 #define WRERR NVMCON1bits.WRERR // bit 3
8185 #define FREE NVMCON1bits.FREE // bit 4
8186 #define LWLO NVMCON1bits.LWLO // bit 5
8187 #define NVMREGS NVMCON1bits.NVMREGS // bit 6
8189 #define NVMDAT8 NVMDATHbits.NVMDAT8 // bit 0
8190 #define NVMDAT9 NVMDATHbits.NVMDAT9 // bit 1
8191 #define NVMDAT10 NVMDATHbits.NVMDAT10 // bit 2
8192 #define NVMDAT11 NVMDATHbits.NVMDAT11 // bit 3
8193 #define NVMDAT12 NVMDATHbits.NVMDAT12 // bit 4
8194 #define NVMDAT13 NVMDATHbits.NVMDAT13 // bit 5
8196 #define NVMDAT0 NVMDATLbits.NVMDAT0 // bit 0
8197 #define NVMDAT1 NVMDATLbits.NVMDAT1 // bit 1
8198 #define NVMDAT2 NVMDATLbits.NVMDAT2 // bit 2
8199 #define NVMDAT3 NVMDATLbits.NVMDAT3 // bit 3
8200 #define NVMDAT4 NVMDATLbits.NVMDAT4 // bit 4
8201 #define NVMDAT5 NVMDATLbits.NVMDAT5 // bit 5
8202 #define NVMDAT6 NVMDATLbits.NVMDAT6 // bit 6
8203 #define NVMDAT7 NVMDATLbits.NVMDAT7 // bit 7
8205 #define ODCA0 ODCONAbits.ODCA0 // bit 0
8206 #define ODCA1 ODCONAbits.ODCA1 // bit 1
8207 #define ODCA2 ODCONAbits.ODCA2 // bit 2
8208 #define ODCA4 ODCONAbits.ODCA4 // bit 4
8209 #define ODCA5 ODCONAbits.ODCA5 // bit 5
8211 #define ODCC0 ODCONCbits.ODCC0 // bit 0
8212 #define ODCC1 ODCONCbits.ODCC1 // bit 1
8213 #define ODCC2 ODCONCbits.ODCC2 // bit 2
8214 #define ODCC3 ODCONCbits.ODCC3 // bit 3
8215 #define ODCC4 ODCONCbits.ODCC4 // bit 4
8216 #define ODCC5 ODCONCbits.ODCC5 // bit 5
8218 #define NDIV0 OSCCON1bits.NDIV0 // bit 0
8219 #define NDIV1 OSCCON1bits.NDIV1 // bit 1
8220 #define NDIV2 OSCCON1bits.NDIV2 // bit 2
8221 #define NDIV3 OSCCON1bits.NDIV3 // bit 3
8222 #define NOSC0 OSCCON1bits.NOSC0 // bit 4
8223 #define NOSC1 OSCCON1bits.NOSC1 // bit 5
8224 #define NOSC2 OSCCON1bits.NOSC2 // bit 6
8226 #define CDIV0 OSCCON2bits.CDIV0 // bit 0
8227 #define CDIV1 OSCCON2bits.CDIV1 // bit 1
8228 #define CDIV2 OSCCON2bits.CDIV2 // bit 2
8229 #define CDIV3 OSCCON2bits.CDIV3 // bit 3
8230 #define COSC0 OSCCON2bits.COSC0 // bit 4
8231 #define COSC1 OSCCON2bits.COSC1 // bit 5
8232 #define COSC2 OSCCON2bits.COSC2 // bit 6
8234 #define NOSCR OSCCON3bits.NOSCR // bit 3
8235 #define ORDY OSCCON3bits.ORDY // bit 4
8236 #define SOSCBE OSCCON3bits.SOSCBE // bit 5
8237 #define SOSCPWR OSCCON3bits.SOSCPWR // bit 6
8238 #define CSWHOLD OSCCON3bits.CSWHOLD // bit 7
8240 #define ADOEN OSCENbits.ADOEN // bit 2
8241 #define SOSCEN OSCENbits.SOSCEN // bit 3
8242 #define LFOEN OSCENbits.LFOEN // bit 4
8243 #define HFOEN OSCENbits.HFOEN // bit 6
8244 #define EXTOEN OSCENbits.EXTOEN // bit 7
8246 #define HFFRQ0 OSCFRQbits.HFFRQ0 // bit 0
8247 #define HFFRQ1 OSCFRQbits.HFFRQ1 // bit 1
8248 #define HFFRQ2 OSCFRQbits.HFFRQ2 // bit 2
8249 #define HFFRQ3 OSCFRQbits.HFFRQ3 // bit 3
8251 #define PLLR OSCSTAT1bits.PLLR // bit 0
8252 #define ADOR OSCSTAT1bits.ADOR // bit 2
8253 #define SOR OSCSTAT1bits.SOR // bit 3
8254 #define LFOR OSCSTAT1bits.LFOR // bit 4
8255 #define HFOR OSCSTAT1bits.HFOR // bit 6
8256 #define EXTOR OSCSTAT1bits.EXTOR // bit 7
8258 #define HFTUN0 OSCTUNEbits.HFTUN0 // bit 0
8259 #define HFTUN1 OSCTUNEbits.HFTUN1 // bit 1
8260 #define HFTUN2 OSCTUNEbits.HFTUN2 // bit 2
8261 #define HFTUN3 OSCTUNEbits.HFTUN3 // bit 3
8262 #define HFTUN4 OSCTUNEbits.HFTUN4 // bit 4
8263 #define HFTUN5 OSCTUNEbits.HFTUN5 // bit 5
8265 #define NOT_BOR PCON0bits.NOT_BOR // bit 0
8266 #define NOT_POR PCON0bits.NOT_POR // bit 1
8267 #define NOT_RI PCON0bits.NOT_RI // bit 2
8268 #define NOT_RMCLR PCON0bits.NOT_RMCLR // bit 3
8269 #define NOT_RWDT PCON0bits.NOT_RWDT // bit 4
8270 #define STKUNF PCON0bits.STKUNF // bit 6
8271 #define STKOVF PCON0bits.STKOVF // bit 7
8273 #define INTE PIE0bits.INTE // bit 0
8274 #define IOCIE PIE0bits.IOCIE // bit 4
8275 #define TMR0IE PIE0bits.TMR0IE // bit 5
8277 #define TMR1IE PIE1bits.TMR1IE // bit 0
8278 #define TMR2IE PIE1bits.TMR2IE // bit 1
8279 #define BCL1IE PIE1bits.BCL1IE // bit 2
8280 #define SSP1IE PIE1bits.SSP1IE // bit 3
8281 #define TXIE PIE1bits.TXIE // bit 4
8282 #define RCIE PIE1bits.RCIE // bit 5
8283 #define ADIE PIE1bits.ADIE // bit 6
8284 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
8286 #define NCO1IE PIE2bits.NCO1IE // bit 0
8287 #define NVMIE PIE2bits.NVMIE // bit 4
8288 #define C1IE PIE2bits.C1IE // bit 5
8289 #define C2IE PIE2bits.C2IE // bit 6
8291 #define CLC1IE PIE3bits.CLC1IE // bit 0
8292 #define CLC2IE PIE3bits.CLC2IE // bit 1
8293 #define CSWIE PIE3bits.CSWIE // bit 6
8294 #define OSFIE PIE3bits.OSFIE // bit 7
8296 #define CCP1IE PIE4bits.CCP1IE // bit 0
8297 #define CCP2IE PIE4bits.CCP2IE // bit 1
8298 #define CWG1IE PIE4bits.CWG1IE // bit 6
8300 #define INTF PIR0bits.INTF // bit 0
8301 #define IOCIF PIR0bits.IOCIF // bit 4
8302 #define TMR0IF PIR0bits.TMR0IF // bit 5
8304 #define TMR1IF PIR1bits.TMR1IF // bit 0
8305 #define TMR2IF PIR1bits.TMR2IF // bit 1
8306 #define BCL1IF PIR1bits.BCL1IF // bit 2
8307 #define SSP1IF PIR1bits.SSP1IF // bit 3
8308 #define TXIF PIR1bits.TXIF // bit 4
8309 #define RCIF PIR1bits.RCIF // bit 5
8310 #define ADIF PIR1bits.ADIF // bit 6
8311 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
8313 #define NCO1IF PIR2bits.NCO1IF // bit 0
8314 #define NVMIF PIR2bits.NVMIF // bit 4
8315 #define C1IF PIR2bits.C1IF // bit 5
8316 #define C2IF PIR2bits.C2IF // bit 6
8318 #define CLC1IF PIR3bits.CLC1IF // bit 0
8319 #define CLC2IF PIR3bits.CLC2IF // bit 1
8320 #define CSWIF PIR3bits.CSWIF // bit 6
8321 #define OSFIF PIR3bits.OSFIF // bit 7
8323 #define CCP1IF PIR4bits.CCP1IF // bit 0
8324 #define CCP2IF PIR4bits.CCP2IF // bit 1
8325 #define CWG1IF PIR4bits.CWG1IF // bit 6
8327 #define IOCMD PMD0bits.IOCMD // bit 0
8328 #define CLKRMD PMD0bits.CLKRMD // bit 1
8329 #define NVMMD PMD0bits.NVMMD // bit 2
8330 #define FVRMD PMD0bits.FVRMD // bit 6
8331 #define SYSCMD PMD0bits.SYSCMD // bit 7
8333 #define TMR0MD PMD1bits.TMR0MD // bit 0
8334 #define TMR1MD PMD1bits.TMR1MD // bit 1
8335 #define TMR2MD PMD1bits.TMR2MD // bit 2
8336 #define NCOMD PMD1bits.NCOMD // bit 7
8338 #define CMP1MD PMD2bits.CMP1MD // bit 1
8339 #define CMP2MD PMD2bits.CMP2MD // bit 2
8340 #define ADCMD PMD2bits.ADCMD // bit 5
8341 #define DACMD PMD2bits.DACMD // bit 6
8343 #define CCP1MD PMD3bits.CCP1MD // bit 0
8344 #define CCP2MD PMD3bits.CCP2MD // bit 1
8345 #define PWM5MD PMD3bits.PWM5MD // bit 4
8346 #define PWM6MD PMD3bits.PWM6MD // bit 5
8347 #define CWG1MD PMD3bits.CWG1MD // bit 6
8349 #define MSSP1MD PMD4bits.MSSP1MD // bit 1
8350 #define UART1MD PMD4bits.UART1MD // bit 5
8352 #define DSMMD PMD5bits.DSMMD // bit 0
8353 #define CLC1MD PMD5bits.CLC1MD // bit 1
8354 #define CLC2MD PMD5bits.CLC2MD // bit 2
8356 #define RA0 PORTAbits.RA0 // bit 0
8357 #define RA1 PORTAbits.RA1 // bit 1
8358 #define RA2 PORTAbits.RA2 // bit 2
8359 #define RA3 PORTAbits.RA3 // bit 3
8360 #define RA4 PORTAbits.RA4 // bit 4
8361 #define RA5 PORTAbits.RA5 // bit 5
8363 #define RC0 PORTCbits.RC0 // bit 0
8364 #define RC1 PORTCbits.RC1 // bit 1
8365 #define RC2 PORTCbits.RC2 // bit 2
8366 #define RC3 PORTCbits.RC3 // bit 3
8367 #define RC4 PORTCbits.RC4 // bit 4
8368 #define RC5 PORTCbits.RC5 // bit 5
8370 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
8372 #define PWM5POL PWM5CONbits.PWM5POL // bit 4
8373 #define PWM5OUT PWM5CONbits.PWM5OUT // bit 5
8374 #define PWM5EN PWM5CONbits.PWM5EN // bit 7
8376 #define PWM5DCH0 PWM5DCHbits.PWM5DCH0 // bit 0
8377 #define PWM5DCH1 PWM5DCHbits.PWM5DCH1 // bit 1
8378 #define PWM5DCH2 PWM5DCHbits.PWM5DCH2 // bit 2
8379 #define PWM5DCH3 PWM5DCHbits.PWM5DCH3 // bit 3
8380 #define PWM5DCH4 PWM5DCHbits.PWM5DCH4 // bit 4
8381 #define PWM5DCH5 PWM5DCHbits.PWM5DCH5 // bit 5
8382 #define PWM5DCH6 PWM5DCHbits.PWM5DCH6 // bit 6
8383 #define PWM5DCH7 PWM5DCHbits.PWM5DCH7 // bit 7
8385 #define PWM5DCL0 PWM5DCLbits.PWM5DCL0 // bit 6
8386 #define PWM5DCL1 PWM5DCLbits.PWM5DCL1 // bit 7
8388 #define PWM6POL PWM6CONbits.PWM6POL // bit 4
8389 #define PWM6OUT PWM6CONbits.PWM6OUT // bit 5
8390 #define PWM6EN PWM6CONbits.PWM6EN // bit 7
8392 #define PWM6DCH0 PWM6DCHbits.PWM6DCH0 // bit 0
8393 #define PWM6DCH1 PWM6DCHbits.PWM6DCH1 // bit 1
8394 #define PWM6DCH2 PWM6DCHbits.PWM6DCH2 // bit 2
8395 #define PWM6DCH3 PWM6DCHbits.PWM6DCH3 // bit 3
8396 #define PWM6DCH4 PWM6DCHbits.PWM6DCH4 // bit 4
8397 #define PWM6DCH5 PWM6DCHbits.PWM6DCH5 // bit 5
8398 #define PWM6DCH6 PWM6DCHbits.PWM6DCH6 // bit 6
8399 #define PWM6DCH7 PWM6DCHbits.PWM6DCH7 // bit 7
8401 #define PWM6DCL0 PWM6DCLbits.PWM6DCL0 // bit 6
8402 #define PWM6DCL1 PWM6DCLbits.PWM6DCL1 // bit 7
8404 #define RA0PPS0 RA0PPSbits.RA0PPS0 // bit 0
8405 #define RA0PPS1 RA0PPSbits.RA0PPS1 // bit 1
8406 #define RA0PPS2 RA0PPSbits.RA0PPS2 // bit 2
8407 #define RA0PPS3 RA0PPSbits.RA0PPS3 // bit 3
8408 #define RA0PPS4 RA0PPSbits.RA0PPS4 // bit 4
8410 #define RA1PPS0 RA1PPSbits.RA1PPS0 // bit 0
8411 #define RA1PPS1 RA1PPSbits.RA1PPS1 // bit 1
8412 #define RA1PPS2 RA1PPSbits.RA1PPS2 // bit 2
8413 #define RA1PPS3 RA1PPSbits.RA1PPS3 // bit 3
8414 #define RA1PPS4 RA1PPSbits.RA1PPS4 // bit 4
8416 #define RA2PPS0 RA2PPSbits.RA2PPS0 // bit 0
8417 #define RA2PPS1 RA2PPSbits.RA2PPS1 // bit 1
8418 #define RA2PPS2 RA2PPSbits.RA2PPS2 // bit 2
8419 #define RA2PPS3 RA2PPSbits.RA2PPS3 // bit 3
8420 #define RA2PPS4 RA2PPSbits.RA2PPS4 // bit 4
8422 #define RA4PPS0 RA4PPSbits.RA4PPS0 // bit 0
8423 #define RA4PPS1 RA4PPSbits.RA4PPS1 // bit 1
8424 #define RA4PPS2 RA4PPSbits.RA4PPS2 // bit 2
8425 #define RA4PPS3 RA4PPSbits.RA4PPS3 // bit 3
8426 #define RA4PPS4 RA4PPSbits.RA4PPS4 // bit 4
8428 #define RA5PPS0 RA5PPSbits.RA5PPS0 // bit 0
8429 #define RA5PPS1 RA5PPSbits.RA5PPS1 // bit 1
8430 #define RA5PPS2 RA5PPSbits.RA5PPS2 // bit 2
8431 #define RA5PPS3 RA5PPSbits.RA5PPS3 // bit 3
8432 #define RA5PPS4 RA5PPSbits.RA5PPS4 // bit 4
8434 #define RC0PPS0 RC0PPSbits.RC0PPS0 // bit 0
8435 #define RC0PPS1 RC0PPSbits.RC0PPS1 // bit 1
8436 #define RC0PPS2 RC0PPSbits.RC0PPS2 // bit 2
8437 #define RC0PPS3 RC0PPSbits.RC0PPS3 // bit 3
8438 #define RC0PPS4 RC0PPSbits.RC0PPS4 // bit 4
8440 #define RC1PPS0 RC1PPSbits.RC1PPS0 // bit 0
8441 #define RC1PPS1 RC1PPSbits.RC1PPS1 // bit 1
8442 #define RC1PPS2 RC1PPSbits.RC1PPS2 // bit 2
8443 #define RC1PPS3 RC1PPSbits.RC1PPS3 // bit 3
8444 #define RC1PPS4 RC1PPSbits.RC1PPS4 // bit 4
8446 #define RX9D RC1STAbits.RX9D // bit 0
8447 #define OERR RC1STAbits.OERR // bit 1
8448 #define FERR RC1STAbits.FERR // bit 2
8449 #define ADDEN RC1STAbits.ADDEN // bit 3
8450 #define CREN RC1STAbits.CREN // bit 4
8451 #define SREN RC1STAbits.SREN // bit 5
8452 #define RX9 RC1STAbits.RX9 // bit 6
8453 #define SPEN RC1STAbits.SPEN // bit 7
8455 #define RC2PPS0 RC2PPSbits.RC2PPS0 // bit 0
8456 #define RC2PPS1 RC2PPSbits.RC2PPS1 // bit 1
8457 #define RC2PPS2 RC2PPSbits.RC2PPS2 // bit 2
8458 #define RC2PPS3 RC2PPSbits.RC2PPS3 // bit 3
8459 #define RC2PPS4 RC2PPSbits.RC2PPS4 // bit 4
8461 #define RC3PPS0 RC3PPSbits.RC3PPS0 // bit 0
8462 #define RC3PPS1 RC3PPSbits.RC3PPS1 // bit 1
8463 #define RC3PPS2 RC3PPSbits.RC3PPS2 // bit 2
8464 #define RC3PPS3 RC3PPSbits.RC3PPS3 // bit 3
8465 #define RC3PPS4 RC3PPSbits.RC3PPS4 // bit 4
8467 #define RC4PPS0 RC4PPSbits.RC4PPS0 // bit 0
8468 #define RC4PPS1 RC4PPSbits.RC4PPS1 // bit 1
8469 #define RC4PPS2 RC4PPSbits.RC4PPS2 // bit 2
8470 #define RC4PPS3 RC4PPSbits.RC4PPS3 // bit 3
8471 #define RC4PPS4 RC4PPSbits.RC4PPS4 // bit 4
8473 #define RC5PPS0 RC5PPSbits.RC5PPS0 // bit 0
8474 #define RC5PPS1 RC5PPSbits.RC5PPS1 // bit 1
8475 #define RC5PPS2 RC5PPSbits.RC5PPS2 // bit 2
8476 #define RC5PPS3 RC5PPSbits.RC5PPS3 // bit 3
8477 #define RC5PPS4 RC5PPSbits.RC5PPS4 // bit 4
8479 #define RXPPS0 RXPPSbits.RXPPS0 // bit 0
8480 #define RXPPS1 RXPPSbits.RXPPS1 // bit 1
8481 #define RXPPS2 RXPPSbits.RXPPS2 // bit 2
8482 #define RXPPS3 RXPPSbits.RXPPS3 // bit 3
8483 #define RXPPS4 RXPPSbits.RXPPS4 // bit 4
8485 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
8486 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
8487 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
8488 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
8489 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
8491 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
8492 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
8493 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
8494 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
8495 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
8496 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
8498 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
8499 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
8500 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
8501 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
8502 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
8503 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
8504 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
8505 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
8506 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
8507 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
8508 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
8509 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
8510 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
8511 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
8512 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
8513 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
8515 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
8516 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
8517 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
8518 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
8519 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
8520 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
8521 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
8522 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
8523 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
8524 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
8525 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
8526 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
8527 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
8528 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
8529 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
8530 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
8532 #define SSP1CLKPPS0 SSP1CLKPPSbits.SSP1CLKPPS0 // bit 0
8533 #define SSP1CLKPPS1 SSP1CLKPPSbits.SSP1CLKPPS1 // bit 1
8534 #define SSP1CLKPPS2 SSP1CLKPPSbits.SSP1CLKPPS2 // bit 2
8535 #define SSP1CLKPPS3 SSP1CLKPPSbits.SSP1CLKPPS3 // bit 3
8536 #define SSP1CLKPPS4 SSP1CLKPPSbits.SSP1CLKPPS4 // bit 4
8538 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
8539 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
8540 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
8541 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
8542 #define CKP SSP1CONbits.CKP // bit 4
8543 #define SSPEN SSP1CONbits.SSPEN // bit 5
8544 #define SSPOV SSP1CONbits.SSPOV // bit 6
8545 #define WCOL SSP1CONbits.WCOL // bit 7
8547 #define SEN SSP1CON2bits.SEN // bit 0
8548 #define RSEN SSP1CON2bits.RSEN // bit 1
8549 #define PEN SSP1CON2bits.PEN // bit 2
8550 #define RCEN SSP1CON2bits.RCEN // bit 3
8551 #define ACKEN SSP1CON2bits.ACKEN // bit 4
8552 #define ACKDT SSP1CON2bits.ACKDT // bit 5
8553 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
8554 #define GCEN SSP1CON2bits.GCEN // bit 7
8556 #define DHEN SSP1CON3bits.DHEN // bit 0
8557 #define AHEN SSP1CON3bits.AHEN // bit 1
8558 #define SBCDE SSP1CON3bits.SBCDE // bit 2
8559 #define SDAHT SSP1CON3bits.SDAHT // bit 3
8560 #define BOEN SSP1CON3bits.BOEN // bit 4
8561 #define SCIE SSP1CON3bits.SCIE // bit 5
8562 #define PCIE SSP1CON3bits.PCIE // bit 6
8563 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
8565 #define SSP1DATPPS0 SSP1DATPPSbits.SSP1DATPPS0 // bit 0
8566 #define SSP1DATPPS1 SSP1DATPPSbits.SSP1DATPPS1 // bit 1
8567 #define SSP1DATPPS2 SSP1DATPPSbits.SSP1DATPPS2 // bit 2
8568 #define SSP1DATPPS3 SSP1DATPPSbits.SSP1DATPPS3 // bit 3
8569 #define SSP1DATPPS4 SSP1DATPPSbits.SSP1DATPPS4 // bit 4
8571 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
8572 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
8573 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
8574 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
8575 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
8576 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
8577 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
8578 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
8579 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
8580 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
8581 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
8582 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
8583 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
8584 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
8585 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
8586 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
8588 #define SSP1SSPPS0 SSP1SSPPSbits.SSP1SSPPS0 // bit 0
8589 #define SSP1SSPPS1 SSP1SSPPSbits.SSP1SSPPS1 // bit 1
8590 #define SSP1SSPPS2 SSP1SSPPSbits.SSP1SSPPS2 // bit 2
8591 #define SSP1SSPPS3 SSP1SSPPSbits.SSP1SSPPS3 // bit 3
8592 #define SSP1SSPPS4 SSP1SSPPSbits.SSP1SSPPS4 // bit 4
8594 #define BF SSP1STATbits.BF // bit 0
8595 #define UA SSP1STATbits.UA // bit 1
8596 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
8597 #define S SSP1STATbits.S // bit 3
8598 #define P SSP1STATbits.P // bit 4
8599 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
8600 #define CKE SSP1STATbits.CKE // bit 6
8601 #define SMP SSP1STATbits.SMP // bit 7
8603 #define C STATUSbits.C // bit 0
8604 #define DC STATUSbits.DC // bit 1
8605 #define Z STATUSbits.Z // bit 2
8606 #define NOT_PD STATUSbits.NOT_PD // bit 3
8607 #define NOT_TO STATUSbits.NOT_TO // bit 4
8609 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
8610 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
8611 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
8613 #define T0CKIPPS0 T0CKIPPSbits.T0CKIPPS0 // bit 0
8614 #define T0CKIPPS1 T0CKIPPSbits.T0CKIPPS1 // bit 1
8615 #define T0CKIPPS2 T0CKIPPSbits.T0CKIPPS2 // bit 2
8616 #define T0CKIPPS3 T0CKIPPSbits.T0CKIPPS3 // bit 3
8617 #define T0CKIPPS4 T0CKIPPSbits.T0CKIPPS4 // bit 4
8619 #define T0OUTPS0 T0CON0bits.T0OUTPS0 // bit 0
8620 #define T0OUTPS1 T0CON0bits.T0OUTPS1 // bit 1
8621 #define T0OUTPS2 T0CON0bits.T0OUTPS2 // bit 2
8622 #define T0OUTPS3 T0CON0bits.T0OUTPS3 // bit 3
8623 #define T016BIT T0CON0bits.T016BIT // bit 4
8624 #define T0OUT T0CON0bits.T0OUT // bit 5
8625 #define T0EN T0CON0bits.T0EN // bit 7
8627 #define T0CKPS0 T0CON1bits.T0CKPS0 // bit 0
8628 #define T0CKPS1 T0CON1bits.T0CKPS1 // bit 1
8629 #define T0CKPS2 T0CON1bits.T0CKPS2 // bit 2
8630 #define T0CKPS3 T0CON1bits.T0CKPS3 // bit 3
8631 #define T0ASYNC T0CON1bits.T0ASYNC // bit 4
8632 #define T0CS0 T0CON1bits.T0CS0 // bit 5
8633 #define T0CS1 T0CON1bits.T0CS1 // bit 6
8634 #define T0CS2 T0CON1bits.T0CS2 // bit 7
8636 #define T1CKIPPS0 T1CKIPPSbits.T1CKIPPS0 // bit 0
8637 #define T1CKIPPS1 T1CKIPPSbits.T1CKIPPS1 // bit 1
8638 #define T1CKIPPS2 T1CKIPPSbits.T1CKIPPS2 // bit 2
8639 #define T1CKIPPS3 T1CKIPPSbits.T1CKIPPS3 // bit 3
8640 #define T1CKIPPS4 T1CKIPPSbits.T1CKIPPS4 // bit 4
8642 #define TMR1ON T1CONbits.TMR1ON // bit 0
8643 #define T1SYNC T1CONbits.T1SYNC // bit 2
8644 #define T1SOSC T1CONbits.T1SOSC // bit 3
8645 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
8646 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
8647 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
8648 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
8650 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
8651 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
8652 #define T1GVAL T1GCONbits.T1GVAL // bit 2
8653 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3
8654 #define T1GSPM T1GCONbits.T1GSPM // bit 4
8655 #define T1GTM T1GCONbits.T1GTM // bit 5
8656 #define T1GPOL T1GCONbits.T1GPOL // bit 6
8657 #define TMR1GE T1GCONbits.TMR1GE // bit 7
8659 #define T1GPPS0 T1GPPSbits.T1GPPS0 // bit 0
8660 #define T1GPPS1 T1GPPSbits.T1GPPS1 // bit 1
8661 #define T1GPPS2 T1GPPSbits.T1GPPS2 // bit 2
8662 #define T1GPPS3 T1GPPSbits.T1GPPS3 // bit 3
8663 #define T1GPPS4 T1GPPSbits.T1GPPS4 // bit 4
8665 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
8666 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
8667 #define TMR2ON T2CONbits.TMR2ON // bit 2
8668 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
8669 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
8670 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
8671 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
8673 #define TMR08 TMR0Hbits.TMR08 // bit 0
8674 #define TMR09 TMR0Hbits.TMR09 // bit 1
8675 #define TMR010 TMR0Hbits.TMR010 // bit 2
8676 #define TMR011 TMR0Hbits.TMR011 // bit 3
8677 #define TMR012 TMR0Hbits.TMR012 // bit 4
8678 #define TMR013 TMR0Hbits.TMR013 // bit 5
8679 #define TMR014 TMR0Hbits.TMR014 // bit 6
8680 #define TMR015 TMR0Hbits.TMR015 // bit 7
8682 #define TMR00 TMR0Lbits.TMR00 // bit 0
8683 #define TMR01 TMR0Lbits.TMR01 // bit 1
8684 #define TMR02 TMR0Lbits.TMR02 // bit 2
8685 #define TMR03 TMR0Lbits.TMR03 // bit 3
8686 #define TMR04 TMR0Lbits.TMR04 // bit 4
8687 #define TMR05 TMR0Lbits.TMR05 // bit 5
8688 #define TMR06 TMR0Lbits.TMR06 // bit 6
8689 #define TMR07 TMR0Lbits.TMR07 // bit 7
8691 #define TRISA0 TRISAbits.TRISA0 // bit 0
8692 #define TRISA1 TRISAbits.TRISA1 // bit 1
8693 #define TRISA2 TRISAbits.TRISA2 // bit 2
8694 #define TRISA4 TRISAbits.TRISA4 // bit 4
8695 #define TRISA5 TRISAbits.TRISA5 // bit 5
8697 #define TRISC0 TRISCbits.TRISC0 // bit 0
8698 #define TRISC1 TRISCbits.TRISC1 // bit 1
8699 #define TRISC2 TRISCbits.TRISC2 // bit 2
8700 #define TRISC3 TRISCbits.TRISC3 // bit 3
8701 #define TRISC4 TRISCbits.TRISC4 // bit 4
8702 #define TRISC5 TRISCbits.TRISC5 // bit 5
8704 #define TX9D TX1STAbits.TX9D // bit 0
8705 #define TRMT TX1STAbits.TRMT // bit 1
8706 #define BRGH TX1STAbits.BRGH // bit 2
8707 #define SENDB TX1STAbits.SENDB // bit 3
8708 #define SYNC TX1STAbits.SYNC // bit 4
8709 #define TXEN TX1STAbits.TXEN // bit 5
8710 #define TX9 TX1STAbits.TX9 // bit 6
8711 #define CSRC TX1STAbits.CSRC // bit 7
8713 #define TXPPS0 TXPPSbits.TXPPS0 // bit 0
8714 #define TXPPS1 TXPPSbits.TXPPS1 // bit 1
8715 #define TXPPS2 TXPPSbits.TXPPS2 // bit 2
8716 #define TXPPS3 TXPPSbits.TXPPS3 // bit 3
8717 #define TXPPS4 TXPPSbits.TXPPS4 // bit 4
8719 #define VREGPM VREGCONbits.VREGPM // bit 1
8721 #define SWDTEN WDTCONbits.SWDTEN // bit 0
8722 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
8723 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
8724 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
8725 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
8726 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
8728 #define WPUA0 WPUAbits.WPUA0 // bit 0
8729 #define WPUA1 WPUAbits.WPUA1 // bit 1
8730 #define WPUA2 WPUAbits.WPUA2 // bit 2
8731 #define WPUA3 WPUAbits.WPUA3 // bit 3
8732 #define WPUA4 WPUAbits.WPUA4 // bit 4
8733 #define WPUA5 WPUAbits.WPUA5 // bit 5
8735 #define WPUC0 WPUCbits.WPUC0 // bit 0
8736 #define WPUC1 WPUCbits.WPUC1 // bit 1
8737 #define WPUC2 WPUCbits.WPUC2 // bit 2
8738 #define WPUC3 WPUCbits.WPUC3 // bit 3
8739 #define WPUC4 WPUCbits.WPUC4 // bit 4
8740 #define WPUC5 WPUCbits.WPUC5 // bit 5
8742 #endif // #ifndef NO_BIT_DEFINES
8744 #endif // #ifndef __PIC16F18323_H__