2 * This declarations of the PIC16F18324 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:23 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F18324_H__
26 #define __PIC16F18324_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTC_ADDR 0x000E
52 #define PIR0_ADDR 0x0010
53 #define PIR1_ADDR 0x0011
54 #define PIR2_ADDR 0x0012
55 #define PIR3_ADDR 0x0013
56 #define PIR4_ADDR 0x0014
57 #define TMR0L_ADDR 0x0015
58 #define TMR0H_ADDR 0x0016
59 #define T0CON0_ADDR 0x0017
60 #define T0CON1_ADDR 0x0018
61 #define TMR1_ADDR 0x0019
62 #define TMR1L_ADDR 0x0019
63 #define TMR1H_ADDR 0x001A
64 #define T1CON_ADDR 0x001B
65 #define T1GCON_ADDR 0x001C
66 #define TMR2_ADDR 0x001D
67 #define PR2_ADDR 0x001E
68 #define T2CON_ADDR 0x001F
69 #define TRISA_ADDR 0x008C
70 #define TRISC_ADDR 0x008E
71 #define PIE0_ADDR 0x0090
72 #define PIE1_ADDR 0x0091
73 #define PIE2_ADDR 0x0092
74 #define PIE3_ADDR 0x0093
75 #define PIE4_ADDR 0x0094
76 #define WDTCON_ADDR 0x0097
77 #define ADRES_ADDR 0x009B
78 #define ADRESL_ADDR 0x009B
79 #define ADRESH_ADDR 0x009C
80 #define ADCON0_ADDR 0x009D
81 #define ADCON1_ADDR 0x009E
82 #define ADACT_ADDR 0x009F
83 #define LATA_ADDR 0x010C
84 #define LATC_ADDR 0x010E
85 #define CM1CON0_ADDR 0x0111
86 #define CM1CON1_ADDR 0x0112
87 #define CM2CON0_ADDR 0x0113
88 #define CM2CON1_ADDR 0x0114
89 #define CMOUT_ADDR 0x0115
90 #define BORCON_ADDR 0x0116
91 #define FVRCON_ADDR 0x0117
92 #define DACCON0_ADDR 0x0118
93 #define DACCON1_ADDR 0x0119
94 #define ANSELA_ADDR 0x018C
95 #define ANSELC_ADDR 0x018E
96 #define VREGCON_ADDR 0x0197
97 #define RC1REG_ADDR 0x0199
98 #define RCREG_ADDR 0x0199
99 #define RCREG1_ADDR 0x0199
100 #define TX1REG_ADDR 0x019A
101 #define TXREG_ADDR 0x019A
102 #define TXREG1_ADDR 0x019A
103 #define SP1BRG_ADDR 0x019B
104 #define SP1BRGL_ADDR 0x019B
105 #define SPBRG_ADDR 0x019B
106 #define SPBRG1_ADDR 0x019B
107 #define SPBRGL_ADDR 0x019B
108 #define SP1BRGH_ADDR 0x019C
109 #define SPBRGH_ADDR 0x019C
110 #define SPBRGH1_ADDR 0x019C
111 #define RC1STA_ADDR 0x019D
112 #define RCSTA_ADDR 0x019D
113 #define RCSTA1_ADDR 0x019D
114 #define TX1STA_ADDR 0x019E
115 #define TXSTA_ADDR 0x019E
116 #define TXSTA1_ADDR 0x019E
117 #define BAUD1CON_ADDR 0x019F
118 #define BAUDCON_ADDR 0x019F
119 #define BAUDCON1_ADDR 0x019F
120 #define BAUDCTL_ADDR 0x019F
121 #define BAUDCTL1_ADDR 0x019F
122 #define WPUA_ADDR 0x020C
123 #define WPUC_ADDR 0x020E
124 #define SSP1BUF_ADDR 0x0211
125 #define SSPBUF_ADDR 0x0211
126 #define SSP1ADD_ADDR 0x0212
127 #define SSPADD_ADDR 0x0212
128 #define SSP1MSK_ADDR 0x0213
129 #define SSPMSK_ADDR 0x0213
130 #define SSP1STAT_ADDR 0x0214
131 #define SSPSTAT_ADDR 0x0214
132 #define SSP1CON_ADDR 0x0215
133 #define SSP1CON1_ADDR 0x0215
134 #define SSPCON_ADDR 0x0215
135 #define SSPCON1_ADDR 0x0215
136 #define SSP1CON2_ADDR 0x0216
137 #define SSPCON2_ADDR 0x0216
138 #define SSP1CON3_ADDR 0x0217
139 #define SSPCON3_ADDR 0x0217
140 #define ODCONA_ADDR 0x028C
141 #define ODCONC_ADDR 0x028E
142 #define CCPR1_ADDR 0x0291
143 #define CCPR1L_ADDR 0x0291
144 #define CCPR1H_ADDR 0x0292
145 #define CCP1CON_ADDR 0x0293
146 #define CCP1CAP_ADDR 0x0294
147 #define CCPR2_ADDR 0x0295
148 #define CCPR2L_ADDR 0x0295
149 #define CCPR2H_ADDR 0x0296
150 #define CCP2CON_ADDR 0x0297
151 #define CCP2CAP_ADDR 0x0298
152 #define CCPTMRS_ADDR 0x029F
153 #define SLRCONA_ADDR 0x030C
154 #define SLRCONC_ADDR 0x030E
155 #define CCPR3_ADDR 0x0311
156 #define CCPR3L_ADDR 0x0311
157 #define CCPR3H_ADDR 0x0312
158 #define CCP3CON_ADDR 0x0313
159 #define CCP3CAP_ADDR 0x0314
160 #define CCPR4_ADDR 0x0315
161 #define CCPR4L_ADDR 0x0315
162 #define CCPR4H_ADDR 0x0316
163 #define CCP4CON_ADDR 0x0317
164 #define CCP4CAP_ADDR 0x0318
165 #define INLVLA_ADDR 0x038C
166 #define INLVLC_ADDR 0x038E
167 #define IOCAP_ADDR 0x0391
168 #define IOCAN_ADDR 0x0392
169 #define IOCAF_ADDR 0x0393
170 #define IOCCP_ADDR 0x0397
171 #define IOCCN_ADDR 0x0398
172 #define IOCCF_ADDR 0x0399
173 #define CLKRCON_ADDR 0x039A
174 #define MDCON_ADDR 0x039C
175 #define MDSRC_ADDR 0x039D
176 #define MDCARH_ADDR 0x039E
177 #define MDCARL_ADDR 0x039F
178 #define CCDNA_ADDR 0x040C
179 #define CCDNC_ADDR 0x040E
180 #define TMR3_ADDR 0x0411
181 #define TMR3L_ADDR 0x0411
182 #define TMR3H_ADDR 0x0412
183 #define T3CON_ADDR 0x0413
184 #define T3GCON_ADDR 0x0414
185 #define TMR4_ADDR 0x0415
186 #define PR4_ADDR 0x0416
187 #define T4CON_ADDR 0x0417
188 #define TMR5_ADDR 0x0418
189 #define TMR5L_ADDR 0x0418
190 #define TMR5H_ADDR 0x0419
191 #define T5CON_ADDR 0x041A
192 #define T5GCON_ADDR 0x041B
193 #define TMR6_ADDR 0x041C
194 #define PR6_ADDR 0x041D
195 #define T6CON_ADDR 0x041E
196 #define CCDCON_ADDR 0x041F
197 #define CCDPA_ADDR 0x048C
198 #define CCDPC_ADDR 0x048E
199 #define NCO1ACC_ADDR 0x0498
200 #define NCO1ACCL_ADDR 0x0498
201 #define NCO1ACCH_ADDR 0x0499
202 #define NCO1ACCU_ADDR 0x049A
203 #define NCO1INC_ADDR 0x049B
204 #define NCO1INCL_ADDR 0x049B
205 #define NCO1INCH_ADDR 0x049C
206 #define NCO1INCU_ADDR 0x049D
207 #define NCO1CON_ADDR 0x049E
208 #define NCO1CLK_ADDR 0x049F
209 #define PWM5DCL_ADDR 0x0617
210 #define PWM5DCH_ADDR 0x0618
211 #define PWM5CON_ADDR 0x0619
212 #define PWM5CON0_ADDR 0x0619
213 #define PWM6DCL_ADDR 0x061A
214 #define PWM6DCH_ADDR 0x061B
215 #define PWM6CON_ADDR 0x061C
216 #define PWM6CON0_ADDR 0x061C
217 #define PWMTMRS_ADDR 0x061F
218 #define CWG1CLKCON_ADDR 0x0691
219 #define CWG1DAT_ADDR 0x0692
220 #define CWG1DBR_ADDR 0x0693
221 #define CWG1DBF_ADDR 0x0694
222 #define CWG1CON0_ADDR 0x0695
223 #define CWG1CON1_ADDR 0x0696
224 #define CWG1AS0_ADDR 0x0697
225 #define CWG1AS1_ADDR 0x0698
226 #define CWG1STR_ADDR 0x0699
227 #define CWG2CLKCON_ADDR 0x0711
228 #define CWG2DAT_ADDR 0x0712
229 #define CWG2DBR_ADDR 0x0713
230 #define CWG2DBF_ADDR 0x0714
231 #define CWG2CON0_ADDR 0x0715
232 #define CWG2CON1_ADDR 0x0716
233 #define CWG2AS0_ADDR 0x0717
234 #define CWG2AS1_ADDR 0x0718
235 #define CWG2STR_ADDR 0x0719
236 #define NVMADR_ADDR 0x0891
237 #define NVMADRL_ADDR 0x0891
238 #define NVMADRH_ADDR 0x0892
239 #define NVMDAT_ADDR 0x0893
240 #define NVMDATL_ADDR 0x0893
241 #define NVMDATH_ADDR 0x0894
242 #define NVMCON1_ADDR 0x0895
243 #define NVMCON2_ADDR 0x0896
244 #define PCON0_ADDR 0x089B
245 #define PMD0_ADDR 0x0911
246 #define PMD1_ADDR 0x0912
247 #define PMD2_ADDR 0x0913
248 #define PMD3_ADDR 0x0914
249 #define PMD4_ADDR 0x0915
250 #define PMD5_ADDR 0x0916
251 #define CPUDOZE_ADDR 0x0918
252 #define OSCCON1_ADDR 0x0919
253 #define OSCCON2_ADDR 0x091A
254 #define OSCCON3_ADDR 0x091B
255 #define OSCSTAT1_ADDR 0x091C
256 #define OSCEN_ADDR 0x091D
257 #define OSCTUNE_ADDR 0x091E
258 #define OSCFRQ_ADDR 0x091F
259 #define PPSLOCK_ADDR 0x0E0F
260 #define INTPPS_ADDR 0x0E10
261 #define T0CKIPPS_ADDR 0x0E11
262 #define T1CKIPPS_ADDR 0x0E12
263 #define T1GPPS_ADDR 0x0E13
264 #define CCP1PPS_ADDR 0x0E14
265 #define CCP2PPS_ADDR 0x0E15
266 #define CCP3PPS_ADDR 0x0E16
267 #define CCP4PPS_ADDR 0x0E17
268 #define CWG1PPS_ADDR 0x0E18
269 #define CWG2PPS_ADDR 0x0E19
270 #define MDCIN1PPS_ADDR 0x0E1A
271 #define MDCIN2PPS_ADDR 0x0E1B
272 #define MDMINPPS_ADDR 0x0E1C
273 #define SSP1CLKPPS_ADDR 0x0E20
274 #define SSP1DATPPS_ADDR 0x0E21
275 #define SSP1SSPPS_ADDR 0x0E22
276 #define RXPPS_ADDR 0x0E24
277 #define TXPPS_ADDR 0x0E25
278 #define CLCIN0PPS_ADDR 0x0E28
279 #define CLCIN1PPS_ADDR 0x0E29
280 #define CLCIN2PPS_ADDR 0x0E2A
281 #define CLCIN3PPS_ADDR 0x0E2B
282 #define T3CKIPPS_ADDR 0x0E2C
283 #define T3GPPS_ADDR 0x0E2D
284 #define T5CKIPPS_ADDR 0x0E2E
285 #define T5GPPS_ADDR 0x0E2F
286 #define RA0PPS_ADDR 0x0E90
287 #define RA1PPS_ADDR 0x0E91
288 #define RA2PPS_ADDR 0x0E92
289 #define RA4PPS_ADDR 0x0E94
290 #define RA5PPS_ADDR 0x0E95
291 #define RC0PPS_ADDR 0x0EA0
292 #define RC1PPS_ADDR 0x0EA1
293 #define RC2PPS_ADDR 0x0EA2
294 #define RC3PPS_ADDR 0x0EA3
295 #define RC4PPS_ADDR 0x0EA4
296 #define RC5PPS_ADDR 0x0EA5
297 #define CLCDATA_ADDR 0x0F0F
298 #define CLC1CON_ADDR 0x0F10
299 #define CLC1POL_ADDR 0x0F11
300 #define CLC1SEL0_ADDR 0x0F12
301 #define CLC1SEL1_ADDR 0x0F13
302 #define CLC1SEL2_ADDR 0x0F14
303 #define CLC1SEL3_ADDR 0x0F15
304 #define CLC1GLS0_ADDR 0x0F16
305 #define CLC1GLS1_ADDR 0x0F17
306 #define CLC1GLS2_ADDR 0x0F18
307 #define CLC1GLS3_ADDR 0x0F19
308 #define CLC2CON_ADDR 0x0F1A
309 #define CLC2POL_ADDR 0x0F1B
310 #define CLC2SEL0_ADDR 0x0F1C
311 #define CLC2SEL1_ADDR 0x0F1D
312 #define CLC2SEL2_ADDR 0x0F1E
313 #define CLC2SEL3_ADDR 0x0F1F
314 #define CLC2GLS0_ADDR 0x0F20
315 #define CLC2GLS1_ADDR 0x0F21
316 #define CLC2GLS2_ADDR 0x0F22
317 #define CLC2GLS3_ADDR 0x0F23
318 #define CLC3CON_ADDR 0x0F24
319 #define CLC3POL_ADDR 0x0F25
320 #define CLC3SEL0_ADDR 0x0F26
321 #define CLC3SEL1_ADDR 0x0F27
322 #define CLC3SEL2_ADDR 0x0F28
323 #define CLC3SEL3_ADDR 0x0F29
324 #define CLC3GLS0_ADDR 0x0F2A
325 #define CLC3GLS1_ADDR 0x0F2B
326 #define CLC3GLS2_ADDR 0x0F2C
327 #define CLC3GLS3_ADDR 0x0F2D
328 #define CLC4CON_ADDR 0x0F2E
329 #define CLC4POL_ADDR 0x0F2F
330 #define CLC4SEL0_ADDR 0x0F30
331 #define CLC4SEL1_ADDR 0x0F31
332 #define CLC4SEL2_ADDR 0x0F32
333 #define CLC4SEL3_ADDR 0x0F33
334 #define CLC4GLS0_ADDR 0x0F34
335 #define CLC4GLS1_ADDR 0x0F35
336 #define CLC4GLS2_ADDR 0x0F36
337 #define CLC4GLS3_ADDR 0x0F37
338 #define STATUS_SHAD_ADDR 0x0FE4
339 #define WREG_SHAD_ADDR 0x0FE5
340 #define BSR_SHAD_ADDR 0x0FE6
341 #define PCLATH_SHAD_ADDR 0x0FE7
342 #define FSR0L_SHAD_ADDR 0x0FE8
343 #define FSR0H_SHAD_ADDR 0x0FE9
344 #define FSR1L_SHAD_ADDR 0x0FEA
345 #define FSR1H_SHAD_ADDR 0x0FEB
346 #define STKPTR_ADDR 0x0FED
347 #define TOSL_ADDR 0x0FEE
348 #define TOSH_ADDR 0x0FEF
350 #endif // #ifndef NO_ADDR_DEFINES
352 //==============================================================================
354 // Register Definitions
356 //==============================================================================
358 extern __at(0x0000) __sfr INDF0
;
359 extern __at(0x0001) __sfr INDF1
;
360 extern __at(0x0002) __sfr PCL
;
362 //==============================================================================
365 extern __at(0x0003) __sfr STATUS
;
379 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
387 //==============================================================================
389 extern __at(0x0004) __sfr FSR0
;
390 extern __at(0x0004) __sfr FSR0L
;
391 extern __at(0x0005) __sfr FSR0H
;
392 extern __at(0x0006) __sfr FSR1
;
393 extern __at(0x0006) __sfr FSR1L
;
394 extern __at(0x0007) __sfr FSR1H
;
396 //==============================================================================
399 extern __at(0x0008) __sfr BSR
;
422 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
430 //==============================================================================
432 extern __at(0x0009) __sfr WREG
;
433 extern __at(0x000A) __sfr PCLATH
;
435 //==============================================================================
438 extern __at(0x000B) __sfr INTCON
;
452 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
458 //==============================================================================
461 //==============================================================================
464 extern __at(0x000C) __sfr PORTA
;
487 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
496 //==============================================================================
499 //==============================================================================
502 extern __at(0x000E) __sfr PORTC
;
525 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
534 //==============================================================================
537 //==============================================================================
540 extern __at(0x0010) __sfr PIR0
;
554 extern __at(0x0010) volatile __PIR0bits_t PIR0bits
;
560 //==============================================================================
563 //==============================================================================
566 extern __at(0x0011) __sfr PIR1
;
577 unsigned TMR1GIF
: 1;
580 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
589 #define _TMR1GIF 0x80
591 //==============================================================================
594 //==============================================================================
597 extern __at(0x0012) __sfr PIR2
;
611 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
620 //==============================================================================
623 //==============================================================================
626 extern __at(0x0013) __sfr PIR3
;
635 unsigned TMR3GIF
: 1;
640 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
647 #define _TMR3GIF 0x20
651 //==============================================================================
654 //==============================================================================
657 extern __at(0x0014) __sfr PIR4
;
666 unsigned TMR5GIF
: 1;
671 extern __at(0x0014) volatile __PIR4bits_t PIR4bits
;
678 #define _TMR5GIF 0x20
682 //==============================================================================
685 //==============================================================================
688 extern __at(0x0015) __sfr TMR0L
;
702 extern __at(0x0015) volatile __TMR0Lbits_t TMR0Lbits
;
713 //==============================================================================
716 //==============================================================================
719 extern __at(0x0016) __sfr TMR0H
;
733 extern __at(0x0016) volatile __TMR0Hbits_t TMR0Hbits
;
744 //==============================================================================
747 //==============================================================================
750 extern __at(0x0017) __sfr T0CON0
;
756 unsigned T0OUTPS0
: 1;
757 unsigned T0OUTPS1
: 1;
758 unsigned T0OUTPS2
: 1;
759 unsigned T0OUTPS3
: 1;
760 unsigned T016BIT
: 1;
768 unsigned T0OUTPS
: 4;
773 extern __at(0x0017) volatile __T0CON0bits_t T0CON0bits
;
775 #define _T0OUTPS0 0x01
776 #define _T0OUTPS1 0x02
777 #define _T0OUTPS2 0x04
778 #define _T0OUTPS3 0x08
779 #define _T016BIT 0x10
783 //==============================================================================
786 //==============================================================================
789 extern __at(0x0018) __sfr T0CON1
;
795 unsigned T0CKPS0
: 1;
796 unsigned T0CKPS1
: 1;
797 unsigned T0CKPS2
: 1;
798 unsigned T0CKPS3
: 1;
799 unsigned T0ASYNC
: 1;
818 extern __at(0x0018) volatile __T0CON1bits_t T0CON1bits
;
820 #define _T0CKPS0 0x01
821 #define _T0CKPS1 0x02
822 #define _T0CKPS2 0x04
823 #define _T0CKPS3 0x08
824 #define _T0ASYNC 0x10
829 //==============================================================================
831 extern __at(0x0019) __sfr TMR1
;
832 extern __at(0x0019) __sfr TMR1L
;
833 extern __at(0x001A) __sfr TMR1H
;
835 //==============================================================================
838 extern __at(0x001B) __sfr T1CON
;
848 unsigned T1CKPS0
: 1;
849 unsigned T1CKPS1
: 1;
850 unsigned TMR1CS0
: 1;
851 unsigned TMR1CS1
: 1;
868 extern __at(0x001B) volatile __T1CONbits_t T1CONbits
;
873 #define _T1CKPS0 0x10
874 #define _T1CKPS1 0x20
875 #define _TMR1CS0 0x40
876 #define _TMR1CS1 0x80
878 //==============================================================================
881 //==============================================================================
884 extern __at(0x001C) __sfr T1GCON
;
893 unsigned T1GGO_NOT_DONE
: 1;
907 extern __at(0x001C) volatile __T1GCONbits_t T1GCONbits
;
912 #define _T1GGO_NOT_DONE 0x08
918 //==============================================================================
920 extern __at(0x001D) __sfr TMR2
;
921 extern __at(0x001E) __sfr PR2
;
923 //==============================================================================
926 extern __at(0x001F) __sfr T2CON
;
932 unsigned T2CKPS0
: 1;
933 unsigned T2CKPS1
: 1;
935 unsigned T2OUTPS0
: 1;
936 unsigned T2OUTPS1
: 1;
937 unsigned T2OUTPS2
: 1;
938 unsigned T2OUTPS3
: 1;
951 unsigned T2OUTPS
: 4;
956 extern __at(0x001F) volatile __T2CONbits_t T2CONbits
;
958 #define _T2CKPS0 0x01
959 #define _T2CKPS1 0x02
961 #define _T2OUTPS0 0x08
962 #define _T2OUTPS1 0x10
963 #define _T2OUTPS2 0x20
964 #define _T2OUTPS3 0x40
966 //==============================================================================
969 //==============================================================================
972 extern __at(0x008C) __sfr TRISA
;
986 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
994 //==============================================================================
997 //==============================================================================
1000 extern __at(0x008E) __sfr TRISC
;
1006 unsigned TRISC0
: 1;
1007 unsigned TRISC1
: 1;
1008 unsigned TRISC2
: 1;
1009 unsigned TRISC3
: 1;
1010 unsigned TRISC4
: 1;
1011 unsigned TRISC5
: 1;
1023 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
1025 #define _TRISC0 0x01
1026 #define _TRISC1 0x02
1027 #define _TRISC2 0x04
1028 #define _TRISC3 0x08
1029 #define _TRISC4 0x10
1030 #define _TRISC5 0x20
1032 //==============================================================================
1035 //==============================================================================
1038 extern __at(0x0090) __sfr PIE0
;
1047 unsigned TMR0IE
: 1;
1052 extern __at(0x0090) volatile __PIE0bits_t PIE0bits
;
1056 #define _TMR0IE 0x20
1058 //==============================================================================
1061 //==============================================================================
1064 extern __at(0x0091) __sfr PIE1
;
1068 unsigned TMR1IE
: 1;
1069 unsigned TMR2IE
: 1;
1070 unsigned BCL1IE
: 1;
1071 unsigned SSP1IE
: 1;
1075 unsigned TMR1GIE
: 1;
1078 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
1080 #define _TMR1IE 0x01
1081 #define _TMR2IE 0x02
1082 #define _BCL1IE 0x04
1083 #define _SSP1IE 0x08
1087 #define _TMR1GIE 0x80
1089 //==============================================================================
1092 //==============================================================================
1095 extern __at(0x0092) __sfr PIE2
;
1099 unsigned NCO1IE
: 1;
1100 unsigned TMR4IE
: 1;
1106 unsigned TMR6IE
: 1;
1109 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
1111 #define _NCO1IE 0x01
1112 #define _TMR4IE 0x02
1116 #define _TMR6IE 0x80
1118 //==============================================================================
1121 //==============================================================================
1124 extern __at(0x0093) __sfr PIE3
;
1128 unsigned CLC1IE
: 1;
1129 unsigned CLC2IE
: 1;
1130 unsigned CLC3IE
: 1;
1131 unsigned CLC4IE
: 1;
1132 unsigned TMR3IE
: 1;
1133 unsigned TMR3GIE
: 1;
1138 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
1140 #define _CLC1IE 0x01
1141 #define _CLC2IE 0x02
1142 #define _CLC3IE 0x04
1143 #define _CLC4IE 0x08
1144 #define _TMR3IE 0x10
1145 #define _TMR3GIE 0x20
1149 //==============================================================================
1152 //==============================================================================
1155 extern __at(0x0094) __sfr PIE4
;
1159 unsigned CCP1IE
: 1;
1160 unsigned CCP2IE
: 1;
1161 unsigned CCP3IE
: 1;
1162 unsigned CCP4IE
: 1;
1163 unsigned TMR5IE
: 1;
1164 unsigned TMR5GIE
: 1;
1165 unsigned CWG1IE
: 1;
1166 unsigned CWG2IE
: 1;
1169 extern __at(0x0094) volatile __PIE4bits_t PIE4bits
;
1171 #define _CCP1IE 0x01
1172 #define _CCP2IE 0x02
1173 #define _CCP3IE 0x04
1174 #define _CCP4IE 0x08
1175 #define _TMR5IE 0x10
1176 #define _TMR5GIE 0x20
1177 #define _CWG1IE 0x40
1178 #define _CWG2IE 0x80
1180 //==============================================================================
1183 //==============================================================================
1186 extern __at(0x0097) __sfr WDTCON
;
1192 unsigned SWDTEN
: 1;
1193 unsigned WDTPS0
: 1;
1194 unsigned WDTPS1
: 1;
1195 unsigned WDTPS2
: 1;
1196 unsigned WDTPS3
: 1;
1197 unsigned WDTPS4
: 1;
1210 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1212 #define _SWDTEN 0x01
1213 #define _WDTPS0 0x02
1214 #define _WDTPS1 0x04
1215 #define _WDTPS2 0x08
1216 #define _WDTPS3 0x10
1217 #define _WDTPS4 0x20
1219 //==============================================================================
1221 extern __at(0x009B) __sfr ADRES
;
1222 extern __at(0x009B) __sfr ADRESL
;
1223 extern __at(0x009C) __sfr ADRESH
;
1225 //==============================================================================
1228 extern __at(0x009D) __sfr ADCON0
;
1235 unsigned GO_NOT_DONE
: 1;
1275 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1278 #define _GO_NOT_DONE 0x02
1288 //==============================================================================
1291 //==============================================================================
1294 extern __at(0x009E) __sfr ADCON1
;
1300 unsigned ADPREF0
: 1;
1301 unsigned ADPREF1
: 1;
1302 unsigned ADNREF
: 1;
1312 unsigned ADPREF
: 2;
1324 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1326 #define _ADPREF0 0x01
1327 #define _ADPREF1 0x02
1328 #define _ADNREF 0x04
1334 //==============================================================================
1337 //==============================================================================
1340 extern __at(0x009F) __sfr ADACT
;
1346 unsigned ADACT0
: 1;
1347 unsigned ADACT1
: 1;
1348 unsigned ADACT2
: 1;
1349 unsigned ADACT3
: 1;
1350 unsigned ADACT4
: 1;
1363 extern __at(0x009F) volatile __ADACTbits_t ADACTbits
;
1365 #define _ADACT0 0x01
1366 #define _ADACT1 0x02
1367 #define _ADACT2 0x04
1368 #define _ADACT3 0x08
1369 #define _ADACT4 0x10
1371 //==============================================================================
1374 //==============================================================================
1377 extern __at(0x010C) __sfr LATA
;
1391 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1399 //==============================================================================
1402 //==============================================================================
1405 extern __at(0x010E) __sfr LATC
;
1428 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1437 //==============================================================================
1440 //==============================================================================
1443 extern __at(0x0111) __sfr CM1CON0
;
1447 unsigned C1SYNC
: 1;
1457 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1459 #define _C1SYNC 0x01
1466 //==============================================================================
1469 //==============================================================================
1472 extern __at(0x0112) __sfr CM1CON1
;
1478 unsigned C1NCH0
: 1;
1479 unsigned C1NCH1
: 1;
1480 unsigned C1NCH2
: 1;
1481 unsigned C1PCH0
: 1;
1482 unsigned C1PCH1
: 1;
1483 unsigned C1PCH2
: 1;
1484 unsigned C1INTN
: 1;
1485 unsigned C1INTP
: 1;
1502 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1504 #define _C1NCH0 0x01
1505 #define _C1NCH1 0x02
1506 #define _C1NCH2 0x04
1507 #define _C1PCH0 0x08
1508 #define _C1PCH1 0x10
1509 #define _C1PCH2 0x20
1510 #define _C1INTN 0x40
1511 #define _C1INTP 0x80
1513 //==============================================================================
1516 //==============================================================================
1519 extern __at(0x0113) __sfr CM2CON0
;
1523 unsigned C2SYNC
: 1;
1533 extern __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits
;
1535 #define _C2SYNC 0x01
1542 //==============================================================================
1545 //==============================================================================
1548 extern __at(0x0114) __sfr CM2CON1
;
1554 unsigned C2NCH0
: 1;
1555 unsigned C2NCH1
: 1;
1556 unsigned C2NCH2
: 1;
1557 unsigned C2PCH0
: 1;
1558 unsigned C2PCH1
: 1;
1559 unsigned C2PCH2
: 1;
1560 unsigned C2INTN
: 1;
1561 unsigned C2INTP
: 1;
1578 extern __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits
;
1580 #define _C2NCH0 0x01
1581 #define _C2NCH1 0x02
1582 #define _C2NCH2 0x04
1583 #define _C2PCH0 0x08
1584 #define _C2PCH1 0x10
1585 #define _C2PCH2 0x20
1586 #define _C2INTN 0x40
1587 #define _C2INTP 0x80
1589 //==============================================================================
1592 //==============================================================================
1595 extern __at(0x0115) __sfr CMOUT
;
1599 unsigned MC1OUT
: 1;
1600 unsigned MC2OUT
: 1;
1609 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1611 #define _MC1OUT 0x01
1612 #define _MC2OUT 0x02
1614 //==============================================================================
1617 //==============================================================================
1620 extern __at(0x0116) __sfr BORCON
;
1624 unsigned BORRDY
: 1;
1631 unsigned SBOREN
: 1;
1634 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1636 #define _BORRDY 0x01
1637 #define _SBOREN 0x80
1639 //==============================================================================
1642 //==============================================================================
1645 extern __at(0x0117) __sfr FVRCON
;
1651 unsigned ADFVR0
: 1;
1652 unsigned ADFVR1
: 1;
1653 unsigned CDAFVR0
: 1;
1654 unsigned CDAFVR1
: 1;
1657 unsigned FVRRDY
: 1;
1670 unsigned CDAFVR
: 2;
1675 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1677 #define _ADFVR0 0x01
1678 #define _ADFVR1 0x02
1679 #define _CDAFVR0 0x04
1680 #define _CDAFVR1 0x08
1683 #define _FVRRDY 0x40
1686 //==============================================================================
1689 //==============================================================================
1692 extern __at(0x0118) __sfr DACCON0
;
1698 unsigned DAC1NSS
: 1;
1700 unsigned DAC1PSS0
: 1;
1701 unsigned DAC1PSS1
: 1;
1703 unsigned DAC1OE
: 1;
1705 unsigned DAC1EN
: 1;
1711 unsigned DAC1PSS
: 2;
1716 extern __at(0x0118) volatile __DACCON0bits_t DACCON0bits
;
1718 #define _DAC1NSS 0x01
1719 #define _DAC1PSS0 0x04
1720 #define _DAC1PSS1 0x08
1721 #define _DAC1OE 0x20
1722 #define _DAC1EN 0x80
1724 //==============================================================================
1727 //==============================================================================
1730 extern __at(0x0119) __sfr DACCON1
;
1736 unsigned DAC1R0
: 1;
1737 unsigned DAC1R1
: 1;
1738 unsigned DAC1R2
: 1;
1739 unsigned DAC1R3
: 1;
1740 unsigned DAC1R4
: 1;
1753 extern __at(0x0119) volatile __DACCON1bits_t DACCON1bits
;
1755 #define _DAC1R0 0x01
1756 #define _DAC1R1 0x02
1757 #define _DAC1R2 0x04
1758 #define _DAC1R3 0x08
1759 #define _DAC1R4 0x10
1761 //==============================================================================
1764 //==============================================================================
1767 extern __at(0x018C) __sfr ANSELA
;
1781 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1789 //==============================================================================
1792 //==============================================================================
1795 extern __at(0x018E) __sfr ANSELC
;
1818 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
1827 //==============================================================================
1830 //==============================================================================
1833 extern __at(0x0197) __sfr VREGCON
;
1838 unsigned VREGPM
: 1;
1847 extern __at(0x0197) volatile __VREGCONbits_t VREGCONbits
;
1849 #define _VREGPM 0x02
1851 //==============================================================================
1853 extern __at(0x0199) __sfr RC1REG
;
1854 extern __at(0x0199) __sfr RCREG
;
1855 extern __at(0x0199) __sfr RCREG1
;
1856 extern __at(0x019A) __sfr TX1REG
;
1857 extern __at(0x019A) __sfr TXREG
;
1858 extern __at(0x019A) __sfr TXREG1
;
1859 extern __at(0x019B) __sfr SP1BRG
;
1860 extern __at(0x019B) __sfr SP1BRGL
;
1861 extern __at(0x019B) __sfr SPBRG
;
1862 extern __at(0x019B) __sfr SPBRG1
;
1863 extern __at(0x019B) __sfr SPBRGL
;
1864 extern __at(0x019C) __sfr SP1BRGH
;
1865 extern __at(0x019C) __sfr SPBRGH
;
1866 extern __at(0x019C) __sfr SPBRGH1
;
1868 //==============================================================================
1871 extern __at(0x019D) __sfr RC1STA
;
1885 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
1896 //==============================================================================
1899 //==============================================================================
1902 extern __at(0x019D) __sfr RCSTA
;
1916 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
1918 #define _RCSTA_RX9D 0x01
1919 #define _RCSTA_OERR 0x02
1920 #define _RCSTA_FERR 0x04
1921 #define _RCSTA_ADDEN 0x08
1922 #define _RCSTA_CREN 0x10
1923 #define _RCSTA_SREN 0x20
1924 #define _RCSTA_RX9 0x40
1925 #define _RCSTA_SPEN 0x80
1927 //==============================================================================
1930 //==============================================================================
1933 extern __at(0x019D) __sfr RCSTA1
;
1947 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
1949 #define _RCSTA1_RX9D 0x01
1950 #define _RCSTA1_OERR 0x02
1951 #define _RCSTA1_FERR 0x04
1952 #define _RCSTA1_ADDEN 0x08
1953 #define _RCSTA1_CREN 0x10
1954 #define _RCSTA1_SREN 0x20
1955 #define _RCSTA1_RX9 0x40
1956 #define _RCSTA1_SPEN 0x80
1958 //==============================================================================
1961 //==============================================================================
1964 extern __at(0x019E) __sfr TX1STA
;
1978 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
1989 //==============================================================================
1992 //==============================================================================
1995 extern __at(0x019E) __sfr TXSTA
;
2009 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
2011 #define _TXSTA_TX9D 0x01
2012 #define _TXSTA_TRMT 0x02
2013 #define _TXSTA_BRGH 0x04
2014 #define _TXSTA_SENDB 0x08
2015 #define _TXSTA_SYNC 0x10
2016 #define _TXSTA_TXEN 0x20
2017 #define _TXSTA_TX9 0x40
2018 #define _TXSTA_CSRC 0x80
2020 //==============================================================================
2023 //==============================================================================
2026 extern __at(0x019E) __sfr TXSTA1
;
2040 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
2042 #define _TXSTA1_TX9D 0x01
2043 #define _TXSTA1_TRMT 0x02
2044 #define _TXSTA1_BRGH 0x04
2045 #define _TXSTA1_SENDB 0x08
2046 #define _TXSTA1_SYNC 0x10
2047 #define _TXSTA1_TXEN 0x20
2048 #define _TXSTA1_TX9 0x40
2049 #define _TXSTA1_CSRC 0x80
2051 //==============================================================================
2054 //==============================================================================
2057 extern __at(0x019F) __sfr BAUD1CON
;
2068 unsigned ABDOVF
: 1;
2071 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
2078 #define _ABDOVF 0x80
2080 //==============================================================================
2083 //==============================================================================
2086 extern __at(0x019F) __sfr BAUDCON
;
2097 unsigned ABDOVF
: 1;
2100 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
2102 #define _BAUDCON_ABDEN 0x01
2103 #define _BAUDCON_WUE 0x02
2104 #define _BAUDCON_BRG16 0x08
2105 #define _BAUDCON_SCKP 0x10
2106 #define _BAUDCON_RCIDL 0x40
2107 #define _BAUDCON_ABDOVF 0x80
2109 //==============================================================================
2112 //==============================================================================
2115 extern __at(0x019F) __sfr BAUDCON1
;
2126 unsigned ABDOVF
: 1;
2129 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
2131 #define _BAUDCON1_ABDEN 0x01
2132 #define _BAUDCON1_WUE 0x02
2133 #define _BAUDCON1_BRG16 0x08
2134 #define _BAUDCON1_SCKP 0x10
2135 #define _BAUDCON1_RCIDL 0x40
2136 #define _BAUDCON1_ABDOVF 0x80
2138 //==============================================================================
2141 //==============================================================================
2144 extern __at(0x019F) __sfr BAUDCTL
;
2155 unsigned ABDOVF
: 1;
2158 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
2160 #define _BAUDCTL_ABDEN 0x01
2161 #define _BAUDCTL_WUE 0x02
2162 #define _BAUDCTL_BRG16 0x08
2163 #define _BAUDCTL_SCKP 0x10
2164 #define _BAUDCTL_RCIDL 0x40
2165 #define _BAUDCTL_ABDOVF 0x80
2167 //==============================================================================
2170 //==============================================================================
2173 extern __at(0x019F) __sfr BAUDCTL1
;
2184 unsigned ABDOVF
: 1;
2187 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
2189 #define _BAUDCTL1_ABDEN 0x01
2190 #define _BAUDCTL1_WUE 0x02
2191 #define _BAUDCTL1_BRG16 0x08
2192 #define _BAUDCTL1_SCKP 0x10
2193 #define _BAUDCTL1_RCIDL 0x40
2194 #define _BAUDCTL1_ABDOVF 0x80
2196 //==============================================================================
2199 //==============================================================================
2202 extern __at(0x020C) __sfr WPUA
;
2225 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
2234 //==============================================================================
2237 //==============================================================================
2240 extern __at(0x020E) __sfr WPUC
;
2263 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
2272 //==============================================================================
2275 //==============================================================================
2278 extern __at(0x0211) __sfr SSP1BUF
;
2284 unsigned SSP1BUF0
: 1;
2285 unsigned SSP1BUF1
: 1;
2286 unsigned SSP1BUF2
: 1;
2287 unsigned SSP1BUF3
: 1;
2288 unsigned SSP1BUF4
: 1;
2289 unsigned SSP1BUF5
: 1;
2290 unsigned SSP1BUF6
: 1;
2291 unsigned SSP1BUF7
: 1;
2307 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
2309 #define _SSP1BUF0 0x01
2311 #define _SSP1BUF1 0x02
2313 #define _SSP1BUF2 0x04
2315 #define _SSP1BUF3 0x08
2317 #define _SSP1BUF4 0x10
2319 #define _SSP1BUF5 0x20
2321 #define _SSP1BUF6 0x40
2323 #define _SSP1BUF7 0x80
2326 //==============================================================================
2329 //==============================================================================
2332 extern __at(0x0211) __sfr SSPBUF
;
2338 unsigned SSP1BUF0
: 1;
2339 unsigned SSP1BUF1
: 1;
2340 unsigned SSP1BUF2
: 1;
2341 unsigned SSP1BUF3
: 1;
2342 unsigned SSP1BUF4
: 1;
2343 unsigned SSP1BUF5
: 1;
2344 unsigned SSP1BUF6
: 1;
2345 unsigned SSP1BUF7
: 1;
2361 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
2363 #define _SSPBUF_SSP1BUF0 0x01
2364 #define _SSPBUF_BUF0 0x01
2365 #define _SSPBUF_SSP1BUF1 0x02
2366 #define _SSPBUF_BUF1 0x02
2367 #define _SSPBUF_SSP1BUF2 0x04
2368 #define _SSPBUF_BUF2 0x04
2369 #define _SSPBUF_SSP1BUF3 0x08
2370 #define _SSPBUF_BUF3 0x08
2371 #define _SSPBUF_SSP1BUF4 0x10
2372 #define _SSPBUF_BUF4 0x10
2373 #define _SSPBUF_SSP1BUF5 0x20
2374 #define _SSPBUF_BUF5 0x20
2375 #define _SSPBUF_SSP1BUF6 0x40
2376 #define _SSPBUF_BUF6 0x40
2377 #define _SSPBUF_SSP1BUF7 0x80
2378 #define _SSPBUF_BUF7 0x80
2380 //==============================================================================
2383 //==============================================================================
2386 extern __at(0x0212) __sfr SSP1ADD
;
2392 unsigned SSP1ADD0
: 1;
2393 unsigned SSP1ADD1
: 1;
2394 unsigned SSP1ADD2
: 1;
2395 unsigned SSP1ADD3
: 1;
2396 unsigned SSP1ADD4
: 1;
2397 unsigned SSP1ADD5
: 1;
2398 unsigned SSP1ADD6
: 1;
2399 unsigned SSP1ADD7
: 1;
2415 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
2417 #define _SSP1ADD0 0x01
2419 #define _SSP1ADD1 0x02
2421 #define _SSP1ADD2 0x04
2423 #define _SSP1ADD3 0x08
2425 #define _SSP1ADD4 0x10
2427 #define _SSP1ADD5 0x20
2429 #define _SSP1ADD6 0x40
2431 #define _SSP1ADD7 0x80
2434 //==============================================================================
2437 //==============================================================================
2440 extern __at(0x0212) __sfr SSPADD
;
2446 unsigned SSP1ADD0
: 1;
2447 unsigned SSP1ADD1
: 1;
2448 unsigned SSP1ADD2
: 1;
2449 unsigned SSP1ADD3
: 1;
2450 unsigned SSP1ADD4
: 1;
2451 unsigned SSP1ADD5
: 1;
2452 unsigned SSP1ADD6
: 1;
2453 unsigned SSP1ADD7
: 1;
2469 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
2471 #define _SSPADD_SSP1ADD0 0x01
2472 #define _SSPADD_ADD0 0x01
2473 #define _SSPADD_SSP1ADD1 0x02
2474 #define _SSPADD_ADD1 0x02
2475 #define _SSPADD_SSP1ADD2 0x04
2476 #define _SSPADD_ADD2 0x04
2477 #define _SSPADD_SSP1ADD3 0x08
2478 #define _SSPADD_ADD3 0x08
2479 #define _SSPADD_SSP1ADD4 0x10
2480 #define _SSPADD_ADD4 0x10
2481 #define _SSPADD_SSP1ADD5 0x20
2482 #define _SSPADD_ADD5 0x20
2483 #define _SSPADD_SSP1ADD6 0x40
2484 #define _SSPADD_ADD6 0x40
2485 #define _SSPADD_SSP1ADD7 0x80
2486 #define _SSPADD_ADD7 0x80
2488 //==============================================================================
2491 //==============================================================================
2494 extern __at(0x0213) __sfr SSP1MSK
;
2500 unsigned SSP1MSK0
: 1;
2501 unsigned SSP1MSK1
: 1;
2502 unsigned SSP1MSK2
: 1;
2503 unsigned SSP1MSK3
: 1;
2504 unsigned SSP1MSK4
: 1;
2505 unsigned SSP1MSK5
: 1;
2506 unsigned SSP1MSK6
: 1;
2507 unsigned SSP1MSK7
: 1;
2523 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
2525 #define _SSP1MSK0 0x01
2527 #define _SSP1MSK1 0x02
2529 #define _SSP1MSK2 0x04
2531 #define _SSP1MSK3 0x08
2533 #define _SSP1MSK4 0x10
2535 #define _SSP1MSK5 0x20
2537 #define _SSP1MSK6 0x40
2539 #define _SSP1MSK7 0x80
2542 //==============================================================================
2545 //==============================================================================
2548 extern __at(0x0213) __sfr SSPMSK
;
2554 unsigned SSP1MSK0
: 1;
2555 unsigned SSP1MSK1
: 1;
2556 unsigned SSP1MSK2
: 1;
2557 unsigned SSP1MSK3
: 1;
2558 unsigned SSP1MSK4
: 1;
2559 unsigned SSP1MSK5
: 1;
2560 unsigned SSP1MSK6
: 1;
2561 unsigned SSP1MSK7
: 1;
2577 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
2579 #define _SSPMSK_SSP1MSK0 0x01
2580 #define _SSPMSK_MSK0 0x01
2581 #define _SSPMSK_SSP1MSK1 0x02
2582 #define _SSPMSK_MSK1 0x02
2583 #define _SSPMSK_SSP1MSK2 0x04
2584 #define _SSPMSK_MSK2 0x04
2585 #define _SSPMSK_SSP1MSK3 0x08
2586 #define _SSPMSK_MSK3 0x08
2587 #define _SSPMSK_SSP1MSK4 0x10
2588 #define _SSPMSK_MSK4 0x10
2589 #define _SSPMSK_SSP1MSK5 0x20
2590 #define _SSPMSK_MSK5 0x20
2591 #define _SSPMSK_SSP1MSK6 0x40
2592 #define _SSPMSK_MSK6 0x40
2593 #define _SSPMSK_SSP1MSK7 0x80
2594 #define _SSPMSK_MSK7 0x80
2596 //==============================================================================
2599 //==============================================================================
2602 extern __at(0x0214) __sfr SSP1STAT
;
2608 unsigned R_NOT_W
: 1;
2611 unsigned D_NOT_A
: 1;
2616 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
2620 #define _R_NOT_W 0x04
2623 #define _D_NOT_A 0x20
2627 //==============================================================================
2630 //==============================================================================
2633 extern __at(0x0214) __sfr SSPSTAT
;
2639 unsigned R_NOT_W
: 1;
2642 unsigned D_NOT_A
: 1;
2647 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
2649 #define _SSPSTAT_BF 0x01
2650 #define _SSPSTAT_UA 0x02
2651 #define _SSPSTAT_R_NOT_W 0x04
2652 #define _SSPSTAT_S 0x08
2653 #define _SSPSTAT_P 0x10
2654 #define _SSPSTAT_D_NOT_A 0x20
2655 #define _SSPSTAT_CKE 0x40
2656 #define _SSPSTAT_SMP 0x80
2658 //==============================================================================
2661 //==============================================================================
2664 extern __at(0x0215) __sfr SSP1CON
;
2687 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
2698 //==============================================================================
2701 //==============================================================================
2704 extern __at(0x0215) __sfr SSP1CON1
;
2727 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
2729 #define _SSP1CON1_SSPM0 0x01
2730 #define _SSP1CON1_SSPM1 0x02
2731 #define _SSP1CON1_SSPM2 0x04
2732 #define _SSP1CON1_SSPM3 0x08
2733 #define _SSP1CON1_CKP 0x10
2734 #define _SSP1CON1_SSPEN 0x20
2735 #define _SSP1CON1_SSPOV 0x40
2736 #define _SSP1CON1_WCOL 0x80
2738 //==============================================================================
2741 //==============================================================================
2744 extern __at(0x0215) __sfr SSPCON
;
2767 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2769 #define _SSPCON_SSPM0 0x01
2770 #define _SSPCON_SSPM1 0x02
2771 #define _SSPCON_SSPM2 0x04
2772 #define _SSPCON_SSPM3 0x08
2773 #define _SSPCON_CKP 0x10
2774 #define _SSPCON_SSPEN 0x20
2775 #define _SSPCON_SSPOV 0x40
2776 #define _SSPCON_WCOL 0x80
2778 //==============================================================================
2781 //==============================================================================
2784 extern __at(0x0215) __sfr SSPCON1
;
2807 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2809 #define _SSPCON1_SSPM0 0x01
2810 #define _SSPCON1_SSPM1 0x02
2811 #define _SSPCON1_SSPM2 0x04
2812 #define _SSPCON1_SSPM3 0x08
2813 #define _SSPCON1_CKP 0x10
2814 #define _SSPCON1_SSPEN 0x20
2815 #define _SSPCON1_SSPOV 0x40
2816 #define _SSPCON1_WCOL 0x80
2818 //==============================================================================
2821 //==============================================================================
2824 extern __at(0x0216) __sfr SSP1CON2
;
2834 unsigned ACKSTAT
: 1;
2838 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
2846 #define _ACKSTAT 0x40
2849 //==============================================================================
2852 //==============================================================================
2855 extern __at(0x0216) __sfr SSPCON2
;
2865 unsigned ACKSTAT
: 1;
2869 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
2871 #define _SSPCON2_SEN 0x01
2872 #define _SSPCON2_RSEN 0x02
2873 #define _SSPCON2_PEN 0x04
2874 #define _SSPCON2_RCEN 0x08
2875 #define _SSPCON2_ACKEN 0x10
2876 #define _SSPCON2_ACKDT 0x20
2877 #define _SSPCON2_ACKSTAT 0x40
2878 #define _SSPCON2_GCEN 0x80
2880 //==============================================================================
2883 //==============================================================================
2886 extern __at(0x0217) __sfr SSP1CON3
;
2897 unsigned ACKTIM
: 1;
2900 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
2909 #define _ACKTIM 0x80
2911 //==============================================================================
2914 //==============================================================================
2917 extern __at(0x0217) __sfr SSPCON3
;
2928 unsigned ACKTIM
: 1;
2931 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
2933 #define _SSPCON3_DHEN 0x01
2934 #define _SSPCON3_AHEN 0x02
2935 #define _SSPCON3_SBCDE 0x04
2936 #define _SSPCON3_SDAHT 0x08
2937 #define _SSPCON3_BOEN 0x10
2938 #define _SSPCON3_SCIE 0x20
2939 #define _SSPCON3_PCIE 0x40
2940 #define _SSPCON3_ACKTIM 0x80
2942 //==============================================================================
2945 //==============================================================================
2948 extern __at(0x028C) __sfr ODCONA
;
2962 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
2970 //==============================================================================
2973 //==============================================================================
2976 extern __at(0x028E) __sfr ODCONC
;
2999 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
3008 //==============================================================================
3010 extern __at(0x0291) __sfr CCPR1
;
3011 extern __at(0x0291) __sfr CCPR1L
;
3012 extern __at(0x0292) __sfr CCPR1H
;
3014 //==============================================================================
3017 extern __at(0x0293) __sfr CCP1CON
;
3023 unsigned CCP1MODE0
: 1;
3024 unsigned CCP1MODE1
: 1;
3025 unsigned CCP1MODE2
: 1;
3026 unsigned CCP1MODE3
: 1;
3027 unsigned CCP1FMT
: 1;
3028 unsigned CCP1OUT
: 1;
3030 unsigned CCP1EN
: 1;
3035 unsigned CCP1MODE
: 4;
3040 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
3042 #define _CCP1MODE0 0x01
3043 #define _CCP1MODE1 0x02
3044 #define _CCP1MODE2 0x04
3045 #define _CCP1MODE3 0x08
3046 #define _CCP1FMT 0x10
3047 #define _CCP1OUT 0x20
3048 #define _CCP1EN 0x80
3050 //==============================================================================
3053 //==============================================================================
3056 extern __at(0x0294) __sfr CCP1CAP
;
3062 unsigned CCP1CTS0
: 1;
3063 unsigned CCP1CTS1
: 1;
3064 unsigned CCP1CTS2
: 1;
3065 unsigned CCP1CTS3
: 1;
3074 unsigned CCP1CTS
: 4;
3079 extern __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits
;
3081 #define _CCP1CTS0 0x01
3082 #define _CCP1CTS1 0x02
3083 #define _CCP1CTS2 0x04
3084 #define _CCP1CTS3 0x08
3086 //==============================================================================
3088 extern __at(0x0295) __sfr CCPR2
;
3089 extern __at(0x0295) __sfr CCPR2L
;
3090 extern __at(0x0296) __sfr CCPR2H
;
3092 //==============================================================================
3095 extern __at(0x0297) __sfr CCP2CON
;
3101 unsigned CCP2MODE0
: 1;
3102 unsigned CCP2MODE1
: 1;
3103 unsigned CCP2MODE2
: 1;
3104 unsigned CCP2MODE3
: 1;
3105 unsigned CCP2FMT
: 1;
3106 unsigned CCP2OUT
: 1;
3108 unsigned CCP2EN
: 1;
3113 unsigned CCP2MODE
: 4;
3118 extern __at(0x0297) volatile __CCP2CONbits_t CCP2CONbits
;
3120 #define _CCP2MODE0 0x01
3121 #define _CCP2MODE1 0x02
3122 #define _CCP2MODE2 0x04
3123 #define _CCP2MODE3 0x08
3124 #define _CCP2FMT 0x10
3125 #define _CCP2OUT 0x20
3126 #define _CCP2EN 0x80
3128 //==============================================================================
3131 //==============================================================================
3134 extern __at(0x0298) __sfr CCP2CAP
;
3140 unsigned CCP2CTS0
: 1;
3141 unsigned CCP2CTS1
: 1;
3142 unsigned CCP2CTS2
: 1;
3143 unsigned CCP2CTS3
: 1;
3152 unsigned CCP2CTS
: 4;
3157 extern __at(0x0298) volatile __CCP2CAPbits_t CCP2CAPbits
;
3159 #define _CCP2CTS0 0x01
3160 #define _CCP2CTS1 0x02
3161 #define _CCP2CTS2 0x04
3162 #define _CCP2CTS3 0x08
3164 //==============================================================================
3167 //==============================================================================
3170 extern __at(0x029F) __sfr CCPTMRS
;
3176 unsigned C1TSEL0
: 1;
3177 unsigned C1TSEL1
: 1;
3178 unsigned C2TSEL0
: 1;
3179 unsigned C2TSEL1
: 1;
3180 unsigned C3TSEL0
: 1;
3181 unsigned C3TSEL1
: 1;
3182 unsigned C4TSEL0
: 1;
3183 unsigned C4TSEL1
: 1;
3188 unsigned C1TSEL
: 2;
3195 unsigned C2TSEL
: 2;
3202 unsigned C3TSEL
: 2;
3209 unsigned C4TSEL
: 2;
3213 extern __at(0x029F) volatile __CCPTMRSbits_t CCPTMRSbits
;
3215 #define _C1TSEL0 0x01
3216 #define _C1TSEL1 0x02
3217 #define _C2TSEL0 0x04
3218 #define _C2TSEL1 0x08
3219 #define _C3TSEL0 0x10
3220 #define _C3TSEL1 0x20
3221 #define _C4TSEL0 0x40
3222 #define _C4TSEL1 0x80
3224 //==============================================================================
3227 //==============================================================================
3230 extern __at(0x030C) __sfr SLRCONA
;
3244 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
3252 //==============================================================================
3255 //==============================================================================
3258 extern __at(0x030E) __sfr SLRCONC
;
3281 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
3290 //==============================================================================
3292 extern __at(0x0311) __sfr CCPR3
;
3293 extern __at(0x0311) __sfr CCPR3L
;
3294 extern __at(0x0312) __sfr CCPR3H
;
3296 //==============================================================================
3299 extern __at(0x0313) __sfr CCP3CON
;
3305 unsigned CCP3MODE0
: 1;
3306 unsigned CCP3MODE1
: 1;
3307 unsigned CCP3MODE2
: 1;
3308 unsigned CCP3MODE3
: 1;
3309 unsigned CCP3FMT
: 1;
3310 unsigned CCP3OUT
: 1;
3312 unsigned CCP3EN
: 1;
3317 unsigned CCP3MODE
: 4;
3322 extern __at(0x0313) volatile __CCP3CONbits_t CCP3CONbits
;
3324 #define _CCP3MODE0 0x01
3325 #define _CCP3MODE1 0x02
3326 #define _CCP3MODE2 0x04
3327 #define _CCP3MODE3 0x08
3328 #define _CCP3FMT 0x10
3329 #define _CCP3OUT 0x20
3330 #define _CCP3EN 0x80
3332 //==============================================================================
3335 //==============================================================================
3338 extern __at(0x0314) __sfr CCP3CAP
;
3344 unsigned CCP3CTS0
: 1;
3345 unsigned CCP3CTS1
: 1;
3346 unsigned CCP3CTS2
: 1;
3347 unsigned CCP3CTS3
: 1;
3356 unsigned CCP3CTS
: 4;
3361 extern __at(0x0314) volatile __CCP3CAPbits_t CCP3CAPbits
;
3363 #define _CCP3CTS0 0x01
3364 #define _CCP3CTS1 0x02
3365 #define _CCP3CTS2 0x04
3366 #define _CCP3CTS3 0x08
3368 //==============================================================================
3370 extern __at(0x0315) __sfr CCPR4
;
3371 extern __at(0x0315) __sfr CCPR4L
;
3372 extern __at(0x0316) __sfr CCPR4H
;
3374 //==============================================================================
3377 extern __at(0x0317) __sfr CCP4CON
;
3383 unsigned CCP4MODE0
: 1;
3384 unsigned CCP4MODE1
: 1;
3385 unsigned CCP4MODE2
: 1;
3386 unsigned CCP4MODE3
: 1;
3387 unsigned CCP4FMT
: 1;
3388 unsigned CCP4OUT
: 1;
3390 unsigned CCP4EN
: 1;
3395 unsigned CCP4MODE
: 4;
3400 extern __at(0x0317) volatile __CCP4CONbits_t CCP4CONbits
;
3402 #define _CCP4MODE0 0x01
3403 #define _CCP4MODE1 0x02
3404 #define _CCP4MODE2 0x04
3405 #define _CCP4MODE3 0x08
3406 #define _CCP4FMT 0x10
3407 #define _CCP4OUT 0x20
3408 #define _CCP4EN 0x80
3410 //==============================================================================
3413 //==============================================================================
3416 extern __at(0x0318) __sfr CCP4CAP
;
3422 unsigned CCP4CTS0
: 1;
3423 unsigned CCP4CTS1
: 1;
3424 unsigned CCP4CTS2
: 1;
3425 unsigned CCP4CTS3
: 1;
3434 unsigned CCP4CTS
: 4;
3439 extern __at(0x0318) volatile __CCP4CAPbits_t CCP4CAPbits
;
3441 #define _CCP4CTS0 0x01
3442 #define _CCP4CTS1 0x02
3443 #define _CCP4CTS2 0x04
3444 #define _CCP4CTS3 0x08
3446 //==============================================================================
3449 //==============================================================================
3452 extern __at(0x038C) __sfr INLVLA
;
3458 unsigned INLVLA0
: 1;
3459 unsigned INLVLA1
: 1;
3460 unsigned INLVLA2
: 1;
3461 unsigned INLVLA3
: 1;
3462 unsigned INLVLA4
: 1;
3463 unsigned INLVLA5
: 1;
3470 unsigned INLVLA
: 6;
3475 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
3477 #define _INLVLA0 0x01
3478 #define _INLVLA1 0x02
3479 #define _INLVLA2 0x04
3480 #define _INLVLA3 0x08
3481 #define _INLVLA4 0x10
3482 #define _INLVLA5 0x20
3484 //==============================================================================
3487 //==============================================================================
3490 extern __at(0x038E) __sfr INLVLC
;
3496 unsigned INLVLC0
: 1;
3497 unsigned INLVLC1
: 1;
3498 unsigned INLVLC2
: 1;
3499 unsigned INLVLC3
: 1;
3500 unsigned INLVLC4
: 1;
3501 unsigned INLVLC5
: 1;
3508 unsigned INLVLC
: 6;
3513 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
3515 #define _INLVLC0 0x01
3516 #define _INLVLC1 0x02
3517 #define _INLVLC2 0x04
3518 #define _INLVLC3 0x08
3519 #define _INLVLC4 0x10
3520 #define _INLVLC5 0x20
3522 //==============================================================================
3525 //==============================================================================
3528 extern __at(0x0391) __sfr IOCAP
;
3534 unsigned IOCAP0
: 1;
3535 unsigned IOCAP1
: 1;
3536 unsigned IOCAP2
: 1;
3537 unsigned IOCAP3
: 1;
3538 unsigned IOCAP4
: 1;
3539 unsigned IOCAP5
: 1;
3551 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
3553 #define _IOCAP0 0x01
3554 #define _IOCAP1 0x02
3555 #define _IOCAP2 0x04
3556 #define _IOCAP3 0x08
3557 #define _IOCAP4 0x10
3558 #define _IOCAP5 0x20
3560 //==============================================================================
3563 //==============================================================================
3566 extern __at(0x0392) __sfr IOCAN
;
3572 unsigned IOCAN0
: 1;
3573 unsigned IOCAN1
: 1;
3574 unsigned IOCAN2
: 1;
3575 unsigned IOCAN3
: 1;
3576 unsigned IOCAN4
: 1;
3577 unsigned IOCAN5
: 1;
3589 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
3591 #define _IOCAN0 0x01
3592 #define _IOCAN1 0x02
3593 #define _IOCAN2 0x04
3594 #define _IOCAN3 0x08
3595 #define _IOCAN4 0x10
3596 #define _IOCAN5 0x20
3598 //==============================================================================
3601 //==============================================================================
3604 extern __at(0x0393) __sfr IOCAF
;
3610 unsigned IOCAF0
: 1;
3611 unsigned IOCAF1
: 1;
3612 unsigned IOCAF2
: 1;
3613 unsigned IOCAF3
: 1;
3614 unsigned IOCAF4
: 1;
3615 unsigned IOCAF5
: 1;
3627 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
3629 #define _IOCAF0 0x01
3630 #define _IOCAF1 0x02
3631 #define _IOCAF2 0x04
3632 #define _IOCAF3 0x08
3633 #define _IOCAF4 0x10
3634 #define _IOCAF5 0x20
3636 //==============================================================================
3639 //==============================================================================
3642 extern __at(0x0397) __sfr IOCCP
;
3648 unsigned IOCCP0
: 1;
3649 unsigned IOCCP1
: 1;
3650 unsigned IOCCP2
: 1;
3651 unsigned IOCCP3
: 1;
3652 unsigned IOCCP4
: 1;
3653 unsigned IOCCP5
: 1;
3665 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
3667 #define _IOCCP0 0x01
3668 #define _IOCCP1 0x02
3669 #define _IOCCP2 0x04
3670 #define _IOCCP3 0x08
3671 #define _IOCCP4 0x10
3672 #define _IOCCP5 0x20
3674 //==============================================================================
3677 //==============================================================================
3680 extern __at(0x0398) __sfr IOCCN
;
3686 unsigned IOCCN0
: 1;
3687 unsigned IOCCN1
: 1;
3688 unsigned IOCCN2
: 1;
3689 unsigned IOCCN3
: 1;
3690 unsigned IOCCN4
: 1;
3691 unsigned IOCCN5
: 1;
3703 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
3705 #define _IOCCN0 0x01
3706 #define _IOCCN1 0x02
3707 #define _IOCCN2 0x04
3708 #define _IOCCN3 0x08
3709 #define _IOCCN4 0x10
3710 #define _IOCCN5 0x20
3712 //==============================================================================
3715 //==============================================================================
3718 extern __at(0x0399) __sfr IOCCF
;
3724 unsigned IOCCF0
: 1;
3725 unsigned IOCCF1
: 1;
3726 unsigned IOCCF2
: 1;
3727 unsigned IOCCF3
: 1;
3728 unsigned IOCCF4
: 1;
3729 unsigned IOCCF5
: 1;
3741 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
3743 #define _IOCCF0 0x01
3744 #define _IOCCF1 0x02
3745 #define _IOCCF2 0x04
3746 #define _IOCCF3 0x08
3747 #define _IOCCF4 0x10
3748 #define _IOCCF5 0x20
3750 //==============================================================================
3753 //==============================================================================
3756 extern __at(0x039A) __sfr CLKRCON
;
3762 unsigned CLKRDIV0
: 1;
3763 unsigned CLKRDIV1
: 1;
3764 unsigned CLKRDIV2
: 1;
3765 unsigned CLKRDC0
: 1;
3766 unsigned CLKRDC1
: 1;
3769 unsigned CLKREN
: 1;
3774 unsigned CLKRDIV
: 3;
3781 unsigned CLKRDC
: 2;
3786 extern __at(0x039A) volatile __CLKRCONbits_t CLKRCONbits
;
3788 #define _CLKRDIV0 0x01
3789 #define _CLKRDIV1 0x02
3790 #define _CLKRDIV2 0x04
3791 #define _CLKRDC0 0x08
3792 #define _CLKRDC1 0x10
3793 #define _CLKREN 0x80
3795 //==============================================================================
3798 //==============================================================================
3801 extern __at(0x039C) __sfr MDCON
;
3809 unsigned MDOPOL
: 1;
3815 extern __at(0x039C) volatile __MDCONbits_t MDCONbits
;
3819 #define _MDOPOL 0x10
3822 //==============================================================================
3825 //==============================================================================
3828 extern __at(0x039D) __sfr MDSRC
;
3851 extern __at(0x039D) volatile __MDSRCbits_t MDSRCbits
;
3858 //==============================================================================
3861 //==============================================================================
3864 extern __at(0x039E) __sfr MDCARH
;
3875 unsigned MDCHSYNC
: 1;
3876 unsigned MDCHPOL
: 1;
3887 extern __at(0x039E) volatile __MDCARHbits_t MDCARHbits
;
3893 #define _MDCHSYNC 0x20
3894 #define _MDCHPOL 0x40
3896 //==============================================================================
3899 //==============================================================================
3902 extern __at(0x039F) __sfr MDCARL
;
3913 unsigned MDCLSYNC
: 1;
3914 unsigned MDCLPOL
: 1;
3925 extern __at(0x039F) volatile __MDCARLbits_t MDCARLbits
;
3931 #define _MDCLSYNC 0x20
3932 #define _MDCLPOL 0x40
3934 //==============================================================================
3937 //==============================================================================
3940 extern __at(0x040C) __sfr CCDNA
;
3944 unsigned CCDNA0
: 1;
3945 unsigned CCDNA1
: 1;
3946 unsigned CCDNA2
: 1;
3948 unsigned CCDNA4
: 1;
3949 unsigned CCDNA5
: 1;
3954 extern __at(0x040C) volatile __CCDNAbits_t CCDNAbits
;
3956 #define _CCDNA0 0x01
3957 #define _CCDNA1 0x02
3958 #define _CCDNA2 0x04
3959 #define _CCDNA4 0x10
3960 #define _CCDNA5 0x20
3962 //==============================================================================
3965 //==============================================================================
3968 extern __at(0x040E) __sfr CCDNC
;
3974 unsigned CCDNC0
: 1;
3975 unsigned CCDNC1
: 1;
3976 unsigned CCDNC2
: 1;
3977 unsigned CCDNC3
: 1;
3978 unsigned CCDNC4
: 1;
3979 unsigned CCDNC5
: 1;
3991 extern __at(0x040E) volatile __CCDNCbits_t CCDNCbits
;
3993 #define _CCDNC0 0x01
3994 #define _CCDNC1 0x02
3995 #define _CCDNC2 0x04
3996 #define _CCDNC3 0x08
3997 #define _CCDNC4 0x10
3998 #define _CCDNC5 0x20
4000 //==============================================================================
4002 extern __at(0x0411) __sfr TMR3
;
4003 extern __at(0x0411) __sfr TMR3L
;
4004 extern __at(0x0412) __sfr TMR3H
;
4006 //==============================================================================
4009 extern __at(0x0413) __sfr T3CON
;
4015 unsigned TMR3ON
: 1;
4017 unsigned T3SYNC
: 1;
4018 unsigned T3SOSC
: 1;
4019 unsigned T3CKPS0
: 1;
4020 unsigned T3CKPS1
: 1;
4021 unsigned TMR3CS0
: 1;
4022 unsigned TMR3CS1
: 1;
4028 unsigned T3CKPS
: 2;
4035 unsigned TMR3CS
: 2;
4039 extern __at(0x0413) volatile __T3CONbits_t T3CONbits
;
4041 #define _TMR3ON 0x01
4042 #define _T3SYNC 0x04
4043 #define _T3SOSC 0x08
4044 #define _T3CKPS0 0x10
4045 #define _T3CKPS1 0x20
4046 #define _TMR3CS0 0x40
4047 #define _TMR3CS1 0x80
4049 //==============================================================================
4052 //==============================================================================
4055 extern __at(0x0414) __sfr T3GCON
;
4061 unsigned T3GSS0
: 1;
4062 unsigned T3GSS1
: 1;
4063 unsigned T3GVAL
: 1;
4064 unsigned T3GGO_NOT_DONE
: 1;
4065 unsigned T3GSPM
: 1;
4067 unsigned T3GPOL
: 1;
4068 unsigned TMR3GE
: 1;
4078 extern __at(0x0414) volatile __T3GCONbits_t T3GCONbits
;
4080 #define _T3GSS0 0x01
4081 #define _T3GSS1 0x02
4082 #define _T3GVAL 0x04
4083 #define _T3GGO_NOT_DONE 0x08
4084 #define _T3GSPM 0x10
4086 #define _T3GPOL 0x40
4087 #define _TMR3GE 0x80
4089 //==============================================================================
4091 extern __at(0x0415) __sfr TMR4
;
4092 extern __at(0x0416) __sfr PR4
;
4094 //==============================================================================
4097 extern __at(0x0417) __sfr T4CON
;
4103 unsigned T4CKPS0
: 1;
4104 unsigned T4CKPS1
: 1;
4105 unsigned TMR4ON
: 1;
4106 unsigned T4OUTPS0
: 1;
4107 unsigned T4OUTPS1
: 1;
4108 unsigned T4OUTPS2
: 1;
4109 unsigned T4OUTPS3
: 1;
4115 unsigned T4CKPS
: 2;
4122 unsigned T4OUTPS
: 4;
4127 extern __at(0x0417) volatile __T4CONbits_t T4CONbits
;
4129 #define _T4CKPS0 0x01
4130 #define _T4CKPS1 0x02
4131 #define _TMR4ON 0x04
4132 #define _T4OUTPS0 0x08
4133 #define _T4OUTPS1 0x10
4134 #define _T4OUTPS2 0x20
4135 #define _T4OUTPS3 0x40
4137 //==============================================================================
4139 extern __at(0x0418) __sfr TMR5
;
4140 extern __at(0x0418) __sfr TMR5L
;
4141 extern __at(0x0419) __sfr TMR5H
;
4143 //==============================================================================
4146 extern __at(0x041A) __sfr T5CON
;
4152 unsigned TMR5ON
: 1;
4154 unsigned T5SYNC
: 1;
4155 unsigned T5SOSC
: 1;
4156 unsigned T5CKPS0
: 1;
4157 unsigned T5CKPS1
: 1;
4158 unsigned TMR5CS0
: 1;
4159 unsigned TMR5CS1
: 1;
4165 unsigned T5CKPS
: 2;
4172 unsigned TMR5CS
: 2;
4176 extern __at(0x041A) volatile __T5CONbits_t T5CONbits
;
4178 #define _TMR5ON 0x01
4179 #define _T5SYNC 0x04
4180 #define _T5SOSC 0x08
4181 #define _T5CKPS0 0x10
4182 #define _T5CKPS1 0x20
4183 #define _TMR5CS0 0x40
4184 #define _TMR5CS1 0x80
4186 //==============================================================================
4189 //==============================================================================
4192 extern __at(0x041B) __sfr T5GCON
;
4198 unsigned T5GSS0
: 1;
4199 unsigned T5GSS1
: 1;
4200 unsigned T5GVAL
: 1;
4201 unsigned T5GGO_NOT_DONE
: 1;
4202 unsigned T5GSPM
: 1;
4204 unsigned T5GPOL
: 1;
4205 unsigned TMR5GE
: 1;
4215 extern __at(0x041B) volatile __T5GCONbits_t T5GCONbits
;
4217 #define _T5GSS0 0x01
4218 #define _T5GSS1 0x02
4219 #define _T5GVAL 0x04
4220 #define _T5GGO_NOT_DONE 0x08
4221 #define _T5GSPM 0x10
4223 #define _T5GPOL 0x40
4224 #define _TMR5GE 0x80
4226 //==============================================================================
4228 extern __at(0x041C) __sfr TMR6
;
4229 extern __at(0x041D) __sfr PR6
;
4231 //==============================================================================
4234 extern __at(0x041E) __sfr T6CON
;
4240 unsigned T6CKPS0
: 1;
4241 unsigned T6CKPS1
: 1;
4242 unsigned TMR6ON
: 1;
4243 unsigned T6OUTPS0
: 1;
4244 unsigned T6OUTPS1
: 1;
4245 unsigned T6OUTPS2
: 1;
4246 unsigned T6OUTPS3
: 1;
4252 unsigned T6CKPS
: 2;
4259 unsigned T6OUTPS
: 4;
4264 extern __at(0x041E) volatile __T6CONbits_t T6CONbits
;
4266 #define _T6CKPS0 0x01
4267 #define _T6CKPS1 0x02
4268 #define _TMR6ON 0x04
4269 #define _T6OUTPS0 0x08
4270 #define _T6OUTPS1 0x10
4271 #define _T6OUTPS2 0x20
4272 #define _T6OUTPS3 0x40
4274 //==============================================================================
4277 //==============================================================================
4280 extern __at(0x041F) __sfr CCDCON
;
4303 extern __at(0x041F) volatile __CCDCONbits_t CCDCONbits
;
4309 //==============================================================================
4312 //==============================================================================
4315 extern __at(0x048C) __sfr CCDPA
;
4319 unsigned CCDPA0
: 1;
4320 unsigned CCDPA1
: 1;
4321 unsigned CCDPA2
: 1;
4323 unsigned CCDPA4
: 1;
4324 unsigned CCDPA5
: 1;
4329 extern __at(0x048C) volatile __CCDPAbits_t CCDPAbits
;
4331 #define _CCDPA0 0x01
4332 #define _CCDPA1 0x02
4333 #define _CCDPA2 0x04
4334 #define _CCDPA4 0x10
4335 #define _CCDPA5 0x20
4337 //==============================================================================
4340 //==============================================================================
4343 extern __at(0x048E) __sfr CCDPC
;
4349 unsigned CCDPC0
: 1;
4350 unsigned CCDPC1
: 1;
4351 unsigned CCDPC2
: 1;
4352 unsigned CCDPC3
: 1;
4353 unsigned CCDPC4
: 1;
4354 unsigned CCDPC5
: 1;
4366 extern __at(0x048E) volatile __CCDPCbits_t CCDPCbits
;
4368 #define _CCDPC0 0x01
4369 #define _CCDPC1 0x02
4370 #define _CCDPC2 0x04
4371 #define _CCDPC3 0x08
4372 #define _CCDPC4 0x10
4373 #define _CCDPC5 0x20
4375 //==============================================================================
4377 extern __at(0x0498) __sfr NCO1ACC
;
4378 extern __at(0x0498) __sfr NCO1ACCL
;
4379 extern __at(0x0499) __sfr NCO1ACCH
;
4380 extern __at(0x049A) __sfr NCO1ACCU
;
4381 extern __at(0x049B) __sfr NCO1INC
;
4382 extern __at(0x049B) __sfr NCO1INCL
;
4383 extern __at(0x049C) __sfr NCO1INCH
;
4384 extern __at(0x049D) __sfr NCO1INCU
;
4386 //==============================================================================
4389 extern __at(0x049E) __sfr NCO1CON
;
4403 extern __at(0x049E) volatile __NCO1CONbits_t NCO1CONbits
;
4410 //==============================================================================
4412 extern __at(0x049F) __sfr NCO1CLK
;
4414 //==============================================================================
4417 extern __at(0x0617) __sfr PWM5DCL
;
4429 unsigned PWM5DCL0
: 1;
4430 unsigned PWM5DCL1
: 1;
4436 unsigned PWM5DCL
: 2;
4440 extern __at(0x0617) volatile __PWM5DCLbits_t PWM5DCLbits
;
4442 #define _PWM5DCL0 0x40
4443 #define _PWM5DCL1 0x80
4445 //==============================================================================
4448 //==============================================================================
4451 extern __at(0x0618) __sfr PWM5DCH
;
4455 unsigned PWM5DCH0
: 1;
4456 unsigned PWM5DCH1
: 1;
4457 unsigned PWM5DCH2
: 1;
4458 unsigned PWM5DCH3
: 1;
4459 unsigned PWM5DCH4
: 1;
4460 unsigned PWM5DCH5
: 1;
4461 unsigned PWM5DCH6
: 1;
4462 unsigned PWM5DCH7
: 1;
4465 extern __at(0x0618) volatile __PWM5DCHbits_t PWM5DCHbits
;
4467 #define _PWM5DCH0 0x01
4468 #define _PWM5DCH1 0x02
4469 #define _PWM5DCH2 0x04
4470 #define _PWM5DCH3 0x08
4471 #define _PWM5DCH4 0x10
4472 #define _PWM5DCH5 0x20
4473 #define _PWM5DCH6 0x40
4474 #define _PWM5DCH7 0x80
4476 //==============================================================================
4479 //==============================================================================
4482 extern __at(0x0619) __sfr PWM5CON
;
4490 unsigned PWM5POL
: 1;
4491 unsigned PWM5OUT
: 1;
4493 unsigned PWM5EN
: 1;
4496 extern __at(0x0619) volatile __PWM5CONbits_t PWM5CONbits
;
4498 #define _PWM5POL 0x10
4499 #define _PWM5OUT 0x20
4500 #define _PWM5EN 0x80
4502 //==============================================================================
4505 //==============================================================================
4508 extern __at(0x0619) __sfr PWM5CON0
;
4516 unsigned PWM5POL
: 1;
4517 unsigned PWM5OUT
: 1;
4519 unsigned PWM5EN
: 1;
4522 extern __at(0x0619) volatile __PWM5CON0bits_t PWM5CON0bits
;
4524 #define _PWM5CON0_PWM5POL 0x10
4525 #define _PWM5CON0_PWM5OUT 0x20
4526 #define _PWM5CON0_PWM5EN 0x80
4528 //==============================================================================
4531 //==============================================================================
4534 extern __at(0x061A) __sfr PWM6DCL
;
4546 unsigned PWM6DCL0
: 1;
4547 unsigned PWM6DCL1
: 1;
4553 unsigned PWM6DCL
: 2;
4557 extern __at(0x061A) volatile __PWM6DCLbits_t PWM6DCLbits
;
4559 #define _PWM6DCL0 0x40
4560 #define _PWM6DCL1 0x80
4562 //==============================================================================
4565 //==============================================================================
4568 extern __at(0x061B) __sfr PWM6DCH
;
4572 unsigned PWM6DCH0
: 1;
4573 unsigned PWM6DCH1
: 1;
4574 unsigned PWM6DCH2
: 1;
4575 unsigned PWM6DCH3
: 1;
4576 unsigned PWM6DCH4
: 1;
4577 unsigned PWM6DCH5
: 1;
4578 unsigned PWM6DCH6
: 1;
4579 unsigned PWM6DCH7
: 1;
4582 extern __at(0x061B) volatile __PWM6DCHbits_t PWM6DCHbits
;
4584 #define _PWM6DCH0 0x01
4585 #define _PWM6DCH1 0x02
4586 #define _PWM6DCH2 0x04
4587 #define _PWM6DCH3 0x08
4588 #define _PWM6DCH4 0x10
4589 #define _PWM6DCH5 0x20
4590 #define _PWM6DCH6 0x40
4591 #define _PWM6DCH7 0x80
4593 //==============================================================================
4596 //==============================================================================
4599 extern __at(0x061C) __sfr PWM6CON
;
4607 unsigned PWM6POL
: 1;
4608 unsigned PWM6OUT
: 1;
4610 unsigned PWM6EN
: 1;
4613 extern __at(0x061C) volatile __PWM6CONbits_t PWM6CONbits
;
4615 #define _PWM6POL 0x10
4616 #define _PWM6OUT 0x20
4617 #define _PWM6EN 0x80
4619 //==============================================================================
4622 //==============================================================================
4625 extern __at(0x061C) __sfr PWM6CON0
;
4633 unsigned PWM6POL
: 1;
4634 unsigned PWM6OUT
: 1;
4636 unsigned PWM6EN
: 1;
4639 extern __at(0x061C) volatile __PWM6CON0bits_t PWM6CON0bits
;
4641 #define _PWM6CON0_PWM6POL 0x10
4642 #define _PWM6CON0_PWM6OUT 0x20
4643 #define _PWM6CON0_PWM6EN 0x80
4645 //==============================================================================
4648 //==============================================================================
4651 extern __at(0x061F) __sfr PWMTMRS
;
4657 unsigned P5TSEL0
: 1;
4658 unsigned P5TSEL1
: 1;
4659 unsigned P6TSEL0
: 1;
4660 unsigned P6TSEL1
: 1;
4669 unsigned P5TSEL
: 2;
4676 unsigned P6TSEL
: 2;
4681 extern __at(0x061F) volatile __PWMTMRSbits_t PWMTMRSbits
;
4683 #define _P5TSEL0 0x01
4684 #define _P5TSEL1 0x02
4685 #define _P6TSEL0 0x04
4686 #define _P6TSEL1 0x08
4688 //==============================================================================
4691 //==============================================================================
4694 extern __at(0x0691) __sfr CWG1CLKCON
;
4712 unsigned CWG1CS
: 1;
4721 } __CWG1CLKCONbits_t
;
4723 extern __at(0x0691) volatile __CWG1CLKCONbits_t CWG1CLKCONbits
;
4726 #define _CWG1CS 0x01
4728 //==============================================================================
4731 //==============================================================================
4734 extern __at(0x0692) __sfr CWG1DAT
;
4740 unsigned CWG1DAT0
: 1;
4741 unsigned CWG1DAT1
: 1;
4742 unsigned CWG1DAT2
: 1;
4743 unsigned CWG1DAT3
: 1;
4752 unsigned CWG1DAT
: 4;
4757 extern __at(0x0692) volatile __CWG1DATbits_t CWG1DATbits
;
4759 #define _CWG1DAT0 0x01
4760 #define _CWG1DAT1 0x02
4761 #define _CWG1DAT2 0x04
4762 #define _CWG1DAT3 0x08
4764 //==============================================================================
4767 //==============================================================================
4770 extern __at(0x0693) __sfr CWG1DBR
;
4788 unsigned CWG1DBR0
: 1;
4789 unsigned CWG1DBR1
: 1;
4790 unsigned CWG1DBR2
: 1;
4791 unsigned CWG1DBR3
: 1;
4792 unsigned CWG1DBR4
: 1;
4793 unsigned CWG1DBR5
: 1;
4806 unsigned CWG1DBR
: 6;
4811 extern __at(0x0693) volatile __CWG1DBRbits_t CWG1DBRbits
;
4814 #define _CWG1DBR0 0x01
4816 #define _CWG1DBR1 0x02
4818 #define _CWG1DBR2 0x04
4820 #define _CWG1DBR3 0x08
4822 #define _CWG1DBR4 0x10
4824 #define _CWG1DBR5 0x20
4826 //==============================================================================
4829 //==============================================================================
4832 extern __at(0x0694) __sfr CWG1DBF
;
4850 unsigned CWG1DBF0
: 1;
4851 unsigned CWG1DBF1
: 1;
4852 unsigned CWG1DBF2
: 1;
4853 unsigned CWG1DBF3
: 1;
4854 unsigned CWG1DBF4
: 1;
4855 unsigned CWG1DBF5
: 1;
4868 unsigned CWG1DBF
: 6;
4873 extern __at(0x0694) volatile __CWG1DBFbits_t CWG1DBFbits
;
4876 #define _CWG1DBF0 0x01
4878 #define _CWG1DBF1 0x02
4880 #define _CWG1DBF2 0x04
4882 #define _CWG1DBF3 0x08
4884 #define _CWG1DBF4 0x10
4886 #define _CWG1DBF5 0x20
4888 //==============================================================================
4891 //==============================================================================
4894 extern __at(0x0695) __sfr CWG1CON0
;
4912 unsigned CWG1MODE0
: 1;
4913 unsigned CWG1MODE1
: 1;
4914 unsigned CWG1MODE2
: 1;
4918 unsigned CWG1LD
: 1;
4931 unsigned CWG1EN
: 1;
4936 unsigned CWG1MODE
: 3;
4947 extern __at(0x0695) volatile __CWG1CON0bits_t CWG1CON0bits
;
4949 #define _CWG1CON0_MODE0 0x01
4950 #define _CWG1CON0_CWG1MODE0 0x01
4951 #define _CWG1CON0_MODE1 0x02
4952 #define _CWG1CON0_CWG1MODE1 0x02
4953 #define _CWG1CON0_MODE2 0x04
4954 #define _CWG1CON0_CWG1MODE2 0x04
4955 #define _CWG1CON0_LD 0x40
4956 #define _CWG1CON0_CWG1LD 0x40
4957 #define _CWG1CON0_EN 0x80
4958 #define _CWG1CON0_G1EN 0x80
4959 #define _CWG1CON0_CWG1EN 0x80
4961 //==============================================================================
4964 //==============================================================================
4967 extern __at(0x0696) __sfr CWG1CON1
;
4985 unsigned CWG1POLA
: 1;
4986 unsigned CWG1POLB
: 1;
4987 unsigned CWG1POLC
: 1;
4988 unsigned CWG1POLD
: 1;
4990 unsigned CWG1IN
: 1;
4996 extern __at(0x0696) volatile __CWG1CON1bits_t CWG1CON1bits
;
4999 #define _CWG1POLA 0x01
5001 #define _CWG1POLB 0x02
5003 #define _CWG1POLC 0x04
5005 #define _CWG1POLD 0x08
5007 #define _CWG1IN 0x20
5009 //==============================================================================
5012 //==============================================================================
5015 extern __at(0x0697) __sfr CWG1AS0
;
5028 unsigned SHUTDOWN
: 1;
5035 unsigned CWG1LSAC0
: 1;
5036 unsigned CWG1LSAC1
: 1;
5037 unsigned CWG1LSBD0
: 1;
5038 unsigned CWG1LSBD1
: 1;
5039 unsigned CWG1REN
: 1;
5040 unsigned CWG1SHUTDOWN
: 1;
5046 unsigned CWG1LSAC
: 2;
5060 unsigned CWG1LSBD
: 2;
5072 extern __at(0x0697) volatile __CWG1AS0bits_t CWG1AS0bits
;
5075 #define _CWG1LSAC0 0x04
5077 #define _CWG1LSAC1 0x08
5079 #define _CWG1LSBD0 0x10
5081 #define _CWG1LSBD1 0x20
5083 #define _CWG1REN 0x40
5084 #define _SHUTDOWN 0x80
5085 #define _CWG1SHUTDOWN 0x80
5087 //==============================================================================
5090 //==============================================================================
5093 extern __at(0x0698) __sfr CWG1AS1
;
5107 extern __at(0x0698) volatile __CWG1AS1bits_t CWG1AS1bits
;
5115 //==============================================================================
5118 //==============================================================================
5121 extern __at(0x0699) __sfr CWG1STR
;
5139 unsigned CWG1STRA
: 1;
5140 unsigned CWG1STRB
: 1;
5141 unsigned CWG1STRC
: 1;
5142 unsigned CWG1STRD
: 1;
5143 unsigned CWG1OVRA
: 1;
5144 unsigned CWG1OVRB
: 1;
5145 unsigned CWG1OVRC
: 1;
5146 unsigned CWG1OVRD
: 1;
5150 extern __at(0x0699) volatile __CWG1STRbits_t CWG1STRbits
;
5153 #define _CWG1STRA 0x01
5155 #define _CWG1STRB 0x02
5157 #define _CWG1STRC 0x04
5159 #define _CWG1STRD 0x08
5161 #define _CWG1OVRA 0x10
5163 #define _CWG1OVRB 0x20
5165 #define _CWG1OVRC 0x40
5167 #define _CWG1OVRD 0x80
5169 //==============================================================================
5172 //==============================================================================
5175 extern __at(0x0711) __sfr CWG2CLKCON
;
5193 unsigned CWG2CS
: 1;
5202 } __CWG2CLKCONbits_t
;
5204 extern __at(0x0711) volatile __CWG2CLKCONbits_t CWG2CLKCONbits
;
5206 #define _CWG2CLKCON_CS 0x01
5207 #define _CWG2CLKCON_CWG2CS 0x01
5209 //==============================================================================
5212 //==============================================================================
5215 extern __at(0x0712) __sfr CWG2DAT
;
5221 unsigned CWG2DAT0
: 1;
5222 unsigned CWG2DAT1
: 1;
5223 unsigned CWG2DAT2
: 1;
5224 unsigned CWG2DAT3
: 1;
5233 unsigned CWG2DAT
: 4;
5238 extern __at(0x0712) volatile __CWG2DATbits_t CWG2DATbits
;
5240 #define _CWG2DAT0 0x01
5241 #define _CWG2DAT1 0x02
5242 #define _CWG2DAT2 0x04
5243 #define _CWG2DAT3 0x08
5245 //==============================================================================
5248 //==============================================================================
5251 extern __at(0x0713) __sfr CWG2DBR
;
5269 unsigned CWG2DBR0
: 1;
5270 unsigned CWG2DBR1
: 1;
5271 unsigned CWG2DBR2
: 1;
5272 unsigned CWG2DBR3
: 1;
5273 unsigned CWG2DBR4
: 1;
5274 unsigned CWG2DBR5
: 1;
5287 unsigned CWG2DBR
: 6;
5292 extern __at(0x0713) volatile __CWG2DBRbits_t CWG2DBRbits
;
5294 #define _CWG2DBR_DBR0 0x01
5295 #define _CWG2DBR_CWG2DBR0 0x01
5296 #define _CWG2DBR_DBR1 0x02
5297 #define _CWG2DBR_CWG2DBR1 0x02
5298 #define _CWG2DBR_DBR2 0x04
5299 #define _CWG2DBR_CWG2DBR2 0x04
5300 #define _CWG2DBR_DBR3 0x08
5301 #define _CWG2DBR_CWG2DBR3 0x08
5302 #define _CWG2DBR_DBR4 0x10
5303 #define _CWG2DBR_CWG2DBR4 0x10
5304 #define _CWG2DBR_DBR5 0x20
5305 #define _CWG2DBR_CWG2DBR5 0x20
5307 //==============================================================================
5310 //==============================================================================
5313 extern __at(0x0714) __sfr CWG2DBF
;
5331 unsigned CWG2DBF0
: 1;
5332 unsigned CWG2DBF1
: 1;
5333 unsigned CWG2DBF2
: 1;
5334 unsigned CWG2DBF3
: 1;
5335 unsigned CWG2DBF4
: 1;
5336 unsigned CWG2DBF5
: 1;
5343 unsigned CWG2DBF
: 6;
5354 extern __at(0x0714) volatile __CWG2DBFbits_t CWG2DBFbits
;
5356 #define _CWG2DBF_DBF0 0x01
5357 #define _CWG2DBF_CWG2DBF0 0x01
5358 #define _CWG2DBF_DBF1 0x02
5359 #define _CWG2DBF_CWG2DBF1 0x02
5360 #define _CWG2DBF_DBF2 0x04
5361 #define _CWG2DBF_CWG2DBF2 0x04
5362 #define _CWG2DBF_DBF3 0x08
5363 #define _CWG2DBF_CWG2DBF3 0x08
5364 #define _CWG2DBF_DBF4 0x10
5365 #define _CWG2DBF_CWG2DBF4 0x10
5366 #define _CWG2DBF_DBF5 0x20
5367 #define _CWG2DBF_CWG2DBF5 0x20
5369 //==============================================================================
5372 //==============================================================================
5375 extern __at(0x0715) __sfr CWG2CON0
;
5393 unsigned CWG2MODE0
: 1;
5394 unsigned CWG2MODE1
: 1;
5395 unsigned CWG2MODE2
: 1;
5399 unsigned CWG2LD
: 1;
5412 unsigned CWG2EN
: 1;
5417 unsigned CWG2MODE
: 3;
5428 extern __at(0x0715) volatile __CWG2CON0bits_t CWG2CON0bits
;
5430 #define _CWG2CON0_MODE0 0x01
5431 #define _CWG2CON0_CWG2MODE0 0x01
5432 #define _CWG2CON0_MODE1 0x02
5433 #define _CWG2CON0_CWG2MODE1 0x02
5434 #define _CWG2CON0_MODE2 0x04
5435 #define _CWG2CON0_CWG2MODE2 0x04
5436 #define _CWG2CON0_LD 0x40
5437 #define _CWG2CON0_CWG2LD 0x40
5438 #define _CWG2CON0_EN 0x80
5439 #define _CWG2CON0_G2EN 0x80
5440 #define _CWG2CON0_CWG2EN 0x80
5442 //==============================================================================
5445 //==============================================================================
5448 extern __at(0x0716) __sfr CWG2CON1
;
5466 unsigned CWG2POLA
: 1;
5467 unsigned CWG2POLB
: 1;
5468 unsigned CWG2POLC
: 1;
5469 unsigned CWG2POLD
: 1;
5471 unsigned CWG2IN
: 1;
5477 extern __at(0x0716) volatile __CWG2CON1bits_t CWG2CON1bits
;
5479 #define _CWG2CON1_POLA 0x01
5480 #define _CWG2CON1_CWG2POLA 0x01
5481 #define _CWG2CON1_POLB 0x02
5482 #define _CWG2CON1_CWG2POLB 0x02
5483 #define _CWG2CON1_POLC 0x04
5484 #define _CWG2CON1_CWG2POLC 0x04
5485 #define _CWG2CON1_POLD 0x08
5486 #define _CWG2CON1_CWG2POLD 0x08
5487 #define _CWG2CON1_IN 0x20
5488 #define _CWG2CON1_CWG2IN 0x20
5490 //==============================================================================
5493 //==============================================================================
5496 extern __at(0x0717) __sfr CWG2AS0
;
5509 unsigned SHUTDOWN
: 1;
5516 unsigned CWG2LSAC0
: 1;
5517 unsigned CWG2LSAC1
: 1;
5518 unsigned CWG2LSBD0
: 1;
5519 unsigned CWG2LSBD1
: 1;
5520 unsigned CWG2REN
: 1;
5521 unsigned CWG2SHUTDOWN
: 1;
5534 unsigned CWG2LSAC
: 2;
5541 unsigned CWG2LSBD
: 2;
5553 extern __at(0x0717) volatile __CWG2AS0bits_t CWG2AS0bits
;
5555 #define _CWG2AS0_LSAC0 0x04
5556 #define _CWG2AS0_CWG2LSAC0 0x04
5557 #define _CWG2AS0_LSAC1 0x08
5558 #define _CWG2AS0_CWG2LSAC1 0x08
5559 #define _CWG2AS0_LSBD0 0x10
5560 #define _CWG2AS0_CWG2LSBD0 0x10
5561 #define _CWG2AS0_LSBD1 0x20
5562 #define _CWG2AS0_CWG2LSBD1 0x20
5563 #define _CWG2AS0_REN 0x40
5564 #define _CWG2AS0_CWG2REN 0x40
5565 #define _CWG2AS0_SHUTDOWN 0x80
5566 #define _CWG2AS0_CWG2SHUTDOWN 0x80
5568 //==============================================================================
5571 //==============================================================================
5574 extern __at(0x0718) __sfr CWG2AS1
;
5588 extern __at(0x0718) volatile __CWG2AS1bits_t CWG2AS1bits
;
5590 #define _CWG2AS1_AS0E 0x01
5591 #define _CWG2AS1_AS1E 0x02
5592 #define _CWG2AS1_AS2E 0x04
5593 #define _CWG2AS1_AS3E 0x08
5594 #define _CWG2AS1_AS4E 0x10
5596 //==============================================================================
5599 //==============================================================================
5602 extern __at(0x0719) __sfr CWG2STR
;
5620 unsigned CWG2STRA
: 1;
5621 unsigned CWG2STRB
: 1;
5622 unsigned CWG2STRC
: 1;
5623 unsigned CWG2STRD
: 1;
5624 unsigned CWG2OVRA
: 1;
5625 unsigned CWG2OVRB
: 1;
5626 unsigned CWG2OVRC
: 1;
5627 unsigned CWG2OVRD
: 1;
5631 extern __at(0x0719) volatile __CWG2STRbits_t CWG2STRbits
;
5633 #define _CWG2STR_STRA 0x01
5634 #define _CWG2STR_CWG2STRA 0x01
5635 #define _CWG2STR_STRB 0x02
5636 #define _CWG2STR_CWG2STRB 0x02
5637 #define _CWG2STR_STRC 0x04
5638 #define _CWG2STR_CWG2STRC 0x04
5639 #define _CWG2STR_STRD 0x08
5640 #define _CWG2STR_CWG2STRD 0x08
5641 #define _CWG2STR_OVRA 0x10
5642 #define _CWG2STR_CWG2OVRA 0x10
5643 #define _CWG2STR_OVRB 0x20
5644 #define _CWG2STR_CWG2OVRB 0x20
5645 #define _CWG2STR_OVRC 0x40
5646 #define _CWG2STR_CWG2OVRC 0x40
5647 #define _CWG2STR_OVRD 0x80
5648 #define _CWG2STR_CWG2OVRD 0x80
5650 //==============================================================================
5652 extern __at(0x0891) __sfr NVMADR
;
5654 //==============================================================================
5657 extern __at(0x0891) __sfr NVMADRL
;
5661 unsigned NVMADR0
: 1;
5662 unsigned NVMADR1
: 1;
5663 unsigned NVMADR2
: 1;
5664 unsigned NVMADR3
: 1;
5665 unsigned NVMADR4
: 1;
5666 unsigned NVMADR5
: 1;
5667 unsigned NVMADR6
: 1;
5668 unsigned NVMADR7
: 1;
5671 extern __at(0x0891) volatile __NVMADRLbits_t NVMADRLbits
;
5673 #define _NVMADR0 0x01
5674 #define _NVMADR1 0x02
5675 #define _NVMADR2 0x04
5676 #define _NVMADR3 0x08
5677 #define _NVMADR4 0x10
5678 #define _NVMADR5 0x20
5679 #define _NVMADR6 0x40
5680 #define _NVMADR7 0x80
5682 //==============================================================================
5685 //==============================================================================
5688 extern __at(0x0892) __sfr NVMADRH
;
5692 unsigned NVMADR8
: 1;
5693 unsigned NVMADR9
: 1;
5694 unsigned NVMADR10
: 1;
5695 unsigned NVMADR11
: 1;
5696 unsigned NVMADR12
: 1;
5697 unsigned NVMADR13
: 1;
5698 unsigned NVMADR14
: 1;
5702 extern __at(0x0892) volatile __NVMADRHbits_t NVMADRHbits
;
5704 #define _NVMADR8 0x01
5705 #define _NVMADR9 0x02
5706 #define _NVMADR10 0x04
5707 #define _NVMADR11 0x08
5708 #define _NVMADR12 0x10
5709 #define _NVMADR13 0x20
5710 #define _NVMADR14 0x40
5712 //==============================================================================
5714 extern __at(0x0893) __sfr NVMDAT
;
5716 //==============================================================================
5719 extern __at(0x0893) __sfr NVMDATL
;
5723 unsigned NVMDAT0
: 1;
5724 unsigned NVMDAT1
: 1;
5725 unsigned NVMDAT2
: 1;
5726 unsigned NVMDAT3
: 1;
5727 unsigned NVMDAT4
: 1;
5728 unsigned NVMDAT5
: 1;
5729 unsigned NVMDAT6
: 1;
5730 unsigned NVMDAT7
: 1;
5733 extern __at(0x0893) volatile __NVMDATLbits_t NVMDATLbits
;
5735 #define _NVMDAT0 0x01
5736 #define _NVMDAT1 0x02
5737 #define _NVMDAT2 0x04
5738 #define _NVMDAT3 0x08
5739 #define _NVMDAT4 0x10
5740 #define _NVMDAT5 0x20
5741 #define _NVMDAT6 0x40
5742 #define _NVMDAT7 0x80
5744 //==============================================================================
5747 //==============================================================================
5750 extern __at(0x0894) __sfr NVMDATH
;
5754 unsigned NVMDAT8
: 1;
5755 unsigned NVMDAT9
: 1;
5756 unsigned NVMDAT10
: 1;
5757 unsigned NVMDAT11
: 1;
5758 unsigned NVMDAT12
: 1;
5759 unsigned NVMDAT13
: 1;
5764 extern __at(0x0894) volatile __NVMDATHbits_t NVMDATHbits
;
5766 #define _NVMDAT8 0x01
5767 #define _NVMDAT9 0x02
5768 #define _NVMDAT10 0x04
5769 #define _NVMDAT11 0x08
5770 #define _NVMDAT12 0x10
5771 #define _NVMDAT13 0x20
5773 //==============================================================================
5776 //==============================================================================
5779 extern __at(0x0895) __sfr NVMCON1
;
5789 unsigned NVMREGS
: 1;
5793 extern __at(0x0895) volatile __NVMCON1bits_t NVMCON1bits
;
5801 #define _NVMREGS 0x40
5803 //==============================================================================
5805 extern __at(0x0896) __sfr NVMCON2
;
5807 //==============================================================================
5810 extern __at(0x089B) __sfr PCON0
;
5814 unsigned NOT_BOR
: 1;
5815 unsigned NOT_POR
: 1;
5816 unsigned NOT_RI
: 1;
5817 unsigned NOT_RMCLR
: 1;
5818 unsigned NOT_RWDT
: 1;
5820 unsigned STKUNF
: 1;
5821 unsigned STKOVF
: 1;
5824 extern __at(0x089B) volatile __PCON0bits_t PCON0bits
;
5826 #define _NOT_BOR 0x01
5827 #define _NOT_POR 0x02
5828 #define _NOT_RI 0x04
5829 #define _NOT_RMCLR 0x08
5830 #define _NOT_RWDT 0x10
5831 #define _STKUNF 0x40
5832 #define _STKOVF 0x80
5834 //==============================================================================
5837 //==============================================================================
5840 extern __at(0x0911) __sfr PMD0
;
5845 unsigned CLKRMD
: 1;
5851 unsigned SYSCMD
: 1;
5854 extern __at(0x0911) volatile __PMD0bits_t PMD0bits
;
5857 #define _CLKRMD 0x02
5860 #define _SYSCMD 0x80
5862 //==============================================================================
5865 //==============================================================================
5868 extern __at(0x0912) __sfr PMD1
;
5872 unsigned TMR0MD
: 1;
5873 unsigned TMR1MD
: 1;
5874 unsigned TMR2MD
: 1;
5875 unsigned TMR3MD
: 1;
5876 unsigned TMR4MD
: 1;
5877 unsigned TMR5MD
: 1;
5878 unsigned TMR6MD
: 1;
5882 extern __at(0x0912) volatile __PMD1bits_t PMD1bits
;
5884 #define _TMR0MD 0x01
5885 #define _TMR1MD 0x02
5886 #define _TMR2MD 0x04
5887 #define _TMR3MD 0x08
5888 #define _TMR4MD 0x10
5889 #define _TMR5MD 0x20
5890 #define _TMR6MD 0x40
5893 //==============================================================================
5896 //==============================================================================
5899 extern __at(0x0913) __sfr PMD2
;
5904 unsigned CMP1MD
: 1;
5905 unsigned CMP2MD
: 1;
5913 extern __at(0x0913) volatile __PMD2bits_t PMD2bits
;
5915 #define _CMP1MD 0x02
5916 #define _CMP2MD 0x04
5920 //==============================================================================
5923 //==============================================================================
5926 extern __at(0x0914) __sfr PMD3
;
5930 unsigned CCP1MD
: 1;
5931 unsigned CCP2MD
: 1;
5932 unsigned CCP3MD
: 1;
5933 unsigned CCP4MD
: 1;
5934 unsigned PWM5MD
: 1;
5935 unsigned PWM6MD
: 1;
5936 unsigned CWG1MD
: 1;
5937 unsigned CWG2MD
: 1;
5940 extern __at(0x0914) volatile __PMD3bits_t PMD3bits
;
5942 #define _CCP1MD 0x01
5943 #define _CCP2MD 0x02
5944 #define _CCP3MD 0x04
5945 #define _CCP4MD 0x08
5946 #define _PWM5MD 0x10
5947 #define _PWM6MD 0x20
5948 #define _CWG1MD 0x40
5949 #define _CWG2MD 0x80
5951 //==============================================================================
5954 //==============================================================================
5957 extern __at(0x0915) __sfr PMD4
;
5962 unsigned MSSP1MD
: 1;
5966 unsigned UART1MD
: 1;
5971 extern __at(0x0915) volatile __PMD4bits_t PMD4bits
;
5973 #define _MSSP1MD 0x02
5974 #define _UART1MD 0x20
5976 //==============================================================================
5979 //==============================================================================
5982 extern __at(0x0916) __sfr PMD5
;
5987 unsigned CLC1MD
: 1;
5988 unsigned CLC2MD
: 1;
5989 unsigned CLC3MD
: 1;
5990 unsigned CLC4MD
: 1;
5996 extern __at(0x0916) volatile __PMD5bits_t PMD5bits
;
5999 #define _CLC1MD 0x02
6000 #define _CLC2MD 0x04
6001 #define _CLC3MD 0x08
6002 #define _CLC4MD 0x10
6004 //==============================================================================
6007 //==============================================================================
6010 extern __at(0x0918) __sfr CPUDOZE
;
6033 extern __at(0x0918) volatile __CPUDOZEbits_t CPUDOZEbits
;
6043 //==============================================================================
6046 //==============================================================================
6049 extern __at(0x0919) __sfr OSCCON1
;
6079 extern __at(0x0919) volatile __OSCCON1bits_t OSCCON1bits
;
6089 //==============================================================================
6092 //==============================================================================
6095 extern __at(0x091A) __sfr OSCCON2
;
6125 extern __at(0x091A) volatile __OSCCON2bits_t OSCCON2bits
;
6135 //==============================================================================
6138 //==============================================================================
6141 extern __at(0x091B) __sfr OSCCON3
;
6150 unsigned SOSCBE
: 1;
6151 unsigned SOSCPWR
: 1;
6152 unsigned CSWHOLD
: 1;
6155 extern __at(0x091B) volatile __OSCCON3bits_t OSCCON3bits
;
6159 #define _SOSCBE 0x20
6160 #define _SOSCPWR 0x40
6161 #define _CSWHOLD 0x80
6163 //==============================================================================
6166 //==============================================================================
6169 extern __at(0x091C) __sfr OSCSTAT1
;
6183 extern __at(0x091C) volatile __OSCSTAT1bits_t OSCSTAT1bits
;
6192 //==============================================================================
6195 //==============================================================================
6198 extern __at(0x091D) __sfr OSCEN
;
6205 unsigned SOSCEN
: 1;
6209 unsigned EXTOEN
: 1;
6212 extern __at(0x091D) volatile __OSCENbits_t OSCENbits
;
6215 #define _SOSCEN 0x08
6218 #define _EXTOEN 0x80
6220 //==============================================================================
6223 //==============================================================================
6226 extern __at(0x091E) __sfr OSCTUNE
;
6232 unsigned HFTUN0
: 1;
6233 unsigned HFTUN1
: 1;
6234 unsigned HFTUN2
: 1;
6235 unsigned HFTUN3
: 1;
6236 unsigned HFTUN4
: 1;
6237 unsigned HFTUN5
: 1;
6249 extern __at(0x091E) volatile __OSCTUNEbits_t OSCTUNEbits
;
6251 #define _HFTUN0 0x01
6252 #define _HFTUN1 0x02
6253 #define _HFTUN2 0x04
6254 #define _HFTUN3 0x08
6255 #define _HFTUN4 0x10
6256 #define _HFTUN5 0x20
6258 //==============================================================================
6261 //==============================================================================
6264 extern __at(0x091F) __sfr OSCFRQ
;
6270 unsigned HFFRQ0
: 1;
6271 unsigned HFFRQ1
: 1;
6272 unsigned HFFRQ2
: 1;
6273 unsigned HFFRQ3
: 1;
6287 extern __at(0x091F) volatile __OSCFRQbits_t OSCFRQbits
;
6289 #define _HFFRQ0 0x01
6290 #define _HFFRQ1 0x02
6291 #define _HFFRQ2 0x04
6292 #define _HFFRQ3 0x08
6294 //==============================================================================
6297 //==============================================================================
6300 extern __at(0x0E0F) __sfr PPSLOCK
;
6304 unsigned PPSLOCKED
: 1;
6314 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
6316 #define _PPSLOCKED 0x01
6318 //==============================================================================
6321 //==============================================================================
6324 extern __at(0x0E10) __sfr INTPPS
;
6330 unsigned INTPPS0
: 1;
6331 unsigned INTPPS1
: 1;
6332 unsigned INTPPS2
: 1;
6333 unsigned INTPPS3
: 1;
6334 unsigned INTPPS4
: 1;
6342 unsigned INTPPS
: 5;
6347 extern __at(0x0E10) volatile __INTPPSbits_t INTPPSbits
;
6349 #define _INTPPS0 0x01
6350 #define _INTPPS1 0x02
6351 #define _INTPPS2 0x04
6352 #define _INTPPS3 0x08
6353 #define _INTPPS4 0x10
6355 //==============================================================================
6358 //==============================================================================
6361 extern __at(0x0E11) __sfr T0CKIPPS
;
6367 unsigned T0CKIPPS0
: 1;
6368 unsigned T0CKIPPS1
: 1;
6369 unsigned T0CKIPPS2
: 1;
6370 unsigned T0CKIPPS3
: 1;
6371 unsigned T0CKIPPS4
: 1;
6379 unsigned T0CKIPPS
: 5;
6384 extern __at(0x0E11) volatile __T0CKIPPSbits_t T0CKIPPSbits
;
6386 #define _T0CKIPPS0 0x01
6387 #define _T0CKIPPS1 0x02
6388 #define _T0CKIPPS2 0x04
6389 #define _T0CKIPPS3 0x08
6390 #define _T0CKIPPS4 0x10
6392 //==============================================================================
6395 //==============================================================================
6398 extern __at(0x0E12) __sfr T1CKIPPS
;
6404 unsigned T1CKIPPS0
: 1;
6405 unsigned T1CKIPPS1
: 1;
6406 unsigned T1CKIPPS2
: 1;
6407 unsigned T1CKIPPS3
: 1;
6408 unsigned T1CKIPPS4
: 1;
6416 unsigned T1CKIPPS
: 5;
6421 extern __at(0x0E12) volatile __T1CKIPPSbits_t T1CKIPPSbits
;
6423 #define _T1CKIPPS0 0x01
6424 #define _T1CKIPPS1 0x02
6425 #define _T1CKIPPS2 0x04
6426 #define _T1CKIPPS3 0x08
6427 #define _T1CKIPPS4 0x10
6429 //==============================================================================
6432 //==============================================================================
6435 extern __at(0x0E13) __sfr T1GPPS
;
6441 unsigned T1GPPS0
: 1;
6442 unsigned T1GPPS1
: 1;
6443 unsigned T1GPPS2
: 1;
6444 unsigned T1GPPS3
: 1;
6445 unsigned T1GPPS4
: 1;
6453 unsigned T1GPPS
: 5;
6458 extern __at(0x0E13) volatile __T1GPPSbits_t T1GPPSbits
;
6460 #define _T1GPPS0 0x01
6461 #define _T1GPPS1 0x02
6462 #define _T1GPPS2 0x04
6463 #define _T1GPPS3 0x08
6464 #define _T1GPPS4 0x10
6466 //==============================================================================
6469 //==============================================================================
6472 extern __at(0x0E14) __sfr CCP1PPS
;
6478 unsigned CCP1PPS0
: 1;
6479 unsigned CCP1PPS1
: 1;
6480 unsigned CCP1PPS2
: 1;
6481 unsigned CCP1PPS3
: 1;
6482 unsigned CCP1PPS4
: 1;
6490 unsigned CCP1PPS
: 5;
6495 extern __at(0x0E14) volatile __CCP1PPSbits_t CCP1PPSbits
;
6497 #define _CCP1PPS0 0x01
6498 #define _CCP1PPS1 0x02
6499 #define _CCP1PPS2 0x04
6500 #define _CCP1PPS3 0x08
6501 #define _CCP1PPS4 0x10
6503 //==============================================================================
6506 //==============================================================================
6509 extern __at(0x0E15) __sfr CCP2PPS
;
6515 unsigned CCP2PPS0
: 1;
6516 unsigned CCP2PPS1
: 1;
6517 unsigned CCP2PPS2
: 1;
6518 unsigned CCP2PPS3
: 1;
6519 unsigned CCP2PPS4
: 1;
6527 unsigned CCP2PPS
: 5;
6532 extern __at(0x0E15) volatile __CCP2PPSbits_t CCP2PPSbits
;
6534 #define _CCP2PPS0 0x01
6535 #define _CCP2PPS1 0x02
6536 #define _CCP2PPS2 0x04
6537 #define _CCP2PPS3 0x08
6538 #define _CCP2PPS4 0x10
6540 //==============================================================================
6543 //==============================================================================
6546 extern __at(0x0E16) __sfr CCP3PPS
;
6552 unsigned CCP3PPS0
: 1;
6553 unsigned CCP3PPS1
: 1;
6554 unsigned CCP3PPS2
: 1;
6555 unsigned CCP3PPS3
: 1;
6556 unsigned CCP3PPS4
: 1;
6564 unsigned CCP3PPS
: 5;
6569 extern __at(0x0E16) volatile __CCP3PPSbits_t CCP3PPSbits
;
6571 #define _CCP3PPS0 0x01
6572 #define _CCP3PPS1 0x02
6573 #define _CCP3PPS2 0x04
6574 #define _CCP3PPS3 0x08
6575 #define _CCP3PPS4 0x10
6577 //==============================================================================
6580 //==============================================================================
6583 extern __at(0x0E17) __sfr CCP4PPS
;
6589 unsigned CCP4PPS0
: 1;
6590 unsigned CCP4PPS1
: 1;
6591 unsigned CCP4PPS2
: 1;
6592 unsigned CCP4PPS3
: 1;
6593 unsigned CCP4PPS4
: 1;
6601 unsigned CCP4PPS
: 5;
6606 extern __at(0x0E17) volatile __CCP4PPSbits_t CCP4PPSbits
;
6608 #define _CCP4PPS0 0x01
6609 #define _CCP4PPS1 0x02
6610 #define _CCP4PPS2 0x04
6611 #define _CCP4PPS3 0x08
6612 #define _CCP4PPS4 0x10
6614 //==============================================================================
6617 //==============================================================================
6620 extern __at(0x0E18) __sfr CWG1PPS
;
6626 unsigned CWG1PPS0
: 1;
6627 unsigned CWG1PPS1
: 1;
6628 unsigned CWG1PPS2
: 1;
6629 unsigned CWG1PPS3
: 1;
6630 unsigned CWG1PPS4
: 1;
6638 unsigned CWG1PPS
: 5;
6643 extern __at(0x0E18) volatile __CWG1PPSbits_t CWG1PPSbits
;
6645 #define _CWG1PPS0 0x01
6646 #define _CWG1PPS1 0x02
6647 #define _CWG1PPS2 0x04
6648 #define _CWG1PPS3 0x08
6649 #define _CWG1PPS4 0x10
6651 //==============================================================================
6654 //==============================================================================
6657 extern __at(0x0E19) __sfr CWG2PPS
;
6663 unsigned CWG2PPS0
: 1;
6664 unsigned CWG2PPS1
: 1;
6665 unsigned CWG2PPS2
: 1;
6666 unsigned CWG2PPS3
: 1;
6667 unsigned CWG2PPS4
: 1;
6675 unsigned CWG2PPS
: 5;
6680 extern __at(0x0E19) volatile __CWG2PPSbits_t CWG2PPSbits
;
6682 #define _CWG2PPS0 0x01
6683 #define _CWG2PPS1 0x02
6684 #define _CWG2PPS2 0x04
6685 #define _CWG2PPS3 0x08
6686 #define _CWG2PPS4 0x10
6688 //==============================================================================
6691 //==============================================================================
6694 extern __at(0x0E1A) __sfr MDCIN1PPS
;
6700 unsigned MDCIN1PPS0
: 1;
6701 unsigned MDCIN1PPS1
: 1;
6702 unsigned MDCIN1PPS2
: 1;
6703 unsigned MDCIN1PPS3
: 1;
6704 unsigned MDCIN1PPS4
: 1;
6712 unsigned MDCIN1PPS
: 5;
6715 } __MDCIN1PPSbits_t
;
6717 extern __at(0x0E1A) volatile __MDCIN1PPSbits_t MDCIN1PPSbits
;
6719 #define _MDCIN1PPS0 0x01
6720 #define _MDCIN1PPS1 0x02
6721 #define _MDCIN1PPS2 0x04
6722 #define _MDCIN1PPS3 0x08
6723 #define _MDCIN1PPS4 0x10
6725 //==============================================================================
6728 //==============================================================================
6731 extern __at(0x0E1B) __sfr MDCIN2PPS
;
6737 unsigned MDCIN2PPS0
: 1;
6738 unsigned MDCIN2PPS1
: 1;
6739 unsigned MDCIN2PPS2
: 1;
6740 unsigned MDCIN2PPS3
: 1;
6741 unsigned MDCIN2PPS4
: 1;
6749 unsigned MDCIN2PPS
: 5;
6752 } __MDCIN2PPSbits_t
;
6754 extern __at(0x0E1B) volatile __MDCIN2PPSbits_t MDCIN2PPSbits
;
6756 #define _MDCIN2PPS0 0x01
6757 #define _MDCIN2PPS1 0x02
6758 #define _MDCIN2PPS2 0x04
6759 #define _MDCIN2PPS3 0x08
6760 #define _MDCIN2PPS4 0x10
6762 //==============================================================================
6765 //==============================================================================
6768 extern __at(0x0E1C) __sfr MDMINPPS
;
6774 unsigned MDMINPPS0
: 1;
6775 unsigned MDMINPPS1
: 1;
6776 unsigned MDMINPPS2
: 1;
6777 unsigned MDMINPPS3
: 1;
6778 unsigned MDMINPPS4
: 1;
6786 unsigned MDMINPPS
: 5;
6791 extern __at(0x0E1C) volatile __MDMINPPSbits_t MDMINPPSbits
;
6793 #define _MDMINPPS0 0x01
6794 #define _MDMINPPS1 0x02
6795 #define _MDMINPPS2 0x04
6796 #define _MDMINPPS3 0x08
6797 #define _MDMINPPS4 0x10
6799 //==============================================================================
6802 //==============================================================================
6805 extern __at(0x0E20) __sfr SSP1CLKPPS
;
6811 unsigned SSP1CLKPPS0
: 1;
6812 unsigned SSP1CLKPPS1
: 1;
6813 unsigned SSP1CLKPPS2
: 1;
6814 unsigned SSP1CLKPPS3
: 1;
6815 unsigned SSP1CLKPPS4
: 1;
6823 unsigned SSP1CLKPPS
: 5;
6826 } __SSP1CLKPPSbits_t
;
6828 extern __at(0x0E20) volatile __SSP1CLKPPSbits_t SSP1CLKPPSbits
;
6830 #define _SSP1CLKPPS0 0x01
6831 #define _SSP1CLKPPS1 0x02
6832 #define _SSP1CLKPPS2 0x04
6833 #define _SSP1CLKPPS3 0x08
6834 #define _SSP1CLKPPS4 0x10
6836 //==============================================================================
6839 //==============================================================================
6842 extern __at(0x0E21) __sfr SSP1DATPPS
;
6848 unsigned SSP1DATPPS0
: 1;
6849 unsigned SSP1DATPPS1
: 1;
6850 unsigned SSP1DATPPS2
: 1;
6851 unsigned SSP1DATPPS3
: 1;
6852 unsigned SSP1DATPPS4
: 1;
6860 unsigned SSP1DATPPS
: 5;
6863 } __SSP1DATPPSbits_t
;
6865 extern __at(0x0E21) volatile __SSP1DATPPSbits_t SSP1DATPPSbits
;
6867 #define _SSP1DATPPS0 0x01
6868 #define _SSP1DATPPS1 0x02
6869 #define _SSP1DATPPS2 0x04
6870 #define _SSP1DATPPS3 0x08
6871 #define _SSP1DATPPS4 0x10
6873 //==============================================================================
6876 //==============================================================================
6879 extern __at(0x0E22) __sfr SSP1SSPPS
;
6885 unsigned SSP1SSPPS0
: 1;
6886 unsigned SSP1SSPPS1
: 1;
6887 unsigned SSP1SSPPS2
: 1;
6888 unsigned SSP1SSPPS3
: 1;
6889 unsigned SSP1SSPPS4
: 1;
6897 unsigned SSP1SSPPS
: 5;
6900 } __SSP1SSPPSbits_t
;
6902 extern __at(0x0E22) volatile __SSP1SSPPSbits_t SSP1SSPPSbits
;
6904 #define _SSP1SSPPS0 0x01
6905 #define _SSP1SSPPS1 0x02
6906 #define _SSP1SSPPS2 0x04
6907 #define _SSP1SSPPS3 0x08
6908 #define _SSP1SSPPS4 0x10
6910 //==============================================================================
6913 //==============================================================================
6916 extern __at(0x0E24) __sfr RXPPS
;
6922 unsigned RXDTPPS0
: 1;
6923 unsigned RXDTPPS1
: 1;
6924 unsigned RXDTPPS2
: 1;
6925 unsigned RXDTPPS3
: 1;
6926 unsigned RXDTPPS4
: 1;
6934 unsigned RXDTPPS
: 5;
6939 extern __at(0x0E24) volatile __RXPPSbits_t RXPPSbits
;
6941 #define _RXDTPPS0 0x01
6942 #define _RXDTPPS1 0x02
6943 #define _RXDTPPS2 0x04
6944 #define _RXDTPPS3 0x08
6945 #define _RXDTPPS4 0x10
6947 //==============================================================================
6950 //==============================================================================
6953 extern __at(0x0E25) __sfr TXPPS
;
6959 unsigned TXCKPPS0
: 1;
6960 unsigned TXCKPPS1
: 1;
6961 unsigned TXCKPPS2
: 1;
6962 unsigned TXCKPPS3
: 1;
6963 unsigned TXCKPPS4
: 1;
6971 unsigned TXCKPPS
: 5;
6976 extern __at(0x0E25) volatile __TXPPSbits_t TXPPSbits
;
6978 #define _TXCKPPS0 0x01
6979 #define _TXCKPPS1 0x02
6980 #define _TXCKPPS2 0x04
6981 #define _TXCKPPS3 0x08
6982 #define _TXCKPPS4 0x10
6984 //==============================================================================
6987 //==============================================================================
6990 extern __at(0x0E28) __sfr CLCIN0PPS
;
6996 unsigned CLCIN0PPS0
: 1;
6997 unsigned CLCIN0PPS1
: 1;
6998 unsigned CLCIN0PPS2
: 1;
6999 unsigned CLCIN0PPS3
: 1;
7000 unsigned CLCIN0PPS4
: 1;
7008 unsigned CLCIN0PPS
: 5;
7011 } __CLCIN0PPSbits_t
;
7013 extern __at(0x0E28) volatile __CLCIN0PPSbits_t CLCIN0PPSbits
;
7015 #define _CLCIN0PPS0 0x01
7016 #define _CLCIN0PPS1 0x02
7017 #define _CLCIN0PPS2 0x04
7018 #define _CLCIN0PPS3 0x08
7019 #define _CLCIN0PPS4 0x10
7021 //==============================================================================
7024 //==============================================================================
7027 extern __at(0x0E29) __sfr CLCIN1PPS
;
7033 unsigned CLCIN1PPS0
: 1;
7034 unsigned CLCIN1PPS1
: 1;
7035 unsigned CLCIN1PPS2
: 1;
7036 unsigned CLCIN1PPS3
: 1;
7037 unsigned CLCIN1PPS4
: 1;
7045 unsigned CLCIN1PPS
: 5;
7048 } __CLCIN1PPSbits_t
;
7050 extern __at(0x0E29) volatile __CLCIN1PPSbits_t CLCIN1PPSbits
;
7052 #define _CLCIN1PPS0 0x01
7053 #define _CLCIN1PPS1 0x02
7054 #define _CLCIN1PPS2 0x04
7055 #define _CLCIN1PPS3 0x08
7056 #define _CLCIN1PPS4 0x10
7058 //==============================================================================
7061 //==============================================================================
7064 extern __at(0x0E2A) __sfr CLCIN2PPS
;
7070 unsigned CLCIN2PPS0
: 1;
7071 unsigned CLCIN2PPS1
: 1;
7072 unsigned CLCIN2PPS2
: 1;
7073 unsigned CLCIN2PPS3
: 1;
7074 unsigned CLCIN2PPS4
: 1;
7082 unsigned CLCIN2PPS
: 5;
7085 } __CLCIN2PPSbits_t
;
7087 extern __at(0x0E2A) volatile __CLCIN2PPSbits_t CLCIN2PPSbits
;
7089 #define _CLCIN2PPS0 0x01
7090 #define _CLCIN2PPS1 0x02
7091 #define _CLCIN2PPS2 0x04
7092 #define _CLCIN2PPS3 0x08
7093 #define _CLCIN2PPS4 0x10
7095 //==============================================================================
7098 //==============================================================================
7101 extern __at(0x0E2B) __sfr CLCIN3PPS
;
7107 unsigned CLCIN3PPS0
: 1;
7108 unsigned CLCIN3PPS1
: 1;
7109 unsigned CLCIN3PPS2
: 1;
7110 unsigned CLCIN3PPS3
: 1;
7111 unsigned CLCIN3PPS4
: 1;
7119 unsigned CLCIN3PPS
: 5;
7122 } __CLCIN3PPSbits_t
;
7124 extern __at(0x0E2B) volatile __CLCIN3PPSbits_t CLCIN3PPSbits
;
7126 #define _CLCIN3PPS0 0x01
7127 #define _CLCIN3PPS1 0x02
7128 #define _CLCIN3PPS2 0x04
7129 #define _CLCIN3PPS3 0x08
7130 #define _CLCIN3PPS4 0x10
7132 //==============================================================================
7134 extern __at(0x0E2C) __sfr T3CKIPPS
;
7135 extern __at(0x0E2D) __sfr T3GPPS
;
7136 extern __at(0x0E2E) __sfr T5CKIPPS
;
7137 extern __at(0x0E2F) __sfr T5GPPS
;
7139 //==============================================================================
7142 extern __at(0x0E90) __sfr RA0PPS
;
7148 unsigned RA0PPS0
: 1;
7149 unsigned RA0PPS1
: 1;
7150 unsigned RA0PPS2
: 1;
7151 unsigned RA0PPS3
: 1;
7152 unsigned RA0PPS4
: 1;
7160 unsigned RA0PPS
: 5;
7165 extern __at(0x0E90) volatile __RA0PPSbits_t RA0PPSbits
;
7167 #define _RA0PPS0 0x01
7168 #define _RA0PPS1 0x02
7169 #define _RA0PPS2 0x04
7170 #define _RA0PPS3 0x08
7171 #define _RA0PPS4 0x10
7173 //==============================================================================
7176 //==============================================================================
7179 extern __at(0x0E91) __sfr RA1PPS
;
7185 unsigned RA1PPS0
: 1;
7186 unsigned RA1PPS1
: 1;
7187 unsigned RA1PPS2
: 1;
7188 unsigned RA1PPS3
: 1;
7189 unsigned RA1PPS4
: 1;
7197 unsigned RA1PPS
: 5;
7202 extern __at(0x0E91) volatile __RA1PPSbits_t RA1PPSbits
;
7204 #define _RA1PPS0 0x01
7205 #define _RA1PPS1 0x02
7206 #define _RA1PPS2 0x04
7207 #define _RA1PPS3 0x08
7208 #define _RA1PPS4 0x10
7210 //==============================================================================
7213 //==============================================================================
7216 extern __at(0x0E92) __sfr RA2PPS
;
7222 unsigned RA2PPS0
: 1;
7223 unsigned RA2PPS1
: 1;
7224 unsigned RA2PPS2
: 1;
7225 unsigned RA2PPS3
: 1;
7226 unsigned RA2PPS4
: 1;
7234 unsigned RA2PPS
: 5;
7239 extern __at(0x0E92) volatile __RA2PPSbits_t RA2PPSbits
;
7241 #define _RA2PPS0 0x01
7242 #define _RA2PPS1 0x02
7243 #define _RA2PPS2 0x04
7244 #define _RA2PPS3 0x08
7245 #define _RA2PPS4 0x10
7247 //==============================================================================
7250 //==============================================================================
7253 extern __at(0x0E94) __sfr RA4PPS
;
7259 unsigned RA4PPS0
: 1;
7260 unsigned RA4PPS1
: 1;
7261 unsigned RA4PPS2
: 1;
7262 unsigned RA4PPS3
: 1;
7263 unsigned RA4PPS4
: 1;
7271 unsigned RA4PPS
: 5;
7276 extern __at(0x0E94) volatile __RA4PPSbits_t RA4PPSbits
;
7278 #define _RA4PPS0 0x01
7279 #define _RA4PPS1 0x02
7280 #define _RA4PPS2 0x04
7281 #define _RA4PPS3 0x08
7282 #define _RA4PPS4 0x10
7284 //==============================================================================
7287 //==============================================================================
7290 extern __at(0x0E95) __sfr RA5PPS
;
7296 unsigned RA5PPS0
: 1;
7297 unsigned RA5PPS1
: 1;
7298 unsigned RA5PPS2
: 1;
7299 unsigned RA5PPS3
: 1;
7300 unsigned RA5PPS4
: 1;
7308 unsigned RA5PPS
: 5;
7313 extern __at(0x0E95) volatile __RA5PPSbits_t RA5PPSbits
;
7315 #define _RA5PPS0 0x01
7316 #define _RA5PPS1 0x02
7317 #define _RA5PPS2 0x04
7318 #define _RA5PPS3 0x08
7319 #define _RA5PPS4 0x10
7321 //==============================================================================
7324 //==============================================================================
7327 extern __at(0x0EA0) __sfr RC0PPS
;
7333 unsigned RC0PPS0
: 1;
7334 unsigned RC0PPS1
: 1;
7335 unsigned RC0PPS2
: 1;
7336 unsigned RC0PPS3
: 1;
7337 unsigned RC0PPS4
: 1;
7345 unsigned RC0PPS
: 5;
7350 extern __at(0x0EA0) volatile __RC0PPSbits_t RC0PPSbits
;
7352 #define _RC0PPS0 0x01
7353 #define _RC0PPS1 0x02
7354 #define _RC0PPS2 0x04
7355 #define _RC0PPS3 0x08
7356 #define _RC0PPS4 0x10
7358 //==============================================================================
7361 //==============================================================================
7364 extern __at(0x0EA1) __sfr RC1PPS
;
7370 unsigned RC1PPS0
: 1;
7371 unsigned RC1PPS1
: 1;
7372 unsigned RC1PPS2
: 1;
7373 unsigned RC1PPS3
: 1;
7374 unsigned RC1PPS4
: 1;
7382 unsigned RC1PPS
: 5;
7387 extern __at(0x0EA1) volatile __RC1PPSbits_t RC1PPSbits
;
7389 #define _RC1PPS0 0x01
7390 #define _RC1PPS1 0x02
7391 #define _RC1PPS2 0x04
7392 #define _RC1PPS3 0x08
7393 #define _RC1PPS4 0x10
7395 //==============================================================================
7398 //==============================================================================
7401 extern __at(0x0EA2) __sfr RC2PPS
;
7407 unsigned RC2PPS0
: 1;
7408 unsigned RC2PPS1
: 1;
7409 unsigned RC2PPS2
: 1;
7410 unsigned RC2PPS3
: 1;
7411 unsigned RC2PPS4
: 1;
7419 unsigned RC2PPS
: 5;
7424 extern __at(0x0EA2) volatile __RC2PPSbits_t RC2PPSbits
;
7426 #define _RC2PPS0 0x01
7427 #define _RC2PPS1 0x02
7428 #define _RC2PPS2 0x04
7429 #define _RC2PPS3 0x08
7430 #define _RC2PPS4 0x10
7432 //==============================================================================
7435 //==============================================================================
7438 extern __at(0x0EA3) __sfr RC3PPS
;
7444 unsigned RC3PPS0
: 1;
7445 unsigned RC3PPS1
: 1;
7446 unsigned RC3PPS2
: 1;
7447 unsigned RC3PPS3
: 1;
7448 unsigned RC3PPS4
: 1;
7456 unsigned RC3PPS
: 5;
7461 extern __at(0x0EA3) volatile __RC3PPSbits_t RC3PPSbits
;
7463 #define _RC3PPS0 0x01
7464 #define _RC3PPS1 0x02
7465 #define _RC3PPS2 0x04
7466 #define _RC3PPS3 0x08
7467 #define _RC3PPS4 0x10
7469 //==============================================================================
7472 //==============================================================================
7475 extern __at(0x0EA4) __sfr RC4PPS
;
7481 unsigned RC4PPS0
: 1;
7482 unsigned RC4PPS1
: 1;
7483 unsigned RC4PPS2
: 1;
7484 unsigned RC4PPS3
: 1;
7485 unsigned RC4PPS4
: 1;
7493 unsigned RC4PPS
: 5;
7498 extern __at(0x0EA4) volatile __RC4PPSbits_t RC4PPSbits
;
7500 #define _RC4PPS0 0x01
7501 #define _RC4PPS1 0x02
7502 #define _RC4PPS2 0x04
7503 #define _RC4PPS3 0x08
7504 #define _RC4PPS4 0x10
7506 //==============================================================================
7509 //==============================================================================
7512 extern __at(0x0EA5) __sfr RC5PPS
;
7518 unsigned RC5PPS0
: 1;
7519 unsigned RC5PPS1
: 1;
7520 unsigned RC5PPS2
: 1;
7521 unsigned RC5PPS3
: 1;
7522 unsigned RC5PPS4
: 1;
7530 unsigned RC5PPS
: 5;
7535 extern __at(0x0EA5) volatile __RC5PPSbits_t RC5PPSbits
;
7537 #define _RC5PPS0 0x01
7538 #define _RC5PPS1 0x02
7539 #define _RC5PPS2 0x04
7540 #define _RC5PPS3 0x08
7541 #define _RC5PPS4 0x10
7543 //==============================================================================
7546 //==============================================================================
7549 extern __at(0x0F0F) __sfr CLCDATA
;
7553 unsigned MLC1OUT
: 1;
7554 unsigned MLC2OUT
: 1;
7555 unsigned MLC3OUT
: 1;
7556 unsigned MLC4OUT
: 1;
7563 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
7565 #define _MLC1OUT 0x01
7566 #define _MLC2OUT 0x02
7567 #define _MLC3OUT 0x04
7568 #define _MLC4OUT 0x08
7570 //==============================================================================
7573 //==============================================================================
7576 extern __at(0x0F10) __sfr CLC1CON
;
7582 unsigned LC1MODE0
: 1;
7583 unsigned LC1MODE1
: 1;
7584 unsigned LC1MODE2
: 1;
7585 unsigned LC1INTN
: 1;
7586 unsigned LC1INTP
: 1;
7587 unsigned LC1OUT
: 1;
7606 unsigned LC1MODE
: 3;
7617 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
7619 #define _LC1MODE0 0x01
7621 #define _LC1MODE1 0x02
7623 #define _LC1MODE2 0x04
7625 #define _LC1INTN 0x08
7627 #define _LC1INTP 0x10
7629 #define _LC1OUT 0x20
7634 //==============================================================================
7637 //==============================================================================
7640 extern __at(0x0F11) __sfr CLC1POL
;
7646 unsigned LC1G1POL
: 1;
7647 unsigned LC1G2POL
: 1;
7648 unsigned LC1G3POL
: 1;
7649 unsigned LC1G4POL
: 1;
7653 unsigned LC1POL
: 1;
7669 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
7671 #define _LC1G1POL 0x01
7673 #define _LC1G2POL 0x02
7675 #define _LC1G3POL 0x04
7677 #define _LC1G4POL 0x08
7679 #define _LC1POL 0x80
7682 //==============================================================================
7685 //==============================================================================
7688 extern __at(0x0F12) __sfr CLC1SEL0
;
7694 unsigned LC1D1S0
: 1;
7695 unsigned LC1D1S1
: 1;
7696 unsigned LC1D1S2
: 1;
7697 unsigned LC1D1S3
: 1;
7698 unsigned LC1D1S4
: 1;
7699 unsigned LC1D1S5
: 1;
7718 unsigned LC1D1S
: 6;
7729 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
7731 #define _LC1D1S0 0x01
7733 #define _LC1D1S1 0x02
7735 #define _LC1D1S2 0x04
7737 #define _LC1D1S3 0x08
7739 #define _LC1D1S4 0x10
7741 #define _LC1D1S5 0x20
7744 //==============================================================================
7747 //==============================================================================
7750 extern __at(0x0F13) __sfr CLC1SEL1
;
7756 unsigned LC1D2S0
: 1;
7757 unsigned LC1D2S1
: 1;
7758 unsigned LC1D2S2
: 1;
7759 unsigned LC1D2S3
: 1;
7760 unsigned LC1D2S4
: 1;
7761 unsigned LC1D2S5
: 1;
7786 unsigned LC1D2S
: 6;
7791 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
7793 #define _LC1D2S0 0x01
7795 #define _LC1D2S1 0x02
7797 #define _LC1D2S2 0x04
7799 #define _LC1D2S3 0x08
7801 #define _LC1D2S4 0x10
7803 #define _LC1D2S5 0x20
7806 //==============================================================================
7809 //==============================================================================
7812 extern __at(0x0F14) __sfr CLC1SEL2
;
7818 unsigned LC1D3S0
: 1;
7819 unsigned LC1D3S1
: 1;
7820 unsigned LC1D3S2
: 1;
7821 unsigned LC1D3S3
: 1;
7822 unsigned LC1D3S4
: 1;
7823 unsigned LC1D3S5
: 1;
7842 unsigned LC1D3S
: 6;
7853 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
7855 #define _LC1D3S0 0x01
7857 #define _LC1D3S1 0x02
7859 #define _LC1D3S2 0x04
7861 #define _LC1D3S3 0x08
7863 #define _LC1D3S4 0x10
7865 #define _LC1D3S5 0x20
7868 //==============================================================================
7871 //==============================================================================
7874 extern __at(0x0F15) __sfr CLC1SEL3
;
7880 unsigned LC1D4S0
: 1;
7881 unsigned LC1D4S1
: 1;
7882 unsigned LC1D4S2
: 1;
7883 unsigned LC1D4S3
: 1;
7884 unsigned LC1D4S4
: 1;
7885 unsigned LC1D4S5
: 1;
7904 unsigned LC1D4S
: 6;
7915 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
7917 #define _LC1D4S0 0x01
7919 #define _LC1D4S1 0x02
7921 #define _LC1D4S2 0x04
7923 #define _LC1D4S3 0x08
7925 #define _LC1D4S4 0x10
7927 #define _LC1D4S5 0x20
7930 //==============================================================================
7933 //==============================================================================
7936 extern __at(0x0F16) __sfr CLC1GLS0
;
7942 unsigned LC1G1D1N
: 1;
7943 unsigned LC1G1D1T
: 1;
7944 unsigned LC1G1D2N
: 1;
7945 unsigned LC1G1D2T
: 1;
7946 unsigned LC1G1D3N
: 1;
7947 unsigned LC1G1D3T
: 1;
7948 unsigned LC1G1D4N
: 1;
7949 unsigned LC1G1D4T
: 1;
7965 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
7967 #define _LC1G1D1N 0x01
7969 #define _LC1G1D1T 0x02
7971 #define _LC1G1D2N 0x04
7973 #define _LC1G1D2T 0x08
7975 #define _LC1G1D3N 0x10
7977 #define _LC1G1D3T 0x20
7979 #define _LC1G1D4N 0x40
7981 #define _LC1G1D4T 0x80
7984 //==============================================================================
7987 //==============================================================================
7990 extern __at(0x0F17) __sfr CLC1GLS1
;
7996 unsigned LC1G2D1N
: 1;
7997 unsigned LC1G2D1T
: 1;
7998 unsigned LC1G2D2N
: 1;
7999 unsigned LC1G2D2T
: 1;
8000 unsigned LC1G2D3N
: 1;
8001 unsigned LC1G2D3T
: 1;
8002 unsigned LC1G2D4N
: 1;
8003 unsigned LC1G2D4T
: 1;
8019 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
8021 #define _CLC1GLS1_LC1G2D1N 0x01
8022 #define _CLC1GLS1_D1N 0x01
8023 #define _CLC1GLS1_LC1G2D1T 0x02
8024 #define _CLC1GLS1_D1T 0x02
8025 #define _CLC1GLS1_LC1G2D2N 0x04
8026 #define _CLC1GLS1_D2N 0x04
8027 #define _CLC1GLS1_LC1G2D2T 0x08
8028 #define _CLC1GLS1_D2T 0x08
8029 #define _CLC1GLS1_LC1G2D3N 0x10
8030 #define _CLC1GLS1_D3N 0x10
8031 #define _CLC1GLS1_LC1G2D3T 0x20
8032 #define _CLC1GLS1_D3T 0x20
8033 #define _CLC1GLS1_LC1G2D4N 0x40
8034 #define _CLC1GLS1_D4N 0x40
8035 #define _CLC1GLS1_LC1G2D4T 0x80
8036 #define _CLC1GLS1_D4T 0x80
8038 //==============================================================================
8041 //==============================================================================
8044 extern __at(0x0F18) __sfr CLC1GLS2
;
8050 unsigned LC1G3D1N
: 1;
8051 unsigned LC1G3D1T
: 1;
8052 unsigned LC1G3D2N
: 1;
8053 unsigned LC1G3D2T
: 1;
8054 unsigned LC1G3D3N
: 1;
8055 unsigned LC1G3D3T
: 1;
8056 unsigned LC1G3D4N
: 1;
8057 unsigned LC1G3D4T
: 1;
8073 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
8075 #define _CLC1GLS2_LC1G3D1N 0x01
8076 #define _CLC1GLS2_D1N 0x01
8077 #define _CLC1GLS2_LC1G3D1T 0x02
8078 #define _CLC1GLS2_D1T 0x02
8079 #define _CLC1GLS2_LC1G3D2N 0x04
8080 #define _CLC1GLS2_D2N 0x04
8081 #define _CLC1GLS2_LC1G3D2T 0x08
8082 #define _CLC1GLS2_D2T 0x08
8083 #define _CLC1GLS2_LC1G3D3N 0x10
8084 #define _CLC1GLS2_D3N 0x10
8085 #define _CLC1GLS2_LC1G3D3T 0x20
8086 #define _CLC1GLS2_D3T 0x20
8087 #define _CLC1GLS2_LC1G3D4N 0x40
8088 #define _CLC1GLS2_D4N 0x40
8089 #define _CLC1GLS2_LC1G3D4T 0x80
8090 #define _CLC1GLS2_D4T 0x80
8092 //==============================================================================
8095 //==============================================================================
8098 extern __at(0x0F19) __sfr CLC1GLS3
;
8104 unsigned LC1G4D1N
: 1;
8105 unsigned LC1G4D1T
: 1;
8106 unsigned LC1G4D2N
: 1;
8107 unsigned LC1G4D2T
: 1;
8108 unsigned LC1G4D3N
: 1;
8109 unsigned LC1G4D3T
: 1;
8110 unsigned LC1G4D4N
: 1;
8111 unsigned LC1G4D4T
: 1;
8127 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
8129 #define _LC1G4D1N 0x01
8131 #define _LC1G4D1T 0x02
8133 #define _LC1G4D2N 0x04
8135 #define _LC1G4D2T 0x08
8137 #define _LC1G4D3N 0x10
8139 #define _LC1G4D3T 0x20
8141 #define _LC1G4D4N 0x40
8143 #define _LC1G4D4T 0x80
8146 //==============================================================================
8149 //==============================================================================
8152 extern __at(0x0F1A) __sfr CLC2CON
;
8158 unsigned LC2MODE0
: 1;
8159 unsigned LC2MODE1
: 1;
8160 unsigned LC2MODE2
: 1;
8161 unsigned LC2INTN
: 1;
8162 unsigned LC2INTP
: 1;
8163 unsigned LC2OUT
: 1;
8188 unsigned LC2MODE
: 3;
8193 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
8195 #define _CLC2CON_LC2MODE0 0x01
8196 #define _CLC2CON_MODE0 0x01
8197 #define _CLC2CON_LC2MODE1 0x02
8198 #define _CLC2CON_MODE1 0x02
8199 #define _CLC2CON_LC2MODE2 0x04
8200 #define _CLC2CON_MODE2 0x04
8201 #define _CLC2CON_LC2INTN 0x08
8202 #define _CLC2CON_INTN 0x08
8203 #define _CLC2CON_LC2INTP 0x10
8204 #define _CLC2CON_INTP 0x10
8205 #define _CLC2CON_LC2OUT 0x20
8206 #define _CLC2CON_OUT 0x20
8207 #define _CLC2CON_LC2EN 0x80
8208 #define _CLC2CON_EN 0x80
8210 //==============================================================================
8213 //==============================================================================
8216 extern __at(0x0F1B) __sfr CLC2POL
;
8222 unsigned LC2G1POL
: 1;
8223 unsigned LC2G2POL
: 1;
8224 unsigned LC2G3POL
: 1;
8225 unsigned LC2G4POL
: 1;
8229 unsigned LC2POL
: 1;
8245 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
8247 #define _CLC2POL_LC2G1POL 0x01
8248 #define _CLC2POL_G1POL 0x01
8249 #define _CLC2POL_LC2G2POL 0x02
8250 #define _CLC2POL_G2POL 0x02
8251 #define _CLC2POL_LC2G3POL 0x04
8252 #define _CLC2POL_G3POL 0x04
8253 #define _CLC2POL_LC2G4POL 0x08
8254 #define _CLC2POL_G4POL 0x08
8255 #define _CLC2POL_LC2POL 0x80
8256 #define _CLC2POL_POL 0x80
8258 //==============================================================================
8261 //==============================================================================
8264 extern __at(0x0F1C) __sfr CLC2SEL0
;
8270 unsigned LC2D1S0
: 1;
8271 unsigned LC2D1S1
: 1;
8272 unsigned LC2D1S2
: 1;
8273 unsigned LC2D1S3
: 1;
8274 unsigned LC2D1S4
: 1;
8275 unsigned LC2D1S5
: 1;
8300 unsigned LC2D1S
: 6;
8305 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
8307 #define _CLC2SEL0_LC2D1S0 0x01
8308 #define _CLC2SEL0_D1S0 0x01
8309 #define _CLC2SEL0_LC2D1S1 0x02
8310 #define _CLC2SEL0_D1S1 0x02
8311 #define _CLC2SEL0_LC2D1S2 0x04
8312 #define _CLC2SEL0_D1S2 0x04
8313 #define _CLC2SEL0_LC2D1S3 0x08
8314 #define _CLC2SEL0_D1S3 0x08
8315 #define _CLC2SEL0_LC2D1S4 0x10
8316 #define _CLC2SEL0_D1S4 0x10
8317 #define _CLC2SEL0_LC2D1S5 0x20
8318 #define _CLC2SEL0_D1S5 0x20
8320 //==============================================================================
8323 //==============================================================================
8326 extern __at(0x0F1D) __sfr CLC2SEL1
;
8332 unsigned LC2D2S0
: 1;
8333 unsigned LC2D2S1
: 1;
8334 unsigned LC2D2S2
: 1;
8335 unsigned LC2D2S3
: 1;
8336 unsigned LC2D2S4
: 1;
8337 unsigned LC2D2S5
: 1;
8362 unsigned LC2D2S
: 6;
8367 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
8369 #define _CLC2SEL1_LC2D2S0 0x01
8370 #define _CLC2SEL1_D2S0 0x01
8371 #define _CLC2SEL1_LC2D2S1 0x02
8372 #define _CLC2SEL1_D2S1 0x02
8373 #define _CLC2SEL1_LC2D2S2 0x04
8374 #define _CLC2SEL1_D2S2 0x04
8375 #define _CLC2SEL1_LC2D2S3 0x08
8376 #define _CLC2SEL1_D2S3 0x08
8377 #define _CLC2SEL1_LC2D2S4 0x10
8378 #define _CLC2SEL1_D2S4 0x10
8379 #define _CLC2SEL1_LC2D2S5 0x20
8380 #define _CLC2SEL1_D2S5 0x20
8382 //==============================================================================
8385 //==============================================================================
8388 extern __at(0x0F1E) __sfr CLC2SEL2
;
8394 unsigned LC2D3S0
: 1;
8395 unsigned LC2D3S1
: 1;
8396 unsigned LC2D3S2
: 1;
8397 unsigned LC2D3S3
: 1;
8398 unsigned LC2D3S4
: 1;
8399 unsigned LC2D3S5
: 1;
8418 unsigned LC2D3S
: 6;
8429 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
8431 #define _CLC2SEL2_LC2D3S0 0x01
8432 #define _CLC2SEL2_D3S0 0x01
8433 #define _CLC2SEL2_LC2D3S1 0x02
8434 #define _CLC2SEL2_D3S1 0x02
8435 #define _CLC2SEL2_LC2D3S2 0x04
8436 #define _CLC2SEL2_D3S2 0x04
8437 #define _CLC2SEL2_LC2D3S3 0x08
8438 #define _CLC2SEL2_D3S3 0x08
8439 #define _CLC2SEL2_LC2D3S4 0x10
8440 #define _CLC2SEL2_D3S4 0x10
8441 #define _CLC2SEL2_LC2D3S5 0x20
8442 #define _CLC2SEL2_D3S5 0x20
8444 //==============================================================================
8447 //==============================================================================
8450 extern __at(0x0F1F) __sfr CLC2SEL3
;
8456 unsigned LC2D4S0
: 1;
8457 unsigned LC2D4S1
: 1;
8458 unsigned LC2D4S2
: 1;
8459 unsigned LC2D4S3
: 1;
8460 unsigned LC2D4S4
: 1;
8461 unsigned LC2D4S5
: 1;
8486 unsigned LC2D4S
: 6;
8491 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
8493 #define _CLC2SEL3_LC2D4S0 0x01
8494 #define _CLC2SEL3_D4S0 0x01
8495 #define _CLC2SEL3_LC2D4S1 0x02
8496 #define _CLC2SEL3_D4S1 0x02
8497 #define _CLC2SEL3_LC2D4S2 0x04
8498 #define _CLC2SEL3_D4S2 0x04
8499 #define _CLC2SEL3_LC2D4S3 0x08
8500 #define _CLC2SEL3_D4S3 0x08
8501 #define _CLC2SEL3_LC2D4S4 0x10
8502 #define _CLC2SEL3_D4S4 0x10
8503 #define _CLC2SEL3_LC2D4S5 0x20
8504 #define _CLC2SEL3_D4S5 0x20
8506 //==============================================================================
8509 //==============================================================================
8512 extern __at(0x0F20) __sfr CLC2GLS0
;
8518 unsigned LC2G1D1N
: 1;
8519 unsigned LC2G1D1T
: 1;
8520 unsigned LC2G1D2N
: 1;
8521 unsigned LC2G1D2T
: 1;
8522 unsigned LC2G1D3N
: 1;
8523 unsigned LC2G1D3T
: 1;
8524 unsigned LC2G1D4N
: 1;
8525 unsigned LC2G1D4T
: 1;
8541 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
8543 #define _CLC2GLS0_LC2G1D1N 0x01
8544 #define _CLC2GLS0_D1N 0x01
8545 #define _CLC2GLS0_LC2G1D1T 0x02
8546 #define _CLC2GLS0_D1T 0x02
8547 #define _CLC2GLS0_LC2G1D2N 0x04
8548 #define _CLC2GLS0_D2N 0x04
8549 #define _CLC2GLS0_LC2G1D2T 0x08
8550 #define _CLC2GLS0_D2T 0x08
8551 #define _CLC2GLS0_LC2G1D3N 0x10
8552 #define _CLC2GLS0_D3N 0x10
8553 #define _CLC2GLS0_LC2G1D3T 0x20
8554 #define _CLC2GLS0_D3T 0x20
8555 #define _CLC2GLS0_LC2G1D4N 0x40
8556 #define _CLC2GLS0_D4N 0x40
8557 #define _CLC2GLS0_LC2G1D4T 0x80
8558 #define _CLC2GLS0_D4T 0x80
8560 //==============================================================================
8563 //==============================================================================
8566 extern __at(0x0F21) __sfr CLC2GLS1
;
8572 unsigned LC2G2D1N
: 1;
8573 unsigned LC2G2D1T
: 1;
8574 unsigned LC2G2D2N
: 1;
8575 unsigned LC2G2D2T
: 1;
8576 unsigned LC2G2D3N
: 1;
8577 unsigned LC2G2D3T
: 1;
8578 unsigned LC2G2D4N
: 1;
8579 unsigned LC2G2D4T
: 1;
8595 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
8597 #define _CLC2GLS1_LC2G2D1N 0x01
8598 #define _CLC2GLS1_D1N 0x01
8599 #define _CLC2GLS1_LC2G2D1T 0x02
8600 #define _CLC2GLS1_D1T 0x02
8601 #define _CLC2GLS1_LC2G2D2N 0x04
8602 #define _CLC2GLS1_D2N 0x04
8603 #define _CLC2GLS1_LC2G2D2T 0x08
8604 #define _CLC2GLS1_D2T 0x08
8605 #define _CLC2GLS1_LC2G2D3N 0x10
8606 #define _CLC2GLS1_D3N 0x10
8607 #define _CLC2GLS1_LC2G2D3T 0x20
8608 #define _CLC2GLS1_D3T 0x20
8609 #define _CLC2GLS1_LC2G2D4N 0x40
8610 #define _CLC2GLS1_D4N 0x40
8611 #define _CLC2GLS1_LC2G2D4T 0x80
8612 #define _CLC2GLS1_D4T 0x80
8614 //==============================================================================
8617 //==============================================================================
8620 extern __at(0x0F22) __sfr CLC2GLS2
;
8626 unsigned LC2G3D1N
: 1;
8627 unsigned LC2G3D1T
: 1;
8628 unsigned LC2G3D2N
: 1;
8629 unsigned LC2G3D2T
: 1;
8630 unsigned LC2G3D3N
: 1;
8631 unsigned LC2G3D3T
: 1;
8632 unsigned LC2G3D4N
: 1;
8633 unsigned LC2G3D4T
: 1;
8649 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
8651 #define _CLC2GLS2_LC2G3D1N 0x01
8652 #define _CLC2GLS2_D1N 0x01
8653 #define _CLC2GLS2_LC2G3D1T 0x02
8654 #define _CLC2GLS2_D1T 0x02
8655 #define _CLC2GLS2_LC2G3D2N 0x04
8656 #define _CLC2GLS2_D2N 0x04
8657 #define _CLC2GLS2_LC2G3D2T 0x08
8658 #define _CLC2GLS2_D2T 0x08
8659 #define _CLC2GLS2_LC2G3D3N 0x10
8660 #define _CLC2GLS2_D3N 0x10
8661 #define _CLC2GLS2_LC2G3D3T 0x20
8662 #define _CLC2GLS2_D3T 0x20
8663 #define _CLC2GLS2_LC2G3D4N 0x40
8664 #define _CLC2GLS2_D4N 0x40
8665 #define _CLC2GLS2_LC2G3D4T 0x80
8666 #define _CLC2GLS2_D4T 0x80
8668 //==============================================================================
8671 //==============================================================================
8674 extern __at(0x0F23) __sfr CLC2GLS3
;
8680 unsigned LC2G4D1N
: 1;
8681 unsigned LC2G4D1T
: 1;
8682 unsigned LC2G4D2N
: 1;
8683 unsigned LC2G4D2T
: 1;
8684 unsigned LC2G4D3N
: 1;
8685 unsigned LC2G4D3T
: 1;
8686 unsigned LC2G4D4N
: 1;
8687 unsigned LC2G4D4T
: 1;
8703 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
8705 #define _CLC2GLS3_LC2G4D1N 0x01
8706 #define _CLC2GLS3_G4D1N 0x01
8707 #define _CLC2GLS3_LC2G4D1T 0x02
8708 #define _CLC2GLS3_G4D1T 0x02
8709 #define _CLC2GLS3_LC2G4D2N 0x04
8710 #define _CLC2GLS3_G4D2N 0x04
8711 #define _CLC2GLS3_LC2G4D2T 0x08
8712 #define _CLC2GLS3_G4D2T 0x08
8713 #define _CLC2GLS3_LC2G4D3N 0x10
8714 #define _CLC2GLS3_G4D3N 0x10
8715 #define _CLC2GLS3_LC2G4D3T 0x20
8716 #define _CLC2GLS3_G4D3T 0x20
8717 #define _CLC2GLS3_LC2G4D4N 0x40
8718 #define _CLC2GLS3_G4D4N 0x40
8719 #define _CLC2GLS3_LC2G4D4T 0x80
8720 #define _CLC2GLS3_G4D4T 0x80
8722 //==============================================================================
8725 //==============================================================================
8728 extern __at(0x0F24) __sfr CLC3CON
;
8734 unsigned LC3MODE0
: 1;
8735 unsigned LC3MODE1
: 1;
8736 unsigned LC3MODE2
: 1;
8737 unsigned LC3INTN
: 1;
8738 unsigned LC3INTP
: 1;
8739 unsigned LC3OUT
: 1;
8758 unsigned LC3MODE
: 3;
8769 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
8771 #define _CLC3CON_LC3MODE0 0x01
8772 #define _CLC3CON_MODE0 0x01
8773 #define _CLC3CON_LC3MODE1 0x02
8774 #define _CLC3CON_MODE1 0x02
8775 #define _CLC3CON_LC3MODE2 0x04
8776 #define _CLC3CON_MODE2 0x04
8777 #define _CLC3CON_LC3INTN 0x08
8778 #define _CLC3CON_INTN 0x08
8779 #define _CLC3CON_LC3INTP 0x10
8780 #define _CLC3CON_INTP 0x10
8781 #define _CLC3CON_LC3OUT 0x20
8782 #define _CLC3CON_OUT 0x20
8783 #define _CLC3CON_LC3EN 0x80
8784 #define _CLC3CON_EN 0x80
8786 //==============================================================================
8789 //==============================================================================
8792 extern __at(0x0F25) __sfr CLC3POL
;
8798 unsigned LC3G1POL
: 1;
8799 unsigned LC3G2POL
: 1;
8800 unsigned LC3G3POL
: 1;
8801 unsigned LC3G4POL
: 1;
8805 unsigned LC3POL
: 1;
8821 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
8823 #define _CLC3POL_LC3G1POL 0x01
8824 #define _CLC3POL_G1POL 0x01
8825 #define _CLC3POL_LC3G2POL 0x02
8826 #define _CLC3POL_G2POL 0x02
8827 #define _CLC3POL_LC3G3POL 0x04
8828 #define _CLC3POL_G3POL 0x04
8829 #define _CLC3POL_LC3G4POL 0x08
8830 #define _CLC3POL_G4POL 0x08
8831 #define _CLC3POL_LC3POL 0x80
8832 #define _CLC3POL_POL 0x80
8834 //==============================================================================
8837 //==============================================================================
8840 extern __at(0x0F26) __sfr CLC3SEL0
;
8846 unsigned LC3D1S0
: 1;
8847 unsigned LC3D1S1
: 1;
8848 unsigned LC3D1S2
: 1;
8849 unsigned LC3D1S3
: 1;
8850 unsigned LC3D1S4
: 1;
8851 unsigned LC3D1S5
: 1;
8870 unsigned LC3D1S
: 6;
8881 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
8883 #define _CLC3SEL0_LC3D1S0 0x01
8884 #define _CLC3SEL0_D1S0 0x01
8885 #define _CLC3SEL0_LC3D1S1 0x02
8886 #define _CLC3SEL0_D1S1 0x02
8887 #define _CLC3SEL0_LC3D1S2 0x04
8888 #define _CLC3SEL0_D1S2 0x04
8889 #define _CLC3SEL0_LC3D1S3 0x08
8890 #define _CLC3SEL0_D1S3 0x08
8891 #define _CLC3SEL0_LC3D1S4 0x10
8892 #define _CLC3SEL0_D1S4 0x10
8893 #define _CLC3SEL0_LC3D1S5 0x20
8894 #define _CLC3SEL0_D1S5 0x20
8896 //==============================================================================
8899 //==============================================================================
8902 extern __at(0x0F27) __sfr CLC3SEL1
;
8908 unsigned LC3D2S0
: 1;
8909 unsigned LC3D2S1
: 1;
8910 unsigned LC3D2S2
: 1;
8911 unsigned LC3D2S3
: 1;
8912 unsigned LC3D2S4
: 1;
8913 unsigned LC3D2S5
: 1;
8938 unsigned LC3D2S
: 6;
8943 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
8945 #define _CLC3SEL1_LC3D2S0 0x01
8946 #define _CLC3SEL1_D2S0 0x01
8947 #define _CLC3SEL1_LC3D2S1 0x02
8948 #define _CLC3SEL1_D2S1 0x02
8949 #define _CLC3SEL1_LC3D2S2 0x04
8950 #define _CLC3SEL1_D2S2 0x04
8951 #define _CLC3SEL1_LC3D2S3 0x08
8952 #define _CLC3SEL1_D2S3 0x08
8953 #define _CLC3SEL1_LC3D2S4 0x10
8954 #define _CLC3SEL1_D2S4 0x10
8955 #define _CLC3SEL1_LC3D2S5 0x20
8956 #define _CLC3SEL1_D2S5 0x20
8958 //==============================================================================
8961 //==============================================================================
8964 extern __at(0x0F28) __sfr CLC3SEL2
;
8970 unsigned LC3D3S0
: 1;
8971 unsigned LC3D3S1
: 1;
8972 unsigned LC3D3S2
: 1;
8973 unsigned LC3D3S3
: 1;
8974 unsigned LC3D3S4
: 1;
8975 unsigned LC3D3S5
: 1;
8994 unsigned LC3D3S
: 6;
9005 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
9007 #define _CLC3SEL2_LC3D3S0 0x01
9008 #define _CLC3SEL2_D3S0 0x01
9009 #define _CLC3SEL2_LC3D3S1 0x02
9010 #define _CLC3SEL2_D3S1 0x02
9011 #define _CLC3SEL2_LC3D3S2 0x04
9012 #define _CLC3SEL2_D3S2 0x04
9013 #define _CLC3SEL2_LC3D3S3 0x08
9014 #define _CLC3SEL2_D3S3 0x08
9015 #define _CLC3SEL2_LC3D3S4 0x10
9016 #define _CLC3SEL2_D3S4 0x10
9017 #define _CLC3SEL2_LC3D3S5 0x20
9018 #define _CLC3SEL2_D3S5 0x20
9020 //==============================================================================
9023 //==============================================================================
9026 extern __at(0x0F29) __sfr CLC3SEL3
;
9032 unsigned LC3D4S0
: 1;
9033 unsigned LC3D4S1
: 1;
9034 unsigned LC3D4S2
: 1;
9035 unsigned LC3D4S3
: 1;
9036 unsigned LC3D4S4
: 1;
9037 unsigned LC3D4S5
: 1;
9062 unsigned LC3D4S
: 6;
9067 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
9069 #define _CLC3SEL3_LC3D4S0 0x01
9070 #define _CLC3SEL3_D4S0 0x01
9071 #define _CLC3SEL3_LC3D4S1 0x02
9072 #define _CLC3SEL3_D4S1 0x02
9073 #define _CLC3SEL3_LC3D4S2 0x04
9074 #define _CLC3SEL3_D4S2 0x04
9075 #define _CLC3SEL3_LC3D4S3 0x08
9076 #define _CLC3SEL3_D4S3 0x08
9077 #define _CLC3SEL3_LC3D4S4 0x10
9078 #define _CLC3SEL3_D4S4 0x10
9079 #define _CLC3SEL3_LC3D4S5 0x20
9080 #define _CLC3SEL3_D4S5 0x20
9082 //==============================================================================
9085 //==============================================================================
9088 extern __at(0x0F2A) __sfr CLC3GLS0
;
9094 unsigned LC3G1D1N
: 1;
9095 unsigned LC3G1D1T
: 1;
9096 unsigned LC3G1D2N
: 1;
9097 unsigned LC3G1D2T
: 1;
9098 unsigned LC3G1D3N
: 1;
9099 unsigned LC3G1D3T
: 1;
9100 unsigned LC3G1D4N
: 1;
9101 unsigned LC3G1D4T
: 1;
9117 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
9119 #define _CLC3GLS0_LC3G1D1N 0x01
9120 #define _CLC3GLS0_D1N 0x01
9121 #define _CLC3GLS0_LC3G1D1T 0x02
9122 #define _CLC3GLS0_D1T 0x02
9123 #define _CLC3GLS0_LC3G1D2N 0x04
9124 #define _CLC3GLS0_D2N 0x04
9125 #define _CLC3GLS0_LC3G1D2T 0x08
9126 #define _CLC3GLS0_D2T 0x08
9127 #define _CLC3GLS0_LC3G1D3N 0x10
9128 #define _CLC3GLS0_D3N 0x10
9129 #define _CLC3GLS0_LC3G1D3T 0x20
9130 #define _CLC3GLS0_D3T 0x20
9131 #define _CLC3GLS0_LC3G1D4N 0x40
9132 #define _CLC3GLS0_D4N 0x40
9133 #define _CLC3GLS0_LC3G1D4T 0x80
9134 #define _CLC3GLS0_D4T 0x80
9136 //==============================================================================
9139 //==============================================================================
9142 extern __at(0x0F2B) __sfr CLC3GLS1
;
9148 unsigned LC3G2D1N
: 1;
9149 unsigned LC3G2D1T
: 1;
9150 unsigned LC3G2D2N
: 1;
9151 unsigned LC3G2D2T
: 1;
9152 unsigned LC3G2D3N
: 1;
9153 unsigned LC3G2D3T
: 1;
9154 unsigned LC3G2D4N
: 1;
9155 unsigned LC3G2D4T
: 1;
9171 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
9173 #define _CLC3GLS1_LC3G2D1N 0x01
9174 #define _CLC3GLS1_D1N 0x01
9175 #define _CLC3GLS1_LC3G2D1T 0x02
9176 #define _CLC3GLS1_D1T 0x02
9177 #define _CLC3GLS1_LC3G2D2N 0x04
9178 #define _CLC3GLS1_D2N 0x04
9179 #define _CLC3GLS1_LC3G2D2T 0x08
9180 #define _CLC3GLS1_D2T 0x08
9181 #define _CLC3GLS1_LC3G2D3N 0x10
9182 #define _CLC3GLS1_D3N 0x10
9183 #define _CLC3GLS1_LC3G2D3T 0x20
9184 #define _CLC3GLS1_D3T 0x20
9185 #define _CLC3GLS1_LC3G2D4N 0x40
9186 #define _CLC3GLS1_D4N 0x40
9187 #define _CLC3GLS1_LC3G2D4T 0x80
9188 #define _CLC3GLS1_D4T 0x80
9190 //==============================================================================
9193 //==============================================================================
9196 extern __at(0x0F2C) __sfr CLC3GLS2
;
9202 unsigned LC3G3D1N
: 1;
9203 unsigned LC3G3D1T
: 1;
9204 unsigned LC3G3D2N
: 1;
9205 unsigned LC3G3D2T
: 1;
9206 unsigned LC3G3D3N
: 1;
9207 unsigned LC3G3D3T
: 1;
9208 unsigned LC3G3D4N
: 1;
9209 unsigned LC3G3D4T
: 1;
9225 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
9227 #define _CLC3GLS2_LC3G3D1N 0x01
9228 #define _CLC3GLS2_D1N 0x01
9229 #define _CLC3GLS2_LC3G3D1T 0x02
9230 #define _CLC3GLS2_D1T 0x02
9231 #define _CLC3GLS2_LC3G3D2N 0x04
9232 #define _CLC3GLS2_D2N 0x04
9233 #define _CLC3GLS2_LC3G3D2T 0x08
9234 #define _CLC3GLS2_D2T 0x08
9235 #define _CLC3GLS2_LC3G3D3N 0x10
9236 #define _CLC3GLS2_D3N 0x10
9237 #define _CLC3GLS2_LC3G3D3T 0x20
9238 #define _CLC3GLS2_D3T 0x20
9239 #define _CLC3GLS2_LC3G3D4N 0x40
9240 #define _CLC3GLS2_D4N 0x40
9241 #define _CLC3GLS2_LC3G3D4T 0x80
9242 #define _CLC3GLS2_D4T 0x80
9244 //==============================================================================
9247 //==============================================================================
9250 extern __at(0x0F2D) __sfr CLC3GLS3
;
9256 unsigned LC3G4D1N
: 1;
9257 unsigned LC3G4D1T
: 1;
9258 unsigned LC3G4D2N
: 1;
9259 unsigned LC3G4D2T
: 1;
9260 unsigned LC3G4D3N
: 1;
9261 unsigned LC3G4D3T
: 1;
9262 unsigned LC3G4D4N
: 1;
9263 unsigned LC3G4D4T
: 1;
9279 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
9281 #define _CLC3GLS3_LC3G4D1N 0x01
9282 #define _CLC3GLS3_G4D1N 0x01
9283 #define _CLC3GLS3_LC3G4D1T 0x02
9284 #define _CLC3GLS3_G4D1T 0x02
9285 #define _CLC3GLS3_LC3G4D2N 0x04
9286 #define _CLC3GLS3_G4D2N 0x04
9287 #define _CLC3GLS3_LC3G4D2T 0x08
9288 #define _CLC3GLS3_G4D2T 0x08
9289 #define _CLC3GLS3_LC3G4D3N 0x10
9290 #define _CLC3GLS3_G4D3N 0x10
9291 #define _CLC3GLS3_LC3G4D3T 0x20
9292 #define _CLC3GLS3_G4D3T 0x20
9293 #define _CLC3GLS3_LC3G4D4N 0x40
9294 #define _CLC3GLS3_G4D4N 0x40
9295 #define _CLC3GLS3_LC3G4D4T 0x80
9296 #define _CLC3GLS3_G4D4T 0x80
9298 //==============================================================================
9301 //==============================================================================
9304 extern __at(0x0F2E) __sfr CLC4CON
;
9310 unsigned LC4MODE0
: 1;
9311 unsigned LC4MODE1
: 1;
9312 unsigned LC4MODE2
: 1;
9313 unsigned LC4INTN
: 1;
9314 unsigned LC4INTP
: 1;
9315 unsigned LC4OUT
: 1;
9340 unsigned LC4MODE
: 3;
9345 extern __at(0x0F2E) volatile __CLC4CONbits_t CLC4CONbits
;
9347 #define _CLC4CON_LC4MODE0 0x01
9348 #define _CLC4CON_MODE0 0x01
9349 #define _CLC4CON_LC4MODE1 0x02
9350 #define _CLC4CON_MODE1 0x02
9351 #define _CLC4CON_LC4MODE2 0x04
9352 #define _CLC4CON_MODE2 0x04
9353 #define _CLC4CON_LC4INTN 0x08
9354 #define _CLC4CON_INTN 0x08
9355 #define _CLC4CON_LC4INTP 0x10
9356 #define _CLC4CON_INTP 0x10
9357 #define _CLC4CON_LC4OUT 0x20
9358 #define _CLC4CON_OUT 0x20
9359 #define _CLC4CON_LC4EN 0x80
9360 #define _CLC4CON_EN 0x80
9362 //==============================================================================
9365 //==============================================================================
9368 extern __at(0x0F2F) __sfr CLC4POL
;
9374 unsigned LC4G1POL
: 1;
9375 unsigned LC4G2POL
: 1;
9376 unsigned LC4G3POL
: 1;
9377 unsigned LC4G4POL
: 1;
9381 unsigned LC4POL
: 1;
9397 extern __at(0x0F2F) volatile __CLC4POLbits_t CLC4POLbits
;
9399 #define _CLC4POL_LC4G1POL 0x01
9400 #define _CLC4POL_G1POL 0x01
9401 #define _CLC4POL_LC4G2POL 0x02
9402 #define _CLC4POL_G2POL 0x02
9403 #define _CLC4POL_LC4G3POL 0x04
9404 #define _CLC4POL_G3POL 0x04
9405 #define _CLC4POL_LC4G4POL 0x08
9406 #define _CLC4POL_G4POL 0x08
9407 #define _CLC4POL_LC4POL 0x80
9408 #define _CLC4POL_POL 0x80
9410 //==============================================================================
9413 //==============================================================================
9416 extern __at(0x0F30) __sfr CLC4SEL0
;
9422 unsigned LC4D1S0
: 1;
9423 unsigned LC4D1S1
: 1;
9424 unsigned LC4D1S2
: 1;
9425 unsigned LC4D1S3
: 1;
9426 unsigned LC4D1S4
: 1;
9427 unsigned LC4D1S5
: 1;
9446 unsigned LC4D1S
: 6;
9457 extern __at(0x0F30) volatile __CLC4SEL0bits_t CLC4SEL0bits
;
9459 #define _CLC4SEL0_LC4D1S0 0x01
9460 #define _CLC4SEL0_D1S0 0x01
9461 #define _CLC4SEL0_LC4D1S1 0x02
9462 #define _CLC4SEL0_D1S1 0x02
9463 #define _CLC4SEL0_LC4D1S2 0x04
9464 #define _CLC4SEL0_D1S2 0x04
9465 #define _CLC4SEL0_LC4D1S3 0x08
9466 #define _CLC4SEL0_D1S3 0x08
9467 #define _CLC4SEL0_LC4D1S4 0x10
9468 #define _CLC4SEL0_D1S4 0x10
9469 #define _CLC4SEL0_LC4D1S5 0x20
9470 #define _CLC4SEL0_D1S5 0x20
9472 //==============================================================================
9475 //==============================================================================
9478 extern __at(0x0F31) __sfr CLC4SEL1
;
9484 unsigned LC4D2S0
: 1;
9485 unsigned LC4D2S1
: 1;
9486 unsigned LC4D2S2
: 1;
9487 unsigned LC4D2S3
: 1;
9488 unsigned LC4D2S4
: 1;
9489 unsigned LC4D2S5
: 1;
9514 unsigned LC4D2S
: 6;
9519 extern __at(0x0F31) volatile __CLC4SEL1bits_t CLC4SEL1bits
;
9521 #define _CLC4SEL1_LC4D2S0 0x01
9522 #define _CLC4SEL1_D2S0 0x01
9523 #define _CLC4SEL1_LC4D2S1 0x02
9524 #define _CLC4SEL1_D2S1 0x02
9525 #define _CLC4SEL1_LC4D2S2 0x04
9526 #define _CLC4SEL1_D2S2 0x04
9527 #define _CLC4SEL1_LC4D2S3 0x08
9528 #define _CLC4SEL1_D2S3 0x08
9529 #define _CLC4SEL1_LC4D2S4 0x10
9530 #define _CLC4SEL1_D2S4 0x10
9531 #define _CLC4SEL1_LC4D2S5 0x20
9532 #define _CLC4SEL1_D2S5 0x20
9534 //==============================================================================
9537 //==============================================================================
9540 extern __at(0x0F32) __sfr CLC4SEL2
;
9546 unsigned LC4D3S0
: 1;
9547 unsigned LC4D3S1
: 1;
9548 unsigned LC4D3S2
: 1;
9549 unsigned LC4D3S3
: 1;
9550 unsigned LC4D3S4
: 1;
9551 unsigned LC4D3S5
: 1;
9570 unsigned LC4D3S
: 6;
9581 extern __at(0x0F32) volatile __CLC4SEL2bits_t CLC4SEL2bits
;
9583 #define _CLC4SEL2_LC4D3S0 0x01
9584 #define _CLC4SEL2_D3S0 0x01
9585 #define _CLC4SEL2_LC4D3S1 0x02
9586 #define _CLC4SEL2_D3S1 0x02
9587 #define _CLC4SEL2_LC4D3S2 0x04
9588 #define _CLC4SEL2_D3S2 0x04
9589 #define _CLC4SEL2_LC4D3S3 0x08
9590 #define _CLC4SEL2_D3S3 0x08
9591 #define _CLC4SEL2_LC4D3S4 0x10
9592 #define _CLC4SEL2_D3S4 0x10
9593 #define _CLC4SEL2_LC4D3S5 0x20
9594 #define _CLC4SEL2_D3S5 0x20
9596 //==============================================================================
9599 //==============================================================================
9602 extern __at(0x0F33) __sfr CLC4SEL3
;
9608 unsigned LC4D4S0
: 1;
9609 unsigned LC4D4S1
: 1;
9610 unsigned LC4D4S2
: 1;
9611 unsigned LC4D4S3
: 1;
9612 unsigned LC4D4S4
: 1;
9613 unsigned LC4D4S5
: 1;
9638 unsigned LC4D4S
: 6;
9643 extern __at(0x0F33) volatile __CLC4SEL3bits_t CLC4SEL3bits
;
9645 #define _CLC4SEL3_LC4D4S0 0x01
9646 #define _CLC4SEL3_D4S0 0x01
9647 #define _CLC4SEL3_LC4D4S1 0x02
9648 #define _CLC4SEL3_D4S1 0x02
9649 #define _CLC4SEL3_LC4D4S2 0x04
9650 #define _CLC4SEL3_D4S2 0x04
9651 #define _CLC4SEL3_LC4D4S3 0x08
9652 #define _CLC4SEL3_D4S3 0x08
9653 #define _CLC4SEL3_LC4D4S4 0x10
9654 #define _CLC4SEL3_D4S4 0x10
9655 #define _CLC4SEL3_LC4D4S5 0x20
9656 #define _CLC4SEL3_D4S5 0x20
9658 //==============================================================================
9661 //==============================================================================
9664 extern __at(0x0F34) __sfr CLC4GLS0
;
9670 unsigned LC4G1D1N
: 1;
9671 unsigned LC4G1D1T
: 1;
9672 unsigned LC4G1D2N
: 1;
9673 unsigned LC4G1D2T
: 1;
9674 unsigned LC4G1D3N
: 1;
9675 unsigned LC4G1D3T
: 1;
9676 unsigned LC4G1D4N
: 1;
9677 unsigned LC4G1D4T
: 1;
9693 extern __at(0x0F34) volatile __CLC4GLS0bits_t CLC4GLS0bits
;
9695 #define _CLC4GLS0_LC4G1D1N 0x01
9696 #define _CLC4GLS0_D1N 0x01
9697 #define _CLC4GLS0_LC4G1D1T 0x02
9698 #define _CLC4GLS0_D1T 0x02
9699 #define _CLC4GLS0_LC4G1D2N 0x04
9700 #define _CLC4GLS0_D2N 0x04
9701 #define _CLC4GLS0_LC4G1D2T 0x08
9702 #define _CLC4GLS0_D2T 0x08
9703 #define _CLC4GLS0_LC4G1D3N 0x10
9704 #define _CLC4GLS0_D3N 0x10
9705 #define _CLC4GLS0_LC4G1D3T 0x20
9706 #define _CLC4GLS0_D3T 0x20
9707 #define _CLC4GLS0_LC4G1D4N 0x40
9708 #define _CLC4GLS0_D4N 0x40
9709 #define _CLC4GLS0_LC4G1D4T 0x80
9710 #define _CLC4GLS0_D4T 0x80
9712 //==============================================================================
9715 //==============================================================================
9718 extern __at(0x0F35) __sfr CLC4GLS1
;
9724 unsigned LC4G2D1N
: 1;
9725 unsigned LC4G2D1T
: 1;
9726 unsigned LC4G2D2N
: 1;
9727 unsigned LC4G2D2T
: 1;
9728 unsigned LC4G2D3N
: 1;
9729 unsigned LC4G2D3T
: 1;
9730 unsigned LC4G2D4N
: 1;
9731 unsigned LC4G2D4T
: 1;
9747 extern __at(0x0F35) volatile __CLC4GLS1bits_t CLC4GLS1bits
;
9749 #define _CLC4GLS1_LC4G2D1N 0x01
9750 #define _CLC4GLS1_D1N 0x01
9751 #define _CLC4GLS1_LC4G2D1T 0x02
9752 #define _CLC4GLS1_D1T 0x02
9753 #define _CLC4GLS1_LC4G2D2N 0x04
9754 #define _CLC4GLS1_D2N 0x04
9755 #define _CLC4GLS1_LC4G2D2T 0x08
9756 #define _CLC4GLS1_D2T 0x08
9757 #define _CLC4GLS1_LC4G2D3N 0x10
9758 #define _CLC4GLS1_D3N 0x10
9759 #define _CLC4GLS1_LC4G2D3T 0x20
9760 #define _CLC4GLS1_D3T 0x20
9761 #define _CLC4GLS1_LC4G2D4N 0x40
9762 #define _CLC4GLS1_D4N 0x40
9763 #define _CLC4GLS1_LC4G2D4T 0x80
9764 #define _CLC4GLS1_D4T 0x80
9766 //==============================================================================
9769 //==============================================================================
9772 extern __at(0x0F36) __sfr CLC4GLS2
;
9778 unsigned LC4G3D1N
: 1;
9779 unsigned LC4G3D1T
: 1;
9780 unsigned LC4G3D2N
: 1;
9781 unsigned LC4G3D2T
: 1;
9782 unsigned LC4G3D3N
: 1;
9783 unsigned LC4G3D3T
: 1;
9784 unsigned LC4G3D4N
: 1;
9785 unsigned LC4G3D4T
: 1;
9801 extern __at(0x0F36) volatile __CLC4GLS2bits_t CLC4GLS2bits
;
9803 #define _CLC4GLS2_LC4G3D1N 0x01
9804 #define _CLC4GLS2_D1N 0x01
9805 #define _CLC4GLS2_LC4G3D1T 0x02
9806 #define _CLC4GLS2_D1T 0x02
9807 #define _CLC4GLS2_LC4G3D2N 0x04
9808 #define _CLC4GLS2_D2N 0x04
9809 #define _CLC4GLS2_LC4G3D2T 0x08
9810 #define _CLC4GLS2_D2T 0x08
9811 #define _CLC4GLS2_LC4G3D3N 0x10
9812 #define _CLC4GLS2_D3N 0x10
9813 #define _CLC4GLS2_LC4G3D3T 0x20
9814 #define _CLC4GLS2_D3T 0x20
9815 #define _CLC4GLS2_LC4G3D4N 0x40
9816 #define _CLC4GLS2_D4N 0x40
9817 #define _CLC4GLS2_LC4G3D4T 0x80
9818 #define _CLC4GLS2_D4T 0x80
9820 //==============================================================================
9823 //==============================================================================
9826 extern __at(0x0F37) __sfr CLC4GLS3
;
9832 unsigned LC4G4D1N
: 1;
9833 unsigned LC4G4D1T
: 1;
9834 unsigned LC4G4D2N
: 1;
9835 unsigned LC4G4D2T
: 1;
9836 unsigned LC4G4D3N
: 1;
9837 unsigned LC4G4D3T
: 1;
9838 unsigned LC4G4D4N
: 1;
9839 unsigned LC4G4D4T
: 1;
9855 extern __at(0x0F37) volatile __CLC4GLS3bits_t CLC4GLS3bits
;
9857 #define _CLC4GLS3_LC4G4D1N 0x01
9858 #define _CLC4GLS3_G4D1N 0x01
9859 #define _CLC4GLS3_LC4G4D1T 0x02
9860 #define _CLC4GLS3_G4D1T 0x02
9861 #define _CLC4GLS3_LC4G4D2N 0x04
9862 #define _CLC4GLS3_G4D2N 0x04
9863 #define _CLC4GLS3_LC4G4D2T 0x08
9864 #define _CLC4GLS3_G4D2T 0x08
9865 #define _CLC4GLS3_LC4G4D3N 0x10
9866 #define _CLC4GLS3_G4D3N 0x10
9867 #define _CLC4GLS3_LC4G4D3T 0x20
9868 #define _CLC4GLS3_G4D3T 0x20
9869 #define _CLC4GLS3_LC4G4D4N 0x40
9870 #define _CLC4GLS3_G4D4N 0x40
9871 #define _CLC4GLS3_LC4G4D4T 0x80
9872 #define _CLC4GLS3_G4D4T 0x80
9874 //==============================================================================
9877 //==============================================================================
9880 extern __at(0x0FE4) __sfr STATUS_SHAD
;
9884 unsigned C_SHAD
: 1;
9885 unsigned DC_SHAD
: 1;
9886 unsigned Z_SHAD
: 1;
9892 } __STATUS_SHADbits_t
;
9894 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
9896 #define _C_SHAD 0x01
9897 #define _DC_SHAD 0x02
9898 #define _Z_SHAD 0x04
9900 //==============================================================================
9902 extern __at(0x0FE5) __sfr WREG_SHAD
;
9903 extern __at(0x0FE6) __sfr BSR_SHAD
;
9904 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
9905 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
9906 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
9907 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
9908 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
9909 extern __at(0x0FED) __sfr STKPTR
;
9910 extern __at(0x0FEE) __sfr TOSL
;
9911 extern __at(0x0FEF) __sfr TOSH
;
9913 //==============================================================================
9915 // Configuration Bits
9917 //==============================================================================
9919 #define _CONFIG1 0x8007
9920 #define _CONFIG2 0x8008
9921 #define _CONFIG3 0x8009
9922 #define _CONFIG4 0x800A
9924 //----------------------------- CONFIG1 Options -------------------------------
9926 #define _FEXTOSC_LP 0x3FF8 // LP (crystal oscillator) optimized for 32.768 kHz.
9927 #define _FEXTOSC_XT 0x3FF9 // XT (crystal oscillator) from 100 kHz to 4 MHz.
9928 #define _FEXTOSC_HS 0x3FFA // HS (crystal oscillator) above 4 MHz.
9929 #define _FEXTOSC_OFF 0x3FFC // Oscillator not enabled.
9930 #define _FEXTOSC_ECL 0x3FFD // EC (external clock) below 100 kHz.
9931 #define _FEXTOSC_ECM 0x3FFE // EC (external clock) for 100 kHz to 8 MHz.
9932 #define _FEXTOSC_ECH 0x3FFF // EC (external clock) above 8 MHz;.
9933 #define _RSTOSC_HFINT32 0x3F8F // HFINTOSC with 2x PLL (32MHz).
9934 #define _RSTOSC_EXT4X 0x3F9F // EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits.
9935 #define _RSTOSC_SOSC 0x3FBF // SOSC (31kHz).
9936 #define _RSTOSC_LFINT 0x3FCF // LFINTOSC (31kHz).
9937 #define _RSTOSC_HFINT1 0x3FEF // HFINTOSC (1MHz).
9938 #define _RSTOSC_EXT1X 0x3FFF // EXTOSC operating per FEXTOSC bits.
9939 #define _CLKOUTEN_ON 0x3EFF // CLKOUT function is enabled; FOSC/4 clock appears at OSC2.
9940 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled; I/O or oscillator function on OSC2.
9941 #define _CSWEN_OFF 0x37FF // The NOSC and NDIV bits cannot be changed by user software.
9942 #define _CSWEN_ON 0x3FFF // Writing to NOSC and NDIV is allowed.
9943 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
9944 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
9946 //----------------------------- CONFIG2 Options -------------------------------
9948 #define _MCLRE_OFF 0x3FFE // MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of port pin's WPU control bit.
9949 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR; Weak pull-up enabled.
9950 #define _PWRTE_ON 0x3FFD // PWRT enabled.
9951 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
9952 #define _WDTE_OFF 0x3FF3 // WDT disabled; SWDTEN is ignored.
9953 #define _WDTE_SWDTEN 0x3FF7 // WDT controlled by the SWDTEN bit in the WDTCON register.
9954 #define _WDTE_SLEEP 0x3FFB // WDT enabled while running and disabled in SLEEP/IDLE; SWDTEN is ignored.
9955 #define _WDTE_ON 0x3FFF // WDT enabled, SWDTEN is ignored.
9956 #define _LPBOREN_ON 0x3FDF // ULPBOR enabled.
9957 #define _LPBOREN_OFF 0x3FFF // ULPBOR disabled.
9958 #define _BOREN_OFF 0x3F3F // Brown-out Reset disabled.
9959 #define _BOREN_SBOREN 0x3F7F // Brown-out Reset enabled according to SBOREN.
9960 #define _BOREN_SLEEP 0x3FBF // Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored.
9961 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled, SBOREN bit ignored.
9962 #define _BORV_HIGH 0x3DFF // Brown-out voltage (Vbor) set to 2.7V.
9963 #define _BORV_LOW 0x3FFF // Brown-out voltage (Vbor) set to 2.45V.
9964 #define _PPS1WAY_OFF 0x37FF // The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence).
9965 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle.
9966 #define _STVREN_OFF 0x2FFF // Stack Overflow or Underflow will not cause a Reset.
9967 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
9968 #define _DEBUG_ON 0x1FFF // Background debugger enabled.
9969 #define _DEBUG_OFF 0x3FFF // Background debugger disabled.
9971 //----------------------------- CONFIG3 Options -------------------------------
9973 #define _WRT_ALL 0x3FFC // 0000h to 0FFFh write protected, no addresses may be modified.
9974 #define _WRT_HALF 0x3FFD // 0000h to 03FFh write-protected, 0400h to 0FFFh may be modified.
9975 #define _WRT_BOOT 0x3FFE // 0000h to 01FFh write-protected, 0200h to 0FFFh may be modified.
9976 #define _WRT_OFF 0x3FFF // Write protection off.
9977 #define _LVP_OFF 0x1FFF // High Voltage on MCLR/VPP must be used for programming.
9978 #define _LVP_ON 0x3FFF // Low Voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.
9980 //----------------------------- CONFIG4 Options -------------------------------
9982 #define _CP_ON 0x3FFE // User NVM code protection enabled.
9983 #define _CP_OFF 0x3FFF // User NVM code protection disabled.
9984 #define _CPD_ON 0x3FFD // Data NVM code protection enabled.
9985 #define _CPD_OFF 0x3FFF // Data NVM code protection disabled.
9987 //==============================================================================
9989 #define _DEVID1 0x8006
9991 #define _IDLOC0 0x8000
9992 #define _IDLOC1 0x8001
9993 #define _IDLOC2 0x8002
9994 #define _IDLOC3 0x8003
9996 //==============================================================================
9998 #ifndef NO_BIT_DEFINES
10000 #define ADACT0 ADACTbits.ADACT0 // bit 0
10001 #define ADACT1 ADACTbits.ADACT1 // bit 1
10002 #define ADACT2 ADACTbits.ADACT2 // bit 2
10003 #define ADACT3 ADACTbits.ADACT3 // bit 3
10004 #define ADACT4 ADACTbits.ADACT4 // bit 4
10006 #define ADON ADCON0bits.ADON // bit 0
10007 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
10008 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
10009 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
10010 #define CHS0 ADCON0bits.CHS0 // bit 2
10011 #define CHS1 ADCON0bits.CHS1 // bit 3
10012 #define CHS2 ADCON0bits.CHS2 // bit 4
10013 #define CHS3 ADCON0bits.CHS3 // bit 5
10014 #define CHS4 ADCON0bits.CHS4 // bit 6
10015 #define CHS5 ADCON0bits.CHS5 // bit 7
10017 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
10018 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
10019 #define ADNREF ADCON1bits.ADNREF // bit 2
10020 #define ADCS0 ADCON1bits.ADCS0 // bit 4
10021 #define ADCS1 ADCON1bits.ADCS1 // bit 5
10022 #define ADCS2 ADCON1bits.ADCS2 // bit 6
10023 #define ADFM ADCON1bits.ADFM // bit 7
10025 #define ANSA0 ANSELAbits.ANSA0 // bit 0
10026 #define ANSA1 ANSELAbits.ANSA1 // bit 1
10027 #define ANSA2 ANSELAbits.ANSA2 // bit 2
10028 #define ANSA4 ANSELAbits.ANSA4 // bit 4
10029 #define ANSA5 ANSELAbits.ANSA5 // bit 5
10031 #define ANSC0 ANSELCbits.ANSC0 // bit 0
10032 #define ANSC1 ANSELCbits.ANSC1 // bit 1
10033 #define ANSC2 ANSELCbits.ANSC2 // bit 2
10034 #define ANSC3 ANSELCbits.ANSC3 // bit 3
10035 #define ANSC4 ANSELCbits.ANSC4 // bit 4
10036 #define ANSC5 ANSELCbits.ANSC5 // bit 5
10038 #define ABDEN BAUD1CONbits.ABDEN // bit 0
10039 #define WUE BAUD1CONbits.WUE // bit 1
10040 #define BRG16 BAUD1CONbits.BRG16 // bit 3
10041 #define SCKP BAUD1CONbits.SCKP // bit 4
10042 #define RCIDL BAUD1CONbits.RCIDL // bit 6
10043 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
10045 #define BORRDY BORCONbits.BORRDY // bit 0
10046 #define SBOREN BORCONbits.SBOREN // bit 7
10048 #define BSR0 BSRbits.BSR0 // bit 0
10049 #define BSR1 BSRbits.BSR1 // bit 1
10050 #define BSR2 BSRbits.BSR2 // bit 2
10051 #define BSR3 BSRbits.BSR3 // bit 3
10052 #define BSR4 BSRbits.BSR4 // bit 4
10054 #define CCDS0 CCDCONbits.CCDS0 // bit 0
10055 #define CCDS1 CCDCONbits.CCDS1 // bit 1
10056 #define CCDEN CCDCONbits.CCDEN // bit 7
10058 #define CCDNA0 CCDNAbits.CCDNA0 // bit 0
10059 #define CCDNA1 CCDNAbits.CCDNA1 // bit 1
10060 #define CCDNA2 CCDNAbits.CCDNA2 // bit 2
10061 #define CCDNA4 CCDNAbits.CCDNA4 // bit 4
10062 #define CCDNA5 CCDNAbits.CCDNA5 // bit 5
10064 #define CCDNC0 CCDNCbits.CCDNC0 // bit 0
10065 #define CCDNC1 CCDNCbits.CCDNC1 // bit 1
10066 #define CCDNC2 CCDNCbits.CCDNC2 // bit 2
10067 #define CCDNC3 CCDNCbits.CCDNC3 // bit 3
10068 #define CCDNC4 CCDNCbits.CCDNC4 // bit 4
10069 #define CCDNC5 CCDNCbits.CCDNC5 // bit 5
10071 #define CCDPA0 CCDPAbits.CCDPA0 // bit 0
10072 #define CCDPA1 CCDPAbits.CCDPA1 // bit 1
10073 #define CCDPA2 CCDPAbits.CCDPA2 // bit 2
10074 #define CCDPA4 CCDPAbits.CCDPA4 // bit 4
10075 #define CCDPA5 CCDPAbits.CCDPA5 // bit 5
10077 #define CCDPC0 CCDPCbits.CCDPC0 // bit 0
10078 #define CCDPC1 CCDPCbits.CCDPC1 // bit 1
10079 #define CCDPC2 CCDPCbits.CCDPC2 // bit 2
10080 #define CCDPC3 CCDPCbits.CCDPC3 // bit 3
10081 #define CCDPC4 CCDPCbits.CCDPC4 // bit 4
10082 #define CCDPC5 CCDPCbits.CCDPC5 // bit 5
10084 #define CCP1CTS0 CCP1CAPbits.CCP1CTS0 // bit 0
10085 #define CCP1CTS1 CCP1CAPbits.CCP1CTS1 // bit 1
10086 #define CCP1CTS2 CCP1CAPbits.CCP1CTS2 // bit 2
10087 #define CCP1CTS3 CCP1CAPbits.CCP1CTS3 // bit 3
10089 #define CCP1MODE0 CCP1CONbits.CCP1MODE0 // bit 0
10090 #define CCP1MODE1 CCP1CONbits.CCP1MODE1 // bit 1
10091 #define CCP1MODE2 CCP1CONbits.CCP1MODE2 // bit 2
10092 #define CCP1MODE3 CCP1CONbits.CCP1MODE3 // bit 3
10093 #define CCP1FMT CCP1CONbits.CCP1FMT // bit 4
10094 #define CCP1OUT CCP1CONbits.CCP1OUT // bit 5
10095 #define CCP1EN CCP1CONbits.CCP1EN // bit 7
10097 #define CCP1PPS0 CCP1PPSbits.CCP1PPS0 // bit 0
10098 #define CCP1PPS1 CCP1PPSbits.CCP1PPS1 // bit 1
10099 #define CCP1PPS2 CCP1PPSbits.CCP1PPS2 // bit 2
10100 #define CCP1PPS3 CCP1PPSbits.CCP1PPS3 // bit 3
10101 #define CCP1PPS4 CCP1PPSbits.CCP1PPS4 // bit 4
10103 #define CCP2CTS0 CCP2CAPbits.CCP2CTS0 // bit 0
10104 #define CCP2CTS1 CCP2CAPbits.CCP2CTS1 // bit 1
10105 #define CCP2CTS2 CCP2CAPbits.CCP2CTS2 // bit 2
10106 #define CCP2CTS3 CCP2CAPbits.CCP2CTS3 // bit 3
10108 #define CCP2MODE0 CCP2CONbits.CCP2MODE0 // bit 0
10109 #define CCP2MODE1 CCP2CONbits.CCP2MODE1 // bit 1
10110 #define CCP2MODE2 CCP2CONbits.CCP2MODE2 // bit 2
10111 #define CCP2MODE3 CCP2CONbits.CCP2MODE3 // bit 3
10112 #define CCP2FMT CCP2CONbits.CCP2FMT // bit 4
10113 #define CCP2OUT CCP2CONbits.CCP2OUT // bit 5
10114 #define CCP2EN CCP2CONbits.CCP2EN // bit 7
10116 #define CCP2PPS0 CCP2PPSbits.CCP2PPS0 // bit 0
10117 #define CCP2PPS1 CCP2PPSbits.CCP2PPS1 // bit 1
10118 #define CCP2PPS2 CCP2PPSbits.CCP2PPS2 // bit 2
10119 #define CCP2PPS3 CCP2PPSbits.CCP2PPS3 // bit 3
10120 #define CCP2PPS4 CCP2PPSbits.CCP2PPS4 // bit 4
10122 #define CCP3CTS0 CCP3CAPbits.CCP3CTS0 // bit 0
10123 #define CCP3CTS1 CCP3CAPbits.CCP3CTS1 // bit 1
10124 #define CCP3CTS2 CCP3CAPbits.CCP3CTS2 // bit 2
10125 #define CCP3CTS3 CCP3CAPbits.CCP3CTS3 // bit 3
10127 #define CCP3MODE0 CCP3CONbits.CCP3MODE0 // bit 0
10128 #define CCP3MODE1 CCP3CONbits.CCP3MODE1 // bit 1
10129 #define CCP3MODE2 CCP3CONbits.CCP3MODE2 // bit 2
10130 #define CCP3MODE3 CCP3CONbits.CCP3MODE3 // bit 3
10131 #define CCP3FMT CCP3CONbits.CCP3FMT // bit 4
10132 #define CCP3OUT CCP3CONbits.CCP3OUT // bit 5
10133 #define CCP3EN CCP3CONbits.CCP3EN // bit 7
10135 #define CCP3PPS0 CCP3PPSbits.CCP3PPS0 // bit 0
10136 #define CCP3PPS1 CCP3PPSbits.CCP3PPS1 // bit 1
10137 #define CCP3PPS2 CCP3PPSbits.CCP3PPS2 // bit 2
10138 #define CCP3PPS3 CCP3PPSbits.CCP3PPS3 // bit 3
10139 #define CCP3PPS4 CCP3PPSbits.CCP3PPS4 // bit 4
10141 #define CCP4CTS0 CCP4CAPbits.CCP4CTS0 // bit 0
10142 #define CCP4CTS1 CCP4CAPbits.CCP4CTS1 // bit 1
10143 #define CCP4CTS2 CCP4CAPbits.CCP4CTS2 // bit 2
10144 #define CCP4CTS3 CCP4CAPbits.CCP4CTS3 // bit 3
10146 #define CCP4MODE0 CCP4CONbits.CCP4MODE0 // bit 0
10147 #define CCP4MODE1 CCP4CONbits.CCP4MODE1 // bit 1
10148 #define CCP4MODE2 CCP4CONbits.CCP4MODE2 // bit 2
10149 #define CCP4MODE3 CCP4CONbits.CCP4MODE3 // bit 3
10150 #define CCP4FMT CCP4CONbits.CCP4FMT // bit 4
10151 #define CCP4OUT CCP4CONbits.CCP4OUT // bit 5
10152 #define CCP4EN CCP4CONbits.CCP4EN // bit 7
10154 #define CCP4PPS0 CCP4PPSbits.CCP4PPS0 // bit 0
10155 #define CCP4PPS1 CCP4PPSbits.CCP4PPS1 // bit 1
10156 #define CCP4PPS2 CCP4PPSbits.CCP4PPS2 // bit 2
10157 #define CCP4PPS3 CCP4PPSbits.CCP4PPS3 // bit 3
10158 #define CCP4PPS4 CCP4PPSbits.CCP4PPS4 // bit 4
10160 #define C1TSEL0 CCPTMRSbits.C1TSEL0 // bit 0
10161 #define C1TSEL1 CCPTMRSbits.C1TSEL1 // bit 1
10162 #define C2TSEL0 CCPTMRSbits.C2TSEL0 // bit 2
10163 #define C2TSEL1 CCPTMRSbits.C2TSEL1 // bit 3
10164 #define C3TSEL0 CCPTMRSbits.C3TSEL0 // bit 4
10165 #define C3TSEL1 CCPTMRSbits.C3TSEL1 // bit 5
10166 #define C4TSEL0 CCPTMRSbits.C4TSEL0 // bit 6
10167 #define C4TSEL1 CCPTMRSbits.C4TSEL1 // bit 7
10169 #define LC1MODE0 CLC1CONbits.LC1MODE0 // bit 0, shadows bit in CLC1CONbits
10170 #define MODE0 CLC1CONbits.MODE0 // bit 0, shadows bit in CLC1CONbits
10171 #define LC1MODE1 CLC1CONbits.LC1MODE1 // bit 1, shadows bit in CLC1CONbits
10172 #define MODE1 CLC1CONbits.MODE1 // bit 1, shadows bit in CLC1CONbits
10173 #define LC1MODE2 CLC1CONbits.LC1MODE2 // bit 2, shadows bit in CLC1CONbits
10174 #define MODE2 CLC1CONbits.MODE2 // bit 2, shadows bit in CLC1CONbits
10175 #define LC1INTN CLC1CONbits.LC1INTN // bit 3, shadows bit in CLC1CONbits
10176 #define INTN CLC1CONbits.INTN // bit 3, shadows bit in CLC1CONbits
10177 #define LC1INTP CLC1CONbits.LC1INTP // bit 4, shadows bit in CLC1CONbits
10178 #define INTP CLC1CONbits.INTP // bit 4, shadows bit in CLC1CONbits
10179 #define LC1OUT CLC1CONbits.LC1OUT // bit 5, shadows bit in CLC1CONbits
10180 #define OUT CLC1CONbits.OUT // bit 5, shadows bit in CLC1CONbits
10181 #define LC1EN CLC1CONbits.LC1EN // bit 7, shadows bit in CLC1CONbits
10182 #define EN CLC1CONbits.EN // bit 7, shadows bit in CLC1CONbits
10184 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
10185 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
10186 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
10187 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
10188 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
10189 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
10190 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
10191 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
10192 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
10193 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
10194 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
10195 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
10196 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
10197 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
10198 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
10199 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
10201 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
10202 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
10203 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
10204 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
10205 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
10206 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
10207 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
10208 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
10209 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
10210 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
10211 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
10212 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
10213 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
10214 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
10215 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
10216 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
10218 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
10219 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
10220 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
10221 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
10222 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
10223 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
10224 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
10225 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
10226 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
10227 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
10229 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
10230 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
10231 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
10232 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
10233 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
10234 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
10235 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
10236 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
10237 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
10238 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
10239 #define LC1D1S5 CLC1SEL0bits.LC1D1S5 // bit 5, shadows bit in CLC1SEL0bits
10240 #define D1S5 CLC1SEL0bits.D1S5 // bit 5, shadows bit in CLC1SEL0bits
10242 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
10243 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
10244 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
10245 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
10246 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
10247 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
10248 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
10249 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
10250 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
10251 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
10252 #define LC1D2S5 CLC1SEL1bits.LC1D2S5 // bit 5, shadows bit in CLC1SEL1bits
10253 #define D2S5 CLC1SEL1bits.D2S5 // bit 5, shadows bit in CLC1SEL1bits
10255 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
10256 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
10257 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
10258 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
10259 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
10260 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
10261 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
10262 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
10263 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
10264 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
10265 #define LC1D3S5 CLC1SEL2bits.LC1D3S5 // bit 5, shadows bit in CLC1SEL2bits
10266 #define D3S5 CLC1SEL2bits.D3S5 // bit 5, shadows bit in CLC1SEL2bits
10268 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
10269 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
10270 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
10271 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
10272 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
10273 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
10274 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
10275 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
10276 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
10277 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
10278 #define LC1D4S5 CLC1SEL3bits.LC1D4S5 // bit 5, shadows bit in CLC1SEL3bits
10279 #define D4S5 CLC1SEL3bits.D4S5 // bit 5, shadows bit in CLC1SEL3bits
10281 #define MLC1OUT CLCDATAbits.MLC1OUT // bit 0
10282 #define MLC2OUT CLCDATAbits.MLC2OUT // bit 1
10283 #define MLC3OUT CLCDATAbits.MLC3OUT // bit 2
10284 #define MLC4OUT CLCDATAbits.MLC4OUT // bit 3
10286 #define CLCIN0PPS0 CLCIN0PPSbits.CLCIN0PPS0 // bit 0
10287 #define CLCIN0PPS1 CLCIN0PPSbits.CLCIN0PPS1 // bit 1
10288 #define CLCIN0PPS2 CLCIN0PPSbits.CLCIN0PPS2 // bit 2
10289 #define CLCIN0PPS3 CLCIN0PPSbits.CLCIN0PPS3 // bit 3
10290 #define CLCIN0PPS4 CLCIN0PPSbits.CLCIN0PPS4 // bit 4
10292 #define CLCIN1PPS0 CLCIN1PPSbits.CLCIN1PPS0 // bit 0
10293 #define CLCIN1PPS1 CLCIN1PPSbits.CLCIN1PPS1 // bit 1
10294 #define CLCIN1PPS2 CLCIN1PPSbits.CLCIN1PPS2 // bit 2
10295 #define CLCIN1PPS3 CLCIN1PPSbits.CLCIN1PPS3 // bit 3
10296 #define CLCIN1PPS4 CLCIN1PPSbits.CLCIN1PPS4 // bit 4
10298 #define CLCIN2PPS0 CLCIN2PPSbits.CLCIN2PPS0 // bit 0
10299 #define CLCIN2PPS1 CLCIN2PPSbits.CLCIN2PPS1 // bit 1
10300 #define CLCIN2PPS2 CLCIN2PPSbits.CLCIN2PPS2 // bit 2
10301 #define CLCIN2PPS3 CLCIN2PPSbits.CLCIN2PPS3 // bit 3
10302 #define CLCIN2PPS4 CLCIN2PPSbits.CLCIN2PPS4 // bit 4
10304 #define CLCIN3PPS0 CLCIN3PPSbits.CLCIN3PPS0 // bit 0
10305 #define CLCIN3PPS1 CLCIN3PPSbits.CLCIN3PPS1 // bit 1
10306 #define CLCIN3PPS2 CLCIN3PPSbits.CLCIN3PPS2 // bit 2
10307 #define CLCIN3PPS3 CLCIN3PPSbits.CLCIN3PPS3 // bit 3
10308 #define CLCIN3PPS4 CLCIN3PPSbits.CLCIN3PPS4 // bit 4
10310 #define CLKRDIV0 CLKRCONbits.CLKRDIV0 // bit 0
10311 #define CLKRDIV1 CLKRCONbits.CLKRDIV1 // bit 1
10312 #define CLKRDIV2 CLKRCONbits.CLKRDIV2 // bit 2
10313 #define CLKRDC0 CLKRCONbits.CLKRDC0 // bit 3
10314 #define CLKRDC1 CLKRCONbits.CLKRDC1 // bit 4
10315 #define CLKREN CLKRCONbits.CLKREN // bit 7
10317 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
10318 #define C1HYS CM1CON0bits.C1HYS // bit 1
10319 #define C1SP CM1CON0bits.C1SP // bit 2
10320 #define C1POL CM1CON0bits.C1POL // bit 4
10321 #define C1OUT CM1CON0bits.C1OUT // bit 6
10322 #define C1ON CM1CON0bits.C1ON // bit 7
10324 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
10325 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
10326 #define C1NCH2 CM1CON1bits.C1NCH2 // bit 2
10327 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 3
10328 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 4
10329 #define C1PCH2 CM1CON1bits.C1PCH2 // bit 5
10330 #define C1INTN CM1CON1bits.C1INTN // bit 6
10331 #define C1INTP CM1CON1bits.C1INTP // bit 7
10333 #define C2SYNC CM2CON0bits.C2SYNC // bit 0
10334 #define C2HYS CM2CON0bits.C2HYS // bit 1
10335 #define C2SP CM2CON0bits.C2SP // bit 2
10336 #define C2POL CM2CON0bits.C2POL // bit 4
10337 #define C2OUT CM2CON0bits.C2OUT // bit 6
10338 #define C2ON CM2CON0bits.C2ON // bit 7
10340 #define C2NCH0 CM2CON1bits.C2NCH0 // bit 0
10341 #define C2NCH1 CM2CON1bits.C2NCH1 // bit 1
10342 #define C2NCH2 CM2CON1bits.C2NCH2 // bit 2
10343 #define C2PCH0 CM2CON1bits.C2PCH0 // bit 3
10344 #define C2PCH1 CM2CON1bits.C2PCH1 // bit 4
10345 #define C2PCH2 CM2CON1bits.C2PCH2 // bit 5
10346 #define C2INTN CM2CON1bits.C2INTN // bit 6
10347 #define C2INTP CM2CON1bits.C2INTP // bit 7
10349 #define MC1OUT CMOUTbits.MC1OUT // bit 0
10350 #define MC2OUT CMOUTbits.MC2OUT // bit 1
10352 #define DOZE0 CPUDOZEbits.DOZE0 // bit 0
10353 #define DOZE1 CPUDOZEbits.DOZE1 // bit 1
10354 #define DOZE2 CPUDOZEbits.DOZE2 // bit 2
10355 #define DOE CPUDOZEbits.DOE // bit 4
10356 #define ROI CPUDOZEbits.ROI // bit 5
10357 #define DOZEN CPUDOZEbits.DOZEN // bit 6
10358 #define IDLEN CPUDOZEbits.IDLEN // bit 7
10360 #define LSAC0 CWG1AS0bits.LSAC0 // bit 2, shadows bit in CWG1AS0bits
10361 #define CWG1LSAC0 CWG1AS0bits.CWG1LSAC0 // bit 2, shadows bit in CWG1AS0bits
10362 #define LSAC1 CWG1AS0bits.LSAC1 // bit 3, shadows bit in CWG1AS0bits
10363 #define CWG1LSAC1 CWG1AS0bits.CWG1LSAC1 // bit 3, shadows bit in CWG1AS0bits
10364 #define LSBD0 CWG1AS0bits.LSBD0 // bit 4, shadows bit in CWG1AS0bits
10365 #define CWG1LSBD0 CWG1AS0bits.CWG1LSBD0 // bit 4, shadows bit in CWG1AS0bits
10366 #define LSBD1 CWG1AS0bits.LSBD1 // bit 5, shadows bit in CWG1AS0bits
10367 #define CWG1LSBD1 CWG1AS0bits.CWG1LSBD1 // bit 5, shadows bit in CWG1AS0bits
10368 #define REN CWG1AS0bits.REN // bit 6, shadows bit in CWG1AS0bits
10369 #define CWG1REN CWG1AS0bits.CWG1REN // bit 6, shadows bit in CWG1AS0bits
10370 #define SHUTDOWN CWG1AS0bits.SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
10371 #define CWG1SHUTDOWN CWG1AS0bits.CWG1SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
10373 #define AS0E CWG1AS1bits.AS0E // bit 0
10374 #define AS1E CWG1AS1bits.AS1E // bit 1
10375 #define AS2E CWG1AS1bits.AS2E // bit 2
10376 #define AS3E CWG1AS1bits.AS3E // bit 3
10377 #define AS4E CWG1AS1bits.AS4E // bit 4
10379 #define CS CWG1CLKCONbits.CS // bit 0, shadows bit in CWG1CLKCONbits
10380 #define CWG1CS CWG1CLKCONbits.CWG1CS // bit 0, shadows bit in CWG1CLKCONbits
10382 #define POLA CWG1CON1bits.POLA // bit 0, shadows bit in CWG1CON1bits
10383 #define CWG1POLA CWG1CON1bits.CWG1POLA // bit 0, shadows bit in CWG1CON1bits
10384 #define POLB CWG1CON1bits.POLB // bit 1, shadows bit in CWG1CON1bits
10385 #define CWG1POLB CWG1CON1bits.CWG1POLB // bit 1, shadows bit in CWG1CON1bits
10386 #define POLC CWG1CON1bits.POLC // bit 2, shadows bit in CWG1CON1bits
10387 #define CWG1POLC CWG1CON1bits.CWG1POLC // bit 2, shadows bit in CWG1CON1bits
10388 #define POLD CWG1CON1bits.POLD // bit 3, shadows bit in CWG1CON1bits
10389 #define CWG1POLD CWG1CON1bits.CWG1POLD // bit 3, shadows bit in CWG1CON1bits
10390 #define IN CWG1CON1bits.IN // bit 5, shadows bit in CWG1CON1bits
10391 #define CWG1IN CWG1CON1bits.CWG1IN // bit 5, shadows bit in CWG1CON1bits
10393 #define CWG1DAT0 CWG1DATbits.CWG1DAT0 // bit 0
10394 #define CWG1DAT1 CWG1DATbits.CWG1DAT1 // bit 1
10395 #define CWG1DAT2 CWG1DATbits.CWG1DAT2 // bit 2
10396 #define CWG1DAT3 CWG1DATbits.CWG1DAT3 // bit 3
10398 #define DBF0 CWG1DBFbits.DBF0 // bit 0, shadows bit in CWG1DBFbits
10399 #define CWG1DBF0 CWG1DBFbits.CWG1DBF0 // bit 0, shadows bit in CWG1DBFbits
10400 #define DBF1 CWG1DBFbits.DBF1 // bit 1, shadows bit in CWG1DBFbits
10401 #define CWG1DBF1 CWG1DBFbits.CWG1DBF1 // bit 1, shadows bit in CWG1DBFbits
10402 #define DBF2 CWG1DBFbits.DBF2 // bit 2, shadows bit in CWG1DBFbits
10403 #define CWG1DBF2 CWG1DBFbits.CWG1DBF2 // bit 2, shadows bit in CWG1DBFbits
10404 #define DBF3 CWG1DBFbits.DBF3 // bit 3, shadows bit in CWG1DBFbits
10405 #define CWG1DBF3 CWG1DBFbits.CWG1DBF3 // bit 3, shadows bit in CWG1DBFbits
10406 #define DBF4 CWG1DBFbits.DBF4 // bit 4, shadows bit in CWG1DBFbits
10407 #define CWG1DBF4 CWG1DBFbits.CWG1DBF4 // bit 4, shadows bit in CWG1DBFbits
10408 #define DBF5 CWG1DBFbits.DBF5 // bit 5, shadows bit in CWG1DBFbits
10409 #define CWG1DBF5 CWG1DBFbits.CWG1DBF5 // bit 5, shadows bit in CWG1DBFbits
10411 #define DBR0 CWG1DBRbits.DBR0 // bit 0, shadows bit in CWG1DBRbits
10412 #define CWG1DBR0 CWG1DBRbits.CWG1DBR0 // bit 0, shadows bit in CWG1DBRbits
10413 #define DBR1 CWG1DBRbits.DBR1 // bit 1, shadows bit in CWG1DBRbits
10414 #define CWG1DBR1 CWG1DBRbits.CWG1DBR1 // bit 1, shadows bit in CWG1DBRbits
10415 #define DBR2 CWG1DBRbits.DBR2 // bit 2, shadows bit in CWG1DBRbits
10416 #define CWG1DBR2 CWG1DBRbits.CWG1DBR2 // bit 2, shadows bit in CWG1DBRbits
10417 #define DBR3 CWG1DBRbits.DBR3 // bit 3, shadows bit in CWG1DBRbits
10418 #define CWG1DBR3 CWG1DBRbits.CWG1DBR3 // bit 3, shadows bit in CWG1DBRbits
10419 #define DBR4 CWG1DBRbits.DBR4 // bit 4, shadows bit in CWG1DBRbits
10420 #define CWG1DBR4 CWG1DBRbits.CWG1DBR4 // bit 4, shadows bit in CWG1DBRbits
10421 #define DBR5 CWG1DBRbits.DBR5 // bit 5, shadows bit in CWG1DBRbits
10422 #define CWG1DBR5 CWG1DBRbits.CWG1DBR5 // bit 5, shadows bit in CWG1DBRbits
10424 #define CWG1PPS0 CWG1PPSbits.CWG1PPS0 // bit 0
10425 #define CWG1PPS1 CWG1PPSbits.CWG1PPS1 // bit 1
10426 #define CWG1PPS2 CWG1PPSbits.CWG1PPS2 // bit 2
10427 #define CWG1PPS3 CWG1PPSbits.CWG1PPS3 // bit 3
10428 #define CWG1PPS4 CWG1PPSbits.CWG1PPS4 // bit 4
10430 #define STRA CWG1STRbits.STRA // bit 0, shadows bit in CWG1STRbits
10431 #define CWG1STRA CWG1STRbits.CWG1STRA // bit 0, shadows bit in CWG1STRbits
10432 #define STRB CWG1STRbits.STRB // bit 1, shadows bit in CWG1STRbits
10433 #define CWG1STRB CWG1STRbits.CWG1STRB // bit 1, shadows bit in CWG1STRbits
10434 #define STRC CWG1STRbits.STRC // bit 2, shadows bit in CWG1STRbits
10435 #define CWG1STRC CWG1STRbits.CWG1STRC // bit 2, shadows bit in CWG1STRbits
10436 #define STRD CWG1STRbits.STRD // bit 3, shadows bit in CWG1STRbits
10437 #define CWG1STRD CWG1STRbits.CWG1STRD // bit 3, shadows bit in CWG1STRbits
10438 #define OVRA CWG1STRbits.OVRA // bit 4, shadows bit in CWG1STRbits
10439 #define CWG1OVRA CWG1STRbits.CWG1OVRA // bit 4, shadows bit in CWG1STRbits
10440 #define OVRB CWG1STRbits.OVRB // bit 5, shadows bit in CWG1STRbits
10441 #define CWG1OVRB CWG1STRbits.CWG1OVRB // bit 5, shadows bit in CWG1STRbits
10442 #define OVRC CWG1STRbits.OVRC // bit 6, shadows bit in CWG1STRbits
10443 #define CWG1OVRC CWG1STRbits.CWG1OVRC // bit 6, shadows bit in CWG1STRbits
10444 #define OVRD CWG1STRbits.OVRD // bit 7, shadows bit in CWG1STRbits
10445 #define CWG1OVRD CWG1STRbits.CWG1OVRD // bit 7, shadows bit in CWG1STRbits
10447 #define CWG2DAT0 CWG2DATbits.CWG2DAT0 // bit 0
10448 #define CWG2DAT1 CWG2DATbits.CWG2DAT1 // bit 1
10449 #define CWG2DAT2 CWG2DATbits.CWG2DAT2 // bit 2
10450 #define CWG2DAT3 CWG2DATbits.CWG2DAT3 // bit 3
10452 #define CWG2PPS0 CWG2PPSbits.CWG2PPS0 // bit 0
10453 #define CWG2PPS1 CWG2PPSbits.CWG2PPS1 // bit 1
10454 #define CWG2PPS2 CWG2PPSbits.CWG2PPS2 // bit 2
10455 #define CWG2PPS3 CWG2PPSbits.CWG2PPS3 // bit 3
10456 #define CWG2PPS4 CWG2PPSbits.CWG2PPS4 // bit 4
10458 #define DAC1NSS DACCON0bits.DAC1NSS // bit 0
10459 #define DAC1PSS0 DACCON0bits.DAC1PSS0 // bit 2
10460 #define DAC1PSS1 DACCON0bits.DAC1PSS1 // bit 3
10461 #define DAC1OE DACCON0bits.DAC1OE // bit 5
10462 #define DAC1EN DACCON0bits.DAC1EN // bit 7
10464 #define DAC1R0 DACCON1bits.DAC1R0 // bit 0
10465 #define DAC1R1 DACCON1bits.DAC1R1 // bit 1
10466 #define DAC1R2 DACCON1bits.DAC1R2 // bit 2
10467 #define DAC1R3 DACCON1bits.DAC1R3 // bit 3
10468 #define DAC1R4 DACCON1bits.DAC1R4 // bit 4
10470 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
10471 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
10472 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
10473 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
10474 #define TSRNG FVRCONbits.TSRNG // bit 4
10475 #define TSEN FVRCONbits.TSEN // bit 5
10476 #define FVRRDY FVRCONbits.FVRRDY // bit 6
10477 #define FVREN FVRCONbits.FVREN // bit 7
10479 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
10480 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
10481 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
10482 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
10483 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
10484 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
10486 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
10487 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
10488 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
10489 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
10490 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
10491 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
10493 #define INTEDG INTCONbits.INTEDG // bit 0
10494 #define PEIE INTCONbits.PEIE // bit 6
10495 #define GIE INTCONbits.GIE // bit 7
10497 #define INTPPS0 INTPPSbits.INTPPS0 // bit 0
10498 #define INTPPS1 INTPPSbits.INTPPS1 // bit 1
10499 #define INTPPS2 INTPPSbits.INTPPS2 // bit 2
10500 #define INTPPS3 INTPPSbits.INTPPS3 // bit 3
10501 #define INTPPS4 INTPPSbits.INTPPS4 // bit 4
10503 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
10504 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
10505 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
10506 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
10507 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
10508 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
10510 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
10511 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
10512 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
10513 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
10514 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
10515 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
10517 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
10518 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
10519 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
10520 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
10521 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
10522 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
10524 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
10525 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
10526 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
10527 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
10528 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
10529 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
10531 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
10532 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
10533 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
10534 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
10535 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
10536 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
10538 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
10539 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
10540 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
10541 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
10542 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
10543 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
10545 #define LATA0 LATAbits.LATA0 // bit 0
10546 #define LATA1 LATAbits.LATA1 // bit 1
10547 #define LATA2 LATAbits.LATA2 // bit 2
10548 #define LATA4 LATAbits.LATA4 // bit 4
10549 #define LATA5 LATAbits.LATA5 // bit 5
10551 #define LATC0 LATCbits.LATC0 // bit 0
10552 #define LATC1 LATCbits.LATC1 // bit 1
10553 #define LATC2 LATCbits.LATC2 // bit 2
10554 #define LATC3 LATCbits.LATC3 // bit 3
10555 #define LATC4 LATCbits.LATC4 // bit 4
10556 #define LATC5 LATCbits.LATC5 // bit 5
10558 #define MDCH0 MDCARHbits.MDCH0 // bit 0
10559 #define MDCH1 MDCARHbits.MDCH1 // bit 1
10560 #define MDCH2 MDCARHbits.MDCH2 // bit 2
10561 #define MDCH3 MDCARHbits.MDCH3 // bit 3
10562 #define MDCHSYNC MDCARHbits.MDCHSYNC // bit 5
10563 #define MDCHPOL MDCARHbits.MDCHPOL // bit 6
10565 #define MDCL0 MDCARLbits.MDCL0 // bit 0
10566 #define MDCL1 MDCARLbits.MDCL1 // bit 1
10567 #define MDCL2 MDCARLbits.MDCL2 // bit 2
10568 #define MDCL3 MDCARLbits.MDCL3 // bit 3
10569 #define MDCLSYNC MDCARLbits.MDCLSYNC // bit 5
10570 #define MDCLPOL MDCARLbits.MDCLPOL // bit 6
10572 #define MDCIN1PPS0 MDCIN1PPSbits.MDCIN1PPS0 // bit 0
10573 #define MDCIN1PPS1 MDCIN1PPSbits.MDCIN1PPS1 // bit 1
10574 #define MDCIN1PPS2 MDCIN1PPSbits.MDCIN1PPS2 // bit 2
10575 #define MDCIN1PPS3 MDCIN1PPSbits.MDCIN1PPS3 // bit 3
10576 #define MDCIN1PPS4 MDCIN1PPSbits.MDCIN1PPS4 // bit 4
10578 #define MDCIN2PPS0 MDCIN2PPSbits.MDCIN2PPS0 // bit 0
10579 #define MDCIN2PPS1 MDCIN2PPSbits.MDCIN2PPS1 // bit 1
10580 #define MDCIN2PPS2 MDCIN2PPSbits.MDCIN2PPS2 // bit 2
10581 #define MDCIN2PPS3 MDCIN2PPSbits.MDCIN2PPS3 // bit 3
10582 #define MDCIN2PPS4 MDCIN2PPSbits.MDCIN2PPS4 // bit 4
10584 #define MDBIT MDCONbits.MDBIT // bit 0
10585 #define MDOUT MDCONbits.MDOUT // bit 3
10586 #define MDOPOL MDCONbits.MDOPOL // bit 4
10587 #define MDEN MDCONbits.MDEN // bit 7
10589 #define MDMINPPS0 MDMINPPSbits.MDMINPPS0 // bit 0
10590 #define MDMINPPS1 MDMINPPSbits.MDMINPPS1 // bit 1
10591 #define MDMINPPS2 MDMINPPSbits.MDMINPPS2 // bit 2
10592 #define MDMINPPS3 MDMINPPSbits.MDMINPPS3 // bit 3
10593 #define MDMINPPS4 MDMINPPSbits.MDMINPPS4 // bit 4
10595 #define MDMS0 MDSRCbits.MDMS0 // bit 0
10596 #define MDMS1 MDSRCbits.MDMS1 // bit 1
10597 #define MDMS2 MDSRCbits.MDMS2 // bit 2
10598 #define MDMS3 MDSRCbits.MDMS3 // bit 3
10600 #define N1PFM NCO1CONbits.N1PFM // bit 0
10601 #define N1POL NCO1CONbits.N1POL // bit 4
10602 #define N1OUT NCO1CONbits.N1OUT // bit 5
10603 #define N1EN NCO1CONbits.N1EN // bit 7
10605 #define NVMADR8 NVMADRHbits.NVMADR8 // bit 0
10606 #define NVMADR9 NVMADRHbits.NVMADR9 // bit 1
10607 #define NVMADR10 NVMADRHbits.NVMADR10 // bit 2
10608 #define NVMADR11 NVMADRHbits.NVMADR11 // bit 3
10609 #define NVMADR12 NVMADRHbits.NVMADR12 // bit 4
10610 #define NVMADR13 NVMADRHbits.NVMADR13 // bit 5
10611 #define NVMADR14 NVMADRHbits.NVMADR14 // bit 6
10613 #define NVMADR0 NVMADRLbits.NVMADR0 // bit 0
10614 #define NVMADR1 NVMADRLbits.NVMADR1 // bit 1
10615 #define NVMADR2 NVMADRLbits.NVMADR2 // bit 2
10616 #define NVMADR3 NVMADRLbits.NVMADR3 // bit 3
10617 #define NVMADR4 NVMADRLbits.NVMADR4 // bit 4
10618 #define NVMADR5 NVMADRLbits.NVMADR5 // bit 5
10619 #define NVMADR6 NVMADRLbits.NVMADR6 // bit 6
10620 #define NVMADR7 NVMADRLbits.NVMADR7 // bit 7
10622 #define RD NVMCON1bits.RD // bit 0
10623 #define WR NVMCON1bits.WR // bit 1
10624 #define WREN NVMCON1bits.WREN // bit 2
10625 #define WRERR NVMCON1bits.WRERR // bit 3
10626 #define FREE NVMCON1bits.FREE // bit 4
10627 #define LWLO NVMCON1bits.LWLO // bit 5
10628 #define NVMREGS NVMCON1bits.NVMREGS // bit 6
10630 #define NVMDAT8 NVMDATHbits.NVMDAT8 // bit 0
10631 #define NVMDAT9 NVMDATHbits.NVMDAT9 // bit 1
10632 #define NVMDAT10 NVMDATHbits.NVMDAT10 // bit 2
10633 #define NVMDAT11 NVMDATHbits.NVMDAT11 // bit 3
10634 #define NVMDAT12 NVMDATHbits.NVMDAT12 // bit 4
10635 #define NVMDAT13 NVMDATHbits.NVMDAT13 // bit 5
10637 #define NVMDAT0 NVMDATLbits.NVMDAT0 // bit 0
10638 #define NVMDAT1 NVMDATLbits.NVMDAT1 // bit 1
10639 #define NVMDAT2 NVMDATLbits.NVMDAT2 // bit 2
10640 #define NVMDAT3 NVMDATLbits.NVMDAT3 // bit 3
10641 #define NVMDAT4 NVMDATLbits.NVMDAT4 // bit 4
10642 #define NVMDAT5 NVMDATLbits.NVMDAT5 // bit 5
10643 #define NVMDAT6 NVMDATLbits.NVMDAT6 // bit 6
10644 #define NVMDAT7 NVMDATLbits.NVMDAT7 // bit 7
10646 #define ODCA0 ODCONAbits.ODCA0 // bit 0
10647 #define ODCA1 ODCONAbits.ODCA1 // bit 1
10648 #define ODCA2 ODCONAbits.ODCA2 // bit 2
10649 #define ODCA4 ODCONAbits.ODCA4 // bit 4
10650 #define ODCA5 ODCONAbits.ODCA5 // bit 5
10652 #define ODCC0 ODCONCbits.ODCC0 // bit 0
10653 #define ODCC1 ODCONCbits.ODCC1 // bit 1
10654 #define ODCC2 ODCONCbits.ODCC2 // bit 2
10655 #define ODCC3 ODCONCbits.ODCC3 // bit 3
10656 #define ODCC4 ODCONCbits.ODCC4 // bit 4
10657 #define ODCC5 ODCONCbits.ODCC5 // bit 5
10659 #define NDIV0 OSCCON1bits.NDIV0 // bit 0
10660 #define NDIV1 OSCCON1bits.NDIV1 // bit 1
10661 #define NDIV2 OSCCON1bits.NDIV2 // bit 2
10662 #define NDIV3 OSCCON1bits.NDIV3 // bit 3
10663 #define NOSC0 OSCCON1bits.NOSC0 // bit 4
10664 #define NOSC1 OSCCON1bits.NOSC1 // bit 5
10665 #define NOSC2 OSCCON1bits.NOSC2 // bit 6
10667 #define CDIV0 OSCCON2bits.CDIV0 // bit 0
10668 #define CDIV1 OSCCON2bits.CDIV1 // bit 1
10669 #define CDIV2 OSCCON2bits.CDIV2 // bit 2
10670 #define CDIV3 OSCCON2bits.CDIV3 // bit 3
10671 #define COSC0 OSCCON2bits.COSC0 // bit 4
10672 #define COSC1 OSCCON2bits.COSC1 // bit 5
10673 #define COSC2 OSCCON2bits.COSC2 // bit 6
10675 #define NOSCR OSCCON3bits.NOSCR // bit 3
10676 #define ORDY OSCCON3bits.ORDY // bit 4
10677 #define SOSCBE OSCCON3bits.SOSCBE // bit 5
10678 #define SOSCPWR OSCCON3bits.SOSCPWR // bit 6
10679 #define CSWHOLD OSCCON3bits.CSWHOLD // bit 7
10681 #define ADOEN OSCENbits.ADOEN // bit 2
10682 #define SOSCEN OSCENbits.SOSCEN // bit 3
10683 #define LFOEN OSCENbits.LFOEN // bit 4
10684 #define HFOEN OSCENbits.HFOEN // bit 6
10685 #define EXTOEN OSCENbits.EXTOEN // bit 7
10687 #define HFFRQ0 OSCFRQbits.HFFRQ0 // bit 0
10688 #define HFFRQ1 OSCFRQbits.HFFRQ1 // bit 1
10689 #define HFFRQ2 OSCFRQbits.HFFRQ2 // bit 2
10690 #define HFFRQ3 OSCFRQbits.HFFRQ3 // bit 3
10692 #define PLLR OSCSTAT1bits.PLLR // bit 0
10693 #define ADOR OSCSTAT1bits.ADOR // bit 2
10694 #define SOR OSCSTAT1bits.SOR // bit 3
10695 #define LFOR OSCSTAT1bits.LFOR // bit 4
10696 #define HFOR OSCSTAT1bits.HFOR // bit 6
10697 #define EXTOR OSCSTAT1bits.EXTOR // bit 7
10699 #define HFTUN0 OSCTUNEbits.HFTUN0 // bit 0
10700 #define HFTUN1 OSCTUNEbits.HFTUN1 // bit 1
10701 #define HFTUN2 OSCTUNEbits.HFTUN2 // bit 2
10702 #define HFTUN3 OSCTUNEbits.HFTUN3 // bit 3
10703 #define HFTUN4 OSCTUNEbits.HFTUN4 // bit 4
10704 #define HFTUN5 OSCTUNEbits.HFTUN5 // bit 5
10706 #define NOT_BOR PCON0bits.NOT_BOR // bit 0
10707 #define NOT_POR PCON0bits.NOT_POR // bit 1
10708 #define NOT_RI PCON0bits.NOT_RI // bit 2
10709 #define NOT_RMCLR PCON0bits.NOT_RMCLR // bit 3
10710 #define NOT_RWDT PCON0bits.NOT_RWDT // bit 4
10711 #define STKUNF PCON0bits.STKUNF // bit 6
10712 #define STKOVF PCON0bits.STKOVF // bit 7
10714 #define INTE PIE0bits.INTE // bit 0
10715 #define IOCIE PIE0bits.IOCIE // bit 4
10716 #define TMR0IE PIE0bits.TMR0IE // bit 5
10718 #define TMR1IE PIE1bits.TMR1IE // bit 0
10719 #define TMR2IE PIE1bits.TMR2IE // bit 1
10720 #define BCL1IE PIE1bits.BCL1IE // bit 2
10721 #define SSP1IE PIE1bits.SSP1IE // bit 3
10722 #define TXIE PIE1bits.TXIE // bit 4
10723 #define RCIE PIE1bits.RCIE // bit 5
10724 #define ADIE PIE1bits.ADIE // bit 6
10725 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
10727 #define NCO1IE PIE2bits.NCO1IE // bit 0
10728 #define TMR4IE PIE2bits.TMR4IE // bit 1
10729 #define NVMIE PIE2bits.NVMIE // bit 4
10730 #define C1IE PIE2bits.C1IE // bit 5
10731 #define C2IE PIE2bits.C2IE // bit 6
10732 #define TMR6IE PIE2bits.TMR6IE // bit 7
10734 #define CLC1IE PIE3bits.CLC1IE // bit 0
10735 #define CLC2IE PIE3bits.CLC2IE // bit 1
10736 #define CLC3IE PIE3bits.CLC3IE // bit 2
10737 #define CLC4IE PIE3bits.CLC4IE // bit 3
10738 #define TMR3IE PIE3bits.TMR3IE // bit 4
10739 #define TMR3GIE PIE3bits.TMR3GIE // bit 5
10740 #define CSWIE PIE3bits.CSWIE // bit 6
10741 #define OSFIE PIE3bits.OSFIE // bit 7
10743 #define CCP1IE PIE4bits.CCP1IE // bit 0
10744 #define CCP2IE PIE4bits.CCP2IE // bit 1
10745 #define CCP3IE PIE4bits.CCP3IE // bit 2
10746 #define CCP4IE PIE4bits.CCP4IE // bit 3
10747 #define TMR5IE PIE4bits.TMR5IE // bit 4
10748 #define TMR5GIE PIE4bits.TMR5GIE // bit 5
10749 #define CWG1IE PIE4bits.CWG1IE // bit 6
10750 #define CWG2IE PIE4bits.CWG2IE // bit 7
10752 #define INTF PIR0bits.INTF // bit 0
10753 #define IOCIF PIR0bits.IOCIF // bit 4
10754 #define TMR0IF PIR0bits.TMR0IF // bit 5
10756 #define TMR1IF PIR1bits.TMR1IF // bit 0
10757 #define TMR2IF PIR1bits.TMR2IF // bit 1
10758 #define BCL1IF PIR1bits.BCL1IF // bit 2
10759 #define SSP1IF PIR1bits.SSP1IF // bit 3
10760 #define TXIF PIR1bits.TXIF // bit 4
10761 #define RCIF PIR1bits.RCIF // bit 5
10762 #define ADIF PIR1bits.ADIF // bit 6
10763 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
10765 #define NCO1IF PIR2bits.NCO1IF // bit 0
10766 #define TMR4IF PIR2bits.TMR4IF // bit 1
10767 #define NVMIF PIR2bits.NVMIF // bit 4
10768 #define C1IF PIR2bits.C1IF // bit 5
10769 #define C2IF PIR2bits.C2IF // bit 6
10770 #define TMR6IF PIR2bits.TMR6IF // bit 7
10772 #define CLC1IF PIR3bits.CLC1IF // bit 0
10773 #define CLC2IF PIR3bits.CLC2IF // bit 1
10774 #define CLC3IF PIR3bits.CLC3IF // bit 2
10775 #define CLC4IF PIR3bits.CLC4IF // bit 3
10776 #define TMR3IF PIR3bits.TMR3IF // bit 4
10777 #define TMR3GIF PIR3bits.TMR3GIF // bit 5
10778 #define CSWIF PIR3bits.CSWIF // bit 6
10779 #define OSFIF PIR3bits.OSFIF // bit 7
10781 #define CCP1IF PIR4bits.CCP1IF // bit 0
10782 #define CCP2IF PIR4bits.CCP2IF // bit 1
10783 #define CCP3IF PIR4bits.CCP3IF // bit 2
10784 #define CCP4IF PIR4bits.CCP4IF // bit 3
10785 #define TMR5IF PIR4bits.TMR5IF // bit 4
10786 #define TMR5GIF PIR4bits.TMR5GIF // bit 5
10787 #define CWG1IF PIR4bits.CWG1IF // bit 6
10788 #define CWG2IF PIR4bits.CWG2IF // bit 7
10790 #define IOCMD PMD0bits.IOCMD // bit 0
10791 #define CLKRMD PMD0bits.CLKRMD // bit 1
10792 #define NVMMD PMD0bits.NVMMD // bit 2
10793 #define FVRMD PMD0bits.FVRMD // bit 6
10794 #define SYSCMD PMD0bits.SYSCMD // bit 7
10796 #define TMR0MD PMD1bits.TMR0MD // bit 0
10797 #define TMR1MD PMD1bits.TMR1MD // bit 1
10798 #define TMR2MD PMD1bits.TMR2MD // bit 2
10799 #define TMR3MD PMD1bits.TMR3MD // bit 3
10800 #define TMR4MD PMD1bits.TMR4MD // bit 4
10801 #define TMR5MD PMD1bits.TMR5MD // bit 5
10802 #define TMR6MD PMD1bits.TMR6MD // bit 6
10803 #define NCOMD PMD1bits.NCOMD // bit 7
10805 #define CMP1MD PMD2bits.CMP1MD // bit 1
10806 #define CMP2MD PMD2bits.CMP2MD // bit 2
10807 #define ADCMD PMD2bits.ADCMD // bit 5
10808 #define DACMD PMD2bits.DACMD // bit 6
10810 #define CCP1MD PMD3bits.CCP1MD // bit 0
10811 #define CCP2MD PMD3bits.CCP2MD // bit 1
10812 #define CCP3MD PMD3bits.CCP3MD // bit 2
10813 #define CCP4MD PMD3bits.CCP4MD // bit 3
10814 #define PWM5MD PMD3bits.PWM5MD // bit 4
10815 #define PWM6MD PMD3bits.PWM6MD // bit 5
10816 #define CWG1MD PMD3bits.CWG1MD // bit 6
10817 #define CWG2MD PMD3bits.CWG2MD // bit 7
10819 #define MSSP1MD PMD4bits.MSSP1MD // bit 1
10820 #define UART1MD PMD4bits.UART1MD // bit 5
10822 #define DSMMD PMD5bits.DSMMD // bit 0
10823 #define CLC1MD PMD5bits.CLC1MD // bit 1
10824 #define CLC2MD PMD5bits.CLC2MD // bit 2
10825 #define CLC3MD PMD5bits.CLC3MD // bit 3
10826 #define CLC4MD PMD5bits.CLC4MD // bit 4
10828 #define RA0 PORTAbits.RA0 // bit 0
10829 #define RA1 PORTAbits.RA1 // bit 1
10830 #define RA2 PORTAbits.RA2 // bit 2
10831 #define RA3 PORTAbits.RA3 // bit 3
10832 #define RA4 PORTAbits.RA4 // bit 4
10833 #define RA5 PORTAbits.RA5 // bit 5
10835 #define RC0 PORTCbits.RC0 // bit 0
10836 #define RC1 PORTCbits.RC1 // bit 1
10837 #define RC2 PORTCbits.RC2 // bit 2
10838 #define RC3 PORTCbits.RC3 // bit 3
10839 #define RC4 PORTCbits.RC4 // bit 4
10840 #define RC5 PORTCbits.RC5 // bit 5
10842 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
10844 #define PWM5POL PWM5CONbits.PWM5POL // bit 4
10845 #define PWM5OUT PWM5CONbits.PWM5OUT // bit 5
10846 #define PWM5EN PWM5CONbits.PWM5EN // bit 7
10848 #define PWM5DCH0 PWM5DCHbits.PWM5DCH0 // bit 0
10849 #define PWM5DCH1 PWM5DCHbits.PWM5DCH1 // bit 1
10850 #define PWM5DCH2 PWM5DCHbits.PWM5DCH2 // bit 2
10851 #define PWM5DCH3 PWM5DCHbits.PWM5DCH3 // bit 3
10852 #define PWM5DCH4 PWM5DCHbits.PWM5DCH4 // bit 4
10853 #define PWM5DCH5 PWM5DCHbits.PWM5DCH5 // bit 5
10854 #define PWM5DCH6 PWM5DCHbits.PWM5DCH6 // bit 6
10855 #define PWM5DCH7 PWM5DCHbits.PWM5DCH7 // bit 7
10857 #define PWM5DCL0 PWM5DCLbits.PWM5DCL0 // bit 6
10858 #define PWM5DCL1 PWM5DCLbits.PWM5DCL1 // bit 7
10860 #define PWM6POL PWM6CONbits.PWM6POL // bit 4
10861 #define PWM6OUT PWM6CONbits.PWM6OUT // bit 5
10862 #define PWM6EN PWM6CONbits.PWM6EN // bit 7
10864 #define PWM6DCH0 PWM6DCHbits.PWM6DCH0 // bit 0
10865 #define PWM6DCH1 PWM6DCHbits.PWM6DCH1 // bit 1
10866 #define PWM6DCH2 PWM6DCHbits.PWM6DCH2 // bit 2
10867 #define PWM6DCH3 PWM6DCHbits.PWM6DCH3 // bit 3
10868 #define PWM6DCH4 PWM6DCHbits.PWM6DCH4 // bit 4
10869 #define PWM6DCH5 PWM6DCHbits.PWM6DCH5 // bit 5
10870 #define PWM6DCH6 PWM6DCHbits.PWM6DCH6 // bit 6
10871 #define PWM6DCH7 PWM6DCHbits.PWM6DCH7 // bit 7
10873 #define PWM6DCL0 PWM6DCLbits.PWM6DCL0 // bit 6
10874 #define PWM6DCL1 PWM6DCLbits.PWM6DCL1 // bit 7
10876 #define P5TSEL0 PWMTMRSbits.P5TSEL0 // bit 0
10877 #define P5TSEL1 PWMTMRSbits.P5TSEL1 // bit 1
10878 #define P6TSEL0 PWMTMRSbits.P6TSEL0 // bit 2
10879 #define P6TSEL1 PWMTMRSbits.P6TSEL1 // bit 3
10881 #define RA0PPS0 RA0PPSbits.RA0PPS0 // bit 0
10882 #define RA0PPS1 RA0PPSbits.RA0PPS1 // bit 1
10883 #define RA0PPS2 RA0PPSbits.RA0PPS2 // bit 2
10884 #define RA0PPS3 RA0PPSbits.RA0PPS3 // bit 3
10885 #define RA0PPS4 RA0PPSbits.RA0PPS4 // bit 4
10887 #define RA1PPS0 RA1PPSbits.RA1PPS0 // bit 0
10888 #define RA1PPS1 RA1PPSbits.RA1PPS1 // bit 1
10889 #define RA1PPS2 RA1PPSbits.RA1PPS2 // bit 2
10890 #define RA1PPS3 RA1PPSbits.RA1PPS3 // bit 3
10891 #define RA1PPS4 RA1PPSbits.RA1PPS4 // bit 4
10893 #define RA2PPS0 RA2PPSbits.RA2PPS0 // bit 0
10894 #define RA2PPS1 RA2PPSbits.RA2PPS1 // bit 1
10895 #define RA2PPS2 RA2PPSbits.RA2PPS2 // bit 2
10896 #define RA2PPS3 RA2PPSbits.RA2PPS3 // bit 3
10897 #define RA2PPS4 RA2PPSbits.RA2PPS4 // bit 4
10899 #define RA4PPS0 RA4PPSbits.RA4PPS0 // bit 0
10900 #define RA4PPS1 RA4PPSbits.RA4PPS1 // bit 1
10901 #define RA4PPS2 RA4PPSbits.RA4PPS2 // bit 2
10902 #define RA4PPS3 RA4PPSbits.RA4PPS3 // bit 3
10903 #define RA4PPS4 RA4PPSbits.RA4PPS4 // bit 4
10905 #define RA5PPS0 RA5PPSbits.RA5PPS0 // bit 0
10906 #define RA5PPS1 RA5PPSbits.RA5PPS1 // bit 1
10907 #define RA5PPS2 RA5PPSbits.RA5PPS2 // bit 2
10908 #define RA5PPS3 RA5PPSbits.RA5PPS3 // bit 3
10909 #define RA5PPS4 RA5PPSbits.RA5PPS4 // bit 4
10911 #define RC0PPS0 RC0PPSbits.RC0PPS0 // bit 0
10912 #define RC0PPS1 RC0PPSbits.RC0PPS1 // bit 1
10913 #define RC0PPS2 RC0PPSbits.RC0PPS2 // bit 2
10914 #define RC0PPS3 RC0PPSbits.RC0PPS3 // bit 3
10915 #define RC0PPS4 RC0PPSbits.RC0PPS4 // bit 4
10917 #define RC1PPS0 RC1PPSbits.RC1PPS0 // bit 0
10918 #define RC1PPS1 RC1PPSbits.RC1PPS1 // bit 1
10919 #define RC1PPS2 RC1PPSbits.RC1PPS2 // bit 2
10920 #define RC1PPS3 RC1PPSbits.RC1PPS3 // bit 3
10921 #define RC1PPS4 RC1PPSbits.RC1PPS4 // bit 4
10923 #define RX9D RC1STAbits.RX9D // bit 0
10924 #define OERR RC1STAbits.OERR // bit 1
10925 #define FERR RC1STAbits.FERR // bit 2
10926 #define ADDEN RC1STAbits.ADDEN // bit 3
10927 #define CREN RC1STAbits.CREN // bit 4
10928 #define SREN RC1STAbits.SREN // bit 5
10929 #define RX9 RC1STAbits.RX9 // bit 6
10930 #define SPEN RC1STAbits.SPEN // bit 7
10932 #define RC2PPS0 RC2PPSbits.RC2PPS0 // bit 0
10933 #define RC2PPS1 RC2PPSbits.RC2PPS1 // bit 1
10934 #define RC2PPS2 RC2PPSbits.RC2PPS2 // bit 2
10935 #define RC2PPS3 RC2PPSbits.RC2PPS3 // bit 3
10936 #define RC2PPS4 RC2PPSbits.RC2PPS4 // bit 4
10938 #define RC3PPS0 RC3PPSbits.RC3PPS0 // bit 0
10939 #define RC3PPS1 RC3PPSbits.RC3PPS1 // bit 1
10940 #define RC3PPS2 RC3PPSbits.RC3PPS2 // bit 2
10941 #define RC3PPS3 RC3PPSbits.RC3PPS3 // bit 3
10942 #define RC3PPS4 RC3PPSbits.RC3PPS4 // bit 4
10944 #define RC4PPS0 RC4PPSbits.RC4PPS0 // bit 0
10945 #define RC4PPS1 RC4PPSbits.RC4PPS1 // bit 1
10946 #define RC4PPS2 RC4PPSbits.RC4PPS2 // bit 2
10947 #define RC4PPS3 RC4PPSbits.RC4PPS3 // bit 3
10948 #define RC4PPS4 RC4PPSbits.RC4PPS4 // bit 4
10950 #define RC5PPS0 RC5PPSbits.RC5PPS0 // bit 0
10951 #define RC5PPS1 RC5PPSbits.RC5PPS1 // bit 1
10952 #define RC5PPS2 RC5PPSbits.RC5PPS2 // bit 2
10953 #define RC5PPS3 RC5PPSbits.RC5PPS3 // bit 3
10954 #define RC5PPS4 RC5PPSbits.RC5PPS4 // bit 4
10956 #define RXDTPPS0 RXPPSbits.RXDTPPS0 // bit 0
10957 #define RXDTPPS1 RXPPSbits.RXDTPPS1 // bit 1
10958 #define RXDTPPS2 RXPPSbits.RXDTPPS2 // bit 2
10959 #define RXDTPPS3 RXPPSbits.RXDTPPS3 // bit 3
10960 #define RXDTPPS4 RXPPSbits.RXDTPPS4 // bit 4
10962 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
10963 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
10964 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
10965 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
10966 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
10968 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
10969 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
10970 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
10971 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
10972 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
10973 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
10975 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
10976 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
10977 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
10978 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
10979 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
10980 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
10981 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
10982 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
10983 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
10984 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
10985 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
10986 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
10987 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
10988 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
10989 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
10990 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
10992 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
10993 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
10994 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
10995 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
10996 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
10997 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
10998 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
10999 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
11000 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
11001 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
11002 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
11003 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
11004 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
11005 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
11006 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
11007 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
11009 #define SSP1CLKPPS0 SSP1CLKPPSbits.SSP1CLKPPS0 // bit 0
11010 #define SSP1CLKPPS1 SSP1CLKPPSbits.SSP1CLKPPS1 // bit 1
11011 #define SSP1CLKPPS2 SSP1CLKPPSbits.SSP1CLKPPS2 // bit 2
11012 #define SSP1CLKPPS3 SSP1CLKPPSbits.SSP1CLKPPS3 // bit 3
11013 #define SSP1CLKPPS4 SSP1CLKPPSbits.SSP1CLKPPS4 // bit 4
11015 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
11016 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
11017 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
11018 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
11019 #define CKP SSP1CONbits.CKP // bit 4
11020 #define SSPEN SSP1CONbits.SSPEN // bit 5
11021 #define SSPOV SSP1CONbits.SSPOV // bit 6
11022 #define WCOL SSP1CONbits.WCOL // bit 7
11024 #define SEN SSP1CON2bits.SEN // bit 0
11025 #define RSEN SSP1CON2bits.RSEN // bit 1
11026 #define PEN SSP1CON2bits.PEN // bit 2
11027 #define RCEN SSP1CON2bits.RCEN // bit 3
11028 #define ACKEN SSP1CON2bits.ACKEN // bit 4
11029 #define ACKDT SSP1CON2bits.ACKDT // bit 5
11030 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
11031 #define GCEN SSP1CON2bits.GCEN // bit 7
11033 #define DHEN SSP1CON3bits.DHEN // bit 0
11034 #define AHEN SSP1CON3bits.AHEN // bit 1
11035 #define SBCDE SSP1CON3bits.SBCDE // bit 2
11036 #define SDAHT SSP1CON3bits.SDAHT // bit 3
11037 #define BOEN SSP1CON3bits.BOEN // bit 4
11038 #define SCIE SSP1CON3bits.SCIE // bit 5
11039 #define PCIE SSP1CON3bits.PCIE // bit 6
11040 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
11042 #define SSP1DATPPS0 SSP1DATPPSbits.SSP1DATPPS0 // bit 0
11043 #define SSP1DATPPS1 SSP1DATPPSbits.SSP1DATPPS1 // bit 1
11044 #define SSP1DATPPS2 SSP1DATPPSbits.SSP1DATPPS2 // bit 2
11045 #define SSP1DATPPS3 SSP1DATPPSbits.SSP1DATPPS3 // bit 3
11046 #define SSP1DATPPS4 SSP1DATPPSbits.SSP1DATPPS4 // bit 4
11048 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
11049 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
11050 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
11051 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
11052 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
11053 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
11054 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
11055 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
11056 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
11057 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
11058 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
11059 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
11060 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
11061 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
11062 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
11063 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
11065 #define SSP1SSPPS0 SSP1SSPPSbits.SSP1SSPPS0 // bit 0
11066 #define SSP1SSPPS1 SSP1SSPPSbits.SSP1SSPPS1 // bit 1
11067 #define SSP1SSPPS2 SSP1SSPPSbits.SSP1SSPPS2 // bit 2
11068 #define SSP1SSPPS3 SSP1SSPPSbits.SSP1SSPPS3 // bit 3
11069 #define SSP1SSPPS4 SSP1SSPPSbits.SSP1SSPPS4 // bit 4
11071 #define BF SSP1STATbits.BF // bit 0
11072 #define UA SSP1STATbits.UA // bit 1
11073 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
11074 #define S SSP1STATbits.S // bit 3
11075 #define P SSP1STATbits.P // bit 4
11076 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
11077 #define CKE SSP1STATbits.CKE // bit 6
11078 #define SMP SSP1STATbits.SMP // bit 7
11080 #define C STATUSbits.C // bit 0
11081 #define DC STATUSbits.DC // bit 1
11082 #define Z STATUSbits.Z // bit 2
11083 #define NOT_PD STATUSbits.NOT_PD // bit 3
11084 #define NOT_TO STATUSbits.NOT_TO // bit 4
11086 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
11087 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
11088 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
11090 #define T0CKIPPS0 T0CKIPPSbits.T0CKIPPS0 // bit 0
11091 #define T0CKIPPS1 T0CKIPPSbits.T0CKIPPS1 // bit 1
11092 #define T0CKIPPS2 T0CKIPPSbits.T0CKIPPS2 // bit 2
11093 #define T0CKIPPS3 T0CKIPPSbits.T0CKIPPS3 // bit 3
11094 #define T0CKIPPS4 T0CKIPPSbits.T0CKIPPS4 // bit 4
11096 #define T0OUTPS0 T0CON0bits.T0OUTPS0 // bit 0
11097 #define T0OUTPS1 T0CON0bits.T0OUTPS1 // bit 1
11098 #define T0OUTPS2 T0CON0bits.T0OUTPS2 // bit 2
11099 #define T0OUTPS3 T0CON0bits.T0OUTPS3 // bit 3
11100 #define T016BIT T0CON0bits.T016BIT // bit 4
11101 #define T0OUT T0CON0bits.T0OUT // bit 5
11102 #define T0EN T0CON0bits.T0EN // bit 7
11104 #define T0CKPS0 T0CON1bits.T0CKPS0 // bit 0
11105 #define T0CKPS1 T0CON1bits.T0CKPS1 // bit 1
11106 #define T0CKPS2 T0CON1bits.T0CKPS2 // bit 2
11107 #define T0CKPS3 T0CON1bits.T0CKPS3 // bit 3
11108 #define T0ASYNC T0CON1bits.T0ASYNC // bit 4
11109 #define T0CS0 T0CON1bits.T0CS0 // bit 5
11110 #define T0CS1 T0CON1bits.T0CS1 // bit 6
11111 #define T0CS2 T0CON1bits.T0CS2 // bit 7
11113 #define T1CKIPPS0 T1CKIPPSbits.T1CKIPPS0 // bit 0
11114 #define T1CKIPPS1 T1CKIPPSbits.T1CKIPPS1 // bit 1
11115 #define T1CKIPPS2 T1CKIPPSbits.T1CKIPPS2 // bit 2
11116 #define T1CKIPPS3 T1CKIPPSbits.T1CKIPPS3 // bit 3
11117 #define T1CKIPPS4 T1CKIPPSbits.T1CKIPPS4 // bit 4
11119 #define TMR1ON T1CONbits.TMR1ON // bit 0
11120 #define T1SYNC T1CONbits.T1SYNC // bit 2
11121 #define T1SOSC T1CONbits.T1SOSC // bit 3
11122 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
11123 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
11124 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
11125 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
11127 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
11128 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
11129 #define T1GVAL T1GCONbits.T1GVAL // bit 2
11130 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3
11131 #define T1GSPM T1GCONbits.T1GSPM // bit 4
11132 #define T1GTM T1GCONbits.T1GTM // bit 5
11133 #define T1GPOL T1GCONbits.T1GPOL // bit 6
11134 #define TMR1GE T1GCONbits.TMR1GE // bit 7
11136 #define T1GPPS0 T1GPPSbits.T1GPPS0 // bit 0
11137 #define T1GPPS1 T1GPPSbits.T1GPPS1 // bit 1
11138 #define T1GPPS2 T1GPPSbits.T1GPPS2 // bit 2
11139 #define T1GPPS3 T1GPPSbits.T1GPPS3 // bit 3
11140 #define T1GPPS4 T1GPPSbits.T1GPPS4 // bit 4
11142 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
11143 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
11144 #define TMR2ON T2CONbits.TMR2ON // bit 2
11145 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
11146 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
11147 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
11148 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
11150 #define TMR3ON T3CONbits.TMR3ON // bit 0
11151 #define T3SYNC T3CONbits.T3SYNC // bit 2
11152 #define T3SOSC T3CONbits.T3SOSC // bit 3
11153 #define T3CKPS0 T3CONbits.T3CKPS0 // bit 4
11154 #define T3CKPS1 T3CONbits.T3CKPS1 // bit 5
11155 #define TMR3CS0 T3CONbits.TMR3CS0 // bit 6
11156 #define TMR3CS1 T3CONbits.TMR3CS1 // bit 7
11158 #define T3GSS0 T3GCONbits.T3GSS0 // bit 0
11159 #define T3GSS1 T3GCONbits.T3GSS1 // bit 1
11160 #define T3GVAL T3GCONbits.T3GVAL // bit 2
11161 #define T3GGO_NOT_DONE T3GCONbits.T3GGO_NOT_DONE // bit 3
11162 #define T3GSPM T3GCONbits.T3GSPM // bit 4
11163 #define T3GTM T3GCONbits.T3GTM // bit 5
11164 #define T3GPOL T3GCONbits.T3GPOL // bit 6
11165 #define TMR3GE T3GCONbits.TMR3GE // bit 7
11167 #define T4CKPS0 T4CONbits.T4CKPS0 // bit 0
11168 #define T4CKPS1 T4CONbits.T4CKPS1 // bit 1
11169 #define TMR4ON T4CONbits.TMR4ON // bit 2
11170 #define T4OUTPS0 T4CONbits.T4OUTPS0 // bit 3
11171 #define T4OUTPS1 T4CONbits.T4OUTPS1 // bit 4
11172 #define T4OUTPS2 T4CONbits.T4OUTPS2 // bit 5
11173 #define T4OUTPS3 T4CONbits.T4OUTPS3 // bit 6
11175 #define TMR5ON T5CONbits.TMR5ON // bit 0
11176 #define T5SYNC T5CONbits.T5SYNC // bit 2
11177 #define T5SOSC T5CONbits.T5SOSC // bit 3
11178 #define T5CKPS0 T5CONbits.T5CKPS0 // bit 4
11179 #define T5CKPS1 T5CONbits.T5CKPS1 // bit 5
11180 #define TMR5CS0 T5CONbits.TMR5CS0 // bit 6
11181 #define TMR5CS1 T5CONbits.TMR5CS1 // bit 7
11183 #define T5GSS0 T5GCONbits.T5GSS0 // bit 0
11184 #define T5GSS1 T5GCONbits.T5GSS1 // bit 1
11185 #define T5GVAL T5GCONbits.T5GVAL // bit 2
11186 #define T5GGO_NOT_DONE T5GCONbits.T5GGO_NOT_DONE // bit 3
11187 #define T5GSPM T5GCONbits.T5GSPM // bit 4
11188 #define T5GTM T5GCONbits.T5GTM // bit 5
11189 #define T5GPOL T5GCONbits.T5GPOL // bit 6
11190 #define TMR5GE T5GCONbits.TMR5GE // bit 7
11192 #define T6CKPS0 T6CONbits.T6CKPS0 // bit 0
11193 #define T6CKPS1 T6CONbits.T6CKPS1 // bit 1
11194 #define TMR6ON T6CONbits.TMR6ON // bit 2
11195 #define T6OUTPS0 T6CONbits.T6OUTPS0 // bit 3
11196 #define T6OUTPS1 T6CONbits.T6OUTPS1 // bit 4
11197 #define T6OUTPS2 T6CONbits.T6OUTPS2 // bit 5
11198 #define T6OUTPS3 T6CONbits.T6OUTPS3 // bit 6
11200 #define TMR08 TMR0Hbits.TMR08 // bit 0
11201 #define TMR09 TMR0Hbits.TMR09 // bit 1
11202 #define TMR010 TMR0Hbits.TMR010 // bit 2
11203 #define TMR011 TMR0Hbits.TMR011 // bit 3
11204 #define TMR012 TMR0Hbits.TMR012 // bit 4
11205 #define TMR013 TMR0Hbits.TMR013 // bit 5
11206 #define TMR014 TMR0Hbits.TMR014 // bit 6
11207 #define TMR015 TMR0Hbits.TMR015 // bit 7
11209 #define TMR00 TMR0Lbits.TMR00 // bit 0
11210 #define TMR01 TMR0Lbits.TMR01 // bit 1
11211 #define TMR02 TMR0Lbits.TMR02 // bit 2
11212 #define TMR03 TMR0Lbits.TMR03 // bit 3
11213 #define TMR04 TMR0Lbits.TMR04 // bit 4
11214 #define TMR05 TMR0Lbits.TMR05 // bit 5
11215 #define TMR06 TMR0Lbits.TMR06 // bit 6
11216 #define TMR07 TMR0Lbits.TMR07 // bit 7
11218 #define TRISA0 TRISAbits.TRISA0 // bit 0
11219 #define TRISA1 TRISAbits.TRISA1 // bit 1
11220 #define TRISA2 TRISAbits.TRISA2 // bit 2
11221 #define TRISA4 TRISAbits.TRISA4 // bit 4
11222 #define TRISA5 TRISAbits.TRISA5 // bit 5
11224 #define TRISC0 TRISCbits.TRISC0 // bit 0
11225 #define TRISC1 TRISCbits.TRISC1 // bit 1
11226 #define TRISC2 TRISCbits.TRISC2 // bit 2
11227 #define TRISC3 TRISCbits.TRISC3 // bit 3
11228 #define TRISC4 TRISCbits.TRISC4 // bit 4
11229 #define TRISC5 TRISCbits.TRISC5 // bit 5
11231 #define TX9D TX1STAbits.TX9D // bit 0
11232 #define TRMT TX1STAbits.TRMT // bit 1
11233 #define BRGH TX1STAbits.BRGH // bit 2
11234 #define SENDB TX1STAbits.SENDB // bit 3
11235 #define SYNC TX1STAbits.SYNC // bit 4
11236 #define TXEN TX1STAbits.TXEN // bit 5
11237 #define TX9 TX1STAbits.TX9 // bit 6
11238 #define CSRC TX1STAbits.CSRC // bit 7
11240 #define TXCKPPS0 TXPPSbits.TXCKPPS0 // bit 0
11241 #define TXCKPPS1 TXPPSbits.TXCKPPS1 // bit 1
11242 #define TXCKPPS2 TXPPSbits.TXCKPPS2 // bit 2
11243 #define TXCKPPS3 TXPPSbits.TXCKPPS3 // bit 3
11244 #define TXCKPPS4 TXPPSbits.TXCKPPS4 // bit 4
11246 #define VREGPM VREGCONbits.VREGPM // bit 1
11248 #define SWDTEN WDTCONbits.SWDTEN // bit 0
11249 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
11250 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
11251 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
11252 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
11253 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
11255 #define WPUA0 WPUAbits.WPUA0 // bit 0
11256 #define WPUA1 WPUAbits.WPUA1 // bit 1
11257 #define WPUA2 WPUAbits.WPUA2 // bit 2
11258 #define WPUA3 WPUAbits.WPUA3 // bit 3
11259 #define WPUA4 WPUAbits.WPUA4 // bit 4
11260 #define WPUA5 WPUAbits.WPUA5 // bit 5
11262 #define WPUC0 WPUCbits.WPUC0 // bit 0
11263 #define WPUC1 WPUCbits.WPUC1 // bit 1
11264 #define WPUC2 WPUCbits.WPUC2 // bit 2
11265 #define WPUC3 WPUCbits.WPUC3 // bit 3
11266 #define WPUC4 WPUCbits.WPUC4 // bit 4
11267 #define WPUC5 WPUCbits.WPUC5 // bit 5
11269 #endif // #ifndef NO_BIT_DEFINES
11271 #endif // #ifndef __PIC16F18324_H__