2 * This declarations of the PIC16F18325 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:24 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F18325_H__
26 #define __PIC16F18325_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTC_ADDR 0x000E
52 #define PIR0_ADDR 0x0010
53 #define PIR1_ADDR 0x0011
54 #define PIR2_ADDR 0x0012
55 #define PIR3_ADDR 0x0013
56 #define PIR4_ADDR 0x0014
57 #define TMR0L_ADDR 0x0015
58 #define TMR0H_ADDR 0x0016
59 #define T0CON0_ADDR 0x0017
60 #define T0CON1_ADDR 0x0018
61 #define TMR1_ADDR 0x0019
62 #define TMR1L_ADDR 0x0019
63 #define TMR1H_ADDR 0x001A
64 #define T1CON_ADDR 0x001B
65 #define T1GCON_ADDR 0x001C
66 #define TMR2_ADDR 0x001D
67 #define PR2_ADDR 0x001E
68 #define T2CON_ADDR 0x001F
69 #define TRISA_ADDR 0x008C
70 #define TRISC_ADDR 0x008E
71 #define PIE0_ADDR 0x0090
72 #define PIE1_ADDR 0x0091
73 #define PIE2_ADDR 0x0092
74 #define PIE3_ADDR 0x0093
75 #define PIE4_ADDR 0x0094
76 #define WDTCON_ADDR 0x0097
77 #define ADRES_ADDR 0x009B
78 #define ADRESL_ADDR 0x009B
79 #define ADRESH_ADDR 0x009C
80 #define ADCON0_ADDR 0x009D
81 #define ADCON1_ADDR 0x009E
82 #define ADACT_ADDR 0x009F
83 #define LATA_ADDR 0x010C
84 #define LATC_ADDR 0x010E
85 #define CM1CON0_ADDR 0x0111
86 #define CM1CON1_ADDR 0x0112
87 #define CM2CON0_ADDR 0x0113
88 #define CM2CON1_ADDR 0x0114
89 #define CMOUT_ADDR 0x0115
90 #define BORCON_ADDR 0x0116
91 #define FVRCON_ADDR 0x0117
92 #define DACCON0_ADDR 0x0118
93 #define DACCON1_ADDR 0x0119
94 #define ANSELA_ADDR 0x018C
95 #define ANSELC_ADDR 0x018E
96 #define VREGCON_ADDR 0x0197
97 #define RC1REG_ADDR 0x0199
98 #define RCREG_ADDR 0x0199
99 #define RCREG1_ADDR 0x0199
100 #define TX1REG_ADDR 0x019A
101 #define TXREG_ADDR 0x019A
102 #define TXREG1_ADDR 0x019A
103 #define SP1BRG_ADDR 0x019B
104 #define SP1BRGL_ADDR 0x019B
105 #define SPBRG_ADDR 0x019B
106 #define SPBRG1_ADDR 0x019B
107 #define SPBRGL_ADDR 0x019B
108 #define SP1BRGH_ADDR 0x019C
109 #define SPBRGH_ADDR 0x019C
110 #define SPBRGH1_ADDR 0x019C
111 #define RC1STA_ADDR 0x019D
112 #define RCSTA_ADDR 0x019D
113 #define RCSTA1_ADDR 0x019D
114 #define TX1STA_ADDR 0x019E
115 #define TXSTA_ADDR 0x019E
116 #define TXSTA1_ADDR 0x019E
117 #define BAUD1CON_ADDR 0x019F
118 #define BAUDCON_ADDR 0x019F
119 #define BAUDCON1_ADDR 0x019F
120 #define BAUDCTL_ADDR 0x019F
121 #define BAUDCTL1_ADDR 0x019F
122 #define WPUA_ADDR 0x020C
123 #define WPUC_ADDR 0x020E
124 #define SSP1BUF_ADDR 0x0211
125 #define SSPBUF_ADDR 0x0211
126 #define SSP1ADD_ADDR 0x0212
127 #define SSPADD_ADDR 0x0212
128 #define SSP1MSK_ADDR 0x0213
129 #define SSPMSK_ADDR 0x0213
130 #define SSP1STAT_ADDR 0x0214
131 #define SSPSTAT_ADDR 0x0214
132 #define SSP1CON_ADDR 0x0215
133 #define SSP1CON1_ADDR 0x0215
134 #define SSPCON_ADDR 0x0215
135 #define SSPCON1_ADDR 0x0215
136 #define SSP1CON2_ADDR 0x0216
137 #define SSPCON2_ADDR 0x0216
138 #define SSP1CON3_ADDR 0x0217
139 #define SSPCON3_ADDR 0x0217
140 #define SSP2BUF_ADDR 0x0219
141 #define SSP2ADD_ADDR 0x021A
142 #define SSP2MSK_ADDR 0x021B
143 #define SSP2STAT_ADDR 0x021C
144 #define SSP2CON_ADDR 0x021D
145 #define SSP2CON1_ADDR 0x021D
146 #define SSP2CON2_ADDR 0x021E
147 #define SSP2CON3_ADDR 0x021F
148 #define ODCONA_ADDR 0x028C
149 #define ODCONC_ADDR 0x028E
150 #define CCPR1_ADDR 0x0291
151 #define CCPR1L_ADDR 0x0291
152 #define CCPR1H_ADDR 0x0292
153 #define CCP1CON_ADDR 0x0293
154 #define CCP1CAP_ADDR 0x0294
155 #define CCPR2_ADDR 0x0295
156 #define CCPR2L_ADDR 0x0295
157 #define CCPR2H_ADDR 0x0296
158 #define CCP2CON_ADDR 0x0297
159 #define CCP2CAP_ADDR 0x0298
160 #define CCPTMRS_ADDR 0x029F
161 #define SLRCONA_ADDR 0x030C
162 #define SLRCONC_ADDR 0x030E
163 #define CCPR3_ADDR 0x0311
164 #define CCPR3L_ADDR 0x0311
165 #define CCPR3H_ADDR 0x0312
166 #define CCP3CON_ADDR 0x0313
167 #define CCP3CAP_ADDR 0x0314
168 #define CCPR4_ADDR 0x0315
169 #define CCPR4L_ADDR 0x0315
170 #define CCPR4H_ADDR 0x0316
171 #define CCP4CON_ADDR 0x0317
172 #define CCP4CAP_ADDR 0x0318
173 #define INLVLA_ADDR 0x038C
174 #define INLVLC_ADDR 0x038E
175 #define IOCAP_ADDR 0x0391
176 #define IOCAN_ADDR 0x0392
177 #define IOCAF_ADDR 0x0393
178 #define IOCCP_ADDR 0x0397
179 #define IOCCN_ADDR 0x0398
180 #define IOCCF_ADDR 0x0399
181 #define CLKRCON_ADDR 0x039A
182 #define MDCON_ADDR 0x039C
183 #define MDSRC_ADDR 0x039D
184 #define MDCARH_ADDR 0x039E
185 #define MDCARL_ADDR 0x039F
186 #define CCDNA_ADDR 0x040C
187 #define CCDNC_ADDR 0x040E
188 #define TMR3_ADDR 0x0411
189 #define TMR3L_ADDR 0x0411
190 #define TMR3H_ADDR 0x0412
191 #define T3CON_ADDR 0x0413
192 #define T3GCON_ADDR 0x0414
193 #define TMR4_ADDR 0x0415
194 #define PR4_ADDR 0x0416
195 #define T4CON_ADDR 0x0417
196 #define TMR5_ADDR 0x0418
197 #define TMR5L_ADDR 0x0418
198 #define TMR5H_ADDR 0x0419
199 #define T5CON_ADDR 0x041A
200 #define T5GCON_ADDR 0x041B
201 #define TMR6_ADDR 0x041C
202 #define PR6_ADDR 0x041D
203 #define T6CON_ADDR 0x041E
204 #define CCDCON_ADDR 0x041F
205 #define CCDPA_ADDR 0x048C
206 #define CCDPC_ADDR 0x048E
207 #define NCO1ACC_ADDR 0x0498
208 #define NCO1ACCL_ADDR 0x0498
209 #define NCO1ACCH_ADDR 0x0499
210 #define NCO1ACCU_ADDR 0x049A
211 #define NCO1INC_ADDR 0x049B
212 #define NCO1INCL_ADDR 0x049B
213 #define NCO1INCH_ADDR 0x049C
214 #define NCO1INCU_ADDR 0x049D
215 #define NCO1CON_ADDR 0x049E
216 #define NCO1CLK_ADDR 0x049F
217 #define PWM5DCL_ADDR 0x0617
218 #define PWM5DCH_ADDR 0x0618
219 #define PWM5CON_ADDR 0x0619
220 #define PWM5CON0_ADDR 0x0619
221 #define PWM6DCL_ADDR 0x061A
222 #define PWM6DCH_ADDR 0x061B
223 #define PWM6CON_ADDR 0x061C
224 #define PWM6CON0_ADDR 0x061C
225 #define PWMTMRS_ADDR 0x061F
226 #define CWG1CLKCON_ADDR 0x0691
227 #define CWG1DAT_ADDR 0x0692
228 #define CWG1DBR_ADDR 0x0693
229 #define CWG1DBF_ADDR 0x0694
230 #define CWG1CON0_ADDR 0x0695
231 #define CWG1CON1_ADDR 0x0696
232 #define CWG1AS0_ADDR 0x0697
233 #define CWG1AS1_ADDR 0x0698
234 #define CWG1STR_ADDR 0x0699
235 #define CWG2CLKCON_ADDR 0x0711
236 #define CWG2DAT_ADDR 0x0712
237 #define CWG2DBR_ADDR 0x0713
238 #define CWG2DBF_ADDR 0x0714
239 #define CWG2CON0_ADDR 0x0715
240 #define CWG2CON1_ADDR 0x0716
241 #define CWG2AS0_ADDR 0x0717
242 #define CWG2AS1_ADDR 0x0718
243 #define CWG2STR_ADDR 0x0719
244 #define NVMADR_ADDR 0x0891
245 #define NVMADRL_ADDR 0x0891
246 #define NVMADRH_ADDR 0x0892
247 #define NVMDAT_ADDR 0x0893
248 #define NVMDATL_ADDR 0x0893
249 #define NVMDATH_ADDR 0x0894
250 #define NVMCON1_ADDR 0x0895
251 #define NVMCON2_ADDR 0x0896
252 #define PCON0_ADDR 0x089B
253 #define PMD0_ADDR 0x0911
254 #define PMD1_ADDR 0x0912
255 #define PMD2_ADDR 0x0913
256 #define PMD3_ADDR 0x0914
257 #define PMD4_ADDR 0x0915
258 #define PMD5_ADDR 0x0916
259 #define CPUDOZE_ADDR 0x0918
260 #define OSCCON1_ADDR 0x0919
261 #define OSCCON2_ADDR 0x091A
262 #define OSCCON3_ADDR 0x091B
263 #define OSCSTAT1_ADDR 0x091C
264 #define OSCEN_ADDR 0x091D
265 #define OSCTUNE_ADDR 0x091E
266 #define OSCFRQ_ADDR 0x091F
267 #define PPSLOCK_ADDR 0x0E0F
268 #define INTPPS_ADDR 0x0E10
269 #define T0CKIPPS_ADDR 0x0E11
270 #define T1CKIPPS_ADDR 0x0E12
271 #define T1GPPS_ADDR 0x0E13
272 #define CCP1PPS_ADDR 0x0E14
273 #define CCP2PPS_ADDR 0x0E15
274 #define CCP3PPS_ADDR 0x0E16
275 #define CCP4PPS_ADDR 0x0E17
276 #define CWG1PPS_ADDR 0x0E18
277 #define CWG2PPS_ADDR 0x0E19
278 #define MDCIN1PPS_ADDR 0x0E1A
279 #define MDCIN2PPS_ADDR 0x0E1B
280 #define MDMINPPS_ADDR 0x0E1C
281 #define SSP2CLKPPS_ADDR 0x0E1D
282 #define SSP2DATPPS_ADDR 0x0E1E
283 #define SSP2SSPPS_ADDR 0x0E1F
284 #define SSP1CLKPPS_ADDR 0x0E20
285 #define SSP1DATPPS_ADDR 0x0E21
286 #define SSP1SSPPS_ADDR 0x0E22
287 #define RXPPS_ADDR 0x0E24
288 #define TXPPS_ADDR 0x0E25
289 #define CLCIN0PPS_ADDR 0x0E28
290 #define CLCIN1PPS_ADDR 0x0E29
291 #define CLCIN2PPS_ADDR 0x0E2A
292 #define CLCIN3PPS_ADDR 0x0E2B
293 #define T3CKIPPS_ADDR 0x0E2C
294 #define T3GPPS_ADDR 0x0E2D
295 #define T5CKIPPS_ADDR 0x0E2E
296 #define T5GPPS_ADDR 0x0E2F
297 #define RA0PPS_ADDR 0x0E90
298 #define RA1PPS_ADDR 0x0E91
299 #define RA2PPS_ADDR 0x0E92
300 #define RA4PPS_ADDR 0x0E94
301 #define RA5PPS_ADDR 0x0E95
302 #define RC0PPS_ADDR 0x0EA0
303 #define RC1PPS_ADDR 0x0EA1
304 #define RC2PPS_ADDR 0x0EA2
305 #define RC3PPS_ADDR 0x0EA3
306 #define RC4PPS_ADDR 0x0EA4
307 #define RC5PPS_ADDR 0x0EA5
308 #define CLCDATA_ADDR 0x0F0F
309 #define CLC1CON_ADDR 0x0F10
310 #define CLC1POL_ADDR 0x0F11
311 #define CLC1SEL0_ADDR 0x0F12
312 #define CLC1SEL1_ADDR 0x0F13
313 #define CLC1SEL2_ADDR 0x0F14
314 #define CLC1SEL3_ADDR 0x0F15
315 #define CLC1GLS0_ADDR 0x0F16
316 #define CLC1GLS1_ADDR 0x0F17
317 #define CLC1GLS2_ADDR 0x0F18
318 #define CLC1GLS3_ADDR 0x0F19
319 #define CLC2CON_ADDR 0x0F1A
320 #define CLC2POL_ADDR 0x0F1B
321 #define CLC2SEL0_ADDR 0x0F1C
322 #define CLC2SEL1_ADDR 0x0F1D
323 #define CLC2SEL2_ADDR 0x0F1E
324 #define CLC2SEL3_ADDR 0x0F1F
325 #define CLC2GLS0_ADDR 0x0F20
326 #define CLC2GLS1_ADDR 0x0F21
327 #define CLC2GLS2_ADDR 0x0F22
328 #define CLC2GLS3_ADDR 0x0F23
329 #define CLC3CON_ADDR 0x0F24
330 #define CLC3POL_ADDR 0x0F25
331 #define CLC3SEL0_ADDR 0x0F26
332 #define CLC3SEL1_ADDR 0x0F27
333 #define CLC3SEL2_ADDR 0x0F28
334 #define CLC3SEL3_ADDR 0x0F29
335 #define CLC3GLS0_ADDR 0x0F2A
336 #define CLC3GLS1_ADDR 0x0F2B
337 #define CLC3GLS2_ADDR 0x0F2C
338 #define CLC3GLS3_ADDR 0x0F2D
339 #define CLC4CON_ADDR 0x0F2E
340 #define CLC4POL_ADDR 0x0F2F
341 #define CLC4SEL0_ADDR 0x0F30
342 #define CLC4SEL1_ADDR 0x0F31
343 #define CLC4SEL2_ADDR 0x0F32
344 #define CLC4SEL3_ADDR 0x0F33
345 #define CLC4GLS0_ADDR 0x0F34
346 #define CLC4GLS1_ADDR 0x0F35
347 #define CLC4GLS2_ADDR 0x0F36
348 #define CLC4GLS3_ADDR 0x0F37
349 #define STATUS_SHAD_ADDR 0x0FE4
350 #define WREG_SHAD_ADDR 0x0FE5
351 #define BSR_SHAD_ADDR 0x0FE6
352 #define PCLATH_SHAD_ADDR 0x0FE7
353 #define FSR0L_SHAD_ADDR 0x0FE8
354 #define FSR0H_SHAD_ADDR 0x0FE9
355 #define FSR1L_SHAD_ADDR 0x0FEA
356 #define FSR1H_SHAD_ADDR 0x0FEB
357 #define STKPTR_ADDR 0x0FED
358 #define TOSL_ADDR 0x0FEE
359 #define TOSH_ADDR 0x0FEF
361 #endif // #ifndef NO_ADDR_DEFINES
363 //==============================================================================
365 // Register Definitions
367 //==============================================================================
369 extern __at(0x0000) __sfr INDF0
;
370 extern __at(0x0001) __sfr INDF1
;
371 extern __at(0x0002) __sfr PCL
;
373 //==============================================================================
376 extern __at(0x0003) __sfr STATUS
;
390 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
398 //==============================================================================
400 extern __at(0x0004) __sfr FSR0
;
401 extern __at(0x0004) __sfr FSR0L
;
402 extern __at(0x0005) __sfr FSR0H
;
403 extern __at(0x0006) __sfr FSR1
;
404 extern __at(0x0006) __sfr FSR1L
;
405 extern __at(0x0007) __sfr FSR1H
;
407 //==============================================================================
410 extern __at(0x0008) __sfr BSR
;
433 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
441 //==============================================================================
443 extern __at(0x0009) __sfr WREG
;
444 extern __at(0x000A) __sfr PCLATH
;
446 //==============================================================================
449 extern __at(0x000B) __sfr INTCON
;
463 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
469 //==============================================================================
472 //==============================================================================
475 extern __at(0x000C) __sfr PORTA
;
498 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
507 //==============================================================================
510 //==============================================================================
513 extern __at(0x000E) __sfr PORTC
;
536 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
545 //==============================================================================
548 //==============================================================================
551 extern __at(0x0010) __sfr PIR0
;
565 extern __at(0x0010) volatile __PIR0bits_t PIR0bits
;
571 //==============================================================================
574 //==============================================================================
577 extern __at(0x0011) __sfr PIR1
;
588 unsigned TMR1GIF
: 1;
591 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
600 #define _TMR1GIF 0x80
602 //==============================================================================
605 //==============================================================================
608 extern __at(0x0012) __sfr PIR2
;
622 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
633 //==============================================================================
636 //==============================================================================
639 extern __at(0x0013) __sfr PIR3
;
648 unsigned TMR3GIF
: 1;
653 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
660 #define _TMR3GIF 0x20
664 //==============================================================================
667 //==============================================================================
670 extern __at(0x0014) __sfr PIR4
;
679 unsigned TMR5GIF
: 1;
684 extern __at(0x0014) volatile __PIR4bits_t PIR4bits
;
691 #define _TMR5GIF 0x20
695 //==============================================================================
698 //==============================================================================
701 extern __at(0x0015) __sfr TMR0L
;
715 extern __at(0x0015) volatile __TMR0Lbits_t TMR0Lbits
;
726 //==============================================================================
729 //==============================================================================
732 extern __at(0x0016) __sfr TMR0H
;
746 extern __at(0x0016) volatile __TMR0Hbits_t TMR0Hbits
;
757 //==============================================================================
760 //==============================================================================
763 extern __at(0x0017) __sfr T0CON0
;
769 unsigned T0OUTPS0
: 1;
770 unsigned T0OUTPS1
: 1;
771 unsigned T0OUTPS2
: 1;
772 unsigned T0OUTPS3
: 1;
773 unsigned T016BIT
: 1;
781 unsigned T0OUTPS
: 4;
786 extern __at(0x0017) volatile __T0CON0bits_t T0CON0bits
;
788 #define _T0OUTPS0 0x01
789 #define _T0OUTPS1 0x02
790 #define _T0OUTPS2 0x04
791 #define _T0OUTPS3 0x08
792 #define _T016BIT 0x10
796 //==============================================================================
799 //==============================================================================
802 extern __at(0x0018) __sfr T0CON1
;
808 unsigned T0CKPS0
: 1;
809 unsigned T0CKPS1
: 1;
810 unsigned T0CKPS2
: 1;
811 unsigned T0CKPS3
: 1;
812 unsigned T0ASYNC
: 1;
831 extern __at(0x0018) volatile __T0CON1bits_t T0CON1bits
;
833 #define _T0CKPS0 0x01
834 #define _T0CKPS1 0x02
835 #define _T0CKPS2 0x04
836 #define _T0CKPS3 0x08
837 #define _T0ASYNC 0x10
842 //==============================================================================
844 extern __at(0x0019) __sfr TMR1
;
845 extern __at(0x0019) __sfr TMR1L
;
846 extern __at(0x001A) __sfr TMR1H
;
848 //==============================================================================
851 extern __at(0x001B) __sfr T1CON
;
861 unsigned T1CKPS0
: 1;
862 unsigned T1CKPS1
: 1;
863 unsigned TMR1CS0
: 1;
864 unsigned TMR1CS1
: 1;
881 extern __at(0x001B) volatile __T1CONbits_t T1CONbits
;
886 #define _T1CKPS0 0x10
887 #define _T1CKPS1 0x20
888 #define _TMR1CS0 0x40
889 #define _TMR1CS1 0x80
891 //==============================================================================
894 //==============================================================================
897 extern __at(0x001C) __sfr T1GCON
;
906 unsigned T1GGO_NOT_DONE
: 1;
920 extern __at(0x001C) volatile __T1GCONbits_t T1GCONbits
;
925 #define _T1GGO_NOT_DONE 0x08
931 //==============================================================================
933 extern __at(0x001D) __sfr TMR2
;
934 extern __at(0x001E) __sfr PR2
;
936 //==============================================================================
939 extern __at(0x001F) __sfr T2CON
;
945 unsigned T2CKPS0
: 1;
946 unsigned T2CKPS1
: 1;
948 unsigned T2OUTPS0
: 1;
949 unsigned T2OUTPS1
: 1;
950 unsigned T2OUTPS2
: 1;
951 unsigned T2OUTPS3
: 1;
964 unsigned T2OUTPS
: 4;
969 extern __at(0x001F) volatile __T2CONbits_t T2CONbits
;
971 #define _T2CKPS0 0x01
972 #define _T2CKPS1 0x02
974 #define _T2OUTPS0 0x08
975 #define _T2OUTPS1 0x10
976 #define _T2OUTPS2 0x20
977 #define _T2OUTPS3 0x40
979 //==============================================================================
982 //==============================================================================
985 extern __at(0x008C) __sfr TRISA
;
999 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
1001 #define _TRISA0 0x01
1002 #define _TRISA1 0x02
1003 #define _TRISA2 0x04
1004 #define _TRISA4 0x10
1005 #define _TRISA5 0x20
1007 //==============================================================================
1010 //==============================================================================
1013 extern __at(0x008E) __sfr TRISC
;
1019 unsigned TRISC0
: 1;
1020 unsigned TRISC1
: 1;
1021 unsigned TRISC2
: 1;
1022 unsigned TRISC3
: 1;
1023 unsigned TRISC4
: 1;
1024 unsigned TRISC5
: 1;
1036 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
1038 #define _TRISC0 0x01
1039 #define _TRISC1 0x02
1040 #define _TRISC2 0x04
1041 #define _TRISC3 0x08
1042 #define _TRISC4 0x10
1043 #define _TRISC5 0x20
1045 //==============================================================================
1048 //==============================================================================
1051 extern __at(0x0090) __sfr PIE0
;
1060 unsigned TMR0IE
: 1;
1065 extern __at(0x0090) volatile __PIE0bits_t PIE0bits
;
1069 #define _TMR0IE 0x20
1071 //==============================================================================
1074 //==============================================================================
1077 extern __at(0x0091) __sfr PIE1
;
1081 unsigned TMR1IE
: 1;
1082 unsigned TMR2IE
: 1;
1083 unsigned BCL1IE
: 1;
1084 unsigned SSP1IE
: 1;
1088 unsigned TMR1GIE
: 1;
1091 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
1093 #define _TMR1IE 0x01
1094 #define _TMR2IE 0x02
1095 #define _BCL1IE 0x04
1096 #define _SSP1IE 0x08
1100 #define _TMR1GIE 0x80
1102 //==============================================================================
1105 //==============================================================================
1108 extern __at(0x0092) __sfr PIE2
;
1112 unsigned NCO1IE
: 1;
1113 unsigned TMR4IE
: 1;
1114 unsigned BCL2IE
: 1;
1115 unsigned SSP2IE
: 1;
1119 unsigned TMR6IE
: 1;
1122 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
1124 #define _NCO1IE 0x01
1125 #define _TMR4IE 0x02
1126 #define _BCL2IE 0x04
1127 #define _SSP2IE 0x08
1131 #define _TMR6IE 0x80
1133 //==============================================================================
1136 //==============================================================================
1139 extern __at(0x0093) __sfr PIE3
;
1143 unsigned CLC1IE
: 1;
1144 unsigned CLC2IE
: 1;
1145 unsigned CLC3IE
: 1;
1146 unsigned CLC4IE
: 1;
1147 unsigned TMR3IE
: 1;
1148 unsigned TMR3GIE
: 1;
1153 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
1155 #define _CLC1IE 0x01
1156 #define _CLC2IE 0x02
1157 #define _CLC3IE 0x04
1158 #define _CLC4IE 0x08
1159 #define _TMR3IE 0x10
1160 #define _TMR3GIE 0x20
1164 //==============================================================================
1167 //==============================================================================
1170 extern __at(0x0094) __sfr PIE4
;
1174 unsigned CCP1IE
: 1;
1175 unsigned CCP2IE
: 1;
1176 unsigned CCP3IE
: 1;
1177 unsigned CCP4IE
: 1;
1178 unsigned TMR5IE
: 1;
1179 unsigned TMR5GIE
: 1;
1180 unsigned CWG1IE
: 1;
1181 unsigned CWG2IE
: 1;
1184 extern __at(0x0094) volatile __PIE4bits_t PIE4bits
;
1186 #define _CCP1IE 0x01
1187 #define _CCP2IE 0x02
1188 #define _CCP3IE 0x04
1189 #define _CCP4IE 0x08
1190 #define _TMR5IE 0x10
1191 #define _TMR5GIE 0x20
1192 #define _CWG1IE 0x40
1193 #define _CWG2IE 0x80
1195 //==============================================================================
1198 //==============================================================================
1201 extern __at(0x0097) __sfr WDTCON
;
1207 unsigned SWDTEN
: 1;
1208 unsigned WDTPS0
: 1;
1209 unsigned WDTPS1
: 1;
1210 unsigned WDTPS2
: 1;
1211 unsigned WDTPS3
: 1;
1212 unsigned WDTPS4
: 1;
1225 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1227 #define _SWDTEN 0x01
1228 #define _WDTPS0 0x02
1229 #define _WDTPS1 0x04
1230 #define _WDTPS2 0x08
1231 #define _WDTPS3 0x10
1232 #define _WDTPS4 0x20
1234 //==============================================================================
1236 extern __at(0x009B) __sfr ADRES
;
1237 extern __at(0x009B) __sfr ADRESL
;
1238 extern __at(0x009C) __sfr ADRESH
;
1240 //==============================================================================
1243 extern __at(0x009D) __sfr ADCON0
;
1250 unsigned GO_NOT_DONE
: 1;
1290 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1293 #define _GO_NOT_DONE 0x02
1303 //==============================================================================
1306 //==============================================================================
1309 extern __at(0x009E) __sfr ADCON1
;
1315 unsigned ADPREF0
: 1;
1316 unsigned ADPREF1
: 1;
1317 unsigned ADNREF
: 1;
1327 unsigned ADPREF
: 2;
1339 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1341 #define _ADPREF0 0x01
1342 #define _ADPREF1 0x02
1343 #define _ADNREF 0x04
1349 //==============================================================================
1352 //==============================================================================
1355 extern __at(0x009F) __sfr ADACT
;
1361 unsigned ADACT0
: 1;
1362 unsigned ADACT1
: 1;
1363 unsigned ADACT2
: 1;
1364 unsigned ADACT3
: 1;
1365 unsigned ADACT4
: 1;
1378 extern __at(0x009F) volatile __ADACTbits_t ADACTbits
;
1380 #define _ADACT0 0x01
1381 #define _ADACT1 0x02
1382 #define _ADACT2 0x04
1383 #define _ADACT3 0x08
1384 #define _ADACT4 0x10
1386 //==============================================================================
1389 //==============================================================================
1392 extern __at(0x010C) __sfr LATA
;
1406 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1414 //==============================================================================
1417 //==============================================================================
1420 extern __at(0x010E) __sfr LATC
;
1443 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1452 //==============================================================================
1455 //==============================================================================
1458 extern __at(0x0111) __sfr CM1CON0
;
1462 unsigned C1SYNC
: 1;
1472 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1474 #define _C1SYNC 0x01
1481 //==============================================================================
1484 //==============================================================================
1487 extern __at(0x0112) __sfr CM1CON1
;
1493 unsigned C1NCH0
: 1;
1494 unsigned C1NCH1
: 1;
1495 unsigned C1NCH2
: 1;
1496 unsigned C1PCH0
: 1;
1497 unsigned C1PCH1
: 1;
1498 unsigned C1PCH2
: 1;
1499 unsigned C1INTN
: 1;
1500 unsigned C1INTP
: 1;
1517 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1519 #define _C1NCH0 0x01
1520 #define _C1NCH1 0x02
1521 #define _C1NCH2 0x04
1522 #define _C1PCH0 0x08
1523 #define _C1PCH1 0x10
1524 #define _C1PCH2 0x20
1525 #define _C1INTN 0x40
1526 #define _C1INTP 0x80
1528 //==============================================================================
1531 //==============================================================================
1534 extern __at(0x0113) __sfr CM2CON0
;
1538 unsigned C2SYNC
: 1;
1548 extern __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits
;
1550 #define _C2SYNC 0x01
1557 //==============================================================================
1560 //==============================================================================
1563 extern __at(0x0114) __sfr CM2CON1
;
1569 unsigned C2NCH0
: 1;
1570 unsigned C2NCH1
: 1;
1571 unsigned C2NCH2
: 1;
1572 unsigned C2PCH0
: 1;
1573 unsigned C2PCH1
: 1;
1574 unsigned C2PCH2
: 1;
1575 unsigned C2INTN
: 1;
1576 unsigned C2INTP
: 1;
1593 extern __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits
;
1595 #define _C2NCH0 0x01
1596 #define _C2NCH1 0x02
1597 #define _C2NCH2 0x04
1598 #define _C2PCH0 0x08
1599 #define _C2PCH1 0x10
1600 #define _C2PCH2 0x20
1601 #define _C2INTN 0x40
1602 #define _C2INTP 0x80
1604 //==============================================================================
1607 //==============================================================================
1610 extern __at(0x0115) __sfr CMOUT
;
1614 unsigned MC1OUT
: 1;
1615 unsigned MC2OUT
: 1;
1624 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1626 #define _MC1OUT 0x01
1627 #define _MC2OUT 0x02
1629 //==============================================================================
1632 //==============================================================================
1635 extern __at(0x0116) __sfr BORCON
;
1639 unsigned BORRDY
: 1;
1646 unsigned SBOREN
: 1;
1649 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1651 #define _BORRDY 0x01
1652 #define _SBOREN 0x80
1654 //==============================================================================
1657 //==============================================================================
1660 extern __at(0x0117) __sfr FVRCON
;
1666 unsigned ADFVR0
: 1;
1667 unsigned ADFVR1
: 1;
1668 unsigned CDAFVR0
: 1;
1669 unsigned CDAFVR1
: 1;
1672 unsigned FVRRDY
: 1;
1685 unsigned CDAFVR
: 2;
1690 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1692 #define _ADFVR0 0x01
1693 #define _ADFVR1 0x02
1694 #define _CDAFVR0 0x04
1695 #define _CDAFVR1 0x08
1698 #define _FVRRDY 0x40
1701 //==============================================================================
1704 //==============================================================================
1707 extern __at(0x0118) __sfr DACCON0
;
1713 unsigned DAC1NSS
: 1;
1715 unsigned DAC1PSS0
: 1;
1716 unsigned DAC1PSS1
: 1;
1718 unsigned DAC1OE
: 1;
1720 unsigned DAC1EN
: 1;
1726 unsigned DAC1PSS
: 2;
1731 extern __at(0x0118) volatile __DACCON0bits_t DACCON0bits
;
1733 #define _DAC1NSS 0x01
1734 #define _DAC1PSS0 0x04
1735 #define _DAC1PSS1 0x08
1736 #define _DAC1OE 0x20
1737 #define _DAC1EN 0x80
1739 //==============================================================================
1742 //==============================================================================
1745 extern __at(0x0119) __sfr DACCON1
;
1751 unsigned DAC1R0
: 1;
1752 unsigned DAC1R1
: 1;
1753 unsigned DAC1R2
: 1;
1754 unsigned DAC1R3
: 1;
1755 unsigned DAC1R4
: 1;
1768 extern __at(0x0119) volatile __DACCON1bits_t DACCON1bits
;
1770 #define _DAC1R0 0x01
1771 #define _DAC1R1 0x02
1772 #define _DAC1R2 0x04
1773 #define _DAC1R3 0x08
1774 #define _DAC1R4 0x10
1776 //==============================================================================
1779 //==============================================================================
1782 extern __at(0x018C) __sfr ANSELA
;
1796 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1804 //==============================================================================
1807 //==============================================================================
1810 extern __at(0x018E) __sfr ANSELC
;
1833 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
1842 //==============================================================================
1845 //==============================================================================
1848 extern __at(0x0197) __sfr VREGCON
;
1853 unsigned VREGPM
: 1;
1862 extern __at(0x0197) volatile __VREGCONbits_t VREGCONbits
;
1864 #define _VREGPM 0x02
1866 //==============================================================================
1868 extern __at(0x0199) __sfr RC1REG
;
1869 extern __at(0x0199) __sfr RCREG
;
1870 extern __at(0x0199) __sfr RCREG1
;
1871 extern __at(0x019A) __sfr TX1REG
;
1872 extern __at(0x019A) __sfr TXREG
;
1873 extern __at(0x019A) __sfr TXREG1
;
1874 extern __at(0x019B) __sfr SP1BRG
;
1875 extern __at(0x019B) __sfr SP1BRGL
;
1876 extern __at(0x019B) __sfr SPBRG
;
1877 extern __at(0x019B) __sfr SPBRG1
;
1878 extern __at(0x019B) __sfr SPBRGL
;
1879 extern __at(0x019C) __sfr SP1BRGH
;
1880 extern __at(0x019C) __sfr SPBRGH
;
1881 extern __at(0x019C) __sfr SPBRGH1
;
1883 //==============================================================================
1886 extern __at(0x019D) __sfr RC1STA
;
1900 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
1911 //==============================================================================
1914 //==============================================================================
1917 extern __at(0x019D) __sfr RCSTA
;
1931 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
1933 #define _RCSTA_RX9D 0x01
1934 #define _RCSTA_OERR 0x02
1935 #define _RCSTA_FERR 0x04
1936 #define _RCSTA_ADDEN 0x08
1937 #define _RCSTA_CREN 0x10
1938 #define _RCSTA_SREN 0x20
1939 #define _RCSTA_RX9 0x40
1940 #define _RCSTA_SPEN 0x80
1942 //==============================================================================
1945 //==============================================================================
1948 extern __at(0x019D) __sfr RCSTA1
;
1962 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
1964 #define _RCSTA1_RX9D 0x01
1965 #define _RCSTA1_OERR 0x02
1966 #define _RCSTA1_FERR 0x04
1967 #define _RCSTA1_ADDEN 0x08
1968 #define _RCSTA1_CREN 0x10
1969 #define _RCSTA1_SREN 0x20
1970 #define _RCSTA1_RX9 0x40
1971 #define _RCSTA1_SPEN 0x80
1973 //==============================================================================
1976 //==============================================================================
1979 extern __at(0x019E) __sfr TX1STA
;
1993 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
2004 //==============================================================================
2007 //==============================================================================
2010 extern __at(0x019E) __sfr TXSTA
;
2024 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
2026 #define _TXSTA_TX9D 0x01
2027 #define _TXSTA_TRMT 0x02
2028 #define _TXSTA_BRGH 0x04
2029 #define _TXSTA_SENDB 0x08
2030 #define _TXSTA_SYNC 0x10
2031 #define _TXSTA_TXEN 0x20
2032 #define _TXSTA_TX9 0x40
2033 #define _TXSTA_CSRC 0x80
2035 //==============================================================================
2038 //==============================================================================
2041 extern __at(0x019E) __sfr TXSTA1
;
2055 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
2057 #define _TXSTA1_TX9D 0x01
2058 #define _TXSTA1_TRMT 0x02
2059 #define _TXSTA1_BRGH 0x04
2060 #define _TXSTA1_SENDB 0x08
2061 #define _TXSTA1_SYNC 0x10
2062 #define _TXSTA1_TXEN 0x20
2063 #define _TXSTA1_TX9 0x40
2064 #define _TXSTA1_CSRC 0x80
2066 //==============================================================================
2069 //==============================================================================
2072 extern __at(0x019F) __sfr BAUD1CON
;
2083 unsigned ABDOVF
: 1;
2086 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
2093 #define _ABDOVF 0x80
2095 //==============================================================================
2098 //==============================================================================
2101 extern __at(0x019F) __sfr BAUDCON
;
2112 unsigned ABDOVF
: 1;
2115 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
2117 #define _BAUDCON_ABDEN 0x01
2118 #define _BAUDCON_WUE 0x02
2119 #define _BAUDCON_BRG16 0x08
2120 #define _BAUDCON_SCKP 0x10
2121 #define _BAUDCON_RCIDL 0x40
2122 #define _BAUDCON_ABDOVF 0x80
2124 //==============================================================================
2127 //==============================================================================
2130 extern __at(0x019F) __sfr BAUDCON1
;
2141 unsigned ABDOVF
: 1;
2144 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
2146 #define _BAUDCON1_ABDEN 0x01
2147 #define _BAUDCON1_WUE 0x02
2148 #define _BAUDCON1_BRG16 0x08
2149 #define _BAUDCON1_SCKP 0x10
2150 #define _BAUDCON1_RCIDL 0x40
2151 #define _BAUDCON1_ABDOVF 0x80
2153 //==============================================================================
2156 //==============================================================================
2159 extern __at(0x019F) __sfr BAUDCTL
;
2170 unsigned ABDOVF
: 1;
2173 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
2175 #define _BAUDCTL_ABDEN 0x01
2176 #define _BAUDCTL_WUE 0x02
2177 #define _BAUDCTL_BRG16 0x08
2178 #define _BAUDCTL_SCKP 0x10
2179 #define _BAUDCTL_RCIDL 0x40
2180 #define _BAUDCTL_ABDOVF 0x80
2182 //==============================================================================
2185 //==============================================================================
2188 extern __at(0x019F) __sfr BAUDCTL1
;
2199 unsigned ABDOVF
: 1;
2202 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
2204 #define _BAUDCTL1_ABDEN 0x01
2205 #define _BAUDCTL1_WUE 0x02
2206 #define _BAUDCTL1_BRG16 0x08
2207 #define _BAUDCTL1_SCKP 0x10
2208 #define _BAUDCTL1_RCIDL 0x40
2209 #define _BAUDCTL1_ABDOVF 0x80
2211 //==============================================================================
2214 //==============================================================================
2217 extern __at(0x020C) __sfr WPUA
;
2240 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
2249 //==============================================================================
2252 //==============================================================================
2255 extern __at(0x020E) __sfr WPUC
;
2278 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
2287 //==============================================================================
2290 //==============================================================================
2293 extern __at(0x0211) __sfr SSP1BUF
;
2299 unsigned SSP1BUF0
: 1;
2300 unsigned SSP1BUF1
: 1;
2301 unsigned SSP1BUF2
: 1;
2302 unsigned SSP1BUF3
: 1;
2303 unsigned SSP1BUF4
: 1;
2304 unsigned SSP1BUF5
: 1;
2305 unsigned SSP1BUF6
: 1;
2306 unsigned SSP1BUF7
: 1;
2322 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
2324 #define _SSP1BUF0 0x01
2326 #define _SSP1BUF1 0x02
2328 #define _SSP1BUF2 0x04
2330 #define _SSP1BUF3 0x08
2332 #define _SSP1BUF4 0x10
2334 #define _SSP1BUF5 0x20
2336 #define _SSP1BUF6 0x40
2338 #define _SSP1BUF7 0x80
2341 //==============================================================================
2344 //==============================================================================
2347 extern __at(0x0211) __sfr SSPBUF
;
2353 unsigned SSP1BUF0
: 1;
2354 unsigned SSP1BUF1
: 1;
2355 unsigned SSP1BUF2
: 1;
2356 unsigned SSP1BUF3
: 1;
2357 unsigned SSP1BUF4
: 1;
2358 unsigned SSP1BUF5
: 1;
2359 unsigned SSP1BUF6
: 1;
2360 unsigned SSP1BUF7
: 1;
2376 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
2378 #define _SSPBUF_SSP1BUF0 0x01
2379 #define _SSPBUF_BUF0 0x01
2380 #define _SSPBUF_SSP1BUF1 0x02
2381 #define _SSPBUF_BUF1 0x02
2382 #define _SSPBUF_SSP1BUF2 0x04
2383 #define _SSPBUF_BUF2 0x04
2384 #define _SSPBUF_SSP1BUF3 0x08
2385 #define _SSPBUF_BUF3 0x08
2386 #define _SSPBUF_SSP1BUF4 0x10
2387 #define _SSPBUF_BUF4 0x10
2388 #define _SSPBUF_SSP1BUF5 0x20
2389 #define _SSPBUF_BUF5 0x20
2390 #define _SSPBUF_SSP1BUF6 0x40
2391 #define _SSPBUF_BUF6 0x40
2392 #define _SSPBUF_SSP1BUF7 0x80
2393 #define _SSPBUF_BUF7 0x80
2395 //==============================================================================
2398 //==============================================================================
2401 extern __at(0x0212) __sfr SSP1ADD
;
2407 unsigned SSP1ADD0
: 1;
2408 unsigned SSP1ADD1
: 1;
2409 unsigned SSP1ADD2
: 1;
2410 unsigned SSP1ADD3
: 1;
2411 unsigned SSP1ADD4
: 1;
2412 unsigned SSP1ADD5
: 1;
2413 unsigned SSP1ADD6
: 1;
2414 unsigned SSP1ADD7
: 1;
2430 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
2432 #define _SSP1ADD0 0x01
2434 #define _SSP1ADD1 0x02
2436 #define _SSP1ADD2 0x04
2438 #define _SSP1ADD3 0x08
2440 #define _SSP1ADD4 0x10
2442 #define _SSP1ADD5 0x20
2444 #define _SSP1ADD6 0x40
2446 #define _SSP1ADD7 0x80
2449 //==============================================================================
2452 //==============================================================================
2455 extern __at(0x0212) __sfr SSPADD
;
2461 unsigned SSP1ADD0
: 1;
2462 unsigned SSP1ADD1
: 1;
2463 unsigned SSP1ADD2
: 1;
2464 unsigned SSP1ADD3
: 1;
2465 unsigned SSP1ADD4
: 1;
2466 unsigned SSP1ADD5
: 1;
2467 unsigned SSP1ADD6
: 1;
2468 unsigned SSP1ADD7
: 1;
2484 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
2486 #define _SSPADD_SSP1ADD0 0x01
2487 #define _SSPADD_ADD0 0x01
2488 #define _SSPADD_SSP1ADD1 0x02
2489 #define _SSPADD_ADD1 0x02
2490 #define _SSPADD_SSP1ADD2 0x04
2491 #define _SSPADD_ADD2 0x04
2492 #define _SSPADD_SSP1ADD3 0x08
2493 #define _SSPADD_ADD3 0x08
2494 #define _SSPADD_SSP1ADD4 0x10
2495 #define _SSPADD_ADD4 0x10
2496 #define _SSPADD_SSP1ADD5 0x20
2497 #define _SSPADD_ADD5 0x20
2498 #define _SSPADD_SSP1ADD6 0x40
2499 #define _SSPADD_ADD6 0x40
2500 #define _SSPADD_SSP1ADD7 0x80
2501 #define _SSPADD_ADD7 0x80
2503 //==============================================================================
2506 //==============================================================================
2509 extern __at(0x0213) __sfr SSP1MSK
;
2515 unsigned SSP1MSK0
: 1;
2516 unsigned SSP1MSK1
: 1;
2517 unsigned SSP1MSK2
: 1;
2518 unsigned SSP1MSK3
: 1;
2519 unsigned SSP1MSK4
: 1;
2520 unsigned SSP1MSK5
: 1;
2521 unsigned SSP1MSK6
: 1;
2522 unsigned SSP1MSK7
: 1;
2538 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
2540 #define _SSP1MSK0 0x01
2542 #define _SSP1MSK1 0x02
2544 #define _SSP1MSK2 0x04
2546 #define _SSP1MSK3 0x08
2548 #define _SSP1MSK4 0x10
2550 #define _SSP1MSK5 0x20
2552 #define _SSP1MSK6 0x40
2554 #define _SSP1MSK7 0x80
2557 //==============================================================================
2560 //==============================================================================
2563 extern __at(0x0213) __sfr SSPMSK
;
2569 unsigned SSP1MSK0
: 1;
2570 unsigned SSP1MSK1
: 1;
2571 unsigned SSP1MSK2
: 1;
2572 unsigned SSP1MSK3
: 1;
2573 unsigned SSP1MSK4
: 1;
2574 unsigned SSP1MSK5
: 1;
2575 unsigned SSP1MSK6
: 1;
2576 unsigned SSP1MSK7
: 1;
2592 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
2594 #define _SSPMSK_SSP1MSK0 0x01
2595 #define _SSPMSK_MSK0 0x01
2596 #define _SSPMSK_SSP1MSK1 0x02
2597 #define _SSPMSK_MSK1 0x02
2598 #define _SSPMSK_SSP1MSK2 0x04
2599 #define _SSPMSK_MSK2 0x04
2600 #define _SSPMSK_SSP1MSK3 0x08
2601 #define _SSPMSK_MSK3 0x08
2602 #define _SSPMSK_SSP1MSK4 0x10
2603 #define _SSPMSK_MSK4 0x10
2604 #define _SSPMSK_SSP1MSK5 0x20
2605 #define _SSPMSK_MSK5 0x20
2606 #define _SSPMSK_SSP1MSK6 0x40
2607 #define _SSPMSK_MSK6 0x40
2608 #define _SSPMSK_SSP1MSK7 0x80
2609 #define _SSPMSK_MSK7 0x80
2611 //==============================================================================
2614 //==============================================================================
2617 extern __at(0x0214) __sfr SSP1STAT
;
2623 unsigned R_NOT_W
: 1;
2626 unsigned D_NOT_A
: 1;
2631 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
2635 #define _R_NOT_W 0x04
2638 #define _D_NOT_A 0x20
2642 //==============================================================================
2645 //==============================================================================
2648 extern __at(0x0214) __sfr SSPSTAT
;
2654 unsigned R_NOT_W
: 1;
2657 unsigned D_NOT_A
: 1;
2662 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
2664 #define _SSPSTAT_BF 0x01
2665 #define _SSPSTAT_UA 0x02
2666 #define _SSPSTAT_R_NOT_W 0x04
2667 #define _SSPSTAT_S 0x08
2668 #define _SSPSTAT_P 0x10
2669 #define _SSPSTAT_D_NOT_A 0x20
2670 #define _SSPSTAT_CKE 0x40
2671 #define _SSPSTAT_SMP 0x80
2673 //==============================================================================
2676 //==============================================================================
2679 extern __at(0x0215) __sfr SSP1CON
;
2702 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
2713 //==============================================================================
2716 //==============================================================================
2719 extern __at(0x0215) __sfr SSP1CON1
;
2742 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
2744 #define _SSP1CON1_SSPM0 0x01
2745 #define _SSP1CON1_SSPM1 0x02
2746 #define _SSP1CON1_SSPM2 0x04
2747 #define _SSP1CON1_SSPM3 0x08
2748 #define _SSP1CON1_CKP 0x10
2749 #define _SSP1CON1_SSPEN 0x20
2750 #define _SSP1CON1_SSPOV 0x40
2751 #define _SSP1CON1_WCOL 0x80
2753 //==============================================================================
2756 //==============================================================================
2759 extern __at(0x0215) __sfr SSPCON
;
2782 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2784 #define _SSPCON_SSPM0 0x01
2785 #define _SSPCON_SSPM1 0x02
2786 #define _SSPCON_SSPM2 0x04
2787 #define _SSPCON_SSPM3 0x08
2788 #define _SSPCON_CKP 0x10
2789 #define _SSPCON_SSPEN 0x20
2790 #define _SSPCON_SSPOV 0x40
2791 #define _SSPCON_WCOL 0x80
2793 //==============================================================================
2796 //==============================================================================
2799 extern __at(0x0215) __sfr SSPCON1
;
2822 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2824 #define _SSPCON1_SSPM0 0x01
2825 #define _SSPCON1_SSPM1 0x02
2826 #define _SSPCON1_SSPM2 0x04
2827 #define _SSPCON1_SSPM3 0x08
2828 #define _SSPCON1_CKP 0x10
2829 #define _SSPCON1_SSPEN 0x20
2830 #define _SSPCON1_SSPOV 0x40
2831 #define _SSPCON1_WCOL 0x80
2833 //==============================================================================
2836 //==============================================================================
2839 extern __at(0x0216) __sfr SSP1CON2
;
2849 unsigned ACKSTAT
: 1;
2853 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
2861 #define _ACKSTAT 0x40
2864 //==============================================================================
2867 //==============================================================================
2870 extern __at(0x0216) __sfr SSPCON2
;
2880 unsigned ACKSTAT
: 1;
2884 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
2886 #define _SSPCON2_SEN 0x01
2887 #define _SSPCON2_RSEN 0x02
2888 #define _SSPCON2_PEN 0x04
2889 #define _SSPCON2_RCEN 0x08
2890 #define _SSPCON2_ACKEN 0x10
2891 #define _SSPCON2_ACKDT 0x20
2892 #define _SSPCON2_ACKSTAT 0x40
2893 #define _SSPCON2_GCEN 0x80
2895 //==============================================================================
2898 //==============================================================================
2901 extern __at(0x0217) __sfr SSP1CON3
;
2912 unsigned ACKTIM
: 1;
2915 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
2924 #define _ACKTIM 0x80
2926 //==============================================================================
2929 //==============================================================================
2932 extern __at(0x0217) __sfr SSPCON3
;
2943 unsigned ACKTIM
: 1;
2946 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
2948 #define _SSPCON3_DHEN 0x01
2949 #define _SSPCON3_AHEN 0x02
2950 #define _SSPCON3_SBCDE 0x04
2951 #define _SSPCON3_SDAHT 0x08
2952 #define _SSPCON3_BOEN 0x10
2953 #define _SSPCON3_SCIE 0x20
2954 #define _SSPCON3_PCIE 0x40
2955 #define _SSPCON3_ACKTIM 0x80
2957 //==============================================================================
2960 //==============================================================================
2963 extern __at(0x0219) __sfr SSP2BUF
;
2969 unsigned SSP2BUF0
: 1;
2970 unsigned SSP2BUF1
: 1;
2971 unsigned SSP2BUF2
: 1;
2972 unsigned SSP2BUF3
: 1;
2973 unsigned SSP2BUF4
: 1;
2974 unsigned SSP2BUF5
: 1;
2975 unsigned SSP2BUF6
: 1;
2976 unsigned SSP2BUF7
: 1;
2992 extern __at(0x0219) volatile __SSP2BUFbits_t SSP2BUFbits
;
2994 #define _SSP2BUF_SSP2BUF0 0x01
2995 #define _SSP2BUF_BUF0 0x01
2996 #define _SSP2BUF_SSP2BUF1 0x02
2997 #define _SSP2BUF_BUF1 0x02
2998 #define _SSP2BUF_SSP2BUF2 0x04
2999 #define _SSP2BUF_BUF2 0x04
3000 #define _SSP2BUF_SSP2BUF3 0x08
3001 #define _SSP2BUF_BUF3 0x08
3002 #define _SSP2BUF_SSP2BUF4 0x10
3003 #define _SSP2BUF_BUF4 0x10
3004 #define _SSP2BUF_SSP2BUF5 0x20
3005 #define _SSP2BUF_BUF5 0x20
3006 #define _SSP2BUF_SSP2BUF6 0x40
3007 #define _SSP2BUF_BUF6 0x40
3008 #define _SSP2BUF_SSP2BUF7 0x80
3009 #define _SSP2BUF_BUF7 0x80
3011 //==============================================================================
3014 //==============================================================================
3017 extern __at(0x021A) __sfr SSP2ADD
;
3023 unsigned SSP2ADD0
: 1;
3024 unsigned SSP2ADD1
: 1;
3025 unsigned SSP2ADD2
: 1;
3026 unsigned SSP2ADD3
: 1;
3027 unsigned SSP2ADD4
: 1;
3028 unsigned SSP2ADD5
: 1;
3029 unsigned SSP2ADD6
: 1;
3030 unsigned SSP2ADD7
: 1;
3046 extern __at(0x021A) volatile __SSP2ADDbits_t SSP2ADDbits
;
3048 #define _SSP2ADD_SSP2ADD0 0x01
3049 #define _SSP2ADD_ADD0 0x01
3050 #define _SSP2ADD_SSP2ADD1 0x02
3051 #define _SSP2ADD_ADD1 0x02
3052 #define _SSP2ADD_SSP2ADD2 0x04
3053 #define _SSP2ADD_ADD2 0x04
3054 #define _SSP2ADD_SSP2ADD3 0x08
3055 #define _SSP2ADD_ADD3 0x08
3056 #define _SSP2ADD_SSP2ADD4 0x10
3057 #define _SSP2ADD_ADD4 0x10
3058 #define _SSP2ADD_SSP2ADD5 0x20
3059 #define _SSP2ADD_ADD5 0x20
3060 #define _SSP2ADD_SSP2ADD6 0x40
3061 #define _SSP2ADD_ADD6 0x40
3062 #define _SSP2ADD_SSP2ADD7 0x80
3063 #define _SSP2ADD_ADD7 0x80
3065 //==============================================================================
3068 //==============================================================================
3071 extern __at(0x021B) __sfr SSP2MSK
;
3077 unsigned SSP2MSK0
: 1;
3078 unsigned SSP2MSK1
: 1;
3079 unsigned SSP2MSK2
: 1;
3080 unsigned SSP2MSK3
: 1;
3081 unsigned SSP2MSK4
: 1;
3082 unsigned SSP2MSK5
: 1;
3083 unsigned SSP2MSK6
: 1;
3084 unsigned SSP2MSK7
: 1;
3100 extern __at(0x021B) volatile __SSP2MSKbits_t SSP2MSKbits
;
3102 #define _SSP2MSK_SSP2MSK0 0x01
3103 #define _SSP2MSK_MSK0 0x01
3104 #define _SSP2MSK_SSP2MSK1 0x02
3105 #define _SSP2MSK_MSK1 0x02
3106 #define _SSP2MSK_SSP2MSK2 0x04
3107 #define _SSP2MSK_MSK2 0x04
3108 #define _SSP2MSK_SSP2MSK3 0x08
3109 #define _SSP2MSK_MSK3 0x08
3110 #define _SSP2MSK_SSP2MSK4 0x10
3111 #define _SSP2MSK_MSK4 0x10
3112 #define _SSP2MSK_SSP2MSK5 0x20
3113 #define _SSP2MSK_MSK5 0x20
3114 #define _SSP2MSK_SSP2MSK6 0x40
3115 #define _SSP2MSK_MSK6 0x40
3116 #define _SSP2MSK_SSP2MSK7 0x80
3117 #define _SSP2MSK_MSK7 0x80
3119 //==============================================================================
3122 //==============================================================================
3125 extern __at(0x021C) __sfr SSP2STAT
;
3131 unsigned R_NOT_W
: 1;
3134 unsigned D_NOT_A
: 1;
3139 extern __at(0x021C) volatile __SSP2STATbits_t SSP2STATbits
;
3141 #define _SSP2STAT_BF 0x01
3142 #define _SSP2STAT_UA 0x02
3143 #define _SSP2STAT_R_NOT_W 0x04
3144 #define _SSP2STAT_S 0x08
3145 #define _SSP2STAT_P 0x10
3146 #define _SSP2STAT_D_NOT_A 0x20
3147 #define _SSP2STAT_CKE 0x40
3148 #define _SSP2STAT_SMP 0x80
3150 //==============================================================================
3153 //==============================================================================
3156 extern __at(0x021D) __sfr SSP2CON
;
3179 extern __at(0x021D) volatile __SSP2CONbits_t SSP2CONbits
;
3181 #define _SSP2CON_SSPM0 0x01
3182 #define _SSP2CON_SSPM1 0x02
3183 #define _SSP2CON_SSPM2 0x04
3184 #define _SSP2CON_SSPM3 0x08
3185 #define _SSP2CON_CKP 0x10
3186 #define _SSP2CON_SSPEN 0x20
3187 #define _SSP2CON_SSPOV 0x40
3188 #define _SSP2CON_WCOL 0x80
3190 //==============================================================================
3193 //==============================================================================
3196 extern __at(0x021D) __sfr SSP2CON1
;
3219 extern __at(0x021D) volatile __SSP2CON1bits_t SSP2CON1bits
;
3221 #define _SSP2CON1_SSPM0 0x01
3222 #define _SSP2CON1_SSPM1 0x02
3223 #define _SSP2CON1_SSPM2 0x04
3224 #define _SSP2CON1_SSPM3 0x08
3225 #define _SSP2CON1_CKP 0x10
3226 #define _SSP2CON1_SSPEN 0x20
3227 #define _SSP2CON1_SSPOV 0x40
3228 #define _SSP2CON1_WCOL 0x80
3230 //==============================================================================
3233 //==============================================================================
3236 extern __at(0x021E) __sfr SSP2CON2
;
3246 unsigned ACKSTAT
: 1;
3250 extern __at(0x021E) volatile __SSP2CON2bits_t SSP2CON2bits
;
3252 #define _SSP2CON2_SEN 0x01
3253 #define _SSP2CON2_RSEN 0x02
3254 #define _SSP2CON2_PEN 0x04
3255 #define _SSP2CON2_RCEN 0x08
3256 #define _SSP2CON2_ACKEN 0x10
3257 #define _SSP2CON2_ACKDT 0x20
3258 #define _SSP2CON2_ACKSTAT 0x40
3259 #define _SSP2CON2_GCEN 0x80
3261 //==============================================================================
3264 //==============================================================================
3267 extern __at(0x021F) __sfr SSP2CON3
;
3278 unsigned ACKTIM
: 1;
3281 extern __at(0x021F) volatile __SSP2CON3bits_t SSP2CON3bits
;
3283 #define _SSP2CON3_DHEN 0x01
3284 #define _SSP2CON3_AHEN 0x02
3285 #define _SSP2CON3_SBCDE 0x04
3286 #define _SSP2CON3_SDAHT 0x08
3287 #define _SSP2CON3_BOEN 0x10
3288 #define _SSP2CON3_SCIE 0x20
3289 #define _SSP2CON3_PCIE 0x40
3290 #define _SSP2CON3_ACKTIM 0x80
3292 //==============================================================================
3295 //==============================================================================
3298 extern __at(0x028C) __sfr ODCONA
;
3312 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
3320 //==============================================================================
3323 //==============================================================================
3326 extern __at(0x028E) __sfr ODCONC
;
3349 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
3358 //==============================================================================
3360 extern __at(0x0291) __sfr CCPR1
;
3361 extern __at(0x0291) __sfr CCPR1L
;
3362 extern __at(0x0292) __sfr CCPR1H
;
3364 //==============================================================================
3367 extern __at(0x0293) __sfr CCP1CON
;
3373 unsigned CCP1MODE0
: 1;
3374 unsigned CCP1MODE1
: 1;
3375 unsigned CCP1MODE2
: 1;
3376 unsigned CCP1MODE3
: 1;
3377 unsigned CCP1FMT
: 1;
3378 unsigned CCP1OUT
: 1;
3380 unsigned CCP1EN
: 1;
3385 unsigned CCP1MODE
: 4;
3390 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
3392 #define _CCP1MODE0 0x01
3393 #define _CCP1MODE1 0x02
3394 #define _CCP1MODE2 0x04
3395 #define _CCP1MODE3 0x08
3396 #define _CCP1FMT 0x10
3397 #define _CCP1OUT 0x20
3398 #define _CCP1EN 0x80
3400 //==============================================================================
3403 //==============================================================================
3406 extern __at(0x0294) __sfr CCP1CAP
;
3412 unsigned CCP1CTS0
: 1;
3413 unsigned CCP1CTS1
: 1;
3414 unsigned CCP1CTS2
: 1;
3415 unsigned CCP1CTS3
: 1;
3424 unsigned CCP1CTS
: 4;
3429 extern __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits
;
3431 #define _CCP1CTS0 0x01
3432 #define _CCP1CTS1 0x02
3433 #define _CCP1CTS2 0x04
3434 #define _CCP1CTS3 0x08
3436 //==============================================================================
3438 extern __at(0x0295) __sfr CCPR2
;
3439 extern __at(0x0295) __sfr CCPR2L
;
3440 extern __at(0x0296) __sfr CCPR2H
;
3442 //==============================================================================
3445 extern __at(0x0297) __sfr CCP2CON
;
3451 unsigned CCP2MODE0
: 1;
3452 unsigned CCP2MODE1
: 1;
3453 unsigned CCP2MODE2
: 1;
3454 unsigned CCP2MODE3
: 1;
3455 unsigned CCP2FMT
: 1;
3456 unsigned CCP2OUT
: 1;
3458 unsigned CCP2EN
: 1;
3463 unsigned CCP2MODE
: 4;
3468 extern __at(0x0297) volatile __CCP2CONbits_t CCP2CONbits
;
3470 #define _CCP2MODE0 0x01
3471 #define _CCP2MODE1 0x02
3472 #define _CCP2MODE2 0x04
3473 #define _CCP2MODE3 0x08
3474 #define _CCP2FMT 0x10
3475 #define _CCP2OUT 0x20
3476 #define _CCP2EN 0x80
3478 //==============================================================================
3481 //==============================================================================
3484 extern __at(0x0298) __sfr CCP2CAP
;
3490 unsigned CCP2CTS0
: 1;
3491 unsigned CCP2CTS1
: 1;
3492 unsigned CCP2CTS2
: 1;
3493 unsigned CCP2CTS3
: 1;
3502 unsigned CCP2CTS
: 4;
3507 extern __at(0x0298) volatile __CCP2CAPbits_t CCP2CAPbits
;
3509 #define _CCP2CTS0 0x01
3510 #define _CCP2CTS1 0x02
3511 #define _CCP2CTS2 0x04
3512 #define _CCP2CTS3 0x08
3514 //==============================================================================
3517 //==============================================================================
3520 extern __at(0x029F) __sfr CCPTMRS
;
3526 unsigned C1TSEL0
: 1;
3527 unsigned C1TSEL1
: 1;
3528 unsigned C2TSEL0
: 1;
3529 unsigned C2TSEL1
: 1;
3530 unsigned C3TSEL0
: 1;
3531 unsigned C3TSEL1
: 1;
3532 unsigned C4TSEL0
: 1;
3533 unsigned C4TSEL1
: 1;
3538 unsigned C1TSEL
: 2;
3545 unsigned C2TSEL
: 2;
3552 unsigned C3TSEL
: 2;
3559 unsigned C4TSEL
: 2;
3563 extern __at(0x029F) volatile __CCPTMRSbits_t CCPTMRSbits
;
3565 #define _C1TSEL0 0x01
3566 #define _C1TSEL1 0x02
3567 #define _C2TSEL0 0x04
3568 #define _C2TSEL1 0x08
3569 #define _C3TSEL0 0x10
3570 #define _C3TSEL1 0x20
3571 #define _C4TSEL0 0x40
3572 #define _C4TSEL1 0x80
3574 //==============================================================================
3577 //==============================================================================
3580 extern __at(0x030C) __sfr SLRCONA
;
3594 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
3602 //==============================================================================
3605 //==============================================================================
3608 extern __at(0x030E) __sfr SLRCONC
;
3631 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
3640 //==============================================================================
3642 extern __at(0x0311) __sfr CCPR3
;
3643 extern __at(0x0311) __sfr CCPR3L
;
3644 extern __at(0x0312) __sfr CCPR3H
;
3646 //==============================================================================
3649 extern __at(0x0313) __sfr CCP3CON
;
3655 unsigned CCP3MODE0
: 1;
3656 unsigned CCP3MODE1
: 1;
3657 unsigned CCP3MODE2
: 1;
3658 unsigned CCP3MODE3
: 1;
3659 unsigned CCP3FMT
: 1;
3660 unsigned CCP3OUT
: 1;
3662 unsigned CCP3EN
: 1;
3667 unsigned CCP3MODE
: 4;
3672 extern __at(0x0313) volatile __CCP3CONbits_t CCP3CONbits
;
3674 #define _CCP3MODE0 0x01
3675 #define _CCP3MODE1 0x02
3676 #define _CCP3MODE2 0x04
3677 #define _CCP3MODE3 0x08
3678 #define _CCP3FMT 0x10
3679 #define _CCP3OUT 0x20
3680 #define _CCP3EN 0x80
3682 //==============================================================================
3685 //==============================================================================
3688 extern __at(0x0314) __sfr CCP3CAP
;
3694 unsigned CCP3CTS0
: 1;
3695 unsigned CCP3CTS1
: 1;
3696 unsigned CCP3CTS2
: 1;
3697 unsigned CCP3CTS3
: 1;
3706 unsigned CCP3CTS
: 4;
3711 extern __at(0x0314) volatile __CCP3CAPbits_t CCP3CAPbits
;
3713 #define _CCP3CTS0 0x01
3714 #define _CCP3CTS1 0x02
3715 #define _CCP3CTS2 0x04
3716 #define _CCP3CTS3 0x08
3718 //==============================================================================
3720 extern __at(0x0315) __sfr CCPR4
;
3721 extern __at(0x0315) __sfr CCPR4L
;
3722 extern __at(0x0316) __sfr CCPR4H
;
3724 //==============================================================================
3727 extern __at(0x0317) __sfr CCP4CON
;
3733 unsigned CCP4MODE0
: 1;
3734 unsigned CCP4MODE1
: 1;
3735 unsigned CCP4MODE2
: 1;
3736 unsigned CCP4MODE3
: 1;
3737 unsigned CCP4FMT
: 1;
3738 unsigned CCP4OUT
: 1;
3740 unsigned CCP4EN
: 1;
3745 unsigned CCP4MODE
: 4;
3750 extern __at(0x0317) volatile __CCP4CONbits_t CCP4CONbits
;
3752 #define _CCP4MODE0 0x01
3753 #define _CCP4MODE1 0x02
3754 #define _CCP4MODE2 0x04
3755 #define _CCP4MODE3 0x08
3756 #define _CCP4FMT 0x10
3757 #define _CCP4OUT 0x20
3758 #define _CCP4EN 0x80
3760 //==============================================================================
3763 //==============================================================================
3766 extern __at(0x0318) __sfr CCP4CAP
;
3772 unsigned CCP4CTS0
: 1;
3773 unsigned CCP4CTS1
: 1;
3774 unsigned CCP4CTS2
: 1;
3775 unsigned CCP4CTS3
: 1;
3784 unsigned CCP4CTS
: 4;
3789 extern __at(0x0318) volatile __CCP4CAPbits_t CCP4CAPbits
;
3791 #define _CCP4CTS0 0x01
3792 #define _CCP4CTS1 0x02
3793 #define _CCP4CTS2 0x04
3794 #define _CCP4CTS3 0x08
3796 //==============================================================================
3799 //==============================================================================
3802 extern __at(0x038C) __sfr INLVLA
;
3808 unsigned INLVLA0
: 1;
3809 unsigned INLVLA1
: 1;
3810 unsigned INLVLA2
: 1;
3811 unsigned INLVLA3
: 1;
3812 unsigned INLVLA4
: 1;
3813 unsigned INLVLA5
: 1;
3820 unsigned INLVLA
: 6;
3825 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
3827 #define _INLVLA0 0x01
3828 #define _INLVLA1 0x02
3829 #define _INLVLA2 0x04
3830 #define _INLVLA3 0x08
3831 #define _INLVLA4 0x10
3832 #define _INLVLA5 0x20
3834 //==============================================================================
3837 //==============================================================================
3840 extern __at(0x038E) __sfr INLVLC
;
3846 unsigned INLVLC0
: 1;
3847 unsigned INLVLC1
: 1;
3848 unsigned INLVLC2
: 1;
3849 unsigned INLVLC3
: 1;
3850 unsigned INLVLC4
: 1;
3851 unsigned INLVLC5
: 1;
3858 unsigned INLVLC
: 6;
3863 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
3865 #define _INLVLC0 0x01
3866 #define _INLVLC1 0x02
3867 #define _INLVLC2 0x04
3868 #define _INLVLC3 0x08
3869 #define _INLVLC4 0x10
3870 #define _INLVLC5 0x20
3872 //==============================================================================
3875 //==============================================================================
3878 extern __at(0x0391) __sfr IOCAP
;
3884 unsigned IOCAP0
: 1;
3885 unsigned IOCAP1
: 1;
3886 unsigned IOCAP2
: 1;
3887 unsigned IOCAP3
: 1;
3888 unsigned IOCAP4
: 1;
3889 unsigned IOCAP5
: 1;
3901 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
3903 #define _IOCAP0 0x01
3904 #define _IOCAP1 0x02
3905 #define _IOCAP2 0x04
3906 #define _IOCAP3 0x08
3907 #define _IOCAP4 0x10
3908 #define _IOCAP5 0x20
3910 //==============================================================================
3913 //==============================================================================
3916 extern __at(0x0392) __sfr IOCAN
;
3922 unsigned IOCAN0
: 1;
3923 unsigned IOCAN1
: 1;
3924 unsigned IOCAN2
: 1;
3925 unsigned IOCAN3
: 1;
3926 unsigned IOCAN4
: 1;
3927 unsigned IOCAN5
: 1;
3939 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
3941 #define _IOCAN0 0x01
3942 #define _IOCAN1 0x02
3943 #define _IOCAN2 0x04
3944 #define _IOCAN3 0x08
3945 #define _IOCAN4 0x10
3946 #define _IOCAN5 0x20
3948 //==============================================================================
3951 //==============================================================================
3954 extern __at(0x0393) __sfr IOCAF
;
3960 unsigned IOCAF0
: 1;
3961 unsigned IOCAF1
: 1;
3962 unsigned IOCAF2
: 1;
3963 unsigned IOCAF3
: 1;
3964 unsigned IOCAF4
: 1;
3965 unsigned IOCAF5
: 1;
3977 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
3979 #define _IOCAF0 0x01
3980 #define _IOCAF1 0x02
3981 #define _IOCAF2 0x04
3982 #define _IOCAF3 0x08
3983 #define _IOCAF4 0x10
3984 #define _IOCAF5 0x20
3986 //==============================================================================
3989 //==============================================================================
3992 extern __at(0x0397) __sfr IOCCP
;
3998 unsigned IOCCP0
: 1;
3999 unsigned IOCCP1
: 1;
4000 unsigned IOCCP2
: 1;
4001 unsigned IOCCP3
: 1;
4002 unsigned IOCCP4
: 1;
4003 unsigned IOCCP5
: 1;
4015 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
4017 #define _IOCCP0 0x01
4018 #define _IOCCP1 0x02
4019 #define _IOCCP2 0x04
4020 #define _IOCCP3 0x08
4021 #define _IOCCP4 0x10
4022 #define _IOCCP5 0x20
4024 //==============================================================================
4027 //==============================================================================
4030 extern __at(0x0398) __sfr IOCCN
;
4036 unsigned IOCCN0
: 1;
4037 unsigned IOCCN1
: 1;
4038 unsigned IOCCN2
: 1;
4039 unsigned IOCCN3
: 1;
4040 unsigned IOCCN4
: 1;
4041 unsigned IOCCN5
: 1;
4053 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
4055 #define _IOCCN0 0x01
4056 #define _IOCCN1 0x02
4057 #define _IOCCN2 0x04
4058 #define _IOCCN3 0x08
4059 #define _IOCCN4 0x10
4060 #define _IOCCN5 0x20
4062 //==============================================================================
4065 //==============================================================================
4068 extern __at(0x0399) __sfr IOCCF
;
4074 unsigned IOCCF0
: 1;
4075 unsigned IOCCF1
: 1;
4076 unsigned IOCCF2
: 1;
4077 unsigned IOCCF3
: 1;
4078 unsigned IOCCF4
: 1;
4079 unsigned IOCCF5
: 1;
4091 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
4093 #define _IOCCF0 0x01
4094 #define _IOCCF1 0x02
4095 #define _IOCCF2 0x04
4096 #define _IOCCF3 0x08
4097 #define _IOCCF4 0x10
4098 #define _IOCCF5 0x20
4100 //==============================================================================
4103 //==============================================================================
4106 extern __at(0x039A) __sfr CLKRCON
;
4112 unsigned CLKRDIV0
: 1;
4113 unsigned CLKRDIV1
: 1;
4114 unsigned CLKRDIV2
: 1;
4115 unsigned CLKRDC0
: 1;
4116 unsigned CLKRDC1
: 1;
4119 unsigned CLKREN
: 1;
4124 unsigned CLKRDIV
: 3;
4131 unsigned CLKRDC
: 2;
4136 extern __at(0x039A) volatile __CLKRCONbits_t CLKRCONbits
;
4138 #define _CLKRDIV0 0x01
4139 #define _CLKRDIV1 0x02
4140 #define _CLKRDIV2 0x04
4141 #define _CLKRDC0 0x08
4142 #define _CLKRDC1 0x10
4143 #define _CLKREN 0x80
4145 //==============================================================================
4148 //==============================================================================
4151 extern __at(0x039C) __sfr MDCON
;
4159 unsigned MDOPOL
: 1;
4165 extern __at(0x039C) volatile __MDCONbits_t MDCONbits
;
4169 #define _MDOPOL 0x10
4172 //==============================================================================
4175 //==============================================================================
4178 extern __at(0x039D) __sfr MDSRC
;
4201 extern __at(0x039D) volatile __MDSRCbits_t MDSRCbits
;
4208 //==============================================================================
4211 //==============================================================================
4214 extern __at(0x039E) __sfr MDCARH
;
4225 unsigned MDCHSYNC
: 1;
4226 unsigned MDCHPOL
: 1;
4237 extern __at(0x039E) volatile __MDCARHbits_t MDCARHbits
;
4243 #define _MDCHSYNC 0x20
4244 #define _MDCHPOL 0x40
4246 //==============================================================================
4249 //==============================================================================
4252 extern __at(0x039F) __sfr MDCARL
;
4263 unsigned MDCLSYNC
: 1;
4264 unsigned MDCLPOL
: 1;
4275 extern __at(0x039F) volatile __MDCARLbits_t MDCARLbits
;
4281 #define _MDCLSYNC 0x20
4282 #define _MDCLPOL 0x40
4284 //==============================================================================
4287 //==============================================================================
4290 extern __at(0x040C) __sfr CCDNA
;
4294 unsigned CCDNA0
: 1;
4295 unsigned CCDNA1
: 1;
4296 unsigned CCDNA2
: 1;
4298 unsigned CCDNA4
: 1;
4299 unsigned CCDNA5
: 1;
4304 extern __at(0x040C) volatile __CCDNAbits_t CCDNAbits
;
4306 #define _CCDNA0 0x01
4307 #define _CCDNA1 0x02
4308 #define _CCDNA2 0x04
4309 #define _CCDNA4 0x10
4310 #define _CCDNA5 0x20
4312 //==============================================================================
4315 //==============================================================================
4318 extern __at(0x040E) __sfr CCDNC
;
4324 unsigned CCDNC0
: 1;
4325 unsigned CCDNC1
: 1;
4326 unsigned CCDNC2
: 1;
4327 unsigned CCDNC3
: 1;
4328 unsigned CCDNC4
: 1;
4329 unsigned CCDNC5
: 1;
4341 extern __at(0x040E) volatile __CCDNCbits_t CCDNCbits
;
4343 #define _CCDNC0 0x01
4344 #define _CCDNC1 0x02
4345 #define _CCDNC2 0x04
4346 #define _CCDNC3 0x08
4347 #define _CCDNC4 0x10
4348 #define _CCDNC5 0x20
4350 //==============================================================================
4352 extern __at(0x0411) __sfr TMR3
;
4353 extern __at(0x0411) __sfr TMR3L
;
4354 extern __at(0x0412) __sfr TMR3H
;
4356 //==============================================================================
4359 extern __at(0x0413) __sfr T3CON
;
4365 unsigned TMR3ON
: 1;
4367 unsigned T3SYNC
: 1;
4368 unsigned T3SOSC
: 1;
4369 unsigned T3CKPS0
: 1;
4370 unsigned T3CKPS1
: 1;
4371 unsigned TMR3CS0
: 1;
4372 unsigned TMR3CS1
: 1;
4378 unsigned T3CKPS
: 2;
4385 unsigned TMR3CS
: 2;
4389 extern __at(0x0413) volatile __T3CONbits_t T3CONbits
;
4391 #define _TMR3ON 0x01
4392 #define _T3SYNC 0x04
4393 #define _T3SOSC 0x08
4394 #define _T3CKPS0 0x10
4395 #define _T3CKPS1 0x20
4396 #define _TMR3CS0 0x40
4397 #define _TMR3CS1 0x80
4399 //==============================================================================
4402 //==============================================================================
4405 extern __at(0x0414) __sfr T3GCON
;
4411 unsigned T3GSS0
: 1;
4412 unsigned T3GSS1
: 1;
4413 unsigned T3GVAL
: 1;
4414 unsigned T3GGO_NOT_DONE
: 1;
4415 unsigned T3GSPM
: 1;
4417 unsigned T3GPOL
: 1;
4418 unsigned TMR3GE
: 1;
4428 extern __at(0x0414) volatile __T3GCONbits_t T3GCONbits
;
4430 #define _T3GSS0 0x01
4431 #define _T3GSS1 0x02
4432 #define _T3GVAL 0x04
4433 #define _T3GGO_NOT_DONE 0x08
4434 #define _T3GSPM 0x10
4436 #define _T3GPOL 0x40
4437 #define _TMR3GE 0x80
4439 //==============================================================================
4441 extern __at(0x0415) __sfr TMR4
;
4442 extern __at(0x0416) __sfr PR4
;
4444 //==============================================================================
4447 extern __at(0x0417) __sfr T4CON
;
4453 unsigned T4CKPS0
: 1;
4454 unsigned T4CKPS1
: 1;
4455 unsigned TMR4ON
: 1;
4456 unsigned T4OUTPS0
: 1;
4457 unsigned T4OUTPS1
: 1;
4458 unsigned T4OUTPS2
: 1;
4459 unsigned T4OUTPS3
: 1;
4465 unsigned T4CKPS
: 2;
4472 unsigned T4OUTPS
: 4;
4477 extern __at(0x0417) volatile __T4CONbits_t T4CONbits
;
4479 #define _T4CKPS0 0x01
4480 #define _T4CKPS1 0x02
4481 #define _TMR4ON 0x04
4482 #define _T4OUTPS0 0x08
4483 #define _T4OUTPS1 0x10
4484 #define _T4OUTPS2 0x20
4485 #define _T4OUTPS3 0x40
4487 //==============================================================================
4489 extern __at(0x0418) __sfr TMR5
;
4490 extern __at(0x0418) __sfr TMR5L
;
4491 extern __at(0x0419) __sfr TMR5H
;
4493 //==============================================================================
4496 extern __at(0x041A) __sfr T5CON
;
4502 unsigned TMR5ON
: 1;
4504 unsigned T5SYNC
: 1;
4505 unsigned T5SOSC
: 1;
4506 unsigned T5CKPS0
: 1;
4507 unsigned T5CKPS1
: 1;
4508 unsigned TMR5CS0
: 1;
4509 unsigned TMR5CS1
: 1;
4515 unsigned T5CKPS
: 2;
4522 unsigned TMR5CS
: 2;
4526 extern __at(0x041A) volatile __T5CONbits_t T5CONbits
;
4528 #define _TMR5ON 0x01
4529 #define _T5SYNC 0x04
4530 #define _T5SOSC 0x08
4531 #define _T5CKPS0 0x10
4532 #define _T5CKPS1 0x20
4533 #define _TMR5CS0 0x40
4534 #define _TMR5CS1 0x80
4536 //==============================================================================
4539 //==============================================================================
4542 extern __at(0x041B) __sfr T5GCON
;
4548 unsigned T5GSS0
: 1;
4549 unsigned T5GSS1
: 1;
4550 unsigned T5GVAL
: 1;
4551 unsigned T5GGO_NOT_DONE
: 1;
4552 unsigned T5GSPM
: 1;
4554 unsigned T5GPOL
: 1;
4555 unsigned TMR5GE
: 1;
4565 extern __at(0x041B) volatile __T5GCONbits_t T5GCONbits
;
4567 #define _T5GSS0 0x01
4568 #define _T5GSS1 0x02
4569 #define _T5GVAL 0x04
4570 #define _T5GGO_NOT_DONE 0x08
4571 #define _T5GSPM 0x10
4573 #define _T5GPOL 0x40
4574 #define _TMR5GE 0x80
4576 //==============================================================================
4578 extern __at(0x041C) __sfr TMR6
;
4579 extern __at(0x041D) __sfr PR6
;
4581 //==============================================================================
4584 extern __at(0x041E) __sfr T6CON
;
4590 unsigned T6CKPS0
: 1;
4591 unsigned T6CKPS1
: 1;
4592 unsigned TMR6ON
: 1;
4593 unsigned T6OUTPS0
: 1;
4594 unsigned T6OUTPS1
: 1;
4595 unsigned T6OUTPS2
: 1;
4596 unsigned T6OUTPS3
: 1;
4602 unsigned T6CKPS
: 2;
4609 unsigned T6OUTPS
: 4;
4614 extern __at(0x041E) volatile __T6CONbits_t T6CONbits
;
4616 #define _T6CKPS0 0x01
4617 #define _T6CKPS1 0x02
4618 #define _TMR6ON 0x04
4619 #define _T6OUTPS0 0x08
4620 #define _T6OUTPS1 0x10
4621 #define _T6OUTPS2 0x20
4622 #define _T6OUTPS3 0x40
4624 //==============================================================================
4627 //==============================================================================
4630 extern __at(0x041F) __sfr CCDCON
;
4653 extern __at(0x041F) volatile __CCDCONbits_t CCDCONbits
;
4659 //==============================================================================
4662 //==============================================================================
4665 extern __at(0x048C) __sfr CCDPA
;
4669 unsigned CCDPA0
: 1;
4670 unsigned CCDPA1
: 1;
4671 unsigned CCDPA2
: 1;
4673 unsigned CCDPA4
: 1;
4674 unsigned CCDPA5
: 1;
4679 extern __at(0x048C) volatile __CCDPAbits_t CCDPAbits
;
4681 #define _CCDPA0 0x01
4682 #define _CCDPA1 0x02
4683 #define _CCDPA2 0x04
4684 #define _CCDPA4 0x10
4685 #define _CCDPA5 0x20
4687 //==============================================================================
4690 //==============================================================================
4693 extern __at(0x048E) __sfr CCDPC
;
4699 unsigned CCDPC0
: 1;
4700 unsigned CCDPC1
: 1;
4701 unsigned CCDPC2
: 1;
4702 unsigned CCDPC3
: 1;
4703 unsigned CCDPC4
: 1;
4704 unsigned CCDPC5
: 1;
4716 extern __at(0x048E) volatile __CCDPCbits_t CCDPCbits
;
4718 #define _CCDPC0 0x01
4719 #define _CCDPC1 0x02
4720 #define _CCDPC2 0x04
4721 #define _CCDPC3 0x08
4722 #define _CCDPC4 0x10
4723 #define _CCDPC5 0x20
4725 //==============================================================================
4727 extern __at(0x0498) __sfr NCO1ACC
;
4728 extern __at(0x0498) __sfr NCO1ACCL
;
4729 extern __at(0x0499) __sfr NCO1ACCH
;
4730 extern __at(0x049A) __sfr NCO1ACCU
;
4731 extern __at(0x049B) __sfr NCO1INC
;
4732 extern __at(0x049B) __sfr NCO1INCL
;
4733 extern __at(0x049C) __sfr NCO1INCH
;
4734 extern __at(0x049D) __sfr NCO1INCU
;
4736 //==============================================================================
4739 extern __at(0x049E) __sfr NCO1CON
;
4753 extern __at(0x049E) volatile __NCO1CONbits_t NCO1CONbits
;
4760 //==============================================================================
4762 extern __at(0x049F) __sfr NCO1CLK
;
4764 //==============================================================================
4767 extern __at(0x0617) __sfr PWM5DCL
;
4779 unsigned PWM5DCL0
: 1;
4780 unsigned PWM5DCL1
: 1;
4786 unsigned PWM5DCL
: 2;
4790 extern __at(0x0617) volatile __PWM5DCLbits_t PWM5DCLbits
;
4792 #define _PWM5DCL0 0x40
4793 #define _PWM5DCL1 0x80
4795 //==============================================================================
4798 //==============================================================================
4801 extern __at(0x0618) __sfr PWM5DCH
;
4805 unsigned PWM5DCH0
: 1;
4806 unsigned PWM5DCH1
: 1;
4807 unsigned PWM5DCH2
: 1;
4808 unsigned PWM5DCH3
: 1;
4809 unsigned PWM5DCH4
: 1;
4810 unsigned PWM5DCH5
: 1;
4811 unsigned PWM5DCH6
: 1;
4812 unsigned PWM5DCH7
: 1;
4815 extern __at(0x0618) volatile __PWM5DCHbits_t PWM5DCHbits
;
4817 #define _PWM5DCH0 0x01
4818 #define _PWM5DCH1 0x02
4819 #define _PWM5DCH2 0x04
4820 #define _PWM5DCH3 0x08
4821 #define _PWM5DCH4 0x10
4822 #define _PWM5DCH5 0x20
4823 #define _PWM5DCH6 0x40
4824 #define _PWM5DCH7 0x80
4826 //==============================================================================
4829 //==============================================================================
4832 extern __at(0x0619) __sfr PWM5CON
;
4840 unsigned PWM5POL
: 1;
4841 unsigned PWM5OUT
: 1;
4843 unsigned PWM5EN
: 1;
4846 extern __at(0x0619) volatile __PWM5CONbits_t PWM5CONbits
;
4848 #define _PWM5POL 0x10
4849 #define _PWM5OUT 0x20
4850 #define _PWM5EN 0x80
4852 //==============================================================================
4855 //==============================================================================
4858 extern __at(0x0619) __sfr PWM5CON0
;
4866 unsigned PWM5POL
: 1;
4867 unsigned PWM5OUT
: 1;
4869 unsigned PWM5EN
: 1;
4872 extern __at(0x0619) volatile __PWM5CON0bits_t PWM5CON0bits
;
4874 #define _PWM5CON0_PWM5POL 0x10
4875 #define _PWM5CON0_PWM5OUT 0x20
4876 #define _PWM5CON0_PWM5EN 0x80
4878 //==============================================================================
4881 //==============================================================================
4884 extern __at(0x061A) __sfr PWM6DCL
;
4896 unsigned PWM6DCL0
: 1;
4897 unsigned PWM6DCL1
: 1;
4903 unsigned PWM6DCL
: 2;
4907 extern __at(0x061A) volatile __PWM6DCLbits_t PWM6DCLbits
;
4909 #define _PWM6DCL0 0x40
4910 #define _PWM6DCL1 0x80
4912 //==============================================================================
4915 //==============================================================================
4918 extern __at(0x061B) __sfr PWM6DCH
;
4922 unsigned PWM6DCH0
: 1;
4923 unsigned PWM6DCH1
: 1;
4924 unsigned PWM6DCH2
: 1;
4925 unsigned PWM6DCH3
: 1;
4926 unsigned PWM6DCH4
: 1;
4927 unsigned PWM6DCH5
: 1;
4928 unsigned PWM6DCH6
: 1;
4929 unsigned PWM6DCH7
: 1;
4932 extern __at(0x061B) volatile __PWM6DCHbits_t PWM6DCHbits
;
4934 #define _PWM6DCH0 0x01
4935 #define _PWM6DCH1 0x02
4936 #define _PWM6DCH2 0x04
4937 #define _PWM6DCH3 0x08
4938 #define _PWM6DCH4 0x10
4939 #define _PWM6DCH5 0x20
4940 #define _PWM6DCH6 0x40
4941 #define _PWM6DCH7 0x80
4943 //==============================================================================
4946 //==============================================================================
4949 extern __at(0x061C) __sfr PWM6CON
;
4957 unsigned PWM6POL
: 1;
4958 unsigned PWM6OUT
: 1;
4960 unsigned PWM6EN
: 1;
4963 extern __at(0x061C) volatile __PWM6CONbits_t PWM6CONbits
;
4965 #define _PWM6POL 0x10
4966 #define _PWM6OUT 0x20
4967 #define _PWM6EN 0x80
4969 //==============================================================================
4972 //==============================================================================
4975 extern __at(0x061C) __sfr PWM6CON0
;
4983 unsigned PWM6POL
: 1;
4984 unsigned PWM6OUT
: 1;
4986 unsigned PWM6EN
: 1;
4989 extern __at(0x061C) volatile __PWM6CON0bits_t PWM6CON0bits
;
4991 #define _PWM6CON0_PWM6POL 0x10
4992 #define _PWM6CON0_PWM6OUT 0x20
4993 #define _PWM6CON0_PWM6EN 0x80
4995 //==============================================================================
4998 //==============================================================================
5001 extern __at(0x061F) __sfr PWMTMRS
;
5007 unsigned P5TSEL0
: 1;
5008 unsigned P5TSEL1
: 1;
5009 unsigned P6TSEL0
: 1;
5010 unsigned P6TSEL1
: 1;
5019 unsigned P5TSEL
: 2;
5026 unsigned P6TSEL
: 2;
5031 extern __at(0x061F) volatile __PWMTMRSbits_t PWMTMRSbits
;
5033 #define _P5TSEL0 0x01
5034 #define _P5TSEL1 0x02
5035 #define _P6TSEL0 0x04
5036 #define _P6TSEL1 0x08
5038 //==============================================================================
5041 //==============================================================================
5044 extern __at(0x0691) __sfr CWG1CLKCON
;
5062 unsigned CWG1CS
: 1;
5071 } __CWG1CLKCONbits_t
;
5073 extern __at(0x0691) volatile __CWG1CLKCONbits_t CWG1CLKCONbits
;
5076 #define _CWG1CS 0x01
5078 //==============================================================================
5081 //==============================================================================
5084 extern __at(0x0692) __sfr CWG1DAT
;
5090 unsigned CWG1DAT0
: 1;
5091 unsigned CWG1DAT1
: 1;
5092 unsigned CWG1DAT2
: 1;
5093 unsigned CWG1DAT3
: 1;
5102 unsigned CWG1DAT
: 4;
5107 extern __at(0x0692) volatile __CWG1DATbits_t CWG1DATbits
;
5109 #define _CWG1DAT0 0x01
5110 #define _CWG1DAT1 0x02
5111 #define _CWG1DAT2 0x04
5112 #define _CWG1DAT3 0x08
5114 //==============================================================================
5117 //==============================================================================
5120 extern __at(0x0693) __sfr CWG1DBR
;
5138 unsigned CWG1DBR0
: 1;
5139 unsigned CWG1DBR1
: 1;
5140 unsigned CWG1DBR2
: 1;
5141 unsigned CWG1DBR3
: 1;
5142 unsigned CWG1DBR4
: 1;
5143 unsigned CWG1DBR5
: 1;
5156 unsigned CWG1DBR
: 6;
5161 extern __at(0x0693) volatile __CWG1DBRbits_t CWG1DBRbits
;
5164 #define _CWG1DBR0 0x01
5166 #define _CWG1DBR1 0x02
5168 #define _CWG1DBR2 0x04
5170 #define _CWG1DBR3 0x08
5172 #define _CWG1DBR4 0x10
5174 #define _CWG1DBR5 0x20
5176 //==============================================================================
5179 //==============================================================================
5182 extern __at(0x0694) __sfr CWG1DBF
;
5200 unsigned CWG1DBF0
: 1;
5201 unsigned CWG1DBF1
: 1;
5202 unsigned CWG1DBF2
: 1;
5203 unsigned CWG1DBF3
: 1;
5204 unsigned CWG1DBF4
: 1;
5205 unsigned CWG1DBF5
: 1;
5218 unsigned CWG1DBF
: 6;
5223 extern __at(0x0694) volatile __CWG1DBFbits_t CWG1DBFbits
;
5226 #define _CWG1DBF0 0x01
5228 #define _CWG1DBF1 0x02
5230 #define _CWG1DBF2 0x04
5232 #define _CWG1DBF3 0x08
5234 #define _CWG1DBF4 0x10
5236 #define _CWG1DBF5 0x20
5238 //==============================================================================
5241 //==============================================================================
5244 extern __at(0x0695) __sfr CWG1CON0
;
5262 unsigned CWG1MODE0
: 1;
5263 unsigned CWG1MODE1
: 1;
5264 unsigned CWG1MODE2
: 1;
5268 unsigned CWG1LD
: 1;
5281 unsigned CWG1EN
: 1;
5286 unsigned CWG1MODE
: 3;
5297 extern __at(0x0695) volatile __CWG1CON0bits_t CWG1CON0bits
;
5299 #define _CWG1CON0_MODE0 0x01
5300 #define _CWG1CON0_CWG1MODE0 0x01
5301 #define _CWG1CON0_MODE1 0x02
5302 #define _CWG1CON0_CWG1MODE1 0x02
5303 #define _CWG1CON0_MODE2 0x04
5304 #define _CWG1CON0_CWG1MODE2 0x04
5305 #define _CWG1CON0_LD 0x40
5306 #define _CWG1CON0_CWG1LD 0x40
5307 #define _CWG1CON0_EN 0x80
5308 #define _CWG1CON0_G1EN 0x80
5309 #define _CWG1CON0_CWG1EN 0x80
5311 //==============================================================================
5314 //==============================================================================
5317 extern __at(0x0696) __sfr CWG1CON1
;
5335 unsigned CWG1POLA
: 1;
5336 unsigned CWG1POLB
: 1;
5337 unsigned CWG1POLC
: 1;
5338 unsigned CWG1POLD
: 1;
5340 unsigned CWG1IN
: 1;
5346 extern __at(0x0696) volatile __CWG1CON1bits_t CWG1CON1bits
;
5349 #define _CWG1POLA 0x01
5351 #define _CWG1POLB 0x02
5353 #define _CWG1POLC 0x04
5355 #define _CWG1POLD 0x08
5357 #define _CWG1IN 0x20
5359 //==============================================================================
5362 //==============================================================================
5365 extern __at(0x0697) __sfr CWG1AS0
;
5378 unsigned SHUTDOWN
: 1;
5385 unsigned CWG1LSAC0
: 1;
5386 unsigned CWG1LSAC1
: 1;
5387 unsigned CWG1LSBD0
: 1;
5388 unsigned CWG1LSBD1
: 1;
5389 unsigned CWG1REN
: 1;
5390 unsigned CWG1SHUTDOWN
: 1;
5403 unsigned CWG1LSAC
: 2;
5410 unsigned CWG1LSBD
: 2;
5422 extern __at(0x0697) volatile __CWG1AS0bits_t CWG1AS0bits
;
5425 #define _CWG1LSAC0 0x04
5427 #define _CWG1LSAC1 0x08
5429 #define _CWG1LSBD0 0x10
5431 #define _CWG1LSBD1 0x20
5433 #define _CWG1REN 0x40
5434 #define _SHUTDOWN 0x80
5435 #define _CWG1SHUTDOWN 0x80
5437 //==============================================================================
5440 //==============================================================================
5443 extern __at(0x0698) __sfr CWG1AS1
;
5457 extern __at(0x0698) volatile __CWG1AS1bits_t CWG1AS1bits
;
5465 //==============================================================================
5468 //==============================================================================
5471 extern __at(0x0699) __sfr CWG1STR
;
5489 unsigned CWG1STRA
: 1;
5490 unsigned CWG1STRB
: 1;
5491 unsigned CWG1STRC
: 1;
5492 unsigned CWG1STRD
: 1;
5493 unsigned CWG1OVRA
: 1;
5494 unsigned CWG1OVRB
: 1;
5495 unsigned CWG1OVRC
: 1;
5496 unsigned CWG1OVRD
: 1;
5500 extern __at(0x0699) volatile __CWG1STRbits_t CWG1STRbits
;
5503 #define _CWG1STRA 0x01
5505 #define _CWG1STRB 0x02
5507 #define _CWG1STRC 0x04
5509 #define _CWG1STRD 0x08
5511 #define _CWG1OVRA 0x10
5513 #define _CWG1OVRB 0x20
5515 #define _CWG1OVRC 0x40
5517 #define _CWG1OVRD 0x80
5519 //==============================================================================
5522 //==============================================================================
5525 extern __at(0x0711) __sfr CWG2CLKCON
;
5543 unsigned CWG2CS
: 1;
5552 } __CWG2CLKCONbits_t
;
5554 extern __at(0x0711) volatile __CWG2CLKCONbits_t CWG2CLKCONbits
;
5556 #define _CWG2CLKCON_CS 0x01
5557 #define _CWG2CLKCON_CWG2CS 0x01
5559 //==============================================================================
5562 //==============================================================================
5565 extern __at(0x0712) __sfr CWG2DAT
;
5571 unsigned CWG2DAT0
: 1;
5572 unsigned CWG2DAT1
: 1;
5573 unsigned CWG2DAT2
: 1;
5574 unsigned CWG2DAT3
: 1;
5583 unsigned CWG2DAT
: 4;
5588 extern __at(0x0712) volatile __CWG2DATbits_t CWG2DATbits
;
5590 #define _CWG2DAT0 0x01
5591 #define _CWG2DAT1 0x02
5592 #define _CWG2DAT2 0x04
5593 #define _CWG2DAT3 0x08
5595 //==============================================================================
5598 //==============================================================================
5601 extern __at(0x0713) __sfr CWG2DBR
;
5619 unsigned CWG2DBR0
: 1;
5620 unsigned CWG2DBR1
: 1;
5621 unsigned CWG2DBR2
: 1;
5622 unsigned CWG2DBR3
: 1;
5623 unsigned CWG2DBR4
: 1;
5624 unsigned CWG2DBR5
: 1;
5637 unsigned CWG2DBR
: 6;
5642 extern __at(0x0713) volatile __CWG2DBRbits_t CWG2DBRbits
;
5644 #define _CWG2DBR_DBR0 0x01
5645 #define _CWG2DBR_CWG2DBR0 0x01
5646 #define _CWG2DBR_DBR1 0x02
5647 #define _CWG2DBR_CWG2DBR1 0x02
5648 #define _CWG2DBR_DBR2 0x04
5649 #define _CWG2DBR_CWG2DBR2 0x04
5650 #define _CWG2DBR_DBR3 0x08
5651 #define _CWG2DBR_CWG2DBR3 0x08
5652 #define _CWG2DBR_DBR4 0x10
5653 #define _CWG2DBR_CWG2DBR4 0x10
5654 #define _CWG2DBR_DBR5 0x20
5655 #define _CWG2DBR_CWG2DBR5 0x20
5657 //==============================================================================
5660 //==============================================================================
5663 extern __at(0x0714) __sfr CWG2DBF
;
5681 unsigned CWG2DBF0
: 1;
5682 unsigned CWG2DBF1
: 1;
5683 unsigned CWG2DBF2
: 1;
5684 unsigned CWG2DBF3
: 1;
5685 unsigned CWG2DBF4
: 1;
5686 unsigned CWG2DBF5
: 1;
5693 unsigned CWG2DBF
: 6;
5704 extern __at(0x0714) volatile __CWG2DBFbits_t CWG2DBFbits
;
5706 #define _CWG2DBF_DBF0 0x01
5707 #define _CWG2DBF_CWG2DBF0 0x01
5708 #define _CWG2DBF_DBF1 0x02
5709 #define _CWG2DBF_CWG2DBF1 0x02
5710 #define _CWG2DBF_DBF2 0x04
5711 #define _CWG2DBF_CWG2DBF2 0x04
5712 #define _CWG2DBF_DBF3 0x08
5713 #define _CWG2DBF_CWG2DBF3 0x08
5714 #define _CWG2DBF_DBF4 0x10
5715 #define _CWG2DBF_CWG2DBF4 0x10
5716 #define _CWG2DBF_DBF5 0x20
5717 #define _CWG2DBF_CWG2DBF5 0x20
5719 //==============================================================================
5722 //==============================================================================
5725 extern __at(0x0715) __sfr CWG2CON0
;
5743 unsigned CWG2MODE0
: 1;
5744 unsigned CWG2MODE1
: 1;
5745 unsigned CWG2MODE2
: 1;
5749 unsigned CWG2LD
: 1;
5762 unsigned CWG2EN
: 1;
5767 unsigned CWG2MODE
: 3;
5778 extern __at(0x0715) volatile __CWG2CON0bits_t CWG2CON0bits
;
5780 #define _CWG2CON0_MODE0 0x01
5781 #define _CWG2CON0_CWG2MODE0 0x01
5782 #define _CWG2CON0_MODE1 0x02
5783 #define _CWG2CON0_CWG2MODE1 0x02
5784 #define _CWG2CON0_MODE2 0x04
5785 #define _CWG2CON0_CWG2MODE2 0x04
5786 #define _CWG2CON0_LD 0x40
5787 #define _CWG2CON0_CWG2LD 0x40
5788 #define _CWG2CON0_EN 0x80
5789 #define _CWG2CON0_G2EN 0x80
5790 #define _CWG2CON0_CWG2EN 0x80
5792 //==============================================================================
5795 //==============================================================================
5798 extern __at(0x0716) __sfr CWG2CON1
;
5816 unsigned CWG2POLA
: 1;
5817 unsigned CWG2POLB
: 1;
5818 unsigned CWG2POLC
: 1;
5819 unsigned CWG2POLD
: 1;
5821 unsigned CWG2IN
: 1;
5827 extern __at(0x0716) volatile __CWG2CON1bits_t CWG2CON1bits
;
5829 #define _CWG2CON1_POLA 0x01
5830 #define _CWG2CON1_CWG2POLA 0x01
5831 #define _CWG2CON1_POLB 0x02
5832 #define _CWG2CON1_CWG2POLB 0x02
5833 #define _CWG2CON1_POLC 0x04
5834 #define _CWG2CON1_CWG2POLC 0x04
5835 #define _CWG2CON1_POLD 0x08
5836 #define _CWG2CON1_CWG2POLD 0x08
5837 #define _CWG2CON1_IN 0x20
5838 #define _CWG2CON1_CWG2IN 0x20
5840 //==============================================================================
5843 //==============================================================================
5846 extern __at(0x0717) __sfr CWG2AS0
;
5859 unsigned SHUTDOWN
: 1;
5866 unsigned CWG2LSAC0
: 1;
5867 unsigned CWG2LSAC1
: 1;
5868 unsigned CWG2LSBD0
: 1;
5869 unsigned CWG2LSBD1
: 1;
5870 unsigned CWG2REN
: 1;
5871 unsigned CWG2SHUTDOWN
: 1;
5884 unsigned CWG2LSAC
: 2;
5891 unsigned CWG2LSBD
: 2;
5903 extern __at(0x0717) volatile __CWG2AS0bits_t CWG2AS0bits
;
5905 #define _CWG2AS0_LSAC0 0x04
5906 #define _CWG2AS0_CWG2LSAC0 0x04
5907 #define _CWG2AS0_LSAC1 0x08
5908 #define _CWG2AS0_CWG2LSAC1 0x08
5909 #define _CWG2AS0_LSBD0 0x10
5910 #define _CWG2AS0_CWG2LSBD0 0x10
5911 #define _CWG2AS0_LSBD1 0x20
5912 #define _CWG2AS0_CWG2LSBD1 0x20
5913 #define _CWG2AS0_REN 0x40
5914 #define _CWG2AS0_CWG2REN 0x40
5915 #define _CWG2AS0_SHUTDOWN 0x80
5916 #define _CWG2AS0_CWG2SHUTDOWN 0x80
5918 //==============================================================================
5921 //==============================================================================
5924 extern __at(0x0718) __sfr CWG2AS1
;
5938 extern __at(0x0718) volatile __CWG2AS1bits_t CWG2AS1bits
;
5940 #define _CWG2AS1_AS0E 0x01
5941 #define _CWG2AS1_AS1E 0x02
5942 #define _CWG2AS1_AS2E 0x04
5943 #define _CWG2AS1_AS3E 0x08
5944 #define _CWG2AS1_AS4E 0x10
5946 //==============================================================================
5949 //==============================================================================
5952 extern __at(0x0719) __sfr CWG2STR
;
5970 unsigned CWG2STRA
: 1;
5971 unsigned CWG2STRB
: 1;
5972 unsigned CWG2STRC
: 1;
5973 unsigned CWG2STRD
: 1;
5974 unsigned CWG2OVRA
: 1;
5975 unsigned CWG2OVRB
: 1;
5976 unsigned CWG2OVRC
: 1;
5977 unsigned CWG2OVRD
: 1;
5981 extern __at(0x0719) volatile __CWG2STRbits_t CWG2STRbits
;
5983 #define _CWG2STR_STRA 0x01
5984 #define _CWG2STR_CWG2STRA 0x01
5985 #define _CWG2STR_STRB 0x02
5986 #define _CWG2STR_CWG2STRB 0x02
5987 #define _CWG2STR_STRC 0x04
5988 #define _CWG2STR_CWG2STRC 0x04
5989 #define _CWG2STR_STRD 0x08
5990 #define _CWG2STR_CWG2STRD 0x08
5991 #define _CWG2STR_OVRA 0x10
5992 #define _CWG2STR_CWG2OVRA 0x10
5993 #define _CWG2STR_OVRB 0x20
5994 #define _CWG2STR_CWG2OVRB 0x20
5995 #define _CWG2STR_OVRC 0x40
5996 #define _CWG2STR_CWG2OVRC 0x40
5997 #define _CWG2STR_OVRD 0x80
5998 #define _CWG2STR_CWG2OVRD 0x80
6000 //==============================================================================
6002 extern __at(0x0891) __sfr NVMADR
;
6004 //==============================================================================
6007 extern __at(0x0891) __sfr NVMADRL
;
6011 unsigned NVMADR0
: 1;
6012 unsigned NVMADR1
: 1;
6013 unsigned NVMADR2
: 1;
6014 unsigned NVMADR3
: 1;
6015 unsigned NVMADR4
: 1;
6016 unsigned NVMADR5
: 1;
6017 unsigned NVMADR6
: 1;
6018 unsigned NVMADR7
: 1;
6021 extern __at(0x0891) volatile __NVMADRLbits_t NVMADRLbits
;
6023 #define _NVMADR0 0x01
6024 #define _NVMADR1 0x02
6025 #define _NVMADR2 0x04
6026 #define _NVMADR3 0x08
6027 #define _NVMADR4 0x10
6028 #define _NVMADR5 0x20
6029 #define _NVMADR6 0x40
6030 #define _NVMADR7 0x80
6032 //==============================================================================
6035 //==============================================================================
6038 extern __at(0x0892) __sfr NVMADRH
;
6042 unsigned NVMADR8
: 1;
6043 unsigned NVMADR9
: 1;
6044 unsigned NVMADR10
: 1;
6045 unsigned NVMADR11
: 1;
6046 unsigned NVMADR12
: 1;
6047 unsigned NVMADR13
: 1;
6048 unsigned NVMADR14
: 1;
6052 extern __at(0x0892) volatile __NVMADRHbits_t NVMADRHbits
;
6054 #define _NVMADR8 0x01
6055 #define _NVMADR9 0x02
6056 #define _NVMADR10 0x04
6057 #define _NVMADR11 0x08
6058 #define _NVMADR12 0x10
6059 #define _NVMADR13 0x20
6060 #define _NVMADR14 0x40
6062 //==============================================================================
6064 extern __at(0x0893) __sfr NVMDAT
;
6066 //==============================================================================
6069 extern __at(0x0893) __sfr NVMDATL
;
6073 unsigned NVMDAT0
: 1;
6074 unsigned NVMDAT1
: 1;
6075 unsigned NVMDAT2
: 1;
6076 unsigned NVMDAT3
: 1;
6077 unsigned NVMDAT4
: 1;
6078 unsigned NVMDAT5
: 1;
6079 unsigned NVMDAT6
: 1;
6080 unsigned NVMDAT7
: 1;
6083 extern __at(0x0893) volatile __NVMDATLbits_t NVMDATLbits
;
6085 #define _NVMDAT0 0x01
6086 #define _NVMDAT1 0x02
6087 #define _NVMDAT2 0x04
6088 #define _NVMDAT3 0x08
6089 #define _NVMDAT4 0x10
6090 #define _NVMDAT5 0x20
6091 #define _NVMDAT6 0x40
6092 #define _NVMDAT7 0x80
6094 //==============================================================================
6097 //==============================================================================
6100 extern __at(0x0894) __sfr NVMDATH
;
6104 unsigned NVMDAT8
: 1;
6105 unsigned NVMDAT9
: 1;
6106 unsigned NVMDAT10
: 1;
6107 unsigned NVMDAT11
: 1;
6108 unsigned NVMDAT12
: 1;
6109 unsigned NVMDAT13
: 1;
6114 extern __at(0x0894) volatile __NVMDATHbits_t NVMDATHbits
;
6116 #define _NVMDAT8 0x01
6117 #define _NVMDAT9 0x02
6118 #define _NVMDAT10 0x04
6119 #define _NVMDAT11 0x08
6120 #define _NVMDAT12 0x10
6121 #define _NVMDAT13 0x20
6123 //==============================================================================
6126 //==============================================================================
6129 extern __at(0x0895) __sfr NVMCON1
;
6139 unsigned NVMREGS
: 1;
6143 extern __at(0x0895) volatile __NVMCON1bits_t NVMCON1bits
;
6151 #define _NVMREGS 0x40
6153 //==============================================================================
6155 extern __at(0x0896) __sfr NVMCON2
;
6157 //==============================================================================
6160 extern __at(0x089B) __sfr PCON0
;
6164 unsigned NOT_BOR
: 1;
6165 unsigned NOT_POR
: 1;
6166 unsigned NOT_RI
: 1;
6167 unsigned NOT_RMCLR
: 1;
6168 unsigned NOT_RWDT
: 1;
6170 unsigned STKUNF
: 1;
6171 unsigned STKOVF
: 1;
6174 extern __at(0x089B) volatile __PCON0bits_t PCON0bits
;
6176 #define _NOT_BOR 0x01
6177 #define _NOT_POR 0x02
6178 #define _NOT_RI 0x04
6179 #define _NOT_RMCLR 0x08
6180 #define _NOT_RWDT 0x10
6181 #define _STKUNF 0x40
6182 #define _STKOVF 0x80
6184 //==============================================================================
6187 //==============================================================================
6190 extern __at(0x0911) __sfr PMD0
;
6195 unsigned CLKRMD
: 1;
6201 unsigned SYSCMD
: 1;
6204 extern __at(0x0911) volatile __PMD0bits_t PMD0bits
;
6207 #define _CLKRMD 0x02
6210 #define _SYSCMD 0x80
6212 //==============================================================================
6215 //==============================================================================
6218 extern __at(0x0912) __sfr PMD1
;
6222 unsigned TMR0MD
: 1;
6223 unsigned TMR1MD
: 1;
6224 unsigned TMR2MD
: 1;
6225 unsigned TMR3MD
: 1;
6226 unsigned TMR4MD
: 1;
6227 unsigned TMR5MD
: 1;
6228 unsigned TMR6MD
: 1;
6232 extern __at(0x0912) volatile __PMD1bits_t PMD1bits
;
6234 #define _TMR0MD 0x01
6235 #define _TMR1MD 0x02
6236 #define _TMR2MD 0x04
6237 #define _TMR3MD 0x08
6238 #define _TMR4MD 0x10
6239 #define _TMR5MD 0x20
6240 #define _TMR6MD 0x40
6243 //==============================================================================
6246 //==============================================================================
6249 extern __at(0x0913) __sfr PMD2
;
6254 unsigned CMP1MD
: 1;
6255 unsigned CMP2MD
: 1;
6263 extern __at(0x0913) volatile __PMD2bits_t PMD2bits
;
6265 #define _CMP1MD 0x02
6266 #define _CMP2MD 0x04
6270 //==============================================================================
6273 //==============================================================================
6276 extern __at(0x0914) __sfr PMD3
;
6280 unsigned CCP1MD
: 1;
6281 unsigned CCP2MD
: 1;
6282 unsigned CCP3MD
: 1;
6283 unsigned CCP4MD
: 1;
6284 unsigned PWM5MD
: 1;
6285 unsigned PWM6MD
: 1;
6286 unsigned CWG1MD
: 1;
6287 unsigned CWG2MD
: 1;
6290 extern __at(0x0914) volatile __PMD3bits_t PMD3bits
;
6292 #define _CCP1MD 0x01
6293 #define _CCP2MD 0x02
6294 #define _CCP3MD 0x04
6295 #define _CCP4MD 0x08
6296 #define _PWM5MD 0x10
6297 #define _PWM6MD 0x20
6298 #define _CWG1MD 0x40
6299 #define _CWG2MD 0x80
6301 //==============================================================================
6304 //==============================================================================
6307 extern __at(0x0915) __sfr PMD4
;
6312 unsigned MSSP1MD
: 1;
6313 unsigned MSSP2MD
: 1;
6316 unsigned UART1MD
: 1;
6321 extern __at(0x0915) volatile __PMD4bits_t PMD4bits
;
6323 #define _MSSP1MD 0x02
6324 #define _MSSP2MD 0x04
6325 #define _UART1MD 0x20
6327 //==============================================================================
6330 //==============================================================================
6333 extern __at(0x0916) __sfr PMD5
;
6338 unsigned CLC1MD
: 1;
6339 unsigned CLC2MD
: 1;
6340 unsigned CLC3MD
: 1;
6341 unsigned CLC4MD
: 1;
6347 extern __at(0x0916) volatile __PMD5bits_t PMD5bits
;
6350 #define _CLC1MD 0x02
6351 #define _CLC2MD 0x04
6352 #define _CLC3MD 0x08
6353 #define _CLC4MD 0x10
6355 //==============================================================================
6358 //==============================================================================
6361 extern __at(0x0918) __sfr CPUDOZE
;
6384 extern __at(0x0918) volatile __CPUDOZEbits_t CPUDOZEbits
;
6394 //==============================================================================
6397 //==============================================================================
6400 extern __at(0x0919) __sfr OSCCON1
;
6430 extern __at(0x0919) volatile __OSCCON1bits_t OSCCON1bits
;
6440 //==============================================================================
6443 //==============================================================================
6446 extern __at(0x091A) __sfr OSCCON2
;
6476 extern __at(0x091A) volatile __OSCCON2bits_t OSCCON2bits
;
6486 //==============================================================================
6489 //==============================================================================
6492 extern __at(0x091B) __sfr OSCCON3
;
6501 unsigned SOSCBE
: 1;
6502 unsigned SOSCPWR
: 1;
6503 unsigned CSWHOLD
: 1;
6506 extern __at(0x091B) volatile __OSCCON3bits_t OSCCON3bits
;
6510 #define _SOSCBE 0x20
6511 #define _SOSCPWR 0x40
6512 #define _CSWHOLD 0x80
6514 //==============================================================================
6517 //==============================================================================
6520 extern __at(0x091C) __sfr OSCSTAT1
;
6534 extern __at(0x091C) volatile __OSCSTAT1bits_t OSCSTAT1bits
;
6543 //==============================================================================
6546 //==============================================================================
6549 extern __at(0x091D) __sfr OSCEN
;
6556 unsigned SOSCEN
: 1;
6560 unsigned EXTOEN
: 1;
6563 extern __at(0x091D) volatile __OSCENbits_t OSCENbits
;
6566 #define _SOSCEN 0x08
6569 #define _EXTOEN 0x80
6571 //==============================================================================
6574 //==============================================================================
6577 extern __at(0x091E) __sfr OSCTUNE
;
6583 unsigned HFTUN0
: 1;
6584 unsigned HFTUN1
: 1;
6585 unsigned HFTUN2
: 1;
6586 unsigned HFTUN3
: 1;
6587 unsigned HFTUN4
: 1;
6588 unsigned HFTUN5
: 1;
6600 extern __at(0x091E) volatile __OSCTUNEbits_t OSCTUNEbits
;
6602 #define _HFTUN0 0x01
6603 #define _HFTUN1 0x02
6604 #define _HFTUN2 0x04
6605 #define _HFTUN3 0x08
6606 #define _HFTUN4 0x10
6607 #define _HFTUN5 0x20
6609 //==============================================================================
6612 //==============================================================================
6615 extern __at(0x091F) __sfr OSCFRQ
;
6621 unsigned HFFRQ0
: 1;
6622 unsigned HFFRQ1
: 1;
6623 unsigned HFFRQ2
: 1;
6624 unsigned HFFRQ3
: 1;
6638 extern __at(0x091F) volatile __OSCFRQbits_t OSCFRQbits
;
6640 #define _HFFRQ0 0x01
6641 #define _HFFRQ1 0x02
6642 #define _HFFRQ2 0x04
6643 #define _HFFRQ3 0x08
6645 //==============================================================================
6648 //==============================================================================
6651 extern __at(0x0E0F) __sfr PPSLOCK
;
6655 unsigned PPSLOCKED
: 1;
6665 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
6667 #define _PPSLOCKED 0x01
6669 //==============================================================================
6672 //==============================================================================
6675 extern __at(0x0E10) __sfr INTPPS
;
6681 unsigned INTPPS0
: 1;
6682 unsigned INTPPS1
: 1;
6683 unsigned INTPPS2
: 1;
6684 unsigned INTPPS3
: 1;
6685 unsigned INTPPS4
: 1;
6693 unsigned INTPPS
: 5;
6698 extern __at(0x0E10) volatile __INTPPSbits_t INTPPSbits
;
6700 #define _INTPPS0 0x01
6701 #define _INTPPS1 0x02
6702 #define _INTPPS2 0x04
6703 #define _INTPPS3 0x08
6704 #define _INTPPS4 0x10
6706 //==============================================================================
6709 //==============================================================================
6712 extern __at(0x0E11) __sfr T0CKIPPS
;
6718 unsigned T0CKIPPS0
: 1;
6719 unsigned T0CKIPPS1
: 1;
6720 unsigned T0CKIPPS2
: 1;
6721 unsigned T0CKIPPS3
: 1;
6722 unsigned T0CKIPPS4
: 1;
6730 unsigned T0CKIPPS
: 5;
6735 extern __at(0x0E11) volatile __T0CKIPPSbits_t T0CKIPPSbits
;
6737 #define _T0CKIPPS0 0x01
6738 #define _T0CKIPPS1 0x02
6739 #define _T0CKIPPS2 0x04
6740 #define _T0CKIPPS3 0x08
6741 #define _T0CKIPPS4 0x10
6743 //==============================================================================
6746 //==============================================================================
6749 extern __at(0x0E12) __sfr T1CKIPPS
;
6755 unsigned T1CKIPPS0
: 1;
6756 unsigned T1CKIPPS1
: 1;
6757 unsigned T1CKIPPS2
: 1;
6758 unsigned T1CKIPPS3
: 1;
6759 unsigned T1CKIPPS4
: 1;
6767 unsigned T1CKIPPS
: 5;
6772 extern __at(0x0E12) volatile __T1CKIPPSbits_t T1CKIPPSbits
;
6774 #define _T1CKIPPS0 0x01
6775 #define _T1CKIPPS1 0x02
6776 #define _T1CKIPPS2 0x04
6777 #define _T1CKIPPS3 0x08
6778 #define _T1CKIPPS4 0x10
6780 //==============================================================================
6783 //==============================================================================
6786 extern __at(0x0E13) __sfr T1GPPS
;
6792 unsigned T1GPPS0
: 1;
6793 unsigned T1GPPS1
: 1;
6794 unsigned T1GPPS2
: 1;
6795 unsigned T1GPPS3
: 1;
6796 unsigned T1GPPS4
: 1;
6804 unsigned T1GPPS
: 5;
6809 extern __at(0x0E13) volatile __T1GPPSbits_t T1GPPSbits
;
6811 #define _T1GPPS0 0x01
6812 #define _T1GPPS1 0x02
6813 #define _T1GPPS2 0x04
6814 #define _T1GPPS3 0x08
6815 #define _T1GPPS4 0x10
6817 //==============================================================================
6820 //==============================================================================
6823 extern __at(0x0E14) __sfr CCP1PPS
;
6829 unsigned CCP1PPS0
: 1;
6830 unsigned CCP1PPS1
: 1;
6831 unsigned CCP1PPS2
: 1;
6832 unsigned CCP1PPS3
: 1;
6833 unsigned CCP1PPS4
: 1;
6841 unsigned CCP1PPS
: 5;
6846 extern __at(0x0E14) volatile __CCP1PPSbits_t CCP1PPSbits
;
6848 #define _CCP1PPS0 0x01
6849 #define _CCP1PPS1 0x02
6850 #define _CCP1PPS2 0x04
6851 #define _CCP1PPS3 0x08
6852 #define _CCP1PPS4 0x10
6854 //==============================================================================
6857 //==============================================================================
6860 extern __at(0x0E15) __sfr CCP2PPS
;
6866 unsigned CCP2PPS0
: 1;
6867 unsigned CCP2PPS1
: 1;
6868 unsigned CCP2PPS2
: 1;
6869 unsigned CCP2PPS3
: 1;
6870 unsigned CCP2PPS4
: 1;
6878 unsigned CCP2PPS
: 5;
6883 extern __at(0x0E15) volatile __CCP2PPSbits_t CCP2PPSbits
;
6885 #define _CCP2PPS0 0x01
6886 #define _CCP2PPS1 0x02
6887 #define _CCP2PPS2 0x04
6888 #define _CCP2PPS3 0x08
6889 #define _CCP2PPS4 0x10
6891 //==============================================================================
6894 //==============================================================================
6897 extern __at(0x0E16) __sfr CCP3PPS
;
6903 unsigned CCP3PPS0
: 1;
6904 unsigned CCP3PPS1
: 1;
6905 unsigned CCP3PPS2
: 1;
6906 unsigned CCP3PPS3
: 1;
6907 unsigned CCP3PPS4
: 1;
6915 unsigned CCP3PPS
: 5;
6920 extern __at(0x0E16) volatile __CCP3PPSbits_t CCP3PPSbits
;
6922 #define _CCP3PPS0 0x01
6923 #define _CCP3PPS1 0x02
6924 #define _CCP3PPS2 0x04
6925 #define _CCP3PPS3 0x08
6926 #define _CCP3PPS4 0x10
6928 //==============================================================================
6931 //==============================================================================
6934 extern __at(0x0E17) __sfr CCP4PPS
;
6940 unsigned CCP4PPS0
: 1;
6941 unsigned CCP4PPS1
: 1;
6942 unsigned CCP4PPS2
: 1;
6943 unsigned CCP4PPS3
: 1;
6944 unsigned CCP4PPS4
: 1;
6952 unsigned CCP4PPS
: 5;
6957 extern __at(0x0E17) volatile __CCP4PPSbits_t CCP4PPSbits
;
6959 #define _CCP4PPS0 0x01
6960 #define _CCP4PPS1 0x02
6961 #define _CCP4PPS2 0x04
6962 #define _CCP4PPS3 0x08
6963 #define _CCP4PPS4 0x10
6965 //==============================================================================
6968 //==============================================================================
6971 extern __at(0x0E18) __sfr CWG1PPS
;
6977 unsigned CWG1PPS0
: 1;
6978 unsigned CWG1PPS1
: 1;
6979 unsigned CWG1PPS2
: 1;
6980 unsigned CWG1PPS3
: 1;
6981 unsigned CWG1PPS4
: 1;
6989 unsigned CWG1PPS
: 5;
6994 extern __at(0x0E18) volatile __CWG1PPSbits_t CWG1PPSbits
;
6996 #define _CWG1PPS0 0x01
6997 #define _CWG1PPS1 0x02
6998 #define _CWG1PPS2 0x04
6999 #define _CWG1PPS3 0x08
7000 #define _CWG1PPS4 0x10
7002 //==============================================================================
7005 //==============================================================================
7008 extern __at(0x0E19) __sfr CWG2PPS
;
7014 unsigned CWG2PPS0
: 1;
7015 unsigned CWG2PPS1
: 1;
7016 unsigned CWG2PPS2
: 1;
7017 unsigned CWG2PPS3
: 1;
7018 unsigned CWG2PPS4
: 1;
7026 unsigned CWG2PPS
: 5;
7031 extern __at(0x0E19) volatile __CWG2PPSbits_t CWG2PPSbits
;
7033 #define _CWG2PPS0 0x01
7034 #define _CWG2PPS1 0x02
7035 #define _CWG2PPS2 0x04
7036 #define _CWG2PPS3 0x08
7037 #define _CWG2PPS4 0x10
7039 //==============================================================================
7042 //==============================================================================
7045 extern __at(0x0E1A) __sfr MDCIN1PPS
;
7051 unsigned MDCIN1PPS0
: 1;
7052 unsigned MDCIN1PPS1
: 1;
7053 unsigned MDCIN1PPS2
: 1;
7054 unsigned MDCIN1PPS3
: 1;
7055 unsigned MDCIN1PPS4
: 1;
7063 unsigned MDCIN1PPS
: 5;
7066 } __MDCIN1PPSbits_t
;
7068 extern __at(0x0E1A) volatile __MDCIN1PPSbits_t MDCIN1PPSbits
;
7070 #define _MDCIN1PPS0 0x01
7071 #define _MDCIN1PPS1 0x02
7072 #define _MDCIN1PPS2 0x04
7073 #define _MDCIN1PPS3 0x08
7074 #define _MDCIN1PPS4 0x10
7076 //==============================================================================
7079 //==============================================================================
7082 extern __at(0x0E1B) __sfr MDCIN2PPS
;
7088 unsigned MDCIN2PPS0
: 1;
7089 unsigned MDCIN2PPS1
: 1;
7090 unsigned MDCIN2PPS2
: 1;
7091 unsigned MDCIN2PPS3
: 1;
7092 unsigned MDCIN2PPS4
: 1;
7100 unsigned MDCIN2PPS
: 5;
7103 } __MDCIN2PPSbits_t
;
7105 extern __at(0x0E1B) volatile __MDCIN2PPSbits_t MDCIN2PPSbits
;
7107 #define _MDCIN2PPS0 0x01
7108 #define _MDCIN2PPS1 0x02
7109 #define _MDCIN2PPS2 0x04
7110 #define _MDCIN2PPS3 0x08
7111 #define _MDCIN2PPS4 0x10
7113 //==============================================================================
7116 //==============================================================================
7119 extern __at(0x0E1C) __sfr MDMINPPS
;
7125 unsigned MDMINPPS0
: 1;
7126 unsigned MDMINPPS1
: 1;
7127 unsigned MDMINPPS2
: 1;
7128 unsigned MDMINPPS3
: 1;
7129 unsigned MDMINPPS4
: 1;
7137 unsigned MDMINPPS
: 5;
7142 extern __at(0x0E1C) volatile __MDMINPPSbits_t MDMINPPSbits
;
7144 #define _MDMINPPS0 0x01
7145 #define _MDMINPPS1 0x02
7146 #define _MDMINPPS2 0x04
7147 #define _MDMINPPS3 0x08
7148 #define _MDMINPPS4 0x10
7150 //==============================================================================
7153 //==============================================================================
7156 extern __at(0x0E1D) __sfr SSP2CLKPPS
;
7162 unsigned SSP2CLKPPS0
: 1;
7163 unsigned SSP2CLKPPS1
: 1;
7164 unsigned SSP2CLKPPS2
: 1;
7165 unsigned SSP2CLKPPS3
: 1;
7166 unsigned SSP2CLKPPS4
: 1;
7174 unsigned SSP2CLKPPS
: 5;
7177 } __SSP2CLKPPSbits_t
;
7179 extern __at(0x0E1D) volatile __SSP2CLKPPSbits_t SSP2CLKPPSbits
;
7181 #define _SSP2CLKPPS0 0x01
7182 #define _SSP2CLKPPS1 0x02
7183 #define _SSP2CLKPPS2 0x04
7184 #define _SSP2CLKPPS3 0x08
7185 #define _SSP2CLKPPS4 0x10
7187 //==============================================================================
7190 //==============================================================================
7193 extern __at(0x0E1E) __sfr SSP2DATPPS
;
7199 unsigned SSP2DATPPS0
: 1;
7200 unsigned SSP2DATPPS1
: 1;
7201 unsigned SSP2DATPPS2
: 1;
7202 unsigned SSP2DATPPS3
: 1;
7203 unsigned SSP2DATPPS4
: 1;
7211 unsigned SSP2DATPPS
: 5;
7214 } __SSP2DATPPSbits_t
;
7216 extern __at(0x0E1E) volatile __SSP2DATPPSbits_t SSP2DATPPSbits
;
7218 #define _SSP2DATPPS0 0x01
7219 #define _SSP2DATPPS1 0x02
7220 #define _SSP2DATPPS2 0x04
7221 #define _SSP2DATPPS3 0x08
7222 #define _SSP2DATPPS4 0x10
7224 //==============================================================================
7227 //==============================================================================
7230 extern __at(0x0E1F) __sfr SSP2SSPPS
;
7236 unsigned SSP2SSPPS0
: 1;
7237 unsigned SSP2SSPPS1
: 1;
7238 unsigned SSP2SSPPS2
: 1;
7239 unsigned SSP2SSPPS3
: 1;
7240 unsigned SSP2SSPPS4
: 1;
7248 unsigned SSP2SSPPS
: 5;
7251 } __SSP2SSPPSbits_t
;
7253 extern __at(0x0E1F) volatile __SSP2SSPPSbits_t SSP2SSPPSbits
;
7255 #define _SSP2SSPPS0 0x01
7256 #define _SSP2SSPPS1 0x02
7257 #define _SSP2SSPPS2 0x04
7258 #define _SSP2SSPPS3 0x08
7259 #define _SSP2SSPPS4 0x10
7261 //==============================================================================
7264 //==============================================================================
7267 extern __at(0x0E20) __sfr SSP1CLKPPS
;
7273 unsigned SSP1CLKPPS0
: 1;
7274 unsigned SSP1CLKPPS1
: 1;
7275 unsigned SSP1CLKPPS2
: 1;
7276 unsigned SSP1CLKPPS3
: 1;
7277 unsigned SSP1CLKPPS4
: 1;
7285 unsigned SSP1CLKPPS
: 5;
7288 } __SSP1CLKPPSbits_t
;
7290 extern __at(0x0E20) volatile __SSP1CLKPPSbits_t SSP1CLKPPSbits
;
7292 #define _SSP1CLKPPS0 0x01
7293 #define _SSP1CLKPPS1 0x02
7294 #define _SSP1CLKPPS2 0x04
7295 #define _SSP1CLKPPS3 0x08
7296 #define _SSP1CLKPPS4 0x10
7298 //==============================================================================
7301 //==============================================================================
7304 extern __at(0x0E21) __sfr SSP1DATPPS
;
7310 unsigned SSP1DATPPS0
: 1;
7311 unsigned SSP1DATPPS1
: 1;
7312 unsigned SSP1DATPPS2
: 1;
7313 unsigned SSP1DATPPS3
: 1;
7314 unsigned SSP1DATPPS4
: 1;
7322 unsigned SSP1DATPPS
: 5;
7325 } __SSP1DATPPSbits_t
;
7327 extern __at(0x0E21) volatile __SSP1DATPPSbits_t SSP1DATPPSbits
;
7329 #define _SSP1DATPPS0 0x01
7330 #define _SSP1DATPPS1 0x02
7331 #define _SSP1DATPPS2 0x04
7332 #define _SSP1DATPPS3 0x08
7333 #define _SSP1DATPPS4 0x10
7335 //==============================================================================
7338 //==============================================================================
7341 extern __at(0x0E22) __sfr SSP1SSPPS
;
7347 unsigned SSP1SSPPS0
: 1;
7348 unsigned SSP1SSPPS1
: 1;
7349 unsigned SSP1SSPPS2
: 1;
7350 unsigned SSP1SSPPS3
: 1;
7351 unsigned SSP1SSPPS4
: 1;
7359 unsigned SSP1SSPPS
: 5;
7362 } __SSP1SSPPSbits_t
;
7364 extern __at(0x0E22) volatile __SSP1SSPPSbits_t SSP1SSPPSbits
;
7366 #define _SSP1SSPPS0 0x01
7367 #define _SSP1SSPPS1 0x02
7368 #define _SSP1SSPPS2 0x04
7369 #define _SSP1SSPPS3 0x08
7370 #define _SSP1SSPPS4 0x10
7372 //==============================================================================
7375 //==============================================================================
7378 extern __at(0x0E24) __sfr RXPPS
;
7384 unsigned RXDTPPS0
: 1;
7385 unsigned RXDTPPS1
: 1;
7386 unsigned RXDTPPS2
: 1;
7387 unsigned RXDTPPS3
: 1;
7388 unsigned RXDTPPS4
: 1;
7396 unsigned RXDTPPS
: 5;
7401 extern __at(0x0E24) volatile __RXPPSbits_t RXPPSbits
;
7403 #define _RXDTPPS0 0x01
7404 #define _RXDTPPS1 0x02
7405 #define _RXDTPPS2 0x04
7406 #define _RXDTPPS3 0x08
7407 #define _RXDTPPS4 0x10
7409 //==============================================================================
7412 //==============================================================================
7415 extern __at(0x0E25) __sfr TXPPS
;
7421 unsigned TXCKPPS0
: 1;
7422 unsigned TXCKPPS1
: 1;
7423 unsigned TXCKPPS2
: 1;
7424 unsigned TXCKPPS3
: 1;
7425 unsigned TXCKPPS4
: 1;
7433 unsigned TXCKPPS
: 5;
7438 extern __at(0x0E25) volatile __TXPPSbits_t TXPPSbits
;
7440 #define _TXCKPPS0 0x01
7441 #define _TXCKPPS1 0x02
7442 #define _TXCKPPS2 0x04
7443 #define _TXCKPPS3 0x08
7444 #define _TXCKPPS4 0x10
7446 //==============================================================================
7449 //==============================================================================
7452 extern __at(0x0E28) __sfr CLCIN0PPS
;
7458 unsigned CLCIN0PPS0
: 1;
7459 unsigned CLCIN0PPS1
: 1;
7460 unsigned CLCIN0PPS2
: 1;
7461 unsigned CLCIN0PPS3
: 1;
7462 unsigned CLCIN0PPS4
: 1;
7470 unsigned CLCIN0PPS
: 5;
7473 } __CLCIN0PPSbits_t
;
7475 extern __at(0x0E28) volatile __CLCIN0PPSbits_t CLCIN0PPSbits
;
7477 #define _CLCIN0PPS0 0x01
7478 #define _CLCIN0PPS1 0x02
7479 #define _CLCIN0PPS2 0x04
7480 #define _CLCIN0PPS3 0x08
7481 #define _CLCIN0PPS4 0x10
7483 //==============================================================================
7486 //==============================================================================
7489 extern __at(0x0E29) __sfr CLCIN1PPS
;
7495 unsigned CLCIN1PPS0
: 1;
7496 unsigned CLCIN1PPS1
: 1;
7497 unsigned CLCIN1PPS2
: 1;
7498 unsigned CLCIN1PPS3
: 1;
7499 unsigned CLCIN1PPS4
: 1;
7507 unsigned CLCIN1PPS
: 5;
7510 } __CLCIN1PPSbits_t
;
7512 extern __at(0x0E29) volatile __CLCIN1PPSbits_t CLCIN1PPSbits
;
7514 #define _CLCIN1PPS0 0x01
7515 #define _CLCIN1PPS1 0x02
7516 #define _CLCIN1PPS2 0x04
7517 #define _CLCIN1PPS3 0x08
7518 #define _CLCIN1PPS4 0x10
7520 //==============================================================================
7523 //==============================================================================
7526 extern __at(0x0E2A) __sfr CLCIN2PPS
;
7532 unsigned CLCIN2PPS0
: 1;
7533 unsigned CLCIN2PPS1
: 1;
7534 unsigned CLCIN2PPS2
: 1;
7535 unsigned CLCIN2PPS3
: 1;
7536 unsigned CLCIN2PPS4
: 1;
7544 unsigned CLCIN2PPS
: 5;
7547 } __CLCIN2PPSbits_t
;
7549 extern __at(0x0E2A) volatile __CLCIN2PPSbits_t CLCIN2PPSbits
;
7551 #define _CLCIN2PPS0 0x01
7552 #define _CLCIN2PPS1 0x02
7553 #define _CLCIN2PPS2 0x04
7554 #define _CLCIN2PPS3 0x08
7555 #define _CLCIN2PPS4 0x10
7557 //==============================================================================
7560 //==============================================================================
7563 extern __at(0x0E2B) __sfr CLCIN3PPS
;
7569 unsigned CLCIN3PPS0
: 1;
7570 unsigned CLCIN3PPS1
: 1;
7571 unsigned CLCIN3PPS2
: 1;
7572 unsigned CLCIN3PPS3
: 1;
7573 unsigned CLCIN3PPS4
: 1;
7581 unsigned CLCIN3PPS
: 5;
7584 } __CLCIN3PPSbits_t
;
7586 extern __at(0x0E2B) volatile __CLCIN3PPSbits_t CLCIN3PPSbits
;
7588 #define _CLCIN3PPS0 0x01
7589 #define _CLCIN3PPS1 0x02
7590 #define _CLCIN3PPS2 0x04
7591 #define _CLCIN3PPS3 0x08
7592 #define _CLCIN3PPS4 0x10
7594 //==============================================================================
7596 extern __at(0x0E2C) __sfr T3CKIPPS
;
7597 extern __at(0x0E2D) __sfr T3GPPS
;
7598 extern __at(0x0E2E) __sfr T5CKIPPS
;
7599 extern __at(0x0E2F) __sfr T5GPPS
;
7601 //==============================================================================
7604 extern __at(0x0E90) __sfr RA0PPS
;
7610 unsigned RA0PPS0
: 1;
7611 unsigned RA0PPS1
: 1;
7612 unsigned RA0PPS2
: 1;
7613 unsigned RA0PPS3
: 1;
7614 unsigned RA0PPS4
: 1;
7622 unsigned RA0PPS
: 5;
7627 extern __at(0x0E90) volatile __RA0PPSbits_t RA0PPSbits
;
7629 #define _RA0PPS0 0x01
7630 #define _RA0PPS1 0x02
7631 #define _RA0PPS2 0x04
7632 #define _RA0PPS3 0x08
7633 #define _RA0PPS4 0x10
7635 //==============================================================================
7638 //==============================================================================
7641 extern __at(0x0E91) __sfr RA1PPS
;
7647 unsigned RA1PPS0
: 1;
7648 unsigned RA1PPS1
: 1;
7649 unsigned RA1PPS2
: 1;
7650 unsigned RA1PPS3
: 1;
7651 unsigned RA1PPS4
: 1;
7659 unsigned RA1PPS
: 5;
7664 extern __at(0x0E91) volatile __RA1PPSbits_t RA1PPSbits
;
7666 #define _RA1PPS0 0x01
7667 #define _RA1PPS1 0x02
7668 #define _RA1PPS2 0x04
7669 #define _RA1PPS3 0x08
7670 #define _RA1PPS4 0x10
7672 //==============================================================================
7675 //==============================================================================
7678 extern __at(0x0E92) __sfr RA2PPS
;
7684 unsigned RA2PPS0
: 1;
7685 unsigned RA2PPS1
: 1;
7686 unsigned RA2PPS2
: 1;
7687 unsigned RA2PPS3
: 1;
7688 unsigned RA2PPS4
: 1;
7696 unsigned RA2PPS
: 5;
7701 extern __at(0x0E92) volatile __RA2PPSbits_t RA2PPSbits
;
7703 #define _RA2PPS0 0x01
7704 #define _RA2PPS1 0x02
7705 #define _RA2PPS2 0x04
7706 #define _RA2PPS3 0x08
7707 #define _RA2PPS4 0x10
7709 //==============================================================================
7712 //==============================================================================
7715 extern __at(0x0E94) __sfr RA4PPS
;
7721 unsigned RA4PPS0
: 1;
7722 unsigned RA4PPS1
: 1;
7723 unsigned RA4PPS2
: 1;
7724 unsigned RA4PPS3
: 1;
7725 unsigned RA4PPS4
: 1;
7733 unsigned RA4PPS
: 5;
7738 extern __at(0x0E94) volatile __RA4PPSbits_t RA4PPSbits
;
7740 #define _RA4PPS0 0x01
7741 #define _RA4PPS1 0x02
7742 #define _RA4PPS2 0x04
7743 #define _RA4PPS3 0x08
7744 #define _RA4PPS4 0x10
7746 //==============================================================================
7749 //==============================================================================
7752 extern __at(0x0E95) __sfr RA5PPS
;
7758 unsigned RA5PPS0
: 1;
7759 unsigned RA5PPS1
: 1;
7760 unsigned RA5PPS2
: 1;
7761 unsigned RA5PPS3
: 1;
7762 unsigned RA5PPS4
: 1;
7770 unsigned RA5PPS
: 5;
7775 extern __at(0x0E95) volatile __RA5PPSbits_t RA5PPSbits
;
7777 #define _RA5PPS0 0x01
7778 #define _RA5PPS1 0x02
7779 #define _RA5PPS2 0x04
7780 #define _RA5PPS3 0x08
7781 #define _RA5PPS4 0x10
7783 //==============================================================================
7786 //==============================================================================
7789 extern __at(0x0EA0) __sfr RC0PPS
;
7795 unsigned RC0PPS0
: 1;
7796 unsigned RC0PPS1
: 1;
7797 unsigned RC0PPS2
: 1;
7798 unsigned RC0PPS3
: 1;
7799 unsigned RC0PPS4
: 1;
7807 unsigned RC0PPS
: 5;
7812 extern __at(0x0EA0) volatile __RC0PPSbits_t RC0PPSbits
;
7814 #define _RC0PPS0 0x01
7815 #define _RC0PPS1 0x02
7816 #define _RC0PPS2 0x04
7817 #define _RC0PPS3 0x08
7818 #define _RC0PPS4 0x10
7820 //==============================================================================
7823 //==============================================================================
7826 extern __at(0x0EA1) __sfr RC1PPS
;
7832 unsigned RC1PPS0
: 1;
7833 unsigned RC1PPS1
: 1;
7834 unsigned RC1PPS2
: 1;
7835 unsigned RC1PPS3
: 1;
7836 unsigned RC1PPS4
: 1;
7844 unsigned RC1PPS
: 5;
7849 extern __at(0x0EA1) volatile __RC1PPSbits_t RC1PPSbits
;
7851 #define _RC1PPS0 0x01
7852 #define _RC1PPS1 0x02
7853 #define _RC1PPS2 0x04
7854 #define _RC1PPS3 0x08
7855 #define _RC1PPS4 0x10
7857 //==============================================================================
7860 //==============================================================================
7863 extern __at(0x0EA2) __sfr RC2PPS
;
7869 unsigned RC2PPS0
: 1;
7870 unsigned RC2PPS1
: 1;
7871 unsigned RC2PPS2
: 1;
7872 unsigned RC2PPS3
: 1;
7873 unsigned RC2PPS4
: 1;
7881 unsigned RC2PPS
: 5;
7886 extern __at(0x0EA2) volatile __RC2PPSbits_t RC2PPSbits
;
7888 #define _RC2PPS0 0x01
7889 #define _RC2PPS1 0x02
7890 #define _RC2PPS2 0x04
7891 #define _RC2PPS3 0x08
7892 #define _RC2PPS4 0x10
7894 //==============================================================================
7897 //==============================================================================
7900 extern __at(0x0EA3) __sfr RC3PPS
;
7906 unsigned RC3PPS0
: 1;
7907 unsigned RC3PPS1
: 1;
7908 unsigned RC3PPS2
: 1;
7909 unsigned RC3PPS3
: 1;
7910 unsigned RC3PPS4
: 1;
7918 unsigned RC3PPS
: 5;
7923 extern __at(0x0EA3) volatile __RC3PPSbits_t RC3PPSbits
;
7925 #define _RC3PPS0 0x01
7926 #define _RC3PPS1 0x02
7927 #define _RC3PPS2 0x04
7928 #define _RC3PPS3 0x08
7929 #define _RC3PPS4 0x10
7931 //==============================================================================
7934 //==============================================================================
7937 extern __at(0x0EA4) __sfr RC4PPS
;
7943 unsigned RC4PPS0
: 1;
7944 unsigned RC4PPS1
: 1;
7945 unsigned RC4PPS2
: 1;
7946 unsigned RC4PPS3
: 1;
7947 unsigned RC4PPS4
: 1;
7955 unsigned RC4PPS
: 5;
7960 extern __at(0x0EA4) volatile __RC4PPSbits_t RC4PPSbits
;
7962 #define _RC4PPS0 0x01
7963 #define _RC4PPS1 0x02
7964 #define _RC4PPS2 0x04
7965 #define _RC4PPS3 0x08
7966 #define _RC4PPS4 0x10
7968 //==============================================================================
7971 //==============================================================================
7974 extern __at(0x0EA5) __sfr RC5PPS
;
7980 unsigned RC5PPS0
: 1;
7981 unsigned RC5PPS1
: 1;
7982 unsigned RC5PPS2
: 1;
7983 unsigned RC5PPS3
: 1;
7984 unsigned RC5PPS4
: 1;
7992 unsigned RC5PPS
: 5;
7997 extern __at(0x0EA5) volatile __RC5PPSbits_t RC5PPSbits
;
7999 #define _RC5PPS0 0x01
8000 #define _RC5PPS1 0x02
8001 #define _RC5PPS2 0x04
8002 #define _RC5PPS3 0x08
8003 #define _RC5PPS4 0x10
8005 //==============================================================================
8008 //==============================================================================
8011 extern __at(0x0F0F) __sfr CLCDATA
;
8015 unsigned MLC1OUT
: 1;
8016 unsigned MLC2OUT
: 1;
8017 unsigned MLC3OUT
: 1;
8018 unsigned MLC4OUT
: 1;
8025 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
8027 #define _MLC1OUT 0x01
8028 #define _MLC2OUT 0x02
8029 #define _MLC3OUT 0x04
8030 #define _MLC4OUT 0x08
8032 //==============================================================================
8035 //==============================================================================
8038 extern __at(0x0F10) __sfr CLC1CON
;
8044 unsigned LC1MODE0
: 1;
8045 unsigned LC1MODE1
: 1;
8046 unsigned LC1MODE2
: 1;
8047 unsigned LC1INTN
: 1;
8048 unsigned LC1INTP
: 1;
8049 unsigned LC1OUT
: 1;
8074 unsigned LC1MODE
: 3;
8079 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
8081 #define _LC1MODE0 0x01
8083 #define _LC1MODE1 0x02
8085 #define _LC1MODE2 0x04
8087 #define _LC1INTN 0x08
8089 #define _LC1INTP 0x10
8091 #define _LC1OUT 0x20
8096 //==============================================================================
8099 //==============================================================================
8102 extern __at(0x0F11) __sfr CLC1POL
;
8108 unsigned LC1G1POL
: 1;
8109 unsigned LC1G2POL
: 1;
8110 unsigned LC1G3POL
: 1;
8111 unsigned LC1G4POL
: 1;
8115 unsigned LC1POL
: 1;
8131 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
8133 #define _LC1G1POL 0x01
8135 #define _LC1G2POL 0x02
8137 #define _LC1G3POL 0x04
8139 #define _LC1G4POL 0x08
8141 #define _LC1POL 0x80
8144 //==============================================================================
8147 //==============================================================================
8150 extern __at(0x0F12) __sfr CLC1SEL0
;
8156 unsigned LC1D1S0
: 1;
8157 unsigned LC1D1S1
: 1;
8158 unsigned LC1D1S2
: 1;
8159 unsigned LC1D1S3
: 1;
8160 unsigned LC1D1S4
: 1;
8161 unsigned LC1D1S5
: 1;
8180 unsigned LC1D1S
: 6;
8191 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
8193 #define _LC1D1S0 0x01
8195 #define _LC1D1S1 0x02
8197 #define _LC1D1S2 0x04
8199 #define _LC1D1S3 0x08
8201 #define _LC1D1S4 0x10
8203 #define _LC1D1S5 0x20
8206 //==============================================================================
8209 //==============================================================================
8212 extern __at(0x0F13) __sfr CLC1SEL1
;
8218 unsigned LC1D2S0
: 1;
8219 unsigned LC1D2S1
: 1;
8220 unsigned LC1D2S2
: 1;
8221 unsigned LC1D2S3
: 1;
8222 unsigned LC1D2S4
: 1;
8223 unsigned LC1D2S5
: 1;
8242 unsigned LC1D2S
: 6;
8253 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
8255 #define _LC1D2S0 0x01
8257 #define _LC1D2S1 0x02
8259 #define _LC1D2S2 0x04
8261 #define _LC1D2S3 0x08
8263 #define _LC1D2S4 0x10
8265 #define _LC1D2S5 0x20
8268 //==============================================================================
8271 //==============================================================================
8274 extern __at(0x0F14) __sfr CLC1SEL2
;
8280 unsigned LC1D3S0
: 1;
8281 unsigned LC1D3S1
: 1;
8282 unsigned LC1D3S2
: 1;
8283 unsigned LC1D3S3
: 1;
8284 unsigned LC1D3S4
: 1;
8285 unsigned LC1D3S5
: 1;
8304 unsigned LC1D3S
: 6;
8315 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
8317 #define _LC1D3S0 0x01
8319 #define _LC1D3S1 0x02
8321 #define _LC1D3S2 0x04
8323 #define _LC1D3S3 0x08
8325 #define _LC1D3S4 0x10
8327 #define _LC1D3S5 0x20
8330 //==============================================================================
8333 //==============================================================================
8336 extern __at(0x0F15) __sfr CLC1SEL3
;
8342 unsigned LC1D4S0
: 1;
8343 unsigned LC1D4S1
: 1;
8344 unsigned LC1D4S2
: 1;
8345 unsigned LC1D4S3
: 1;
8346 unsigned LC1D4S4
: 1;
8347 unsigned LC1D4S5
: 1;
8366 unsigned LC1D4S
: 6;
8377 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
8379 #define _LC1D4S0 0x01
8381 #define _LC1D4S1 0x02
8383 #define _LC1D4S2 0x04
8385 #define _LC1D4S3 0x08
8387 #define _LC1D4S4 0x10
8389 #define _LC1D4S5 0x20
8392 //==============================================================================
8395 //==============================================================================
8398 extern __at(0x0F16) __sfr CLC1GLS0
;
8404 unsigned LC1G1D1N
: 1;
8405 unsigned LC1G1D1T
: 1;
8406 unsigned LC1G1D2N
: 1;
8407 unsigned LC1G1D2T
: 1;
8408 unsigned LC1G1D3N
: 1;
8409 unsigned LC1G1D3T
: 1;
8410 unsigned LC1G1D4N
: 1;
8411 unsigned LC1G1D4T
: 1;
8427 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
8429 #define _LC1G1D1N 0x01
8431 #define _LC1G1D1T 0x02
8433 #define _LC1G1D2N 0x04
8435 #define _LC1G1D2T 0x08
8437 #define _LC1G1D3N 0x10
8439 #define _LC1G1D3T 0x20
8441 #define _LC1G1D4N 0x40
8443 #define _LC1G1D4T 0x80
8446 //==============================================================================
8449 //==============================================================================
8452 extern __at(0x0F17) __sfr CLC1GLS1
;
8458 unsigned LC1G2D1N
: 1;
8459 unsigned LC1G2D1T
: 1;
8460 unsigned LC1G2D2N
: 1;
8461 unsigned LC1G2D2T
: 1;
8462 unsigned LC1G2D3N
: 1;
8463 unsigned LC1G2D3T
: 1;
8464 unsigned LC1G2D4N
: 1;
8465 unsigned LC1G2D4T
: 1;
8481 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
8483 #define _CLC1GLS1_LC1G2D1N 0x01
8484 #define _CLC1GLS1_D1N 0x01
8485 #define _CLC1GLS1_LC1G2D1T 0x02
8486 #define _CLC1GLS1_D1T 0x02
8487 #define _CLC1GLS1_LC1G2D2N 0x04
8488 #define _CLC1GLS1_D2N 0x04
8489 #define _CLC1GLS1_LC1G2D2T 0x08
8490 #define _CLC1GLS1_D2T 0x08
8491 #define _CLC1GLS1_LC1G2D3N 0x10
8492 #define _CLC1GLS1_D3N 0x10
8493 #define _CLC1GLS1_LC1G2D3T 0x20
8494 #define _CLC1GLS1_D3T 0x20
8495 #define _CLC1GLS1_LC1G2D4N 0x40
8496 #define _CLC1GLS1_D4N 0x40
8497 #define _CLC1GLS1_LC1G2D4T 0x80
8498 #define _CLC1GLS1_D4T 0x80
8500 //==============================================================================
8503 //==============================================================================
8506 extern __at(0x0F18) __sfr CLC1GLS2
;
8512 unsigned LC1G3D1N
: 1;
8513 unsigned LC1G3D1T
: 1;
8514 unsigned LC1G3D2N
: 1;
8515 unsigned LC1G3D2T
: 1;
8516 unsigned LC1G3D3N
: 1;
8517 unsigned LC1G3D3T
: 1;
8518 unsigned LC1G3D4N
: 1;
8519 unsigned LC1G3D4T
: 1;
8535 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
8537 #define _CLC1GLS2_LC1G3D1N 0x01
8538 #define _CLC1GLS2_D1N 0x01
8539 #define _CLC1GLS2_LC1G3D1T 0x02
8540 #define _CLC1GLS2_D1T 0x02
8541 #define _CLC1GLS2_LC1G3D2N 0x04
8542 #define _CLC1GLS2_D2N 0x04
8543 #define _CLC1GLS2_LC1G3D2T 0x08
8544 #define _CLC1GLS2_D2T 0x08
8545 #define _CLC1GLS2_LC1G3D3N 0x10
8546 #define _CLC1GLS2_D3N 0x10
8547 #define _CLC1GLS2_LC1G3D3T 0x20
8548 #define _CLC1GLS2_D3T 0x20
8549 #define _CLC1GLS2_LC1G3D4N 0x40
8550 #define _CLC1GLS2_D4N 0x40
8551 #define _CLC1GLS2_LC1G3D4T 0x80
8552 #define _CLC1GLS2_D4T 0x80
8554 //==============================================================================
8557 //==============================================================================
8560 extern __at(0x0F19) __sfr CLC1GLS3
;
8566 unsigned LC1G4D1N
: 1;
8567 unsigned LC1G4D1T
: 1;
8568 unsigned LC1G4D2N
: 1;
8569 unsigned LC1G4D2T
: 1;
8570 unsigned LC1G4D3N
: 1;
8571 unsigned LC1G4D3T
: 1;
8572 unsigned LC1G4D4N
: 1;
8573 unsigned LC1G4D4T
: 1;
8589 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
8591 #define _LC1G4D1N 0x01
8593 #define _LC1G4D1T 0x02
8595 #define _LC1G4D2N 0x04
8597 #define _LC1G4D2T 0x08
8599 #define _LC1G4D3N 0x10
8601 #define _LC1G4D3T 0x20
8603 #define _LC1G4D4N 0x40
8605 #define _LC1G4D4T 0x80
8608 //==============================================================================
8611 //==============================================================================
8614 extern __at(0x0F1A) __sfr CLC2CON
;
8620 unsigned LC2MODE0
: 1;
8621 unsigned LC2MODE1
: 1;
8622 unsigned LC2MODE2
: 1;
8623 unsigned LC2INTN
: 1;
8624 unsigned LC2INTP
: 1;
8625 unsigned LC2OUT
: 1;
8644 unsigned LC2MODE
: 3;
8655 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
8657 #define _CLC2CON_LC2MODE0 0x01
8658 #define _CLC2CON_MODE0 0x01
8659 #define _CLC2CON_LC2MODE1 0x02
8660 #define _CLC2CON_MODE1 0x02
8661 #define _CLC2CON_LC2MODE2 0x04
8662 #define _CLC2CON_MODE2 0x04
8663 #define _CLC2CON_LC2INTN 0x08
8664 #define _CLC2CON_INTN 0x08
8665 #define _CLC2CON_LC2INTP 0x10
8666 #define _CLC2CON_INTP 0x10
8667 #define _CLC2CON_LC2OUT 0x20
8668 #define _CLC2CON_OUT 0x20
8669 #define _CLC2CON_LC2EN 0x80
8670 #define _CLC2CON_EN 0x80
8672 //==============================================================================
8675 //==============================================================================
8678 extern __at(0x0F1B) __sfr CLC2POL
;
8684 unsigned LC2G1POL
: 1;
8685 unsigned LC2G2POL
: 1;
8686 unsigned LC2G3POL
: 1;
8687 unsigned LC2G4POL
: 1;
8691 unsigned LC2POL
: 1;
8707 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
8709 #define _CLC2POL_LC2G1POL 0x01
8710 #define _CLC2POL_G1POL 0x01
8711 #define _CLC2POL_LC2G2POL 0x02
8712 #define _CLC2POL_G2POL 0x02
8713 #define _CLC2POL_LC2G3POL 0x04
8714 #define _CLC2POL_G3POL 0x04
8715 #define _CLC2POL_LC2G4POL 0x08
8716 #define _CLC2POL_G4POL 0x08
8717 #define _CLC2POL_LC2POL 0x80
8718 #define _CLC2POL_POL 0x80
8720 //==============================================================================
8723 //==============================================================================
8726 extern __at(0x0F1C) __sfr CLC2SEL0
;
8732 unsigned LC2D1S0
: 1;
8733 unsigned LC2D1S1
: 1;
8734 unsigned LC2D1S2
: 1;
8735 unsigned LC2D1S3
: 1;
8736 unsigned LC2D1S4
: 1;
8737 unsigned LC2D1S5
: 1;
8756 unsigned LC2D1S
: 6;
8767 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
8769 #define _CLC2SEL0_LC2D1S0 0x01
8770 #define _CLC2SEL0_D1S0 0x01
8771 #define _CLC2SEL0_LC2D1S1 0x02
8772 #define _CLC2SEL0_D1S1 0x02
8773 #define _CLC2SEL0_LC2D1S2 0x04
8774 #define _CLC2SEL0_D1S2 0x04
8775 #define _CLC2SEL0_LC2D1S3 0x08
8776 #define _CLC2SEL0_D1S3 0x08
8777 #define _CLC2SEL0_LC2D1S4 0x10
8778 #define _CLC2SEL0_D1S4 0x10
8779 #define _CLC2SEL0_LC2D1S5 0x20
8780 #define _CLC2SEL0_D1S5 0x20
8782 //==============================================================================
8785 //==============================================================================
8788 extern __at(0x0F1D) __sfr CLC2SEL1
;
8794 unsigned LC2D2S0
: 1;
8795 unsigned LC2D2S1
: 1;
8796 unsigned LC2D2S2
: 1;
8797 unsigned LC2D2S3
: 1;
8798 unsigned LC2D2S4
: 1;
8799 unsigned LC2D2S5
: 1;
8818 unsigned LC2D2S
: 6;
8829 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
8831 #define _CLC2SEL1_LC2D2S0 0x01
8832 #define _CLC2SEL1_D2S0 0x01
8833 #define _CLC2SEL1_LC2D2S1 0x02
8834 #define _CLC2SEL1_D2S1 0x02
8835 #define _CLC2SEL1_LC2D2S2 0x04
8836 #define _CLC2SEL1_D2S2 0x04
8837 #define _CLC2SEL1_LC2D2S3 0x08
8838 #define _CLC2SEL1_D2S3 0x08
8839 #define _CLC2SEL1_LC2D2S4 0x10
8840 #define _CLC2SEL1_D2S4 0x10
8841 #define _CLC2SEL1_LC2D2S5 0x20
8842 #define _CLC2SEL1_D2S5 0x20
8844 //==============================================================================
8847 //==============================================================================
8850 extern __at(0x0F1E) __sfr CLC2SEL2
;
8856 unsigned LC2D3S0
: 1;
8857 unsigned LC2D3S1
: 1;
8858 unsigned LC2D3S2
: 1;
8859 unsigned LC2D3S3
: 1;
8860 unsigned LC2D3S4
: 1;
8861 unsigned LC2D3S5
: 1;
8886 unsigned LC2D3S
: 6;
8891 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
8893 #define _CLC2SEL2_LC2D3S0 0x01
8894 #define _CLC2SEL2_D3S0 0x01
8895 #define _CLC2SEL2_LC2D3S1 0x02
8896 #define _CLC2SEL2_D3S1 0x02
8897 #define _CLC2SEL2_LC2D3S2 0x04
8898 #define _CLC2SEL2_D3S2 0x04
8899 #define _CLC2SEL2_LC2D3S3 0x08
8900 #define _CLC2SEL2_D3S3 0x08
8901 #define _CLC2SEL2_LC2D3S4 0x10
8902 #define _CLC2SEL2_D3S4 0x10
8903 #define _CLC2SEL2_LC2D3S5 0x20
8904 #define _CLC2SEL2_D3S5 0x20
8906 //==============================================================================
8909 //==============================================================================
8912 extern __at(0x0F1F) __sfr CLC2SEL3
;
8918 unsigned LC2D4S0
: 1;
8919 unsigned LC2D4S1
: 1;
8920 unsigned LC2D4S2
: 1;
8921 unsigned LC2D4S3
: 1;
8922 unsigned LC2D4S4
: 1;
8923 unsigned LC2D4S5
: 1;
8942 unsigned LC2D4S
: 6;
8953 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
8955 #define _CLC2SEL3_LC2D4S0 0x01
8956 #define _CLC2SEL3_D4S0 0x01
8957 #define _CLC2SEL3_LC2D4S1 0x02
8958 #define _CLC2SEL3_D4S1 0x02
8959 #define _CLC2SEL3_LC2D4S2 0x04
8960 #define _CLC2SEL3_D4S2 0x04
8961 #define _CLC2SEL3_LC2D4S3 0x08
8962 #define _CLC2SEL3_D4S3 0x08
8963 #define _CLC2SEL3_LC2D4S4 0x10
8964 #define _CLC2SEL3_D4S4 0x10
8965 #define _CLC2SEL3_LC2D4S5 0x20
8966 #define _CLC2SEL3_D4S5 0x20
8968 //==============================================================================
8971 //==============================================================================
8974 extern __at(0x0F20) __sfr CLC2GLS0
;
8980 unsigned LC2G1D1N
: 1;
8981 unsigned LC2G1D1T
: 1;
8982 unsigned LC2G1D2N
: 1;
8983 unsigned LC2G1D2T
: 1;
8984 unsigned LC2G1D3N
: 1;
8985 unsigned LC2G1D3T
: 1;
8986 unsigned LC2G1D4N
: 1;
8987 unsigned LC2G1D4T
: 1;
9003 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
9005 #define _CLC2GLS0_LC2G1D1N 0x01
9006 #define _CLC2GLS0_D1N 0x01
9007 #define _CLC2GLS0_LC2G1D1T 0x02
9008 #define _CLC2GLS0_D1T 0x02
9009 #define _CLC2GLS0_LC2G1D2N 0x04
9010 #define _CLC2GLS0_D2N 0x04
9011 #define _CLC2GLS0_LC2G1D2T 0x08
9012 #define _CLC2GLS0_D2T 0x08
9013 #define _CLC2GLS0_LC2G1D3N 0x10
9014 #define _CLC2GLS0_D3N 0x10
9015 #define _CLC2GLS0_LC2G1D3T 0x20
9016 #define _CLC2GLS0_D3T 0x20
9017 #define _CLC2GLS0_LC2G1D4N 0x40
9018 #define _CLC2GLS0_D4N 0x40
9019 #define _CLC2GLS0_LC2G1D4T 0x80
9020 #define _CLC2GLS0_D4T 0x80
9022 //==============================================================================
9025 //==============================================================================
9028 extern __at(0x0F21) __sfr CLC2GLS1
;
9034 unsigned LC2G2D1N
: 1;
9035 unsigned LC2G2D1T
: 1;
9036 unsigned LC2G2D2N
: 1;
9037 unsigned LC2G2D2T
: 1;
9038 unsigned LC2G2D3N
: 1;
9039 unsigned LC2G2D3T
: 1;
9040 unsigned LC2G2D4N
: 1;
9041 unsigned LC2G2D4T
: 1;
9057 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
9059 #define _CLC2GLS1_LC2G2D1N 0x01
9060 #define _CLC2GLS1_D1N 0x01
9061 #define _CLC2GLS1_LC2G2D1T 0x02
9062 #define _CLC2GLS1_D1T 0x02
9063 #define _CLC2GLS1_LC2G2D2N 0x04
9064 #define _CLC2GLS1_D2N 0x04
9065 #define _CLC2GLS1_LC2G2D2T 0x08
9066 #define _CLC2GLS1_D2T 0x08
9067 #define _CLC2GLS1_LC2G2D3N 0x10
9068 #define _CLC2GLS1_D3N 0x10
9069 #define _CLC2GLS1_LC2G2D3T 0x20
9070 #define _CLC2GLS1_D3T 0x20
9071 #define _CLC2GLS1_LC2G2D4N 0x40
9072 #define _CLC2GLS1_D4N 0x40
9073 #define _CLC2GLS1_LC2G2D4T 0x80
9074 #define _CLC2GLS1_D4T 0x80
9076 //==============================================================================
9079 //==============================================================================
9082 extern __at(0x0F22) __sfr CLC2GLS2
;
9088 unsigned LC2G3D1N
: 1;
9089 unsigned LC2G3D1T
: 1;
9090 unsigned LC2G3D2N
: 1;
9091 unsigned LC2G3D2T
: 1;
9092 unsigned LC2G3D3N
: 1;
9093 unsigned LC2G3D3T
: 1;
9094 unsigned LC2G3D4N
: 1;
9095 unsigned LC2G3D4T
: 1;
9111 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
9113 #define _CLC2GLS2_LC2G3D1N 0x01
9114 #define _CLC2GLS2_D1N 0x01
9115 #define _CLC2GLS2_LC2G3D1T 0x02
9116 #define _CLC2GLS2_D1T 0x02
9117 #define _CLC2GLS2_LC2G3D2N 0x04
9118 #define _CLC2GLS2_D2N 0x04
9119 #define _CLC2GLS2_LC2G3D2T 0x08
9120 #define _CLC2GLS2_D2T 0x08
9121 #define _CLC2GLS2_LC2G3D3N 0x10
9122 #define _CLC2GLS2_D3N 0x10
9123 #define _CLC2GLS2_LC2G3D3T 0x20
9124 #define _CLC2GLS2_D3T 0x20
9125 #define _CLC2GLS2_LC2G3D4N 0x40
9126 #define _CLC2GLS2_D4N 0x40
9127 #define _CLC2GLS2_LC2G3D4T 0x80
9128 #define _CLC2GLS2_D4T 0x80
9130 //==============================================================================
9133 //==============================================================================
9136 extern __at(0x0F23) __sfr CLC2GLS3
;
9142 unsigned LC2G4D1N
: 1;
9143 unsigned LC2G4D1T
: 1;
9144 unsigned LC2G4D2N
: 1;
9145 unsigned LC2G4D2T
: 1;
9146 unsigned LC2G4D3N
: 1;
9147 unsigned LC2G4D3T
: 1;
9148 unsigned LC2G4D4N
: 1;
9149 unsigned LC2G4D4T
: 1;
9165 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
9167 #define _CLC2GLS3_LC2G4D1N 0x01
9168 #define _CLC2GLS3_G4D1N 0x01
9169 #define _CLC2GLS3_LC2G4D1T 0x02
9170 #define _CLC2GLS3_G4D1T 0x02
9171 #define _CLC2GLS3_LC2G4D2N 0x04
9172 #define _CLC2GLS3_G4D2N 0x04
9173 #define _CLC2GLS3_LC2G4D2T 0x08
9174 #define _CLC2GLS3_G4D2T 0x08
9175 #define _CLC2GLS3_LC2G4D3N 0x10
9176 #define _CLC2GLS3_G4D3N 0x10
9177 #define _CLC2GLS3_LC2G4D3T 0x20
9178 #define _CLC2GLS3_G4D3T 0x20
9179 #define _CLC2GLS3_LC2G4D4N 0x40
9180 #define _CLC2GLS3_G4D4N 0x40
9181 #define _CLC2GLS3_LC2G4D4T 0x80
9182 #define _CLC2GLS3_G4D4T 0x80
9184 //==============================================================================
9187 //==============================================================================
9190 extern __at(0x0F24) __sfr CLC3CON
;
9196 unsigned LC3MODE0
: 1;
9197 unsigned LC3MODE1
: 1;
9198 unsigned LC3MODE2
: 1;
9199 unsigned LC3INTN
: 1;
9200 unsigned LC3INTP
: 1;
9201 unsigned LC3OUT
: 1;
9220 unsigned LC3MODE
: 3;
9231 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
9233 #define _CLC3CON_LC3MODE0 0x01
9234 #define _CLC3CON_MODE0 0x01
9235 #define _CLC3CON_LC3MODE1 0x02
9236 #define _CLC3CON_MODE1 0x02
9237 #define _CLC3CON_LC3MODE2 0x04
9238 #define _CLC3CON_MODE2 0x04
9239 #define _CLC3CON_LC3INTN 0x08
9240 #define _CLC3CON_INTN 0x08
9241 #define _CLC3CON_LC3INTP 0x10
9242 #define _CLC3CON_INTP 0x10
9243 #define _CLC3CON_LC3OUT 0x20
9244 #define _CLC3CON_OUT 0x20
9245 #define _CLC3CON_LC3EN 0x80
9246 #define _CLC3CON_EN 0x80
9248 //==============================================================================
9251 //==============================================================================
9254 extern __at(0x0F25) __sfr CLC3POL
;
9260 unsigned LC3G1POL
: 1;
9261 unsigned LC3G2POL
: 1;
9262 unsigned LC3G3POL
: 1;
9263 unsigned LC3G4POL
: 1;
9267 unsigned LC3POL
: 1;
9283 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
9285 #define _CLC3POL_LC3G1POL 0x01
9286 #define _CLC3POL_G1POL 0x01
9287 #define _CLC3POL_LC3G2POL 0x02
9288 #define _CLC3POL_G2POL 0x02
9289 #define _CLC3POL_LC3G3POL 0x04
9290 #define _CLC3POL_G3POL 0x04
9291 #define _CLC3POL_LC3G4POL 0x08
9292 #define _CLC3POL_G4POL 0x08
9293 #define _CLC3POL_LC3POL 0x80
9294 #define _CLC3POL_POL 0x80
9296 //==============================================================================
9299 //==============================================================================
9302 extern __at(0x0F26) __sfr CLC3SEL0
;
9308 unsigned LC3D1S0
: 1;
9309 unsigned LC3D1S1
: 1;
9310 unsigned LC3D1S2
: 1;
9311 unsigned LC3D1S3
: 1;
9312 unsigned LC3D1S4
: 1;
9313 unsigned LC3D1S5
: 1;
9332 unsigned LC3D1S
: 6;
9343 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
9345 #define _CLC3SEL0_LC3D1S0 0x01
9346 #define _CLC3SEL0_D1S0 0x01
9347 #define _CLC3SEL0_LC3D1S1 0x02
9348 #define _CLC3SEL0_D1S1 0x02
9349 #define _CLC3SEL0_LC3D1S2 0x04
9350 #define _CLC3SEL0_D1S2 0x04
9351 #define _CLC3SEL0_LC3D1S3 0x08
9352 #define _CLC3SEL0_D1S3 0x08
9353 #define _CLC3SEL0_LC3D1S4 0x10
9354 #define _CLC3SEL0_D1S4 0x10
9355 #define _CLC3SEL0_LC3D1S5 0x20
9356 #define _CLC3SEL0_D1S5 0x20
9358 //==============================================================================
9361 //==============================================================================
9364 extern __at(0x0F27) __sfr CLC3SEL1
;
9370 unsigned LC3D2S0
: 1;
9371 unsigned LC3D2S1
: 1;
9372 unsigned LC3D2S2
: 1;
9373 unsigned LC3D2S3
: 1;
9374 unsigned LC3D2S4
: 1;
9375 unsigned LC3D2S5
: 1;
9400 unsigned LC3D2S
: 6;
9405 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
9407 #define _CLC3SEL1_LC3D2S0 0x01
9408 #define _CLC3SEL1_D2S0 0x01
9409 #define _CLC3SEL1_LC3D2S1 0x02
9410 #define _CLC3SEL1_D2S1 0x02
9411 #define _CLC3SEL1_LC3D2S2 0x04
9412 #define _CLC3SEL1_D2S2 0x04
9413 #define _CLC3SEL1_LC3D2S3 0x08
9414 #define _CLC3SEL1_D2S3 0x08
9415 #define _CLC3SEL1_LC3D2S4 0x10
9416 #define _CLC3SEL1_D2S4 0x10
9417 #define _CLC3SEL1_LC3D2S5 0x20
9418 #define _CLC3SEL1_D2S5 0x20
9420 //==============================================================================
9423 //==============================================================================
9426 extern __at(0x0F28) __sfr CLC3SEL2
;
9432 unsigned LC3D3S0
: 1;
9433 unsigned LC3D3S1
: 1;
9434 unsigned LC3D3S2
: 1;
9435 unsigned LC3D3S3
: 1;
9436 unsigned LC3D3S4
: 1;
9437 unsigned LC3D3S5
: 1;
9462 unsigned LC3D3S
: 6;
9467 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
9469 #define _CLC3SEL2_LC3D3S0 0x01
9470 #define _CLC3SEL2_D3S0 0x01
9471 #define _CLC3SEL2_LC3D3S1 0x02
9472 #define _CLC3SEL2_D3S1 0x02
9473 #define _CLC3SEL2_LC3D3S2 0x04
9474 #define _CLC3SEL2_D3S2 0x04
9475 #define _CLC3SEL2_LC3D3S3 0x08
9476 #define _CLC3SEL2_D3S3 0x08
9477 #define _CLC3SEL2_LC3D3S4 0x10
9478 #define _CLC3SEL2_D3S4 0x10
9479 #define _CLC3SEL2_LC3D3S5 0x20
9480 #define _CLC3SEL2_D3S5 0x20
9482 //==============================================================================
9485 //==============================================================================
9488 extern __at(0x0F29) __sfr CLC3SEL3
;
9494 unsigned LC3D4S0
: 1;
9495 unsigned LC3D4S1
: 1;
9496 unsigned LC3D4S2
: 1;
9497 unsigned LC3D4S3
: 1;
9498 unsigned LC3D4S4
: 1;
9499 unsigned LC3D4S5
: 1;
9524 unsigned LC3D4S
: 6;
9529 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
9531 #define _CLC3SEL3_LC3D4S0 0x01
9532 #define _CLC3SEL3_D4S0 0x01
9533 #define _CLC3SEL3_LC3D4S1 0x02
9534 #define _CLC3SEL3_D4S1 0x02
9535 #define _CLC3SEL3_LC3D4S2 0x04
9536 #define _CLC3SEL3_D4S2 0x04
9537 #define _CLC3SEL3_LC3D4S3 0x08
9538 #define _CLC3SEL3_D4S3 0x08
9539 #define _CLC3SEL3_LC3D4S4 0x10
9540 #define _CLC3SEL3_D4S4 0x10
9541 #define _CLC3SEL3_LC3D4S5 0x20
9542 #define _CLC3SEL3_D4S5 0x20
9544 //==============================================================================
9547 //==============================================================================
9550 extern __at(0x0F2A) __sfr CLC3GLS0
;
9556 unsigned LC3G1D1N
: 1;
9557 unsigned LC3G1D1T
: 1;
9558 unsigned LC3G1D2N
: 1;
9559 unsigned LC3G1D2T
: 1;
9560 unsigned LC3G1D3N
: 1;
9561 unsigned LC3G1D3T
: 1;
9562 unsigned LC3G1D4N
: 1;
9563 unsigned LC3G1D4T
: 1;
9579 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
9581 #define _CLC3GLS0_LC3G1D1N 0x01
9582 #define _CLC3GLS0_D1N 0x01
9583 #define _CLC3GLS0_LC3G1D1T 0x02
9584 #define _CLC3GLS0_D1T 0x02
9585 #define _CLC3GLS0_LC3G1D2N 0x04
9586 #define _CLC3GLS0_D2N 0x04
9587 #define _CLC3GLS0_LC3G1D2T 0x08
9588 #define _CLC3GLS0_D2T 0x08
9589 #define _CLC3GLS0_LC3G1D3N 0x10
9590 #define _CLC3GLS0_D3N 0x10
9591 #define _CLC3GLS0_LC3G1D3T 0x20
9592 #define _CLC3GLS0_D3T 0x20
9593 #define _CLC3GLS0_LC3G1D4N 0x40
9594 #define _CLC3GLS0_D4N 0x40
9595 #define _CLC3GLS0_LC3G1D4T 0x80
9596 #define _CLC3GLS0_D4T 0x80
9598 //==============================================================================
9601 //==============================================================================
9604 extern __at(0x0F2B) __sfr CLC3GLS1
;
9610 unsigned LC3G2D1N
: 1;
9611 unsigned LC3G2D1T
: 1;
9612 unsigned LC3G2D2N
: 1;
9613 unsigned LC3G2D2T
: 1;
9614 unsigned LC3G2D3N
: 1;
9615 unsigned LC3G2D3T
: 1;
9616 unsigned LC3G2D4N
: 1;
9617 unsigned LC3G2D4T
: 1;
9633 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
9635 #define _CLC3GLS1_LC3G2D1N 0x01
9636 #define _CLC3GLS1_D1N 0x01
9637 #define _CLC3GLS1_LC3G2D1T 0x02
9638 #define _CLC3GLS1_D1T 0x02
9639 #define _CLC3GLS1_LC3G2D2N 0x04
9640 #define _CLC3GLS1_D2N 0x04
9641 #define _CLC3GLS1_LC3G2D2T 0x08
9642 #define _CLC3GLS1_D2T 0x08
9643 #define _CLC3GLS1_LC3G2D3N 0x10
9644 #define _CLC3GLS1_D3N 0x10
9645 #define _CLC3GLS1_LC3G2D3T 0x20
9646 #define _CLC3GLS1_D3T 0x20
9647 #define _CLC3GLS1_LC3G2D4N 0x40
9648 #define _CLC3GLS1_D4N 0x40
9649 #define _CLC3GLS1_LC3G2D4T 0x80
9650 #define _CLC3GLS1_D4T 0x80
9652 //==============================================================================
9655 //==============================================================================
9658 extern __at(0x0F2C) __sfr CLC3GLS2
;
9664 unsigned LC3G3D1N
: 1;
9665 unsigned LC3G3D1T
: 1;
9666 unsigned LC3G3D2N
: 1;
9667 unsigned LC3G3D2T
: 1;
9668 unsigned LC3G3D3N
: 1;
9669 unsigned LC3G3D3T
: 1;
9670 unsigned LC3G3D4N
: 1;
9671 unsigned LC3G3D4T
: 1;
9687 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
9689 #define _CLC3GLS2_LC3G3D1N 0x01
9690 #define _CLC3GLS2_D1N 0x01
9691 #define _CLC3GLS2_LC3G3D1T 0x02
9692 #define _CLC3GLS2_D1T 0x02
9693 #define _CLC3GLS2_LC3G3D2N 0x04
9694 #define _CLC3GLS2_D2N 0x04
9695 #define _CLC3GLS2_LC3G3D2T 0x08
9696 #define _CLC3GLS2_D2T 0x08
9697 #define _CLC3GLS2_LC3G3D3N 0x10
9698 #define _CLC3GLS2_D3N 0x10
9699 #define _CLC3GLS2_LC3G3D3T 0x20
9700 #define _CLC3GLS2_D3T 0x20
9701 #define _CLC3GLS2_LC3G3D4N 0x40
9702 #define _CLC3GLS2_D4N 0x40
9703 #define _CLC3GLS2_LC3G3D4T 0x80
9704 #define _CLC3GLS2_D4T 0x80
9706 //==============================================================================
9709 //==============================================================================
9712 extern __at(0x0F2D) __sfr CLC3GLS3
;
9718 unsigned LC3G4D1N
: 1;
9719 unsigned LC3G4D1T
: 1;
9720 unsigned LC3G4D2N
: 1;
9721 unsigned LC3G4D2T
: 1;
9722 unsigned LC3G4D3N
: 1;
9723 unsigned LC3G4D3T
: 1;
9724 unsigned LC3G4D4N
: 1;
9725 unsigned LC3G4D4T
: 1;
9741 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
9743 #define _CLC3GLS3_LC3G4D1N 0x01
9744 #define _CLC3GLS3_G4D1N 0x01
9745 #define _CLC3GLS3_LC3G4D1T 0x02
9746 #define _CLC3GLS3_G4D1T 0x02
9747 #define _CLC3GLS3_LC3G4D2N 0x04
9748 #define _CLC3GLS3_G4D2N 0x04
9749 #define _CLC3GLS3_LC3G4D2T 0x08
9750 #define _CLC3GLS3_G4D2T 0x08
9751 #define _CLC3GLS3_LC3G4D3N 0x10
9752 #define _CLC3GLS3_G4D3N 0x10
9753 #define _CLC3GLS3_LC3G4D3T 0x20
9754 #define _CLC3GLS3_G4D3T 0x20
9755 #define _CLC3GLS3_LC3G4D4N 0x40
9756 #define _CLC3GLS3_G4D4N 0x40
9757 #define _CLC3GLS3_LC3G4D4T 0x80
9758 #define _CLC3GLS3_G4D4T 0x80
9760 //==============================================================================
9763 //==============================================================================
9766 extern __at(0x0F2E) __sfr CLC4CON
;
9772 unsigned LC4MODE0
: 1;
9773 unsigned LC4MODE1
: 1;
9774 unsigned LC4MODE2
: 1;
9775 unsigned LC4INTN
: 1;
9776 unsigned LC4INTP
: 1;
9777 unsigned LC4OUT
: 1;
9796 unsigned LC4MODE
: 3;
9807 extern __at(0x0F2E) volatile __CLC4CONbits_t CLC4CONbits
;
9809 #define _CLC4CON_LC4MODE0 0x01
9810 #define _CLC4CON_MODE0 0x01
9811 #define _CLC4CON_LC4MODE1 0x02
9812 #define _CLC4CON_MODE1 0x02
9813 #define _CLC4CON_LC4MODE2 0x04
9814 #define _CLC4CON_MODE2 0x04
9815 #define _CLC4CON_LC4INTN 0x08
9816 #define _CLC4CON_INTN 0x08
9817 #define _CLC4CON_LC4INTP 0x10
9818 #define _CLC4CON_INTP 0x10
9819 #define _CLC4CON_LC4OUT 0x20
9820 #define _CLC4CON_OUT 0x20
9821 #define _CLC4CON_LC4EN 0x80
9822 #define _CLC4CON_EN 0x80
9824 //==============================================================================
9827 //==============================================================================
9830 extern __at(0x0F2F) __sfr CLC4POL
;
9836 unsigned LC4G1POL
: 1;
9837 unsigned LC4G2POL
: 1;
9838 unsigned LC4G3POL
: 1;
9839 unsigned LC4G4POL
: 1;
9843 unsigned LC4POL
: 1;
9859 extern __at(0x0F2F) volatile __CLC4POLbits_t CLC4POLbits
;
9861 #define _CLC4POL_LC4G1POL 0x01
9862 #define _CLC4POL_G1POL 0x01
9863 #define _CLC4POL_LC4G2POL 0x02
9864 #define _CLC4POL_G2POL 0x02
9865 #define _CLC4POL_LC4G3POL 0x04
9866 #define _CLC4POL_G3POL 0x04
9867 #define _CLC4POL_LC4G4POL 0x08
9868 #define _CLC4POL_G4POL 0x08
9869 #define _CLC4POL_LC4POL 0x80
9870 #define _CLC4POL_POL 0x80
9872 //==============================================================================
9875 //==============================================================================
9878 extern __at(0x0F30) __sfr CLC4SEL0
;
9884 unsigned LC4D1S0
: 1;
9885 unsigned LC4D1S1
: 1;
9886 unsigned LC4D1S2
: 1;
9887 unsigned LC4D1S3
: 1;
9888 unsigned LC4D1S4
: 1;
9889 unsigned LC4D1S5
: 1;
9914 unsigned LC4D1S
: 6;
9919 extern __at(0x0F30) volatile __CLC4SEL0bits_t CLC4SEL0bits
;
9921 #define _CLC4SEL0_LC4D1S0 0x01
9922 #define _CLC4SEL0_D1S0 0x01
9923 #define _CLC4SEL0_LC4D1S1 0x02
9924 #define _CLC4SEL0_D1S1 0x02
9925 #define _CLC4SEL0_LC4D1S2 0x04
9926 #define _CLC4SEL0_D1S2 0x04
9927 #define _CLC4SEL0_LC4D1S3 0x08
9928 #define _CLC4SEL0_D1S3 0x08
9929 #define _CLC4SEL0_LC4D1S4 0x10
9930 #define _CLC4SEL0_D1S4 0x10
9931 #define _CLC4SEL0_LC4D1S5 0x20
9932 #define _CLC4SEL0_D1S5 0x20
9934 //==============================================================================
9937 //==============================================================================
9940 extern __at(0x0F31) __sfr CLC4SEL1
;
9946 unsigned LC4D2S0
: 1;
9947 unsigned LC4D2S1
: 1;
9948 unsigned LC4D2S2
: 1;
9949 unsigned LC4D2S3
: 1;
9950 unsigned LC4D2S4
: 1;
9951 unsigned LC4D2S5
: 1;
9970 unsigned LC4D2S
: 6;
9981 extern __at(0x0F31) volatile __CLC4SEL1bits_t CLC4SEL1bits
;
9983 #define _CLC4SEL1_LC4D2S0 0x01
9984 #define _CLC4SEL1_D2S0 0x01
9985 #define _CLC4SEL1_LC4D2S1 0x02
9986 #define _CLC4SEL1_D2S1 0x02
9987 #define _CLC4SEL1_LC4D2S2 0x04
9988 #define _CLC4SEL1_D2S2 0x04
9989 #define _CLC4SEL1_LC4D2S3 0x08
9990 #define _CLC4SEL1_D2S3 0x08
9991 #define _CLC4SEL1_LC4D2S4 0x10
9992 #define _CLC4SEL1_D2S4 0x10
9993 #define _CLC4SEL1_LC4D2S5 0x20
9994 #define _CLC4SEL1_D2S5 0x20
9996 //==============================================================================
9999 //==============================================================================
10002 extern __at(0x0F32) __sfr CLC4SEL2
;
10008 unsigned LC4D3S0
: 1;
10009 unsigned LC4D3S1
: 1;
10010 unsigned LC4D3S2
: 1;
10011 unsigned LC4D3S3
: 1;
10012 unsigned LC4D3S4
: 1;
10013 unsigned LC4D3S5
: 1;
10032 unsigned LC4D3S
: 6;
10041 } __CLC4SEL2bits_t
;
10043 extern __at(0x0F32) volatile __CLC4SEL2bits_t CLC4SEL2bits
;
10045 #define _CLC4SEL2_LC4D3S0 0x01
10046 #define _CLC4SEL2_D3S0 0x01
10047 #define _CLC4SEL2_LC4D3S1 0x02
10048 #define _CLC4SEL2_D3S1 0x02
10049 #define _CLC4SEL2_LC4D3S2 0x04
10050 #define _CLC4SEL2_D3S2 0x04
10051 #define _CLC4SEL2_LC4D3S3 0x08
10052 #define _CLC4SEL2_D3S3 0x08
10053 #define _CLC4SEL2_LC4D3S4 0x10
10054 #define _CLC4SEL2_D3S4 0x10
10055 #define _CLC4SEL2_LC4D3S5 0x20
10056 #define _CLC4SEL2_D3S5 0x20
10058 //==============================================================================
10061 //==============================================================================
10064 extern __at(0x0F33) __sfr CLC4SEL3
;
10070 unsigned LC4D4S0
: 1;
10071 unsigned LC4D4S1
: 1;
10072 unsigned LC4D4S2
: 1;
10073 unsigned LC4D4S3
: 1;
10074 unsigned LC4D4S4
: 1;
10075 unsigned LC4D4S5
: 1;
10100 unsigned LC4D4S
: 6;
10103 } __CLC4SEL3bits_t
;
10105 extern __at(0x0F33) volatile __CLC4SEL3bits_t CLC4SEL3bits
;
10107 #define _CLC4SEL3_LC4D4S0 0x01
10108 #define _CLC4SEL3_D4S0 0x01
10109 #define _CLC4SEL3_LC4D4S1 0x02
10110 #define _CLC4SEL3_D4S1 0x02
10111 #define _CLC4SEL3_LC4D4S2 0x04
10112 #define _CLC4SEL3_D4S2 0x04
10113 #define _CLC4SEL3_LC4D4S3 0x08
10114 #define _CLC4SEL3_D4S3 0x08
10115 #define _CLC4SEL3_LC4D4S4 0x10
10116 #define _CLC4SEL3_D4S4 0x10
10117 #define _CLC4SEL3_LC4D4S5 0x20
10118 #define _CLC4SEL3_D4S5 0x20
10120 //==============================================================================
10123 //==============================================================================
10126 extern __at(0x0F34) __sfr CLC4GLS0
;
10132 unsigned LC4G1D1N
: 1;
10133 unsigned LC4G1D1T
: 1;
10134 unsigned LC4G1D2N
: 1;
10135 unsigned LC4G1D2T
: 1;
10136 unsigned LC4G1D3N
: 1;
10137 unsigned LC4G1D3T
: 1;
10138 unsigned LC4G1D4N
: 1;
10139 unsigned LC4G1D4T
: 1;
10153 } __CLC4GLS0bits_t
;
10155 extern __at(0x0F34) volatile __CLC4GLS0bits_t CLC4GLS0bits
;
10157 #define _CLC4GLS0_LC4G1D1N 0x01
10158 #define _CLC4GLS0_D1N 0x01
10159 #define _CLC4GLS0_LC4G1D1T 0x02
10160 #define _CLC4GLS0_D1T 0x02
10161 #define _CLC4GLS0_LC4G1D2N 0x04
10162 #define _CLC4GLS0_D2N 0x04
10163 #define _CLC4GLS0_LC4G1D2T 0x08
10164 #define _CLC4GLS0_D2T 0x08
10165 #define _CLC4GLS0_LC4G1D3N 0x10
10166 #define _CLC4GLS0_D3N 0x10
10167 #define _CLC4GLS0_LC4G1D3T 0x20
10168 #define _CLC4GLS0_D3T 0x20
10169 #define _CLC4GLS0_LC4G1D4N 0x40
10170 #define _CLC4GLS0_D4N 0x40
10171 #define _CLC4GLS0_LC4G1D4T 0x80
10172 #define _CLC4GLS0_D4T 0x80
10174 //==============================================================================
10177 //==============================================================================
10180 extern __at(0x0F35) __sfr CLC4GLS1
;
10186 unsigned LC4G2D1N
: 1;
10187 unsigned LC4G2D1T
: 1;
10188 unsigned LC4G2D2N
: 1;
10189 unsigned LC4G2D2T
: 1;
10190 unsigned LC4G2D3N
: 1;
10191 unsigned LC4G2D3T
: 1;
10192 unsigned LC4G2D4N
: 1;
10193 unsigned LC4G2D4T
: 1;
10207 } __CLC4GLS1bits_t
;
10209 extern __at(0x0F35) volatile __CLC4GLS1bits_t CLC4GLS1bits
;
10211 #define _CLC4GLS1_LC4G2D1N 0x01
10212 #define _CLC4GLS1_D1N 0x01
10213 #define _CLC4GLS1_LC4G2D1T 0x02
10214 #define _CLC4GLS1_D1T 0x02
10215 #define _CLC4GLS1_LC4G2D2N 0x04
10216 #define _CLC4GLS1_D2N 0x04
10217 #define _CLC4GLS1_LC4G2D2T 0x08
10218 #define _CLC4GLS1_D2T 0x08
10219 #define _CLC4GLS1_LC4G2D3N 0x10
10220 #define _CLC4GLS1_D3N 0x10
10221 #define _CLC4GLS1_LC4G2D3T 0x20
10222 #define _CLC4GLS1_D3T 0x20
10223 #define _CLC4GLS1_LC4G2D4N 0x40
10224 #define _CLC4GLS1_D4N 0x40
10225 #define _CLC4GLS1_LC4G2D4T 0x80
10226 #define _CLC4GLS1_D4T 0x80
10228 //==============================================================================
10231 //==============================================================================
10234 extern __at(0x0F36) __sfr CLC4GLS2
;
10240 unsigned LC4G3D1N
: 1;
10241 unsigned LC4G3D1T
: 1;
10242 unsigned LC4G3D2N
: 1;
10243 unsigned LC4G3D2T
: 1;
10244 unsigned LC4G3D3N
: 1;
10245 unsigned LC4G3D3T
: 1;
10246 unsigned LC4G3D4N
: 1;
10247 unsigned LC4G3D4T
: 1;
10261 } __CLC4GLS2bits_t
;
10263 extern __at(0x0F36) volatile __CLC4GLS2bits_t CLC4GLS2bits
;
10265 #define _CLC4GLS2_LC4G3D1N 0x01
10266 #define _CLC4GLS2_D1N 0x01
10267 #define _CLC4GLS2_LC4G3D1T 0x02
10268 #define _CLC4GLS2_D1T 0x02
10269 #define _CLC4GLS2_LC4G3D2N 0x04
10270 #define _CLC4GLS2_D2N 0x04
10271 #define _CLC4GLS2_LC4G3D2T 0x08
10272 #define _CLC4GLS2_D2T 0x08
10273 #define _CLC4GLS2_LC4G3D3N 0x10
10274 #define _CLC4GLS2_D3N 0x10
10275 #define _CLC4GLS2_LC4G3D3T 0x20
10276 #define _CLC4GLS2_D3T 0x20
10277 #define _CLC4GLS2_LC4G3D4N 0x40
10278 #define _CLC4GLS2_D4N 0x40
10279 #define _CLC4GLS2_LC4G3D4T 0x80
10280 #define _CLC4GLS2_D4T 0x80
10282 //==============================================================================
10285 //==============================================================================
10288 extern __at(0x0F37) __sfr CLC4GLS3
;
10294 unsigned LC4G4D1N
: 1;
10295 unsigned LC4G4D1T
: 1;
10296 unsigned LC4G4D2N
: 1;
10297 unsigned LC4G4D2T
: 1;
10298 unsigned LC4G4D3N
: 1;
10299 unsigned LC4G4D3T
: 1;
10300 unsigned LC4G4D4N
: 1;
10301 unsigned LC4G4D4T
: 1;
10306 unsigned G4D1N
: 1;
10307 unsigned G4D1T
: 1;
10308 unsigned G4D2N
: 1;
10309 unsigned G4D2T
: 1;
10310 unsigned G4D3N
: 1;
10311 unsigned G4D3T
: 1;
10312 unsigned G4D4N
: 1;
10313 unsigned G4D4T
: 1;
10315 } __CLC4GLS3bits_t
;
10317 extern __at(0x0F37) volatile __CLC4GLS3bits_t CLC4GLS3bits
;
10319 #define _CLC4GLS3_LC4G4D1N 0x01
10320 #define _CLC4GLS3_G4D1N 0x01
10321 #define _CLC4GLS3_LC4G4D1T 0x02
10322 #define _CLC4GLS3_G4D1T 0x02
10323 #define _CLC4GLS3_LC4G4D2N 0x04
10324 #define _CLC4GLS3_G4D2N 0x04
10325 #define _CLC4GLS3_LC4G4D2T 0x08
10326 #define _CLC4GLS3_G4D2T 0x08
10327 #define _CLC4GLS3_LC4G4D3N 0x10
10328 #define _CLC4GLS3_G4D3N 0x10
10329 #define _CLC4GLS3_LC4G4D3T 0x20
10330 #define _CLC4GLS3_G4D3T 0x20
10331 #define _CLC4GLS3_LC4G4D4N 0x40
10332 #define _CLC4GLS3_G4D4N 0x40
10333 #define _CLC4GLS3_LC4G4D4T 0x80
10334 #define _CLC4GLS3_G4D4T 0x80
10336 //==============================================================================
10339 //==============================================================================
10340 // STATUS_SHAD Bits
10342 extern __at(0x0FE4) __sfr STATUS_SHAD
;
10346 unsigned C_SHAD
: 1;
10347 unsigned DC_SHAD
: 1;
10348 unsigned Z_SHAD
: 1;
10354 } __STATUS_SHADbits_t
;
10356 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
10358 #define _C_SHAD 0x01
10359 #define _DC_SHAD 0x02
10360 #define _Z_SHAD 0x04
10362 //==============================================================================
10364 extern __at(0x0FE5) __sfr WREG_SHAD
;
10365 extern __at(0x0FE6) __sfr BSR_SHAD
;
10366 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
10367 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
10368 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
10369 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
10370 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
10371 extern __at(0x0FED) __sfr STKPTR
;
10372 extern __at(0x0FEE) __sfr TOSL
;
10373 extern __at(0x0FEF) __sfr TOSH
;
10375 //==============================================================================
10377 // Configuration Bits
10379 //==============================================================================
10381 #define _CONFIG1 0x8007
10382 #define _CONFIG2 0x8008
10383 #define _CONFIG3 0x8009
10384 #define _CONFIG4 0x800A
10386 //----------------------------- CONFIG1 Options -------------------------------
10388 #define _FEXTOSC_LP 0x3FF8 // LP (crystal oscillator) optimized for 32.768 kHz.
10389 #define _FEXTOSC_XT 0x3FF9 // XT (crystal oscillator) from 100 kHz to 4 MHz.
10390 #define _FEXTOSC_HS 0x3FFA // HS (crystal oscillator) above 4 MHz.
10391 #define _FEXTOSC_OFF 0x3FFC // Oscillator not enabled.
10392 #define _FEXTOSC_ECL 0x3FFD // EC (external clock) below 100 kHz.
10393 #define _FEXTOSC_ECM 0x3FFE // EC (external clock) for 100 kHz to 8 MHz.
10394 #define _FEXTOSC_ECH 0x3FFF // EC (external clock) above 8 MHz.
10395 #define _RSTOSC_HFINT32 0x3F8F // HFINTOSC with 2x PLL (32MHz).
10396 #define _RSTOSC_EXT4X 0x3F9F // EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits.
10397 #define _RSTOSC_SOSC 0x3FBF // SOSC (31kHz).
10398 #define _RSTOSC_LFINT 0x3FCF // LFINTOSC (31kHz).
10399 #define _RSTOSC_HFINT1 0x3FEF // HFINTOSC (1MHz).
10400 #define _RSTOSC_EXT1X 0x3FFF // EXTOSC operating per FEXTOSC bits.
10401 #define _CLKOUTEN_ON 0x3EFF // CLKOUT function is enabled; FOSC/4 clock appears at OSC2.
10402 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled; I/O or oscillator function on OSC2.
10403 #define _CSWEN_OFF 0x37FF // The NOSC and NDIV bits cannot be changed by user software.
10404 #define _CSWEN_ON 0x3FFF // Writing to NOSC and NDIV is allowed.
10405 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
10406 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
10408 //----------------------------- CONFIG2 Options -------------------------------
10410 #define _MCLRE_OFF 0x3FFE // MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of port pin's WPU control bit.
10411 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR; Weak pull-up enabled.
10412 #define _PWRTE_ON 0x3FFD // PWRT enabled.
10413 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
10414 #define _WDTE_OFF 0x3FF3 // WDT disabled; SWDTEN is ignored.
10415 #define _WDTE_SWDTEN 0x3FF7 // WDT controlled by the SWDTEN bit in the WDTCON register.
10416 #define _WDTE_SLEEP 0x3FFB // WDT enabled while running and disabled in SLEEP/IDLE; SWDTEN is ignored.
10417 #define _WDTE_ON 0x3FFF // WDT enabled, SWDTEN is ignored.
10418 #define _LPBOREN_ON 0x3FDF // ULPBOR enabled.
10419 #define _LPBOREN_OFF 0x3FFF // ULPBOR disabled.
10420 #define _BOREN_OFF 0x3F3F // Brown-out Reset disabled.
10421 #define _BOREN_SBOREN 0x3F7F // Brown-out Reset enabled according to SBOREN.
10422 #define _BOREN_SLEEP 0x3FBF // Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored.
10423 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled, SBOREN bit ignored.
10424 #define _BORV_HIGH 0x3DFF // Brown-out voltage (Vbor) set to 2.7V.
10425 #define _BORV_LOW 0x3FFF // Brown-out voltage (Vbor) set to 2.45V.
10426 #define _PPS1WAY_OFF 0x37FF // The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence).
10427 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle.
10428 #define _STVREN_OFF 0x2FFF // Stack Overflow or Underflow will not cause a Reset.
10429 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
10430 #define _DEBUG_ON 0x1FFF // Background debugger enabled.
10431 #define _DEBUG_OFF 0x3FFF // Background debugger disabled.
10433 //----------------------------- CONFIG3 Options -------------------------------
10435 #define _WRT_ALL 0x3FFC // 0000h to 1FFFh write protected, no addresses may be modified.
10436 #define _WRT_HALF 0x3FFD // 0000h to 03FFh write-protected, 0400h to 1FFFh may be modified.
10437 #define _WRT_BOOT 0x3FFE // 0000h to 01FFh write-protected, 0200h to 1FFFh may be modified.
10438 #define _WRT_OFF 0x3FFF // Write protection off.
10439 #define _LVP_OFF 0x1FFF // High Voltage on MCLR/VPP must be used for programming.
10440 #define _LVP_ON 0x3FFF // Low Voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.
10442 //----------------------------- CONFIG4 Options -------------------------------
10444 #define _CP_ON 0x3FFE // User NVM code protection enabled.
10445 #define _CP_OFF 0x3FFF // User NVM code protection disabled.
10446 #define _CPD_ON 0x3FFD // Data NVM code protection enabled.
10447 #define _CPD_OFF 0x3FFF // Data NVM code protection disabled.
10449 //==============================================================================
10451 #define _DEVID1 0x8006
10453 #define _IDLOC0 0x8000
10454 #define _IDLOC1 0x8001
10455 #define _IDLOC2 0x8002
10456 #define _IDLOC3 0x8003
10458 //==============================================================================
10460 #ifndef NO_BIT_DEFINES
10462 #define ADACT0 ADACTbits.ADACT0 // bit 0
10463 #define ADACT1 ADACTbits.ADACT1 // bit 1
10464 #define ADACT2 ADACTbits.ADACT2 // bit 2
10465 #define ADACT3 ADACTbits.ADACT3 // bit 3
10466 #define ADACT4 ADACTbits.ADACT4 // bit 4
10468 #define ADON ADCON0bits.ADON // bit 0
10469 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
10470 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
10471 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
10472 #define CHS0 ADCON0bits.CHS0 // bit 2
10473 #define CHS1 ADCON0bits.CHS1 // bit 3
10474 #define CHS2 ADCON0bits.CHS2 // bit 4
10475 #define CHS3 ADCON0bits.CHS3 // bit 5
10476 #define CHS4 ADCON0bits.CHS4 // bit 6
10477 #define CHS5 ADCON0bits.CHS5 // bit 7
10479 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
10480 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
10481 #define ADNREF ADCON1bits.ADNREF // bit 2
10482 #define ADCS0 ADCON1bits.ADCS0 // bit 4
10483 #define ADCS1 ADCON1bits.ADCS1 // bit 5
10484 #define ADCS2 ADCON1bits.ADCS2 // bit 6
10485 #define ADFM ADCON1bits.ADFM // bit 7
10487 #define ANSA0 ANSELAbits.ANSA0 // bit 0
10488 #define ANSA1 ANSELAbits.ANSA1 // bit 1
10489 #define ANSA2 ANSELAbits.ANSA2 // bit 2
10490 #define ANSA4 ANSELAbits.ANSA4 // bit 4
10491 #define ANSA5 ANSELAbits.ANSA5 // bit 5
10493 #define ANSC0 ANSELCbits.ANSC0 // bit 0
10494 #define ANSC1 ANSELCbits.ANSC1 // bit 1
10495 #define ANSC2 ANSELCbits.ANSC2 // bit 2
10496 #define ANSC3 ANSELCbits.ANSC3 // bit 3
10497 #define ANSC4 ANSELCbits.ANSC4 // bit 4
10498 #define ANSC5 ANSELCbits.ANSC5 // bit 5
10500 #define ABDEN BAUD1CONbits.ABDEN // bit 0
10501 #define WUE BAUD1CONbits.WUE // bit 1
10502 #define BRG16 BAUD1CONbits.BRG16 // bit 3
10503 #define SCKP BAUD1CONbits.SCKP // bit 4
10504 #define RCIDL BAUD1CONbits.RCIDL // bit 6
10505 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
10507 #define BORRDY BORCONbits.BORRDY // bit 0
10508 #define SBOREN BORCONbits.SBOREN // bit 7
10510 #define BSR0 BSRbits.BSR0 // bit 0
10511 #define BSR1 BSRbits.BSR1 // bit 1
10512 #define BSR2 BSRbits.BSR2 // bit 2
10513 #define BSR3 BSRbits.BSR3 // bit 3
10514 #define BSR4 BSRbits.BSR4 // bit 4
10516 #define CCDS0 CCDCONbits.CCDS0 // bit 0
10517 #define CCDS1 CCDCONbits.CCDS1 // bit 1
10518 #define CCDEN CCDCONbits.CCDEN // bit 7
10520 #define CCDNA0 CCDNAbits.CCDNA0 // bit 0
10521 #define CCDNA1 CCDNAbits.CCDNA1 // bit 1
10522 #define CCDNA2 CCDNAbits.CCDNA2 // bit 2
10523 #define CCDNA4 CCDNAbits.CCDNA4 // bit 4
10524 #define CCDNA5 CCDNAbits.CCDNA5 // bit 5
10526 #define CCDNC0 CCDNCbits.CCDNC0 // bit 0
10527 #define CCDNC1 CCDNCbits.CCDNC1 // bit 1
10528 #define CCDNC2 CCDNCbits.CCDNC2 // bit 2
10529 #define CCDNC3 CCDNCbits.CCDNC3 // bit 3
10530 #define CCDNC4 CCDNCbits.CCDNC4 // bit 4
10531 #define CCDNC5 CCDNCbits.CCDNC5 // bit 5
10533 #define CCDPA0 CCDPAbits.CCDPA0 // bit 0
10534 #define CCDPA1 CCDPAbits.CCDPA1 // bit 1
10535 #define CCDPA2 CCDPAbits.CCDPA2 // bit 2
10536 #define CCDPA4 CCDPAbits.CCDPA4 // bit 4
10537 #define CCDPA5 CCDPAbits.CCDPA5 // bit 5
10539 #define CCDPC0 CCDPCbits.CCDPC0 // bit 0
10540 #define CCDPC1 CCDPCbits.CCDPC1 // bit 1
10541 #define CCDPC2 CCDPCbits.CCDPC2 // bit 2
10542 #define CCDPC3 CCDPCbits.CCDPC3 // bit 3
10543 #define CCDPC4 CCDPCbits.CCDPC4 // bit 4
10544 #define CCDPC5 CCDPCbits.CCDPC5 // bit 5
10546 #define CCP1CTS0 CCP1CAPbits.CCP1CTS0 // bit 0
10547 #define CCP1CTS1 CCP1CAPbits.CCP1CTS1 // bit 1
10548 #define CCP1CTS2 CCP1CAPbits.CCP1CTS2 // bit 2
10549 #define CCP1CTS3 CCP1CAPbits.CCP1CTS3 // bit 3
10551 #define CCP1MODE0 CCP1CONbits.CCP1MODE0 // bit 0
10552 #define CCP1MODE1 CCP1CONbits.CCP1MODE1 // bit 1
10553 #define CCP1MODE2 CCP1CONbits.CCP1MODE2 // bit 2
10554 #define CCP1MODE3 CCP1CONbits.CCP1MODE3 // bit 3
10555 #define CCP1FMT CCP1CONbits.CCP1FMT // bit 4
10556 #define CCP1OUT CCP1CONbits.CCP1OUT // bit 5
10557 #define CCP1EN CCP1CONbits.CCP1EN // bit 7
10559 #define CCP1PPS0 CCP1PPSbits.CCP1PPS0 // bit 0
10560 #define CCP1PPS1 CCP1PPSbits.CCP1PPS1 // bit 1
10561 #define CCP1PPS2 CCP1PPSbits.CCP1PPS2 // bit 2
10562 #define CCP1PPS3 CCP1PPSbits.CCP1PPS3 // bit 3
10563 #define CCP1PPS4 CCP1PPSbits.CCP1PPS4 // bit 4
10565 #define CCP2CTS0 CCP2CAPbits.CCP2CTS0 // bit 0
10566 #define CCP2CTS1 CCP2CAPbits.CCP2CTS1 // bit 1
10567 #define CCP2CTS2 CCP2CAPbits.CCP2CTS2 // bit 2
10568 #define CCP2CTS3 CCP2CAPbits.CCP2CTS3 // bit 3
10570 #define CCP2MODE0 CCP2CONbits.CCP2MODE0 // bit 0
10571 #define CCP2MODE1 CCP2CONbits.CCP2MODE1 // bit 1
10572 #define CCP2MODE2 CCP2CONbits.CCP2MODE2 // bit 2
10573 #define CCP2MODE3 CCP2CONbits.CCP2MODE3 // bit 3
10574 #define CCP2FMT CCP2CONbits.CCP2FMT // bit 4
10575 #define CCP2OUT CCP2CONbits.CCP2OUT // bit 5
10576 #define CCP2EN CCP2CONbits.CCP2EN // bit 7
10578 #define CCP2PPS0 CCP2PPSbits.CCP2PPS0 // bit 0
10579 #define CCP2PPS1 CCP2PPSbits.CCP2PPS1 // bit 1
10580 #define CCP2PPS2 CCP2PPSbits.CCP2PPS2 // bit 2
10581 #define CCP2PPS3 CCP2PPSbits.CCP2PPS3 // bit 3
10582 #define CCP2PPS4 CCP2PPSbits.CCP2PPS4 // bit 4
10584 #define CCP3CTS0 CCP3CAPbits.CCP3CTS0 // bit 0
10585 #define CCP3CTS1 CCP3CAPbits.CCP3CTS1 // bit 1
10586 #define CCP3CTS2 CCP3CAPbits.CCP3CTS2 // bit 2
10587 #define CCP3CTS3 CCP3CAPbits.CCP3CTS3 // bit 3
10589 #define CCP3MODE0 CCP3CONbits.CCP3MODE0 // bit 0
10590 #define CCP3MODE1 CCP3CONbits.CCP3MODE1 // bit 1
10591 #define CCP3MODE2 CCP3CONbits.CCP3MODE2 // bit 2
10592 #define CCP3MODE3 CCP3CONbits.CCP3MODE3 // bit 3
10593 #define CCP3FMT CCP3CONbits.CCP3FMT // bit 4
10594 #define CCP3OUT CCP3CONbits.CCP3OUT // bit 5
10595 #define CCP3EN CCP3CONbits.CCP3EN // bit 7
10597 #define CCP3PPS0 CCP3PPSbits.CCP3PPS0 // bit 0
10598 #define CCP3PPS1 CCP3PPSbits.CCP3PPS1 // bit 1
10599 #define CCP3PPS2 CCP3PPSbits.CCP3PPS2 // bit 2
10600 #define CCP3PPS3 CCP3PPSbits.CCP3PPS3 // bit 3
10601 #define CCP3PPS4 CCP3PPSbits.CCP3PPS4 // bit 4
10603 #define CCP4CTS0 CCP4CAPbits.CCP4CTS0 // bit 0
10604 #define CCP4CTS1 CCP4CAPbits.CCP4CTS1 // bit 1
10605 #define CCP4CTS2 CCP4CAPbits.CCP4CTS2 // bit 2
10606 #define CCP4CTS3 CCP4CAPbits.CCP4CTS3 // bit 3
10608 #define CCP4MODE0 CCP4CONbits.CCP4MODE0 // bit 0
10609 #define CCP4MODE1 CCP4CONbits.CCP4MODE1 // bit 1
10610 #define CCP4MODE2 CCP4CONbits.CCP4MODE2 // bit 2
10611 #define CCP4MODE3 CCP4CONbits.CCP4MODE3 // bit 3
10612 #define CCP4FMT CCP4CONbits.CCP4FMT // bit 4
10613 #define CCP4OUT CCP4CONbits.CCP4OUT // bit 5
10614 #define CCP4EN CCP4CONbits.CCP4EN // bit 7
10616 #define CCP4PPS0 CCP4PPSbits.CCP4PPS0 // bit 0
10617 #define CCP4PPS1 CCP4PPSbits.CCP4PPS1 // bit 1
10618 #define CCP4PPS2 CCP4PPSbits.CCP4PPS2 // bit 2
10619 #define CCP4PPS3 CCP4PPSbits.CCP4PPS3 // bit 3
10620 #define CCP4PPS4 CCP4PPSbits.CCP4PPS4 // bit 4
10622 #define C1TSEL0 CCPTMRSbits.C1TSEL0 // bit 0
10623 #define C1TSEL1 CCPTMRSbits.C1TSEL1 // bit 1
10624 #define C2TSEL0 CCPTMRSbits.C2TSEL0 // bit 2
10625 #define C2TSEL1 CCPTMRSbits.C2TSEL1 // bit 3
10626 #define C3TSEL0 CCPTMRSbits.C3TSEL0 // bit 4
10627 #define C3TSEL1 CCPTMRSbits.C3TSEL1 // bit 5
10628 #define C4TSEL0 CCPTMRSbits.C4TSEL0 // bit 6
10629 #define C4TSEL1 CCPTMRSbits.C4TSEL1 // bit 7
10631 #define LC1MODE0 CLC1CONbits.LC1MODE0 // bit 0, shadows bit in CLC1CONbits
10632 #define MODE0 CLC1CONbits.MODE0 // bit 0, shadows bit in CLC1CONbits
10633 #define LC1MODE1 CLC1CONbits.LC1MODE1 // bit 1, shadows bit in CLC1CONbits
10634 #define MODE1 CLC1CONbits.MODE1 // bit 1, shadows bit in CLC1CONbits
10635 #define LC1MODE2 CLC1CONbits.LC1MODE2 // bit 2, shadows bit in CLC1CONbits
10636 #define MODE2 CLC1CONbits.MODE2 // bit 2, shadows bit in CLC1CONbits
10637 #define LC1INTN CLC1CONbits.LC1INTN // bit 3, shadows bit in CLC1CONbits
10638 #define INTN CLC1CONbits.INTN // bit 3, shadows bit in CLC1CONbits
10639 #define LC1INTP CLC1CONbits.LC1INTP // bit 4, shadows bit in CLC1CONbits
10640 #define INTP CLC1CONbits.INTP // bit 4, shadows bit in CLC1CONbits
10641 #define LC1OUT CLC1CONbits.LC1OUT // bit 5, shadows bit in CLC1CONbits
10642 #define OUT CLC1CONbits.OUT // bit 5, shadows bit in CLC1CONbits
10643 #define LC1EN CLC1CONbits.LC1EN // bit 7, shadows bit in CLC1CONbits
10644 #define EN CLC1CONbits.EN // bit 7, shadows bit in CLC1CONbits
10646 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
10647 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
10648 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
10649 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
10650 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
10651 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
10652 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
10653 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
10654 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
10655 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
10656 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
10657 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
10658 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
10659 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
10660 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
10661 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
10663 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
10664 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
10665 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
10666 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
10667 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
10668 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
10669 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
10670 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
10671 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
10672 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
10673 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
10674 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
10675 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
10676 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
10677 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
10678 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
10680 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
10681 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
10682 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
10683 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
10684 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
10685 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
10686 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
10687 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
10688 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
10689 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
10691 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
10692 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
10693 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
10694 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
10695 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
10696 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
10697 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
10698 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
10699 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
10700 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
10701 #define LC1D1S5 CLC1SEL0bits.LC1D1S5 // bit 5, shadows bit in CLC1SEL0bits
10702 #define D1S5 CLC1SEL0bits.D1S5 // bit 5, shadows bit in CLC1SEL0bits
10704 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
10705 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
10706 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
10707 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
10708 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
10709 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
10710 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
10711 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
10712 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
10713 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
10714 #define LC1D2S5 CLC1SEL1bits.LC1D2S5 // bit 5, shadows bit in CLC1SEL1bits
10715 #define D2S5 CLC1SEL1bits.D2S5 // bit 5, shadows bit in CLC1SEL1bits
10717 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
10718 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
10719 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
10720 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
10721 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
10722 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
10723 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
10724 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
10725 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
10726 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
10727 #define LC1D3S5 CLC1SEL2bits.LC1D3S5 // bit 5, shadows bit in CLC1SEL2bits
10728 #define D3S5 CLC1SEL2bits.D3S5 // bit 5, shadows bit in CLC1SEL2bits
10730 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
10731 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
10732 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
10733 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
10734 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
10735 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
10736 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
10737 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
10738 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
10739 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
10740 #define LC1D4S5 CLC1SEL3bits.LC1D4S5 // bit 5, shadows bit in CLC1SEL3bits
10741 #define D4S5 CLC1SEL3bits.D4S5 // bit 5, shadows bit in CLC1SEL3bits
10743 #define MLC1OUT CLCDATAbits.MLC1OUT // bit 0
10744 #define MLC2OUT CLCDATAbits.MLC2OUT // bit 1
10745 #define MLC3OUT CLCDATAbits.MLC3OUT // bit 2
10746 #define MLC4OUT CLCDATAbits.MLC4OUT // bit 3
10748 #define CLCIN0PPS0 CLCIN0PPSbits.CLCIN0PPS0 // bit 0
10749 #define CLCIN0PPS1 CLCIN0PPSbits.CLCIN0PPS1 // bit 1
10750 #define CLCIN0PPS2 CLCIN0PPSbits.CLCIN0PPS2 // bit 2
10751 #define CLCIN0PPS3 CLCIN0PPSbits.CLCIN0PPS3 // bit 3
10752 #define CLCIN0PPS4 CLCIN0PPSbits.CLCIN0PPS4 // bit 4
10754 #define CLCIN1PPS0 CLCIN1PPSbits.CLCIN1PPS0 // bit 0
10755 #define CLCIN1PPS1 CLCIN1PPSbits.CLCIN1PPS1 // bit 1
10756 #define CLCIN1PPS2 CLCIN1PPSbits.CLCIN1PPS2 // bit 2
10757 #define CLCIN1PPS3 CLCIN1PPSbits.CLCIN1PPS3 // bit 3
10758 #define CLCIN1PPS4 CLCIN1PPSbits.CLCIN1PPS4 // bit 4
10760 #define CLCIN2PPS0 CLCIN2PPSbits.CLCIN2PPS0 // bit 0
10761 #define CLCIN2PPS1 CLCIN2PPSbits.CLCIN2PPS1 // bit 1
10762 #define CLCIN2PPS2 CLCIN2PPSbits.CLCIN2PPS2 // bit 2
10763 #define CLCIN2PPS3 CLCIN2PPSbits.CLCIN2PPS3 // bit 3
10764 #define CLCIN2PPS4 CLCIN2PPSbits.CLCIN2PPS4 // bit 4
10766 #define CLCIN3PPS0 CLCIN3PPSbits.CLCIN3PPS0 // bit 0
10767 #define CLCIN3PPS1 CLCIN3PPSbits.CLCIN3PPS1 // bit 1
10768 #define CLCIN3PPS2 CLCIN3PPSbits.CLCIN3PPS2 // bit 2
10769 #define CLCIN3PPS3 CLCIN3PPSbits.CLCIN3PPS3 // bit 3
10770 #define CLCIN3PPS4 CLCIN3PPSbits.CLCIN3PPS4 // bit 4
10772 #define CLKRDIV0 CLKRCONbits.CLKRDIV0 // bit 0
10773 #define CLKRDIV1 CLKRCONbits.CLKRDIV1 // bit 1
10774 #define CLKRDIV2 CLKRCONbits.CLKRDIV2 // bit 2
10775 #define CLKRDC0 CLKRCONbits.CLKRDC0 // bit 3
10776 #define CLKRDC1 CLKRCONbits.CLKRDC1 // bit 4
10777 #define CLKREN CLKRCONbits.CLKREN // bit 7
10779 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
10780 #define C1HYS CM1CON0bits.C1HYS // bit 1
10781 #define C1SP CM1CON0bits.C1SP // bit 2
10782 #define C1POL CM1CON0bits.C1POL // bit 4
10783 #define C1OUT CM1CON0bits.C1OUT // bit 6
10784 #define C1ON CM1CON0bits.C1ON // bit 7
10786 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
10787 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
10788 #define C1NCH2 CM1CON1bits.C1NCH2 // bit 2
10789 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 3
10790 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 4
10791 #define C1PCH2 CM1CON1bits.C1PCH2 // bit 5
10792 #define C1INTN CM1CON1bits.C1INTN // bit 6
10793 #define C1INTP CM1CON1bits.C1INTP // bit 7
10795 #define C2SYNC CM2CON0bits.C2SYNC // bit 0
10796 #define C2HYS CM2CON0bits.C2HYS // bit 1
10797 #define C2SP CM2CON0bits.C2SP // bit 2
10798 #define C2POL CM2CON0bits.C2POL // bit 4
10799 #define C2OUT CM2CON0bits.C2OUT // bit 6
10800 #define C2ON CM2CON0bits.C2ON // bit 7
10802 #define C2NCH0 CM2CON1bits.C2NCH0 // bit 0
10803 #define C2NCH1 CM2CON1bits.C2NCH1 // bit 1
10804 #define C2NCH2 CM2CON1bits.C2NCH2 // bit 2
10805 #define C2PCH0 CM2CON1bits.C2PCH0 // bit 3
10806 #define C2PCH1 CM2CON1bits.C2PCH1 // bit 4
10807 #define C2PCH2 CM2CON1bits.C2PCH2 // bit 5
10808 #define C2INTN CM2CON1bits.C2INTN // bit 6
10809 #define C2INTP CM2CON1bits.C2INTP // bit 7
10811 #define MC1OUT CMOUTbits.MC1OUT // bit 0
10812 #define MC2OUT CMOUTbits.MC2OUT // bit 1
10814 #define DOZE0 CPUDOZEbits.DOZE0 // bit 0
10815 #define DOZE1 CPUDOZEbits.DOZE1 // bit 1
10816 #define DOZE2 CPUDOZEbits.DOZE2 // bit 2
10817 #define DOE CPUDOZEbits.DOE // bit 4
10818 #define ROI CPUDOZEbits.ROI // bit 5
10819 #define DOZEN CPUDOZEbits.DOZEN // bit 6
10820 #define IDLEN CPUDOZEbits.IDLEN // bit 7
10822 #define LSAC0 CWG1AS0bits.LSAC0 // bit 2, shadows bit in CWG1AS0bits
10823 #define CWG1LSAC0 CWG1AS0bits.CWG1LSAC0 // bit 2, shadows bit in CWG1AS0bits
10824 #define LSAC1 CWG1AS0bits.LSAC1 // bit 3, shadows bit in CWG1AS0bits
10825 #define CWG1LSAC1 CWG1AS0bits.CWG1LSAC1 // bit 3, shadows bit in CWG1AS0bits
10826 #define LSBD0 CWG1AS0bits.LSBD0 // bit 4, shadows bit in CWG1AS0bits
10827 #define CWG1LSBD0 CWG1AS0bits.CWG1LSBD0 // bit 4, shadows bit in CWG1AS0bits
10828 #define LSBD1 CWG1AS0bits.LSBD1 // bit 5, shadows bit in CWG1AS0bits
10829 #define CWG1LSBD1 CWG1AS0bits.CWG1LSBD1 // bit 5, shadows bit in CWG1AS0bits
10830 #define REN CWG1AS0bits.REN // bit 6, shadows bit in CWG1AS0bits
10831 #define CWG1REN CWG1AS0bits.CWG1REN // bit 6, shadows bit in CWG1AS0bits
10832 #define SHUTDOWN CWG1AS0bits.SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
10833 #define CWG1SHUTDOWN CWG1AS0bits.CWG1SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
10835 #define AS0E CWG1AS1bits.AS0E // bit 0
10836 #define AS1E CWG1AS1bits.AS1E // bit 1
10837 #define AS2E CWG1AS1bits.AS2E // bit 2
10838 #define AS3E CWG1AS1bits.AS3E // bit 3
10839 #define AS4E CWG1AS1bits.AS4E // bit 4
10841 #define CS CWG1CLKCONbits.CS // bit 0, shadows bit in CWG1CLKCONbits
10842 #define CWG1CS CWG1CLKCONbits.CWG1CS // bit 0, shadows bit in CWG1CLKCONbits
10844 #define POLA CWG1CON1bits.POLA // bit 0, shadows bit in CWG1CON1bits
10845 #define CWG1POLA CWG1CON1bits.CWG1POLA // bit 0, shadows bit in CWG1CON1bits
10846 #define POLB CWG1CON1bits.POLB // bit 1, shadows bit in CWG1CON1bits
10847 #define CWG1POLB CWG1CON1bits.CWG1POLB // bit 1, shadows bit in CWG1CON1bits
10848 #define POLC CWG1CON1bits.POLC // bit 2, shadows bit in CWG1CON1bits
10849 #define CWG1POLC CWG1CON1bits.CWG1POLC // bit 2, shadows bit in CWG1CON1bits
10850 #define POLD CWG1CON1bits.POLD // bit 3, shadows bit in CWG1CON1bits
10851 #define CWG1POLD CWG1CON1bits.CWG1POLD // bit 3, shadows bit in CWG1CON1bits
10852 #define IN CWG1CON1bits.IN // bit 5, shadows bit in CWG1CON1bits
10853 #define CWG1IN CWG1CON1bits.CWG1IN // bit 5, shadows bit in CWG1CON1bits
10855 #define CWG1DAT0 CWG1DATbits.CWG1DAT0 // bit 0
10856 #define CWG1DAT1 CWG1DATbits.CWG1DAT1 // bit 1
10857 #define CWG1DAT2 CWG1DATbits.CWG1DAT2 // bit 2
10858 #define CWG1DAT3 CWG1DATbits.CWG1DAT3 // bit 3
10860 #define DBF0 CWG1DBFbits.DBF0 // bit 0, shadows bit in CWG1DBFbits
10861 #define CWG1DBF0 CWG1DBFbits.CWG1DBF0 // bit 0, shadows bit in CWG1DBFbits
10862 #define DBF1 CWG1DBFbits.DBF1 // bit 1, shadows bit in CWG1DBFbits
10863 #define CWG1DBF1 CWG1DBFbits.CWG1DBF1 // bit 1, shadows bit in CWG1DBFbits
10864 #define DBF2 CWG1DBFbits.DBF2 // bit 2, shadows bit in CWG1DBFbits
10865 #define CWG1DBF2 CWG1DBFbits.CWG1DBF2 // bit 2, shadows bit in CWG1DBFbits
10866 #define DBF3 CWG1DBFbits.DBF3 // bit 3, shadows bit in CWG1DBFbits
10867 #define CWG1DBF3 CWG1DBFbits.CWG1DBF3 // bit 3, shadows bit in CWG1DBFbits
10868 #define DBF4 CWG1DBFbits.DBF4 // bit 4, shadows bit in CWG1DBFbits
10869 #define CWG1DBF4 CWG1DBFbits.CWG1DBF4 // bit 4, shadows bit in CWG1DBFbits
10870 #define DBF5 CWG1DBFbits.DBF5 // bit 5, shadows bit in CWG1DBFbits
10871 #define CWG1DBF5 CWG1DBFbits.CWG1DBF5 // bit 5, shadows bit in CWG1DBFbits
10873 #define DBR0 CWG1DBRbits.DBR0 // bit 0, shadows bit in CWG1DBRbits
10874 #define CWG1DBR0 CWG1DBRbits.CWG1DBR0 // bit 0, shadows bit in CWG1DBRbits
10875 #define DBR1 CWG1DBRbits.DBR1 // bit 1, shadows bit in CWG1DBRbits
10876 #define CWG1DBR1 CWG1DBRbits.CWG1DBR1 // bit 1, shadows bit in CWG1DBRbits
10877 #define DBR2 CWG1DBRbits.DBR2 // bit 2, shadows bit in CWG1DBRbits
10878 #define CWG1DBR2 CWG1DBRbits.CWG1DBR2 // bit 2, shadows bit in CWG1DBRbits
10879 #define DBR3 CWG1DBRbits.DBR3 // bit 3, shadows bit in CWG1DBRbits
10880 #define CWG1DBR3 CWG1DBRbits.CWG1DBR3 // bit 3, shadows bit in CWG1DBRbits
10881 #define DBR4 CWG1DBRbits.DBR4 // bit 4, shadows bit in CWG1DBRbits
10882 #define CWG1DBR4 CWG1DBRbits.CWG1DBR4 // bit 4, shadows bit in CWG1DBRbits
10883 #define DBR5 CWG1DBRbits.DBR5 // bit 5, shadows bit in CWG1DBRbits
10884 #define CWG1DBR5 CWG1DBRbits.CWG1DBR5 // bit 5, shadows bit in CWG1DBRbits
10886 #define CWG1PPS0 CWG1PPSbits.CWG1PPS0 // bit 0
10887 #define CWG1PPS1 CWG1PPSbits.CWG1PPS1 // bit 1
10888 #define CWG1PPS2 CWG1PPSbits.CWG1PPS2 // bit 2
10889 #define CWG1PPS3 CWG1PPSbits.CWG1PPS3 // bit 3
10890 #define CWG1PPS4 CWG1PPSbits.CWG1PPS4 // bit 4
10892 #define STRA CWG1STRbits.STRA // bit 0, shadows bit in CWG1STRbits
10893 #define CWG1STRA CWG1STRbits.CWG1STRA // bit 0, shadows bit in CWG1STRbits
10894 #define STRB CWG1STRbits.STRB // bit 1, shadows bit in CWG1STRbits
10895 #define CWG1STRB CWG1STRbits.CWG1STRB // bit 1, shadows bit in CWG1STRbits
10896 #define STRC CWG1STRbits.STRC // bit 2, shadows bit in CWG1STRbits
10897 #define CWG1STRC CWG1STRbits.CWG1STRC // bit 2, shadows bit in CWG1STRbits
10898 #define STRD CWG1STRbits.STRD // bit 3, shadows bit in CWG1STRbits
10899 #define CWG1STRD CWG1STRbits.CWG1STRD // bit 3, shadows bit in CWG1STRbits
10900 #define OVRA CWG1STRbits.OVRA // bit 4, shadows bit in CWG1STRbits
10901 #define CWG1OVRA CWG1STRbits.CWG1OVRA // bit 4, shadows bit in CWG1STRbits
10902 #define OVRB CWG1STRbits.OVRB // bit 5, shadows bit in CWG1STRbits
10903 #define CWG1OVRB CWG1STRbits.CWG1OVRB // bit 5, shadows bit in CWG1STRbits
10904 #define OVRC CWG1STRbits.OVRC // bit 6, shadows bit in CWG1STRbits
10905 #define CWG1OVRC CWG1STRbits.CWG1OVRC // bit 6, shadows bit in CWG1STRbits
10906 #define OVRD CWG1STRbits.OVRD // bit 7, shadows bit in CWG1STRbits
10907 #define CWG1OVRD CWG1STRbits.CWG1OVRD // bit 7, shadows bit in CWG1STRbits
10909 #define CWG2DAT0 CWG2DATbits.CWG2DAT0 // bit 0
10910 #define CWG2DAT1 CWG2DATbits.CWG2DAT1 // bit 1
10911 #define CWG2DAT2 CWG2DATbits.CWG2DAT2 // bit 2
10912 #define CWG2DAT3 CWG2DATbits.CWG2DAT3 // bit 3
10914 #define CWG2PPS0 CWG2PPSbits.CWG2PPS0 // bit 0
10915 #define CWG2PPS1 CWG2PPSbits.CWG2PPS1 // bit 1
10916 #define CWG2PPS2 CWG2PPSbits.CWG2PPS2 // bit 2
10917 #define CWG2PPS3 CWG2PPSbits.CWG2PPS3 // bit 3
10918 #define CWG2PPS4 CWG2PPSbits.CWG2PPS4 // bit 4
10920 #define DAC1NSS DACCON0bits.DAC1NSS // bit 0
10921 #define DAC1PSS0 DACCON0bits.DAC1PSS0 // bit 2
10922 #define DAC1PSS1 DACCON0bits.DAC1PSS1 // bit 3
10923 #define DAC1OE DACCON0bits.DAC1OE // bit 5
10924 #define DAC1EN DACCON0bits.DAC1EN // bit 7
10926 #define DAC1R0 DACCON1bits.DAC1R0 // bit 0
10927 #define DAC1R1 DACCON1bits.DAC1R1 // bit 1
10928 #define DAC1R2 DACCON1bits.DAC1R2 // bit 2
10929 #define DAC1R3 DACCON1bits.DAC1R3 // bit 3
10930 #define DAC1R4 DACCON1bits.DAC1R4 // bit 4
10932 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
10933 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
10934 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
10935 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
10936 #define TSRNG FVRCONbits.TSRNG // bit 4
10937 #define TSEN FVRCONbits.TSEN // bit 5
10938 #define FVRRDY FVRCONbits.FVRRDY // bit 6
10939 #define FVREN FVRCONbits.FVREN // bit 7
10941 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
10942 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
10943 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
10944 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
10945 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
10946 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
10948 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
10949 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
10950 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
10951 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
10952 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
10953 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
10955 #define INTEDG INTCONbits.INTEDG // bit 0
10956 #define PEIE INTCONbits.PEIE // bit 6
10957 #define GIE INTCONbits.GIE // bit 7
10959 #define INTPPS0 INTPPSbits.INTPPS0 // bit 0
10960 #define INTPPS1 INTPPSbits.INTPPS1 // bit 1
10961 #define INTPPS2 INTPPSbits.INTPPS2 // bit 2
10962 #define INTPPS3 INTPPSbits.INTPPS3 // bit 3
10963 #define INTPPS4 INTPPSbits.INTPPS4 // bit 4
10965 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
10966 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
10967 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
10968 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
10969 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
10970 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
10972 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
10973 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
10974 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
10975 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
10976 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
10977 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
10979 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
10980 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
10981 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
10982 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
10983 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
10984 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
10986 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
10987 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
10988 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
10989 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
10990 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
10991 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
10993 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
10994 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
10995 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
10996 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
10997 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
10998 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
11000 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
11001 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
11002 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
11003 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
11004 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
11005 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
11007 #define LATA0 LATAbits.LATA0 // bit 0
11008 #define LATA1 LATAbits.LATA1 // bit 1
11009 #define LATA2 LATAbits.LATA2 // bit 2
11010 #define LATA4 LATAbits.LATA4 // bit 4
11011 #define LATA5 LATAbits.LATA5 // bit 5
11013 #define LATC0 LATCbits.LATC0 // bit 0
11014 #define LATC1 LATCbits.LATC1 // bit 1
11015 #define LATC2 LATCbits.LATC2 // bit 2
11016 #define LATC3 LATCbits.LATC3 // bit 3
11017 #define LATC4 LATCbits.LATC4 // bit 4
11018 #define LATC5 LATCbits.LATC5 // bit 5
11020 #define MDCH0 MDCARHbits.MDCH0 // bit 0
11021 #define MDCH1 MDCARHbits.MDCH1 // bit 1
11022 #define MDCH2 MDCARHbits.MDCH2 // bit 2
11023 #define MDCH3 MDCARHbits.MDCH3 // bit 3
11024 #define MDCHSYNC MDCARHbits.MDCHSYNC // bit 5
11025 #define MDCHPOL MDCARHbits.MDCHPOL // bit 6
11027 #define MDCL0 MDCARLbits.MDCL0 // bit 0
11028 #define MDCL1 MDCARLbits.MDCL1 // bit 1
11029 #define MDCL2 MDCARLbits.MDCL2 // bit 2
11030 #define MDCL3 MDCARLbits.MDCL3 // bit 3
11031 #define MDCLSYNC MDCARLbits.MDCLSYNC // bit 5
11032 #define MDCLPOL MDCARLbits.MDCLPOL // bit 6
11034 #define MDCIN1PPS0 MDCIN1PPSbits.MDCIN1PPS0 // bit 0
11035 #define MDCIN1PPS1 MDCIN1PPSbits.MDCIN1PPS1 // bit 1
11036 #define MDCIN1PPS2 MDCIN1PPSbits.MDCIN1PPS2 // bit 2
11037 #define MDCIN1PPS3 MDCIN1PPSbits.MDCIN1PPS3 // bit 3
11038 #define MDCIN1PPS4 MDCIN1PPSbits.MDCIN1PPS4 // bit 4
11040 #define MDCIN2PPS0 MDCIN2PPSbits.MDCIN2PPS0 // bit 0
11041 #define MDCIN2PPS1 MDCIN2PPSbits.MDCIN2PPS1 // bit 1
11042 #define MDCIN2PPS2 MDCIN2PPSbits.MDCIN2PPS2 // bit 2
11043 #define MDCIN2PPS3 MDCIN2PPSbits.MDCIN2PPS3 // bit 3
11044 #define MDCIN2PPS4 MDCIN2PPSbits.MDCIN2PPS4 // bit 4
11046 #define MDBIT MDCONbits.MDBIT // bit 0
11047 #define MDOUT MDCONbits.MDOUT // bit 3
11048 #define MDOPOL MDCONbits.MDOPOL // bit 4
11049 #define MDEN MDCONbits.MDEN // bit 7
11051 #define MDMINPPS0 MDMINPPSbits.MDMINPPS0 // bit 0
11052 #define MDMINPPS1 MDMINPPSbits.MDMINPPS1 // bit 1
11053 #define MDMINPPS2 MDMINPPSbits.MDMINPPS2 // bit 2
11054 #define MDMINPPS3 MDMINPPSbits.MDMINPPS3 // bit 3
11055 #define MDMINPPS4 MDMINPPSbits.MDMINPPS4 // bit 4
11057 #define MDMS0 MDSRCbits.MDMS0 // bit 0
11058 #define MDMS1 MDSRCbits.MDMS1 // bit 1
11059 #define MDMS2 MDSRCbits.MDMS2 // bit 2
11060 #define MDMS3 MDSRCbits.MDMS3 // bit 3
11062 #define N1PFM NCO1CONbits.N1PFM // bit 0
11063 #define N1POL NCO1CONbits.N1POL // bit 4
11064 #define N1OUT NCO1CONbits.N1OUT // bit 5
11065 #define N1EN NCO1CONbits.N1EN // bit 7
11067 #define NVMADR8 NVMADRHbits.NVMADR8 // bit 0
11068 #define NVMADR9 NVMADRHbits.NVMADR9 // bit 1
11069 #define NVMADR10 NVMADRHbits.NVMADR10 // bit 2
11070 #define NVMADR11 NVMADRHbits.NVMADR11 // bit 3
11071 #define NVMADR12 NVMADRHbits.NVMADR12 // bit 4
11072 #define NVMADR13 NVMADRHbits.NVMADR13 // bit 5
11073 #define NVMADR14 NVMADRHbits.NVMADR14 // bit 6
11075 #define NVMADR0 NVMADRLbits.NVMADR0 // bit 0
11076 #define NVMADR1 NVMADRLbits.NVMADR1 // bit 1
11077 #define NVMADR2 NVMADRLbits.NVMADR2 // bit 2
11078 #define NVMADR3 NVMADRLbits.NVMADR3 // bit 3
11079 #define NVMADR4 NVMADRLbits.NVMADR4 // bit 4
11080 #define NVMADR5 NVMADRLbits.NVMADR5 // bit 5
11081 #define NVMADR6 NVMADRLbits.NVMADR6 // bit 6
11082 #define NVMADR7 NVMADRLbits.NVMADR7 // bit 7
11084 #define RD NVMCON1bits.RD // bit 0
11085 #define WR NVMCON1bits.WR // bit 1
11086 #define WREN NVMCON1bits.WREN // bit 2
11087 #define WRERR NVMCON1bits.WRERR // bit 3
11088 #define FREE NVMCON1bits.FREE // bit 4
11089 #define LWLO NVMCON1bits.LWLO // bit 5
11090 #define NVMREGS NVMCON1bits.NVMREGS // bit 6
11092 #define NVMDAT8 NVMDATHbits.NVMDAT8 // bit 0
11093 #define NVMDAT9 NVMDATHbits.NVMDAT9 // bit 1
11094 #define NVMDAT10 NVMDATHbits.NVMDAT10 // bit 2
11095 #define NVMDAT11 NVMDATHbits.NVMDAT11 // bit 3
11096 #define NVMDAT12 NVMDATHbits.NVMDAT12 // bit 4
11097 #define NVMDAT13 NVMDATHbits.NVMDAT13 // bit 5
11099 #define NVMDAT0 NVMDATLbits.NVMDAT0 // bit 0
11100 #define NVMDAT1 NVMDATLbits.NVMDAT1 // bit 1
11101 #define NVMDAT2 NVMDATLbits.NVMDAT2 // bit 2
11102 #define NVMDAT3 NVMDATLbits.NVMDAT3 // bit 3
11103 #define NVMDAT4 NVMDATLbits.NVMDAT4 // bit 4
11104 #define NVMDAT5 NVMDATLbits.NVMDAT5 // bit 5
11105 #define NVMDAT6 NVMDATLbits.NVMDAT6 // bit 6
11106 #define NVMDAT7 NVMDATLbits.NVMDAT7 // bit 7
11108 #define ODCA0 ODCONAbits.ODCA0 // bit 0
11109 #define ODCA1 ODCONAbits.ODCA1 // bit 1
11110 #define ODCA2 ODCONAbits.ODCA2 // bit 2
11111 #define ODCA4 ODCONAbits.ODCA4 // bit 4
11112 #define ODCA5 ODCONAbits.ODCA5 // bit 5
11114 #define ODCC0 ODCONCbits.ODCC0 // bit 0
11115 #define ODCC1 ODCONCbits.ODCC1 // bit 1
11116 #define ODCC2 ODCONCbits.ODCC2 // bit 2
11117 #define ODCC3 ODCONCbits.ODCC3 // bit 3
11118 #define ODCC4 ODCONCbits.ODCC4 // bit 4
11119 #define ODCC5 ODCONCbits.ODCC5 // bit 5
11121 #define NDIV0 OSCCON1bits.NDIV0 // bit 0
11122 #define NDIV1 OSCCON1bits.NDIV1 // bit 1
11123 #define NDIV2 OSCCON1bits.NDIV2 // bit 2
11124 #define NDIV3 OSCCON1bits.NDIV3 // bit 3
11125 #define NOSC0 OSCCON1bits.NOSC0 // bit 4
11126 #define NOSC1 OSCCON1bits.NOSC1 // bit 5
11127 #define NOSC2 OSCCON1bits.NOSC2 // bit 6
11129 #define CDIV0 OSCCON2bits.CDIV0 // bit 0
11130 #define CDIV1 OSCCON2bits.CDIV1 // bit 1
11131 #define CDIV2 OSCCON2bits.CDIV2 // bit 2
11132 #define CDIV3 OSCCON2bits.CDIV3 // bit 3
11133 #define COSC0 OSCCON2bits.COSC0 // bit 4
11134 #define COSC1 OSCCON2bits.COSC1 // bit 5
11135 #define COSC2 OSCCON2bits.COSC2 // bit 6
11137 #define NOSCR OSCCON3bits.NOSCR // bit 3
11138 #define ORDY OSCCON3bits.ORDY // bit 4
11139 #define SOSCBE OSCCON3bits.SOSCBE // bit 5
11140 #define SOSCPWR OSCCON3bits.SOSCPWR // bit 6
11141 #define CSWHOLD OSCCON3bits.CSWHOLD // bit 7
11143 #define ADOEN OSCENbits.ADOEN // bit 2
11144 #define SOSCEN OSCENbits.SOSCEN // bit 3
11145 #define LFOEN OSCENbits.LFOEN // bit 4
11146 #define HFOEN OSCENbits.HFOEN // bit 6
11147 #define EXTOEN OSCENbits.EXTOEN // bit 7
11149 #define HFFRQ0 OSCFRQbits.HFFRQ0 // bit 0
11150 #define HFFRQ1 OSCFRQbits.HFFRQ1 // bit 1
11151 #define HFFRQ2 OSCFRQbits.HFFRQ2 // bit 2
11152 #define HFFRQ3 OSCFRQbits.HFFRQ3 // bit 3
11154 #define PLLR OSCSTAT1bits.PLLR // bit 0
11155 #define ADOR OSCSTAT1bits.ADOR // bit 2
11156 #define SOR OSCSTAT1bits.SOR // bit 3
11157 #define LFOR OSCSTAT1bits.LFOR // bit 4
11158 #define HFOR OSCSTAT1bits.HFOR // bit 6
11159 #define EXTOR OSCSTAT1bits.EXTOR // bit 7
11161 #define HFTUN0 OSCTUNEbits.HFTUN0 // bit 0
11162 #define HFTUN1 OSCTUNEbits.HFTUN1 // bit 1
11163 #define HFTUN2 OSCTUNEbits.HFTUN2 // bit 2
11164 #define HFTUN3 OSCTUNEbits.HFTUN3 // bit 3
11165 #define HFTUN4 OSCTUNEbits.HFTUN4 // bit 4
11166 #define HFTUN5 OSCTUNEbits.HFTUN5 // bit 5
11168 #define NOT_BOR PCON0bits.NOT_BOR // bit 0
11169 #define NOT_POR PCON0bits.NOT_POR // bit 1
11170 #define NOT_RI PCON0bits.NOT_RI // bit 2
11171 #define NOT_RMCLR PCON0bits.NOT_RMCLR // bit 3
11172 #define NOT_RWDT PCON0bits.NOT_RWDT // bit 4
11173 #define STKUNF PCON0bits.STKUNF // bit 6
11174 #define STKOVF PCON0bits.STKOVF // bit 7
11176 #define INTE PIE0bits.INTE // bit 0
11177 #define IOCIE PIE0bits.IOCIE // bit 4
11178 #define TMR0IE PIE0bits.TMR0IE // bit 5
11180 #define TMR1IE PIE1bits.TMR1IE // bit 0
11181 #define TMR2IE PIE1bits.TMR2IE // bit 1
11182 #define BCL1IE PIE1bits.BCL1IE // bit 2
11183 #define SSP1IE PIE1bits.SSP1IE // bit 3
11184 #define TXIE PIE1bits.TXIE // bit 4
11185 #define RCIE PIE1bits.RCIE // bit 5
11186 #define ADIE PIE1bits.ADIE // bit 6
11187 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
11189 #define NCO1IE PIE2bits.NCO1IE // bit 0
11190 #define TMR4IE PIE2bits.TMR4IE // bit 1
11191 #define BCL2IE PIE2bits.BCL2IE // bit 2
11192 #define SSP2IE PIE2bits.SSP2IE // bit 3
11193 #define NVMIE PIE2bits.NVMIE // bit 4
11194 #define C1IE PIE2bits.C1IE // bit 5
11195 #define C2IE PIE2bits.C2IE // bit 6
11196 #define TMR6IE PIE2bits.TMR6IE // bit 7
11198 #define CLC1IE PIE3bits.CLC1IE // bit 0
11199 #define CLC2IE PIE3bits.CLC2IE // bit 1
11200 #define CLC3IE PIE3bits.CLC3IE // bit 2
11201 #define CLC4IE PIE3bits.CLC4IE // bit 3
11202 #define TMR3IE PIE3bits.TMR3IE // bit 4
11203 #define TMR3GIE PIE3bits.TMR3GIE // bit 5
11204 #define CSWIE PIE3bits.CSWIE // bit 6
11205 #define OSFIE PIE3bits.OSFIE // bit 7
11207 #define CCP1IE PIE4bits.CCP1IE // bit 0
11208 #define CCP2IE PIE4bits.CCP2IE // bit 1
11209 #define CCP3IE PIE4bits.CCP3IE // bit 2
11210 #define CCP4IE PIE4bits.CCP4IE // bit 3
11211 #define TMR5IE PIE4bits.TMR5IE // bit 4
11212 #define TMR5GIE PIE4bits.TMR5GIE // bit 5
11213 #define CWG1IE PIE4bits.CWG1IE // bit 6
11214 #define CWG2IE PIE4bits.CWG2IE // bit 7
11216 #define INTF PIR0bits.INTF // bit 0
11217 #define IOCIF PIR0bits.IOCIF // bit 4
11218 #define TMR0IF PIR0bits.TMR0IF // bit 5
11220 #define TMR1IF PIR1bits.TMR1IF // bit 0
11221 #define TMR2IF PIR1bits.TMR2IF // bit 1
11222 #define BCL1IF PIR1bits.BCL1IF // bit 2
11223 #define SSP1IF PIR1bits.SSP1IF // bit 3
11224 #define TXIF PIR1bits.TXIF // bit 4
11225 #define RCIF PIR1bits.RCIF // bit 5
11226 #define ADIF PIR1bits.ADIF // bit 6
11227 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
11229 #define NCO1IF PIR2bits.NCO1IF // bit 0
11230 #define TMR4IF PIR2bits.TMR4IF // bit 1
11231 #define BCL2IF PIR2bits.BCL2IF // bit 2
11232 #define SSP2IF PIR2bits.SSP2IF // bit 3
11233 #define NVMIF PIR2bits.NVMIF // bit 4
11234 #define C1IF PIR2bits.C1IF // bit 5
11235 #define C2IF PIR2bits.C2IF // bit 6
11236 #define TMR6IF PIR2bits.TMR6IF // bit 7
11238 #define CLC1IF PIR3bits.CLC1IF // bit 0
11239 #define CLC2IF PIR3bits.CLC2IF // bit 1
11240 #define CLC3IF PIR3bits.CLC3IF // bit 2
11241 #define CLC4IF PIR3bits.CLC4IF // bit 3
11242 #define TMR3IF PIR3bits.TMR3IF // bit 4
11243 #define TMR3GIF PIR3bits.TMR3GIF // bit 5
11244 #define CSWIF PIR3bits.CSWIF // bit 6
11245 #define OSFIF PIR3bits.OSFIF // bit 7
11247 #define CCP1IF PIR4bits.CCP1IF // bit 0
11248 #define CCP2IF PIR4bits.CCP2IF // bit 1
11249 #define CCP3IF PIR4bits.CCP3IF // bit 2
11250 #define CCP4IF PIR4bits.CCP4IF // bit 3
11251 #define TMR5IF PIR4bits.TMR5IF // bit 4
11252 #define TMR5GIF PIR4bits.TMR5GIF // bit 5
11253 #define CWG1IF PIR4bits.CWG1IF // bit 6
11254 #define CWG2IF PIR4bits.CWG2IF // bit 7
11256 #define IOCMD PMD0bits.IOCMD // bit 0
11257 #define CLKRMD PMD0bits.CLKRMD // bit 1
11258 #define NVMMD PMD0bits.NVMMD // bit 2
11259 #define FVRMD PMD0bits.FVRMD // bit 6
11260 #define SYSCMD PMD0bits.SYSCMD // bit 7
11262 #define TMR0MD PMD1bits.TMR0MD // bit 0
11263 #define TMR1MD PMD1bits.TMR1MD // bit 1
11264 #define TMR2MD PMD1bits.TMR2MD // bit 2
11265 #define TMR3MD PMD1bits.TMR3MD // bit 3
11266 #define TMR4MD PMD1bits.TMR4MD // bit 4
11267 #define TMR5MD PMD1bits.TMR5MD // bit 5
11268 #define TMR6MD PMD1bits.TMR6MD // bit 6
11269 #define NCOMD PMD1bits.NCOMD // bit 7
11271 #define CMP1MD PMD2bits.CMP1MD // bit 1
11272 #define CMP2MD PMD2bits.CMP2MD // bit 2
11273 #define ADCMD PMD2bits.ADCMD // bit 5
11274 #define DACMD PMD2bits.DACMD // bit 6
11276 #define CCP1MD PMD3bits.CCP1MD // bit 0
11277 #define CCP2MD PMD3bits.CCP2MD // bit 1
11278 #define CCP3MD PMD3bits.CCP3MD // bit 2
11279 #define CCP4MD PMD3bits.CCP4MD // bit 3
11280 #define PWM5MD PMD3bits.PWM5MD // bit 4
11281 #define PWM6MD PMD3bits.PWM6MD // bit 5
11282 #define CWG1MD PMD3bits.CWG1MD // bit 6
11283 #define CWG2MD PMD3bits.CWG2MD // bit 7
11285 #define MSSP1MD PMD4bits.MSSP1MD // bit 1
11286 #define MSSP2MD PMD4bits.MSSP2MD // bit 2
11287 #define UART1MD PMD4bits.UART1MD // bit 5
11289 #define DSMMD PMD5bits.DSMMD // bit 0
11290 #define CLC1MD PMD5bits.CLC1MD // bit 1
11291 #define CLC2MD PMD5bits.CLC2MD // bit 2
11292 #define CLC3MD PMD5bits.CLC3MD // bit 3
11293 #define CLC4MD PMD5bits.CLC4MD // bit 4
11295 #define RA0 PORTAbits.RA0 // bit 0
11296 #define RA1 PORTAbits.RA1 // bit 1
11297 #define RA2 PORTAbits.RA2 // bit 2
11298 #define RA3 PORTAbits.RA3 // bit 3
11299 #define RA4 PORTAbits.RA4 // bit 4
11300 #define RA5 PORTAbits.RA5 // bit 5
11302 #define RC0 PORTCbits.RC0 // bit 0
11303 #define RC1 PORTCbits.RC1 // bit 1
11304 #define RC2 PORTCbits.RC2 // bit 2
11305 #define RC3 PORTCbits.RC3 // bit 3
11306 #define RC4 PORTCbits.RC4 // bit 4
11307 #define RC5 PORTCbits.RC5 // bit 5
11309 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
11311 #define PWM5POL PWM5CONbits.PWM5POL // bit 4
11312 #define PWM5OUT PWM5CONbits.PWM5OUT // bit 5
11313 #define PWM5EN PWM5CONbits.PWM5EN // bit 7
11315 #define PWM5DCH0 PWM5DCHbits.PWM5DCH0 // bit 0
11316 #define PWM5DCH1 PWM5DCHbits.PWM5DCH1 // bit 1
11317 #define PWM5DCH2 PWM5DCHbits.PWM5DCH2 // bit 2
11318 #define PWM5DCH3 PWM5DCHbits.PWM5DCH3 // bit 3
11319 #define PWM5DCH4 PWM5DCHbits.PWM5DCH4 // bit 4
11320 #define PWM5DCH5 PWM5DCHbits.PWM5DCH5 // bit 5
11321 #define PWM5DCH6 PWM5DCHbits.PWM5DCH6 // bit 6
11322 #define PWM5DCH7 PWM5DCHbits.PWM5DCH7 // bit 7
11324 #define PWM5DCL0 PWM5DCLbits.PWM5DCL0 // bit 6
11325 #define PWM5DCL1 PWM5DCLbits.PWM5DCL1 // bit 7
11327 #define PWM6POL PWM6CONbits.PWM6POL // bit 4
11328 #define PWM6OUT PWM6CONbits.PWM6OUT // bit 5
11329 #define PWM6EN PWM6CONbits.PWM6EN // bit 7
11331 #define PWM6DCH0 PWM6DCHbits.PWM6DCH0 // bit 0
11332 #define PWM6DCH1 PWM6DCHbits.PWM6DCH1 // bit 1
11333 #define PWM6DCH2 PWM6DCHbits.PWM6DCH2 // bit 2
11334 #define PWM6DCH3 PWM6DCHbits.PWM6DCH3 // bit 3
11335 #define PWM6DCH4 PWM6DCHbits.PWM6DCH4 // bit 4
11336 #define PWM6DCH5 PWM6DCHbits.PWM6DCH5 // bit 5
11337 #define PWM6DCH6 PWM6DCHbits.PWM6DCH6 // bit 6
11338 #define PWM6DCH7 PWM6DCHbits.PWM6DCH7 // bit 7
11340 #define PWM6DCL0 PWM6DCLbits.PWM6DCL0 // bit 6
11341 #define PWM6DCL1 PWM6DCLbits.PWM6DCL1 // bit 7
11343 #define P5TSEL0 PWMTMRSbits.P5TSEL0 // bit 0
11344 #define P5TSEL1 PWMTMRSbits.P5TSEL1 // bit 1
11345 #define P6TSEL0 PWMTMRSbits.P6TSEL0 // bit 2
11346 #define P6TSEL1 PWMTMRSbits.P6TSEL1 // bit 3
11348 #define RA0PPS0 RA0PPSbits.RA0PPS0 // bit 0
11349 #define RA0PPS1 RA0PPSbits.RA0PPS1 // bit 1
11350 #define RA0PPS2 RA0PPSbits.RA0PPS2 // bit 2
11351 #define RA0PPS3 RA0PPSbits.RA0PPS3 // bit 3
11352 #define RA0PPS4 RA0PPSbits.RA0PPS4 // bit 4
11354 #define RA1PPS0 RA1PPSbits.RA1PPS0 // bit 0
11355 #define RA1PPS1 RA1PPSbits.RA1PPS1 // bit 1
11356 #define RA1PPS2 RA1PPSbits.RA1PPS2 // bit 2
11357 #define RA1PPS3 RA1PPSbits.RA1PPS3 // bit 3
11358 #define RA1PPS4 RA1PPSbits.RA1PPS4 // bit 4
11360 #define RA2PPS0 RA2PPSbits.RA2PPS0 // bit 0
11361 #define RA2PPS1 RA2PPSbits.RA2PPS1 // bit 1
11362 #define RA2PPS2 RA2PPSbits.RA2PPS2 // bit 2
11363 #define RA2PPS3 RA2PPSbits.RA2PPS3 // bit 3
11364 #define RA2PPS4 RA2PPSbits.RA2PPS4 // bit 4
11366 #define RA4PPS0 RA4PPSbits.RA4PPS0 // bit 0
11367 #define RA4PPS1 RA4PPSbits.RA4PPS1 // bit 1
11368 #define RA4PPS2 RA4PPSbits.RA4PPS2 // bit 2
11369 #define RA4PPS3 RA4PPSbits.RA4PPS3 // bit 3
11370 #define RA4PPS4 RA4PPSbits.RA4PPS4 // bit 4
11372 #define RA5PPS0 RA5PPSbits.RA5PPS0 // bit 0
11373 #define RA5PPS1 RA5PPSbits.RA5PPS1 // bit 1
11374 #define RA5PPS2 RA5PPSbits.RA5PPS2 // bit 2
11375 #define RA5PPS3 RA5PPSbits.RA5PPS3 // bit 3
11376 #define RA5PPS4 RA5PPSbits.RA5PPS4 // bit 4
11378 #define RC0PPS0 RC0PPSbits.RC0PPS0 // bit 0
11379 #define RC0PPS1 RC0PPSbits.RC0PPS1 // bit 1
11380 #define RC0PPS2 RC0PPSbits.RC0PPS2 // bit 2
11381 #define RC0PPS3 RC0PPSbits.RC0PPS3 // bit 3
11382 #define RC0PPS4 RC0PPSbits.RC0PPS4 // bit 4
11384 #define RC1PPS0 RC1PPSbits.RC1PPS0 // bit 0
11385 #define RC1PPS1 RC1PPSbits.RC1PPS1 // bit 1
11386 #define RC1PPS2 RC1PPSbits.RC1PPS2 // bit 2
11387 #define RC1PPS3 RC1PPSbits.RC1PPS3 // bit 3
11388 #define RC1PPS4 RC1PPSbits.RC1PPS4 // bit 4
11390 #define RX9D RC1STAbits.RX9D // bit 0
11391 #define OERR RC1STAbits.OERR // bit 1
11392 #define FERR RC1STAbits.FERR // bit 2
11393 #define ADDEN RC1STAbits.ADDEN // bit 3
11394 #define CREN RC1STAbits.CREN // bit 4
11395 #define SREN RC1STAbits.SREN // bit 5
11396 #define RX9 RC1STAbits.RX9 // bit 6
11397 #define SPEN RC1STAbits.SPEN // bit 7
11399 #define RC2PPS0 RC2PPSbits.RC2PPS0 // bit 0
11400 #define RC2PPS1 RC2PPSbits.RC2PPS1 // bit 1
11401 #define RC2PPS2 RC2PPSbits.RC2PPS2 // bit 2
11402 #define RC2PPS3 RC2PPSbits.RC2PPS3 // bit 3
11403 #define RC2PPS4 RC2PPSbits.RC2PPS4 // bit 4
11405 #define RC3PPS0 RC3PPSbits.RC3PPS0 // bit 0
11406 #define RC3PPS1 RC3PPSbits.RC3PPS1 // bit 1
11407 #define RC3PPS2 RC3PPSbits.RC3PPS2 // bit 2
11408 #define RC3PPS3 RC3PPSbits.RC3PPS3 // bit 3
11409 #define RC3PPS4 RC3PPSbits.RC3PPS4 // bit 4
11411 #define RC4PPS0 RC4PPSbits.RC4PPS0 // bit 0
11412 #define RC4PPS1 RC4PPSbits.RC4PPS1 // bit 1
11413 #define RC4PPS2 RC4PPSbits.RC4PPS2 // bit 2
11414 #define RC4PPS3 RC4PPSbits.RC4PPS3 // bit 3
11415 #define RC4PPS4 RC4PPSbits.RC4PPS4 // bit 4
11417 #define RC5PPS0 RC5PPSbits.RC5PPS0 // bit 0
11418 #define RC5PPS1 RC5PPSbits.RC5PPS1 // bit 1
11419 #define RC5PPS2 RC5PPSbits.RC5PPS2 // bit 2
11420 #define RC5PPS3 RC5PPSbits.RC5PPS3 // bit 3
11421 #define RC5PPS4 RC5PPSbits.RC5PPS4 // bit 4
11423 #define RXDTPPS0 RXPPSbits.RXDTPPS0 // bit 0
11424 #define RXDTPPS1 RXPPSbits.RXDTPPS1 // bit 1
11425 #define RXDTPPS2 RXPPSbits.RXDTPPS2 // bit 2
11426 #define RXDTPPS3 RXPPSbits.RXDTPPS3 // bit 3
11427 #define RXDTPPS4 RXPPSbits.RXDTPPS4 // bit 4
11429 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
11430 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
11431 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
11432 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
11433 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
11435 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
11436 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
11437 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
11438 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
11439 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
11440 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
11442 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
11443 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
11444 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
11445 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
11446 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
11447 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
11448 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
11449 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
11450 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
11451 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
11452 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
11453 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
11454 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
11455 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
11456 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
11457 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
11459 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
11460 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
11461 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
11462 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
11463 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
11464 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
11465 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
11466 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
11467 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
11468 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
11469 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
11470 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
11471 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
11472 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
11473 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
11474 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
11476 #define SSP1CLKPPS0 SSP1CLKPPSbits.SSP1CLKPPS0 // bit 0
11477 #define SSP1CLKPPS1 SSP1CLKPPSbits.SSP1CLKPPS1 // bit 1
11478 #define SSP1CLKPPS2 SSP1CLKPPSbits.SSP1CLKPPS2 // bit 2
11479 #define SSP1CLKPPS3 SSP1CLKPPSbits.SSP1CLKPPS3 // bit 3
11480 #define SSP1CLKPPS4 SSP1CLKPPSbits.SSP1CLKPPS4 // bit 4
11482 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
11483 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
11484 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
11485 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
11486 #define CKP SSP1CONbits.CKP // bit 4
11487 #define SSPEN SSP1CONbits.SSPEN // bit 5
11488 #define SSPOV SSP1CONbits.SSPOV // bit 6
11489 #define WCOL SSP1CONbits.WCOL // bit 7
11491 #define SEN SSP1CON2bits.SEN // bit 0
11492 #define RSEN SSP1CON2bits.RSEN // bit 1
11493 #define PEN SSP1CON2bits.PEN // bit 2
11494 #define RCEN SSP1CON2bits.RCEN // bit 3
11495 #define ACKEN SSP1CON2bits.ACKEN // bit 4
11496 #define ACKDT SSP1CON2bits.ACKDT // bit 5
11497 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
11498 #define GCEN SSP1CON2bits.GCEN // bit 7
11500 #define DHEN SSP1CON3bits.DHEN // bit 0
11501 #define AHEN SSP1CON3bits.AHEN // bit 1
11502 #define SBCDE SSP1CON3bits.SBCDE // bit 2
11503 #define SDAHT SSP1CON3bits.SDAHT // bit 3
11504 #define BOEN SSP1CON3bits.BOEN // bit 4
11505 #define SCIE SSP1CON3bits.SCIE // bit 5
11506 #define PCIE SSP1CON3bits.PCIE // bit 6
11507 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
11509 #define SSP1DATPPS0 SSP1DATPPSbits.SSP1DATPPS0 // bit 0
11510 #define SSP1DATPPS1 SSP1DATPPSbits.SSP1DATPPS1 // bit 1
11511 #define SSP1DATPPS2 SSP1DATPPSbits.SSP1DATPPS2 // bit 2
11512 #define SSP1DATPPS3 SSP1DATPPSbits.SSP1DATPPS3 // bit 3
11513 #define SSP1DATPPS4 SSP1DATPPSbits.SSP1DATPPS4 // bit 4
11515 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
11516 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
11517 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
11518 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
11519 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
11520 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
11521 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
11522 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
11523 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
11524 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
11525 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
11526 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
11527 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
11528 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
11529 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
11530 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
11532 #define SSP1SSPPS0 SSP1SSPPSbits.SSP1SSPPS0 // bit 0
11533 #define SSP1SSPPS1 SSP1SSPPSbits.SSP1SSPPS1 // bit 1
11534 #define SSP1SSPPS2 SSP1SSPPSbits.SSP1SSPPS2 // bit 2
11535 #define SSP1SSPPS3 SSP1SSPPSbits.SSP1SSPPS3 // bit 3
11536 #define SSP1SSPPS4 SSP1SSPPSbits.SSP1SSPPS4 // bit 4
11538 #define BF SSP1STATbits.BF // bit 0
11539 #define UA SSP1STATbits.UA // bit 1
11540 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
11541 #define S SSP1STATbits.S // bit 3
11542 #define P SSP1STATbits.P // bit 4
11543 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
11544 #define CKE SSP1STATbits.CKE // bit 6
11545 #define SMP SSP1STATbits.SMP // bit 7
11547 #define SSP2CLKPPS0 SSP2CLKPPSbits.SSP2CLKPPS0 // bit 0
11548 #define SSP2CLKPPS1 SSP2CLKPPSbits.SSP2CLKPPS1 // bit 1
11549 #define SSP2CLKPPS2 SSP2CLKPPSbits.SSP2CLKPPS2 // bit 2
11550 #define SSP2CLKPPS3 SSP2CLKPPSbits.SSP2CLKPPS3 // bit 3
11551 #define SSP2CLKPPS4 SSP2CLKPPSbits.SSP2CLKPPS4 // bit 4
11553 #define SSP2DATPPS0 SSP2DATPPSbits.SSP2DATPPS0 // bit 0
11554 #define SSP2DATPPS1 SSP2DATPPSbits.SSP2DATPPS1 // bit 1
11555 #define SSP2DATPPS2 SSP2DATPPSbits.SSP2DATPPS2 // bit 2
11556 #define SSP2DATPPS3 SSP2DATPPSbits.SSP2DATPPS3 // bit 3
11557 #define SSP2DATPPS4 SSP2DATPPSbits.SSP2DATPPS4 // bit 4
11559 #define SSP2SSPPS0 SSP2SSPPSbits.SSP2SSPPS0 // bit 0
11560 #define SSP2SSPPS1 SSP2SSPPSbits.SSP2SSPPS1 // bit 1
11561 #define SSP2SSPPS2 SSP2SSPPSbits.SSP2SSPPS2 // bit 2
11562 #define SSP2SSPPS3 SSP2SSPPSbits.SSP2SSPPS3 // bit 3
11563 #define SSP2SSPPS4 SSP2SSPPSbits.SSP2SSPPS4 // bit 4
11565 #define C STATUSbits.C // bit 0
11566 #define DC STATUSbits.DC // bit 1
11567 #define Z STATUSbits.Z // bit 2
11568 #define NOT_PD STATUSbits.NOT_PD // bit 3
11569 #define NOT_TO STATUSbits.NOT_TO // bit 4
11571 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
11572 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
11573 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
11575 #define T0CKIPPS0 T0CKIPPSbits.T0CKIPPS0 // bit 0
11576 #define T0CKIPPS1 T0CKIPPSbits.T0CKIPPS1 // bit 1
11577 #define T0CKIPPS2 T0CKIPPSbits.T0CKIPPS2 // bit 2
11578 #define T0CKIPPS3 T0CKIPPSbits.T0CKIPPS3 // bit 3
11579 #define T0CKIPPS4 T0CKIPPSbits.T0CKIPPS4 // bit 4
11581 #define T0OUTPS0 T0CON0bits.T0OUTPS0 // bit 0
11582 #define T0OUTPS1 T0CON0bits.T0OUTPS1 // bit 1
11583 #define T0OUTPS2 T0CON0bits.T0OUTPS2 // bit 2
11584 #define T0OUTPS3 T0CON0bits.T0OUTPS3 // bit 3
11585 #define T016BIT T0CON0bits.T016BIT // bit 4
11586 #define T0OUT T0CON0bits.T0OUT // bit 5
11587 #define T0EN T0CON0bits.T0EN // bit 7
11589 #define T0CKPS0 T0CON1bits.T0CKPS0 // bit 0
11590 #define T0CKPS1 T0CON1bits.T0CKPS1 // bit 1
11591 #define T0CKPS2 T0CON1bits.T0CKPS2 // bit 2
11592 #define T0CKPS3 T0CON1bits.T0CKPS3 // bit 3
11593 #define T0ASYNC T0CON1bits.T0ASYNC // bit 4
11594 #define T0CS0 T0CON1bits.T0CS0 // bit 5
11595 #define T0CS1 T0CON1bits.T0CS1 // bit 6
11596 #define T0CS2 T0CON1bits.T0CS2 // bit 7
11598 #define T1CKIPPS0 T1CKIPPSbits.T1CKIPPS0 // bit 0
11599 #define T1CKIPPS1 T1CKIPPSbits.T1CKIPPS1 // bit 1
11600 #define T1CKIPPS2 T1CKIPPSbits.T1CKIPPS2 // bit 2
11601 #define T1CKIPPS3 T1CKIPPSbits.T1CKIPPS3 // bit 3
11602 #define T1CKIPPS4 T1CKIPPSbits.T1CKIPPS4 // bit 4
11604 #define TMR1ON T1CONbits.TMR1ON // bit 0
11605 #define T1SYNC T1CONbits.T1SYNC // bit 2
11606 #define T1SOSC T1CONbits.T1SOSC // bit 3
11607 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
11608 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
11609 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
11610 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
11612 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
11613 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
11614 #define T1GVAL T1GCONbits.T1GVAL // bit 2
11615 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3
11616 #define T1GSPM T1GCONbits.T1GSPM // bit 4
11617 #define T1GTM T1GCONbits.T1GTM // bit 5
11618 #define T1GPOL T1GCONbits.T1GPOL // bit 6
11619 #define TMR1GE T1GCONbits.TMR1GE // bit 7
11621 #define T1GPPS0 T1GPPSbits.T1GPPS0 // bit 0
11622 #define T1GPPS1 T1GPPSbits.T1GPPS1 // bit 1
11623 #define T1GPPS2 T1GPPSbits.T1GPPS2 // bit 2
11624 #define T1GPPS3 T1GPPSbits.T1GPPS3 // bit 3
11625 #define T1GPPS4 T1GPPSbits.T1GPPS4 // bit 4
11627 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
11628 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
11629 #define TMR2ON T2CONbits.TMR2ON // bit 2
11630 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
11631 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
11632 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
11633 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
11635 #define TMR3ON T3CONbits.TMR3ON // bit 0
11636 #define T3SYNC T3CONbits.T3SYNC // bit 2
11637 #define T3SOSC T3CONbits.T3SOSC // bit 3
11638 #define T3CKPS0 T3CONbits.T3CKPS0 // bit 4
11639 #define T3CKPS1 T3CONbits.T3CKPS1 // bit 5
11640 #define TMR3CS0 T3CONbits.TMR3CS0 // bit 6
11641 #define TMR3CS1 T3CONbits.TMR3CS1 // bit 7
11643 #define T3GSS0 T3GCONbits.T3GSS0 // bit 0
11644 #define T3GSS1 T3GCONbits.T3GSS1 // bit 1
11645 #define T3GVAL T3GCONbits.T3GVAL // bit 2
11646 #define T3GGO_NOT_DONE T3GCONbits.T3GGO_NOT_DONE // bit 3
11647 #define T3GSPM T3GCONbits.T3GSPM // bit 4
11648 #define T3GTM T3GCONbits.T3GTM // bit 5
11649 #define T3GPOL T3GCONbits.T3GPOL // bit 6
11650 #define TMR3GE T3GCONbits.TMR3GE // bit 7
11652 #define T4CKPS0 T4CONbits.T4CKPS0 // bit 0
11653 #define T4CKPS1 T4CONbits.T4CKPS1 // bit 1
11654 #define TMR4ON T4CONbits.TMR4ON // bit 2
11655 #define T4OUTPS0 T4CONbits.T4OUTPS0 // bit 3
11656 #define T4OUTPS1 T4CONbits.T4OUTPS1 // bit 4
11657 #define T4OUTPS2 T4CONbits.T4OUTPS2 // bit 5
11658 #define T4OUTPS3 T4CONbits.T4OUTPS3 // bit 6
11660 #define TMR5ON T5CONbits.TMR5ON // bit 0
11661 #define T5SYNC T5CONbits.T5SYNC // bit 2
11662 #define T5SOSC T5CONbits.T5SOSC // bit 3
11663 #define T5CKPS0 T5CONbits.T5CKPS0 // bit 4
11664 #define T5CKPS1 T5CONbits.T5CKPS1 // bit 5
11665 #define TMR5CS0 T5CONbits.TMR5CS0 // bit 6
11666 #define TMR5CS1 T5CONbits.TMR5CS1 // bit 7
11668 #define T5GSS0 T5GCONbits.T5GSS0 // bit 0
11669 #define T5GSS1 T5GCONbits.T5GSS1 // bit 1
11670 #define T5GVAL T5GCONbits.T5GVAL // bit 2
11671 #define T5GGO_NOT_DONE T5GCONbits.T5GGO_NOT_DONE // bit 3
11672 #define T5GSPM T5GCONbits.T5GSPM // bit 4
11673 #define T5GTM T5GCONbits.T5GTM // bit 5
11674 #define T5GPOL T5GCONbits.T5GPOL // bit 6
11675 #define TMR5GE T5GCONbits.TMR5GE // bit 7
11677 #define T6CKPS0 T6CONbits.T6CKPS0 // bit 0
11678 #define T6CKPS1 T6CONbits.T6CKPS1 // bit 1
11679 #define TMR6ON T6CONbits.TMR6ON // bit 2
11680 #define T6OUTPS0 T6CONbits.T6OUTPS0 // bit 3
11681 #define T6OUTPS1 T6CONbits.T6OUTPS1 // bit 4
11682 #define T6OUTPS2 T6CONbits.T6OUTPS2 // bit 5
11683 #define T6OUTPS3 T6CONbits.T6OUTPS3 // bit 6
11685 #define TMR08 TMR0Hbits.TMR08 // bit 0
11686 #define TMR09 TMR0Hbits.TMR09 // bit 1
11687 #define TMR010 TMR0Hbits.TMR010 // bit 2
11688 #define TMR011 TMR0Hbits.TMR011 // bit 3
11689 #define TMR012 TMR0Hbits.TMR012 // bit 4
11690 #define TMR013 TMR0Hbits.TMR013 // bit 5
11691 #define TMR014 TMR0Hbits.TMR014 // bit 6
11692 #define TMR015 TMR0Hbits.TMR015 // bit 7
11694 #define TMR00 TMR0Lbits.TMR00 // bit 0
11695 #define TMR01 TMR0Lbits.TMR01 // bit 1
11696 #define TMR02 TMR0Lbits.TMR02 // bit 2
11697 #define TMR03 TMR0Lbits.TMR03 // bit 3
11698 #define TMR04 TMR0Lbits.TMR04 // bit 4
11699 #define TMR05 TMR0Lbits.TMR05 // bit 5
11700 #define TMR06 TMR0Lbits.TMR06 // bit 6
11701 #define TMR07 TMR0Lbits.TMR07 // bit 7
11703 #define TRISA0 TRISAbits.TRISA0 // bit 0
11704 #define TRISA1 TRISAbits.TRISA1 // bit 1
11705 #define TRISA2 TRISAbits.TRISA2 // bit 2
11706 #define TRISA4 TRISAbits.TRISA4 // bit 4
11707 #define TRISA5 TRISAbits.TRISA5 // bit 5
11709 #define TRISC0 TRISCbits.TRISC0 // bit 0
11710 #define TRISC1 TRISCbits.TRISC1 // bit 1
11711 #define TRISC2 TRISCbits.TRISC2 // bit 2
11712 #define TRISC3 TRISCbits.TRISC3 // bit 3
11713 #define TRISC4 TRISCbits.TRISC4 // bit 4
11714 #define TRISC5 TRISCbits.TRISC5 // bit 5
11716 #define TX9D TX1STAbits.TX9D // bit 0
11717 #define TRMT TX1STAbits.TRMT // bit 1
11718 #define BRGH TX1STAbits.BRGH // bit 2
11719 #define SENDB TX1STAbits.SENDB // bit 3
11720 #define SYNC TX1STAbits.SYNC // bit 4
11721 #define TXEN TX1STAbits.TXEN // bit 5
11722 #define TX9 TX1STAbits.TX9 // bit 6
11723 #define CSRC TX1STAbits.CSRC // bit 7
11725 #define TXCKPPS0 TXPPSbits.TXCKPPS0 // bit 0
11726 #define TXCKPPS1 TXPPSbits.TXCKPPS1 // bit 1
11727 #define TXCKPPS2 TXPPSbits.TXCKPPS2 // bit 2
11728 #define TXCKPPS3 TXPPSbits.TXCKPPS3 // bit 3
11729 #define TXCKPPS4 TXPPSbits.TXCKPPS4 // bit 4
11731 #define VREGPM VREGCONbits.VREGPM // bit 1
11733 #define SWDTEN WDTCONbits.SWDTEN // bit 0
11734 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
11735 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
11736 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
11737 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
11738 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
11740 #define WPUA0 WPUAbits.WPUA0 // bit 0
11741 #define WPUA1 WPUAbits.WPUA1 // bit 1
11742 #define WPUA2 WPUAbits.WPUA2 // bit 2
11743 #define WPUA3 WPUAbits.WPUA3 // bit 3
11744 #define WPUA4 WPUAbits.WPUA4 // bit 4
11745 #define WPUA5 WPUAbits.WPUA5 // bit 5
11747 #define WPUC0 WPUCbits.WPUC0 // bit 0
11748 #define WPUC1 WPUCbits.WPUC1 // bit 1
11749 #define WPUC2 WPUCbits.WPUC2 // bit 2
11750 #define WPUC3 WPUCbits.WPUC3 // bit 3
11751 #define WPUC4 WPUCbits.WPUC4 // bit 4
11752 #define WPUC5 WPUCbits.WPUC5 // bit 5
11754 #endif // #ifndef NO_BIT_DEFINES
11756 #endif // #ifndef __PIC16F18325_H__