2 * This declarations of the PIC16F18344 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:24 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F18344_H__
26 #define __PIC16F18344_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTB_ADDR 0x000D
52 #define PORTC_ADDR 0x000E
53 #define PIR0_ADDR 0x0010
54 #define PIR1_ADDR 0x0011
55 #define PIR2_ADDR 0x0012
56 #define PIR3_ADDR 0x0013
57 #define PIR4_ADDR 0x0014
58 #define TMR0L_ADDR 0x0015
59 #define TMR0H_ADDR 0x0016
60 #define T0CON0_ADDR 0x0017
61 #define T0CON1_ADDR 0x0018
62 #define TMR1_ADDR 0x0019
63 #define TMR1L_ADDR 0x0019
64 #define TMR1H_ADDR 0x001A
65 #define T1CON_ADDR 0x001B
66 #define T1GCON_ADDR 0x001C
67 #define TMR2_ADDR 0x001D
68 #define PR2_ADDR 0x001E
69 #define T2CON_ADDR 0x001F
70 #define TRISA_ADDR 0x008C
71 #define TRISB_ADDR 0x008D
72 #define TRISC_ADDR 0x008E
73 #define PIE0_ADDR 0x0090
74 #define PIE1_ADDR 0x0091
75 #define PIE2_ADDR 0x0092
76 #define PIE3_ADDR 0x0093
77 #define PIE4_ADDR 0x0094
78 #define WDTCON_ADDR 0x0097
79 #define ADRES_ADDR 0x009B
80 #define ADRESL_ADDR 0x009B
81 #define ADRESH_ADDR 0x009C
82 #define ADCON0_ADDR 0x009D
83 #define ADCON1_ADDR 0x009E
84 #define ADACT_ADDR 0x009F
85 #define LATA_ADDR 0x010C
86 #define LATB_ADDR 0x010D
87 #define LATC_ADDR 0x010E
88 #define CM1CON0_ADDR 0x0111
89 #define CM1CON1_ADDR 0x0112
90 #define CM2CON0_ADDR 0x0113
91 #define CM2CON1_ADDR 0x0114
92 #define CMOUT_ADDR 0x0115
93 #define BORCON_ADDR 0x0116
94 #define FVRCON_ADDR 0x0117
95 #define DACCON0_ADDR 0x0118
96 #define DACCON1_ADDR 0x0119
97 #define ANSELA_ADDR 0x018C
98 #define ANSELB_ADDR 0x018D
99 #define ANSELC_ADDR 0x018E
100 #define VREGCON_ADDR 0x0197
101 #define RC1REG_ADDR 0x0199
102 #define RCREG_ADDR 0x0199
103 #define RCREG1_ADDR 0x0199
104 #define TX1REG_ADDR 0x019A
105 #define TXREG_ADDR 0x019A
106 #define TXREG1_ADDR 0x019A
107 #define SP1BRG_ADDR 0x019B
108 #define SP1BRGL_ADDR 0x019B
109 #define SPBRG_ADDR 0x019B
110 #define SPBRG1_ADDR 0x019B
111 #define SPBRGL_ADDR 0x019B
112 #define SP1BRGH_ADDR 0x019C
113 #define SPBRGH_ADDR 0x019C
114 #define SPBRGH1_ADDR 0x019C
115 #define RC1STA_ADDR 0x019D
116 #define RCSTA_ADDR 0x019D
117 #define RCSTA1_ADDR 0x019D
118 #define TX1STA_ADDR 0x019E
119 #define TXSTA_ADDR 0x019E
120 #define TXSTA1_ADDR 0x019E
121 #define BAUD1CON_ADDR 0x019F
122 #define BAUDCON_ADDR 0x019F
123 #define BAUDCON1_ADDR 0x019F
124 #define BAUDCTL_ADDR 0x019F
125 #define BAUDCTL1_ADDR 0x019F
126 #define WPUA_ADDR 0x020C
127 #define WPUB_ADDR 0x020D
128 #define WPUC_ADDR 0x020E
129 #define SSP1BUF_ADDR 0x0211
130 #define SSPBUF_ADDR 0x0211
131 #define SSP1ADD_ADDR 0x0212
132 #define SSPADD_ADDR 0x0212
133 #define SSP1MSK_ADDR 0x0213
134 #define SSPMSK_ADDR 0x0213
135 #define SSP1STAT_ADDR 0x0214
136 #define SSPSTAT_ADDR 0x0214
137 #define SSP1CON_ADDR 0x0215
138 #define SSP1CON1_ADDR 0x0215
139 #define SSPCON_ADDR 0x0215
140 #define SSPCON1_ADDR 0x0215
141 #define SSP1CON2_ADDR 0x0216
142 #define SSPCON2_ADDR 0x0216
143 #define SSP1CON3_ADDR 0x0217
144 #define SSPCON3_ADDR 0x0217
145 #define ODCONA_ADDR 0x028C
146 #define ODCONB_ADDR 0x028D
147 #define ODCONC_ADDR 0x028E
148 #define CCPR1_ADDR 0x0291
149 #define CCPR1L_ADDR 0x0291
150 #define CCPR1H_ADDR 0x0292
151 #define CCP1CON_ADDR 0x0293
152 #define CCP1CAP_ADDR 0x0294
153 #define CCPR2_ADDR 0x0295
154 #define CCPR2L_ADDR 0x0295
155 #define CCPR2H_ADDR 0x0296
156 #define CCP2CON_ADDR 0x0297
157 #define CCP2CAP_ADDR 0x0298
158 #define CCPTMRS_ADDR 0x029F
159 #define SLRCONA_ADDR 0x030C
160 #define SLRCONB_ADDR 0x030D
161 #define SLRCONC_ADDR 0x030E
162 #define CCPR3_ADDR 0x0311
163 #define CCPR3L_ADDR 0x0311
164 #define CCPR3H_ADDR 0x0312
165 #define CCP3CON_ADDR 0x0313
166 #define CCP3CAP_ADDR 0x0314
167 #define CCPR4_ADDR 0x0315
168 #define CCPR4L_ADDR 0x0315
169 #define CCPR4H_ADDR 0x0316
170 #define CCP4CON_ADDR 0x0317
171 #define CCP4CAP_ADDR 0x0318
172 #define INLVLA_ADDR 0x038C
173 #define INLVLB_ADDR 0x038D
174 #define INLVLC_ADDR 0x038E
175 #define IOCAP_ADDR 0x0391
176 #define IOCAN_ADDR 0x0392
177 #define IOCAF_ADDR 0x0393
178 #define IOCBP_ADDR 0x0394
179 #define IOCBN_ADDR 0x0395
180 #define IOCBF_ADDR 0x0396
181 #define IOCCP_ADDR 0x0397
182 #define IOCCN_ADDR 0x0398
183 #define IOCCF_ADDR 0x0399
184 #define CLKRCON_ADDR 0x039A
185 #define MDCON_ADDR 0x039C
186 #define MDSRC_ADDR 0x039D
187 #define MDCARH_ADDR 0x039E
188 #define MDCARL_ADDR 0x039F
189 #define CCDNA_ADDR 0x040C
190 #define CCDNB_ADDR 0x040D
191 #define CCDNC_ADDR 0x040E
192 #define TMR3_ADDR 0x0411
193 #define TMR3L_ADDR 0x0411
194 #define TMR3H_ADDR 0x0412
195 #define T3CON_ADDR 0x0413
196 #define T3GCON_ADDR 0x0414
197 #define TMR4_ADDR 0x0415
198 #define PR4_ADDR 0x0416
199 #define T4CON_ADDR 0x0417
200 #define TMR5_ADDR 0x0418
201 #define TMR5L_ADDR 0x0418
202 #define TMR5H_ADDR 0x0419
203 #define T5CON_ADDR 0x041A
204 #define T5GCON_ADDR 0x041B
205 #define TMR6_ADDR 0x041C
206 #define PR6_ADDR 0x041D
207 #define T6CON_ADDR 0x041E
208 #define CCDCON_ADDR 0x041F
209 #define CCDPA_ADDR 0x048C
210 #define CCDPB_ADDR 0x048D
211 #define CCDPC_ADDR 0x048E
212 #define NCO1ACC_ADDR 0x0498
213 #define NCO1ACCL_ADDR 0x0498
214 #define NCO1ACCH_ADDR 0x0499
215 #define NCO1ACCU_ADDR 0x049A
216 #define NCO1INC_ADDR 0x049B
217 #define NCO1INCL_ADDR 0x049B
218 #define NCO1INCH_ADDR 0x049C
219 #define NCO1INCU_ADDR 0x049D
220 #define NCO1CON_ADDR 0x049E
221 #define NCO1CLK_ADDR 0x049F
222 #define PWM5DCL_ADDR 0x0617
223 #define PWM5DCH_ADDR 0x0618
224 #define PWM5CON_ADDR 0x0619
225 #define PWM5CON0_ADDR 0x0619
226 #define PWM6DCL_ADDR 0x061A
227 #define PWM6DCH_ADDR 0x061B
228 #define PWM6CON_ADDR 0x061C
229 #define PWM6CON0_ADDR 0x061C
230 #define PWMTMRS_ADDR 0x061F
231 #define CWG1CLKCON_ADDR 0x0691
232 #define CWG1DAT_ADDR 0x0692
233 #define CWG1DBR_ADDR 0x0693
234 #define CWG1DBF_ADDR 0x0694
235 #define CWG1CON0_ADDR 0x0695
236 #define CWG1CON1_ADDR 0x0696
237 #define CWG1AS0_ADDR 0x0697
238 #define CWG1AS1_ADDR 0x0698
239 #define CWG1STR_ADDR 0x0699
240 #define CWG2CLKCON_ADDR 0x0711
241 #define CWG2DAT_ADDR 0x0712
242 #define CWG2DBR_ADDR 0x0713
243 #define CWG2DBF_ADDR 0x0714
244 #define CWG2CON0_ADDR 0x0715
245 #define CWG2CON1_ADDR 0x0716
246 #define CWG2AS0_ADDR 0x0717
247 #define CWG2AS1_ADDR 0x0718
248 #define CWG2STR_ADDR 0x0719
249 #define NVMADR_ADDR 0x0891
250 #define NVMADRL_ADDR 0x0891
251 #define NVMADRH_ADDR 0x0892
252 #define NVMDAT_ADDR 0x0893
253 #define NVMDATL_ADDR 0x0893
254 #define NVMDATH_ADDR 0x0894
255 #define NVMCON1_ADDR 0x0895
256 #define NVMCON2_ADDR 0x0896
257 #define PCON0_ADDR 0x089B
258 #define PMD0_ADDR 0x0911
259 #define PMD1_ADDR 0x0912
260 #define PMD2_ADDR 0x0913
261 #define PMD3_ADDR 0x0914
262 #define PMD4_ADDR 0x0915
263 #define PMD5_ADDR 0x0916
264 #define CPUDOZE_ADDR 0x0918
265 #define OSCCON1_ADDR 0x0919
266 #define OSCCON2_ADDR 0x091A
267 #define OSCCON3_ADDR 0x091B
268 #define OSCSTAT1_ADDR 0x091C
269 #define OSCEN_ADDR 0x091D
270 #define OSCTUNE_ADDR 0x091E
271 #define OSCFRQ_ADDR 0x091F
272 #define PPSLOCK_ADDR 0x0E0F
273 #define INTPPS_ADDR 0x0E10
274 #define T0CKIPPS_ADDR 0x0E11
275 #define T1CKIPPS_ADDR 0x0E12
276 #define T1GPPS_ADDR 0x0E13
277 #define CCP1PPS_ADDR 0x0E14
278 #define CCP2PPS_ADDR 0x0E15
279 #define CCP3PPS_ADDR 0x0E16
280 #define CCP4PPS_ADDR 0x0E17
281 #define CWG1PPS_ADDR 0x0E18
282 #define CWG2PPS_ADDR 0x0E19
283 #define MDCIN1PPS_ADDR 0x0E1A
284 #define MDCIN2PPS_ADDR 0x0E1B
285 #define MDMINPPS_ADDR 0x0E1C
286 #define SSP1CLKPPS_ADDR 0x0E20
287 #define SSP1DATPPS_ADDR 0x0E21
288 #define SSP1SSPPS_ADDR 0x0E22
289 #define RXPPS_ADDR 0x0E24
290 #define TXPPS_ADDR 0x0E25
291 #define CLCIN0PPS_ADDR 0x0E28
292 #define CLCIN1PPS_ADDR 0x0E29
293 #define CLCIN2PPS_ADDR 0x0E2A
294 #define CLCIN3PPS_ADDR 0x0E2B
295 #define T3CKIPPS_ADDR 0x0E2C
296 #define T3GPPS_ADDR 0x0E2D
297 #define T5CKIPPS_ADDR 0x0E2E
298 #define T5GPPS_ADDR 0x0E2F
299 #define RA0PPS_ADDR 0x0E90
300 #define RA1PPS_ADDR 0x0E91
301 #define RA2PPS_ADDR 0x0E92
302 #define RA4PPS_ADDR 0x0E94
303 #define RA5PPS_ADDR 0x0E95
304 #define RB4PPS_ADDR 0x0E9C
305 #define RB5PPS_ADDR 0x0E9D
306 #define RB6PPS_ADDR 0x0E9E
307 #define RB7PPS_ADDR 0x0E9F
308 #define RC0PPS_ADDR 0x0EA0
309 #define RC1PPS_ADDR 0x0EA1
310 #define RC2PPS_ADDR 0x0EA2
311 #define RC3PPS_ADDR 0x0EA3
312 #define RC4PPS_ADDR 0x0EA4
313 #define RC5PPS_ADDR 0x0EA5
314 #define RC6PPS_ADDR 0x0EA6
315 #define RC7PPS_ADDR 0x0EA7
316 #define CLCDATA_ADDR 0x0F0F
317 #define CLC1CON_ADDR 0x0F10
318 #define CLC1POL_ADDR 0x0F11
319 #define CLC1SEL0_ADDR 0x0F12
320 #define CLC1SEL1_ADDR 0x0F13
321 #define CLC1SEL2_ADDR 0x0F14
322 #define CLC1SEL3_ADDR 0x0F15
323 #define CLC1GLS0_ADDR 0x0F16
324 #define CLC1GLS1_ADDR 0x0F17
325 #define CLC1GLS2_ADDR 0x0F18
326 #define CLC1GLS3_ADDR 0x0F19
327 #define CLC2CON_ADDR 0x0F1A
328 #define CLC2POL_ADDR 0x0F1B
329 #define CLC2SEL0_ADDR 0x0F1C
330 #define CLC2SEL1_ADDR 0x0F1D
331 #define CLC2SEL2_ADDR 0x0F1E
332 #define CLC2SEL3_ADDR 0x0F1F
333 #define CLC2GLS0_ADDR 0x0F20
334 #define CLC2GLS1_ADDR 0x0F21
335 #define CLC2GLS2_ADDR 0x0F22
336 #define CLC2GLS3_ADDR 0x0F23
337 #define CLC3CON_ADDR 0x0F24
338 #define CLC3POL_ADDR 0x0F25
339 #define CLC3SEL0_ADDR 0x0F26
340 #define CLC3SEL1_ADDR 0x0F27
341 #define CLC3SEL2_ADDR 0x0F28
342 #define CLC3SEL3_ADDR 0x0F29
343 #define CLC3GLS0_ADDR 0x0F2A
344 #define CLC3GLS1_ADDR 0x0F2B
345 #define CLC3GLS2_ADDR 0x0F2C
346 #define CLC3GLS3_ADDR 0x0F2D
347 #define CLC4CON_ADDR 0x0F2E
348 #define CLC4POL_ADDR 0x0F2F
349 #define CLC4SEL0_ADDR 0x0F30
350 #define CLC4SEL1_ADDR 0x0F31
351 #define CLC4SEL2_ADDR 0x0F32
352 #define CLC4SEL3_ADDR 0x0F33
353 #define CLC4GLS0_ADDR 0x0F34
354 #define CLC4GLS1_ADDR 0x0F35
355 #define CLC4GLS2_ADDR 0x0F36
356 #define CLC4GLS3_ADDR 0x0F37
357 #define STATUS_SHAD_ADDR 0x0FE4
358 #define WREG_SHAD_ADDR 0x0FE5
359 #define BSR_SHAD_ADDR 0x0FE6
360 #define PCLATH_SHAD_ADDR 0x0FE7
361 #define FSR0L_SHAD_ADDR 0x0FE8
362 #define FSR0H_SHAD_ADDR 0x0FE9
363 #define FSR1L_SHAD_ADDR 0x0FEA
364 #define FSR1H_SHAD_ADDR 0x0FEB
365 #define STKPTR_ADDR 0x0FED
366 #define TOSL_ADDR 0x0FEE
367 #define TOSH_ADDR 0x0FEF
369 #endif // #ifndef NO_ADDR_DEFINES
371 //==============================================================================
373 // Register Definitions
375 //==============================================================================
377 extern __at(0x0000) __sfr INDF0
;
378 extern __at(0x0001) __sfr INDF1
;
379 extern __at(0x0002) __sfr PCL
;
381 //==============================================================================
384 extern __at(0x0003) __sfr STATUS
;
398 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
406 //==============================================================================
408 extern __at(0x0004) __sfr FSR0
;
409 extern __at(0x0004) __sfr FSR0L
;
410 extern __at(0x0005) __sfr FSR0H
;
411 extern __at(0x0006) __sfr FSR1
;
412 extern __at(0x0006) __sfr FSR1L
;
413 extern __at(0x0007) __sfr FSR1H
;
415 //==============================================================================
418 extern __at(0x0008) __sfr BSR
;
441 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
449 //==============================================================================
451 extern __at(0x0009) __sfr WREG
;
452 extern __at(0x000A) __sfr PCLATH
;
454 //==============================================================================
457 extern __at(0x000B) __sfr INTCON
;
471 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
477 //==============================================================================
480 //==============================================================================
483 extern __at(0x000C) __sfr PORTA
;
506 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
515 //==============================================================================
518 //==============================================================================
521 extern __at(0x000D) __sfr PORTB
;
535 extern __at(0x000D) volatile __PORTBbits_t PORTBbits
;
542 //==============================================================================
545 //==============================================================================
548 extern __at(0x000E) __sfr PORTC
;
562 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
573 //==============================================================================
576 //==============================================================================
579 extern __at(0x0010) __sfr PIR0
;
593 extern __at(0x0010) volatile __PIR0bits_t PIR0bits
;
599 //==============================================================================
602 //==============================================================================
605 extern __at(0x0011) __sfr PIR1
;
616 unsigned TMR1GIF
: 1;
619 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
628 #define _TMR1GIF 0x80
630 //==============================================================================
633 //==============================================================================
636 extern __at(0x0012) __sfr PIR2
;
650 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
659 //==============================================================================
662 //==============================================================================
665 extern __at(0x0013) __sfr PIR3
;
674 unsigned TMR3GIF
: 1;
679 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
686 #define _TMR3GIF 0x20
690 //==============================================================================
693 //==============================================================================
696 extern __at(0x0014) __sfr PIR4
;
705 unsigned TMR5GIF
: 1;
710 extern __at(0x0014) volatile __PIR4bits_t PIR4bits
;
717 #define _TMR5GIF 0x20
721 //==============================================================================
724 //==============================================================================
727 extern __at(0x0015) __sfr TMR0L
;
741 extern __at(0x0015) volatile __TMR0Lbits_t TMR0Lbits
;
752 //==============================================================================
755 //==============================================================================
758 extern __at(0x0016) __sfr TMR0H
;
772 extern __at(0x0016) volatile __TMR0Hbits_t TMR0Hbits
;
783 //==============================================================================
786 //==============================================================================
789 extern __at(0x0017) __sfr T0CON0
;
795 unsigned T0OUTPS0
: 1;
796 unsigned T0OUTPS1
: 1;
797 unsigned T0OUTPS2
: 1;
798 unsigned T0OUTPS3
: 1;
799 unsigned T016BIT
: 1;
807 unsigned T0OUTPS
: 4;
812 extern __at(0x0017) volatile __T0CON0bits_t T0CON0bits
;
814 #define _T0OUTPS0 0x01
815 #define _T0OUTPS1 0x02
816 #define _T0OUTPS2 0x04
817 #define _T0OUTPS3 0x08
818 #define _T016BIT 0x10
822 //==============================================================================
825 //==============================================================================
828 extern __at(0x0018) __sfr T0CON1
;
834 unsigned T0CKPS0
: 1;
835 unsigned T0CKPS1
: 1;
836 unsigned T0CKPS2
: 1;
837 unsigned T0CKPS3
: 1;
838 unsigned T0ASYNC
: 1;
857 extern __at(0x0018) volatile __T0CON1bits_t T0CON1bits
;
859 #define _T0CKPS0 0x01
860 #define _T0CKPS1 0x02
861 #define _T0CKPS2 0x04
862 #define _T0CKPS3 0x08
863 #define _T0ASYNC 0x10
868 //==============================================================================
870 extern __at(0x0019) __sfr TMR1
;
871 extern __at(0x0019) __sfr TMR1L
;
872 extern __at(0x001A) __sfr TMR1H
;
874 //==============================================================================
877 extern __at(0x001B) __sfr T1CON
;
887 unsigned T1CKPS0
: 1;
888 unsigned T1CKPS1
: 1;
889 unsigned TMR1CS0
: 1;
890 unsigned TMR1CS1
: 1;
907 extern __at(0x001B) volatile __T1CONbits_t T1CONbits
;
912 #define _T1CKPS0 0x10
913 #define _T1CKPS1 0x20
914 #define _TMR1CS0 0x40
915 #define _TMR1CS1 0x80
917 //==============================================================================
920 //==============================================================================
923 extern __at(0x001C) __sfr T1GCON
;
932 unsigned T1GGO_NOT_DONE
: 1;
946 extern __at(0x001C) volatile __T1GCONbits_t T1GCONbits
;
951 #define _T1GGO_NOT_DONE 0x08
957 //==============================================================================
959 extern __at(0x001D) __sfr TMR2
;
960 extern __at(0x001E) __sfr PR2
;
962 //==============================================================================
965 extern __at(0x001F) __sfr T2CON
;
971 unsigned T2CKPS0
: 1;
972 unsigned T2CKPS1
: 1;
974 unsigned T2OUTPS0
: 1;
975 unsigned T2OUTPS1
: 1;
976 unsigned T2OUTPS2
: 1;
977 unsigned T2OUTPS3
: 1;
990 unsigned T2OUTPS
: 4;
995 extern __at(0x001F) volatile __T2CONbits_t T2CONbits
;
997 #define _T2CKPS0 0x01
998 #define _T2CKPS1 0x02
1000 #define _T2OUTPS0 0x08
1001 #define _T2OUTPS1 0x10
1002 #define _T2OUTPS2 0x20
1003 #define _T2OUTPS3 0x40
1005 //==============================================================================
1008 //==============================================================================
1011 extern __at(0x008C) __sfr TRISA
;
1015 unsigned TRISA0
: 1;
1016 unsigned TRISA1
: 1;
1017 unsigned TRISA2
: 1;
1019 unsigned TRISA4
: 1;
1020 unsigned TRISA5
: 1;
1025 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
1027 #define _TRISA0 0x01
1028 #define _TRISA1 0x02
1029 #define _TRISA2 0x04
1030 #define _TRISA4 0x10
1031 #define _TRISA5 0x20
1033 //==============================================================================
1036 //==============================================================================
1039 extern __at(0x008D) __sfr TRISB
;
1047 unsigned TRISB4
: 1;
1048 unsigned TRISB5
: 1;
1049 unsigned TRISB6
: 1;
1050 unsigned TRISB7
: 1;
1053 extern __at(0x008D) volatile __TRISBbits_t TRISBbits
;
1055 #define _TRISB4 0x10
1056 #define _TRISB5 0x20
1057 #define _TRISB6 0x40
1058 #define _TRISB7 0x80
1060 //==============================================================================
1063 //==============================================================================
1066 extern __at(0x008E) __sfr TRISC
;
1070 unsigned TRISC0
: 1;
1071 unsigned TRISC1
: 1;
1072 unsigned TRISC2
: 1;
1073 unsigned TRISC3
: 1;
1074 unsigned TRISC4
: 1;
1075 unsigned TRISC5
: 1;
1076 unsigned TRISC6
: 1;
1077 unsigned TRISC7
: 1;
1080 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
1082 #define _TRISC0 0x01
1083 #define _TRISC1 0x02
1084 #define _TRISC2 0x04
1085 #define _TRISC3 0x08
1086 #define _TRISC4 0x10
1087 #define _TRISC5 0x20
1088 #define _TRISC6 0x40
1089 #define _TRISC7 0x80
1091 //==============================================================================
1094 //==============================================================================
1097 extern __at(0x0090) __sfr PIE0
;
1106 unsigned TMR0IE
: 1;
1111 extern __at(0x0090) volatile __PIE0bits_t PIE0bits
;
1115 #define _TMR0IE 0x20
1117 //==============================================================================
1120 //==============================================================================
1123 extern __at(0x0091) __sfr PIE1
;
1127 unsigned TMR1IE
: 1;
1128 unsigned TMR2IE
: 1;
1129 unsigned BCL1IE
: 1;
1130 unsigned SSP1IE
: 1;
1134 unsigned TMR1GIE
: 1;
1137 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
1139 #define _TMR1IE 0x01
1140 #define _TMR2IE 0x02
1141 #define _BCL1IE 0x04
1142 #define _SSP1IE 0x08
1146 #define _TMR1GIE 0x80
1148 //==============================================================================
1151 //==============================================================================
1154 extern __at(0x0092) __sfr PIE2
;
1158 unsigned NCO1IE
: 1;
1159 unsigned TMR4IE
: 1;
1165 unsigned TMR6IE
: 1;
1168 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
1170 #define _NCO1IE 0x01
1171 #define _TMR4IE 0x02
1175 #define _TMR6IE 0x80
1177 //==============================================================================
1180 //==============================================================================
1183 extern __at(0x0093) __sfr PIE3
;
1187 unsigned CLC1IE
: 1;
1188 unsigned CLC2IE
: 1;
1189 unsigned CLC3IE
: 1;
1190 unsigned CLC4IE
: 1;
1191 unsigned TMR3IE
: 1;
1192 unsigned TMR3GIE
: 1;
1197 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
1199 #define _CLC1IE 0x01
1200 #define _CLC2IE 0x02
1201 #define _CLC3IE 0x04
1202 #define _CLC4IE 0x08
1203 #define _TMR3IE 0x10
1204 #define _TMR3GIE 0x20
1208 //==============================================================================
1211 //==============================================================================
1214 extern __at(0x0094) __sfr PIE4
;
1218 unsigned CCP1IE
: 1;
1219 unsigned CCP2IE
: 1;
1220 unsigned CCP3IE
: 1;
1221 unsigned CCP4IE
: 1;
1222 unsigned TMR5IE
: 1;
1223 unsigned TMR5GIE
: 1;
1224 unsigned CWG1IE
: 1;
1225 unsigned CWG2IE
: 1;
1228 extern __at(0x0094) volatile __PIE4bits_t PIE4bits
;
1230 #define _CCP1IE 0x01
1231 #define _CCP2IE 0x02
1232 #define _CCP3IE 0x04
1233 #define _CCP4IE 0x08
1234 #define _TMR5IE 0x10
1235 #define _TMR5GIE 0x20
1236 #define _CWG1IE 0x40
1237 #define _CWG2IE 0x80
1239 //==============================================================================
1242 //==============================================================================
1245 extern __at(0x0097) __sfr WDTCON
;
1251 unsigned SWDTEN
: 1;
1252 unsigned WDTPS0
: 1;
1253 unsigned WDTPS1
: 1;
1254 unsigned WDTPS2
: 1;
1255 unsigned WDTPS3
: 1;
1256 unsigned WDTPS4
: 1;
1269 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1271 #define _SWDTEN 0x01
1272 #define _WDTPS0 0x02
1273 #define _WDTPS1 0x04
1274 #define _WDTPS2 0x08
1275 #define _WDTPS3 0x10
1276 #define _WDTPS4 0x20
1278 //==============================================================================
1280 extern __at(0x009B) __sfr ADRES
;
1281 extern __at(0x009B) __sfr ADRESL
;
1282 extern __at(0x009C) __sfr ADRESH
;
1284 //==============================================================================
1287 extern __at(0x009D) __sfr ADCON0
;
1294 unsigned GO_NOT_DONE
: 1;
1334 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1337 #define _GO_NOT_DONE 0x02
1347 //==============================================================================
1350 //==============================================================================
1353 extern __at(0x009E) __sfr ADCON1
;
1359 unsigned ADPREF0
: 1;
1360 unsigned ADPREF1
: 1;
1361 unsigned ADNREF
: 1;
1371 unsigned ADPREF
: 2;
1383 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1385 #define _ADPREF0 0x01
1386 #define _ADPREF1 0x02
1387 #define _ADNREF 0x04
1393 //==============================================================================
1396 //==============================================================================
1399 extern __at(0x009F) __sfr ADACT
;
1405 unsigned ADACT0
: 1;
1406 unsigned ADACT1
: 1;
1407 unsigned ADACT2
: 1;
1408 unsigned ADACT3
: 1;
1409 unsigned ADACT4
: 1;
1422 extern __at(0x009F) volatile __ADACTbits_t ADACTbits
;
1424 #define _ADACT0 0x01
1425 #define _ADACT1 0x02
1426 #define _ADACT2 0x04
1427 #define _ADACT3 0x08
1428 #define _ADACT4 0x10
1430 //==============================================================================
1433 //==============================================================================
1436 extern __at(0x010C) __sfr LATA
;
1450 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1458 //==============================================================================
1461 //==============================================================================
1464 extern __at(0x010D) __sfr LATB
;
1478 extern __at(0x010D) volatile __LATBbits_t LATBbits
;
1485 //==============================================================================
1488 //==============================================================================
1491 extern __at(0x010E) __sfr LATC
;
1505 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1516 //==============================================================================
1519 //==============================================================================
1522 extern __at(0x0111) __sfr CM1CON0
;
1526 unsigned C1SYNC
: 1;
1536 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1538 #define _C1SYNC 0x01
1545 //==============================================================================
1548 //==============================================================================
1551 extern __at(0x0112) __sfr CM1CON1
;
1557 unsigned C1NCH0
: 1;
1558 unsigned C1NCH1
: 1;
1559 unsigned C1NCH2
: 1;
1560 unsigned C1PCH0
: 1;
1561 unsigned C1PCH1
: 1;
1562 unsigned C1PCH2
: 1;
1563 unsigned C1INTN
: 1;
1564 unsigned C1INTP
: 1;
1581 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1583 #define _C1NCH0 0x01
1584 #define _C1NCH1 0x02
1585 #define _C1NCH2 0x04
1586 #define _C1PCH0 0x08
1587 #define _C1PCH1 0x10
1588 #define _C1PCH2 0x20
1589 #define _C1INTN 0x40
1590 #define _C1INTP 0x80
1592 //==============================================================================
1595 //==============================================================================
1598 extern __at(0x0113) __sfr CM2CON0
;
1602 unsigned C2SYNC
: 1;
1612 extern __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits
;
1614 #define _C2SYNC 0x01
1621 //==============================================================================
1624 //==============================================================================
1627 extern __at(0x0114) __sfr CM2CON1
;
1633 unsigned C2NCH0
: 1;
1634 unsigned C2NCH1
: 1;
1635 unsigned C2NCH2
: 1;
1636 unsigned C2PCH0
: 1;
1637 unsigned C2PCH1
: 1;
1638 unsigned C2PCH2
: 1;
1639 unsigned C2INTN
: 1;
1640 unsigned C2INTP
: 1;
1657 extern __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits
;
1659 #define _C2NCH0 0x01
1660 #define _C2NCH1 0x02
1661 #define _C2NCH2 0x04
1662 #define _C2PCH0 0x08
1663 #define _C2PCH1 0x10
1664 #define _C2PCH2 0x20
1665 #define _C2INTN 0x40
1666 #define _C2INTP 0x80
1668 //==============================================================================
1671 //==============================================================================
1674 extern __at(0x0115) __sfr CMOUT
;
1678 unsigned MC1OUT
: 1;
1679 unsigned MC2OUT
: 1;
1688 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1690 #define _MC1OUT 0x01
1691 #define _MC2OUT 0x02
1693 //==============================================================================
1696 //==============================================================================
1699 extern __at(0x0116) __sfr BORCON
;
1703 unsigned BORRDY
: 1;
1710 unsigned SBOREN
: 1;
1713 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1715 #define _BORRDY 0x01
1716 #define _SBOREN 0x80
1718 //==============================================================================
1721 //==============================================================================
1724 extern __at(0x0117) __sfr FVRCON
;
1730 unsigned ADFVR0
: 1;
1731 unsigned ADFVR1
: 1;
1732 unsigned CDAFVR0
: 1;
1733 unsigned CDAFVR1
: 1;
1736 unsigned FVRRDY
: 1;
1749 unsigned CDAFVR
: 2;
1754 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1756 #define _ADFVR0 0x01
1757 #define _ADFVR1 0x02
1758 #define _CDAFVR0 0x04
1759 #define _CDAFVR1 0x08
1762 #define _FVRRDY 0x40
1765 //==============================================================================
1768 //==============================================================================
1771 extern __at(0x0118) __sfr DACCON0
;
1777 unsigned DAC1NSS
: 1;
1779 unsigned DAC1PSS0
: 1;
1780 unsigned DAC1PSS1
: 1;
1782 unsigned DAC1OE
: 1;
1784 unsigned DAC1EN
: 1;
1790 unsigned DAC1PSS
: 2;
1795 extern __at(0x0118) volatile __DACCON0bits_t DACCON0bits
;
1797 #define _DAC1NSS 0x01
1798 #define _DAC1PSS0 0x04
1799 #define _DAC1PSS1 0x08
1800 #define _DAC1OE 0x20
1801 #define _DAC1EN 0x80
1803 //==============================================================================
1806 //==============================================================================
1809 extern __at(0x0119) __sfr DACCON1
;
1815 unsigned DAC1R0
: 1;
1816 unsigned DAC1R1
: 1;
1817 unsigned DAC1R2
: 1;
1818 unsigned DAC1R3
: 1;
1819 unsigned DAC1R4
: 1;
1832 extern __at(0x0119) volatile __DACCON1bits_t DACCON1bits
;
1834 #define _DAC1R0 0x01
1835 #define _DAC1R1 0x02
1836 #define _DAC1R2 0x04
1837 #define _DAC1R3 0x08
1838 #define _DAC1R4 0x10
1840 //==============================================================================
1843 //==============================================================================
1846 extern __at(0x018C) __sfr ANSELA
;
1860 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1868 //==============================================================================
1871 //==============================================================================
1874 extern __at(0x018D) __sfr ANSELB
;
1888 extern __at(0x018D) volatile __ANSELBbits_t ANSELBbits
;
1895 //==============================================================================
1898 //==============================================================================
1901 extern __at(0x018E) __sfr ANSELC
;
1915 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
1926 //==============================================================================
1929 //==============================================================================
1932 extern __at(0x0197) __sfr VREGCON
;
1937 unsigned VREGPM
: 1;
1946 extern __at(0x0197) volatile __VREGCONbits_t VREGCONbits
;
1948 #define _VREGPM 0x02
1950 //==============================================================================
1952 extern __at(0x0199) __sfr RC1REG
;
1953 extern __at(0x0199) __sfr RCREG
;
1954 extern __at(0x0199) __sfr RCREG1
;
1955 extern __at(0x019A) __sfr TX1REG
;
1956 extern __at(0x019A) __sfr TXREG
;
1957 extern __at(0x019A) __sfr TXREG1
;
1958 extern __at(0x019B) __sfr SP1BRG
;
1959 extern __at(0x019B) __sfr SP1BRGL
;
1960 extern __at(0x019B) __sfr SPBRG
;
1961 extern __at(0x019B) __sfr SPBRG1
;
1962 extern __at(0x019B) __sfr SPBRGL
;
1963 extern __at(0x019C) __sfr SP1BRGH
;
1964 extern __at(0x019C) __sfr SPBRGH
;
1965 extern __at(0x019C) __sfr SPBRGH1
;
1967 //==============================================================================
1970 extern __at(0x019D) __sfr RC1STA
;
1984 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
1995 //==============================================================================
1998 //==============================================================================
2001 extern __at(0x019D) __sfr RCSTA
;
2015 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
2017 #define _RCSTA_RX9D 0x01
2018 #define _RCSTA_OERR 0x02
2019 #define _RCSTA_FERR 0x04
2020 #define _RCSTA_ADDEN 0x08
2021 #define _RCSTA_CREN 0x10
2022 #define _RCSTA_SREN 0x20
2023 #define _RCSTA_RX9 0x40
2024 #define _RCSTA_SPEN 0x80
2026 //==============================================================================
2029 //==============================================================================
2032 extern __at(0x019D) __sfr RCSTA1
;
2046 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
2048 #define _RCSTA1_RX9D 0x01
2049 #define _RCSTA1_OERR 0x02
2050 #define _RCSTA1_FERR 0x04
2051 #define _RCSTA1_ADDEN 0x08
2052 #define _RCSTA1_CREN 0x10
2053 #define _RCSTA1_SREN 0x20
2054 #define _RCSTA1_RX9 0x40
2055 #define _RCSTA1_SPEN 0x80
2057 //==============================================================================
2060 //==============================================================================
2063 extern __at(0x019E) __sfr TX1STA
;
2077 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
2088 //==============================================================================
2091 //==============================================================================
2094 extern __at(0x019E) __sfr TXSTA
;
2108 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
2110 #define _TXSTA_TX9D 0x01
2111 #define _TXSTA_TRMT 0x02
2112 #define _TXSTA_BRGH 0x04
2113 #define _TXSTA_SENDB 0x08
2114 #define _TXSTA_SYNC 0x10
2115 #define _TXSTA_TXEN 0x20
2116 #define _TXSTA_TX9 0x40
2117 #define _TXSTA_CSRC 0x80
2119 //==============================================================================
2122 //==============================================================================
2125 extern __at(0x019E) __sfr TXSTA1
;
2139 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
2141 #define _TXSTA1_TX9D 0x01
2142 #define _TXSTA1_TRMT 0x02
2143 #define _TXSTA1_BRGH 0x04
2144 #define _TXSTA1_SENDB 0x08
2145 #define _TXSTA1_SYNC 0x10
2146 #define _TXSTA1_TXEN 0x20
2147 #define _TXSTA1_TX9 0x40
2148 #define _TXSTA1_CSRC 0x80
2150 //==============================================================================
2153 //==============================================================================
2156 extern __at(0x019F) __sfr BAUD1CON
;
2167 unsigned ABDOVF
: 1;
2170 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
2177 #define _ABDOVF 0x80
2179 //==============================================================================
2182 //==============================================================================
2185 extern __at(0x019F) __sfr BAUDCON
;
2196 unsigned ABDOVF
: 1;
2199 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
2201 #define _BAUDCON_ABDEN 0x01
2202 #define _BAUDCON_WUE 0x02
2203 #define _BAUDCON_BRG16 0x08
2204 #define _BAUDCON_SCKP 0x10
2205 #define _BAUDCON_RCIDL 0x40
2206 #define _BAUDCON_ABDOVF 0x80
2208 //==============================================================================
2211 //==============================================================================
2214 extern __at(0x019F) __sfr BAUDCON1
;
2225 unsigned ABDOVF
: 1;
2228 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
2230 #define _BAUDCON1_ABDEN 0x01
2231 #define _BAUDCON1_WUE 0x02
2232 #define _BAUDCON1_BRG16 0x08
2233 #define _BAUDCON1_SCKP 0x10
2234 #define _BAUDCON1_RCIDL 0x40
2235 #define _BAUDCON1_ABDOVF 0x80
2237 //==============================================================================
2240 //==============================================================================
2243 extern __at(0x019F) __sfr BAUDCTL
;
2254 unsigned ABDOVF
: 1;
2257 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
2259 #define _BAUDCTL_ABDEN 0x01
2260 #define _BAUDCTL_WUE 0x02
2261 #define _BAUDCTL_BRG16 0x08
2262 #define _BAUDCTL_SCKP 0x10
2263 #define _BAUDCTL_RCIDL 0x40
2264 #define _BAUDCTL_ABDOVF 0x80
2266 //==============================================================================
2269 //==============================================================================
2272 extern __at(0x019F) __sfr BAUDCTL1
;
2283 unsigned ABDOVF
: 1;
2286 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
2288 #define _BAUDCTL1_ABDEN 0x01
2289 #define _BAUDCTL1_WUE 0x02
2290 #define _BAUDCTL1_BRG16 0x08
2291 #define _BAUDCTL1_SCKP 0x10
2292 #define _BAUDCTL1_RCIDL 0x40
2293 #define _BAUDCTL1_ABDOVF 0x80
2295 //==============================================================================
2298 //==============================================================================
2301 extern __at(0x020C) __sfr WPUA
;
2324 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
2333 //==============================================================================
2336 //==============================================================================
2339 extern __at(0x020D) __sfr WPUB
;
2353 extern __at(0x020D) volatile __WPUBbits_t WPUBbits
;
2360 //==============================================================================
2363 //==============================================================================
2366 extern __at(0x020E) __sfr WPUC
;
2380 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
2391 //==============================================================================
2394 //==============================================================================
2397 extern __at(0x0211) __sfr SSP1BUF
;
2403 unsigned SSP1BUF0
: 1;
2404 unsigned SSP1BUF1
: 1;
2405 unsigned SSP1BUF2
: 1;
2406 unsigned SSP1BUF3
: 1;
2407 unsigned SSP1BUF4
: 1;
2408 unsigned SSP1BUF5
: 1;
2409 unsigned SSP1BUF6
: 1;
2410 unsigned SSP1BUF7
: 1;
2426 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
2428 #define _SSP1BUF0 0x01
2430 #define _SSP1BUF1 0x02
2432 #define _SSP1BUF2 0x04
2434 #define _SSP1BUF3 0x08
2436 #define _SSP1BUF4 0x10
2438 #define _SSP1BUF5 0x20
2440 #define _SSP1BUF6 0x40
2442 #define _SSP1BUF7 0x80
2445 //==============================================================================
2448 //==============================================================================
2451 extern __at(0x0211) __sfr SSPBUF
;
2457 unsigned SSP1BUF0
: 1;
2458 unsigned SSP1BUF1
: 1;
2459 unsigned SSP1BUF2
: 1;
2460 unsigned SSP1BUF3
: 1;
2461 unsigned SSP1BUF4
: 1;
2462 unsigned SSP1BUF5
: 1;
2463 unsigned SSP1BUF6
: 1;
2464 unsigned SSP1BUF7
: 1;
2480 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
2482 #define _SSPBUF_SSP1BUF0 0x01
2483 #define _SSPBUF_BUF0 0x01
2484 #define _SSPBUF_SSP1BUF1 0x02
2485 #define _SSPBUF_BUF1 0x02
2486 #define _SSPBUF_SSP1BUF2 0x04
2487 #define _SSPBUF_BUF2 0x04
2488 #define _SSPBUF_SSP1BUF3 0x08
2489 #define _SSPBUF_BUF3 0x08
2490 #define _SSPBUF_SSP1BUF4 0x10
2491 #define _SSPBUF_BUF4 0x10
2492 #define _SSPBUF_SSP1BUF5 0x20
2493 #define _SSPBUF_BUF5 0x20
2494 #define _SSPBUF_SSP1BUF6 0x40
2495 #define _SSPBUF_BUF6 0x40
2496 #define _SSPBUF_SSP1BUF7 0x80
2497 #define _SSPBUF_BUF7 0x80
2499 //==============================================================================
2502 //==============================================================================
2505 extern __at(0x0212) __sfr SSP1ADD
;
2511 unsigned SSP1ADD0
: 1;
2512 unsigned SSP1ADD1
: 1;
2513 unsigned SSP1ADD2
: 1;
2514 unsigned SSP1ADD3
: 1;
2515 unsigned SSP1ADD4
: 1;
2516 unsigned SSP1ADD5
: 1;
2517 unsigned SSP1ADD6
: 1;
2518 unsigned SSP1ADD7
: 1;
2534 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
2536 #define _SSP1ADD0 0x01
2538 #define _SSP1ADD1 0x02
2540 #define _SSP1ADD2 0x04
2542 #define _SSP1ADD3 0x08
2544 #define _SSP1ADD4 0x10
2546 #define _SSP1ADD5 0x20
2548 #define _SSP1ADD6 0x40
2550 #define _SSP1ADD7 0x80
2553 //==============================================================================
2556 //==============================================================================
2559 extern __at(0x0212) __sfr SSPADD
;
2565 unsigned SSP1ADD0
: 1;
2566 unsigned SSP1ADD1
: 1;
2567 unsigned SSP1ADD2
: 1;
2568 unsigned SSP1ADD3
: 1;
2569 unsigned SSP1ADD4
: 1;
2570 unsigned SSP1ADD5
: 1;
2571 unsigned SSP1ADD6
: 1;
2572 unsigned SSP1ADD7
: 1;
2588 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
2590 #define _SSPADD_SSP1ADD0 0x01
2591 #define _SSPADD_ADD0 0x01
2592 #define _SSPADD_SSP1ADD1 0x02
2593 #define _SSPADD_ADD1 0x02
2594 #define _SSPADD_SSP1ADD2 0x04
2595 #define _SSPADD_ADD2 0x04
2596 #define _SSPADD_SSP1ADD3 0x08
2597 #define _SSPADD_ADD3 0x08
2598 #define _SSPADD_SSP1ADD4 0x10
2599 #define _SSPADD_ADD4 0x10
2600 #define _SSPADD_SSP1ADD5 0x20
2601 #define _SSPADD_ADD5 0x20
2602 #define _SSPADD_SSP1ADD6 0x40
2603 #define _SSPADD_ADD6 0x40
2604 #define _SSPADD_SSP1ADD7 0x80
2605 #define _SSPADD_ADD7 0x80
2607 //==============================================================================
2610 //==============================================================================
2613 extern __at(0x0213) __sfr SSP1MSK
;
2619 unsigned SSP1MSK0
: 1;
2620 unsigned SSP1MSK1
: 1;
2621 unsigned SSP1MSK2
: 1;
2622 unsigned SSP1MSK3
: 1;
2623 unsigned SSP1MSK4
: 1;
2624 unsigned SSP1MSK5
: 1;
2625 unsigned SSP1MSK6
: 1;
2626 unsigned SSP1MSK7
: 1;
2642 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
2644 #define _SSP1MSK0 0x01
2646 #define _SSP1MSK1 0x02
2648 #define _SSP1MSK2 0x04
2650 #define _SSP1MSK3 0x08
2652 #define _SSP1MSK4 0x10
2654 #define _SSP1MSK5 0x20
2656 #define _SSP1MSK6 0x40
2658 #define _SSP1MSK7 0x80
2661 //==============================================================================
2664 //==============================================================================
2667 extern __at(0x0213) __sfr SSPMSK
;
2673 unsigned SSP1MSK0
: 1;
2674 unsigned SSP1MSK1
: 1;
2675 unsigned SSP1MSK2
: 1;
2676 unsigned SSP1MSK3
: 1;
2677 unsigned SSP1MSK4
: 1;
2678 unsigned SSP1MSK5
: 1;
2679 unsigned SSP1MSK6
: 1;
2680 unsigned SSP1MSK7
: 1;
2696 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
2698 #define _SSPMSK_SSP1MSK0 0x01
2699 #define _SSPMSK_MSK0 0x01
2700 #define _SSPMSK_SSP1MSK1 0x02
2701 #define _SSPMSK_MSK1 0x02
2702 #define _SSPMSK_SSP1MSK2 0x04
2703 #define _SSPMSK_MSK2 0x04
2704 #define _SSPMSK_SSP1MSK3 0x08
2705 #define _SSPMSK_MSK3 0x08
2706 #define _SSPMSK_SSP1MSK4 0x10
2707 #define _SSPMSK_MSK4 0x10
2708 #define _SSPMSK_SSP1MSK5 0x20
2709 #define _SSPMSK_MSK5 0x20
2710 #define _SSPMSK_SSP1MSK6 0x40
2711 #define _SSPMSK_MSK6 0x40
2712 #define _SSPMSK_SSP1MSK7 0x80
2713 #define _SSPMSK_MSK7 0x80
2715 //==============================================================================
2718 //==============================================================================
2721 extern __at(0x0214) __sfr SSP1STAT
;
2727 unsigned R_NOT_W
: 1;
2730 unsigned D_NOT_A
: 1;
2735 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
2739 #define _R_NOT_W 0x04
2742 #define _D_NOT_A 0x20
2746 //==============================================================================
2749 //==============================================================================
2752 extern __at(0x0214) __sfr SSPSTAT
;
2758 unsigned R_NOT_W
: 1;
2761 unsigned D_NOT_A
: 1;
2766 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
2768 #define _SSPSTAT_BF 0x01
2769 #define _SSPSTAT_UA 0x02
2770 #define _SSPSTAT_R_NOT_W 0x04
2771 #define _SSPSTAT_S 0x08
2772 #define _SSPSTAT_P 0x10
2773 #define _SSPSTAT_D_NOT_A 0x20
2774 #define _SSPSTAT_CKE 0x40
2775 #define _SSPSTAT_SMP 0x80
2777 //==============================================================================
2780 //==============================================================================
2783 extern __at(0x0215) __sfr SSP1CON
;
2806 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
2817 //==============================================================================
2820 //==============================================================================
2823 extern __at(0x0215) __sfr SSP1CON1
;
2846 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
2848 #define _SSP1CON1_SSPM0 0x01
2849 #define _SSP1CON1_SSPM1 0x02
2850 #define _SSP1CON1_SSPM2 0x04
2851 #define _SSP1CON1_SSPM3 0x08
2852 #define _SSP1CON1_CKP 0x10
2853 #define _SSP1CON1_SSPEN 0x20
2854 #define _SSP1CON1_SSPOV 0x40
2855 #define _SSP1CON1_WCOL 0x80
2857 //==============================================================================
2860 //==============================================================================
2863 extern __at(0x0215) __sfr SSPCON
;
2886 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2888 #define _SSPCON_SSPM0 0x01
2889 #define _SSPCON_SSPM1 0x02
2890 #define _SSPCON_SSPM2 0x04
2891 #define _SSPCON_SSPM3 0x08
2892 #define _SSPCON_CKP 0x10
2893 #define _SSPCON_SSPEN 0x20
2894 #define _SSPCON_SSPOV 0x40
2895 #define _SSPCON_WCOL 0x80
2897 //==============================================================================
2900 //==============================================================================
2903 extern __at(0x0215) __sfr SSPCON1
;
2926 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2928 #define _SSPCON1_SSPM0 0x01
2929 #define _SSPCON1_SSPM1 0x02
2930 #define _SSPCON1_SSPM2 0x04
2931 #define _SSPCON1_SSPM3 0x08
2932 #define _SSPCON1_CKP 0x10
2933 #define _SSPCON1_SSPEN 0x20
2934 #define _SSPCON1_SSPOV 0x40
2935 #define _SSPCON1_WCOL 0x80
2937 //==============================================================================
2940 //==============================================================================
2943 extern __at(0x0216) __sfr SSP1CON2
;
2953 unsigned ACKSTAT
: 1;
2957 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
2965 #define _ACKSTAT 0x40
2968 //==============================================================================
2971 //==============================================================================
2974 extern __at(0x0216) __sfr SSPCON2
;
2984 unsigned ACKSTAT
: 1;
2988 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
2990 #define _SSPCON2_SEN 0x01
2991 #define _SSPCON2_RSEN 0x02
2992 #define _SSPCON2_PEN 0x04
2993 #define _SSPCON2_RCEN 0x08
2994 #define _SSPCON2_ACKEN 0x10
2995 #define _SSPCON2_ACKDT 0x20
2996 #define _SSPCON2_ACKSTAT 0x40
2997 #define _SSPCON2_GCEN 0x80
2999 //==============================================================================
3002 //==============================================================================
3005 extern __at(0x0217) __sfr SSP1CON3
;
3016 unsigned ACKTIM
: 1;
3019 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
3028 #define _ACKTIM 0x80
3030 //==============================================================================
3033 //==============================================================================
3036 extern __at(0x0217) __sfr SSPCON3
;
3047 unsigned ACKTIM
: 1;
3050 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
3052 #define _SSPCON3_DHEN 0x01
3053 #define _SSPCON3_AHEN 0x02
3054 #define _SSPCON3_SBCDE 0x04
3055 #define _SSPCON3_SDAHT 0x08
3056 #define _SSPCON3_BOEN 0x10
3057 #define _SSPCON3_SCIE 0x20
3058 #define _SSPCON3_PCIE 0x40
3059 #define _SSPCON3_ACKTIM 0x80
3061 //==============================================================================
3064 //==============================================================================
3067 extern __at(0x028C) __sfr ODCONA
;
3081 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
3089 //==============================================================================
3092 //==============================================================================
3095 extern __at(0x028D) __sfr ODCONB
;
3109 extern __at(0x028D) volatile __ODCONBbits_t ODCONBbits
;
3116 //==============================================================================
3119 //==============================================================================
3122 extern __at(0x028E) __sfr ODCONC
;
3136 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
3147 //==============================================================================
3149 extern __at(0x0291) __sfr CCPR1
;
3150 extern __at(0x0291) __sfr CCPR1L
;
3151 extern __at(0x0292) __sfr CCPR1H
;
3153 //==============================================================================
3156 extern __at(0x0293) __sfr CCP1CON
;
3162 unsigned CCP1MODE0
: 1;
3163 unsigned CCP1MODE1
: 1;
3164 unsigned CCP1MODE2
: 1;
3165 unsigned CCP1MODE3
: 1;
3166 unsigned CCP1FMT
: 1;
3167 unsigned CCP1OUT
: 1;
3169 unsigned CCP1EN
: 1;
3174 unsigned CCP1MODE
: 4;
3179 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
3181 #define _CCP1MODE0 0x01
3182 #define _CCP1MODE1 0x02
3183 #define _CCP1MODE2 0x04
3184 #define _CCP1MODE3 0x08
3185 #define _CCP1FMT 0x10
3186 #define _CCP1OUT 0x20
3187 #define _CCP1EN 0x80
3189 //==============================================================================
3192 //==============================================================================
3195 extern __at(0x0294) __sfr CCP1CAP
;
3201 unsigned CCP1CTS0
: 1;
3202 unsigned CCP1CTS1
: 1;
3203 unsigned CCP1CTS2
: 1;
3204 unsigned CCP1CTS3
: 1;
3213 unsigned CCP1CTS
: 4;
3218 extern __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits
;
3220 #define _CCP1CTS0 0x01
3221 #define _CCP1CTS1 0x02
3222 #define _CCP1CTS2 0x04
3223 #define _CCP1CTS3 0x08
3225 //==============================================================================
3227 extern __at(0x0295) __sfr CCPR2
;
3228 extern __at(0x0295) __sfr CCPR2L
;
3229 extern __at(0x0296) __sfr CCPR2H
;
3231 //==============================================================================
3234 extern __at(0x0297) __sfr CCP2CON
;
3240 unsigned CCP2MODE0
: 1;
3241 unsigned CCP2MODE1
: 1;
3242 unsigned CCP2MODE2
: 1;
3243 unsigned CCP2MODE3
: 1;
3244 unsigned CCP2FMT
: 1;
3245 unsigned CCP2OUT
: 1;
3247 unsigned CCP2EN
: 1;
3252 unsigned CCP2MODE
: 4;
3257 extern __at(0x0297) volatile __CCP2CONbits_t CCP2CONbits
;
3259 #define _CCP2MODE0 0x01
3260 #define _CCP2MODE1 0x02
3261 #define _CCP2MODE2 0x04
3262 #define _CCP2MODE3 0x08
3263 #define _CCP2FMT 0x10
3264 #define _CCP2OUT 0x20
3265 #define _CCP2EN 0x80
3267 //==============================================================================
3270 //==============================================================================
3273 extern __at(0x0298) __sfr CCP2CAP
;
3279 unsigned CCP2CTS0
: 1;
3280 unsigned CCP2CTS1
: 1;
3281 unsigned CCP2CTS2
: 1;
3282 unsigned CCP2CTS3
: 1;
3291 unsigned CCP2CTS
: 4;
3296 extern __at(0x0298) volatile __CCP2CAPbits_t CCP2CAPbits
;
3298 #define _CCP2CTS0 0x01
3299 #define _CCP2CTS1 0x02
3300 #define _CCP2CTS2 0x04
3301 #define _CCP2CTS3 0x08
3303 //==============================================================================
3306 //==============================================================================
3309 extern __at(0x029F) __sfr CCPTMRS
;
3315 unsigned C1TSEL0
: 1;
3316 unsigned C1TSEL1
: 1;
3317 unsigned C2TSEL0
: 1;
3318 unsigned C2TSEL1
: 1;
3319 unsigned C3TSEL0
: 1;
3320 unsigned C3TSEL1
: 1;
3321 unsigned C4TSEL0
: 1;
3322 unsigned C4TSEL1
: 1;
3327 unsigned C1TSEL
: 2;
3334 unsigned C2TSEL
: 2;
3341 unsigned C3TSEL
: 2;
3348 unsigned C4TSEL
: 2;
3352 extern __at(0x029F) volatile __CCPTMRSbits_t CCPTMRSbits
;
3354 #define _C1TSEL0 0x01
3355 #define _C1TSEL1 0x02
3356 #define _C2TSEL0 0x04
3357 #define _C2TSEL1 0x08
3358 #define _C3TSEL0 0x10
3359 #define _C3TSEL1 0x20
3360 #define _C4TSEL0 0x40
3361 #define _C4TSEL1 0x80
3363 //==============================================================================
3366 //==============================================================================
3369 extern __at(0x030C) __sfr SLRCONA
;
3383 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
3391 //==============================================================================
3394 //==============================================================================
3397 extern __at(0x030D) __sfr SLRCONB
;
3411 extern __at(0x030D) volatile __SLRCONBbits_t SLRCONBbits
;
3418 //==============================================================================
3421 //==============================================================================
3424 extern __at(0x030E) __sfr SLRCONC
;
3438 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
3449 //==============================================================================
3451 extern __at(0x0311) __sfr CCPR3
;
3452 extern __at(0x0311) __sfr CCPR3L
;
3453 extern __at(0x0312) __sfr CCPR3H
;
3455 //==============================================================================
3458 extern __at(0x0313) __sfr CCP3CON
;
3464 unsigned CCP3MODE0
: 1;
3465 unsigned CCP3MODE1
: 1;
3466 unsigned CCP3MODE2
: 1;
3467 unsigned CCP3MODE3
: 1;
3468 unsigned CCP3FMT
: 1;
3469 unsigned CCP3OUT
: 1;
3471 unsigned CCP3EN
: 1;
3476 unsigned CCP3MODE
: 4;
3481 extern __at(0x0313) volatile __CCP3CONbits_t CCP3CONbits
;
3483 #define _CCP3MODE0 0x01
3484 #define _CCP3MODE1 0x02
3485 #define _CCP3MODE2 0x04
3486 #define _CCP3MODE3 0x08
3487 #define _CCP3FMT 0x10
3488 #define _CCP3OUT 0x20
3489 #define _CCP3EN 0x80
3491 //==============================================================================
3494 //==============================================================================
3497 extern __at(0x0314) __sfr CCP3CAP
;
3503 unsigned CCP3CTS0
: 1;
3504 unsigned CCP3CTS1
: 1;
3505 unsigned CCP3CTS2
: 1;
3506 unsigned CCP3CTS3
: 1;
3515 unsigned CCP3CTS
: 4;
3520 extern __at(0x0314) volatile __CCP3CAPbits_t CCP3CAPbits
;
3522 #define _CCP3CTS0 0x01
3523 #define _CCP3CTS1 0x02
3524 #define _CCP3CTS2 0x04
3525 #define _CCP3CTS3 0x08
3527 //==============================================================================
3529 extern __at(0x0315) __sfr CCPR4
;
3530 extern __at(0x0315) __sfr CCPR4L
;
3531 extern __at(0x0316) __sfr CCPR4H
;
3533 //==============================================================================
3536 extern __at(0x0317) __sfr CCP4CON
;
3542 unsigned CCP4MODE0
: 1;
3543 unsigned CCP4MODE1
: 1;
3544 unsigned CCP4MODE2
: 1;
3545 unsigned CCP4MODE3
: 1;
3546 unsigned CCP4FMT
: 1;
3547 unsigned CCP4OUT
: 1;
3549 unsigned CCP4EN
: 1;
3554 unsigned CCP4MODE
: 4;
3559 extern __at(0x0317) volatile __CCP4CONbits_t CCP4CONbits
;
3561 #define _CCP4MODE0 0x01
3562 #define _CCP4MODE1 0x02
3563 #define _CCP4MODE2 0x04
3564 #define _CCP4MODE3 0x08
3565 #define _CCP4FMT 0x10
3566 #define _CCP4OUT 0x20
3567 #define _CCP4EN 0x80
3569 //==============================================================================
3572 //==============================================================================
3575 extern __at(0x0318) __sfr CCP4CAP
;
3581 unsigned CCP4CTS0
: 1;
3582 unsigned CCP4CTS1
: 1;
3583 unsigned CCP4CTS2
: 1;
3584 unsigned CCP4CTS3
: 1;
3593 unsigned CCP4CTS
: 4;
3598 extern __at(0x0318) volatile __CCP4CAPbits_t CCP4CAPbits
;
3600 #define _CCP4CTS0 0x01
3601 #define _CCP4CTS1 0x02
3602 #define _CCP4CTS2 0x04
3603 #define _CCP4CTS3 0x08
3605 //==============================================================================
3608 //==============================================================================
3611 extern __at(0x038C) __sfr INLVLA
;
3617 unsigned INLVLA0
: 1;
3618 unsigned INLVLA1
: 1;
3619 unsigned INLVLA2
: 1;
3620 unsigned INLVLA3
: 1;
3621 unsigned INLVLA4
: 1;
3622 unsigned INLVLA5
: 1;
3629 unsigned INLVLA
: 6;
3634 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
3636 #define _INLVLA0 0x01
3637 #define _INLVLA1 0x02
3638 #define _INLVLA2 0x04
3639 #define _INLVLA3 0x08
3640 #define _INLVLA4 0x10
3641 #define _INLVLA5 0x20
3643 //==============================================================================
3646 //==============================================================================
3649 extern __at(0x038D) __sfr INLVLB
;
3657 unsigned INLVLB4
: 1;
3658 unsigned INLVLB5
: 1;
3659 unsigned INLVLB6
: 1;
3660 unsigned INLVLB7
: 1;
3663 extern __at(0x038D) volatile __INLVLBbits_t INLVLBbits
;
3665 #define _INLVLB4 0x10
3666 #define _INLVLB5 0x20
3667 #define _INLVLB6 0x40
3668 #define _INLVLB7 0x80
3670 //==============================================================================
3673 //==============================================================================
3676 extern __at(0x038E) __sfr INLVLC
;
3680 unsigned INLVLC0
: 1;
3681 unsigned INLVLC1
: 1;
3682 unsigned INLVLC2
: 1;
3683 unsigned INLVLC3
: 1;
3684 unsigned INLVLC4
: 1;
3685 unsigned INLVLC5
: 1;
3686 unsigned INLVLC6
: 1;
3687 unsigned INLVLC7
: 1;
3690 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
3692 #define _INLVLC0 0x01
3693 #define _INLVLC1 0x02
3694 #define _INLVLC2 0x04
3695 #define _INLVLC3 0x08
3696 #define _INLVLC4 0x10
3697 #define _INLVLC5 0x20
3698 #define _INLVLC6 0x40
3699 #define _INLVLC7 0x80
3701 //==============================================================================
3704 //==============================================================================
3707 extern __at(0x0391) __sfr IOCAP
;
3713 unsigned IOCAP0
: 1;
3714 unsigned IOCAP1
: 1;
3715 unsigned IOCAP2
: 1;
3716 unsigned IOCAP3
: 1;
3717 unsigned IOCAP4
: 1;
3718 unsigned IOCAP5
: 1;
3730 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
3732 #define _IOCAP0 0x01
3733 #define _IOCAP1 0x02
3734 #define _IOCAP2 0x04
3735 #define _IOCAP3 0x08
3736 #define _IOCAP4 0x10
3737 #define _IOCAP5 0x20
3739 //==============================================================================
3742 //==============================================================================
3745 extern __at(0x0392) __sfr IOCAN
;
3751 unsigned IOCAN0
: 1;
3752 unsigned IOCAN1
: 1;
3753 unsigned IOCAN2
: 1;
3754 unsigned IOCAN3
: 1;
3755 unsigned IOCAN4
: 1;
3756 unsigned IOCAN5
: 1;
3768 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
3770 #define _IOCAN0 0x01
3771 #define _IOCAN1 0x02
3772 #define _IOCAN2 0x04
3773 #define _IOCAN3 0x08
3774 #define _IOCAN4 0x10
3775 #define _IOCAN5 0x20
3777 //==============================================================================
3780 //==============================================================================
3783 extern __at(0x0393) __sfr IOCAF
;
3789 unsigned IOCAF0
: 1;
3790 unsigned IOCAF1
: 1;
3791 unsigned IOCAF2
: 1;
3792 unsigned IOCAF3
: 1;
3793 unsigned IOCAF4
: 1;
3794 unsigned IOCAF5
: 1;
3806 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
3808 #define _IOCAF0 0x01
3809 #define _IOCAF1 0x02
3810 #define _IOCAF2 0x04
3811 #define _IOCAF3 0x08
3812 #define _IOCAF4 0x10
3813 #define _IOCAF5 0x20
3815 //==============================================================================
3818 //==============================================================================
3821 extern __at(0x0394) __sfr IOCBP
;
3829 unsigned IOCBP4
: 1;
3830 unsigned IOCBP5
: 1;
3831 unsigned IOCBP6
: 1;
3832 unsigned IOCBP7
: 1;
3835 extern __at(0x0394) volatile __IOCBPbits_t IOCBPbits
;
3837 #define _IOCBP4 0x10
3838 #define _IOCBP5 0x20
3839 #define _IOCBP6 0x40
3840 #define _IOCBP7 0x80
3842 //==============================================================================
3845 //==============================================================================
3848 extern __at(0x0395) __sfr IOCBN
;
3856 unsigned IOCBN4
: 1;
3857 unsigned IOCBN5
: 1;
3858 unsigned IOCBN6
: 1;
3859 unsigned IOCBN7
: 1;
3862 extern __at(0x0395) volatile __IOCBNbits_t IOCBNbits
;
3864 #define _IOCBN4 0x10
3865 #define _IOCBN5 0x20
3866 #define _IOCBN6 0x40
3867 #define _IOCBN7 0x80
3869 //==============================================================================
3872 //==============================================================================
3875 extern __at(0x0396) __sfr IOCBF
;
3883 unsigned IOCBF4
: 1;
3884 unsigned IOCBF5
: 1;
3885 unsigned IOCBF6
: 1;
3886 unsigned IOCBF7
: 1;
3889 extern __at(0x0396) volatile __IOCBFbits_t IOCBFbits
;
3891 #define _IOCBF4 0x10
3892 #define _IOCBF5 0x20
3893 #define _IOCBF6 0x40
3894 #define _IOCBF7 0x80
3896 //==============================================================================
3899 //==============================================================================
3902 extern __at(0x0397) __sfr IOCCP
;
3906 unsigned IOCCP0
: 1;
3907 unsigned IOCCP1
: 1;
3908 unsigned IOCCP2
: 1;
3909 unsigned IOCCP3
: 1;
3910 unsigned IOCCP4
: 1;
3911 unsigned IOCCP5
: 1;
3912 unsigned IOCCP6
: 1;
3913 unsigned IOCCP7
: 1;
3916 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
3918 #define _IOCCP0 0x01
3919 #define _IOCCP1 0x02
3920 #define _IOCCP2 0x04
3921 #define _IOCCP3 0x08
3922 #define _IOCCP4 0x10
3923 #define _IOCCP5 0x20
3924 #define _IOCCP6 0x40
3925 #define _IOCCP7 0x80
3927 //==============================================================================
3930 //==============================================================================
3933 extern __at(0x0398) __sfr IOCCN
;
3937 unsigned IOCCN0
: 1;
3938 unsigned IOCCN1
: 1;
3939 unsigned IOCCN2
: 1;
3940 unsigned IOCCN3
: 1;
3941 unsigned IOCCN4
: 1;
3942 unsigned IOCCN5
: 1;
3943 unsigned IOCCN6
: 1;
3944 unsigned IOCCN7
: 1;
3947 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
3949 #define _IOCCN0 0x01
3950 #define _IOCCN1 0x02
3951 #define _IOCCN2 0x04
3952 #define _IOCCN3 0x08
3953 #define _IOCCN4 0x10
3954 #define _IOCCN5 0x20
3955 #define _IOCCN6 0x40
3956 #define _IOCCN7 0x80
3958 //==============================================================================
3961 //==============================================================================
3964 extern __at(0x0399) __sfr IOCCF
;
3968 unsigned IOCCF0
: 1;
3969 unsigned IOCCF1
: 1;
3970 unsigned IOCCF2
: 1;
3971 unsigned IOCCF3
: 1;
3972 unsigned IOCCF4
: 1;
3973 unsigned IOCCF5
: 1;
3974 unsigned IOCCF6
: 1;
3975 unsigned IOCCF7
: 1;
3978 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
3980 #define _IOCCF0 0x01
3981 #define _IOCCF1 0x02
3982 #define _IOCCF2 0x04
3983 #define _IOCCF3 0x08
3984 #define _IOCCF4 0x10
3985 #define _IOCCF5 0x20
3986 #define _IOCCF6 0x40
3987 #define _IOCCF7 0x80
3989 //==============================================================================
3992 //==============================================================================
3995 extern __at(0x039A) __sfr CLKRCON
;
4001 unsigned CLKRDIV0
: 1;
4002 unsigned CLKRDIV1
: 1;
4003 unsigned CLKRDIV2
: 1;
4004 unsigned CLKRDC0
: 1;
4005 unsigned CLKRDC1
: 1;
4008 unsigned CLKREN
: 1;
4013 unsigned CLKRDIV
: 3;
4020 unsigned CLKRDC
: 2;
4025 extern __at(0x039A) volatile __CLKRCONbits_t CLKRCONbits
;
4027 #define _CLKRDIV0 0x01
4028 #define _CLKRDIV1 0x02
4029 #define _CLKRDIV2 0x04
4030 #define _CLKRDC0 0x08
4031 #define _CLKRDC1 0x10
4032 #define _CLKREN 0x80
4034 //==============================================================================
4037 //==============================================================================
4040 extern __at(0x039C) __sfr MDCON
;
4048 unsigned MDOPOL
: 1;
4054 extern __at(0x039C) volatile __MDCONbits_t MDCONbits
;
4058 #define _MDOPOL 0x10
4061 //==============================================================================
4064 //==============================================================================
4067 extern __at(0x039D) __sfr MDSRC
;
4090 extern __at(0x039D) volatile __MDSRCbits_t MDSRCbits
;
4097 //==============================================================================
4100 //==============================================================================
4103 extern __at(0x039E) __sfr MDCARH
;
4114 unsigned MDCHSYNC
: 1;
4115 unsigned MDCHPOL
: 1;
4126 extern __at(0x039E) volatile __MDCARHbits_t MDCARHbits
;
4132 #define _MDCHSYNC 0x20
4133 #define _MDCHPOL 0x40
4135 //==============================================================================
4138 //==============================================================================
4141 extern __at(0x039F) __sfr MDCARL
;
4152 unsigned MDCLSYNC
: 1;
4153 unsigned MDCLPOL
: 1;
4164 extern __at(0x039F) volatile __MDCARLbits_t MDCARLbits
;
4170 #define _MDCLSYNC 0x20
4171 #define _MDCLPOL 0x40
4173 //==============================================================================
4176 //==============================================================================
4179 extern __at(0x040C) __sfr CCDNA
;
4183 unsigned CCDNA0
: 1;
4184 unsigned CCDNA1
: 1;
4185 unsigned CCDNA2
: 1;
4187 unsigned CCDNA4
: 1;
4188 unsigned CCDNA5
: 1;
4193 extern __at(0x040C) volatile __CCDNAbits_t CCDNAbits
;
4195 #define _CCDNA0 0x01
4196 #define _CCDNA1 0x02
4197 #define _CCDNA2 0x04
4198 #define _CCDNA4 0x10
4199 #define _CCDNA5 0x20
4201 //==============================================================================
4204 //==============================================================================
4207 extern __at(0x040D) __sfr CCDNB
;
4215 unsigned CCDNB4
: 1;
4216 unsigned CCDNB5
: 1;
4217 unsigned CCDNB6
: 1;
4218 unsigned CCDNB7
: 1;
4221 extern __at(0x040D) volatile __CCDNBbits_t CCDNBbits
;
4223 #define _CCDNB4 0x10
4224 #define _CCDNB5 0x20
4225 #define _CCDNB6 0x40
4226 #define _CCDNB7 0x80
4228 //==============================================================================
4231 //==============================================================================
4234 extern __at(0x040E) __sfr CCDNC
;
4238 unsigned CCDNC0
: 1;
4239 unsigned CCDNC1
: 1;
4240 unsigned CCDNC2
: 1;
4241 unsigned CCDNC3
: 1;
4242 unsigned CCDNC4
: 1;
4243 unsigned CCDNC5
: 1;
4244 unsigned CCDNC6
: 1;
4245 unsigned CCDNC7
: 1;
4248 extern __at(0x040E) volatile __CCDNCbits_t CCDNCbits
;
4250 #define _CCDNC0 0x01
4251 #define _CCDNC1 0x02
4252 #define _CCDNC2 0x04
4253 #define _CCDNC3 0x08
4254 #define _CCDNC4 0x10
4255 #define _CCDNC5 0x20
4256 #define _CCDNC6 0x40
4257 #define _CCDNC7 0x80
4259 //==============================================================================
4261 extern __at(0x0411) __sfr TMR3
;
4262 extern __at(0x0411) __sfr TMR3L
;
4263 extern __at(0x0412) __sfr TMR3H
;
4265 //==============================================================================
4268 extern __at(0x0413) __sfr T3CON
;
4274 unsigned TMR3ON
: 1;
4276 unsigned T3SYNC
: 1;
4277 unsigned T3SOSC
: 1;
4278 unsigned T3CKPS0
: 1;
4279 unsigned T3CKPS1
: 1;
4280 unsigned TMR3CS0
: 1;
4281 unsigned TMR3CS1
: 1;
4287 unsigned T3CKPS
: 2;
4294 unsigned TMR3CS
: 2;
4298 extern __at(0x0413) volatile __T3CONbits_t T3CONbits
;
4300 #define _TMR3ON 0x01
4301 #define _T3SYNC 0x04
4302 #define _T3SOSC 0x08
4303 #define _T3CKPS0 0x10
4304 #define _T3CKPS1 0x20
4305 #define _TMR3CS0 0x40
4306 #define _TMR3CS1 0x80
4308 //==============================================================================
4311 //==============================================================================
4314 extern __at(0x0414) __sfr T3GCON
;
4320 unsigned T3GSS0
: 1;
4321 unsigned T3GSS1
: 1;
4322 unsigned T3GVAL
: 1;
4323 unsigned T3GGO_NOT_DONE
: 1;
4324 unsigned T3GSPM
: 1;
4326 unsigned T3GPOL
: 1;
4327 unsigned TMR3GE
: 1;
4337 extern __at(0x0414) volatile __T3GCONbits_t T3GCONbits
;
4339 #define _T3GSS0 0x01
4340 #define _T3GSS1 0x02
4341 #define _T3GVAL 0x04
4342 #define _T3GGO_NOT_DONE 0x08
4343 #define _T3GSPM 0x10
4345 #define _T3GPOL 0x40
4346 #define _TMR3GE 0x80
4348 //==============================================================================
4350 extern __at(0x0415) __sfr TMR4
;
4351 extern __at(0x0416) __sfr PR4
;
4353 //==============================================================================
4356 extern __at(0x0417) __sfr T4CON
;
4362 unsigned T4CKPS0
: 1;
4363 unsigned T4CKPS1
: 1;
4364 unsigned TMR4ON
: 1;
4365 unsigned T4OUTPS0
: 1;
4366 unsigned T4OUTPS1
: 1;
4367 unsigned T4OUTPS2
: 1;
4368 unsigned T4OUTPS3
: 1;
4374 unsigned T4CKPS
: 2;
4381 unsigned T4OUTPS
: 4;
4386 extern __at(0x0417) volatile __T4CONbits_t T4CONbits
;
4388 #define _T4CKPS0 0x01
4389 #define _T4CKPS1 0x02
4390 #define _TMR4ON 0x04
4391 #define _T4OUTPS0 0x08
4392 #define _T4OUTPS1 0x10
4393 #define _T4OUTPS2 0x20
4394 #define _T4OUTPS3 0x40
4396 //==============================================================================
4398 extern __at(0x0418) __sfr TMR5
;
4399 extern __at(0x0418) __sfr TMR5L
;
4400 extern __at(0x0419) __sfr TMR5H
;
4402 //==============================================================================
4405 extern __at(0x041A) __sfr T5CON
;
4411 unsigned TMR5ON
: 1;
4413 unsigned T5SYNC
: 1;
4414 unsigned T5SOSC
: 1;
4415 unsigned T5CKPS0
: 1;
4416 unsigned T5CKPS1
: 1;
4417 unsigned TMR5CS0
: 1;
4418 unsigned TMR5CS1
: 1;
4424 unsigned T5CKPS
: 2;
4431 unsigned TMR5CS
: 2;
4435 extern __at(0x041A) volatile __T5CONbits_t T5CONbits
;
4437 #define _TMR5ON 0x01
4438 #define _T5SYNC 0x04
4439 #define _T5SOSC 0x08
4440 #define _T5CKPS0 0x10
4441 #define _T5CKPS1 0x20
4442 #define _TMR5CS0 0x40
4443 #define _TMR5CS1 0x80
4445 //==============================================================================
4448 //==============================================================================
4451 extern __at(0x041B) __sfr T5GCON
;
4457 unsigned T5GSS0
: 1;
4458 unsigned T5GSS1
: 1;
4459 unsigned T5GVAL
: 1;
4460 unsigned T5GGO_NOT_DONE
: 1;
4461 unsigned T5GSPM
: 1;
4463 unsigned T5GPOL
: 1;
4464 unsigned TMR5GE
: 1;
4474 extern __at(0x041B) volatile __T5GCONbits_t T5GCONbits
;
4476 #define _T5GSS0 0x01
4477 #define _T5GSS1 0x02
4478 #define _T5GVAL 0x04
4479 #define _T5GGO_NOT_DONE 0x08
4480 #define _T5GSPM 0x10
4482 #define _T5GPOL 0x40
4483 #define _TMR5GE 0x80
4485 //==============================================================================
4487 extern __at(0x041C) __sfr TMR6
;
4488 extern __at(0x041D) __sfr PR6
;
4490 //==============================================================================
4493 extern __at(0x041E) __sfr T6CON
;
4499 unsigned T6CKPS0
: 1;
4500 unsigned T6CKPS1
: 1;
4501 unsigned TMR6ON
: 1;
4502 unsigned T6OUTPS0
: 1;
4503 unsigned T6OUTPS1
: 1;
4504 unsigned T6OUTPS2
: 1;
4505 unsigned T6OUTPS3
: 1;
4511 unsigned T6CKPS
: 2;
4518 unsigned T6OUTPS
: 4;
4523 extern __at(0x041E) volatile __T6CONbits_t T6CONbits
;
4525 #define _T6CKPS0 0x01
4526 #define _T6CKPS1 0x02
4527 #define _TMR6ON 0x04
4528 #define _T6OUTPS0 0x08
4529 #define _T6OUTPS1 0x10
4530 #define _T6OUTPS2 0x20
4531 #define _T6OUTPS3 0x40
4533 //==============================================================================
4536 //==============================================================================
4539 extern __at(0x041F) __sfr CCDCON
;
4562 extern __at(0x041F) volatile __CCDCONbits_t CCDCONbits
;
4568 //==============================================================================
4571 //==============================================================================
4574 extern __at(0x048C) __sfr CCDPA
;
4578 unsigned CCDPA0
: 1;
4579 unsigned CCDPA1
: 1;
4580 unsigned CCDPA2
: 1;
4582 unsigned CCDPA4
: 1;
4583 unsigned CCDPA5
: 1;
4588 extern __at(0x048C) volatile __CCDPAbits_t CCDPAbits
;
4590 #define _CCDPA0 0x01
4591 #define _CCDPA1 0x02
4592 #define _CCDPA2 0x04
4593 #define _CCDPA4 0x10
4594 #define _CCDPA5 0x20
4596 //==============================================================================
4599 //==============================================================================
4602 extern __at(0x048D) __sfr CCDPB
;
4610 unsigned CCDPB4
: 1;
4611 unsigned CCDPB5
: 1;
4612 unsigned CCDPB6
: 1;
4613 unsigned CCDPB7
: 1;
4616 extern __at(0x048D) volatile __CCDPBbits_t CCDPBbits
;
4618 #define _CCDPB4 0x10
4619 #define _CCDPB5 0x20
4620 #define _CCDPB6 0x40
4621 #define _CCDPB7 0x80
4623 //==============================================================================
4626 //==============================================================================
4629 extern __at(0x048E) __sfr CCDPC
;
4633 unsigned CCDPC0
: 1;
4634 unsigned CCDPC1
: 1;
4635 unsigned CCDPC2
: 1;
4636 unsigned CCDPC3
: 1;
4637 unsigned CCDPC4
: 1;
4638 unsigned CCDPC5
: 1;
4639 unsigned CCDPC6
: 1;
4640 unsigned CCDPC7
: 1;
4643 extern __at(0x048E) volatile __CCDPCbits_t CCDPCbits
;
4645 #define _CCDPC0 0x01
4646 #define _CCDPC1 0x02
4647 #define _CCDPC2 0x04
4648 #define _CCDPC3 0x08
4649 #define _CCDPC4 0x10
4650 #define _CCDPC5 0x20
4651 #define _CCDPC6 0x40
4652 #define _CCDPC7 0x80
4654 //==============================================================================
4656 extern __at(0x0498) __sfr NCO1ACC
;
4657 extern __at(0x0498) __sfr NCO1ACCL
;
4658 extern __at(0x0499) __sfr NCO1ACCH
;
4659 extern __at(0x049A) __sfr NCO1ACCU
;
4660 extern __at(0x049B) __sfr NCO1INC
;
4661 extern __at(0x049B) __sfr NCO1INCL
;
4662 extern __at(0x049C) __sfr NCO1INCH
;
4663 extern __at(0x049D) __sfr NCO1INCU
;
4665 //==============================================================================
4668 extern __at(0x049E) __sfr NCO1CON
;
4682 extern __at(0x049E) volatile __NCO1CONbits_t NCO1CONbits
;
4689 //==============================================================================
4691 extern __at(0x049F) __sfr NCO1CLK
;
4693 //==============================================================================
4696 extern __at(0x0617) __sfr PWM5DCL
;
4708 unsigned PWM5DCL0
: 1;
4709 unsigned PWM5DCL1
: 1;
4715 unsigned PWM5DCL
: 2;
4719 extern __at(0x0617) volatile __PWM5DCLbits_t PWM5DCLbits
;
4721 #define _PWM5DCL0 0x40
4722 #define _PWM5DCL1 0x80
4724 //==============================================================================
4727 //==============================================================================
4730 extern __at(0x0618) __sfr PWM5DCH
;
4734 unsigned PWM5DCH0
: 1;
4735 unsigned PWM5DCH1
: 1;
4736 unsigned PWM5DCH2
: 1;
4737 unsigned PWM5DCH3
: 1;
4738 unsigned PWM5DCH4
: 1;
4739 unsigned PWM5DCH5
: 1;
4740 unsigned PWM5DCH6
: 1;
4741 unsigned PWM5DCH7
: 1;
4744 extern __at(0x0618) volatile __PWM5DCHbits_t PWM5DCHbits
;
4746 #define _PWM5DCH0 0x01
4747 #define _PWM5DCH1 0x02
4748 #define _PWM5DCH2 0x04
4749 #define _PWM5DCH3 0x08
4750 #define _PWM5DCH4 0x10
4751 #define _PWM5DCH5 0x20
4752 #define _PWM5DCH6 0x40
4753 #define _PWM5DCH7 0x80
4755 //==============================================================================
4758 //==============================================================================
4761 extern __at(0x0619) __sfr PWM5CON
;
4769 unsigned PWM5POL
: 1;
4770 unsigned PWM5OUT
: 1;
4772 unsigned PWM5EN
: 1;
4775 extern __at(0x0619) volatile __PWM5CONbits_t PWM5CONbits
;
4777 #define _PWM5POL 0x10
4778 #define _PWM5OUT 0x20
4779 #define _PWM5EN 0x80
4781 //==============================================================================
4784 //==============================================================================
4787 extern __at(0x0619) __sfr PWM5CON0
;
4795 unsigned PWM5POL
: 1;
4796 unsigned PWM5OUT
: 1;
4798 unsigned PWM5EN
: 1;
4801 extern __at(0x0619) volatile __PWM5CON0bits_t PWM5CON0bits
;
4803 #define _PWM5CON0_PWM5POL 0x10
4804 #define _PWM5CON0_PWM5OUT 0x20
4805 #define _PWM5CON0_PWM5EN 0x80
4807 //==============================================================================
4810 //==============================================================================
4813 extern __at(0x061A) __sfr PWM6DCL
;
4825 unsigned PWM6DCL0
: 1;
4826 unsigned PWM6DCL1
: 1;
4832 unsigned PWM6DCL
: 2;
4836 extern __at(0x061A) volatile __PWM6DCLbits_t PWM6DCLbits
;
4838 #define _PWM6DCL0 0x40
4839 #define _PWM6DCL1 0x80
4841 //==============================================================================
4844 //==============================================================================
4847 extern __at(0x061B) __sfr PWM6DCH
;
4851 unsigned PWM6DCH0
: 1;
4852 unsigned PWM6DCH1
: 1;
4853 unsigned PWM6DCH2
: 1;
4854 unsigned PWM6DCH3
: 1;
4855 unsigned PWM6DCH4
: 1;
4856 unsigned PWM6DCH5
: 1;
4857 unsigned PWM6DCH6
: 1;
4858 unsigned PWM6DCH7
: 1;
4861 extern __at(0x061B) volatile __PWM6DCHbits_t PWM6DCHbits
;
4863 #define _PWM6DCH0 0x01
4864 #define _PWM6DCH1 0x02
4865 #define _PWM6DCH2 0x04
4866 #define _PWM6DCH3 0x08
4867 #define _PWM6DCH4 0x10
4868 #define _PWM6DCH5 0x20
4869 #define _PWM6DCH6 0x40
4870 #define _PWM6DCH7 0x80
4872 //==============================================================================
4875 //==============================================================================
4878 extern __at(0x061C) __sfr PWM6CON
;
4886 unsigned PWM6POL
: 1;
4887 unsigned PWM6OUT
: 1;
4889 unsigned PWM6EN
: 1;
4892 extern __at(0x061C) volatile __PWM6CONbits_t PWM6CONbits
;
4894 #define _PWM6POL 0x10
4895 #define _PWM6OUT 0x20
4896 #define _PWM6EN 0x80
4898 //==============================================================================
4901 //==============================================================================
4904 extern __at(0x061C) __sfr PWM6CON0
;
4912 unsigned PWM6POL
: 1;
4913 unsigned PWM6OUT
: 1;
4915 unsigned PWM6EN
: 1;
4918 extern __at(0x061C) volatile __PWM6CON0bits_t PWM6CON0bits
;
4920 #define _PWM6CON0_PWM6POL 0x10
4921 #define _PWM6CON0_PWM6OUT 0x20
4922 #define _PWM6CON0_PWM6EN 0x80
4924 //==============================================================================
4927 //==============================================================================
4930 extern __at(0x061F) __sfr PWMTMRS
;
4936 unsigned P5TSEL0
: 1;
4937 unsigned P5TSEL1
: 1;
4938 unsigned P6TSEL0
: 1;
4939 unsigned P6TSEL1
: 1;
4948 unsigned P5TSEL
: 2;
4955 unsigned P6TSEL
: 2;
4960 extern __at(0x061F) volatile __PWMTMRSbits_t PWMTMRSbits
;
4962 #define _P5TSEL0 0x01
4963 #define _P5TSEL1 0x02
4964 #define _P6TSEL0 0x04
4965 #define _P6TSEL1 0x08
4967 //==============================================================================
4970 //==============================================================================
4973 extern __at(0x0691) __sfr CWG1CLKCON
;
4991 unsigned CWG1CS
: 1;
5000 } __CWG1CLKCONbits_t
;
5002 extern __at(0x0691) volatile __CWG1CLKCONbits_t CWG1CLKCONbits
;
5005 #define _CWG1CS 0x01
5007 //==============================================================================
5010 //==============================================================================
5013 extern __at(0x0692) __sfr CWG1DAT
;
5019 unsigned CWG1DAT0
: 1;
5020 unsigned CWG1DAT1
: 1;
5021 unsigned CWG1DAT2
: 1;
5022 unsigned CWG1DAT3
: 1;
5031 unsigned CWG1DAT
: 4;
5036 extern __at(0x0692) volatile __CWG1DATbits_t CWG1DATbits
;
5038 #define _CWG1DAT0 0x01
5039 #define _CWG1DAT1 0x02
5040 #define _CWG1DAT2 0x04
5041 #define _CWG1DAT3 0x08
5043 //==============================================================================
5046 //==============================================================================
5049 extern __at(0x0693) __sfr CWG1DBR
;
5067 unsigned CWG1DBR0
: 1;
5068 unsigned CWG1DBR1
: 1;
5069 unsigned CWG1DBR2
: 1;
5070 unsigned CWG1DBR3
: 1;
5071 unsigned CWG1DBR4
: 1;
5072 unsigned CWG1DBR5
: 1;
5085 unsigned CWG1DBR
: 6;
5090 extern __at(0x0693) volatile __CWG1DBRbits_t CWG1DBRbits
;
5093 #define _CWG1DBR0 0x01
5095 #define _CWG1DBR1 0x02
5097 #define _CWG1DBR2 0x04
5099 #define _CWG1DBR3 0x08
5101 #define _CWG1DBR4 0x10
5103 #define _CWG1DBR5 0x20
5105 //==============================================================================
5108 //==============================================================================
5111 extern __at(0x0694) __sfr CWG1DBF
;
5129 unsigned CWG1DBF0
: 1;
5130 unsigned CWG1DBF1
: 1;
5131 unsigned CWG1DBF2
: 1;
5132 unsigned CWG1DBF3
: 1;
5133 unsigned CWG1DBF4
: 1;
5134 unsigned CWG1DBF5
: 1;
5141 unsigned CWG1DBF
: 6;
5152 extern __at(0x0694) volatile __CWG1DBFbits_t CWG1DBFbits
;
5155 #define _CWG1DBF0 0x01
5157 #define _CWG1DBF1 0x02
5159 #define _CWG1DBF2 0x04
5161 #define _CWG1DBF3 0x08
5163 #define _CWG1DBF4 0x10
5165 #define _CWG1DBF5 0x20
5167 //==============================================================================
5170 //==============================================================================
5173 extern __at(0x0695) __sfr CWG1CON0
;
5191 unsigned CWG1MODE0
: 1;
5192 unsigned CWG1MODE1
: 1;
5193 unsigned CWG1MODE2
: 1;
5197 unsigned CWG1LD
: 1;
5210 unsigned CWG1EN
: 1;
5221 unsigned CWG1MODE
: 3;
5226 extern __at(0x0695) volatile __CWG1CON0bits_t CWG1CON0bits
;
5228 #define _CWG1CON0_MODE0 0x01
5229 #define _CWG1CON0_CWG1MODE0 0x01
5230 #define _CWG1CON0_MODE1 0x02
5231 #define _CWG1CON0_CWG1MODE1 0x02
5232 #define _CWG1CON0_MODE2 0x04
5233 #define _CWG1CON0_CWG1MODE2 0x04
5234 #define _CWG1CON0_LD 0x40
5235 #define _CWG1CON0_CWG1LD 0x40
5236 #define _CWG1CON0_EN 0x80
5237 #define _CWG1CON0_G1EN 0x80
5238 #define _CWG1CON0_CWG1EN 0x80
5240 //==============================================================================
5243 //==============================================================================
5246 extern __at(0x0696) __sfr CWG1CON1
;
5264 unsigned CWG1POLA
: 1;
5265 unsigned CWG1POLB
: 1;
5266 unsigned CWG1POLC
: 1;
5267 unsigned CWG1POLD
: 1;
5269 unsigned CWG1IN
: 1;
5275 extern __at(0x0696) volatile __CWG1CON1bits_t CWG1CON1bits
;
5278 #define _CWG1POLA 0x01
5280 #define _CWG1POLB 0x02
5282 #define _CWG1POLC 0x04
5284 #define _CWG1POLD 0x08
5286 #define _CWG1IN 0x20
5288 //==============================================================================
5291 //==============================================================================
5294 extern __at(0x0697) __sfr CWG1AS0
;
5307 unsigned SHUTDOWN
: 1;
5314 unsigned CWG1LSAC0
: 1;
5315 unsigned CWG1LSAC1
: 1;
5316 unsigned CWG1LSBD0
: 1;
5317 unsigned CWG1LSBD1
: 1;
5318 unsigned CWG1REN
: 1;
5319 unsigned CWG1SHUTDOWN
: 1;
5332 unsigned CWG1LSAC
: 2;
5346 unsigned CWG1LSBD
: 2;
5351 extern __at(0x0697) volatile __CWG1AS0bits_t CWG1AS0bits
;
5354 #define _CWG1LSAC0 0x04
5356 #define _CWG1LSAC1 0x08
5358 #define _CWG1LSBD0 0x10
5360 #define _CWG1LSBD1 0x20
5362 #define _CWG1REN 0x40
5363 #define _SHUTDOWN 0x80
5364 #define _CWG1SHUTDOWN 0x80
5366 //==============================================================================
5369 //==============================================================================
5372 extern __at(0x0698) __sfr CWG1AS1
;
5386 extern __at(0x0698) volatile __CWG1AS1bits_t CWG1AS1bits
;
5394 //==============================================================================
5397 //==============================================================================
5400 extern __at(0x0699) __sfr CWG1STR
;
5418 unsigned CWG1STRA
: 1;
5419 unsigned CWG1STRB
: 1;
5420 unsigned CWG1STRC
: 1;
5421 unsigned CWG1STRD
: 1;
5422 unsigned CWG1OVRA
: 1;
5423 unsigned CWG1OVRB
: 1;
5424 unsigned CWG1OVRC
: 1;
5425 unsigned CWG1OVRD
: 1;
5429 extern __at(0x0699) volatile __CWG1STRbits_t CWG1STRbits
;
5432 #define _CWG1STRA 0x01
5434 #define _CWG1STRB 0x02
5436 #define _CWG1STRC 0x04
5438 #define _CWG1STRD 0x08
5440 #define _CWG1OVRA 0x10
5442 #define _CWG1OVRB 0x20
5444 #define _CWG1OVRC 0x40
5446 #define _CWG1OVRD 0x80
5448 //==============================================================================
5451 //==============================================================================
5454 extern __at(0x0711) __sfr CWG2CLKCON
;
5472 unsigned CWG2CS
: 1;
5481 } __CWG2CLKCONbits_t
;
5483 extern __at(0x0711) volatile __CWG2CLKCONbits_t CWG2CLKCONbits
;
5485 #define _CWG2CLKCON_CS 0x01
5486 #define _CWG2CLKCON_CWG2CS 0x01
5488 //==============================================================================
5491 //==============================================================================
5494 extern __at(0x0712) __sfr CWG2DAT
;
5500 unsigned CWG2DAT0
: 1;
5501 unsigned CWG2DAT1
: 1;
5502 unsigned CWG2DAT2
: 1;
5503 unsigned CWG2DAT3
: 1;
5512 unsigned CWG2DAT
: 4;
5517 extern __at(0x0712) volatile __CWG2DATbits_t CWG2DATbits
;
5519 #define _CWG2DAT0 0x01
5520 #define _CWG2DAT1 0x02
5521 #define _CWG2DAT2 0x04
5522 #define _CWG2DAT3 0x08
5524 //==============================================================================
5527 //==============================================================================
5530 extern __at(0x0713) __sfr CWG2DBR
;
5548 unsigned CWG2DBR0
: 1;
5549 unsigned CWG2DBR1
: 1;
5550 unsigned CWG2DBR2
: 1;
5551 unsigned CWG2DBR3
: 1;
5552 unsigned CWG2DBR4
: 1;
5553 unsigned CWG2DBR5
: 1;
5560 unsigned CWG2DBR
: 6;
5571 extern __at(0x0713) volatile __CWG2DBRbits_t CWG2DBRbits
;
5573 #define _CWG2DBR_DBR0 0x01
5574 #define _CWG2DBR_CWG2DBR0 0x01
5575 #define _CWG2DBR_DBR1 0x02
5576 #define _CWG2DBR_CWG2DBR1 0x02
5577 #define _CWG2DBR_DBR2 0x04
5578 #define _CWG2DBR_CWG2DBR2 0x04
5579 #define _CWG2DBR_DBR3 0x08
5580 #define _CWG2DBR_CWG2DBR3 0x08
5581 #define _CWG2DBR_DBR4 0x10
5582 #define _CWG2DBR_CWG2DBR4 0x10
5583 #define _CWG2DBR_DBR5 0x20
5584 #define _CWG2DBR_CWG2DBR5 0x20
5586 //==============================================================================
5589 //==============================================================================
5592 extern __at(0x0714) __sfr CWG2DBF
;
5610 unsigned CWG2DBF0
: 1;
5611 unsigned CWG2DBF1
: 1;
5612 unsigned CWG2DBF2
: 1;
5613 unsigned CWG2DBF3
: 1;
5614 unsigned CWG2DBF4
: 1;
5615 unsigned CWG2DBF5
: 1;
5622 unsigned CWG2DBF
: 6;
5633 extern __at(0x0714) volatile __CWG2DBFbits_t CWG2DBFbits
;
5635 #define _CWG2DBF_DBF0 0x01
5636 #define _CWG2DBF_CWG2DBF0 0x01
5637 #define _CWG2DBF_DBF1 0x02
5638 #define _CWG2DBF_CWG2DBF1 0x02
5639 #define _CWG2DBF_DBF2 0x04
5640 #define _CWG2DBF_CWG2DBF2 0x04
5641 #define _CWG2DBF_DBF3 0x08
5642 #define _CWG2DBF_CWG2DBF3 0x08
5643 #define _CWG2DBF_DBF4 0x10
5644 #define _CWG2DBF_CWG2DBF4 0x10
5645 #define _CWG2DBF_DBF5 0x20
5646 #define _CWG2DBF_CWG2DBF5 0x20
5648 //==============================================================================
5651 //==============================================================================
5654 extern __at(0x0715) __sfr CWG2CON0
;
5672 unsigned CWG2MODE0
: 1;
5673 unsigned CWG2MODE1
: 1;
5674 unsigned CWG2MODE2
: 1;
5678 unsigned CWG2LD
: 1;
5691 unsigned CWG2EN
: 1;
5696 unsigned CWG2MODE
: 3;
5707 extern __at(0x0715) volatile __CWG2CON0bits_t CWG2CON0bits
;
5709 #define _CWG2CON0_MODE0 0x01
5710 #define _CWG2CON0_CWG2MODE0 0x01
5711 #define _CWG2CON0_MODE1 0x02
5712 #define _CWG2CON0_CWG2MODE1 0x02
5713 #define _CWG2CON0_MODE2 0x04
5714 #define _CWG2CON0_CWG2MODE2 0x04
5715 #define _CWG2CON0_LD 0x40
5716 #define _CWG2CON0_CWG2LD 0x40
5717 #define _CWG2CON0_EN 0x80
5718 #define _CWG2CON0_G2EN 0x80
5719 #define _CWG2CON0_CWG2EN 0x80
5721 //==============================================================================
5724 //==============================================================================
5727 extern __at(0x0716) __sfr CWG2CON1
;
5745 unsigned CWG2POLA
: 1;
5746 unsigned CWG2POLB
: 1;
5747 unsigned CWG2POLC
: 1;
5748 unsigned CWG2POLD
: 1;
5750 unsigned CWG2IN
: 1;
5756 extern __at(0x0716) volatile __CWG2CON1bits_t CWG2CON1bits
;
5758 #define _CWG2CON1_POLA 0x01
5759 #define _CWG2CON1_CWG2POLA 0x01
5760 #define _CWG2CON1_POLB 0x02
5761 #define _CWG2CON1_CWG2POLB 0x02
5762 #define _CWG2CON1_POLC 0x04
5763 #define _CWG2CON1_CWG2POLC 0x04
5764 #define _CWG2CON1_POLD 0x08
5765 #define _CWG2CON1_CWG2POLD 0x08
5766 #define _CWG2CON1_IN 0x20
5767 #define _CWG2CON1_CWG2IN 0x20
5769 //==============================================================================
5772 //==============================================================================
5775 extern __at(0x0717) __sfr CWG2AS0
;
5788 unsigned SHUTDOWN
: 1;
5795 unsigned CWG2LSAC0
: 1;
5796 unsigned CWG2LSAC1
: 1;
5797 unsigned CWG2LSBD0
: 1;
5798 unsigned CWG2LSBD1
: 1;
5799 unsigned CWG2REN
: 1;
5800 unsigned CWG2SHUTDOWN
: 1;
5806 unsigned CWG2LSAC
: 2;
5827 unsigned CWG2LSBD
: 2;
5832 extern __at(0x0717) volatile __CWG2AS0bits_t CWG2AS0bits
;
5834 #define _CWG2AS0_LSAC0 0x04
5835 #define _CWG2AS0_CWG2LSAC0 0x04
5836 #define _CWG2AS0_LSAC1 0x08
5837 #define _CWG2AS0_CWG2LSAC1 0x08
5838 #define _CWG2AS0_LSBD0 0x10
5839 #define _CWG2AS0_CWG2LSBD0 0x10
5840 #define _CWG2AS0_LSBD1 0x20
5841 #define _CWG2AS0_CWG2LSBD1 0x20
5842 #define _CWG2AS0_REN 0x40
5843 #define _CWG2AS0_CWG2REN 0x40
5844 #define _CWG2AS0_SHUTDOWN 0x80
5845 #define _CWG2AS0_CWG2SHUTDOWN 0x80
5847 //==============================================================================
5850 //==============================================================================
5853 extern __at(0x0718) __sfr CWG2AS1
;
5867 extern __at(0x0718) volatile __CWG2AS1bits_t CWG2AS1bits
;
5869 #define _CWG2AS1_AS0E 0x01
5870 #define _CWG2AS1_AS1E 0x02
5871 #define _CWG2AS1_AS2E 0x04
5872 #define _CWG2AS1_AS3E 0x08
5873 #define _CWG2AS1_AS4E 0x10
5875 //==============================================================================
5878 //==============================================================================
5881 extern __at(0x0719) __sfr CWG2STR
;
5899 unsigned CWG2STRA
: 1;
5900 unsigned CWG2STRB
: 1;
5901 unsigned CWG2STRC
: 1;
5902 unsigned CWG2STRD
: 1;
5903 unsigned CWG2OVRA
: 1;
5904 unsigned CWG2OVRB
: 1;
5905 unsigned CWG2OVRC
: 1;
5906 unsigned CWG2OVRD
: 1;
5910 extern __at(0x0719) volatile __CWG2STRbits_t CWG2STRbits
;
5912 #define _CWG2STR_STRA 0x01
5913 #define _CWG2STR_CWG2STRA 0x01
5914 #define _CWG2STR_STRB 0x02
5915 #define _CWG2STR_CWG2STRB 0x02
5916 #define _CWG2STR_STRC 0x04
5917 #define _CWG2STR_CWG2STRC 0x04
5918 #define _CWG2STR_STRD 0x08
5919 #define _CWG2STR_CWG2STRD 0x08
5920 #define _CWG2STR_OVRA 0x10
5921 #define _CWG2STR_CWG2OVRA 0x10
5922 #define _CWG2STR_OVRB 0x20
5923 #define _CWG2STR_CWG2OVRB 0x20
5924 #define _CWG2STR_OVRC 0x40
5925 #define _CWG2STR_CWG2OVRC 0x40
5926 #define _CWG2STR_OVRD 0x80
5927 #define _CWG2STR_CWG2OVRD 0x80
5929 //==============================================================================
5931 extern __at(0x0891) __sfr NVMADR
;
5933 //==============================================================================
5936 extern __at(0x0891) __sfr NVMADRL
;
5940 unsigned NVMADR0
: 1;
5941 unsigned NVMADR1
: 1;
5942 unsigned NVMADR2
: 1;
5943 unsigned NVMADR3
: 1;
5944 unsigned NVMADR4
: 1;
5945 unsigned NVMADR5
: 1;
5946 unsigned NVMADR6
: 1;
5947 unsigned NVMADR7
: 1;
5950 extern __at(0x0891) volatile __NVMADRLbits_t NVMADRLbits
;
5952 #define _NVMADR0 0x01
5953 #define _NVMADR1 0x02
5954 #define _NVMADR2 0x04
5955 #define _NVMADR3 0x08
5956 #define _NVMADR4 0x10
5957 #define _NVMADR5 0x20
5958 #define _NVMADR6 0x40
5959 #define _NVMADR7 0x80
5961 //==============================================================================
5964 //==============================================================================
5967 extern __at(0x0892) __sfr NVMADRH
;
5971 unsigned NVMADR8
: 1;
5972 unsigned NVMADR9
: 1;
5973 unsigned NVMADR10
: 1;
5974 unsigned NVMADR11
: 1;
5975 unsigned NVMADR12
: 1;
5976 unsigned NVMADR13
: 1;
5977 unsigned NVMADR14
: 1;
5981 extern __at(0x0892) volatile __NVMADRHbits_t NVMADRHbits
;
5983 #define _NVMADR8 0x01
5984 #define _NVMADR9 0x02
5985 #define _NVMADR10 0x04
5986 #define _NVMADR11 0x08
5987 #define _NVMADR12 0x10
5988 #define _NVMADR13 0x20
5989 #define _NVMADR14 0x40
5991 //==============================================================================
5993 extern __at(0x0893) __sfr NVMDAT
;
5995 //==============================================================================
5998 extern __at(0x0893) __sfr NVMDATL
;
6002 unsigned NVMDAT0
: 1;
6003 unsigned NVMDAT1
: 1;
6004 unsigned NVMDAT2
: 1;
6005 unsigned NVMDAT3
: 1;
6006 unsigned NVMDAT4
: 1;
6007 unsigned NVMDAT5
: 1;
6008 unsigned NVMDAT6
: 1;
6009 unsigned NVMDAT7
: 1;
6012 extern __at(0x0893) volatile __NVMDATLbits_t NVMDATLbits
;
6014 #define _NVMDAT0 0x01
6015 #define _NVMDAT1 0x02
6016 #define _NVMDAT2 0x04
6017 #define _NVMDAT3 0x08
6018 #define _NVMDAT4 0x10
6019 #define _NVMDAT5 0x20
6020 #define _NVMDAT6 0x40
6021 #define _NVMDAT7 0x80
6023 //==============================================================================
6026 //==============================================================================
6029 extern __at(0x0894) __sfr NVMDATH
;
6033 unsigned NVMDAT8
: 1;
6034 unsigned NVMDAT9
: 1;
6035 unsigned NVMDAT10
: 1;
6036 unsigned NVMDAT11
: 1;
6037 unsigned NVMDAT12
: 1;
6038 unsigned NVMDAT13
: 1;
6043 extern __at(0x0894) volatile __NVMDATHbits_t NVMDATHbits
;
6045 #define _NVMDAT8 0x01
6046 #define _NVMDAT9 0x02
6047 #define _NVMDAT10 0x04
6048 #define _NVMDAT11 0x08
6049 #define _NVMDAT12 0x10
6050 #define _NVMDAT13 0x20
6052 //==============================================================================
6055 //==============================================================================
6058 extern __at(0x0895) __sfr NVMCON1
;
6068 unsigned NVMREGS
: 1;
6072 extern __at(0x0895) volatile __NVMCON1bits_t NVMCON1bits
;
6080 #define _NVMREGS 0x40
6082 //==============================================================================
6084 extern __at(0x0896) __sfr NVMCON2
;
6086 //==============================================================================
6089 extern __at(0x089B) __sfr PCON0
;
6093 unsigned NOT_BOR
: 1;
6094 unsigned NOT_POR
: 1;
6095 unsigned NOT_RI
: 1;
6096 unsigned NOT_RMCLR
: 1;
6097 unsigned NOT_RWDT
: 1;
6099 unsigned STKUNF
: 1;
6100 unsigned STKOVF
: 1;
6103 extern __at(0x089B) volatile __PCON0bits_t PCON0bits
;
6105 #define _NOT_BOR 0x01
6106 #define _NOT_POR 0x02
6107 #define _NOT_RI 0x04
6108 #define _NOT_RMCLR 0x08
6109 #define _NOT_RWDT 0x10
6110 #define _STKUNF 0x40
6111 #define _STKOVF 0x80
6113 //==============================================================================
6116 //==============================================================================
6119 extern __at(0x0911) __sfr PMD0
;
6124 unsigned CLKRMD
: 1;
6130 unsigned SYSCMD
: 1;
6133 extern __at(0x0911) volatile __PMD0bits_t PMD0bits
;
6136 #define _CLKRMD 0x02
6139 #define _SYSCMD 0x80
6141 //==============================================================================
6144 //==============================================================================
6147 extern __at(0x0912) __sfr PMD1
;
6151 unsigned TMR0MD
: 1;
6152 unsigned TMR1MD
: 1;
6153 unsigned TMR2MD
: 1;
6154 unsigned TMR3MD
: 1;
6155 unsigned TMR4MD
: 1;
6156 unsigned TMR5MD
: 1;
6157 unsigned TMR6MD
: 1;
6161 extern __at(0x0912) volatile __PMD1bits_t PMD1bits
;
6163 #define _TMR0MD 0x01
6164 #define _TMR1MD 0x02
6165 #define _TMR2MD 0x04
6166 #define _TMR3MD 0x08
6167 #define _TMR4MD 0x10
6168 #define _TMR5MD 0x20
6169 #define _TMR6MD 0x40
6172 //==============================================================================
6175 //==============================================================================
6178 extern __at(0x0913) __sfr PMD2
;
6183 unsigned CMP1MD
: 1;
6184 unsigned CMP2MD
: 1;
6192 extern __at(0x0913) volatile __PMD2bits_t PMD2bits
;
6194 #define _CMP1MD 0x02
6195 #define _CMP2MD 0x04
6199 //==============================================================================
6202 //==============================================================================
6205 extern __at(0x0914) __sfr PMD3
;
6209 unsigned CCP1MD
: 1;
6210 unsigned CCP2MD
: 1;
6211 unsigned CCP3MD
: 1;
6212 unsigned CCP4MD
: 1;
6213 unsigned PWM5MD
: 1;
6214 unsigned PWM6MD
: 1;
6215 unsigned CWG1MD
: 1;
6216 unsigned CWG2MD
: 1;
6219 extern __at(0x0914) volatile __PMD3bits_t PMD3bits
;
6221 #define _CCP1MD 0x01
6222 #define _CCP2MD 0x02
6223 #define _CCP3MD 0x04
6224 #define _CCP4MD 0x08
6225 #define _PWM5MD 0x10
6226 #define _PWM6MD 0x20
6227 #define _CWG1MD 0x40
6228 #define _CWG2MD 0x80
6230 //==============================================================================
6233 //==============================================================================
6236 extern __at(0x0915) __sfr PMD4
;
6241 unsigned MSSP1MD
: 1;
6245 unsigned UART1MD
: 1;
6250 extern __at(0x0915) volatile __PMD4bits_t PMD4bits
;
6252 #define _MSSP1MD 0x02
6253 #define _UART1MD 0x20
6255 //==============================================================================
6258 //==============================================================================
6261 extern __at(0x0916) __sfr PMD5
;
6266 unsigned CLC1MD
: 1;
6267 unsigned CLC2MD
: 1;
6268 unsigned CLC3MD
: 1;
6269 unsigned CLC4MD
: 1;
6275 extern __at(0x0916) volatile __PMD5bits_t PMD5bits
;
6278 #define _CLC1MD 0x02
6279 #define _CLC2MD 0x04
6280 #define _CLC3MD 0x08
6281 #define _CLC4MD 0x10
6283 //==============================================================================
6286 //==============================================================================
6289 extern __at(0x0918) __sfr CPUDOZE
;
6312 extern __at(0x0918) volatile __CPUDOZEbits_t CPUDOZEbits
;
6322 //==============================================================================
6325 //==============================================================================
6328 extern __at(0x0919) __sfr OSCCON1
;
6358 extern __at(0x0919) volatile __OSCCON1bits_t OSCCON1bits
;
6368 //==============================================================================
6371 //==============================================================================
6374 extern __at(0x091A) __sfr OSCCON2
;
6404 extern __at(0x091A) volatile __OSCCON2bits_t OSCCON2bits
;
6414 //==============================================================================
6417 //==============================================================================
6420 extern __at(0x091B) __sfr OSCCON3
;
6429 unsigned SOSCBE
: 1;
6430 unsigned SOSCPWR
: 1;
6431 unsigned CSWHOLD
: 1;
6434 extern __at(0x091B) volatile __OSCCON3bits_t OSCCON3bits
;
6438 #define _SOSCBE 0x20
6439 #define _SOSCPWR 0x40
6440 #define _CSWHOLD 0x80
6442 //==============================================================================
6445 //==============================================================================
6448 extern __at(0x091C) __sfr OSCSTAT1
;
6462 extern __at(0x091C) volatile __OSCSTAT1bits_t OSCSTAT1bits
;
6471 //==============================================================================
6474 //==============================================================================
6477 extern __at(0x091D) __sfr OSCEN
;
6484 unsigned SOSCEN
: 1;
6488 unsigned EXTOEN
: 1;
6491 extern __at(0x091D) volatile __OSCENbits_t OSCENbits
;
6494 #define _SOSCEN 0x08
6497 #define _EXTOEN 0x80
6499 //==============================================================================
6502 //==============================================================================
6505 extern __at(0x091E) __sfr OSCTUNE
;
6511 unsigned HFTUN0
: 1;
6512 unsigned HFTUN1
: 1;
6513 unsigned HFTUN2
: 1;
6514 unsigned HFTUN3
: 1;
6515 unsigned HFTUN4
: 1;
6516 unsigned HFTUN5
: 1;
6528 extern __at(0x091E) volatile __OSCTUNEbits_t OSCTUNEbits
;
6530 #define _HFTUN0 0x01
6531 #define _HFTUN1 0x02
6532 #define _HFTUN2 0x04
6533 #define _HFTUN3 0x08
6534 #define _HFTUN4 0x10
6535 #define _HFTUN5 0x20
6537 //==============================================================================
6540 //==============================================================================
6543 extern __at(0x091F) __sfr OSCFRQ
;
6549 unsigned HFFRQ0
: 1;
6550 unsigned HFFRQ1
: 1;
6551 unsigned HFFRQ2
: 1;
6552 unsigned HFFRQ3
: 1;
6566 extern __at(0x091F) volatile __OSCFRQbits_t OSCFRQbits
;
6568 #define _HFFRQ0 0x01
6569 #define _HFFRQ1 0x02
6570 #define _HFFRQ2 0x04
6571 #define _HFFRQ3 0x08
6573 //==============================================================================
6576 //==============================================================================
6579 extern __at(0x0E0F) __sfr PPSLOCK
;
6583 unsigned PPSLOCKED
: 1;
6593 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
6595 #define _PPSLOCKED 0x01
6597 //==============================================================================
6600 //==============================================================================
6603 extern __at(0x0E10) __sfr INTPPS
;
6609 unsigned INTPPS0
: 1;
6610 unsigned INTPPS1
: 1;
6611 unsigned INTPPS2
: 1;
6612 unsigned INTPPS3
: 1;
6613 unsigned INTPPS4
: 1;
6621 unsigned INTPPS
: 5;
6626 extern __at(0x0E10) volatile __INTPPSbits_t INTPPSbits
;
6628 #define _INTPPS0 0x01
6629 #define _INTPPS1 0x02
6630 #define _INTPPS2 0x04
6631 #define _INTPPS3 0x08
6632 #define _INTPPS4 0x10
6634 //==============================================================================
6637 //==============================================================================
6640 extern __at(0x0E11) __sfr T0CKIPPS
;
6646 unsigned T0CKIPPS0
: 1;
6647 unsigned T0CKIPPS1
: 1;
6648 unsigned T0CKIPPS2
: 1;
6649 unsigned T0CKIPPS3
: 1;
6650 unsigned T0CKIPPS4
: 1;
6658 unsigned T0CKIPPS
: 5;
6663 extern __at(0x0E11) volatile __T0CKIPPSbits_t T0CKIPPSbits
;
6665 #define _T0CKIPPS0 0x01
6666 #define _T0CKIPPS1 0x02
6667 #define _T0CKIPPS2 0x04
6668 #define _T0CKIPPS3 0x08
6669 #define _T0CKIPPS4 0x10
6671 //==============================================================================
6674 //==============================================================================
6677 extern __at(0x0E12) __sfr T1CKIPPS
;
6683 unsigned T1CKIPPS0
: 1;
6684 unsigned T1CKIPPS1
: 1;
6685 unsigned T1CKIPPS2
: 1;
6686 unsigned T1CKIPPS3
: 1;
6687 unsigned T1CKIPPS4
: 1;
6695 unsigned T1CKIPPS
: 5;
6700 extern __at(0x0E12) volatile __T1CKIPPSbits_t T1CKIPPSbits
;
6702 #define _T1CKIPPS0 0x01
6703 #define _T1CKIPPS1 0x02
6704 #define _T1CKIPPS2 0x04
6705 #define _T1CKIPPS3 0x08
6706 #define _T1CKIPPS4 0x10
6708 //==============================================================================
6711 //==============================================================================
6714 extern __at(0x0E13) __sfr T1GPPS
;
6720 unsigned T1GPPS0
: 1;
6721 unsigned T1GPPS1
: 1;
6722 unsigned T1GPPS2
: 1;
6723 unsigned T1GPPS3
: 1;
6724 unsigned T1GPPS4
: 1;
6732 unsigned T1GPPS
: 5;
6737 extern __at(0x0E13) volatile __T1GPPSbits_t T1GPPSbits
;
6739 #define _T1GPPS0 0x01
6740 #define _T1GPPS1 0x02
6741 #define _T1GPPS2 0x04
6742 #define _T1GPPS3 0x08
6743 #define _T1GPPS4 0x10
6745 //==============================================================================
6748 //==============================================================================
6751 extern __at(0x0E14) __sfr CCP1PPS
;
6757 unsigned CCP1PPS0
: 1;
6758 unsigned CCP1PPS1
: 1;
6759 unsigned CCP1PPS2
: 1;
6760 unsigned CCP1PPS3
: 1;
6761 unsigned CCP1PPS4
: 1;
6769 unsigned CCP1PPS
: 5;
6774 extern __at(0x0E14) volatile __CCP1PPSbits_t CCP1PPSbits
;
6776 #define _CCP1PPS0 0x01
6777 #define _CCP1PPS1 0x02
6778 #define _CCP1PPS2 0x04
6779 #define _CCP1PPS3 0x08
6780 #define _CCP1PPS4 0x10
6782 //==============================================================================
6785 //==============================================================================
6788 extern __at(0x0E15) __sfr CCP2PPS
;
6794 unsigned CCP2PPS0
: 1;
6795 unsigned CCP2PPS1
: 1;
6796 unsigned CCP2PPS2
: 1;
6797 unsigned CCP2PPS3
: 1;
6798 unsigned CCP2PPS4
: 1;
6806 unsigned CCP2PPS
: 5;
6811 extern __at(0x0E15) volatile __CCP2PPSbits_t CCP2PPSbits
;
6813 #define _CCP2PPS0 0x01
6814 #define _CCP2PPS1 0x02
6815 #define _CCP2PPS2 0x04
6816 #define _CCP2PPS3 0x08
6817 #define _CCP2PPS4 0x10
6819 //==============================================================================
6822 //==============================================================================
6825 extern __at(0x0E16) __sfr CCP3PPS
;
6831 unsigned CCP3PPS0
: 1;
6832 unsigned CCP3PPS1
: 1;
6833 unsigned CCP3PPS2
: 1;
6834 unsigned CCP3PPS3
: 1;
6835 unsigned CCP3PPS4
: 1;
6843 unsigned CCP3PPS
: 5;
6848 extern __at(0x0E16) volatile __CCP3PPSbits_t CCP3PPSbits
;
6850 #define _CCP3PPS0 0x01
6851 #define _CCP3PPS1 0x02
6852 #define _CCP3PPS2 0x04
6853 #define _CCP3PPS3 0x08
6854 #define _CCP3PPS4 0x10
6856 //==============================================================================
6859 //==============================================================================
6862 extern __at(0x0E17) __sfr CCP4PPS
;
6868 unsigned CCP4PPS0
: 1;
6869 unsigned CCP4PPS1
: 1;
6870 unsigned CCP4PPS2
: 1;
6871 unsigned CCP4PPS3
: 1;
6872 unsigned CCP4PPS4
: 1;
6880 unsigned CCP4PPS
: 5;
6885 extern __at(0x0E17) volatile __CCP4PPSbits_t CCP4PPSbits
;
6887 #define _CCP4PPS0 0x01
6888 #define _CCP4PPS1 0x02
6889 #define _CCP4PPS2 0x04
6890 #define _CCP4PPS3 0x08
6891 #define _CCP4PPS4 0x10
6893 //==============================================================================
6896 //==============================================================================
6899 extern __at(0x0E18) __sfr CWG1PPS
;
6905 unsigned CWG1PPS0
: 1;
6906 unsigned CWG1PPS1
: 1;
6907 unsigned CWG1PPS2
: 1;
6908 unsigned CWG1PPS3
: 1;
6909 unsigned CWG1PPS4
: 1;
6917 unsigned CWG1PPS
: 5;
6922 extern __at(0x0E18) volatile __CWG1PPSbits_t CWG1PPSbits
;
6924 #define _CWG1PPS0 0x01
6925 #define _CWG1PPS1 0x02
6926 #define _CWG1PPS2 0x04
6927 #define _CWG1PPS3 0x08
6928 #define _CWG1PPS4 0x10
6930 //==============================================================================
6933 //==============================================================================
6936 extern __at(0x0E19) __sfr CWG2PPS
;
6942 unsigned CWG2PPS0
: 1;
6943 unsigned CWG2PPS1
: 1;
6944 unsigned CWG2PPS2
: 1;
6945 unsigned CWG2PPS3
: 1;
6946 unsigned CWG2PPS4
: 1;
6954 unsigned CWG2PPS
: 5;
6959 extern __at(0x0E19) volatile __CWG2PPSbits_t CWG2PPSbits
;
6961 #define _CWG2PPS0 0x01
6962 #define _CWG2PPS1 0x02
6963 #define _CWG2PPS2 0x04
6964 #define _CWG2PPS3 0x08
6965 #define _CWG2PPS4 0x10
6967 //==============================================================================
6970 //==============================================================================
6973 extern __at(0x0E1A) __sfr MDCIN1PPS
;
6979 unsigned MDCIN1PPS0
: 1;
6980 unsigned MDCIN1PPS1
: 1;
6981 unsigned MDCIN1PPS2
: 1;
6982 unsigned MDCIN1PPS3
: 1;
6983 unsigned MDCIN1PPS4
: 1;
6991 unsigned MDCIN1PPS
: 5;
6994 } __MDCIN1PPSbits_t
;
6996 extern __at(0x0E1A) volatile __MDCIN1PPSbits_t MDCIN1PPSbits
;
6998 #define _MDCIN1PPS0 0x01
6999 #define _MDCIN1PPS1 0x02
7000 #define _MDCIN1PPS2 0x04
7001 #define _MDCIN1PPS3 0x08
7002 #define _MDCIN1PPS4 0x10
7004 //==============================================================================
7007 //==============================================================================
7010 extern __at(0x0E1B) __sfr MDCIN2PPS
;
7016 unsigned MDCIN2PPS0
: 1;
7017 unsigned MDCIN2PPS1
: 1;
7018 unsigned MDCIN2PPS2
: 1;
7019 unsigned MDCIN2PPS3
: 1;
7020 unsigned MDCIN2PPS4
: 1;
7028 unsigned MDCIN2PPS
: 5;
7031 } __MDCIN2PPSbits_t
;
7033 extern __at(0x0E1B) volatile __MDCIN2PPSbits_t MDCIN2PPSbits
;
7035 #define _MDCIN2PPS0 0x01
7036 #define _MDCIN2PPS1 0x02
7037 #define _MDCIN2PPS2 0x04
7038 #define _MDCIN2PPS3 0x08
7039 #define _MDCIN2PPS4 0x10
7041 //==============================================================================
7044 //==============================================================================
7047 extern __at(0x0E1C) __sfr MDMINPPS
;
7053 unsigned MDMINPPS0
: 1;
7054 unsigned MDMINPPS1
: 1;
7055 unsigned MDMINPPS2
: 1;
7056 unsigned MDMINPPS3
: 1;
7057 unsigned MDMINPPS4
: 1;
7065 unsigned MDMINPPS
: 5;
7070 extern __at(0x0E1C) volatile __MDMINPPSbits_t MDMINPPSbits
;
7072 #define _MDMINPPS0 0x01
7073 #define _MDMINPPS1 0x02
7074 #define _MDMINPPS2 0x04
7075 #define _MDMINPPS3 0x08
7076 #define _MDMINPPS4 0x10
7078 //==============================================================================
7081 //==============================================================================
7084 extern __at(0x0E20) __sfr SSP1CLKPPS
;
7090 unsigned SSP1CLKPPS0
: 1;
7091 unsigned SSP1CLKPPS1
: 1;
7092 unsigned SSP1CLKPPS2
: 1;
7093 unsigned SSP1CLKPPS3
: 1;
7094 unsigned SSP1CLKPPS4
: 1;
7102 unsigned SSP1CLKPPS
: 5;
7105 } __SSP1CLKPPSbits_t
;
7107 extern __at(0x0E20) volatile __SSP1CLKPPSbits_t SSP1CLKPPSbits
;
7109 #define _SSP1CLKPPS0 0x01
7110 #define _SSP1CLKPPS1 0x02
7111 #define _SSP1CLKPPS2 0x04
7112 #define _SSP1CLKPPS3 0x08
7113 #define _SSP1CLKPPS4 0x10
7115 //==============================================================================
7118 //==============================================================================
7121 extern __at(0x0E21) __sfr SSP1DATPPS
;
7127 unsigned SSP1DATPPS0
: 1;
7128 unsigned SSP1DATPPS1
: 1;
7129 unsigned SSP1DATPPS2
: 1;
7130 unsigned SSP1DATPPS3
: 1;
7131 unsigned SSP1DATPPS4
: 1;
7139 unsigned SSP1DATPPS
: 5;
7142 } __SSP1DATPPSbits_t
;
7144 extern __at(0x0E21) volatile __SSP1DATPPSbits_t SSP1DATPPSbits
;
7146 #define _SSP1DATPPS0 0x01
7147 #define _SSP1DATPPS1 0x02
7148 #define _SSP1DATPPS2 0x04
7149 #define _SSP1DATPPS3 0x08
7150 #define _SSP1DATPPS4 0x10
7152 //==============================================================================
7155 //==============================================================================
7158 extern __at(0x0E22) __sfr SSP1SSPPS
;
7164 unsigned SSP1SSPPS0
: 1;
7165 unsigned SSP1SSPPS1
: 1;
7166 unsigned SSP1SSPPS2
: 1;
7167 unsigned SSP1SSPPS3
: 1;
7168 unsigned SSP1SSPPS4
: 1;
7176 unsigned SSP1SSPPS
: 5;
7179 } __SSP1SSPPSbits_t
;
7181 extern __at(0x0E22) volatile __SSP1SSPPSbits_t SSP1SSPPSbits
;
7183 #define _SSP1SSPPS0 0x01
7184 #define _SSP1SSPPS1 0x02
7185 #define _SSP1SSPPS2 0x04
7186 #define _SSP1SSPPS3 0x08
7187 #define _SSP1SSPPS4 0x10
7189 //==============================================================================
7192 //==============================================================================
7195 extern __at(0x0E24) __sfr RXPPS
;
7201 unsigned RXDTPPS0
: 1;
7202 unsigned RXDTPPS1
: 1;
7203 unsigned RXDTPPS2
: 1;
7204 unsigned RXDTPPS3
: 1;
7205 unsigned RXDTPPS4
: 1;
7213 unsigned RXDTPPS
: 5;
7218 extern __at(0x0E24) volatile __RXPPSbits_t RXPPSbits
;
7220 #define _RXDTPPS0 0x01
7221 #define _RXDTPPS1 0x02
7222 #define _RXDTPPS2 0x04
7223 #define _RXDTPPS3 0x08
7224 #define _RXDTPPS4 0x10
7226 //==============================================================================
7229 //==============================================================================
7232 extern __at(0x0E25) __sfr TXPPS
;
7238 unsigned TXCKPPS0
: 1;
7239 unsigned TXCKPPS1
: 1;
7240 unsigned TXCKPPS2
: 1;
7241 unsigned TXCKPPS3
: 1;
7242 unsigned TXCKPPS4
: 1;
7250 unsigned TXCKPPS
: 5;
7255 extern __at(0x0E25) volatile __TXPPSbits_t TXPPSbits
;
7257 #define _TXCKPPS0 0x01
7258 #define _TXCKPPS1 0x02
7259 #define _TXCKPPS2 0x04
7260 #define _TXCKPPS3 0x08
7261 #define _TXCKPPS4 0x10
7263 //==============================================================================
7266 //==============================================================================
7269 extern __at(0x0E28) __sfr CLCIN0PPS
;
7275 unsigned CLCIN0PPS0
: 1;
7276 unsigned CLCIN0PPS1
: 1;
7277 unsigned CLCIN0PPS2
: 1;
7278 unsigned CLCIN0PPS3
: 1;
7279 unsigned CLCIN0PPS4
: 1;
7287 unsigned CLCIN0PPS
: 5;
7290 } __CLCIN0PPSbits_t
;
7292 extern __at(0x0E28) volatile __CLCIN0PPSbits_t CLCIN0PPSbits
;
7294 #define _CLCIN0PPS0 0x01
7295 #define _CLCIN0PPS1 0x02
7296 #define _CLCIN0PPS2 0x04
7297 #define _CLCIN0PPS3 0x08
7298 #define _CLCIN0PPS4 0x10
7300 //==============================================================================
7303 //==============================================================================
7306 extern __at(0x0E29) __sfr CLCIN1PPS
;
7312 unsigned CLCIN1PPS0
: 1;
7313 unsigned CLCIN1PPS1
: 1;
7314 unsigned CLCIN1PPS2
: 1;
7315 unsigned CLCIN1PPS3
: 1;
7316 unsigned CLCIN1PPS4
: 1;
7324 unsigned CLCIN1PPS
: 5;
7327 } __CLCIN1PPSbits_t
;
7329 extern __at(0x0E29) volatile __CLCIN1PPSbits_t CLCIN1PPSbits
;
7331 #define _CLCIN1PPS0 0x01
7332 #define _CLCIN1PPS1 0x02
7333 #define _CLCIN1PPS2 0x04
7334 #define _CLCIN1PPS3 0x08
7335 #define _CLCIN1PPS4 0x10
7337 //==============================================================================
7340 //==============================================================================
7343 extern __at(0x0E2A) __sfr CLCIN2PPS
;
7349 unsigned CLCIN2PPS0
: 1;
7350 unsigned CLCIN2PPS1
: 1;
7351 unsigned CLCIN2PPS2
: 1;
7352 unsigned CLCIN2PPS3
: 1;
7353 unsigned CLCIN2PPS4
: 1;
7361 unsigned CLCIN2PPS
: 5;
7364 } __CLCIN2PPSbits_t
;
7366 extern __at(0x0E2A) volatile __CLCIN2PPSbits_t CLCIN2PPSbits
;
7368 #define _CLCIN2PPS0 0x01
7369 #define _CLCIN2PPS1 0x02
7370 #define _CLCIN2PPS2 0x04
7371 #define _CLCIN2PPS3 0x08
7372 #define _CLCIN2PPS4 0x10
7374 //==============================================================================
7377 //==============================================================================
7380 extern __at(0x0E2B) __sfr CLCIN3PPS
;
7386 unsigned CLCIN3PPS0
: 1;
7387 unsigned CLCIN3PPS1
: 1;
7388 unsigned CLCIN3PPS2
: 1;
7389 unsigned CLCIN3PPS3
: 1;
7390 unsigned CLCIN3PPS4
: 1;
7398 unsigned CLCIN3PPS
: 5;
7401 } __CLCIN3PPSbits_t
;
7403 extern __at(0x0E2B) volatile __CLCIN3PPSbits_t CLCIN3PPSbits
;
7405 #define _CLCIN3PPS0 0x01
7406 #define _CLCIN3PPS1 0x02
7407 #define _CLCIN3PPS2 0x04
7408 #define _CLCIN3PPS3 0x08
7409 #define _CLCIN3PPS4 0x10
7411 //==============================================================================
7413 extern __at(0x0E2C) __sfr T3CKIPPS
;
7414 extern __at(0x0E2D) __sfr T3GPPS
;
7415 extern __at(0x0E2E) __sfr T5CKIPPS
;
7416 extern __at(0x0E2F) __sfr T5GPPS
;
7418 //==============================================================================
7421 extern __at(0x0E90) __sfr RA0PPS
;
7427 unsigned RA0PPS0
: 1;
7428 unsigned RA0PPS1
: 1;
7429 unsigned RA0PPS2
: 1;
7430 unsigned RA0PPS3
: 1;
7431 unsigned RA0PPS4
: 1;
7439 unsigned RA0PPS
: 5;
7444 extern __at(0x0E90) volatile __RA0PPSbits_t RA0PPSbits
;
7446 #define _RA0PPS0 0x01
7447 #define _RA0PPS1 0x02
7448 #define _RA0PPS2 0x04
7449 #define _RA0PPS3 0x08
7450 #define _RA0PPS4 0x10
7452 //==============================================================================
7455 //==============================================================================
7458 extern __at(0x0E91) __sfr RA1PPS
;
7464 unsigned RA1PPS0
: 1;
7465 unsigned RA1PPS1
: 1;
7466 unsigned RA1PPS2
: 1;
7467 unsigned RA1PPS3
: 1;
7468 unsigned RA1PPS4
: 1;
7476 unsigned RA1PPS
: 5;
7481 extern __at(0x0E91) volatile __RA1PPSbits_t RA1PPSbits
;
7483 #define _RA1PPS0 0x01
7484 #define _RA1PPS1 0x02
7485 #define _RA1PPS2 0x04
7486 #define _RA1PPS3 0x08
7487 #define _RA1PPS4 0x10
7489 //==============================================================================
7492 //==============================================================================
7495 extern __at(0x0E92) __sfr RA2PPS
;
7501 unsigned RA2PPS0
: 1;
7502 unsigned RA2PPS1
: 1;
7503 unsigned RA2PPS2
: 1;
7504 unsigned RA2PPS3
: 1;
7505 unsigned RA2PPS4
: 1;
7513 unsigned RA2PPS
: 5;
7518 extern __at(0x0E92) volatile __RA2PPSbits_t RA2PPSbits
;
7520 #define _RA2PPS0 0x01
7521 #define _RA2PPS1 0x02
7522 #define _RA2PPS2 0x04
7523 #define _RA2PPS3 0x08
7524 #define _RA2PPS4 0x10
7526 //==============================================================================
7529 //==============================================================================
7532 extern __at(0x0E94) __sfr RA4PPS
;
7538 unsigned RA4PPS0
: 1;
7539 unsigned RA4PPS1
: 1;
7540 unsigned RA4PPS2
: 1;
7541 unsigned RA4PPS3
: 1;
7542 unsigned RA4PPS4
: 1;
7550 unsigned RA4PPS
: 5;
7555 extern __at(0x0E94) volatile __RA4PPSbits_t RA4PPSbits
;
7557 #define _RA4PPS0 0x01
7558 #define _RA4PPS1 0x02
7559 #define _RA4PPS2 0x04
7560 #define _RA4PPS3 0x08
7561 #define _RA4PPS4 0x10
7563 //==============================================================================
7566 //==============================================================================
7569 extern __at(0x0E95) __sfr RA5PPS
;
7575 unsigned RA5PPS0
: 1;
7576 unsigned RA5PPS1
: 1;
7577 unsigned RA5PPS2
: 1;
7578 unsigned RA5PPS3
: 1;
7579 unsigned RA5PPS4
: 1;
7587 unsigned RA5PPS
: 5;
7592 extern __at(0x0E95) volatile __RA5PPSbits_t RA5PPSbits
;
7594 #define _RA5PPS0 0x01
7595 #define _RA5PPS1 0x02
7596 #define _RA5PPS2 0x04
7597 #define _RA5PPS3 0x08
7598 #define _RA5PPS4 0x10
7600 //==============================================================================
7603 //==============================================================================
7606 extern __at(0x0E9C) __sfr RB4PPS
;
7612 unsigned RB4PPS0
: 1;
7613 unsigned RB4PPS1
: 1;
7614 unsigned RB4PPS2
: 1;
7615 unsigned RB4PPS3
: 1;
7616 unsigned RB4PPS4
: 1;
7624 unsigned RB4PPS
: 5;
7629 extern __at(0x0E9C) volatile __RB4PPSbits_t RB4PPSbits
;
7631 #define _RB4PPS0 0x01
7632 #define _RB4PPS1 0x02
7633 #define _RB4PPS2 0x04
7634 #define _RB4PPS3 0x08
7635 #define _RB4PPS4 0x10
7637 //==============================================================================
7640 //==============================================================================
7643 extern __at(0x0E9D) __sfr RB5PPS
;
7649 unsigned RB5PPS0
: 1;
7650 unsigned RB5PPS1
: 1;
7651 unsigned RB5PPS2
: 1;
7652 unsigned RB5PPS3
: 1;
7653 unsigned RB5PPS4
: 1;
7661 unsigned RB5PPS
: 5;
7666 extern __at(0x0E9D) volatile __RB5PPSbits_t RB5PPSbits
;
7668 #define _RB5PPS0 0x01
7669 #define _RB5PPS1 0x02
7670 #define _RB5PPS2 0x04
7671 #define _RB5PPS3 0x08
7672 #define _RB5PPS4 0x10
7674 //==============================================================================
7677 //==============================================================================
7680 extern __at(0x0E9E) __sfr RB6PPS
;
7686 unsigned RB6PPS0
: 1;
7687 unsigned RB6PPS1
: 1;
7688 unsigned RB6PPS2
: 1;
7689 unsigned RB6PPS3
: 1;
7690 unsigned RB6PPS4
: 1;
7698 unsigned RB6PPS
: 5;
7703 extern __at(0x0E9E) volatile __RB6PPSbits_t RB6PPSbits
;
7705 #define _RB6PPS0 0x01
7706 #define _RB6PPS1 0x02
7707 #define _RB6PPS2 0x04
7708 #define _RB6PPS3 0x08
7709 #define _RB6PPS4 0x10
7711 //==============================================================================
7714 //==============================================================================
7717 extern __at(0x0E9F) __sfr RB7PPS
;
7723 unsigned RB7PPS0
: 1;
7724 unsigned RB7PPS1
: 1;
7725 unsigned RB7PPS2
: 1;
7726 unsigned RB7PPS3
: 1;
7727 unsigned RB7PPS4
: 1;
7735 unsigned RB7PPS
: 5;
7740 extern __at(0x0E9F) volatile __RB7PPSbits_t RB7PPSbits
;
7742 #define _RB7PPS0 0x01
7743 #define _RB7PPS1 0x02
7744 #define _RB7PPS2 0x04
7745 #define _RB7PPS3 0x08
7746 #define _RB7PPS4 0x10
7748 //==============================================================================
7751 //==============================================================================
7754 extern __at(0x0EA0) __sfr RC0PPS
;
7760 unsigned RC0PPS0
: 1;
7761 unsigned RC0PPS1
: 1;
7762 unsigned RC0PPS2
: 1;
7763 unsigned RC0PPS3
: 1;
7764 unsigned RC0PPS4
: 1;
7772 unsigned RC0PPS
: 5;
7777 extern __at(0x0EA0) volatile __RC0PPSbits_t RC0PPSbits
;
7779 #define _RC0PPS0 0x01
7780 #define _RC0PPS1 0x02
7781 #define _RC0PPS2 0x04
7782 #define _RC0PPS3 0x08
7783 #define _RC0PPS4 0x10
7785 //==============================================================================
7788 //==============================================================================
7791 extern __at(0x0EA1) __sfr RC1PPS
;
7797 unsigned RC1PPS0
: 1;
7798 unsigned RC1PPS1
: 1;
7799 unsigned RC1PPS2
: 1;
7800 unsigned RC1PPS3
: 1;
7801 unsigned RC1PPS4
: 1;
7809 unsigned RC1PPS
: 5;
7814 extern __at(0x0EA1) volatile __RC1PPSbits_t RC1PPSbits
;
7816 #define _RC1PPS0 0x01
7817 #define _RC1PPS1 0x02
7818 #define _RC1PPS2 0x04
7819 #define _RC1PPS3 0x08
7820 #define _RC1PPS4 0x10
7822 //==============================================================================
7825 //==============================================================================
7828 extern __at(0x0EA2) __sfr RC2PPS
;
7834 unsigned RC2PPS0
: 1;
7835 unsigned RC2PPS1
: 1;
7836 unsigned RC2PPS2
: 1;
7837 unsigned RC2PPS3
: 1;
7838 unsigned RC2PPS4
: 1;
7846 unsigned RC2PPS
: 5;
7851 extern __at(0x0EA2) volatile __RC2PPSbits_t RC2PPSbits
;
7853 #define _RC2PPS0 0x01
7854 #define _RC2PPS1 0x02
7855 #define _RC2PPS2 0x04
7856 #define _RC2PPS3 0x08
7857 #define _RC2PPS4 0x10
7859 //==============================================================================
7862 //==============================================================================
7865 extern __at(0x0EA3) __sfr RC3PPS
;
7871 unsigned RC3PPS0
: 1;
7872 unsigned RC3PPS1
: 1;
7873 unsigned RC3PPS2
: 1;
7874 unsigned RC3PPS3
: 1;
7875 unsigned RC3PPS4
: 1;
7883 unsigned RC3PPS
: 5;
7888 extern __at(0x0EA3) volatile __RC3PPSbits_t RC3PPSbits
;
7890 #define _RC3PPS0 0x01
7891 #define _RC3PPS1 0x02
7892 #define _RC3PPS2 0x04
7893 #define _RC3PPS3 0x08
7894 #define _RC3PPS4 0x10
7896 //==============================================================================
7899 //==============================================================================
7902 extern __at(0x0EA4) __sfr RC4PPS
;
7908 unsigned RC4PPS0
: 1;
7909 unsigned RC4PPS1
: 1;
7910 unsigned RC4PPS2
: 1;
7911 unsigned RC4PPS3
: 1;
7912 unsigned RC4PPS4
: 1;
7920 unsigned RC4PPS
: 5;
7925 extern __at(0x0EA4) volatile __RC4PPSbits_t RC4PPSbits
;
7927 #define _RC4PPS0 0x01
7928 #define _RC4PPS1 0x02
7929 #define _RC4PPS2 0x04
7930 #define _RC4PPS3 0x08
7931 #define _RC4PPS4 0x10
7933 //==============================================================================
7936 //==============================================================================
7939 extern __at(0x0EA5) __sfr RC5PPS
;
7945 unsigned RC5PPS0
: 1;
7946 unsigned RC5PPS1
: 1;
7947 unsigned RC5PPS2
: 1;
7948 unsigned RC5PPS3
: 1;
7949 unsigned RC5PPS4
: 1;
7957 unsigned RC5PPS
: 5;
7962 extern __at(0x0EA5) volatile __RC5PPSbits_t RC5PPSbits
;
7964 #define _RC5PPS0 0x01
7965 #define _RC5PPS1 0x02
7966 #define _RC5PPS2 0x04
7967 #define _RC5PPS3 0x08
7968 #define _RC5PPS4 0x10
7970 //==============================================================================
7973 //==============================================================================
7976 extern __at(0x0EA6) __sfr RC6PPS
;
7982 unsigned RC6PPS0
: 1;
7983 unsigned RC6PPS1
: 1;
7984 unsigned RC6PPS2
: 1;
7985 unsigned RC6PPS3
: 1;
7986 unsigned RC6PPS4
: 1;
7994 unsigned RC6PPS
: 5;
7999 extern __at(0x0EA6) volatile __RC6PPSbits_t RC6PPSbits
;
8001 #define _RC6PPS0 0x01
8002 #define _RC6PPS1 0x02
8003 #define _RC6PPS2 0x04
8004 #define _RC6PPS3 0x08
8005 #define _RC6PPS4 0x10
8007 //==============================================================================
8010 //==============================================================================
8013 extern __at(0x0EA7) __sfr RC7PPS
;
8019 unsigned RC7PPS0
: 1;
8020 unsigned RC7PPS1
: 1;
8021 unsigned RC7PPS2
: 1;
8022 unsigned RC7PPS3
: 1;
8023 unsigned RC7PPS4
: 1;
8031 unsigned RC7PPS
: 5;
8036 extern __at(0x0EA7) volatile __RC7PPSbits_t RC7PPSbits
;
8038 #define _RC7PPS0 0x01
8039 #define _RC7PPS1 0x02
8040 #define _RC7PPS2 0x04
8041 #define _RC7PPS3 0x08
8042 #define _RC7PPS4 0x10
8044 //==============================================================================
8047 //==============================================================================
8050 extern __at(0x0F0F) __sfr CLCDATA
;
8054 unsigned MLC1OUT
: 1;
8055 unsigned MLC2OUT
: 1;
8056 unsigned MLC3OUT
: 1;
8057 unsigned MLC4OUT
: 1;
8064 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
8066 #define _MLC1OUT 0x01
8067 #define _MLC2OUT 0x02
8068 #define _MLC3OUT 0x04
8069 #define _MLC4OUT 0x08
8071 //==============================================================================
8074 //==============================================================================
8077 extern __at(0x0F10) __sfr CLC1CON
;
8083 unsigned LC1MODE0
: 1;
8084 unsigned LC1MODE1
: 1;
8085 unsigned LC1MODE2
: 1;
8086 unsigned LC1INTN
: 1;
8087 unsigned LC1INTP
: 1;
8088 unsigned LC1OUT
: 1;
8113 unsigned LC1MODE
: 3;
8118 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
8120 #define _LC1MODE0 0x01
8122 #define _LC1MODE1 0x02
8124 #define _LC1MODE2 0x04
8126 #define _LC1INTN 0x08
8128 #define _LC1INTP 0x10
8130 #define _LC1OUT 0x20
8135 //==============================================================================
8138 //==============================================================================
8141 extern __at(0x0F11) __sfr CLC1POL
;
8147 unsigned LC1G1POL
: 1;
8148 unsigned LC1G2POL
: 1;
8149 unsigned LC1G3POL
: 1;
8150 unsigned LC1G4POL
: 1;
8154 unsigned LC1POL
: 1;
8170 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
8172 #define _LC1G1POL 0x01
8174 #define _LC1G2POL 0x02
8176 #define _LC1G3POL 0x04
8178 #define _LC1G4POL 0x08
8180 #define _LC1POL 0x80
8183 //==============================================================================
8186 //==============================================================================
8189 extern __at(0x0F12) __sfr CLC1SEL0
;
8195 unsigned LC1D1S0
: 1;
8196 unsigned LC1D1S1
: 1;
8197 unsigned LC1D1S2
: 1;
8198 unsigned LC1D1S3
: 1;
8199 unsigned LC1D1S4
: 1;
8200 unsigned LC1D1S5
: 1;
8225 unsigned LC1D1S
: 6;
8230 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
8232 #define _LC1D1S0 0x01
8234 #define _LC1D1S1 0x02
8236 #define _LC1D1S2 0x04
8238 #define _LC1D1S3 0x08
8240 #define _LC1D1S4 0x10
8242 #define _LC1D1S5 0x20
8245 //==============================================================================
8248 //==============================================================================
8251 extern __at(0x0F13) __sfr CLC1SEL1
;
8257 unsigned LC1D2S0
: 1;
8258 unsigned LC1D2S1
: 1;
8259 unsigned LC1D2S2
: 1;
8260 unsigned LC1D2S3
: 1;
8261 unsigned LC1D2S4
: 1;
8262 unsigned LC1D2S5
: 1;
8281 unsigned LC1D2S
: 6;
8292 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
8294 #define _LC1D2S0 0x01
8296 #define _LC1D2S1 0x02
8298 #define _LC1D2S2 0x04
8300 #define _LC1D2S3 0x08
8302 #define _LC1D2S4 0x10
8304 #define _LC1D2S5 0x20
8307 //==============================================================================
8310 //==============================================================================
8313 extern __at(0x0F14) __sfr CLC1SEL2
;
8319 unsigned LC1D3S0
: 1;
8320 unsigned LC1D3S1
: 1;
8321 unsigned LC1D3S2
: 1;
8322 unsigned LC1D3S3
: 1;
8323 unsigned LC1D3S4
: 1;
8324 unsigned LC1D3S5
: 1;
8343 unsigned LC1D3S
: 6;
8354 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
8356 #define _LC1D3S0 0x01
8358 #define _LC1D3S1 0x02
8360 #define _LC1D3S2 0x04
8362 #define _LC1D3S3 0x08
8364 #define _LC1D3S4 0x10
8366 #define _LC1D3S5 0x20
8369 //==============================================================================
8372 //==============================================================================
8375 extern __at(0x0F15) __sfr CLC1SEL3
;
8381 unsigned LC1D4S0
: 1;
8382 unsigned LC1D4S1
: 1;
8383 unsigned LC1D4S2
: 1;
8384 unsigned LC1D4S3
: 1;
8385 unsigned LC1D4S4
: 1;
8386 unsigned LC1D4S5
: 1;
8411 unsigned LC1D4S
: 6;
8416 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
8418 #define _LC1D4S0 0x01
8420 #define _LC1D4S1 0x02
8422 #define _LC1D4S2 0x04
8424 #define _LC1D4S3 0x08
8426 #define _LC1D4S4 0x10
8428 #define _LC1D4S5 0x20
8431 //==============================================================================
8434 //==============================================================================
8437 extern __at(0x0F16) __sfr CLC1GLS0
;
8443 unsigned LC1G1D1N
: 1;
8444 unsigned LC1G1D1T
: 1;
8445 unsigned LC1G1D2N
: 1;
8446 unsigned LC1G1D2T
: 1;
8447 unsigned LC1G1D3N
: 1;
8448 unsigned LC1G1D3T
: 1;
8449 unsigned LC1G1D4N
: 1;
8450 unsigned LC1G1D4T
: 1;
8466 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
8468 #define _LC1G1D1N 0x01
8470 #define _LC1G1D1T 0x02
8472 #define _LC1G1D2N 0x04
8474 #define _LC1G1D2T 0x08
8476 #define _LC1G1D3N 0x10
8478 #define _LC1G1D3T 0x20
8480 #define _LC1G1D4N 0x40
8482 #define _LC1G1D4T 0x80
8485 //==============================================================================
8488 //==============================================================================
8491 extern __at(0x0F17) __sfr CLC1GLS1
;
8497 unsigned LC1G2D1N
: 1;
8498 unsigned LC1G2D1T
: 1;
8499 unsigned LC1G2D2N
: 1;
8500 unsigned LC1G2D2T
: 1;
8501 unsigned LC1G2D3N
: 1;
8502 unsigned LC1G2D3T
: 1;
8503 unsigned LC1G2D4N
: 1;
8504 unsigned LC1G2D4T
: 1;
8520 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
8522 #define _CLC1GLS1_LC1G2D1N 0x01
8523 #define _CLC1GLS1_D1N 0x01
8524 #define _CLC1GLS1_LC1G2D1T 0x02
8525 #define _CLC1GLS1_D1T 0x02
8526 #define _CLC1GLS1_LC1G2D2N 0x04
8527 #define _CLC1GLS1_D2N 0x04
8528 #define _CLC1GLS1_LC1G2D2T 0x08
8529 #define _CLC1GLS1_D2T 0x08
8530 #define _CLC1GLS1_LC1G2D3N 0x10
8531 #define _CLC1GLS1_D3N 0x10
8532 #define _CLC1GLS1_LC1G2D3T 0x20
8533 #define _CLC1GLS1_D3T 0x20
8534 #define _CLC1GLS1_LC1G2D4N 0x40
8535 #define _CLC1GLS1_D4N 0x40
8536 #define _CLC1GLS1_LC1G2D4T 0x80
8537 #define _CLC1GLS1_D4T 0x80
8539 //==============================================================================
8542 //==============================================================================
8545 extern __at(0x0F18) __sfr CLC1GLS2
;
8551 unsigned LC1G3D1N
: 1;
8552 unsigned LC1G3D1T
: 1;
8553 unsigned LC1G3D2N
: 1;
8554 unsigned LC1G3D2T
: 1;
8555 unsigned LC1G3D3N
: 1;
8556 unsigned LC1G3D3T
: 1;
8557 unsigned LC1G3D4N
: 1;
8558 unsigned LC1G3D4T
: 1;
8574 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
8576 #define _CLC1GLS2_LC1G3D1N 0x01
8577 #define _CLC1GLS2_D1N 0x01
8578 #define _CLC1GLS2_LC1G3D1T 0x02
8579 #define _CLC1GLS2_D1T 0x02
8580 #define _CLC1GLS2_LC1G3D2N 0x04
8581 #define _CLC1GLS2_D2N 0x04
8582 #define _CLC1GLS2_LC1G3D2T 0x08
8583 #define _CLC1GLS2_D2T 0x08
8584 #define _CLC1GLS2_LC1G3D3N 0x10
8585 #define _CLC1GLS2_D3N 0x10
8586 #define _CLC1GLS2_LC1G3D3T 0x20
8587 #define _CLC1GLS2_D3T 0x20
8588 #define _CLC1GLS2_LC1G3D4N 0x40
8589 #define _CLC1GLS2_D4N 0x40
8590 #define _CLC1GLS2_LC1G3D4T 0x80
8591 #define _CLC1GLS2_D4T 0x80
8593 //==============================================================================
8596 //==============================================================================
8599 extern __at(0x0F19) __sfr CLC1GLS3
;
8605 unsigned LC1G4D1N
: 1;
8606 unsigned LC1G4D1T
: 1;
8607 unsigned LC1G4D2N
: 1;
8608 unsigned LC1G4D2T
: 1;
8609 unsigned LC1G4D3N
: 1;
8610 unsigned LC1G4D3T
: 1;
8611 unsigned LC1G4D4N
: 1;
8612 unsigned LC1G4D4T
: 1;
8628 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
8630 #define _LC1G4D1N 0x01
8632 #define _LC1G4D1T 0x02
8634 #define _LC1G4D2N 0x04
8636 #define _LC1G4D2T 0x08
8638 #define _LC1G4D3N 0x10
8640 #define _LC1G4D3T 0x20
8642 #define _LC1G4D4N 0x40
8644 #define _LC1G4D4T 0x80
8647 //==============================================================================
8650 //==============================================================================
8653 extern __at(0x0F1A) __sfr CLC2CON
;
8659 unsigned LC2MODE0
: 1;
8660 unsigned LC2MODE1
: 1;
8661 unsigned LC2MODE2
: 1;
8662 unsigned LC2INTN
: 1;
8663 unsigned LC2INTP
: 1;
8664 unsigned LC2OUT
: 1;
8689 unsigned LC2MODE
: 3;
8694 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
8696 #define _CLC2CON_LC2MODE0 0x01
8697 #define _CLC2CON_MODE0 0x01
8698 #define _CLC2CON_LC2MODE1 0x02
8699 #define _CLC2CON_MODE1 0x02
8700 #define _CLC2CON_LC2MODE2 0x04
8701 #define _CLC2CON_MODE2 0x04
8702 #define _CLC2CON_LC2INTN 0x08
8703 #define _CLC2CON_INTN 0x08
8704 #define _CLC2CON_LC2INTP 0x10
8705 #define _CLC2CON_INTP 0x10
8706 #define _CLC2CON_LC2OUT 0x20
8707 #define _CLC2CON_OUT 0x20
8708 #define _CLC2CON_LC2EN 0x80
8709 #define _CLC2CON_EN 0x80
8711 //==============================================================================
8714 //==============================================================================
8717 extern __at(0x0F1B) __sfr CLC2POL
;
8723 unsigned LC2G1POL
: 1;
8724 unsigned LC2G2POL
: 1;
8725 unsigned LC2G3POL
: 1;
8726 unsigned LC2G4POL
: 1;
8730 unsigned LC2POL
: 1;
8746 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
8748 #define _CLC2POL_LC2G1POL 0x01
8749 #define _CLC2POL_G1POL 0x01
8750 #define _CLC2POL_LC2G2POL 0x02
8751 #define _CLC2POL_G2POL 0x02
8752 #define _CLC2POL_LC2G3POL 0x04
8753 #define _CLC2POL_G3POL 0x04
8754 #define _CLC2POL_LC2G4POL 0x08
8755 #define _CLC2POL_G4POL 0x08
8756 #define _CLC2POL_LC2POL 0x80
8757 #define _CLC2POL_POL 0x80
8759 //==============================================================================
8762 //==============================================================================
8765 extern __at(0x0F1C) __sfr CLC2SEL0
;
8771 unsigned LC2D1S0
: 1;
8772 unsigned LC2D1S1
: 1;
8773 unsigned LC2D1S2
: 1;
8774 unsigned LC2D1S3
: 1;
8775 unsigned LC2D1S4
: 1;
8776 unsigned LC2D1S5
: 1;
8795 unsigned LC2D1S
: 6;
8806 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
8808 #define _CLC2SEL0_LC2D1S0 0x01
8809 #define _CLC2SEL0_D1S0 0x01
8810 #define _CLC2SEL0_LC2D1S1 0x02
8811 #define _CLC2SEL0_D1S1 0x02
8812 #define _CLC2SEL0_LC2D1S2 0x04
8813 #define _CLC2SEL0_D1S2 0x04
8814 #define _CLC2SEL0_LC2D1S3 0x08
8815 #define _CLC2SEL0_D1S3 0x08
8816 #define _CLC2SEL0_LC2D1S4 0x10
8817 #define _CLC2SEL0_D1S4 0x10
8818 #define _CLC2SEL0_LC2D1S5 0x20
8819 #define _CLC2SEL0_D1S5 0x20
8821 //==============================================================================
8824 //==============================================================================
8827 extern __at(0x0F1D) __sfr CLC2SEL1
;
8833 unsigned LC2D2S0
: 1;
8834 unsigned LC2D2S1
: 1;
8835 unsigned LC2D2S2
: 1;
8836 unsigned LC2D2S3
: 1;
8837 unsigned LC2D2S4
: 1;
8838 unsigned LC2D2S5
: 1;
8857 unsigned LC2D2S
: 6;
8868 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
8870 #define _CLC2SEL1_LC2D2S0 0x01
8871 #define _CLC2SEL1_D2S0 0x01
8872 #define _CLC2SEL1_LC2D2S1 0x02
8873 #define _CLC2SEL1_D2S1 0x02
8874 #define _CLC2SEL1_LC2D2S2 0x04
8875 #define _CLC2SEL1_D2S2 0x04
8876 #define _CLC2SEL1_LC2D2S3 0x08
8877 #define _CLC2SEL1_D2S3 0x08
8878 #define _CLC2SEL1_LC2D2S4 0x10
8879 #define _CLC2SEL1_D2S4 0x10
8880 #define _CLC2SEL1_LC2D2S5 0x20
8881 #define _CLC2SEL1_D2S5 0x20
8883 //==============================================================================
8886 //==============================================================================
8889 extern __at(0x0F1E) __sfr CLC2SEL2
;
8895 unsigned LC2D3S0
: 1;
8896 unsigned LC2D3S1
: 1;
8897 unsigned LC2D3S2
: 1;
8898 unsigned LC2D3S3
: 1;
8899 unsigned LC2D3S4
: 1;
8900 unsigned LC2D3S5
: 1;
8925 unsigned LC2D3S
: 6;
8930 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
8932 #define _CLC2SEL2_LC2D3S0 0x01
8933 #define _CLC2SEL2_D3S0 0x01
8934 #define _CLC2SEL2_LC2D3S1 0x02
8935 #define _CLC2SEL2_D3S1 0x02
8936 #define _CLC2SEL2_LC2D3S2 0x04
8937 #define _CLC2SEL2_D3S2 0x04
8938 #define _CLC2SEL2_LC2D3S3 0x08
8939 #define _CLC2SEL2_D3S3 0x08
8940 #define _CLC2SEL2_LC2D3S4 0x10
8941 #define _CLC2SEL2_D3S4 0x10
8942 #define _CLC2SEL2_LC2D3S5 0x20
8943 #define _CLC2SEL2_D3S5 0x20
8945 //==============================================================================
8948 //==============================================================================
8951 extern __at(0x0F1F) __sfr CLC2SEL3
;
8957 unsigned LC2D4S0
: 1;
8958 unsigned LC2D4S1
: 1;
8959 unsigned LC2D4S2
: 1;
8960 unsigned LC2D4S3
: 1;
8961 unsigned LC2D4S4
: 1;
8962 unsigned LC2D4S5
: 1;
8981 unsigned LC2D4S
: 6;
8992 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
8994 #define _CLC2SEL3_LC2D4S0 0x01
8995 #define _CLC2SEL3_D4S0 0x01
8996 #define _CLC2SEL3_LC2D4S1 0x02
8997 #define _CLC2SEL3_D4S1 0x02
8998 #define _CLC2SEL3_LC2D4S2 0x04
8999 #define _CLC2SEL3_D4S2 0x04
9000 #define _CLC2SEL3_LC2D4S3 0x08
9001 #define _CLC2SEL3_D4S3 0x08
9002 #define _CLC2SEL3_LC2D4S4 0x10
9003 #define _CLC2SEL3_D4S4 0x10
9004 #define _CLC2SEL3_LC2D4S5 0x20
9005 #define _CLC2SEL3_D4S5 0x20
9007 //==============================================================================
9010 //==============================================================================
9013 extern __at(0x0F20) __sfr CLC2GLS0
;
9019 unsigned LC2G1D1N
: 1;
9020 unsigned LC2G1D1T
: 1;
9021 unsigned LC2G1D2N
: 1;
9022 unsigned LC2G1D2T
: 1;
9023 unsigned LC2G1D3N
: 1;
9024 unsigned LC2G1D3T
: 1;
9025 unsigned LC2G1D4N
: 1;
9026 unsigned LC2G1D4T
: 1;
9042 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
9044 #define _CLC2GLS0_LC2G1D1N 0x01
9045 #define _CLC2GLS0_D1N 0x01
9046 #define _CLC2GLS0_LC2G1D1T 0x02
9047 #define _CLC2GLS0_D1T 0x02
9048 #define _CLC2GLS0_LC2G1D2N 0x04
9049 #define _CLC2GLS0_D2N 0x04
9050 #define _CLC2GLS0_LC2G1D2T 0x08
9051 #define _CLC2GLS0_D2T 0x08
9052 #define _CLC2GLS0_LC2G1D3N 0x10
9053 #define _CLC2GLS0_D3N 0x10
9054 #define _CLC2GLS0_LC2G1D3T 0x20
9055 #define _CLC2GLS0_D3T 0x20
9056 #define _CLC2GLS0_LC2G1D4N 0x40
9057 #define _CLC2GLS0_D4N 0x40
9058 #define _CLC2GLS0_LC2G1D4T 0x80
9059 #define _CLC2GLS0_D4T 0x80
9061 //==============================================================================
9064 //==============================================================================
9067 extern __at(0x0F21) __sfr CLC2GLS1
;
9073 unsigned LC2G2D1N
: 1;
9074 unsigned LC2G2D1T
: 1;
9075 unsigned LC2G2D2N
: 1;
9076 unsigned LC2G2D2T
: 1;
9077 unsigned LC2G2D3N
: 1;
9078 unsigned LC2G2D3T
: 1;
9079 unsigned LC2G2D4N
: 1;
9080 unsigned LC2G2D4T
: 1;
9096 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
9098 #define _CLC2GLS1_LC2G2D1N 0x01
9099 #define _CLC2GLS1_D1N 0x01
9100 #define _CLC2GLS1_LC2G2D1T 0x02
9101 #define _CLC2GLS1_D1T 0x02
9102 #define _CLC2GLS1_LC2G2D2N 0x04
9103 #define _CLC2GLS1_D2N 0x04
9104 #define _CLC2GLS1_LC2G2D2T 0x08
9105 #define _CLC2GLS1_D2T 0x08
9106 #define _CLC2GLS1_LC2G2D3N 0x10
9107 #define _CLC2GLS1_D3N 0x10
9108 #define _CLC2GLS1_LC2G2D3T 0x20
9109 #define _CLC2GLS1_D3T 0x20
9110 #define _CLC2GLS1_LC2G2D4N 0x40
9111 #define _CLC2GLS1_D4N 0x40
9112 #define _CLC2GLS1_LC2G2D4T 0x80
9113 #define _CLC2GLS1_D4T 0x80
9115 //==============================================================================
9118 //==============================================================================
9121 extern __at(0x0F22) __sfr CLC2GLS2
;
9127 unsigned LC2G3D1N
: 1;
9128 unsigned LC2G3D1T
: 1;
9129 unsigned LC2G3D2N
: 1;
9130 unsigned LC2G3D2T
: 1;
9131 unsigned LC2G3D3N
: 1;
9132 unsigned LC2G3D3T
: 1;
9133 unsigned LC2G3D4N
: 1;
9134 unsigned LC2G3D4T
: 1;
9150 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
9152 #define _CLC2GLS2_LC2G3D1N 0x01
9153 #define _CLC2GLS2_D1N 0x01
9154 #define _CLC2GLS2_LC2G3D1T 0x02
9155 #define _CLC2GLS2_D1T 0x02
9156 #define _CLC2GLS2_LC2G3D2N 0x04
9157 #define _CLC2GLS2_D2N 0x04
9158 #define _CLC2GLS2_LC2G3D2T 0x08
9159 #define _CLC2GLS2_D2T 0x08
9160 #define _CLC2GLS2_LC2G3D3N 0x10
9161 #define _CLC2GLS2_D3N 0x10
9162 #define _CLC2GLS2_LC2G3D3T 0x20
9163 #define _CLC2GLS2_D3T 0x20
9164 #define _CLC2GLS2_LC2G3D4N 0x40
9165 #define _CLC2GLS2_D4N 0x40
9166 #define _CLC2GLS2_LC2G3D4T 0x80
9167 #define _CLC2GLS2_D4T 0x80
9169 //==============================================================================
9172 //==============================================================================
9175 extern __at(0x0F23) __sfr CLC2GLS3
;
9181 unsigned LC2G4D1N
: 1;
9182 unsigned LC2G4D1T
: 1;
9183 unsigned LC2G4D2N
: 1;
9184 unsigned LC2G4D2T
: 1;
9185 unsigned LC2G4D3N
: 1;
9186 unsigned LC2G4D3T
: 1;
9187 unsigned LC2G4D4N
: 1;
9188 unsigned LC2G4D4T
: 1;
9204 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
9206 #define _CLC2GLS3_LC2G4D1N 0x01
9207 #define _CLC2GLS3_G4D1N 0x01
9208 #define _CLC2GLS3_LC2G4D1T 0x02
9209 #define _CLC2GLS3_G4D1T 0x02
9210 #define _CLC2GLS3_LC2G4D2N 0x04
9211 #define _CLC2GLS3_G4D2N 0x04
9212 #define _CLC2GLS3_LC2G4D2T 0x08
9213 #define _CLC2GLS3_G4D2T 0x08
9214 #define _CLC2GLS3_LC2G4D3N 0x10
9215 #define _CLC2GLS3_G4D3N 0x10
9216 #define _CLC2GLS3_LC2G4D3T 0x20
9217 #define _CLC2GLS3_G4D3T 0x20
9218 #define _CLC2GLS3_LC2G4D4N 0x40
9219 #define _CLC2GLS3_G4D4N 0x40
9220 #define _CLC2GLS3_LC2G4D4T 0x80
9221 #define _CLC2GLS3_G4D4T 0x80
9223 //==============================================================================
9226 //==============================================================================
9229 extern __at(0x0F24) __sfr CLC3CON
;
9235 unsigned LC3MODE0
: 1;
9236 unsigned LC3MODE1
: 1;
9237 unsigned LC3MODE2
: 1;
9238 unsigned LC3INTN
: 1;
9239 unsigned LC3INTP
: 1;
9240 unsigned LC3OUT
: 1;
9265 unsigned LC3MODE
: 3;
9270 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
9272 #define _CLC3CON_LC3MODE0 0x01
9273 #define _CLC3CON_MODE0 0x01
9274 #define _CLC3CON_LC3MODE1 0x02
9275 #define _CLC3CON_MODE1 0x02
9276 #define _CLC3CON_LC3MODE2 0x04
9277 #define _CLC3CON_MODE2 0x04
9278 #define _CLC3CON_LC3INTN 0x08
9279 #define _CLC3CON_INTN 0x08
9280 #define _CLC3CON_LC3INTP 0x10
9281 #define _CLC3CON_INTP 0x10
9282 #define _CLC3CON_LC3OUT 0x20
9283 #define _CLC3CON_OUT 0x20
9284 #define _CLC3CON_LC3EN 0x80
9285 #define _CLC3CON_EN 0x80
9287 //==============================================================================
9290 //==============================================================================
9293 extern __at(0x0F25) __sfr CLC3POL
;
9299 unsigned LC3G1POL
: 1;
9300 unsigned LC3G2POL
: 1;
9301 unsigned LC3G3POL
: 1;
9302 unsigned LC3G4POL
: 1;
9306 unsigned LC3POL
: 1;
9322 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
9324 #define _CLC3POL_LC3G1POL 0x01
9325 #define _CLC3POL_G1POL 0x01
9326 #define _CLC3POL_LC3G2POL 0x02
9327 #define _CLC3POL_G2POL 0x02
9328 #define _CLC3POL_LC3G3POL 0x04
9329 #define _CLC3POL_G3POL 0x04
9330 #define _CLC3POL_LC3G4POL 0x08
9331 #define _CLC3POL_G4POL 0x08
9332 #define _CLC3POL_LC3POL 0x80
9333 #define _CLC3POL_POL 0x80
9335 //==============================================================================
9338 //==============================================================================
9341 extern __at(0x0F26) __sfr CLC3SEL0
;
9347 unsigned LC3D1S0
: 1;
9348 unsigned LC3D1S1
: 1;
9349 unsigned LC3D1S2
: 1;
9350 unsigned LC3D1S3
: 1;
9351 unsigned LC3D1S4
: 1;
9352 unsigned LC3D1S5
: 1;
9371 unsigned LC3D1S
: 6;
9382 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
9384 #define _CLC3SEL0_LC3D1S0 0x01
9385 #define _CLC3SEL0_D1S0 0x01
9386 #define _CLC3SEL0_LC3D1S1 0x02
9387 #define _CLC3SEL0_D1S1 0x02
9388 #define _CLC3SEL0_LC3D1S2 0x04
9389 #define _CLC3SEL0_D1S2 0x04
9390 #define _CLC3SEL0_LC3D1S3 0x08
9391 #define _CLC3SEL0_D1S3 0x08
9392 #define _CLC3SEL0_LC3D1S4 0x10
9393 #define _CLC3SEL0_D1S4 0x10
9394 #define _CLC3SEL0_LC3D1S5 0x20
9395 #define _CLC3SEL0_D1S5 0x20
9397 //==============================================================================
9400 //==============================================================================
9403 extern __at(0x0F27) __sfr CLC3SEL1
;
9409 unsigned LC3D2S0
: 1;
9410 unsigned LC3D2S1
: 1;
9411 unsigned LC3D2S2
: 1;
9412 unsigned LC3D2S3
: 1;
9413 unsigned LC3D2S4
: 1;
9414 unsigned LC3D2S5
: 1;
9439 unsigned LC3D2S
: 6;
9444 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
9446 #define _CLC3SEL1_LC3D2S0 0x01
9447 #define _CLC3SEL1_D2S0 0x01
9448 #define _CLC3SEL1_LC3D2S1 0x02
9449 #define _CLC3SEL1_D2S1 0x02
9450 #define _CLC3SEL1_LC3D2S2 0x04
9451 #define _CLC3SEL1_D2S2 0x04
9452 #define _CLC3SEL1_LC3D2S3 0x08
9453 #define _CLC3SEL1_D2S3 0x08
9454 #define _CLC3SEL1_LC3D2S4 0x10
9455 #define _CLC3SEL1_D2S4 0x10
9456 #define _CLC3SEL1_LC3D2S5 0x20
9457 #define _CLC3SEL1_D2S5 0x20
9459 //==============================================================================
9462 //==============================================================================
9465 extern __at(0x0F28) __sfr CLC3SEL2
;
9471 unsigned LC3D3S0
: 1;
9472 unsigned LC3D3S1
: 1;
9473 unsigned LC3D3S2
: 1;
9474 unsigned LC3D3S3
: 1;
9475 unsigned LC3D3S4
: 1;
9476 unsigned LC3D3S5
: 1;
9501 unsigned LC3D3S
: 6;
9506 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
9508 #define _CLC3SEL2_LC3D3S0 0x01
9509 #define _CLC3SEL2_D3S0 0x01
9510 #define _CLC3SEL2_LC3D3S1 0x02
9511 #define _CLC3SEL2_D3S1 0x02
9512 #define _CLC3SEL2_LC3D3S2 0x04
9513 #define _CLC3SEL2_D3S2 0x04
9514 #define _CLC3SEL2_LC3D3S3 0x08
9515 #define _CLC3SEL2_D3S3 0x08
9516 #define _CLC3SEL2_LC3D3S4 0x10
9517 #define _CLC3SEL2_D3S4 0x10
9518 #define _CLC3SEL2_LC3D3S5 0x20
9519 #define _CLC3SEL2_D3S5 0x20
9521 //==============================================================================
9524 //==============================================================================
9527 extern __at(0x0F29) __sfr CLC3SEL3
;
9533 unsigned LC3D4S0
: 1;
9534 unsigned LC3D4S1
: 1;
9535 unsigned LC3D4S2
: 1;
9536 unsigned LC3D4S3
: 1;
9537 unsigned LC3D4S4
: 1;
9538 unsigned LC3D4S5
: 1;
9563 unsigned LC3D4S
: 6;
9568 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
9570 #define _CLC3SEL3_LC3D4S0 0x01
9571 #define _CLC3SEL3_D4S0 0x01
9572 #define _CLC3SEL3_LC3D4S1 0x02
9573 #define _CLC3SEL3_D4S1 0x02
9574 #define _CLC3SEL3_LC3D4S2 0x04
9575 #define _CLC3SEL3_D4S2 0x04
9576 #define _CLC3SEL3_LC3D4S3 0x08
9577 #define _CLC3SEL3_D4S3 0x08
9578 #define _CLC3SEL3_LC3D4S4 0x10
9579 #define _CLC3SEL3_D4S4 0x10
9580 #define _CLC3SEL3_LC3D4S5 0x20
9581 #define _CLC3SEL3_D4S5 0x20
9583 //==============================================================================
9586 //==============================================================================
9589 extern __at(0x0F2A) __sfr CLC3GLS0
;
9595 unsigned LC3G1D1N
: 1;
9596 unsigned LC3G1D1T
: 1;
9597 unsigned LC3G1D2N
: 1;
9598 unsigned LC3G1D2T
: 1;
9599 unsigned LC3G1D3N
: 1;
9600 unsigned LC3G1D3T
: 1;
9601 unsigned LC3G1D4N
: 1;
9602 unsigned LC3G1D4T
: 1;
9618 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
9620 #define _CLC3GLS0_LC3G1D1N 0x01
9621 #define _CLC3GLS0_D1N 0x01
9622 #define _CLC3GLS0_LC3G1D1T 0x02
9623 #define _CLC3GLS0_D1T 0x02
9624 #define _CLC3GLS0_LC3G1D2N 0x04
9625 #define _CLC3GLS0_D2N 0x04
9626 #define _CLC3GLS0_LC3G1D2T 0x08
9627 #define _CLC3GLS0_D2T 0x08
9628 #define _CLC3GLS0_LC3G1D3N 0x10
9629 #define _CLC3GLS0_D3N 0x10
9630 #define _CLC3GLS0_LC3G1D3T 0x20
9631 #define _CLC3GLS0_D3T 0x20
9632 #define _CLC3GLS0_LC3G1D4N 0x40
9633 #define _CLC3GLS0_D4N 0x40
9634 #define _CLC3GLS0_LC3G1D4T 0x80
9635 #define _CLC3GLS0_D4T 0x80
9637 //==============================================================================
9640 //==============================================================================
9643 extern __at(0x0F2B) __sfr CLC3GLS1
;
9649 unsigned LC3G2D1N
: 1;
9650 unsigned LC3G2D1T
: 1;
9651 unsigned LC3G2D2N
: 1;
9652 unsigned LC3G2D2T
: 1;
9653 unsigned LC3G2D3N
: 1;
9654 unsigned LC3G2D3T
: 1;
9655 unsigned LC3G2D4N
: 1;
9656 unsigned LC3G2D4T
: 1;
9672 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
9674 #define _CLC3GLS1_LC3G2D1N 0x01
9675 #define _CLC3GLS1_D1N 0x01
9676 #define _CLC3GLS1_LC3G2D1T 0x02
9677 #define _CLC3GLS1_D1T 0x02
9678 #define _CLC3GLS1_LC3G2D2N 0x04
9679 #define _CLC3GLS1_D2N 0x04
9680 #define _CLC3GLS1_LC3G2D2T 0x08
9681 #define _CLC3GLS1_D2T 0x08
9682 #define _CLC3GLS1_LC3G2D3N 0x10
9683 #define _CLC3GLS1_D3N 0x10
9684 #define _CLC3GLS1_LC3G2D3T 0x20
9685 #define _CLC3GLS1_D3T 0x20
9686 #define _CLC3GLS1_LC3G2D4N 0x40
9687 #define _CLC3GLS1_D4N 0x40
9688 #define _CLC3GLS1_LC3G2D4T 0x80
9689 #define _CLC3GLS1_D4T 0x80
9691 //==============================================================================
9694 //==============================================================================
9697 extern __at(0x0F2C) __sfr CLC3GLS2
;
9703 unsigned LC3G3D1N
: 1;
9704 unsigned LC3G3D1T
: 1;
9705 unsigned LC3G3D2N
: 1;
9706 unsigned LC3G3D2T
: 1;
9707 unsigned LC3G3D3N
: 1;
9708 unsigned LC3G3D3T
: 1;
9709 unsigned LC3G3D4N
: 1;
9710 unsigned LC3G3D4T
: 1;
9726 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
9728 #define _CLC3GLS2_LC3G3D1N 0x01
9729 #define _CLC3GLS2_D1N 0x01
9730 #define _CLC3GLS2_LC3G3D1T 0x02
9731 #define _CLC3GLS2_D1T 0x02
9732 #define _CLC3GLS2_LC3G3D2N 0x04
9733 #define _CLC3GLS2_D2N 0x04
9734 #define _CLC3GLS2_LC3G3D2T 0x08
9735 #define _CLC3GLS2_D2T 0x08
9736 #define _CLC3GLS2_LC3G3D3N 0x10
9737 #define _CLC3GLS2_D3N 0x10
9738 #define _CLC3GLS2_LC3G3D3T 0x20
9739 #define _CLC3GLS2_D3T 0x20
9740 #define _CLC3GLS2_LC3G3D4N 0x40
9741 #define _CLC3GLS2_D4N 0x40
9742 #define _CLC3GLS2_LC3G3D4T 0x80
9743 #define _CLC3GLS2_D4T 0x80
9745 //==============================================================================
9748 //==============================================================================
9751 extern __at(0x0F2D) __sfr CLC3GLS3
;
9757 unsigned LC3G4D1N
: 1;
9758 unsigned LC3G4D1T
: 1;
9759 unsigned LC3G4D2N
: 1;
9760 unsigned LC3G4D2T
: 1;
9761 unsigned LC3G4D3N
: 1;
9762 unsigned LC3G4D3T
: 1;
9763 unsigned LC3G4D4N
: 1;
9764 unsigned LC3G4D4T
: 1;
9780 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
9782 #define _CLC3GLS3_LC3G4D1N 0x01
9783 #define _CLC3GLS3_G4D1N 0x01
9784 #define _CLC3GLS3_LC3G4D1T 0x02
9785 #define _CLC3GLS3_G4D1T 0x02
9786 #define _CLC3GLS3_LC3G4D2N 0x04
9787 #define _CLC3GLS3_G4D2N 0x04
9788 #define _CLC3GLS3_LC3G4D2T 0x08
9789 #define _CLC3GLS3_G4D2T 0x08
9790 #define _CLC3GLS3_LC3G4D3N 0x10
9791 #define _CLC3GLS3_G4D3N 0x10
9792 #define _CLC3GLS3_LC3G4D3T 0x20
9793 #define _CLC3GLS3_G4D3T 0x20
9794 #define _CLC3GLS3_LC3G4D4N 0x40
9795 #define _CLC3GLS3_G4D4N 0x40
9796 #define _CLC3GLS3_LC3G4D4T 0x80
9797 #define _CLC3GLS3_G4D4T 0x80
9799 //==============================================================================
9802 //==============================================================================
9805 extern __at(0x0F2E) __sfr CLC4CON
;
9811 unsigned LC4MODE0
: 1;
9812 unsigned LC4MODE1
: 1;
9813 unsigned LC4MODE2
: 1;
9814 unsigned LC4INTN
: 1;
9815 unsigned LC4INTP
: 1;
9816 unsigned LC4OUT
: 1;
9841 unsigned LC4MODE
: 3;
9846 extern __at(0x0F2E) volatile __CLC4CONbits_t CLC4CONbits
;
9848 #define _CLC4CON_LC4MODE0 0x01
9849 #define _CLC4CON_MODE0 0x01
9850 #define _CLC4CON_LC4MODE1 0x02
9851 #define _CLC4CON_MODE1 0x02
9852 #define _CLC4CON_LC4MODE2 0x04
9853 #define _CLC4CON_MODE2 0x04
9854 #define _CLC4CON_LC4INTN 0x08
9855 #define _CLC4CON_INTN 0x08
9856 #define _CLC4CON_LC4INTP 0x10
9857 #define _CLC4CON_INTP 0x10
9858 #define _CLC4CON_LC4OUT 0x20
9859 #define _CLC4CON_OUT 0x20
9860 #define _CLC4CON_LC4EN 0x80
9861 #define _CLC4CON_EN 0x80
9863 //==============================================================================
9866 //==============================================================================
9869 extern __at(0x0F2F) __sfr CLC4POL
;
9875 unsigned LC4G1POL
: 1;
9876 unsigned LC4G2POL
: 1;
9877 unsigned LC4G3POL
: 1;
9878 unsigned LC4G4POL
: 1;
9882 unsigned LC4POL
: 1;
9898 extern __at(0x0F2F) volatile __CLC4POLbits_t CLC4POLbits
;
9900 #define _CLC4POL_LC4G1POL 0x01
9901 #define _CLC4POL_G1POL 0x01
9902 #define _CLC4POL_LC4G2POL 0x02
9903 #define _CLC4POL_G2POL 0x02
9904 #define _CLC4POL_LC4G3POL 0x04
9905 #define _CLC4POL_G3POL 0x04
9906 #define _CLC4POL_LC4G4POL 0x08
9907 #define _CLC4POL_G4POL 0x08
9908 #define _CLC4POL_LC4POL 0x80
9909 #define _CLC4POL_POL 0x80
9911 //==============================================================================
9914 //==============================================================================
9917 extern __at(0x0F30) __sfr CLC4SEL0
;
9923 unsigned LC4D1S0
: 1;
9924 unsigned LC4D1S1
: 1;
9925 unsigned LC4D1S2
: 1;
9926 unsigned LC4D1S3
: 1;
9927 unsigned LC4D1S4
: 1;
9928 unsigned LC4D1S5
: 1;
9953 unsigned LC4D1S
: 6;
9958 extern __at(0x0F30) volatile __CLC4SEL0bits_t CLC4SEL0bits
;
9960 #define _CLC4SEL0_LC4D1S0 0x01
9961 #define _CLC4SEL0_D1S0 0x01
9962 #define _CLC4SEL0_LC4D1S1 0x02
9963 #define _CLC4SEL0_D1S1 0x02
9964 #define _CLC4SEL0_LC4D1S2 0x04
9965 #define _CLC4SEL0_D1S2 0x04
9966 #define _CLC4SEL0_LC4D1S3 0x08
9967 #define _CLC4SEL0_D1S3 0x08
9968 #define _CLC4SEL0_LC4D1S4 0x10
9969 #define _CLC4SEL0_D1S4 0x10
9970 #define _CLC4SEL0_LC4D1S5 0x20
9971 #define _CLC4SEL0_D1S5 0x20
9973 //==============================================================================
9976 //==============================================================================
9979 extern __at(0x0F31) __sfr CLC4SEL1
;
9985 unsigned LC4D2S0
: 1;
9986 unsigned LC4D2S1
: 1;
9987 unsigned LC4D2S2
: 1;
9988 unsigned LC4D2S3
: 1;
9989 unsigned LC4D2S4
: 1;
9990 unsigned LC4D2S5
: 1;
10015 unsigned LC4D2S
: 6;
10018 } __CLC4SEL1bits_t
;
10020 extern __at(0x0F31) volatile __CLC4SEL1bits_t CLC4SEL1bits
;
10022 #define _CLC4SEL1_LC4D2S0 0x01
10023 #define _CLC4SEL1_D2S0 0x01
10024 #define _CLC4SEL1_LC4D2S1 0x02
10025 #define _CLC4SEL1_D2S1 0x02
10026 #define _CLC4SEL1_LC4D2S2 0x04
10027 #define _CLC4SEL1_D2S2 0x04
10028 #define _CLC4SEL1_LC4D2S3 0x08
10029 #define _CLC4SEL1_D2S3 0x08
10030 #define _CLC4SEL1_LC4D2S4 0x10
10031 #define _CLC4SEL1_D2S4 0x10
10032 #define _CLC4SEL1_LC4D2S5 0x20
10033 #define _CLC4SEL1_D2S5 0x20
10035 //==============================================================================
10038 //==============================================================================
10041 extern __at(0x0F32) __sfr CLC4SEL2
;
10047 unsigned LC4D3S0
: 1;
10048 unsigned LC4D3S1
: 1;
10049 unsigned LC4D3S2
: 1;
10050 unsigned LC4D3S3
: 1;
10051 unsigned LC4D3S4
: 1;
10052 unsigned LC4D3S5
: 1;
10071 unsigned LC4D3S
: 6;
10080 } __CLC4SEL2bits_t
;
10082 extern __at(0x0F32) volatile __CLC4SEL2bits_t CLC4SEL2bits
;
10084 #define _CLC4SEL2_LC4D3S0 0x01
10085 #define _CLC4SEL2_D3S0 0x01
10086 #define _CLC4SEL2_LC4D3S1 0x02
10087 #define _CLC4SEL2_D3S1 0x02
10088 #define _CLC4SEL2_LC4D3S2 0x04
10089 #define _CLC4SEL2_D3S2 0x04
10090 #define _CLC4SEL2_LC4D3S3 0x08
10091 #define _CLC4SEL2_D3S3 0x08
10092 #define _CLC4SEL2_LC4D3S4 0x10
10093 #define _CLC4SEL2_D3S4 0x10
10094 #define _CLC4SEL2_LC4D3S5 0x20
10095 #define _CLC4SEL2_D3S5 0x20
10097 //==============================================================================
10100 //==============================================================================
10103 extern __at(0x0F33) __sfr CLC4SEL3
;
10109 unsigned LC4D4S0
: 1;
10110 unsigned LC4D4S1
: 1;
10111 unsigned LC4D4S2
: 1;
10112 unsigned LC4D4S3
: 1;
10113 unsigned LC4D4S4
: 1;
10114 unsigned LC4D4S5
: 1;
10139 unsigned LC4D4S
: 6;
10142 } __CLC4SEL3bits_t
;
10144 extern __at(0x0F33) volatile __CLC4SEL3bits_t CLC4SEL3bits
;
10146 #define _CLC4SEL3_LC4D4S0 0x01
10147 #define _CLC4SEL3_D4S0 0x01
10148 #define _CLC4SEL3_LC4D4S1 0x02
10149 #define _CLC4SEL3_D4S1 0x02
10150 #define _CLC4SEL3_LC4D4S2 0x04
10151 #define _CLC4SEL3_D4S2 0x04
10152 #define _CLC4SEL3_LC4D4S3 0x08
10153 #define _CLC4SEL3_D4S3 0x08
10154 #define _CLC4SEL3_LC4D4S4 0x10
10155 #define _CLC4SEL3_D4S4 0x10
10156 #define _CLC4SEL3_LC4D4S5 0x20
10157 #define _CLC4SEL3_D4S5 0x20
10159 //==============================================================================
10162 //==============================================================================
10165 extern __at(0x0F34) __sfr CLC4GLS0
;
10171 unsigned LC4G1D1N
: 1;
10172 unsigned LC4G1D1T
: 1;
10173 unsigned LC4G1D2N
: 1;
10174 unsigned LC4G1D2T
: 1;
10175 unsigned LC4G1D3N
: 1;
10176 unsigned LC4G1D3T
: 1;
10177 unsigned LC4G1D4N
: 1;
10178 unsigned LC4G1D4T
: 1;
10192 } __CLC4GLS0bits_t
;
10194 extern __at(0x0F34) volatile __CLC4GLS0bits_t CLC4GLS0bits
;
10196 #define _CLC4GLS0_LC4G1D1N 0x01
10197 #define _CLC4GLS0_D1N 0x01
10198 #define _CLC4GLS0_LC4G1D1T 0x02
10199 #define _CLC4GLS0_D1T 0x02
10200 #define _CLC4GLS0_LC4G1D2N 0x04
10201 #define _CLC4GLS0_D2N 0x04
10202 #define _CLC4GLS0_LC4G1D2T 0x08
10203 #define _CLC4GLS0_D2T 0x08
10204 #define _CLC4GLS0_LC4G1D3N 0x10
10205 #define _CLC4GLS0_D3N 0x10
10206 #define _CLC4GLS0_LC4G1D3T 0x20
10207 #define _CLC4GLS0_D3T 0x20
10208 #define _CLC4GLS0_LC4G1D4N 0x40
10209 #define _CLC4GLS0_D4N 0x40
10210 #define _CLC4GLS0_LC4G1D4T 0x80
10211 #define _CLC4GLS0_D4T 0x80
10213 //==============================================================================
10216 //==============================================================================
10219 extern __at(0x0F35) __sfr CLC4GLS1
;
10225 unsigned LC4G2D1N
: 1;
10226 unsigned LC4G2D1T
: 1;
10227 unsigned LC4G2D2N
: 1;
10228 unsigned LC4G2D2T
: 1;
10229 unsigned LC4G2D3N
: 1;
10230 unsigned LC4G2D3T
: 1;
10231 unsigned LC4G2D4N
: 1;
10232 unsigned LC4G2D4T
: 1;
10246 } __CLC4GLS1bits_t
;
10248 extern __at(0x0F35) volatile __CLC4GLS1bits_t CLC4GLS1bits
;
10250 #define _CLC4GLS1_LC4G2D1N 0x01
10251 #define _CLC4GLS1_D1N 0x01
10252 #define _CLC4GLS1_LC4G2D1T 0x02
10253 #define _CLC4GLS1_D1T 0x02
10254 #define _CLC4GLS1_LC4G2D2N 0x04
10255 #define _CLC4GLS1_D2N 0x04
10256 #define _CLC4GLS1_LC4G2D2T 0x08
10257 #define _CLC4GLS1_D2T 0x08
10258 #define _CLC4GLS1_LC4G2D3N 0x10
10259 #define _CLC4GLS1_D3N 0x10
10260 #define _CLC4GLS1_LC4G2D3T 0x20
10261 #define _CLC4GLS1_D3T 0x20
10262 #define _CLC4GLS1_LC4G2D4N 0x40
10263 #define _CLC4GLS1_D4N 0x40
10264 #define _CLC4GLS1_LC4G2D4T 0x80
10265 #define _CLC4GLS1_D4T 0x80
10267 //==============================================================================
10270 //==============================================================================
10273 extern __at(0x0F36) __sfr CLC4GLS2
;
10279 unsigned LC4G3D1N
: 1;
10280 unsigned LC4G3D1T
: 1;
10281 unsigned LC4G3D2N
: 1;
10282 unsigned LC4G3D2T
: 1;
10283 unsigned LC4G3D3N
: 1;
10284 unsigned LC4G3D3T
: 1;
10285 unsigned LC4G3D4N
: 1;
10286 unsigned LC4G3D4T
: 1;
10300 } __CLC4GLS2bits_t
;
10302 extern __at(0x0F36) volatile __CLC4GLS2bits_t CLC4GLS2bits
;
10304 #define _CLC4GLS2_LC4G3D1N 0x01
10305 #define _CLC4GLS2_D1N 0x01
10306 #define _CLC4GLS2_LC4G3D1T 0x02
10307 #define _CLC4GLS2_D1T 0x02
10308 #define _CLC4GLS2_LC4G3D2N 0x04
10309 #define _CLC4GLS2_D2N 0x04
10310 #define _CLC4GLS2_LC4G3D2T 0x08
10311 #define _CLC4GLS2_D2T 0x08
10312 #define _CLC4GLS2_LC4G3D3N 0x10
10313 #define _CLC4GLS2_D3N 0x10
10314 #define _CLC4GLS2_LC4G3D3T 0x20
10315 #define _CLC4GLS2_D3T 0x20
10316 #define _CLC4GLS2_LC4G3D4N 0x40
10317 #define _CLC4GLS2_D4N 0x40
10318 #define _CLC4GLS2_LC4G3D4T 0x80
10319 #define _CLC4GLS2_D4T 0x80
10321 //==============================================================================
10324 //==============================================================================
10327 extern __at(0x0F37) __sfr CLC4GLS3
;
10333 unsigned LC4G4D1N
: 1;
10334 unsigned LC4G4D1T
: 1;
10335 unsigned LC4G4D2N
: 1;
10336 unsigned LC4G4D2T
: 1;
10337 unsigned LC4G4D3N
: 1;
10338 unsigned LC4G4D3T
: 1;
10339 unsigned LC4G4D4N
: 1;
10340 unsigned LC4G4D4T
: 1;
10345 unsigned G4D1N
: 1;
10346 unsigned G4D1T
: 1;
10347 unsigned G4D2N
: 1;
10348 unsigned G4D2T
: 1;
10349 unsigned G4D3N
: 1;
10350 unsigned G4D3T
: 1;
10351 unsigned G4D4N
: 1;
10352 unsigned G4D4T
: 1;
10354 } __CLC4GLS3bits_t
;
10356 extern __at(0x0F37) volatile __CLC4GLS3bits_t CLC4GLS3bits
;
10358 #define _CLC4GLS3_LC4G4D1N 0x01
10359 #define _CLC4GLS3_G4D1N 0x01
10360 #define _CLC4GLS3_LC4G4D1T 0x02
10361 #define _CLC4GLS3_G4D1T 0x02
10362 #define _CLC4GLS3_LC4G4D2N 0x04
10363 #define _CLC4GLS3_G4D2N 0x04
10364 #define _CLC4GLS3_LC4G4D2T 0x08
10365 #define _CLC4GLS3_G4D2T 0x08
10366 #define _CLC4GLS3_LC4G4D3N 0x10
10367 #define _CLC4GLS3_G4D3N 0x10
10368 #define _CLC4GLS3_LC4G4D3T 0x20
10369 #define _CLC4GLS3_G4D3T 0x20
10370 #define _CLC4GLS3_LC4G4D4N 0x40
10371 #define _CLC4GLS3_G4D4N 0x40
10372 #define _CLC4GLS3_LC4G4D4T 0x80
10373 #define _CLC4GLS3_G4D4T 0x80
10375 //==============================================================================
10378 //==============================================================================
10379 // STATUS_SHAD Bits
10381 extern __at(0x0FE4) __sfr STATUS_SHAD
;
10385 unsigned C_SHAD
: 1;
10386 unsigned DC_SHAD
: 1;
10387 unsigned Z_SHAD
: 1;
10393 } __STATUS_SHADbits_t
;
10395 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
10397 #define _C_SHAD 0x01
10398 #define _DC_SHAD 0x02
10399 #define _Z_SHAD 0x04
10401 //==============================================================================
10403 extern __at(0x0FE5) __sfr WREG_SHAD
;
10404 extern __at(0x0FE6) __sfr BSR_SHAD
;
10405 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
10406 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
10407 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
10408 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
10409 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
10410 extern __at(0x0FED) __sfr STKPTR
;
10411 extern __at(0x0FEE) __sfr TOSL
;
10412 extern __at(0x0FEF) __sfr TOSH
;
10414 //==============================================================================
10416 // Configuration Bits
10418 //==============================================================================
10420 #define _CONFIG1 0x8007
10421 #define _CONFIG2 0x8008
10422 #define _CONFIG3 0x8009
10423 #define _CONFIG4 0x800A
10425 //----------------------------- CONFIG1 Options -------------------------------
10427 #define _FEXTOSC_LP 0x3FF8 // LP (crystal oscillator) optimized for 32.768 kHz.
10428 #define _FEXTOSC_XT 0x3FF9 // XT (crystal oscillator) from 100 kHz to 4 MHz.
10429 #define _FEXTOSC_HS 0x3FFA // HS (crystal oscillator) above 4 MHz.
10430 #define _FEXTOSC_OFF 0x3FFC // Oscillator not enabled.
10431 #define _FEXTOSC_ECL 0x3FFD // EC (external clock) below 100 kHz.
10432 #define _FEXTOSC_ECM 0x3FFE // EC (external clock) for 100 kHz to 8 MHz.
10433 #define _FEXTOSC_ECH 0x3FFF // EC (external clock) above 8 MHz.
10434 #define _RSTOSC_HFINT32 0x3F8F // HFINTOSC with 2x PLL (32MHz).
10435 #define _RSTOSC_EXT4X 0x3F9F // EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits.
10436 #define _RSTOSC_SOSC 0x3FBF // SOSC (31kHz).
10437 #define _RSTOSC_LFINT 0x3FCF // LFINTOSC (31kHz).
10438 #define _RSTOSC_HFINT1 0x3FEF // HFINTOSC (1MHz).
10439 #define _RSTOSC_EXT1X 0x3FFF // EXTOSC operating per FEXTOSC bits.
10440 #define _CLKOUTEN_ON 0x3EFF // CLKOUT function is enabled; FOSC/4 clock appears at OSC2.
10441 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled; I/O or oscillator function on OSC2.
10442 #define _CSWEN_OFF 0x37FF // The NOSC and NDIV bits cannot be changed by user software.
10443 #define _CSWEN_ON 0x3FFF // Writing to NOSC and NDIV is allowed.
10444 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
10445 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
10447 //----------------------------- CONFIG2 Options -------------------------------
10449 #define _MCLRE_OFF 0x3FFE // MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of port pin's WPU control bit.
10450 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR; Weak pull-up enabled.
10451 #define _PWRTE_ON 0x3FFD // PWRT enabled.
10452 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
10453 #define _WDTE_OFF 0x3FF3 // WDT disabled; SWDTEN is ignored.
10454 #define _WDTE_SWDTEN 0x3FF7 // WDT controlled by the SWDTEN bit in the WDTCON register.
10455 #define _WDTE_SLEEP 0x3FFB // WDT enabled while running and disabled in SLEEP/IDLE; SWDTEN is ignored.
10456 #define _WDTE_ON 0x3FFF // WDT enabled, SWDTEN is ignored.
10457 #define _LPBOREN_ON 0x3FDF // ULPBOR enabled.
10458 #define _LPBOREN_OFF 0x3FFF // ULPBOR disabled.
10459 #define _BOREN_OFF 0x3F3F // Brown-out Reset disabled.
10460 #define _BOREN_SBOREN 0x3F7F // Brown-out Reset enabled according to SBOREN.
10461 #define _BOREN_SLEEP 0x3FBF // Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored.
10462 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled, SBOREN bit ignored.
10463 #define _BORV_HIGH 0x3DFF // Brown-out voltage (Vbor) set to 2.7V.
10464 #define _BORV_LOW 0x3FFF // Brown-out voltage (Vbor) set to 2.45V.
10465 #define _PPS1WAY_OFF 0x37FF // The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence).
10466 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle.
10467 #define _STVREN_OFF 0x2FFF // Stack Overflow or Underflow will not cause a Reset.
10468 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
10469 #define _DEBUG_ON 0x1FFF // Background debugger enabled.
10470 #define _DEBUG_OFF 0x3FFF // Background debugger disabled.
10472 //----------------------------- CONFIG3 Options -------------------------------
10474 #define _WRT_ALL 0x3FFC // 0000h to 0FFFh write protected, no addresses may be modified.
10475 #define _WRT_HALF 0x3FFD // 0000h to 03FFh write-protected, 0400h to 0FFFh may be modified.
10476 #define _WRT_BOOT 0x3FFE // 0000h to 01FFh write-protected, 0200h to 0FFFh may be modified.
10477 #define _WRT_OFF 0x3FFF // Write protection off.
10478 #define _LVP_OFF 0x1FFF // High Voltage on MCLR/VPP must be used for programming.
10479 #define _LVP_ON 0x3FFF // Low Voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.
10481 //----------------------------- CONFIG4 Options -------------------------------
10483 #define _CP_ON 0x3FFE // User NVM code protection enabled.
10484 #define _CP_OFF 0x3FFF // User NVM code protection disabled.
10485 #define _CPD_ON 0x3FFD // Data NVM code protection enabled.
10486 #define _CPD_OFF 0x3FFF // Data NVM code protection disabled.
10488 //==============================================================================
10490 #define _DEVID1 0x8006
10492 #define _IDLOC0 0x8000
10493 #define _IDLOC1 0x8001
10494 #define _IDLOC2 0x8002
10495 #define _IDLOC3 0x8003
10497 //==============================================================================
10499 #ifndef NO_BIT_DEFINES
10501 #define ADACT0 ADACTbits.ADACT0 // bit 0
10502 #define ADACT1 ADACTbits.ADACT1 // bit 1
10503 #define ADACT2 ADACTbits.ADACT2 // bit 2
10504 #define ADACT3 ADACTbits.ADACT3 // bit 3
10505 #define ADACT4 ADACTbits.ADACT4 // bit 4
10507 #define ADON ADCON0bits.ADON // bit 0
10508 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
10509 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
10510 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
10511 #define CHS0 ADCON0bits.CHS0 // bit 2
10512 #define CHS1 ADCON0bits.CHS1 // bit 3
10513 #define CHS2 ADCON0bits.CHS2 // bit 4
10514 #define CHS3 ADCON0bits.CHS3 // bit 5
10515 #define CHS4 ADCON0bits.CHS4 // bit 6
10516 #define CHS5 ADCON0bits.CHS5 // bit 7
10518 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
10519 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
10520 #define ADNREF ADCON1bits.ADNREF // bit 2
10521 #define ADCS0 ADCON1bits.ADCS0 // bit 4
10522 #define ADCS1 ADCON1bits.ADCS1 // bit 5
10523 #define ADCS2 ADCON1bits.ADCS2 // bit 6
10524 #define ADFM ADCON1bits.ADFM // bit 7
10526 #define ANSA0 ANSELAbits.ANSA0 // bit 0
10527 #define ANSA1 ANSELAbits.ANSA1 // bit 1
10528 #define ANSA2 ANSELAbits.ANSA2 // bit 2
10529 #define ANSA4 ANSELAbits.ANSA4 // bit 4
10530 #define ANSA5 ANSELAbits.ANSA5 // bit 5
10532 #define ANSB4 ANSELBbits.ANSB4 // bit 4
10533 #define ANSB5 ANSELBbits.ANSB5 // bit 5
10534 #define ANSB6 ANSELBbits.ANSB6 // bit 6
10535 #define ANSB7 ANSELBbits.ANSB7 // bit 7
10537 #define ANSC0 ANSELCbits.ANSC0 // bit 0
10538 #define ANSC1 ANSELCbits.ANSC1 // bit 1
10539 #define ANSC2 ANSELCbits.ANSC2 // bit 2
10540 #define ANSC3 ANSELCbits.ANSC3 // bit 3
10541 #define ANSC4 ANSELCbits.ANSC4 // bit 4
10542 #define ANSC5 ANSELCbits.ANSC5 // bit 5
10543 #define ANSC6 ANSELCbits.ANSC6 // bit 6
10544 #define ANSC7 ANSELCbits.ANSC7 // bit 7
10546 #define ABDEN BAUD1CONbits.ABDEN // bit 0
10547 #define WUE BAUD1CONbits.WUE // bit 1
10548 #define BRG16 BAUD1CONbits.BRG16 // bit 3
10549 #define SCKP BAUD1CONbits.SCKP // bit 4
10550 #define RCIDL BAUD1CONbits.RCIDL // bit 6
10551 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
10553 #define BORRDY BORCONbits.BORRDY // bit 0
10554 #define SBOREN BORCONbits.SBOREN // bit 7
10556 #define BSR0 BSRbits.BSR0 // bit 0
10557 #define BSR1 BSRbits.BSR1 // bit 1
10558 #define BSR2 BSRbits.BSR2 // bit 2
10559 #define BSR3 BSRbits.BSR3 // bit 3
10560 #define BSR4 BSRbits.BSR4 // bit 4
10562 #define CCDS0 CCDCONbits.CCDS0 // bit 0
10563 #define CCDS1 CCDCONbits.CCDS1 // bit 1
10564 #define CCDEN CCDCONbits.CCDEN // bit 7
10566 #define CCDNA0 CCDNAbits.CCDNA0 // bit 0
10567 #define CCDNA1 CCDNAbits.CCDNA1 // bit 1
10568 #define CCDNA2 CCDNAbits.CCDNA2 // bit 2
10569 #define CCDNA4 CCDNAbits.CCDNA4 // bit 4
10570 #define CCDNA5 CCDNAbits.CCDNA5 // bit 5
10572 #define CCDNB4 CCDNBbits.CCDNB4 // bit 4
10573 #define CCDNB5 CCDNBbits.CCDNB5 // bit 5
10574 #define CCDNB6 CCDNBbits.CCDNB6 // bit 6
10575 #define CCDNB7 CCDNBbits.CCDNB7 // bit 7
10577 #define CCDNC0 CCDNCbits.CCDNC0 // bit 0
10578 #define CCDNC1 CCDNCbits.CCDNC1 // bit 1
10579 #define CCDNC2 CCDNCbits.CCDNC2 // bit 2
10580 #define CCDNC3 CCDNCbits.CCDNC3 // bit 3
10581 #define CCDNC4 CCDNCbits.CCDNC4 // bit 4
10582 #define CCDNC5 CCDNCbits.CCDNC5 // bit 5
10583 #define CCDNC6 CCDNCbits.CCDNC6 // bit 6
10584 #define CCDNC7 CCDNCbits.CCDNC7 // bit 7
10586 #define CCDPA0 CCDPAbits.CCDPA0 // bit 0
10587 #define CCDPA1 CCDPAbits.CCDPA1 // bit 1
10588 #define CCDPA2 CCDPAbits.CCDPA2 // bit 2
10589 #define CCDPA4 CCDPAbits.CCDPA4 // bit 4
10590 #define CCDPA5 CCDPAbits.CCDPA5 // bit 5
10592 #define CCDPB4 CCDPBbits.CCDPB4 // bit 4
10593 #define CCDPB5 CCDPBbits.CCDPB5 // bit 5
10594 #define CCDPB6 CCDPBbits.CCDPB6 // bit 6
10595 #define CCDPB7 CCDPBbits.CCDPB7 // bit 7
10597 #define CCDPC0 CCDPCbits.CCDPC0 // bit 0
10598 #define CCDPC1 CCDPCbits.CCDPC1 // bit 1
10599 #define CCDPC2 CCDPCbits.CCDPC2 // bit 2
10600 #define CCDPC3 CCDPCbits.CCDPC3 // bit 3
10601 #define CCDPC4 CCDPCbits.CCDPC4 // bit 4
10602 #define CCDPC5 CCDPCbits.CCDPC5 // bit 5
10603 #define CCDPC6 CCDPCbits.CCDPC6 // bit 6
10604 #define CCDPC7 CCDPCbits.CCDPC7 // bit 7
10606 #define CCP1CTS0 CCP1CAPbits.CCP1CTS0 // bit 0
10607 #define CCP1CTS1 CCP1CAPbits.CCP1CTS1 // bit 1
10608 #define CCP1CTS2 CCP1CAPbits.CCP1CTS2 // bit 2
10609 #define CCP1CTS3 CCP1CAPbits.CCP1CTS3 // bit 3
10611 #define CCP1MODE0 CCP1CONbits.CCP1MODE0 // bit 0
10612 #define CCP1MODE1 CCP1CONbits.CCP1MODE1 // bit 1
10613 #define CCP1MODE2 CCP1CONbits.CCP1MODE2 // bit 2
10614 #define CCP1MODE3 CCP1CONbits.CCP1MODE3 // bit 3
10615 #define CCP1FMT CCP1CONbits.CCP1FMT // bit 4
10616 #define CCP1OUT CCP1CONbits.CCP1OUT // bit 5
10617 #define CCP1EN CCP1CONbits.CCP1EN // bit 7
10619 #define CCP1PPS0 CCP1PPSbits.CCP1PPS0 // bit 0
10620 #define CCP1PPS1 CCP1PPSbits.CCP1PPS1 // bit 1
10621 #define CCP1PPS2 CCP1PPSbits.CCP1PPS2 // bit 2
10622 #define CCP1PPS3 CCP1PPSbits.CCP1PPS3 // bit 3
10623 #define CCP1PPS4 CCP1PPSbits.CCP1PPS4 // bit 4
10625 #define CCP2CTS0 CCP2CAPbits.CCP2CTS0 // bit 0
10626 #define CCP2CTS1 CCP2CAPbits.CCP2CTS1 // bit 1
10627 #define CCP2CTS2 CCP2CAPbits.CCP2CTS2 // bit 2
10628 #define CCP2CTS3 CCP2CAPbits.CCP2CTS3 // bit 3
10630 #define CCP2MODE0 CCP2CONbits.CCP2MODE0 // bit 0
10631 #define CCP2MODE1 CCP2CONbits.CCP2MODE1 // bit 1
10632 #define CCP2MODE2 CCP2CONbits.CCP2MODE2 // bit 2
10633 #define CCP2MODE3 CCP2CONbits.CCP2MODE3 // bit 3
10634 #define CCP2FMT CCP2CONbits.CCP2FMT // bit 4
10635 #define CCP2OUT CCP2CONbits.CCP2OUT // bit 5
10636 #define CCP2EN CCP2CONbits.CCP2EN // bit 7
10638 #define CCP2PPS0 CCP2PPSbits.CCP2PPS0 // bit 0
10639 #define CCP2PPS1 CCP2PPSbits.CCP2PPS1 // bit 1
10640 #define CCP2PPS2 CCP2PPSbits.CCP2PPS2 // bit 2
10641 #define CCP2PPS3 CCP2PPSbits.CCP2PPS3 // bit 3
10642 #define CCP2PPS4 CCP2PPSbits.CCP2PPS4 // bit 4
10644 #define CCP3CTS0 CCP3CAPbits.CCP3CTS0 // bit 0
10645 #define CCP3CTS1 CCP3CAPbits.CCP3CTS1 // bit 1
10646 #define CCP3CTS2 CCP3CAPbits.CCP3CTS2 // bit 2
10647 #define CCP3CTS3 CCP3CAPbits.CCP3CTS3 // bit 3
10649 #define CCP3MODE0 CCP3CONbits.CCP3MODE0 // bit 0
10650 #define CCP3MODE1 CCP3CONbits.CCP3MODE1 // bit 1
10651 #define CCP3MODE2 CCP3CONbits.CCP3MODE2 // bit 2
10652 #define CCP3MODE3 CCP3CONbits.CCP3MODE3 // bit 3
10653 #define CCP3FMT CCP3CONbits.CCP3FMT // bit 4
10654 #define CCP3OUT CCP3CONbits.CCP3OUT // bit 5
10655 #define CCP3EN CCP3CONbits.CCP3EN // bit 7
10657 #define CCP3PPS0 CCP3PPSbits.CCP3PPS0 // bit 0
10658 #define CCP3PPS1 CCP3PPSbits.CCP3PPS1 // bit 1
10659 #define CCP3PPS2 CCP3PPSbits.CCP3PPS2 // bit 2
10660 #define CCP3PPS3 CCP3PPSbits.CCP3PPS3 // bit 3
10661 #define CCP3PPS4 CCP3PPSbits.CCP3PPS4 // bit 4
10663 #define CCP4CTS0 CCP4CAPbits.CCP4CTS0 // bit 0
10664 #define CCP4CTS1 CCP4CAPbits.CCP4CTS1 // bit 1
10665 #define CCP4CTS2 CCP4CAPbits.CCP4CTS2 // bit 2
10666 #define CCP4CTS3 CCP4CAPbits.CCP4CTS3 // bit 3
10668 #define CCP4MODE0 CCP4CONbits.CCP4MODE0 // bit 0
10669 #define CCP4MODE1 CCP4CONbits.CCP4MODE1 // bit 1
10670 #define CCP4MODE2 CCP4CONbits.CCP4MODE2 // bit 2
10671 #define CCP4MODE3 CCP4CONbits.CCP4MODE3 // bit 3
10672 #define CCP4FMT CCP4CONbits.CCP4FMT // bit 4
10673 #define CCP4OUT CCP4CONbits.CCP4OUT // bit 5
10674 #define CCP4EN CCP4CONbits.CCP4EN // bit 7
10676 #define CCP4PPS0 CCP4PPSbits.CCP4PPS0 // bit 0
10677 #define CCP4PPS1 CCP4PPSbits.CCP4PPS1 // bit 1
10678 #define CCP4PPS2 CCP4PPSbits.CCP4PPS2 // bit 2
10679 #define CCP4PPS3 CCP4PPSbits.CCP4PPS3 // bit 3
10680 #define CCP4PPS4 CCP4PPSbits.CCP4PPS4 // bit 4
10682 #define C1TSEL0 CCPTMRSbits.C1TSEL0 // bit 0
10683 #define C1TSEL1 CCPTMRSbits.C1TSEL1 // bit 1
10684 #define C2TSEL0 CCPTMRSbits.C2TSEL0 // bit 2
10685 #define C2TSEL1 CCPTMRSbits.C2TSEL1 // bit 3
10686 #define C3TSEL0 CCPTMRSbits.C3TSEL0 // bit 4
10687 #define C3TSEL1 CCPTMRSbits.C3TSEL1 // bit 5
10688 #define C4TSEL0 CCPTMRSbits.C4TSEL0 // bit 6
10689 #define C4TSEL1 CCPTMRSbits.C4TSEL1 // bit 7
10691 #define LC1MODE0 CLC1CONbits.LC1MODE0 // bit 0, shadows bit in CLC1CONbits
10692 #define MODE0 CLC1CONbits.MODE0 // bit 0, shadows bit in CLC1CONbits
10693 #define LC1MODE1 CLC1CONbits.LC1MODE1 // bit 1, shadows bit in CLC1CONbits
10694 #define MODE1 CLC1CONbits.MODE1 // bit 1, shadows bit in CLC1CONbits
10695 #define LC1MODE2 CLC1CONbits.LC1MODE2 // bit 2, shadows bit in CLC1CONbits
10696 #define MODE2 CLC1CONbits.MODE2 // bit 2, shadows bit in CLC1CONbits
10697 #define LC1INTN CLC1CONbits.LC1INTN // bit 3, shadows bit in CLC1CONbits
10698 #define INTN CLC1CONbits.INTN // bit 3, shadows bit in CLC1CONbits
10699 #define LC1INTP CLC1CONbits.LC1INTP // bit 4, shadows bit in CLC1CONbits
10700 #define INTP CLC1CONbits.INTP // bit 4, shadows bit in CLC1CONbits
10701 #define LC1OUT CLC1CONbits.LC1OUT // bit 5, shadows bit in CLC1CONbits
10702 #define OUT CLC1CONbits.OUT // bit 5, shadows bit in CLC1CONbits
10703 #define LC1EN CLC1CONbits.LC1EN // bit 7, shadows bit in CLC1CONbits
10704 #define EN CLC1CONbits.EN // bit 7, shadows bit in CLC1CONbits
10706 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
10707 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
10708 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
10709 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
10710 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
10711 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
10712 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
10713 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
10714 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
10715 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
10716 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
10717 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
10718 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
10719 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
10720 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
10721 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
10723 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
10724 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
10725 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
10726 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
10727 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
10728 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
10729 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
10730 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
10731 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
10732 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
10733 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
10734 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
10735 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
10736 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
10737 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
10738 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
10740 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
10741 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
10742 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
10743 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
10744 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
10745 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
10746 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
10747 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
10748 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
10749 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
10751 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
10752 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
10753 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
10754 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
10755 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
10756 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
10757 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
10758 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
10759 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
10760 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
10761 #define LC1D1S5 CLC1SEL0bits.LC1D1S5 // bit 5, shadows bit in CLC1SEL0bits
10762 #define D1S5 CLC1SEL0bits.D1S5 // bit 5, shadows bit in CLC1SEL0bits
10764 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
10765 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
10766 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
10767 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
10768 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
10769 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
10770 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
10771 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
10772 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
10773 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
10774 #define LC1D2S5 CLC1SEL1bits.LC1D2S5 // bit 5, shadows bit in CLC1SEL1bits
10775 #define D2S5 CLC1SEL1bits.D2S5 // bit 5, shadows bit in CLC1SEL1bits
10777 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
10778 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
10779 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
10780 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
10781 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
10782 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
10783 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
10784 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
10785 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
10786 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
10787 #define LC1D3S5 CLC1SEL2bits.LC1D3S5 // bit 5, shadows bit in CLC1SEL2bits
10788 #define D3S5 CLC1SEL2bits.D3S5 // bit 5, shadows bit in CLC1SEL2bits
10790 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
10791 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
10792 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
10793 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
10794 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
10795 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
10796 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
10797 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
10798 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
10799 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
10800 #define LC1D4S5 CLC1SEL3bits.LC1D4S5 // bit 5, shadows bit in CLC1SEL3bits
10801 #define D4S5 CLC1SEL3bits.D4S5 // bit 5, shadows bit in CLC1SEL3bits
10803 #define MLC1OUT CLCDATAbits.MLC1OUT // bit 0
10804 #define MLC2OUT CLCDATAbits.MLC2OUT // bit 1
10805 #define MLC3OUT CLCDATAbits.MLC3OUT // bit 2
10806 #define MLC4OUT CLCDATAbits.MLC4OUT // bit 3
10808 #define CLCIN0PPS0 CLCIN0PPSbits.CLCIN0PPS0 // bit 0
10809 #define CLCIN0PPS1 CLCIN0PPSbits.CLCIN0PPS1 // bit 1
10810 #define CLCIN0PPS2 CLCIN0PPSbits.CLCIN0PPS2 // bit 2
10811 #define CLCIN0PPS3 CLCIN0PPSbits.CLCIN0PPS3 // bit 3
10812 #define CLCIN0PPS4 CLCIN0PPSbits.CLCIN0PPS4 // bit 4
10814 #define CLCIN1PPS0 CLCIN1PPSbits.CLCIN1PPS0 // bit 0
10815 #define CLCIN1PPS1 CLCIN1PPSbits.CLCIN1PPS1 // bit 1
10816 #define CLCIN1PPS2 CLCIN1PPSbits.CLCIN1PPS2 // bit 2
10817 #define CLCIN1PPS3 CLCIN1PPSbits.CLCIN1PPS3 // bit 3
10818 #define CLCIN1PPS4 CLCIN1PPSbits.CLCIN1PPS4 // bit 4
10820 #define CLCIN2PPS0 CLCIN2PPSbits.CLCIN2PPS0 // bit 0
10821 #define CLCIN2PPS1 CLCIN2PPSbits.CLCIN2PPS1 // bit 1
10822 #define CLCIN2PPS2 CLCIN2PPSbits.CLCIN2PPS2 // bit 2
10823 #define CLCIN2PPS3 CLCIN2PPSbits.CLCIN2PPS3 // bit 3
10824 #define CLCIN2PPS4 CLCIN2PPSbits.CLCIN2PPS4 // bit 4
10826 #define CLCIN3PPS0 CLCIN3PPSbits.CLCIN3PPS0 // bit 0
10827 #define CLCIN3PPS1 CLCIN3PPSbits.CLCIN3PPS1 // bit 1
10828 #define CLCIN3PPS2 CLCIN3PPSbits.CLCIN3PPS2 // bit 2
10829 #define CLCIN3PPS3 CLCIN3PPSbits.CLCIN3PPS3 // bit 3
10830 #define CLCIN3PPS4 CLCIN3PPSbits.CLCIN3PPS4 // bit 4
10832 #define CLKRDIV0 CLKRCONbits.CLKRDIV0 // bit 0
10833 #define CLKRDIV1 CLKRCONbits.CLKRDIV1 // bit 1
10834 #define CLKRDIV2 CLKRCONbits.CLKRDIV2 // bit 2
10835 #define CLKRDC0 CLKRCONbits.CLKRDC0 // bit 3
10836 #define CLKRDC1 CLKRCONbits.CLKRDC1 // bit 4
10837 #define CLKREN CLKRCONbits.CLKREN // bit 7
10839 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
10840 #define C1HYS CM1CON0bits.C1HYS // bit 1
10841 #define C1SP CM1CON0bits.C1SP // bit 2
10842 #define C1POL CM1CON0bits.C1POL // bit 4
10843 #define C1OUT CM1CON0bits.C1OUT // bit 6
10844 #define C1ON CM1CON0bits.C1ON // bit 7
10846 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
10847 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
10848 #define C1NCH2 CM1CON1bits.C1NCH2 // bit 2
10849 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 3
10850 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 4
10851 #define C1PCH2 CM1CON1bits.C1PCH2 // bit 5
10852 #define C1INTN CM1CON1bits.C1INTN // bit 6
10853 #define C1INTP CM1CON1bits.C1INTP // bit 7
10855 #define C2SYNC CM2CON0bits.C2SYNC // bit 0
10856 #define C2HYS CM2CON0bits.C2HYS // bit 1
10857 #define C2SP CM2CON0bits.C2SP // bit 2
10858 #define C2POL CM2CON0bits.C2POL // bit 4
10859 #define C2OUT CM2CON0bits.C2OUT // bit 6
10860 #define C2ON CM2CON0bits.C2ON // bit 7
10862 #define C2NCH0 CM2CON1bits.C2NCH0 // bit 0
10863 #define C2NCH1 CM2CON1bits.C2NCH1 // bit 1
10864 #define C2NCH2 CM2CON1bits.C2NCH2 // bit 2
10865 #define C2PCH0 CM2CON1bits.C2PCH0 // bit 3
10866 #define C2PCH1 CM2CON1bits.C2PCH1 // bit 4
10867 #define C2PCH2 CM2CON1bits.C2PCH2 // bit 5
10868 #define C2INTN CM2CON1bits.C2INTN // bit 6
10869 #define C2INTP CM2CON1bits.C2INTP // bit 7
10871 #define MC1OUT CMOUTbits.MC1OUT // bit 0
10872 #define MC2OUT CMOUTbits.MC2OUT // bit 1
10874 #define DOZE0 CPUDOZEbits.DOZE0 // bit 0
10875 #define DOZE1 CPUDOZEbits.DOZE1 // bit 1
10876 #define DOZE2 CPUDOZEbits.DOZE2 // bit 2
10877 #define DOE CPUDOZEbits.DOE // bit 4
10878 #define ROI CPUDOZEbits.ROI // bit 5
10879 #define DOZEN CPUDOZEbits.DOZEN // bit 6
10880 #define IDLEN CPUDOZEbits.IDLEN // bit 7
10882 #define LSAC0 CWG1AS0bits.LSAC0 // bit 2, shadows bit in CWG1AS0bits
10883 #define CWG1LSAC0 CWG1AS0bits.CWG1LSAC0 // bit 2, shadows bit in CWG1AS0bits
10884 #define LSAC1 CWG1AS0bits.LSAC1 // bit 3, shadows bit in CWG1AS0bits
10885 #define CWG1LSAC1 CWG1AS0bits.CWG1LSAC1 // bit 3, shadows bit in CWG1AS0bits
10886 #define LSBD0 CWG1AS0bits.LSBD0 // bit 4, shadows bit in CWG1AS0bits
10887 #define CWG1LSBD0 CWG1AS0bits.CWG1LSBD0 // bit 4, shadows bit in CWG1AS0bits
10888 #define LSBD1 CWG1AS0bits.LSBD1 // bit 5, shadows bit in CWG1AS0bits
10889 #define CWG1LSBD1 CWG1AS0bits.CWG1LSBD1 // bit 5, shadows bit in CWG1AS0bits
10890 #define REN CWG1AS0bits.REN // bit 6, shadows bit in CWG1AS0bits
10891 #define CWG1REN CWG1AS0bits.CWG1REN // bit 6, shadows bit in CWG1AS0bits
10892 #define SHUTDOWN CWG1AS0bits.SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
10893 #define CWG1SHUTDOWN CWG1AS0bits.CWG1SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
10895 #define AS0E CWG1AS1bits.AS0E // bit 0
10896 #define AS1E CWG1AS1bits.AS1E // bit 1
10897 #define AS2E CWG1AS1bits.AS2E // bit 2
10898 #define AS3E CWG1AS1bits.AS3E // bit 3
10899 #define AS4E CWG1AS1bits.AS4E // bit 4
10901 #define CS CWG1CLKCONbits.CS // bit 0, shadows bit in CWG1CLKCONbits
10902 #define CWG1CS CWG1CLKCONbits.CWG1CS // bit 0, shadows bit in CWG1CLKCONbits
10904 #define POLA CWG1CON1bits.POLA // bit 0, shadows bit in CWG1CON1bits
10905 #define CWG1POLA CWG1CON1bits.CWG1POLA // bit 0, shadows bit in CWG1CON1bits
10906 #define POLB CWG1CON1bits.POLB // bit 1, shadows bit in CWG1CON1bits
10907 #define CWG1POLB CWG1CON1bits.CWG1POLB // bit 1, shadows bit in CWG1CON1bits
10908 #define POLC CWG1CON1bits.POLC // bit 2, shadows bit in CWG1CON1bits
10909 #define CWG1POLC CWG1CON1bits.CWG1POLC // bit 2, shadows bit in CWG1CON1bits
10910 #define POLD CWG1CON1bits.POLD // bit 3, shadows bit in CWG1CON1bits
10911 #define CWG1POLD CWG1CON1bits.CWG1POLD // bit 3, shadows bit in CWG1CON1bits
10912 #define IN CWG1CON1bits.IN // bit 5, shadows bit in CWG1CON1bits
10913 #define CWG1IN CWG1CON1bits.CWG1IN // bit 5, shadows bit in CWG1CON1bits
10915 #define CWG1DAT0 CWG1DATbits.CWG1DAT0 // bit 0
10916 #define CWG1DAT1 CWG1DATbits.CWG1DAT1 // bit 1
10917 #define CWG1DAT2 CWG1DATbits.CWG1DAT2 // bit 2
10918 #define CWG1DAT3 CWG1DATbits.CWG1DAT3 // bit 3
10920 #define DBF0 CWG1DBFbits.DBF0 // bit 0, shadows bit in CWG1DBFbits
10921 #define CWG1DBF0 CWG1DBFbits.CWG1DBF0 // bit 0, shadows bit in CWG1DBFbits
10922 #define DBF1 CWG1DBFbits.DBF1 // bit 1, shadows bit in CWG1DBFbits
10923 #define CWG1DBF1 CWG1DBFbits.CWG1DBF1 // bit 1, shadows bit in CWG1DBFbits
10924 #define DBF2 CWG1DBFbits.DBF2 // bit 2, shadows bit in CWG1DBFbits
10925 #define CWG1DBF2 CWG1DBFbits.CWG1DBF2 // bit 2, shadows bit in CWG1DBFbits
10926 #define DBF3 CWG1DBFbits.DBF3 // bit 3, shadows bit in CWG1DBFbits
10927 #define CWG1DBF3 CWG1DBFbits.CWG1DBF3 // bit 3, shadows bit in CWG1DBFbits
10928 #define DBF4 CWG1DBFbits.DBF4 // bit 4, shadows bit in CWG1DBFbits
10929 #define CWG1DBF4 CWG1DBFbits.CWG1DBF4 // bit 4, shadows bit in CWG1DBFbits
10930 #define DBF5 CWG1DBFbits.DBF5 // bit 5, shadows bit in CWG1DBFbits
10931 #define CWG1DBF5 CWG1DBFbits.CWG1DBF5 // bit 5, shadows bit in CWG1DBFbits
10933 #define DBR0 CWG1DBRbits.DBR0 // bit 0, shadows bit in CWG1DBRbits
10934 #define CWG1DBR0 CWG1DBRbits.CWG1DBR0 // bit 0, shadows bit in CWG1DBRbits
10935 #define DBR1 CWG1DBRbits.DBR1 // bit 1, shadows bit in CWG1DBRbits
10936 #define CWG1DBR1 CWG1DBRbits.CWG1DBR1 // bit 1, shadows bit in CWG1DBRbits
10937 #define DBR2 CWG1DBRbits.DBR2 // bit 2, shadows bit in CWG1DBRbits
10938 #define CWG1DBR2 CWG1DBRbits.CWG1DBR2 // bit 2, shadows bit in CWG1DBRbits
10939 #define DBR3 CWG1DBRbits.DBR3 // bit 3, shadows bit in CWG1DBRbits
10940 #define CWG1DBR3 CWG1DBRbits.CWG1DBR3 // bit 3, shadows bit in CWG1DBRbits
10941 #define DBR4 CWG1DBRbits.DBR4 // bit 4, shadows bit in CWG1DBRbits
10942 #define CWG1DBR4 CWG1DBRbits.CWG1DBR4 // bit 4, shadows bit in CWG1DBRbits
10943 #define DBR5 CWG1DBRbits.DBR5 // bit 5, shadows bit in CWG1DBRbits
10944 #define CWG1DBR5 CWG1DBRbits.CWG1DBR5 // bit 5, shadows bit in CWG1DBRbits
10946 #define CWG1PPS0 CWG1PPSbits.CWG1PPS0 // bit 0
10947 #define CWG1PPS1 CWG1PPSbits.CWG1PPS1 // bit 1
10948 #define CWG1PPS2 CWG1PPSbits.CWG1PPS2 // bit 2
10949 #define CWG1PPS3 CWG1PPSbits.CWG1PPS3 // bit 3
10950 #define CWG1PPS4 CWG1PPSbits.CWG1PPS4 // bit 4
10952 #define STRA CWG1STRbits.STRA // bit 0, shadows bit in CWG1STRbits
10953 #define CWG1STRA CWG1STRbits.CWG1STRA // bit 0, shadows bit in CWG1STRbits
10954 #define STRB CWG1STRbits.STRB // bit 1, shadows bit in CWG1STRbits
10955 #define CWG1STRB CWG1STRbits.CWG1STRB // bit 1, shadows bit in CWG1STRbits
10956 #define STRC CWG1STRbits.STRC // bit 2, shadows bit in CWG1STRbits
10957 #define CWG1STRC CWG1STRbits.CWG1STRC // bit 2, shadows bit in CWG1STRbits
10958 #define STRD CWG1STRbits.STRD // bit 3, shadows bit in CWG1STRbits
10959 #define CWG1STRD CWG1STRbits.CWG1STRD // bit 3, shadows bit in CWG1STRbits
10960 #define OVRA CWG1STRbits.OVRA // bit 4, shadows bit in CWG1STRbits
10961 #define CWG1OVRA CWG1STRbits.CWG1OVRA // bit 4, shadows bit in CWG1STRbits
10962 #define OVRB CWG1STRbits.OVRB // bit 5, shadows bit in CWG1STRbits
10963 #define CWG1OVRB CWG1STRbits.CWG1OVRB // bit 5, shadows bit in CWG1STRbits
10964 #define OVRC CWG1STRbits.OVRC // bit 6, shadows bit in CWG1STRbits
10965 #define CWG1OVRC CWG1STRbits.CWG1OVRC // bit 6, shadows bit in CWG1STRbits
10966 #define OVRD CWG1STRbits.OVRD // bit 7, shadows bit in CWG1STRbits
10967 #define CWG1OVRD CWG1STRbits.CWG1OVRD // bit 7, shadows bit in CWG1STRbits
10969 #define CWG2DAT0 CWG2DATbits.CWG2DAT0 // bit 0
10970 #define CWG2DAT1 CWG2DATbits.CWG2DAT1 // bit 1
10971 #define CWG2DAT2 CWG2DATbits.CWG2DAT2 // bit 2
10972 #define CWG2DAT3 CWG2DATbits.CWG2DAT3 // bit 3
10974 #define CWG2PPS0 CWG2PPSbits.CWG2PPS0 // bit 0
10975 #define CWG2PPS1 CWG2PPSbits.CWG2PPS1 // bit 1
10976 #define CWG2PPS2 CWG2PPSbits.CWG2PPS2 // bit 2
10977 #define CWG2PPS3 CWG2PPSbits.CWG2PPS3 // bit 3
10978 #define CWG2PPS4 CWG2PPSbits.CWG2PPS4 // bit 4
10980 #define DAC1NSS DACCON0bits.DAC1NSS // bit 0
10981 #define DAC1PSS0 DACCON0bits.DAC1PSS0 // bit 2
10982 #define DAC1PSS1 DACCON0bits.DAC1PSS1 // bit 3
10983 #define DAC1OE DACCON0bits.DAC1OE // bit 5
10984 #define DAC1EN DACCON0bits.DAC1EN // bit 7
10986 #define DAC1R0 DACCON1bits.DAC1R0 // bit 0
10987 #define DAC1R1 DACCON1bits.DAC1R1 // bit 1
10988 #define DAC1R2 DACCON1bits.DAC1R2 // bit 2
10989 #define DAC1R3 DACCON1bits.DAC1R3 // bit 3
10990 #define DAC1R4 DACCON1bits.DAC1R4 // bit 4
10992 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
10993 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
10994 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
10995 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
10996 #define TSRNG FVRCONbits.TSRNG // bit 4
10997 #define TSEN FVRCONbits.TSEN // bit 5
10998 #define FVRRDY FVRCONbits.FVRRDY // bit 6
10999 #define FVREN FVRCONbits.FVREN // bit 7
11001 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
11002 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
11003 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
11004 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
11005 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
11006 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
11008 #define INLVLB4 INLVLBbits.INLVLB4 // bit 4
11009 #define INLVLB5 INLVLBbits.INLVLB5 // bit 5
11010 #define INLVLB6 INLVLBbits.INLVLB6 // bit 6
11011 #define INLVLB7 INLVLBbits.INLVLB7 // bit 7
11013 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
11014 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
11015 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
11016 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
11017 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
11018 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
11019 #define INLVLC6 INLVLCbits.INLVLC6 // bit 6
11020 #define INLVLC7 INLVLCbits.INLVLC7 // bit 7
11022 #define INTEDG INTCONbits.INTEDG // bit 0
11023 #define PEIE INTCONbits.PEIE // bit 6
11024 #define GIE INTCONbits.GIE // bit 7
11026 #define INTPPS0 INTPPSbits.INTPPS0 // bit 0
11027 #define INTPPS1 INTPPSbits.INTPPS1 // bit 1
11028 #define INTPPS2 INTPPSbits.INTPPS2 // bit 2
11029 #define INTPPS3 INTPPSbits.INTPPS3 // bit 3
11030 #define INTPPS4 INTPPSbits.INTPPS4 // bit 4
11032 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
11033 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
11034 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
11035 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
11036 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
11037 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
11039 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
11040 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
11041 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
11042 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
11043 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
11044 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
11046 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
11047 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
11048 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
11049 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
11050 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
11051 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
11053 #define IOCBF4 IOCBFbits.IOCBF4 // bit 4
11054 #define IOCBF5 IOCBFbits.IOCBF5 // bit 5
11055 #define IOCBF6 IOCBFbits.IOCBF6 // bit 6
11056 #define IOCBF7 IOCBFbits.IOCBF7 // bit 7
11058 #define IOCBN4 IOCBNbits.IOCBN4 // bit 4
11059 #define IOCBN5 IOCBNbits.IOCBN5 // bit 5
11060 #define IOCBN6 IOCBNbits.IOCBN6 // bit 6
11061 #define IOCBN7 IOCBNbits.IOCBN7 // bit 7
11063 #define IOCBP4 IOCBPbits.IOCBP4 // bit 4
11064 #define IOCBP5 IOCBPbits.IOCBP5 // bit 5
11065 #define IOCBP6 IOCBPbits.IOCBP6 // bit 6
11066 #define IOCBP7 IOCBPbits.IOCBP7 // bit 7
11068 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
11069 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
11070 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
11071 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
11072 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
11073 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
11074 #define IOCCF6 IOCCFbits.IOCCF6 // bit 6
11075 #define IOCCF7 IOCCFbits.IOCCF7 // bit 7
11077 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
11078 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
11079 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
11080 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
11081 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
11082 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
11083 #define IOCCN6 IOCCNbits.IOCCN6 // bit 6
11084 #define IOCCN7 IOCCNbits.IOCCN7 // bit 7
11086 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
11087 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
11088 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
11089 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
11090 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
11091 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
11092 #define IOCCP6 IOCCPbits.IOCCP6 // bit 6
11093 #define IOCCP7 IOCCPbits.IOCCP7 // bit 7
11095 #define LATA0 LATAbits.LATA0 // bit 0
11096 #define LATA1 LATAbits.LATA1 // bit 1
11097 #define LATA2 LATAbits.LATA2 // bit 2
11098 #define LATA4 LATAbits.LATA4 // bit 4
11099 #define LATA5 LATAbits.LATA5 // bit 5
11101 #define LATB4 LATBbits.LATB4 // bit 4
11102 #define LATB5 LATBbits.LATB5 // bit 5
11103 #define LATB6 LATBbits.LATB6 // bit 6
11104 #define LATB7 LATBbits.LATB7 // bit 7
11106 #define LATC0 LATCbits.LATC0 // bit 0
11107 #define LATC1 LATCbits.LATC1 // bit 1
11108 #define LATC2 LATCbits.LATC2 // bit 2
11109 #define LATC3 LATCbits.LATC3 // bit 3
11110 #define LATC4 LATCbits.LATC4 // bit 4
11111 #define LATC5 LATCbits.LATC5 // bit 5
11112 #define LATC6 LATCbits.LATC6 // bit 6
11113 #define LATC7 LATCbits.LATC7 // bit 7
11115 #define MDCH0 MDCARHbits.MDCH0 // bit 0
11116 #define MDCH1 MDCARHbits.MDCH1 // bit 1
11117 #define MDCH2 MDCARHbits.MDCH2 // bit 2
11118 #define MDCH3 MDCARHbits.MDCH3 // bit 3
11119 #define MDCHSYNC MDCARHbits.MDCHSYNC // bit 5
11120 #define MDCHPOL MDCARHbits.MDCHPOL // bit 6
11122 #define MDCL0 MDCARLbits.MDCL0 // bit 0
11123 #define MDCL1 MDCARLbits.MDCL1 // bit 1
11124 #define MDCL2 MDCARLbits.MDCL2 // bit 2
11125 #define MDCL3 MDCARLbits.MDCL3 // bit 3
11126 #define MDCLSYNC MDCARLbits.MDCLSYNC // bit 5
11127 #define MDCLPOL MDCARLbits.MDCLPOL // bit 6
11129 #define MDCIN1PPS0 MDCIN1PPSbits.MDCIN1PPS0 // bit 0
11130 #define MDCIN1PPS1 MDCIN1PPSbits.MDCIN1PPS1 // bit 1
11131 #define MDCIN1PPS2 MDCIN1PPSbits.MDCIN1PPS2 // bit 2
11132 #define MDCIN1PPS3 MDCIN1PPSbits.MDCIN1PPS3 // bit 3
11133 #define MDCIN1PPS4 MDCIN1PPSbits.MDCIN1PPS4 // bit 4
11135 #define MDCIN2PPS0 MDCIN2PPSbits.MDCIN2PPS0 // bit 0
11136 #define MDCIN2PPS1 MDCIN2PPSbits.MDCIN2PPS1 // bit 1
11137 #define MDCIN2PPS2 MDCIN2PPSbits.MDCIN2PPS2 // bit 2
11138 #define MDCIN2PPS3 MDCIN2PPSbits.MDCIN2PPS3 // bit 3
11139 #define MDCIN2PPS4 MDCIN2PPSbits.MDCIN2PPS4 // bit 4
11141 #define MDBIT MDCONbits.MDBIT // bit 0
11142 #define MDOUT MDCONbits.MDOUT // bit 3
11143 #define MDOPOL MDCONbits.MDOPOL // bit 4
11144 #define MDEN MDCONbits.MDEN // bit 7
11146 #define MDMINPPS0 MDMINPPSbits.MDMINPPS0 // bit 0
11147 #define MDMINPPS1 MDMINPPSbits.MDMINPPS1 // bit 1
11148 #define MDMINPPS2 MDMINPPSbits.MDMINPPS2 // bit 2
11149 #define MDMINPPS3 MDMINPPSbits.MDMINPPS3 // bit 3
11150 #define MDMINPPS4 MDMINPPSbits.MDMINPPS4 // bit 4
11152 #define MDMS0 MDSRCbits.MDMS0 // bit 0
11153 #define MDMS1 MDSRCbits.MDMS1 // bit 1
11154 #define MDMS2 MDSRCbits.MDMS2 // bit 2
11155 #define MDMS3 MDSRCbits.MDMS3 // bit 3
11157 #define N1PFM NCO1CONbits.N1PFM // bit 0
11158 #define N1POL NCO1CONbits.N1POL // bit 4
11159 #define N1OUT NCO1CONbits.N1OUT // bit 5
11160 #define N1EN NCO1CONbits.N1EN // bit 7
11162 #define NVMADR8 NVMADRHbits.NVMADR8 // bit 0
11163 #define NVMADR9 NVMADRHbits.NVMADR9 // bit 1
11164 #define NVMADR10 NVMADRHbits.NVMADR10 // bit 2
11165 #define NVMADR11 NVMADRHbits.NVMADR11 // bit 3
11166 #define NVMADR12 NVMADRHbits.NVMADR12 // bit 4
11167 #define NVMADR13 NVMADRHbits.NVMADR13 // bit 5
11168 #define NVMADR14 NVMADRHbits.NVMADR14 // bit 6
11170 #define NVMADR0 NVMADRLbits.NVMADR0 // bit 0
11171 #define NVMADR1 NVMADRLbits.NVMADR1 // bit 1
11172 #define NVMADR2 NVMADRLbits.NVMADR2 // bit 2
11173 #define NVMADR3 NVMADRLbits.NVMADR3 // bit 3
11174 #define NVMADR4 NVMADRLbits.NVMADR4 // bit 4
11175 #define NVMADR5 NVMADRLbits.NVMADR5 // bit 5
11176 #define NVMADR6 NVMADRLbits.NVMADR6 // bit 6
11177 #define NVMADR7 NVMADRLbits.NVMADR7 // bit 7
11179 #define RD NVMCON1bits.RD // bit 0
11180 #define WR NVMCON1bits.WR // bit 1
11181 #define WREN NVMCON1bits.WREN // bit 2
11182 #define WRERR NVMCON1bits.WRERR // bit 3
11183 #define FREE NVMCON1bits.FREE // bit 4
11184 #define LWLO NVMCON1bits.LWLO // bit 5
11185 #define NVMREGS NVMCON1bits.NVMREGS // bit 6
11187 #define NVMDAT8 NVMDATHbits.NVMDAT8 // bit 0
11188 #define NVMDAT9 NVMDATHbits.NVMDAT9 // bit 1
11189 #define NVMDAT10 NVMDATHbits.NVMDAT10 // bit 2
11190 #define NVMDAT11 NVMDATHbits.NVMDAT11 // bit 3
11191 #define NVMDAT12 NVMDATHbits.NVMDAT12 // bit 4
11192 #define NVMDAT13 NVMDATHbits.NVMDAT13 // bit 5
11194 #define NVMDAT0 NVMDATLbits.NVMDAT0 // bit 0
11195 #define NVMDAT1 NVMDATLbits.NVMDAT1 // bit 1
11196 #define NVMDAT2 NVMDATLbits.NVMDAT2 // bit 2
11197 #define NVMDAT3 NVMDATLbits.NVMDAT3 // bit 3
11198 #define NVMDAT4 NVMDATLbits.NVMDAT4 // bit 4
11199 #define NVMDAT5 NVMDATLbits.NVMDAT5 // bit 5
11200 #define NVMDAT6 NVMDATLbits.NVMDAT6 // bit 6
11201 #define NVMDAT7 NVMDATLbits.NVMDAT7 // bit 7
11203 #define ODCA0 ODCONAbits.ODCA0 // bit 0
11204 #define ODCA1 ODCONAbits.ODCA1 // bit 1
11205 #define ODCA2 ODCONAbits.ODCA2 // bit 2
11206 #define ODCA4 ODCONAbits.ODCA4 // bit 4
11207 #define ODCA5 ODCONAbits.ODCA5 // bit 5
11209 #define ODCB4 ODCONBbits.ODCB4 // bit 4
11210 #define ODCB5 ODCONBbits.ODCB5 // bit 5
11211 #define ODCB6 ODCONBbits.ODCB6 // bit 6
11212 #define ODCB7 ODCONBbits.ODCB7 // bit 7
11214 #define ODCC0 ODCONCbits.ODCC0 // bit 0
11215 #define ODCC1 ODCONCbits.ODCC1 // bit 1
11216 #define ODCC2 ODCONCbits.ODCC2 // bit 2
11217 #define ODCC3 ODCONCbits.ODCC3 // bit 3
11218 #define ODCC4 ODCONCbits.ODCC4 // bit 4
11219 #define ODCC5 ODCONCbits.ODCC5 // bit 5
11220 #define ODCC6 ODCONCbits.ODCC6 // bit 6
11221 #define ODCC7 ODCONCbits.ODCC7 // bit 7
11223 #define NDIV0 OSCCON1bits.NDIV0 // bit 0
11224 #define NDIV1 OSCCON1bits.NDIV1 // bit 1
11225 #define NDIV2 OSCCON1bits.NDIV2 // bit 2
11226 #define NDIV3 OSCCON1bits.NDIV3 // bit 3
11227 #define NOSC0 OSCCON1bits.NOSC0 // bit 4
11228 #define NOSC1 OSCCON1bits.NOSC1 // bit 5
11229 #define NOSC2 OSCCON1bits.NOSC2 // bit 6
11231 #define CDIV0 OSCCON2bits.CDIV0 // bit 0
11232 #define CDIV1 OSCCON2bits.CDIV1 // bit 1
11233 #define CDIV2 OSCCON2bits.CDIV2 // bit 2
11234 #define CDIV3 OSCCON2bits.CDIV3 // bit 3
11235 #define COSC0 OSCCON2bits.COSC0 // bit 4
11236 #define COSC1 OSCCON2bits.COSC1 // bit 5
11237 #define COSC2 OSCCON2bits.COSC2 // bit 6
11239 #define NOSCR OSCCON3bits.NOSCR // bit 3
11240 #define ORDY OSCCON3bits.ORDY // bit 4
11241 #define SOSCBE OSCCON3bits.SOSCBE // bit 5
11242 #define SOSCPWR OSCCON3bits.SOSCPWR // bit 6
11243 #define CSWHOLD OSCCON3bits.CSWHOLD // bit 7
11245 #define ADOEN OSCENbits.ADOEN // bit 2
11246 #define SOSCEN OSCENbits.SOSCEN // bit 3
11247 #define LFOEN OSCENbits.LFOEN // bit 4
11248 #define HFOEN OSCENbits.HFOEN // bit 6
11249 #define EXTOEN OSCENbits.EXTOEN // bit 7
11251 #define HFFRQ0 OSCFRQbits.HFFRQ0 // bit 0
11252 #define HFFRQ1 OSCFRQbits.HFFRQ1 // bit 1
11253 #define HFFRQ2 OSCFRQbits.HFFRQ2 // bit 2
11254 #define HFFRQ3 OSCFRQbits.HFFRQ3 // bit 3
11256 #define PLLR OSCSTAT1bits.PLLR // bit 0
11257 #define ADOR OSCSTAT1bits.ADOR // bit 2
11258 #define SOR OSCSTAT1bits.SOR // bit 3
11259 #define LFOR OSCSTAT1bits.LFOR // bit 4
11260 #define HFOR OSCSTAT1bits.HFOR // bit 6
11261 #define EXTOR OSCSTAT1bits.EXTOR // bit 7
11263 #define HFTUN0 OSCTUNEbits.HFTUN0 // bit 0
11264 #define HFTUN1 OSCTUNEbits.HFTUN1 // bit 1
11265 #define HFTUN2 OSCTUNEbits.HFTUN2 // bit 2
11266 #define HFTUN3 OSCTUNEbits.HFTUN3 // bit 3
11267 #define HFTUN4 OSCTUNEbits.HFTUN4 // bit 4
11268 #define HFTUN5 OSCTUNEbits.HFTUN5 // bit 5
11270 #define NOT_BOR PCON0bits.NOT_BOR // bit 0
11271 #define NOT_POR PCON0bits.NOT_POR // bit 1
11272 #define NOT_RI PCON0bits.NOT_RI // bit 2
11273 #define NOT_RMCLR PCON0bits.NOT_RMCLR // bit 3
11274 #define NOT_RWDT PCON0bits.NOT_RWDT // bit 4
11275 #define STKUNF PCON0bits.STKUNF // bit 6
11276 #define STKOVF PCON0bits.STKOVF // bit 7
11278 #define INTE PIE0bits.INTE // bit 0
11279 #define IOCIE PIE0bits.IOCIE // bit 4
11280 #define TMR0IE PIE0bits.TMR0IE // bit 5
11282 #define TMR1IE PIE1bits.TMR1IE // bit 0
11283 #define TMR2IE PIE1bits.TMR2IE // bit 1
11284 #define BCL1IE PIE1bits.BCL1IE // bit 2
11285 #define SSP1IE PIE1bits.SSP1IE // bit 3
11286 #define TXIE PIE1bits.TXIE // bit 4
11287 #define RCIE PIE1bits.RCIE // bit 5
11288 #define ADIE PIE1bits.ADIE // bit 6
11289 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
11291 #define NCO1IE PIE2bits.NCO1IE // bit 0
11292 #define TMR4IE PIE2bits.TMR4IE // bit 1
11293 #define NVMIE PIE2bits.NVMIE // bit 4
11294 #define C1IE PIE2bits.C1IE // bit 5
11295 #define C2IE PIE2bits.C2IE // bit 6
11296 #define TMR6IE PIE2bits.TMR6IE // bit 7
11298 #define CLC1IE PIE3bits.CLC1IE // bit 0
11299 #define CLC2IE PIE3bits.CLC2IE // bit 1
11300 #define CLC3IE PIE3bits.CLC3IE // bit 2
11301 #define CLC4IE PIE3bits.CLC4IE // bit 3
11302 #define TMR3IE PIE3bits.TMR3IE // bit 4
11303 #define TMR3GIE PIE3bits.TMR3GIE // bit 5
11304 #define CSWIE PIE3bits.CSWIE // bit 6
11305 #define OSFIE PIE3bits.OSFIE // bit 7
11307 #define CCP1IE PIE4bits.CCP1IE // bit 0
11308 #define CCP2IE PIE4bits.CCP2IE // bit 1
11309 #define CCP3IE PIE4bits.CCP3IE // bit 2
11310 #define CCP4IE PIE4bits.CCP4IE // bit 3
11311 #define TMR5IE PIE4bits.TMR5IE // bit 4
11312 #define TMR5GIE PIE4bits.TMR5GIE // bit 5
11313 #define CWG1IE PIE4bits.CWG1IE // bit 6
11314 #define CWG2IE PIE4bits.CWG2IE // bit 7
11316 #define INTF PIR0bits.INTF // bit 0
11317 #define IOCIF PIR0bits.IOCIF // bit 4
11318 #define TMR0IF PIR0bits.TMR0IF // bit 5
11320 #define TMR1IF PIR1bits.TMR1IF // bit 0
11321 #define TMR2IF PIR1bits.TMR2IF // bit 1
11322 #define BCL1IF PIR1bits.BCL1IF // bit 2
11323 #define SSP1IF PIR1bits.SSP1IF // bit 3
11324 #define TXIF PIR1bits.TXIF // bit 4
11325 #define RCIF PIR1bits.RCIF // bit 5
11326 #define ADIF PIR1bits.ADIF // bit 6
11327 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
11329 #define NCO1IF PIR2bits.NCO1IF // bit 0
11330 #define TMR4IF PIR2bits.TMR4IF // bit 1
11331 #define NVMIF PIR2bits.NVMIF // bit 4
11332 #define C1IF PIR2bits.C1IF // bit 5
11333 #define C2IF PIR2bits.C2IF // bit 6
11334 #define TMR6IF PIR2bits.TMR6IF // bit 7
11336 #define CLC1IF PIR3bits.CLC1IF // bit 0
11337 #define CLC2IF PIR3bits.CLC2IF // bit 1
11338 #define CLC3IF PIR3bits.CLC3IF // bit 2
11339 #define CLC4IF PIR3bits.CLC4IF // bit 3
11340 #define TMR3IF PIR3bits.TMR3IF // bit 4
11341 #define TMR3GIF PIR3bits.TMR3GIF // bit 5
11342 #define CSWIF PIR3bits.CSWIF // bit 6
11343 #define OSFIF PIR3bits.OSFIF // bit 7
11345 #define CCP1IF PIR4bits.CCP1IF // bit 0
11346 #define CCP2IF PIR4bits.CCP2IF // bit 1
11347 #define CCP3IF PIR4bits.CCP3IF // bit 2
11348 #define CCP4IF PIR4bits.CCP4IF // bit 3
11349 #define TMR5IF PIR4bits.TMR5IF // bit 4
11350 #define TMR5GIF PIR4bits.TMR5GIF // bit 5
11351 #define CWG1IF PIR4bits.CWG1IF // bit 6
11352 #define CWG2IF PIR4bits.CWG2IF // bit 7
11354 #define IOCMD PMD0bits.IOCMD // bit 0
11355 #define CLKRMD PMD0bits.CLKRMD // bit 1
11356 #define NVMMD PMD0bits.NVMMD // bit 2
11357 #define FVRMD PMD0bits.FVRMD // bit 6
11358 #define SYSCMD PMD0bits.SYSCMD // bit 7
11360 #define TMR0MD PMD1bits.TMR0MD // bit 0
11361 #define TMR1MD PMD1bits.TMR1MD // bit 1
11362 #define TMR2MD PMD1bits.TMR2MD // bit 2
11363 #define TMR3MD PMD1bits.TMR3MD // bit 3
11364 #define TMR4MD PMD1bits.TMR4MD // bit 4
11365 #define TMR5MD PMD1bits.TMR5MD // bit 5
11366 #define TMR6MD PMD1bits.TMR6MD // bit 6
11367 #define NCOMD PMD1bits.NCOMD // bit 7
11369 #define CMP1MD PMD2bits.CMP1MD // bit 1
11370 #define CMP2MD PMD2bits.CMP2MD // bit 2
11371 #define ADCMD PMD2bits.ADCMD // bit 5
11372 #define DACMD PMD2bits.DACMD // bit 6
11374 #define CCP1MD PMD3bits.CCP1MD // bit 0
11375 #define CCP2MD PMD3bits.CCP2MD // bit 1
11376 #define CCP3MD PMD3bits.CCP3MD // bit 2
11377 #define CCP4MD PMD3bits.CCP4MD // bit 3
11378 #define PWM5MD PMD3bits.PWM5MD // bit 4
11379 #define PWM6MD PMD3bits.PWM6MD // bit 5
11380 #define CWG1MD PMD3bits.CWG1MD // bit 6
11381 #define CWG2MD PMD3bits.CWG2MD // bit 7
11383 #define MSSP1MD PMD4bits.MSSP1MD // bit 1
11384 #define UART1MD PMD4bits.UART1MD // bit 5
11386 #define DSMMD PMD5bits.DSMMD // bit 0
11387 #define CLC1MD PMD5bits.CLC1MD // bit 1
11388 #define CLC2MD PMD5bits.CLC2MD // bit 2
11389 #define CLC3MD PMD5bits.CLC3MD // bit 3
11390 #define CLC4MD PMD5bits.CLC4MD // bit 4
11392 #define RA0 PORTAbits.RA0 // bit 0
11393 #define RA1 PORTAbits.RA1 // bit 1
11394 #define RA2 PORTAbits.RA2 // bit 2
11395 #define RA3 PORTAbits.RA3 // bit 3
11396 #define RA4 PORTAbits.RA4 // bit 4
11397 #define RA5 PORTAbits.RA5 // bit 5
11399 #define RB4 PORTBbits.RB4 // bit 4
11400 #define RB5 PORTBbits.RB5 // bit 5
11401 #define RB6 PORTBbits.RB6 // bit 6
11402 #define RB7 PORTBbits.RB7 // bit 7
11404 #define RC0 PORTCbits.RC0 // bit 0
11405 #define RC1 PORTCbits.RC1 // bit 1
11406 #define RC2 PORTCbits.RC2 // bit 2
11407 #define RC3 PORTCbits.RC3 // bit 3
11408 #define RC4 PORTCbits.RC4 // bit 4
11409 #define RC5 PORTCbits.RC5 // bit 5
11410 #define RC6 PORTCbits.RC6 // bit 6
11411 #define RC7 PORTCbits.RC7 // bit 7
11413 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
11415 #define PWM5POL PWM5CONbits.PWM5POL // bit 4
11416 #define PWM5OUT PWM5CONbits.PWM5OUT // bit 5
11417 #define PWM5EN PWM5CONbits.PWM5EN // bit 7
11419 #define PWM5DCH0 PWM5DCHbits.PWM5DCH0 // bit 0
11420 #define PWM5DCH1 PWM5DCHbits.PWM5DCH1 // bit 1
11421 #define PWM5DCH2 PWM5DCHbits.PWM5DCH2 // bit 2
11422 #define PWM5DCH3 PWM5DCHbits.PWM5DCH3 // bit 3
11423 #define PWM5DCH4 PWM5DCHbits.PWM5DCH4 // bit 4
11424 #define PWM5DCH5 PWM5DCHbits.PWM5DCH5 // bit 5
11425 #define PWM5DCH6 PWM5DCHbits.PWM5DCH6 // bit 6
11426 #define PWM5DCH7 PWM5DCHbits.PWM5DCH7 // bit 7
11428 #define PWM5DCL0 PWM5DCLbits.PWM5DCL0 // bit 6
11429 #define PWM5DCL1 PWM5DCLbits.PWM5DCL1 // bit 7
11431 #define PWM6POL PWM6CONbits.PWM6POL // bit 4
11432 #define PWM6OUT PWM6CONbits.PWM6OUT // bit 5
11433 #define PWM6EN PWM6CONbits.PWM6EN // bit 7
11435 #define PWM6DCH0 PWM6DCHbits.PWM6DCH0 // bit 0
11436 #define PWM6DCH1 PWM6DCHbits.PWM6DCH1 // bit 1
11437 #define PWM6DCH2 PWM6DCHbits.PWM6DCH2 // bit 2
11438 #define PWM6DCH3 PWM6DCHbits.PWM6DCH3 // bit 3
11439 #define PWM6DCH4 PWM6DCHbits.PWM6DCH4 // bit 4
11440 #define PWM6DCH5 PWM6DCHbits.PWM6DCH5 // bit 5
11441 #define PWM6DCH6 PWM6DCHbits.PWM6DCH6 // bit 6
11442 #define PWM6DCH7 PWM6DCHbits.PWM6DCH7 // bit 7
11444 #define PWM6DCL0 PWM6DCLbits.PWM6DCL0 // bit 6
11445 #define PWM6DCL1 PWM6DCLbits.PWM6DCL1 // bit 7
11447 #define P5TSEL0 PWMTMRSbits.P5TSEL0 // bit 0
11448 #define P5TSEL1 PWMTMRSbits.P5TSEL1 // bit 1
11449 #define P6TSEL0 PWMTMRSbits.P6TSEL0 // bit 2
11450 #define P6TSEL1 PWMTMRSbits.P6TSEL1 // bit 3
11452 #define RA0PPS0 RA0PPSbits.RA0PPS0 // bit 0
11453 #define RA0PPS1 RA0PPSbits.RA0PPS1 // bit 1
11454 #define RA0PPS2 RA0PPSbits.RA0PPS2 // bit 2
11455 #define RA0PPS3 RA0PPSbits.RA0PPS3 // bit 3
11456 #define RA0PPS4 RA0PPSbits.RA0PPS4 // bit 4
11458 #define RA1PPS0 RA1PPSbits.RA1PPS0 // bit 0
11459 #define RA1PPS1 RA1PPSbits.RA1PPS1 // bit 1
11460 #define RA1PPS2 RA1PPSbits.RA1PPS2 // bit 2
11461 #define RA1PPS3 RA1PPSbits.RA1PPS3 // bit 3
11462 #define RA1PPS4 RA1PPSbits.RA1PPS4 // bit 4
11464 #define RA2PPS0 RA2PPSbits.RA2PPS0 // bit 0
11465 #define RA2PPS1 RA2PPSbits.RA2PPS1 // bit 1
11466 #define RA2PPS2 RA2PPSbits.RA2PPS2 // bit 2
11467 #define RA2PPS3 RA2PPSbits.RA2PPS3 // bit 3
11468 #define RA2PPS4 RA2PPSbits.RA2PPS4 // bit 4
11470 #define RA4PPS0 RA4PPSbits.RA4PPS0 // bit 0
11471 #define RA4PPS1 RA4PPSbits.RA4PPS1 // bit 1
11472 #define RA4PPS2 RA4PPSbits.RA4PPS2 // bit 2
11473 #define RA4PPS3 RA4PPSbits.RA4PPS3 // bit 3
11474 #define RA4PPS4 RA4PPSbits.RA4PPS4 // bit 4
11476 #define RA5PPS0 RA5PPSbits.RA5PPS0 // bit 0
11477 #define RA5PPS1 RA5PPSbits.RA5PPS1 // bit 1
11478 #define RA5PPS2 RA5PPSbits.RA5PPS2 // bit 2
11479 #define RA5PPS3 RA5PPSbits.RA5PPS3 // bit 3
11480 #define RA5PPS4 RA5PPSbits.RA5PPS4 // bit 4
11482 #define RB4PPS0 RB4PPSbits.RB4PPS0 // bit 0
11483 #define RB4PPS1 RB4PPSbits.RB4PPS1 // bit 1
11484 #define RB4PPS2 RB4PPSbits.RB4PPS2 // bit 2
11485 #define RB4PPS3 RB4PPSbits.RB4PPS3 // bit 3
11486 #define RB4PPS4 RB4PPSbits.RB4PPS4 // bit 4
11488 #define RB5PPS0 RB5PPSbits.RB5PPS0 // bit 0
11489 #define RB5PPS1 RB5PPSbits.RB5PPS1 // bit 1
11490 #define RB5PPS2 RB5PPSbits.RB5PPS2 // bit 2
11491 #define RB5PPS3 RB5PPSbits.RB5PPS3 // bit 3
11492 #define RB5PPS4 RB5PPSbits.RB5PPS4 // bit 4
11494 #define RB6PPS0 RB6PPSbits.RB6PPS0 // bit 0
11495 #define RB6PPS1 RB6PPSbits.RB6PPS1 // bit 1
11496 #define RB6PPS2 RB6PPSbits.RB6PPS2 // bit 2
11497 #define RB6PPS3 RB6PPSbits.RB6PPS3 // bit 3
11498 #define RB6PPS4 RB6PPSbits.RB6PPS4 // bit 4
11500 #define RB7PPS0 RB7PPSbits.RB7PPS0 // bit 0
11501 #define RB7PPS1 RB7PPSbits.RB7PPS1 // bit 1
11502 #define RB7PPS2 RB7PPSbits.RB7PPS2 // bit 2
11503 #define RB7PPS3 RB7PPSbits.RB7PPS3 // bit 3
11504 #define RB7PPS4 RB7PPSbits.RB7PPS4 // bit 4
11506 #define RC0PPS0 RC0PPSbits.RC0PPS0 // bit 0
11507 #define RC0PPS1 RC0PPSbits.RC0PPS1 // bit 1
11508 #define RC0PPS2 RC0PPSbits.RC0PPS2 // bit 2
11509 #define RC0PPS3 RC0PPSbits.RC0PPS3 // bit 3
11510 #define RC0PPS4 RC0PPSbits.RC0PPS4 // bit 4
11512 #define RC1PPS0 RC1PPSbits.RC1PPS0 // bit 0
11513 #define RC1PPS1 RC1PPSbits.RC1PPS1 // bit 1
11514 #define RC1PPS2 RC1PPSbits.RC1PPS2 // bit 2
11515 #define RC1PPS3 RC1PPSbits.RC1PPS3 // bit 3
11516 #define RC1PPS4 RC1PPSbits.RC1PPS4 // bit 4
11518 #define RX9D RC1STAbits.RX9D // bit 0
11519 #define OERR RC1STAbits.OERR // bit 1
11520 #define FERR RC1STAbits.FERR // bit 2
11521 #define ADDEN RC1STAbits.ADDEN // bit 3
11522 #define CREN RC1STAbits.CREN // bit 4
11523 #define SREN RC1STAbits.SREN // bit 5
11524 #define RX9 RC1STAbits.RX9 // bit 6
11525 #define SPEN RC1STAbits.SPEN // bit 7
11527 #define RC2PPS0 RC2PPSbits.RC2PPS0 // bit 0
11528 #define RC2PPS1 RC2PPSbits.RC2PPS1 // bit 1
11529 #define RC2PPS2 RC2PPSbits.RC2PPS2 // bit 2
11530 #define RC2PPS3 RC2PPSbits.RC2PPS3 // bit 3
11531 #define RC2PPS4 RC2PPSbits.RC2PPS4 // bit 4
11533 #define RC3PPS0 RC3PPSbits.RC3PPS0 // bit 0
11534 #define RC3PPS1 RC3PPSbits.RC3PPS1 // bit 1
11535 #define RC3PPS2 RC3PPSbits.RC3PPS2 // bit 2
11536 #define RC3PPS3 RC3PPSbits.RC3PPS3 // bit 3
11537 #define RC3PPS4 RC3PPSbits.RC3PPS4 // bit 4
11539 #define RC4PPS0 RC4PPSbits.RC4PPS0 // bit 0
11540 #define RC4PPS1 RC4PPSbits.RC4PPS1 // bit 1
11541 #define RC4PPS2 RC4PPSbits.RC4PPS2 // bit 2
11542 #define RC4PPS3 RC4PPSbits.RC4PPS3 // bit 3
11543 #define RC4PPS4 RC4PPSbits.RC4PPS4 // bit 4
11545 #define RC5PPS0 RC5PPSbits.RC5PPS0 // bit 0
11546 #define RC5PPS1 RC5PPSbits.RC5PPS1 // bit 1
11547 #define RC5PPS2 RC5PPSbits.RC5PPS2 // bit 2
11548 #define RC5PPS3 RC5PPSbits.RC5PPS3 // bit 3
11549 #define RC5PPS4 RC5PPSbits.RC5PPS4 // bit 4
11551 #define RC6PPS0 RC6PPSbits.RC6PPS0 // bit 0
11552 #define RC6PPS1 RC6PPSbits.RC6PPS1 // bit 1
11553 #define RC6PPS2 RC6PPSbits.RC6PPS2 // bit 2
11554 #define RC6PPS3 RC6PPSbits.RC6PPS3 // bit 3
11555 #define RC6PPS4 RC6PPSbits.RC6PPS4 // bit 4
11557 #define RC7PPS0 RC7PPSbits.RC7PPS0 // bit 0
11558 #define RC7PPS1 RC7PPSbits.RC7PPS1 // bit 1
11559 #define RC7PPS2 RC7PPSbits.RC7PPS2 // bit 2
11560 #define RC7PPS3 RC7PPSbits.RC7PPS3 // bit 3
11561 #define RC7PPS4 RC7PPSbits.RC7PPS4 // bit 4
11563 #define RXDTPPS0 RXPPSbits.RXDTPPS0 // bit 0
11564 #define RXDTPPS1 RXPPSbits.RXDTPPS1 // bit 1
11565 #define RXDTPPS2 RXPPSbits.RXDTPPS2 // bit 2
11566 #define RXDTPPS3 RXPPSbits.RXDTPPS3 // bit 3
11567 #define RXDTPPS4 RXPPSbits.RXDTPPS4 // bit 4
11569 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
11570 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
11571 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
11572 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
11573 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
11575 #define SLRB4 SLRCONBbits.SLRB4 // bit 4
11576 #define SLRB5 SLRCONBbits.SLRB5 // bit 5
11577 #define SLRB6 SLRCONBbits.SLRB6 // bit 6
11578 #define SLRB7 SLRCONBbits.SLRB7 // bit 7
11580 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
11581 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
11582 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
11583 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
11584 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
11585 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
11586 #define SLRC6 SLRCONCbits.SLRC6 // bit 6
11587 #define SLRC7 SLRCONCbits.SLRC7 // bit 7
11589 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
11590 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
11591 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
11592 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
11593 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
11594 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
11595 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
11596 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
11597 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
11598 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
11599 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
11600 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
11601 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
11602 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
11603 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
11604 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
11606 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
11607 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
11608 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
11609 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
11610 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
11611 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
11612 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
11613 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
11614 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
11615 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
11616 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
11617 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
11618 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
11619 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
11620 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
11621 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
11623 #define SSP1CLKPPS0 SSP1CLKPPSbits.SSP1CLKPPS0 // bit 0
11624 #define SSP1CLKPPS1 SSP1CLKPPSbits.SSP1CLKPPS1 // bit 1
11625 #define SSP1CLKPPS2 SSP1CLKPPSbits.SSP1CLKPPS2 // bit 2
11626 #define SSP1CLKPPS3 SSP1CLKPPSbits.SSP1CLKPPS3 // bit 3
11627 #define SSP1CLKPPS4 SSP1CLKPPSbits.SSP1CLKPPS4 // bit 4
11629 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
11630 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
11631 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
11632 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
11633 #define CKP SSP1CONbits.CKP // bit 4
11634 #define SSPEN SSP1CONbits.SSPEN // bit 5
11635 #define SSPOV SSP1CONbits.SSPOV // bit 6
11636 #define WCOL SSP1CONbits.WCOL // bit 7
11638 #define SEN SSP1CON2bits.SEN // bit 0
11639 #define RSEN SSP1CON2bits.RSEN // bit 1
11640 #define PEN SSP1CON2bits.PEN // bit 2
11641 #define RCEN SSP1CON2bits.RCEN // bit 3
11642 #define ACKEN SSP1CON2bits.ACKEN // bit 4
11643 #define ACKDT SSP1CON2bits.ACKDT // bit 5
11644 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
11645 #define GCEN SSP1CON2bits.GCEN // bit 7
11647 #define DHEN SSP1CON3bits.DHEN // bit 0
11648 #define AHEN SSP1CON3bits.AHEN // bit 1
11649 #define SBCDE SSP1CON3bits.SBCDE // bit 2
11650 #define SDAHT SSP1CON3bits.SDAHT // bit 3
11651 #define BOEN SSP1CON3bits.BOEN // bit 4
11652 #define SCIE SSP1CON3bits.SCIE // bit 5
11653 #define PCIE SSP1CON3bits.PCIE // bit 6
11654 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
11656 #define SSP1DATPPS0 SSP1DATPPSbits.SSP1DATPPS0 // bit 0
11657 #define SSP1DATPPS1 SSP1DATPPSbits.SSP1DATPPS1 // bit 1
11658 #define SSP1DATPPS2 SSP1DATPPSbits.SSP1DATPPS2 // bit 2
11659 #define SSP1DATPPS3 SSP1DATPPSbits.SSP1DATPPS3 // bit 3
11660 #define SSP1DATPPS4 SSP1DATPPSbits.SSP1DATPPS4 // bit 4
11662 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
11663 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
11664 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
11665 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
11666 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
11667 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
11668 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
11669 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
11670 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
11671 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
11672 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
11673 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
11674 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
11675 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
11676 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
11677 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
11679 #define SSP1SSPPS0 SSP1SSPPSbits.SSP1SSPPS0 // bit 0
11680 #define SSP1SSPPS1 SSP1SSPPSbits.SSP1SSPPS1 // bit 1
11681 #define SSP1SSPPS2 SSP1SSPPSbits.SSP1SSPPS2 // bit 2
11682 #define SSP1SSPPS3 SSP1SSPPSbits.SSP1SSPPS3 // bit 3
11683 #define SSP1SSPPS4 SSP1SSPPSbits.SSP1SSPPS4 // bit 4
11685 #define BF SSP1STATbits.BF // bit 0
11686 #define UA SSP1STATbits.UA // bit 1
11687 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
11688 #define S SSP1STATbits.S // bit 3
11689 #define P SSP1STATbits.P // bit 4
11690 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
11691 #define CKE SSP1STATbits.CKE // bit 6
11692 #define SMP SSP1STATbits.SMP // bit 7
11694 #define C STATUSbits.C // bit 0
11695 #define DC STATUSbits.DC // bit 1
11696 #define Z STATUSbits.Z // bit 2
11697 #define NOT_PD STATUSbits.NOT_PD // bit 3
11698 #define NOT_TO STATUSbits.NOT_TO // bit 4
11700 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
11701 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
11702 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
11704 #define T0CKIPPS0 T0CKIPPSbits.T0CKIPPS0 // bit 0
11705 #define T0CKIPPS1 T0CKIPPSbits.T0CKIPPS1 // bit 1
11706 #define T0CKIPPS2 T0CKIPPSbits.T0CKIPPS2 // bit 2
11707 #define T0CKIPPS3 T0CKIPPSbits.T0CKIPPS3 // bit 3
11708 #define T0CKIPPS4 T0CKIPPSbits.T0CKIPPS4 // bit 4
11710 #define T0OUTPS0 T0CON0bits.T0OUTPS0 // bit 0
11711 #define T0OUTPS1 T0CON0bits.T0OUTPS1 // bit 1
11712 #define T0OUTPS2 T0CON0bits.T0OUTPS2 // bit 2
11713 #define T0OUTPS3 T0CON0bits.T0OUTPS3 // bit 3
11714 #define T016BIT T0CON0bits.T016BIT // bit 4
11715 #define T0OUT T0CON0bits.T0OUT // bit 5
11716 #define T0EN T0CON0bits.T0EN // bit 7
11718 #define T0CKPS0 T0CON1bits.T0CKPS0 // bit 0
11719 #define T0CKPS1 T0CON1bits.T0CKPS1 // bit 1
11720 #define T0CKPS2 T0CON1bits.T0CKPS2 // bit 2
11721 #define T0CKPS3 T0CON1bits.T0CKPS3 // bit 3
11722 #define T0ASYNC T0CON1bits.T0ASYNC // bit 4
11723 #define T0CS0 T0CON1bits.T0CS0 // bit 5
11724 #define T0CS1 T0CON1bits.T0CS1 // bit 6
11725 #define T0CS2 T0CON1bits.T0CS2 // bit 7
11727 #define T1CKIPPS0 T1CKIPPSbits.T1CKIPPS0 // bit 0
11728 #define T1CKIPPS1 T1CKIPPSbits.T1CKIPPS1 // bit 1
11729 #define T1CKIPPS2 T1CKIPPSbits.T1CKIPPS2 // bit 2
11730 #define T1CKIPPS3 T1CKIPPSbits.T1CKIPPS3 // bit 3
11731 #define T1CKIPPS4 T1CKIPPSbits.T1CKIPPS4 // bit 4
11733 #define TMR1ON T1CONbits.TMR1ON // bit 0
11734 #define T1SYNC T1CONbits.T1SYNC // bit 2
11735 #define T1SOSC T1CONbits.T1SOSC // bit 3
11736 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
11737 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
11738 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
11739 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
11741 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
11742 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
11743 #define T1GVAL T1GCONbits.T1GVAL // bit 2
11744 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3
11745 #define T1GSPM T1GCONbits.T1GSPM // bit 4
11746 #define T1GTM T1GCONbits.T1GTM // bit 5
11747 #define T1GPOL T1GCONbits.T1GPOL // bit 6
11748 #define TMR1GE T1GCONbits.TMR1GE // bit 7
11750 #define T1GPPS0 T1GPPSbits.T1GPPS0 // bit 0
11751 #define T1GPPS1 T1GPPSbits.T1GPPS1 // bit 1
11752 #define T1GPPS2 T1GPPSbits.T1GPPS2 // bit 2
11753 #define T1GPPS3 T1GPPSbits.T1GPPS3 // bit 3
11754 #define T1GPPS4 T1GPPSbits.T1GPPS4 // bit 4
11756 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
11757 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
11758 #define TMR2ON T2CONbits.TMR2ON // bit 2
11759 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
11760 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
11761 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
11762 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
11764 #define TMR3ON T3CONbits.TMR3ON // bit 0
11765 #define T3SYNC T3CONbits.T3SYNC // bit 2
11766 #define T3SOSC T3CONbits.T3SOSC // bit 3
11767 #define T3CKPS0 T3CONbits.T3CKPS0 // bit 4
11768 #define T3CKPS1 T3CONbits.T3CKPS1 // bit 5
11769 #define TMR3CS0 T3CONbits.TMR3CS0 // bit 6
11770 #define TMR3CS1 T3CONbits.TMR3CS1 // bit 7
11772 #define T3GSS0 T3GCONbits.T3GSS0 // bit 0
11773 #define T3GSS1 T3GCONbits.T3GSS1 // bit 1
11774 #define T3GVAL T3GCONbits.T3GVAL // bit 2
11775 #define T3GGO_NOT_DONE T3GCONbits.T3GGO_NOT_DONE // bit 3
11776 #define T3GSPM T3GCONbits.T3GSPM // bit 4
11777 #define T3GTM T3GCONbits.T3GTM // bit 5
11778 #define T3GPOL T3GCONbits.T3GPOL // bit 6
11779 #define TMR3GE T3GCONbits.TMR3GE // bit 7
11781 #define T4CKPS0 T4CONbits.T4CKPS0 // bit 0
11782 #define T4CKPS1 T4CONbits.T4CKPS1 // bit 1
11783 #define TMR4ON T4CONbits.TMR4ON // bit 2
11784 #define T4OUTPS0 T4CONbits.T4OUTPS0 // bit 3
11785 #define T4OUTPS1 T4CONbits.T4OUTPS1 // bit 4
11786 #define T4OUTPS2 T4CONbits.T4OUTPS2 // bit 5
11787 #define T4OUTPS3 T4CONbits.T4OUTPS3 // bit 6
11789 #define TMR5ON T5CONbits.TMR5ON // bit 0
11790 #define T5SYNC T5CONbits.T5SYNC // bit 2
11791 #define T5SOSC T5CONbits.T5SOSC // bit 3
11792 #define T5CKPS0 T5CONbits.T5CKPS0 // bit 4
11793 #define T5CKPS1 T5CONbits.T5CKPS1 // bit 5
11794 #define TMR5CS0 T5CONbits.TMR5CS0 // bit 6
11795 #define TMR5CS1 T5CONbits.TMR5CS1 // bit 7
11797 #define T5GSS0 T5GCONbits.T5GSS0 // bit 0
11798 #define T5GSS1 T5GCONbits.T5GSS1 // bit 1
11799 #define T5GVAL T5GCONbits.T5GVAL // bit 2
11800 #define T5GGO_NOT_DONE T5GCONbits.T5GGO_NOT_DONE // bit 3
11801 #define T5GSPM T5GCONbits.T5GSPM // bit 4
11802 #define T5GTM T5GCONbits.T5GTM // bit 5
11803 #define T5GPOL T5GCONbits.T5GPOL // bit 6
11804 #define TMR5GE T5GCONbits.TMR5GE // bit 7
11806 #define T6CKPS0 T6CONbits.T6CKPS0 // bit 0
11807 #define T6CKPS1 T6CONbits.T6CKPS1 // bit 1
11808 #define TMR6ON T6CONbits.TMR6ON // bit 2
11809 #define T6OUTPS0 T6CONbits.T6OUTPS0 // bit 3
11810 #define T6OUTPS1 T6CONbits.T6OUTPS1 // bit 4
11811 #define T6OUTPS2 T6CONbits.T6OUTPS2 // bit 5
11812 #define T6OUTPS3 T6CONbits.T6OUTPS3 // bit 6
11814 #define TMR08 TMR0Hbits.TMR08 // bit 0
11815 #define TMR09 TMR0Hbits.TMR09 // bit 1
11816 #define TMR010 TMR0Hbits.TMR010 // bit 2
11817 #define TMR011 TMR0Hbits.TMR011 // bit 3
11818 #define TMR012 TMR0Hbits.TMR012 // bit 4
11819 #define TMR013 TMR0Hbits.TMR013 // bit 5
11820 #define TMR014 TMR0Hbits.TMR014 // bit 6
11821 #define TMR015 TMR0Hbits.TMR015 // bit 7
11823 #define TMR00 TMR0Lbits.TMR00 // bit 0
11824 #define TMR01 TMR0Lbits.TMR01 // bit 1
11825 #define TMR02 TMR0Lbits.TMR02 // bit 2
11826 #define TMR03 TMR0Lbits.TMR03 // bit 3
11827 #define TMR04 TMR0Lbits.TMR04 // bit 4
11828 #define TMR05 TMR0Lbits.TMR05 // bit 5
11829 #define TMR06 TMR0Lbits.TMR06 // bit 6
11830 #define TMR07 TMR0Lbits.TMR07 // bit 7
11832 #define TRISA0 TRISAbits.TRISA0 // bit 0
11833 #define TRISA1 TRISAbits.TRISA1 // bit 1
11834 #define TRISA2 TRISAbits.TRISA2 // bit 2
11835 #define TRISA4 TRISAbits.TRISA4 // bit 4
11836 #define TRISA5 TRISAbits.TRISA5 // bit 5
11838 #define TRISB4 TRISBbits.TRISB4 // bit 4
11839 #define TRISB5 TRISBbits.TRISB5 // bit 5
11840 #define TRISB6 TRISBbits.TRISB6 // bit 6
11841 #define TRISB7 TRISBbits.TRISB7 // bit 7
11843 #define TRISC0 TRISCbits.TRISC0 // bit 0
11844 #define TRISC1 TRISCbits.TRISC1 // bit 1
11845 #define TRISC2 TRISCbits.TRISC2 // bit 2
11846 #define TRISC3 TRISCbits.TRISC3 // bit 3
11847 #define TRISC4 TRISCbits.TRISC4 // bit 4
11848 #define TRISC5 TRISCbits.TRISC5 // bit 5
11849 #define TRISC6 TRISCbits.TRISC6 // bit 6
11850 #define TRISC7 TRISCbits.TRISC7 // bit 7
11852 #define TX9D TX1STAbits.TX9D // bit 0
11853 #define TRMT TX1STAbits.TRMT // bit 1
11854 #define BRGH TX1STAbits.BRGH // bit 2
11855 #define SENDB TX1STAbits.SENDB // bit 3
11856 #define SYNC TX1STAbits.SYNC // bit 4
11857 #define TXEN TX1STAbits.TXEN // bit 5
11858 #define TX9 TX1STAbits.TX9 // bit 6
11859 #define CSRC TX1STAbits.CSRC // bit 7
11861 #define TXCKPPS0 TXPPSbits.TXCKPPS0 // bit 0
11862 #define TXCKPPS1 TXPPSbits.TXCKPPS1 // bit 1
11863 #define TXCKPPS2 TXPPSbits.TXCKPPS2 // bit 2
11864 #define TXCKPPS3 TXPPSbits.TXCKPPS3 // bit 3
11865 #define TXCKPPS4 TXPPSbits.TXCKPPS4 // bit 4
11867 #define VREGPM VREGCONbits.VREGPM // bit 1
11869 #define SWDTEN WDTCONbits.SWDTEN // bit 0
11870 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
11871 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
11872 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
11873 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
11874 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
11876 #define WPUA0 WPUAbits.WPUA0 // bit 0
11877 #define WPUA1 WPUAbits.WPUA1 // bit 1
11878 #define WPUA2 WPUAbits.WPUA2 // bit 2
11879 #define WPUA3 WPUAbits.WPUA3 // bit 3
11880 #define WPUA4 WPUAbits.WPUA4 // bit 4
11881 #define WPUA5 WPUAbits.WPUA5 // bit 5
11883 #define WPUB4 WPUBbits.WPUB4 // bit 4
11884 #define WPUB5 WPUBbits.WPUB5 // bit 5
11885 #define WPUB6 WPUBbits.WPUB6 // bit 6
11886 #define WPUB7 WPUBbits.WPUB7 // bit 7
11888 #define WPUC0 WPUCbits.WPUC0 // bit 0
11889 #define WPUC1 WPUCbits.WPUC1 // bit 1
11890 #define WPUC2 WPUCbits.WPUC2 // bit 2
11891 #define WPUC3 WPUCbits.WPUC3 // bit 3
11892 #define WPUC4 WPUCbits.WPUC4 // bit 4
11893 #define WPUC5 WPUCbits.WPUC5 // bit 5
11894 #define WPUC6 WPUCbits.WPUC6 // bit 6
11895 #define WPUC7 WPUCbits.WPUC7 // bit 7
11897 #endif // #ifndef NO_BIT_DEFINES
11899 #endif // #ifndef __PIC16F18344_H__