2 * This declarations of the PIC16F631 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:22:57 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F631_H__
26 #define __PIC16F631_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF_ADDR 0x0000
37 #define TMR0_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR_ADDR 0x0004
41 #define PORTA_ADDR 0x0005
42 #define PORTB_ADDR 0x0006
43 #define PORTC_ADDR 0x0007
44 #define PCLATH_ADDR 0x000A
45 #define INTCON_ADDR 0x000B
46 #define PIR1_ADDR 0x000C
47 #define PIR2_ADDR 0x000D
48 #define TMR1_ADDR 0x000E
49 #define TMR1L_ADDR 0x000E
50 #define TMR1H_ADDR 0x000F
51 #define T1CON_ADDR 0x0010
52 #define OPTION_REG_ADDR 0x0081
53 #define TRISA_ADDR 0x0085
54 #define TRISB_ADDR 0x0086
55 #define TRISC_ADDR 0x0087
56 #define PIE1_ADDR 0x008C
57 #define PIE2_ADDR 0x008D
58 #define PCON_ADDR 0x008E
59 #define OSCCON_ADDR 0x008F
60 #define OSCTUNE_ADDR 0x0090
61 #define WPU_ADDR 0x0095
62 #define WPUA_ADDR 0x0095
63 #define IOC_ADDR 0x0096
64 #define IOCA_ADDR 0x0096
65 #define WDTCON_ADDR 0x0097
66 #define EEDAT_ADDR 0x010C
67 #define EEDATA_ADDR 0x010C
68 #define EEADR_ADDR 0x010D
69 #define WPUB_ADDR 0x0115
70 #define IOCB_ADDR 0x0116
71 #define VRCON_ADDR 0x0118
72 #define CM1CON0_ADDR 0x0119
73 #define CM2CON0_ADDR 0x011A
74 #define CM2CON1_ADDR 0x011B
75 #define ANSEL_ADDR 0x011E
76 #define EECON1_ADDR 0x018C
77 #define EECON2_ADDR 0x018D
78 #define SRCON_ADDR 0x019E
80 #endif // #ifndef NO_ADDR_DEFINES
82 //==============================================================================
84 // Register Definitions
86 //==============================================================================
88 extern __at(0x0000) __sfr INDF
;
89 extern __at(0x0001) __sfr TMR0
;
90 extern __at(0x0002) __sfr PCL
;
92 //==============================================================================
95 extern __at(0x0003) __sfr STATUS
;
119 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
130 //==============================================================================
132 extern __at(0x0004) __sfr FSR
;
134 //==============================================================================
137 extern __at(0x0005) __sfr PORTA
;
160 extern __at(0x0005) volatile __PORTAbits_t PORTAbits
;
169 //==============================================================================
172 //==============================================================================
175 extern __at(0x0006) __sfr PORTB
;
189 extern __at(0x0006) volatile __PORTBbits_t PORTBbits
;
196 //==============================================================================
199 //==============================================================================
202 extern __at(0x0007) __sfr PORTC
;
216 extern __at(0x0007) volatile __PORTCbits_t PORTCbits
;
227 //==============================================================================
229 extern __at(0x000A) __sfr PCLATH
;
231 //==============================================================================
234 extern __at(0x000B) __sfr INTCON
;
248 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
259 //==============================================================================
262 //==============================================================================
265 extern __at(0x000C) __sfr PIR1
;
294 extern __at(0x000C) volatile __PIR1bits_t PIR1bits
;
299 //==============================================================================
302 //==============================================================================
305 extern __at(0x000D) __sfr PIR2
;
319 extern __at(0x000D) volatile __PIR2bits_t PIR2bits
;
326 //==============================================================================
328 extern __at(0x000E) __sfr TMR1
;
329 extern __at(0x000E) __sfr TMR1L
;
330 extern __at(0x000F) __sfr TMR1H
;
332 //==============================================================================
335 extern __at(0x0010) __sfr T1CON
;
343 unsigned NOT_T1SYNC
: 1;
344 unsigned T1OSCEN
: 1;
345 unsigned T1CKPS0
: 1;
346 unsigned T1CKPS1
: 1;
359 extern __at(0x0010) volatile __T1CONbits_t T1CONbits
;
363 #define _NOT_T1SYNC 0x04
364 #define _T1OSCEN 0x08
365 #define _T1CKPS0 0x10
366 #define _T1CKPS1 0x20
370 //==============================================================================
373 //==============================================================================
376 extern __at(0x0081) __sfr OPTION_REG
;
389 unsigned NOT_RABPU
: 1;
397 } __OPTION_REGbits_t
;
399 extern __at(0x0081) volatile __OPTION_REGbits_t OPTION_REGbits
;
408 #define _NOT_RABPU 0x80
410 //==============================================================================
413 //==============================================================================
416 extern __at(0x0085) __sfr TRISA
;
439 extern __at(0x0085) volatile __TRISAbits_t TRISAbits
;
448 //==============================================================================
451 //==============================================================================
454 extern __at(0x0086) __sfr TRISB
;
468 extern __at(0x0086) volatile __TRISBbits_t TRISBbits
;
475 //==============================================================================
478 //==============================================================================
481 extern __at(0x0087) __sfr TRISC
;
495 extern __at(0x0087) volatile __TRISCbits_t TRISCbits
;
506 //==============================================================================
509 //==============================================================================
512 extern __at(0x008C) __sfr PIE1
;
541 extern __at(0x008C) volatile __PIE1bits_t PIE1bits
;
546 //==============================================================================
549 //==============================================================================
552 extern __at(0x008D) __sfr PIE2
;
566 extern __at(0x008D) volatile __PIE2bits_t PIE2bits
;
573 //==============================================================================
576 //==============================================================================
579 extern __at(0x008E) __sfr PCON
;
585 unsigned NOT_BOR
: 1;
586 unsigned NOT_POR
: 1;
608 extern __at(0x008E) volatile __PCONbits_t PCONbits
;
610 #define _NOT_BOR 0x01
612 #define _NOT_POR 0x02
617 //==============================================================================
620 //==============================================================================
623 extern __at(0x008F) __sfr OSCCON
;
647 extern __at(0x008F) volatile __OSCCONbits_t OSCCONbits
;
657 //==============================================================================
660 //==============================================================================
663 extern __at(0x0090) __sfr OSCTUNE
;
686 extern __at(0x0090) volatile __OSCTUNEbits_t OSCTUNEbits
;
694 //==============================================================================
697 //==============================================================================
700 extern __at(0x0095) __sfr WPU
;
729 extern __at(0x0095) volatile __WPUbits_t WPUbits
;
742 //==============================================================================
745 //==============================================================================
748 extern __at(0x0095) __sfr WPUA
;
777 extern __at(0x0095) volatile __WPUAbits_t WPUAbits
;
779 #define _WPUA_WPUA0 0x01
780 #define _WPUA_WPU0 0x01
781 #define _WPUA_WPUA1 0x02
782 #define _WPUA_WPU1 0x02
783 #define _WPUA_WPUA2 0x04
784 #define _WPUA_WPU2 0x04
785 #define _WPUA_WPUA4 0x10
786 #define _WPUA_WPU4 0x10
787 #define _WPUA_WPUA5 0x20
788 #define _WPUA_WPU5 0x20
790 //==============================================================================
793 //==============================================================================
796 extern __at(0x0096) __sfr IOC
;
837 extern __at(0x0096) volatile __IOCbits_t IOCbits
;
852 //==============================================================================
855 //==============================================================================
858 extern __at(0x0096) __sfr IOCA
;
899 extern __at(0x0096) volatile __IOCAbits_t IOCAbits
;
901 #define _IOCA_IOCA0 0x01
902 #define _IOCA_IOC0 0x01
903 #define _IOCA_IOCA1 0x02
904 #define _IOCA_IOC1 0x02
905 #define _IOCA_IOCA2 0x04
906 #define _IOCA_IOC2 0x04
907 #define _IOCA_IOCA3 0x08
908 #define _IOCA_IOC3 0x08
909 #define _IOCA_IOCA4 0x10
910 #define _IOCA_IOC4 0x10
911 #define _IOCA_IOCA5 0x20
912 #define _IOCA_IOC5 0x20
914 //==============================================================================
917 //==============================================================================
920 extern __at(0x0097) __sfr WDTCON
;
944 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
952 //==============================================================================
954 extern __at(0x010C) __sfr EEDAT
;
955 extern __at(0x010C) __sfr EEDATA
;
956 extern __at(0x010D) __sfr EEADR
;
958 //==============================================================================
961 extern __at(0x0115) __sfr WPUB
;
975 extern __at(0x0115) volatile __WPUBbits_t WPUBbits
;
982 //==============================================================================
985 //==============================================================================
988 extern __at(0x0116) __sfr IOCB
;
1002 extern __at(0x0116) volatile __IOCBbits_t IOCBbits
;
1009 //==============================================================================
1012 //==============================================================================
1015 extern __at(0x0118) __sfr VRCON
;
1027 unsigned C2VREN
: 1;
1028 unsigned C1VREN
: 1;
1038 extern __at(0x0118) volatile __VRCONbits_t VRCONbits
;
1046 #define _C2VREN 0x40
1047 #define _C1VREN 0x80
1049 //==============================================================================
1052 //==============================================================================
1055 extern __at(0x0119) __sfr CM1CON0
;
1078 extern __at(0x0119) volatile __CM1CON0bits_t CM1CON0bits
;
1088 //==============================================================================
1091 //==============================================================================
1094 extern __at(0x011A) __sfr CM2CON0
;
1117 extern __at(0x011A) volatile __CM2CON0bits_t CM2CON0bits
;
1127 //==============================================================================
1130 //==============================================================================
1133 extern __at(0x011B) __sfr CM2CON1
;
1137 unsigned C2SYNC
: 1;
1143 unsigned MC2OUT
: 1;
1144 unsigned MC1OUT
: 1;
1147 extern __at(0x011B) volatile __CM2CON1bits_t CM2CON1bits
;
1149 #define _C2SYNC 0x01
1151 #define _MC2OUT 0x40
1152 #define _MC1OUT 0x80
1154 //==============================================================================
1157 //==============================================================================
1160 extern __at(0x011E) __sfr ANSEL
;
1174 extern __at(0x011E) volatile __ANSELbits_t ANSELbits
;
1183 //==============================================================================
1186 //==============================================================================
1189 extern __at(0x018C) __sfr EECON1
;
1203 extern __at(0x018C) volatile __EECON1bits_t EECON1bits
;
1210 //==============================================================================
1212 extern __at(0x018D) __sfr EECON2
;
1214 //==============================================================================
1217 extern __at(0x019E) __sfr SRCON
;
1240 extern __at(0x019E) volatile __SRCONbits_t SRCONbits
;
1249 //==============================================================================
1252 //==============================================================================
1254 // Configuration Bits
1256 //==============================================================================
1258 #define _CONFIG 0x2007
1260 //----------------------------- CONFIG Options -------------------------------
1262 #define _FOSC_LP 0x3FF8 // LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1263 #define _LP_OSC 0x3FF8 // LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1264 #define _FOSC_XT 0x3FF9 // XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1265 #define _XT_OSC 0x3FF9 // XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1266 #define _FOSC_HS 0x3FFA // HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1267 #define _HS_OSC 0x3FFA // HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1268 #define _FOSC_EC 0x3FFB // EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN.
1269 #define _EC_OSC 0x3FFB // EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN.
1270 #define _FOSC_INTRCIO 0x3FFC // INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1271 #define _INTRC_OSC_NOCLKOUT 0x3FFC // INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1272 #define _INTOSCIO 0x3FFC // INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1273 #define _FOSC_INTRCCLK 0x3FFD // INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1274 #define _INTRC_OSC_CLKOUT 0x3FFD // INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1275 #define _INTOSC 0x3FFD // INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1276 #define _FOSC_EXTRCIO 0x3FFE // RCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN.
1277 #define _EXTRC_OSC_NOCLKOUT 0x3FFE // RCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN.
1278 #define _EXTRCIO 0x3FFE // RCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN.
1279 #define _FOSC_EXTRCCLK 0x3FFF // RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN.
1280 #define _EXTRC_OSC_CLKOUT 0x3FFF // RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN.
1281 #define _EXTRC 0x3FFF // RC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, RC on RA5/OSC1/CLKIN.
1282 #define _WDTE_OFF 0x3FF7 // WDT disabled and can be enabled by SWDTEN bit of the WDTCON register.
1283 #define _WDT_OFF 0x3FF7 // WDT disabled and can be enabled by SWDTEN bit of the WDTCON register.
1284 #define _WDTE_ON 0x3FFF // WDT enabled.
1285 #define _WDT_ON 0x3FFF // WDT enabled.
1286 #define _PWRTE_ON 0x3FEF // PWRT enabled.
1287 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
1288 #define _MCLRE_OFF 0x3FDF // MCLR pin function is digital input, MCLR internally tied to VDD.
1289 #define _MCLRE_ON 0x3FFF // MCLR pin function is MCLR.
1290 #define _CP_ON 0x3FBF // Program memory code protection is enabled.
1291 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
1292 #define _CPD_ON 0x3F7F // Data memory code protection is enabled.
1293 #define _CPD_OFF 0x3FFF // Data memory code protection is disabled.
1294 #define _BOREN_OFF 0x3CFF // BOR disabled.
1295 #define _BOD_OFF 0x3CFF // BOR disabled.
1296 #define _BOR_OFF 0x3CFF // BOR disabled.
1297 #define _BOREN_SBODEN 0x3DFF // BOR controlled by SBOREN bit of the PCON register.
1298 #define _BOD_SBODEN 0x3DFF // BOR controlled by SBOREN bit of the PCON register.
1299 #define _BOR_SBODEN 0x3DFF // BOR controlled by SBOREN bit of the PCON register.
1300 #define _BOREN_NSLEEP 0x3EFF // BOR enabled during operation and disabled in Sleep.
1301 #define _BOD_NSLEEP 0x3EFF // BOR enabled during operation and disabled in Sleep.
1302 #define _BOR_NSLEEP 0x3EFF // BOR enabled during operation and disabled in Sleep.
1303 #define _BOREN_ON 0x3FFF // BOR enabled.
1304 #define _BOD_ON 0x3FFF // BOR enabled.
1305 #define _BOR_ON 0x3FFF // BOR enabled.
1306 #define _IESO_OFF 0x3BFF // Internal External Switchover mode is disabled.
1307 #define _IESO_ON 0x3FFF // Internal External Switchover mode is enabled.
1308 #define _FCMEN_OFF 0x37FF // Fail-Safe Clock Monitor is disabled.
1309 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
1311 //==============================================================================
1313 #define _DEVID1 0x2006
1315 #define _IDLOC0 0x2000
1316 #define _IDLOC1 0x2001
1317 #define _IDLOC2 0x2002
1318 #define _IDLOC3 0x2003
1320 //==============================================================================
1322 #ifndef NO_BIT_DEFINES
1324 #define ANS0 ANSELbits.ANS0 // bit 0
1325 #define ANS1 ANSELbits.ANS1 // bit 1
1326 #define ANS4 ANSELbits.ANS4 // bit 4
1327 #define ANS5 ANSELbits.ANS5 // bit 5
1328 #define ANS6 ANSELbits.ANS6 // bit 6
1329 #define ANS7 ANSELbits.ANS7 // bit 7
1331 #define C1CH0 CM1CON0bits.C1CH0 // bit 0
1332 #define C1CH1 CM1CON0bits.C1CH1 // bit 1
1333 #define C1R CM1CON0bits.C1R // bit 2
1334 #define C1POL CM1CON0bits.C1POL // bit 4
1335 #define C1OE CM1CON0bits.C1OE // bit 5
1336 #define C1OUT CM1CON0bits.C1OUT // bit 6
1337 #define C1ON CM1CON0bits.C1ON // bit 7
1339 #define C2CH0 CM2CON0bits.C2CH0 // bit 0
1340 #define C2CH1 CM2CON0bits.C2CH1 // bit 1
1341 #define C2R CM2CON0bits.C2R // bit 2
1342 #define C2POL CM2CON0bits.C2POL // bit 4
1343 #define C2OE CM2CON0bits.C2OE // bit 5
1344 #define C2OUT CM2CON0bits.C2OUT // bit 6
1345 #define C2ON CM2CON0bits.C2ON // bit 7
1347 #define C2SYNC CM2CON1bits.C2SYNC // bit 0
1348 #define T1GSS CM2CON1bits.T1GSS // bit 1
1349 #define MC2OUT CM2CON1bits.MC2OUT // bit 6
1350 #define MC1OUT CM2CON1bits.MC1OUT // bit 7
1352 #define RD EECON1bits.RD // bit 0
1353 #define WR EECON1bits.WR // bit 1
1354 #define WREN EECON1bits.WREN // bit 2
1355 #define WRERR EECON1bits.WRERR // bit 3
1357 #define RABIF INTCONbits.RABIF // bit 0
1358 #define INTF INTCONbits.INTF // bit 1
1359 #define T0IF INTCONbits.T0IF // bit 2
1360 #define RABIE INTCONbits.RABIE // bit 3
1361 #define INTE INTCONbits.INTE // bit 4
1362 #define T0IE INTCONbits.T0IE // bit 5
1363 #define PEIE INTCONbits.PEIE // bit 6
1364 #define GIE INTCONbits.GIE // bit 7
1366 #define IOCA0 IOCbits.IOCA0 // bit 0, shadows bit in IOCbits
1367 #define IOC0 IOCbits.IOC0 // bit 0, shadows bit in IOCbits
1368 #define IOCA1 IOCbits.IOCA1 // bit 1, shadows bit in IOCbits
1369 #define IOC1 IOCbits.IOC1 // bit 1, shadows bit in IOCbits
1370 #define IOCA2 IOCbits.IOCA2 // bit 2, shadows bit in IOCbits
1371 #define IOC2 IOCbits.IOC2 // bit 2, shadows bit in IOCbits
1372 #define IOCA3 IOCbits.IOCA3 // bit 3, shadows bit in IOCbits
1373 #define IOC3 IOCbits.IOC3 // bit 3, shadows bit in IOCbits
1374 #define IOCA4 IOCbits.IOCA4 // bit 4, shadows bit in IOCbits
1375 #define IOC4 IOCbits.IOC4 // bit 4, shadows bit in IOCbits
1376 #define IOCA5 IOCbits.IOCA5 // bit 5, shadows bit in IOCbits
1377 #define IOC5 IOCbits.IOC5 // bit 5, shadows bit in IOCbits
1379 #define IOCB4 IOCBbits.IOCB4 // bit 4
1380 #define IOCB5 IOCBbits.IOCB5 // bit 5
1381 #define IOCB6 IOCBbits.IOCB6 // bit 6
1382 #define IOCB7 IOCBbits.IOCB7 // bit 7
1384 #define PS0 OPTION_REGbits.PS0 // bit 0
1385 #define PS1 OPTION_REGbits.PS1 // bit 1
1386 #define PS2 OPTION_REGbits.PS2 // bit 2
1387 #define PSA OPTION_REGbits.PSA // bit 3
1388 #define T0SE OPTION_REGbits.T0SE // bit 4
1389 #define T0CS OPTION_REGbits.T0CS // bit 5
1390 #define INTEDG OPTION_REGbits.INTEDG // bit 6
1391 #define NOT_RABPU OPTION_REGbits.NOT_RABPU // bit 7
1393 #define SCS OSCCONbits.SCS // bit 0
1394 #define LTS OSCCONbits.LTS // bit 1
1395 #define HTS OSCCONbits.HTS // bit 2
1396 #define OSTS OSCCONbits.OSTS // bit 3
1397 #define IRCF0 OSCCONbits.IRCF0 // bit 4
1398 #define IRCF1 OSCCONbits.IRCF1 // bit 5
1399 #define IRCF2 OSCCONbits.IRCF2 // bit 6
1401 #define TUN0 OSCTUNEbits.TUN0 // bit 0
1402 #define TUN1 OSCTUNEbits.TUN1 // bit 1
1403 #define TUN2 OSCTUNEbits.TUN2 // bit 2
1404 #define TUN3 OSCTUNEbits.TUN3 // bit 3
1405 #define TUN4 OSCTUNEbits.TUN4 // bit 4
1407 #define NOT_BOR PCONbits.NOT_BOR // bit 0, shadows bit in PCONbits
1408 #define BOR PCONbits.BOR // bit 0, shadows bit in PCONbits
1409 #define NOT_POR PCONbits.NOT_POR // bit 1, shadows bit in PCONbits
1410 #define POR PCONbits.POR // bit 1, shadows bit in PCONbits
1411 #define SBOREN PCONbits.SBOREN // bit 4
1412 #define ULPWUE PCONbits.ULPWUE // bit 5
1414 #define TMR1IE PIE1bits.TMR1IE // bit 0, shadows bit in PIE1bits
1415 #define T1IE PIE1bits.T1IE // bit 0, shadows bit in PIE1bits
1417 #define EEIE PIE2bits.EEIE // bit 4
1418 #define C1IE PIE2bits.C1IE // bit 5
1419 #define C2IE PIE2bits.C2IE // bit 6
1420 #define OSFIE PIE2bits.OSFIE // bit 7
1422 #define TMR1IF PIR1bits.TMR1IF // bit 0, shadows bit in PIR1bits
1423 #define T1IF PIR1bits.T1IF // bit 0, shadows bit in PIR1bits
1425 #define EEIF PIR2bits.EEIF // bit 4
1426 #define C1IF PIR2bits.C1IF // bit 5
1427 #define C2IF PIR2bits.C2IF // bit 6
1428 #define OSFIF PIR2bits.OSFIF // bit 7
1430 #define RA0 PORTAbits.RA0 // bit 0
1431 #define RA1 PORTAbits.RA1 // bit 1
1432 #define RA2 PORTAbits.RA2 // bit 2
1433 #define RA3 PORTAbits.RA3 // bit 3
1434 #define RA4 PORTAbits.RA4 // bit 4
1435 #define RA5 PORTAbits.RA5 // bit 5
1437 #define RB4 PORTBbits.RB4 // bit 4
1438 #define RB5 PORTBbits.RB5 // bit 5
1439 #define RB6 PORTBbits.RB6 // bit 6
1440 #define RB7 PORTBbits.RB7 // bit 7
1442 #define RC0 PORTCbits.RC0 // bit 0
1443 #define RC1 PORTCbits.RC1 // bit 1
1444 #define RC2 PORTCbits.RC2 // bit 2
1445 #define RC3 PORTCbits.RC3 // bit 3
1446 #define RC4 PORTCbits.RC4 // bit 4
1447 #define RC5 PORTCbits.RC5 // bit 5
1448 #define RC6 PORTCbits.RC6 // bit 6
1449 #define RC7 PORTCbits.RC7 // bit 7
1451 #define PULSR SRCONbits.PULSR // bit 2
1452 #define PULSS SRCONbits.PULSS // bit 3
1453 #define C2REN SRCONbits.C2REN // bit 4
1454 #define C1SEN SRCONbits.C1SEN // bit 5
1455 #define SR0 SRCONbits.SR0 // bit 6
1456 #define SR1 SRCONbits.SR1 // bit 7
1458 #define C STATUSbits.C // bit 0
1459 #define DC STATUSbits.DC // bit 1
1460 #define Z STATUSbits.Z // bit 2
1461 #define NOT_PD STATUSbits.NOT_PD // bit 3
1462 #define NOT_TO STATUSbits.NOT_TO // bit 4
1463 #define RP0 STATUSbits.RP0 // bit 5
1464 #define RP1 STATUSbits.RP1 // bit 6
1465 #define IRP STATUSbits.IRP // bit 7
1467 #define TMR1ON T1CONbits.TMR1ON // bit 0
1468 #define TMR1CS T1CONbits.TMR1CS // bit 1
1469 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
1470 #define T1OSCEN T1CONbits.T1OSCEN // bit 3
1471 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
1472 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
1473 #define TMR1GE T1CONbits.TMR1GE // bit 6
1474 #define T1GINV T1CONbits.T1GINV // bit 7
1476 #define TRISA0 TRISAbits.TRISA0 // bit 0
1477 #define TRISA1 TRISAbits.TRISA1 // bit 1
1478 #define TRISA2 TRISAbits.TRISA2 // bit 2
1479 #define TRISA3 TRISAbits.TRISA3 // bit 3
1480 #define TRISA4 TRISAbits.TRISA4 // bit 4
1481 #define TRISA5 TRISAbits.TRISA5 // bit 5
1483 #define TRISB4 TRISBbits.TRISB4 // bit 4
1484 #define TRISB5 TRISBbits.TRISB5 // bit 5
1485 #define TRISB6 TRISBbits.TRISB6 // bit 6
1486 #define TRISB7 TRISBbits.TRISB7 // bit 7
1488 #define TRISC0 TRISCbits.TRISC0 // bit 0
1489 #define TRISC1 TRISCbits.TRISC1 // bit 1
1490 #define TRISC2 TRISCbits.TRISC2 // bit 2
1491 #define TRISC3 TRISCbits.TRISC3 // bit 3
1492 #define TRISC4 TRISCbits.TRISC4 // bit 4
1493 #define TRISC5 TRISCbits.TRISC5 // bit 5
1494 #define TRISC6 TRISCbits.TRISC6 // bit 6
1495 #define TRISC7 TRISCbits.TRISC7 // bit 7
1497 #define VR0 VRCONbits.VR0 // bit 0
1498 #define VR1 VRCONbits.VR1 // bit 1
1499 #define VR2 VRCONbits.VR2 // bit 2
1500 #define VR3 VRCONbits.VR3 // bit 3
1501 #define VP6EN VRCONbits.VP6EN // bit 4
1502 #define VRR VRCONbits.VRR // bit 5
1503 #define C2VREN VRCONbits.C2VREN // bit 6
1504 #define C1VREN VRCONbits.C1VREN // bit 7
1506 #define SWDTEN WDTCONbits.SWDTEN // bit 0
1507 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
1508 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
1509 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
1510 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
1512 #define WPUA0 WPUbits.WPUA0 // bit 0, shadows bit in WPUbits
1513 #define WPU0 WPUbits.WPU0 // bit 0, shadows bit in WPUbits
1514 #define WPUA1 WPUbits.WPUA1 // bit 1, shadows bit in WPUbits
1515 #define WPU1 WPUbits.WPU1 // bit 1, shadows bit in WPUbits
1516 #define WPUA2 WPUbits.WPUA2 // bit 2, shadows bit in WPUbits
1517 #define WPU2 WPUbits.WPU2 // bit 2, shadows bit in WPUbits
1518 #define WPUA4 WPUbits.WPUA4 // bit 4, shadows bit in WPUbits
1519 #define WPU4 WPUbits.WPU4 // bit 4, shadows bit in WPUbits
1520 #define WPUA5 WPUbits.WPUA5 // bit 5, shadows bit in WPUbits
1521 #define WPU5 WPUbits.WPU5 // bit 5, shadows bit in WPUbits
1523 #define WPUB4 WPUBbits.WPUB4 // bit 4
1524 #define WPUB5 WPUBbits.WPUB5 // bit 5
1525 #define WPUB6 WPUBbits.WPUB6 // bit 6
1526 #define WPUB7 WPUBbits.WPUB7 // bit 7
1528 #endif // #ifndef NO_BIT_DEFINES
1530 #endif // #ifndef __PIC16F631_H__