2 * This declarations of the PIC16F688 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:22:57 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F688_H__
26 #define __PIC16F688_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF_ADDR 0x0000
37 #define TMR0_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR_ADDR 0x0004
41 #define PORTA_ADDR 0x0005
42 #define PORTC_ADDR 0x0007
43 #define PCLATH_ADDR 0x000A
44 #define INTCON_ADDR 0x000B
45 #define PIR1_ADDR 0x000C
46 #define TMR1_ADDR 0x000E
47 #define TMR1L_ADDR 0x000E
48 #define TMR1H_ADDR 0x000F
49 #define T1CON_ADDR 0x0010
50 #define BAUDCTL_ADDR 0x0011
51 #define SPBRGH_ADDR 0x0012
52 #define SPBRG_ADDR 0x0013
53 #define RCREG_ADDR 0x0014
54 #define TXREG_ADDR 0x0015
55 #define TXSTA_ADDR 0x0016
56 #define RCSTA_ADDR 0x0017
57 #define WDTCON_ADDR 0x0018
58 #define CMCON0_ADDR 0x0019
59 #define CMCON1_ADDR 0x001A
60 #define ADRESH_ADDR 0x001E
61 #define ADCON0_ADDR 0x001F
62 #define OPTION_REG_ADDR 0x0081
63 #define TRISA_ADDR 0x0085
64 #define TRISC_ADDR 0x0087
65 #define PIE1_ADDR 0x008C
66 #define PCON_ADDR 0x008E
67 #define OSCCON_ADDR 0x008F
68 #define OSCTUNE_ADDR 0x0090
69 #define ANSEL_ADDR 0x0091
70 #define WPU_ADDR 0x0095
71 #define WPUA_ADDR 0x0095
72 #define IOC_ADDR 0x0096
73 #define IOCA_ADDR 0x0096
74 #define EEDATH_ADDR 0x0097
75 #define EEADRH_ADDR 0x0098
76 #define VRCON_ADDR 0x0099
77 #define EEDAT_ADDR 0x009A
78 #define EEDATA_ADDR 0x009A
79 #define EEADR_ADDR 0x009B
80 #define EECON1_ADDR 0x009C
81 #define EECON2_ADDR 0x009D
82 #define ADRESL_ADDR 0x009E
83 #define ADCON1_ADDR 0x009F
85 #endif // #ifndef NO_ADDR_DEFINES
87 //==============================================================================
89 // Register Definitions
91 //==============================================================================
93 extern __at(0x0000) __sfr INDF
;
94 extern __at(0x0001) __sfr TMR0
;
95 extern __at(0x0002) __sfr PCL
;
97 //==============================================================================
100 extern __at(0x0003) __sfr STATUS
;
124 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
135 //==============================================================================
137 extern __at(0x0004) __sfr FSR
;
139 //==============================================================================
142 extern __at(0x0005) __sfr PORTA
;
165 extern __at(0x0005) volatile __PORTAbits_t PORTAbits
;
174 //==============================================================================
177 //==============================================================================
180 extern __at(0x0007) __sfr PORTC
;
203 extern __at(0x0007) volatile __PORTCbits_t PORTCbits
;
212 //==============================================================================
214 extern __at(0x000A) __sfr PCLATH
;
216 //==============================================================================
219 extern __at(0x000B) __sfr INTCON
;
248 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
261 //==============================================================================
264 //==============================================================================
267 extern __at(0x000C) __sfr PIR1
;
296 extern __at(0x000C) volatile __PIR1bits_t PIR1bits
;
308 //==============================================================================
310 extern __at(0x000E) __sfr TMR1
;
311 extern __at(0x000E) __sfr TMR1L
;
312 extern __at(0x000F) __sfr TMR1H
;
314 //==============================================================================
317 extern __at(0x0010) __sfr T1CON
;
325 unsigned NOT_T1SYNC
: 1;
326 unsigned T1OSCEN
: 1;
327 unsigned T1CKPS0
: 1;
328 unsigned T1CKPS1
: 1;
341 extern __at(0x0010) volatile __T1CONbits_t T1CONbits
;
345 #define _NOT_T1SYNC 0x04
346 #define _T1OSCEN 0x08
347 #define _T1CKPS0 0x10
348 #define _T1CKPS1 0x20
352 //==============================================================================
355 //==============================================================================
358 extern __at(0x0011) __sfr BAUDCTL
;
360 #define BAUDCON BAUDCTL
374 extern __at(0x0011) volatile __BAUDCTLbits_t BAUDCTLbits
;
376 #define BAUDCONbits BAUDCTLbits
385 //==============================================================================
387 extern __at(0x0012) __sfr SPBRGH
;
388 extern __at(0x0013) __sfr SPBRG
;
389 extern __at(0x0014) __sfr RCREG
;
390 extern __at(0x0015) __sfr TXREG
;
392 //==============================================================================
395 extern __at(0x0016) __sfr TXSTA
;
409 extern __at(0x0016) volatile __TXSTAbits_t TXSTAbits
;
420 //==============================================================================
423 //==============================================================================
426 extern __at(0x0017) __sfr RCSTA
;
440 extern __at(0x0017) volatile __RCSTAbits_t RCSTAbits
;
451 //==============================================================================
454 //==============================================================================
457 extern __at(0x0018) __sfr WDTCON
;
481 extern __at(0x0018) volatile __WDTCONbits_t WDTCONbits
;
489 //==============================================================================
492 //==============================================================================
495 extern __at(0x0019) __sfr CMCON0
;
518 extern __at(0x0019) volatile __CMCON0bits_t CMCON0bits
;
529 //==============================================================================
532 //==============================================================================
535 extern __at(0x001A) __sfr CMCON1
;
549 extern __at(0x001A) volatile __CMCON1bits_t CMCON1bits
;
554 //==============================================================================
556 extern __at(0x001E) __sfr ADRESH
;
558 //==============================================================================
561 extern __at(0x001F) __sfr ADCON0
;
568 unsigned GO_NOT_DONE
: 1;
592 unsigned NOT_DONE
: 1;
604 unsigned GO_DONE
: 1;
621 extern __at(0x001F) volatile __ADCON0bits_t ADCON0bits
;
624 #define _GO_NOT_DONE 0x02
626 #define _NOT_DONE 0x02
627 #define _GO_DONE 0x02
634 //==============================================================================
637 //==============================================================================
640 extern __at(0x0081) __sfr OPTION_REG
;
653 unsigned NOT_RAPU
: 1;
661 } __OPTION_REGbits_t
;
663 extern __at(0x0081) volatile __OPTION_REGbits_t OPTION_REGbits
;
672 #define _NOT_RAPU 0x80
674 //==============================================================================
677 //==============================================================================
680 extern __at(0x0085) __sfr TRISA
;
703 extern __at(0x0085) volatile __TRISAbits_t TRISAbits
;
712 //==============================================================================
715 //==============================================================================
718 extern __at(0x0087) __sfr TRISC
;
741 extern __at(0x0087) volatile __TRISCbits_t TRISCbits
;
750 //==============================================================================
753 //==============================================================================
756 extern __at(0x008C) __sfr PIE1
;
785 extern __at(0x008C) volatile __PIE1bits_t PIE1bits
;
797 //==============================================================================
800 //==============================================================================
803 extern __at(0x008E) __sfr PCON
;
809 unsigned NOT_BOR
: 1;
810 unsigned NOT_POR
: 1;
821 unsigned NOT_BOD
: 1;
832 extern __at(0x008E) volatile __PCONbits_t PCONbits
;
834 #define _NOT_BOR 0x01
835 #define _NOT_BOD 0x01
836 #define _NOT_POR 0x02
840 //==============================================================================
843 //==============================================================================
846 extern __at(0x008F) __sfr OSCCON
;
870 extern __at(0x008F) volatile __OSCCONbits_t OSCCONbits
;
880 //==============================================================================
883 //==============================================================================
886 extern __at(0x0090) __sfr OSCTUNE
;
909 extern __at(0x0090) volatile __OSCTUNEbits_t OSCTUNEbits
;
917 //==============================================================================
920 //==============================================================================
923 extern __at(0x0091) __sfr ANSEL
;
937 extern __at(0x0091) volatile __ANSELbits_t ANSELbits
;
948 //==============================================================================
951 //==============================================================================
954 extern __at(0x0095) __sfr WPU
;
983 extern __at(0x0095) volatile __WPUbits_t WPUbits
;
996 //==============================================================================
999 //==============================================================================
1002 extern __at(0x0095) __sfr WPUA
;
1031 extern __at(0x0095) volatile __WPUAbits_t WPUAbits
;
1033 #define _WPUA_WPUA0 0x01
1034 #define _WPUA_WPU0 0x01
1035 #define _WPUA_WPUA1 0x02
1036 #define _WPUA_WPU1 0x02
1037 #define _WPUA_WPUA2 0x04
1038 #define _WPUA_WPU2 0x04
1039 #define _WPUA_WPUA4 0x10
1040 #define _WPUA_WPU4 0x10
1041 #define _WPUA_WPUA5 0x20
1042 #define _WPUA_WPU5 0x20
1044 //==============================================================================
1047 //==============================================================================
1050 extern __at(0x0096) __sfr IOC
;
1091 extern __at(0x0096) volatile __IOCbits_t IOCbits
;
1106 //==============================================================================
1109 //==============================================================================
1112 extern __at(0x0096) __sfr IOCA
;
1153 extern __at(0x0096) volatile __IOCAbits_t IOCAbits
;
1155 #define _IOCA_IOCA0 0x01
1156 #define _IOCA_IOC0 0x01
1157 #define _IOCA_IOCA1 0x02
1158 #define _IOCA_IOC1 0x02
1159 #define _IOCA_IOCA2 0x04
1160 #define _IOCA_IOC2 0x04
1161 #define _IOCA_IOCA3 0x08
1162 #define _IOCA_IOC3 0x08
1163 #define _IOCA_IOCA4 0x10
1164 #define _IOCA_IOC4 0x10
1165 #define _IOCA_IOCA5 0x20
1166 #define _IOCA_IOC5 0x20
1168 //==============================================================================
1170 extern __at(0x0097) __sfr EEDATH
;
1171 extern __at(0x0098) __sfr EEADRH
;
1173 //==============================================================================
1176 extern __at(0x0099) __sfr VRCON
;
1199 extern __at(0x0099) volatile __VRCONbits_t VRCONbits
;
1208 //==============================================================================
1210 extern __at(0x009A) __sfr EEDAT
;
1211 extern __at(0x009A) __sfr EEDATA
;
1212 extern __at(0x009B) __sfr EEADR
;
1214 //==============================================================================
1217 extern __at(0x009C) __sfr EECON1
;
1231 extern __at(0x009C) volatile __EECON1bits_t EECON1bits
;
1239 //==============================================================================
1241 extern __at(0x009D) __sfr EECON2
;
1242 extern __at(0x009E) __sfr ADRESL
;
1244 //==============================================================================
1247 extern __at(0x009F) __sfr ADCON1
;
1271 extern __at(0x009F) volatile __ADCON1bits_t ADCON1bits
;
1277 //==============================================================================
1280 //==============================================================================
1282 // Configuration Bits
1284 //==============================================================================
1286 #define _CONFIG 0x2007
1288 //----------------------------- CONFIG Options -------------------------------
1290 #define _FOSC_LP 0x3FF8 // LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1291 #define _LP_OSC 0x3FF8 // LP oscillator: Low-power crystal on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1292 #define _FOSC_XT 0x3FF9 // XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKINT.
1293 #define _XT_OSC 0x3FF9 // XT oscillator: Crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKINT.
1294 #define _FOSC_HS 0x3FFA // HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1295 #define _HS_OSC 0x3FFA // HS oscillator: High-speed crystal/resonator on RA4/OSC2/CLKOUT and RA5/OSC1/CLKIN.
1296 #define _FOSC_EC 0x3FFB // EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN.
1297 #define _EC_OSC 0x3FFB // EC: I/O function on RA4/OSC2/CLKOUT pin, CLKIN on RA5/OSC1/CLKIN.
1298 #define _FOSC_INTOSCIO 0x3FFC // INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1299 #define _INTOSCIO 0x3FFC // INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1300 #define _INTRC_OSC_NOCLKOUT 0x3FFC // INTOSCIO oscillator: I/O function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1301 #define _FOSC_INTOSCCLK 0x3FFD // INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1302 #define _INTOSC 0x3FFD // INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1303 #define _INTRC_OSC_CLKOUT 0x3FFD // INTOSC oscillator: CLKOUT function on RA4/OSC2/CLKOUT pin, I/O function on RA5/OSC1/CLKIN.
1304 #define _FOSC_EXTRCIO 0x3FFE // EXTRCIO oscillator: External RC on RA5/OSC1/CLKIN, I/O function on RA4/OSC2/CLKOUT pin.
1305 #define _EXTRCIO 0x3FFE // EXTRCIO oscillator: External RC on RA5/OSC1/CLKIN, I/O function on RA4/OSC2/CLKOUT pin.
1306 #define _EXTRC_OSC_NOCLKOUT 0x3FFE // EXTRCIO oscillator: External RC on RA5/OSC1/CLKIN, I/O function on RA4/OSC2/CLKOUT pin.
1307 #define _FOSC_EXTRCCLK 0x3FFF // EXTRC oscillator: External RC on RA5/OSC1/CLKIN, CLKOUT function on RA4/OSC2/CLKOUT pin.
1308 #define _EXTRC 0x3FFF // EXTRC oscillator: External RC on RA5/OSC1/CLKIN, CLKOUT function on RA4/OSC2/CLKOUT pin.
1309 #define _EXTRC_OSC_CLKOUT 0x3FFF // EXTRC oscillator: External RC on RA5/OSC1/CLKIN, CLKOUT function on RA4/OSC2/CLKOUT pin.
1310 #define _WDTE_OFF 0x3FF7 // WDT disabled.
1311 #define _WDT_OFF 0x3FF7 // WDT disabled.
1312 #define _WDTE_ON 0x3FFF // WDT enabled.
1313 #define _WDT_ON 0x3FFF // WDT enabled.
1314 #define _PWRTE_ON 0x3FEF // PWRT enabled.
1315 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
1316 #define _MCLRE_OFF 0x3FDF // MCLR pin function is digital input, MCLR internally tied to VDD.
1317 #define _MCLRE_ON 0x3FFF // MCLR pin function is MCLR.
1318 #define _CP_ON 0x3FBF // Program memory code protection is enabled.
1319 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
1320 #define _CPD_ON 0x3F7F // Data memory code protection is enabled.
1321 #define _CPD_OFF 0x3FFF // Data memory code protection is disabled.
1322 #define _BOREN_OFF 0x3CFF // BOR disabled.
1323 #define _BOD_OFF 0x3CFF // BOR disabled.
1324 #define _BOR_OFF 0x3CFF // BOR disabled.
1325 #define _BOREN_SBODEN 0x3DFF // BOR controlled by SBOREN bit of the PCON register.
1326 #define _BOD_SBODEN 0x3DFF // BOR controlled by SBOREN bit of the PCON register.
1327 #define _BOR_SBODEN 0x3DFF // BOR controlled by SBOREN bit of the PCON register.
1328 #define _BOREN_NSLEEP 0x3EFF // BOR enabled during operation and disabled in Sleep.
1329 #define _BOD_NSLEEP 0x3EFF // BOR enabled during operation and disabled in Sleep.
1330 #define _BOR_NSLEEP 0x3EFF // BOR enabled during operation and disabled in Sleep.
1331 #define _BOREN_ON 0x3FFF // BOR enabled.
1332 #define _BOD_ON 0x3FFF // BOR enabled.
1333 #define _BOR_ON 0x3FFF // BOR enabled.
1334 #define _IESO_OFF 0x3BFF // Internal External Switchover mode is disabled.
1335 #define _IESO_ON 0x3FFF // Internal External Switchover mode is enabled.
1336 #define _FCMEN_OFF 0x37FF // Fail-Safe Clock Monitor is disabled.
1337 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
1339 //==============================================================================
1341 #define _DEVID1 0x2006
1343 #define _IDLOC0 0x2000
1344 #define _IDLOC1 0x2001
1345 #define _IDLOC2 0x2002
1346 #define _IDLOC3 0x2003
1348 //==============================================================================
1350 #ifndef NO_BIT_DEFINES
1352 #define ADON ADCON0bits.ADON // bit 0
1353 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
1354 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
1355 #define NOT_DONE ADCON0bits.NOT_DONE // bit 1, shadows bit in ADCON0bits
1356 #define GO_DONE ADCON0bits.GO_DONE // bit 1, shadows bit in ADCON0bits
1357 #define CHS0 ADCON0bits.CHS0 // bit 2
1358 #define CHS1 ADCON0bits.CHS1 // bit 3
1359 #define CHS2 ADCON0bits.CHS2 // bit 4
1360 #define VCFG ADCON0bits.VCFG // bit 6
1361 #define ADFM ADCON0bits.ADFM // bit 7
1363 #define ADCS0 ADCON1bits.ADCS0 // bit 4
1364 #define ADCS1 ADCON1bits.ADCS1 // bit 5
1365 #define ADCS2 ADCON1bits.ADCS2 // bit 6
1367 #define ANS0 ANSELbits.ANS0 // bit 0
1368 #define ANS1 ANSELbits.ANS1 // bit 1
1369 #define ANS2 ANSELbits.ANS2 // bit 2
1370 #define ANS3 ANSELbits.ANS3 // bit 3
1371 #define ANS4 ANSELbits.ANS4 // bit 4
1372 #define ANS5 ANSELbits.ANS5 // bit 5
1373 #define ANS6 ANSELbits.ANS6 // bit 6
1374 #define ANS7 ANSELbits.ANS7 // bit 7
1376 #define ABDEN BAUDCTLbits.ABDEN // bit 0
1377 #define WUE BAUDCTLbits.WUE // bit 1
1378 #define BRG16 BAUDCTLbits.BRG16 // bit 3
1379 #define SCKP BAUDCTLbits.SCKP // bit 4
1380 #define RCIDL BAUDCTLbits.RCIDL // bit 6
1381 #define ABDOVF BAUDCTLbits.ABDOVF // bit 7
1383 #define CM0 CMCON0bits.CM0 // bit 0
1384 #define CM1 CMCON0bits.CM1 // bit 1
1385 #define CM2 CMCON0bits.CM2 // bit 2
1386 #define CIS CMCON0bits.CIS // bit 3
1387 #define C1INV CMCON0bits.C1INV // bit 4
1388 #define C2INV CMCON0bits.C2INV // bit 5
1389 #define C1OUT CMCON0bits.C1OUT // bit 6
1390 #define C2OUT CMCON0bits.C2OUT // bit 7
1392 #define C2SYNC CMCON1bits.C2SYNC // bit 0
1393 #define T1GSS CMCON1bits.T1GSS // bit 1
1395 #define RD EECON1bits.RD // bit 0
1396 #define WR EECON1bits.WR // bit 1
1397 #define WREN EECON1bits.WREN // bit 2
1398 #define WRERR EECON1bits.WRERR // bit 3
1399 #define EEPGD EECON1bits.EEPGD // bit 7
1401 #define RAIF INTCONbits.RAIF // bit 0
1402 #define INTF INTCONbits.INTF // bit 1
1403 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
1404 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
1405 #define RAIE INTCONbits.RAIE // bit 3
1406 #define INTE INTCONbits.INTE // bit 4
1407 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
1408 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
1409 #define PEIE INTCONbits.PEIE // bit 6
1410 #define GIE INTCONbits.GIE // bit 7
1412 #define IOCA0 IOCbits.IOCA0 // bit 0, shadows bit in IOCbits
1413 #define IOC0 IOCbits.IOC0 // bit 0, shadows bit in IOCbits
1414 #define IOCA1 IOCbits.IOCA1 // bit 1, shadows bit in IOCbits
1415 #define IOC1 IOCbits.IOC1 // bit 1, shadows bit in IOCbits
1416 #define IOCA2 IOCbits.IOCA2 // bit 2, shadows bit in IOCbits
1417 #define IOC2 IOCbits.IOC2 // bit 2, shadows bit in IOCbits
1418 #define IOCA3 IOCbits.IOCA3 // bit 3, shadows bit in IOCbits
1419 #define IOC3 IOCbits.IOC3 // bit 3, shadows bit in IOCbits
1420 #define IOCA4 IOCbits.IOCA4 // bit 4, shadows bit in IOCbits
1421 #define IOC4 IOCbits.IOC4 // bit 4, shadows bit in IOCbits
1422 #define IOCA5 IOCbits.IOCA5 // bit 5, shadows bit in IOCbits
1423 #define IOC5 IOCbits.IOC5 // bit 5, shadows bit in IOCbits
1425 #define PS0 OPTION_REGbits.PS0 // bit 0
1426 #define PS1 OPTION_REGbits.PS1 // bit 1
1427 #define PS2 OPTION_REGbits.PS2 // bit 2
1428 #define PSA OPTION_REGbits.PSA // bit 3
1429 #define T0SE OPTION_REGbits.T0SE // bit 4
1430 #define T0CS OPTION_REGbits.T0CS // bit 5
1431 #define INTEDG OPTION_REGbits.INTEDG // bit 6
1432 #define NOT_RAPU OPTION_REGbits.NOT_RAPU // bit 7
1434 #define SCS OSCCONbits.SCS // bit 0
1435 #define LTS OSCCONbits.LTS // bit 1
1436 #define HTS OSCCONbits.HTS // bit 2
1437 #define OSTS OSCCONbits.OSTS // bit 3
1438 #define IRCF0 OSCCONbits.IRCF0 // bit 4
1439 #define IRCF1 OSCCONbits.IRCF1 // bit 5
1440 #define IRCF2 OSCCONbits.IRCF2 // bit 6
1442 #define TUN0 OSCTUNEbits.TUN0 // bit 0
1443 #define TUN1 OSCTUNEbits.TUN1 // bit 1
1444 #define TUN2 OSCTUNEbits.TUN2 // bit 2
1445 #define TUN3 OSCTUNEbits.TUN3 // bit 3
1446 #define TUN4 OSCTUNEbits.TUN4 // bit 4
1448 #define NOT_BOR PCONbits.NOT_BOR // bit 0, shadows bit in PCONbits
1449 #define NOT_BOD PCONbits.NOT_BOD // bit 0, shadows bit in PCONbits
1450 #define NOT_POR PCONbits.NOT_POR // bit 1
1451 #define SBODEN PCONbits.SBODEN // bit 4
1452 #define ULPWUE PCONbits.ULPWUE // bit 5
1454 #define TMR1IE PIE1bits.TMR1IE // bit 0, shadows bit in PIE1bits
1455 #define T1IE PIE1bits.T1IE // bit 0, shadows bit in PIE1bits
1456 #define TXIE PIE1bits.TXIE // bit 1
1457 #define OSFIE PIE1bits.OSFIE // bit 2
1458 #define C1IE PIE1bits.C1IE // bit 3
1459 #define C2IE PIE1bits.C2IE // bit 4
1460 #define RCIE PIE1bits.RCIE // bit 5
1461 #define ADIE PIE1bits.ADIE // bit 6
1462 #define EEIE PIE1bits.EEIE // bit 7
1464 #define TMR1IF PIR1bits.TMR1IF // bit 0, shadows bit in PIR1bits
1465 #define T1IF PIR1bits.T1IF // bit 0, shadows bit in PIR1bits
1466 #define TXIF PIR1bits.TXIF // bit 1
1467 #define OSFIF PIR1bits.OSFIF // bit 2
1468 #define C1IF PIR1bits.C1IF // bit 3
1469 #define C2IF PIR1bits.C2IF // bit 4
1470 #define RCIF PIR1bits.RCIF // bit 5
1471 #define ADIF PIR1bits.ADIF // bit 6
1472 #define EEIF PIR1bits.EEIF // bit 7
1474 #define RA0 PORTAbits.RA0 // bit 0
1475 #define RA1 PORTAbits.RA1 // bit 1
1476 #define RA2 PORTAbits.RA2 // bit 2
1477 #define RA3 PORTAbits.RA3 // bit 3
1478 #define RA4 PORTAbits.RA4 // bit 4
1479 #define RA5 PORTAbits.RA5 // bit 5
1481 #define RC0 PORTCbits.RC0 // bit 0
1482 #define RC1 PORTCbits.RC1 // bit 1
1483 #define RC2 PORTCbits.RC2 // bit 2
1484 #define RC3 PORTCbits.RC3 // bit 3
1485 #define RC4 PORTCbits.RC4 // bit 4
1486 #define RC5 PORTCbits.RC5 // bit 5
1488 #define RX9D RCSTAbits.RX9D // bit 0
1489 #define OERR RCSTAbits.OERR // bit 1
1490 #define FERR RCSTAbits.FERR // bit 2
1491 #define ADDEN RCSTAbits.ADDEN // bit 3
1492 #define CREN RCSTAbits.CREN // bit 4
1493 #define SREN RCSTAbits.SREN // bit 5
1494 #define RX9 RCSTAbits.RX9 // bit 6
1495 #define SPEN RCSTAbits.SPEN // bit 7
1497 #define C STATUSbits.C // bit 0
1498 #define DC STATUSbits.DC // bit 1
1499 #define Z STATUSbits.Z // bit 2
1500 #define NOT_PD STATUSbits.NOT_PD // bit 3
1501 #define NOT_TO STATUSbits.NOT_TO // bit 4
1502 #define RP0 STATUSbits.RP0 // bit 5
1503 #define RP1 STATUSbits.RP1 // bit 6
1504 #define IRP STATUSbits.IRP // bit 7
1506 #define TMR1ON T1CONbits.TMR1ON // bit 0
1507 #define TMR1CS T1CONbits.TMR1CS // bit 1
1508 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
1509 #define T1OSCEN T1CONbits.T1OSCEN // bit 3
1510 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
1511 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
1512 #define TMR1GE T1CONbits.TMR1GE // bit 6
1513 #define T1GINV T1CONbits.T1GINV // bit 7
1515 #define TRISA0 TRISAbits.TRISA0 // bit 0
1516 #define TRISA1 TRISAbits.TRISA1 // bit 1
1517 #define TRISA2 TRISAbits.TRISA2 // bit 2
1518 #define TRISA3 TRISAbits.TRISA3 // bit 3
1519 #define TRISA4 TRISAbits.TRISA4 // bit 4
1520 #define TRISA5 TRISAbits.TRISA5 // bit 5
1522 #define TRISC0 TRISCbits.TRISC0 // bit 0
1523 #define TRISC1 TRISCbits.TRISC1 // bit 1
1524 #define TRISC2 TRISCbits.TRISC2 // bit 2
1525 #define TRISC3 TRISCbits.TRISC3 // bit 3
1526 #define TRISC4 TRISCbits.TRISC4 // bit 4
1527 #define TRISC5 TRISCbits.TRISC5 // bit 5
1529 #define TX9D TXSTAbits.TX9D // bit 0
1530 #define TRMT TXSTAbits.TRMT // bit 1
1531 #define BRGH TXSTAbits.BRGH // bit 2
1532 #define SENDB TXSTAbits.SENDB // bit 3
1533 #define SYNC TXSTAbits.SYNC // bit 4
1534 #define TXEN TXSTAbits.TXEN // bit 5
1535 #define TX9 TXSTAbits.TX9 // bit 6
1536 #define CSRC TXSTAbits.CSRC // bit 7
1538 #define VR0 VRCONbits.VR0 // bit 0
1539 #define VR1 VRCONbits.VR1 // bit 1
1540 #define VR2 VRCONbits.VR2 // bit 2
1541 #define VR3 VRCONbits.VR3 // bit 3
1542 #define VRR VRCONbits.VRR // bit 5
1543 #define VREN VRCONbits.VREN // bit 7
1545 #define SWDTEN WDTCONbits.SWDTEN // bit 0
1546 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
1547 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
1548 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
1549 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
1551 #define WPUA0 WPUbits.WPUA0 // bit 0, shadows bit in WPUbits
1552 #define WPU0 WPUbits.WPU0 // bit 0, shadows bit in WPUbits
1553 #define WPUA1 WPUbits.WPUA1 // bit 1, shadows bit in WPUbits
1554 #define WPU1 WPUbits.WPU1 // bit 1, shadows bit in WPUbits
1555 #define WPUA2 WPUbits.WPUA2 // bit 2, shadows bit in WPUbits
1556 #define WPU2 WPUbits.WPU2 // bit 2, shadows bit in WPUbits
1557 #define WPUA4 WPUbits.WPUA4 // bit 4, shadows bit in WPUbits
1558 #define WPU4 WPUbits.WPU4 // bit 4, shadows bit in WPUbits
1559 #define WPUA5 WPUbits.WPUA5 // bit 5, shadows bit in WPUbits
1560 #define WPU5 WPUbits.WPU5 // bit 5, shadows bit in WPUbits
1562 #endif // #ifndef NO_BIT_DEFINES
1564 #endif // #ifndef __PIC16F688_H__