2 * This declarations of the PIC16F753 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:22:59 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F753_H__
26 #define __PIC16F753_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF_ADDR 0x0000
37 #define TMR0_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR_ADDR 0x0004
41 #define PORTA_ADDR 0x0005
42 #define PORTC_ADDR 0x0007
43 #define IOCAF_ADDR 0x0008
44 #define IOCCF_ADDR 0x0009
45 #define PCLATH_ADDR 0x000A
46 #define INTCON_ADDR 0x000B
47 #define PIR1_ADDR 0x000C
48 #define PIR2_ADDR 0x000D
49 #define TMR1_ADDR 0x000F
50 #define TMR1L_ADDR 0x000F
51 #define TMR1H_ADDR 0x0010
52 #define T1CON_ADDR 0x0011
53 #define T1GCON_ADDR 0x0012
54 #define CCPR1_ADDR 0x0013
55 #define CCPR1L_ADDR 0x0013
56 #define CCPR1H_ADDR 0x0014
57 #define CCP1CON_ADDR 0x0015
58 #define ADRES_ADDR 0x001C
59 #define ADRESL_ADDR 0x001C
60 #define ADRESH_ADDR 0x001D
61 #define ADCON0_ADDR 0x001E
62 #define ADCON1_ADDR 0x001F
63 #define OPTION_REG_ADDR 0x0081
64 #define TRISA_ADDR 0x0085
65 #define TRISC_ADDR 0x0087
66 #define IOCAP_ADDR 0x0088
67 #define IOCCP_ADDR 0x0089
68 #define PIE1_ADDR 0x008C
69 #define PIE2_ADDR 0x008D
70 #define OSCCON_ADDR 0x008F
71 #define FVR1CON0_ADDR 0x0090
72 #define DAC1CON0_ADDR 0x0091
73 #define DAC1REFL_ADDR 0x0092
74 #define DAC1REFH_ADDR 0x0093
75 #define OPA1CON_ADDR 0x0096
76 #define OPA1CON0_ADDR 0x0096
77 #define C2CON0_ADDR 0x009B
78 #define CM2CON0_ADDR 0x009B
79 #define C2CON1_ADDR 0x009C
80 #define CM2CON1_ADDR 0x009C
81 #define C1CON0_ADDR 0x009D
82 #define CM1CON0_ADDR 0x009D
83 #define C1CON1_ADDR 0x009E
84 #define CM1CON1_ADDR 0x009E
85 #define CMOUT_ADDR 0x009F
86 #define MCOUT_ADDR 0x009F
87 #define LATA_ADDR 0x0105
88 #define LATC_ADDR 0x0107
89 #define IOCAN_ADDR 0x0108
90 #define IOCCN_ADDR 0x0109
91 #define WPUA_ADDR 0x010C
92 #define WPUC_ADDR 0x010D
93 #define SLRCONC_ADDR 0x010E
94 #define PCON_ADDR 0x010F
95 #define TMR2_ADDR 0x0110
96 #define PR2_ADDR 0x0111
97 #define T2CON_ADDR 0x0112
98 #define HLTMR1_ADDR 0x0113
99 #define HLTPR1_ADDR 0x0114
100 #define HLT1CON0_ADDR 0x0115
101 #define HLT1CON1_ADDR 0x0116
102 #define HLTMR2_ADDR 0x0117
103 #define HLTPR2_ADDR 0x0118
104 #define HLT2CON0_ADDR 0x0119
105 #define HLT2CON1_ADDR 0x011A
106 #define SLPC1CON0_ADDR 0x011E
107 #define SLPCCON0_ADDR 0x011E
108 #define SLPC1CON1_ADDR 0x011F
109 #define SLPCCON1_ADDR 0x011F
110 #define ANSELA_ADDR 0x0185
111 #define ANSELC_ADDR 0x0187
112 #define APFCON_ADDR 0x0188
113 #define OSCTUNE_ADDR 0x0189
114 #define PMCON1_ADDR 0x018C
115 #define PMCON2_ADDR 0x018D
116 #define PMADR_ADDR 0x018E
117 #define PMADRL_ADDR 0x018E
118 #define PMADRH_ADDR 0x018F
119 #define PMDAT_ADDR 0x0190
120 #define PMDATL_ADDR 0x0190
121 #define PMDATH_ADDR 0x0191
122 #define COG1PHR_ADDR 0x0192
123 #define COG1PHF_ADDR 0x0193
124 #define COG1BKR_ADDR 0x0194
125 #define COG1BKF_ADDR 0x0195
126 #define COG1DBR_ADDR 0x0196
127 #define COG1DBF_ADDR 0x0197
128 #define COG1CON0_ADDR 0x0198
129 #define COG1CON1_ADDR 0x0199
130 #define COG1RIS_ADDR 0x019A
131 #define COG1RSIM_ADDR 0x019B
132 #define COG1FIS_ADDR 0x019C
133 #define COG1FSIM_ADDR 0x019D
134 #define COG1ASD0_ADDR 0x019E
135 #define COG1ASD1_ADDR 0x019F
137 #endif // #ifndef NO_ADDR_DEFINES
139 //==============================================================================
141 // Register Definitions
143 //==============================================================================
145 extern __at(0x0000) __sfr INDF
;
146 extern __at(0x0001) __sfr TMR0
;
147 extern __at(0x0002) __sfr PCL
;
149 //==============================================================================
152 extern __at(0x0003) __sfr STATUS
;
176 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
187 //==============================================================================
189 extern __at(0x0004) __sfr FSR
;
191 //==============================================================================
194 extern __at(0x0005) __sfr PORTA
;
217 extern __at(0x0005) volatile __PORTAbits_t PORTAbits
;
226 //==============================================================================
229 //==============================================================================
232 extern __at(0x0007) __sfr PORTC
;
255 extern __at(0x0007) volatile __PORTCbits_t PORTCbits
;
264 //==============================================================================
267 //==============================================================================
270 extern __at(0x0008) __sfr IOCAF
;
293 extern __at(0x0008) volatile __IOCAFbits_t IOCAFbits
;
302 //==============================================================================
305 //==============================================================================
308 extern __at(0x0009) __sfr IOCCF
;
331 extern __at(0x0009) volatile __IOCCFbits_t IOCCFbits
;
340 //==============================================================================
342 extern __at(0x000A) __sfr PCLATH
;
344 //==============================================================================
347 extern __at(0x000B) __sfr INTCON
;
361 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
372 //==============================================================================
375 //==============================================================================
378 extern __at(0x000C) __sfr PIR1
;
384 unsigned HLTMR1IF
: 1;
385 unsigned HLTMR2IF
: 1;
389 unsigned TMR1GIF
: 1;
392 extern __at(0x000C) volatile __PIR1bits_t PIR1bits
;
396 #define _HLTMR1IF 0x04
397 #define _HLTMR2IF 0x08
399 #define _TMR1GIF 0x80
401 //==============================================================================
404 //==============================================================================
407 extern __at(0x000D) __sfr PIR2
;
421 extern __at(0x000D) volatile __PIR2bits_t PIR2bits
;
428 //==============================================================================
430 extern __at(0x000F) __sfr TMR1
;
431 extern __at(0x000F) __sfr TMR1L
;
432 extern __at(0x0010) __sfr TMR1H
;
434 //==============================================================================
437 extern __at(0x0011) __sfr T1CON
;
445 unsigned NOT_T1SYNC
: 1;
447 unsigned T1CKPS0
: 1;
448 unsigned T1CKPS1
: 1;
449 unsigned TMR1CS0
: 1;
450 unsigned TMR1CS1
: 1;
467 extern __at(0x0011) volatile __T1CONbits_t T1CONbits
;
470 #define _NOT_T1SYNC 0x04
471 #define _T1CKPS0 0x10
472 #define _T1CKPS1 0x20
473 #define _TMR1CS0 0x40
474 #define _TMR1CS1 0x80
476 //==============================================================================
479 //==============================================================================
482 extern __at(0x0012) __sfr T1GCON
;
491 unsigned T1GGO_NOT_DONE
: 1;
517 extern __at(0x0012) volatile __T1GCONbits_t T1GCONbits
;
522 #define _T1GGO_NOT_DONE 0x08
529 //==============================================================================
531 extern __at(0x0013) __sfr CCPR1
;
532 extern __at(0x0013) __sfr CCPR1L
;
533 extern __at(0x0014) __sfr CCPR1H
;
535 //==============================================================================
538 extern __at(0x0015) __sfr CCP1CON
;
568 extern __at(0x0015) volatile __CCP1CONbits_t CCP1CONbits
;
577 //==============================================================================
579 extern __at(0x001C) __sfr ADRES
;
580 extern __at(0x001C) __sfr ADRESL
;
581 extern __at(0x001D) __sfr ADRESH
;
583 //==============================================================================
586 extern __at(0x001E) __sfr ADCON0
;
593 unsigned GO_NOT_DONE
: 1;
610 extern __at(0x001E) volatile __ADCON0bits_t ADCON0bits
;
613 #define _GO_NOT_DONE 0x02
620 //==============================================================================
623 //==============================================================================
626 extern __at(0x001F) __sfr ADCON1
;
632 unsigned ADPREF1
: 1;
650 extern __at(0x001F) volatile __ADCON1bits_t ADCON1bits
;
652 #define _ADPREF1 0x01
657 //==============================================================================
660 //==============================================================================
663 extern __at(0x0081) __sfr OPTION_REG
;
676 unsigned NOT_RAPU
: 1;
684 } __OPTION_REGbits_t
;
686 extern __at(0x0081) volatile __OPTION_REGbits_t OPTION_REGbits
;
695 #define _NOT_RAPU 0x80
697 //==============================================================================
700 //==============================================================================
703 extern __at(0x0085) __sfr TRISA
;
726 extern __at(0x0085) volatile __TRISAbits_t TRISAbits
;
735 //==============================================================================
738 //==============================================================================
741 extern __at(0x0087) __sfr TRISC
;
764 extern __at(0x0087) volatile __TRISCbits_t TRISCbits
;
773 //==============================================================================
776 //==============================================================================
779 extern __at(0x0088) __sfr IOCAP
;
802 extern __at(0x0088) volatile __IOCAPbits_t IOCAPbits
;
811 //==============================================================================
814 //==============================================================================
817 extern __at(0x0089) __sfr IOCCP
;
840 extern __at(0x0089) volatile __IOCCPbits_t IOCCPbits
;
849 //==============================================================================
852 //==============================================================================
855 extern __at(0x008C) __sfr PIE1
;
861 unsigned HLTMR1IE
: 1;
862 unsigned HLTMR2IE
: 1;
866 unsigned TMR1GIE
: 1;
869 extern __at(0x008C) volatile __PIE1bits_t PIE1bits
;
873 #define _HLTMR1IE 0x04
874 #define _HLTMR2IE 0x08
876 #define _TMR1GIE 0x80
878 //==============================================================================
881 //==============================================================================
884 extern __at(0x008D) __sfr PIE2
;
898 extern __at(0x008D) volatile __PIE2bits_t PIE2bits
;
905 //==============================================================================
908 //==============================================================================
911 extern __at(0x008F) __sfr OSCCON
;
935 extern __at(0x008F) volatile __OSCCONbits_t OSCCONbits
;
942 //==============================================================================
945 //==============================================================================
948 extern __at(0x0090) __sfr FVR1CON0
;
954 unsigned FVRBUFEN
: 1;
957 unsigned FVRBUSS0
: 1;
958 unsigned FVRBUSS1
: 1;
967 unsigned FVRBUSS
: 2;
972 extern __at(0x0090) volatile __FVR1CON0bits_t FVR1CON0bits
;
974 #define _FVRBUFEN 0x01
975 #define _FVRBUSS0 0x08
976 #define _FVRBUSS1 0x10
981 //==============================================================================
984 //==============================================================================
987 extern __at(0x0091) __sfr DAC1CON0
;
995 unsigned DACPSS0
: 1;
996 unsigned DACPSS1
: 1;
1006 unsigned DACPSS
: 2;
1011 extern __at(0x0091) volatile __DAC1CON0bits_t DAC1CON0bits
;
1013 #define _DACPSS0 0x04
1014 #define _DACPSS1 0x08
1019 //==============================================================================
1021 extern __at(0x0092) __sfr DAC1REFL
;
1022 extern __at(0x0093) __sfr DAC1REFH
;
1024 //==============================================================================
1027 extern __at(0x0096) __sfr OPA1CON
;
1033 unsigned OPA1PCH0
: 1;
1034 unsigned OPA1PCH1
: 1;
1035 unsigned OPA1NCH0
: 1;
1036 unsigned OPA1NCH1
: 1;
1037 unsigned OPAUGM
: 1;
1045 unsigned OPA1PCH
: 2;
1052 unsigned OPA1NCH
: 2;
1057 extern __at(0x0096) volatile __OPA1CONbits_t OPA1CONbits
;
1059 #define _OPA1PCH0 0x01
1060 #define _OPA1PCH1 0x02
1061 #define _OPA1NCH0 0x04
1062 #define _OPA1NCH1 0x08
1063 #define _OPAUGM 0x10
1066 //==============================================================================
1069 //==============================================================================
1072 extern __at(0x0096) __sfr OPA1CON0
;
1078 unsigned OPA1PCH0
: 1;
1079 unsigned OPA1PCH1
: 1;
1080 unsigned OPA1NCH0
: 1;
1081 unsigned OPA1NCH1
: 1;
1082 unsigned OPAUGM
: 1;
1090 unsigned OPA1PCH
: 2;
1097 unsigned OPA1NCH
: 2;
1102 extern __at(0x0096) volatile __OPA1CON0bits_t OPA1CON0bits
;
1104 #define _OPA1CON0_OPA1PCH0 0x01
1105 #define _OPA1CON0_OPA1PCH1 0x02
1106 #define _OPA1CON0_OPA1NCH0 0x04
1107 #define _OPA1CON0_OPA1NCH1 0x08
1108 #define _OPA1CON0_OPAUGM 0x10
1109 #define _OPA1CON0_OPAEN 0x80
1111 //==============================================================================
1114 //==============================================================================
1117 extern __at(0x009B) __sfr C2CON0
;
1121 unsigned C2SYNC
: 1;
1131 extern __at(0x009B) volatile __C2CON0bits_t C2CON0bits
;
1133 #define _C2SYNC 0x01
1142 //==============================================================================
1145 //==============================================================================
1148 extern __at(0x009B) __sfr CM2CON0
;
1152 unsigned C2SYNC
: 1;
1162 extern __at(0x009B) volatile __CM2CON0bits_t CM2CON0bits
;
1164 #define _CM2CON0_C2SYNC 0x01
1165 #define _CM2CON0_C2HYS 0x02
1166 #define _CM2CON0_C2SP 0x04
1167 #define _CM2CON0_C2ZLF 0x08
1168 #define _CM2CON0_C2POL 0x10
1169 #define _CM2CON0_C2OE 0x20
1170 #define _CM2CON0_C2OUT 0x40
1171 #define _CM2CON0_C2ON 0x80
1173 //==============================================================================
1176 //==============================================================================
1179 extern __at(0x009C) __sfr C2CON1
;
1185 unsigned C2NCH0
: 1;
1186 unsigned C2NCH1
: 1;
1187 unsigned C2NCH2
: 1;
1188 unsigned C2PCH0
: 1;
1189 unsigned C2PCH1
: 1;
1190 unsigned C2PCH2
: 1;
1191 unsigned C2INTN
: 1;
1192 unsigned C2INTP
: 1;
1209 extern __at(0x009C) volatile __C2CON1bits_t C2CON1bits
;
1211 #define _C2NCH0 0x01
1212 #define _C2NCH1 0x02
1213 #define _C2NCH2 0x04
1214 #define _C2PCH0 0x08
1215 #define _C2PCH1 0x10
1216 #define _C2PCH2 0x20
1217 #define _C2INTN 0x40
1218 #define _C2INTP 0x80
1220 //==============================================================================
1223 //==============================================================================
1226 extern __at(0x009C) __sfr CM2CON1
;
1232 unsigned C2NCH0
: 1;
1233 unsigned C2NCH1
: 1;
1234 unsigned C2NCH2
: 1;
1235 unsigned C2PCH0
: 1;
1236 unsigned C2PCH1
: 1;
1237 unsigned C2PCH2
: 1;
1238 unsigned C2INTN
: 1;
1239 unsigned C2INTP
: 1;
1256 extern __at(0x009C) volatile __CM2CON1bits_t CM2CON1bits
;
1258 #define _CM2CON1_C2NCH0 0x01
1259 #define _CM2CON1_C2NCH1 0x02
1260 #define _CM2CON1_C2NCH2 0x04
1261 #define _CM2CON1_C2PCH0 0x08
1262 #define _CM2CON1_C2PCH1 0x10
1263 #define _CM2CON1_C2PCH2 0x20
1264 #define _CM2CON1_C2INTN 0x40
1265 #define _CM2CON1_C2INTP 0x80
1267 //==============================================================================
1270 //==============================================================================
1273 extern __at(0x009D) __sfr C1CON0
;
1277 unsigned C1SYNC
: 1;
1287 extern __at(0x009D) volatile __C1CON0bits_t C1CON0bits
;
1289 #define _C1SYNC 0x01
1298 //==============================================================================
1301 //==============================================================================
1304 extern __at(0x009D) __sfr CM1CON0
;
1308 unsigned C1SYNC
: 1;
1318 extern __at(0x009D) volatile __CM1CON0bits_t CM1CON0bits
;
1320 #define _CM1CON0_C1SYNC 0x01
1321 #define _CM1CON0_C1HYS 0x02
1322 #define _CM1CON0_C1SP 0x04
1323 #define _CM1CON0_C1ZLF 0x08
1324 #define _CM1CON0_C1POL 0x10
1325 #define _CM1CON0_C1OE 0x20
1326 #define _CM1CON0_C1OUT 0x40
1327 #define _CM1CON0_C1ON 0x80
1329 //==============================================================================
1332 //==============================================================================
1335 extern __at(0x009E) __sfr C1CON1
;
1341 unsigned C1NCH0
: 1;
1342 unsigned C1NCH1
: 1;
1343 unsigned C1NCH2
: 1;
1344 unsigned C1PCH0
: 1;
1345 unsigned C1PCH1
: 1;
1346 unsigned C1PCH2
: 1;
1347 unsigned C1INTN
: 1;
1348 unsigned C1INTP
: 1;
1365 extern __at(0x009E) volatile __C1CON1bits_t C1CON1bits
;
1367 #define _C1NCH0 0x01
1368 #define _C1NCH1 0x02
1369 #define _C1NCH2 0x04
1370 #define _C1PCH0 0x08
1371 #define _C1PCH1 0x10
1372 #define _C1PCH2 0x20
1373 #define _C1INTN 0x40
1374 #define _C1INTP 0x80
1376 //==============================================================================
1379 //==============================================================================
1382 extern __at(0x009E) __sfr CM1CON1
;
1388 unsigned C1NCH0
: 1;
1389 unsigned C1NCH1
: 1;
1390 unsigned C1NCH2
: 1;
1391 unsigned C1PCH0
: 1;
1392 unsigned C1PCH1
: 1;
1393 unsigned C1PCH2
: 1;
1394 unsigned C1INTN
: 1;
1395 unsigned C1INTP
: 1;
1412 extern __at(0x009E) volatile __CM1CON1bits_t CM1CON1bits
;
1414 #define _CM1CON1_C1NCH0 0x01
1415 #define _CM1CON1_C1NCH1 0x02
1416 #define _CM1CON1_C1NCH2 0x04
1417 #define _CM1CON1_C1PCH0 0x08
1418 #define _CM1CON1_C1PCH1 0x10
1419 #define _CM1CON1_C1PCH2 0x20
1420 #define _CM1CON1_C1INTN 0x40
1421 #define _CM1CON1_C1INTP 0x80
1423 //==============================================================================
1426 //==============================================================================
1429 extern __at(0x009F) __sfr CMOUT
;
1433 unsigned MCOUT1
: 1;
1434 unsigned MCOUT2
: 1;
1443 extern __at(0x009F) volatile __CMOUTbits_t CMOUTbits
;
1445 #define _MCOUT1 0x01
1446 #define _MCOUT2 0x02
1448 //==============================================================================
1451 //==============================================================================
1454 extern __at(0x009F) __sfr MCOUT
;
1458 unsigned MCOUT1
: 1;
1459 unsigned MCOUT2
: 1;
1468 extern __at(0x009F) volatile __MCOUTbits_t MCOUTbits
;
1470 #define _MCOUT_MCOUT1 0x01
1471 #define _MCOUT_MCOUT2 0x02
1473 //==============================================================================
1476 //==============================================================================
1479 extern __at(0x0105) __sfr LATA
;
1493 extern __at(0x0105) volatile __LATAbits_t LATAbits
;
1501 //==============================================================================
1504 //==============================================================================
1507 extern __at(0x0107) __sfr LATC
;
1530 extern __at(0x0107) volatile __LATCbits_t LATCbits
;
1539 //==============================================================================
1542 //==============================================================================
1545 extern __at(0x0108) __sfr IOCAN
;
1551 unsigned IOCAN0
: 1;
1552 unsigned IOCAN1
: 1;
1553 unsigned IOCAN2
: 1;
1554 unsigned IOCAN3
: 1;
1555 unsigned IOCAN4
: 1;
1556 unsigned IOCAN5
: 1;
1568 extern __at(0x0108) volatile __IOCANbits_t IOCANbits
;
1570 #define _IOCAN0 0x01
1571 #define _IOCAN1 0x02
1572 #define _IOCAN2 0x04
1573 #define _IOCAN3 0x08
1574 #define _IOCAN4 0x10
1575 #define _IOCAN5 0x20
1577 //==============================================================================
1580 //==============================================================================
1583 extern __at(0x0109) __sfr IOCCN
;
1589 unsigned IOCCN0
: 1;
1590 unsigned IOCCN1
: 1;
1591 unsigned IOCCN2
: 1;
1592 unsigned IOCCN3
: 1;
1593 unsigned IOCCN4
: 1;
1594 unsigned IOCCN5
: 1;
1606 extern __at(0x0109) volatile __IOCCNbits_t IOCCNbits
;
1608 #define _IOCCN0 0x01
1609 #define _IOCCN1 0x02
1610 #define _IOCCN2 0x04
1611 #define _IOCCN3 0x08
1612 #define _IOCCN4 0x10
1613 #define _IOCCN5 0x20
1615 //==============================================================================
1618 //==============================================================================
1621 extern __at(0x010C) __sfr WPUA
;
1644 extern __at(0x010C) volatile __WPUAbits_t WPUAbits
;
1653 //==============================================================================
1656 //==============================================================================
1659 extern __at(0x010D) __sfr WPUC
;
1682 extern __at(0x010D) volatile __WPUCbits_t WPUCbits
;
1691 //==============================================================================
1694 //==============================================================================
1697 extern __at(0x010E) __sfr SLRCONC
;
1711 extern __at(0x010E) volatile __SLRCONCbits_t SLRCONCbits
;
1716 //==============================================================================
1719 //==============================================================================
1722 extern __at(0x010F) __sfr PCON
;
1726 unsigned NOT_BOR
: 1;
1727 unsigned NOT_POR
: 1;
1736 extern __at(0x010F) volatile __PCONbits_t PCONbits
;
1738 #define _NOT_BOR 0x01
1739 #define _NOT_POR 0x02
1741 //==============================================================================
1743 extern __at(0x0110) __sfr TMR2
;
1744 extern __at(0x0111) __sfr PR2
;
1746 //==============================================================================
1749 extern __at(0x0112) __sfr T2CON
;
1755 unsigned T2CKPS0
: 1;
1756 unsigned T2CKPS1
: 1;
1757 unsigned TMR2ON
: 1;
1758 unsigned T2OUTPS0
: 1;
1759 unsigned T2OUTPS1
: 1;
1760 unsigned T2OUTPS2
: 1;
1761 unsigned T2OUTPS3
: 1;
1767 unsigned T2CKPS
: 2;
1774 unsigned T2OUTPS
: 4;
1779 extern __at(0x0112) volatile __T2CONbits_t T2CONbits
;
1781 #define _T2CKPS0 0x01
1782 #define _T2CKPS1 0x02
1783 #define _TMR2ON 0x04
1784 #define _T2OUTPS0 0x08
1785 #define _T2OUTPS1 0x10
1786 #define _T2OUTPS2 0x20
1787 #define _T2OUTPS3 0x40
1789 //==============================================================================
1791 extern __at(0x0113) __sfr HLTMR1
;
1792 extern __at(0x0114) __sfr HLTPR1
;
1794 //==============================================================================
1797 extern __at(0x0115) __sfr HLT1CON0
;
1803 unsigned H1CKPS0
: 1;
1804 unsigned H1CKPS1
: 1;
1806 unsigned H1OUTPS0
: 1;
1807 unsigned H1OUTPS1
: 1;
1808 unsigned H1OUTPS2
: 1;
1809 unsigned H1OUTPS3
: 1;
1815 unsigned H1CKPS
: 2;
1822 unsigned H1OUTPS
: 4;
1827 extern __at(0x0115) volatile __HLT1CON0bits_t HLT1CON0bits
;
1829 #define _H1CKPS0 0x01
1830 #define _H1CKPS1 0x02
1832 #define _H1OUTPS0 0x08
1833 #define _H1OUTPS1 0x10
1834 #define _H1OUTPS2 0x20
1835 #define _H1OUTPS3 0x40
1837 //==============================================================================
1840 //==============================================================================
1843 extern __at(0x0116) __sfr HLT1CON1
;
1849 unsigned H1REREN
: 1;
1850 unsigned H1FEREN
: 1;
1851 unsigned H1ERS0
: 1;
1852 unsigned H1ERS1
: 1;
1853 unsigned H1ERS2
: 1;
1867 extern __at(0x0116) volatile __HLT1CON1bits_t HLT1CON1bits
;
1869 #define _H1REREN 0x01
1870 #define _H1FEREN 0x02
1871 #define _H1ERS0 0x04
1872 #define _H1ERS1 0x08
1873 #define _H1ERS2 0x10
1877 //==============================================================================
1879 extern __at(0x0117) __sfr HLTMR2
;
1880 extern __at(0x0118) __sfr HLTPR2
;
1882 //==============================================================================
1885 extern __at(0x0119) __sfr HLT2CON0
;
1891 unsigned H2CKPS0
: 1;
1892 unsigned H2CKPS1
: 1;
1894 unsigned H2OUTPS0
: 1;
1895 unsigned H2OUTPS1
: 1;
1896 unsigned H2OUTPS2
: 1;
1897 unsigned H2OUTPS3
: 1;
1903 unsigned H2CKPS
: 2;
1910 unsigned H2OUTPS
: 4;
1915 extern __at(0x0119) volatile __HLT2CON0bits_t HLT2CON0bits
;
1917 #define _H2CKPS0 0x01
1918 #define _H2CKPS1 0x02
1920 #define _H2OUTPS0 0x08
1921 #define _H2OUTPS1 0x10
1922 #define _H2OUTPS2 0x20
1923 #define _H2OUTPS3 0x40
1925 //==============================================================================
1928 //==============================================================================
1931 extern __at(0x011A) __sfr HLT2CON1
;
1937 unsigned H2REREN
: 1;
1938 unsigned H2FEREN
: 1;
1939 unsigned H2ERS0
: 1;
1940 unsigned H2ERS1
: 1;
1941 unsigned H2ERS2
: 1;
1955 extern __at(0x011A) volatile __HLT2CON1bits_t HLT2CON1bits
;
1957 #define _H2REREN 0x01
1958 #define _H2FEREN 0x02
1959 #define _H2ERS0 0x04
1960 #define _H2ERS1 0x08
1961 #define _H2ERS2 0x10
1965 //==============================================================================
1968 //==============================================================================
1971 extern __at(0x011E) __sfr SLPC1CON0
;
1977 unsigned SC1INS
: 1;
1979 unsigned SCS1TSS0
: 1;
1980 unsigned SCS1TSS1
: 1;
1981 unsigned SC1POL
: 1;
1982 unsigned SC1MRPE
: 1;
1990 unsigned SCS1TSS
: 2;
1993 } __SLPC1CON0bits_t
;
1995 extern __at(0x011E) volatile __SLPC1CON0bits_t SLPC1CON0bits
;
1997 #define _SC1INS 0x01
1998 #define _SCS1TSS0 0x04
1999 #define _SCS1TSS1 0x08
2000 #define _SC1POL 0x10
2001 #define _SC1MRPE 0x20
2004 //==============================================================================
2007 //==============================================================================
2010 extern __at(0x011E) __sfr SLPCCON0
;
2016 unsigned SC1INS
: 1;
2018 unsigned SCS1TSS0
: 1;
2019 unsigned SCS1TSS1
: 1;
2020 unsigned SC1POL
: 1;
2021 unsigned SC1MRPE
: 1;
2029 unsigned SCS1TSS
: 2;
2034 extern __at(0x011E) volatile __SLPCCON0bits_t SLPCCON0bits
;
2036 #define _SLPCCON0_SC1INS 0x01
2037 #define _SLPCCON0_SCS1TSS0 0x04
2038 #define _SLPCCON0_SCS1TSS1 0x08
2039 #define _SLPCCON0_SC1POL 0x10
2040 #define _SLPCCON0_SC1MRPE 0x20
2041 #define _SLPCCON0_SC1EN 0x80
2043 //==============================================================================
2046 //==============================================================================
2049 extern __at(0x011F) __sfr SLPC1CON1
;
2055 unsigned SC1ISET0
: 1;
2056 unsigned SC1ISET1
: 1;
2057 unsigned SC1ISET2
: 1;
2058 unsigned SC1ISET3
: 1;
2059 unsigned SC1RNG
: 1;
2067 unsigned SC1ISET
: 4;
2070 } __SLPC1CON1bits_t
;
2072 extern __at(0x011F) volatile __SLPC1CON1bits_t SLPC1CON1bits
;
2074 #define _SC1ISET0 0x01
2075 #define _SC1ISET1 0x02
2076 #define _SC1ISET2 0x04
2077 #define _SC1ISET3 0x08
2078 #define _SC1RNG 0x10
2080 //==============================================================================
2083 //==============================================================================
2086 extern __at(0x011F) __sfr SLPCCON1
;
2092 unsigned SC1ISET0
: 1;
2093 unsigned SC1ISET1
: 1;
2094 unsigned SC1ISET2
: 1;
2095 unsigned SC1ISET3
: 1;
2096 unsigned SC1RNG
: 1;
2104 unsigned SC1ISET
: 4;
2109 extern __at(0x011F) volatile __SLPCCON1bits_t SLPCCON1bits
;
2111 #define _SLPCCON1_SC1ISET0 0x01
2112 #define _SLPCCON1_SC1ISET1 0x02
2113 #define _SLPCCON1_SC1ISET2 0x04
2114 #define _SLPCCON1_SC1ISET3 0x08
2115 #define _SLPCCON1_SC1RNG 0x10
2117 //==============================================================================
2120 //==============================================================================
2123 extern __at(0x0185) __sfr ANSELA
;
2137 extern __at(0x0185) volatile __ANSELAbits_t ANSELAbits
;
2144 //==============================================================================
2147 //==============================================================================
2150 extern __at(0x0187) __sfr ANSELC
;
2173 extern __at(0x0187) volatile __ANSELCbits_t ANSELCbits
;
2180 //==============================================================================
2183 //==============================================================================
2186 extern __at(0x0188) __sfr APFCON
;
2194 unsigned T1GSEL
: 1;
2200 extern __at(0x0188) volatile __APFCONbits_t APFCONbits
;
2202 #define _T1GSEL 0x10
2204 //==============================================================================
2207 //==============================================================================
2210 extern __at(0x0189) __sfr OSCTUNE
;
2233 extern __at(0x0189) volatile __OSCTUNEbits_t OSCTUNEbits
;
2241 //==============================================================================
2244 //==============================================================================
2247 extern __at(0x018C) __sfr PMCON1
;
2261 extern __at(0x018C) volatile __PMCON1bits_t PMCON1bits
;
2267 //==============================================================================
2269 extern __at(0x018D) __sfr PMCON2
;
2270 extern __at(0x018E) __sfr PMADR
;
2271 extern __at(0x018E) __sfr PMADRL
;
2272 extern __at(0x018F) __sfr PMADRH
;
2273 extern __at(0x0190) __sfr PMDAT
;
2274 extern __at(0x0190) __sfr PMDATL
;
2275 extern __at(0x0191) __sfr PMDATH
;
2277 //==============================================================================
2280 extern __at(0x0192) __sfr COG1PHR
;
2286 unsigned G1PHR0
: 1;
2287 unsigned G1PHR1
: 1;
2288 unsigned G1PHR2
: 1;
2289 unsigned G1PHR3
: 1;
2303 extern __at(0x0192) volatile __COG1PHRbits_t COG1PHRbits
;
2305 #define _G1PHR0 0x01
2306 #define _G1PHR1 0x02
2307 #define _G1PHR2 0x04
2308 #define _G1PHR3 0x08
2310 //==============================================================================
2313 //==============================================================================
2316 extern __at(0x0193) __sfr COG1PHF
;
2322 unsigned G1PHF0
: 1;
2323 unsigned G1PHF1
: 1;
2324 unsigned G1PHF2
: 1;
2325 unsigned G1PHF3
: 1;
2339 extern __at(0x0193) volatile __COG1PHFbits_t COG1PHFbits
;
2341 #define _G1PHF0 0x01
2342 #define _G1PHF1 0x02
2343 #define _G1PHF2 0x04
2344 #define _G1PHF3 0x08
2346 //==============================================================================
2349 //==============================================================================
2352 extern __at(0x0194) __sfr COG1BKR
;
2358 unsigned G1BKR0
: 1;
2359 unsigned G1BKR1
: 1;
2360 unsigned G1BKR2
: 1;
2361 unsigned G1BKR3
: 1;
2375 extern __at(0x0194) volatile __COG1BKRbits_t COG1BKRbits
;
2377 #define _G1BKR0 0x01
2378 #define _G1BKR1 0x02
2379 #define _G1BKR2 0x04
2380 #define _G1BKR3 0x08
2382 //==============================================================================
2385 //==============================================================================
2388 extern __at(0x0195) __sfr COG1BKF
;
2394 unsigned G1BKF0
: 1;
2395 unsigned G1BKF1
: 1;
2396 unsigned G1BKF2
: 1;
2397 unsigned G1BKF3
: 1;
2411 extern __at(0x0195) volatile __COG1BKFbits_t COG1BKFbits
;
2413 #define _G1BKF0 0x01
2414 #define _G1BKF1 0x02
2415 #define _G1BKF2 0x04
2416 #define _G1BKF3 0x08
2418 //==============================================================================
2421 //==============================================================================
2424 extern __at(0x0196) __sfr COG1DBR
;
2430 unsigned G1DBR0
: 1;
2431 unsigned G1DBR1
: 1;
2432 unsigned G1DBR2
: 1;
2433 unsigned G1DBR3
: 1;
2447 extern __at(0x0196) volatile __COG1DBRbits_t COG1DBRbits
;
2449 #define _G1DBR0 0x01
2450 #define _G1DBR1 0x02
2451 #define _G1DBR2 0x04
2452 #define _G1DBR3 0x08
2454 //==============================================================================
2457 //==============================================================================
2460 extern __at(0x0197) __sfr COG1DBF
;
2466 unsigned G1DBF0
: 1;
2467 unsigned G1DBF1
: 1;
2468 unsigned G1DBF2
: 1;
2469 unsigned G1DBF3
: 1;
2483 extern __at(0x0197) volatile __COG1DBFbits_t COG1DBFbits
;
2485 #define _G1DBF0 0x01
2486 #define _G1DBF1 0x02
2487 #define _G1DBF2 0x04
2488 #define _G1DBF3 0x08
2490 //==============================================================================
2493 //==============================================================================
2496 extern __at(0x0198) __sfr COG1CON0
;
2505 unsigned G1POL0
: 1;
2506 unsigned G1POL1
: 1;
2527 extern __at(0x0198) volatile __COG1CON0bits_t COG1CON0bits
;
2531 #define _G1POL0 0x08
2532 #define _G1POL1 0x10
2537 //==============================================================================
2540 //==============================================================================
2543 extern __at(0x0199) __sfr COG1CON1
;
2555 unsigned G1FDBTS
: 1;
2556 unsigned G1RDBTS
: 1;
2566 extern __at(0x0199) volatile __COG1CON1bits_t COG1CON1bits
;
2570 #define _G1FDBTS 0x40
2571 #define _G1RDBTS 0x80
2573 //==============================================================================
2576 //==============================================================================
2579 extern __at(0x019A) __sfr COG1RIS
;
2583 unsigned G1RIC1
: 1;
2584 unsigned G1RIC2
: 1;
2585 unsigned C1RICCP1
: 1;
2586 unsigned G1RIFLT
: 1;
2587 unsigned G1RIT2M
: 1;
2588 unsigned G1R1HLT1
: 1;
2589 unsigned G1RIHLT2
: 1;
2593 extern __at(0x019A) volatile __COG1RISbits_t COG1RISbits
;
2595 #define _G1RIC1 0x01
2596 #define _G1RIC2 0x02
2597 #define _C1RICCP1 0x04
2598 #define _G1RIFLT 0x08
2599 #define _G1RIT2M 0x10
2600 #define _G1R1HLT1 0x20
2601 #define _G1RIHLT2 0x40
2603 //==============================================================================
2606 //==============================================================================
2609 extern __at(0x019B) __sfr COG1RSIM
;
2613 unsigned G1RMC1
: 1;
2614 unsigned G1RMC2
: 1;
2615 unsigned G1RMCCP1
: 1;
2616 unsigned G1RMFLT
: 1;
2617 unsigned G1RTM2M
: 1;
2618 unsigned G1RMHLT1
: 1;
2619 unsigned G1RMHLT2
: 1;
2623 extern __at(0x019B) volatile __COG1RSIMbits_t COG1RSIMbits
;
2625 #define _G1RMC1 0x01
2626 #define _G1RMC2 0x02
2627 #define _G1RMCCP1 0x04
2628 #define _G1RMFLT 0x08
2629 #define _G1RTM2M 0x10
2630 #define _G1RMHLT1 0x20
2631 #define _G1RMHLT2 0x40
2633 //==============================================================================
2636 //==============================================================================
2639 extern __at(0x019C) __sfr COG1FIS
;
2643 unsigned G1FIC1
: 1;
2644 unsigned G1FIC2
: 1;
2645 unsigned G1FICCP1
: 1;
2646 unsigned G1FIFLT
: 1;
2647 unsigned G1FIT2M
: 1;
2648 unsigned G1FIHLT1
: 1;
2649 unsigned G1FIHLT2
: 1;
2653 extern __at(0x019C) volatile __COG1FISbits_t COG1FISbits
;
2655 #define _G1FIC1 0x01
2656 #define _G1FIC2 0x02
2657 #define _G1FICCP1 0x04
2658 #define _G1FIFLT 0x08
2659 #define _G1FIT2M 0x10
2660 #define _G1FIHLT1 0x20
2661 #define _G1FIHLT2 0x40
2663 //==============================================================================
2666 //==============================================================================
2669 extern __at(0x019D) __sfr COG1FSIM
;
2673 unsigned G1FMC1
: 1;
2674 unsigned G1FMC2
: 1;
2675 unsigned G1FMCCP1
: 1;
2676 unsigned G1FMFLT
: 1;
2677 unsigned G1FMT2M
: 1;
2678 unsigned G1FMHLT1
: 1;
2679 unsigned G1FMHLT2
: 1;
2683 extern __at(0x019D) volatile __COG1FSIMbits_t COG1FSIMbits
;
2685 #define _G1FMC1 0x01
2686 #define _G1FMC2 0x02
2687 #define _G1FMCCP1 0x04
2688 #define _G1FMFLT 0x08
2689 #define _G1FMT2M 0x10
2690 #define _G1FMHLT1 0x20
2691 #define _G1FMHLT2 0x40
2693 //==============================================================================
2696 //==============================================================================
2699 extern __at(0x019E) __sfr COG1ASD0
;
2707 unsigned G1ASD0L0
: 1;
2708 unsigned G1ASD0L1
: 1;
2709 unsigned G1ASD1L0
: 1;
2710 unsigned G1ASD1L1
: 1;
2711 unsigned G1ARSEN
: 1;
2712 unsigned G1ASDE
: 1;
2718 unsigned G1ASD0L
: 2;
2725 unsigned G1ASD1L
: 2;
2730 extern __at(0x019E) volatile __COG1ASD0bits_t COG1ASD0bits
;
2732 #define _G1ASD0L0 0x04
2733 #define _G1ASD0L1 0x08
2734 #define _G1ASD1L0 0x10
2735 #define _G1ASD1L1 0x20
2736 #define _G1ARSEN 0x40
2737 #define _G1ASDE 0x80
2739 //==============================================================================
2742 //==============================================================================
2745 extern __at(0x019F) __sfr COG1ASD1
;
2749 unsigned G1ASDSFLT
: 1;
2750 unsigned G1ASDSC1
: 1;
2751 unsigned G1ASDSC2
: 1;
2752 unsigned G1ASDSHLT1
: 1;
2753 unsigned G1ASDSHLT2
: 1;
2759 extern __at(0x019F) volatile __COG1ASD1bits_t COG1ASD1bits
;
2761 #define _G1ASDSFLT 0x01
2762 #define _G1ASDSC1 0x02
2763 #define _G1ASDSC2 0x04
2764 #define _G1ASDSHLT1 0x08
2765 #define _G1ASDSHLT2 0x10
2767 //==============================================================================
2770 //==============================================================================
2772 // Configuration Bits
2774 //==============================================================================
2776 #define _CONFIG 0x2007
2778 //----------------------------- CONFIG Options -------------------------------
2780 #define _FOSC0_INT 0x3FFE // Internal oscillator mode. I/O function on RA5/CLKIN.
2781 #define _FOSC0_EC 0x3FFF // EC oscillator mode. CLKIN function on RA5/CLKIN.
2782 #define _WDTE_OFF 0x3FF7 // Watchdog Timer disabled.
2783 #define _WDTE_ON 0x3FFF // Watchdog Timer enabled.
2784 #define _PWRTE_ON 0x3FEF // Power-up Timer enabled.
2785 #define _PWRTE_OFF 0x3FFF // Power-up Timer disabled.
2786 #define _MCLRE_OFF 0x3FDF // MCLR pin is alternate function.
2787 #define _MCLRE_ON 0x3FFF // MCLR pin is MCLR function with internal weak pullup.
2788 #define _CP_ON 0x3FBF // Program memory code protection is enabled.
2789 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
2790 #define _BOREN_DIS 0x3CFF // BOR disabled.
2791 #define _BOREN_SLEEP_DIS 0x3EFF // BOR enabled during operation and disabled in Sleep.
2792 #define _BOREN_EN 0x3FFF // BOR enabled.
2793 #define _WRT_ALL 0x33FF // 000h to 3FFh self-write protected.
2794 #define _WRT_HALF 0x37FF // 000h to 1FFh self-write protected.
2795 #define _WRT_FOURTH 0x3BFF // 000h to 0FFh self-write protected.
2796 #define _WRT_OFF 0x3FFF // Flash self-write protection off.
2797 #define _CLKOUTEN_ON 0x2FFF // CLKOUT function enabled. CLKOUT pin is CLKOUT.
2798 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function disabled. CLKOUT pin acts as I/O.
2800 //==============================================================================
2802 #define _DEVID1 0x2006
2804 #define _IDLOC0 0x2000
2805 #define _IDLOC1 0x2001
2806 #define _IDLOC2 0x2002
2807 #define _IDLOC3 0x2003
2809 //==============================================================================
2811 #ifndef NO_BIT_DEFINES
2813 #define ADON ADCON0bits.ADON // bit 0
2814 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1
2815 #define CHS0 ADCON0bits.CHS0 // bit 2
2816 #define CHS1 ADCON0bits.CHS1 // bit 3
2817 #define CHS2 ADCON0bits.CHS2 // bit 4
2818 #define CHS3 ADCON0bits.CHS3 // bit 5
2819 #define ADFM ADCON0bits.ADFM // bit 7
2821 #define ADPREF1 ADCON1bits.ADPREF1 // bit 0
2822 #define ADCS0 ADCON1bits.ADCS0 // bit 4
2823 #define ADCS1 ADCON1bits.ADCS1 // bit 5
2824 #define ADCS2 ADCON1bits.ADCS2 // bit 6
2826 #define ANSA0 ANSELAbits.ANSA0 // bit 0
2827 #define ANSA1 ANSELAbits.ANSA1 // bit 1
2828 #define ANSA2 ANSELAbits.ANSA2 // bit 2
2829 #define ANSA4 ANSELAbits.ANSA4 // bit 4
2831 #define ANSC0 ANSELCbits.ANSC0 // bit 0
2832 #define ANSC1 ANSELCbits.ANSC1 // bit 1
2833 #define ANSC2 ANSELCbits.ANSC2 // bit 2
2834 #define ANSC3 ANSELCbits.ANSC3 // bit 3
2836 #define T1GSEL APFCONbits.T1GSEL // bit 4
2838 #define C1SYNC C1CON0bits.C1SYNC // bit 0
2839 #define C1HYS C1CON0bits.C1HYS // bit 1
2840 #define C1SP C1CON0bits.C1SP // bit 2
2841 #define C1ZLF C1CON0bits.C1ZLF // bit 3
2842 #define C1POL C1CON0bits.C1POL // bit 4
2843 #define C1OE C1CON0bits.C1OE // bit 5
2844 #define C1OUT C1CON0bits.C1OUT // bit 6
2845 #define C1ON C1CON0bits.C1ON // bit 7
2847 #define C1NCH0 C1CON1bits.C1NCH0 // bit 0
2848 #define C1NCH1 C1CON1bits.C1NCH1 // bit 1
2849 #define C1NCH2 C1CON1bits.C1NCH2 // bit 2
2850 #define C1PCH0 C1CON1bits.C1PCH0 // bit 3
2851 #define C1PCH1 C1CON1bits.C1PCH1 // bit 4
2852 #define C1PCH2 C1CON1bits.C1PCH2 // bit 5
2853 #define C1INTN C1CON1bits.C1INTN // bit 6
2854 #define C1INTP C1CON1bits.C1INTP // bit 7
2856 #define C2SYNC C2CON0bits.C2SYNC // bit 0
2857 #define C2HYS C2CON0bits.C2HYS // bit 1
2858 #define C2SP C2CON0bits.C2SP // bit 2
2859 #define C2ZLF C2CON0bits.C2ZLF // bit 3
2860 #define C2POL C2CON0bits.C2POL // bit 4
2861 #define C2OE C2CON0bits.C2OE // bit 5
2862 #define C2OUT C2CON0bits.C2OUT // bit 6
2863 #define C2ON C2CON0bits.C2ON // bit 7
2865 #define C2NCH0 C2CON1bits.C2NCH0 // bit 0
2866 #define C2NCH1 C2CON1bits.C2NCH1 // bit 1
2867 #define C2NCH2 C2CON1bits.C2NCH2 // bit 2
2868 #define C2PCH0 C2CON1bits.C2PCH0 // bit 3
2869 #define C2PCH1 C2CON1bits.C2PCH1 // bit 4
2870 #define C2PCH2 C2CON1bits.C2PCH2 // bit 5
2871 #define C2INTN C2CON1bits.C2INTN // bit 6
2872 #define C2INTP C2CON1bits.C2INTP // bit 7
2874 #define CCP1M0 CCP1CONbits.CCP1M0 // bit 0
2875 #define CCP1M1 CCP1CONbits.CCP1M1 // bit 1
2876 #define CCP1M2 CCP1CONbits.CCP1M2 // bit 2
2877 #define CCP1M3 CCP1CONbits.CCP1M3 // bit 3
2878 #define DC1B0 CCP1CONbits.DC1B0 // bit 4
2879 #define DC1B1 CCP1CONbits.DC1B1 // bit 5
2881 #define MCOUT1 CMOUTbits.MCOUT1 // bit 0
2882 #define MCOUT2 CMOUTbits.MCOUT2 // bit 1
2884 #define G1ASD0L0 COG1ASD0bits.G1ASD0L0 // bit 2
2885 #define G1ASD0L1 COG1ASD0bits.G1ASD0L1 // bit 3
2886 #define G1ASD1L0 COG1ASD0bits.G1ASD1L0 // bit 4
2887 #define G1ASD1L1 COG1ASD0bits.G1ASD1L1 // bit 5
2888 #define G1ARSEN COG1ASD0bits.G1ARSEN // bit 6
2889 #define G1ASDE COG1ASD0bits.G1ASDE // bit 7
2891 #define G1ASDSFLT COG1ASD1bits.G1ASDSFLT // bit 0
2892 #define G1ASDSC1 COG1ASD1bits.G1ASDSC1 // bit 1
2893 #define G1ASDSC2 COG1ASD1bits.G1ASDSC2 // bit 2
2894 #define G1ASDSHLT1 COG1ASD1bits.G1ASDSHLT1 // bit 3
2895 #define G1ASDSHLT2 COG1ASD1bits.G1ASDSHLT2 // bit 4
2897 #define G1BKF0 COG1BKFbits.G1BKF0 // bit 0
2898 #define G1BKF1 COG1BKFbits.G1BKF1 // bit 1
2899 #define G1BKF2 COG1BKFbits.G1BKF2 // bit 2
2900 #define G1BKF3 COG1BKFbits.G1BKF3 // bit 3
2902 #define G1BKR0 COG1BKRbits.G1BKR0 // bit 0
2903 #define G1BKR1 COG1BKRbits.G1BKR1 // bit 1
2904 #define G1BKR2 COG1BKRbits.G1BKR2 // bit 2
2905 #define G1BKR3 COG1BKRbits.G1BKR3 // bit 3
2907 #define G1MD COG1CON0bits.G1MD // bit 0
2908 #define G1LD COG1CON0bits.G1LD // bit 2
2909 #define G1POL0 COG1CON0bits.G1POL0 // bit 3
2910 #define G1POL1 COG1CON0bits.G1POL1 // bit 4
2911 #define G1OE0 COG1CON0bits.G1OE0 // bit 5
2912 #define G1OE1 COG1CON0bits.G1OE1 // bit 6
2913 #define G1EN COG1CON0bits.G1EN // bit 7
2915 #define G1CS0 COG1CON1bits.G1CS0 // bit 0
2916 #define G1CS1 COG1CON1bits.G1CS1 // bit 1
2917 #define G1FDBTS COG1CON1bits.G1FDBTS // bit 6
2918 #define G1RDBTS COG1CON1bits.G1RDBTS // bit 7
2920 #define G1DBF0 COG1DBFbits.G1DBF0 // bit 0
2921 #define G1DBF1 COG1DBFbits.G1DBF1 // bit 1
2922 #define G1DBF2 COG1DBFbits.G1DBF2 // bit 2
2923 #define G1DBF3 COG1DBFbits.G1DBF3 // bit 3
2925 #define G1DBR0 COG1DBRbits.G1DBR0 // bit 0
2926 #define G1DBR1 COG1DBRbits.G1DBR1 // bit 1
2927 #define G1DBR2 COG1DBRbits.G1DBR2 // bit 2
2928 #define G1DBR3 COG1DBRbits.G1DBR3 // bit 3
2930 #define G1FIC1 COG1FISbits.G1FIC1 // bit 0
2931 #define G1FIC2 COG1FISbits.G1FIC2 // bit 1
2932 #define G1FICCP1 COG1FISbits.G1FICCP1 // bit 2
2933 #define G1FIFLT COG1FISbits.G1FIFLT // bit 3
2934 #define G1FIT2M COG1FISbits.G1FIT2M // bit 4
2935 #define G1FIHLT1 COG1FISbits.G1FIHLT1 // bit 5
2936 #define G1FIHLT2 COG1FISbits.G1FIHLT2 // bit 6
2938 #define G1FMC1 COG1FSIMbits.G1FMC1 // bit 0
2939 #define G1FMC2 COG1FSIMbits.G1FMC2 // bit 1
2940 #define G1FMCCP1 COG1FSIMbits.G1FMCCP1 // bit 2
2941 #define G1FMFLT COG1FSIMbits.G1FMFLT // bit 3
2942 #define G1FMT2M COG1FSIMbits.G1FMT2M // bit 4
2943 #define G1FMHLT1 COG1FSIMbits.G1FMHLT1 // bit 5
2944 #define G1FMHLT2 COG1FSIMbits.G1FMHLT2 // bit 6
2946 #define G1PHF0 COG1PHFbits.G1PHF0 // bit 0
2947 #define G1PHF1 COG1PHFbits.G1PHF1 // bit 1
2948 #define G1PHF2 COG1PHFbits.G1PHF2 // bit 2
2949 #define G1PHF3 COG1PHFbits.G1PHF3 // bit 3
2951 #define G1PHR0 COG1PHRbits.G1PHR0 // bit 0
2952 #define G1PHR1 COG1PHRbits.G1PHR1 // bit 1
2953 #define G1PHR2 COG1PHRbits.G1PHR2 // bit 2
2954 #define G1PHR3 COG1PHRbits.G1PHR3 // bit 3
2956 #define G1RIC1 COG1RISbits.G1RIC1 // bit 0
2957 #define G1RIC2 COG1RISbits.G1RIC2 // bit 1
2958 #define C1RICCP1 COG1RISbits.C1RICCP1 // bit 2
2959 #define G1RIFLT COG1RISbits.G1RIFLT // bit 3
2960 #define G1RIT2M COG1RISbits.G1RIT2M // bit 4
2961 #define G1R1HLT1 COG1RISbits.G1R1HLT1 // bit 5
2962 #define G1RIHLT2 COG1RISbits.G1RIHLT2 // bit 6
2964 #define G1RMC1 COG1RSIMbits.G1RMC1 // bit 0
2965 #define G1RMC2 COG1RSIMbits.G1RMC2 // bit 1
2966 #define G1RMCCP1 COG1RSIMbits.G1RMCCP1 // bit 2
2967 #define G1RMFLT COG1RSIMbits.G1RMFLT // bit 3
2968 #define G1RTM2M COG1RSIMbits.G1RTM2M // bit 4
2969 #define G1RMHLT1 COG1RSIMbits.G1RMHLT1 // bit 5
2970 #define G1RMHLT2 COG1RSIMbits.G1RMHLT2 // bit 6
2972 #define DACPSS0 DAC1CON0bits.DACPSS0 // bit 2
2973 #define DACPSS1 DAC1CON0bits.DACPSS1 // bit 3
2974 #define DACOE DAC1CON0bits.DACOE // bit 5
2975 #define DACFM DAC1CON0bits.DACFM // bit 6
2976 #define DACEN DAC1CON0bits.DACEN // bit 7
2978 #define FVRBUFEN FVR1CON0bits.FVRBUFEN // bit 0
2979 #define FVRBUSS0 FVR1CON0bits.FVRBUSS0 // bit 3
2980 #define FVRBUSS1 FVR1CON0bits.FVRBUSS1 // bit 4
2981 #define FVROE FVR1CON0bits.FVROE // bit 5
2982 #define FVRRDY FVR1CON0bits.FVRRDY // bit 6
2983 #define FVREN FVR1CON0bits.FVREN // bit 7
2985 #define H1CKPS0 HLT1CON0bits.H1CKPS0 // bit 0
2986 #define H1CKPS1 HLT1CON0bits.H1CKPS1 // bit 1
2987 #define H1ON HLT1CON0bits.H1ON // bit 2
2988 #define H1OUTPS0 HLT1CON0bits.H1OUTPS0 // bit 3
2989 #define H1OUTPS1 HLT1CON0bits.H1OUTPS1 // bit 4
2990 #define H1OUTPS2 HLT1CON0bits.H1OUTPS2 // bit 5
2991 #define H1OUTPS3 HLT1CON0bits.H1OUTPS3 // bit 6
2993 #define H1REREN HLT1CON1bits.H1REREN // bit 0
2994 #define H1FEREN HLT1CON1bits.H1FEREN // bit 1
2995 #define H1ERS0 HLT1CON1bits.H1ERS0 // bit 2
2996 #define H1ERS1 HLT1CON1bits.H1ERS1 // bit 3
2997 #define H1ERS2 HLT1CON1bits.H1ERS2 // bit 4
2998 #define H1RES HLT1CON1bits.H1RES // bit 6
2999 #define H1FES HLT1CON1bits.H1FES // bit 7
3001 #define H2CKPS0 HLT2CON0bits.H2CKPS0 // bit 0
3002 #define H2CKPS1 HLT2CON0bits.H2CKPS1 // bit 1
3003 #define H2ON HLT2CON0bits.H2ON // bit 2
3004 #define H2OUTPS0 HLT2CON0bits.H2OUTPS0 // bit 3
3005 #define H2OUTPS1 HLT2CON0bits.H2OUTPS1 // bit 4
3006 #define H2OUTPS2 HLT2CON0bits.H2OUTPS2 // bit 5
3007 #define H2OUTPS3 HLT2CON0bits.H2OUTPS3 // bit 6
3009 #define H2REREN HLT2CON1bits.H2REREN // bit 0
3010 #define H2FEREN HLT2CON1bits.H2FEREN // bit 1
3011 #define H2ERS0 HLT2CON1bits.H2ERS0 // bit 2
3012 #define H2ERS1 HLT2CON1bits.H2ERS1 // bit 3
3013 #define H2ERS2 HLT2CON1bits.H2ERS2 // bit 4
3014 #define H2RES HLT2CON1bits.H2RES // bit 6
3015 #define H2FES HLT2CON1bits.H2FES // bit 7
3017 #define IOCIF INTCONbits.IOCIF // bit 0
3018 #define INTF INTCONbits.INTF // bit 1
3019 #define T0IF INTCONbits.T0IF // bit 2
3020 #define IOCIE INTCONbits.IOCIE // bit 3
3021 #define INTE INTCONbits.INTE // bit 4
3022 #define T0IE INTCONbits.T0IE // bit 5
3023 #define PEIE INTCONbits.PEIE // bit 6
3024 #define GIE INTCONbits.GIE // bit 7
3026 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
3027 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
3028 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
3029 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
3030 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
3031 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
3033 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
3034 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
3035 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
3036 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
3037 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
3038 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
3040 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
3041 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
3042 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
3043 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
3044 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
3045 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
3047 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
3048 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
3049 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
3050 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
3051 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
3052 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
3054 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
3055 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
3056 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
3057 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
3058 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
3059 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
3061 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
3062 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
3063 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
3064 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
3065 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
3066 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
3068 #define LATA0 LATAbits.LATA0 // bit 0
3069 #define LATA1 LATAbits.LATA1 // bit 1
3070 #define LATA2 LATAbits.LATA2 // bit 2
3071 #define LATA4 LATAbits.LATA4 // bit 4
3072 #define LATA5 LATAbits.LATA5 // bit 5
3074 #define LATC0 LATCbits.LATC0 // bit 0
3075 #define LATC1 LATCbits.LATC1 // bit 1
3076 #define LATC2 LATCbits.LATC2 // bit 2
3077 #define LATC3 LATCbits.LATC3 // bit 3
3078 #define LATC4 LATCbits.LATC4 // bit 4
3079 #define LATC5 LATCbits.LATC5 // bit 5
3081 #define OPA1PCH0 OPA1CONbits.OPA1PCH0 // bit 0
3082 #define OPA1PCH1 OPA1CONbits.OPA1PCH1 // bit 1
3083 #define OPA1NCH0 OPA1CONbits.OPA1NCH0 // bit 2
3084 #define OPA1NCH1 OPA1CONbits.OPA1NCH1 // bit 3
3085 #define OPAUGM OPA1CONbits.OPAUGM // bit 4
3086 #define OPAEN OPA1CONbits.OPAEN // bit 7
3088 #define PS0 OPTION_REGbits.PS0 // bit 0
3089 #define PS1 OPTION_REGbits.PS1 // bit 1
3090 #define PS2 OPTION_REGbits.PS2 // bit 2
3091 #define PSA OPTION_REGbits.PSA // bit 3
3092 #define T0SE OPTION_REGbits.T0SE // bit 4
3093 #define T0CS OPTION_REGbits.T0CS // bit 5
3094 #define INTEDG OPTION_REGbits.INTEDG // bit 6
3095 #define NOT_RAPU OPTION_REGbits.NOT_RAPU // bit 7
3097 #define LTS OSCCONbits.LTS // bit 1
3098 #define HTS OSCCONbits.HTS // bit 2
3099 #define IRCF0 OSCCONbits.IRCF0 // bit 4
3100 #define IRCF1 OSCCONbits.IRCF1 // bit 5
3102 #define TUN0 OSCTUNEbits.TUN0 // bit 0
3103 #define TUN1 OSCTUNEbits.TUN1 // bit 1
3104 #define TUN2 OSCTUNEbits.TUN2 // bit 2
3105 #define TUN3 OSCTUNEbits.TUN3 // bit 3
3106 #define TUN4 OSCTUNEbits.TUN4 // bit 4
3108 #define NOT_BOR PCONbits.NOT_BOR // bit 0
3109 #define NOT_POR PCONbits.NOT_POR // bit 1
3111 #define TMR1IE PIE1bits.TMR1IE // bit 0
3112 #define TMR2IE PIE1bits.TMR2IE // bit 1
3113 #define HLTMR1IE PIE1bits.HLTMR1IE // bit 2
3114 #define HLTMR2IE PIE1bits.HLTMR2IE // bit 3
3115 #define ADIE PIE1bits.ADIE // bit 6
3116 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
3118 #define CCP1IE PIE2bits.CCP1IE // bit 0
3119 #define COG1IE PIE2bits.COG1IE // bit 2
3120 #define C1IE PIE2bits.C1IE // bit 4
3121 #define C2IE PIE2bits.C2IE // bit 5
3123 #define TMR1IF PIR1bits.TMR1IF // bit 0
3124 #define TMR2IF PIR1bits.TMR2IF // bit 1
3125 #define HLTMR1IF PIR1bits.HLTMR1IF // bit 2
3126 #define HLTMR2IF PIR1bits.HLTMR2IF // bit 3
3127 #define ADIF PIR1bits.ADIF // bit 6
3128 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
3130 #define CCP1IF PIR2bits.CCP1IF // bit 0
3131 #define COG1IF PIR2bits.COG1IF // bit 2
3132 #define C1IF PIR2bits.C1IF // bit 4
3133 #define C2IF PIR2bits.C2IF // bit 5
3135 #define RD PMCON1bits.RD // bit 0
3136 #define WR PMCON1bits.WR // bit 1
3137 #define WREN PMCON1bits.WREN // bit 2
3139 #define RA0 PORTAbits.RA0 // bit 0
3140 #define RA1 PORTAbits.RA1 // bit 1
3141 #define RA2 PORTAbits.RA2 // bit 2
3142 #define RA3 PORTAbits.RA3 // bit 3
3143 #define RA4 PORTAbits.RA4 // bit 4
3144 #define RA5 PORTAbits.RA5 // bit 5
3146 #define RC0 PORTCbits.RC0 // bit 0
3147 #define RC1 PORTCbits.RC1 // bit 1
3148 #define RC2 PORTCbits.RC2 // bit 2
3149 #define RC3 PORTCbits.RC3 // bit 3
3150 #define RC4 PORTCbits.RC4 // bit 4
3151 #define RC5 PORTCbits.RC5 // bit 5
3153 #define SC1INS SLPC1CON0bits.SC1INS // bit 0
3154 #define SCS1TSS0 SLPC1CON0bits.SCS1TSS0 // bit 2
3155 #define SCS1TSS1 SLPC1CON0bits.SCS1TSS1 // bit 3
3156 #define SC1POL SLPC1CON0bits.SC1POL // bit 4
3157 #define SC1MRPE SLPC1CON0bits.SC1MRPE // bit 5
3158 #define SC1EN SLPC1CON0bits.SC1EN // bit 7
3160 #define SC1ISET0 SLPC1CON1bits.SC1ISET0 // bit 0
3161 #define SC1ISET1 SLPC1CON1bits.SC1ISET1 // bit 1
3162 #define SC1ISET2 SLPC1CON1bits.SC1ISET2 // bit 2
3163 #define SC1ISET3 SLPC1CON1bits.SC1ISET3 // bit 3
3164 #define SC1RNG SLPC1CON1bits.SC1RNG // bit 4
3166 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
3167 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
3169 #define C STATUSbits.C // bit 0
3170 #define DC STATUSbits.DC // bit 1
3171 #define Z STATUSbits.Z // bit 2
3172 #define NOT_PD STATUSbits.NOT_PD // bit 3
3173 #define NOT_TO STATUSbits.NOT_TO // bit 4
3174 #define RP0 STATUSbits.RP0 // bit 5
3175 #define RP1 STATUSbits.RP1 // bit 6
3176 #define IRP STATUSbits.IRP // bit 7
3178 #define TMR1ON T1CONbits.TMR1ON // bit 0
3179 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
3180 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
3181 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
3182 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
3183 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
3185 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
3186 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
3187 #define T1GVAL T1GCONbits.T1GVAL // bit 2
3188 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3, shadows bit in T1GCONbits
3189 #define T1GGO T1GCONbits.T1GGO // bit 3, shadows bit in T1GCONbits
3190 #define T1GSPM T1GCONbits.T1GSPM // bit 4
3191 #define T1GTM T1GCONbits.T1GTM // bit 5
3192 #define T1GPOL T1GCONbits.T1GPOL // bit 6
3193 #define TMR1GE T1GCONbits.TMR1GE // bit 7
3195 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
3196 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
3197 #define TMR2ON T2CONbits.TMR2ON // bit 2
3198 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
3199 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
3200 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
3201 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
3203 #define TRISA0 TRISAbits.TRISA0 // bit 0
3204 #define TRISA1 TRISAbits.TRISA1 // bit 1
3205 #define TRISA2 TRISAbits.TRISA2 // bit 2
3206 #define TRISA3 TRISAbits.TRISA3 // bit 3
3207 #define TRISA4 TRISAbits.TRISA4 // bit 4
3208 #define TRISA5 TRISAbits.TRISA5 // bit 5
3210 #define TRISC0 TRISCbits.TRISC0 // bit 0
3211 #define TRISC1 TRISCbits.TRISC1 // bit 1
3212 #define TRISC2 TRISCbits.TRISC2 // bit 2
3213 #define TRISC3 TRISCbits.TRISC3 // bit 3
3214 #define TRISC4 TRISCbits.TRISC4 // bit 4
3215 #define TRISC5 TRISCbits.TRISC5 // bit 5
3217 #define WPUA0 WPUAbits.WPUA0 // bit 0
3218 #define WPUA1 WPUAbits.WPUA1 // bit 1
3219 #define WPUA2 WPUAbits.WPUA2 // bit 2
3220 #define WPUA3 WPUAbits.WPUA3 // bit 3
3221 #define WPUA4 WPUAbits.WPUA4 // bit 4
3222 #define WPUA5 WPUAbits.WPUA5 // bit 5
3224 #define WPUC0 WPUCbits.WPUC0 // bit 0
3225 #define WPUC1 WPUCbits.WPUC1 // bit 1
3226 #define WPUC2 WPUCbits.WPUC2 // bit 2
3227 #define WPUC3 WPUCbits.WPUC3 // bit 3
3228 #define WPUC4 WPUCbits.WPUC4 // bit 4
3229 #define WPUC5 WPUCbits.WPUC5 // bit 5
3231 #endif // #ifndef NO_BIT_DEFINES
3233 #endif // #ifndef __PIC16F753_H__