2 * This declarations of the PIC16F819 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:01 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16F819_H__
26 #define __PIC16F819_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF_ADDR 0x0000
37 #define TMR0_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR_ADDR 0x0004
41 #define PORTA_ADDR 0x0005
42 #define PORTB_ADDR 0x0006
43 #define PCLATH_ADDR 0x000A
44 #define INTCON_ADDR 0x000B
45 #define PIR1_ADDR 0x000C
46 #define PIR2_ADDR 0x000D
47 #define TMR1_ADDR 0x000E
48 #define TMR1L_ADDR 0x000E
49 #define TMR1H_ADDR 0x000F
50 #define T1CON_ADDR 0x0010
51 #define TMR2_ADDR 0x0011
52 #define T2CON_ADDR 0x0012
53 #define SSPBUF_ADDR 0x0013
54 #define SSPCON_ADDR 0x0014
55 #define CCPR1_ADDR 0x0015
56 #define CCPR1L_ADDR 0x0015
57 #define CCPR1H_ADDR 0x0016
58 #define CCP1CON_ADDR 0x0017
59 #define ADRESH_ADDR 0x001E
60 #define ADCON0_ADDR 0x001F
61 #define OPTION_REG_ADDR 0x0081
62 #define TRISA_ADDR 0x0085
63 #define TRISB_ADDR 0x0086
64 #define PIE1_ADDR 0x008C
65 #define PIE2_ADDR 0x008D
66 #define PCON_ADDR 0x008E
67 #define OSCCON_ADDR 0x008F
68 #define OSCTUNE_ADDR 0x0090
69 #define PR2_ADDR 0x0092
70 #define SSPADD_ADDR 0x0093
71 #define SSPSTAT_ADDR 0x0094
72 #define ADRESL_ADDR 0x009E
73 #define ADCON1_ADDR 0x009F
74 #define EEDATA_ADDR 0x010C
75 #define EEADR_ADDR 0x010D
76 #define EEDATH_ADDR 0x010E
77 #define EEADRH_ADDR 0x010F
78 #define EECON1_ADDR 0x018C
79 #define EECON2_ADDR 0x018D
81 #endif // #ifndef NO_ADDR_DEFINES
83 //==============================================================================
85 // Register Definitions
87 //==============================================================================
89 extern __at(0x0000) __sfr INDF
;
90 extern __at(0x0001) __sfr TMR0
;
91 extern __at(0x0002) __sfr PCL
;
93 //==============================================================================
96 extern __at(0x0003) __sfr STATUS
;
120 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
131 //==============================================================================
133 extern __at(0x0004) __sfr FSR
;
135 //==============================================================================
138 extern __at(0x0005) __sfr PORTA
;
152 extern __at(0x0005) volatile __PORTAbits_t PORTAbits
;
163 //==============================================================================
166 //==============================================================================
169 extern __at(0x0006) __sfr PORTB
;
183 extern __at(0x0006) volatile __PORTBbits_t PORTBbits
;
194 //==============================================================================
196 extern __at(0x000A) __sfr PCLATH
;
198 //==============================================================================
201 extern __at(0x000B) __sfr INTCON
;
215 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
226 //==============================================================================
229 //==============================================================================
232 extern __at(0x000C) __sfr PIR1
;
246 extern __at(0x000C) volatile __PIR1bits_t PIR1bits
;
254 //==============================================================================
257 //==============================================================================
260 extern __at(0x000D) __sfr PIR2
;
274 extern __at(0x000D) volatile __PIR2bits_t PIR2bits
;
278 //==============================================================================
280 extern __at(0x000E) __sfr TMR1
;
281 extern __at(0x000E) __sfr TMR1L
;
282 extern __at(0x000F) __sfr TMR1H
;
284 //==============================================================================
287 extern __at(0x0010) __sfr T1CON
;
295 unsigned NOT_T1SYNC
: 1;
296 unsigned T1OSCEN
: 1;
297 unsigned T1CKPS0
: 1;
298 unsigned T1CKPS1
: 1;
307 unsigned T1INSYNC
: 1;
323 extern __at(0x0010) volatile __T1CONbits_t T1CONbits
;
327 #define _NOT_T1SYNC 0x04
328 #define _T1INSYNC 0x04
329 #define _T1OSCEN 0x08
330 #define _T1CKPS0 0x10
331 #define _T1CKPS1 0x20
333 //==============================================================================
335 extern __at(0x0011) __sfr TMR2
;
337 //==============================================================================
340 extern __at(0x0012) __sfr T2CON
;
346 unsigned T2CKPS0
: 1;
347 unsigned T2CKPS1
: 1;
349 unsigned TOUTPS0
: 1;
350 unsigned TOUTPS1
: 1;
351 unsigned TOUTPS2
: 1;
352 unsigned TOUTPS3
: 1;
370 extern __at(0x0012) volatile __T2CONbits_t T2CONbits
;
372 #define _T2CKPS0 0x01
373 #define _T2CKPS1 0x02
375 #define _TOUTPS0 0x08
376 #define _TOUTPS1 0x10
377 #define _TOUTPS2 0x20
378 #define _TOUTPS3 0x40
380 //==============================================================================
382 extern __at(0x0013) __sfr SSPBUF
;
384 //==============================================================================
387 extern __at(0x0014) __sfr SSPCON
;
410 extern __at(0x0014) volatile __SSPCONbits_t SSPCONbits
;
421 //==============================================================================
423 extern __at(0x0015) __sfr CCPR1
;
424 extern __at(0x0015) __sfr CCPR1L
;
425 extern __at(0x0016) __sfr CCPR1H
;
427 //==============================================================================
430 extern __at(0x0017) __sfr CCP1CON
;
453 extern __at(0x0017) volatile __CCP1CONbits_t CCP1CONbits
;
462 //==============================================================================
464 extern __at(0x001E) __sfr ADRESH
;
466 //==============================================================================
469 extern __at(0x001F) __sfr ADCON0
;
477 unsigned GO_NOT_DONE
: 1;
501 unsigned NOT_DONE
: 1;
513 unsigned GO_DONE
: 1;
535 extern __at(0x001F) volatile __ADCON0bits_t ADCON0bits
;
538 #define _GO_NOT_DONE 0x04
540 #define _NOT_DONE 0x04
541 #define _GO_DONE 0x04
548 //==============================================================================
551 //==============================================================================
554 extern __at(0x0081) __sfr OPTION_REG
;
567 unsigned NOT_RBPU
: 1;
575 } __OPTION_REGbits_t
;
577 extern __at(0x0081) volatile __OPTION_REGbits_t OPTION_REGbits
;
586 #define _NOT_RBPU 0x80
588 //==============================================================================
591 //==============================================================================
594 extern __at(0x0085) __sfr TRISA
;
608 extern __at(0x0085) volatile __TRISAbits_t TRISAbits
;
619 //==============================================================================
622 //==============================================================================
625 extern __at(0x0086) __sfr TRISB
;
639 extern __at(0x0086) volatile __TRISBbits_t TRISBbits
;
650 //==============================================================================
653 //==============================================================================
656 extern __at(0x008C) __sfr PIE1
;
670 extern __at(0x008C) volatile __PIE1bits_t PIE1bits
;
678 //==============================================================================
681 //==============================================================================
684 extern __at(0x008D) __sfr PIE2
;
698 extern __at(0x008D) volatile __PIE2bits_t PIE2bits
;
702 //==============================================================================
705 //==============================================================================
708 extern __at(0x008E) __sfr PCON
;
714 unsigned NOT_BOR
: 1;
715 unsigned NOT_POR
: 1;
737 extern __at(0x008E) volatile __PCONbits_t PCONbits
;
739 #define _NOT_BOR 0x01
741 #define _NOT_POR 0x02
743 //==============================================================================
746 //==============================================================================
749 extern __at(0x008F) __sfr OSCCON
;
773 extern __at(0x008F) volatile __OSCCONbits_t OSCCONbits
;
780 //==============================================================================
783 //==============================================================================
786 extern __at(0x0090) __sfr OSCTUNE
;
809 extern __at(0x0090) volatile __OSCTUNEbits_t OSCTUNEbits
;
818 //==============================================================================
820 extern __at(0x0092) __sfr PR2
;
821 extern __at(0x0093) __sfr SSPADD
;
823 //==============================================================================
826 extern __at(0x0094) __sfr SSPSTAT
;
834 unsigned R_NOT_W
: 1;
837 unsigned D_NOT_A
: 1;
847 unsigned I2C_START
: 1;
848 unsigned I2C_STOP
: 1;
858 unsigned I2C_READ
: 1;
861 unsigned I2C_DATA
: 1;
882 unsigned NOT_WRITE
: 1;
885 unsigned NOT_ADDRESS
: 1;
906 unsigned READ_WRITE
: 1;
909 unsigned DATA_ADDRESS
: 1;
915 extern __at(0x0094) volatile __SSPSTATbits_t SSPSTATbits
;
919 #define _R_NOT_W 0x04
921 #define _I2C_READ 0x04
923 #define _NOT_WRITE 0x04
925 #define _READ_WRITE 0x04
927 #define _I2C_START 0x08
929 #define _I2C_STOP 0x10
930 #define _D_NOT_A 0x20
932 #define _I2C_DATA 0x20
934 #define _NOT_ADDRESS 0x20
936 #define _DATA_ADDRESS 0x20
940 //==============================================================================
942 extern __at(0x009E) __sfr ADRESL
;
944 //==============================================================================
947 extern __at(0x009F) __sfr ADCON1
;
970 extern __at(0x009F) volatile __ADCON1bits_t ADCON1bits
;
979 //==============================================================================
981 extern __at(0x010C) __sfr EEDATA
;
982 extern __at(0x010D) __sfr EEADR
;
983 extern __at(0x010E) __sfr EEDATH
;
984 extern __at(0x010F) __sfr EEADRH
;
986 //==============================================================================
989 extern __at(0x018C) __sfr EECON1
;
1003 extern __at(0x018C) volatile __EECON1bits_t EECON1bits
;
1012 //==============================================================================
1014 extern __at(0x018D) __sfr EECON2
;
1016 //==============================================================================
1018 // Configuration Bits
1020 //==============================================================================
1022 #define _CONFIG 0x2007
1024 //----------------------------- CONFIG Options -------------------------------
1026 #define _FOSC_LP 0x3FEC // LP oscillator.
1027 #define _LP_OSC 0x3FEC // LP oscillator.
1028 #define _FOSC_XT 0x3FED // XT oscillator.
1029 #define _XT_OSC 0x3FED // XT oscillator.
1030 #define _FOSC_HS 0x3FEE // HS oscillator.
1031 #define _HS_OSC 0x3FEE // HS oscillator.
1032 #define _FOSC_EC 0x3FEF // EXTCLK; port I/O function on RA6/OSC2/CLKO pin.
1033 #define _EXTCLK 0x3FEF // EXTCLK; port I/O function on RA6/OSC2/CLKO pin.
1034 #define _FOSC_INTOSCIO 0x3FFC // INTRC oscillator; port I/O function on both RA6/OSC2/CLKO pin and RA7/OSC1/CLKI pin.
1035 #define _INTRC_IO 0x3FFC // INTRC oscillator; port I/O function on both RA6/OSC2/CLKO pin and RA7/OSC1/CLKI pin.
1036 #define _FOSC_INTOSCCLK 0x3FFD // INTRC oscillator; CLKO function on RA6/OSC2/CLKO pin and port I/O function on RA7/OSC1/CLKI pin.
1037 #define _INTRC_CLKOUT 0x3FFD // INTRC oscillator; CLKO function on RA6/OSC2/CLKO pin and port I/O function on RA7/OSC1/CLKI pin.
1038 #define _FOSC_EXTRCIO 0x3FFE // EXTRC oscillator; port I/O function on RA6/OSC2/CLKO pin.
1039 #define _EXTRC_IO 0x3FFE // EXTRC oscillator; port I/O function on RA6/OSC2/CLKO pin.
1040 #define _FOSC_EXTRCCLK 0x3FFF // EXTRC oscillator; CLKO function on RA6/OSC2/CLKO pin.
1041 #define _EXTRC_CLKOUT 0x3FFF // EXTRC oscillator; CLKO function on RA6/OSC2/CLKO pin.
1042 #define _WDTE_OFF 0x3FFB // WDT disabled.
1043 #define _WDT_OFF 0x3FFB // WDT disabled.
1044 #define _WDTE_ON 0x3FFF // WDT enabled.
1045 #define _WDT_ON 0x3FFF // WDT enabled.
1046 #define _PWRTE_ON 0x3FF7 // PWRT enabled.
1047 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
1048 #define _MCLRE_OFF 0x3FDF // RA5/MCLR/VPP pin function is digital I/O, MCLR internally tied to VDD.
1049 #define _MCLR_OFF 0x3FDF // RA5/MCLR/VPP pin function is digital I/O, MCLR internally tied to VDD.
1050 #define _MCLRE_ON 0x3FFF // RA5/MCLR/VPP pin function is MCLR.
1051 #define _MCLR_ON 0x3FFF // RA5/MCLR/VPP pin function is MCLR.
1052 #define _BOREN_OFF 0x3FBF // BOR disabled.
1053 #define _BODEN_OFF 0x3FBF // BOR disabled.
1054 #define _BOREN_ON 0x3FFF // BOR enabled.
1055 #define _BODEN_ON 0x3FFF // BOR enabled.
1056 #define _LVP_OFF 0x3F7F // RB3/PGM pin has digital I/O function, HV on MCLR must be used for programming.
1057 #define _LVP_ON 0x3FFF // RB3/PGM pin has PGM function, Low-Voltage Programming enabled.
1058 #define _CPD_ON 0x3EFF // Data EE memory locations code-protected.
1059 #define _CPD_OFF 0x3FFF // Code protection off.
1060 #define _WRT_1536 0x39FF // 0000h to 05FFh write-protected, 0600h to 07FFh may be modified by EECON control.
1061 #define _WRT_ENABLE_1536 0x39FF // 0000h to 05FFh write-protected, 0600h to 07FFh may be modified by EECON control.
1062 #define _WRT_1024 0x3BFF // 0000h to 03FFh write-protected, 0400h to 07FFh may be modified by EECON control.
1063 #define _WRT_ENABLE_1024 0x3BFF // 0000h to 03FFh write-protected, 0400h to 07FFh may be modified by EECON control.
1064 #define _WRT_512 0x3DFF // 0000h to 01FFh write-protected, 0200h to 07FFh may be modified by EECON control.
1065 #define _WRT_ENABLE_512 0x3DFF // 0000h to 01FFh write-protected, 0200h to 07FFh may be modified by EECON control.
1066 #define _WRT_OFF 0x3FFF // Write protection off.
1067 #define _WRT_ENABLE_OFF 0x3FFF // Write protection off.
1068 #define _DEBUG_ON 0x37FF // In-Circuit Debugger enabled, RB6 and RB7 are dedicated to the debugger.
1069 #define _DEBUG_OFF 0x3FFF // In-Circuit Debugger disabled, RB6 and RB7 are general purpose I/O pins.
1070 #define _CCPMX_RB3 0x2FFF // CCP1 function on RB3.
1071 #define _CCP1_RB3 0x2FFF // CCP1 function on RB3.
1072 #define _CCPMX_RB2 0x3FFF // CCP1 function on RB2.
1073 #define _CCP1_RB2 0x3FFF // CCP1 function on RB2.
1074 #define _CP_ON 0x1FFF // All memory locations code-protected.
1075 #define _CP_ALL 0x1FFF // All memory locations code-protected.
1076 #define _CP_OFF 0x3FFF // Code protection off.
1078 //==============================================================================
1080 #define _DEVID1 0x2006
1082 #define _IDLOC0 0x2000
1083 #define _IDLOC1 0x2001
1084 #define _IDLOC2 0x2002
1085 #define _IDLOC3 0x2003
1087 //==============================================================================
1089 #ifndef NO_BIT_DEFINES
1091 #define ADON ADCON0bits.ADON // bit 0
1092 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 2, shadows bit in ADCON0bits
1093 #define GO ADCON0bits.GO // bit 2, shadows bit in ADCON0bits
1094 #define NOT_DONE ADCON0bits.NOT_DONE // bit 2, shadows bit in ADCON0bits
1095 #define GO_DONE ADCON0bits.GO_DONE // bit 2, shadows bit in ADCON0bits
1096 #define CHS0 ADCON0bits.CHS0 // bit 3
1097 #define CHS1 ADCON0bits.CHS1 // bit 4
1098 #define CHS2 ADCON0bits.CHS2 // bit 5
1099 #define ADCS0 ADCON0bits.ADCS0 // bit 6
1100 #define ADCS1 ADCON0bits.ADCS1 // bit 7
1102 #define PCFG0 ADCON1bits.PCFG0 // bit 0
1103 #define PCFG1 ADCON1bits.PCFG1 // bit 1
1104 #define PCFG2 ADCON1bits.PCFG2 // bit 2
1105 #define PCFG3 ADCON1bits.PCFG3 // bit 3
1106 #define ADCS2 ADCON1bits.ADCS2 // bit 6
1107 #define ADFM ADCON1bits.ADFM // bit 7
1109 #define CCP1M0 CCP1CONbits.CCP1M0 // bit 0
1110 #define CCP1M1 CCP1CONbits.CCP1M1 // bit 1
1111 #define CCP1M2 CCP1CONbits.CCP1M2 // bit 2
1112 #define CCP1M3 CCP1CONbits.CCP1M3 // bit 3
1113 #define CCP1Y CCP1CONbits.CCP1Y // bit 4
1114 #define CCP1X CCP1CONbits.CCP1X // bit 5
1116 #define RD EECON1bits.RD // bit 0
1117 #define WR EECON1bits.WR // bit 1
1118 #define WREN EECON1bits.WREN // bit 2
1119 #define WRERR EECON1bits.WRERR // bit 3
1120 #define FREE EECON1bits.FREE // bit 4
1121 #define EEPGD EECON1bits.EEPGD // bit 7
1123 #define RBIF INTCONbits.RBIF // bit 0
1124 #define INTF INTCONbits.INTF // bit 1
1125 #define TMR0IF INTCONbits.TMR0IF // bit 2
1126 #define RBIE INTCONbits.RBIE // bit 3
1127 #define INTE INTCONbits.INTE // bit 4
1128 #define TMR0IE INTCONbits.TMR0IE // bit 5
1129 #define PEIE INTCONbits.PEIE // bit 6
1130 #define GIE INTCONbits.GIE // bit 7
1132 #define PS0 OPTION_REGbits.PS0 // bit 0
1133 #define PS1 OPTION_REGbits.PS1 // bit 1
1134 #define PS2 OPTION_REGbits.PS2 // bit 2
1135 #define PSA OPTION_REGbits.PSA // bit 3
1136 #define T0SE OPTION_REGbits.T0SE // bit 4
1137 #define T0CS OPTION_REGbits.T0CS // bit 5
1138 #define INTEDG OPTION_REGbits.INTEDG // bit 6
1139 #define NOT_RBPU OPTION_REGbits.NOT_RBPU // bit 7
1141 #define IOFS OSCCONbits.IOFS // bit 2
1142 #define IRCF0 OSCCONbits.IRCF0 // bit 4
1143 #define IRCF1 OSCCONbits.IRCF1 // bit 5
1144 #define IRCF2 OSCCONbits.IRCF2 // bit 6
1146 #define TUN0 OSCTUNEbits.TUN0 // bit 0
1147 #define TUN1 OSCTUNEbits.TUN1 // bit 1
1148 #define TUN2 OSCTUNEbits.TUN2 // bit 2
1149 #define TUN3 OSCTUNEbits.TUN3 // bit 3
1150 #define TUN4 OSCTUNEbits.TUN4 // bit 4
1151 #define TUN5 OSCTUNEbits.TUN5 // bit 5
1153 #define NOT_BOR PCONbits.NOT_BOR // bit 0, shadows bit in PCONbits
1154 #define NOT_BO PCONbits.NOT_BO // bit 0, shadows bit in PCONbits
1155 #define NOT_POR PCONbits.NOT_POR // bit 1
1157 #define TMR1IE PIE1bits.TMR1IE // bit 0
1158 #define TMR2IE PIE1bits.TMR2IE // bit 1
1159 #define CCP1IE PIE1bits.CCP1IE // bit 2
1160 #define SSPIE PIE1bits.SSPIE // bit 3
1161 #define ADIE PIE1bits.ADIE // bit 6
1163 #define EEIE PIE2bits.EEIE // bit 4
1165 #define TMR1IF PIR1bits.TMR1IF // bit 0
1166 #define TMR2IF PIR1bits.TMR2IF // bit 1
1167 #define CCP1IF PIR1bits.CCP1IF // bit 2
1168 #define SSPIF PIR1bits.SSPIF // bit 3
1169 #define ADIF PIR1bits.ADIF // bit 6
1171 #define EEIF PIR2bits.EEIF // bit 4
1173 #define RA0 PORTAbits.RA0 // bit 0
1174 #define RA1 PORTAbits.RA1 // bit 1
1175 #define RA2 PORTAbits.RA2 // bit 2
1176 #define RA3 PORTAbits.RA3 // bit 3
1177 #define RA4 PORTAbits.RA4 // bit 4
1178 #define RA5 PORTAbits.RA5 // bit 5
1179 #define RA6 PORTAbits.RA6 // bit 6
1180 #define RA7 PORTAbits.RA7 // bit 7
1182 #define RB0 PORTBbits.RB0 // bit 0
1183 #define RB1 PORTBbits.RB1 // bit 1
1184 #define RB2 PORTBbits.RB2 // bit 2
1185 #define RB3 PORTBbits.RB3 // bit 3
1186 #define RB4 PORTBbits.RB4 // bit 4
1187 #define RB5 PORTBbits.RB5 // bit 5
1188 #define RB6 PORTBbits.RB6 // bit 6
1189 #define RB7 PORTBbits.RB7 // bit 7
1191 #define SSPM0 SSPCONbits.SSPM0 // bit 0
1192 #define SSPM1 SSPCONbits.SSPM1 // bit 1
1193 #define SSPM2 SSPCONbits.SSPM2 // bit 2
1194 #define SSPM3 SSPCONbits.SSPM3 // bit 3
1195 #define CKP SSPCONbits.CKP // bit 4
1196 #define SSPEN SSPCONbits.SSPEN // bit 5
1197 #define SSPOV SSPCONbits.SSPOV // bit 6
1198 #define WCOL SSPCONbits.WCOL // bit 7
1200 #define BF SSPSTATbits.BF // bit 0
1201 #define UA SSPSTATbits.UA // bit 1
1202 #define R_NOT_W SSPSTATbits.R_NOT_W // bit 2, shadows bit in SSPSTATbits
1203 #define R SSPSTATbits.R // bit 2, shadows bit in SSPSTATbits
1204 #define I2C_READ SSPSTATbits.I2C_READ // bit 2, shadows bit in SSPSTATbits
1205 #define NOT_W SSPSTATbits.NOT_W // bit 2, shadows bit in SSPSTATbits
1206 #define NOT_WRITE SSPSTATbits.NOT_WRITE // bit 2, shadows bit in SSPSTATbits
1207 #define R_W SSPSTATbits.R_W // bit 2, shadows bit in SSPSTATbits
1208 #define READ_WRITE SSPSTATbits.READ_WRITE // bit 2, shadows bit in SSPSTATbits
1209 #define S SSPSTATbits.S // bit 3, shadows bit in SSPSTATbits
1210 #define I2C_START SSPSTATbits.I2C_START // bit 3, shadows bit in SSPSTATbits
1211 #define P SSPSTATbits.P // bit 4, shadows bit in SSPSTATbits
1212 #define I2C_STOP SSPSTATbits.I2C_STOP // bit 4, shadows bit in SSPSTATbits
1213 #define D_NOT_A SSPSTATbits.D_NOT_A // bit 5, shadows bit in SSPSTATbits
1214 #define D SSPSTATbits.D // bit 5, shadows bit in SSPSTATbits
1215 #define I2C_DATA SSPSTATbits.I2C_DATA // bit 5, shadows bit in SSPSTATbits
1216 #define NOT_A SSPSTATbits.NOT_A // bit 5, shadows bit in SSPSTATbits
1217 #define NOT_ADDRESS SSPSTATbits.NOT_ADDRESS // bit 5, shadows bit in SSPSTATbits
1218 #define D_A SSPSTATbits.D_A // bit 5, shadows bit in SSPSTATbits
1219 #define DATA_ADDRESS SSPSTATbits.DATA_ADDRESS // bit 5, shadows bit in SSPSTATbits
1220 #define CKE SSPSTATbits.CKE // bit 6
1221 #define SMP SSPSTATbits.SMP // bit 7
1223 #define C STATUSbits.C // bit 0
1224 #define DC STATUSbits.DC // bit 1
1225 #define Z STATUSbits.Z // bit 2
1226 #define NOT_PD STATUSbits.NOT_PD // bit 3
1227 #define NOT_TO STATUSbits.NOT_TO // bit 4
1228 #define RP0 STATUSbits.RP0 // bit 5
1229 #define RP1 STATUSbits.RP1 // bit 6
1230 #define IRP STATUSbits.IRP // bit 7
1232 #define TMR1ON T1CONbits.TMR1ON // bit 0
1233 #define TMR1CS T1CONbits.TMR1CS // bit 1
1234 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2, shadows bit in T1CONbits
1235 #define T1INSYNC T1CONbits.T1INSYNC // bit 2, shadows bit in T1CONbits
1236 #define T1OSCEN T1CONbits.T1OSCEN // bit 3
1237 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
1238 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
1240 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
1241 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
1242 #define TMR2ON T2CONbits.TMR2ON // bit 2
1243 #define TOUTPS0 T2CONbits.TOUTPS0 // bit 3
1244 #define TOUTPS1 T2CONbits.TOUTPS1 // bit 4
1245 #define TOUTPS2 T2CONbits.TOUTPS2 // bit 5
1246 #define TOUTPS3 T2CONbits.TOUTPS3 // bit 6
1248 #define TRISA0 TRISAbits.TRISA0 // bit 0
1249 #define TRISA1 TRISAbits.TRISA1 // bit 1
1250 #define TRISA2 TRISAbits.TRISA2 // bit 2
1251 #define TRISA3 TRISAbits.TRISA3 // bit 3
1252 #define TRISA4 TRISAbits.TRISA4 // bit 4
1253 #define TRISA5 TRISAbits.TRISA5 // bit 5
1254 #define TRISA6 TRISAbits.TRISA6 // bit 6
1255 #define TRISA7 TRISAbits.TRISA7 // bit 7
1257 #define TRISB0 TRISBbits.TRISB0 // bit 0
1258 #define TRISB1 TRISBbits.TRISB1 // bit 1
1259 #define TRISB2 TRISBbits.TRISB2 // bit 2
1260 #define TRISB3 TRISBbits.TRISB3 // bit 3
1261 #define TRISB4 TRISBbits.TRISB4 // bit 4
1262 #define TRISB5 TRISBbits.TRISB5 // bit 5
1263 #define TRISB6 TRISBbits.TRISB6 // bit 6
1264 #define TRISB7 TRISBbits.TRISB7 // bit 7
1266 #endif // #ifndef NO_BIT_DEFINES
1268 #endif // #ifndef __PIC16F819_H__