2 * This declarations of the PIC16LF1709 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:12 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16LF1709_H__
26 #define __PIC16LF1709_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTB_ADDR 0x000D
52 #define PORTC_ADDR 0x000E
53 #define PIR1_ADDR 0x0011
54 #define PIR2_ADDR 0x0012
55 #define PIR3_ADDR 0x0013
56 #define TMR0_ADDR 0x0015
57 #define TMR1_ADDR 0x0016
58 #define TMR1L_ADDR 0x0016
59 #define TMR1H_ADDR 0x0017
60 #define T1CON_ADDR 0x0018
61 #define T1GCON_ADDR 0x0019
62 #define TMR2_ADDR 0x001A
63 #define PR2_ADDR 0x001B
64 #define T2CON_ADDR 0x001C
65 #define TRISA_ADDR 0x008C
66 #define TRISB_ADDR 0x008D
67 #define TRISC_ADDR 0x008E
68 #define PIE1_ADDR 0x0091
69 #define PIE2_ADDR 0x0092
70 #define PIE3_ADDR 0x0093
71 #define OPTION_REG_ADDR 0x0095
72 #define PCON_ADDR 0x0096
73 #define WDTCON_ADDR 0x0097
74 #define OSCTUNE_ADDR 0x0098
75 #define OSCCON_ADDR 0x0099
76 #define OSCSTAT_ADDR 0x009A
77 #define ADRES_ADDR 0x009B
78 #define ADRESL_ADDR 0x009B
79 #define ADRESH_ADDR 0x009C
80 #define ADCON0_ADDR 0x009D
81 #define ADCON1_ADDR 0x009E
82 #define ADCON2_ADDR 0x009F
83 #define LATA_ADDR 0x010C
84 #define LATB_ADDR 0x010D
85 #define LATC_ADDR 0x010E
86 #define CM1CON0_ADDR 0x0111
87 #define CM1CON1_ADDR 0x0112
88 #define CM2CON0_ADDR 0x0113
89 #define CM2CON1_ADDR 0x0114
90 #define CMOUT_ADDR 0x0115
91 #define BORCON_ADDR 0x0116
92 #define FVRCON_ADDR 0x0117
93 #define DAC1CON0_ADDR 0x0118
94 #define DAC1CON1_ADDR 0x0119
95 #define ZCD1CON_ADDR 0x011C
96 #define ANSELA_ADDR 0x018C
97 #define ANSELB_ADDR 0x018D
98 #define ANSELC_ADDR 0x018E
99 #define PMADR_ADDR 0x0191
100 #define PMADRL_ADDR 0x0191
101 #define PMADRH_ADDR 0x0192
102 #define PMDAT_ADDR 0x0193
103 #define PMDATL_ADDR 0x0193
104 #define PMDATH_ADDR 0x0194
105 #define PMCON1_ADDR 0x0195
106 #define PMCON2_ADDR 0x0196
107 #define RC1REG_ADDR 0x0199
108 #define RCREG_ADDR 0x0199
109 #define RCREG1_ADDR 0x0199
110 #define TX1REG_ADDR 0x019A
111 #define TXREG_ADDR 0x019A
112 #define TXREG1_ADDR 0x019A
113 #define SP1BRG_ADDR 0x019B
114 #define SP1BRGL_ADDR 0x019B
115 #define SPBRG_ADDR 0x019B
116 #define SPBRG1_ADDR 0x019B
117 #define SPBRGL_ADDR 0x019B
118 #define SP1BRGH_ADDR 0x019C
119 #define SPBRGH_ADDR 0x019C
120 #define SPBRGH1_ADDR 0x019C
121 #define RC1STA_ADDR 0x019D
122 #define RCSTA_ADDR 0x019D
123 #define RCSTA1_ADDR 0x019D
124 #define TX1STA_ADDR 0x019E
125 #define TXSTA_ADDR 0x019E
126 #define TXSTA1_ADDR 0x019E
127 #define BAUD1CON_ADDR 0x019F
128 #define BAUDCON_ADDR 0x019F
129 #define BAUDCON1_ADDR 0x019F
130 #define BAUDCTL_ADDR 0x019F
131 #define BAUDCTL1_ADDR 0x019F
132 #define WPUA_ADDR 0x020C
133 #define WPUB_ADDR 0x020D
134 #define WPUC_ADDR 0x020E
135 #define SSP1BUF_ADDR 0x0211
136 #define SSPBUF_ADDR 0x0211
137 #define SSP1ADD_ADDR 0x0212
138 #define SSPADD_ADDR 0x0212
139 #define SSP1MSK_ADDR 0x0213
140 #define SSPMSK_ADDR 0x0213
141 #define SSP1STAT_ADDR 0x0214
142 #define SSPSTAT_ADDR 0x0214
143 #define SSP1CON_ADDR 0x0215
144 #define SSP1CON1_ADDR 0x0215
145 #define SSPCON_ADDR 0x0215
146 #define SSPCON1_ADDR 0x0215
147 #define SSP1CON2_ADDR 0x0216
148 #define SSPCON2_ADDR 0x0216
149 #define SSP1CON3_ADDR 0x0217
150 #define SSPCON3_ADDR 0x0217
151 #define ODCONA_ADDR 0x028C
152 #define ODCONB_ADDR 0x028D
153 #define ODCONC_ADDR 0x028E
154 #define CCPR1_ADDR 0x0291
155 #define CCPR1L_ADDR 0x0291
156 #define CCPR1H_ADDR 0x0292
157 #define CCP1CON_ADDR 0x0293
158 #define ECCP1CON_ADDR 0x0293
159 #define CCPR2_ADDR 0x0298
160 #define CCPR2L_ADDR 0x0298
161 #define CCPR2H_ADDR 0x0299
162 #define CCP2CON_ADDR 0x029A
163 #define ECCP2CON_ADDR 0x029A
164 #define CCPTMRS_ADDR 0x029E
165 #define SLRCONA_ADDR 0x030C
166 #define SLRCONB_ADDR 0x030D
167 #define SLRCONC_ADDR 0x030E
168 #define INLVLA_ADDR 0x038C
169 #define INLVLB_ADDR 0x038D
170 #define INLVLC_ADDR 0x038E
171 #define IOCAP_ADDR 0x0391
172 #define IOCAN_ADDR 0x0392
173 #define IOCAF_ADDR 0x0393
174 #define IOCBP_ADDR 0x0394
175 #define IOCBN_ADDR 0x0395
176 #define IOCBF_ADDR 0x0396
177 #define IOCCP_ADDR 0x0397
178 #define IOCCN_ADDR 0x0398
179 #define IOCCF_ADDR 0x0399
180 #define TMR4_ADDR 0x0415
181 #define PR4_ADDR 0x0416
182 #define T4CON_ADDR 0x0417
183 #define TMR6_ADDR 0x041C
184 #define PR6_ADDR 0x041D
185 #define T6CON_ADDR 0x041E
186 #define OPA1CON_ADDR 0x0511
187 #define OPA2CON_ADDR 0x0515
188 #define PWM3DCL_ADDR 0x0617
189 #define PWM3DCH_ADDR 0x0618
190 #define PWM3CON_ADDR 0x0619
191 #define PWM3CON0_ADDR 0x0619
192 #define PWM4DCL_ADDR 0x061A
193 #define PWM4DCH_ADDR 0x061B
194 #define PWM4CON_ADDR 0x061C
195 #define PWM4CON0_ADDR 0x061C
196 #define COG1PHR_ADDR 0x0691
197 #define COG1PHF_ADDR 0x0692
198 #define COG1BLKR_ADDR 0x0693
199 #define COG1BLKF_ADDR 0x0694
200 #define COG1DBR_ADDR 0x0695
201 #define COG1DBF_ADDR 0x0696
202 #define COG1CON0_ADDR 0x0697
203 #define COG1CON1_ADDR 0x0698
204 #define COG1RIS_ADDR 0x0699
205 #define COG1RSIM_ADDR 0x069A
206 #define COG1FIS_ADDR 0x069B
207 #define COG1FSIM_ADDR 0x069C
208 #define COG1ASD0_ADDR 0x069D
209 #define COG1ASD1_ADDR 0x069E
210 #define COG1STR_ADDR 0x069F
211 #define PPSLOCK_ADDR 0x0E0F
212 #define INTPPS_ADDR 0x0E10
213 #define T0CKIPPS_ADDR 0x0E11
214 #define T1CKIPPS_ADDR 0x0E12
215 #define T1GPPS_ADDR 0x0E13
216 #define CCP1PPS_ADDR 0x0E14
217 #define CCP2PPS_ADDR 0x0E15
218 #define COGINPPS_ADDR 0x0E17
219 #define SSPCLKPPS_ADDR 0x0E20
220 #define SSPDATPPS_ADDR 0x0E21
221 #define SSPSSPPS_ADDR 0x0E22
222 #define RXPPS_ADDR 0x0E24
223 #define CKPPS_ADDR 0x0E25
224 #define CLCIN0PPS_ADDR 0x0E28
225 #define CLCIN1PPS_ADDR 0x0E29
226 #define CLCIN2PPS_ADDR 0x0E2A
227 #define CLCIN3PPS_ADDR 0x0E2B
228 #define RA0PPS_ADDR 0x0E90
229 #define RA1PPS_ADDR 0x0E91
230 #define RA2PPS_ADDR 0x0E92
231 #define RA4PPS_ADDR 0x0E94
232 #define RA5PPS_ADDR 0x0E95
233 #define RB4PPS_ADDR 0x0E9C
234 #define RB5PPS_ADDR 0x0E9D
235 #define RB6PPS_ADDR 0x0E9E
236 #define RB7PPS_ADDR 0x0E9F
237 #define RC0PPS_ADDR 0x0EA0
238 #define RC1PPS_ADDR 0x0EA1
239 #define RC2PPS_ADDR 0x0EA2
240 #define RC3PPS_ADDR 0x0EA3
241 #define RC4PPS_ADDR 0x0EA4
242 #define RC5PPS_ADDR 0x0EA5
243 #define RC6PPS_ADDR 0x0EA6
244 #define RC7PPS_ADDR 0x0EA7
245 #define CLCDATA_ADDR 0x0F0F
246 #define CLC1CON_ADDR 0x0F10
247 #define CLC1POL_ADDR 0x0F11
248 #define CLC1SEL0_ADDR 0x0F12
249 #define CLC1SEL1_ADDR 0x0F13
250 #define CLC1SEL2_ADDR 0x0F14
251 #define CLC1SEL3_ADDR 0x0F15
252 #define CLC1GLS0_ADDR 0x0F16
253 #define CLC1GLS1_ADDR 0x0F17
254 #define CLC1GLS2_ADDR 0x0F18
255 #define CLC1GLS3_ADDR 0x0F19
256 #define CLC2CON_ADDR 0x0F1A
257 #define CLC2POL_ADDR 0x0F1B
258 #define CLC2SEL0_ADDR 0x0F1C
259 #define CLC2SEL1_ADDR 0x0F1D
260 #define CLC2SEL2_ADDR 0x0F1E
261 #define CLC2SEL3_ADDR 0x0F1F
262 #define CLC2GLS0_ADDR 0x0F20
263 #define CLC2GLS1_ADDR 0x0F21
264 #define CLC2GLS2_ADDR 0x0F22
265 #define CLC2GLS3_ADDR 0x0F23
266 #define CLC3CON_ADDR 0x0F24
267 #define CLC3POL_ADDR 0x0F25
268 #define CLC3SEL0_ADDR 0x0F26
269 #define CLC3SEL1_ADDR 0x0F27
270 #define CLC3SEL2_ADDR 0x0F28
271 #define CLC3SEL3_ADDR 0x0F29
272 #define CLC3GLS0_ADDR 0x0F2A
273 #define CLC3GLS1_ADDR 0x0F2B
274 #define CLC3GLS2_ADDR 0x0F2C
275 #define CLC3GLS3_ADDR 0x0F2D
276 #define ICDBK0H_ADDR 0x0F9E
277 #define STATUS_SHAD_ADDR 0x0FE4
278 #define WREG_SHAD_ADDR 0x0FE5
279 #define BSR_SHAD_ADDR 0x0FE6
280 #define PCLATH_SHAD_ADDR 0x0FE7
281 #define FSR0L_SHAD_ADDR 0x0FE8
282 #define FSR0H_SHAD_ADDR 0x0FE9
283 #define FSR1L_SHAD_ADDR 0x0FEA
284 #define FSR1H_SHAD_ADDR 0x0FEB
285 #define STKPTR_ADDR 0x0FED
286 #define TOSL_ADDR 0x0FEE
287 #define TOSH_ADDR 0x0FEF
289 #endif // #ifndef NO_ADDR_DEFINES
291 //==============================================================================
293 // Register Definitions
295 //==============================================================================
297 extern __at(0x0000) __sfr INDF0
;
298 extern __at(0x0001) __sfr INDF1
;
299 extern __at(0x0002) __sfr PCL
;
301 //==============================================================================
304 extern __at(0x0003) __sfr STATUS
;
318 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
326 //==============================================================================
328 extern __at(0x0004) __sfr FSR0
;
329 extern __at(0x0004) __sfr FSR0L
;
330 extern __at(0x0005) __sfr FSR0H
;
331 extern __at(0x0006) __sfr FSR1
;
332 extern __at(0x0006) __sfr FSR1L
;
333 extern __at(0x0007) __sfr FSR1H
;
335 //==============================================================================
338 extern __at(0x0008) __sfr BSR
;
361 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
369 //==============================================================================
371 extern __at(0x0009) __sfr WREG
;
372 extern __at(0x000A) __sfr PCLATH
;
374 //==============================================================================
377 extern __at(0x000B) __sfr INTCON
;
406 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
419 //==============================================================================
422 //==============================================================================
425 extern __at(0x000C) __sfr PORTA
;
448 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
457 //==============================================================================
460 //==============================================================================
463 extern __at(0x000D) __sfr PORTB
;
477 extern __at(0x000D) volatile __PORTBbits_t PORTBbits
;
484 //==============================================================================
487 //==============================================================================
490 extern __at(0x000E) __sfr PORTC
;
504 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
515 //==============================================================================
518 //==============================================================================
521 extern __at(0x0011) __sfr PIR1
;
534 unsigned TMR1GIF
: 1;
550 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
560 #define _TMR1GIF 0x80
562 //==============================================================================
565 //==============================================================================
568 extern __at(0x0012) __sfr PIR2
;
582 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
592 //==============================================================================
595 //==============================================================================
598 extern __at(0x0013) __sfr PIR3
;
612 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
620 //==============================================================================
622 extern __at(0x0015) __sfr TMR0
;
623 extern __at(0x0016) __sfr TMR1
;
624 extern __at(0x0016) __sfr TMR1L
;
625 extern __at(0x0017) __sfr TMR1H
;
627 //==============================================================================
630 extern __at(0x0018) __sfr T1CON
;
638 unsigned NOT_T1SYNC
: 1;
639 unsigned T1OSCEN
: 1;
640 unsigned T1CKPS0
: 1;
641 unsigned T1CKPS1
: 1;
642 unsigned TMR1CS0
: 1;
643 unsigned TMR1CS1
: 1;
660 extern __at(0x0018) volatile __T1CONbits_t T1CONbits
;
663 #define _NOT_T1SYNC 0x04
664 #define _T1OSCEN 0x08
665 #define _T1CKPS0 0x10
666 #define _T1CKPS1 0x20
667 #define _TMR1CS0 0x40
668 #define _TMR1CS1 0x80
670 //==============================================================================
673 //==============================================================================
676 extern __at(0x0019) __sfr T1GCON
;
685 unsigned T1GGO_NOT_DONE
: 1;
699 extern __at(0x0019) volatile __T1GCONbits_t T1GCONbits
;
704 #define _T1GGO_NOT_DONE 0x08
710 //==============================================================================
712 extern __at(0x001A) __sfr TMR2
;
713 extern __at(0x001B) __sfr PR2
;
715 //==============================================================================
718 extern __at(0x001C) __sfr T2CON
;
724 unsigned T2CKPS0
: 1;
725 unsigned T2CKPS1
: 1;
727 unsigned T2OUTPS0
: 1;
728 unsigned T2OUTPS1
: 1;
729 unsigned T2OUTPS2
: 1;
730 unsigned T2OUTPS3
: 1;
743 unsigned T2OUTPS
: 4;
748 extern __at(0x001C) volatile __T2CONbits_t T2CONbits
;
750 #define _T2CKPS0 0x01
751 #define _T2CKPS1 0x02
753 #define _T2OUTPS0 0x08
754 #define _T2OUTPS1 0x10
755 #define _T2OUTPS2 0x20
756 #define _T2OUTPS3 0x40
758 //==============================================================================
761 //==============================================================================
764 extern __at(0x008C) __sfr TRISA
;
778 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
786 //==============================================================================
789 //==============================================================================
792 extern __at(0x008D) __sfr TRISB
;
806 extern __at(0x008D) volatile __TRISBbits_t TRISBbits
;
813 //==============================================================================
816 //==============================================================================
819 extern __at(0x008E) __sfr TRISC
;
833 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
844 //==============================================================================
847 //==============================================================================
850 extern __at(0x0091) __sfr PIE1
;
863 unsigned TMR1GIE
: 1;
879 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
889 #define _TMR1GIE 0x80
891 //==============================================================================
894 //==============================================================================
897 extern __at(0x0092) __sfr PIE2
;
911 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
921 //==============================================================================
924 //==============================================================================
927 extern __at(0x0093) __sfr PIE3
;
941 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
943 #define _PIE3_CLC1IE 0x01
944 #define _PIE3_CLC2IE 0x02
945 #define _PIE3_CLC3IE 0x04
946 #define _PIE3_CCP1IE 0x08
947 #define _PIE3_ZCDIE 0x10
948 #define _PIE3_COGIE 0x20
950 //==============================================================================
953 //==============================================================================
956 extern __at(0x0095) __sfr OPTION_REG
;
969 unsigned NOT_WPUEN
: 1;
989 } __OPTION_REGbits_t
;
991 extern __at(0x0095) volatile __OPTION_REGbits_t OPTION_REGbits
;
1001 #define _INTEDG 0x40
1002 #define _NOT_WPUEN 0x80
1004 //==============================================================================
1007 //==============================================================================
1010 extern __at(0x0096) __sfr PCON
;
1014 unsigned NOT_BOR
: 1;
1015 unsigned NOT_POR
: 1;
1016 unsigned NOT_RI
: 1;
1017 unsigned NOT_RMCLR
: 1;
1018 unsigned NOT_RWDT
: 1;
1020 unsigned STKUNF
: 1;
1021 unsigned STKOVF
: 1;
1024 extern __at(0x0096) volatile __PCONbits_t PCONbits
;
1026 #define _NOT_BOR 0x01
1027 #define _NOT_POR 0x02
1028 #define _NOT_RI 0x04
1029 #define _NOT_RMCLR 0x08
1030 #define _NOT_RWDT 0x10
1031 #define _STKUNF 0x40
1032 #define _STKOVF 0x80
1034 //==============================================================================
1037 //==============================================================================
1040 extern __at(0x0097) __sfr WDTCON
;
1046 unsigned SWDTEN
: 1;
1047 unsigned WDTPS0
: 1;
1048 unsigned WDTPS1
: 1;
1049 unsigned WDTPS2
: 1;
1050 unsigned WDTPS3
: 1;
1051 unsigned WDTPS4
: 1;
1064 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1066 #define _SWDTEN 0x01
1067 #define _WDTPS0 0x02
1068 #define _WDTPS1 0x04
1069 #define _WDTPS2 0x08
1070 #define _WDTPS3 0x10
1071 #define _WDTPS4 0x20
1073 //==============================================================================
1076 //==============================================================================
1079 extern __at(0x0098) __sfr OSCTUNE
;
1102 extern __at(0x0098) volatile __OSCTUNEbits_t OSCTUNEbits
;
1111 //==============================================================================
1114 //==============================================================================
1117 extern __at(0x0099) __sfr OSCCON
;
1130 unsigned SPLLEN
: 1;
1147 extern __at(0x0099) volatile __OSCCONbits_t OSCCONbits
;
1155 #define _SPLLEN 0x80
1157 //==============================================================================
1160 //==============================================================================
1163 extern __at(0x009A) __sfr OSCSTAT
;
1167 unsigned HFIOFS
: 1;
1168 unsigned LFIOFR
: 1;
1169 unsigned MFIOFR
: 1;
1170 unsigned HFIOFL
: 1;
1171 unsigned HFIOFR
: 1;
1177 extern __at(0x009A) volatile __OSCSTATbits_t OSCSTATbits
;
1179 #define _HFIOFS 0x01
1180 #define _LFIOFR 0x02
1181 #define _MFIOFR 0x04
1182 #define _HFIOFL 0x08
1183 #define _HFIOFR 0x10
1188 //==============================================================================
1190 extern __at(0x009B) __sfr ADRES
;
1191 extern __at(0x009B) __sfr ADRESL
;
1192 extern __at(0x009C) __sfr ADRESH
;
1194 //==============================================================================
1197 extern __at(0x009D) __sfr ADCON0
;
1204 unsigned GO_NOT_DONE
: 1;
1245 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1248 #define _GO_NOT_DONE 0x02
1257 //==============================================================================
1260 //==============================================================================
1263 extern __at(0x009E) __sfr ADCON1
;
1269 unsigned ADPREF0
: 1;
1270 unsigned ADPREF1
: 1;
1271 unsigned ADNREF
: 1;
1281 unsigned ADPREF
: 2;
1286 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1288 #define _ADPREF0 0x01
1289 #define _ADPREF1 0x02
1290 #define _ADNREF 0x04
1293 //==============================================================================
1296 //==============================================================================
1299 extern __at(0x009F) __sfr ADCON2
;
1309 unsigned TRIGSEL0
: 1;
1310 unsigned TRIGSEL1
: 1;
1311 unsigned TRIGSEL2
: 1;
1312 unsigned TRIGSEL3
: 1;
1318 unsigned TRIGSEL
: 4;
1322 extern __at(0x009F) volatile __ADCON2bits_t ADCON2bits
;
1324 #define _TRIGSEL0 0x10
1325 #define _TRIGSEL1 0x20
1326 #define _TRIGSEL2 0x40
1327 #define _TRIGSEL3 0x80
1329 //==============================================================================
1332 //==============================================================================
1335 extern __at(0x010C) __sfr LATA
;
1349 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1357 //==============================================================================
1360 //==============================================================================
1363 extern __at(0x010D) __sfr LATB
;
1377 extern __at(0x010D) volatile __LATBbits_t LATBbits
;
1384 //==============================================================================
1387 //==============================================================================
1390 extern __at(0x010E) __sfr LATC
;
1404 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1415 //==============================================================================
1418 //==============================================================================
1421 extern __at(0x0111) __sfr CM1CON0
;
1425 unsigned C1SYNC
: 1;
1435 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1437 #define _C1SYNC 0x01
1445 //==============================================================================
1448 //==============================================================================
1451 extern __at(0x0112) __sfr CM1CON1
;
1457 unsigned C1NCH0
: 1;
1458 unsigned C1NCH1
: 1;
1459 unsigned C1NCH2
: 1;
1460 unsigned C1PCH0
: 1;
1461 unsigned C1PCH1
: 1;
1462 unsigned C1PCH2
: 1;
1463 unsigned C1INTN
: 1;
1464 unsigned C1INTP
: 1;
1481 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1483 #define _C1NCH0 0x01
1484 #define _C1NCH1 0x02
1485 #define _C1NCH2 0x04
1486 #define _C1PCH0 0x08
1487 #define _C1PCH1 0x10
1488 #define _C1PCH2 0x20
1489 #define _C1INTN 0x40
1490 #define _C1INTP 0x80
1492 //==============================================================================
1495 //==============================================================================
1498 extern __at(0x0113) __sfr CM2CON0
;
1502 unsigned C2SYNC
: 1;
1512 extern __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits
;
1514 #define _C2SYNC 0x01
1522 //==============================================================================
1525 //==============================================================================
1528 extern __at(0x0114) __sfr CM2CON1
;
1534 unsigned C2NCH0
: 1;
1535 unsigned C2NCH1
: 1;
1536 unsigned C2NCH2
: 1;
1537 unsigned C2PCH0
: 1;
1538 unsigned C2PCH1
: 1;
1539 unsigned C2PCH2
: 1;
1540 unsigned C2INTN
: 1;
1541 unsigned C2INTP
: 1;
1558 extern __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits
;
1560 #define _C2NCH0 0x01
1561 #define _C2NCH1 0x02
1562 #define _C2NCH2 0x04
1563 #define _C2PCH0 0x08
1564 #define _C2PCH1 0x10
1565 #define _C2PCH2 0x20
1566 #define _C2INTN 0x40
1567 #define _C2INTP 0x80
1569 //==============================================================================
1572 //==============================================================================
1575 extern __at(0x0115) __sfr CMOUT
;
1579 unsigned MC1OUT
: 1;
1580 unsigned MC2OUT
: 1;
1589 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1591 #define _MC1OUT 0x01
1592 #define _MC2OUT 0x02
1594 //==============================================================================
1597 //==============================================================================
1600 extern __at(0x0116) __sfr BORCON
;
1604 unsigned BORRDY
: 1;
1611 unsigned SBOREN
: 1;
1614 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1616 #define _BORRDY 0x01
1618 #define _SBOREN 0x80
1620 //==============================================================================
1623 //==============================================================================
1626 extern __at(0x0117) __sfr FVRCON
;
1632 unsigned ADFVR0
: 1;
1633 unsigned ADFVR1
: 1;
1634 unsigned CDAFVR0
: 1;
1635 unsigned CDAFVR1
: 1;
1638 unsigned FVRRDY
: 1;
1651 unsigned CDAFVR
: 2;
1656 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1658 #define _ADFVR0 0x01
1659 #define _ADFVR1 0x02
1660 #define _CDAFVR0 0x04
1661 #define _CDAFVR1 0x08
1664 #define _FVRRDY 0x40
1667 //==============================================================================
1670 //==============================================================================
1673 extern __at(0x0118) __sfr DAC1CON0
;
1679 unsigned DAC1NSS
: 1;
1681 unsigned DAC1PSS0
: 1;
1682 unsigned DAC1PSS1
: 1;
1683 unsigned DAC1OE2
: 1;
1684 unsigned DAC1OE1
: 1;
1686 unsigned DAC1EN
: 1;
1691 unsigned DACNSS
: 1;
1693 unsigned DACPSS0
: 1;
1694 unsigned DACPSS1
: 1;
1695 unsigned DACOE0
: 1;
1696 unsigned DACOE1
: 1;
1704 unsigned DACPSS
: 2;
1711 unsigned DAC1PSS
: 2;
1723 extern __at(0x0118) volatile __DAC1CON0bits_t DAC1CON0bits
;
1725 #define _DAC1NSS 0x01
1726 #define _DACNSS 0x01
1727 #define _DAC1PSS0 0x04
1728 #define _DACPSS0 0x04
1729 #define _DAC1PSS1 0x08
1730 #define _DACPSS1 0x08
1731 #define _DAC1OE2 0x10
1732 #define _DACOE0 0x10
1733 #define _DAC1OE1 0x20
1734 #define _DACOE1 0x20
1735 #define _DAC1EN 0x80
1738 //==============================================================================
1741 //==============================================================================
1744 extern __at(0x0119) __sfr DAC1CON1
;
1750 unsigned DAC1R0
: 1;
1751 unsigned DAC1R1
: 1;
1752 unsigned DAC1R2
: 1;
1753 unsigned DAC1R3
: 1;
1754 unsigned DAC1R4
: 1;
1755 unsigned DAC1R5
: 1;
1756 unsigned DAC1R6
: 1;
1757 unsigned DAC1R7
: 1;
1773 extern __at(0x0119) volatile __DAC1CON1bits_t DAC1CON1bits
;
1775 #define _DAC1R0 0x01
1777 #define _DAC1R1 0x02
1779 #define _DAC1R2 0x04
1781 #define _DAC1R3 0x08
1783 #define _DAC1R4 0x10
1785 #define _DAC1R5 0x20
1787 #define _DAC1R6 0x40
1789 #define _DAC1R7 0x80
1792 //==============================================================================
1795 //==============================================================================
1798 extern __at(0x011C) __sfr ZCD1CON
;
1802 unsigned ZCD1INTN
: 1;
1803 unsigned ZCD1INTP
: 1;
1806 unsigned ZCD1POL
: 1;
1807 unsigned ZCD1OUT
: 1;
1809 unsigned ZCD1EN
: 1;
1812 extern __at(0x011C) volatile __ZCD1CONbits_t ZCD1CONbits
;
1814 #define _ZCD1INTN 0x01
1815 #define _ZCD1INTP 0x02
1816 #define _ZCD1POL 0x10
1817 #define _ZCD1OUT 0x20
1818 #define _ZCD1EN 0x80
1820 //==============================================================================
1823 //==============================================================================
1826 extern __at(0x018C) __sfr ANSELA
;
1840 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1848 //==============================================================================
1851 //==============================================================================
1854 extern __at(0x018D) __sfr ANSELB
;
1868 extern __at(0x018D) volatile __ANSELBbits_t ANSELBbits
;
1873 //==============================================================================
1876 //==============================================================================
1879 extern __at(0x018E) __sfr ANSELC
;
1893 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
1902 //==============================================================================
1904 extern __at(0x0191) __sfr PMADR
;
1905 extern __at(0x0191) __sfr PMADRL
;
1906 extern __at(0x0192) __sfr PMADRH
;
1907 extern __at(0x0193) __sfr PMDAT
;
1908 extern __at(0x0193) __sfr PMDATL
;
1909 extern __at(0x0194) __sfr PMDATH
;
1911 //==============================================================================
1914 extern __at(0x0195) __sfr PMCON1
;
1928 extern __at(0x0195) volatile __PMCON1bits_t PMCON1bits
;
1938 //==============================================================================
1940 extern __at(0x0196) __sfr PMCON2
;
1941 extern __at(0x0199) __sfr RC1REG
;
1942 extern __at(0x0199) __sfr RCREG
;
1943 extern __at(0x0199) __sfr RCREG1
;
1944 extern __at(0x019A) __sfr TX1REG
;
1945 extern __at(0x019A) __sfr TXREG
;
1946 extern __at(0x019A) __sfr TXREG1
;
1947 extern __at(0x019B) __sfr SP1BRG
;
1948 extern __at(0x019B) __sfr SP1BRGL
;
1949 extern __at(0x019B) __sfr SPBRG
;
1950 extern __at(0x019B) __sfr SPBRG1
;
1951 extern __at(0x019B) __sfr SPBRGL
;
1952 extern __at(0x019C) __sfr SP1BRGH
;
1953 extern __at(0x019C) __sfr SPBRGH
;
1954 extern __at(0x019C) __sfr SPBRGH1
;
1956 //==============================================================================
1959 extern __at(0x019D) __sfr RC1STA
;
1973 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
1984 //==============================================================================
1987 //==============================================================================
1990 extern __at(0x019D) __sfr RCSTA
;
2004 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
2006 #define _RCSTA_RX9D 0x01
2007 #define _RCSTA_OERR 0x02
2008 #define _RCSTA_FERR 0x04
2009 #define _RCSTA_ADDEN 0x08
2010 #define _RCSTA_CREN 0x10
2011 #define _RCSTA_SREN 0x20
2012 #define _RCSTA_RX9 0x40
2013 #define _RCSTA_SPEN 0x80
2015 //==============================================================================
2018 //==============================================================================
2021 extern __at(0x019D) __sfr RCSTA1
;
2035 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
2037 #define _RCSTA1_RX9D 0x01
2038 #define _RCSTA1_OERR 0x02
2039 #define _RCSTA1_FERR 0x04
2040 #define _RCSTA1_ADDEN 0x08
2041 #define _RCSTA1_CREN 0x10
2042 #define _RCSTA1_SREN 0x20
2043 #define _RCSTA1_RX9 0x40
2044 #define _RCSTA1_SPEN 0x80
2046 //==============================================================================
2049 //==============================================================================
2052 extern __at(0x019E) __sfr TX1STA
;
2066 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
2077 //==============================================================================
2080 //==============================================================================
2083 extern __at(0x019E) __sfr TXSTA
;
2097 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
2099 #define _TXSTA_TX9D 0x01
2100 #define _TXSTA_TRMT 0x02
2101 #define _TXSTA_BRGH 0x04
2102 #define _TXSTA_SENDB 0x08
2103 #define _TXSTA_SYNC 0x10
2104 #define _TXSTA_TXEN 0x20
2105 #define _TXSTA_TX9 0x40
2106 #define _TXSTA_CSRC 0x80
2108 //==============================================================================
2111 //==============================================================================
2114 extern __at(0x019E) __sfr TXSTA1
;
2128 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
2130 #define _TXSTA1_TX9D 0x01
2131 #define _TXSTA1_TRMT 0x02
2132 #define _TXSTA1_BRGH 0x04
2133 #define _TXSTA1_SENDB 0x08
2134 #define _TXSTA1_SYNC 0x10
2135 #define _TXSTA1_TXEN 0x20
2136 #define _TXSTA1_TX9 0x40
2137 #define _TXSTA1_CSRC 0x80
2139 //==============================================================================
2142 //==============================================================================
2145 extern __at(0x019F) __sfr BAUD1CON
;
2156 unsigned ABDOVF
: 1;
2159 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
2166 #define _ABDOVF 0x80
2168 //==============================================================================
2171 //==============================================================================
2174 extern __at(0x019F) __sfr BAUDCON
;
2185 unsigned ABDOVF
: 1;
2188 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
2190 #define _BAUDCON_ABDEN 0x01
2191 #define _BAUDCON_WUE 0x02
2192 #define _BAUDCON_BRG16 0x08
2193 #define _BAUDCON_SCKP 0x10
2194 #define _BAUDCON_RCIDL 0x40
2195 #define _BAUDCON_ABDOVF 0x80
2197 //==============================================================================
2200 //==============================================================================
2203 extern __at(0x019F) __sfr BAUDCON1
;
2214 unsigned ABDOVF
: 1;
2217 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
2219 #define _BAUDCON1_ABDEN 0x01
2220 #define _BAUDCON1_WUE 0x02
2221 #define _BAUDCON1_BRG16 0x08
2222 #define _BAUDCON1_SCKP 0x10
2223 #define _BAUDCON1_RCIDL 0x40
2224 #define _BAUDCON1_ABDOVF 0x80
2226 //==============================================================================
2229 //==============================================================================
2232 extern __at(0x019F) __sfr BAUDCTL
;
2243 unsigned ABDOVF
: 1;
2246 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
2248 #define _BAUDCTL_ABDEN 0x01
2249 #define _BAUDCTL_WUE 0x02
2250 #define _BAUDCTL_BRG16 0x08
2251 #define _BAUDCTL_SCKP 0x10
2252 #define _BAUDCTL_RCIDL 0x40
2253 #define _BAUDCTL_ABDOVF 0x80
2255 //==============================================================================
2258 //==============================================================================
2261 extern __at(0x019F) __sfr BAUDCTL1
;
2272 unsigned ABDOVF
: 1;
2275 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
2277 #define _BAUDCTL1_ABDEN 0x01
2278 #define _BAUDCTL1_WUE 0x02
2279 #define _BAUDCTL1_BRG16 0x08
2280 #define _BAUDCTL1_SCKP 0x10
2281 #define _BAUDCTL1_RCIDL 0x40
2282 #define _BAUDCTL1_ABDOVF 0x80
2284 //==============================================================================
2287 //==============================================================================
2290 extern __at(0x020C) __sfr WPUA
;
2313 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
2322 //==============================================================================
2325 //==============================================================================
2328 extern __at(0x020D) __sfr WPUB
;
2342 extern __at(0x020D) volatile __WPUBbits_t WPUBbits
;
2349 //==============================================================================
2352 //==============================================================================
2355 extern __at(0x020E) __sfr WPUC
;
2369 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
2380 //==============================================================================
2383 //==============================================================================
2386 extern __at(0x0211) __sfr SSP1BUF
;
2392 unsigned SSP1BUF0
: 1;
2393 unsigned SSP1BUF1
: 1;
2394 unsigned SSP1BUF2
: 1;
2395 unsigned SSP1BUF3
: 1;
2396 unsigned SSP1BUF4
: 1;
2397 unsigned SSP1BUF5
: 1;
2398 unsigned SSP1BUF6
: 1;
2399 unsigned SSP1BUF7
: 1;
2415 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
2417 #define _SSP1BUF0 0x01
2419 #define _SSP1BUF1 0x02
2421 #define _SSP1BUF2 0x04
2423 #define _SSP1BUF3 0x08
2425 #define _SSP1BUF4 0x10
2427 #define _SSP1BUF5 0x20
2429 #define _SSP1BUF6 0x40
2431 #define _SSP1BUF7 0x80
2434 //==============================================================================
2437 //==============================================================================
2440 extern __at(0x0211) __sfr SSPBUF
;
2446 unsigned SSP1BUF0
: 1;
2447 unsigned SSP1BUF1
: 1;
2448 unsigned SSP1BUF2
: 1;
2449 unsigned SSP1BUF3
: 1;
2450 unsigned SSP1BUF4
: 1;
2451 unsigned SSP1BUF5
: 1;
2452 unsigned SSP1BUF6
: 1;
2453 unsigned SSP1BUF7
: 1;
2469 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
2471 #define _SSPBUF_SSP1BUF0 0x01
2472 #define _SSPBUF_BUF0 0x01
2473 #define _SSPBUF_SSP1BUF1 0x02
2474 #define _SSPBUF_BUF1 0x02
2475 #define _SSPBUF_SSP1BUF2 0x04
2476 #define _SSPBUF_BUF2 0x04
2477 #define _SSPBUF_SSP1BUF3 0x08
2478 #define _SSPBUF_BUF3 0x08
2479 #define _SSPBUF_SSP1BUF4 0x10
2480 #define _SSPBUF_BUF4 0x10
2481 #define _SSPBUF_SSP1BUF5 0x20
2482 #define _SSPBUF_BUF5 0x20
2483 #define _SSPBUF_SSP1BUF6 0x40
2484 #define _SSPBUF_BUF6 0x40
2485 #define _SSPBUF_SSP1BUF7 0x80
2486 #define _SSPBUF_BUF7 0x80
2488 //==============================================================================
2491 //==============================================================================
2494 extern __at(0x0212) __sfr SSP1ADD
;
2500 unsigned SSP1ADD0
: 1;
2501 unsigned SSP1ADD1
: 1;
2502 unsigned SSP1ADD2
: 1;
2503 unsigned SSP1ADD3
: 1;
2504 unsigned SSP1ADD4
: 1;
2505 unsigned SSP1ADD5
: 1;
2506 unsigned SSP1ADD6
: 1;
2507 unsigned SSP1ADD7
: 1;
2523 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
2525 #define _SSP1ADD0 0x01
2527 #define _SSP1ADD1 0x02
2529 #define _SSP1ADD2 0x04
2531 #define _SSP1ADD3 0x08
2533 #define _SSP1ADD4 0x10
2535 #define _SSP1ADD5 0x20
2537 #define _SSP1ADD6 0x40
2539 #define _SSP1ADD7 0x80
2542 //==============================================================================
2545 //==============================================================================
2548 extern __at(0x0212) __sfr SSPADD
;
2554 unsigned SSP1ADD0
: 1;
2555 unsigned SSP1ADD1
: 1;
2556 unsigned SSP1ADD2
: 1;
2557 unsigned SSP1ADD3
: 1;
2558 unsigned SSP1ADD4
: 1;
2559 unsigned SSP1ADD5
: 1;
2560 unsigned SSP1ADD6
: 1;
2561 unsigned SSP1ADD7
: 1;
2577 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
2579 #define _SSPADD_SSP1ADD0 0x01
2580 #define _SSPADD_ADD0 0x01
2581 #define _SSPADD_SSP1ADD1 0x02
2582 #define _SSPADD_ADD1 0x02
2583 #define _SSPADD_SSP1ADD2 0x04
2584 #define _SSPADD_ADD2 0x04
2585 #define _SSPADD_SSP1ADD3 0x08
2586 #define _SSPADD_ADD3 0x08
2587 #define _SSPADD_SSP1ADD4 0x10
2588 #define _SSPADD_ADD4 0x10
2589 #define _SSPADD_SSP1ADD5 0x20
2590 #define _SSPADD_ADD5 0x20
2591 #define _SSPADD_SSP1ADD6 0x40
2592 #define _SSPADD_ADD6 0x40
2593 #define _SSPADD_SSP1ADD7 0x80
2594 #define _SSPADD_ADD7 0x80
2596 //==============================================================================
2599 //==============================================================================
2602 extern __at(0x0213) __sfr SSP1MSK
;
2608 unsigned SSP1MSK0
: 1;
2609 unsigned SSP1MSK1
: 1;
2610 unsigned SSP1MSK2
: 1;
2611 unsigned SSP1MSK3
: 1;
2612 unsigned SSP1MSK4
: 1;
2613 unsigned SSP1MSK5
: 1;
2614 unsigned SSP1MSK6
: 1;
2615 unsigned SSP1MSK7
: 1;
2631 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
2633 #define _SSP1MSK0 0x01
2635 #define _SSP1MSK1 0x02
2637 #define _SSP1MSK2 0x04
2639 #define _SSP1MSK3 0x08
2641 #define _SSP1MSK4 0x10
2643 #define _SSP1MSK5 0x20
2645 #define _SSP1MSK6 0x40
2647 #define _SSP1MSK7 0x80
2650 //==============================================================================
2653 //==============================================================================
2656 extern __at(0x0213) __sfr SSPMSK
;
2662 unsigned SSP1MSK0
: 1;
2663 unsigned SSP1MSK1
: 1;
2664 unsigned SSP1MSK2
: 1;
2665 unsigned SSP1MSK3
: 1;
2666 unsigned SSP1MSK4
: 1;
2667 unsigned SSP1MSK5
: 1;
2668 unsigned SSP1MSK6
: 1;
2669 unsigned SSP1MSK7
: 1;
2685 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
2687 #define _SSPMSK_SSP1MSK0 0x01
2688 #define _SSPMSK_MSK0 0x01
2689 #define _SSPMSK_SSP1MSK1 0x02
2690 #define _SSPMSK_MSK1 0x02
2691 #define _SSPMSK_SSP1MSK2 0x04
2692 #define _SSPMSK_MSK2 0x04
2693 #define _SSPMSK_SSP1MSK3 0x08
2694 #define _SSPMSK_MSK3 0x08
2695 #define _SSPMSK_SSP1MSK4 0x10
2696 #define _SSPMSK_MSK4 0x10
2697 #define _SSPMSK_SSP1MSK5 0x20
2698 #define _SSPMSK_MSK5 0x20
2699 #define _SSPMSK_SSP1MSK6 0x40
2700 #define _SSPMSK_MSK6 0x40
2701 #define _SSPMSK_SSP1MSK7 0x80
2702 #define _SSPMSK_MSK7 0x80
2704 //==============================================================================
2707 //==============================================================================
2710 extern __at(0x0214) __sfr SSP1STAT
;
2716 unsigned R_NOT_W
: 1;
2719 unsigned D_NOT_A
: 1;
2724 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
2728 #define _R_NOT_W 0x04
2731 #define _D_NOT_A 0x20
2735 //==============================================================================
2738 //==============================================================================
2741 extern __at(0x0214) __sfr SSPSTAT
;
2747 unsigned R_NOT_W
: 1;
2750 unsigned D_NOT_A
: 1;
2755 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
2757 #define _SSPSTAT_BF 0x01
2758 #define _SSPSTAT_UA 0x02
2759 #define _SSPSTAT_R_NOT_W 0x04
2760 #define _SSPSTAT_S 0x08
2761 #define _SSPSTAT_P 0x10
2762 #define _SSPSTAT_D_NOT_A 0x20
2763 #define _SSPSTAT_CKE 0x40
2764 #define _SSPSTAT_SMP 0x80
2766 //==============================================================================
2769 //==============================================================================
2772 extern __at(0x0215) __sfr SSP1CON
;
2795 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
2806 //==============================================================================
2809 //==============================================================================
2812 extern __at(0x0215) __sfr SSP1CON1
;
2835 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
2837 #define _SSP1CON1_SSPM0 0x01
2838 #define _SSP1CON1_SSPM1 0x02
2839 #define _SSP1CON1_SSPM2 0x04
2840 #define _SSP1CON1_SSPM3 0x08
2841 #define _SSP1CON1_CKP 0x10
2842 #define _SSP1CON1_SSPEN 0x20
2843 #define _SSP1CON1_SSPOV 0x40
2844 #define _SSP1CON1_WCOL 0x80
2846 //==============================================================================
2849 //==============================================================================
2852 extern __at(0x0215) __sfr SSPCON
;
2875 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2877 #define _SSPCON_SSPM0 0x01
2878 #define _SSPCON_SSPM1 0x02
2879 #define _SSPCON_SSPM2 0x04
2880 #define _SSPCON_SSPM3 0x08
2881 #define _SSPCON_CKP 0x10
2882 #define _SSPCON_SSPEN 0x20
2883 #define _SSPCON_SSPOV 0x40
2884 #define _SSPCON_WCOL 0x80
2886 //==============================================================================
2889 //==============================================================================
2892 extern __at(0x0215) __sfr SSPCON1
;
2915 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2917 #define _SSPCON1_SSPM0 0x01
2918 #define _SSPCON1_SSPM1 0x02
2919 #define _SSPCON1_SSPM2 0x04
2920 #define _SSPCON1_SSPM3 0x08
2921 #define _SSPCON1_CKP 0x10
2922 #define _SSPCON1_SSPEN 0x20
2923 #define _SSPCON1_SSPOV 0x40
2924 #define _SSPCON1_WCOL 0x80
2926 //==============================================================================
2929 //==============================================================================
2932 extern __at(0x0216) __sfr SSP1CON2
;
2942 unsigned ACKSTAT
: 1;
2946 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
2954 #define _ACKSTAT 0x40
2957 //==============================================================================
2960 //==============================================================================
2963 extern __at(0x0216) __sfr SSPCON2
;
2973 unsigned ACKSTAT
: 1;
2977 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
2979 #define _SSPCON2_SEN 0x01
2980 #define _SSPCON2_RSEN 0x02
2981 #define _SSPCON2_PEN 0x04
2982 #define _SSPCON2_RCEN 0x08
2983 #define _SSPCON2_ACKEN 0x10
2984 #define _SSPCON2_ACKDT 0x20
2985 #define _SSPCON2_ACKSTAT 0x40
2986 #define _SSPCON2_GCEN 0x80
2988 //==============================================================================
2991 //==============================================================================
2994 extern __at(0x0217) __sfr SSP1CON3
;
3005 unsigned ACKTIM
: 1;
3008 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
3017 #define _ACKTIM 0x80
3019 //==============================================================================
3022 //==============================================================================
3025 extern __at(0x0217) __sfr SSPCON3
;
3036 unsigned ACKTIM
: 1;
3039 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
3041 #define _SSPCON3_DHEN 0x01
3042 #define _SSPCON3_AHEN 0x02
3043 #define _SSPCON3_SBCDE 0x04
3044 #define _SSPCON3_SDAHT 0x08
3045 #define _SSPCON3_BOEN 0x10
3046 #define _SSPCON3_SCIE 0x20
3047 #define _SSPCON3_PCIE 0x40
3048 #define _SSPCON3_ACKTIM 0x80
3050 //==============================================================================
3053 //==============================================================================
3056 extern __at(0x028C) __sfr ODCONA
;
3070 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
3078 //==============================================================================
3081 //==============================================================================
3084 extern __at(0x028D) __sfr ODCONB
;
3098 extern __at(0x028D) volatile __ODCONBbits_t ODCONBbits
;
3105 //==============================================================================
3108 //==============================================================================
3111 extern __at(0x028E) __sfr ODCONC
;
3125 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
3136 //==============================================================================
3138 extern __at(0x0291) __sfr CCPR1
;
3139 extern __at(0x0291) __sfr CCPR1L
;
3140 extern __at(0x0292) __sfr CCPR1H
;
3142 //==============================================================================
3145 extern __at(0x0293) __sfr CCP1CON
;
3151 unsigned CCP1M0
: 1;
3152 unsigned CCP1M1
: 1;
3153 unsigned CCP1M2
: 1;
3154 unsigned CCP1M3
: 1;
3187 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
3189 #define _CCP1M0 0x01
3190 #define _CCP1M1 0x02
3191 #define _CCP1M2 0x04
3192 #define _CCP1M3 0x08
3198 //==============================================================================
3201 //==============================================================================
3204 extern __at(0x0293) __sfr ECCP1CON
;
3210 unsigned CCP1M0
: 1;
3211 unsigned CCP1M1
: 1;
3212 unsigned CCP1M2
: 1;
3213 unsigned CCP1M3
: 1;
3246 extern __at(0x0293) volatile __ECCP1CONbits_t ECCP1CONbits
;
3248 #define _ECCP1CON_CCP1M0 0x01
3249 #define _ECCP1CON_CCP1M1 0x02
3250 #define _ECCP1CON_CCP1M2 0x04
3251 #define _ECCP1CON_CCP1M3 0x08
3252 #define _ECCP1CON_DC1B0 0x10
3253 #define _ECCP1CON_CCP1Y 0x10
3254 #define _ECCP1CON_DC1B1 0x20
3255 #define _ECCP1CON_CCP1X 0x20
3257 //==============================================================================
3259 extern __at(0x0298) __sfr CCPR2
;
3260 extern __at(0x0298) __sfr CCPR2L
;
3261 extern __at(0x0299) __sfr CCPR2H
;
3263 //==============================================================================
3266 extern __at(0x029A) __sfr CCP2CON
;
3272 unsigned CCP2M0
: 1;
3273 unsigned CCP2M1
: 1;
3274 unsigned CCP2M2
: 1;
3275 unsigned CCP2M3
: 1;
3308 extern __at(0x029A) volatile __CCP2CONbits_t CCP2CONbits
;
3310 #define _CCP2M0 0x01
3311 #define _CCP2M1 0x02
3312 #define _CCP2M2 0x04
3313 #define _CCP2M3 0x08
3319 //==============================================================================
3322 //==============================================================================
3325 extern __at(0x029A) __sfr ECCP2CON
;
3331 unsigned CCP2M0
: 1;
3332 unsigned CCP2M1
: 1;
3333 unsigned CCP2M2
: 1;
3334 unsigned CCP2M3
: 1;
3367 extern __at(0x029A) volatile __ECCP2CONbits_t ECCP2CONbits
;
3369 #define _ECCP2CON_CCP2M0 0x01
3370 #define _ECCP2CON_CCP2M1 0x02
3371 #define _ECCP2CON_CCP2M2 0x04
3372 #define _ECCP2CON_CCP2M3 0x08
3373 #define _ECCP2CON_DC2B0 0x10
3374 #define _ECCP2CON_CCP2Y 0x10
3375 #define _ECCP2CON_DC2B1 0x20
3376 #define _ECCP2CON_CCP2X 0x20
3378 //==============================================================================
3381 //==============================================================================
3384 extern __at(0x029E) __sfr CCPTMRS
;
3390 unsigned C1TSEL0
: 1;
3391 unsigned C1TSEL1
: 1;
3392 unsigned C2TSEL0
: 1;
3393 unsigned C2TSEL1
: 1;
3394 unsigned P3TSEL0
: 1;
3395 unsigned P3TSEL1
: 1;
3396 unsigned P4TSEL0
: 1;
3397 unsigned P4TSEL1
: 1;
3402 unsigned C1TSEL
: 2;
3409 unsigned C2TSEL
: 2;
3416 unsigned P3TSEL
: 2;
3423 unsigned P4TSEL
: 2;
3427 extern __at(0x029E) volatile __CCPTMRSbits_t CCPTMRSbits
;
3429 #define _C1TSEL0 0x01
3430 #define _C1TSEL1 0x02
3431 #define _C2TSEL0 0x04
3432 #define _C2TSEL1 0x08
3433 #define _P3TSEL0 0x10
3434 #define _P3TSEL1 0x20
3435 #define _P4TSEL0 0x40
3436 #define _P4TSEL1 0x80
3438 //==============================================================================
3441 //==============================================================================
3444 extern __at(0x030C) __sfr SLRCONA
;
3458 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
3466 //==============================================================================
3469 //==============================================================================
3472 extern __at(0x030D) __sfr SLRCONB
;
3486 extern __at(0x030D) volatile __SLRCONBbits_t SLRCONBbits
;
3493 //==============================================================================
3496 //==============================================================================
3499 extern __at(0x030E) __sfr SLRCONC
;
3513 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
3524 //==============================================================================
3527 //==============================================================================
3530 extern __at(0x038C) __sfr INLVLA
;
3536 unsigned INLVLA0
: 1;
3537 unsigned INLVLA1
: 1;
3538 unsigned INLVLA2
: 1;
3539 unsigned INLVLA3
: 1;
3540 unsigned INLVLA4
: 1;
3541 unsigned INLVLA5
: 1;
3548 unsigned INLVLA
: 6;
3553 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
3555 #define _INLVLA0 0x01
3556 #define _INLVLA1 0x02
3557 #define _INLVLA2 0x04
3558 #define _INLVLA3 0x08
3559 #define _INLVLA4 0x10
3560 #define _INLVLA5 0x20
3562 //==============================================================================
3565 //==============================================================================
3568 extern __at(0x038D) __sfr INLVLB
;
3576 unsigned INLVLB4
: 1;
3577 unsigned INLVLB5
: 1;
3578 unsigned INLVLB6
: 1;
3579 unsigned INLVLB7
: 1;
3582 extern __at(0x038D) volatile __INLVLBbits_t INLVLBbits
;
3584 #define _INLVLB4 0x10
3585 #define _INLVLB5 0x20
3586 #define _INLVLB6 0x40
3587 #define _INLVLB7 0x80
3589 //==============================================================================
3592 //==============================================================================
3595 extern __at(0x038E) __sfr INLVLC
;
3599 unsigned INLVLC0
: 1;
3600 unsigned INLVLC1
: 1;
3601 unsigned INLVLC2
: 1;
3602 unsigned INLVLC3
: 1;
3603 unsigned INLVLC4
: 1;
3604 unsigned INLVLC5
: 1;
3605 unsigned INLVLC6
: 1;
3606 unsigned INLVLC7
: 1;
3609 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
3611 #define _INLVLC0 0x01
3612 #define _INLVLC1 0x02
3613 #define _INLVLC2 0x04
3614 #define _INLVLC3 0x08
3615 #define _INLVLC4 0x10
3616 #define _INLVLC5 0x20
3617 #define _INLVLC6 0x40
3618 #define _INLVLC7 0x80
3620 //==============================================================================
3623 //==============================================================================
3626 extern __at(0x0391) __sfr IOCAP
;
3632 unsigned IOCAP0
: 1;
3633 unsigned IOCAP1
: 1;
3634 unsigned IOCAP2
: 1;
3635 unsigned IOCAP3
: 1;
3636 unsigned IOCAP4
: 1;
3637 unsigned IOCAP5
: 1;
3649 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
3651 #define _IOCAP0 0x01
3652 #define _IOCAP1 0x02
3653 #define _IOCAP2 0x04
3654 #define _IOCAP3 0x08
3655 #define _IOCAP4 0x10
3656 #define _IOCAP5 0x20
3658 //==============================================================================
3661 //==============================================================================
3664 extern __at(0x0392) __sfr IOCAN
;
3670 unsigned IOCAN0
: 1;
3671 unsigned IOCAN1
: 1;
3672 unsigned IOCAN2
: 1;
3673 unsigned IOCAN3
: 1;
3674 unsigned IOCAN4
: 1;
3675 unsigned IOCAN5
: 1;
3687 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
3689 #define _IOCAN0 0x01
3690 #define _IOCAN1 0x02
3691 #define _IOCAN2 0x04
3692 #define _IOCAN3 0x08
3693 #define _IOCAN4 0x10
3694 #define _IOCAN5 0x20
3696 //==============================================================================
3699 //==============================================================================
3702 extern __at(0x0393) __sfr IOCAF
;
3708 unsigned IOCAF0
: 1;
3709 unsigned IOCAF1
: 1;
3710 unsigned IOCAF2
: 1;
3711 unsigned IOCAF3
: 1;
3712 unsigned IOCAF4
: 1;
3713 unsigned IOCAF5
: 1;
3725 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
3727 #define _IOCAF0 0x01
3728 #define _IOCAF1 0x02
3729 #define _IOCAF2 0x04
3730 #define _IOCAF3 0x08
3731 #define _IOCAF4 0x10
3732 #define _IOCAF5 0x20
3734 //==============================================================================
3737 //==============================================================================
3740 extern __at(0x0394) __sfr IOCBP
;
3748 unsigned IOCBP4
: 1;
3749 unsigned IOCBP5
: 1;
3750 unsigned IOCBP6
: 1;
3751 unsigned IOCBP7
: 1;
3754 extern __at(0x0394) volatile __IOCBPbits_t IOCBPbits
;
3756 #define _IOCBP4 0x10
3757 #define _IOCBP5 0x20
3758 #define _IOCBP6 0x40
3759 #define _IOCBP7 0x80
3761 //==============================================================================
3764 //==============================================================================
3767 extern __at(0x0395) __sfr IOCBN
;
3775 unsigned IOCBN4
: 1;
3776 unsigned IOCBN5
: 1;
3777 unsigned IOCBN6
: 1;
3778 unsigned IOCBN7
: 1;
3781 extern __at(0x0395) volatile __IOCBNbits_t IOCBNbits
;
3783 #define _IOCBN4 0x10
3784 #define _IOCBN5 0x20
3785 #define _IOCBN6 0x40
3786 #define _IOCBN7 0x80
3788 //==============================================================================
3791 //==============================================================================
3794 extern __at(0x0396) __sfr IOCBF
;
3802 unsigned IOCBF4
: 1;
3803 unsigned IOCBF5
: 1;
3804 unsigned IOCBF6
: 1;
3805 unsigned IOCBF7
: 1;
3808 extern __at(0x0396) volatile __IOCBFbits_t IOCBFbits
;
3810 #define _IOCBF4 0x10
3811 #define _IOCBF5 0x20
3812 #define _IOCBF6 0x40
3813 #define _IOCBF7 0x80
3815 //==============================================================================
3818 //==============================================================================
3821 extern __at(0x0397) __sfr IOCCP
;
3825 unsigned IOCCP0
: 1;
3826 unsigned IOCCP1
: 1;
3827 unsigned IOCCP2
: 1;
3828 unsigned IOCCP3
: 1;
3829 unsigned IOCCP4
: 1;
3830 unsigned IOCCP5
: 1;
3831 unsigned IOCCP6
: 1;
3832 unsigned IOCCP7
: 1;
3835 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
3837 #define _IOCCP0 0x01
3838 #define _IOCCP1 0x02
3839 #define _IOCCP2 0x04
3840 #define _IOCCP3 0x08
3841 #define _IOCCP4 0x10
3842 #define _IOCCP5 0x20
3843 #define _IOCCP6 0x40
3844 #define _IOCCP7 0x80
3846 //==============================================================================
3849 //==============================================================================
3852 extern __at(0x0398) __sfr IOCCN
;
3856 unsigned IOCCN0
: 1;
3857 unsigned IOCCN1
: 1;
3858 unsigned IOCCN2
: 1;
3859 unsigned IOCCN3
: 1;
3860 unsigned IOCCN4
: 1;
3861 unsigned IOCCN5
: 1;
3862 unsigned IOCCN6
: 1;
3863 unsigned IOCCN7
: 1;
3866 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
3868 #define _IOCCN0 0x01
3869 #define _IOCCN1 0x02
3870 #define _IOCCN2 0x04
3871 #define _IOCCN3 0x08
3872 #define _IOCCN4 0x10
3873 #define _IOCCN5 0x20
3874 #define _IOCCN6 0x40
3875 #define _IOCCN7 0x80
3877 //==============================================================================
3880 //==============================================================================
3883 extern __at(0x0399) __sfr IOCCF
;
3887 unsigned IOCCF0
: 1;
3888 unsigned IOCCF1
: 1;
3889 unsigned IOCCF2
: 1;
3890 unsigned IOCCF3
: 1;
3891 unsigned IOCCF4
: 1;
3892 unsigned IOCCF5
: 1;
3893 unsigned IOCCF6
: 1;
3894 unsigned IOCCF7
: 1;
3897 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
3899 #define _IOCCF0 0x01
3900 #define _IOCCF1 0x02
3901 #define _IOCCF2 0x04
3902 #define _IOCCF3 0x08
3903 #define _IOCCF4 0x10
3904 #define _IOCCF5 0x20
3905 #define _IOCCF6 0x40
3906 #define _IOCCF7 0x80
3908 //==============================================================================
3910 extern __at(0x0415) __sfr TMR4
;
3911 extern __at(0x0416) __sfr PR4
;
3913 //==============================================================================
3916 extern __at(0x0417) __sfr T4CON
;
3922 unsigned T4CKPS0
: 1;
3923 unsigned T4CKPS1
: 1;
3924 unsigned TMR4ON
: 1;
3925 unsigned T4OUTPS0
: 1;
3926 unsigned T4OUTPS1
: 1;
3927 unsigned T4OUTPS2
: 1;
3928 unsigned T4OUTPS3
: 1;
3934 unsigned T4CKPS
: 2;
3941 unsigned T4OUTPS
: 4;
3946 extern __at(0x0417) volatile __T4CONbits_t T4CONbits
;
3948 #define _T4CKPS0 0x01
3949 #define _T4CKPS1 0x02
3950 #define _TMR4ON 0x04
3951 #define _T4OUTPS0 0x08
3952 #define _T4OUTPS1 0x10
3953 #define _T4OUTPS2 0x20
3954 #define _T4OUTPS3 0x40
3956 //==============================================================================
3958 extern __at(0x041C) __sfr TMR6
;
3959 extern __at(0x041D) __sfr PR6
;
3961 //==============================================================================
3964 extern __at(0x041E) __sfr T6CON
;
3970 unsigned T6CKPS0
: 1;
3971 unsigned T6CKPS1
: 1;
3972 unsigned TMR6ON
: 1;
3973 unsigned T6OUTPS0
: 1;
3974 unsigned T6OUTPS1
: 1;
3975 unsigned T6OUTPS2
: 1;
3976 unsigned T6OUTPS3
: 1;
3982 unsigned T6CKPS
: 2;
3989 unsigned T6OUTPS
: 4;
3994 extern __at(0x041E) volatile __T6CONbits_t T6CONbits
;
3996 #define _T6CKPS0 0x01
3997 #define _T6CKPS1 0x02
3998 #define _TMR6ON 0x04
3999 #define _T6OUTPS0 0x08
4000 #define _T6OUTPS1 0x10
4001 #define _T6OUTPS2 0x20
4002 #define _T6OUTPS3 0x40
4004 //==============================================================================
4007 //==============================================================================
4010 extern __at(0x0511) __sfr OPA1CON
;
4016 unsigned OPA1PCH0
: 1;
4017 unsigned OPA1PCH1
: 1;
4020 unsigned OPA1UG
: 1;
4022 unsigned OPA1SP
: 1;
4023 unsigned OPA1EN
: 1;
4028 unsigned OPA1PCH
: 2;
4033 extern __at(0x0511) volatile __OPA1CONbits_t OPA1CONbits
;
4035 #define _OPA1PCH0 0x01
4036 #define _OPA1PCH1 0x02
4037 #define _OPA1UG 0x10
4038 #define _OPA1SP 0x40
4039 #define _OPA1EN 0x80
4041 //==============================================================================
4044 //==============================================================================
4047 extern __at(0x0515) __sfr OPA2CON
;
4053 unsigned OPA2PCH0
: 1;
4054 unsigned OPA2PCH1
: 1;
4057 unsigned OPA2UG
: 1;
4059 unsigned OPA2SP
: 1;
4060 unsigned OPA2EN
: 1;
4065 unsigned OPA2PCH
: 2;
4070 extern __at(0x0515) volatile __OPA2CONbits_t OPA2CONbits
;
4072 #define _OPA2PCH0 0x01
4073 #define _OPA2PCH1 0x02
4074 #define _OPA2UG 0x10
4075 #define _OPA2SP 0x40
4076 #define _OPA2EN 0x80
4078 //==============================================================================
4081 //==============================================================================
4084 extern __at(0x0617) __sfr PWM3DCL
;
4096 unsigned PWM3DCL0
: 1;
4097 unsigned PWM3DCL1
: 1;
4103 unsigned PWM3DCL
: 2;
4107 extern __at(0x0617) volatile __PWM3DCLbits_t PWM3DCLbits
;
4109 #define _PWM3DCL0 0x40
4110 #define _PWM3DCL1 0x80
4112 //==============================================================================
4115 //==============================================================================
4118 extern __at(0x0618) __sfr PWM3DCH
;
4122 unsigned PWM3DCH0
: 1;
4123 unsigned PWM3DCH1
: 1;
4124 unsigned PWM3DCH2
: 1;
4125 unsigned PWM3DCH3
: 1;
4126 unsigned PWM3DCH4
: 1;
4127 unsigned PWM3DCH5
: 1;
4128 unsigned PWM3DCH6
: 1;
4129 unsigned PWM3DCH7
: 1;
4132 extern __at(0x0618) volatile __PWM3DCHbits_t PWM3DCHbits
;
4134 #define _PWM3DCH0 0x01
4135 #define _PWM3DCH1 0x02
4136 #define _PWM3DCH2 0x04
4137 #define _PWM3DCH3 0x08
4138 #define _PWM3DCH4 0x10
4139 #define _PWM3DCH5 0x20
4140 #define _PWM3DCH6 0x40
4141 #define _PWM3DCH7 0x80
4143 //==============================================================================
4146 //==============================================================================
4149 extern __at(0x0619) __sfr PWM3CON
;
4157 unsigned PWM3POL
: 1;
4158 unsigned PWM3OUT
: 1;
4160 unsigned PWM3EN
: 1;
4163 extern __at(0x0619) volatile __PWM3CONbits_t PWM3CONbits
;
4165 #define _PWM3POL 0x10
4166 #define _PWM3OUT 0x20
4167 #define _PWM3EN 0x80
4169 //==============================================================================
4172 //==============================================================================
4175 extern __at(0x0619) __sfr PWM3CON0
;
4183 unsigned PWM3POL
: 1;
4184 unsigned PWM3OUT
: 1;
4186 unsigned PWM3EN
: 1;
4189 extern __at(0x0619) volatile __PWM3CON0bits_t PWM3CON0bits
;
4191 #define _PWM3CON0_PWM3POL 0x10
4192 #define _PWM3CON0_PWM3OUT 0x20
4193 #define _PWM3CON0_PWM3EN 0x80
4195 //==============================================================================
4198 //==============================================================================
4201 extern __at(0x061A) __sfr PWM4DCL
;
4213 unsigned PWM4DCL0
: 1;
4214 unsigned PWM4DCL1
: 1;
4220 unsigned PWM4DCL
: 2;
4224 extern __at(0x061A) volatile __PWM4DCLbits_t PWM4DCLbits
;
4226 #define _PWM4DCL0 0x40
4227 #define _PWM4DCL1 0x80
4229 //==============================================================================
4232 //==============================================================================
4235 extern __at(0x061B) __sfr PWM4DCH
;
4239 unsigned PWM4DCH0
: 1;
4240 unsigned PWM4DCH1
: 1;
4241 unsigned PWM4DCH2
: 1;
4242 unsigned PWM4DCH3
: 1;
4243 unsigned PWM4DCH4
: 1;
4244 unsigned PWM4DCH5
: 1;
4245 unsigned PWM4DCH6
: 1;
4246 unsigned PWM4DCH7
: 1;
4249 extern __at(0x061B) volatile __PWM4DCHbits_t PWM4DCHbits
;
4251 #define _PWM4DCH0 0x01
4252 #define _PWM4DCH1 0x02
4253 #define _PWM4DCH2 0x04
4254 #define _PWM4DCH3 0x08
4255 #define _PWM4DCH4 0x10
4256 #define _PWM4DCH5 0x20
4257 #define _PWM4DCH6 0x40
4258 #define _PWM4DCH7 0x80
4260 //==============================================================================
4263 //==============================================================================
4266 extern __at(0x061C) __sfr PWM4CON
;
4274 unsigned PWM4POL
: 1;
4275 unsigned PWM4OUT
: 1;
4277 unsigned PWM4EN
: 1;
4280 extern __at(0x061C) volatile __PWM4CONbits_t PWM4CONbits
;
4282 #define _PWM4POL 0x10
4283 #define _PWM4OUT 0x20
4284 #define _PWM4EN 0x80
4286 //==============================================================================
4289 //==============================================================================
4292 extern __at(0x061C) __sfr PWM4CON0
;
4300 unsigned PWM4POL
: 1;
4301 unsigned PWM4OUT
: 1;
4303 unsigned PWM4EN
: 1;
4306 extern __at(0x061C) volatile __PWM4CON0bits_t PWM4CON0bits
;
4308 #define _PWM4CON0_PWM4POL 0x10
4309 #define _PWM4CON0_PWM4OUT 0x20
4310 #define _PWM4CON0_PWM4EN 0x80
4312 //==============================================================================
4315 //==============================================================================
4318 extern __at(0x0691) __sfr COG1PHR
;
4324 unsigned G1PHR0
: 1;
4325 unsigned G1PHR1
: 1;
4326 unsigned G1PHR2
: 1;
4327 unsigned G1PHR3
: 1;
4328 unsigned G1PHR4
: 1;
4329 unsigned G1PHR5
: 1;
4341 extern __at(0x0691) volatile __COG1PHRbits_t COG1PHRbits
;
4343 #define _G1PHR0 0x01
4344 #define _G1PHR1 0x02
4345 #define _G1PHR2 0x04
4346 #define _G1PHR3 0x08
4347 #define _G1PHR4 0x10
4348 #define _G1PHR5 0x20
4350 //==============================================================================
4353 //==============================================================================
4356 extern __at(0x0692) __sfr COG1PHF
;
4362 unsigned G1PHF0
: 1;
4363 unsigned G1PHF1
: 1;
4364 unsigned G1PHF2
: 1;
4365 unsigned G1PHF3
: 1;
4366 unsigned G1PHF4
: 1;
4367 unsigned G1PHF5
: 1;
4379 extern __at(0x0692) volatile __COG1PHFbits_t COG1PHFbits
;
4381 #define _G1PHF0 0x01
4382 #define _G1PHF1 0x02
4383 #define _G1PHF2 0x04
4384 #define _G1PHF3 0x08
4385 #define _G1PHF4 0x10
4386 #define _G1PHF5 0x20
4388 //==============================================================================
4391 //==============================================================================
4394 extern __at(0x0693) __sfr COG1BLKR
;
4400 unsigned G1BLKR0
: 1;
4401 unsigned G1BLKR1
: 1;
4402 unsigned G1BLKR2
: 1;
4403 unsigned G1BLKR3
: 1;
4404 unsigned G1BLKR4
: 1;
4405 unsigned G1BLKR5
: 1;
4412 unsigned G1BLKR
: 6;
4417 extern __at(0x0693) volatile __COG1BLKRbits_t COG1BLKRbits
;
4419 #define _G1BLKR0 0x01
4420 #define _G1BLKR1 0x02
4421 #define _G1BLKR2 0x04
4422 #define _G1BLKR3 0x08
4423 #define _G1BLKR4 0x10
4424 #define _G1BLKR5 0x20
4426 //==============================================================================
4429 //==============================================================================
4432 extern __at(0x0694) __sfr COG1BLKF
;
4438 unsigned G1BLKF0
: 1;
4439 unsigned G1BLKF1
: 1;
4440 unsigned G1BLKF2
: 1;
4441 unsigned G1BLKF3
: 1;
4442 unsigned G1BLKF4
: 1;
4443 unsigned G1BLKF5
: 1;
4450 unsigned G1BLKF
: 6;
4455 extern __at(0x0694) volatile __COG1BLKFbits_t COG1BLKFbits
;
4457 #define _G1BLKF0 0x01
4458 #define _G1BLKF1 0x02
4459 #define _G1BLKF2 0x04
4460 #define _G1BLKF3 0x08
4461 #define _G1BLKF4 0x10
4462 #define _G1BLKF5 0x20
4464 //==============================================================================
4467 //==============================================================================
4470 extern __at(0x0695) __sfr COG1DBR
;
4476 unsigned G1DBR0
: 1;
4477 unsigned G1DBR1
: 1;
4478 unsigned G1DBR2
: 1;
4479 unsigned G1DBR3
: 1;
4480 unsigned G1DBR4
: 1;
4481 unsigned G1DBR5
: 1;
4493 extern __at(0x0695) volatile __COG1DBRbits_t COG1DBRbits
;
4495 #define _G1DBR0 0x01
4496 #define _G1DBR1 0x02
4497 #define _G1DBR2 0x04
4498 #define _G1DBR3 0x08
4499 #define _G1DBR4 0x10
4500 #define _G1DBR5 0x20
4502 //==============================================================================
4505 //==============================================================================
4508 extern __at(0x0696) __sfr COG1DBF
;
4514 unsigned G1DBF0
: 1;
4515 unsigned G1DBF1
: 1;
4516 unsigned G1DBF2
: 1;
4517 unsigned G1DBF3
: 1;
4518 unsigned G1DBF4
: 1;
4519 unsigned G1DBF5
: 1;
4531 extern __at(0x0696) volatile __COG1DBFbits_t COG1DBFbits
;
4533 #define _G1DBF0 0x01
4534 #define _G1DBF1 0x02
4535 #define _G1DBF2 0x04
4536 #define _G1DBF3 0x08
4537 #define _G1DBF4 0x10
4538 #define _G1DBF5 0x20
4540 //==============================================================================
4543 //==============================================================================
4546 extern __at(0x0697) __sfr COG1CON0
;
4576 extern __at(0x0697) volatile __COG1CON0bits_t COG1CON0bits
;
4586 //==============================================================================
4589 //==============================================================================
4592 extern __at(0x0698) __sfr COG1CON1
;
4596 unsigned G1POLA
: 1;
4597 unsigned G1POLB
: 1;
4598 unsigned G1POLC
: 1;
4599 unsigned G1POLD
: 1;
4602 unsigned G1FDBS
: 1;
4603 unsigned G1RDBS
: 1;
4606 extern __at(0x0698) volatile __COG1CON1bits_t COG1CON1bits
;
4608 #define _G1POLA 0x01
4609 #define _G1POLB 0x02
4610 #define _G1POLC 0x04
4611 #define _G1POLD 0x08
4612 #define _G1FDBS 0x40
4613 #define _G1RDBS 0x80
4615 //==============================================================================
4618 //==============================================================================
4621 extern __at(0x0699) __sfr COG1RIS
;
4627 unsigned G1RIS0
: 1;
4628 unsigned G1RIS1
: 1;
4629 unsigned G1RIS2
: 1;
4630 unsigned G1RIS3
: 1;
4631 unsigned G1RIS4
: 1;
4632 unsigned G1RIS5
: 1;
4633 unsigned G1RIS6
: 1;
4644 extern __at(0x0699) volatile __COG1RISbits_t COG1RISbits
;
4646 #define _G1RIS0 0x01
4647 #define _G1RIS1 0x02
4648 #define _G1RIS2 0x04
4649 #define _G1RIS3 0x08
4650 #define _G1RIS4 0x10
4651 #define _G1RIS5 0x20
4652 #define _G1RIS6 0x40
4654 //==============================================================================
4657 //==============================================================================
4660 extern __at(0x069A) __sfr COG1RSIM
;
4666 unsigned G1RSIM0
: 1;
4667 unsigned G1RSIM1
: 1;
4668 unsigned G1RSIM2
: 1;
4669 unsigned G1RSIM3
: 1;
4670 unsigned G1RSIM4
: 1;
4671 unsigned G1RSIM5
: 1;
4672 unsigned G1RSIM6
: 1;
4678 unsigned G1RSIM
: 7;
4683 extern __at(0x069A) volatile __COG1RSIMbits_t COG1RSIMbits
;
4685 #define _G1RSIM0 0x01
4686 #define _G1RSIM1 0x02
4687 #define _G1RSIM2 0x04
4688 #define _G1RSIM3 0x08
4689 #define _G1RSIM4 0x10
4690 #define _G1RSIM5 0x20
4691 #define _G1RSIM6 0x40
4693 //==============================================================================
4696 //==============================================================================
4699 extern __at(0x069B) __sfr COG1FIS
;
4705 unsigned G1FIS0
: 1;
4706 unsigned G1FIS1
: 1;
4707 unsigned G1FIS2
: 1;
4708 unsigned G1FIS3
: 1;
4709 unsigned G1FIS4
: 1;
4710 unsigned G1FIS5
: 1;
4711 unsigned G1FIS6
: 1;
4722 extern __at(0x069B) volatile __COG1FISbits_t COG1FISbits
;
4724 #define _G1FIS0 0x01
4725 #define _G1FIS1 0x02
4726 #define _G1FIS2 0x04
4727 #define _G1FIS3 0x08
4728 #define _G1FIS4 0x10
4729 #define _G1FIS5 0x20
4730 #define _G1FIS6 0x40
4732 //==============================================================================
4735 //==============================================================================
4738 extern __at(0x069C) __sfr COG1FSIM
;
4744 unsigned G1FSIM0
: 1;
4745 unsigned G1FSIM1
: 1;
4746 unsigned G1FSIM2
: 1;
4747 unsigned G1FSIM3
: 1;
4748 unsigned G1FSIM4
: 1;
4749 unsigned G1FSIM5
: 1;
4750 unsigned G1FSIM6
: 1;
4756 unsigned G1FSIM
: 7;
4761 extern __at(0x069C) volatile __COG1FSIMbits_t COG1FSIMbits
;
4763 #define _G1FSIM0 0x01
4764 #define _G1FSIM1 0x02
4765 #define _G1FSIM2 0x04
4766 #define _G1FSIM3 0x08
4767 #define _G1FSIM4 0x10
4768 #define _G1FSIM5 0x20
4769 #define _G1FSIM6 0x40
4771 //==============================================================================
4774 //==============================================================================
4777 extern __at(0x069D) __sfr COG1ASD0
;
4785 unsigned G1ASDAC0
: 1;
4786 unsigned G1ASDAC1
: 1;
4787 unsigned G1ASDBD0
: 1;
4788 unsigned G1ASDBD1
: 1;
4789 unsigned G1ARSEN
: 1;
4796 unsigned G1ASDAC
: 2;
4803 unsigned G1ASDBD
: 2;
4808 extern __at(0x069D) volatile __COG1ASD0bits_t COG1ASD0bits
;
4810 #define _G1ASDAC0 0x04
4811 #define _G1ASDAC1 0x08
4812 #define _G1ASDBD0 0x10
4813 #define _G1ASDBD1 0x20
4814 #define _G1ARSEN 0x40
4817 //==============================================================================
4820 //==============================================================================
4823 extern __at(0x069E) __sfr COG1ASD1
;
4827 unsigned G1AS0E
: 1;
4828 unsigned G1AS1E
: 1;
4829 unsigned G1AS2E
: 1;
4830 unsigned G1AS3E
: 1;
4837 extern __at(0x069E) volatile __COG1ASD1bits_t COG1ASD1bits
;
4839 #define _G1AS0E 0x01
4840 #define _G1AS1E 0x02
4841 #define _G1AS2E 0x04
4842 #define _G1AS3E 0x08
4844 //==============================================================================
4847 //==============================================================================
4850 extern __at(0x069F) __sfr COG1STR
;
4854 unsigned G1STRA
: 1;
4855 unsigned G1STRB
: 1;
4856 unsigned G1STRC
: 1;
4857 unsigned G1STRD
: 1;
4858 unsigned G1SDATA
: 1;
4859 unsigned G1SDATB
: 1;
4860 unsigned G1SDATC
: 1;
4861 unsigned G1SDATD
: 1;
4864 extern __at(0x069F) volatile __COG1STRbits_t COG1STRbits
;
4866 #define _G1STRA 0x01
4867 #define _G1STRB 0x02
4868 #define _G1STRC 0x04
4869 #define _G1STRD 0x08
4870 #define _G1SDATA 0x10
4871 #define _G1SDATB 0x20
4872 #define _G1SDATC 0x40
4873 #define _G1SDATD 0x80
4875 //==============================================================================
4878 //==============================================================================
4881 extern __at(0x0E0F) __sfr PPSLOCK
;
4885 unsigned PPSLOCKED
: 1;
4895 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
4897 #define _PPSLOCKED 0x01
4899 //==============================================================================
4901 extern __at(0x0E10) __sfr INTPPS
;
4902 extern __at(0x0E11) __sfr T0CKIPPS
;
4903 extern __at(0x0E12) __sfr T1CKIPPS
;
4904 extern __at(0x0E13) __sfr T1GPPS
;
4905 extern __at(0x0E14) __sfr CCP1PPS
;
4906 extern __at(0x0E15) __sfr CCP2PPS
;
4907 extern __at(0x0E17) __sfr COGINPPS
;
4908 extern __at(0x0E20) __sfr SSPCLKPPS
;
4909 extern __at(0x0E21) __sfr SSPDATPPS
;
4910 extern __at(0x0E22) __sfr SSPSSPPS
;
4911 extern __at(0x0E24) __sfr RXPPS
;
4912 extern __at(0x0E25) __sfr CKPPS
;
4913 extern __at(0x0E28) __sfr CLCIN0PPS
;
4914 extern __at(0x0E29) __sfr CLCIN1PPS
;
4915 extern __at(0x0E2A) __sfr CLCIN2PPS
;
4916 extern __at(0x0E2B) __sfr CLCIN3PPS
;
4917 extern __at(0x0E90) __sfr RA0PPS
;
4918 extern __at(0x0E91) __sfr RA1PPS
;
4919 extern __at(0x0E92) __sfr RA2PPS
;
4920 extern __at(0x0E94) __sfr RA4PPS
;
4921 extern __at(0x0E95) __sfr RA5PPS
;
4922 extern __at(0x0E9C) __sfr RB4PPS
;
4923 extern __at(0x0E9D) __sfr RB5PPS
;
4924 extern __at(0x0E9E) __sfr RB6PPS
;
4925 extern __at(0x0E9F) __sfr RB7PPS
;
4926 extern __at(0x0EA0) __sfr RC0PPS
;
4927 extern __at(0x0EA1) __sfr RC1PPS
;
4928 extern __at(0x0EA2) __sfr RC2PPS
;
4929 extern __at(0x0EA3) __sfr RC3PPS
;
4930 extern __at(0x0EA4) __sfr RC4PPS
;
4931 extern __at(0x0EA5) __sfr RC5PPS
;
4932 extern __at(0x0EA6) __sfr RC6PPS
;
4933 extern __at(0x0EA7) __sfr RC7PPS
;
4935 //==============================================================================
4938 extern __at(0x0F0F) __sfr CLCDATA
;
4942 unsigned MCLC1OUT
: 1;
4943 unsigned MCLC2OUT
: 1;
4944 unsigned MCLC3OUT
: 1;
4952 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
4954 #define _MCLC1OUT 0x01
4955 #define _MCLC2OUT 0x02
4956 #define _MCLC3OUT 0x04
4958 //==============================================================================
4961 //==============================================================================
4964 extern __at(0x0F10) __sfr CLC1CON
;
4970 unsigned LC1MODE0
: 1;
4971 unsigned LC1MODE1
: 1;
4972 unsigned LC1MODE2
: 1;
4973 unsigned LC1INTN
: 1;
4974 unsigned LC1INTP
: 1;
4975 unsigned LC1OUT
: 1;
5000 unsigned LC1MODE
: 3;
5005 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
5007 #define _LC1MODE0 0x01
5009 #define _LC1MODE1 0x02
5011 #define _LC1MODE2 0x04
5013 #define _LC1INTN 0x08
5015 #define _LC1INTP 0x10
5017 #define _LC1OUT 0x20
5022 //==============================================================================
5025 //==============================================================================
5028 extern __at(0x0F11) __sfr CLC1POL
;
5034 unsigned LC1G1POL
: 1;
5035 unsigned LC1G2POL
: 1;
5036 unsigned LC1G3POL
: 1;
5037 unsigned LC1G4POL
: 1;
5041 unsigned LC1POL
: 1;
5057 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
5059 #define _LC1G1POL 0x01
5061 #define _LC1G2POL 0x02
5063 #define _LC1G3POL 0x04
5065 #define _LC1G4POL 0x08
5067 #define _LC1POL 0x80
5070 //==============================================================================
5073 //==============================================================================
5076 extern __at(0x0F12) __sfr CLC1SEL0
;
5082 unsigned LC1D1S0
: 1;
5083 unsigned LC1D1S1
: 1;
5084 unsigned LC1D1S2
: 1;
5085 unsigned LC1D1S3
: 1;
5086 unsigned LC1D1S4
: 1;
5106 unsigned LC1D1S
: 5;
5117 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
5119 #define _LC1D1S0 0x01
5121 #define _LC1D1S1 0x02
5123 #define _LC1D1S2 0x04
5125 #define _LC1D1S3 0x08
5127 #define _LC1D1S4 0x10
5130 //==============================================================================
5133 //==============================================================================
5136 extern __at(0x0F13) __sfr CLC1SEL1
;
5142 unsigned LC1D2S0
: 1;
5143 unsigned LC1D2S1
: 1;
5144 unsigned LC1D2S2
: 1;
5145 unsigned LC1D2S3
: 1;
5146 unsigned LC1D2S4
: 1;
5166 unsigned LC1D2S
: 5;
5177 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
5179 #define _LC1D2S0 0x01
5181 #define _LC1D2S1 0x02
5183 #define _LC1D2S2 0x04
5185 #define _LC1D2S3 0x08
5187 #define _LC1D2S4 0x10
5190 //==============================================================================
5193 //==============================================================================
5196 extern __at(0x0F14) __sfr CLC1SEL2
;
5202 unsigned LC1D3S0
: 1;
5203 unsigned LC1D3S1
: 1;
5204 unsigned LC1D3S2
: 1;
5205 unsigned LC1D3S3
: 1;
5206 unsigned LC1D3S4
: 1;
5226 unsigned LC1D3S
: 5;
5237 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
5239 #define _LC1D3S0 0x01
5241 #define _LC1D3S1 0x02
5243 #define _LC1D3S2 0x04
5245 #define _LC1D3S3 0x08
5247 #define _LC1D3S4 0x10
5250 //==============================================================================
5253 //==============================================================================
5256 extern __at(0x0F15) __sfr CLC1SEL3
;
5262 unsigned LC1D4S0
: 1;
5263 unsigned LC1D4S1
: 1;
5264 unsigned LC1D4S2
: 1;
5265 unsigned LC1D4S3
: 1;
5266 unsigned LC1D4S4
: 1;
5292 unsigned LC1D4S
: 5;
5297 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
5299 #define _LC1D4S0 0x01
5301 #define _LC1D4S1 0x02
5303 #define _LC1D4S2 0x04
5305 #define _LC1D4S3 0x08
5307 #define _LC1D4S4 0x10
5310 //==============================================================================
5313 //==============================================================================
5316 extern __at(0x0F16) __sfr CLC1GLS0
;
5322 unsigned LC1G1D1N
: 1;
5323 unsigned LC1G1D1T
: 1;
5324 unsigned LC1G1D2N
: 1;
5325 unsigned LC1G1D2T
: 1;
5326 unsigned LC1G1D3N
: 1;
5327 unsigned LC1G1D3T
: 1;
5328 unsigned LC1G1D4N
: 1;
5329 unsigned LC1G1D4T
: 1;
5345 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
5347 #define _LC1G1D1N 0x01
5349 #define _LC1G1D1T 0x02
5351 #define _LC1G1D2N 0x04
5353 #define _LC1G1D2T 0x08
5355 #define _LC1G1D3N 0x10
5357 #define _LC1G1D3T 0x20
5359 #define _LC1G1D4N 0x40
5361 #define _LC1G1D4T 0x80
5364 //==============================================================================
5367 //==============================================================================
5370 extern __at(0x0F17) __sfr CLC1GLS1
;
5376 unsigned LC1G2D1N
: 1;
5377 unsigned LC1G2D1T
: 1;
5378 unsigned LC1G2D2N
: 1;
5379 unsigned LC1G2D2T
: 1;
5380 unsigned LC1G2D3N
: 1;
5381 unsigned LC1G2D3T
: 1;
5382 unsigned LC1G2D4N
: 1;
5383 unsigned LC1G2D4T
: 1;
5399 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
5401 #define _CLC1GLS1_LC1G2D1N 0x01
5402 #define _CLC1GLS1_D1N 0x01
5403 #define _CLC1GLS1_LC1G2D1T 0x02
5404 #define _CLC1GLS1_D1T 0x02
5405 #define _CLC1GLS1_LC1G2D2N 0x04
5406 #define _CLC1GLS1_D2N 0x04
5407 #define _CLC1GLS1_LC1G2D2T 0x08
5408 #define _CLC1GLS1_D2T 0x08
5409 #define _CLC1GLS1_LC1G2D3N 0x10
5410 #define _CLC1GLS1_D3N 0x10
5411 #define _CLC1GLS1_LC1G2D3T 0x20
5412 #define _CLC1GLS1_D3T 0x20
5413 #define _CLC1GLS1_LC1G2D4N 0x40
5414 #define _CLC1GLS1_D4N 0x40
5415 #define _CLC1GLS1_LC1G2D4T 0x80
5416 #define _CLC1GLS1_D4T 0x80
5418 //==============================================================================
5421 //==============================================================================
5424 extern __at(0x0F18) __sfr CLC1GLS2
;
5430 unsigned LC1G3D1N
: 1;
5431 unsigned LC1G3D1T
: 1;
5432 unsigned LC1G3D2N
: 1;
5433 unsigned LC1G3D2T
: 1;
5434 unsigned LC1G3D3N
: 1;
5435 unsigned LC1G3D3T
: 1;
5436 unsigned LC1G3D4N
: 1;
5437 unsigned LC1G3D4T
: 1;
5453 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
5455 #define _CLC1GLS2_LC1G3D1N 0x01
5456 #define _CLC1GLS2_D1N 0x01
5457 #define _CLC1GLS2_LC1G3D1T 0x02
5458 #define _CLC1GLS2_D1T 0x02
5459 #define _CLC1GLS2_LC1G3D2N 0x04
5460 #define _CLC1GLS2_D2N 0x04
5461 #define _CLC1GLS2_LC1G3D2T 0x08
5462 #define _CLC1GLS2_D2T 0x08
5463 #define _CLC1GLS2_LC1G3D3N 0x10
5464 #define _CLC1GLS2_D3N 0x10
5465 #define _CLC1GLS2_LC1G3D3T 0x20
5466 #define _CLC1GLS2_D3T 0x20
5467 #define _CLC1GLS2_LC1G3D4N 0x40
5468 #define _CLC1GLS2_D4N 0x40
5469 #define _CLC1GLS2_LC1G3D4T 0x80
5470 #define _CLC1GLS2_D4T 0x80
5472 //==============================================================================
5475 //==============================================================================
5478 extern __at(0x0F19) __sfr CLC1GLS3
;
5484 unsigned LC1G4D1N
: 1;
5485 unsigned LC1G4D1T
: 1;
5486 unsigned LC1G4D2N
: 1;
5487 unsigned LC1G4D2T
: 1;
5488 unsigned LC1G4D3N
: 1;
5489 unsigned LC1G4D3T
: 1;
5490 unsigned LC1G4D4N
: 1;
5491 unsigned LC1G4D4T
: 1;
5507 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
5509 #define _LC1G4D1N 0x01
5511 #define _LC1G4D1T 0x02
5513 #define _LC1G4D2N 0x04
5515 #define _LC1G4D2T 0x08
5517 #define _LC1G4D3N 0x10
5519 #define _LC1G4D3T 0x20
5521 #define _LC1G4D4N 0x40
5523 #define _LC1G4D4T 0x80
5526 //==============================================================================
5529 //==============================================================================
5532 extern __at(0x0F1A) __sfr CLC2CON
;
5538 unsigned LC2MODE0
: 1;
5539 unsigned LC2MODE1
: 1;
5540 unsigned LC2MODE2
: 1;
5541 unsigned LC2INTN
: 1;
5542 unsigned LC2INTP
: 1;
5543 unsigned LC2OUT
: 1;
5568 unsigned LC2MODE
: 3;
5573 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
5575 #define _CLC2CON_LC2MODE0 0x01
5576 #define _CLC2CON_MODE0 0x01
5577 #define _CLC2CON_LC2MODE1 0x02
5578 #define _CLC2CON_MODE1 0x02
5579 #define _CLC2CON_LC2MODE2 0x04
5580 #define _CLC2CON_MODE2 0x04
5581 #define _CLC2CON_LC2INTN 0x08
5582 #define _CLC2CON_INTN 0x08
5583 #define _CLC2CON_LC2INTP 0x10
5584 #define _CLC2CON_INTP 0x10
5585 #define _CLC2CON_LC2OUT 0x20
5586 #define _CLC2CON_OUT 0x20
5587 #define _CLC2CON_LC2EN 0x80
5588 #define _CLC2CON_EN 0x80
5590 //==============================================================================
5593 //==============================================================================
5596 extern __at(0x0F1B) __sfr CLC2POL
;
5602 unsigned LC2G1POL
: 1;
5603 unsigned LC2G2POL
: 1;
5604 unsigned LC2G3POL
: 1;
5605 unsigned LC2G4POL
: 1;
5609 unsigned LC2POL
: 1;
5625 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
5627 #define _CLC2POL_LC2G1POL 0x01
5628 #define _CLC2POL_G1POL 0x01
5629 #define _CLC2POL_LC2G2POL 0x02
5630 #define _CLC2POL_G2POL 0x02
5631 #define _CLC2POL_LC2G3POL 0x04
5632 #define _CLC2POL_G3POL 0x04
5633 #define _CLC2POL_LC2G4POL 0x08
5634 #define _CLC2POL_G4POL 0x08
5635 #define _CLC2POL_LC2POL 0x80
5636 #define _CLC2POL_POL 0x80
5638 //==============================================================================
5641 //==============================================================================
5644 extern __at(0x0F1C) __sfr CLC2SEL0
;
5650 unsigned LC2D1S0
: 1;
5651 unsigned LC2D1S1
: 1;
5652 unsigned LC2D1S2
: 1;
5653 unsigned LC2D1S3
: 1;
5654 unsigned LC2D1S4
: 1;
5680 unsigned LC2D1S
: 5;
5685 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
5687 #define _CLC2SEL0_LC2D1S0 0x01
5688 #define _CLC2SEL0_D1S0 0x01
5689 #define _CLC2SEL0_LC2D1S1 0x02
5690 #define _CLC2SEL0_D1S1 0x02
5691 #define _CLC2SEL0_LC2D1S2 0x04
5692 #define _CLC2SEL0_D1S2 0x04
5693 #define _CLC2SEL0_LC2D1S3 0x08
5694 #define _CLC2SEL0_D1S3 0x08
5695 #define _CLC2SEL0_LC2D1S4 0x10
5696 #define _CLC2SEL0_D1S4 0x10
5698 //==============================================================================
5701 //==============================================================================
5704 extern __at(0x0F1D) __sfr CLC2SEL1
;
5710 unsigned LC2D2S0
: 1;
5711 unsigned LC2D2S1
: 1;
5712 unsigned LC2D2S2
: 1;
5713 unsigned LC2D2S3
: 1;
5714 unsigned LC2D2S4
: 1;
5740 unsigned LC2D2S
: 5;
5745 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
5747 #define _CLC2SEL1_LC2D2S0 0x01
5748 #define _CLC2SEL1_D2S0 0x01
5749 #define _CLC2SEL1_LC2D2S1 0x02
5750 #define _CLC2SEL1_D2S1 0x02
5751 #define _CLC2SEL1_LC2D2S2 0x04
5752 #define _CLC2SEL1_D2S2 0x04
5753 #define _CLC2SEL1_LC2D2S3 0x08
5754 #define _CLC2SEL1_D2S3 0x08
5755 #define _CLC2SEL1_LC2D2S4 0x10
5756 #define _CLC2SEL1_D2S4 0x10
5758 //==============================================================================
5761 //==============================================================================
5764 extern __at(0x0F1E) __sfr CLC2SEL2
;
5770 unsigned LC2D3S0
: 1;
5771 unsigned LC2D3S1
: 1;
5772 unsigned LC2D3S2
: 1;
5773 unsigned LC2D3S3
: 1;
5774 unsigned LC2D3S4
: 1;
5800 unsigned LC2D3S
: 5;
5805 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
5807 #define _CLC2SEL2_LC2D3S0 0x01
5808 #define _CLC2SEL2_D3S0 0x01
5809 #define _CLC2SEL2_LC2D3S1 0x02
5810 #define _CLC2SEL2_D3S1 0x02
5811 #define _CLC2SEL2_LC2D3S2 0x04
5812 #define _CLC2SEL2_D3S2 0x04
5813 #define _CLC2SEL2_LC2D3S3 0x08
5814 #define _CLC2SEL2_D3S3 0x08
5815 #define _CLC2SEL2_LC2D3S4 0x10
5816 #define _CLC2SEL2_D3S4 0x10
5818 //==============================================================================
5821 //==============================================================================
5824 extern __at(0x0F1F) __sfr CLC2SEL3
;
5830 unsigned LC2D4S0
: 1;
5831 unsigned LC2D4S1
: 1;
5832 unsigned LC2D4S2
: 1;
5833 unsigned LC2D4S3
: 1;
5834 unsigned LC2D4S4
: 1;
5860 unsigned LC2D4S
: 5;
5865 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
5867 #define _CLC2SEL3_LC2D4S0 0x01
5868 #define _CLC2SEL3_D4S0 0x01
5869 #define _CLC2SEL3_LC2D4S1 0x02
5870 #define _CLC2SEL3_D4S1 0x02
5871 #define _CLC2SEL3_LC2D4S2 0x04
5872 #define _CLC2SEL3_D4S2 0x04
5873 #define _CLC2SEL3_LC2D4S3 0x08
5874 #define _CLC2SEL3_D4S3 0x08
5875 #define _CLC2SEL3_LC2D4S4 0x10
5876 #define _CLC2SEL3_D4S4 0x10
5878 //==============================================================================
5881 //==============================================================================
5884 extern __at(0x0F20) __sfr CLC2GLS0
;
5890 unsigned LC2G1D1N
: 1;
5891 unsigned LC2G1D1T
: 1;
5892 unsigned LC2G1D2N
: 1;
5893 unsigned LC2G1D2T
: 1;
5894 unsigned LC2G1D3N
: 1;
5895 unsigned LC2G1D3T
: 1;
5896 unsigned LC2G1D4N
: 1;
5897 unsigned LC2G1D4T
: 1;
5913 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
5915 #define _CLC2GLS0_LC2G1D1N 0x01
5916 #define _CLC2GLS0_D1N 0x01
5917 #define _CLC2GLS0_LC2G1D1T 0x02
5918 #define _CLC2GLS0_D1T 0x02
5919 #define _CLC2GLS0_LC2G1D2N 0x04
5920 #define _CLC2GLS0_D2N 0x04
5921 #define _CLC2GLS0_LC2G1D2T 0x08
5922 #define _CLC2GLS0_D2T 0x08
5923 #define _CLC2GLS0_LC2G1D3N 0x10
5924 #define _CLC2GLS0_D3N 0x10
5925 #define _CLC2GLS0_LC2G1D3T 0x20
5926 #define _CLC2GLS0_D3T 0x20
5927 #define _CLC2GLS0_LC2G1D4N 0x40
5928 #define _CLC2GLS0_D4N 0x40
5929 #define _CLC2GLS0_LC2G1D4T 0x80
5930 #define _CLC2GLS0_D4T 0x80
5932 //==============================================================================
5935 //==============================================================================
5938 extern __at(0x0F21) __sfr CLC2GLS1
;
5944 unsigned LC2G2D1N
: 1;
5945 unsigned LC2G2D1T
: 1;
5946 unsigned LC2G2D2N
: 1;
5947 unsigned LC2G2D2T
: 1;
5948 unsigned LC2G2D3N
: 1;
5949 unsigned LC2G2D3T
: 1;
5950 unsigned LC2G2D4N
: 1;
5951 unsigned LC2G2D4T
: 1;
5967 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
5969 #define _CLC2GLS1_LC2G2D1N 0x01
5970 #define _CLC2GLS1_D1N 0x01
5971 #define _CLC2GLS1_LC2G2D1T 0x02
5972 #define _CLC2GLS1_D1T 0x02
5973 #define _CLC2GLS1_LC2G2D2N 0x04
5974 #define _CLC2GLS1_D2N 0x04
5975 #define _CLC2GLS1_LC2G2D2T 0x08
5976 #define _CLC2GLS1_D2T 0x08
5977 #define _CLC2GLS1_LC2G2D3N 0x10
5978 #define _CLC2GLS1_D3N 0x10
5979 #define _CLC2GLS1_LC2G2D3T 0x20
5980 #define _CLC2GLS1_D3T 0x20
5981 #define _CLC2GLS1_LC2G2D4N 0x40
5982 #define _CLC2GLS1_D4N 0x40
5983 #define _CLC2GLS1_LC2G2D4T 0x80
5984 #define _CLC2GLS1_D4T 0x80
5986 //==============================================================================
5989 //==============================================================================
5992 extern __at(0x0F22) __sfr CLC2GLS2
;
5998 unsigned LC2G3D1N
: 1;
5999 unsigned LC2G3D1T
: 1;
6000 unsigned LC2G3D2N
: 1;
6001 unsigned LC2G3D2T
: 1;
6002 unsigned LC2G3D3N
: 1;
6003 unsigned LC2G3D3T
: 1;
6004 unsigned LC2G3D4N
: 1;
6005 unsigned LC2G3D4T
: 1;
6021 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
6023 #define _CLC2GLS2_LC2G3D1N 0x01
6024 #define _CLC2GLS2_D1N 0x01
6025 #define _CLC2GLS2_LC2G3D1T 0x02
6026 #define _CLC2GLS2_D1T 0x02
6027 #define _CLC2GLS2_LC2G3D2N 0x04
6028 #define _CLC2GLS2_D2N 0x04
6029 #define _CLC2GLS2_LC2G3D2T 0x08
6030 #define _CLC2GLS2_D2T 0x08
6031 #define _CLC2GLS2_LC2G3D3N 0x10
6032 #define _CLC2GLS2_D3N 0x10
6033 #define _CLC2GLS2_LC2G3D3T 0x20
6034 #define _CLC2GLS2_D3T 0x20
6035 #define _CLC2GLS2_LC2G3D4N 0x40
6036 #define _CLC2GLS2_D4N 0x40
6037 #define _CLC2GLS2_LC2G3D4T 0x80
6038 #define _CLC2GLS2_D4T 0x80
6040 //==============================================================================
6043 //==============================================================================
6046 extern __at(0x0F23) __sfr CLC2GLS3
;
6052 unsigned LC2G4D1N
: 1;
6053 unsigned LC2G4D1T
: 1;
6054 unsigned LC2G4D2N
: 1;
6055 unsigned LC2G4D2T
: 1;
6056 unsigned LC2G4D3N
: 1;
6057 unsigned LC2G4D3T
: 1;
6058 unsigned LC2G4D4N
: 1;
6059 unsigned LC2G4D4T
: 1;
6075 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
6077 #define _CLC2GLS3_LC2G4D1N 0x01
6078 #define _CLC2GLS3_G4D1N 0x01
6079 #define _CLC2GLS3_LC2G4D1T 0x02
6080 #define _CLC2GLS3_G4D1T 0x02
6081 #define _CLC2GLS3_LC2G4D2N 0x04
6082 #define _CLC2GLS3_G4D2N 0x04
6083 #define _CLC2GLS3_LC2G4D2T 0x08
6084 #define _CLC2GLS3_G4D2T 0x08
6085 #define _CLC2GLS3_LC2G4D3N 0x10
6086 #define _CLC2GLS3_G4D3N 0x10
6087 #define _CLC2GLS3_LC2G4D3T 0x20
6088 #define _CLC2GLS3_G4D3T 0x20
6089 #define _CLC2GLS3_LC2G4D4N 0x40
6090 #define _CLC2GLS3_G4D4N 0x40
6091 #define _CLC2GLS3_LC2G4D4T 0x80
6092 #define _CLC2GLS3_G4D4T 0x80
6094 //==============================================================================
6097 //==============================================================================
6100 extern __at(0x0F24) __sfr CLC3CON
;
6106 unsigned LC3MODE0
: 1;
6107 unsigned LC3MODE1
: 1;
6108 unsigned LC3MODE2
: 1;
6109 unsigned LC3INTN
: 1;
6110 unsigned LC3INTP
: 1;
6111 unsigned LC3OUT
: 1;
6136 unsigned LC3MODE
: 3;
6141 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
6143 #define _CLC3CON_LC3MODE0 0x01
6144 #define _CLC3CON_MODE0 0x01
6145 #define _CLC3CON_LC3MODE1 0x02
6146 #define _CLC3CON_MODE1 0x02
6147 #define _CLC3CON_LC3MODE2 0x04
6148 #define _CLC3CON_MODE2 0x04
6149 #define _CLC3CON_LC3INTN 0x08
6150 #define _CLC3CON_INTN 0x08
6151 #define _CLC3CON_LC3INTP 0x10
6152 #define _CLC3CON_INTP 0x10
6153 #define _CLC3CON_LC3OUT 0x20
6154 #define _CLC3CON_OUT 0x20
6155 #define _CLC3CON_LC3EN 0x80
6156 #define _CLC3CON_EN 0x80
6158 //==============================================================================
6161 //==============================================================================
6164 extern __at(0x0F25) __sfr CLC3POL
;
6170 unsigned LC3G1POL
: 1;
6171 unsigned LC3G2POL
: 1;
6172 unsigned LC3G3POL
: 1;
6173 unsigned LC3G4POL
: 1;
6177 unsigned LC3POL
: 1;
6193 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
6195 #define _CLC3POL_LC3G1POL 0x01
6196 #define _CLC3POL_G1POL 0x01
6197 #define _CLC3POL_LC3G2POL 0x02
6198 #define _CLC3POL_G2POL 0x02
6199 #define _CLC3POL_LC3G3POL 0x04
6200 #define _CLC3POL_G3POL 0x04
6201 #define _CLC3POL_LC3G4POL 0x08
6202 #define _CLC3POL_G4POL 0x08
6203 #define _CLC3POL_LC3POL 0x80
6204 #define _CLC3POL_POL 0x80
6206 //==============================================================================
6209 //==============================================================================
6212 extern __at(0x0F26) __sfr CLC3SEL0
;
6218 unsigned LC3D1S0
: 1;
6219 unsigned LC3D1S1
: 1;
6220 unsigned LC3D1S2
: 1;
6221 unsigned LC3D1S3
: 1;
6222 unsigned LC3D1S4
: 1;
6242 unsigned LC3D1S
: 5;
6253 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
6255 #define _CLC3SEL0_LC3D1S0 0x01
6256 #define _CLC3SEL0_D1S0 0x01
6257 #define _CLC3SEL0_LC3D1S1 0x02
6258 #define _CLC3SEL0_D1S1 0x02
6259 #define _CLC3SEL0_LC3D1S2 0x04
6260 #define _CLC3SEL0_D1S2 0x04
6261 #define _CLC3SEL0_LC3D1S3 0x08
6262 #define _CLC3SEL0_D1S3 0x08
6263 #define _CLC3SEL0_LC3D1S4 0x10
6264 #define _CLC3SEL0_D1S4 0x10
6266 //==============================================================================
6269 //==============================================================================
6272 extern __at(0x0F27) __sfr CLC3SEL1
;
6278 unsigned LC3D2S0
: 1;
6279 unsigned LC3D2S1
: 1;
6280 unsigned LC3D2S2
: 1;
6281 unsigned LC3D2S3
: 1;
6282 unsigned LC3D2S4
: 1;
6308 unsigned LC3D2S
: 5;
6313 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
6315 #define _CLC3SEL1_LC3D2S0 0x01
6316 #define _CLC3SEL1_D2S0 0x01
6317 #define _CLC3SEL1_LC3D2S1 0x02
6318 #define _CLC3SEL1_D2S1 0x02
6319 #define _CLC3SEL1_LC3D2S2 0x04
6320 #define _CLC3SEL1_D2S2 0x04
6321 #define _CLC3SEL1_LC3D2S3 0x08
6322 #define _CLC3SEL1_D2S3 0x08
6323 #define _CLC3SEL1_LC3D2S4 0x10
6324 #define _CLC3SEL1_D2S4 0x10
6326 //==============================================================================
6329 //==============================================================================
6332 extern __at(0x0F28) __sfr CLC3SEL2
;
6338 unsigned LC3D3S0
: 1;
6339 unsigned LC3D3S1
: 1;
6340 unsigned LC3D3S2
: 1;
6341 unsigned LC3D3S3
: 1;
6342 unsigned LC3D3S4
: 1;
6362 unsigned LC3D3S
: 5;
6373 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
6375 #define _CLC3SEL2_LC3D3S0 0x01
6376 #define _CLC3SEL2_D3S0 0x01
6377 #define _CLC3SEL2_LC3D3S1 0x02
6378 #define _CLC3SEL2_D3S1 0x02
6379 #define _CLC3SEL2_LC3D3S2 0x04
6380 #define _CLC3SEL2_D3S2 0x04
6381 #define _CLC3SEL2_LC3D3S3 0x08
6382 #define _CLC3SEL2_D3S3 0x08
6383 #define _CLC3SEL2_LC3D3S4 0x10
6384 #define _CLC3SEL2_D3S4 0x10
6386 //==============================================================================
6389 //==============================================================================
6392 extern __at(0x0F29) __sfr CLC3SEL3
;
6398 unsigned LC3D4S0
: 1;
6399 unsigned LC3D4S1
: 1;
6400 unsigned LC3D4S2
: 1;
6401 unsigned LC3D4S3
: 1;
6402 unsigned LC3D4S4
: 1;
6422 unsigned LC3D4S
: 5;
6433 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
6435 #define _CLC3SEL3_LC3D4S0 0x01
6436 #define _CLC3SEL3_D4S0 0x01
6437 #define _CLC3SEL3_LC3D4S1 0x02
6438 #define _CLC3SEL3_D4S1 0x02
6439 #define _CLC3SEL3_LC3D4S2 0x04
6440 #define _CLC3SEL3_D4S2 0x04
6441 #define _CLC3SEL3_LC3D4S3 0x08
6442 #define _CLC3SEL3_D4S3 0x08
6443 #define _CLC3SEL3_LC3D4S4 0x10
6444 #define _CLC3SEL3_D4S4 0x10
6446 //==============================================================================
6449 //==============================================================================
6452 extern __at(0x0F2A) __sfr CLC3GLS0
;
6458 unsigned LC3G1D1N
: 1;
6459 unsigned LC3G1D1T
: 1;
6460 unsigned LC3G1D2N
: 1;
6461 unsigned LC3G1D2T
: 1;
6462 unsigned LC3G1D3N
: 1;
6463 unsigned LC3G1D3T
: 1;
6464 unsigned LC3G1D4N
: 1;
6465 unsigned LC3G1D4T
: 1;
6481 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
6483 #define _CLC3GLS0_LC3G1D1N 0x01
6484 #define _CLC3GLS0_D1N 0x01
6485 #define _CLC3GLS0_LC3G1D1T 0x02
6486 #define _CLC3GLS0_D1T 0x02
6487 #define _CLC3GLS0_LC3G1D2N 0x04
6488 #define _CLC3GLS0_D2N 0x04
6489 #define _CLC3GLS0_LC3G1D2T 0x08
6490 #define _CLC3GLS0_D2T 0x08
6491 #define _CLC3GLS0_LC3G1D3N 0x10
6492 #define _CLC3GLS0_D3N 0x10
6493 #define _CLC3GLS0_LC3G1D3T 0x20
6494 #define _CLC3GLS0_D3T 0x20
6495 #define _CLC3GLS0_LC3G1D4N 0x40
6496 #define _CLC3GLS0_D4N 0x40
6497 #define _CLC3GLS0_LC3G1D4T 0x80
6498 #define _CLC3GLS0_D4T 0x80
6500 //==============================================================================
6503 //==============================================================================
6506 extern __at(0x0F2B) __sfr CLC3GLS1
;
6512 unsigned LC3G2D1N
: 1;
6513 unsigned LC3G2D1T
: 1;
6514 unsigned LC3G2D2N
: 1;
6515 unsigned LC3G2D2T
: 1;
6516 unsigned LC3G2D3N
: 1;
6517 unsigned LC3G2D3T
: 1;
6518 unsigned LC3G2D4N
: 1;
6519 unsigned LC3G2D4T
: 1;
6535 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
6537 #define _CLC3GLS1_LC3G2D1N 0x01
6538 #define _CLC3GLS1_D1N 0x01
6539 #define _CLC3GLS1_LC3G2D1T 0x02
6540 #define _CLC3GLS1_D1T 0x02
6541 #define _CLC3GLS1_LC3G2D2N 0x04
6542 #define _CLC3GLS1_D2N 0x04
6543 #define _CLC3GLS1_LC3G2D2T 0x08
6544 #define _CLC3GLS1_D2T 0x08
6545 #define _CLC3GLS1_LC3G2D3N 0x10
6546 #define _CLC3GLS1_D3N 0x10
6547 #define _CLC3GLS1_LC3G2D3T 0x20
6548 #define _CLC3GLS1_D3T 0x20
6549 #define _CLC3GLS1_LC3G2D4N 0x40
6550 #define _CLC3GLS1_D4N 0x40
6551 #define _CLC3GLS1_LC3G2D4T 0x80
6552 #define _CLC3GLS1_D4T 0x80
6554 //==============================================================================
6557 //==============================================================================
6560 extern __at(0x0F2C) __sfr CLC3GLS2
;
6566 unsigned LC3G3D1N
: 1;
6567 unsigned LC3G3D1T
: 1;
6568 unsigned LC3G3D2N
: 1;
6569 unsigned LC3G3D2T
: 1;
6570 unsigned LC3G3D3N
: 1;
6571 unsigned LC3G3D3T
: 1;
6572 unsigned LC3G3D4N
: 1;
6573 unsigned LC3G3D4T
: 1;
6589 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
6591 #define _CLC3GLS2_LC3G3D1N 0x01
6592 #define _CLC3GLS2_D1N 0x01
6593 #define _CLC3GLS2_LC3G3D1T 0x02
6594 #define _CLC3GLS2_D1T 0x02
6595 #define _CLC3GLS2_LC3G3D2N 0x04
6596 #define _CLC3GLS2_D2N 0x04
6597 #define _CLC3GLS2_LC3G3D2T 0x08
6598 #define _CLC3GLS2_D2T 0x08
6599 #define _CLC3GLS2_LC3G3D3N 0x10
6600 #define _CLC3GLS2_D3N 0x10
6601 #define _CLC3GLS2_LC3G3D3T 0x20
6602 #define _CLC3GLS2_D3T 0x20
6603 #define _CLC3GLS2_LC3G3D4N 0x40
6604 #define _CLC3GLS2_D4N 0x40
6605 #define _CLC3GLS2_LC3G3D4T 0x80
6606 #define _CLC3GLS2_D4T 0x80
6608 //==============================================================================
6611 //==============================================================================
6614 extern __at(0x0F2D) __sfr CLC3GLS3
;
6620 unsigned LC3G4D1N
: 1;
6621 unsigned LC3G4D1T
: 1;
6622 unsigned LC3G4D2N
: 1;
6623 unsigned LC3G4D2T
: 1;
6624 unsigned LC3G4D3N
: 1;
6625 unsigned LC3G4D3T
: 1;
6626 unsigned LC3G4D4N
: 1;
6627 unsigned LC3G4D4T
: 1;
6643 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
6645 #define _CLC3GLS3_LC3G4D1N 0x01
6646 #define _CLC3GLS3_G4D1N 0x01
6647 #define _CLC3GLS3_LC3G4D1T 0x02
6648 #define _CLC3GLS3_G4D1T 0x02
6649 #define _CLC3GLS3_LC3G4D2N 0x04
6650 #define _CLC3GLS3_G4D2N 0x04
6651 #define _CLC3GLS3_LC3G4D2T 0x08
6652 #define _CLC3GLS3_G4D2T 0x08
6653 #define _CLC3GLS3_LC3G4D3N 0x10
6654 #define _CLC3GLS3_G4D3N 0x10
6655 #define _CLC3GLS3_LC3G4D3T 0x20
6656 #define _CLC3GLS3_G4D3T 0x20
6657 #define _CLC3GLS3_LC3G4D4N 0x40
6658 #define _CLC3GLS3_G4D4N 0x40
6659 #define _CLC3GLS3_LC3G4D4T 0x80
6660 #define _CLC3GLS3_G4D4T 0x80
6662 //==============================================================================
6665 //==============================================================================
6668 extern __at(0x0F9E) __sfr ICDBK0H
;
6682 extern __at(0x0F9E) volatile __ICDBK0Hbits_t ICDBK0Hbits
;
6692 //==============================================================================
6695 //==============================================================================
6698 extern __at(0x0FE4) __sfr STATUS_SHAD
;
6702 unsigned C_SHAD
: 1;
6703 unsigned DC_SHAD
: 1;
6704 unsigned Z_SHAD
: 1;
6710 } __STATUS_SHADbits_t
;
6712 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
6714 #define _C_SHAD 0x01
6715 #define _DC_SHAD 0x02
6716 #define _Z_SHAD 0x04
6718 //==============================================================================
6720 extern __at(0x0FE5) __sfr WREG_SHAD
;
6721 extern __at(0x0FE6) __sfr BSR_SHAD
;
6722 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
6723 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
6724 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
6725 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
6726 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
6727 extern __at(0x0FED) __sfr STKPTR
;
6728 extern __at(0x0FEE) __sfr TOSL
;
6729 extern __at(0x0FEF) __sfr TOSH
;
6731 //==============================================================================
6733 // Configuration Bits
6735 //==============================================================================
6737 #define _CONFIG1 0x8007
6738 #define _CONFIG2 0x8008
6740 //----------------------------- CONFIG1 Options -------------------------------
6742 #define _FOSC_LP 0x3FF8 // LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins.
6743 #define _FOSC_XT 0x3FF9 // XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins.
6744 #define _FOSC_HS 0x3FFA // HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins.
6745 #define _FOSC_EXTRC 0x3FFB // EXTRC oscillator: External RC circuit connected to CLKIN pin.
6746 #define _FOSC_INTOSC 0x3FFC // INTOSC oscillator: I/O function on CLKIN pin.
6747 #define _FOSC_ECL 0x3FFD // ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pins.
6748 #define _FOSC_ECM 0x3FFE // ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pins.
6749 #define _FOSC_ECH 0x3FFF // ECH, External Clock, High Power Mode (4-20 MHz): device clock supplied to CLKIN pins.
6750 #define _WDTE_OFF 0x3FE7 // WDT disabled.
6751 #define _WDTE_SWDTEN 0x3FEF // WDT controlled by the SWDTEN bit in the WDTCON register.
6752 #define _WDTE_NSLEEP 0x3FF7 // WDT enabled while running and disabled in Sleep.
6753 #define _WDTE_ON 0x3FFF // WDT enabled.
6754 #define _PWRTE_ON 0x3FDF // PWRT enabled.
6755 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
6756 #define _MCLRE_OFF 0x3FBF // MCLR/VPP pin function is digital input.
6757 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR.
6758 #define _CP_ON 0x3F7F // Program memory code protection is enabled.
6759 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
6760 #define _BOREN_OFF 0x39FF // Brown-out Reset disabled.
6761 #define _BOREN_SBODEN 0x3BFF // Brown-out Reset controlled by the SBOREN bit in the BORCON register.
6762 #define _BOREN_NSLEEP 0x3DFF // Brown-out Reset enabled while running and disabled in Sleep.
6763 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled.
6764 #define _CLKOUTEN_ON 0x37FF // CLKOUT function is enabled on the CLKOUT pin.
6765 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
6766 #define _IESO_OFF 0x2FFF // Internal/External Switchover Mode is disabled.
6767 #define _IESO_ON 0x3FFF // Internal/External Switchover Mode is enabled.
6768 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
6769 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
6771 //----------------------------- CONFIG2 Options -------------------------------
6773 #define _WRT_ALL 0x3FFC // 000h to 1FFFh write protected, no addresses may be modified by EECON control.
6774 #define _WRT_HALF 0x3FFD // 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control.
6775 #define _WRT_BOOT 0x3FFE // 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control.
6776 #define _WRT_OFF 0x3FFF // Write protection off.
6777 #define _PPS1WAY_OFF 0x3FFB // The PPSLOCK bit can be set and cleared repeatedly by software.
6778 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit cannot be cleared once it is set by software.
6779 #define _ZCDDIS_OFF 0x3F7F // Zero-cross detect circuit is enabled at POR.
6780 #define _ZCDDIS_ON 0x3FFF // Zero-cross detect circuit is disabled at POR.
6781 #define _PLLEN_OFF 0x3EFF // 4x PLL is enabled when software sets the SPLLEN bit.
6782 #define _PLLEN_ON 0x3FFF // 4x PLL is always enabled.
6783 #define _STVREN_OFF 0x3DFF // Stack Overflow or Underflow will not cause a Reset.
6784 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
6785 #define _BORV_HI 0x3BFF // Brown-out Reset Voltage (Vbor), high trip point selected.
6786 #define _BORV_LO 0x3FFF // Brown-out Reset Voltage (Vbor), low trip point selected.
6787 #define _LPBOR_ON 0x37FF // Low-Power BOR is enabled.
6788 #define _LPBOR_OFF 0x3FFF // Low-Power BOR is disabled.
6789 #define _DEBUG_ON 0x2FFF // In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger.
6790 #define _DEBUG_OFF 0x3FFF // In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins.
6791 #define _LVP_OFF 0x1FFF // High-voltage on MCLR/VPP must be used for programming.
6792 #define _LVP_ON 0x3FFF // Low-voltage programming enabled.
6794 //==============================================================================
6796 #define _DEVID1 0x8006
6798 #define _IDLOC0 0x8000
6799 #define _IDLOC1 0x8001
6800 #define _IDLOC2 0x8002
6801 #define _IDLOC3 0x8003
6803 //==============================================================================
6805 #ifndef NO_BIT_DEFINES
6807 #define ADON ADCON0bits.ADON // bit 0
6808 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
6809 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
6810 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
6811 #define CHS0 ADCON0bits.CHS0 // bit 2
6812 #define CHS1 ADCON0bits.CHS1 // bit 3
6813 #define CHS2 ADCON0bits.CHS2 // bit 4
6814 #define CHS3 ADCON0bits.CHS3 // bit 5
6815 #define CHS4 ADCON0bits.CHS4 // bit 6
6817 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
6818 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
6819 #define ADNREF ADCON1bits.ADNREF // bit 2
6820 #define ADFM ADCON1bits.ADFM // bit 7
6822 #define TRIGSEL0 ADCON2bits.TRIGSEL0 // bit 4
6823 #define TRIGSEL1 ADCON2bits.TRIGSEL1 // bit 5
6824 #define TRIGSEL2 ADCON2bits.TRIGSEL2 // bit 6
6825 #define TRIGSEL3 ADCON2bits.TRIGSEL3 // bit 7
6827 #define ANSA0 ANSELAbits.ANSA0 // bit 0
6828 #define ANSA1 ANSELAbits.ANSA1 // bit 1
6829 #define ANSA2 ANSELAbits.ANSA2 // bit 2
6830 #define ANSA4 ANSELAbits.ANSA4 // bit 4
6831 #define ANS5 ANSELAbits.ANS5 // bit 5
6833 #define ANSB4 ANSELBbits.ANSB4 // bit 4
6834 #define ANSB5 ANSELBbits.ANSB5 // bit 5
6836 #define ANSC0 ANSELCbits.ANSC0 // bit 0
6837 #define ANSC1 ANSELCbits.ANSC1 // bit 1
6838 #define ANSC2 ANSELCbits.ANSC2 // bit 2
6839 #define ANSC3 ANSELCbits.ANSC3 // bit 3
6840 #define ANSC6 ANSELCbits.ANSC6 // bit 6
6841 #define ANSC7 ANSELCbits.ANSC7 // bit 7
6843 #define ABDEN BAUD1CONbits.ABDEN // bit 0
6844 #define WUE BAUD1CONbits.WUE // bit 1
6845 #define BRG16 BAUD1CONbits.BRG16 // bit 3
6846 #define SCKP BAUD1CONbits.SCKP // bit 4
6847 #define RCIDL BAUD1CONbits.RCIDL // bit 6
6848 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
6850 #define BORRDY BORCONbits.BORRDY // bit 0
6851 #define BORFS BORCONbits.BORFS // bit 6
6852 #define SBOREN BORCONbits.SBOREN // bit 7
6854 #define BSR0 BSRbits.BSR0 // bit 0
6855 #define BSR1 BSRbits.BSR1 // bit 1
6856 #define BSR2 BSRbits.BSR2 // bit 2
6857 #define BSR3 BSRbits.BSR3 // bit 3
6858 #define BSR4 BSRbits.BSR4 // bit 4
6860 #define CCP1M0 CCP1CONbits.CCP1M0 // bit 0
6861 #define CCP1M1 CCP1CONbits.CCP1M1 // bit 1
6862 #define CCP1M2 CCP1CONbits.CCP1M2 // bit 2
6863 #define CCP1M3 CCP1CONbits.CCP1M3 // bit 3
6864 #define DC1B0 CCP1CONbits.DC1B0 // bit 4, shadows bit in CCP1CONbits
6865 #define CCP1Y CCP1CONbits.CCP1Y // bit 4, shadows bit in CCP1CONbits
6866 #define DC1B1 CCP1CONbits.DC1B1 // bit 5, shadows bit in CCP1CONbits
6867 #define CCP1X CCP1CONbits.CCP1X // bit 5, shadows bit in CCP1CONbits
6869 #define CCP2M0 CCP2CONbits.CCP2M0 // bit 0
6870 #define CCP2M1 CCP2CONbits.CCP2M1 // bit 1
6871 #define CCP2M2 CCP2CONbits.CCP2M2 // bit 2
6872 #define CCP2M3 CCP2CONbits.CCP2M3 // bit 3
6873 #define DC2B0 CCP2CONbits.DC2B0 // bit 4, shadows bit in CCP2CONbits
6874 #define CCP2Y CCP2CONbits.CCP2Y // bit 4, shadows bit in CCP2CONbits
6875 #define DC2B1 CCP2CONbits.DC2B1 // bit 5, shadows bit in CCP2CONbits
6876 #define CCP2X CCP2CONbits.CCP2X // bit 5, shadows bit in CCP2CONbits
6878 #define C1TSEL0 CCPTMRSbits.C1TSEL0 // bit 0
6879 #define C1TSEL1 CCPTMRSbits.C1TSEL1 // bit 1
6880 #define C2TSEL0 CCPTMRSbits.C2TSEL0 // bit 2
6881 #define C2TSEL1 CCPTMRSbits.C2TSEL1 // bit 3
6882 #define P3TSEL0 CCPTMRSbits.P3TSEL0 // bit 4
6883 #define P3TSEL1 CCPTMRSbits.P3TSEL1 // bit 5
6884 #define P4TSEL0 CCPTMRSbits.P4TSEL0 // bit 6
6885 #define P4TSEL1 CCPTMRSbits.P4TSEL1 // bit 7
6887 #define LC1MODE0 CLC1CONbits.LC1MODE0 // bit 0, shadows bit in CLC1CONbits
6888 #define MODE0 CLC1CONbits.MODE0 // bit 0, shadows bit in CLC1CONbits
6889 #define LC1MODE1 CLC1CONbits.LC1MODE1 // bit 1, shadows bit in CLC1CONbits
6890 #define MODE1 CLC1CONbits.MODE1 // bit 1, shadows bit in CLC1CONbits
6891 #define LC1MODE2 CLC1CONbits.LC1MODE2 // bit 2, shadows bit in CLC1CONbits
6892 #define MODE2 CLC1CONbits.MODE2 // bit 2, shadows bit in CLC1CONbits
6893 #define LC1INTN CLC1CONbits.LC1INTN // bit 3, shadows bit in CLC1CONbits
6894 #define INTN CLC1CONbits.INTN // bit 3, shadows bit in CLC1CONbits
6895 #define LC1INTP CLC1CONbits.LC1INTP // bit 4, shadows bit in CLC1CONbits
6896 #define INTP CLC1CONbits.INTP // bit 4, shadows bit in CLC1CONbits
6897 #define LC1OUT CLC1CONbits.LC1OUT // bit 5, shadows bit in CLC1CONbits
6898 #define OUT CLC1CONbits.OUT // bit 5, shadows bit in CLC1CONbits
6899 #define LC1EN CLC1CONbits.LC1EN // bit 7, shadows bit in CLC1CONbits
6900 #define EN CLC1CONbits.EN // bit 7, shadows bit in CLC1CONbits
6902 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
6903 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
6904 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
6905 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
6906 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
6907 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
6908 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
6909 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
6910 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
6911 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
6912 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
6913 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
6914 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
6915 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
6916 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
6917 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
6919 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
6920 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
6921 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
6922 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
6923 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
6924 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
6925 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
6926 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
6927 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
6928 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
6929 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
6930 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
6931 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
6932 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
6933 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
6934 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
6936 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
6937 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
6938 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
6939 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
6940 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
6941 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
6942 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
6943 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
6944 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
6945 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
6947 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
6948 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
6949 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
6950 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
6951 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
6952 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
6953 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
6954 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
6955 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
6956 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
6958 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
6959 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
6960 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
6961 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
6962 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
6963 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
6964 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
6965 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
6966 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
6967 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
6969 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
6970 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
6971 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
6972 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
6973 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
6974 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
6975 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
6976 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
6977 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
6978 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
6980 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
6981 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
6982 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
6983 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
6984 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
6985 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
6986 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
6987 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
6988 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
6989 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
6991 #define MCLC1OUT CLCDATAbits.MCLC1OUT // bit 0
6992 #define MCLC2OUT CLCDATAbits.MCLC2OUT // bit 1
6993 #define MCLC3OUT CLCDATAbits.MCLC3OUT // bit 2
6995 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
6996 #define C1HYS CM1CON0bits.C1HYS // bit 1
6997 #define C1SP CM1CON0bits.C1SP // bit 2
6998 #define C1ZLF CM1CON0bits.C1ZLF // bit 3
6999 #define C1POL CM1CON0bits.C1POL // bit 4
7000 #define C1OUT CM1CON0bits.C1OUT // bit 6
7001 #define C1ON CM1CON0bits.C1ON // bit 7
7003 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
7004 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
7005 #define C1NCH2 CM1CON1bits.C1NCH2 // bit 2
7006 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 3
7007 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 4
7008 #define C1PCH2 CM1CON1bits.C1PCH2 // bit 5
7009 #define C1INTN CM1CON1bits.C1INTN // bit 6
7010 #define C1INTP CM1CON1bits.C1INTP // bit 7
7012 #define C2SYNC CM2CON0bits.C2SYNC // bit 0
7013 #define C2HYS CM2CON0bits.C2HYS // bit 1
7014 #define C2SP CM2CON0bits.C2SP // bit 2
7015 #define C2ZLF CM2CON0bits.C2ZLF // bit 3
7016 #define C2POL CM2CON0bits.C2POL // bit 4
7017 #define C2OUT CM2CON0bits.C2OUT // bit 6
7018 #define C2ON CM2CON0bits.C2ON // bit 7
7020 #define C2NCH0 CM2CON1bits.C2NCH0 // bit 0
7021 #define C2NCH1 CM2CON1bits.C2NCH1 // bit 1
7022 #define C2NCH2 CM2CON1bits.C2NCH2 // bit 2
7023 #define C2PCH0 CM2CON1bits.C2PCH0 // bit 3
7024 #define C2PCH1 CM2CON1bits.C2PCH1 // bit 4
7025 #define C2PCH2 CM2CON1bits.C2PCH2 // bit 5
7026 #define C2INTN CM2CON1bits.C2INTN // bit 6
7027 #define C2INTP CM2CON1bits.C2INTP // bit 7
7029 #define MC1OUT CMOUTbits.MC1OUT // bit 0
7030 #define MC2OUT CMOUTbits.MC2OUT // bit 1
7032 #define G1ASDAC0 COG1ASD0bits.G1ASDAC0 // bit 2
7033 #define G1ASDAC1 COG1ASD0bits.G1ASDAC1 // bit 3
7034 #define G1ASDBD0 COG1ASD0bits.G1ASDBD0 // bit 4
7035 #define G1ASDBD1 COG1ASD0bits.G1ASDBD1 // bit 5
7036 #define G1ARSEN COG1ASD0bits.G1ARSEN // bit 6
7037 #define G1ASE COG1ASD0bits.G1ASE // bit 7
7039 #define G1AS0E COG1ASD1bits.G1AS0E // bit 0
7040 #define G1AS1E COG1ASD1bits.G1AS1E // bit 1
7041 #define G1AS2E COG1ASD1bits.G1AS2E // bit 2
7042 #define G1AS3E COG1ASD1bits.G1AS3E // bit 3
7044 #define G1BLKF0 COG1BLKFbits.G1BLKF0 // bit 0
7045 #define G1BLKF1 COG1BLKFbits.G1BLKF1 // bit 1
7046 #define G1BLKF2 COG1BLKFbits.G1BLKF2 // bit 2
7047 #define G1BLKF3 COG1BLKFbits.G1BLKF3 // bit 3
7048 #define G1BLKF4 COG1BLKFbits.G1BLKF4 // bit 4
7049 #define G1BLKF5 COG1BLKFbits.G1BLKF5 // bit 5
7051 #define G1BLKR0 COG1BLKRbits.G1BLKR0 // bit 0
7052 #define G1BLKR1 COG1BLKRbits.G1BLKR1 // bit 1
7053 #define G1BLKR2 COG1BLKRbits.G1BLKR2 // bit 2
7054 #define G1BLKR3 COG1BLKRbits.G1BLKR3 // bit 3
7055 #define G1BLKR4 COG1BLKRbits.G1BLKR4 // bit 4
7056 #define G1BLKR5 COG1BLKRbits.G1BLKR5 // bit 5
7058 #define G1MD0 COG1CON0bits.G1MD0 // bit 0
7059 #define G1MD1 COG1CON0bits.G1MD1 // bit 1
7060 #define G1MD2 COG1CON0bits.G1MD2 // bit 2
7061 #define G1CS0 COG1CON0bits.G1CS0 // bit 3
7062 #define G1CS1 COG1CON0bits.G1CS1 // bit 4
7063 #define G1LD COG1CON0bits.G1LD // bit 6
7064 #define G1EN COG1CON0bits.G1EN // bit 7
7066 #define G1POLA COG1CON1bits.G1POLA // bit 0
7067 #define G1POLB COG1CON1bits.G1POLB // bit 1
7068 #define G1POLC COG1CON1bits.G1POLC // bit 2
7069 #define G1POLD COG1CON1bits.G1POLD // bit 3
7070 #define G1FDBS COG1CON1bits.G1FDBS // bit 6
7071 #define G1RDBS COG1CON1bits.G1RDBS // bit 7
7073 #define G1DBF0 COG1DBFbits.G1DBF0 // bit 0
7074 #define G1DBF1 COG1DBFbits.G1DBF1 // bit 1
7075 #define G1DBF2 COG1DBFbits.G1DBF2 // bit 2
7076 #define G1DBF3 COG1DBFbits.G1DBF3 // bit 3
7077 #define G1DBF4 COG1DBFbits.G1DBF4 // bit 4
7078 #define G1DBF5 COG1DBFbits.G1DBF5 // bit 5
7080 #define G1DBR0 COG1DBRbits.G1DBR0 // bit 0
7081 #define G1DBR1 COG1DBRbits.G1DBR1 // bit 1
7082 #define G1DBR2 COG1DBRbits.G1DBR2 // bit 2
7083 #define G1DBR3 COG1DBRbits.G1DBR3 // bit 3
7084 #define G1DBR4 COG1DBRbits.G1DBR4 // bit 4
7085 #define G1DBR5 COG1DBRbits.G1DBR5 // bit 5
7087 #define G1FIS0 COG1FISbits.G1FIS0 // bit 0
7088 #define G1FIS1 COG1FISbits.G1FIS1 // bit 1
7089 #define G1FIS2 COG1FISbits.G1FIS2 // bit 2
7090 #define G1FIS3 COG1FISbits.G1FIS3 // bit 3
7091 #define G1FIS4 COG1FISbits.G1FIS4 // bit 4
7092 #define G1FIS5 COG1FISbits.G1FIS5 // bit 5
7093 #define G1FIS6 COG1FISbits.G1FIS6 // bit 6
7095 #define G1FSIM0 COG1FSIMbits.G1FSIM0 // bit 0
7096 #define G1FSIM1 COG1FSIMbits.G1FSIM1 // bit 1
7097 #define G1FSIM2 COG1FSIMbits.G1FSIM2 // bit 2
7098 #define G1FSIM3 COG1FSIMbits.G1FSIM3 // bit 3
7099 #define G1FSIM4 COG1FSIMbits.G1FSIM4 // bit 4
7100 #define G1FSIM5 COG1FSIMbits.G1FSIM5 // bit 5
7101 #define G1FSIM6 COG1FSIMbits.G1FSIM6 // bit 6
7103 #define G1PHF0 COG1PHFbits.G1PHF0 // bit 0
7104 #define G1PHF1 COG1PHFbits.G1PHF1 // bit 1
7105 #define G1PHF2 COG1PHFbits.G1PHF2 // bit 2
7106 #define G1PHF3 COG1PHFbits.G1PHF3 // bit 3
7107 #define G1PHF4 COG1PHFbits.G1PHF4 // bit 4
7108 #define G1PHF5 COG1PHFbits.G1PHF5 // bit 5
7110 #define G1PHR0 COG1PHRbits.G1PHR0 // bit 0
7111 #define G1PHR1 COG1PHRbits.G1PHR1 // bit 1
7112 #define G1PHR2 COG1PHRbits.G1PHR2 // bit 2
7113 #define G1PHR3 COG1PHRbits.G1PHR3 // bit 3
7114 #define G1PHR4 COG1PHRbits.G1PHR4 // bit 4
7115 #define G1PHR5 COG1PHRbits.G1PHR5 // bit 5
7117 #define G1RIS0 COG1RISbits.G1RIS0 // bit 0
7118 #define G1RIS1 COG1RISbits.G1RIS1 // bit 1
7119 #define G1RIS2 COG1RISbits.G1RIS2 // bit 2
7120 #define G1RIS3 COG1RISbits.G1RIS3 // bit 3
7121 #define G1RIS4 COG1RISbits.G1RIS4 // bit 4
7122 #define G1RIS5 COG1RISbits.G1RIS5 // bit 5
7123 #define G1RIS6 COG1RISbits.G1RIS6 // bit 6
7125 #define G1RSIM0 COG1RSIMbits.G1RSIM0 // bit 0
7126 #define G1RSIM1 COG1RSIMbits.G1RSIM1 // bit 1
7127 #define G1RSIM2 COG1RSIMbits.G1RSIM2 // bit 2
7128 #define G1RSIM3 COG1RSIMbits.G1RSIM3 // bit 3
7129 #define G1RSIM4 COG1RSIMbits.G1RSIM4 // bit 4
7130 #define G1RSIM5 COG1RSIMbits.G1RSIM5 // bit 5
7131 #define G1RSIM6 COG1RSIMbits.G1RSIM6 // bit 6
7133 #define G1STRA COG1STRbits.G1STRA // bit 0
7134 #define G1STRB COG1STRbits.G1STRB // bit 1
7135 #define G1STRC COG1STRbits.G1STRC // bit 2
7136 #define G1STRD COG1STRbits.G1STRD // bit 3
7137 #define G1SDATA COG1STRbits.G1SDATA // bit 4
7138 #define G1SDATB COG1STRbits.G1SDATB // bit 5
7139 #define G1SDATC COG1STRbits.G1SDATC // bit 6
7140 #define G1SDATD COG1STRbits.G1SDATD // bit 7
7142 #define DAC1NSS DAC1CON0bits.DAC1NSS // bit 0, shadows bit in DAC1CON0bits
7143 #define DACNSS DAC1CON0bits.DACNSS // bit 0, shadows bit in DAC1CON0bits
7144 #define DAC1PSS0 DAC1CON0bits.DAC1PSS0 // bit 2, shadows bit in DAC1CON0bits
7145 #define DACPSS0 DAC1CON0bits.DACPSS0 // bit 2, shadows bit in DAC1CON0bits
7146 #define DAC1PSS1 DAC1CON0bits.DAC1PSS1 // bit 3, shadows bit in DAC1CON0bits
7147 #define DACPSS1 DAC1CON0bits.DACPSS1 // bit 3, shadows bit in DAC1CON0bits
7148 #define DAC1OE2 DAC1CON0bits.DAC1OE2 // bit 4, shadows bit in DAC1CON0bits
7149 #define DACOE0 DAC1CON0bits.DACOE0 // bit 4, shadows bit in DAC1CON0bits
7150 #define DAC1OE1 DAC1CON0bits.DAC1OE1 // bit 5, shadows bit in DAC1CON0bits
7151 #define DACOE1 DAC1CON0bits.DACOE1 // bit 5, shadows bit in DAC1CON0bits
7152 #define DAC1EN DAC1CON0bits.DAC1EN // bit 7, shadows bit in DAC1CON0bits
7153 #define DACEN DAC1CON0bits.DACEN // bit 7, shadows bit in DAC1CON0bits
7155 #define DAC1R0 DAC1CON1bits.DAC1R0 // bit 0, shadows bit in DAC1CON1bits
7156 #define DACR0 DAC1CON1bits.DACR0 // bit 0, shadows bit in DAC1CON1bits
7157 #define DAC1R1 DAC1CON1bits.DAC1R1 // bit 1, shadows bit in DAC1CON1bits
7158 #define DACR1 DAC1CON1bits.DACR1 // bit 1, shadows bit in DAC1CON1bits
7159 #define DAC1R2 DAC1CON1bits.DAC1R2 // bit 2, shadows bit in DAC1CON1bits
7160 #define DACR2 DAC1CON1bits.DACR2 // bit 2, shadows bit in DAC1CON1bits
7161 #define DAC1R3 DAC1CON1bits.DAC1R3 // bit 3, shadows bit in DAC1CON1bits
7162 #define DACR3 DAC1CON1bits.DACR3 // bit 3, shadows bit in DAC1CON1bits
7163 #define DAC1R4 DAC1CON1bits.DAC1R4 // bit 4, shadows bit in DAC1CON1bits
7164 #define DACR4 DAC1CON1bits.DACR4 // bit 4, shadows bit in DAC1CON1bits
7165 #define DAC1R5 DAC1CON1bits.DAC1R5 // bit 5, shadows bit in DAC1CON1bits
7166 #define DACR5 DAC1CON1bits.DACR5 // bit 5, shadows bit in DAC1CON1bits
7167 #define DAC1R6 DAC1CON1bits.DAC1R6 // bit 6, shadows bit in DAC1CON1bits
7168 #define DACR6 DAC1CON1bits.DACR6 // bit 6, shadows bit in DAC1CON1bits
7169 #define DAC1R7 DAC1CON1bits.DAC1R7 // bit 7, shadows bit in DAC1CON1bits
7170 #define DACR7 DAC1CON1bits.DACR7 // bit 7, shadows bit in DAC1CON1bits
7172 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
7173 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
7174 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
7175 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
7176 #define TSRNG FVRCONbits.TSRNG // bit 4
7177 #define TSEN FVRCONbits.TSEN // bit 5
7178 #define FVRRDY FVRCONbits.FVRRDY // bit 6
7179 #define FVREN FVRCONbits.FVREN // bit 7
7181 #define BKA8 ICDBK0Hbits.BKA8 // bit 0
7182 #define BKA9 ICDBK0Hbits.BKA9 // bit 1
7183 #define BKA10 ICDBK0Hbits.BKA10 // bit 2
7184 #define BKA11 ICDBK0Hbits.BKA11 // bit 3
7185 #define BKA12 ICDBK0Hbits.BKA12 // bit 4
7186 #define BKA13 ICDBK0Hbits.BKA13 // bit 5
7187 #define BKA14 ICDBK0Hbits.BKA14 // bit 6
7189 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
7190 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
7191 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
7192 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
7193 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
7194 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
7196 #define INLVLB4 INLVLBbits.INLVLB4 // bit 4
7197 #define INLVLB5 INLVLBbits.INLVLB5 // bit 5
7198 #define INLVLB6 INLVLBbits.INLVLB6 // bit 6
7199 #define INLVLB7 INLVLBbits.INLVLB7 // bit 7
7201 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
7202 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
7203 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
7204 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
7205 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
7206 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
7207 #define INLVLC6 INLVLCbits.INLVLC6 // bit 6
7208 #define INLVLC7 INLVLCbits.INLVLC7 // bit 7
7210 #define IOCIF INTCONbits.IOCIF // bit 0
7211 #define INTF INTCONbits.INTF // bit 1
7212 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
7213 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
7214 #define IOCIE INTCONbits.IOCIE // bit 3
7215 #define INTE INTCONbits.INTE // bit 4
7216 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
7217 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
7218 #define PEIE INTCONbits.PEIE // bit 6
7219 #define GIE INTCONbits.GIE // bit 7
7221 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
7222 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
7223 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
7224 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
7225 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
7226 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
7228 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
7229 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
7230 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
7231 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
7232 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
7233 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
7235 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
7236 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
7237 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
7238 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
7239 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
7240 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
7242 #define IOCBF4 IOCBFbits.IOCBF4 // bit 4
7243 #define IOCBF5 IOCBFbits.IOCBF5 // bit 5
7244 #define IOCBF6 IOCBFbits.IOCBF6 // bit 6
7245 #define IOCBF7 IOCBFbits.IOCBF7 // bit 7
7247 #define IOCBN4 IOCBNbits.IOCBN4 // bit 4
7248 #define IOCBN5 IOCBNbits.IOCBN5 // bit 5
7249 #define IOCBN6 IOCBNbits.IOCBN6 // bit 6
7250 #define IOCBN7 IOCBNbits.IOCBN7 // bit 7
7252 #define IOCBP4 IOCBPbits.IOCBP4 // bit 4
7253 #define IOCBP5 IOCBPbits.IOCBP5 // bit 5
7254 #define IOCBP6 IOCBPbits.IOCBP6 // bit 6
7255 #define IOCBP7 IOCBPbits.IOCBP7 // bit 7
7257 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
7258 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
7259 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
7260 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
7261 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
7262 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
7263 #define IOCCF6 IOCCFbits.IOCCF6 // bit 6
7264 #define IOCCF7 IOCCFbits.IOCCF7 // bit 7
7266 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
7267 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
7268 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
7269 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
7270 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
7271 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
7272 #define IOCCN6 IOCCNbits.IOCCN6 // bit 6
7273 #define IOCCN7 IOCCNbits.IOCCN7 // bit 7
7275 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
7276 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
7277 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
7278 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
7279 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
7280 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
7281 #define IOCCP6 IOCCPbits.IOCCP6 // bit 6
7282 #define IOCCP7 IOCCPbits.IOCCP7 // bit 7
7284 #define LATA0 LATAbits.LATA0 // bit 0
7285 #define LATA1 LATAbits.LATA1 // bit 1
7286 #define LATA2 LATAbits.LATA2 // bit 2
7287 #define LATA4 LATAbits.LATA4 // bit 4
7288 #define LATA5 LATAbits.LATA5 // bit 5
7290 #define LATB4 LATBbits.LATB4 // bit 4
7291 #define LATB5 LATBbits.LATB5 // bit 5
7292 #define LATB6 LATBbits.LATB6 // bit 6
7293 #define LATB7 LATBbits.LATB7 // bit 7
7295 #define LATC0 LATCbits.LATC0 // bit 0
7296 #define LATC1 LATCbits.LATC1 // bit 1
7297 #define LATC2 LATCbits.LATC2 // bit 2
7298 #define LATC3 LATCbits.LATC3 // bit 3
7299 #define LATC4 LATCbits.LATC4 // bit 4
7300 #define LATC5 LATCbits.LATC5 // bit 5
7301 #define LATC6 LATCbits.LATC6 // bit 6
7302 #define LATC7 LATCbits.LATC7 // bit 7
7304 #define ODA0 ODCONAbits.ODA0 // bit 0
7305 #define ODA1 ODCONAbits.ODA1 // bit 1
7306 #define ODA2 ODCONAbits.ODA2 // bit 2
7307 #define ODA4 ODCONAbits.ODA4 // bit 4
7308 #define ODA5 ODCONAbits.ODA5 // bit 5
7310 #define ODB4 ODCONBbits.ODB4 // bit 4
7311 #define ODB5 ODCONBbits.ODB5 // bit 5
7312 #define ODB6 ODCONBbits.ODB6 // bit 6
7313 #define ODB7 ODCONBbits.ODB7 // bit 7
7315 #define ODC0 ODCONCbits.ODC0 // bit 0
7316 #define ODC1 ODCONCbits.ODC1 // bit 1
7317 #define ODC2 ODCONCbits.ODC2 // bit 2
7318 #define ODC3 ODCONCbits.ODC3 // bit 3
7319 #define ODC4 ODCONCbits.ODC4 // bit 4
7320 #define ODC5 ODCONCbits.ODC5 // bit 5
7321 #define ODC6 ODCONCbits.ODC6 // bit 6
7322 #define ODC7 ODCONCbits.ODC7 // bit 7
7324 #define OPA1PCH0 OPA1CONbits.OPA1PCH0 // bit 0
7325 #define OPA1PCH1 OPA1CONbits.OPA1PCH1 // bit 1
7326 #define OPA1UG OPA1CONbits.OPA1UG // bit 4
7327 #define OPA1SP OPA1CONbits.OPA1SP // bit 6
7328 #define OPA1EN OPA1CONbits.OPA1EN // bit 7
7330 #define OPA2PCH0 OPA2CONbits.OPA2PCH0 // bit 0
7331 #define OPA2PCH1 OPA2CONbits.OPA2PCH1 // bit 1
7332 #define OPA2UG OPA2CONbits.OPA2UG // bit 4
7333 #define OPA2SP OPA2CONbits.OPA2SP // bit 6
7334 #define OPA2EN OPA2CONbits.OPA2EN // bit 7
7336 #define PS0 OPTION_REGbits.PS0 // bit 0
7337 #define PS1 OPTION_REGbits.PS1 // bit 1
7338 #define PS2 OPTION_REGbits.PS2 // bit 2
7339 #define PSA OPTION_REGbits.PSA // bit 3
7340 #define TMR0SE OPTION_REGbits.TMR0SE // bit 4, shadows bit in OPTION_REGbits
7341 #define T0SE OPTION_REGbits.T0SE // bit 4, shadows bit in OPTION_REGbits
7342 #define TMR0CS OPTION_REGbits.TMR0CS // bit 5, shadows bit in OPTION_REGbits
7343 #define T0CS OPTION_REGbits.T0CS // bit 5, shadows bit in OPTION_REGbits
7344 #define INTEDG OPTION_REGbits.INTEDG // bit 6
7345 #define NOT_WPUEN OPTION_REGbits.NOT_WPUEN // bit 7
7347 #define SCS0 OSCCONbits.SCS0 // bit 0
7348 #define SCS1 OSCCONbits.SCS1 // bit 1
7349 #define IRCF0 OSCCONbits.IRCF0 // bit 3
7350 #define IRCF1 OSCCONbits.IRCF1 // bit 4
7351 #define IRCF2 OSCCONbits.IRCF2 // bit 5
7352 #define IRCF3 OSCCONbits.IRCF3 // bit 6
7353 #define SPLLEN OSCCONbits.SPLLEN // bit 7
7355 #define HFIOFS OSCSTATbits.HFIOFS // bit 0
7356 #define LFIOFR OSCSTATbits.LFIOFR // bit 1
7357 #define MFIOFR OSCSTATbits.MFIOFR // bit 2
7358 #define HFIOFL OSCSTATbits.HFIOFL // bit 3
7359 #define HFIOFR OSCSTATbits.HFIOFR // bit 4
7360 #define OSTS OSCSTATbits.OSTS // bit 5
7361 #define PLLR OSCSTATbits.PLLR // bit 6
7362 #define SOSCR OSCSTATbits.SOSCR // bit 7
7364 #define TUN0 OSCTUNEbits.TUN0 // bit 0
7365 #define TUN1 OSCTUNEbits.TUN1 // bit 1
7366 #define TUN2 OSCTUNEbits.TUN2 // bit 2
7367 #define TUN3 OSCTUNEbits.TUN3 // bit 3
7368 #define TUN4 OSCTUNEbits.TUN4 // bit 4
7369 #define TUN5 OSCTUNEbits.TUN5 // bit 5
7371 #define NOT_BOR PCONbits.NOT_BOR // bit 0
7372 #define NOT_POR PCONbits.NOT_POR // bit 1
7373 #define NOT_RI PCONbits.NOT_RI // bit 2
7374 #define NOT_RMCLR PCONbits.NOT_RMCLR // bit 3
7375 #define NOT_RWDT PCONbits.NOT_RWDT // bit 4
7376 #define STKUNF PCONbits.STKUNF // bit 6
7377 #define STKOVF PCONbits.STKOVF // bit 7
7379 #define TMR1IE PIE1bits.TMR1IE // bit 0
7380 #define TMR2IE PIE1bits.TMR2IE // bit 1
7381 #define CCP1IE PIE1bits.CCP1IE // bit 2, shadows bit in PIE1bits
7382 #define CCPIE PIE1bits.CCPIE // bit 2, shadows bit in PIE1bits
7383 #define SSP1IE PIE1bits.SSP1IE // bit 3
7384 #define TXIE PIE1bits.TXIE // bit 4
7385 #define RCIE PIE1bits.RCIE // bit 5
7386 #define ADIE PIE1bits.ADIE // bit 6
7387 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
7389 #define CCP2IE PIE2bits.CCP2IE // bit 0
7390 #define TMR4IE PIE2bits.TMR4IE // bit 1
7391 #define TMR6IE PIE2bits.TMR6IE // bit 2
7392 #define BCL1IE PIE2bits.BCL1IE // bit 3
7393 #define C1IE PIE2bits.C1IE // bit 5
7394 #define C2IE PIE2bits.C2IE // bit 6
7395 #define OSFIE PIE2bits.OSFIE // bit 7
7397 #define TMR1IF PIR1bits.TMR1IF // bit 0
7398 #define TMR2IF PIR1bits.TMR2IF // bit 1
7399 #define CCP1IF PIR1bits.CCP1IF // bit 2, shadows bit in PIR1bits
7400 #define CCPIF PIR1bits.CCPIF // bit 2, shadows bit in PIR1bits
7401 #define SSP1IF PIR1bits.SSP1IF // bit 3
7402 #define TXIF PIR1bits.TXIF // bit 4
7403 #define RCIF PIR1bits.RCIF // bit 5
7404 #define ADIF PIR1bits.ADIF // bit 6
7405 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
7407 #define CCP2IF PIR2bits.CCP2IF // bit 0
7408 #define TMR4IF PIR2bits.TMR4IF // bit 1
7409 #define TMR6IF PIR2bits.TMR6IF // bit 2
7410 #define BCL1IF PIR2bits.BCL1IF // bit 3
7411 #define C1IF PIR2bits.C1IF // bit 5
7412 #define C2IF PIR2bits.C2IF // bit 6
7413 #define OSFIF PIR2bits.OSFIF // bit 7
7415 #define CLC1IF PIR3bits.CLC1IF // bit 0
7416 #define CLC2IF PIR3bits.CLC2IF // bit 1
7417 #define CLC3IF PIR3bits.CLC3IF // bit 2
7418 #define ZCDIF PIR3bits.ZCDIF // bit 4
7419 #define COGIF PIR3bits.COGIF // bit 5
7421 #define RD PMCON1bits.RD // bit 0
7422 #define WR PMCON1bits.WR // bit 1
7423 #define WREN PMCON1bits.WREN // bit 2
7424 #define WRERR PMCON1bits.WRERR // bit 3
7425 #define FREE PMCON1bits.FREE // bit 4
7426 #define LWLO PMCON1bits.LWLO // bit 5
7427 #define CFGS PMCON1bits.CFGS // bit 6
7429 #define RA0 PORTAbits.RA0 // bit 0
7430 #define RA1 PORTAbits.RA1 // bit 1
7431 #define RA2 PORTAbits.RA2 // bit 2
7432 #define RA3 PORTAbits.RA3 // bit 3
7433 #define RA4 PORTAbits.RA4 // bit 4
7434 #define RA5 PORTAbits.RA5 // bit 5
7436 #define RB4 PORTBbits.RB4 // bit 4
7437 #define RB5 PORTBbits.RB5 // bit 5
7438 #define RB6 PORTBbits.RB6 // bit 6
7439 #define RB7 PORTBbits.RB7 // bit 7
7441 #define RC0 PORTCbits.RC0 // bit 0
7442 #define RC1 PORTCbits.RC1 // bit 1
7443 #define RC2 PORTCbits.RC2 // bit 2
7444 #define RC3 PORTCbits.RC3 // bit 3
7445 #define RC4 PORTCbits.RC4 // bit 4
7446 #define RC5 PORTCbits.RC5 // bit 5
7447 #define RC6 PORTCbits.RC6 // bit 6
7448 #define RC7 PORTCbits.RC7 // bit 7
7450 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
7452 #define PWM3POL PWM3CONbits.PWM3POL // bit 4
7453 #define PWM3OUT PWM3CONbits.PWM3OUT // bit 5
7454 #define PWM3EN PWM3CONbits.PWM3EN // bit 7
7456 #define PWM3DCH0 PWM3DCHbits.PWM3DCH0 // bit 0
7457 #define PWM3DCH1 PWM3DCHbits.PWM3DCH1 // bit 1
7458 #define PWM3DCH2 PWM3DCHbits.PWM3DCH2 // bit 2
7459 #define PWM3DCH3 PWM3DCHbits.PWM3DCH3 // bit 3
7460 #define PWM3DCH4 PWM3DCHbits.PWM3DCH4 // bit 4
7461 #define PWM3DCH5 PWM3DCHbits.PWM3DCH5 // bit 5
7462 #define PWM3DCH6 PWM3DCHbits.PWM3DCH6 // bit 6
7463 #define PWM3DCH7 PWM3DCHbits.PWM3DCH7 // bit 7
7465 #define PWM3DCL0 PWM3DCLbits.PWM3DCL0 // bit 6
7466 #define PWM3DCL1 PWM3DCLbits.PWM3DCL1 // bit 7
7468 #define PWM4POL PWM4CONbits.PWM4POL // bit 4
7469 #define PWM4OUT PWM4CONbits.PWM4OUT // bit 5
7470 #define PWM4EN PWM4CONbits.PWM4EN // bit 7
7472 #define PWM4DCH0 PWM4DCHbits.PWM4DCH0 // bit 0
7473 #define PWM4DCH1 PWM4DCHbits.PWM4DCH1 // bit 1
7474 #define PWM4DCH2 PWM4DCHbits.PWM4DCH2 // bit 2
7475 #define PWM4DCH3 PWM4DCHbits.PWM4DCH3 // bit 3
7476 #define PWM4DCH4 PWM4DCHbits.PWM4DCH4 // bit 4
7477 #define PWM4DCH5 PWM4DCHbits.PWM4DCH5 // bit 5
7478 #define PWM4DCH6 PWM4DCHbits.PWM4DCH6 // bit 6
7479 #define PWM4DCH7 PWM4DCHbits.PWM4DCH7 // bit 7
7481 #define PWM4DCL0 PWM4DCLbits.PWM4DCL0 // bit 6
7482 #define PWM4DCL1 PWM4DCLbits.PWM4DCL1 // bit 7
7484 #define RX9D RC1STAbits.RX9D // bit 0
7485 #define OERR RC1STAbits.OERR // bit 1
7486 #define FERR RC1STAbits.FERR // bit 2
7487 #define ADDEN RC1STAbits.ADDEN // bit 3
7488 #define CREN RC1STAbits.CREN // bit 4
7489 #define SREN RC1STAbits.SREN // bit 5
7490 #define RX9 RC1STAbits.RX9 // bit 6
7491 #define SPEN RC1STAbits.SPEN // bit 7
7493 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
7494 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
7495 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
7496 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
7497 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
7499 #define SLRB4 SLRCONBbits.SLRB4 // bit 4
7500 #define SLRB5 SLRCONBbits.SLRB5 // bit 5
7501 #define SLRB6 SLRCONBbits.SLRB6 // bit 6
7502 #define SLRB7 SLRCONBbits.SLRB7 // bit 7
7504 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
7505 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
7506 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
7507 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
7508 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
7509 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
7510 #define SLRC6 SLRCONCbits.SLRC6 // bit 6
7511 #define SLRC7 SLRCONCbits.SLRC7 // bit 7
7513 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
7514 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
7515 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
7516 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
7517 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
7518 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
7519 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
7520 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
7521 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
7522 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
7523 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
7524 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
7525 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
7526 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
7527 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
7528 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
7530 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
7531 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
7532 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
7533 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
7534 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
7535 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
7536 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
7537 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
7538 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
7539 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
7540 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
7541 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
7542 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
7543 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
7544 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
7545 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
7547 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
7548 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
7549 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
7550 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
7551 #define CKP SSP1CONbits.CKP // bit 4
7552 #define SSPEN SSP1CONbits.SSPEN // bit 5
7553 #define SSPOV SSP1CONbits.SSPOV // bit 6
7554 #define WCOL SSP1CONbits.WCOL // bit 7
7556 #define SEN SSP1CON2bits.SEN // bit 0
7557 #define RSEN SSP1CON2bits.RSEN // bit 1
7558 #define PEN SSP1CON2bits.PEN // bit 2
7559 #define RCEN SSP1CON2bits.RCEN // bit 3
7560 #define ACKEN SSP1CON2bits.ACKEN // bit 4
7561 #define ACKDT SSP1CON2bits.ACKDT // bit 5
7562 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
7563 #define GCEN SSP1CON2bits.GCEN // bit 7
7565 #define DHEN SSP1CON3bits.DHEN // bit 0
7566 #define AHEN SSP1CON3bits.AHEN // bit 1
7567 #define SBCDE SSP1CON3bits.SBCDE // bit 2
7568 #define SDAHT SSP1CON3bits.SDAHT // bit 3
7569 #define BOEN SSP1CON3bits.BOEN // bit 4
7570 #define SCIE SSP1CON3bits.SCIE // bit 5
7571 #define PCIE SSP1CON3bits.PCIE // bit 6
7572 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
7574 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
7575 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
7576 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
7577 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
7578 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
7579 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
7580 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
7581 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
7582 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
7583 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
7584 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
7585 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
7586 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
7587 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
7588 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
7589 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
7591 #define BF SSP1STATbits.BF // bit 0
7592 #define UA SSP1STATbits.UA // bit 1
7593 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
7594 #define S SSP1STATbits.S // bit 3
7595 #define P SSP1STATbits.P // bit 4
7596 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
7597 #define CKE SSP1STATbits.CKE // bit 6
7598 #define SMP SSP1STATbits.SMP // bit 7
7600 #define C STATUSbits.C // bit 0
7601 #define DC STATUSbits.DC // bit 1
7602 #define Z STATUSbits.Z // bit 2
7603 #define NOT_PD STATUSbits.NOT_PD // bit 3
7604 #define NOT_TO STATUSbits.NOT_TO // bit 4
7606 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
7607 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
7608 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
7610 #define TMR1ON T1CONbits.TMR1ON // bit 0
7611 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
7612 #define T1OSCEN T1CONbits.T1OSCEN // bit 3
7613 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
7614 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
7615 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
7616 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
7618 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
7619 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
7620 #define T1GVAL T1GCONbits.T1GVAL // bit 2
7621 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3
7622 #define T1GSPM T1GCONbits.T1GSPM // bit 4
7623 #define T1GTM T1GCONbits.T1GTM // bit 5
7624 #define T1GPOL T1GCONbits.T1GPOL // bit 6
7625 #define TMR1GE T1GCONbits.TMR1GE // bit 7
7627 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
7628 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
7629 #define TMR2ON T2CONbits.TMR2ON // bit 2
7630 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
7631 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
7632 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
7633 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
7635 #define T4CKPS0 T4CONbits.T4CKPS0 // bit 0
7636 #define T4CKPS1 T4CONbits.T4CKPS1 // bit 1
7637 #define TMR4ON T4CONbits.TMR4ON // bit 2
7638 #define T4OUTPS0 T4CONbits.T4OUTPS0 // bit 3
7639 #define T4OUTPS1 T4CONbits.T4OUTPS1 // bit 4
7640 #define T4OUTPS2 T4CONbits.T4OUTPS2 // bit 5
7641 #define T4OUTPS3 T4CONbits.T4OUTPS3 // bit 6
7643 #define T6CKPS0 T6CONbits.T6CKPS0 // bit 0
7644 #define T6CKPS1 T6CONbits.T6CKPS1 // bit 1
7645 #define TMR6ON T6CONbits.TMR6ON // bit 2
7646 #define T6OUTPS0 T6CONbits.T6OUTPS0 // bit 3
7647 #define T6OUTPS1 T6CONbits.T6OUTPS1 // bit 4
7648 #define T6OUTPS2 T6CONbits.T6OUTPS2 // bit 5
7649 #define T6OUTPS3 T6CONbits.T6OUTPS3 // bit 6
7651 #define TRISA0 TRISAbits.TRISA0 // bit 0
7652 #define TRISA1 TRISAbits.TRISA1 // bit 1
7653 #define TRISA2 TRISAbits.TRISA2 // bit 2
7654 #define TRISA4 TRISAbits.TRISA4 // bit 4
7655 #define TRISA5 TRISAbits.TRISA5 // bit 5
7657 #define TRISB4 TRISBbits.TRISB4 // bit 4
7658 #define TRISB5 TRISBbits.TRISB5 // bit 5
7659 #define TRISB6 TRISBbits.TRISB6 // bit 6
7660 #define TRISB7 TRISBbits.TRISB7 // bit 7
7662 #define TRISC0 TRISCbits.TRISC0 // bit 0
7663 #define TRISC1 TRISCbits.TRISC1 // bit 1
7664 #define TRISC2 TRISCbits.TRISC2 // bit 2
7665 #define TRISC3 TRISCbits.TRISC3 // bit 3
7666 #define TRISC4 TRISCbits.TRISC4 // bit 4
7667 #define TRISC5 TRISCbits.TRISC5 // bit 5
7668 #define TRISC6 TRISCbits.TRISC6 // bit 6
7669 #define TRISC7 TRISCbits.TRISC7 // bit 7
7671 #define TX9D TX1STAbits.TX9D // bit 0
7672 #define TRMT TX1STAbits.TRMT // bit 1
7673 #define BRGH TX1STAbits.BRGH // bit 2
7674 #define SENDB TX1STAbits.SENDB // bit 3
7675 #define SYNC TX1STAbits.SYNC // bit 4
7676 #define TXEN TX1STAbits.TXEN // bit 5
7677 #define TX9 TX1STAbits.TX9 // bit 6
7678 #define CSRC TX1STAbits.CSRC // bit 7
7680 #define SWDTEN WDTCONbits.SWDTEN // bit 0
7681 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
7682 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
7683 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
7684 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
7685 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
7687 #define WPUA0 WPUAbits.WPUA0 // bit 0
7688 #define WPUA1 WPUAbits.WPUA1 // bit 1
7689 #define WPUA2 WPUAbits.WPUA2 // bit 2
7690 #define WPUA3 WPUAbits.WPUA3 // bit 3
7691 #define WPUA4 WPUAbits.WPUA4 // bit 4
7692 #define WPUA5 WPUAbits.WPUA5 // bit 5
7694 #define WPUB4 WPUBbits.WPUB4 // bit 4
7695 #define WPUB5 WPUBbits.WPUB5 // bit 5
7696 #define WPUB6 WPUBbits.WPUB6 // bit 6
7697 #define WPUB7 WPUBbits.WPUB7 // bit 7
7699 #define WPUC0 WPUCbits.WPUC0 // bit 0
7700 #define WPUC1 WPUCbits.WPUC1 // bit 1
7701 #define WPUC2 WPUCbits.WPUC2 // bit 2
7702 #define WPUC3 WPUCbits.WPUC3 // bit 3
7703 #define WPUC4 WPUCbits.WPUC4 // bit 4
7704 #define WPUC5 WPUCbits.WPUC5 // bit 5
7705 #define WPUC6 WPUCbits.WPUC6 // bit 6
7706 #define WPUC7 WPUCbits.WPUC7 // bit 7
7708 #define ZCD1INTN ZCD1CONbits.ZCD1INTN // bit 0
7709 #define ZCD1INTP ZCD1CONbits.ZCD1INTP // bit 1
7710 #define ZCD1POL ZCD1CONbits.ZCD1POL // bit 4
7711 #define ZCD1OUT ZCD1CONbits.ZCD1OUT // bit 5
7712 #define ZCD1EN ZCD1CONbits.ZCD1EN // bit 7
7714 #endif // #ifndef NO_BIT_DEFINES
7716 #endif // #ifndef __PIC16LF1709_H__