2 * This declarations of the PIC16LF1765 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:14 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16LF1765_H__
26 #define __PIC16LF1765_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTC_ADDR 0x000E
52 #define PIR1_ADDR 0x0011
53 #define PIR2_ADDR 0x0012
54 #define PIR3_ADDR 0x0013
55 #define PIR4_ADDR 0x0014
56 #define TMR0_ADDR 0x0015
57 #define TMR1_ADDR 0x0016
58 #define TMR1L_ADDR 0x0016
59 #define TMR1H_ADDR 0x0017
60 #define T1CON_ADDR 0x0018
61 #define T1GCON_ADDR 0x0019
62 #define T2TMR_ADDR 0x001A
63 #define TMR2_ADDR 0x001A
64 #define PR2_ADDR 0x001B
65 #define T2PR_ADDR 0x001B
66 #define T2CON_ADDR 0x001C
67 #define T2HLT_ADDR 0x001D
68 #define T2CLKCON_ADDR 0x001E
69 #define T2RST_ADDR 0x001F
70 #define TRISA_ADDR 0x008C
71 #define TRISC_ADDR 0x008E
72 #define PIE1_ADDR 0x0091
73 #define PIE2_ADDR 0x0092
74 #define PIE3_ADDR 0x0093
75 #define PIE4_ADDR 0x0094
76 #define OPTION_REG_ADDR 0x0095
77 #define PCON_ADDR 0x0096
78 #define WDTCON_ADDR 0x0097
79 #define OSCTUNE_ADDR 0x0098
80 #define OSCCON_ADDR 0x0099
81 #define OSCSTAT_ADDR 0x009A
82 #define ADRES_ADDR 0x009B
83 #define ADRESL_ADDR 0x009B
84 #define ADRESH_ADDR 0x009C
85 #define ADCON0_ADDR 0x009D
86 #define ADCON1_ADDR 0x009E
87 #define ADCON2_ADDR 0x009F
88 #define LATA_ADDR 0x010C
89 #define LATC_ADDR 0x010E
90 #define CMOUT_ADDR 0x010F
91 #define CM1CON0_ADDR 0x0110
92 #define CM1CON1_ADDR 0x0111
93 #define CM1NSEL_ADDR 0x0112
94 #define CM1PSEL_ADDR 0x0113
95 #define CM2CON0_ADDR 0x0114
96 #define CM2CON1_ADDR 0x0115
97 #define CM2NSEL_ADDR 0x0116
98 #define CM2PSEL_ADDR 0x0117
99 #define ANSELA_ADDR 0x018C
100 #define ANSELC_ADDR 0x018E
101 #define PMADR_ADDR 0x0191
102 #define PMADRL_ADDR 0x0191
103 #define PMADRH_ADDR 0x0192
104 #define PMDAT_ADDR 0x0193
105 #define PMDATL_ADDR 0x0193
106 #define PMDATH_ADDR 0x0194
107 #define PMCON1_ADDR 0x0195
108 #define PMCON2_ADDR 0x0196
109 #define RC1REG_ADDR 0x0199
110 #define RCREG_ADDR 0x0199
111 #define RCREG1_ADDR 0x0199
112 #define TX1REG_ADDR 0x019A
113 #define TXREG_ADDR 0x019A
114 #define TXREG1_ADDR 0x019A
115 #define SP1BRG_ADDR 0x019B
116 #define SP1BRGL_ADDR 0x019B
117 #define SPBRG_ADDR 0x019B
118 #define SPBRG1_ADDR 0x019B
119 #define SPBRGL_ADDR 0x019B
120 #define SP1BRGH_ADDR 0x019C
121 #define SPBRGH_ADDR 0x019C
122 #define SPBRGH1_ADDR 0x019C
123 #define RC1STA_ADDR 0x019D
124 #define RCSTA_ADDR 0x019D
125 #define RCSTA1_ADDR 0x019D
126 #define TX1STA_ADDR 0x019E
127 #define TXSTA_ADDR 0x019E
128 #define TXSTA1_ADDR 0x019E
129 #define BAUD1CON_ADDR 0x019F
130 #define BAUDCON_ADDR 0x019F
131 #define BAUDCON1_ADDR 0x019F
132 #define BAUDCTL_ADDR 0x019F
133 #define BAUDCTL1_ADDR 0x019F
134 #define WPUA_ADDR 0x020C
135 #define WPUC_ADDR 0x020E
136 #define SSP1BUF_ADDR 0x0211
137 #define SSPBUF_ADDR 0x0211
138 #define SSP1ADD_ADDR 0x0212
139 #define SSPADD_ADDR 0x0212
140 #define SSP1MSK_ADDR 0x0213
141 #define SSPMSK_ADDR 0x0213
142 #define SSP1STAT_ADDR 0x0214
143 #define SSPSTAT_ADDR 0x0214
144 #define SSP1CON_ADDR 0x0215
145 #define SSP1CON1_ADDR 0x0215
146 #define SSPCON_ADDR 0x0215
147 #define SSPCON1_ADDR 0x0215
148 #define SSP1CON2_ADDR 0x0216
149 #define SSPCON2_ADDR 0x0216
150 #define SSP1CON3_ADDR 0x0217
151 #define SSPCON3_ADDR 0x0217
152 #define BORCON_ADDR 0x021D
153 #define FVRCON_ADDR 0x021E
154 #define ZCD1CON_ADDR 0x021F
155 #define ODCONA_ADDR 0x028C
156 #define ODCONC_ADDR 0x028E
157 #define CCPR1_ADDR 0x0291
158 #define CCPR1L_ADDR 0x0291
159 #define CCPR1H_ADDR 0x0292
160 #define CCP1CON_ADDR 0x0293
161 #define CCP1CAP_ADDR 0x0294
162 #define CCPTMRS_ADDR 0x029E
163 #define SLRCONA_ADDR 0x030C
164 #define SLRCONC_ADDR 0x030E
165 #define INLVLA_ADDR 0x038C
166 #define INLVLC_ADDR 0x038E
167 #define IOCAP_ADDR 0x0391
168 #define IOCAN_ADDR 0x0392
169 #define IOCAF_ADDR 0x0393
170 #define IOCCP_ADDR 0x0397
171 #define IOCCN_ADDR 0x0398
172 #define IOCCF_ADDR 0x0399
173 #define MD1CON0_ADDR 0x039B
174 #define MD1CON1_ADDR 0x039C
175 #define MD1SRC_ADDR 0x039D
176 #define MD1CARL_ADDR 0x039E
177 #define MD1CARH_ADDR 0x039F
178 #define HIDRVC_ADDR 0x040E
179 #define T4TMR_ADDR 0x0413
180 #define TMR4_ADDR 0x0413
181 #define PR4_ADDR 0x0414
182 #define T4PR_ADDR 0x0414
183 #define T4CON_ADDR 0x0415
184 #define T4HLT_ADDR 0x0416
185 #define T4CLKCON_ADDR 0x0417
186 #define T4RST_ADDR 0x0418
187 #define T6TMR_ADDR 0x041A
188 #define TMR6_ADDR 0x041A
189 #define PR6_ADDR 0x041B
190 #define T6PR_ADDR 0x041B
191 #define T6CON_ADDR 0x041C
192 #define T6HLT_ADDR 0x041D
193 #define T6CLKCON_ADDR 0x041E
194 #define T6RST_ADDR 0x041F
195 #define TMR3_ADDR 0x0493
196 #define TMR3L_ADDR 0x0493
197 #define TMR3H_ADDR 0x0494
198 #define T3CON_ADDR 0x0495
199 #define T3GCON_ADDR 0x0496
200 #define TMR5_ADDR 0x049A
201 #define TMR5L_ADDR 0x049A
202 #define TMR5H_ADDR 0x049B
203 #define T5CON_ADDR 0x049C
204 #define T5GCON_ADDR 0x049D
205 #define OPA1NCHS_ADDR 0x050F
206 #define OPA1PCHS_ADDR 0x0510
207 #define OPA1CON_ADDR 0x0511
208 #define OPA1ORS_ADDR 0x0512
209 #define DACLD_ADDR 0x0590
210 #define DAC1CON0_ADDR 0x0591
211 #define DAC1CON1_ADDR 0x0592
212 #define DAC1REF_ADDR 0x0592
213 #define DAC1REFL_ADDR 0x0592
214 #define DAC1CON2_ADDR 0x0593
215 #define DAC1REFH_ADDR 0x0593
216 #define DAC3CON0_ADDR 0x0597
217 #define DAC3CON1_ADDR 0x0598
218 #define DAC3REF_ADDR 0x0598
219 #define PWM3DCL_ADDR 0x0617
220 #define PWM3DCH_ADDR 0x0618
221 #define PWM3CON_ADDR 0x0619
222 #define COG1PHR_ADDR 0x068D
223 #define COG1PHF_ADDR 0x068E
224 #define COG1BLKR_ADDR 0x068F
225 #define COG1BLKF_ADDR 0x0690
226 #define COG1DBR_ADDR 0x0691
227 #define COG1DBF_ADDR 0x0692
228 #define COG1CON0_ADDR 0x0693
229 #define COG1CON1_ADDR 0x0694
230 #define COG1RIS0_ADDR 0x0695
231 #define COG1RIS1_ADDR 0x0696
232 #define COG1RSIM0_ADDR 0x0697
233 #define COG1RSIM1_ADDR 0x0698
234 #define COG1FIS0_ADDR 0x0699
235 #define COG1FIS1_ADDR 0x069A
236 #define COG1FSIM0_ADDR 0x069B
237 #define COG1FSIM1_ADDR 0x069C
238 #define COG1ASD0_ADDR 0x069D
239 #define COG1ASD1_ADDR 0x069E
240 #define COG1STR_ADDR 0x069F
241 #define PRG1RTSS_ADDR 0x0794
242 #define PRG1FTSS_ADDR 0x0795
243 #define PRG1INS_ADDR 0x0796
244 #define PRG1CON0_ADDR 0x0797
245 #define PRG1CON1_ADDR 0x0798
246 #define PRG1CON2_ADDR 0x0799
247 #define PWMEN_ADDR 0x0D8E
248 #define PWMLD_ADDR 0x0D8F
249 #define PWMOUT_ADDR 0x0D90
250 #define PWM5PH_ADDR 0x0D91
251 #define PWM5PHL_ADDR 0x0D91
252 #define PWM5PHH_ADDR 0x0D92
253 #define PWM5DC_ADDR 0x0D93
254 #define PWM5DCL_ADDR 0x0D93
255 #define PWM5DCH_ADDR 0x0D94
256 #define PWM5PR_ADDR 0x0D95
257 #define PWM5PRL_ADDR 0x0D95
258 #define PWM5PRH_ADDR 0x0D96
259 #define PWM5OF_ADDR 0x0D97
260 #define PWM5OFL_ADDR 0x0D97
261 #define PWM5OFH_ADDR 0x0D98
262 #define PWM5TMR_ADDR 0x0D99
263 #define PWM5TMRL_ADDR 0x0D99
264 #define PWM5TMRH_ADDR 0x0D9A
265 #define PWM5CON_ADDR 0x0D9B
266 #define PWM5INTCON_ADDR 0x0D9C
267 #define PWM5INTE_ADDR 0x0D9C
268 #define PWM5INTF_ADDR 0x0D9D
269 #define PWM5INTFLG_ADDR 0x0D9D
270 #define PWM5CLKCON_ADDR 0x0D9E
271 #define PWM5LDCON_ADDR 0x0D9F
272 #define PWM5OFCON_ADDR 0x0DA0
273 #define PPSLOCK_ADDR 0x0E0F
274 #define INTPPS_ADDR 0x0E10
275 #define T0CKIPPS_ADDR 0x0E11
276 #define T1CKIPPS_ADDR 0x0E12
277 #define T1GPPS_ADDR 0x0E13
278 #define CCP1PPS_ADDR 0x0E14
279 #define COG1INPPS_ADDR 0x0E16
280 #define T2CKIPPS_ADDR 0x0E19
281 #define T3CKIPPS_ADDR 0x0E1A
282 #define T3GPPS_ADDR 0x0E1B
283 #define T4CKIPPS_ADDR 0x0E1C
284 #define T5CKIPPS_ADDR 0x0E1D
285 #define T5GPPS_ADDR 0x0E1E
286 #define T6CKIPPS_ADDR 0x0E1F
287 #define SSPCLKPPS_ADDR 0x0E20
288 #define SSPDATPPS_ADDR 0x0E21
289 #define SSPSSPPS_ADDR 0x0E22
290 #define RXPPS_ADDR 0x0E24
291 #define CKPPS_ADDR 0x0E25
292 #define CLCIN0PPS_ADDR 0x0E28
293 #define CLCIN1PPS_ADDR 0x0E29
294 #define CLCIN2PPS_ADDR 0x0E2A
295 #define CLCIN3PPS_ADDR 0x0E2B
296 #define PRG1RPPS_ADDR 0x0E2C
297 #define PRG1FPPS_ADDR 0x0E2D
298 #define MD1CHPPS_ADDR 0x0E30
299 #define MD1CLPPS_ADDR 0x0E31
300 #define MD1MODPPS_ADDR 0x0E32
301 #define RA0PPS_ADDR 0x0E90
302 #define RA1PPS_ADDR 0x0E91
303 #define RA2PPS_ADDR 0x0E92
304 #define RA4PPS_ADDR 0x0E94
305 #define RA5PPS_ADDR 0x0E95
306 #define RC0PPS_ADDR 0x0EA0
307 #define RC1PPS_ADDR 0x0EA1
308 #define RC2PPS_ADDR 0x0EA2
309 #define RC3PPS_ADDR 0x0EA3
310 #define RC4PPS_ADDR 0x0EA4
311 #define RC5PPS_ADDR 0x0EA5
312 #define CLCDATA_ADDR 0x0F0F
313 #define CLC1CON_ADDR 0x0F10
314 #define CLC1POL_ADDR 0x0F11
315 #define CLC1SEL0_ADDR 0x0F12
316 #define CLC1SEL1_ADDR 0x0F13
317 #define CLC1SEL2_ADDR 0x0F14
318 #define CLC1SEL3_ADDR 0x0F15
319 #define CLC1GLS0_ADDR 0x0F16
320 #define CLC1GLS1_ADDR 0x0F17
321 #define CLC1GLS2_ADDR 0x0F18
322 #define CLC1GLS3_ADDR 0x0F19
323 #define CLC2CON_ADDR 0x0F1A
324 #define CLC2POL_ADDR 0x0F1B
325 #define CLC2SEL0_ADDR 0x0F1C
326 #define CLC2SEL1_ADDR 0x0F1D
327 #define CLC2SEL2_ADDR 0x0F1E
328 #define CLC2SEL3_ADDR 0x0F1F
329 #define CLC2GLS0_ADDR 0x0F20
330 #define CLC2GLS1_ADDR 0x0F21
331 #define CLC2GLS2_ADDR 0x0F22
332 #define CLC2GLS3_ADDR 0x0F23
333 #define CLC3CON_ADDR 0x0F24
334 #define CLC3POL_ADDR 0x0F25
335 #define CLC3SEL0_ADDR 0x0F26
336 #define CLC3SEL1_ADDR 0x0F27
337 #define CLC3SEL2_ADDR 0x0F28
338 #define CLC3SEL3_ADDR 0x0F29
339 #define CLC3GLS0_ADDR 0x0F2A
340 #define CLC3GLS1_ADDR 0x0F2B
341 #define CLC3GLS2_ADDR 0x0F2C
342 #define CLC3GLS3_ADDR 0x0F2D
343 #define STATUS_SHAD_ADDR 0x0FE4
344 #define WREG_SHAD_ADDR 0x0FE5
345 #define BSR_SHAD_ADDR 0x0FE6
346 #define PCLATH_SHAD_ADDR 0x0FE7
347 #define FSR0L_SHAD_ADDR 0x0FE8
348 #define FSR0H_SHAD_ADDR 0x0FE9
349 #define FSR1L_SHAD_ADDR 0x0FEA
350 #define FSR1H_SHAD_ADDR 0x0FEB
351 #define STKPTR_ADDR 0x0FED
352 #define TOSL_ADDR 0x0FEE
353 #define TOSH_ADDR 0x0FEF
355 #endif // #ifndef NO_ADDR_DEFINES
357 //==============================================================================
359 // Register Definitions
361 //==============================================================================
363 extern __at(0x0000) __sfr INDF0
;
364 extern __at(0x0001) __sfr INDF1
;
365 extern __at(0x0002) __sfr PCL
;
367 //==============================================================================
370 extern __at(0x0003) __sfr STATUS
;
384 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
392 //==============================================================================
394 extern __at(0x0004) __sfr FSR0
;
395 extern __at(0x0004) __sfr FSR0L
;
396 extern __at(0x0005) __sfr FSR0H
;
397 extern __at(0x0006) __sfr FSR1
;
398 extern __at(0x0006) __sfr FSR1L
;
399 extern __at(0x0007) __sfr FSR1H
;
401 //==============================================================================
404 extern __at(0x0008) __sfr BSR
;
427 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
435 //==============================================================================
437 extern __at(0x0009) __sfr WREG
;
438 extern __at(0x000A) __sfr PCLATH
;
440 //==============================================================================
443 extern __at(0x000B) __sfr INTCON
;
472 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
485 //==============================================================================
488 //==============================================================================
491 extern __at(0x000C) __sfr PORTA
;
514 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
523 //==============================================================================
526 //==============================================================================
529 extern __at(0x000E) __sfr PORTC
;
552 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
561 //==============================================================================
564 //==============================================================================
567 extern __at(0x0011) __sfr PIR1
;
580 unsigned TMR1GIF
: 1;
596 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
606 #define _TMR1GIF 0x80
608 //==============================================================================
611 //==============================================================================
614 extern __at(0x0012) __sfr PIR2
;
628 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
635 //==============================================================================
638 //==============================================================================
641 extern __at(0x0013) __sfr PIR3
;
655 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
664 //==============================================================================
667 //==============================================================================
670 extern __at(0x0014) __sfr PIR4
;
677 unsigned TMR3GIF
: 1;
679 unsigned TMR5GIF
: 1;
684 extern __at(0x0014) volatile __PIR4bits_t PIR4bits
;
689 #define _TMR3GIF 0x08
691 #define _TMR5GIF 0x20
693 //==============================================================================
695 extern __at(0x0015) __sfr TMR0
;
696 extern __at(0x0016) __sfr TMR1
;
697 extern __at(0x0016) __sfr TMR1L
;
698 extern __at(0x0017) __sfr TMR1H
;
700 //==============================================================================
703 extern __at(0x0018) __sfr T1CON
;
711 unsigned NOT_SYNC
: 1;
725 unsigned T1CKPS0
: 1;
726 unsigned T1CKPS1
: 1;
735 unsigned NOT_T1SYNC
: 1;
736 unsigned T1OSCEN
: 1;
739 unsigned TMR1CS0
: 1;
740 unsigned TMR1CS1
: 1;
788 extern __at(0x0018) volatile __T1CONbits_t T1CONbits
;
790 #define _T1CON_ON 0x01
791 #define _T1CON_TMRON 0x01
792 #define _T1CON_TMR1ON 0x01
793 #define _T1CON_T1ON 0x01
794 #define _T1CON_NOT_SYNC 0x04
795 #define _T1CON_SYNC 0x04
796 #define _T1CON_NOT_T1SYNC 0x04
797 #define _T1CON_OSCEN 0x08
798 #define _T1CON_SOSCEN 0x08
799 #define _T1CON_T1OSCEN 0x08
800 #define _T1CON_CKPS0 0x10
801 #define _T1CON_T1CKPS0 0x10
802 #define _T1CON_CKPS1 0x20
803 #define _T1CON_T1CKPS1 0x20
804 #define _T1CON_CS0 0x40
805 #define _T1CON_T1CS0 0x40
806 #define _T1CON_TMR1CS0 0x40
807 #define _T1CON_CS1 0x80
808 #define _T1CON_T1CS1 0x80
809 #define _T1CON_TMR1CS1 0x80
811 //==============================================================================
814 //==============================================================================
817 extern __at(0x0019) __sfr T1GCON
;
826 unsigned GGO_NOT_DONE
: 1;
838 unsigned T1GGO_NOT_DONE
: 1;
870 extern __at(0x0019) volatile __T1GCONbits_t T1GCONbits
;
878 #define _GGO_NOT_DONE 0x08
879 #define _T1GGO_NOT_DONE 0x08
890 //==============================================================================
892 extern __at(0x001A) __sfr T2TMR
;
893 extern __at(0x001A) __sfr TMR2
;
894 extern __at(0x001B) __sfr PR2
;
895 extern __at(0x001B) __sfr T2PR
;
897 //==============================================================================
900 extern __at(0x001C) __sfr T2CON
;
918 unsigned T2OUTPS0
: 1;
919 unsigned T2OUTPS1
: 1;
920 unsigned T2OUTPS2
: 1;
921 unsigned T2OUTPS3
: 1;
922 unsigned T2CKPS0
: 1;
923 unsigned T2CKPS1
: 1;
924 unsigned T2CKPS2
: 1;
942 unsigned T2OUTPS
: 4;
967 extern __at(0x001C) volatile __T2CONbits_t T2CONbits
;
969 #define _T2CON_OUTPS0 0x01
970 #define _T2CON_T2OUTPS0 0x01
971 #define _T2CON_OUTPS1 0x02
972 #define _T2CON_T2OUTPS1 0x02
973 #define _T2CON_OUTPS2 0x04
974 #define _T2CON_T2OUTPS2 0x04
975 #define _T2CON_OUTPS3 0x08
976 #define _T2CON_T2OUTPS3 0x08
977 #define _T2CON_CKPS0 0x10
978 #define _T2CON_T2CKPS0 0x10
979 #define _T2CON_CKPS1 0x20
980 #define _T2CON_T2CKPS1 0x20
981 #define _T2CON_CKPS2 0x40
982 #define _T2CON_T2CKPS2 0x40
983 #define _T2CON_ON 0x80
984 #define _T2CON_T2ON 0x80
985 #define _T2CON_TMR2ON 0x80
987 //==============================================================================
990 //==============================================================================
993 extern __at(0x001D) __sfr T2HLT
;
1004 unsigned CKSYNC
: 1;
1011 unsigned T2MODE0
: 1;
1012 unsigned T2MODE1
: 1;
1013 unsigned T2MODE2
: 1;
1014 unsigned T2MODE3
: 1;
1015 unsigned T2MODE4
: 1;
1016 unsigned T2CKSYNC
: 1;
1017 unsigned T2CKPOL
: 1;
1018 unsigned T2PSYNC
: 1;
1029 unsigned T2MODE
: 5;
1034 extern __at(0x001D) volatile __T2HLTbits_t T2HLTbits
;
1036 #define _T2HLT_MODE0 0x01
1037 #define _T2HLT_T2MODE0 0x01
1038 #define _T2HLT_MODE1 0x02
1039 #define _T2HLT_T2MODE1 0x02
1040 #define _T2HLT_MODE2 0x04
1041 #define _T2HLT_T2MODE2 0x04
1042 #define _T2HLT_MODE3 0x08
1043 #define _T2HLT_T2MODE3 0x08
1044 #define _T2HLT_MODE4 0x10
1045 #define _T2HLT_T2MODE4 0x10
1046 #define _T2HLT_CKSYNC 0x20
1047 #define _T2HLT_T2CKSYNC 0x20
1048 #define _T2HLT_CKPOL 0x40
1049 #define _T2HLT_T2CKPOL 0x40
1050 #define _T2HLT_PSYNC 0x80
1051 #define _T2HLT_T2PSYNC 0x80
1053 //==============================================================================
1056 //==============================================================================
1059 extern __at(0x001E) __sfr T2CLKCON
;
1100 extern __at(0x001E) volatile __T2CLKCONbits_t T2CLKCONbits
;
1102 #define _T2CLKCON_CS0 0x01
1103 #define _T2CLKCON_T2CS0 0x01
1104 #define _T2CLKCON_CS1 0x02
1105 #define _T2CLKCON_T2CS1 0x02
1106 #define _T2CLKCON_CS2 0x04
1107 #define _T2CLKCON_T2CS2 0x04
1108 #define _T2CLKCON_CS3 0x08
1109 #define _T2CLKCON_T2CS3 0x08
1111 //==============================================================================
1114 //==============================================================================
1117 extern __at(0x001F) __sfr T2RST
;
1135 unsigned T2RSEL0
: 1;
1136 unsigned T2RSEL1
: 1;
1137 unsigned T2RSEL2
: 1;
1138 unsigned T2RSEL3
: 1;
1147 unsigned T2RSEL
: 4;
1158 extern __at(0x001F) volatile __T2RSTbits_t T2RSTbits
;
1161 #define _T2RSEL0 0x01
1163 #define _T2RSEL1 0x02
1165 #define _T2RSEL2 0x04
1167 #define _T2RSEL3 0x08
1169 //==============================================================================
1172 //==============================================================================
1175 extern __at(0x008C) __sfr TRISA
;
1179 unsigned TRISA0
: 1;
1180 unsigned TRISA1
: 1;
1181 unsigned TRISA2
: 1;
1183 unsigned TRISA4
: 1;
1184 unsigned TRISA5
: 1;
1189 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
1191 #define _TRISA0 0x01
1192 #define _TRISA1 0x02
1193 #define _TRISA2 0x04
1194 #define _TRISA4 0x10
1195 #define _TRISA5 0x20
1197 //==============================================================================
1200 //==============================================================================
1203 extern __at(0x008E) __sfr TRISC
;
1209 unsigned TRISC0
: 1;
1210 unsigned TRISC1
: 1;
1211 unsigned TRISC2
: 1;
1212 unsigned TRISC3
: 1;
1213 unsigned TRISC4
: 1;
1214 unsigned TRISC5
: 1;
1226 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
1228 #define _TRISC0 0x01
1229 #define _TRISC1 0x02
1230 #define _TRISC2 0x04
1231 #define _TRISC3 0x08
1232 #define _TRISC4 0x10
1233 #define _TRISC5 0x20
1235 //==============================================================================
1238 //==============================================================================
1241 extern __at(0x0091) __sfr PIE1
;
1247 unsigned TMR1IE
: 1;
1248 unsigned TMR2IE
: 1;
1249 unsigned CCP1IE
: 1;
1250 unsigned SSP1IE
: 1;
1254 unsigned TMR1GIE
: 1;
1270 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
1272 #define _TMR1IE 0x01
1273 #define _TMR2IE 0x02
1274 #define _CCP1IE 0x04
1276 #define _SSP1IE 0x08
1280 #define _TMR1GIE 0x80
1282 //==============================================================================
1285 //==============================================================================
1288 extern __at(0x0092) __sfr PIE2
;
1295 unsigned BCL1IE
: 1;
1302 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
1304 #define _BCL1IE 0x08
1309 //==============================================================================
1312 //==============================================================================
1315 extern __at(0x0093) __sfr PIE3
;
1319 unsigned CLC1IE
: 1;
1320 unsigned CLC2IE
: 1;
1321 unsigned CLC3IE
: 1;
1325 unsigned PWM5IE
: 1;
1329 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
1331 #define _CLC1IE 0x01
1332 #define _CLC2IE 0x02
1333 #define _CLC3IE 0x04
1336 #define _PWM5IE 0x40
1338 //==============================================================================
1341 //==============================================================================
1344 extern __at(0x0094) __sfr PIE4
;
1348 unsigned TMR4IE
: 1;
1349 unsigned TMR6IE
: 1;
1350 unsigned TMR3IE
: 1;
1351 unsigned TMR3GIE
: 1;
1352 unsigned TMR5IE
: 1;
1353 unsigned TMR5GIE
: 1;
1358 extern __at(0x0094) volatile __PIE4bits_t PIE4bits
;
1360 #define _TMR4IE 0x01
1361 #define _TMR6IE 0x02
1362 #define _TMR3IE 0x04
1363 #define _TMR3GIE 0x08
1364 #define _TMR5IE 0x10
1365 #define _TMR5GIE 0x20
1367 //==============================================================================
1370 //==============================================================================
1373 extern __at(0x0095) __sfr OPTION_REG
;
1383 unsigned TMR0SE
: 1;
1384 unsigned TMR0CS
: 1;
1385 unsigned INTEDG
: 1;
1386 unsigned NOT_WPUEN
: 1;
1406 } __OPTION_REGbits_t
;
1408 extern __at(0x0095) volatile __OPTION_REGbits_t OPTION_REGbits
;
1414 #define _TMR0SE 0x10
1416 #define _TMR0CS 0x20
1418 #define _INTEDG 0x40
1419 #define _NOT_WPUEN 0x80
1421 //==============================================================================
1424 //==============================================================================
1427 extern __at(0x0096) __sfr PCON
;
1431 unsigned NOT_BOR
: 1;
1432 unsigned NOT_POR
: 1;
1433 unsigned NOT_RI
: 1;
1434 unsigned NOT_RMCLR
: 1;
1435 unsigned NOT_RWDT
: 1;
1437 unsigned STKUNF
: 1;
1438 unsigned STKOVF
: 1;
1441 extern __at(0x0096) volatile __PCONbits_t PCONbits
;
1443 #define _NOT_BOR 0x01
1444 #define _NOT_POR 0x02
1445 #define _NOT_RI 0x04
1446 #define _NOT_RMCLR 0x08
1447 #define _NOT_RWDT 0x10
1448 #define _STKUNF 0x40
1449 #define _STKOVF 0x80
1451 //==============================================================================
1454 //==============================================================================
1457 extern __at(0x0097) __sfr WDTCON
;
1463 unsigned SWDTEN
: 1;
1464 unsigned WDTPS0
: 1;
1465 unsigned WDTPS1
: 1;
1466 unsigned WDTPS2
: 1;
1467 unsigned WDTPS3
: 1;
1468 unsigned WDTPS4
: 1;
1481 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1483 #define _SWDTEN 0x01
1484 #define _WDTPS0 0x02
1485 #define _WDTPS1 0x04
1486 #define _WDTPS2 0x08
1487 #define _WDTPS3 0x10
1488 #define _WDTPS4 0x20
1490 //==============================================================================
1493 //==============================================================================
1496 extern __at(0x0098) __sfr OSCTUNE
;
1519 extern __at(0x0098) volatile __OSCTUNEbits_t OSCTUNEbits
;
1528 //==============================================================================
1531 //==============================================================================
1534 extern __at(0x0099) __sfr OSCCON
;
1547 unsigned SPLLEN
: 1;
1564 extern __at(0x0099) volatile __OSCCONbits_t OSCCONbits
;
1572 #define _SPLLEN 0x80
1574 //==============================================================================
1577 //==============================================================================
1580 extern __at(0x009A) __sfr OSCSTAT
;
1584 unsigned HFIOFS
: 1;
1585 unsigned LFIOFR
: 1;
1586 unsigned MFIOFR
: 1;
1587 unsigned HFIOFL
: 1;
1588 unsigned HFIOFR
: 1;
1594 extern __at(0x009A) volatile __OSCSTATbits_t OSCSTATbits
;
1596 #define _HFIOFS 0x01
1597 #define _LFIOFR 0x02
1598 #define _MFIOFR 0x04
1599 #define _HFIOFL 0x08
1600 #define _HFIOFR 0x10
1605 //==============================================================================
1607 extern __at(0x009B) __sfr ADRES
;
1608 extern __at(0x009B) __sfr ADRESL
;
1609 extern __at(0x009C) __sfr ADRESH
;
1611 //==============================================================================
1614 extern __at(0x009D) __sfr ADCON0
;
1621 unsigned GO_NOT_DONE
: 1;
1662 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1665 #define _GO_NOT_DONE 0x02
1674 //==============================================================================
1677 //==============================================================================
1680 extern __at(0x009E) __sfr ADCON1
;
1686 unsigned ADPREF0
: 1;
1687 unsigned ADPREF1
: 1;
1688 unsigned ADNREF
: 1;
1698 unsigned ADPREF
: 2;
1703 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1705 #define _ADPREF0 0x01
1706 #define _ADPREF1 0x02
1707 #define _ADNREF 0x04
1710 //==============================================================================
1713 //==============================================================================
1716 extern __at(0x009F) __sfr ADCON2
;
1725 unsigned TRIGSEL0
: 1;
1726 unsigned TRIGSEL1
: 1;
1727 unsigned TRIGSEL2
: 1;
1728 unsigned TRIGSEL3
: 1;
1729 unsigned TRIGSEL4
: 1;
1735 unsigned TRIGSEL
: 5;
1739 extern __at(0x009F) volatile __ADCON2bits_t ADCON2bits
;
1741 #define _TRIGSEL0 0x08
1742 #define _TRIGSEL1 0x10
1743 #define _TRIGSEL2 0x20
1744 #define _TRIGSEL3 0x40
1745 #define _TRIGSEL4 0x80
1747 //==============================================================================
1750 //==============================================================================
1753 extern __at(0x010C) __sfr LATA
;
1767 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1775 //==============================================================================
1778 //==============================================================================
1781 extern __at(0x010E) __sfr LATC
;
1804 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1813 //==============================================================================
1816 //==============================================================================
1819 extern __at(0x010F) __sfr CMOUT
;
1823 unsigned MC1OUT
: 1;
1824 unsigned MC2OUT
: 1;
1833 extern __at(0x010F) volatile __CMOUTbits_t CMOUTbits
;
1835 #define _MC1OUT 0x01
1836 #define _MC2OUT 0x02
1838 //==============================================================================
1841 //==============================================================================
1844 extern __at(0x0110) __sfr CM1CON0
;
1852 unsigned Reserved
: 1;
1862 unsigned C1SYNC
: 1;
1873 extern __at(0x0110) volatile __CM1CON0bits_t CM1CON0bits
;
1875 #define _CM1CON0_SYNC 0x01
1876 #define _CM1CON0_C1SYNC 0x01
1877 #define _CM1CON0_HYS 0x02
1878 #define _CM1CON0_C1HYS 0x02
1879 #define _CM1CON0_Reserved 0x04
1880 #define _CM1CON0_C1SP 0x04
1881 #define _CM1CON0_ZLF 0x08
1882 #define _CM1CON0_C1ZLF 0x08
1883 #define _CM1CON0_POL 0x10
1884 #define _CM1CON0_C1POL 0x10
1885 #define _CM1CON0_OUT 0x40
1886 #define _CM1CON0_C1OUT 0x40
1887 #define _CM1CON0_ON 0x80
1888 #define _CM1CON0_C1ON 0x80
1890 //==============================================================================
1893 //==============================================================================
1896 extern __at(0x0111) __sfr CM1CON1
;
1914 unsigned C1INTN
: 1;
1915 unsigned C1INTP
: 1;
1925 extern __at(0x0111) volatile __CM1CON1bits_t CM1CON1bits
;
1927 #define _CM1CON1_INTN 0x01
1928 #define _CM1CON1_C1INTN 0x01
1929 #define _CM1CON1_INTP 0x02
1930 #define _CM1CON1_C1INTP 0x02
1932 //==============================================================================
1935 //==============================================================================
1938 extern __at(0x0112) __sfr CM1NSEL
;
1956 unsigned C1NCH0
: 1;
1957 unsigned C1NCH1
: 1;
1958 unsigned C1NCH2
: 1;
1979 extern __at(0x0112) volatile __CM1NSELbits_t CM1NSELbits
;
1982 #define _C1NCH0 0x01
1984 #define _C1NCH1 0x02
1986 #define _C1NCH2 0x04
1988 //==============================================================================
1991 //==============================================================================
1994 extern __at(0x0113) __sfr CM1PSEL
;
2012 unsigned C1PCH0
: 1;
2013 unsigned C1PCH1
: 1;
2014 unsigned C1PCH2
: 1;
2015 unsigned C1PCH3
: 1;
2035 extern __at(0x0113) volatile __CM1PSELbits_t CM1PSELbits
;
2038 #define _C1PCH0 0x01
2040 #define _C1PCH1 0x02
2042 #define _C1PCH2 0x04
2044 #define _C1PCH3 0x08
2046 //==============================================================================
2049 //==============================================================================
2052 extern __at(0x0114) __sfr CM2CON0
;
2060 unsigned Reserved
: 1;
2070 unsigned C2SYNC
: 1;
2081 extern __at(0x0114) volatile __CM2CON0bits_t CM2CON0bits
;
2083 #define _CM2CON0_SYNC 0x01
2084 #define _CM2CON0_C2SYNC 0x01
2085 #define _CM2CON0_HYS 0x02
2086 #define _CM2CON0_C2HYS 0x02
2087 #define _CM2CON0_Reserved 0x04
2088 #define _CM2CON0_C2SP 0x04
2089 #define _CM2CON0_ZLF 0x08
2090 #define _CM2CON0_C2ZLF 0x08
2091 #define _CM2CON0_POL 0x10
2092 #define _CM2CON0_C2POL 0x10
2093 #define _CM2CON0_OUT 0x40
2094 #define _CM2CON0_C2OUT 0x40
2095 #define _CM2CON0_ON 0x80
2096 #define _CM2CON0_C2ON 0x80
2098 //==============================================================================
2101 //==============================================================================
2104 extern __at(0x0115) __sfr CM2CON1
;
2122 unsigned C2INTN
: 1;
2123 unsigned C2INTP
: 1;
2133 extern __at(0x0115) volatile __CM2CON1bits_t CM2CON1bits
;
2135 #define _CM2CON1_INTN 0x01
2136 #define _CM2CON1_C2INTN 0x01
2137 #define _CM2CON1_INTP 0x02
2138 #define _CM2CON1_C2INTP 0x02
2140 //==============================================================================
2143 //==============================================================================
2146 extern __at(0x0116) __sfr CM2NSEL
;
2164 unsigned C2NCH0
: 1;
2165 unsigned C2NCH1
: 1;
2166 unsigned C2NCH2
: 1;
2187 extern __at(0x0116) volatile __CM2NSELbits_t CM2NSELbits
;
2189 #define _CM2NSEL_NCH0 0x01
2190 #define _CM2NSEL_C2NCH0 0x01
2191 #define _CM2NSEL_NCH1 0x02
2192 #define _CM2NSEL_C2NCH1 0x02
2193 #define _CM2NSEL_NCH2 0x04
2194 #define _CM2NSEL_C2NCH2 0x04
2196 //==============================================================================
2199 //==============================================================================
2202 extern __at(0x0117) __sfr CM2PSEL
;
2220 unsigned C2PCH0
: 1;
2221 unsigned C2PCH1
: 1;
2222 unsigned C2PCH2
: 1;
2223 unsigned C2PCH3
: 1;
2243 extern __at(0x0117) volatile __CM2PSELbits_t CM2PSELbits
;
2245 #define _CM2PSEL_PCH0 0x01
2246 #define _CM2PSEL_C2PCH0 0x01
2247 #define _CM2PSEL_PCH1 0x02
2248 #define _CM2PSEL_C2PCH1 0x02
2249 #define _CM2PSEL_PCH2 0x04
2250 #define _CM2PSEL_C2PCH2 0x04
2251 #define _CM2PSEL_PCH3 0x08
2252 #define _CM2PSEL_C2PCH3 0x08
2254 //==============================================================================
2257 //==============================================================================
2260 extern __at(0x018C) __sfr ANSELA
;
2274 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
2281 //==============================================================================
2284 //==============================================================================
2287 extern __at(0x018E) __sfr ANSELC
;
2310 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
2317 //==============================================================================
2319 extern __at(0x0191) __sfr PMADR
;
2320 extern __at(0x0191) __sfr PMADRL
;
2321 extern __at(0x0192) __sfr PMADRH
;
2322 extern __at(0x0193) __sfr PMDAT
;
2323 extern __at(0x0193) __sfr PMDATL
;
2324 extern __at(0x0194) __sfr PMDATH
;
2326 //==============================================================================
2329 extern __at(0x0195) __sfr PMCON1
;
2343 extern __at(0x0195) volatile __PMCON1bits_t PMCON1bits
;
2353 //==============================================================================
2355 extern __at(0x0196) __sfr PMCON2
;
2356 extern __at(0x0199) __sfr RC1REG
;
2357 extern __at(0x0199) __sfr RCREG
;
2358 extern __at(0x0199) __sfr RCREG1
;
2359 extern __at(0x019A) __sfr TX1REG
;
2360 extern __at(0x019A) __sfr TXREG
;
2361 extern __at(0x019A) __sfr TXREG1
;
2362 extern __at(0x019B) __sfr SP1BRG
;
2363 extern __at(0x019B) __sfr SP1BRGL
;
2364 extern __at(0x019B) __sfr SPBRG
;
2365 extern __at(0x019B) __sfr SPBRG1
;
2366 extern __at(0x019B) __sfr SPBRGL
;
2367 extern __at(0x019C) __sfr SP1BRGH
;
2368 extern __at(0x019C) __sfr SPBRGH
;
2369 extern __at(0x019C) __sfr SPBRGH1
;
2371 //==============================================================================
2374 extern __at(0x019D) __sfr RC1STA
;
2388 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
2399 //==============================================================================
2402 //==============================================================================
2405 extern __at(0x019D) __sfr RCSTA
;
2419 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
2421 #define _RCSTA_RX9D 0x01
2422 #define _RCSTA_OERR 0x02
2423 #define _RCSTA_FERR 0x04
2424 #define _RCSTA_ADDEN 0x08
2425 #define _RCSTA_CREN 0x10
2426 #define _RCSTA_SREN 0x20
2427 #define _RCSTA_RX9 0x40
2428 #define _RCSTA_SPEN 0x80
2430 //==============================================================================
2433 //==============================================================================
2436 extern __at(0x019D) __sfr RCSTA1
;
2450 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
2452 #define _RCSTA1_RX9D 0x01
2453 #define _RCSTA1_OERR 0x02
2454 #define _RCSTA1_FERR 0x04
2455 #define _RCSTA1_ADDEN 0x08
2456 #define _RCSTA1_CREN 0x10
2457 #define _RCSTA1_SREN 0x20
2458 #define _RCSTA1_RX9 0x40
2459 #define _RCSTA1_SPEN 0x80
2461 //==============================================================================
2464 //==============================================================================
2467 extern __at(0x019E) __sfr TX1STA
;
2481 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
2483 #define _TX1STA_TX9D 0x01
2484 #define _TX1STA_TRMT 0x02
2485 #define _TX1STA_BRGH 0x04
2486 #define _TX1STA_SENDB 0x08
2487 #define _TX1STA_SYNC 0x10
2488 #define _TX1STA_TXEN 0x20
2489 #define _TX1STA_TX9 0x40
2490 #define _TX1STA_CSRC 0x80
2492 //==============================================================================
2495 //==============================================================================
2498 extern __at(0x019E) __sfr TXSTA
;
2512 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
2514 #define _TXSTA_TX9D 0x01
2515 #define _TXSTA_TRMT 0x02
2516 #define _TXSTA_BRGH 0x04
2517 #define _TXSTA_SENDB 0x08
2518 #define _TXSTA_SYNC 0x10
2519 #define _TXSTA_TXEN 0x20
2520 #define _TXSTA_TX9 0x40
2521 #define _TXSTA_CSRC 0x80
2523 //==============================================================================
2526 //==============================================================================
2529 extern __at(0x019E) __sfr TXSTA1
;
2543 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
2545 #define _TXSTA1_TX9D 0x01
2546 #define _TXSTA1_TRMT 0x02
2547 #define _TXSTA1_BRGH 0x04
2548 #define _TXSTA1_SENDB 0x08
2549 #define _TXSTA1_SYNC 0x10
2550 #define _TXSTA1_TXEN 0x20
2551 #define _TXSTA1_TX9 0x40
2552 #define _TXSTA1_CSRC 0x80
2554 //==============================================================================
2557 //==============================================================================
2560 extern __at(0x019F) __sfr BAUD1CON
;
2571 unsigned ABDOVF
: 1;
2574 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
2581 #define _ABDOVF 0x80
2583 //==============================================================================
2586 //==============================================================================
2589 extern __at(0x019F) __sfr BAUDCON
;
2600 unsigned ABDOVF
: 1;
2603 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
2605 #define _BAUDCON_ABDEN 0x01
2606 #define _BAUDCON_WUE 0x02
2607 #define _BAUDCON_BRG16 0x08
2608 #define _BAUDCON_SCKP 0x10
2609 #define _BAUDCON_RCIDL 0x40
2610 #define _BAUDCON_ABDOVF 0x80
2612 //==============================================================================
2615 //==============================================================================
2618 extern __at(0x019F) __sfr BAUDCON1
;
2629 unsigned ABDOVF
: 1;
2632 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
2634 #define _BAUDCON1_ABDEN 0x01
2635 #define _BAUDCON1_WUE 0x02
2636 #define _BAUDCON1_BRG16 0x08
2637 #define _BAUDCON1_SCKP 0x10
2638 #define _BAUDCON1_RCIDL 0x40
2639 #define _BAUDCON1_ABDOVF 0x80
2641 //==============================================================================
2644 //==============================================================================
2647 extern __at(0x019F) __sfr BAUDCTL
;
2658 unsigned ABDOVF
: 1;
2661 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
2663 #define _BAUDCTL_ABDEN 0x01
2664 #define _BAUDCTL_WUE 0x02
2665 #define _BAUDCTL_BRG16 0x08
2666 #define _BAUDCTL_SCKP 0x10
2667 #define _BAUDCTL_RCIDL 0x40
2668 #define _BAUDCTL_ABDOVF 0x80
2670 //==============================================================================
2673 //==============================================================================
2676 extern __at(0x019F) __sfr BAUDCTL1
;
2687 unsigned ABDOVF
: 1;
2690 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
2692 #define _BAUDCTL1_ABDEN 0x01
2693 #define _BAUDCTL1_WUE 0x02
2694 #define _BAUDCTL1_BRG16 0x08
2695 #define _BAUDCTL1_SCKP 0x10
2696 #define _BAUDCTL1_RCIDL 0x40
2697 #define _BAUDCTL1_ABDOVF 0x80
2699 //==============================================================================
2702 //==============================================================================
2705 extern __at(0x020C) __sfr WPUA
;
2728 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
2737 //==============================================================================
2740 //==============================================================================
2743 extern __at(0x020E) __sfr WPUC
;
2766 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
2775 //==============================================================================
2778 //==============================================================================
2781 extern __at(0x0211) __sfr SSP1BUF
;
2787 unsigned SSP1BUF0
: 1;
2788 unsigned SSP1BUF1
: 1;
2789 unsigned SSP1BUF2
: 1;
2790 unsigned SSP1BUF3
: 1;
2791 unsigned SSP1BUF4
: 1;
2792 unsigned SSP1BUF5
: 1;
2793 unsigned SSP1BUF6
: 1;
2794 unsigned SSP1BUF7
: 1;
2810 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
2812 #define _SSP1BUF0 0x01
2814 #define _SSP1BUF1 0x02
2816 #define _SSP1BUF2 0x04
2818 #define _SSP1BUF3 0x08
2820 #define _SSP1BUF4 0x10
2822 #define _SSP1BUF5 0x20
2824 #define _SSP1BUF6 0x40
2826 #define _SSP1BUF7 0x80
2829 //==============================================================================
2832 //==============================================================================
2835 extern __at(0x0211) __sfr SSPBUF
;
2841 unsigned SSP1BUF0
: 1;
2842 unsigned SSP1BUF1
: 1;
2843 unsigned SSP1BUF2
: 1;
2844 unsigned SSP1BUF3
: 1;
2845 unsigned SSP1BUF4
: 1;
2846 unsigned SSP1BUF5
: 1;
2847 unsigned SSP1BUF6
: 1;
2848 unsigned SSP1BUF7
: 1;
2864 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
2866 #define _SSPBUF_SSP1BUF0 0x01
2867 #define _SSPBUF_BUF0 0x01
2868 #define _SSPBUF_SSP1BUF1 0x02
2869 #define _SSPBUF_BUF1 0x02
2870 #define _SSPBUF_SSP1BUF2 0x04
2871 #define _SSPBUF_BUF2 0x04
2872 #define _SSPBUF_SSP1BUF3 0x08
2873 #define _SSPBUF_BUF3 0x08
2874 #define _SSPBUF_SSP1BUF4 0x10
2875 #define _SSPBUF_BUF4 0x10
2876 #define _SSPBUF_SSP1BUF5 0x20
2877 #define _SSPBUF_BUF5 0x20
2878 #define _SSPBUF_SSP1BUF6 0x40
2879 #define _SSPBUF_BUF6 0x40
2880 #define _SSPBUF_SSP1BUF7 0x80
2881 #define _SSPBUF_BUF7 0x80
2883 //==============================================================================
2886 //==============================================================================
2889 extern __at(0x0212) __sfr SSP1ADD
;
2895 unsigned SSP1ADD0
: 1;
2896 unsigned SSP1ADD1
: 1;
2897 unsigned SSP1ADD2
: 1;
2898 unsigned SSP1ADD3
: 1;
2899 unsigned SSP1ADD4
: 1;
2900 unsigned SSP1ADD5
: 1;
2901 unsigned SSP1ADD6
: 1;
2902 unsigned SSP1ADD7
: 1;
2918 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
2920 #define _SSP1ADD0 0x01
2922 #define _SSP1ADD1 0x02
2924 #define _SSP1ADD2 0x04
2926 #define _SSP1ADD3 0x08
2928 #define _SSP1ADD4 0x10
2930 #define _SSP1ADD5 0x20
2932 #define _SSP1ADD6 0x40
2934 #define _SSP1ADD7 0x80
2937 //==============================================================================
2940 //==============================================================================
2943 extern __at(0x0212) __sfr SSPADD
;
2949 unsigned SSP1ADD0
: 1;
2950 unsigned SSP1ADD1
: 1;
2951 unsigned SSP1ADD2
: 1;
2952 unsigned SSP1ADD3
: 1;
2953 unsigned SSP1ADD4
: 1;
2954 unsigned SSP1ADD5
: 1;
2955 unsigned SSP1ADD6
: 1;
2956 unsigned SSP1ADD7
: 1;
2972 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
2974 #define _SSPADD_SSP1ADD0 0x01
2975 #define _SSPADD_ADD0 0x01
2976 #define _SSPADD_SSP1ADD1 0x02
2977 #define _SSPADD_ADD1 0x02
2978 #define _SSPADD_SSP1ADD2 0x04
2979 #define _SSPADD_ADD2 0x04
2980 #define _SSPADD_SSP1ADD3 0x08
2981 #define _SSPADD_ADD3 0x08
2982 #define _SSPADD_SSP1ADD4 0x10
2983 #define _SSPADD_ADD4 0x10
2984 #define _SSPADD_SSP1ADD5 0x20
2985 #define _SSPADD_ADD5 0x20
2986 #define _SSPADD_SSP1ADD6 0x40
2987 #define _SSPADD_ADD6 0x40
2988 #define _SSPADD_SSP1ADD7 0x80
2989 #define _SSPADD_ADD7 0x80
2991 //==============================================================================
2994 //==============================================================================
2997 extern __at(0x0213) __sfr SSP1MSK
;
3003 unsigned SSP1MSK0
: 1;
3004 unsigned SSP1MSK1
: 1;
3005 unsigned SSP1MSK2
: 1;
3006 unsigned SSP1MSK3
: 1;
3007 unsigned SSP1MSK4
: 1;
3008 unsigned SSP1MSK5
: 1;
3009 unsigned SSP1MSK6
: 1;
3010 unsigned SSP1MSK7
: 1;
3026 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
3028 #define _SSP1MSK0 0x01
3030 #define _SSP1MSK1 0x02
3032 #define _SSP1MSK2 0x04
3034 #define _SSP1MSK3 0x08
3036 #define _SSP1MSK4 0x10
3038 #define _SSP1MSK5 0x20
3040 #define _SSP1MSK6 0x40
3042 #define _SSP1MSK7 0x80
3045 //==============================================================================
3048 //==============================================================================
3051 extern __at(0x0213) __sfr SSPMSK
;
3057 unsigned SSP1MSK0
: 1;
3058 unsigned SSP1MSK1
: 1;
3059 unsigned SSP1MSK2
: 1;
3060 unsigned SSP1MSK3
: 1;
3061 unsigned SSP1MSK4
: 1;
3062 unsigned SSP1MSK5
: 1;
3063 unsigned SSP1MSK6
: 1;
3064 unsigned SSP1MSK7
: 1;
3080 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
3082 #define _SSPMSK_SSP1MSK0 0x01
3083 #define _SSPMSK_MSK0 0x01
3084 #define _SSPMSK_SSP1MSK1 0x02
3085 #define _SSPMSK_MSK1 0x02
3086 #define _SSPMSK_SSP1MSK2 0x04
3087 #define _SSPMSK_MSK2 0x04
3088 #define _SSPMSK_SSP1MSK3 0x08
3089 #define _SSPMSK_MSK3 0x08
3090 #define _SSPMSK_SSP1MSK4 0x10
3091 #define _SSPMSK_MSK4 0x10
3092 #define _SSPMSK_SSP1MSK5 0x20
3093 #define _SSPMSK_MSK5 0x20
3094 #define _SSPMSK_SSP1MSK6 0x40
3095 #define _SSPMSK_MSK6 0x40
3096 #define _SSPMSK_SSP1MSK7 0x80
3097 #define _SSPMSK_MSK7 0x80
3099 //==============================================================================
3102 //==============================================================================
3105 extern __at(0x0214) __sfr SSP1STAT
;
3111 unsigned R_NOT_W
: 1;
3114 unsigned D_NOT_A
: 1;
3119 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
3123 #define _R_NOT_W 0x04
3126 #define _D_NOT_A 0x20
3130 //==============================================================================
3133 //==============================================================================
3136 extern __at(0x0214) __sfr SSPSTAT
;
3142 unsigned R_NOT_W
: 1;
3145 unsigned D_NOT_A
: 1;
3150 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
3152 #define _SSPSTAT_BF 0x01
3153 #define _SSPSTAT_UA 0x02
3154 #define _SSPSTAT_R_NOT_W 0x04
3155 #define _SSPSTAT_S 0x08
3156 #define _SSPSTAT_P 0x10
3157 #define _SSPSTAT_D_NOT_A 0x20
3158 #define _SSPSTAT_CKE 0x40
3159 #define _SSPSTAT_SMP 0x80
3161 //==============================================================================
3164 //==============================================================================
3167 extern __at(0x0215) __sfr SSP1CON
;
3190 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
3201 //==============================================================================
3204 //==============================================================================
3207 extern __at(0x0215) __sfr SSP1CON1
;
3230 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
3232 #define _SSP1CON1_SSPM0 0x01
3233 #define _SSP1CON1_SSPM1 0x02
3234 #define _SSP1CON1_SSPM2 0x04
3235 #define _SSP1CON1_SSPM3 0x08
3236 #define _SSP1CON1_CKP 0x10
3237 #define _SSP1CON1_SSPEN 0x20
3238 #define _SSP1CON1_SSPOV 0x40
3239 #define _SSP1CON1_WCOL 0x80
3241 //==============================================================================
3244 //==============================================================================
3247 extern __at(0x0215) __sfr SSPCON
;
3270 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
3272 #define _SSPCON_SSPM0 0x01
3273 #define _SSPCON_SSPM1 0x02
3274 #define _SSPCON_SSPM2 0x04
3275 #define _SSPCON_SSPM3 0x08
3276 #define _SSPCON_CKP 0x10
3277 #define _SSPCON_SSPEN 0x20
3278 #define _SSPCON_SSPOV 0x40
3279 #define _SSPCON_WCOL 0x80
3281 //==============================================================================
3284 //==============================================================================
3287 extern __at(0x0215) __sfr SSPCON1
;
3310 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
3312 #define _SSPCON1_SSPM0 0x01
3313 #define _SSPCON1_SSPM1 0x02
3314 #define _SSPCON1_SSPM2 0x04
3315 #define _SSPCON1_SSPM3 0x08
3316 #define _SSPCON1_CKP 0x10
3317 #define _SSPCON1_SSPEN 0x20
3318 #define _SSPCON1_SSPOV 0x40
3319 #define _SSPCON1_WCOL 0x80
3321 //==============================================================================
3324 //==============================================================================
3327 extern __at(0x0216) __sfr SSP1CON2
;
3337 unsigned ACKSTAT
: 1;
3341 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
3349 #define _ACKSTAT 0x40
3352 //==============================================================================
3355 //==============================================================================
3358 extern __at(0x0216) __sfr SSPCON2
;
3368 unsigned ACKSTAT
: 1;
3372 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
3374 #define _SSPCON2_SEN 0x01
3375 #define _SSPCON2_RSEN 0x02
3376 #define _SSPCON2_PEN 0x04
3377 #define _SSPCON2_RCEN 0x08
3378 #define _SSPCON2_ACKEN 0x10
3379 #define _SSPCON2_ACKDT 0x20
3380 #define _SSPCON2_ACKSTAT 0x40
3381 #define _SSPCON2_GCEN 0x80
3383 //==============================================================================
3386 //==============================================================================
3389 extern __at(0x0217) __sfr SSP1CON3
;
3400 unsigned ACKTIM
: 1;
3403 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
3412 #define _ACKTIM 0x80
3414 //==============================================================================
3417 //==============================================================================
3420 extern __at(0x0217) __sfr SSPCON3
;
3431 unsigned ACKTIM
: 1;
3434 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
3436 #define _SSPCON3_DHEN 0x01
3437 #define _SSPCON3_AHEN 0x02
3438 #define _SSPCON3_SBCDE 0x04
3439 #define _SSPCON3_SDAHT 0x08
3440 #define _SSPCON3_BOEN 0x10
3441 #define _SSPCON3_SCIE 0x20
3442 #define _SSPCON3_PCIE 0x40
3443 #define _SSPCON3_ACKTIM 0x80
3445 //==============================================================================
3448 //==============================================================================
3451 extern __at(0x021D) __sfr BORCON
;
3455 unsigned BORRDY
: 1;
3462 unsigned SBOREN
: 1;
3465 extern __at(0x021D) volatile __BORCONbits_t BORCONbits
;
3467 #define _BORRDY 0x01
3469 #define _SBOREN 0x80
3471 //==============================================================================
3474 //==============================================================================
3477 extern __at(0x021E) __sfr FVRCON
;
3487 unsigned FVRRDY
: 1;
3491 extern __at(0x021E) volatile __FVRCONbits_t FVRCONbits
;
3495 #define _FVRRDY 0x40
3498 //==============================================================================
3501 //==============================================================================
3504 extern __at(0x021F) __sfr ZCD1CON
;
3508 unsigned ZCD1INTN
: 1;
3509 unsigned ZCD1INTP
: 1;
3512 unsigned ZCD1POL
: 1;
3513 unsigned ZCD1OUT
: 1;
3515 unsigned ZCD1EN
: 1;
3518 extern __at(0x021F) volatile __ZCD1CONbits_t ZCD1CONbits
;
3520 #define _ZCD1INTN 0x01
3521 #define _ZCD1INTP 0x02
3522 #define _ZCD1POL 0x10
3523 #define _ZCD1OUT 0x20
3524 #define _ZCD1EN 0x80
3526 //==============================================================================
3529 //==============================================================================
3532 extern __at(0x028C) __sfr ODCONA
;
3546 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
3554 //==============================================================================
3557 //==============================================================================
3560 extern __at(0x028E) __sfr ODCONC
;
3583 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
3592 //==============================================================================
3594 extern __at(0x0291) __sfr CCPR1
;
3595 extern __at(0x0291) __sfr CCPR1L
;
3596 extern __at(0x0292) __sfr CCPR1H
;
3598 //==============================================================================
3601 extern __at(0x0293) __sfr CCP1CON
;
3619 unsigned CCP1MODE0
: 1;
3620 unsigned CCP1MODE1
: 1;
3621 unsigned CCP1MODE2
: 1;
3622 unsigned CCP1MODE3
: 1;
3623 unsigned CCP1FMT
: 1;
3624 unsigned CCP1OUT
: 1;
3626 unsigned CCP1EN
: 1;
3637 unsigned CCP1MODE
: 4;
3642 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
3645 #define _CCP1MODE0 0x01
3647 #define _CCP1MODE1 0x02
3649 #define _CCP1MODE2 0x04
3651 #define _CCP1MODE3 0x08
3653 #define _CCP1FMT 0x10
3655 #define _CCP1OUT 0x20
3657 #define _CCP1EN 0x80
3659 //==============================================================================
3662 //==============================================================================
3665 extern __at(0x0294) __sfr CCP1CAP
;
3683 unsigned CCP1CTS0
: 1;
3684 unsigned CCP1CTS1
: 1;
3685 unsigned CCP1CTS2
: 1;
3701 unsigned CCP1CTS
: 3;
3706 extern __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits
;
3709 #define _CCP1CTS0 0x01
3711 #define _CCP1CTS1 0x02
3713 #define _CCP1CTS2 0x04
3715 //==============================================================================
3718 //==============================================================================
3721 extern __at(0x029E) __sfr CCPTMRS
;
3727 unsigned C1TSEL0
: 1;
3728 unsigned C1TSEL1
: 1;
3731 unsigned P3TSEL0
: 1;
3732 unsigned P3TSEL1
: 1;
3739 unsigned C1TSEL
: 2;
3746 unsigned P3TSEL
: 2;
3751 extern __at(0x029E) volatile __CCPTMRSbits_t CCPTMRSbits
;
3753 #define _C1TSEL0 0x01
3754 #define _C1TSEL1 0x02
3755 #define _P3TSEL0 0x10
3756 #define _P3TSEL1 0x20
3758 //==============================================================================
3761 //==============================================================================
3764 extern __at(0x030C) __sfr SLRCONA
;
3778 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
3786 //==============================================================================
3789 //==============================================================================
3792 extern __at(0x030E) __sfr SLRCONC
;
3815 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
3824 //==============================================================================
3827 //==============================================================================
3830 extern __at(0x038C) __sfr INLVLA
;
3836 unsigned INLVLA0
: 1;
3837 unsigned INLVLA1
: 1;
3838 unsigned INLVLA2
: 1;
3839 unsigned INLVLA3
: 1;
3840 unsigned INLVLA4
: 1;
3841 unsigned INLVLA5
: 1;
3848 unsigned INLVLA
: 6;
3853 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
3855 #define _INLVLA0 0x01
3856 #define _INLVLA1 0x02
3857 #define _INLVLA2 0x04
3858 #define _INLVLA3 0x08
3859 #define _INLVLA4 0x10
3860 #define _INLVLA5 0x20
3862 //==============================================================================
3865 //==============================================================================
3868 extern __at(0x038E) __sfr INLVLC
;
3874 unsigned INLVLC0
: 1;
3875 unsigned INLVLC1
: 1;
3876 unsigned INLVLC2
: 1;
3877 unsigned INLVLC3
: 1;
3878 unsigned INLVLC4
: 1;
3879 unsigned INLVLC5
: 1;
3886 unsigned INLVLC
: 6;
3891 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
3893 #define _INLVLC0 0x01
3894 #define _INLVLC1 0x02
3895 #define _INLVLC2 0x04
3896 #define _INLVLC3 0x08
3897 #define _INLVLC4 0x10
3898 #define _INLVLC5 0x20
3900 //==============================================================================
3903 //==============================================================================
3906 extern __at(0x0391) __sfr IOCAP
;
3912 unsigned IOCAP0
: 1;
3913 unsigned IOCAP1
: 1;
3914 unsigned IOCAP2
: 1;
3915 unsigned IOCAP3
: 1;
3916 unsigned IOCAP4
: 1;
3917 unsigned IOCAP5
: 1;
3929 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
3931 #define _IOCAP0 0x01
3932 #define _IOCAP1 0x02
3933 #define _IOCAP2 0x04
3934 #define _IOCAP3 0x08
3935 #define _IOCAP4 0x10
3936 #define _IOCAP5 0x20
3938 //==============================================================================
3941 //==============================================================================
3944 extern __at(0x0392) __sfr IOCAN
;
3950 unsigned IOCAN0
: 1;
3951 unsigned IOCAN1
: 1;
3952 unsigned IOCAN2
: 1;
3953 unsigned IOCAN3
: 1;
3954 unsigned IOCAN4
: 1;
3955 unsigned IOCAN5
: 1;
3967 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
3969 #define _IOCAN0 0x01
3970 #define _IOCAN1 0x02
3971 #define _IOCAN2 0x04
3972 #define _IOCAN3 0x08
3973 #define _IOCAN4 0x10
3974 #define _IOCAN5 0x20
3976 //==============================================================================
3979 //==============================================================================
3982 extern __at(0x0393) __sfr IOCAF
;
3988 unsigned IOCAF0
: 1;
3989 unsigned IOCAF1
: 1;
3990 unsigned IOCAF2
: 1;
3991 unsigned IOCAF3
: 1;
3992 unsigned IOCAF4
: 1;
3993 unsigned IOCAF5
: 1;
4005 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
4007 #define _IOCAF0 0x01
4008 #define _IOCAF1 0x02
4009 #define _IOCAF2 0x04
4010 #define _IOCAF3 0x08
4011 #define _IOCAF4 0x10
4012 #define _IOCAF5 0x20
4014 //==============================================================================
4017 //==============================================================================
4020 extern __at(0x0397) __sfr IOCCP
;
4026 unsigned IOCCP0
: 1;
4027 unsigned IOCCP1
: 1;
4028 unsigned IOCCP2
: 1;
4029 unsigned IOCCP3
: 1;
4030 unsigned IOCCP4
: 1;
4031 unsigned IOCCP5
: 1;
4043 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
4045 #define _IOCCP0 0x01
4046 #define _IOCCP1 0x02
4047 #define _IOCCP2 0x04
4048 #define _IOCCP3 0x08
4049 #define _IOCCP4 0x10
4050 #define _IOCCP5 0x20
4052 //==============================================================================
4055 //==============================================================================
4058 extern __at(0x0398) __sfr IOCCN
;
4064 unsigned IOCCN0
: 1;
4065 unsigned IOCCN1
: 1;
4066 unsigned IOCCN2
: 1;
4067 unsigned IOCCN3
: 1;
4068 unsigned IOCCN4
: 1;
4069 unsigned IOCCN5
: 1;
4081 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
4083 #define _IOCCN0 0x01
4084 #define _IOCCN1 0x02
4085 #define _IOCCN2 0x04
4086 #define _IOCCN3 0x08
4087 #define _IOCCN4 0x10
4088 #define _IOCCN5 0x20
4090 //==============================================================================
4093 //==============================================================================
4096 extern __at(0x0399) __sfr IOCCF
;
4102 unsigned IOCCF0
: 1;
4103 unsigned IOCCF1
: 1;
4104 unsigned IOCCF2
: 1;
4105 unsigned IOCCF3
: 1;
4106 unsigned IOCCF4
: 1;
4107 unsigned IOCCF5
: 1;
4119 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
4121 #define _IOCCF0 0x01
4122 #define _IOCCF1 0x02
4123 #define _IOCCF2 0x04
4124 #define _IOCCF3 0x08
4125 #define _IOCCF4 0x10
4126 #define _IOCCF5 0x20
4128 //==============================================================================
4131 //==============================================================================
4134 extern __at(0x039B) __sfr MD1CON0
;
4152 unsigned MD1BIT
: 1;
4156 unsigned MD1OPOL
: 1;
4157 unsigned MD1OUT
: 1;
4163 extern __at(0x039B) volatile __MD1CON0bits_t MD1CON0bits
;
4165 #define _MD1CON0_BIT 0x01
4166 #define _MD1CON0_MD1BIT 0x01
4167 #define _MD1CON0_OPOL 0x10
4168 #define _MD1CON0_MD1OPOL 0x10
4169 #define _MD1CON0_OUT 0x20
4170 #define _MD1CON0_MD1OUT 0x20
4171 #define _MD1CON0_EN 0x80
4172 #define _MD1CON0_MD1EN 0x80
4174 //==============================================================================
4177 //==============================================================================
4180 extern __at(0x039C) __sfr MD1CON1
;
4186 unsigned CLSYNC
: 1;
4190 unsigned CHSYNC
: 1;
4198 unsigned MD1CLSYNC
: 1;
4199 unsigned MD1CLPOL
: 1;
4202 unsigned MD1CHSYNC
: 1;
4203 unsigned MD1CHPOL
: 1;
4209 extern __at(0x039C) volatile __MD1CON1bits_t MD1CON1bits
;
4211 #define _CLSYNC 0x01
4212 #define _MD1CLSYNC 0x01
4214 #define _MD1CLPOL 0x02
4215 #define _CHSYNC 0x10
4216 #define _MD1CHSYNC 0x10
4218 #define _MD1CHPOL 0x20
4220 //==============================================================================
4223 //==============================================================================
4226 extern __at(0x039D) __sfr MD1SRC
;
4244 unsigned MD1MS0
: 1;
4245 unsigned MD1MS1
: 1;
4246 unsigned MD1MS2
: 1;
4247 unsigned MD1MS3
: 1;
4248 unsigned MD1MS4
: 1;
4267 extern __at(0x039D) volatile __MD1SRCbits_t MD1SRCbits
;
4270 #define _MD1MS0 0x01
4272 #define _MD1MS1 0x02
4274 #define _MD1MS2 0x04
4276 #define _MD1MS3 0x08
4278 #define _MD1MS4 0x10
4280 //==============================================================================
4283 //==============================================================================
4286 extern __at(0x039E) __sfr MD1CARL
;
4304 unsigned MD1CL0
: 1;
4305 unsigned MD1CL1
: 1;
4306 unsigned MD1CL2
: 1;
4307 unsigned MD1CL3
: 1;
4327 extern __at(0x039E) volatile __MD1CARLbits_t MD1CARLbits
;
4330 #define _MD1CL0 0x01
4332 #define _MD1CL1 0x02
4334 #define _MD1CL2 0x04
4336 #define _MD1CL3 0x08
4338 //==============================================================================
4341 //==============================================================================
4344 extern __at(0x039F) __sfr MD1CARH
;
4362 unsigned MD1CH0
: 1;
4363 unsigned MD1CH1
: 1;
4364 unsigned MD1CH2
: 1;
4365 unsigned MD1CH3
: 1;
4385 extern __at(0x039F) volatile __MD1CARHbits_t MD1CARHbits
;
4388 #define _MD1CH0 0x01
4390 #define _MD1CH1 0x02
4392 #define _MD1CH2 0x04
4394 #define _MD1CH3 0x08
4396 //==============================================================================
4399 //==============================================================================
4402 extern __at(0x040E) __sfr HIDRVC
;
4416 extern __at(0x040E) volatile __HIDRVCbits_t HIDRVCbits
;
4421 //==============================================================================
4423 extern __at(0x0413) __sfr T4TMR
;
4424 extern __at(0x0413) __sfr TMR4
;
4425 extern __at(0x0414) __sfr PR4
;
4426 extern __at(0x0414) __sfr T4PR
;
4428 //==============================================================================
4431 extern __at(0x0415) __sfr T4CON
;
4437 unsigned OUTPS0
: 1;
4438 unsigned OUTPS1
: 1;
4439 unsigned OUTPS2
: 1;
4440 unsigned OUTPS3
: 1;
4449 unsigned T4OUTPS0
: 1;
4450 unsigned T4OUTPS1
: 1;
4451 unsigned T4OUTPS2
: 1;
4452 unsigned T4OUTPS3
: 1;
4453 unsigned T4CKPS0
: 1;
4454 unsigned T4CKPS1
: 1;
4455 unsigned T4CKPS2
: 1;
4468 unsigned TMR4ON
: 1;
4479 unsigned T4OUTPS
: 4;
4493 unsigned T4CKPS
: 3;
4498 extern __at(0x0415) volatile __T4CONbits_t T4CONbits
;
4500 #define _T4CON_OUTPS0 0x01
4501 #define _T4CON_T4OUTPS0 0x01
4502 #define _T4CON_OUTPS1 0x02
4503 #define _T4CON_T4OUTPS1 0x02
4504 #define _T4CON_OUTPS2 0x04
4505 #define _T4CON_T4OUTPS2 0x04
4506 #define _T4CON_OUTPS3 0x08
4507 #define _T4CON_T4OUTPS3 0x08
4508 #define _T4CON_CKPS0 0x10
4509 #define _T4CON_T4CKPS0 0x10
4510 #define _T4CON_CKPS1 0x20
4511 #define _T4CON_T4CKPS1 0x20
4512 #define _T4CON_CKPS2 0x40
4513 #define _T4CON_T4CKPS2 0x40
4514 #define _T4CON_ON 0x80
4515 #define _T4CON_T4ON 0x80
4516 #define _T4CON_TMR4ON 0x80
4518 //==============================================================================
4521 //==============================================================================
4524 extern __at(0x0416) __sfr T4HLT
;
4535 unsigned CKSYNC
: 1;
4542 unsigned T4MODE0
: 1;
4543 unsigned T4MODE1
: 1;
4544 unsigned T4MODE2
: 1;
4545 unsigned T4MODE3
: 1;
4546 unsigned T4MODE4
: 1;
4547 unsigned T4CKSYNC
: 1;
4548 unsigned T4CKPOL
: 1;
4549 unsigned T4PSYNC
: 1;
4554 unsigned T4MODE
: 5;
4565 extern __at(0x0416) volatile __T4HLTbits_t T4HLTbits
;
4567 #define _T4HLT_MODE0 0x01
4568 #define _T4HLT_T4MODE0 0x01
4569 #define _T4HLT_MODE1 0x02
4570 #define _T4HLT_T4MODE1 0x02
4571 #define _T4HLT_MODE2 0x04
4572 #define _T4HLT_T4MODE2 0x04
4573 #define _T4HLT_MODE3 0x08
4574 #define _T4HLT_T4MODE3 0x08
4575 #define _T4HLT_MODE4 0x10
4576 #define _T4HLT_T4MODE4 0x10
4577 #define _T4HLT_CKSYNC 0x20
4578 #define _T4HLT_T4CKSYNC 0x20
4579 #define _T4HLT_CKPOL 0x40
4580 #define _T4HLT_T4CKPOL 0x40
4581 #define _T4HLT_PSYNC 0x80
4582 #define _T4HLT_T4PSYNC 0x80
4584 //==============================================================================
4587 //==============================================================================
4590 extern __at(0x0417) __sfr T4CLKCON
;
4631 extern __at(0x0417) volatile __T4CLKCONbits_t T4CLKCONbits
;
4633 #define _T4CLKCON_CS0 0x01
4634 #define _T4CLKCON_T4CS0 0x01
4635 #define _T4CLKCON_CS1 0x02
4636 #define _T4CLKCON_T4CS1 0x02
4637 #define _T4CLKCON_CS2 0x04
4638 #define _T4CLKCON_T4CS2 0x04
4639 #define _T4CLKCON_CS3 0x08
4640 #define _T4CLKCON_T4CS3 0x08
4642 //==============================================================================
4645 //==============================================================================
4648 extern __at(0x0418) __sfr T4RST
;
4666 unsigned T4RSEL0
: 1;
4667 unsigned T4RSEL1
: 1;
4668 unsigned T4RSEL2
: 1;
4669 unsigned T4RSEL3
: 1;
4684 unsigned T4RSEL
: 4;
4689 extern __at(0x0418) volatile __T4RSTbits_t T4RSTbits
;
4691 #define _T4RST_RSEL0 0x01
4692 #define _T4RST_T4RSEL0 0x01
4693 #define _T4RST_RSEL1 0x02
4694 #define _T4RST_T4RSEL1 0x02
4695 #define _T4RST_RSEL2 0x04
4696 #define _T4RST_T4RSEL2 0x04
4697 #define _T4RST_RSEL3 0x08
4698 #define _T4RST_T4RSEL3 0x08
4700 //==============================================================================
4702 extern __at(0x041A) __sfr T6TMR
;
4703 extern __at(0x041A) __sfr TMR6
;
4704 extern __at(0x041B) __sfr PR6
;
4705 extern __at(0x041B) __sfr T6PR
;
4707 //==============================================================================
4710 extern __at(0x041C) __sfr T6CON
;
4716 unsigned OUTPS0
: 1;
4717 unsigned OUTPS1
: 1;
4718 unsigned OUTPS2
: 1;
4719 unsigned OUTPS3
: 1;
4728 unsigned T6OUTPS0
: 1;
4729 unsigned T6OUTPS1
: 1;
4730 unsigned T6OUTPS2
: 1;
4731 unsigned T6OUTPS3
: 1;
4732 unsigned T6CKPS0
: 1;
4733 unsigned T6CKPS1
: 1;
4734 unsigned T6CKPS2
: 1;
4747 unsigned TMR6ON
: 1;
4758 unsigned T6OUTPS
: 4;
4765 unsigned T6CKPS
: 3;
4777 extern __at(0x041C) volatile __T6CONbits_t T6CONbits
;
4779 #define _T6CON_OUTPS0 0x01
4780 #define _T6CON_T6OUTPS0 0x01
4781 #define _T6CON_OUTPS1 0x02
4782 #define _T6CON_T6OUTPS1 0x02
4783 #define _T6CON_OUTPS2 0x04
4784 #define _T6CON_T6OUTPS2 0x04
4785 #define _T6CON_OUTPS3 0x08
4786 #define _T6CON_T6OUTPS3 0x08
4787 #define _T6CON_CKPS0 0x10
4788 #define _T6CON_T6CKPS0 0x10
4789 #define _T6CON_CKPS1 0x20
4790 #define _T6CON_T6CKPS1 0x20
4791 #define _T6CON_CKPS2 0x40
4792 #define _T6CON_T6CKPS2 0x40
4793 #define _T6CON_ON 0x80
4794 #define _T6CON_T6ON 0x80
4795 #define _T6CON_TMR6ON 0x80
4797 //==============================================================================
4800 //==============================================================================
4803 extern __at(0x041D) __sfr T6HLT
;
4814 unsigned CKSYNC
: 1;
4821 unsigned T6MODE0
: 1;
4822 unsigned T6MODE1
: 1;
4823 unsigned T6MODE2
: 1;
4824 unsigned T6MODE3
: 1;
4825 unsigned T6MODE4
: 1;
4826 unsigned T6CKSYNC
: 1;
4827 unsigned T6CKPOL
: 1;
4828 unsigned T6PSYNC
: 1;
4839 unsigned T6MODE
: 5;
4844 extern __at(0x041D) volatile __T6HLTbits_t T6HLTbits
;
4846 #define _T6HLT_MODE0 0x01
4847 #define _T6HLT_T6MODE0 0x01
4848 #define _T6HLT_MODE1 0x02
4849 #define _T6HLT_T6MODE1 0x02
4850 #define _T6HLT_MODE2 0x04
4851 #define _T6HLT_T6MODE2 0x04
4852 #define _T6HLT_MODE3 0x08
4853 #define _T6HLT_T6MODE3 0x08
4854 #define _T6HLT_MODE4 0x10
4855 #define _T6HLT_T6MODE4 0x10
4856 #define _T6HLT_CKSYNC 0x20
4857 #define _T6HLT_T6CKSYNC 0x20
4858 #define _T6HLT_CKPOL 0x40
4859 #define _T6HLT_T6CKPOL 0x40
4860 #define _T6HLT_PSYNC 0x80
4861 #define _T6HLT_T6PSYNC 0x80
4863 //==============================================================================
4866 //==============================================================================
4869 extern __at(0x041E) __sfr T6CLKCON
;
4910 extern __at(0x041E) volatile __T6CLKCONbits_t T6CLKCONbits
;
4912 #define _T6CLKCON_CS0 0x01
4913 #define _T6CLKCON_T6CS0 0x01
4914 #define _T6CLKCON_CS1 0x02
4915 #define _T6CLKCON_T6CS1 0x02
4916 #define _T6CLKCON_CS2 0x04
4917 #define _T6CLKCON_T6CS2 0x04
4918 #define _T6CLKCON_CS3 0x08
4919 #define _T6CLKCON_T6CS3 0x08
4921 //==============================================================================
4924 //==============================================================================
4927 extern __at(0x041F) __sfr T6RST
;
4945 unsigned T6RSEL0
: 1;
4946 unsigned T6RSEL1
: 1;
4947 unsigned T6RSEL2
: 1;
4948 unsigned T6RSEL3
: 1;
4957 unsigned T6RSEL
: 4;
4968 extern __at(0x041F) volatile __T6RSTbits_t T6RSTbits
;
4970 #define _T6RST_RSEL0 0x01
4971 #define _T6RST_T6RSEL0 0x01
4972 #define _T6RST_RSEL1 0x02
4973 #define _T6RST_T6RSEL1 0x02
4974 #define _T6RST_RSEL2 0x04
4975 #define _T6RST_T6RSEL2 0x04
4976 #define _T6RST_RSEL3 0x08
4977 #define _T6RST_T6RSEL3 0x08
4979 //==============================================================================
4981 extern __at(0x0493) __sfr TMR3
;
4982 extern __at(0x0493) __sfr TMR3L
;
4983 extern __at(0x0494) __sfr TMR3H
;
4985 //==============================================================================
4988 extern __at(0x0495) __sfr T3CON
;
4996 unsigned NOT_SYNC
: 1;
5010 unsigned T3CKPS0
: 1;
5011 unsigned T3CKPS1
: 1;
5018 unsigned TMR3ON
: 1;
5020 unsigned NOT_T3SYNC
: 1;
5024 unsigned TMR3CS0
: 1;
5025 unsigned TMR3CS1
: 1;
5050 unsigned T3CKPS
: 2;
5063 unsigned TMR3CS
: 2;
5073 extern __at(0x0495) volatile __T3CONbits_t T3CONbits
;
5075 #define _T3CON_ON 0x01
5076 #define _T3CON_TMRON 0x01
5077 #define _T3CON_TMR3ON 0x01
5078 #define _T3CON_T3ON 0x01
5079 #define _T3CON_NOT_SYNC 0x04
5080 #define _T3CON_SYNC 0x04
5081 #define _T3CON_NOT_T3SYNC 0x04
5082 #define _T3CON_CKPS0 0x10
5083 #define _T3CON_T3CKPS0 0x10
5084 #define _T3CON_CKPS1 0x20
5085 #define _T3CON_T3CKPS1 0x20
5086 #define _T3CON_CS0 0x40
5087 #define _T3CON_T3CS0 0x40
5088 #define _T3CON_TMR3CS0 0x40
5089 #define _T3CON_CS1 0x80
5090 #define _T3CON_T3CS1 0x80
5091 #define _T3CON_TMR3CS1 0x80
5093 //==============================================================================
5096 //==============================================================================
5099 extern __at(0x0496) __sfr T3GCON
;
5108 unsigned GGO_NOT_DONE
: 1;
5117 unsigned T3GSS0
: 1;
5118 unsigned T3GSS1
: 1;
5119 unsigned T3GVAL
: 1;
5120 unsigned T3GGO_NOT_DONE
: 1;
5121 unsigned T3GSPM
: 1;
5123 unsigned T3GPOL
: 1;
5136 unsigned TMR3GE
: 1;
5152 extern __at(0x0496) volatile __T3GCONbits_t T3GCONbits
;
5154 #define _T3GCON_GSS0 0x01
5155 #define _T3GCON_T3GSS0 0x01
5156 #define _T3GCON_GSS1 0x02
5157 #define _T3GCON_T3GSS1 0x02
5158 #define _T3GCON_GVAL 0x04
5159 #define _T3GCON_T3GVAL 0x04
5160 #define _T3GCON_GGO_NOT_DONE 0x08
5161 #define _T3GCON_T3GGO_NOT_DONE 0x08
5162 #define _T3GCON_GSPM 0x10
5163 #define _T3GCON_T3GSPM 0x10
5164 #define _T3GCON_GTM 0x20
5165 #define _T3GCON_T3GTM 0x20
5166 #define _T3GCON_GPOL 0x40
5167 #define _T3GCON_T3GPOL 0x40
5168 #define _T3GCON_GE 0x80
5169 #define _T3GCON_T3GE 0x80
5170 #define _T3GCON_TMR3GE 0x80
5172 //==============================================================================
5174 extern __at(0x049A) __sfr TMR5
;
5175 extern __at(0x049A) __sfr TMR5L
;
5176 extern __at(0x049B) __sfr TMR5H
;
5178 //==============================================================================
5181 extern __at(0x049C) __sfr T5CON
;
5189 unsigned NOT_SYNC
: 1;
5203 unsigned T5CKPS0
: 1;
5204 unsigned T5CKPS1
: 1;
5211 unsigned TMR5ON
: 1;
5213 unsigned NOT_T5SYNC
: 1;
5217 unsigned TMR5CS0
: 1;
5218 unsigned TMR5CS1
: 1;
5236 unsigned T5CKPS
: 2;
5262 unsigned TMR5CS
: 2;
5266 extern __at(0x049C) volatile __T5CONbits_t T5CONbits
;
5268 #define _T5CON_ON 0x01
5269 #define _T5CON_TMRON 0x01
5270 #define _T5CON_TMR5ON 0x01
5271 #define _T5CON_T5ON 0x01
5272 #define _T5CON_NOT_SYNC 0x04
5273 #define _T5CON_SYNC 0x04
5274 #define _T5CON_NOT_T5SYNC 0x04
5275 #define _T5CON_CKPS0 0x10
5276 #define _T5CON_T5CKPS0 0x10
5277 #define _T5CON_CKPS1 0x20
5278 #define _T5CON_T5CKPS1 0x20
5279 #define _T5CON_CS0 0x40
5280 #define _T5CON_T5CS0 0x40
5281 #define _T5CON_TMR5CS0 0x40
5282 #define _T5CON_CS1 0x80
5283 #define _T5CON_T5CS1 0x80
5284 #define _T5CON_TMR5CS1 0x80
5286 //==============================================================================
5289 //==============================================================================
5292 extern __at(0x049D) __sfr T5GCON
;
5301 unsigned GGO_NOT_DONE
: 1;
5310 unsigned T5GSS0
: 1;
5311 unsigned T5GSS1
: 1;
5312 unsigned T5GVAL
: 1;
5313 unsigned T5GGO_NOT_DONE
: 1;
5314 unsigned T5GSPM
: 1;
5316 unsigned T5GPOL
: 1;
5329 unsigned TMR5GE
: 1;
5345 extern __at(0x049D) volatile __T5GCONbits_t T5GCONbits
;
5347 #define _T5GCON_GSS0 0x01
5348 #define _T5GCON_T5GSS0 0x01
5349 #define _T5GCON_GSS1 0x02
5350 #define _T5GCON_T5GSS1 0x02
5351 #define _T5GCON_GVAL 0x04
5352 #define _T5GCON_T5GVAL 0x04
5353 #define _T5GCON_GGO_NOT_DONE 0x08
5354 #define _T5GCON_T5GGO_NOT_DONE 0x08
5355 #define _T5GCON_GSPM 0x10
5356 #define _T5GCON_T5GSPM 0x10
5357 #define _T5GCON_GTM 0x20
5358 #define _T5GCON_T5GTM 0x20
5359 #define _T5GCON_GPOL 0x40
5360 #define _T5GCON_T5GPOL 0x40
5361 #define _T5GCON_GE 0x80
5362 #define _T5GCON_T5GE 0x80
5363 #define _T5GCON_TMR5GE 0x80
5365 //==============================================================================
5367 extern __at(0x050F) __sfr OPA1NCHS
;
5368 extern __at(0x0510) __sfr OPA1PCHS
;
5370 //==============================================================================
5373 extern __at(0x0511) __sfr OPA1CON
;
5391 unsigned OPA1ORM0
: 1;
5392 unsigned OPA1ORM1
: 1;
5393 unsigned OPA1ORPOL
: 1;
5395 unsigned OPA1UG
: 1;
5398 unsigned OPA1EN
: 1;
5403 unsigned OPA1ORM
: 2;
5414 extern __at(0x0511) volatile __OPA1CONbits_t OPA1CONbits
;
5416 #define _OPA1CON_ORM0 0x01
5417 #define _OPA1CON_OPA1ORM0 0x01
5418 #define _OPA1CON_ORM1 0x02
5419 #define _OPA1CON_OPA1ORM1 0x02
5420 #define _OPA1CON_ORPOL 0x04
5421 #define _OPA1CON_OPA1ORPOL 0x04
5422 #define _OPA1CON_UG 0x10
5423 #define _OPA1CON_OPA1UG 0x10
5424 #define _OPA1CON_EN 0x80
5425 #define _OPA1CON_OPA1EN 0x80
5427 //==============================================================================
5429 extern __at(0x0512) __sfr OPA1ORS
;
5431 //==============================================================================
5434 extern __at(0x0590) __sfr DACLD
;
5438 unsigned DAC1LD
: 1;
5448 extern __at(0x0590) volatile __DACLDbits_t DACLDbits
;
5450 #define _DAC1LD 0x01
5452 //==============================================================================
5455 //==============================================================================
5458 extern __at(0x0591) __sfr DAC1CON0
;
5476 unsigned DACNSS0
: 1;
5478 unsigned DACPSS0
: 1;
5479 unsigned DACPSS1
: 1;
5488 unsigned DAC1NSS0
: 1;
5490 unsigned DAC1PSS0
: 1;
5491 unsigned DAC1PSS1
: 1;
5493 unsigned DACOE1
: 1;
5494 unsigned DAC1FM
: 1;
5495 unsigned DAC1EN
: 1;
5517 unsigned DAC1OE1
: 1;
5525 unsigned DAC1PSS
: 2;
5532 unsigned DACPSS
: 2;
5544 extern __at(0x0591) volatile __DAC1CON0bits_t DAC1CON0bits
;
5546 #define _DAC1CON0_NSS0 0x01
5547 #define _DAC1CON0_DACNSS0 0x01
5548 #define _DAC1CON0_DAC1NSS0 0x01
5549 #define _DAC1CON0_PSS0 0x04
5550 #define _DAC1CON0_DACPSS0 0x04
5551 #define _DAC1CON0_DAC1PSS0 0x04
5552 #define _DAC1CON0_PSS1 0x08
5553 #define _DAC1CON0_DACPSS1 0x08
5554 #define _DAC1CON0_DAC1PSS1 0x08
5555 #define _DAC1CON0_OE1 0x20
5556 #define _DAC1CON0_OE 0x20
5557 #define _DAC1CON0_DACOE1 0x20
5558 #define _DAC1CON0_DACOE 0x20
5559 #define _DAC1CON0_DAC1OE1 0x20
5560 #define _DAC1CON0_FM 0x40
5561 #define _DAC1CON0_DACFM 0x40
5562 #define _DAC1CON0_DAC1FM 0x40
5563 #define _DAC1CON0_EN 0x80
5564 #define _DAC1CON0_DACEN 0x80
5565 #define _DAC1CON0_DAC1EN 0x80
5567 //==============================================================================
5570 //==============================================================================
5573 extern __at(0x0592) __sfr DAC1CON1
;
5591 unsigned DAC1REF0
: 1;
5592 unsigned DAC1REF1
: 1;
5593 unsigned DAC1REF2
: 1;
5594 unsigned DAC1REF3
: 1;
5595 unsigned DAC1REF4
: 1;
5596 unsigned DAC1REF5
: 1;
5597 unsigned DAC1REF6
: 1;
5598 unsigned DAC1REF7
: 1;
5615 unsigned DAC1R0
: 1;
5616 unsigned DAC1R1
: 1;
5617 unsigned DAC1R2
: 1;
5618 unsigned DAC1R3
: 1;
5619 unsigned DAC1R4
: 1;
5620 unsigned DAC1R5
: 1;
5621 unsigned DAC1R6
: 1;
5622 unsigned DAC1R7
: 1;
5626 extern __at(0x0592) volatile __DAC1CON1bits_t DAC1CON1bits
;
5629 #define _DAC1REF0 0x01
5631 #define _DAC1R0 0x01
5633 #define _DAC1REF1 0x02
5635 #define _DAC1R1 0x02
5637 #define _DAC1REF2 0x04
5639 #define _DAC1R2 0x04
5641 #define _DAC1REF3 0x08
5643 #define _DAC1R3 0x08
5645 #define _DAC1REF4 0x10
5647 #define _DAC1R4 0x10
5649 #define _DAC1REF5 0x20
5651 #define _DAC1R5 0x20
5653 #define _DAC1REF6 0x40
5655 #define _DAC1R6 0x40
5657 #define _DAC1REF7 0x80
5659 #define _DAC1R7 0x80
5661 //==============================================================================
5663 extern __at(0x0592) __sfr DAC1REF
;
5665 //==============================================================================
5668 extern __at(0x0592) __sfr DAC1REFL
;
5686 unsigned DAC1REF0
: 1;
5687 unsigned DAC1REF1
: 1;
5688 unsigned DAC1REF2
: 1;
5689 unsigned DAC1REF3
: 1;
5690 unsigned DAC1REF4
: 1;
5691 unsigned DAC1REF5
: 1;
5692 unsigned DAC1REF6
: 1;
5693 unsigned DAC1REF7
: 1;
5710 unsigned DAC1R0
: 1;
5711 unsigned DAC1R1
: 1;
5712 unsigned DAC1R2
: 1;
5713 unsigned DAC1R3
: 1;
5714 unsigned DAC1R4
: 1;
5715 unsigned DAC1R5
: 1;
5716 unsigned DAC1R6
: 1;
5717 unsigned DAC1R7
: 1;
5721 extern __at(0x0592) volatile __DAC1REFLbits_t DAC1REFLbits
;
5723 #define _DAC1REFL_REF0 0x01
5724 #define _DAC1REFL_DAC1REF0 0x01
5725 #define _DAC1REFL_R0 0x01
5726 #define _DAC1REFL_DAC1R0 0x01
5727 #define _DAC1REFL_REF1 0x02
5728 #define _DAC1REFL_DAC1REF1 0x02
5729 #define _DAC1REFL_R1 0x02
5730 #define _DAC1REFL_DAC1R1 0x02
5731 #define _DAC1REFL_REF2 0x04
5732 #define _DAC1REFL_DAC1REF2 0x04
5733 #define _DAC1REFL_R2 0x04
5734 #define _DAC1REFL_DAC1R2 0x04
5735 #define _DAC1REFL_REF3 0x08
5736 #define _DAC1REFL_DAC1REF3 0x08
5737 #define _DAC1REFL_R3 0x08
5738 #define _DAC1REFL_DAC1R3 0x08
5739 #define _DAC1REFL_REF4 0x10
5740 #define _DAC1REFL_DAC1REF4 0x10
5741 #define _DAC1REFL_R4 0x10
5742 #define _DAC1REFL_DAC1R4 0x10
5743 #define _DAC1REFL_REF5 0x20
5744 #define _DAC1REFL_DAC1REF5 0x20
5745 #define _DAC1REFL_R5 0x20
5746 #define _DAC1REFL_DAC1R5 0x20
5747 #define _DAC1REFL_REF6 0x40
5748 #define _DAC1REFL_DAC1REF6 0x40
5749 #define _DAC1REFL_R6 0x40
5750 #define _DAC1REFL_DAC1R6 0x40
5751 #define _DAC1REFL_REF7 0x80
5752 #define _DAC1REFL_DAC1REF7 0x80
5753 #define _DAC1REFL_R7 0x80
5754 #define _DAC1REFL_DAC1R7 0x80
5756 //==============================================================================
5759 //==============================================================================
5762 extern __at(0x0593) __sfr DAC1CON2
;
5780 unsigned DAC1REF8
: 1;
5781 unsigned DAC1REF9
: 1;
5782 unsigned DAC1REF10
: 1;
5783 unsigned DAC1REF11
: 1;
5784 unsigned DAC1REF12
: 1;
5785 unsigned DAC1REF13
: 1;
5786 unsigned DAC1REF14
: 1;
5787 unsigned DAC1REF15
: 1;
5804 unsigned DAC1R8
: 1;
5805 unsigned DAC1R9
: 1;
5806 unsigned DAC1R10
: 1;
5807 unsigned DAC1R11
: 1;
5808 unsigned DAC1R12
: 1;
5809 unsigned DAC1R13
: 1;
5810 unsigned DAC1R14
: 1;
5811 unsigned DAC1R15
: 1;
5815 extern __at(0x0593) volatile __DAC1CON2bits_t DAC1CON2bits
;
5818 #define _DAC1REF8 0x01
5820 #define _DAC1R8 0x01
5822 #define _DAC1REF9 0x02
5824 #define _DAC1R9 0x02
5826 #define _DAC1REF10 0x04
5828 #define _DAC1R10 0x04
5830 #define _DAC1REF11 0x08
5832 #define _DAC1R11 0x08
5834 #define _DAC1REF12 0x10
5836 #define _DAC1R12 0x10
5838 #define _DAC1REF13 0x20
5840 #define _DAC1R13 0x20
5842 #define _DAC1REF14 0x40
5844 #define _DAC1R14 0x40
5846 #define _DAC1REF15 0x80
5848 #define _DAC1R15 0x80
5850 //==============================================================================
5853 //==============================================================================
5856 extern __at(0x0593) __sfr DAC1REFH
;
5874 unsigned DAC1REF8
: 1;
5875 unsigned DAC1REF9
: 1;
5876 unsigned DAC1REF10
: 1;
5877 unsigned DAC1REF11
: 1;
5878 unsigned DAC1REF12
: 1;
5879 unsigned DAC1REF13
: 1;
5880 unsigned DAC1REF14
: 1;
5881 unsigned DAC1REF15
: 1;
5898 unsigned DAC1R8
: 1;
5899 unsigned DAC1R9
: 1;
5900 unsigned DAC1R10
: 1;
5901 unsigned DAC1R11
: 1;
5902 unsigned DAC1R12
: 1;
5903 unsigned DAC1R13
: 1;
5904 unsigned DAC1R14
: 1;
5905 unsigned DAC1R15
: 1;
5909 extern __at(0x0593) volatile __DAC1REFHbits_t DAC1REFHbits
;
5911 #define _DAC1REFH_REF8 0x01
5912 #define _DAC1REFH_DAC1REF8 0x01
5913 #define _DAC1REFH_R8 0x01
5914 #define _DAC1REFH_DAC1R8 0x01
5915 #define _DAC1REFH_REF9 0x02
5916 #define _DAC1REFH_DAC1REF9 0x02
5917 #define _DAC1REFH_R9 0x02
5918 #define _DAC1REFH_DAC1R9 0x02
5919 #define _DAC1REFH_REF10 0x04
5920 #define _DAC1REFH_DAC1REF10 0x04
5921 #define _DAC1REFH_R10 0x04
5922 #define _DAC1REFH_DAC1R10 0x04
5923 #define _DAC1REFH_REF11 0x08
5924 #define _DAC1REFH_DAC1REF11 0x08
5925 #define _DAC1REFH_R11 0x08
5926 #define _DAC1REFH_DAC1R11 0x08
5927 #define _DAC1REFH_REF12 0x10
5928 #define _DAC1REFH_DAC1REF12 0x10
5929 #define _DAC1REFH_R12 0x10
5930 #define _DAC1REFH_DAC1R12 0x10
5931 #define _DAC1REFH_REF13 0x20
5932 #define _DAC1REFH_DAC1REF13 0x20
5933 #define _DAC1REFH_R13 0x20
5934 #define _DAC1REFH_DAC1R13 0x20
5935 #define _DAC1REFH_REF14 0x40
5936 #define _DAC1REFH_DAC1REF14 0x40
5937 #define _DAC1REFH_R14 0x40
5938 #define _DAC1REFH_DAC1R14 0x40
5939 #define _DAC1REFH_REF15 0x80
5940 #define _DAC1REFH_DAC1REF15 0x80
5941 #define _DAC1REFH_R15 0x80
5942 #define _DAC1REFH_DAC1R15 0x80
5944 //==============================================================================
5947 //==============================================================================
5950 extern __at(0x0597) __sfr DAC3CON0
;
5968 unsigned DACNSS
: 1;
5970 unsigned DACPSS0
: 1;
5971 unsigned DACPSS1
: 1;
5973 unsigned DACOE1
: 1;
5980 unsigned DAC3NSS
: 1;
5982 unsigned DAC3PSS0
: 1;
5983 unsigned DAC3PSS1
: 1;
5985 unsigned DAC3OE1
: 1;
5987 unsigned DAC3EN
: 1;
6000 unsigned DACPSS
: 2;
6007 unsigned DAC3PSS
: 2;
6012 extern __at(0x0597) volatile __DAC3CON0bits_t DAC3CON0bits
;
6014 #define _DAC3CON0_NSS 0x01
6015 #define _DAC3CON0_DACNSS 0x01
6016 #define _DAC3CON0_DAC3NSS 0x01
6017 #define _DAC3CON0_PSS0 0x04
6018 #define _DAC3CON0_DACPSS0 0x04
6019 #define _DAC3CON0_DAC3PSS0 0x04
6020 #define _DAC3CON0_PSS1 0x08
6021 #define _DAC3CON0_DACPSS1 0x08
6022 #define _DAC3CON0_DAC3PSS1 0x08
6023 #define _DAC3CON0_OE1 0x20
6024 #define _DAC3CON0_DACOE1 0x20
6025 #define _DAC3CON0_DAC3OE1 0x20
6026 #define _DAC3CON0_EN 0x80
6027 #define _DAC3CON0_DACEN 0x80
6028 #define _DAC3CON0_DAC3EN 0x80
6030 //==============================================================================
6033 //==============================================================================
6036 extern __at(0x0598) __sfr DAC3CON1
;
6059 unsigned DAC3REF5
: 1;
6066 unsigned DAC3R0
: 1;
6067 unsigned DAC3R1
: 1;
6068 unsigned DAC3R2
: 1;
6069 unsigned DAC3R3
: 1;
6070 unsigned DAC3R4
: 1;
6090 unsigned DAC3REF0
: 1;
6091 unsigned DAC3REF1
: 1;
6092 unsigned DAC3REF2
: 1;
6093 unsigned DAC3REF3
: 1;
6094 unsigned DAC3REF4
: 1;
6126 unsigned DAC3REF
: 6;
6131 extern __at(0x0598) volatile __DAC3CON1bits_t DAC3CON1bits
;
6133 #define _DAC3CON1_DACR0 0x01
6134 #define _DAC3CON1_R0 0x01
6135 #define _DAC3CON1_DAC3R0 0x01
6136 #define _DAC3CON1_REF0 0x01
6137 #define _DAC3CON1_DAC3REF0 0x01
6138 #define _DAC3CON1_DACR1 0x02
6139 #define _DAC3CON1_R1 0x02
6140 #define _DAC3CON1_DAC3R1 0x02
6141 #define _DAC3CON1_REF1 0x02
6142 #define _DAC3CON1_DAC3REF1 0x02
6143 #define _DAC3CON1_DACR2 0x04
6144 #define _DAC3CON1_R2 0x04
6145 #define _DAC3CON1_DAC3R2 0x04
6146 #define _DAC3CON1_REF2 0x04
6147 #define _DAC3CON1_DAC3REF2 0x04
6148 #define _DAC3CON1_DACR3 0x08
6149 #define _DAC3CON1_R3 0x08
6150 #define _DAC3CON1_DAC3R3 0x08
6151 #define _DAC3CON1_REF3 0x08
6152 #define _DAC3CON1_DAC3REF3 0x08
6153 #define _DAC3CON1_DACR4 0x10
6154 #define _DAC3CON1_R4 0x10
6155 #define _DAC3CON1_DAC3R4 0x10
6156 #define _DAC3CON1_REF4 0x10
6157 #define _DAC3CON1_DAC3REF4 0x10
6158 #define _DAC3CON1_REF5 0x20
6159 #define _DAC3CON1_DAC3REF5 0x20
6161 //==============================================================================
6164 //==============================================================================
6167 extern __at(0x0598) __sfr DAC3REF
;
6190 unsigned DAC3REF5
: 1;
6197 unsigned DAC3R0
: 1;
6198 unsigned DAC3R1
: 1;
6199 unsigned DAC3R2
: 1;
6200 unsigned DAC3R3
: 1;
6201 unsigned DAC3R4
: 1;
6221 unsigned DAC3REF0
: 1;
6222 unsigned DAC3REF1
: 1;
6223 unsigned DAC3REF2
: 1;
6224 unsigned DAC3REF3
: 1;
6225 unsigned DAC3REF4
: 1;
6251 unsigned DAC3REF
: 6;
6262 extern __at(0x0598) volatile __DAC3REFbits_t DAC3REFbits
;
6264 #define _DAC3REF_DACR0 0x01
6265 #define _DAC3REF_R0 0x01
6266 #define _DAC3REF_DAC3R0 0x01
6267 #define _DAC3REF_REF0 0x01
6268 #define _DAC3REF_DAC3REF0 0x01
6269 #define _DAC3REF_DACR1 0x02
6270 #define _DAC3REF_R1 0x02
6271 #define _DAC3REF_DAC3R1 0x02
6272 #define _DAC3REF_REF1 0x02
6273 #define _DAC3REF_DAC3REF1 0x02
6274 #define _DAC3REF_DACR2 0x04
6275 #define _DAC3REF_R2 0x04
6276 #define _DAC3REF_DAC3R2 0x04
6277 #define _DAC3REF_REF2 0x04
6278 #define _DAC3REF_DAC3REF2 0x04
6279 #define _DAC3REF_DACR3 0x08
6280 #define _DAC3REF_R3 0x08
6281 #define _DAC3REF_DAC3R3 0x08
6282 #define _DAC3REF_REF3 0x08
6283 #define _DAC3REF_DAC3REF3 0x08
6284 #define _DAC3REF_DACR4 0x10
6285 #define _DAC3REF_R4 0x10
6286 #define _DAC3REF_DAC3R4 0x10
6287 #define _DAC3REF_REF4 0x10
6288 #define _DAC3REF_DAC3REF4 0x10
6289 #define _DAC3REF_REF5 0x20
6290 #define _DAC3REF_DAC3REF5 0x20
6292 //==============================================================================
6295 //==============================================================================
6298 extern __at(0x0617) __sfr PWM3DCL
;
6322 unsigned PWM3DC0
: 1;
6323 unsigned PWM3DC1
: 1;
6334 unsigned PWMPW0
: 1;
6335 unsigned PWMPW1
: 1;
6347 unsigned PWM3DC
: 2;
6357 extern __at(0x0617) volatile __PWM3DCLbits_t PWM3DCLbits
;
6360 #define _PWM3DC0 0x40
6361 #define _PWMPW0 0x40
6363 #define _PWM3DC1 0x80
6364 #define _PWMPW1 0x80
6366 //==============================================================================
6369 //==============================================================================
6372 extern __at(0x0618) __sfr PWM3DCH
;
6390 unsigned PWM3DC2
: 1;
6391 unsigned PWM3DC3
: 1;
6392 unsigned PWM3DC4
: 1;
6393 unsigned PWM3DC5
: 1;
6394 unsigned PWM3DC6
: 1;
6395 unsigned PWM3DC7
: 1;
6396 unsigned PWM3DC8
: 1;
6397 unsigned PWM3DC9
: 1;
6402 unsigned PWMPW2
: 1;
6403 unsigned PWMPW3
: 1;
6404 unsigned PWMPW4
: 1;
6405 unsigned PWMPW5
: 1;
6406 unsigned PWMPW6
: 1;
6407 unsigned PWMPW7
: 1;
6408 unsigned PWMPW8
: 1;
6409 unsigned PWMPW9
: 1;
6413 extern __at(0x0618) volatile __PWM3DCHbits_t PWM3DCHbits
;
6416 #define _PWM3DC2 0x01
6417 #define _PWMPW2 0x01
6419 #define _PWM3DC3 0x02
6420 #define _PWMPW3 0x02
6422 #define _PWM3DC4 0x04
6423 #define _PWMPW4 0x04
6425 #define _PWM3DC5 0x08
6426 #define _PWMPW5 0x08
6428 #define _PWM3DC6 0x10
6429 #define _PWMPW6 0x10
6431 #define _PWM3DC7 0x20
6432 #define _PWMPW7 0x20
6434 #define _PWM3DC8 0x40
6435 #define _PWMPW8 0x40
6437 #define _PWM3DC9 0x80
6438 #define _PWMPW9 0x80
6440 //==============================================================================
6443 //==============================================================================
6446 extern __at(0x0619) __sfr PWM3CON
;
6468 unsigned PWM3POL
: 1;
6469 unsigned PWM3OUT
: 1;
6471 unsigned PWM3EN
: 1;
6475 extern __at(0x0619) volatile __PWM3CONbits_t PWM3CONbits
;
6477 #define _PWM3CON_POL 0x10
6478 #define _PWM3CON_PWM3POL 0x10
6479 #define _PWM3CON_OUT 0x20
6480 #define _PWM3CON_PWM3OUT 0x20
6481 #define _PWM3CON_EN 0x80
6482 #define _PWM3CON_PWM3EN 0x80
6484 //==============================================================================
6487 //==============================================================================
6490 extern __at(0x068D) __sfr COG1PHR
;
6508 unsigned G1PHR0
: 1;
6509 unsigned G1PHR1
: 1;
6510 unsigned G1PHR2
: 1;
6511 unsigned G1PHR3
: 1;
6512 unsigned G1PHR4
: 1;
6513 unsigned G1PHR5
: 1;
6531 extern __at(0x068D) volatile __COG1PHRbits_t COG1PHRbits
;
6534 #define _G1PHR0 0x01
6536 #define _G1PHR1 0x02
6538 #define _G1PHR2 0x04
6540 #define _G1PHR3 0x08
6542 #define _G1PHR4 0x10
6544 #define _G1PHR5 0x20
6546 //==============================================================================
6549 //==============================================================================
6552 extern __at(0x068E) __sfr COG1PHF
;
6570 unsigned G1PHF0
: 1;
6571 unsigned G1PHF1
: 1;
6572 unsigned G1PHF2
: 1;
6573 unsigned G1PHF3
: 1;
6574 unsigned G1PHF4
: 1;
6575 unsigned G1PHF5
: 1;
6593 extern __at(0x068E) volatile __COG1PHFbits_t COG1PHFbits
;
6596 #define _G1PHF0 0x01
6598 #define _G1PHF1 0x02
6600 #define _G1PHF2 0x04
6602 #define _G1PHF3 0x08
6604 #define _G1PHF4 0x10
6606 #define _G1PHF5 0x20
6608 //==============================================================================
6611 //==============================================================================
6614 extern __at(0x068F) __sfr COG1BLKR
;
6632 unsigned G1BLKR0
: 1;
6633 unsigned G1BLKR1
: 1;
6634 unsigned G1BLKR2
: 1;
6635 unsigned G1BLKR3
: 1;
6636 unsigned G1BLKR4
: 1;
6637 unsigned G1BLKR5
: 1;
6650 unsigned G1BLKR
: 6;
6655 extern __at(0x068F) volatile __COG1BLKRbits_t COG1BLKRbits
;
6658 #define _G1BLKR0 0x01
6660 #define _G1BLKR1 0x02
6662 #define _G1BLKR2 0x04
6664 #define _G1BLKR3 0x08
6666 #define _G1BLKR4 0x10
6668 #define _G1BLKR5 0x20
6670 //==============================================================================
6673 //==============================================================================
6676 extern __at(0x0690) __sfr COG1BLKF
;
6694 unsigned G1BLKF0
: 1;
6695 unsigned G1BLKF1
: 1;
6696 unsigned G1BLKF2
: 1;
6697 unsigned G1BLKF3
: 1;
6698 unsigned G1BLKF4
: 1;
6699 unsigned G1BLKF5
: 1;
6712 unsigned G1BLKF
: 6;
6717 extern __at(0x0690) volatile __COG1BLKFbits_t COG1BLKFbits
;
6720 #define _G1BLKF0 0x01
6722 #define _G1BLKF1 0x02
6724 #define _G1BLKF2 0x04
6726 #define _G1BLKF3 0x08
6728 #define _G1BLKF4 0x10
6730 #define _G1BLKF5 0x20
6732 //==============================================================================
6735 //==============================================================================
6738 extern __at(0x0691) __sfr COG1DBR
;
6756 unsigned G1DBR0
: 1;
6757 unsigned G1DBR1
: 1;
6758 unsigned G1DBR2
: 1;
6759 unsigned G1DBR3
: 1;
6760 unsigned G1DBR4
: 1;
6761 unsigned G1DBR5
: 1;
6779 extern __at(0x0691) volatile __COG1DBRbits_t COG1DBRbits
;
6782 #define _G1DBR0 0x01
6784 #define _G1DBR1 0x02
6786 #define _G1DBR2 0x04
6788 #define _G1DBR3 0x08
6790 #define _G1DBR4 0x10
6792 #define _G1DBR5 0x20
6794 //==============================================================================
6797 //==============================================================================
6800 extern __at(0x0692) __sfr COG1DBF
;
6818 unsigned G1DBF0
: 1;
6819 unsigned G1DBF1
: 1;
6820 unsigned G1DBF2
: 1;
6821 unsigned G1DBF3
: 1;
6822 unsigned G1DBF4
: 1;
6823 unsigned G1DBF5
: 1;
6841 extern __at(0x0692) volatile __COG1DBFbits_t COG1DBFbits
;
6844 #define _G1DBF0 0x01
6846 #define _G1DBF1 0x02
6848 #define _G1DBF2 0x04
6850 #define _G1DBF3 0x08
6852 #define _G1DBF4 0x10
6854 #define _G1DBF5 0x20
6856 //==============================================================================
6859 //==============================================================================
6862 extern __at(0x0693) __sfr COG1CON0
;
6917 extern __at(0x0693) volatile __COG1CON0bits_t COG1CON0bits
;
6919 #define _COG1CON0_MD0 0x01
6920 #define _COG1CON0_G1MD0 0x01
6921 #define _COG1CON0_MD1 0x02
6922 #define _COG1CON0_G1MD1 0x02
6923 #define _COG1CON0_MD2 0x04
6924 #define _COG1CON0_G1MD2 0x04
6925 #define _COG1CON0_CS0 0x08
6926 #define _COG1CON0_G1CS0 0x08
6927 #define _COG1CON0_CS1 0x10
6928 #define _COG1CON0_G1CS1 0x10
6929 #define _COG1CON0_LD 0x40
6930 #define _COG1CON0_G1LD 0x40
6931 #define _COG1CON0_EN 0x80
6932 #define _COG1CON0_G1EN 0x80
6934 //==============================================================================
6937 //==============================================================================
6940 extern __at(0x0694) __sfr COG1CON1
;
6958 unsigned G1POLA
: 1;
6959 unsigned G1POLB
: 1;
6960 unsigned G1POLC
: 1;
6961 unsigned G1POLD
: 1;
6964 unsigned G1FDBS
: 1;
6965 unsigned G1RDBS
: 1;
6969 extern __at(0x0694) volatile __COG1CON1bits_t COG1CON1bits
;
6972 #define _G1POLA 0x01
6974 #define _G1POLB 0x02
6976 #define _G1POLC 0x04
6978 #define _G1POLD 0x08
6980 #define _G1FDBS 0x40
6982 #define _G1RDBS 0x80
6984 //==============================================================================
6987 //==============================================================================
6990 extern __at(0x0695) __sfr COG1RIS0
;
7008 unsigned G1RIS0
: 1;
7009 unsigned G1RIS1
: 1;
7010 unsigned G1RIS2
: 1;
7011 unsigned G1RIS3
: 1;
7012 unsigned G1RIS4
: 1;
7013 unsigned G1RIS5
: 1;
7014 unsigned G1RIS6
: 1;
7015 unsigned G1RIS7
: 1;
7019 extern __at(0x0695) volatile __COG1RIS0bits_t COG1RIS0bits
;
7022 #define _G1RIS0 0x01
7024 #define _G1RIS1 0x02
7026 #define _G1RIS2 0x04
7028 #define _G1RIS3 0x08
7030 #define _G1RIS4 0x10
7032 #define _G1RIS5 0x20
7034 #define _G1RIS6 0x40
7036 #define _G1RIS7 0x80
7038 //==============================================================================
7041 //==============================================================================
7044 extern __at(0x0696) __sfr COG1RIS1
;
7062 unsigned G1RIS8
: 1;
7063 unsigned G1RIS9
: 1;
7064 unsigned G1RIS10
: 1;
7065 unsigned G1RIS11
: 1;
7066 unsigned G1RIS12
: 1;
7067 unsigned G1RIS13
: 1;
7068 unsigned G1RIS14
: 1;
7073 extern __at(0x0696) volatile __COG1RIS1bits_t COG1RIS1bits
;
7076 #define _G1RIS8 0x01
7078 #define _G1RIS9 0x02
7080 #define _G1RIS10 0x04
7082 #define _G1RIS11 0x08
7084 #define _G1RIS12 0x10
7086 #define _G1RIS13 0x20
7088 #define _G1RIS14 0x40
7090 //==============================================================================
7093 //==============================================================================
7096 extern __at(0x0697) __sfr COG1RSIM0
;
7114 unsigned G1RSIM0
: 1;
7115 unsigned G1RSIM1
: 1;
7116 unsigned G1RSIM2
: 1;
7117 unsigned G1RSIM3
: 1;
7118 unsigned G1RSIM4
: 1;
7119 unsigned G1RSIM5
: 1;
7120 unsigned G1RSIM6
: 1;
7121 unsigned G1RSIM7
: 1;
7123 } __COG1RSIM0bits_t
;
7125 extern __at(0x0697) volatile __COG1RSIM0bits_t COG1RSIM0bits
;
7128 #define _G1RSIM0 0x01
7130 #define _G1RSIM1 0x02
7132 #define _G1RSIM2 0x04
7134 #define _G1RSIM3 0x08
7136 #define _G1RSIM4 0x10
7138 #define _G1RSIM5 0x20
7140 #define _G1RSIM6 0x40
7142 #define _G1RSIM7 0x80
7144 //==============================================================================
7147 //==============================================================================
7150 extern __at(0x0698) __sfr COG1RSIM1
;
7158 unsigned RSIM10
: 1;
7159 unsigned RSIM11
: 1;
7160 unsigned RSIM12
: 1;
7161 unsigned RSIM13
: 1;
7162 unsigned RSIM14
: 1;
7168 unsigned G1RSIM8
: 1;
7169 unsigned G1RSIM9
: 1;
7170 unsigned G1RSIM10
: 1;
7171 unsigned G1RSIM11
: 1;
7172 unsigned G1RSIM12
: 1;
7173 unsigned G1RSIM13
: 1;
7174 unsigned G1RSIM14
: 1;
7177 } __COG1RSIM1bits_t
;
7179 extern __at(0x0698) volatile __COG1RSIM1bits_t COG1RSIM1bits
;
7182 #define _G1RSIM8 0x01
7184 #define _G1RSIM9 0x02
7185 #define _RSIM10 0x04
7186 #define _G1RSIM10 0x04
7187 #define _RSIM11 0x08
7188 #define _G1RSIM11 0x08
7189 #define _RSIM12 0x10
7190 #define _G1RSIM12 0x10
7191 #define _RSIM13 0x20
7192 #define _G1RSIM13 0x20
7193 #define _RSIM14 0x40
7194 #define _G1RSIM14 0x40
7196 //==============================================================================
7199 //==============================================================================
7202 extern __at(0x0699) __sfr COG1FIS0
;
7220 unsigned G1FIS0
: 1;
7221 unsigned G1FIS1
: 1;
7222 unsigned G1FIS2
: 1;
7223 unsigned G1FIS3
: 1;
7224 unsigned G1FIS4
: 1;
7225 unsigned G1FIS5
: 1;
7226 unsigned G1FIS6
: 1;
7227 unsigned G1FIS7
: 1;
7231 extern __at(0x0699) volatile __COG1FIS0bits_t COG1FIS0bits
;
7234 #define _G1FIS0 0x01
7236 #define _G1FIS1 0x02
7238 #define _G1FIS2 0x04
7240 #define _G1FIS3 0x08
7242 #define _G1FIS4 0x10
7244 #define _G1FIS5 0x20
7246 #define _G1FIS6 0x40
7248 #define _G1FIS7 0x80
7250 //==============================================================================
7253 //==============================================================================
7256 extern __at(0x069A) __sfr COG1FIS1
;
7274 unsigned G1FIS8
: 1;
7275 unsigned G1FIS9
: 1;
7276 unsigned G1FIS10
: 1;
7277 unsigned G1FIS11
: 1;
7278 unsigned G1FIS12
: 1;
7279 unsigned G1FIS13
: 1;
7280 unsigned G1FIS14
: 1;
7285 extern __at(0x069A) volatile __COG1FIS1bits_t COG1FIS1bits
;
7288 #define _G1FIS8 0x01
7290 #define _G1FIS9 0x02
7292 #define _G1FIS10 0x04
7294 #define _G1FIS11 0x08
7296 #define _G1FIS12 0x10
7298 #define _G1FIS13 0x20
7300 #define _G1FIS14 0x40
7302 //==============================================================================
7305 //==============================================================================
7308 extern __at(0x069B) __sfr COG1FSIM0
;
7326 unsigned G1FSIM0
: 1;
7327 unsigned G1FSIM1
: 1;
7328 unsigned G1FSIM2
: 1;
7329 unsigned G1FSIM3
: 1;
7330 unsigned G1FSIM4
: 1;
7331 unsigned G1FSIM5
: 1;
7332 unsigned G1FSIM6
: 1;
7333 unsigned G1FSIM7
: 1;
7335 } __COG1FSIM0bits_t
;
7337 extern __at(0x069B) volatile __COG1FSIM0bits_t COG1FSIM0bits
;
7340 #define _G1FSIM0 0x01
7342 #define _G1FSIM1 0x02
7344 #define _G1FSIM2 0x04
7346 #define _G1FSIM3 0x08
7348 #define _G1FSIM4 0x10
7350 #define _G1FSIM5 0x20
7352 #define _G1FSIM6 0x40
7354 #define _G1FSIM7 0x80
7356 //==============================================================================
7359 //==============================================================================
7362 extern __at(0x069C) __sfr COG1FSIM1
;
7370 unsigned FSIM10
: 1;
7371 unsigned FSIM11
: 1;
7372 unsigned FSIM12
: 1;
7373 unsigned FSIM13
: 1;
7374 unsigned FSIM14
: 1;
7380 unsigned G1FSIM8
: 1;
7381 unsigned G1FSIM9
: 1;
7382 unsigned G1FSIM10
: 1;
7383 unsigned G1FSIM11
: 1;
7384 unsigned G1FSIM12
: 1;
7385 unsigned G1FSIM13
: 1;
7386 unsigned G1FSIM14
: 1;
7389 } __COG1FSIM1bits_t
;
7391 extern __at(0x069C) volatile __COG1FSIM1bits_t COG1FSIM1bits
;
7394 #define _G1FSIM8 0x01
7396 #define _G1FSIM9 0x02
7397 #define _FSIM10 0x04
7398 #define _G1FSIM10 0x04
7399 #define _FSIM11 0x08
7400 #define _G1FSIM11 0x08
7401 #define _FSIM12 0x10
7402 #define _G1FSIM12 0x10
7403 #define _FSIM13 0x20
7404 #define _G1FSIM13 0x20
7405 #define _FSIM14 0x40
7406 #define _G1FSIM14 0x40
7408 //==============================================================================
7411 //==============================================================================
7414 extern __at(0x069D) __sfr COG1ASD0
;
7422 unsigned ASDAC0
: 1;
7423 unsigned ASDAC1
: 1;
7424 unsigned ASDBD0
: 1;
7425 unsigned ASDBD1
: 1;
7434 unsigned G1ASDAC0
: 1;
7435 unsigned G1ASDAC1
: 1;
7436 unsigned G1ASDBD0
: 1;
7437 unsigned G1ASDBD1
: 1;
7450 unsigned G1ARSEN
: 1;
7462 unsigned G1ASREN
: 1;
7469 unsigned G1ASDAC
: 2;
7490 unsigned G1ASDBD
: 2;
7495 extern __at(0x069D) volatile __COG1ASD0bits_t COG1ASD0bits
;
7497 #define _ASDAC0 0x04
7498 #define _G1ASDAC0 0x04
7499 #define _ASDAC1 0x08
7500 #define _G1ASDAC1 0x08
7501 #define _ASDBD0 0x10
7502 #define _G1ASDBD0 0x10
7503 #define _ASDBD1 0x20
7504 #define _G1ASDBD1 0x20
7507 #define _G1ARSEN 0x40
7508 #define _G1ASREN 0x40
7512 //==============================================================================
7515 //==============================================================================
7518 extern __at(0x069E) __sfr COG1ASD1
;
7536 unsigned G1AS0E
: 1;
7537 unsigned G1AS1E
: 1;
7538 unsigned G1AS2E
: 1;
7539 unsigned G1AS3E
: 1;
7540 unsigned G1AS4E
: 1;
7541 unsigned G1AS5E
: 1;
7542 unsigned G1AS6E
: 1;
7543 unsigned G1AS7E
: 1;
7547 extern __at(0x069E) volatile __COG1ASD1bits_t COG1ASD1bits
;
7550 #define _G1AS0E 0x01
7552 #define _G1AS1E 0x02
7554 #define _G1AS2E 0x04
7556 #define _G1AS3E 0x08
7558 #define _G1AS4E 0x10
7560 #define _G1AS5E 0x20
7562 #define _G1AS6E 0x40
7564 #define _G1AS7E 0x80
7566 //==============================================================================
7569 //==============================================================================
7572 extern __at(0x069F) __sfr COG1STR
;
7590 unsigned G1STRA
: 1;
7591 unsigned G1STRB
: 1;
7592 unsigned G1STRC
: 1;
7593 unsigned G1STRD
: 1;
7594 unsigned G1SDATA
: 1;
7595 unsigned G1SDATB
: 1;
7596 unsigned G1SDATC
: 1;
7597 unsigned G1SDATD
: 1;
7601 extern __at(0x069F) volatile __COG1STRbits_t COG1STRbits
;
7604 #define _G1STRA 0x01
7606 #define _G1STRB 0x02
7608 #define _G1STRC 0x04
7610 #define _G1STRD 0x08
7612 #define _G1SDATA 0x10
7614 #define _G1SDATB 0x20
7616 #define _G1SDATC 0x40
7618 #define _G1SDATD 0x80
7620 //==============================================================================
7623 //==============================================================================
7626 extern __at(0x0794) __sfr PRG1RTSS
;
7644 unsigned RG1RTSS0
: 1;
7645 unsigned RG1RTSS1
: 1;
7646 unsigned RG1RTSS2
: 1;
7647 unsigned RG1RTSS3
: 1;
7656 unsigned RG1RTSS
: 4;
7667 extern __at(0x0794) volatile __PRG1RTSSbits_t PRG1RTSSbits
;
7670 #define _RG1RTSS0 0x01
7672 #define _RG1RTSS1 0x02
7674 #define _RG1RTSS2 0x04
7676 #define _RG1RTSS3 0x08
7678 //==============================================================================
7681 //==============================================================================
7684 extern __at(0x0795) __sfr PRG1FTSS
;
7702 unsigned RG1FTSS0
: 1;
7703 unsigned RG1FTSS1
: 1;
7704 unsigned RG1FTSS2
: 1;
7705 unsigned RG1FTSS3
: 1;
7720 unsigned RG1FTSS
: 4;
7725 extern __at(0x0795) volatile __PRG1FTSSbits_t PRG1FTSSbits
;
7728 #define _RG1FTSS0 0x01
7730 #define _RG1FTSS1 0x02
7732 #define _RG1FTSS2 0x04
7734 #define _RG1FTSS3 0x08
7736 //==============================================================================
7739 //==============================================================================
7742 extern __at(0x0796) __sfr PRG1INS
;
7760 unsigned RG1INS0
: 1;
7761 unsigned RG1INS1
: 1;
7762 unsigned RG1INS2
: 1;
7763 unsigned RG1INS3
: 1;
7778 unsigned RG1INS
: 4;
7783 extern __at(0x0796) volatile __PRG1INSbits_t PRG1INSbits
;
7786 #define _RG1INS0 0x01
7788 #define _RG1INS1 0x02
7790 #define _RG1INS2 0x04
7792 #define _RG1INS3 0x08
7794 //==============================================================================
7797 //==============================================================================
7800 extern __at(0x0797) __sfr PRG1CON0
;
7820 unsigned RG1MODE0
: 1;
7821 unsigned RG1MODE1
: 1;
7822 unsigned RG1REDG
: 1;
7823 unsigned RG1FEDG
: 1;
7831 unsigned RG1MODE
: 2;
7843 extern __at(0x0797) volatile __PRG1CON0bits_t PRG1CON0bits
;
7845 #define _PRG1CON0_GO 0x01
7846 #define _PRG1CON0_RG1GO 0x01
7847 #define _PRG1CON0_OS 0x02
7848 #define _PRG1CON0_RG1OS 0x02
7849 #define _PRG1CON0_MODE0 0x04
7850 #define _PRG1CON0_RG1MODE0 0x04
7851 #define _PRG1CON0_MODE1 0x08
7852 #define _PRG1CON0_RG1MODE1 0x08
7853 #define _PRG1CON0_REDG 0x10
7854 #define _PRG1CON0_RG1REDG 0x10
7855 #define _PRG1CON0_FEDG 0x20
7856 #define _PRG1CON0_RG1FEDG 0x20
7857 #define _PRG1CON0_EN 0x80
7858 #define _PRG1CON0_RG1EN 0x80
7860 //==============================================================================
7863 //==============================================================================
7866 extern __at(0x0798) __sfr PRG1CON1
;
7884 unsigned RG1RPOL
: 1;
7885 unsigned RG1FPOL
: 1;
7886 unsigned RG1RDY
: 1;
7895 extern __at(0x0798) volatile __PRG1CON1bits_t PRG1CON1bits
;
7898 #define _RG1RPOL 0x01
7900 #define _RG1FPOL 0x02
7902 #define _RG1RDY 0x04
7904 //==============================================================================
7907 //==============================================================================
7910 extern __at(0x0799) __sfr PRG1CON2
;
7928 unsigned RG1ISET0
: 1;
7929 unsigned RG1ISET1
: 1;
7930 unsigned RG1ISET2
: 1;
7931 unsigned RG1ISET3
: 1;
7932 unsigned RG1ISET4
: 1;
7946 unsigned RG1ISET
: 5;
7951 extern __at(0x0799) volatile __PRG1CON2bits_t PRG1CON2bits
;
7954 #define _RG1ISET0 0x01
7956 #define _RG1ISET1 0x02
7958 #define _RG1ISET2 0x04
7960 #define _RG1ISET3 0x08
7962 #define _RG1ISET4 0x10
7964 //==============================================================================
7967 //==============================================================================
7970 extern __at(0x0D8E) __sfr PWMEN
;
7978 unsigned MPWM5EN
: 1;
7984 extern __at(0x0D8E) volatile __PWMENbits_t PWMENbits
;
7986 #define _MPWM5EN 0x10
7988 //==============================================================================
7991 //==============================================================================
7994 extern __at(0x0D8F) __sfr PWMLD
;
8002 unsigned MPWM5LD
: 1;
8008 extern __at(0x0D8F) volatile __PWMLDbits_t PWMLDbits
;
8010 #define _MPWM5LD 0x10
8012 //==============================================================================
8015 //==============================================================================
8018 extern __at(0x0D90) __sfr PWMOUT
;
8026 unsigned MPWM5OUT
: 1;
8032 extern __at(0x0D90) volatile __PWMOUTbits_t PWMOUTbits
;
8034 #define _MPWM5OUT 0x10
8036 //==============================================================================
8038 extern __at(0x0D91) __sfr PWM5PH
;
8040 //==============================================================================
8043 extern __at(0x0D91) __sfr PWM5PHL
;
8047 unsigned PWM5PHL0
: 1;
8048 unsigned PWM5PHL1
: 1;
8049 unsigned PWM5PHL2
: 1;
8050 unsigned PWM5PHL3
: 1;
8051 unsigned PWM5PHL4
: 1;
8052 unsigned PWM5PHL5
: 1;
8053 unsigned PWM5PHL6
: 1;
8054 unsigned PWM5PHL7
: 1;
8057 extern __at(0x0D91) volatile __PWM5PHLbits_t PWM5PHLbits
;
8059 #define _PWM5PHL0 0x01
8060 #define _PWM5PHL1 0x02
8061 #define _PWM5PHL2 0x04
8062 #define _PWM5PHL3 0x08
8063 #define _PWM5PHL4 0x10
8064 #define _PWM5PHL5 0x20
8065 #define _PWM5PHL6 0x40
8066 #define _PWM5PHL7 0x80
8068 //==============================================================================
8071 //==============================================================================
8074 extern __at(0x0D92) __sfr PWM5PHH
;
8078 unsigned PWM5PHH0
: 1;
8079 unsigned PWM5PHH1
: 1;
8080 unsigned PWM5PHH2
: 1;
8081 unsigned PWM5PHH3
: 1;
8082 unsigned PWM5PHH4
: 1;
8083 unsigned PWM5PHH5
: 1;
8084 unsigned PWM5PHH6
: 1;
8085 unsigned PWM5PHH7
: 1;
8088 extern __at(0x0D92) volatile __PWM5PHHbits_t PWM5PHHbits
;
8090 #define _PWM5PHH0 0x01
8091 #define _PWM5PHH1 0x02
8092 #define _PWM5PHH2 0x04
8093 #define _PWM5PHH3 0x08
8094 #define _PWM5PHH4 0x10
8095 #define _PWM5PHH5 0x20
8096 #define _PWM5PHH6 0x40
8097 #define _PWM5PHH7 0x80
8099 //==============================================================================
8101 extern __at(0x0D93) __sfr PWM5DC
;
8103 //==============================================================================
8106 extern __at(0x0D93) __sfr PWM5DCL
;
8110 unsigned PWM5DCL0
: 1;
8111 unsigned PWM5DCL1
: 1;
8112 unsigned PWM5DCL2
: 1;
8113 unsigned PWM5DCL3
: 1;
8114 unsigned PWM5DCL4
: 1;
8115 unsigned PWM5DCL5
: 1;
8116 unsigned PWM5DCL6
: 1;
8117 unsigned PWM5DCL7
: 1;
8120 extern __at(0x0D93) volatile __PWM5DCLbits_t PWM5DCLbits
;
8122 #define _PWM5DCL0 0x01
8123 #define _PWM5DCL1 0x02
8124 #define _PWM5DCL2 0x04
8125 #define _PWM5DCL3 0x08
8126 #define _PWM5DCL4 0x10
8127 #define _PWM5DCL5 0x20
8128 #define _PWM5DCL6 0x40
8129 #define _PWM5DCL7 0x80
8131 //==============================================================================
8134 //==============================================================================
8137 extern __at(0x0D94) __sfr PWM5DCH
;
8141 unsigned PWM5DCH0
: 1;
8142 unsigned PWM5DCH1
: 1;
8143 unsigned PWM5DCH2
: 1;
8144 unsigned PWM5DCH3
: 1;
8145 unsigned PWM5DCH4
: 1;
8146 unsigned PWM5DCH5
: 1;
8147 unsigned PWM5DCH6
: 1;
8148 unsigned PWM5DCH7
: 1;
8151 extern __at(0x0D94) volatile __PWM5DCHbits_t PWM5DCHbits
;
8153 #define _PWM5DCH0 0x01
8154 #define _PWM5DCH1 0x02
8155 #define _PWM5DCH2 0x04
8156 #define _PWM5DCH3 0x08
8157 #define _PWM5DCH4 0x10
8158 #define _PWM5DCH5 0x20
8159 #define _PWM5DCH6 0x40
8160 #define _PWM5DCH7 0x80
8162 //==============================================================================
8164 extern __at(0x0D95) __sfr PWM5PR
;
8166 //==============================================================================
8169 extern __at(0x0D95) __sfr PWM5PRL
;
8173 unsigned PWM5PRL0
: 1;
8174 unsigned PWM5PRL1
: 1;
8175 unsigned PWM5PRL2
: 1;
8176 unsigned PWM5PRL3
: 1;
8177 unsigned PWM5PRL4
: 1;
8178 unsigned PWM5PRL5
: 1;
8179 unsigned PWM5PRL6
: 1;
8180 unsigned PWM5PRL7
: 1;
8183 extern __at(0x0D95) volatile __PWM5PRLbits_t PWM5PRLbits
;
8185 #define _PWM5PRL0 0x01
8186 #define _PWM5PRL1 0x02
8187 #define _PWM5PRL2 0x04
8188 #define _PWM5PRL3 0x08
8189 #define _PWM5PRL4 0x10
8190 #define _PWM5PRL5 0x20
8191 #define _PWM5PRL6 0x40
8192 #define _PWM5PRL7 0x80
8194 //==============================================================================
8197 //==============================================================================
8200 extern __at(0x0D96) __sfr PWM5PRH
;
8204 unsigned PWM5PRH0
: 1;
8205 unsigned PWM5PRH1
: 1;
8206 unsigned PWM5PRH2
: 1;
8207 unsigned PWM5PRH3
: 1;
8208 unsigned PWM5PRH4
: 1;
8209 unsigned PWM5PRH5
: 1;
8210 unsigned PWM5PRH6
: 1;
8211 unsigned PWM5PRH7
: 1;
8214 extern __at(0x0D96) volatile __PWM5PRHbits_t PWM5PRHbits
;
8216 #define _PWM5PRH0 0x01
8217 #define _PWM5PRH1 0x02
8218 #define _PWM5PRH2 0x04
8219 #define _PWM5PRH3 0x08
8220 #define _PWM5PRH4 0x10
8221 #define _PWM5PRH5 0x20
8222 #define _PWM5PRH6 0x40
8223 #define _PWM5PRH7 0x80
8225 //==============================================================================
8227 extern __at(0x0D97) __sfr PWM5OF
;
8229 //==============================================================================
8232 extern __at(0x0D97) __sfr PWM5OFL
;
8236 unsigned PWM5OFL0
: 1;
8237 unsigned PWM5OFL1
: 1;
8238 unsigned PWM5OFL2
: 1;
8239 unsigned PWM5OFL3
: 1;
8240 unsigned PWM5OFL4
: 1;
8241 unsigned PWM5OFL5
: 1;
8242 unsigned PWM5OFL6
: 1;
8243 unsigned PWM5OFL7
: 1;
8246 extern __at(0x0D97) volatile __PWM5OFLbits_t PWM5OFLbits
;
8248 #define _PWM5OFL0 0x01
8249 #define _PWM5OFL1 0x02
8250 #define _PWM5OFL2 0x04
8251 #define _PWM5OFL3 0x08
8252 #define _PWM5OFL4 0x10
8253 #define _PWM5OFL5 0x20
8254 #define _PWM5OFL6 0x40
8255 #define _PWM5OFL7 0x80
8257 //==============================================================================
8260 //==============================================================================
8263 extern __at(0x0D98) __sfr PWM5OFH
;
8267 unsigned PWM5OFH0
: 1;
8268 unsigned PWM5OFH1
: 1;
8269 unsigned PWM5OFH2
: 1;
8270 unsigned PWM5OFH3
: 1;
8271 unsigned PWM5OFH4
: 1;
8272 unsigned PWM5OFH5
: 1;
8273 unsigned PWM5OFH6
: 1;
8274 unsigned PWM5OFH7
: 1;
8277 extern __at(0x0D98) volatile __PWM5OFHbits_t PWM5OFHbits
;
8279 #define _PWM5OFH0 0x01
8280 #define _PWM5OFH1 0x02
8281 #define _PWM5OFH2 0x04
8282 #define _PWM5OFH3 0x08
8283 #define _PWM5OFH4 0x10
8284 #define _PWM5OFH5 0x20
8285 #define _PWM5OFH6 0x40
8286 #define _PWM5OFH7 0x80
8288 //==============================================================================
8290 extern __at(0x0D99) __sfr PWM5TMR
;
8292 //==============================================================================
8295 extern __at(0x0D99) __sfr PWM5TMRL
;
8299 unsigned PWM5TMRL0
: 1;
8300 unsigned PWM5TMRL1
: 1;
8301 unsigned PWM5TMRL2
: 1;
8302 unsigned PWM5TMRL3
: 1;
8303 unsigned PWM5TMRL4
: 1;
8304 unsigned PWM5TMRL5
: 1;
8305 unsigned PWM5TMRL6
: 1;
8306 unsigned PWM5TMRL7
: 1;
8309 extern __at(0x0D99) volatile __PWM5TMRLbits_t PWM5TMRLbits
;
8311 #define _PWM5TMRL0 0x01
8312 #define _PWM5TMRL1 0x02
8313 #define _PWM5TMRL2 0x04
8314 #define _PWM5TMRL3 0x08
8315 #define _PWM5TMRL4 0x10
8316 #define _PWM5TMRL5 0x20
8317 #define _PWM5TMRL6 0x40
8318 #define _PWM5TMRL7 0x80
8320 //==============================================================================
8323 //==============================================================================
8326 extern __at(0x0D9A) __sfr PWM5TMRH
;
8330 unsigned PWM5TMRH0
: 1;
8331 unsigned PWM5TMRH1
: 1;
8332 unsigned PWM5TMRH2
: 1;
8333 unsigned PWM5TMRH3
: 1;
8334 unsigned PWM5TMRH4
: 1;
8335 unsigned PWM5TMRH5
: 1;
8336 unsigned PWM5TMRH6
: 1;
8337 unsigned PWM5TMRH7
: 1;
8340 extern __at(0x0D9A) volatile __PWM5TMRHbits_t PWM5TMRHbits
;
8342 #define _PWM5TMRH0 0x01
8343 #define _PWM5TMRH1 0x02
8344 #define _PWM5TMRH2 0x04
8345 #define _PWM5TMRH3 0x08
8346 #define _PWM5TMRH4 0x10
8347 #define _PWM5TMRH5 0x20
8348 #define _PWM5TMRH6 0x40
8349 #define _PWM5TMRH7 0x80
8351 //==============================================================================
8354 //==============================================================================
8357 extern __at(0x0D9B) __sfr PWM5CON
;
8365 unsigned PWM5MODE0
: 1;
8366 unsigned PWM5MODE1
: 1;
8379 unsigned PWM5POL
: 1;
8380 unsigned PWM5OUT
: 1;
8382 unsigned PWM5EN
: 1;
8395 unsigned PWM5MODE
: 2;
8400 extern __at(0x0D9B) volatile __PWM5CONbits_t PWM5CONbits
;
8402 #define _PWM5CON_PWM5MODE0 0x04
8403 #define _PWM5CON_MODE0 0x04
8404 #define _PWM5CON_PWM5MODE1 0x08
8405 #define _PWM5CON_MODE1 0x08
8406 #define _PWM5CON_POL 0x10
8407 #define _PWM5CON_PWM5POL 0x10
8408 #define _PWM5CON_OUT 0x20
8409 #define _PWM5CON_PWM5OUT 0x20
8410 #define _PWM5CON_EN 0x80
8411 #define _PWM5CON_PWM5EN 0x80
8413 //==============================================================================
8416 //==============================================================================
8419 extern __at(0x0D9C) __sfr PWM5INTCON
;
8437 unsigned PWM5PRIE
: 1;
8438 unsigned PWM5DCIE
: 1;
8439 unsigned PWM5PHIE
: 1;
8440 unsigned PWM5OFIE
: 1;
8446 } __PWM5INTCONbits_t
;
8448 extern __at(0x0D9C) volatile __PWM5INTCONbits_t PWM5INTCONbits
;
8451 #define _PWM5PRIE 0x01
8453 #define _PWM5DCIE 0x02
8455 #define _PWM5PHIE 0x04
8457 #define _PWM5OFIE 0x08
8459 //==============================================================================
8462 //==============================================================================
8465 extern __at(0x0D9C) __sfr PWM5INTE
;
8483 unsigned PWM5PRIE
: 1;
8484 unsigned PWM5DCIE
: 1;
8485 unsigned PWM5PHIE
: 1;
8486 unsigned PWM5OFIE
: 1;
8494 extern __at(0x0D9C) volatile __PWM5INTEbits_t PWM5INTEbits
;
8496 #define _PWM5INTE_PRIE 0x01
8497 #define _PWM5INTE_PWM5PRIE 0x01
8498 #define _PWM5INTE_DCIE 0x02
8499 #define _PWM5INTE_PWM5DCIE 0x02
8500 #define _PWM5INTE_PHIE 0x04
8501 #define _PWM5INTE_PWM5PHIE 0x04
8502 #define _PWM5INTE_OFIE 0x08
8503 #define _PWM5INTE_PWM5OFIE 0x08
8505 //==============================================================================
8508 //==============================================================================
8511 extern __at(0x0D9D) __sfr PWM5INTF
;
8529 unsigned PWM5PRIF
: 1;
8530 unsigned PWM5DCIF
: 1;
8531 unsigned PWM5PHIF
: 1;
8532 unsigned PWM5OFIF
: 1;
8540 extern __at(0x0D9D) volatile __PWM5INTFbits_t PWM5INTFbits
;
8543 #define _PWM5PRIF 0x01
8545 #define _PWM5DCIF 0x02
8547 #define _PWM5PHIF 0x04
8549 #define _PWM5OFIF 0x08
8551 //==============================================================================
8554 //==============================================================================
8557 extern __at(0x0D9D) __sfr PWM5INTFLG
;
8575 unsigned PWM5PRIF
: 1;
8576 unsigned PWM5DCIF
: 1;
8577 unsigned PWM5PHIF
: 1;
8578 unsigned PWM5OFIF
: 1;
8584 } __PWM5INTFLGbits_t
;
8586 extern __at(0x0D9D) volatile __PWM5INTFLGbits_t PWM5INTFLGbits
;
8588 #define _PWM5INTFLG_PRIF 0x01
8589 #define _PWM5INTFLG_PWM5PRIF 0x01
8590 #define _PWM5INTFLG_DCIF 0x02
8591 #define _PWM5INTFLG_PWM5DCIF 0x02
8592 #define _PWM5INTFLG_PHIF 0x04
8593 #define _PWM5INTFLG_PWM5PHIF 0x04
8594 #define _PWM5INTFLG_OFIF 0x08
8595 #define _PWM5INTFLG_PWM5OFIF 0x08
8597 //==============================================================================
8600 //==============================================================================
8603 extern __at(0x0D9E) __sfr PWM5CLKCON
;
8609 unsigned PWM5CS0
: 1;
8610 unsigned PWM5CS1
: 1;
8611 unsigned PWM5CS2
: 1;
8613 unsigned PWM5PS0
: 1;
8614 unsigned PWM5PS1
: 1;
8615 unsigned PWM5PS2
: 1;
8633 unsigned PWM5CS
: 3;
8653 unsigned PWM5PS
: 3;
8656 } __PWM5CLKCONbits_t
;
8658 extern __at(0x0D9E) volatile __PWM5CLKCONbits_t PWM5CLKCONbits
;
8660 #define _PWM5CLKCON_PWM5CS0 0x01
8661 #define _PWM5CLKCON_CS0 0x01
8662 #define _PWM5CLKCON_PWM5CS1 0x02
8663 #define _PWM5CLKCON_CS1 0x02
8664 #define _PWM5CLKCON_PWM5CS2 0x04
8665 #define _PWM5CLKCON_CS2 0x04
8666 #define _PWM5CLKCON_PWM5PS0 0x10
8667 #define _PWM5CLKCON_PS0 0x10
8668 #define _PWM5CLKCON_PWM5PS1 0x20
8669 #define _PWM5CLKCON_PS1 0x20
8670 #define _PWM5CLKCON_PWM5PS2 0x40
8671 #define _PWM5CLKCON_PS2 0x40
8673 //==============================================================================
8676 //==============================================================================
8679 extern __at(0x0D9F) __sfr PWM5LDCON
;
8704 unsigned PWM5LD
: 1;
8706 } __PWM5LDCONbits_t
;
8708 extern __at(0x0D9F) volatile __PWM5LDCONbits_t PWM5LDCONbits
;
8711 #define _PWM5LD 0x80
8713 //==============================================================================
8716 //==============================================================================
8719 extern __at(0x0DA0) __sfr PWM5OFCON
;
8741 unsigned PWM5OFMC
: 1;
8746 } __PWM5OFCONbits_t
;
8748 extern __at(0x0DA0) volatile __PWM5OFCONbits_t PWM5OFCONbits
;
8751 #define _PWM5OFMC 0x10
8753 //==============================================================================
8756 //==============================================================================
8759 extern __at(0x0E0F) __sfr PPSLOCK
;
8763 unsigned PPSLOCKED
: 1;
8773 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
8775 #define _PPSLOCKED 0x01
8777 //==============================================================================
8779 extern __at(0x0E10) __sfr INTPPS
;
8780 extern __at(0x0E11) __sfr T0CKIPPS
;
8781 extern __at(0x0E12) __sfr T1CKIPPS
;
8782 extern __at(0x0E13) __sfr T1GPPS
;
8783 extern __at(0x0E14) __sfr CCP1PPS
;
8784 extern __at(0x0E16) __sfr COG1INPPS
;
8785 extern __at(0x0E19) __sfr T2CKIPPS
;
8786 extern __at(0x0E1A) __sfr T3CKIPPS
;
8787 extern __at(0x0E1B) __sfr T3GPPS
;
8788 extern __at(0x0E1C) __sfr T4CKIPPS
;
8789 extern __at(0x0E1D) __sfr T5CKIPPS
;
8790 extern __at(0x0E1E) __sfr T5GPPS
;
8791 extern __at(0x0E1F) __sfr T6CKIPPS
;
8792 extern __at(0x0E20) __sfr SSPCLKPPS
;
8793 extern __at(0x0E21) __sfr SSPDATPPS
;
8794 extern __at(0x0E22) __sfr SSPSSPPS
;
8795 extern __at(0x0E24) __sfr RXPPS
;
8796 extern __at(0x0E25) __sfr CKPPS
;
8797 extern __at(0x0E28) __sfr CLCIN0PPS
;
8798 extern __at(0x0E29) __sfr CLCIN1PPS
;
8799 extern __at(0x0E2A) __sfr CLCIN2PPS
;
8800 extern __at(0x0E2B) __sfr CLCIN3PPS
;
8801 extern __at(0x0E2C) __sfr PRG1RPPS
;
8802 extern __at(0x0E2D) __sfr PRG1FPPS
;
8803 extern __at(0x0E30) __sfr MD1CHPPS
;
8804 extern __at(0x0E31) __sfr MD1CLPPS
;
8805 extern __at(0x0E32) __sfr MD1MODPPS
;
8806 extern __at(0x0E90) __sfr RA0PPS
;
8807 extern __at(0x0E91) __sfr RA1PPS
;
8808 extern __at(0x0E92) __sfr RA2PPS
;
8809 extern __at(0x0E94) __sfr RA4PPS
;
8810 extern __at(0x0E95) __sfr RA5PPS
;
8811 extern __at(0x0EA0) __sfr RC0PPS
;
8812 extern __at(0x0EA1) __sfr RC1PPS
;
8813 extern __at(0x0EA2) __sfr RC2PPS
;
8814 extern __at(0x0EA3) __sfr RC3PPS
;
8815 extern __at(0x0EA4) __sfr RC4PPS
;
8816 extern __at(0x0EA5) __sfr RC5PPS
;
8818 //==============================================================================
8821 extern __at(0x0F0F) __sfr CLCDATA
;
8825 unsigned MCLC1OUT
: 1;
8826 unsigned MCLC2OUT
: 1;
8827 unsigned MCLC3OUT
: 1;
8835 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
8837 #define _MCLC1OUT 0x01
8838 #define _MCLC2OUT 0x02
8839 #define _MCLC3OUT 0x04
8841 //==============================================================================
8844 //==============================================================================
8847 extern __at(0x0F10) __sfr CLC1CON
;
8853 unsigned LC1MODE0
: 1;
8854 unsigned LC1MODE1
: 1;
8855 unsigned LC1MODE2
: 1;
8856 unsigned LC1INTN
: 1;
8857 unsigned LC1INTP
: 1;
8858 unsigned LC1OUT
: 1;
8883 unsigned LC1MODE
: 3;
8888 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
8890 #define _CLC1CON_LC1MODE0 0x01
8891 #define _CLC1CON_MODE0 0x01
8892 #define _CLC1CON_LC1MODE1 0x02
8893 #define _CLC1CON_MODE1 0x02
8894 #define _CLC1CON_LC1MODE2 0x04
8895 #define _CLC1CON_MODE2 0x04
8896 #define _CLC1CON_LC1INTN 0x08
8897 #define _CLC1CON_INTN 0x08
8898 #define _CLC1CON_LC1INTP 0x10
8899 #define _CLC1CON_INTP 0x10
8900 #define _CLC1CON_LC1OUT 0x20
8901 #define _CLC1CON_OUT 0x20
8902 #define _CLC1CON_LC1EN 0x80
8903 #define _CLC1CON_EN 0x80
8905 //==============================================================================
8908 //==============================================================================
8911 extern __at(0x0F11) __sfr CLC1POL
;
8917 unsigned LC1G1POL
: 1;
8918 unsigned LC1G2POL
: 1;
8919 unsigned LC1G3POL
: 1;
8920 unsigned LC1G4POL
: 1;
8924 unsigned LC1POL
: 1;
8940 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
8942 #define _LC1G1POL 0x01
8944 #define _LC1G2POL 0x02
8946 #define _LC1G3POL 0x04
8948 #define _LC1G4POL 0x08
8950 #define _LC1POL 0x80
8953 //==============================================================================
8956 //==============================================================================
8959 extern __at(0x0F12) __sfr CLC1SEL0
;
8965 unsigned LC1D1S0
: 1;
8966 unsigned LC1D1S1
: 1;
8967 unsigned LC1D1S2
: 1;
8968 unsigned LC1D1S3
: 1;
8969 unsigned LC1D1S4
: 1;
8995 unsigned LC1D1S
: 5;
9000 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
9002 #define _LC1D1S0 0x01
9004 #define _LC1D1S1 0x02
9006 #define _LC1D1S2 0x04
9008 #define _LC1D1S3 0x08
9010 #define _LC1D1S4 0x10
9013 //==============================================================================
9016 //==============================================================================
9019 extern __at(0x0F13) __sfr CLC1SEL1
;
9025 unsigned LC1D2S0
: 1;
9026 unsigned LC1D2S1
: 1;
9027 unsigned LC1D2S2
: 1;
9028 unsigned LC1D2S3
: 1;
9029 unsigned LC1D2S4
: 1;
9049 unsigned LC1D2S
: 5;
9060 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
9062 #define _LC1D2S0 0x01
9064 #define _LC1D2S1 0x02
9066 #define _LC1D2S2 0x04
9068 #define _LC1D2S3 0x08
9070 #define _LC1D2S4 0x10
9073 //==============================================================================
9076 //==============================================================================
9079 extern __at(0x0F14) __sfr CLC1SEL2
;
9085 unsigned LC1D3S0
: 1;
9086 unsigned LC1D3S1
: 1;
9087 unsigned LC1D3S2
: 1;
9088 unsigned LC1D3S3
: 1;
9089 unsigned LC1D3S4
: 1;
9115 unsigned LC1D3S
: 5;
9120 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
9122 #define _LC1D3S0 0x01
9124 #define _LC1D3S1 0x02
9126 #define _LC1D3S2 0x04
9128 #define _LC1D3S3 0x08
9130 #define _LC1D3S4 0x10
9133 //==============================================================================
9136 //==============================================================================
9139 extern __at(0x0F15) __sfr CLC1SEL3
;
9145 unsigned LC1D4S0
: 1;
9146 unsigned LC1D4S1
: 1;
9147 unsigned LC1D4S2
: 1;
9148 unsigned LC1D4S3
: 1;
9149 unsigned LC1D4S4
: 1;
9175 unsigned LC1D4S
: 5;
9180 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
9182 #define _LC1D4S0 0x01
9184 #define _LC1D4S1 0x02
9186 #define _LC1D4S2 0x04
9188 #define _LC1D4S3 0x08
9190 #define _LC1D4S4 0x10
9193 //==============================================================================
9196 //==============================================================================
9199 extern __at(0x0F16) __sfr CLC1GLS0
;
9205 unsigned LC1G1D1N
: 1;
9206 unsigned LC1G1D1T
: 1;
9207 unsigned LC1G1D2N
: 1;
9208 unsigned LC1G1D2T
: 1;
9209 unsigned LC1G1D3N
: 1;
9210 unsigned LC1G1D3T
: 1;
9211 unsigned LC1G1D4N
: 1;
9212 unsigned LC1G1D4T
: 1;
9228 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
9230 #define _LC1G1D1N 0x01
9232 #define _LC1G1D1T 0x02
9234 #define _LC1G1D2N 0x04
9236 #define _LC1G1D2T 0x08
9238 #define _LC1G1D3N 0x10
9240 #define _LC1G1D3T 0x20
9242 #define _LC1G1D4N 0x40
9244 #define _LC1G1D4T 0x80
9247 //==============================================================================
9250 //==============================================================================
9253 extern __at(0x0F17) __sfr CLC1GLS1
;
9259 unsigned LC1G2D1N
: 1;
9260 unsigned LC1G2D1T
: 1;
9261 unsigned LC1G2D2N
: 1;
9262 unsigned LC1G2D2T
: 1;
9263 unsigned LC1G2D3N
: 1;
9264 unsigned LC1G2D3T
: 1;
9265 unsigned LC1G2D4N
: 1;
9266 unsigned LC1G2D4T
: 1;
9282 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
9284 #define _CLC1GLS1_LC1G2D1N 0x01
9285 #define _CLC1GLS1_D1N 0x01
9286 #define _CLC1GLS1_LC1G2D1T 0x02
9287 #define _CLC1GLS1_D1T 0x02
9288 #define _CLC1GLS1_LC1G2D2N 0x04
9289 #define _CLC1GLS1_D2N 0x04
9290 #define _CLC1GLS1_LC1G2D2T 0x08
9291 #define _CLC1GLS1_D2T 0x08
9292 #define _CLC1GLS1_LC1G2D3N 0x10
9293 #define _CLC1GLS1_D3N 0x10
9294 #define _CLC1GLS1_LC1G2D3T 0x20
9295 #define _CLC1GLS1_D3T 0x20
9296 #define _CLC1GLS1_LC1G2D4N 0x40
9297 #define _CLC1GLS1_D4N 0x40
9298 #define _CLC1GLS1_LC1G2D4T 0x80
9299 #define _CLC1GLS1_D4T 0x80
9301 //==============================================================================
9304 //==============================================================================
9307 extern __at(0x0F18) __sfr CLC1GLS2
;
9313 unsigned LC1G3D1N
: 1;
9314 unsigned LC1G3D1T
: 1;
9315 unsigned LC1G3D2N
: 1;
9316 unsigned LC1G3D2T
: 1;
9317 unsigned LC1G3D3N
: 1;
9318 unsigned LC1G3D3T
: 1;
9319 unsigned LC1G3D4N
: 1;
9320 unsigned LC1G3D4T
: 1;
9336 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
9338 #define _CLC1GLS2_LC1G3D1N 0x01
9339 #define _CLC1GLS2_D1N 0x01
9340 #define _CLC1GLS2_LC1G3D1T 0x02
9341 #define _CLC1GLS2_D1T 0x02
9342 #define _CLC1GLS2_LC1G3D2N 0x04
9343 #define _CLC1GLS2_D2N 0x04
9344 #define _CLC1GLS2_LC1G3D2T 0x08
9345 #define _CLC1GLS2_D2T 0x08
9346 #define _CLC1GLS2_LC1G3D3N 0x10
9347 #define _CLC1GLS2_D3N 0x10
9348 #define _CLC1GLS2_LC1G3D3T 0x20
9349 #define _CLC1GLS2_D3T 0x20
9350 #define _CLC1GLS2_LC1G3D4N 0x40
9351 #define _CLC1GLS2_D4N 0x40
9352 #define _CLC1GLS2_LC1G3D4T 0x80
9353 #define _CLC1GLS2_D4T 0x80
9355 //==============================================================================
9358 //==============================================================================
9361 extern __at(0x0F19) __sfr CLC1GLS3
;
9367 unsigned LC1G4D1N
: 1;
9368 unsigned LC1G4D1T
: 1;
9369 unsigned LC1G4D2N
: 1;
9370 unsigned LC1G4D2T
: 1;
9371 unsigned LC1G4D3N
: 1;
9372 unsigned LC1G4D3T
: 1;
9373 unsigned LC1G4D4N
: 1;
9374 unsigned LC1G4D4T
: 1;
9390 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
9392 #define _LC1G4D1N 0x01
9394 #define _LC1G4D1T 0x02
9396 #define _LC1G4D2N 0x04
9398 #define _LC1G4D2T 0x08
9400 #define _LC1G4D3N 0x10
9402 #define _LC1G4D3T 0x20
9404 #define _LC1G4D4N 0x40
9406 #define _LC1G4D4T 0x80
9409 //==============================================================================
9412 //==============================================================================
9415 extern __at(0x0F1A) __sfr CLC2CON
;
9421 unsigned LC2MODE0
: 1;
9422 unsigned LC2MODE1
: 1;
9423 unsigned LC2MODE2
: 1;
9424 unsigned LC2INTN
: 1;
9425 unsigned LC2INTP
: 1;
9426 unsigned LC2OUT
: 1;
9451 unsigned LC2MODE
: 3;
9456 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
9458 #define _CLC2CON_LC2MODE0 0x01
9459 #define _CLC2CON_MODE0 0x01
9460 #define _CLC2CON_LC2MODE1 0x02
9461 #define _CLC2CON_MODE1 0x02
9462 #define _CLC2CON_LC2MODE2 0x04
9463 #define _CLC2CON_MODE2 0x04
9464 #define _CLC2CON_LC2INTN 0x08
9465 #define _CLC2CON_INTN 0x08
9466 #define _CLC2CON_LC2INTP 0x10
9467 #define _CLC2CON_INTP 0x10
9468 #define _CLC2CON_LC2OUT 0x20
9469 #define _CLC2CON_OUT 0x20
9470 #define _CLC2CON_LC2EN 0x80
9471 #define _CLC2CON_EN 0x80
9473 //==============================================================================
9476 //==============================================================================
9479 extern __at(0x0F1B) __sfr CLC2POL
;
9485 unsigned LC2G1POL
: 1;
9486 unsigned LC2G2POL
: 1;
9487 unsigned LC2G3POL
: 1;
9488 unsigned LC2G4POL
: 1;
9492 unsigned LC2POL
: 1;
9508 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
9510 #define _CLC2POL_LC2G1POL 0x01
9511 #define _CLC2POL_G1POL 0x01
9512 #define _CLC2POL_LC2G2POL 0x02
9513 #define _CLC2POL_G2POL 0x02
9514 #define _CLC2POL_LC2G3POL 0x04
9515 #define _CLC2POL_G3POL 0x04
9516 #define _CLC2POL_LC2G4POL 0x08
9517 #define _CLC2POL_G4POL 0x08
9518 #define _CLC2POL_LC2POL 0x80
9519 #define _CLC2POL_POL 0x80
9521 //==============================================================================
9524 //==============================================================================
9527 extern __at(0x0F1C) __sfr CLC2SEL0
;
9533 unsigned LC2D1S0
: 1;
9534 unsigned LC2D1S1
: 1;
9535 unsigned LC2D1S2
: 1;
9536 unsigned LC2D1S3
: 1;
9537 unsigned LC2D1S4
: 1;
9563 unsigned LC2D1S
: 5;
9568 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
9570 #define _CLC2SEL0_LC2D1S0 0x01
9571 #define _CLC2SEL0_D1S0 0x01
9572 #define _CLC2SEL0_LC2D1S1 0x02
9573 #define _CLC2SEL0_D1S1 0x02
9574 #define _CLC2SEL0_LC2D1S2 0x04
9575 #define _CLC2SEL0_D1S2 0x04
9576 #define _CLC2SEL0_LC2D1S3 0x08
9577 #define _CLC2SEL0_D1S3 0x08
9578 #define _CLC2SEL0_LC2D1S4 0x10
9579 #define _CLC2SEL0_D1S4 0x10
9581 //==============================================================================
9584 //==============================================================================
9587 extern __at(0x0F1D) __sfr CLC2SEL1
;
9593 unsigned LC2D2S0
: 1;
9594 unsigned LC2D2S1
: 1;
9595 unsigned LC2D2S2
: 1;
9596 unsigned LC2D2S3
: 1;
9597 unsigned LC2D2S4
: 1;
9617 unsigned LC2D2S
: 5;
9628 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
9630 #define _CLC2SEL1_LC2D2S0 0x01
9631 #define _CLC2SEL1_D2S0 0x01
9632 #define _CLC2SEL1_LC2D2S1 0x02
9633 #define _CLC2SEL1_D2S1 0x02
9634 #define _CLC2SEL1_LC2D2S2 0x04
9635 #define _CLC2SEL1_D2S2 0x04
9636 #define _CLC2SEL1_LC2D2S3 0x08
9637 #define _CLC2SEL1_D2S3 0x08
9638 #define _CLC2SEL1_LC2D2S4 0x10
9639 #define _CLC2SEL1_D2S4 0x10
9641 //==============================================================================
9644 //==============================================================================
9647 extern __at(0x0F1E) __sfr CLC2SEL2
;
9653 unsigned LC2D3S0
: 1;
9654 unsigned LC2D3S1
: 1;
9655 unsigned LC2D3S2
: 1;
9656 unsigned LC2D3S3
: 1;
9657 unsigned LC2D3S4
: 1;
9683 unsigned LC2D3S
: 5;
9688 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
9690 #define _CLC2SEL2_LC2D3S0 0x01
9691 #define _CLC2SEL2_D3S0 0x01
9692 #define _CLC2SEL2_LC2D3S1 0x02
9693 #define _CLC2SEL2_D3S1 0x02
9694 #define _CLC2SEL2_LC2D3S2 0x04
9695 #define _CLC2SEL2_D3S2 0x04
9696 #define _CLC2SEL2_LC2D3S3 0x08
9697 #define _CLC2SEL2_D3S3 0x08
9698 #define _CLC2SEL2_LC2D3S4 0x10
9699 #define _CLC2SEL2_D3S4 0x10
9701 //==============================================================================
9704 //==============================================================================
9707 extern __at(0x0F1F) __sfr CLC2SEL3
;
9713 unsigned LC2D4S0
: 1;
9714 unsigned LC2D4S1
: 1;
9715 unsigned LC2D4S2
: 1;
9716 unsigned LC2D4S3
: 1;
9717 unsigned LC2D4S4
: 1;
9737 unsigned LC2D4S
: 5;
9748 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
9750 #define _CLC2SEL3_LC2D4S0 0x01
9751 #define _CLC2SEL3_D4S0 0x01
9752 #define _CLC2SEL3_LC2D4S1 0x02
9753 #define _CLC2SEL3_D4S1 0x02
9754 #define _CLC2SEL3_LC2D4S2 0x04
9755 #define _CLC2SEL3_D4S2 0x04
9756 #define _CLC2SEL3_LC2D4S3 0x08
9757 #define _CLC2SEL3_D4S3 0x08
9758 #define _CLC2SEL3_LC2D4S4 0x10
9759 #define _CLC2SEL3_D4S4 0x10
9761 //==============================================================================
9764 //==============================================================================
9767 extern __at(0x0F20) __sfr CLC2GLS0
;
9773 unsigned LC2G1D1N
: 1;
9774 unsigned LC2G1D1T
: 1;
9775 unsigned LC2G1D2N
: 1;
9776 unsigned LC2G1D2T
: 1;
9777 unsigned LC2G1D3N
: 1;
9778 unsigned LC2G1D3T
: 1;
9779 unsigned LC2G1D4N
: 1;
9780 unsigned LC2G1D4T
: 1;
9796 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
9798 #define _CLC2GLS0_LC2G1D1N 0x01
9799 #define _CLC2GLS0_D1N 0x01
9800 #define _CLC2GLS0_LC2G1D1T 0x02
9801 #define _CLC2GLS0_D1T 0x02
9802 #define _CLC2GLS0_LC2G1D2N 0x04
9803 #define _CLC2GLS0_D2N 0x04
9804 #define _CLC2GLS0_LC2G1D2T 0x08
9805 #define _CLC2GLS0_D2T 0x08
9806 #define _CLC2GLS0_LC2G1D3N 0x10
9807 #define _CLC2GLS0_D3N 0x10
9808 #define _CLC2GLS0_LC2G1D3T 0x20
9809 #define _CLC2GLS0_D3T 0x20
9810 #define _CLC2GLS0_LC2G1D4N 0x40
9811 #define _CLC2GLS0_D4N 0x40
9812 #define _CLC2GLS0_LC2G1D4T 0x80
9813 #define _CLC2GLS0_D4T 0x80
9815 //==============================================================================
9818 //==============================================================================
9821 extern __at(0x0F21) __sfr CLC2GLS1
;
9827 unsigned LC2G2D1N
: 1;
9828 unsigned LC2G2D1T
: 1;
9829 unsigned LC2G2D2N
: 1;
9830 unsigned LC2G2D2T
: 1;
9831 unsigned LC2G2D3N
: 1;
9832 unsigned LC2G2D3T
: 1;
9833 unsigned LC2G2D4N
: 1;
9834 unsigned LC2G2D4T
: 1;
9850 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
9852 #define _CLC2GLS1_LC2G2D1N 0x01
9853 #define _CLC2GLS1_D1N 0x01
9854 #define _CLC2GLS1_LC2G2D1T 0x02
9855 #define _CLC2GLS1_D1T 0x02
9856 #define _CLC2GLS1_LC2G2D2N 0x04
9857 #define _CLC2GLS1_D2N 0x04
9858 #define _CLC2GLS1_LC2G2D2T 0x08
9859 #define _CLC2GLS1_D2T 0x08
9860 #define _CLC2GLS1_LC2G2D3N 0x10
9861 #define _CLC2GLS1_D3N 0x10
9862 #define _CLC2GLS1_LC2G2D3T 0x20
9863 #define _CLC2GLS1_D3T 0x20
9864 #define _CLC2GLS1_LC2G2D4N 0x40
9865 #define _CLC2GLS1_D4N 0x40
9866 #define _CLC2GLS1_LC2G2D4T 0x80
9867 #define _CLC2GLS1_D4T 0x80
9869 //==============================================================================
9872 //==============================================================================
9875 extern __at(0x0F22) __sfr CLC2GLS2
;
9881 unsigned LC2G3D1N
: 1;
9882 unsigned LC2G3D1T
: 1;
9883 unsigned LC2G3D2N
: 1;
9884 unsigned LC2G3D2T
: 1;
9885 unsigned LC2G3D3N
: 1;
9886 unsigned LC2G3D3T
: 1;
9887 unsigned LC2G3D4N
: 1;
9888 unsigned LC2G3D4T
: 1;
9904 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
9906 #define _CLC2GLS2_LC2G3D1N 0x01
9907 #define _CLC2GLS2_D1N 0x01
9908 #define _CLC2GLS2_LC2G3D1T 0x02
9909 #define _CLC2GLS2_D1T 0x02
9910 #define _CLC2GLS2_LC2G3D2N 0x04
9911 #define _CLC2GLS2_D2N 0x04
9912 #define _CLC2GLS2_LC2G3D2T 0x08
9913 #define _CLC2GLS2_D2T 0x08
9914 #define _CLC2GLS2_LC2G3D3N 0x10
9915 #define _CLC2GLS2_D3N 0x10
9916 #define _CLC2GLS2_LC2G3D3T 0x20
9917 #define _CLC2GLS2_D3T 0x20
9918 #define _CLC2GLS2_LC2G3D4N 0x40
9919 #define _CLC2GLS2_D4N 0x40
9920 #define _CLC2GLS2_LC2G3D4T 0x80
9921 #define _CLC2GLS2_D4T 0x80
9923 //==============================================================================
9926 //==============================================================================
9929 extern __at(0x0F23) __sfr CLC2GLS3
;
9935 unsigned LC2G4D1N
: 1;
9936 unsigned LC2G4D1T
: 1;
9937 unsigned LC2G4D2N
: 1;
9938 unsigned LC2G4D2T
: 1;
9939 unsigned LC2G4D3N
: 1;
9940 unsigned LC2G4D3T
: 1;
9941 unsigned LC2G4D4N
: 1;
9942 unsigned LC2G4D4T
: 1;
9958 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
9960 #define _CLC2GLS3_LC2G4D1N 0x01
9961 #define _CLC2GLS3_G4D1N 0x01
9962 #define _CLC2GLS3_LC2G4D1T 0x02
9963 #define _CLC2GLS3_G4D1T 0x02
9964 #define _CLC2GLS3_LC2G4D2N 0x04
9965 #define _CLC2GLS3_G4D2N 0x04
9966 #define _CLC2GLS3_LC2G4D2T 0x08
9967 #define _CLC2GLS3_G4D2T 0x08
9968 #define _CLC2GLS3_LC2G4D3N 0x10
9969 #define _CLC2GLS3_G4D3N 0x10
9970 #define _CLC2GLS3_LC2G4D3T 0x20
9971 #define _CLC2GLS3_G4D3T 0x20
9972 #define _CLC2GLS3_LC2G4D4N 0x40
9973 #define _CLC2GLS3_G4D4N 0x40
9974 #define _CLC2GLS3_LC2G4D4T 0x80
9975 #define _CLC2GLS3_G4D4T 0x80
9977 //==============================================================================
9980 //==============================================================================
9983 extern __at(0x0F24) __sfr CLC3CON
;
9989 unsigned LC3MODE0
: 1;
9990 unsigned LC3MODE1
: 1;
9991 unsigned LC3MODE2
: 1;
9992 unsigned LC3INTN
: 1;
9993 unsigned LC3INTP
: 1;
9994 unsigned LC3OUT
: 1;
10001 unsigned MODE0
: 1;
10002 unsigned MODE1
: 1;
10003 unsigned MODE2
: 1;
10013 unsigned LC3MODE
: 3;
10024 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
10026 #define _CLC3CON_LC3MODE0 0x01
10027 #define _CLC3CON_MODE0 0x01
10028 #define _CLC3CON_LC3MODE1 0x02
10029 #define _CLC3CON_MODE1 0x02
10030 #define _CLC3CON_LC3MODE2 0x04
10031 #define _CLC3CON_MODE2 0x04
10032 #define _CLC3CON_LC3INTN 0x08
10033 #define _CLC3CON_INTN 0x08
10034 #define _CLC3CON_LC3INTP 0x10
10035 #define _CLC3CON_INTP 0x10
10036 #define _CLC3CON_LC3OUT 0x20
10037 #define _CLC3CON_OUT 0x20
10038 #define _CLC3CON_LC3EN 0x80
10039 #define _CLC3CON_EN 0x80
10041 //==============================================================================
10044 //==============================================================================
10047 extern __at(0x0F25) __sfr CLC3POL
;
10053 unsigned LC3G1POL
: 1;
10054 unsigned LC3G2POL
: 1;
10055 unsigned LC3G3POL
: 1;
10056 unsigned LC3G4POL
: 1;
10060 unsigned LC3POL
: 1;
10065 unsigned G1POL
: 1;
10066 unsigned G2POL
: 1;
10067 unsigned G3POL
: 1;
10068 unsigned G4POL
: 1;
10076 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
10078 #define _CLC3POL_LC3G1POL 0x01
10079 #define _CLC3POL_G1POL 0x01
10080 #define _CLC3POL_LC3G2POL 0x02
10081 #define _CLC3POL_G2POL 0x02
10082 #define _CLC3POL_LC3G3POL 0x04
10083 #define _CLC3POL_G3POL 0x04
10084 #define _CLC3POL_LC3G4POL 0x08
10085 #define _CLC3POL_G4POL 0x08
10086 #define _CLC3POL_LC3POL 0x80
10087 #define _CLC3POL_POL 0x80
10089 //==============================================================================
10092 //==============================================================================
10095 extern __at(0x0F26) __sfr CLC3SEL0
;
10101 unsigned LC3D1S0
: 1;
10102 unsigned LC3D1S1
: 1;
10103 unsigned LC3D1S2
: 1;
10104 unsigned LC3D1S3
: 1;
10105 unsigned LC3D1S4
: 1;
10131 unsigned LC3D1S
: 5;
10134 } __CLC3SEL0bits_t
;
10136 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
10138 #define _CLC3SEL0_LC3D1S0 0x01
10139 #define _CLC3SEL0_D1S0 0x01
10140 #define _CLC3SEL0_LC3D1S1 0x02
10141 #define _CLC3SEL0_D1S1 0x02
10142 #define _CLC3SEL0_LC3D1S2 0x04
10143 #define _CLC3SEL0_D1S2 0x04
10144 #define _CLC3SEL0_LC3D1S3 0x08
10145 #define _CLC3SEL0_D1S3 0x08
10146 #define _CLC3SEL0_LC3D1S4 0x10
10147 #define _CLC3SEL0_D1S4 0x10
10149 //==============================================================================
10152 //==============================================================================
10155 extern __at(0x0F27) __sfr CLC3SEL1
;
10161 unsigned LC3D2S0
: 1;
10162 unsigned LC3D2S1
: 1;
10163 unsigned LC3D2S2
: 1;
10164 unsigned LC3D2S3
: 1;
10165 unsigned LC3D2S4
: 1;
10191 unsigned LC3D2S
: 5;
10194 } __CLC3SEL1bits_t
;
10196 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
10198 #define _CLC3SEL1_LC3D2S0 0x01
10199 #define _CLC3SEL1_D2S0 0x01
10200 #define _CLC3SEL1_LC3D2S1 0x02
10201 #define _CLC3SEL1_D2S1 0x02
10202 #define _CLC3SEL1_LC3D2S2 0x04
10203 #define _CLC3SEL1_D2S2 0x04
10204 #define _CLC3SEL1_LC3D2S3 0x08
10205 #define _CLC3SEL1_D2S3 0x08
10206 #define _CLC3SEL1_LC3D2S4 0x10
10207 #define _CLC3SEL1_D2S4 0x10
10209 //==============================================================================
10212 //==============================================================================
10215 extern __at(0x0F28) __sfr CLC3SEL2
;
10221 unsigned LC3D3S0
: 1;
10222 unsigned LC3D3S1
: 1;
10223 unsigned LC3D3S2
: 1;
10224 unsigned LC3D3S3
: 1;
10225 unsigned LC3D3S4
: 1;
10251 unsigned LC3D3S
: 5;
10254 } __CLC3SEL2bits_t
;
10256 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
10258 #define _CLC3SEL2_LC3D3S0 0x01
10259 #define _CLC3SEL2_D3S0 0x01
10260 #define _CLC3SEL2_LC3D3S1 0x02
10261 #define _CLC3SEL2_D3S1 0x02
10262 #define _CLC3SEL2_LC3D3S2 0x04
10263 #define _CLC3SEL2_D3S2 0x04
10264 #define _CLC3SEL2_LC3D3S3 0x08
10265 #define _CLC3SEL2_D3S3 0x08
10266 #define _CLC3SEL2_LC3D3S4 0x10
10267 #define _CLC3SEL2_D3S4 0x10
10269 //==============================================================================
10272 //==============================================================================
10275 extern __at(0x0F29) __sfr CLC3SEL3
;
10281 unsigned LC3D4S0
: 1;
10282 unsigned LC3D4S1
: 1;
10283 unsigned LC3D4S2
: 1;
10284 unsigned LC3D4S3
: 1;
10285 unsigned LC3D4S4
: 1;
10305 unsigned LC3D4S
: 5;
10314 } __CLC3SEL3bits_t
;
10316 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
10318 #define _CLC3SEL3_LC3D4S0 0x01
10319 #define _CLC3SEL3_D4S0 0x01
10320 #define _CLC3SEL3_LC3D4S1 0x02
10321 #define _CLC3SEL3_D4S1 0x02
10322 #define _CLC3SEL3_LC3D4S2 0x04
10323 #define _CLC3SEL3_D4S2 0x04
10324 #define _CLC3SEL3_LC3D4S3 0x08
10325 #define _CLC3SEL3_D4S3 0x08
10326 #define _CLC3SEL3_LC3D4S4 0x10
10327 #define _CLC3SEL3_D4S4 0x10
10329 //==============================================================================
10332 //==============================================================================
10335 extern __at(0x0F2A) __sfr CLC3GLS0
;
10341 unsigned LC3G1D1N
: 1;
10342 unsigned LC3G1D1T
: 1;
10343 unsigned LC3G1D2N
: 1;
10344 unsigned LC3G1D2T
: 1;
10345 unsigned LC3G1D3N
: 1;
10346 unsigned LC3G1D3T
: 1;
10347 unsigned LC3G1D4N
: 1;
10348 unsigned LC3G1D4T
: 1;
10362 } __CLC3GLS0bits_t
;
10364 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
10366 #define _CLC3GLS0_LC3G1D1N 0x01
10367 #define _CLC3GLS0_D1N 0x01
10368 #define _CLC3GLS0_LC3G1D1T 0x02
10369 #define _CLC3GLS0_D1T 0x02
10370 #define _CLC3GLS0_LC3G1D2N 0x04
10371 #define _CLC3GLS0_D2N 0x04
10372 #define _CLC3GLS0_LC3G1D2T 0x08
10373 #define _CLC3GLS0_D2T 0x08
10374 #define _CLC3GLS0_LC3G1D3N 0x10
10375 #define _CLC3GLS0_D3N 0x10
10376 #define _CLC3GLS0_LC3G1D3T 0x20
10377 #define _CLC3GLS0_D3T 0x20
10378 #define _CLC3GLS0_LC3G1D4N 0x40
10379 #define _CLC3GLS0_D4N 0x40
10380 #define _CLC3GLS0_LC3G1D4T 0x80
10381 #define _CLC3GLS0_D4T 0x80
10383 //==============================================================================
10386 //==============================================================================
10389 extern __at(0x0F2B) __sfr CLC3GLS1
;
10395 unsigned LC3G2D1N
: 1;
10396 unsigned LC3G2D1T
: 1;
10397 unsigned LC3G2D2N
: 1;
10398 unsigned LC3G2D2T
: 1;
10399 unsigned LC3G2D3N
: 1;
10400 unsigned LC3G2D3T
: 1;
10401 unsigned LC3G2D4N
: 1;
10402 unsigned LC3G2D4T
: 1;
10416 } __CLC3GLS1bits_t
;
10418 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
10420 #define _CLC3GLS1_LC3G2D1N 0x01
10421 #define _CLC3GLS1_D1N 0x01
10422 #define _CLC3GLS1_LC3G2D1T 0x02
10423 #define _CLC3GLS1_D1T 0x02
10424 #define _CLC3GLS1_LC3G2D2N 0x04
10425 #define _CLC3GLS1_D2N 0x04
10426 #define _CLC3GLS1_LC3G2D2T 0x08
10427 #define _CLC3GLS1_D2T 0x08
10428 #define _CLC3GLS1_LC3G2D3N 0x10
10429 #define _CLC3GLS1_D3N 0x10
10430 #define _CLC3GLS1_LC3G2D3T 0x20
10431 #define _CLC3GLS1_D3T 0x20
10432 #define _CLC3GLS1_LC3G2D4N 0x40
10433 #define _CLC3GLS1_D4N 0x40
10434 #define _CLC3GLS1_LC3G2D4T 0x80
10435 #define _CLC3GLS1_D4T 0x80
10437 //==============================================================================
10440 //==============================================================================
10443 extern __at(0x0F2C) __sfr CLC3GLS2
;
10449 unsigned LC3G3D1N
: 1;
10450 unsigned LC3G3D1T
: 1;
10451 unsigned LC3G3D2N
: 1;
10452 unsigned LC3G3D2T
: 1;
10453 unsigned LC3G3D3N
: 1;
10454 unsigned LC3G3D3T
: 1;
10455 unsigned LC3G3D4N
: 1;
10456 unsigned LC3G3D4T
: 1;
10470 } __CLC3GLS2bits_t
;
10472 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
10474 #define _CLC3GLS2_LC3G3D1N 0x01
10475 #define _CLC3GLS2_D1N 0x01
10476 #define _CLC3GLS2_LC3G3D1T 0x02
10477 #define _CLC3GLS2_D1T 0x02
10478 #define _CLC3GLS2_LC3G3D2N 0x04
10479 #define _CLC3GLS2_D2N 0x04
10480 #define _CLC3GLS2_LC3G3D2T 0x08
10481 #define _CLC3GLS2_D2T 0x08
10482 #define _CLC3GLS2_LC3G3D3N 0x10
10483 #define _CLC3GLS2_D3N 0x10
10484 #define _CLC3GLS2_LC3G3D3T 0x20
10485 #define _CLC3GLS2_D3T 0x20
10486 #define _CLC3GLS2_LC3G3D4N 0x40
10487 #define _CLC3GLS2_D4N 0x40
10488 #define _CLC3GLS2_LC3G3D4T 0x80
10489 #define _CLC3GLS2_D4T 0x80
10491 //==============================================================================
10494 //==============================================================================
10497 extern __at(0x0F2D) __sfr CLC3GLS3
;
10503 unsigned LC3G4D1N
: 1;
10504 unsigned LC3G4D1T
: 1;
10505 unsigned LC3G4D2N
: 1;
10506 unsigned LC3G4D2T
: 1;
10507 unsigned LC3G4D3N
: 1;
10508 unsigned LC3G4D3T
: 1;
10509 unsigned LC3G4D4N
: 1;
10510 unsigned LC3G4D4T
: 1;
10515 unsigned G4D1N
: 1;
10516 unsigned G4D1T
: 1;
10517 unsigned G4D2N
: 1;
10518 unsigned G4D2T
: 1;
10519 unsigned G4D3N
: 1;
10520 unsigned G4D3T
: 1;
10521 unsigned G4D4N
: 1;
10522 unsigned G4D4T
: 1;
10524 } __CLC3GLS3bits_t
;
10526 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
10528 #define _CLC3GLS3_LC3G4D1N 0x01
10529 #define _CLC3GLS3_G4D1N 0x01
10530 #define _CLC3GLS3_LC3G4D1T 0x02
10531 #define _CLC3GLS3_G4D1T 0x02
10532 #define _CLC3GLS3_LC3G4D2N 0x04
10533 #define _CLC3GLS3_G4D2N 0x04
10534 #define _CLC3GLS3_LC3G4D2T 0x08
10535 #define _CLC3GLS3_G4D2T 0x08
10536 #define _CLC3GLS3_LC3G4D3N 0x10
10537 #define _CLC3GLS3_G4D3N 0x10
10538 #define _CLC3GLS3_LC3G4D3T 0x20
10539 #define _CLC3GLS3_G4D3T 0x20
10540 #define _CLC3GLS3_LC3G4D4N 0x40
10541 #define _CLC3GLS3_G4D4N 0x40
10542 #define _CLC3GLS3_LC3G4D4T 0x80
10543 #define _CLC3GLS3_G4D4T 0x80
10545 //==============================================================================
10548 //==============================================================================
10549 // STATUS_SHAD Bits
10551 extern __at(0x0FE4) __sfr STATUS_SHAD
;
10555 unsigned C_SHAD
: 1;
10556 unsigned DC_SHAD
: 1;
10557 unsigned Z_SHAD
: 1;
10563 } __STATUS_SHADbits_t
;
10565 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
10567 #define _C_SHAD 0x01
10568 #define _DC_SHAD 0x02
10569 #define _Z_SHAD 0x04
10571 //==============================================================================
10573 extern __at(0x0FE5) __sfr WREG_SHAD
;
10574 extern __at(0x0FE6) __sfr BSR_SHAD
;
10575 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
10576 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
10577 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
10578 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
10579 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
10580 extern __at(0x0FED) __sfr STKPTR
;
10581 extern __at(0x0FEE) __sfr TOSL
;
10582 extern __at(0x0FEF) __sfr TOSH
;
10584 //==============================================================================
10586 // Configuration Bits
10588 //==============================================================================
10590 #define _CONFIG1 0x8007
10591 #define _CONFIG2 0x8008
10593 //----------------------------- CONFIG1 Options -------------------------------
10595 #define _FOSC_LP 0x3FF8 // LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins.
10596 #define _FOSC_XT 0x3FF9 // XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins.
10597 #define _FOSC_HS 0x3FFA // HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins.
10598 #define _FOSC_EXTRC 0x3FFB // EXTRC oscillator: External RC circuit connected to CLKIN pin.
10599 #define _FOSC_INTOSC 0x3FFC // INTOSC oscillator: I/O function on CLKIN pin.
10600 #define _FOSC_ECL 0x3FFD // ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pins.
10601 #define _FOSC_ECM 0x3FFE // ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pins.
10602 #define _FOSC_ECH 0x3FFF // ECH, External Clock, High Power Mode (4-20 MHz): device clock supplied to CLKIN pins.
10603 #define _WDTE_OFF 0x3FE7 // WDT disabled.
10604 #define _WDTE_SWDTEN 0x3FEF // WDT controlled by the SWDTEN bit in the WDTCON register.
10605 #define _WDTE_NSLEEP 0x3FF7 // WDT enabled while running and disabled in Sleep.
10606 #define _WDTE_ON 0x3FFF // WDT enabled.
10607 #define _PWRTE_ON 0x3FDF // PWRT enabled.
10608 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
10609 #define _MCLRE_OFF 0x3FBF // MCLR/VPP pin function is digital input.
10610 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR.
10611 #define _CP_ON 0x3F7F // Program memory code protection is enabled.
10612 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
10613 #define _BOREN_OFF 0x39FF // Brown-out Reset disabled.
10614 #define _BOREN_SBODEN 0x3BFF // Brown-out Reset controlled by the SBOREN bit in the BORCON register.
10615 #define _BOREN_NSLEEP 0x3DFF // Brown-out Reset enabled while running and disabled in Sleep.
10616 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled.
10617 #define _CLKOUTEN_ON 0x37FF // CLKOUT function is enabled on the CLKOUT pin.
10618 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
10619 #define _IESO_OFF 0x2FFF // Internal/External Switchover Mode is disabled.
10620 #define _IESO_ON 0x3FFF // Internal/External Switchover Mode is enabled.
10621 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
10622 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
10624 //----------------------------- CONFIG2 Options -------------------------------
10626 #define _WRT_ALL 0x3FFC // 000h to 1FFFh write protected, no addresses may be modified by EECON control.
10627 #define _WRT_HALF 0x3FFD // 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control.
10628 #define _WRT_BOOT 0x3FFE // 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control.
10629 #define _WRT_OFF 0x3FFF // Write protection off.
10630 #define _PPS1WAY_OFF 0x3FFB // The PPSLOCK bit can be set and cleared repeatedly by software.
10631 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit cannot be cleared once it is set by software.
10632 #define _ZCD_ON 0x3F7F // Zero-cross detect circuit is enabled at POR.
10633 #define _ZCD_OFF 0x3FFF // Zero-cross detect circuit is disabled at POR.
10634 #define _PLLEN_OFF 0x3EFF // 4x PLL is enabled when software sets the SPLLEN bit.
10635 #define _PLLEN_ON 0x3FFF // 4x PLL is always enabled.
10636 #define _STVREN_OFF 0x3DFF // Stack Overflow or Underflow will not cause a Reset.
10637 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
10638 #define _BORV_HI 0x3BFF // Brown-out Reset Voltage (Vbor), high trip point selected.
10639 #define _BORV_LO 0x3FFF // Brown-out Reset Voltage (Vbor), low trip point selected.
10640 #define _LPBOR_ON 0x37FF // Low-Power BOR is enabled.
10641 #define _LPBOR_OFF 0x3FFF // Low-Power BOR is disabled.
10642 #define _DEBUG_ON 0x2FFF // In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger.
10643 #define _DEBUG_OFF 0x3FFF // In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins.
10644 #define _LVP_OFF 0x1FFF // High-voltage on MCLR/VPP must be used for programming.
10645 #define _LVP_ON 0x3FFF // Low-voltage programming enabled.
10647 //==============================================================================
10649 #define _DEVID1 0x8006
10651 #define _IDLOC0 0x8000
10652 #define _IDLOC1 0x8001
10653 #define _IDLOC2 0x8002
10654 #define _IDLOC3 0x8003
10656 //==============================================================================
10658 #ifndef NO_BIT_DEFINES
10660 #define ADON ADCON0bits.ADON // bit 0
10661 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
10662 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
10663 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
10664 #define CHS0 ADCON0bits.CHS0 // bit 2
10665 #define CHS1 ADCON0bits.CHS1 // bit 3
10666 #define CHS2 ADCON0bits.CHS2 // bit 4
10667 #define CHS3 ADCON0bits.CHS3 // bit 5
10668 #define CHS4 ADCON0bits.CHS4 // bit 6
10670 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
10671 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
10672 #define ADNREF ADCON1bits.ADNREF // bit 2
10673 #define ADFM ADCON1bits.ADFM // bit 7
10675 #define TRIGSEL0 ADCON2bits.TRIGSEL0 // bit 3
10676 #define TRIGSEL1 ADCON2bits.TRIGSEL1 // bit 4
10677 #define TRIGSEL2 ADCON2bits.TRIGSEL2 // bit 5
10678 #define TRIGSEL3 ADCON2bits.TRIGSEL3 // bit 6
10679 #define TRIGSEL4 ADCON2bits.TRIGSEL4 // bit 7
10681 #define ANSA0 ANSELAbits.ANSA0 // bit 0
10682 #define ANSA1 ANSELAbits.ANSA1 // bit 1
10683 #define ANSA2 ANSELAbits.ANSA2 // bit 2
10684 #define ANSA4 ANSELAbits.ANSA4 // bit 4
10686 #define ANSC0 ANSELCbits.ANSC0 // bit 0
10687 #define ANSC1 ANSELCbits.ANSC1 // bit 1
10688 #define ANSC2 ANSELCbits.ANSC2 // bit 2
10689 #define ANSC3 ANSELCbits.ANSC3 // bit 3
10691 #define ABDEN BAUD1CONbits.ABDEN // bit 0
10692 #define WUE BAUD1CONbits.WUE // bit 1
10693 #define BRG16 BAUD1CONbits.BRG16 // bit 3
10694 #define SCKP BAUD1CONbits.SCKP // bit 4
10695 #define RCIDL BAUD1CONbits.RCIDL // bit 6
10696 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
10698 #define BORRDY BORCONbits.BORRDY // bit 0
10699 #define BORFS BORCONbits.BORFS // bit 6
10700 #define SBOREN BORCONbits.SBOREN // bit 7
10702 #define BSR0 BSRbits.BSR0 // bit 0
10703 #define BSR1 BSRbits.BSR1 // bit 1
10704 #define BSR2 BSRbits.BSR2 // bit 2
10705 #define BSR3 BSRbits.BSR3 // bit 3
10706 #define BSR4 BSRbits.BSR4 // bit 4
10708 #define CTS0 CCP1CAPbits.CTS0 // bit 0, shadows bit in CCP1CAPbits
10709 #define CCP1CTS0 CCP1CAPbits.CCP1CTS0 // bit 0, shadows bit in CCP1CAPbits
10710 #define CTS1 CCP1CAPbits.CTS1 // bit 1, shadows bit in CCP1CAPbits
10711 #define CCP1CTS1 CCP1CAPbits.CCP1CTS1 // bit 1, shadows bit in CCP1CAPbits
10712 #define CTS2 CCP1CAPbits.CTS2 // bit 2, shadows bit in CCP1CAPbits
10713 #define CCP1CTS2 CCP1CAPbits.CCP1CTS2 // bit 2, shadows bit in CCP1CAPbits
10715 #define MODE0 CCP1CONbits.MODE0 // bit 0, shadows bit in CCP1CONbits
10716 #define CCP1MODE0 CCP1CONbits.CCP1MODE0 // bit 0, shadows bit in CCP1CONbits
10717 #define MODE1 CCP1CONbits.MODE1 // bit 1, shadows bit in CCP1CONbits
10718 #define CCP1MODE1 CCP1CONbits.CCP1MODE1 // bit 1, shadows bit in CCP1CONbits
10719 #define MODE2 CCP1CONbits.MODE2 // bit 2, shadows bit in CCP1CONbits
10720 #define CCP1MODE2 CCP1CONbits.CCP1MODE2 // bit 2, shadows bit in CCP1CONbits
10721 #define MODE3 CCP1CONbits.MODE3 // bit 3, shadows bit in CCP1CONbits
10722 #define CCP1MODE3 CCP1CONbits.CCP1MODE3 // bit 3, shadows bit in CCP1CONbits
10723 #define FMT CCP1CONbits.FMT // bit 4, shadows bit in CCP1CONbits
10724 #define CCP1FMT CCP1CONbits.CCP1FMT // bit 4, shadows bit in CCP1CONbits
10725 #define OUT CCP1CONbits.OUT // bit 5, shadows bit in CCP1CONbits
10726 #define CCP1OUT CCP1CONbits.CCP1OUT // bit 5, shadows bit in CCP1CONbits
10727 #define EN CCP1CONbits.EN // bit 7, shadows bit in CCP1CONbits
10728 #define CCP1EN CCP1CONbits.CCP1EN // bit 7, shadows bit in CCP1CONbits
10730 #define C1TSEL0 CCPTMRSbits.C1TSEL0 // bit 0
10731 #define C1TSEL1 CCPTMRSbits.C1TSEL1 // bit 1
10732 #define P3TSEL0 CCPTMRSbits.P3TSEL0 // bit 4
10733 #define P3TSEL1 CCPTMRSbits.P3TSEL1 // bit 5
10735 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
10736 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
10737 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
10738 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
10739 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
10740 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
10741 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
10742 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
10743 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
10744 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
10745 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
10746 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
10747 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
10748 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
10749 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
10750 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
10752 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
10753 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
10754 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
10755 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
10756 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
10757 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
10758 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
10759 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
10760 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
10761 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
10762 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
10763 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
10764 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
10765 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
10766 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
10767 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
10769 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
10770 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
10771 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
10772 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
10773 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
10774 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
10775 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
10776 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
10777 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
10778 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
10780 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
10781 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
10782 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
10783 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
10784 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
10785 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
10786 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
10787 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
10788 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
10789 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
10791 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
10792 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
10793 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
10794 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
10795 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
10796 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
10797 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
10798 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
10799 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
10800 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
10802 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
10803 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
10804 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
10805 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
10806 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
10807 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
10808 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
10809 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
10810 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
10811 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
10813 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
10814 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
10815 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
10816 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
10817 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
10818 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
10819 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
10820 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
10821 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
10822 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
10824 #define MCLC1OUT CLCDATAbits.MCLC1OUT // bit 0
10825 #define MCLC2OUT CLCDATAbits.MCLC2OUT // bit 1
10826 #define MCLC3OUT CLCDATAbits.MCLC3OUT // bit 2
10828 #define NCH0 CM1NSELbits.NCH0 // bit 0, shadows bit in CM1NSELbits
10829 #define C1NCH0 CM1NSELbits.C1NCH0 // bit 0, shadows bit in CM1NSELbits
10830 #define NCH1 CM1NSELbits.NCH1 // bit 1, shadows bit in CM1NSELbits
10831 #define C1NCH1 CM1NSELbits.C1NCH1 // bit 1, shadows bit in CM1NSELbits
10832 #define NCH2 CM1NSELbits.NCH2 // bit 2, shadows bit in CM1NSELbits
10833 #define C1NCH2 CM1NSELbits.C1NCH2 // bit 2, shadows bit in CM1NSELbits
10835 #define PCH0 CM1PSELbits.PCH0 // bit 0, shadows bit in CM1PSELbits
10836 #define C1PCH0 CM1PSELbits.C1PCH0 // bit 0, shadows bit in CM1PSELbits
10837 #define PCH1 CM1PSELbits.PCH1 // bit 1, shadows bit in CM1PSELbits
10838 #define C1PCH1 CM1PSELbits.C1PCH1 // bit 1, shadows bit in CM1PSELbits
10839 #define PCH2 CM1PSELbits.PCH2 // bit 2, shadows bit in CM1PSELbits
10840 #define C1PCH2 CM1PSELbits.C1PCH2 // bit 2, shadows bit in CM1PSELbits
10841 #define PCH3 CM1PSELbits.PCH3 // bit 3, shadows bit in CM1PSELbits
10842 #define C1PCH3 CM1PSELbits.C1PCH3 // bit 3, shadows bit in CM1PSELbits
10844 #define MC1OUT CMOUTbits.MC1OUT // bit 0
10845 #define MC2OUT CMOUTbits.MC2OUT // bit 1
10847 #define ASDAC0 COG1ASD0bits.ASDAC0 // bit 2, shadows bit in COG1ASD0bits
10848 #define G1ASDAC0 COG1ASD0bits.G1ASDAC0 // bit 2, shadows bit in COG1ASD0bits
10849 #define ASDAC1 COG1ASD0bits.ASDAC1 // bit 3, shadows bit in COG1ASD0bits
10850 #define G1ASDAC1 COG1ASD0bits.G1ASDAC1 // bit 3, shadows bit in COG1ASD0bits
10851 #define ASDBD0 COG1ASD0bits.ASDBD0 // bit 4, shadows bit in COG1ASD0bits
10852 #define G1ASDBD0 COG1ASD0bits.G1ASDBD0 // bit 4, shadows bit in COG1ASD0bits
10853 #define ASDBD1 COG1ASD0bits.ASDBD1 // bit 5, shadows bit in COG1ASD0bits
10854 #define G1ASDBD1 COG1ASD0bits.G1ASDBD1 // bit 5, shadows bit in COG1ASD0bits
10855 #define ASREN COG1ASD0bits.ASREN // bit 6, shadows bit in COG1ASD0bits
10856 #define ARSEN COG1ASD0bits.ARSEN // bit 6, shadows bit in COG1ASD0bits
10857 #define G1ARSEN COG1ASD0bits.G1ARSEN // bit 6, shadows bit in COG1ASD0bits
10858 #define G1ASREN COG1ASD0bits.G1ASREN // bit 6, shadows bit in COG1ASD0bits
10859 #define ASE COG1ASD0bits.ASE // bit 7, shadows bit in COG1ASD0bits
10860 #define G1ASE COG1ASD0bits.G1ASE // bit 7, shadows bit in COG1ASD0bits
10862 #define AS0E COG1ASD1bits.AS0E // bit 0, shadows bit in COG1ASD1bits
10863 #define G1AS0E COG1ASD1bits.G1AS0E // bit 0, shadows bit in COG1ASD1bits
10864 #define AS1E COG1ASD1bits.AS1E // bit 1, shadows bit in COG1ASD1bits
10865 #define G1AS1E COG1ASD1bits.G1AS1E // bit 1, shadows bit in COG1ASD1bits
10866 #define AS2E COG1ASD1bits.AS2E // bit 2, shadows bit in COG1ASD1bits
10867 #define G1AS2E COG1ASD1bits.G1AS2E // bit 2, shadows bit in COG1ASD1bits
10868 #define AS3E COG1ASD1bits.AS3E // bit 3, shadows bit in COG1ASD1bits
10869 #define G1AS3E COG1ASD1bits.G1AS3E // bit 3, shadows bit in COG1ASD1bits
10870 #define AS4E COG1ASD1bits.AS4E // bit 4, shadows bit in COG1ASD1bits
10871 #define G1AS4E COG1ASD1bits.G1AS4E // bit 4, shadows bit in COG1ASD1bits
10872 #define AS5E COG1ASD1bits.AS5E // bit 5, shadows bit in COG1ASD1bits
10873 #define G1AS5E COG1ASD1bits.G1AS5E // bit 5, shadows bit in COG1ASD1bits
10874 #define AS6E COG1ASD1bits.AS6E // bit 6, shadows bit in COG1ASD1bits
10875 #define G1AS6E COG1ASD1bits.G1AS6E // bit 6, shadows bit in COG1ASD1bits
10876 #define AS7E COG1ASD1bits.AS7E // bit 7, shadows bit in COG1ASD1bits
10877 #define G1AS7E COG1ASD1bits.G1AS7E // bit 7, shadows bit in COG1ASD1bits
10879 #define BLKF0 COG1BLKFbits.BLKF0 // bit 0, shadows bit in COG1BLKFbits
10880 #define G1BLKF0 COG1BLKFbits.G1BLKF0 // bit 0, shadows bit in COG1BLKFbits
10881 #define BLKF1 COG1BLKFbits.BLKF1 // bit 1, shadows bit in COG1BLKFbits
10882 #define G1BLKF1 COG1BLKFbits.G1BLKF1 // bit 1, shadows bit in COG1BLKFbits
10883 #define BLKF2 COG1BLKFbits.BLKF2 // bit 2, shadows bit in COG1BLKFbits
10884 #define G1BLKF2 COG1BLKFbits.G1BLKF2 // bit 2, shadows bit in COG1BLKFbits
10885 #define BLKF3 COG1BLKFbits.BLKF3 // bit 3, shadows bit in COG1BLKFbits
10886 #define G1BLKF3 COG1BLKFbits.G1BLKF3 // bit 3, shadows bit in COG1BLKFbits
10887 #define BLKF4 COG1BLKFbits.BLKF4 // bit 4, shadows bit in COG1BLKFbits
10888 #define G1BLKF4 COG1BLKFbits.G1BLKF4 // bit 4, shadows bit in COG1BLKFbits
10889 #define BLKF5 COG1BLKFbits.BLKF5 // bit 5, shadows bit in COG1BLKFbits
10890 #define G1BLKF5 COG1BLKFbits.G1BLKF5 // bit 5, shadows bit in COG1BLKFbits
10892 #define BLKR0 COG1BLKRbits.BLKR0 // bit 0, shadows bit in COG1BLKRbits
10893 #define G1BLKR0 COG1BLKRbits.G1BLKR0 // bit 0, shadows bit in COG1BLKRbits
10894 #define BLKR1 COG1BLKRbits.BLKR1 // bit 1, shadows bit in COG1BLKRbits
10895 #define G1BLKR1 COG1BLKRbits.G1BLKR1 // bit 1, shadows bit in COG1BLKRbits
10896 #define BLKR2 COG1BLKRbits.BLKR2 // bit 2, shadows bit in COG1BLKRbits
10897 #define G1BLKR2 COG1BLKRbits.G1BLKR2 // bit 2, shadows bit in COG1BLKRbits
10898 #define BLKR3 COG1BLKRbits.BLKR3 // bit 3, shadows bit in COG1BLKRbits
10899 #define G1BLKR3 COG1BLKRbits.G1BLKR3 // bit 3, shadows bit in COG1BLKRbits
10900 #define BLKR4 COG1BLKRbits.BLKR4 // bit 4, shadows bit in COG1BLKRbits
10901 #define G1BLKR4 COG1BLKRbits.G1BLKR4 // bit 4, shadows bit in COG1BLKRbits
10902 #define BLKR5 COG1BLKRbits.BLKR5 // bit 5, shadows bit in COG1BLKRbits
10903 #define G1BLKR5 COG1BLKRbits.G1BLKR5 // bit 5, shadows bit in COG1BLKRbits
10905 #define POLA COG1CON1bits.POLA // bit 0, shadows bit in COG1CON1bits
10906 #define G1POLA COG1CON1bits.G1POLA // bit 0, shadows bit in COG1CON1bits
10907 #define POLB COG1CON1bits.POLB // bit 1, shadows bit in COG1CON1bits
10908 #define G1POLB COG1CON1bits.G1POLB // bit 1, shadows bit in COG1CON1bits
10909 #define POLC COG1CON1bits.POLC // bit 2, shadows bit in COG1CON1bits
10910 #define G1POLC COG1CON1bits.G1POLC // bit 2, shadows bit in COG1CON1bits
10911 #define POLD COG1CON1bits.POLD // bit 3, shadows bit in COG1CON1bits
10912 #define G1POLD COG1CON1bits.G1POLD // bit 3, shadows bit in COG1CON1bits
10913 #define FDBS COG1CON1bits.FDBS // bit 6, shadows bit in COG1CON1bits
10914 #define G1FDBS COG1CON1bits.G1FDBS // bit 6, shadows bit in COG1CON1bits
10915 #define RDBS COG1CON1bits.RDBS // bit 7, shadows bit in COG1CON1bits
10916 #define G1RDBS COG1CON1bits.G1RDBS // bit 7, shadows bit in COG1CON1bits
10918 #define DBF0 COG1DBFbits.DBF0 // bit 0, shadows bit in COG1DBFbits
10919 #define G1DBF0 COG1DBFbits.G1DBF0 // bit 0, shadows bit in COG1DBFbits
10920 #define DBF1 COG1DBFbits.DBF1 // bit 1, shadows bit in COG1DBFbits
10921 #define G1DBF1 COG1DBFbits.G1DBF1 // bit 1, shadows bit in COG1DBFbits
10922 #define DBF2 COG1DBFbits.DBF2 // bit 2, shadows bit in COG1DBFbits
10923 #define G1DBF2 COG1DBFbits.G1DBF2 // bit 2, shadows bit in COG1DBFbits
10924 #define DBF3 COG1DBFbits.DBF3 // bit 3, shadows bit in COG1DBFbits
10925 #define G1DBF3 COG1DBFbits.G1DBF3 // bit 3, shadows bit in COG1DBFbits
10926 #define DBF4 COG1DBFbits.DBF4 // bit 4, shadows bit in COG1DBFbits
10927 #define G1DBF4 COG1DBFbits.G1DBF4 // bit 4, shadows bit in COG1DBFbits
10928 #define DBF5 COG1DBFbits.DBF5 // bit 5, shadows bit in COG1DBFbits
10929 #define G1DBF5 COG1DBFbits.G1DBF5 // bit 5, shadows bit in COG1DBFbits
10931 #define DBR0 COG1DBRbits.DBR0 // bit 0, shadows bit in COG1DBRbits
10932 #define G1DBR0 COG1DBRbits.G1DBR0 // bit 0, shadows bit in COG1DBRbits
10933 #define DBR1 COG1DBRbits.DBR1 // bit 1, shadows bit in COG1DBRbits
10934 #define G1DBR1 COG1DBRbits.G1DBR1 // bit 1, shadows bit in COG1DBRbits
10935 #define DBR2 COG1DBRbits.DBR2 // bit 2, shadows bit in COG1DBRbits
10936 #define G1DBR2 COG1DBRbits.G1DBR2 // bit 2, shadows bit in COG1DBRbits
10937 #define DBR3 COG1DBRbits.DBR3 // bit 3, shadows bit in COG1DBRbits
10938 #define G1DBR3 COG1DBRbits.G1DBR3 // bit 3, shadows bit in COG1DBRbits
10939 #define DBR4 COG1DBRbits.DBR4 // bit 4, shadows bit in COG1DBRbits
10940 #define G1DBR4 COG1DBRbits.G1DBR4 // bit 4, shadows bit in COG1DBRbits
10941 #define DBR5 COG1DBRbits.DBR5 // bit 5, shadows bit in COG1DBRbits
10942 #define G1DBR5 COG1DBRbits.G1DBR5 // bit 5, shadows bit in COG1DBRbits
10944 #define FIS0 COG1FIS0bits.FIS0 // bit 0, shadows bit in COG1FIS0bits
10945 #define G1FIS0 COG1FIS0bits.G1FIS0 // bit 0, shadows bit in COG1FIS0bits
10946 #define FIS1 COG1FIS0bits.FIS1 // bit 1, shadows bit in COG1FIS0bits
10947 #define G1FIS1 COG1FIS0bits.G1FIS1 // bit 1, shadows bit in COG1FIS0bits
10948 #define FIS2 COG1FIS0bits.FIS2 // bit 2, shadows bit in COG1FIS0bits
10949 #define G1FIS2 COG1FIS0bits.G1FIS2 // bit 2, shadows bit in COG1FIS0bits
10950 #define FIS3 COG1FIS0bits.FIS3 // bit 3, shadows bit in COG1FIS0bits
10951 #define G1FIS3 COG1FIS0bits.G1FIS3 // bit 3, shadows bit in COG1FIS0bits
10952 #define FIS4 COG1FIS0bits.FIS4 // bit 4, shadows bit in COG1FIS0bits
10953 #define G1FIS4 COG1FIS0bits.G1FIS4 // bit 4, shadows bit in COG1FIS0bits
10954 #define FIS5 COG1FIS0bits.FIS5 // bit 5, shadows bit in COG1FIS0bits
10955 #define G1FIS5 COG1FIS0bits.G1FIS5 // bit 5, shadows bit in COG1FIS0bits
10956 #define FIS6 COG1FIS0bits.FIS6 // bit 6, shadows bit in COG1FIS0bits
10957 #define G1FIS6 COG1FIS0bits.G1FIS6 // bit 6, shadows bit in COG1FIS0bits
10958 #define FIS7 COG1FIS0bits.FIS7 // bit 7, shadows bit in COG1FIS0bits
10959 #define G1FIS7 COG1FIS0bits.G1FIS7 // bit 7, shadows bit in COG1FIS0bits
10961 #define FIS8 COG1FIS1bits.FIS8 // bit 0, shadows bit in COG1FIS1bits
10962 #define G1FIS8 COG1FIS1bits.G1FIS8 // bit 0, shadows bit in COG1FIS1bits
10963 #define FIS9 COG1FIS1bits.FIS9 // bit 1, shadows bit in COG1FIS1bits
10964 #define G1FIS9 COG1FIS1bits.G1FIS9 // bit 1, shadows bit in COG1FIS1bits
10965 #define FIS10 COG1FIS1bits.FIS10 // bit 2, shadows bit in COG1FIS1bits
10966 #define G1FIS10 COG1FIS1bits.G1FIS10 // bit 2, shadows bit in COG1FIS1bits
10967 #define FIS11 COG1FIS1bits.FIS11 // bit 3, shadows bit in COG1FIS1bits
10968 #define G1FIS11 COG1FIS1bits.G1FIS11 // bit 3, shadows bit in COG1FIS1bits
10969 #define FIS12 COG1FIS1bits.FIS12 // bit 4, shadows bit in COG1FIS1bits
10970 #define G1FIS12 COG1FIS1bits.G1FIS12 // bit 4, shadows bit in COG1FIS1bits
10971 #define FIS13 COG1FIS1bits.FIS13 // bit 5, shadows bit in COG1FIS1bits
10972 #define G1FIS13 COG1FIS1bits.G1FIS13 // bit 5, shadows bit in COG1FIS1bits
10973 #define FIS14 COG1FIS1bits.FIS14 // bit 6, shadows bit in COG1FIS1bits
10974 #define G1FIS14 COG1FIS1bits.G1FIS14 // bit 6, shadows bit in COG1FIS1bits
10976 #define FSIM0 COG1FSIM0bits.FSIM0 // bit 0, shadows bit in COG1FSIM0bits
10977 #define G1FSIM0 COG1FSIM0bits.G1FSIM0 // bit 0, shadows bit in COG1FSIM0bits
10978 #define FSIM1 COG1FSIM0bits.FSIM1 // bit 1, shadows bit in COG1FSIM0bits
10979 #define G1FSIM1 COG1FSIM0bits.G1FSIM1 // bit 1, shadows bit in COG1FSIM0bits
10980 #define FSIM2 COG1FSIM0bits.FSIM2 // bit 2, shadows bit in COG1FSIM0bits
10981 #define G1FSIM2 COG1FSIM0bits.G1FSIM2 // bit 2, shadows bit in COG1FSIM0bits
10982 #define FSIM3 COG1FSIM0bits.FSIM3 // bit 3, shadows bit in COG1FSIM0bits
10983 #define G1FSIM3 COG1FSIM0bits.G1FSIM3 // bit 3, shadows bit in COG1FSIM0bits
10984 #define FSIM4 COG1FSIM0bits.FSIM4 // bit 4, shadows bit in COG1FSIM0bits
10985 #define G1FSIM4 COG1FSIM0bits.G1FSIM4 // bit 4, shadows bit in COG1FSIM0bits
10986 #define FSIM5 COG1FSIM0bits.FSIM5 // bit 5, shadows bit in COG1FSIM0bits
10987 #define G1FSIM5 COG1FSIM0bits.G1FSIM5 // bit 5, shadows bit in COG1FSIM0bits
10988 #define FSIM6 COG1FSIM0bits.FSIM6 // bit 6, shadows bit in COG1FSIM0bits
10989 #define G1FSIM6 COG1FSIM0bits.G1FSIM6 // bit 6, shadows bit in COG1FSIM0bits
10990 #define FSIM7 COG1FSIM0bits.FSIM7 // bit 7, shadows bit in COG1FSIM0bits
10991 #define G1FSIM7 COG1FSIM0bits.G1FSIM7 // bit 7, shadows bit in COG1FSIM0bits
10993 #define FSIM8 COG1FSIM1bits.FSIM8 // bit 0, shadows bit in COG1FSIM1bits
10994 #define G1FSIM8 COG1FSIM1bits.G1FSIM8 // bit 0, shadows bit in COG1FSIM1bits
10995 #define FSIM9 COG1FSIM1bits.FSIM9 // bit 1, shadows bit in COG1FSIM1bits
10996 #define G1FSIM9 COG1FSIM1bits.G1FSIM9 // bit 1, shadows bit in COG1FSIM1bits
10997 #define FSIM10 COG1FSIM1bits.FSIM10 // bit 2, shadows bit in COG1FSIM1bits
10998 #define G1FSIM10 COG1FSIM1bits.G1FSIM10 // bit 2, shadows bit in COG1FSIM1bits
10999 #define FSIM11 COG1FSIM1bits.FSIM11 // bit 3, shadows bit in COG1FSIM1bits
11000 #define G1FSIM11 COG1FSIM1bits.G1FSIM11 // bit 3, shadows bit in COG1FSIM1bits
11001 #define FSIM12 COG1FSIM1bits.FSIM12 // bit 4, shadows bit in COG1FSIM1bits
11002 #define G1FSIM12 COG1FSIM1bits.G1FSIM12 // bit 4, shadows bit in COG1FSIM1bits
11003 #define FSIM13 COG1FSIM1bits.FSIM13 // bit 5, shadows bit in COG1FSIM1bits
11004 #define G1FSIM13 COG1FSIM1bits.G1FSIM13 // bit 5, shadows bit in COG1FSIM1bits
11005 #define FSIM14 COG1FSIM1bits.FSIM14 // bit 6, shadows bit in COG1FSIM1bits
11006 #define G1FSIM14 COG1FSIM1bits.G1FSIM14 // bit 6, shadows bit in COG1FSIM1bits
11008 #define PHF0 COG1PHFbits.PHF0 // bit 0, shadows bit in COG1PHFbits
11009 #define G1PHF0 COG1PHFbits.G1PHF0 // bit 0, shadows bit in COG1PHFbits
11010 #define PHF1 COG1PHFbits.PHF1 // bit 1, shadows bit in COG1PHFbits
11011 #define G1PHF1 COG1PHFbits.G1PHF1 // bit 1, shadows bit in COG1PHFbits
11012 #define PHF2 COG1PHFbits.PHF2 // bit 2, shadows bit in COG1PHFbits
11013 #define G1PHF2 COG1PHFbits.G1PHF2 // bit 2, shadows bit in COG1PHFbits
11014 #define PHF3 COG1PHFbits.PHF3 // bit 3, shadows bit in COG1PHFbits
11015 #define G1PHF3 COG1PHFbits.G1PHF3 // bit 3, shadows bit in COG1PHFbits
11016 #define PHF4 COG1PHFbits.PHF4 // bit 4, shadows bit in COG1PHFbits
11017 #define G1PHF4 COG1PHFbits.G1PHF4 // bit 4, shadows bit in COG1PHFbits
11018 #define PHF5 COG1PHFbits.PHF5 // bit 5, shadows bit in COG1PHFbits
11019 #define G1PHF5 COG1PHFbits.G1PHF5 // bit 5, shadows bit in COG1PHFbits
11021 #define PHR0 COG1PHRbits.PHR0 // bit 0, shadows bit in COG1PHRbits
11022 #define G1PHR0 COG1PHRbits.G1PHR0 // bit 0, shadows bit in COG1PHRbits
11023 #define PHR1 COG1PHRbits.PHR1 // bit 1, shadows bit in COG1PHRbits
11024 #define G1PHR1 COG1PHRbits.G1PHR1 // bit 1, shadows bit in COG1PHRbits
11025 #define PHR2 COG1PHRbits.PHR2 // bit 2, shadows bit in COG1PHRbits
11026 #define G1PHR2 COG1PHRbits.G1PHR2 // bit 2, shadows bit in COG1PHRbits
11027 #define PHR3 COG1PHRbits.PHR3 // bit 3, shadows bit in COG1PHRbits
11028 #define G1PHR3 COG1PHRbits.G1PHR3 // bit 3, shadows bit in COG1PHRbits
11029 #define PHR4 COG1PHRbits.PHR4 // bit 4, shadows bit in COG1PHRbits
11030 #define G1PHR4 COG1PHRbits.G1PHR4 // bit 4, shadows bit in COG1PHRbits
11031 #define PHR5 COG1PHRbits.PHR5 // bit 5, shadows bit in COG1PHRbits
11032 #define G1PHR5 COG1PHRbits.G1PHR5 // bit 5, shadows bit in COG1PHRbits
11034 #define RIS0 COG1RIS0bits.RIS0 // bit 0, shadows bit in COG1RIS0bits
11035 #define G1RIS0 COG1RIS0bits.G1RIS0 // bit 0, shadows bit in COG1RIS0bits
11036 #define RIS1 COG1RIS0bits.RIS1 // bit 1, shadows bit in COG1RIS0bits
11037 #define G1RIS1 COG1RIS0bits.G1RIS1 // bit 1, shadows bit in COG1RIS0bits
11038 #define RIS2 COG1RIS0bits.RIS2 // bit 2, shadows bit in COG1RIS0bits
11039 #define G1RIS2 COG1RIS0bits.G1RIS2 // bit 2, shadows bit in COG1RIS0bits
11040 #define RIS3 COG1RIS0bits.RIS3 // bit 3, shadows bit in COG1RIS0bits
11041 #define G1RIS3 COG1RIS0bits.G1RIS3 // bit 3, shadows bit in COG1RIS0bits
11042 #define RIS4 COG1RIS0bits.RIS4 // bit 4, shadows bit in COG1RIS0bits
11043 #define G1RIS4 COG1RIS0bits.G1RIS4 // bit 4, shadows bit in COG1RIS0bits
11044 #define RIS5 COG1RIS0bits.RIS5 // bit 5, shadows bit in COG1RIS0bits
11045 #define G1RIS5 COG1RIS0bits.G1RIS5 // bit 5, shadows bit in COG1RIS0bits
11046 #define RIS6 COG1RIS0bits.RIS6 // bit 6, shadows bit in COG1RIS0bits
11047 #define G1RIS6 COG1RIS0bits.G1RIS6 // bit 6, shadows bit in COG1RIS0bits
11048 #define RIS7 COG1RIS0bits.RIS7 // bit 7, shadows bit in COG1RIS0bits
11049 #define G1RIS7 COG1RIS0bits.G1RIS7 // bit 7, shadows bit in COG1RIS0bits
11051 #define RIS8 COG1RIS1bits.RIS8 // bit 0, shadows bit in COG1RIS1bits
11052 #define G1RIS8 COG1RIS1bits.G1RIS8 // bit 0, shadows bit in COG1RIS1bits
11053 #define RIS9 COG1RIS1bits.RIS9 // bit 1, shadows bit in COG1RIS1bits
11054 #define G1RIS9 COG1RIS1bits.G1RIS9 // bit 1, shadows bit in COG1RIS1bits
11055 #define RIS10 COG1RIS1bits.RIS10 // bit 2, shadows bit in COG1RIS1bits
11056 #define G1RIS10 COG1RIS1bits.G1RIS10 // bit 2, shadows bit in COG1RIS1bits
11057 #define RIS11 COG1RIS1bits.RIS11 // bit 3, shadows bit in COG1RIS1bits
11058 #define G1RIS11 COG1RIS1bits.G1RIS11 // bit 3, shadows bit in COG1RIS1bits
11059 #define RIS12 COG1RIS1bits.RIS12 // bit 4, shadows bit in COG1RIS1bits
11060 #define G1RIS12 COG1RIS1bits.G1RIS12 // bit 4, shadows bit in COG1RIS1bits
11061 #define RIS13 COG1RIS1bits.RIS13 // bit 5, shadows bit in COG1RIS1bits
11062 #define G1RIS13 COG1RIS1bits.G1RIS13 // bit 5, shadows bit in COG1RIS1bits
11063 #define RIS14 COG1RIS1bits.RIS14 // bit 6, shadows bit in COG1RIS1bits
11064 #define G1RIS14 COG1RIS1bits.G1RIS14 // bit 6, shadows bit in COG1RIS1bits
11066 #define RSIM0 COG1RSIM0bits.RSIM0 // bit 0, shadows bit in COG1RSIM0bits
11067 #define G1RSIM0 COG1RSIM0bits.G1RSIM0 // bit 0, shadows bit in COG1RSIM0bits
11068 #define RSIM1 COG1RSIM0bits.RSIM1 // bit 1, shadows bit in COG1RSIM0bits
11069 #define G1RSIM1 COG1RSIM0bits.G1RSIM1 // bit 1, shadows bit in COG1RSIM0bits
11070 #define RSIM2 COG1RSIM0bits.RSIM2 // bit 2, shadows bit in COG1RSIM0bits
11071 #define G1RSIM2 COG1RSIM0bits.G1RSIM2 // bit 2, shadows bit in COG1RSIM0bits
11072 #define RSIM3 COG1RSIM0bits.RSIM3 // bit 3, shadows bit in COG1RSIM0bits
11073 #define G1RSIM3 COG1RSIM0bits.G1RSIM3 // bit 3, shadows bit in COG1RSIM0bits
11074 #define RSIM4 COG1RSIM0bits.RSIM4 // bit 4, shadows bit in COG1RSIM0bits
11075 #define G1RSIM4 COG1RSIM0bits.G1RSIM4 // bit 4, shadows bit in COG1RSIM0bits
11076 #define RSIM5 COG1RSIM0bits.RSIM5 // bit 5, shadows bit in COG1RSIM0bits
11077 #define G1RSIM5 COG1RSIM0bits.G1RSIM5 // bit 5, shadows bit in COG1RSIM0bits
11078 #define RSIM6 COG1RSIM0bits.RSIM6 // bit 6, shadows bit in COG1RSIM0bits
11079 #define G1RSIM6 COG1RSIM0bits.G1RSIM6 // bit 6, shadows bit in COG1RSIM0bits
11080 #define RSIM7 COG1RSIM0bits.RSIM7 // bit 7, shadows bit in COG1RSIM0bits
11081 #define G1RSIM7 COG1RSIM0bits.G1RSIM7 // bit 7, shadows bit in COG1RSIM0bits
11083 #define RSIM8 COG1RSIM1bits.RSIM8 // bit 0, shadows bit in COG1RSIM1bits
11084 #define G1RSIM8 COG1RSIM1bits.G1RSIM8 // bit 0, shadows bit in COG1RSIM1bits
11085 #define RSIM9 COG1RSIM1bits.RSIM9 // bit 1, shadows bit in COG1RSIM1bits
11086 #define G1RSIM9 COG1RSIM1bits.G1RSIM9 // bit 1, shadows bit in COG1RSIM1bits
11087 #define RSIM10 COG1RSIM1bits.RSIM10 // bit 2, shadows bit in COG1RSIM1bits
11088 #define G1RSIM10 COG1RSIM1bits.G1RSIM10 // bit 2, shadows bit in COG1RSIM1bits
11089 #define RSIM11 COG1RSIM1bits.RSIM11 // bit 3, shadows bit in COG1RSIM1bits
11090 #define G1RSIM11 COG1RSIM1bits.G1RSIM11 // bit 3, shadows bit in COG1RSIM1bits
11091 #define RSIM12 COG1RSIM1bits.RSIM12 // bit 4, shadows bit in COG1RSIM1bits
11092 #define G1RSIM12 COG1RSIM1bits.G1RSIM12 // bit 4, shadows bit in COG1RSIM1bits
11093 #define RSIM13 COG1RSIM1bits.RSIM13 // bit 5, shadows bit in COG1RSIM1bits
11094 #define G1RSIM13 COG1RSIM1bits.G1RSIM13 // bit 5, shadows bit in COG1RSIM1bits
11095 #define RSIM14 COG1RSIM1bits.RSIM14 // bit 6, shadows bit in COG1RSIM1bits
11096 #define G1RSIM14 COG1RSIM1bits.G1RSIM14 // bit 6, shadows bit in COG1RSIM1bits
11098 #define STRA COG1STRbits.STRA // bit 0, shadows bit in COG1STRbits
11099 #define G1STRA COG1STRbits.G1STRA // bit 0, shadows bit in COG1STRbits
11100 #define STRB COG1STRbits.STRB // bit 1, shadows bit in COG1STRbits
11101 #define G1STRB COG1STRbits.G1STRB // bit 1, shadows bit in COG1STRbits
11102 #define STRC COG1STRbits.STRC // bit 2, shadows bit in COG1STRbits
11103 #define G1STRC COG1STRbits.G1STRC // bit 2, shadows bit in COG1STRbits
11104 #define STRD COG1STRbits.STRD // bit 3, shadows bit in COG1STRbits
11105 #define G1STRD COG1STRbits.G1STRD // bit 3, shadows bit in COG1STRbits
11106 #define SDATA COG1STRbits.SDATA // bit 4, shadows bit in COG1STRbits
11107 #define G1SDATA COG1STRbits.G1SDATA // bit 4, shadows bit in COG1STRbits
11108 #define SDATB COG1STRbits.SDATB // bit 5, shadows bit in COG1STRbits
11109 #define G1SDATB COG1STRbits.G1SDATB // bit 5, shadows bit in COG1STRbits
11110 #define SDATC COG1STRbits.SDATC // bit 6, shadows bit in COG1STRbits
11111 #define G1SDATC COG1STRbits.G1SDATC // bit 6, shadows bit in COG1STRbits
11112 #define SDATD COG1STRbits.SDATD // bit 7, shadows bit in COG1STRbits
11113 #define G1SDATD COG1STRbits.G1SDATD // bit 7, shadows bit in COG1STRbits
11115 #define REF0 DAC1CON1bits.REF0 // bit 0, shadows bit in DAC1CON1bits
11116 #define DAC1REF0 DAC1CON1bits.DAC1REF0 // bit 0, shadows bit in DAC1CON1bits
11117 #define R0 DAC1CON1bits.R0 // bit 0, shadows bit in DAC1CON1bits
11118 #define DAC1R0 DAC1CON1bits.DAC1R0 // bit 0, shadows bit in DAC1CON1bits
11119 #define REF1 DAC1CON1bits.REF1 // bit 1, shadows bit in DAC1CON1bits
11120 #define DAC1REF1 DAC1CON1bits.DAC1REF1 // bit 1, shadows bit in DAC1CON1bits
11121 #define R1 DAC1CON1bits.R1 // bit 1, shadows bit in DAC1CON1bits
11122 #define DAC1R1 DAC1CON1bits.DAC1R1 // bit 1, shadows bit in DAC1CON1bits
11123 #define REF2 DAC1CON1bits.REF2 // bit 2, shadows bit in DAC1CON1bits
11124 #define DAC1REF2 DAC1CON1bits.DAC1REF2 // bit 2, shadows bit in DAC1CON1bits
11125 #define R2 DAC1CON1bits.R2 // bit 2, shadows bit in DAC1CON1bits
11126 #define DAC1R2 DAC1CON1bits.DAC1R2 // bit 2, shadows bit in DAC1CON1bits
11127 #define REF3 DAC1CON1bits.REF3 // bit 3, shadows bit in DAC1CON1bits
11128 #define DAC1REF3 DAC1CON1bits.DAC1REF3 // bit 3, shadows bit in DAC1CON1bits
11129 #define R3 DAC1CON1bits.R3 // bit 3, shadows bit in DAC1CON1bits
11130 #define DAC1R3 DAC1CON1bits.DAC1R3 // bit 3, shadows bit in DAC1CON1bits
11131 #define REF4 DAC1CON1bits.REF4 // bit 4, shadows bit in DAC1CON1bits
11132 #define DAC1REF4 DAC1CON1bits.DAC1REF4 // bit 4, shadows bit in DAC1CON1bits
11133 #define R4 DAC1CON1bits.R4 // bit 4, shadows bit in DAC1CON1bits
11134 #define DAC1R4 DAC1CON1bits.DAC1R4 // bit 4, shadows bit in DAC1CON1bits
11135 #define REF5 DAC1CON1bits.REF5 // bit 5, shadows bit in DAC1CON1bits
11136 #define DAC1REF5 DAC1CON1bits.DAC1REF5 // bit 5, shadows bit in DAC1CON1bits
11137 #define R5 DAC1CON1bits.R5 // bit 5, shadows bit in DAC1CON1bits
11138 #define DAC1R5 DAC1CON1bits.DAC1R5 // bit 5, shadows bit in DAC1CON1bits
11139 #define REF6 DAC1CON1bits.REF6 // bit 6, shadows bit in DAC1CON1bits
11140 #define DAC1REF6 DAC1CON1bits.DAC1REF6 // bit 6, shadows bit in DAC1CON1bits
11141 #define R6 DAC1CON1bits.R6 // bit 6, shadows bit in DAC1CON1bits
11142 #define DAC1R6 DAC1CON1bits.DAC1R6 // bit 6, shadows bit in DAC1CON1bits
11143 #define REF7 DAC1CON1bits.REF7 // bit 7, shadows bit in DAC1CON1bits
11144 #define DAC1REF7 DAC1CON1bits.DAC1REF7 // bit 7, shadows bit in DAC1CON1bits
11145 #define R7 DAC1CON1bits.R7 // bit 7, shadows bit in DAC1CON1bits
11146 #define DAC1R7 DAC1CON1bits.DAC1R7 // bit 7, shadows bit in DAC1CON1bits
11148 #define REF8 DAC1CON2bits.REF8 // bit 0, shadows bit in DAC1CON2bits
11149 #define DAC1REF8 DAC1CON2bits.DAC1REF8 // bit 0, shadows bit in DAC1CON2bits
11150 #define R8 DAC1CON2bits.R8 // bit 0, shadows bit in DAC1CON2bits
11151 #define DAC1R8 DAC1CON2bits.DAC1R8 // bit 0, shadows bit in DAC1CON2bits
11152 #define REF9 DAC1CON2bits.REF9 // bit 1, shadows bit in DAC1CON2bits
11153 #define DAC1REF9 DAC1CON2bits.DAC1REF9 // bit 1, shadows bit in DAC1CON2bits
11154 #define R9 DAC1CON2bits.R9 // bit 1, shadows bit in DAC1CON2bits
11155 #define DAC1R9 DAC1CON2bits.DAC1R9 // bit 1, shadows bit in DAC1CON2bits
11156 #define REF10 DAC1CON2bits.REF10 // bit 2, shadows bit in DAC1CON2bits
11157 #define DAC1REF10 DAC1CON2bits.DAC1REF10 // bit 2, shadows bit in DAC1CON2bits
11158 #define R10 DAC1CON2bits.R10 // bit 2, shadows bit in DAC1CON2bits
11159 #define DAC1R10 DAC1CON2bits.DAC1R10 // bit 2, shadows bit in DAC1CON2bits
11160 #define REF11 DAC1CON2bits.REF11 // bit 3, shadows bit in DAC1CON2bits
11161 #define DAC1REF11 DAC1CON2bits.DAC1REF11 // bit 3, shadows bit in DAC1CON2bits
11162 #define R11 DAC1CON2bits.R11 // bit 3, shadows bit in DAC1CON2bits
11163 #define DAC1R11 DAC1CON2bits.DAC1R11 // bit 3, shadows bit in DAC1CON2bits
11164 #define REF12 DAC1CON2bits.REF12 // bit 4, shadows bit in DAC1CON2bits
11165 #define DAC1REF12 DAC1CON2bits.DAC1REF12 // bit 4, shadows bit in DAC1CON2bits
11166 #define R12 DAC1CON2bits.R12 // bit 4, shadows bit in DAC1CON2bits
11167 #define DAC1R12 DAC1CON2bits.DAC1R12 // bit 4, shadows bit in DAC1CON2bits
11168 #define REF13 DAC1CON2bits.REF13 // bit 5, shadows bit in DAC1CON2bits
11169 #define DAC1REF13 DAC1CON2bits.DAC1REF13 // bit 5, shadows bit in DAC1CON2bits
11170 #define R13 DAC1CON2bits.R13 // bit 5, shadows bit in DAC1CON2bits
11171 #define DAC1R13 DAC1CON2bits.DAC1R13 // bit 5, shadows bit in DAC1CON2bits
11172 #define REF14 DAC1CON2bits.REF14 // bit 6, shadows bit in DAC1CON2bits
11173 #define DAC1REF14 DAC1CON2bits.DAC1REF14 // bit 6, shadows bit in DAC1CON2bits
11174 #define R14 DAC1CON2bits.R14 // bit 6, shadows bit in DAC1CON2bits
11175 #define DAC1R14 DAC1CON2bits.DAC1R14 // bit 6, shadows bit in DAC1CON2bits
11176 #define REF15 DAC1CON2bits.REF15 // bit 7, shadows bit in DAC1CON2bits
11177 #define DAC1REF15 DAC1CON2bits.DAC1REF15 // bit 7, shadows bit in DAC1CON2bits
11178 #define R15 DAC1CON2bits.R15 // bit 7, shadows bit in DAC1CON2bits
11179 #define DAC1R15 DAC1CON2bits.DAC1R15 // bit 7, shadows bit in DAC1CON2bits
11181 #define DAC1LD DACLDbits.DAC1LD // bit 0
11183 #define TSRNG FVRCONbits.TSRNG // bit 4
11184 #define TSEN FVRCONbits.TSEN // bit 5
11185 #define FVRRDY FVRCONbits.FVRRDY // bit 6
11186 #define FVREN FVRCONbits.FVREN // bit 7
11188 #define HIDC4 HIDRVCbits.HIDC4 // bit 4
11189 #define HIDC5 HIDRVCbits.HIDC5 // bit 5
11191 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
11192 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
11193 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
11194 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
11195 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
11196 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
11198 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
11199 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
11200 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
11201 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
11202 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
11203 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
11205 #define IOCIF INTCONbits.IOCIF // bit 0
11206 #define INTF INTCONbits.INTF // bit 1
11207 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
11208 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
11209 #define IOCIE INTCONbits.IOCIE // bit 3
11210 #define INTE INTCONbits.INTE // bit 4
11211 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
11212 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
11213 #define PEIE INTCONbits.PEIE // bit 6
11214 #define GIE INTCONbits.GIE // bit 7
11216 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
11217 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
11218 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
11219 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
11220 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
11221 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
11223 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
11224 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
11225 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
11226 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
11227 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
11228 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
11230 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
11231 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
11232 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
11233 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
11234 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
11235 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
11237 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
11238 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
11239 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
11240 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
11241 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
11242 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
11244 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
11245 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
11246 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
11247 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
11248 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
11249 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
11251 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
11252 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
11253 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
11254 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
11255 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
11256 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
11258 #define LATA0 LATAbits.LATA0 // bit 0
11259 #define LATA1 LATAbits.LATA1 // bit 1
11260 #define LATA2 LATAbits.LATA2 // bit 2
11261 #define LATA4 LATAbits.LATA4 // bit 4
11262 #define LATA5 LATAbits.LATA5 // bit 5
11264 #define LATC0 LATCbits.LATC0 // bit 0
11265 #define LATC1 LATCbits.LATC1 // bit 1
11266 #define LATC2 LATCbits.LATC2 // bit 2
11267 #define LATC3 LATCbits.LATC3 // bit 3
11268 #define LATC4 LATCbits.LATC4 // bit 4
11269 #define LATC5 LATCbits.LATC5 // bit 5
11271 #define CH0 MD1CARHbits.CH0 // bit 0, shadows bit in MD1CARHbits
11272 #define MD1CH0 MD1CARHbits.MD1CH0 // bit 0, shadows bit in MD1CARHbits
11273 #define CH1 MD1CARHbits.CH1 // bit 1, shadows bit in MD1CARHbits
11274 #define MD1CH1 MD1CARHbits.MD1CH1 // bit 1, shadows bit in MD1CARHbits
11275 #define CH2 MD1CARHbits.CH2 // bit 2, shadows bit in MD1CARHbits
11276 #define MD1CH2 MD1CARHbits.MD1CH2 // bit 2, shadows bit in MD1CARHbits
11277 #define CH3 MD1CARHbits.CH3 // bit 3, shadows bit in MD1CARHbits
11278 #define MD1CH3 MD1CARHbits.MD1CH3 // bit 3, shadows bit in MD1CARHbits
11280 #define CL0 MD1CARLbits.CL0 // bit 0, shadows bit in MD1CARLbits
11281 #define MD1CL0 MD1CARLbits.MD1CL0 // bit 0, shadows bit in MD1CARLbits
11282 #define CL1 MD1CARLbits.CL1 // bit 1, shadows bit in MD1CARLbits
11283 #define MD1CL1 MD1CARLbits.MD1CL1 // bit 1, shadows bit in MD1CARLbits
11284 #define CL2 MD1CARLbits.CL2 // bit 2, shadows bit in MD1CARLbits
11285 #define MD1CL2 MD1CARLbits.MD1CL2 // bit 2, shadows bit in MD1CARLbits
11286 #define CL3 MD1CARLbits.CL3 // bit 3, shadows bit in MD1CARLbits
11287 #define MD1CL3 MD1CARLbits.MD1CL3 // bit 3, shadows bit in MD1CARLbits
11289 #define CLSYNC MD1CON1bits.CLSYNC // bit 0, shadows bit in MD1CON1bits
11290 #define MD1CLSYNC MD1CON1bits.MD1CLSYNC // bit 0, shadows bit in MD1CON1bits
11291 #define CLPOL MD1CON1bits.CLPOL // bit 1, shadows bit in MD1CON1bits
11292 #define MD1CLPOL MD1CON1bits.MD1CLPOL // bit 1, shadows bit in MD1CON1bits
11293 #define CHSYNC MD1CON1bits.CHSYNC // bit 4, shadows bit in MD1CON1bits
11294 #define MD1CHSYNC MD1CON1bits.MD1CHSYNC // bit 4, shadows bit in MD1CON1bits
11295 #define CHPOL MD1CON1bits.CHPOL // bit 5, shadows bit in MD1CON1bits
11296 #define MD1CHPOL MD1CON1bits.MD1CHPOL // bit 5, shadows bit in MD1CON1bits
11298 #define MS0 MD1SRCbits.MS0 // bit 0, shadows bit in MD1SRCbits
11299 #define MD1MS0 MD1SRCbits.MD1MS0 // bit 0, shadows bit in MD1SRCbits
11300 #define MS1 MD1SRCbits.MS1 // bit 1, shadows bit in MD1SRCbits
11301 #define MD1MS1 MD1SRCbits.MD1MS1 // bit 1, shadows bit in MD1SRCbits
11302 #define MS2 MD1SRCbits.MS2 // bit 2, shadows bit in MD1SRCbits
11303 #define MD1MS2 MD1SRCbits.MD1MS2 // bit 2, shadows bit in MD1SRCbits
11304 #define MS3 MD1SRCbits.MS3 // bit 3, shadows bit in MD1SRCbits
11305 #define MD1MS3 MD1SRCbits.MD1MS3 // bit 3, shadows bit in MD1SRCbits
11306 #define MS4 MD1SRCbits.MS4 // bit 4, shadows bit in MD1SRCbits
11307 #define MD1MS4 MD1SRCbits.MD1MS4 // bit 4, shadows bit in MD1SRCbits
11309 #define ODA0 ODCONAbits.ODA0 // bit 0
11310 #define ODA1 ODCONAbits.ODA1 // bit 1
11311 #define ODA2 ODCONAbits.ODA2 // bit 2
11312 #define ODA4 ODCONAbits.ODA4 // bit 4
11313 #define ODA5 ODCONAbits.ODA5 // bit 5
11315 #define ODC0 ODCONCbits.ODC0 // bit 0
11316 #define ODC1 ODCONCbits.ODC1 // bit 1
11317 #define ODC2 ODCONCbits.ODC2 // bit 2
11318 #define ODC3 ODCONCbits.ODC3 // bit 3
11319 #define ODC4 ODCONCbits.ODC4 // bit 4
11320 #define ODC5 ODCONCbits.ODC5 // bit 5
11322 #define PS0 OPTION_REGbits.PS0 // bit 0
11323 #define PS1 OPTION_REGbits.PS1 // bit 1
11324 #define PS2 OPTION_REGbits.PS2 // bit 2
11325 #define PSA OPTION_REGbits.PSA // bit 3
11326 #define TMR0SE OPTION_REGbits.TMR0SE // bit 4, shadows bit in OPTION_REGbits
11327 #define T0SE OPTION_REGbits.T0SE // bit 4, shadows bit in OPTION_REGbits
11328 #define TMR0CS OPTION_REGbits.TMR0CS // bit 5, shadows bit in OPTION_REGbits
11329 #define T0CS OPTION_REGbits.T0CS // bit 5, shadows bit in OPTION_REGbits
11330 #define INTEDG OPTION_REGbits.INTEDG // bit 6
11331 #define NOT_WPUEN OPTION_REGbits.NOT_WPUEN // bit 7
11333 #define SCS0 OSCCONbits.SCS0 // bit 0
11334 #define SCS1 OSCCONbits.SCS1 // bit 1
11335 #define IRCF0 OSCCONbits.IRCF0 // bit 3
11336 #define IRCF1 OSCCONbits.IRCF1 // bit 4
11337 #define IRCF2 OSCCONbits.IRCF2 // bit 5
11338 #define IRCF3 OSCCONbits.IRCF3 // bit 6
11339 #define SPLLEN OSCCONbits.SPLLEN // bit 7
11341 #define HFIOFS OSCSTATbits.HFIOFS // bit 0
11342 #define LFIOFR OSCSTATbits.LFIOFR // bit 1
11343 #define MFIOFR OSCSTATbits.MFIOFR // bit 2
11344 #define HFIOFL OSCSTATbits.HFIOFL // bit 3
11345 #define HFIOFR OSCSTATbits.HFIOFR // bit 4
11346 #define OSTS OSCSTATbits.OSTS // bit 5
11347 #define PLLR OSCSTATbits.PLLR // bit 6
11348 #define SOSCR OSCSTATbits.SOSCR // bit 7
11350 #define TUN0 OSCTUNEbits.TUN0 // bit 0
11351 #define TUN1 OSCTUNEbits.TUN1 // bit 1
11352 #define TUN2 OSCTUNEbits.TUN2 // bit 2
11353 #define TUN3 OSCTUNEbits.TUN3 // bit 3
11354 #define TUN4 OSCTUNEbits.TUN4 // bit 4
11355 #define TUN5 OSCTUNEbits.TUN5 // bit 5
11357 #define NOT_BOR PCONbits.NOT_BOR // bit 0
11358 #define NOT_POR PCONbits.NOT_POR // bit 1
11359 #define NOT_RI PCONbits.NOT_RI // bit 2
11360 #define NOT_RMCLR PCONbits.NOT_RMCLR // bit 3
11361 #define NOT_RWDT PCONbits.NOT_RWDT // bit 4
11362 #define STKUNF PCONbits.STKUNF // bit 6
11363 #define STKOVF PCONbits.STKOVF // bit 7
11365 #define TMR1IE PIE1bits.TMR1IE // bit 0
11366 #define TMR2IE PIE1bits.TMR2IE // bit 1
11367 #define CCP1IE PIE1bits.CCP1IE // bit 2, shadows bit in PIE1bits
11368 #define CCPIE PIE1bits.CCPIE // bit 2, shadows bit in PIE1bits
11369 #define SSP1IE PIE1bits.SSP1IE // bit 3
11370 #define TXIE PIE1bits.TXIE // bit 4
11371 #define RCIE PIE1bits.RCIE // bit 5
11372 #define ADIE PIE1bits.ADIE // bit 6
11373 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
11375 #define BCL1IE PIE2bits.BCL1IE // bit 3
11376 #define C1IE PIE2bits.C1IE // bit 5
11377 #define C2IE PIE2bits.C2IE // bit 6
11378 #define OSFIE PIE2bits.OSFIE // bit 7
11380 #define CLC1IE PIE3bits.CLC1IE // bit 0
11381 #define CLC2IE PIE3bits.CLC2IE // bit 1
11382 #define CLC3IE PIE3bits.CLC3IE // bit 2
11383 #define ZCDIE PIE3bits.ZCDIE // bit 4
11384 #define COGIE PIE3bits.COGIE // bit 5
11385 #define PWM5IE PIE3bits.PWM5IE // bit 6
11387 #define TMR4IE PIE4bits.TMR4IE // bit 0
11388 #define TMR6IE PIE4bits.TMR6IE // bit 1
11389 #define TMR3IE PIE4bits.TMR3IE // bit 2
11390 #define TMR3GIE PIE4bits.TMR3GIE // bit 3
11391 #define TMR5IE PIE4bits.TMR5IE // bit 4
11392 #define TMR5GIE PIE4bits.TMR5GIE // bit 5
11394 #define TMR1IF PIR1bits.TMR1IF // bit 0
11395 #define TMR2IF PIR1bits.TMR2IF // bit 1
11396 #define CCP1IF PIR1bits.CCP1IF // bit 2, shadows bit in PIR1bits
11397 #define CCPIF PIR1bits.CCPIF // bit 2, shadows bit in PIR1bits
11398 #define SSP1IF PIR1bits.SSP1IF // bit 3
11399 #define TXIF PIR1bits.TXIF // bit 4
11400 #define RCIF PIR1bits.RCIF // bit 5
11401 #define ADIF PIR1bits.ADIF // bit 6
11402 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
11404 #define BCL1IF PIR2bits.BCL1IF // bit 3
11405 #define C1IF PIR2bits.C1IF // bit 5
11406 #define C2IF PIR2bits.C2IF // bit 6
11407 #define OSFIF PIR2bits.OSFIF // bit 7
11409 #define CLC1IF PIR3bits.CLC1IF // bit 0
11410 #define CLC2IF PIR3bits.CLC2IF // bit 1
11411 #define CLC3IF PIR3bits.CLC3IF // bit 2
11412 #define ZCDIF PIR3bits.ZCDIF // bit 4
11413 #define COG1IF PIR3bits.COG1IF // bit 5
11414 #define PWM5IF PIR3bits.PWM5IF // bit 6
11416 #define TMR4IF PIR4bits.TMR4IF // bit 0
11417 #define TMR6IF PIR4bits.TMR6IF // bit 1
11418 #define TMR3IF PIR4bits.TMR3IF // bit 2
11419 #define TMR3GIF PIR4bits.TMR3GIF // bit 3
11420 #define TMR5IF PIR4bits.TMR5IF // bit 4
11421 #define TMR5GIF PIR4bits.TMR5GIF // bit 5
11423 #define RD PMCON1bits.RD // bit 0
11424 #define WR PMCON1bits.WR // bit 1
11425 #define WREN PMCON1bits.WREN // bit 2
11426 #define WRERR PMCON1bits.WRERR // bit 3
11427 #define FREE PMCON1bits.FREE // bit 4
11428 #define LWLO PMCON1bits.LWLO // bit 5
11429 #define CFGS PMCON1bits.CFGS // bit 6
11431 #define RA0 PORTAbits.RA0 // bit 0
11432 #define RA1 PORTAbits.RA1 // bit 1
11433 #define RA2 PORTAbits.RA2 // bit 2
11434 #define RA3 PORTAbits.RA3 // bit 3
11435 #define RA4 PORTAbits.RA4 // bit 4
11436 #define RA5 PORTAbits.RA5 // bit 5
11438 #define RC0 PORTCbits.RC0 // bit 0
11439 #define RC1 PORTCbits.RC1 // bit 1
11440 #define RC2 PORTCbits.RC2 // bit 2
11441 #define RC3 PORTCbits.RC3 // bit 3
11442 #define RC4 PORTCbits.RC4 // bit 4
11443 #define RC5 PORTCbits.RC5 // bit 5
11445 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
11447 #define RPOL PRG1CON1bits.RPOL // bit 0, shadows bit in PRG1CON1bits
11448 #define RG1RPOL PRG1CON1bits.RG1RPOL // bit 0, shadows bit in PRG1CON1bits
11449 #define FPOL PRG1CON1bits.FPOL // bit 1, shadows bit in PRG1CON1bits
11450 #define RG1FPOL PRG1CON1bits.RG1FPOL // bit 1, shadows bit in PRG1CON1bits
11451 #define RDY PRG1CON1bits.RDY // bit 2, shadows bit in PRG1CON1bits
11452 #define RG1RDY PRG1CON1bits.RG1RDY // bit 2, shadows bit in PRG1CON1bits
11454 #define ISET0 PRG1CON2bits.ISET0 // bit 0, shadows bit in PRG1CON2bits
11455 #define RG1ISET0 PRG1CON2bits.RG1ISET0 // bit 0, shadows bit in PRG1CON2bits
11456 #define ISET1 PRG1CON2bits.ISET1 // bit 1, shadows bit in PRG1CON2bits
11457 #define RG1ISET1 PRG1CON2bits.RG1ISET1 // bit 1, shadows bit in PRG1CON2bits
11458 #define ISET2 PRG1CON2bits.ISET2 // bit 2, shadows bit in PRG1CON2bits
11459 #define RG1ISET2 PRG1CON2bits.RG1ISET2 // bit 2, shadows bit in PRG1CON2bits
11460 #define ISET3 PRG1CON2bits.ISET3 // bit 3, shadows bit in PRG1CON2bits
11461 #define RG1ISET3 PRG1CON2bits.RG1ISET3 // bit 3, shadows bit in PRG1CON2bits
11462 #define ISET4 PRG1CON2bits.ISET4 // bit 4, shadows bit in PRG1CON2bits
11463 #define RG1ISET4 PRG1CON2bits.RG1ISET4 // bit 4, shadows bit in PRG1CON2bits
11465 #define FTSS0 PRG1FTSSbits.FTSS0 // bit 0, shadows bit in PRG1FTSSbits
11466 #define RG1FTSS0 PRG1FTSSbits.RG1FTSS0 // bit 0, shadows bit in PRG1FTSSbits
11467 #define FTSS1 PRG1FTSSbits.FTSS1 // bit 1, shadows bit in PRG1FTSSbits
11468 #define RG1FTSS1 PRG1FTSSbits.RG1FTSS1 // bit 1, shadows bit in PRG1FTSSbits
11469 #define FTSS2 PRG1FTSSbits.FTSS2 // bit 2, shadows bit in PRG1FTSSbits
11470 #define RG1FTSS2 PRG1FTSSbits.RG1FTSS2 // bit 2, shadows bit in PRG1FTSSbits
11471 #define FTSS3 PRG1FTSSbits.FTSS3 // bit 3, shadows bit in PRG1FTSSbits
11472 #define RG1FTSS3 PRG1FTSSbits.RG1FTSS3 // bit 3, shadows bit in PRG1FTSSbits
11474 #define INS0 PRG1INSbits.INS0 // bit 0, shadows bit in PRG1INSbits
11475 #define RG1INS0 PRG1INSbits.RG1INS0 // bit 0, shadows bit in PRG1INSbits
11476 #define INS1 PRG1INSbits.INS1 // bit 1, shadows bit in PRG1INSbits
11477 #define RG1INS1 PRG1INSbits.RG1INS1 // bit 1, shadows bit in PRG1INSbits
11478 #define INS2 PRG1INSbits.INS2 // bit 2, shadows bit in PRG1INSbits
11479 #define RG1INS2 PRG1INSbits.RG1INS2 // bit 2, shadows bit in PRG1INSbits
11480 #define INS3 PRG1INSbits.INS3 // bit 3, shadows bit in PRG1INSbits
11481 #define RG1INS3 PRG1INSbits.RG1INS3 // bit 3, shadows bit in PRG1INSbits
11483 #define RTSS0 PRG1RTSSbits.RTSS0 // bit 0, shadows bit in PRG1RTSSbits
11484 #define RG1RTSS0 PRG1RTSSbits.RG1RTSS0 // bit 0, shadows bit in PRG1RTSSbits
11485 #define RTSS1 PRG1RTSSbits.RTSS1 // bit 1, shadows bit in PRG1RTSSbits
11486 #define RG1RTSS1 PRG1RTSSbits.RG1RTSS1 // bit 1, shadows bit in PRG1RTSSbits
11487 #define RTSS2 PRG1RTSSbits.RTSS2 // bit 2, shadows bit in PRG1RTSSbits
11488 #define RG1RTSS2 PRG1RTSSbits.RG1RTSS2 // bit 2, shadows bit in PRG1RTSSbits
11489 #define RTSS3 PRG1RTSSbits.RTSS3 // bit 3, shadows bit in PRG1RTSSbits
11490 #define RG1RTSS3 PRG1RTSSbits.RG1RTSS3 // bit 3, shadows bit in PRG1RTSSbits
11492 #define DC2 PWM3DCHbits.DC2 // bit 0, shadows bit in PWM3DCHbits
11493 #define PWM3DC2 PWM3DCHbits.PWM3DC2 // bit 0, shadows bit in PWM3DCHbits
11494 #define PWMPW2 PWM3DCHbits.PWMPW2 // bit 0, shadows bit in PWM3DCHbits
11495 #define DC3 PWM3DCHbits.DC3 // bit 1, shadows bit in PWM3DCHbits
11496 #define PWM3DC3 PWM3DCHbits.PWM3DC3 // bit 1, shadows bit in PWM3DCHbits
11497 #define PWMPW3 PWM3DCHbits.PWMPW3 // bit 1, shadows bit in PWM3DCHbits
11498 #define DC4 PWM3DCHbits.DC4 // bit 2, shadows bit in PWM3DCHbits
11499 #define PWM3DC4 PWM3DCHbits.PWM3DC4 // bit 2, shadows bit in PWM3DCHbits
11500 #define PWMPW4 PWM3DCHbits.PWMPW4 // bit 2, shadows bit in PWM3DCHbits
11501 #define DC5 PWM3DCHbits.DC5 // bit 3, shadows bit in PWM3DCHbits
11502 #define PWM3DC5 PWM3DCHbits.PWM3DC5 // bit 3, shadows bit in PWM3DCHbits
11503 #define PWMPW5 PWM3DCHbits.PWMPW5 // bit 3, shadows bit in PWM3DCHbits
11504 #define DC6 PWM3DCHbits.DC6 // bit 4, shadows bit in PWM3DCHbits
11505 #define PWM3DC6 PWM3DCHbits.PWM3DC6 // bit 4, shadows bit in PWM3DCHbits
11506 #define PWMPW6 PWM3DCHbits.PWMPW6 // bit 4, shadows bit in PWM3DCHbits
11507 #define DC7 PWM3DCHbits.DC7 // bit 5, shadows bit in PWM3DCHbits
11508 #define PWM3DC7 PWM3DCHbits.PWM3DC7 // bit 5, shadows bit in PWM3DCHbits
11509 #define PWMPW7 PWM3DCHbits.PWMPW7 // bit 5, shadows bit in PWM3DCHbits
11510 #define DC8 PWM3DCHbits.DC8 // bit 6, shadows bit in PWM3DCHbits
11511 #define PWM3DC8 PWM3DCHbits.PWM3DC8 // bit 6, shadows bit in PWM3DCHbits
11512 #define PWMPW8 PWM3DCHbits.PWMPW8 // bit 6, shadows bit in PWM3DCHbits
11513 #define DC9 PWM3DCHbits.DC9 // bit 7, shadows bit in PWM3DCHbits
11514 #define PWM3DC9 PWM3DCHbits.PWM3DC9 // bit 7, shadows bit in PWM3DCHbits
11515 #define PWMPW9 PWM3DCHbits.PWMPW9 // bit 7, shadows bit in PWM3DCHbits
11517 #define DC0 PWM3DCLbits.DC0 // bit 6, shadows bit in PWM3DCLbits
11518 #define PWM3DC0 PWM3DCLbits.PWM3DC0 // bit 6, shadows bit in PWM3DCLbits
11519 #define PWMPW0 PWM3DCLbits.PWMPW0 // bit 6, shadows bit in PWM3DCLbits
11520 #define DC1 PWM3DCLbits.DC1 // bit 7, shadows bit in PWM3DCLbits
11521 #define PWM3DC1 PWM3DCLbits.PWM3DC1 // bit 7, shadows bit in PWM3DCLbits
11522 #define PWMPW1 PWM3DCLbits.PWMPW1 // bit 7, shadows bit in PWM3DCLbits
11524 #define PWM5DCH0 PWM5DCHbits.PWM5DCH0 // bit 0
11525 #define PWM5DCH1 PWM5DCHbits.PWM5DCH1 // bit 1
11526 #define PWM5DCH2 PWM5DCHbits.PWM5DCH2 // bit 2
11527 #define PWM5DCH3 PWM5DCHbits.PWM5DCH3 // bit 3
11528 #define PWM5DCH4 PWM5DCHbits.PWM5DCH4 // bit 4
11529 #define PWM5DCH5 PWM5DCHbits.PWM5DCH5 // bit 5
11530 #define PWM5DCH6 PWM5DCHbits.PWM5DCH6 // bit 6
11531 #define PWM5DCH7 PWM5DCHbits.PWM5DCH7 // bit 7
11533 #define PWM5DCL0 PWM5DCLbits.PWM5DCL0 // bit 0
11534 #define PWM5DCL1 PWM5DCLbits.PWM5DCL1 // bit 1
11535 #define PWM5DCL2 PWM5DCLbits.PWM5DCL2 // bit 2
11536 #define PWM5DCL3 PWM5DCLbits.PWM5DCL3 // bit 3
11537 #define PWM5DCL4 PWM5DCLbits.PWM5DCL4 // bit 4
11538 #define PWM5DCL5 PWM5DCLbits.PWM5DCL5 // bit 5
11539 #define PWM5DCL6 PWM5DCLbits.PWM5DCL6 // bit 6
11540 #define PWM5DCL7 PWM5DCLbits.PWM5DCL7 // bit 7
11542 #define PRIE PWM5INTCONbits.PRIE // bit 0, shadows bit in PWM5INTCONbits
11543 #define PWM5PRIE PWM5INTCONbits.PWM5PRIE // bit 0, shadows bit in PWM5INTCONbits
11544 #define DCIE PWM5INTCONbits.DCIE // bit 1, shadows bit in PWM5INTCONbits
11545 #define PWM5DCIE PWM5INTCONbits.PWM5DCIE // bit 1, shadows bit in PWM5INTCONbits
11546 #define PHIE PWM5INTCONbits.PHIE // bit 2, shadows bit in PWM5INTCONbits
11547 #define PWM5PHIE PWM5INTCONbits.PWM5PHIE // bit 2, shadows bit in PWM5INTCONbits
11548 #define OFIE PWM5INTCONbits.OFIE // bit 3, shadows bit in PWM5INTCONbits
11549 #define PWM5OFIE PWM5INTCONbits.PWM5OFIE // bit 3, shadows bit in PWM5INTCONbits
11551 #define PRIF PWM5INTFbits.PRIF // bit 0, shadows bit in PWM5INTFbits
11552 #define PWM5PRIF PWM5INTFbits.PWM5PRIF // bit 0, shadows bit in PWM5INTFbits
11553 #define DCIF PWM5INTFbits.DCIF // bit 1, shadows bit in PWM5INTFbits
11554 #define PWM5DCIF PWM5INTFbits.PWM5DCIF // bit 1, shadows bit in PWM5INTFbits
11555 #define PHIF PWM5INTFbits.PHIF // bit 2, shadows bit in PWM5INTFbits
11556 #define PWM5PHIF PWM5INTFbits.PWM5PHIF // bit 2, shadows bit in PWM5INTFbits
11557 #define OFIF PWM5INTFbits.OFIF // bit 3, shadows bit in PWM5INTFbits
11558 #define PWM5OFIF PWM5INTFbits.PWM5OFIF // bit 3, shadows bit in PWM5INTFbits
11560 #define LDA PWM5LDCONbits.LDA // bit 7, shadows bit in PWM5LDCONbits
11561 #define PWM5LD PWM5LDCONbits.PWM5LD // bit 7, shadows bit in PWM5LDCONbits
11563 #define OFO PWM5OFCONbits.OFO // bit 4, shadows bit in PWM5OFCONbits
11564 #define PWM5OFMC PWM5OFCONbits.PWM5OFMC // bit 4, shadows bit in PWM5OFCONbits
11566 #define PWM5OFH0 PWM5OFHbits.PWM5OFH0 // bit 0
11567 #define PWM5OFH1 PWM5OFHbits.PWM5OFH1 // bit 1
11568 #define PWM5OFH2 PWM5OFHbits.PWM5OFH2 // bit 2
11569 #define PWM5OFH3 PWM5OFHbits.PWM5OFH3 // bit 3
11570 #define PWM5OFH4 PWM5OFHbits.PWM5OFH4 // bit 4
11571 #define PWM5OFH5 PWM5OFHbits.PWM5OFH5 // bit 5
11572 #define PWM5OFH6 PWM5OFHbits.PWM5OFH6 // bit 6
11573 #define PWM5OFH7 PWM5OFHbits.PWM5OFH7 // bit 7
11575 #define PWM5OFL0 PWM5OFLbits.PWM5OFL0 // bit 0
11576 #define PWM5OFL1 PWM5OFLbits.PWM5OFL1 // bit 1
11577 #define PWM5OFL2 PWM5OFLbits.PWM5OFL2 // bit 2
11578 #define PWM5OFL3 PWM5OFLbits.PWM5OFL3 // bit 3
11579 #define PWM5OFL4 PWM5OFLbits.PWM5OFL4 // bit 4
11580 #define PWM5OFL5 PWM5OFLbits.PWM5OFL5 // bit 5
11581 #define PWM5OFL6 PWM5OFLbits.PWM5OFL6 // bit 6
11582 #define PWM5OFL7 PWM5OFLbits.PWM5OFL7 // bit 7
11584 #define PWM5PHH0 PWM5PHHbits.PWM5PHH0 // bit 0
11585 #define PWM5PHH1 PWM5PHHbits.PWM5PHH1 // bit 1
11586 #define PWM5PHH2 PWM5PHHbits.PWM5PHH2 // bit 2
11587 #define PWM5PHH3 PWM5PHHbits.PWM5PHH3 // bit 3
11588 #define PWM5PHH4 PWM5PHHbits.PWM5PHH4 // bit 4
11589 #define PWM5PHH5 PWM5PHHbits.PWM5PHH5 // bit 5
11590 #define PWM5PHH6 PWM5PHHbits.PWM5PHH6 // bit 6
11591 #define PWM5PHH7 PWM5PHHbits.PWM5PHH7 // bit 7
11593 #define PWM5PHL0 PWM5PHLbits.PWM5PHL0 // bit 0
11594 #define PWM5PHL1 PWM5PHLbits.PWM5PHL1 // bit 1
11595 #define PWM5PHL2 PWM5PHLbits.PWM5PHL2 // bit 2
11596 #define PWM5PHL3 PWM5PHLbits.PWM5PHL3 // bit 3
11597 #define PWM5PHL4 PWM5PHLbits.PWM5PHL4 // bit 4
11598 #define PWM5PHL5 PWM5PHLbits.PWM5PHL5 // bit 5
11599 #define PWM5PHL6 PWM5PHLbits.PWM5PHL6 // bit 6
11600 #define PWM5PHL7 PWM5PHLbits.PWM5PHL7 // bit 7
11602 #define PWM5PRH0 PWM5PRHbits.PWM5PRH0 // bit 0
11603 #define PWM5PRH1 PWM5PRHbits.PWM5PRH1 // bit 1
11604 #define PWM5PRH2 PWM5PRHbits.PWM5PRH2 // bit 2
11605 #define PWM5PRH3 PWM5PRHbits.PWM5PRH3 // bit 3
11606 #define PWM5PRH4 PWM5PRHbits.PWM5PRH4 // bit 4
11607 #define PWM5PRH5 PWM5PRHbits.PWM5PRH5 // bit 5
11608 #define PWM5PRH6 PWM5PRHbits.PWM5PRH6 // bit 6
11609 #define PWM5PRH7 PWM5PRHbits.PWM5PRH7 // bit 7
11611 #define PWM5PRL0 PWM5PRLbits.PWM5PRL0 // bit 0
11612 #define PWM5PRL1 PWM5PRLbits.PWM5PRL1 // bit 1
11613 #define PWM5PRL2 PWM5PRLbits.PWM5PRL2 // bit 2
11614 #define PWM5PRL3 PWM5PRLbits.PWM5PRL3 // bit 3
11615 #define PWM5PRL4 PWM5PRLbits.PWM5PRL4 // bit 4
11616 #define PWM5PRL5 PWM5PRLbits.PWM5PRL5 // bit 5
11617 #define PWM5PRL6 PWM5PRLbits.PWM5PRL6 // bit 6
11618 #define PWM5PRL7 PWM5PRLbits.PWM5PRL7 // bit 7
11620 #define PWM5TMRH0 PWM5TMRHbits.PWM5TMRH0 // bit 0
11621 #define PWM5TMRH1 PWM5TMRHbits.PWM5TMRH1 // bit 1
11622 #define PWM5TMRH2 PWM5TMRHbits.PWM5TMRH2 // bit 2
11623 #define PWM5TMRH3 PWM5TMRHbits.PWM5TMRH3 // bit 3
11624 #define PWM5TMRH4 PWM5TMRHbits.PWM5TMRH4 // bit 4
11625 #define PWM5TMRH5 PWM5TMRHbits.PWM5TMRH5 // bit 5
11626 #define PWM5TMRH6 PWM5TMRHbits.PWM5TMRH6 // bit 6
11627 #define PWM5TMRH7 PWM5TMRHbits.PWM5TMRH7 // bit 7
11629 #define PWM5TMRL0 PWM5TMRLbits.PWM5TMRL0 // bit 0
11630 #define PWM5TMRL1 PWM5TMRLbits.PWM5TMRL1 // bit 1
11631 #define PWM5TMRL2 PWM5TMRLbits.PWM5TMRL2 // bit 2
11632 #define PWM5TMRL3 PWM5TMRLbits.PWM5TMRL3 // bit 3
11633 #define PWM5TMRL4 PWM5TMRLbits.PWM5TMRL4 // bit 4
11634 #define PWM5TMRL5 PWM5TMRLbits.PWM5TMRL5 // bit 5
11635 #define PWM5TMRL6 PWM5TMRLbits.PWM5TMRL6 // bit 6
11636 #define PWM5TMRL7 PWM5TMRLbits.PWM5TMRL7 // bit 7
11638 #define MPWM5EN PWMENbits.MPWM5EN // bit 4
11640 #define MPWM5LD PWMLDbits.MPWM5LD // bit 4
11642 #define MPWM5OUT PWMOUTbits.MPWM5OUT // bit 4
11644 #define RX9D RC1STAbits.RX9D // bit 0
11645 #define OERR RC1STAbits.OERR // bit 1
11646 #define FERR RC1STAbits.FERR // bit 2
11647 #define ADDEN RC1STAbits.ADDEN // bit 3
11648 #define CREN RC1STAbits.CREN // bit 4
11649 #define SREN RC1STAbits.SREN // bit 5
11650 #define RX9 RC1STAbits.RX9 // bit 6
11651 #define SPEN RC1STAbits.SPEN // bit 7
11653 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
11654 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
11655 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
11656 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
11657 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
11659 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
11660 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
11661 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
11662 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
11663 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
11664 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
11666 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
11667 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
11668 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
11669 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
11670 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
11671 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
11672 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
11673 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
11674 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
11675 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
11676 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
11677 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
11678 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
11679 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
11680 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
11681 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
11683 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
11684 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
11685 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
11686 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
11687 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
11688 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
11689 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
11690 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
11691 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
11692 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
11693 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
11694 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
11695 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
11696 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
11697 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
11698 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
11700 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
11701 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
11702 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
11703 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
11704 #define CKP SSP1CONbits.CKP // bit 4
11705 #define SSPEN SSP1CONbits.SSPEN // bit 5
11706 #define SSPOV SSP1CONbits.SSPOV // bit 6
11707 #define WCOL SSP1CONbits.WCOL // bit 7
11709 #define SEN SSP1CON2bits.SEN // bit 0
11710 #define RSEN SSP1CON2bits.RSEN // bit 1
11711 #define PEN SSP1CON2bits.PEN // bit 2
11712 #define RCEN SSP1CON2bits.RCEN // bit 3
11713 #define ACKEN SSP1CON2bits.ACKEN // bit 4
11714 #define ACKDT SSP1CON2bits.ACKDT // bit 5
11715 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
11716 #define GCEN SSP1CON2bits.GCEN // bit 7
11718 #define DHEN SSP1CON3bits.DHEN // bit 0
11719 #define AHEN SSP1CON3bits.AHEN // bit 1
11720 #define SBCDE SSP1CON3bits.SBCDE // bit 2
11721 #define SDAHT SSP1CON3bits.SDAHT // bit 3
11722 #define BOEN SSP1CON3bits.BOEN // bit 4
11723 #define SCIE SSP1CON3bits.SCIE // bit 5
11724 #define PCIE SSP1CON3bits.PCIE // bit 6
11725 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
11727 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
11728 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
11729 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
11730 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
11731 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
11732 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
11733 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
11734 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
11735 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
11736 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
11737 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
11738 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
11739 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
11740 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
11741 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
11742 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
11744 #define BF SSP1STATbits.BF // bit 0
11745 #define UA SSP1STATbits.UA // bit 1
11746 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
11747 #define S SSP1STATbits.S // bit 3
11748 #define P SSP1STATbits.P // bit 4
11749 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
11750 #define CKE SSP1STATbits.CKE // bit 6
11751 #define SMP SSP1STATbits.SMP // bit 7
11753 #define C STATUSbits.C // bit 0
11754 #define DC STATUSbits.DC // bit 1
11755 #define Z STATUSbits.Z // bit 2
11756 #define NOT_PD STATUSbits.NOT_PD // bit 3
11757 #define NOT_TO STATUSbits.NOT_TO // bit 4
11759 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
11760 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
11761 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
11763 #define GSS0 T1GCONbits.GSS0 // bit 0, shadows bit in T1GCONbits
11764 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0, shadows bit in T1GCONbits
11765 #define GSS1 T1GCONbits.GSS1 // bit 1, shadows bit in T1GCONbits
11766 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1, shadows bit in T1GCONbits
11767 #define GVAL T1GCONbits.GVAL // bit 2, shadows bit in T1GCONbits
11768 #define T1GVAL T1GCONbits.T1GVAL // bit 2, shadows bit in T1GCONbits
11769 #define GGO_NOT_DONE T1GCONbits.GGO_NOT_DONE // bit 3, shadows bit in T1GCONbits
11770 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3, shadows bit in T1GCONbits
11771 #define GSPM T1GCONbits.GSPM // bit 4, shadows bit in T1GCONbits
11772 #define T1GSPM T1GCONbits.T1GSPM // bit 4, shadows bit in T1GCONbits
11773 #define GTM T1GCONbits.GTM // bit 5, shadows bit in T1GCONbits
11774 #define T1GTM T1GCONbits.T1GTM // bit 5, shadows bit in T1GCONbits
11775 #define GPOL T1GCONbits.GPOL // bit 6, shadows bit in T1GCONbits
11776 #define T1GPOL T1GCONbits.T1GPOL // bit 6, shadows bit in T1GCONbits
11777 #define GE T1GCONbits.GE // bit 7, shadows bit in T1GCONbits
11778 #define T1GE T1GCONbits.T1GE // bit 7, shadows bit in T1GCONbits
11779 #define TMR1GE T1GCONbits.TMR1GE // bit 7, shadows bit in T1GCONbits
11781 #define RSEL0 T2RSTbits.RSEL0 // bit 0, shadows bit in T2RSTbits
11782 #define T2RSEL0 T2RSTbits.T2RSEL0 // bit 0, shadows bit in T2RSTbits
11783 #define RSEL1 T2RSTbits.RSEL1 // bit 1, shadows bit in T2RSTbits
11784 #define T2RSEL1 T2RSTbits.T2RSEL1 // bit 1, shadows bit in T2RSTbits
11785 #define RSEL2 T2RSTbits.RSEL2 // bit 2, shadows bit in T2RSTbits
11786 #define T2RSEL2 T2RSTbits.T2RSEL2 // bit 2, shadows bit in T2RSTbits
11787 #define RSEL3 T2RSTbits.RSEL3 // bit 3, shadows bit in T2RSTbits
11788 #define T2RSEL3 T2RSTbits.T2RSEL3 // bit 3, shadows bit in T2RSTbits
11790 #define TRISA0 TRISAbits.TRISA0 // bit 0
11791 #define TRISA1 TRISAbits.TRISA1 // bit 1
11792 #define TRISA2 TRISAbits.TRISA2 // bit 2
11793 #define TRISA4 TRISAbits.TRISA4 // bit 4
11794 #define TRISA5 TRISAbits.TRISA5 // bit 5
11796 #define TRISC0 TRISCbits.TRISC0 // bit 0
11797 #define TRISC1 TRISCbits.TRISC1 // bit 1
11798 #define TRISC2 TRISCbits.TRISC2 // bit 2
11799 #define TRISC3 TRISCbits.TRISC3 // bit 3
11800 #define TRISC4 TRISCbits.TRISC4 // bit 4
11801 #define TRISC5 TRISCbits.TRISC5 // bit 5
11803 #define SWDTEN WDTCONbits.SWDTEN // bit 0
11804 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
11805 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
11806 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
11807 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
11808 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
11810 #define WPUA0 WPUAbits.WPUA0 // bit 0
11811 #define WPUA1 WPUAbits.WPUA1 // bit 1
11812 #define WPUA2 WPUAbits.WPUA2 // bit 2
11813 #define WPUA3 WPUAbits.WPUA3 // bit 3
11814 #define WPUA4 WPUAbits.WPUA4 // bit 4
11815 #define WPUA5 WPUAbits.WPUA5 // bit 5
11817 #define WPUC0 WPUCbits.WPUC0 // bit 0
11818 #define WPUC1 WPUCbits.WPUC1 // bit 1
11819 #define WPUC2 WPUCbits.WPUC2 // bit 2
11820 #define WPUC3 WPUCbits.WPUC3 // bit 3
11821 #define WPUC4 WPUCbits.WPUC4 // bit 4
11822 #define WPUC5 WPUCbits.WPUC5 // bit 5
11824 #define ZCD1INTN ZCD1CONbits.ZCD1INTN // bit 0
11825 #define ZCD1INTP ZCD1CONbits.ZCD1INTP // bit 1
11826 #define ZCD1POL ZCD1CONbits.ZCD1POL // bit 4
11827 #define ZCD1OUT ZCD1CONbits.ZCD1OUT // bit 5
11828 #define ZCD1EN ZCD1CONbits.ZCD1EN // bit 7
11830 #endif // #ifndef NO_BIT_DEFINES
11832 #endif // #ifndef __PIC16LF1765_H__