2 * This declarations of the PIC16LF1776 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:15 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16LF1776_H__
26 #define __PIC16LF1776_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTB_ADDR 0x000D
52 #define PORTC_ADDR 0x000E
53 #define PORTE_ADDR 0x0010
54 #define PIR1_ADDR 0x0011
55 #define PIR2_ADDR 0x0012
56 #define PIR3_ADDR 0x0013
57 #define PIR4_ADDR 0x0014
58 #define PIR5_ADDR 0x0015
59 #define PIR6_ADDR 0x0016
60 #define TMR0_ADDR 0x0017
61 #define TMR1_ADDR 0x0018
62 #define TMR1L_ADDR 0x0018
63 #define TMR1H_ADDR 0x0019
64 #define T1CON_ADDR 0x001A
65 #define T1GCON_ADDR 0x001B
66 #define TMR3_ADDR 0x001C
67 #define TMR3L_ADDR 0x001C
68 #define TMR3H_ADDR 0x001D
69 #define T3CON_ADDR 0x001E
70 #define T3GCON_ADDR 0x001F
71 #define TRISA_ADDR 0x008C
72 #define TRISB_ADDR 0x008D
73 #define TRISC_ADDR 0x008E
74 #define TRISE_ADDR 0x0090
75 #define PIE1_ADDR 0x0091
76 #define PIE2_ADDR 0x0092
77 #define PIE3_ADDR 0x0093
78 #define PIE4_ADDR 0x0094
79 #define PIE5_ADDR 0x0095
80 #define PIE6_ADDR 0x0096
81 #define OPTION_REG_ADDR 0x0097
82 #define PCON_ADDR 0x0098
83 #define WDTCON_ADDR 0x0099
84 #define OSCTUNE_ADDR 0x009A
85 #define OSCCON_ADDR 0x009B
86 #define OSCSTAT_ADDR 0x009C
87 #define BORCON_ADDR 0x009D
88 #define FVRCON_ADDR 0x009E
89 #define ZCD1CON_ADDR 0x009F
90 #define LATA_ADDR 0x010C
91 #define LATB_ADDR 0x010D
92 #define LATC_ADDR 0x010E
93 #define CMOUT_ADDR 0x0111
94 #define CM1CON0_ADDR 0x0112
95 #define CM1CON1_ADDR 0x0113
96 #define CM1NSEL_ADDR 0x0114
97 #define CM1PSEL_ADDR 0x0115
98 #define CM2CON0_ADDR 0x0116
99 #define CM2CON1_ADDR 0x0117
100 #define CM2NSEL_ADDR 0x0118
101 #define CM2PSEL_ADDR 0x0119
102 #define CM3CON0_ADDR 0x011A
103 #define CM3CON1_ADDR 0x011B
104 #define CM3NSEL_ADDR 0x011C
105 #define CM3PSEL_ADDR 0x011D
106 #define ANSELA_ADDR 0x018C
107 #define ANSELB_ADDR 0x018D
108 #define ANSELC_ADDR 0x018E
109 #define PMADR_ADDR 0x0191
110 #define PMADRL_ADDR 0x0191
111 #define PMADRH_ADDR 0x0192
112 #define PMDAT_ADDR 0x0193
113 #define PMDATL_ADDR 0x0193
114 #define PMDATH_ADDR 0x0194
115 #define PMCON1_ADDR 0x0195
116 #define PMCON2_ADDR 0x0196
117 #define RC1REG_ADDR 0x0199
118 #define RCREG_ADDR 0x0199
119 #define RCREG1_ADDR 0x0199
120 #define TX1REG_ADDR 0x019A
121 #define TXREG_ADDR 0x019A
122 #define TXREG1_ADDR 0x019A
123 #define SP1BRG_ADDR 0x019B
124 #define SP1BRGL_ADDR 0x019B
125 #define SPBRG_ADDR 0x019B
126 #define SPBRG1_ADDR 0x019B
127 #define SPBRGL_ADDR 0x019B
128 #define SP1BRGH_ADDR 0x019C
129 #define SPBRGH_ADDR 0x019C
130 #define SPBRGH1_ADDR 0x019C
131 #define RC1STA_ADDR 0x019D
132 #define RCSTA_ADDR 0x019D
133 #define RCSTA1_ADDR 0x019D
134 #define TX1STA_ADDR 0x019E
135 #define TXSTA_ADDR 0x019E
136 #define TXSTA1_ADDR 0x019E
137 #define BAUD1CON_ADDR 0x019F
138 #define BAUDCON_ADDR 0x019F
139 #define BAUDCON1_ADDR 0x019F
140 #define BAUDCTL_ADDR 0x019F
141 #define BAUDCTL1_ADDR 0x019F
142 #define WPUA_ADDR 0x020C
143 #define WPUB_ADDR 0x020D
144 #define WPUC_ADDR 0x020E
145 #define WPUE_ADDR 0x0210
146 #define SSP1BUF_ADDR 0x0211
147 #define SSPBUF_ADDR 0x0211
148 #define SSP1ADD_ADDR 0x0212
149 #define SSPADD_ADDR 0x0212
150 #define SSP1MSK_ADDR 0x0213
151 #define SSPMSK_ADDR 0x0213
152 #define SSP1STAT_ADDR 0x0214
153 #define SSPSTAT_ADDR 0x0214
154 #define SSP1CON_ADDR 0x0215
155 #define SSP1CON1_ADDR 0x0215
156 #define SSPCON_ADDR 0x0215
157 #define SSPCON1_ADDR 0x0215
158 #define SSP1CON2_ADDR 0x0216
159 #define SSPCON2_ADDR 0x0216
160 #define SSP1CON3_ADDR 0x0217
161 #define SSPCON3_ADDR 0x0217
162 #define MD3CON0_ADDR 0x021B
163 #define MD3CON1_ADDR 0x021C
164 #define MD3SRC_ADDR 0x021D
165 #define MD3CARL_ADDR 0x021E
166 #define MD3CARH_ADDR 0x021F
167 #define ODCONA_ADDR 0x028C
168 #define ODCONB_ADDR 0x028D
169 #define ODCONC_ADDR 0x028E
170 #define CCPR1_ADDR 0x0291
171 #define CCPR1L_ADDR 0x0291
172 #define CCPR1H_ADDR 0x0292
173 #define CCP1CON_ADDR 0x0293
174 #define CCP1CAP_ADDR 0x0294
175 #define CCPR2_ADDR 0x0295
176 #define CCPR2L_ADDR 0x0295
177 #define CCPR2H_ADDR 0x0296
178 #define CCP2CON_ADDR 0x0297
179 #define CCP2CAP_ADDR 0x0298
180 #define CCPR7_ADDR 0x0299
181 #define CCPR7L_ADDR 0x0299
182 #define CCPR7H_ADDR 0x029A
183 #define CCP7CON_ADDR 0x029B
184 #define CCP7CAP_ADDR 0x029C
185 #define CCPTMRS1_ADDR 0x029E
186 #define CCPTMRS2_ADDR 0x029F
187 #define SLRCONA_ADDR 0x030C
188 #define SLRCONB_ADDR 0x030D
189 #define SLRCONC_ADDR 0x030E
190 #define MD1CON0_ADDR 0x0315
191 #define MD1CON1_ADDR 0x0316
192 #define MD1SRC_ADDR 0x0317
193 #define MD1CARL_ADDR 0x0318
194 #define MD1CARH_ADDR 0x0319
195 #define MD2CON0_ADDR 0x031B
196 #define MD2CON1_ADDR 0x031C
197 #define MD2SRC_ADDR 0x031D
198 #define MD2CARL_ADDR 0x031E
199 #define MD2CARH_ADDR 0x031F
200 #define INLVLA_ADDR 0x038C
201 #define INLVLB_ADDR 0x038D
202 #define INLVLC_ADDR 0x038E
203 #define INLVE_ADDR 0x0390
204 #define IOCAP_ADDR 0x0391
205 #define IOCAN_ADDR 0x0392
206 #define IOCAF_ADDR 0x0393
207 #define IOCBP_ADDR 0x0394
208 #define IOCBN_ADDR 0x0395
209 #define IOCBF_ADDR 0x0396
210 #define IOCCP_ADDR 0x0397
211 #define IOCCN_ADDR 0x0398
212 #define IOCCF_ADDR 0x0399
213 #define IOCEP_ADDR 0x039D
214 #define IOCEN_ADDR 0x039E
215 #define IOCEF_ADDR 0x039F
216 #define HIDRVB_ADDR 0x040D
217 #define TMR5_ADDR 0x040F
218 #define TMR5L_ADDR 0x040F
219 #define TMR5H_ADDR 0x0410
220 #define T5CON_ADDR 0x0411
221 #define T5GCON_ADDR 0x0412
222 #define T4TMR_ADDR 0x0413
223 #define TMR4_ADDR 0x0413
224 #define PR4_ADDR 0x0414
225 #define T4PR_ADDR 0x0414
226 #define T4CON_ADDR 0x0415
227 #define T4HLT_ADDR 0x0416
228 #define T4CLKCON_ADDR 0x0417
229 #define T4RST_ADDR 0x0418
230 #define T6TMR_ADDR 0x041A
231 #define TMR6_ADDR 0x041A
232 #define PR6_ADDR 0x041B
233 #define T6PR_ADDR 0x041B
234 #define T6CON_ADDR 0x041C
235 #define T6HLT_ADDR 0x041D
236 #define T6CLKCON_ADDR 0x041E
237 #define T6RST_ADDR 0x041F
238 #define ADRESL_ADDR 0x048E
239 #define ADRESH_ADDR 0x048F
240 #define ADCON0_ADDR 0x0490
241 #define ADCON1_ADDR 0x0491
242 #define ADCON2_ADDR 0x0492
243 #define T2TMR_ADDR 0x0493
244 #define TMR2_ADDR 0x0493
245 #define PR2_ADDR 0x0494
246 #define T2PR_ADDR 0x0494
247 #define T2CON_ADDR 0x0495
248 #define T2HLT_ADDR 0x0496
249 #define T2CLKCON_ADDR 0x0497
250 #define T2RST_ADDR 0x0498
251 #define T8TMR_ADDR 0x049A
252 #define TMR8_ADDR 0x049A
253 #define PR8_ADDR 0x049B
254 #define T8PR_ADDR 0x049B
255 #define T8CON_ADDR 0x049C
256 #define T8HLT_ADDR 0x049D
257 #define T8CLKCON_ADDR 0x049E
258 #define T8RST_ADDR 0x049F
259 #define OPA1NCHS_ADDR 0x050F
260 #define OPA1PCHS_ADDR 0x0510
261 #define OPA1CON_ADDR 0x0511
262 #define OPA1ORS_ADDR 0x0512
263 #define OPA2NCHS_ADDR 0x0513
264 #define OPA2PCHS_ADDR 0x0514
265 #define OPA2CON_ADDR 0x0515
266 #define OPA2ORS_ADDR 0x0516
267 #define OPA3NCHS_ADDR 0x0517
268 #define OPA3PCHS_ADDR 0x0518
269 #define OPA3CON_ADDR 0x0519
270 #define OPA3ORS_ADDR 0x051A
271 #define DACLD_ADDR 0x058D
272 #define DAC1CON0_ADDR 0x058E
273 #define DAC1CON1_ADDR 0x058F
274 #define DAC1REF_ADDR 0x058F
275 #define DAC1REFL_ADDR 0x058F
276 #define DAC1CON2_ADDR 0x0590
277 #define DAC1REFH_ADDR 0x0590
278 #define DAC2CON0_ADDR 0x0591
279 #define DAC2CON1_ADDR 0x0592
280 #define DAC2REF_ADDR 0x0592
281 #define DAC2REFL_ADDR 0x0592
282 #define DAC2CON2_ADDR 0x0593
283 #define DAC2REFH_ADDR 0x0593
284 #define DAC3CON0_ADDR 0x0594
285 #define DAC3CON1_ADDR 0x0595
286 #define DAC3REF_ADDR 0x0595
287 #define DAC4CON0_ADDR 0x0596
288 #define DAC4CON1_ADDR 0x0597
289 #define DAC4REF_ADDR 0x0597
290 #define DAC5CON0_ADDR 0x0598
291 #define DAC5CON1_ADDR 0x0599
292 #define DAC5REF_ADDR 0x0599
293 #define DAC5REFL_ADDR 0x0599
294 #define DAC5CON2_ADDR 0x059A
295 #define DAC5REFH_ADDR 0x059A
296 #define DAC7CON0_ADDR 0x059E
297 #define DAC7CON1_ADDR 0x059F
298 #define DAC7REF_ADDR 0x059F
299 #define PWM3DCL_ADDR 0x0614
300 #define PWM3DCH_ADDR 0x0615
301 #define PWM3CON_ADDR 0x0616
302 #define PWM4DCL_ADDR 0x0617
303 #define PWM4DCH_ADDR 0x0618
304 #define PWM4CON_ADDR 0x0619
305 #define PWM9DCL_ADDR 0x061A
306 #define PWM9DCH_ADDR 0x061B
307 #define PWM9CON_ADDR 0x061C
308 #define COG1PHR_ADDR 0x068D
309 #define COG1PHF_ADDR 0x068E
310 #define COG1BLKR_ADDR 0x068F
311 #define COG1BLKF_ADDR 0x0690
312 #define COG1DBR_ADDR 0x0691
313 #define COG1DBF_ADDR 0x0692
314 #define COG1CON0_ADDR 0x0693
315 #define COG1CON1_ADDR 0x0694
316 #define COG1RIS0_ADDR 0x0695
317 #define COG1RIS1_ADDR 0x0696
318 #define COG1RSIM0_ADDR 0x0697
319 #define COG1RSIM1_ADDR 0x0698
320 #define COG1FIS0_ADDR 0x0699
321 #define COG1FIS1_ADDR 0x069A
322 #define COG1FSIM0_ADDR 0x069B
323 #define COG1FSIM1_ADDR 0x069C
324 #define COG1ASD0_ADDR 0x069D
325 #define COG1ASD1_ADDR 0x069E
326 #define COG1STR_ADDR 0x069F
327 #define COG2PHR_ADDR 0x070D
328 #define COG2PHF_ADDR 0x070E
329 #define COG2BLKR_ADDR 0x070F
330 #define COG2BLKF_ADDR 0x0710
331 #define COG2DBR_ADDR 0x0711
332 #define COG2DBF_ADDR 0x0712
333 #define COG2CON0_ADDR 0x0713
334 #define COG2CON1_ADDR 0x0714
335 #define COG2RIS0_ADDR 0x0715
336 #define COG2RIS1_ADDR 0x0716
337 #define COG2RSIM0_ADDR 0x0717
338 #define COG2RSIM1_ADDR 0x0718
339 #define COG2FIS0_ADDR 0x0719
340 #define COG2FIS1_ADDR 0x071A
341 #define COG2FSIM0_ADDR 0x071B
342 #define COG2FSIM1_ADDR 0x071C
343 #define COG2ASD0_ADDR 0x071D
344 #define COG2ASD1_ADDR 0x071E
345 #define COG2STR_ADDR 0x071F
346 #define PRG1RTSS_ADDR 0x078E
347 #define PRG1FTSS_ADDR 0x078F
348 #define PRG1INS_ADDR 0x0790
349 #define PRG1CON0_ADDR 0x0791
350 #define PRG1CON1_ADDR 0x0792
351 #define PRG1CON2_ADDR 0x0793
352 #define PRG2RTSS_ADDR 0x0794
353 #define PRG2FTSS_ADDR 0x0795
354 #define PRG2INS_ADDR 0x0796
355 #define PRG2CON0_ADDR 0x0797
356 #define PRG2CON1_ADDR 0x0798
357 #define PRG2CON2_ADDR 0x0799
358 #define PRG3RTSS_ADDR 0x079A
359 #define PRG3FTSS_ADDR 0x079B
360 #define PRG3INS_ADDR 0x079C
361 #define PRG3CON0_ADDR 0x079D
362 #define PRG3CON1_ADDR 0x079E
363 #define PRG3CON2_ADDR 0x079F
364 #define COG3PHR_ADDR 0x080D
365 #define COG3PHF_ADDR 0x080E
366 #define COG3BLKR_ADDR 0x080F
367 #define COG3BLKF_ADDR 0x0810
368 #define COG3DBR_ADDR 0x0811
369 #define COG3DBF_ADDR 0x0812
370 #define COG3CON0_ADDR 0x0813
371 #define COG3CON1_ADDR 0x0814
372 #define COG3RIS0_ADDR 0x0815
373 #define COG3RIS1_ADDR 0x0816
374 #define COG3RSIM0_ADDR 0x0817
375 #define COG3RSIM1_ADDR 0x0818
376 #define COG3FIS0_ADDR 0x0819
377 #define COG3FIS1_ADDR 0x081A
378 #define COG3FSIM0_ADDR 0x081B
379 #define COG3FSIM1_ADDR 0x081C
380 #define COG3ASD0_ADDR 0x081D
381 #define COG3ASD1_ADDR 0x081E
382 #define COG3STR_ADDR 0x081F
383 #define CM4CON0_ADDR 0x090C
384 #define CM4CON1_ADDR 0x090D
385 #define CM4NSEL_ADDR 0x090E
386 #define CM4PSEL_ADDR 0x090F
387 #define CM5CON0_ADDR 0x0910
388 #define CM5CON1_ADDR 0x0911
389 #define CM5NSEL_ADDR 0x0912
390 #define CM5PSEL_ADDR 0x0913
391 #define CM6CON0_ADDR 0x0914
392 #define CM6CON1_ADDR 0x0915
393 #define CM6NSEL_ADDR 0x0916
394 #define CM6PSEL_ADDR 0x0917
395 #define PWMEN_ADDR 0x0D8E
396 #define PWMLD_ADDR 0x0D8F
397 #define PWMOUT_ADDR 0x0D90
398 #define PWM5PH_ADDR 0x0D91
399 #define PWM5PHL_ADDR 0x0D91
400 #define PWM5PHH_ADDR 0x0D92
401 #define PWM5DC_ADDR 0x0D93
402 #define PWM5DCL_ADDR 0x0D93
403 #define PWM5DCH_ADDR 0x0D94
404 #define PWM5PR_ADDR 0x0D95
405 #define PWM5PRL_ADDR 0x0D95
406 #define PWM5PRH_ADDR 0x0D96
407 #define PWM5OF_ADDR 0x0D97
408 #define PWM5OFL_ADDR 0x0D97
409 #define PWM5OFH_ADDR 0x0D98
410 #define PWM5TMR_ADDR 0x0D99
411 #define PWM5TMRL_ADDR 0x0D99
412 #define PWM5TMRH_ADDR 0x0D9A
413 #define PWM5CON_ADDR 0x0D9B
414 #define PWM5INTCON_ADDR 0x0D9C
415 #define PWM5INTE_ADDR 0x0D9C
416 #define PWM5INTF_ADDR 0x0D9D
417 #define PWM5INTFLG_ADDR 0x0D9D
418 #define PWM5CLKCON_ADDR 0x0D9E
419 #define PWM5LDCON_ADDR 0x0D9F
420 #define PWM5OFCON_ADDR 0x0DA0
421 #define PWM6PH_ADDR 0x0DA1
422 #define PWM6PHL_ADDR 0x0DA1
423 #define PWM6PHH_ADDR 0x0DA2
424 #define PWM6DC_ADDR 0x0DA3
425 #define PWM6DCL_ADDR 0x0DA3
426 #define PWM6DCH_ADDR 0x0DA4
427 #define PWM6PR_ADDR 0x0DA5
428 #define PWM6PRL_ADDR 0x0DA5
429 #define PWM6PRH_ADDR 0x0DA6
430 #define PWM6OF_ADDR 0x0DA7
431 #define PWM6OFL_ADDR 0x0DA7
432 #define PWM6OFH_ADDR 0x0DA8
433 #define PWM6TMR_ADDR 0x0DA9
434 #define PWM6TMRL_ADDR 0x0DA9
435 #define PWM6TMRH_ADDR 0x0DAA
436 #define PWM6CON_ADDR 0x0DAB
437 #define PWM6INTCON_ADDR 0x0DAC
438 #define PWM6INTE_ADDR 0x0DAC
439 #define PWM6INTF_ADDR 0x0DAD
440 #define PWM6INTFLG_ADDR 0x0DAD
441 #define PWM6CLKCON_ADDR 0x0DAE
442 #define PWM6LDCON_ADDR 0x0DAF
443 #define PWM6OFCON_ADDR 0x0DB0
444 #define PWM11PH_ADDR 0x0DB1
445 #define PWM11PHL_ADDR 0x0DB1
446 #define PWM11PHH_ADDR 0x0DB2
447 #define PWM11DC_ADDR 0x0DB3
448 #define PWM11DCL_ADDR 0x0DB3
449 #define PWM11DCH_ADDR 0x0DB4
450 #define PWM11PR_ADDR 0x0DB5
451 #define PWM11PRL_ADDR 0x0DB5
452 #define PWM11PRH_ADDR 0x0DB6
453 #define PWM11OF_ADDR 0x0DB7
454 #define PWM11OFL_ADDR 0x0DB7
455 #define PWM11OFH_ADDR 0x0DB8
456 #define PWM11TMR_ADDR 0x0DB9
457 #define PWM11TMRL_ADDR 0x0DB9
458 #define PWM11TMRH_ADDR 0x0DBA
459 #define PWM11CON_ADDR 0x0DBB
460 #define PWM11INTCON_ADDR 0x0DBC
461 #define PWM11INTE_ADDR 0x0DBC
462 #define PWM11INTF_ADDR 0x0DBD
463 #define PWM11INTFLG_ADDR 0x0DBD
464 #define PWM11CLKCON_ADDR 0x0DBE
465 #define PWM11LDCON_ADDR 0x0DBF
466 #define PWM11OFCON_ADDR 0x0DC0
467 #define PPSLOCK_ADDR 0x0E0C
468 #define INTPPS_ADDR 0x0E0D
469 #define T0CKIPPS_ADDR 0x0E0E
470 #define T1CKIPPS_ADDR 0x0E0F
471 #define T1GPPS_ADDR 0x0E10
472 #define T3CKIPPS_ADDR 0x0E11
473 #define T3GPPS_ADDR 0x0E12
474 #define T5CKIPPS_ADDR 0x0E13
475 #define T5GPPS_ADDR 0x0E14
476 #define T2CKIPPS_ADDR 0x0E15
477 #define T4CKIPPS_ADDR 0x0E16
478 #define T6CKIPPS_ADDR 0x0E17
479 #define T8CKIPPS_ADDR 0x0E18
480 #define CCP1PPS_ADDR 0x0E19
481 #define CCP2PPS_ADDR 0x0E1A
482 #define CCP7PPS_ADDR 0x0E1B
483 #define COG1INPPS_ADDR 0x0E1D
484 #define COG2INPPS_ADDR 0x0E1E
485 #define COG3INPPS_ADDR 0x0E1F
486 #define MD1CLPPS_ADDR 0x0E21
487 #define MD1CHPPS_ADDR 0x0E22
488 #define MD1MODPPS_ADDR 0x0E23
489 #define MD2CLPPS_ADDR 0x0E24
490 #define MD2CHPPS_ADDR 0x0E25
491 #define MD2MODPPS_ADDR 0x0E26
492 #define MD3CLPPS_ADDR 0x0E27
493 #define MD3CHPPS_ADDR 0x0E28
494 #define MD3MODPPS_ADDR 0x0E29
495 #define PRG1RPPS_ADDR 0x0E2D
496 #define PRG1FPPS_ADDR 0x0E2E
497 #define PRG2RPPS_ADDR 0x0E2F
498 #define PRG2FPPS_ADDR 0x0E30
499 #define PRG3RPPS_ADDR 0x0E31
500 #define PRG3FPPS_ADDR 0x0E32
501 #define CLCIN0PPS_ADDR 0x0E35
502 #define CLCIN1PPS_ADDR 0x0E36
503 #define CLCIN2PPS_ADDR 0x0E37
504 #define CLCIN3PPS_ADDR 0x0E38
505 #define ADCACTPPS_ADDR 0x0E39
506 #define SSPCLKPPS_ADDR 0x0E3A
507 #define SSPDATPPS_ADDR 0x0E3B
508 #define SSPSSPPS_ADDR 0x0E3C
509 #define RXPPS_ADDR 0x0E3D
510 #define CKPPS_ADDR 0x0E3E
511 #define RA0PPS_ADDR 0x0E90
512 #define RA1PPS_ADDR 0x0E91
513 #define RA2PPS_ADDR 0x0E92
514 #define RA3PPS_ADDR 0x0E93
515 #define RA4PPS_ADDR 0x0E94
516 #define RA5PPS_ADDR 0x0E95
517 #define RA6PPS_ADDR 0x0E96
518 #define RA7PPS_ADDR 0x0E97
519 #define RB0PPS_ADDR 0x0E98
520 #define RB1PPS_ADDR 0x0E99
521 #define RB2PPS_ADDR 0x0E9A
522 #define RB3PPS_ADDR 0x0E9B
523 #define RB4PPS_ADDR 0x0E9C
524 #define RB5PPS_ADDR 0x0E9D
525 #define RB6PPS_ADDR 0x0E9E
526 #define RB7PPS_ADDR 0x0E9F
527 #define RC0PPS_ADDR 0x0EA0
528 #define RC1PPS_ADDR 0x0EA1
529 #define RC2PPS_ADDR 0x0EA2
530 #define RC3PPS_ADDR 0x0EA3
531 #define RC4PPS_ADDR 0x0EA4
532 #define RC5PPS_ADDR 0x0EA5
533 #define RC6PPS_ADDR 0x0EA6
534 #define RC7PPS_ADDR 0x0EA7
535 #define CLCDATA_ADDR 0x0F0F
536 #define CLC1CON_ADDR 0x0F10
537 #define CLC1POL_ADDR 0x0F11
538 #define CLC1SEL0_ADDR 0x0F12
539 #define CLC1SEL1_ADDR 0x0F13
540 #define CLC1SEL2_ADDR 0x0F14
541 #define CLC1SEL3_ADDR 0x0F15
542 #define CLC1GLS0_ADDR 0x0F16
543 #define CLC1GLS1_ADDR 0x0F17
544 #define CLC1GLS2_ADDR 0x0F18
545 #define CLC1GLS3_ADDR 0x0F19
546 #define CLC2CON_ADDR 0x0F1A
547 #define CLC2POL_ADDR 0x0F1B
548 #define CLC2SEL0_ADDR 0x0F1C
549 #define CLC2SEL1_ADDR 0x0F1D
550 #define CLC2SEL2_ADDR 0x0F1E
551 #define CLC2SEL3_ADDR 0x0F1F
552 #define CLC2GLS0_ADDR 0x0F20
553 #define CLC2GLS1_ADDR 0x0F21
554 #define CLC2GLS2_ADDR 0x0F22
555 #define CLC2GLS3_ADDR 0x0F23
556 #define CLC3CON_ADDR 0x0F24
557 #define CLC3POL_ADDR 0x0F25
558 #define CLC3SEL0_ADDR 0x0F26
559 #define CLC3SEL1_ADDR 0x0F27
560 #define CLC3SEL2_ADDR 0x0F28
561 #define CLC3SEL3_ADDR 0x0F29
562 #define CLC3GLS0_ADDR 0x0F2A
563 #define CLC3GLS1_ADDR 0x0F2B
564 #define CLC3GLS2_ADDR 0x0F2C
565 #define CLC3GLS3_ADDR 0x0F2D
566 #define CLC4CON_ADDR 0x0F2E
567 #define CLC4POL_ADDR 0x0F2F
568 #define CLC4SEL0_ADDR 0x0F30
569 #define CLC4SEL1_ADDR 0x0F31
570 #define CLC4SEL2_ADDR 0x0F32
571 #define CLC4SEL3_ADDR 0x0F33
572 #define CLC4GLS0_ADDR 0x0F34
573 #define CLC4GLS1_ADDR 0x0F35
574 #define CLC4GLS2_ADDR 0x0F36
575 #define CLC4GLS3_ADDR 0x0F37
576 #define STATUS_SHAD_ADDR 0x0FE4
577 #define WREG_SHAD_ADDR 0x0FE5
578 #define BSR_SHAD_ADDR 0x0FE6
579 #define PCLATH_SHAD_ADDR 0x0FE7
580 #define FSR0L_SHAD_ADDR 0x0FE8
581 #define FSR0H_SHAD_ADDR 0x0FE9
582 #define FSR1L_SHAD_ADDR 0x0FEA
583 #define FSR1H_SHAD_ADDR 0x0FEB
584 #define STKPTR_ADDR 0x0FED
585 #define TOSL_ADDR 0x0FEE
586 #define TOSH_ADDR 0x0FEF
588 #endif // #ifndef NO_ADDR_DEFINES
590 //==============================================================================
592 // Register Definitions
594 //==============================================================================
596 extern __at(0x0000) __sfr INDF0
;
597 extern __at(0x0001) __sfr INDF1
;
598 extern __at(0x0002) __sfr PCL
;
600 //==============================================================================
603 extern __at(0x0003) __sfr STATUS
;
617 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
625 //==============================================================================
627 extern __at(0x0004) __sfr FSR0
;
628 extern __at(0x0004) __sfr FSR0L
;
629 extern __at(0x0005) __sfr FSR0H
;
630 extern __at(0x0006) __sfr FSR1
;
631 extern __at(0x0006) __sfr FSR1L
;
632 extern __at(0x0007) __sfr FSR1H
;
634 //==============================================================================
637 extern __at(0x0008) __sfr BSR
;
660 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
668 //==============================================================================
670 extern __at(0x0009) __sfr WREG
;
671 extern __at(0x000A) __sfr PCLATH
;
673 //==============================================================================
676 extern __at(0x000B) __sfr INTCON
;
705 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
718 //==============================================================================
721 //==============================================================================
724 extern __at(0x000C) __sfr PORTA
;
738 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
749 //==============================================================================
752 //==============================================================================
755 extern __at(0x000D) __sfr PORTB
;
769 extern __at(0x000D) volatile __PORTBbits_t PORTBbits
;
780 //==============================================================================
783 //==============================================================================
786 extern __at(0x000E) __sfr PORTC
;
800 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
811 //==============================================================================
814 //==============================================================================
817 extern __at(0x0010) __sfr PORTE
;
831 extern __at(0x0010) volatile __PORTEbits_t PORTEbits
;
835 //==============================================================================
838 //==============================================================================
841 extern __at(0x0011) __sfr PIR1
;
854 unsigned TMR1GIF
: 1;
870 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
880 #define _TMR1GIF 0x80
882 //==============================================================================
885 //==============================================================================
888 extern __at(0x0012) __sfr PIR2
;
902 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
913 //==============================================================================
916 //==============================================================================
919 extern __at(0x0013) __sfr PIR3
;
933 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
942 //==============================================================================
945 //==============================================================================
948 extern __at(0x0014) __sfr PIR4
;
955 unsigned TMR3GIF
: 1;
957 unsigned TMR5GIF
: 1;
962 extern __at(0x0014) volatile __PIR4bits_t PIR4bits
;
967 #define _TMR3GIF 0x08
969 #define _TMR5GIF 0x20
972 //==============================================================================
975 //==============================================================================
978 extern __at(0x0015) __sfr PIR5
;
992 extern __at(0x0015) volatile __PIR5bits_t PIR5bits
;
999 //==============================================================================
1002 //==============================================================================
1005 extern __at(0x0016) __sfr PIR6
;
1009 unsigned PWM5IF
: 1;
1010 unsigned PWM6IF
: 1;
1011 unsigned PWM11IF
: 1;
1019 extern __at(0x0016) volatile __PIR6bits_t PIR6bits
;
1021 #define _PWM5IF 0x01
1022 #define _PWM6IF 0x02
1023 #define _PWM11IF 0x04
1025 //==============================================================================
1027 extern __at(0x0017) __sfr TMR0
;
1028 extern __at(0x0018) __sfr TMR1
;
1029 extern __at(0x0018) __sfr TMR1L
;
1030 extern __at(0x0019) __sfr TMR1H
;
1032 //==============================================================================
1035 extern __at(0x001A) __sfr T1CON
;
1043 unsigned NOT_SYNC
: 1;
1056 unsigned SOSCEN
: 1;
1057 unsigned T1CKPS0
: 1;
1058 unsigned T1CKPS1
: 1;
1065 unsigned TMR1ON
: 1;
1067 unsigned NOT_T1SYNC
: 1;
1068 unsigned T1OSCEN
: 1;
1071 unsigned TMR1CS0
: 1;
1072 unsigned TMR1CS1
: 1;
1090 unsigned T1CKPS
: 2;
1116 unsigned TMR1CS
: 2;
1120 extern __at(0x001A) volatile __T1CONbits_t T1CONbits
;
1122 #define _T1CON_ON 0x01
1123 #define _T1CON_TMRON 0x01
1124 #define _T1CON_TMR1ON 0x01
1125 #define _T1CON_T1ON 0x01
1126 #define _T1CON_NOT_SYNC 0x04
1127 #define _T1CON_SYNC 0x04
1128 #define _T1CON_NOT_T1SYNC 0x04
1129 #define _T1CON_OSCEN 0x08
1130 #define _T1CON_SOSCEN 0x08
1131 #define _T1CON_T1OSCEN 0x08
1132 #define _T1CON_CKPS0 0x10
1133 #define _T1CON_T1CKPS0 0x10
1134 #define _T1CON_CKPS1 0x20
1135 #define _T1CON_T1CKPS1 0x20
1136 #define _T1CON_CS0 0x40
1137 #define _T1CON_T1CS0 0x40
1138 #define _T1CON_TMR1CS0 0x40
1139 #define _T1CON_CS1 0x80
1140 #define _T1CON_T1CS1 0x80
1141 #define _T1CON_TMR1CS1 0x80
1143 //==============================================================================
1146 //==============================================================================
1149 extern __at(0x001B) __sfr T1GCON
;
1158 unsigned GGO_NOT_DONE
: 1;
1167 unsigned T1GSS0
: 1;
1168 unsigned T1GSS1
: 1;
1169 unsigned T1GVAL
: 1;
1170 unsigned T1GGO_NOT_DONE
: 1;
1171 unsigned T1GSPM
: 1;
1173 unsigned T1GPOL
: 1;
1186 unsigned TMR1GE
: 1;
1202 extern __at(0x001B) volatile __T1GCONbits_t T1GCONbits
;
1205 #define _T1GSS0 0x01
1207 #define _T1GSS1 0x02
1209 #define _T1GVAL 0x04
1210 #define _GGO_NOT_DONE 0x08
1211 #define _T1GGO_NOT_DONE 0x08
1213 #define _T1GSPM 0x10
1217 #define _T1GPOL 0x40
1220 #define _TMR1GE 0x80
1222 //==============================================================================
1224 extern __at(0x001C) __sfr TMR3
;
1225 extern __at(0x001C) __sfr TMR3L
;
1226 extern __at(0x001D) __sfr TMR3H
;
1228 //==============================================================================
1231 extern __at(0x001E) __sfr T3CON
;
1239 unsigned NOT_SYNC
: 1;
1252 unsigned SOSCEN
: 1;
1253 unsigned T3CKPS0
: 1;
1254 unsigned T3CKPS1
: 1;
1261 unsigned TMR3ON
: 1;
1263 unsigned NOT_T3SYNC
: 1;
1264 unsigned T3OSCEN
: 1;
1267 unsigned TMR3CS0
: 1;
1268 unsigned TMR3CS1
: 1;
1286 unsigned T3CKPS
: 2;
1300 unsigned TMR3CS
: 2;
1316 extern __at(0x001E) volatile __T3CONbits_t T3CONbits
;
1318 #define _T3CON_ON 0x01
1319 #define _T3CON_TMRON 0x01
1320 #define _T3CON_TMR3ON 0x01
1321 #define _T3CON_T3ON 0x01
1322 #define _T3CON_NOT_SYNC 0x04
1323 #define _T3CON_SYNC 0x04
1324 #define _T3CON_NOT_T3SYNC 0x04
1325 #define _T3CON_OSCEN 0x08
1326 #define _T3CON_SOSCEN 0x08
1327 #define _T3CON_T3OSCEN 0x08
1328 #define _T3CON_CKPS0 0x10
1329 #define _T3CON_T3CKPS0 0x10
1330 #define _T3CON_CKPS1 0x20
1331 #define _T3CON_T3CKPS1 0x20
1332 #define _T3CON_CS0 0x40
1333 #define _T3CON_T3CS0 0x40
1334 #define _T3CON_TMR3CS0 0x40
1335 #define _T3CON_CS1 0x80
1336 #define _T3CON_T3CS1 0x80
1337 #define _T3CON_TMR3CS1 0x80
1339 //==============================================================================
1342 //==============================================================================
1345 extern __at(0x001F) __sfr T3GCON
;
1354 unsigned GGO_NOT_DONE
: 1;
1363 unsigned T3GSS0
: 1;
1364 unsigned T3GSS1
: 1;
1365 unsigned T3GVAL
: 1;
1366 unsigned T3GGO_NOT_DONE
: 1;
1367 unsigned T3GSPM
: 1;
1369 unsigned T3GPOL
: 1;
1382 unsigned TMR3GE
: 1;
1398 extern __at(0x001F) volatile __T3GCONbits_t T3GCONbits
;
1400 #define _T3GCON_GSS0 0x01
1401 #define _T3GCON_T3GSS0 0x01
1402 #define _T3GCON_GSS1 0x02
1403 #define _T3GCON_T3GSS1 0x02
1404 #define _T3GCON_GVAL 0x04
1405 #define _T3GCON_T3GVAL 0x04
1406 #define _T3GCON_GGO_NOT_DONE 0x08
1407 #define _T3GCON_T3GGO_NOT_DONE 0x08
1408 #define _T3GCON_GSPM 0x10
1409 #define _T3GCON_T3GSPM 0x10
1410 #define _T3GCON_GTM 0x20
1411 #define _T3GCON_T3GTM 0x20
1412 #define _T3GCON_GPOL 0x40
1413 #define _T3GCON_T3GPOL 0x40
1414 #define _T3GCON_GE 0x80
1415 #define _T3GCON_T3GE 0x80
1416 #define _T3GCON_TMR3GE 0x80
1418 //==============================================================================
1421 //==============================================================================
1424 extern __at(0x008C) __sfr TRISA
;
1428 unsigned TRISA0
: 1;
1429 unsigned TRISA1
: 1;
1430 unsigned TRISA2
: 1;
1431 unsigned TRISA3
: 1;
1432 unsigned TRISA4
: 1;
1433 unsigned TRISA5
: 1;
1434 unsigned TRISA6
: 1;
1435 unsigned TRISA7
: 1;
1438 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
1440 #define _TRISA0 0x01
1441 #define _TRISA1 0x02
1442 #define _TRISA2 0x04
1443 #define _TRISA3 0x08
1444 #define _TRISA4 0x10
1445 #define _TRISA5 0x20
1446 #define _TRISA6 0x40
1447 #define _TRISA7 0x80
1449 //==============================================================================
1452 //==============================================================================
1455 extern __at(0x008D) __sfr TRISB
;
1459 unsigned TRISB0
: 1;
1460 unsigned TRISB1
: 1;
1461 unsigned TRISB2
: 1;
1462 unsigned TRISB3
: 1;
1463 unsigned TRISB4
: 1;
1464 unsigned TRISB5
: 1;
1465 unsigned TRISB6
: 1;
1466 unsigned TRISB7
: 1;
1469 extern __at(0x008D) volatile __TRISBbits_t TRISBbits
;
1471 #define _TRISB0 0x01
1472 #define _TRISB1 0x02
1473 #define _TRISB2 0x04
1474 #define _TRISB3 0x08
1475 #define _TRISB4 0x10
1476 #define _TRISB5 0x20
1477 #define _TRISB6 0x40
1478 #define _TRISB7 0x80
1480 //==============================================================================
1483 //==============================================================================
1486 extern __at(0x008E) __sfr TRISC
;
1490 unsigned TRISC0
: 1;
1491 unsigned TRISC1
: 1;
1492 unsigned TRISC2
: 1;
1493 unsigned TRISC3
: 1;
1494 unsigned TRISC4
: 1;
1495 unsigned TRISC5
: 1;
1496 unsigned TRISC6
: 1;
1497 unsigned TRISC7
: 1;
1500 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
1502 #define _TRISC0 0x01
1503 #define _TRISC1 0x02
1504 #define _TRISC2 0x04
1505 #define _TRISC3 0x08
1506 #define _TRISC4 0x10
1507 #define _TRISC5 0x20
1508 #define _TRISC6 0x40
1509 #define _TRISC7 0x80
1511 //==============================================================================
1514 //==============================================================================
1517 extern __at(0x0090) __sfr TRISE
;
1524 unsigned TRISE3
: 1;
1531 extern __at(0x0090) volatile __TRISEbits_t TRISEbits
;
1533 #define _TRISE3 0x08
1535 //==============================================================================
1538 //==============================================================================
1541 extern __at(0x0091) __sfr PIE1
;
1547 unsigned TMR1IE
: 1;
1548 unsigned TMR2IE
: 1;
1549 unsigned CCP1IE
: 1;
1550 unsigned SSP1IE
: 1;
1554 unsigned TMR1GIE
: 1;
1570 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
1572 #define _TMR1IE 0x01
1573 #define _TMR2IE 0x02
1574 #define _CCP1IE 0x04
1576 #define _SSP1IE 0x08
1580 #define _TMR1GIE 0x80
1582 //==============================================================================
1585 //==============================================================================
1588 extern __at(0x0092) __sfr PIE2
;
1592 unsigned CCP2IE
: 1;
1595 unsigned BCL1IE
: 1;
1602 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
1604 #define _CCP2IE 0x01
1607 #define _BCL1IE 0x08
1613 //==============================================================================
1616 //==============================================================================
1619 extern __at(0x0093) __sfr PIE3
;
1623 unsigned CLC1IE
: 1;
1624 unsigned CLC2IE
: 1;
1625 unsigned CLC3IE
: 1;
1626 unsigned CLC4IE
: 1;
1628 unsigned COG2IE
: 1;
1633 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
1635 #define _CLC1IE 0x01
1636 #define _CLC2IE 0x02
1637 #define _CLC3IE 0x04
1638 #define _CLC4IE 0x08
1640 #define _COG2IE 0x20
1642 //==============================================================================
1645 //==============================================================================
1648 extern __at(0x0094) __sfr PIE4
;
1652 unsigned TMR4IE
: 1;
1653 unsigned TMR6IE
: 1;
1654 unsigned TMR3IE
: 1;
1655 unsigned TMR3GIE
: 1;
1656 unsigned TMR5IE
: 1;
1657 unsigned TMR5GIE
: 1;
1658 unsigned TMR8IE
: 1;
1662 extern __at(0x0094) volatile __PIE4bits_t PIE4bits
;
1664 #define _TMR4IE 0x01
1665 #define _TMR6IE 0x02
1666 #define _TMR3IE 0x04
1667 #define _TMR3GIE 0x08
1668 #define _TMR5IE 0x10
1669 #define _TMR5GIE 0x20
1670 #define _TMR8IE 0x40
1672 //==============================================================================
1675 //==============================================================================
1678 extern __at(0x0095) __sfr PIE5
;
1686 unsigned COG3IE
: 1;
1688 unsigned CCP7IE
: 1;
1692 extern __at(0x0095) volatile __PIE5bits_t PIE5bits
;
1696 #define _COG3IE 0x10
1697 #define _CCP7IE 0x40
1699 //==============================================================================
1702 //==============================================================================
1705 extern __at(0x0096) __sfr PIE6
;
1709 unsigned PWM5IE
: 1;
1710 unsigned PWM6IE
: 1;
1711 unsigned PWM11IE
: 1;
1719 extern __at(0x0096) volatile __PIE6bits_t PIE6bits
;
1721 #define _PWM5IE 0x01
1722 #define _PWM6IE 0x02
1723 #define _PWM11IE 0x04
1725 //==============================================================================
1728 //==============================================================================
1731 extern __at(0x0097) __sfr OPTION_REG
;
1741 unsigned TMR0SE
: 1;
1742 unsigned TMR0CS
: 1;
1743 unsigned INTEDG
: 1;
1744 unsigned NOT_WPUEN
: 1;
1764 } __OPTION_REGbits_t
;
1766 extern __at(0x0097) volatile __OPTION_REGbits_t OPTION_REGbits
;
1772 #define _TMR0SE 0x10
1774 #define _TMR0CS 0x20
1776 #define _INTEDG 0x40
1777 #define _NOT_WPUEN 0x80
1779 //==============================================================================
1782 //==============================================================================
1785 extern __at(0x0098) __sfr PCON
;
1789 unsigned NOT_BOR
: 1;
1790 unsigned NOT_POR
: 1;
1791 unsigned NOT_RI
: 1;
1792 unsigned NOT_RMCLR
: 1;
1793 unsigned NOT_RWDT
: 1;
1795 unsigned STKUNF
: 1;
1796 unsigned STKOVF
: 1;
1799 extern __at(0x0098) volatile __PCONbits_t PCONbits
;
1801 #define _NOT_BOR 0x01
1802 #define _NOT_POR 0x02
1803 #define _NOT_RI 0x04
1804 #define _NOT_RMCLR 0x08
1805 #define _NOT_RWDT 0x10
1806 #define _STKUNF 0x40
1807 #define _STKOVF 0x80
1809 //==============================================================================
1812 //==============================================================================
1815 extern __at(0x0099) __sfr WDTCON
;
1821 unsigned SWDTEN
: 1;
1822 unsigned WDTPS0
: 1;
1823 unsigned WDTPS1
: 1;
1824 unsigned WDTPS2
: 1;
1825 unsigned WDTPS3
: 1;
1826 unsigned WDTPS4
: 1;
1839 extern __at(0x0099) volatile __WDTCONbits_t WDTCONbits
;
1841 #define _SWDTEN 0x01
1842 #define _WDTPS0 0x02
1843 #define _WDTPS1 0x04
1844 #define _WDTPS2 0x08
1845 #define _WDTPS3 0x10
1846 #define _WDTPS4 0x20
1848 //==============================================================================
1851 //==============================================================================
1854 extern __at(0x009A) __sfr OSCTUNE
;
1877 extern __at(0x009A) volatile __OSCTUNEbits_t OSCTUNEbits
;
1886 //==============================================================================
1889 //==============================================================================
1892 extern __at(0x009B) __sfr OSCCON
;
1905 unsigned SPLLEN
: 1;
1922 extern __at(0x009B) volatile __OSCCONbits_t OSCCONbits
;
1930 #define _SPLLEN 0x80
1932 //==============================================================================
1935 //==============================================================================
1938 extern __at(0x009C) __sfr OSCSTAT
;
1942 unsigned HFIOFS
: 1;
1943 unsigned LFIOFR
: 1;
1944 unsigned MFIOFR
: 1;
1945 unsigned HFIOFL
: 1;
1946 unsigned HFIOFR
: 1;
1952 extern __at(0x009C) volatile __OSCSTATbits_t OSCSTATbits
;
1954 #define _HFIOFS 0x01
1955 #define _LFIOFR 0x02
1956 #define _MFIOFR 0x04
1957 #define _HFIOFL 0x08
1958 #define _HFIOFR 0x10
1963 //==============================================================================
1966 //==============================================================================
1969 extern __at(0x009D) __sfr BORCON
;
1973 unsigned BORRDY
: 1;
1980 unsigned SBOREN
: 1;
1983 extern __at(0x009D) volatile __BORCONbits_t BORCONbits
;
1985 #define _BORRDY 0x01
1987 #define _SBOREN 0x80
1989 //==============================================================================
1992 //==============================================================================
1995 extern __at(0x009E) __sfr FVRCON
;
2005 unsigned FVRRDY
: 1;
2009 extern __at(0x009E) volatile __FVRCONbits_t FVRCONbits
;
2013 #define _FVRRDY 0x40
2016 //==============================================================================
2019 //==============================================================================
2022 extern __at(0x009F) __sfr ZCD1CON
;
2026 unsigned ZCD1INTN
: 1;
2027 unsigned ZCD1INTP
: 1;
2030 unsigned ZCD1POL
: 1;
2031 unsigned ZCD1OUT
: 1;
2033 unsigned ZCD1EN
: 1;
2036 extern __at(0x009F) volatile __ZCD1CONbits_t ZCD1CONbits
;
2038 #define _ZCD1INTN 0x01
2039 #define _ZCD1INTP 0x02
2040 #define _ZCD1POL 0x10
2041 #define _ZCD1OUT 0x20
2042 #define _ZCD1EN 0x80
2044 //==============================================================================
2047 //==============================================================================
2050 extern __at(0x010C) __sfr LATA
;
2064 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
2075 //==============================================================================
2078 //==============================================================================
2081 extern __at(0x010D) __sfr LATB
;
2095 extern __at(0x010D) volatile __LATBbits_t LATBbits
;
2106 //==============================================================================
2109 //==============================================================================
2112 extern __at(0x010E) __sfr LATC
;
2126 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
2137 //==============================================================================
2140 //==============================================================================
2143 extern __at(0x0111) __sfr CMOUT
;
2147 unsigned MC1OUT
: 1;
2148 unsigned MC2OUT
: 1;
2149 unsigned MC3OUT
: 1;
2150 unsigned MC4OUT
: 1;
2151 unsigned MC5OUT
: 1;
2152 unsigned MC6OUT
: 1;
2157 extern __at(0x0111) volatile __CMOUTbits_t CMOUTbits
;
2159 #define _MC1OUT 0x01
2160 #define _MC2OUT 0x02
2161 #define _MC3OUT 0x04
2162 #define _MC4OUT 0x08
2163 #define _MC5OUT 0x10
2164 #define _MC6OUT 0x20
2166 //==============================================================================
2169 //==============================================================================
2172 extern __at(0x0112) __sfr CM1CON0
;
2180 unsigned Reserved
: 1;
2190 unsigned C1SYNC
: 1;
2201 extern __at(0x0112) volatile __CM1CON0bits_t CM1CON0bits
;
2203 #define _CM1CON0_SYNC 0x01
2204 #define _CM1CON0_C1SYNC 0x01
2205 #define _CM1CON0_HYS 0x02
2206 #define _CM1CON0_C1HYS 0x02
2207 #define _CM1CON0_Reserved 0x04
2208 #define _CM1CON0_C1SP 0x04
2209 #define _CM1CON0_ZLF 0x08
2210 #define _CM1CON0_C1ZLF 0x08
2211 #define _CM1CON0_POL 0x10
2212 #define _CM1CON0_C1POL 0x10
2213 #define _CM1CON0_OUT 0x40
2214 #define _CM1CON0_C1OUT 0x40
2215 #define _CM1CON0_ON 0x80
2216 #define _CM1CON0_C1ON 0x80
2218 //==============================================================================
2221 //==============================================================================
2224 extern __at(0x0113) __sfr CM1CON1
;
2242 unsigned C1INTN
: 1;
2243 unsigned C1INTP
: 1;
2253 extern __at(0x0113) volatile __CM1CON1bits_t CM1CON1bits
;
2255 #define _CM1CON1_INTN 0x01
2256 #define _CM1CON1_C1INTN 0x01
2257 #define _CM1CON1_INTP 0x02
2258 #define _CM1CON1_C1INTP 0x02
2260 //==============================================================================
2263 //==============================================================================
2266 extern __at(0x0114) __sfr CM1NSEL
;
2272 unsigned C1NCH0
: 1;
2273 unsigned C1NCH1
: 1;
2274 unsigned C1NCH2
: 1;
2275 unsigned C1NCH3
: 1;
2289 extern __at(0x0114) volatile __CM1NSELbits_t CM1NSELbits
;
2291 #define _C1NCH0 0x01
2292 #define _C1NCH1 0x02
2293 #define _C1NCH2 0x04
2294 #define _C1NCH3 0x08
2296 //==============================================================================
2299 //==============================================================================
2302 extern __at(0x0115) __sfr CM1PSEL
;
2320 unsigned C1PCH0
: 1;
2321 unsigned C1PCH1
: 1;
2322 unsigned C1PCH2
: 1;
2323 unsigned C1PCH3
: 1;
2343 extern __at(0x0115) volatile __CM1PSELbits_t CM1PSELbits
;
2346 #define _C1PCH0 0x01
2348 #define _C1PCH1 0x02
2350 #define _C1PCH2 0x04
2352 #define _C1PCH3 0x08
2354 //==============================================================================
2357 //==============================================================================
2360 extern __at(0x0116) __sfr CM2CON0
;
2368 unsigned Reserved
: 1;
2378 unsigned C2SYNC
: 1;
2389 extern __at(0x0116) volatile __CM2CON0bits_t CM2CON0bits
;
2391 #define _CM2CON0_SYNC 0x01
2392 #define _CM2CON0_C2SYNC 0x01
2393 #define _CM2CON0_HYS 0x02
2394 #define _CM2CON0_C2HYS 0x02
2395 #define _CM2CON0_Reserved 0x04
2396 #define _CM2CON0_C2SP 0x04
2397 #define _CM2CON0_ZLF 0x08
2398 #define _CM2CON0_C2ZLF 0x08
2399 #define _CM2CON0_POL 0x10
2400 #define _CM2CON0_C2POL 0x10
2401 #define _CM2CON0_OUT 0x40
2402 #define _CM2CON0_C2OUT 0x40
2403 #define _CM2CON0_ON 0x80
2404 #define _CM2CON0_C2ON 0x80
2406 //==============================================================================
2409 //==============================================================================
2412 extern __at(0x0117) __sfr CM2CON1
;
2430 unsigned C2INTN
: 1;
2431 unsigned C2INTP
: 1;
2441 extern __at(0x0117) volatile __CM2CON1bits_t CM2CON1bits
;
2443 #define _CM2CON1_INTN 0x01
2444 #define _CM2CON1_C2INTN 0x01
2445 #define _CM2CON1_INTP 0x02
2446 #define _CM2CON1_C2INTP 0x02
2448 //==============================================================================
2451 //==============================================================================
2454 extern __at(0x0118) __sfr CM2NSEL
;
2460 unsigned C2NCH0
: 1;
2461 unsigned C2NCH1
: 1;
2462 unsigned C2NCH2
: 1;
2463 unsigned C2NCH3
: 1;
2477 extern __at(0x0118) volatile __CM2NSELbits_t CM2NSELbits
;
2479 #define _C2NCH0 0x01
2480 #define _C2NCH1 0x02
2481 #define _C2NCH2 0x04
2482 #define _C2NCH3 0x08
2484 //==============================================================================
2487 //==============================================================================
2490 extern __at(0x0119) __sfr CM2PSEL
;
2508 unsigned C2PCH0
: 1;
2509 unsigned C2PCH1
: 1;
2510 unsigned C2PCH2
: 1;
2511 unsigned C2PCH3
: 1;
2531 extern __at(0x0119) volatile __CM2PSELbits_t CM2PSELbits
;
2533 #define _CM2PSEL_PCH0 0x01
2534 #define _CM2PSEL_C2PCH0 0x01
2535 #define _CM2PSEL_PCH1 0x02
2536 #define _CM2PSEL_C2PCH1 0x02
2537 #define _CM2PSEL_PCH2 0x04
2538 #define _CM2PSEL_C2PCH2 0x04
2539 #define _CM2PSEL_PCH3 0x08
2540 #define _CM2PSEL_C2PCH3 0x08
2542 //==============================================================================
2545 //==============================================================================
2548 extern __at(0x011A) __sfr CM3CON0
;
2556 unsigned Reserved
: 1;
2566 unsigned C3SYNC
: 1;
2577 extern __at(0x011A) volatile __CM3CON0bits_t CM3CON0bits
;
2579 #define _CM3CON0_SYNC 0x01
2580 #define _CM3CON0_C3SYNC 0x01
2581 #define _CM3CON0_HYS 0x02
2582 #define _CM3CON0_C3HYS 0x02
2583 #define _CM3CON0_Reserved 0x04
2584 #define _CM3CON0_C3SP 0x04
2585 #define _CM3CON0_ZLF 0x08
2586 #define _CM3CON0_C3ZLF 0x08
2587 #define _CM3CON0_POL 0x10
2588 #define _CM3CON0_C3POL 0x10
2589 #define _CM3CON0_OUT 0x40
2590 #define _CM3CON0_C3OUT 0x40
2591 #define _CM3CON0_ON 0x80
2592 #define _CM3CON0_C3ON 0x80
2594 //==============================================================================
2597 //==============================================================================
2600 extern __at(0x011B) __sfr CM3CON1
;
2618 unsigned C3INTN
: 1;
2619 unsigned C3INTP
: 1;
2629 extern __at(0x011B) volatile __CM3CON1bits_t CM3CON1bits
;
2631 #define _CM3CON1_INTN 0x01
2632 #define _CM3CON1_C3INTN 0x01
2633 #define _CM3CON1_INTP 0x02
2634 #define _CM3CON1_C3INTP 0x02
2636 //==============================================================================
2639 //==============================================================================
2642 extern __at(0x011C) __sfr CM3NSEL
;
2648 unsigned C3NCH0
: 1;
2649 unsigned C3NCH1
: 1;
2650 unsigned C3NCH2
: 1;
2651 unsigned C3NCH3
: 1;
2665 extern __at(0x011C) volatile __CM3NSELbits_t CM3NSELbits
;
2667 #define _C3NCH0 0x01
2668 #define _C3NCH1 0x02
2669 #define _C3NCH2 0x04
2670 #define _C3NCH3 0x08
2672 //==============================================================================
2675 //==============================================================================
2678 extern __at(0x011D) __sfr CM3PSEL
;
2696 unsigned C3PCH0
: 1;
2697 unsigned C3PCH1
: 1;
2698 unsigned C3PCH2
: 1;
2699 unsigned C3PCH3
: 1;
2719 extern __at(0x011D) volatile __CM3PSELbits_t CM3PSELbits
;
2721 #define _CM3PSEL_PCH0 0x01
2722 #define _CM3PSEL_C3PCH0 0x01
2723 #define _CM3PSEL_PCH1 0x02
2724 #define _CM3PSEL_C3PCH1 0x02
2725 #define _CM3PSEL_PCH2 0x04
2726 #define _CM3PSEL_C3PCH2 0x04
2727 #define _CM3PSEL_PCH3 0x08
2728 #define _CM3PSEL_C3PCH3 0x08
2730 //==============================================================================
2733 //==============================================================================
2736 extern __at(0x018C) __sfr ANSELA
;
2759 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
2768 //==============================================================================
2771 //==============================================================================
2774 extern __at(0x018D) __sfr ANSELB
;
2797 extern __at(0x018D) volatile __ANSELBbits_t ANSELBbits
;
2806 //==============================================================================
2809 //==============================================================================
2812 extern __at(0x018E) __sfr ANSELC
;
2826 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
2835 //==============================================================================
2837 extern __at(0x0191) __sfr PMADR
;
2838 extern __at(0x0191) __sfr PMADRL
;
2839 extern __at(0x0192) __sfr PMADRH
;
2840 extern __at(0x0193) __sfr PMDAT
;
2841 extern __at(0x0193) __sfr PMDATL
;
2842 extern __at(0x0194) __sfr PMDATH
;
2844 //==============================================================================
2847 extern __at(0x0195) __sfr PMCON1
;
2861 extern __at(0x0195) volatile __PMCON1bits_t PMCON1bits
;
2871 //==============================================================================
2873 extern __at(0x0196) __sfr PMCON2
;
2874 extern __at(0x0199) __sfr RC1REG
;
2875 extern __at(0x0199) __sfr RCREG
;
2876 extern __at(0x0199) __sfr RCREG1
;
2877 extern __at(0x019A) __sfr TX1REG
;
2878 extern __at(0x019A) __sfr TXREG
;
2879 extern __at(0x019A) __sfr TXREG1
;
2880 extern __at(0x019B) __sfr SP1BRG
;
2881 extern __at(0x019B) __sfr SP1BRGL
;
2882 extern __at(0x019B) __sfr SPBRG
;
2883 extern __at(0x019B) __sfr SPBRG1
;
2884 extern __at(0x019B) __sfr SPBRGL
;
2885 extern __at(0x019C) __sfr SP1BRGH
;
2886 extern __at(0x019C) __sfr SPBRGH
;
2887 extern __at(0x019C) __sfr SPBRGH1
;
2889 //==============================================================================
2892 extern __at(0x019D) __sfr RC1STA
;
2906 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
2917 //==============================================================================
2920 //==============================================================================
2923 extern __at(0x019D) __sfr RCSTA
;
2937 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
2939 #define _RCSTA_RX9D 0x01
2940 #define _RCSTA_OERR 0x02
2941 #define _RCSTA_FERR 0x04
2942 #define _RCSTA_ADDEN 0x08
2943 #define _RCSTA_CREN 0x10
2944 #define _RCSTA_SREN 0x20
2945 #define _RCSTA_RX9 0x40
2946 #define _RCSTA_SPEN 0x80
2948 //==============================================================================
2951 //==============================================================================
2954 extern __at(0x019D) __sfr RCSTA1
;
2968 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
2970 #define _RCSTA1_RX9D 0x01
2971 #define _RCSTA1_OERR 0x02
2972 #define _RCSTA1_FERR 0x04
2973 #define _RCSTA1_ADDEN 0x08
2974 #define _RCSTA1_CREN 0x10
2975 #define _RCSTA1_SREN 0x20
2976 #define _RCSTA1_RX9 0x40
2977 #define _RCSTA1_SPEN 0x80
2979 //==============================================================================
2982 //==============================================================================
2985 extern __at(0x019E) __sfr TX1STA
;
2999 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
3001 #define _TX1STA_TX9D 0x01
3002 #define _TX1STA_TRMT 0x02
3003 #define _TX1STA_BRGH 0x04
3004 #define _TX1STA_SENDB 0x08
3005 #define _TX1STA_SYNC 0x10
3006 #define _TX1STA_TXEN 0x20
3007 #define _TX1STA_TX9 0x40
3008 #define _TX1STA_CSRC 0x80
3010 //==============================================================================
3013 //==============================================================================
3016 extern __at(0x019E) __sfr TXSTA
;
3030 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
3032 #define _TXSTA_TX9D 0x01
3033 #define _TXSTA_TRMT 0x02
3034 #define _TXSTA_BRGH 0x04
3035 #define _TXSTA_SENDB 0x08
3036 #define _TXSTA_SYNC 0x10
3037 #define _TXSTA_TXEN 0x20
3038 #define _TXSTA_TX9 0x40
3039 #define _TXSTA_CSRC 0x80
3041 //==============================================================================
3044 //==============================================================================
3047 extern __at(0x019E) __sfr TXSTA1
;
3061 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
3063 #define _TXSTA1_TX9D 0x01
3064 #define _TXSTA1_TRMT 0x02
3065 #define _TXSTA1_BRGH 0x04
3066 #define _TXSTA1_SENDB 0x08
3067 #define _TXSTA1_SYNC 0x10
3068 #define _TXSTA1_TXEN 0x20
3069 #define _TXSTA1_TX9 0x40
3070 #define _TXSTA1_CSRC 0x80
3072 //==============================================================================
3075 //==============================================================================
3078 extern __at(0x019F) __sfr BAUD1CON
;
3089 unsigned ABDOVF
: 1;
3092 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
3099 #define _ABDOVF 0x80
3101 //==============================================================================
3104 //==============================================================================
3107 extern __at(0x019F) __sfr BAUDCON
;
3118 unsigned ABDOVF
: 1;
3121 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
3123 #define _BAUDCON_ABDEN 0x01
3124 #define _BAUDCON_WUE 0x02
3125 #define _BAUDCON_BRG16 0x08
3126 #define _BAUDCON_SCKP 0x10
3127 #define _BAUDCON_RCIDL 0x40
3128 #define _BAUDCON_ABDOVF 0x80
3130 //==============================================================================
3133 //==============================================================================
3136 extern __at(0x019F) __sfr BAUDCON1
;
3147 unsigned ABDOVF
: 1;
3150 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
3152 #define _BAUDCON1_ABDEN 0x01
3153 #define _BAUDCON1_WUE 0x02
3154 #define _BAUDCON1_BRG16 0x08
3155 #define _BAUDCON1_SCKP 0x10
3156 #define _BAUDCON1_RCIDL 0x40
3157 #define _BAUDCON1_ABDOVF 0x80
3159 //==============================================================================
3162 //==============================================================================
3165 extern __at(0x019F) __sfr BAUDCTL
;
3176 unsigned ABDOVF
: 1;
3179 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
3181 #define _BAUDCTL_ABDEN 0x01
3182 #define _BAUDCTL_WUE 0x02
3183 #define _BAUDCTL_BRG16 0x08
3184 #define _BAUDCTL_SCKP 0x10
3185 #define _BAUDCTL_RCIDL 0x40
3186 #define _BAUDCTL_ABDOVF 0x80
3188 //==============================================================================
3191 //==============================================================================
3194 extern __at(0x019F) __sfr BAUDCTL1
;
3205 unsigned ABDOVF
: 1;
3208 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
3210 #define _BAUDCTL1_ABDEN 0x01
3211 #define _BAUDCTL1_WUE 0x02
3212 #define _BAUDCTL1_BRG16 0x08
3213 #define _BAUDCTL1_SCKP 0x10
3214 #define _BAUDCTL1_RCIDL 0x40
3215 #define _BAUDCTL1_ABDOVF 0x80
3217 //==============================================================================
3220 //==============================================================================
3223 extern __at(0x020C) __sfr WPUA
;
3237 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
3248 //==============================================================================
3251 //==============================================================================
3254 extern __at(0x020D) __sfr WPUB
;
3268 extern __at(0x020D) volatile __WPUBbits_t WPUBbits
;
3279 //==============================================================================
3282 //==============================================================================
3285 extern __at(0x020E) __sfr WPUC
;
3299 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
3310 //==============================================================================
3313 //==============================================================================
3316 extern __at(0x0210) __sfr WPUE
;
3330 extern __at(0x0210) volatile __WPUEbits_t WPUEbits
;
3334 //==============================================================================
3337 //==============================================================================
3340 extern __at(0x0211) __sfr SSP1BUF
;
3346 unsigned SSP1BUF0
: 1;
3347 unsigned SSP1BUF1
: 1;
3348 unsigned SSP1BUF2
: 1;
3349 unsigned SSP1BUF3
: 1;
3350 unsigned SSP1BUF4
: 1;
3351 unsigned SSP1BUF5
: 1;
3352 unsigned SSP1BUF6
: 1;
3353 unsigned SSP1BUF7
: 1;
3369 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
3371 #define _SSP1BUF0 0x01
3373 #define _SSP1BUF1 0x02
3375 #define _SSP1BUF2 0x04
3377 #define _SSP1BUF3 0x08
3379 #define _SSP1BUF4 0x10
3381 #define _SSP1BUF5 0x20
3383 #define _SSP1BUF6 0x40
3385 #define _SSP1BUF7 0x80
3388 //==============================================================================
3391 //==============================================================================
3394 extern __at(0x0211) __sfr SSPBUF
;
3400 unsigned SSP1BUF0
: 1;
3401 unsigned SSP1BUF1
: 1;
3402 unsigned SSP1BUF2
: 1;
3403 unsigned SSP1BUF3
: 1;
3404 unsigned SSP1BUF4
: 1;
3405 unsigned SSP1BUF5
: 1;
3406 unsigned SSP1BUF6
: 1;
3407 unsigned SSP1BUF7
: 1;
3423 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
3425 #define _SSPBUF_SSP1BUF0 0x01
3426 #define _SSPBUF_BUF0 0x01
3427 #define _SSPBUF_SSP1BUF1 0x02
3428 #define _SSPBUF_BUF1 0x02
3429 #define _SSPBUF_SSP1BUF2 0x04
3430 #define _SSPBUF_BUF2 0x04
3431 #define _SSPBUF_SSP1BUF3 0x08
3432 #define _SSPBUF_BUF3 0x08
3433 #define _SSPBUF_SSP1BUF4 0x10
3434 #define _SSPBUF_BUF4 0x10
3435 #define _SSPBUF_SSP1BUF5 0x20
3436 #define _SSPBUF_BUF5 0x20
3437 #define _SSPBUF_SSP1BUF6 0x40
3438 #define _SSPBUF_BUF6 0x40
3439 #define _SSPBUF_SSP1BUF7 0x80
3440 #define _SSPBUF_BUF7 0x80
3442 //==============================================================================
3445 //==============================================================================
3448 extern __at(0x0212) __sfr SSP1ADD
;
3454 unsigned SSP1ADD0
: 1;
3455 unsigned SSP1ADD1
: 1;
3456 unsigned SSP1ADD2
: 1;
3457 unsigned SSP1ADD3
: 1;
3458 unsigned SSP1ADD4
: 1;
3459 unsigned SSP1ADD5
: 1;
3460 unsigned SSP1ADD6
: 1;
3461 unsigned SSP1ADD7
: 1;
3477 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
3479 #define _SSP1ADD0 0x01
3481 #define _SSP1ADD1 0x02
3483 #define _SSP1ADD2 0x04
3485 #define _SSP1ADD3 0x08
3487 #define _SSP1ADD4 0x10
3489 #define _SSP1ADD5 0x20
3491 #define _SSP1ADD6 0x40
3493 #define _SSP1ADD7 0x80
3496 //==============================================================================
3499 //==============================================================================
3502 extern __at(0x0212) __sfr SSPADD
;
3508 unsigned SSP1ADD0
: 1;
3509 unsigned SSP1ADD1
: 1;
3510 unsigned SSP1ADD2
: 1;
3511 unsigned SSP1ADD3
: 1;
3512 unsigned SSP1ADD4
: 1;
3513 unsigned SSP1ADD5
: 1;
3514 unsigned SSP1ADD6
: 1;
3515 unsigned SSP1ADD7
: 1;
3531 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
3533 #define _SSPADD_SSP1ADD0 0x01
3534 #define _SSPADD_ADD0 0x01
3535 #define _SSPADD_SSP1ADD1 0x02
3536 #define _SSPADD_ADD1 0x02
3537 #define _SSPADD_SSP1ADD2 0x04
3538 #define _SSPADD_ADD2 0x04
3539 #define _SSPADD_SSP1ADD3 0x08
3540 #define _SSPADD_ADD3 0x08
3541 #define _SSPADD_SSP1ADD4 0x10
3542 #define _SSPADD_ADD4 0x10
3543 #define _SSPADD_SSP1ADD5 0x20
3544 #define _SSPADD_ADD5 0x20
3545 #define _SSPADD_SSP1ADD6 0x40
3546 #define _SSPADD_ADD6 0x40
3547 #define _SSPADD_SSP1ADD7 0x80
3548 #define _SSPADD_ADD7 0x80
3550 //==============================================================================
3553 //==============================================================================
3556 extern __at(0x0213) __sfr SSP1MSK
;
3562 unsigned SSP1MSK0
: 1;
3563 unsigned SSP1MSK1
: 1;
3564 unsigned SSP1MSK2
: 1;
3565 unsigned SSP1MSK3
: 1;
3566 unsigned SSP1MSK4
: 1;
3567 unsigned SSP1MSK5
: 1;
3568 unsigned SSP1MSK6
: 1;
3569 unsigned SSP1MSK7
: 1;
3585 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
3587 #define _SSP1MSK0 0x01
3589 #define _SSP1MSK1 0x02
3591 #define _SSP1MSK2 0x04
3593 #define _SSP1MSK3 0x08
3595 #define _SSP1MSK4 0x10
3597 #define _SSP1MSK5 0x20
3599 #define _SSP1MSK6 0x40
3601 #define _SSP1MSK7 0x80
3604 //==============================================================================
3607 //==============================================================================
3610 extern __at(0x0213) __sfr SSPMSK
;
3616 unsigned SSP1MSK0
: 1;
3617 unsigned SSP1MSK1
: 1;
3618 unsigned SSP1MSK2
: 1;
3619 unsigned SSP1MSK3
: 1;
3620 unsigned SSP1MSK4
: 1;
3621 unsigned SSP1MSK5
: 1;
3622 unsigned SSP1MSK6
: 1;
3623 unsigned SSP1MSK7
: 1;
3639 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
3641 #define _SSPMSK_SSP1MSK0 0x01
3642 #define _SSPMSK_MSK0 0x01
3643 #define _SSPMSK_SSP1MSK1 0x02
3644 #define _SSPMSK_MSK1 0x02
3645 #define _SSPMSK_SSP1MSK2 0x04
3646 #define _SSPMSK_MSK2 0x04
3647 #define _SSPMSK_SSP1MSK3 0x08
3648 #define _SSPMSK_MSK3 0x08
3649 #define _SSPMSK_SSP1MSK4 0x10
3650 #define _SSPMSK_MSK4 0x10
3651 #define _SSPMSK_SSP1MSK5 0x20
3652 #define _SSPMSK_MSK5 0x20
3653 #define _SSPMSK_SSP1MSK6 0x40
3654 #define _SSPMSK_MSK6 0x40
3655 #define _SSPMSK_SSP1MSK7 0x80
3656 #define _SSPMSK_MSK7 0x80
3658 //==============================================================================
3661 //==============================================================================
3664 extern __at(0x0214) __sfr SSP1STAT
;
3670 unsigned R_NOT_W
: 1;
3673 unsigned D_NOT_A
: 1;
3678 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
3682 #define _R_NOT_W 0x04
3685 #define _D_NOT_A 0x20
3689 //==============================================================================
3692 //==============================================================================
3695 extern __at(0x0214) __sfr SSPSTAT
;
3701 unsigned R_NOT_W
: 1;
3704 unsigned D_NOT_A
: 1;
3709 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
3711 #define _SSPSTAT_BF 0x01
3712 #define _SSPSTAT_UA 0x02
3713 #define _SSPSTAT_R_NOT_W 0x04
3714 #define _SSPSTAT_S 0x08
3715 #define _SSPSTAT_P 0x10
3716 #define _SSPSTAT_D_NOT_A 0x20
3717 #define _SSPSTAT_CKE 0x40
3718 #define _SSPSTAT_SMP 0x80
3720 //==============================================================================
3723 //==============================================================================
3726 extern __at(0x0215) __sfr SSP1CON
;
3749 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
3760 //==============================================================================
3763 //==============================================================================
3766 extern __at(0x0215) __sfr SSP1CON1
;
3789 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
3791 #define _SSP1CON1_SSPM0 0x01
3792 #define _SSP1CON1_SSPM1 0x02
3793 #define _SSP1CON1_SSPM2 0x04
3794 #define _SSP1CON1_SSPM3 0x08
3795 #define _SSP1CON1_CKP 0x10
3796 #define _SSP1CON1_SSPEN 0x20
3797 #define _SSP1CON1_SSPOV 0x40
3798 #define _SSP1CON1_WCOL 0x80
3800 //==============================================================================
3803 //==============================================================================
3806 extern __at(0x0215) __sfr SSPCON
;
3829 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
3831 #define _SSPCON_SSPM0 0x01
3832 #define _SSPCON_SSPM1 0x02
3833 #define _SSPCON_SSPM2 0x04
3834 #define _SSPCON_SSPM3 0x08
3835 #define _SSPCON_CKP 0x10
3836 #define _SSPCON_SSPEN 0x20
3837 #define _SSPCON_SSPOV 0x40
3838 #define _SSPCON_WCOL 0x80
3840 //==============================================================================
3843 //==============================================================================
3846 extern __at(0x0215) __sfr SSPCON1
;
3869 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
3871 #define _SSPCON1_SSPM0 0x01
3872 #define _SSPCON1_SSPM1 0x02
3873 #define _SSPCON1_SSPM2 0x04
3874 #define _SSPCON1_SSPM3 0x08
3875 #define _SSPCON1_CKP 0x10
3876 #define _SSPCON1_SSPEN 0x20
3877 #define _SSPCON1_SSPOV 0x40
3878 #define _SSPCON1_WCOL 0x80
3880 //==============================================================================
3883 //==============================================================================
3886 extern __at(0x0216) __sfr SSP1CON2
;
3896 unsigned ACKSTAT
: 1;
3900 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
3908 #define _ACKSTAT 0x40
3911 //==============================================================================
3914 //==============================================================================
3917 extern __at(0x0216) __sfr SSPCON2
;
3927 unsigned ACKSTAT
: 1;
3931 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
3933 #define _SSPCON2_SEN 0x01
3934 #define _SSPCON2_RSEN 0x02
3935 #define _SSPCON2_PEN 0x04
3936 #define _SSPCON2_RCEN 0x08
3937 #define _SSPCON2_ACKEN 0x10
3938 #define _SSPCON2_ACKDT 0x20
3939 #define _SSPCON2_ACKSTAT 0x40
3940 #define _SSPCON2_GCEN 0x80
3942 //==============================================================================
3945 //==============================================================================
3948 extern __at(0x0217) __sfr SSP1CON3
;
3959 unsigned ACKTIM
: 1;
3962 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
3971 #define _ACKTIM 0x80
3973 //==============================================================================
3976 //==============================================================================
3979 extern __at(0x0217) __sfr SSPCON3
;
3990 unsigned ACKTIM
: 1;
3993 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
3995 #define _SSPCON3_DHEN 0x01
3996 #define _SSPCON3_AHEN 0x02
3997 #define _SSPCON3_SBCDE 0x04
3998 #define _SSPCON3_SDAHT 0x08
3999 #define _SSPCON3_BOEN 0x10
4000 #define _SSPCON3_SCIE 0x20
4001 #define _SSPCON3_PCIE 0x40
4002 #define _SSPCON3_ACKTIM 0x80
4004 //==============================================================================
4007 //==============================================================================
4010 extern __at(0x021B) __sfr MD3CON0
;
4028 unsigned MD3BIT
: 1;
4032 unsigned MD3OPOL
: 1;
4033 unsigned MD3OUT
: 1;
4039 extern __at(0x021B) volatile __MD3CON0bits_t MD3CON0bits
;
4041 #define _MD3CON0_BIT 0x01
4042 #define _MD3CON0_MD3BIT 0x01
4043 #define _MD3CON0_OPOL 0x10
4044 #define _MD3CON0_MD3OPOL 0x10
4045 #define _MD3CON0_OUT 0x20
4046 #define _MD3CON0_MD3OUT 0x20
4047 #define _MD3CON0_EN 0x80
4048 #define _MD3CON0_MD3EN 0x80
4050 //==============================================================================
4053 //==============================================================================
4056 extern __at(0x021C) __sfr MD3CON1
;
4062 unsigned CLSYNC
: 1;
4066 unsigned CHSYNC
: 1;
4074 unsigned MD3CLSYNC
: 1;
4075 unsigned MD3CLPOL
: 1;
4078 unsigned MD3CHSYNC
: 1;
4079 unsigned MD3CHPOL
: 1;
4085 extern __at(0x021C) volatile __MD3CON1bits_t MD3CON1bits
;
4087 #define _MD3CON1_CLSYNC 0x01
4088 #define _MD3CON1_MD3CLSYNC 0x01
4089 #define _MD3CON1_CLPOL 0x02
4090 #define _MD3CON1_MD3CLPOL 0x02
4091 #define _MD3CON1_CHSYNC 0x10
4092 #define _MD3CON1_MD3CHSYNC 0x10
4093 #define _MD3CON1_CHPOL 0x20
4094 #define _MD3CON1_MD3CHPOL 0x20
4096 //==============================================================================
4099 //==============================================================================
4102 extern __at(0x021D) __sfr MD3SRC
;
4120 unsigned MD3MS0
: 1;
4121 unsigned MD3MS1
: 1;
4122 unsigned MD3MS2
: 1;
4123 unsigned MD3MS3
: 1;
4124 unsigned MD3MS4
: 1;
4143 extern __at(0x021D) volatile __MD3SRCbits_t MD3SRCbits
;
4145 #define _MD3SRC_MS0 0x01
4146 #define _MD3SRC_MD3MS0 0x01
4147 #define _MD3SRC_MS1 0x02
4148 #define _MD3SRC_MD3MS1 0x02
4149 #define _MD3SRC_MS2 0x04
4150 #define _MD3SRC_MD3MS2 0x04
4151 #define _MD3SRC_MS3 0x08
4152 #define _MD3SRC_MD3MS3 0x08
4153 #define _MD3SRC_MS4 0x10
4154 #define _MD3SRC_MD3MS4 0x10
4156 //==============================================================================
4159 //==============================================================================
4162 extern __at(0x021E) __sfr MD3CARL
;
4180 unsigned MD3CL0
: 1;
4181 unsigned MD3CL1
: 1;
4182 unsigned MD3CL2
: 1;
4183 unsigned MD3CL3
: 1;
4203 extern __at(0x021E) volatile __MD3CARLbits_t MD3CARLbits
;
4205 #define _MD3CARL_CL0 0x01
4206 #define _MD3CARL_MD3CL0 0x01
4207 #define _MD3CARL_CL1 0x02
4208 #define _MD3CARL_MD3CL1 0x02
4209 #define _MD3CARL_CL2 0x04
4210 #define _MD3CARL_MD3CL2 0x04
4211 #define _MD3CARL_CL3 0x08
4212 #define _MD3CARL_MD3CL3 0x08
4213 #define _MD3CARL_CL4 0x10
4215 //==============================================================================
4218 //==============================================================================
4221 extern __at(0x021F) __sfr MD3CARH
;
4239 unsigned MD3CH0
: 1;
4240 unsigned MD3CH1
: 1;
4241 unsigned MD3CH2
: 1;
4242 unsigned MD3CH3
: 1;
4262 extern __at(0x021F) volatile __MD3CARHbits_t MD3CARHbits
;
4264 #define _MD3CARH_CH0 0x01
4265 #define _MD3CARH_MD3CH0 0x01
4266 #define _MD3CARH_CH1 0x02
4267 #define _MD3CARH_MD3CH1 0x02
4268 #define _MD3CARH_CH2 0x04
4269 #define _MD3CARH_MD3CH2 0x04
4270 #define _MD3CARH_CH3 0x08
4271 #define _MD3CARH_MD3CH3 0x08
4272 #define _MD3CARH_CH4 0x10
4274 //==============================================================================
4277 //==============================================================================
4280 extern __at(0x028C) __sfr ODCONA
;
4294 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
4305 //==============================================================================
4308 //==============================================================================
4311 extern __at(0x028D) __sfr ODCONB
;
4334 extern __at(0x028D) volatile __ODCONBbits_t ODCONBbits
;
4336 #define _ODCONB_ODA0 0x01
4337 #define _ODCONB_ODA1 0x02
4338 #define _ODCONB_ODA2 0x04
4339 #define _ODCONB_ODA3 0x08
4340 #define _ODCONB_ODB4 0x10
4341 #define _ODCONB_ODB5 0x20
4342 #define _ODCONB_ODB6 0x40
4343 #define _ODCONB_ODB7 0x80
4345 //==============================================================================
4348 //==============================================================================
4351 extern __at(0x028E) __sfr ODCONC
;
4365 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
4376 //==============================================================================
4378 extern __at(0x0291) __sfr CCPR1
;
4379 extern __at(0x0291) __sfr CCPR1L
;
4380 extern __at(0x0292) __sfr CCPR1H
;
4382 //==============================================================================
4385 extern __at(0x0293) __sfr CCP1CON
;
4403 unsigned CCP1MODE0
: 1;
4404 unsigned CCP1MODE1
: 1;
4405 unsigned CCP1MODE2
: 1;
4406 unsigned CCP1MODE3
: 1;
4407 unsigned CCP1FMT
: 1;
4408 unsigned CCP1OUT
: 1;
4410 unsigned CCP1EN
: 1;
4415 unsigned CCP1MODE
: 4;
4426 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
4429 #define _CCP1MODE0 0x01
4431 #define _CCP1MODE1 0x02
4433 #define _CCP1MODE2 0x04
4435 #define _CCP1MODE3 0x08
4437 #define _CCP1FMT 0x10
4439 #define _CCP1OUT 0x20
4441 #define _CCP1EN 0x80
4443 //==============================================================================
4446 //==============================================================================
4449 extern __at(0x0294) __sfr CCP1CAP
;
4467 unsigned CCP1CTS0
: 1;
4468 unsigned CCP1CTS1
: 1;
4469 unsigned CCP1CTS2
: 1;
4470 unsigned CCP1CTS3
: 1;
4479 unsigned CCP1CTS
: 4;
4490 extern __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits
;
4493 #define _CCP1CTS0 0x01
4495 #define _CCP1CTS1 0x02
4497 #define _CCP1CTS2 0x04
4499 #define _CCP1CTS3 0x08
4501 //==============================================================================
4503 extern __at(0x0295) __sfr CCPR2
;
4504 extern __at(0x0295) __sfr CCPR2L
;
4505 extern __at(0x0296) __sfr CCPR2H
;
4507 //==============================================================================
4510 extern __at(0x0297) __sfr CCP2CON
;
4528 unsigned CCP2MODE0
: 1;
4529 unsigned CCP2MODE1
: 1;
4530 unsigned CCP2MODE2
: 1;
4531 unsigned CCP2MODE3
: 1;
4532 unsigned CCP2FMT
: 1;
4533 unsigned CCP2OUT
: 1;
4535 unsigned CCP2EN
: 1;
4546 unsigned CCP2MODE
: 4;
4551 extern __at(0x0297) volatile __CCP2CONbits_t CCP2CONbits
;
4553 #define _CCP2CON_MODE0 0x01
4554 #define _CCP2CON_CCP2MODE0 0x01
4555 #define _CCP2CON_MODE1 0x02
4556 #define _CCP2CON_CCP2MODE1 0x02
4557 #define _CCP2CON_MODE2 0x04
4558 #define _CCP2CON_CCP2MODE2 0x04
4559 #define _CCP2CON_MODE3 0x08
4560 #define _CCP2CON_CCP2MODE3 0x08
4561 #define _CCP2CON_FMT 0x10
4562 #define _CCP2CON_CCP2FMT 0x10
4563 #define _CCP2CON_OUT 0x20
4564 #define _CCP2CON_CCP2OUT 0x20
4565 #define _CCP2CON_EN 0x80
4566 #define _CCP2CON_CCP2EN 0x80
4568 //==============================================================================
4571 //==============================================================================
4574 extern __at(0x0298) __sfr CCP2CAP
;
4592 unsigned CCP2CTS0
: 1;
4593 unsigned CCP2CTS1
: 1;
4594 unsigned CCP2CTS2
: 1;
4595 unsigned CCP2CTS3
: 1;
4610 unsigned CCP2CTS
: 4;
4615 extern __at(0x0298) volatile __CCP2CAPbits_t CCP2CAPbits
;
4617 #define _CCP2CAP_CTS0 0x01
4618 #define _CCP2CAP_CCP2CTS0 0x01
4619 #define _CCP2CAP_CTS1 0x02
4620 #define _CCP2CAP_CCP2CTS1 0x02
4621 #define _CCP2CAP_CTS2 0x04
4622 #define _CCP2CAP_CCP2CTS2 0x04
4623 #define _CCP2CAP_CTS3 0x08
4624 #define _CCP2CAP_CCP2CTS3 0x08
4626 //==============================================================================
4628 extern __at(0x0299) __sfr CCPR7
;
4629 extern __at(0x0299) __sfr CCPR7L
;
4630 extern __at(0x029A) __sfr CCPR7H
;
4632 //==============================================================================
4635 extern __at(0x029B) __sfr CCP7CON
;
4653 unsigned CCP7MODE0
: 1;
4654 unsigned CCP7MODE1
: 1;
4655 unsigned CCP7MODE2
: 1;
4656 unsigned CCP7MODE3
: 1;
4657 unsigned CCP7FMT
: 1;
4658 unsigned CCP7OUT
: 1;
4660 unsigned CCP7EN
: 1;
4665 unsigned CCP7MODE
: 4;
4676 extern __at(0x029B) volatile __CCP7CONbits_t CCP7CONbits
;
4678 #define _CCP7CON_MODE0 0x01
4679 #define _CCP7CON_CCP7MODE0 0x01
4680 #define _CCP7CON_MODE1 0x02
4681 #define _CCP7CON_CCP7MODE1 0x02
4682 #define _CCP7CON_MODE2 0x04
4683 #define _CCP7CON_CCP7MODE2 0x04
4684 #define _CCP7CON_MODE3 0x08
4685 #define _CCP7CON_CCP7MODE3 0x08
4686 #define _CCP7CON_FMT 0x10
4687 #define _CCP7CON_CCP7FMT 0x10
4688 #define _CCP7CON_OUT 0x20
4689 #define _CCP7CON_CCP7OUT 0x20
4690 #define _CCP7CON_EN 0x80
4691 #define _CCP7CON_CCP7EN 0x80
4693 //==============================================================================
4696 //==============================================================================
4699 extern __at(0x029C) __sfr CCP7CAP
;
4717 unsigned CCP7CTS0
: 1;
4718 unsigned CCP7CTS1
: 1;
4719 unsigned CCP7CTS2
: 1;
4720 unsigned CCP7CTS3
: 1;
4735 unsigned CCP7CTS
: 4;
4740 extern __at(0x029C) volatile __CCP7CAPbits_t CCP7CAPbits
;
4742 #define _CCP7CAP_CTS0 0x01
4743 #define _CCP7CAP_CCP7CTS0 0x01
4744 #define _CCP7CAP_CTS1 0x02
4745 #define _CCP7CAP_CCP7CTS1 0x02
4746 #define _CCP7CAP_CTS2 0x04
4747 #define _CCP7CAP_CCP7CTS2 0x04
4748 #define _CCP7CAP_CTS3 0x08
4749 #define _CCP7CAP_CCP7CTS3 0x08
4751 //==============================================================================
4754 //==============================================================================
4757 extern __at(0x029E) __sfr CCPTMRS1
;
4763 unsigned C1TSEL0
: 1;
4764 unsigned C1TSEL1
: 1;
4765 unsigned C2TSEL0
: 1;
4766 unsigned C2TSEL1
: 1;
4767 unsigned C7TSEL0
: 1;
4768 unsigned C7TSEL1
: 1;
4775 unsigned C1TSEL
: 2;
4782 unsigned C2TSEL
: 2;
4789 unsigned C7TSEL
: 2;
4794 extern __at(0x029E) volatile __CCPTMRS1bits_t CCPTMRS1bits
;
4796 #define _C1TSEL0 0x01
4797 #define _C1TSEL1 0x02
4798 #define _C2TSEL0 0x04
4799 #define _C2TSEL1 0x08
4800 #define _C7TSEL0 0x10
4801 #define _C7TSEL1 0x20
4803 //==============================================================================
4806 //==============================================================================
4809 extern __at(0x029F) __sfr CCPTMRS2
;
4815 unsigned P3TSEL0
: 1;
4816 unsigned P3TSEL1
: 1;
4817 unsigned P4TSEL0
: 1;
4818 unsigned P4TSEL1
: 1;
4819 unsigned P9TSEL0
: 1;
4820 unsigned P9TSEL1
: 1;
4827 unsigned P3TSEL
: 2;
4834 unsigned P4TSEL
: 2;
4841 unsigned P9TSEL
: 2;
4846 extern __at(0x029F) volatile __CCPTMRS2bits_t CCPTMRS2bits
;
4848 #define _P3TSEL0 0x01
4849 #define _P3TSEL1 0x02
4850 #define _P4TSEL0 0x04
4851 #define _P4TSEL1 0x08
4852 #define _P9TSEL0 0x10
4853 #define _P9TSEL1 0x20
4855 //==============================================================================
4858 //==============================================================================
4861 extern __at(0x030C) __sfr SLRCONA
;
4875 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
4886 //==============================================================================
4889 //==============================================================================
4892 extern __at(0x030D) __sfr SLRCONB
;
4906 extern __at(0x030D) volatile __SLRCONBbits_t SLRCONBbits
;
4917 //==============================================================================
4920 //==============================================================================
4923 extern __at(0x030E) __sfr SLRCONC
;
4937 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
4948 //==============================================================================
4951 //==============================================================================
4954 extern __at(0x0315) __sfr MD1CON0
;
4972 unsigned MD1BIT
: 1;
4976 unsigned MD1OPOL
: 1;
4977 unsigned MD1OUT
: 1;
4983 extern __at(0x0315) volatile __MD1CON0bits_t MD1CON0bits
;
4985 #define _MD1CON0_BIT 0x01
4986 #define _MD1CON0_MD1BIT 0x01
4987 #define _MD1CON0_OPOL 0x10
4988 #define _MD1CON0_MD1OPOL 0x10
4989 #define _MD1CON0_OUT 0x20
4990 #define _MD1CON0_MD1OUT 0x20
4991 #define _MD1CON0_EN 0x80
4992 #define _MD1CON0_MD1EN 0x80
4994 //==============================================================================
4997 //==============================================================================
5000 extern __at(0x0316) __sfr MD1CON1
;
5006 unsigned CLSYNC
: 1;
5010 unsigned CHSYNC
: 1;
5018 unsigned MD1CLSYNC
: 1;
5019 unsigned MD1CLPOL
: 1;
5022 unsigned MD1CHSYNC
: 1;
5023 unsigned MD1CHPOL
: 1;
5029 extern __at(0x0316) volatile __MD1CON1bits_t MD1CON1bits
;
5031 #define _CLSYNC 0x01
5032 #define _MD1CLSYNC 0x01
5034 #define _MD1CLPOL 0x02
5035 #define _CHSYNC 0x10
5036 #define _MD1CHSYNC 0x10
5038 #define _MD1CHPOL 0x20
5040 //==============================================================================
5043 //==============================================================================
5046 extern __at(0x0317) __sfr MD1SRC
;
5064 unsigned MD1MS0
: 1;
5065 unsigned MD1MS1
: 1;
5066 unsigned MD1MS2
: 1;
5067 unsigned MD1MS3
: 1;
5068 unsigned MD1MS4
: 1;
5087 extern __at(0x0317) volatile __MD1SRCbits_t MD1SRCbits
;
5090 #define _MD1MS0 0x01
5092 #define _MD1MS1 0x02
5094 #define _MD1MS2 0x04
5096 #define _MD1MS3 0x08
5098 #define _MD1MS4 0x10
5100 //==============================================================================
5103 //==============================================================================
5106 extern __at(0x0318) __sfr MD1CARL
;
5124 unsigned MD1CL0
: 1;
5125 unsigned MD1CL1
: 1;
5126 unsigned MD1CL2
: 1;
5127 unsigned MD1CL3
: 1;
5147 extern __at(0x0318) volatile __MD1CARLbits_t MD1CARLbits
;
5150 #define _MD1CL0 0x01
5152 #define _MD1CL1 0x02
5154 #define _MD1CL2 0x04
5156 #define _MD1CL3 0x08
5159 //==============================================================================
5162 //==============================================================================
5165 extern __at(0x0319) __sfr MD1CARH
;
5183 unsigned MD1CH0
: 1;
5184 unsigned MD1CH1
: 1;
5185 unsigned MD1CH2
: 1;
5186 unsigned MD1CH3
: 1;
5206 extern __at(0x0319) volatile __MD1CARHbits_t MD1CARHbits
;
5209 #define _MD1CH0 0x01
5211 #define _MD1CH1 0x02
5213 #define _MD1CH2 0x04
5215 #define _MD1CH3 0x08
5218 //==============================================================================
5221 //==============================================================================
5224 extern __at(0x031B) __sfr MD2CON0
;
5242 unsigned MD2BIT
: 1;
5246 unsigned MD2OPOL
: 1;
5247 unsigned MD2OUT
: 1;
5253 extern __at(0x031B) volatile __MD2CON0bits_t MD2CON0bits
;
5255 #define _MD2CON0_BIT 0x01
5256 #define _MD2CON0_MD2BIT 0x01
5257 #define _MD2CON0_OPOL 0x10
5258 #define _MD2CON0_MD2OPOL 0x10
5259 #define _MD2CON0_OUT 0x20
5260 #define _MD2CON0_MD2OUT 0x20
5261 #define _MD2CON0_EN 0x80
5262 #define _MD2CON0_MD2EN 0x80
5264 //==============================================================================
5267 //==============================================================================
5270 extern __at(0x031C) __sfr MD2CON1
;
5276 unsigned CLSYNC
: 1;
5280 unsigned CHSYNC
: 1;
5288 unsigned MD2CLSYNC
: 1;
5289 unsigned MD2CLPOL
: 1;
5292 unsigned MD2CHSYNC
: 1;
5293 unsigned MD2CHPOL
: 1;
5299 extern __at(0x031C) volatile __MD2CON1bits_t MD2CON1bits
;
5301 #define _MD2CON1_CLSYNC 0x01
5302 #define _MD2CON1_MD2CLSYNC 0x01
5303 #define _MD2CON1_CLPOL 0x02
5304 #define _MD2CON1_MD2CLPOL 0x02
5305 #define _MD2CON1_CHSYNC 0x10
5306 #define _MD2CON1_MD2CHSYNC 0x10
5307 #define _MD2CON1_CHPOL 0x20
5308 #define _MD2CON1_MD2CHPOL 0x20
5310 //==============================================================================
5313 //==============================================================================
5316 extern __at(0x031D) __sfr MD2SRC
;
5334 unsigned MD2MS0
: 1;
5335 unsigned MD2MS1
: 1;
5336 unsigned MD2MS2
: 1;
5337 unsigned MD2MS3
: 1;
5338 unsigned MD2MS4
: 1;
5357 extern __at(0x031D) volatile __MD2SRCbits_t MD2SRCbits
;
5359 #define _MD2SRC_MS0 0x01
5360 #define _MD2SRC_MD2MS0 0x01
5361 #define _MD2SRC_MS1 0x02
5362 #define _MD2SRC_MD2MS1 0x02
5363 #define _MD2SRC_MS2 0x04
5364 #define _MD2SRC_MD2MS2 0x04
5365 #define _MD2SRC_MS3 0x08
5366 #define _MD2SRC_MD2MS3 0x08
5367 #define _MD2SRC_MS4 0x10
5368 #define _MD2SRC_MD2MS4 0x10
5370 //==============================================================================
5373 //==============================================================================
5376 extern __at(0x031E) __sfr MD2CARL
;
5394 unsigned MD2CL0
: 1;
5395 unsigned MD2CL1
: 1;
5396 unsigned MD2CL2
: 1;
5397 unsigned MD2CL3
: 1;
5417 extern __at(0x031E) volatile __MD2CARLbits_t MD2CARLbits
;
5419 #define _MD2CARL_CL0 0x01
5420 #define _MD2CARL_MD2CL0 0x01
5421 #define _MD2CARL_CL1 0x02
5422 #define _MD2CARL_MD2CL1 0x02
5423 #define _MD2CARL_CL2 0x04
5424 #define _MD2CARL_MD2CL2 0x04
5425 #define _MD2CARL_CL3 0x08
5426 #define _MD2CARL_MD2CL3 0x08
5427 #define _MD2CARL_CL4 0x10
5429 //==============================================================================
5432 //==============================================================================
5435 extern __at(0x031F) __sfr MD2CARH
;
5453 unsigned MD2CH0
: 1;
5454 unsigned MD2CH1
: 1;
5455 unsigned MD2CH2
: 1;
5456 unsigned MD2CH3
: 1;
5476 extern __at(0x031F) volatile __MD2CARHbits_t MD2CARHbits
;
5478 #define _MD2CARH_CH0 0x01
5479 #define _MD2CARH_MD2CH0 0x01
5480 #define _MD2CARH_CH1 0x02
5481 #define _MD2CARH_MD2CH1 0x02
5482 #define _MD2CARH_CH2 0x04
5483 #define _MD2CARH_MD2CH2 0x04
5484 #define _MD2CARH_CH3 0x08
5485 #define _MD2CARH_MD2CH3 0x08
5486 #define _MD2CARH_CH4 0x10
5488 //==============================================================================
5491 //==============================================================================
5494 extern __at(0x038C) __sfr INLVLA
;
5500 unsigned INLVLA0
: 1;
5501 unsigned INLVLA1
: 1;
5502 unsigned INLVLA2
: 1;
5503 unsigned INLVLA3
: 1;
5504 unsigned INLVLA4
: 1;
5505 unsigned INLVLA5
: 1;
5506 unsigned INLVA6
: 1;
5507 unsigned INLVA7
: 1;
5512 unsigned INLVLA
: 6;
5517 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
5519 #define _INLVLA0 0x01
5520 #define _INLVLA1 0x02
5521 #define _INLVLA2 0x04
5522 #define _INLVLA3 0x08
5523 #define _INLVLA4 0x10
5524 #define _INLVLA5 0x20
5525 #define _INLVA6 0x40
5526 #define _INLVA7 0x80
5528 //==============================================================================
5531 //==============================================================================
5534 extern __at(0x038D) __sfr INLVLB
;
5540 unsigned INLVB0
: 1;
5541 unsigned INLVB1
: 1;
5542 unsigned INLVB2
: 1;
5543 unsigned INLVB3
: 1;
5544 unsigned INLVLB4
: 1;
5545 unsigned INLVLB5
: 1;
5546 unsigned INLVLB6
: 1;
5547 unsigned INLVLB7
: 1;
5557 extern __at(0x038D) volatile __INLVLBbits_t INLVLBbits
;
5559 #define _INLVB0 0x01
5560 #define _INLVB1 0x02
5561 #define _INLVB2 0x04
5562 #define _INLVB3 0x08
5563 #define _INLVLB4 0x10
5564 #define _INLVLB5 0x20
5565 #define _INLVLB6 0x40
5566 #define _INLVLB7 0x80
5568 //==============================================================================
5571 //==============================================================================
5574 extern __at(0x038E) __sfr INLVLC
;
5578 unsigned INLVLC0
: 1;
5579 unsigned INLVLC1
: 1;
5580 unsigned INLVLC2
: 1;
5581 unsigned INLVLC3
: 1;
5582 unsigned INLVLC4
: 1;
5583 unsigned INLVLC5
: 1;
5584 unsigned INLVLC6
: 1;
5585 unsigned INLVLC7
: 1;
5588 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
5590 #define _INLVLC0 0x01
5591 #define _INLVLC1 0x02
5592 #define _INLVLC2 0x04
5593 #define _INLVLC3 0x08
5594 #define _INLVLC4 0x10
5595 #define _INLVLC5 0x20
5596 #define _INLVLC6 0x40
5597 #define _INLVLC7 0x80
5599 //==============================================================================
5602 //==============================================================================
5605 extern __at(0x0390) __sfr INLVE
;
5612 unsigned INLVE3
: 1;
5619 extern __at(0x0390) volatile __INLVEbits_t INLVEbits
;
5621 #define _INLVE3 0x08
5623 //==============================================================================
5626 //==============================================================================
5629 extern __at(0x0391) __sfr IOCAP
;
5633 unsigned IOCAP0
: 1;
5634 unsigned IOCAP1
: 1;
5635 unsigned IOCAP2
: 1;
5636 unsigned IOCAP3
: 1;
5637 unsigned IOCAP4
: 1;
5638 unsigned IOCAP5
: 1;
5639 unsigned IOCAP6
: 1;
5640 unsigned IOCAP7
: 1;
5643 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
5645 #define _IOCAP0 0x01
5646 #define _IOCAP1 0x02
5647 #define _IOCAP2 0x04
5648 #define _IOCAP3 0x08
5649 #define _IOCAP4 0x10
5650 #define _IOCAP5 0x20
5651 #define _IOCAP6 0x40
5652 #define _IOCAP7 0x80
5654 //==============================================================================
5657 //==============================================================================
5660 extern __at(0x0392) __sfr IOCAN
;
5664 unsigned IOCAN0
: 1;
5665 unsigned IOCAN1
: 1;
5666 unsigned IOCAN2
: 1;
5667 unsigned IOCAN3
: 1;
5668 unsigned IOCAN4
: 1;
5669 unsigned IOCAN5
: 1;
5670 unsigned IOCAN6
: 1;
5671 unsigned IOCAN7
: 1;
5674 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
5676 #define _IOCAN0 0x01
5677 #define _IOCAN1 0x02
5678 #define _IOCAN2 0x04
5679 #define _IOCAN3 0x08
5680 #define _IOCAN4 0x10
5681 #define _IOCAN5 0x20
5682 #define _IOCAN6 0x40
5683 #define _IOCAN7 0x80
5685 //==============================================================================
5688 //==============================================================================
5691 extern __at(0x0393) __sfr IOCAF
;
5695 unsigned IOCAF0
: 1;
5696 unsigned IOCAF1
: 1;
5697 unsigned IOCAF2
: 1;
5698 unsigned IOCAF3
: 1;
5699 unsigned IOCAF4
: 1;
5700 unsigned IOCAF5
: 1;
5701 unsigned IOCAF6
: 1;
5702 unsigned IOCAF7
: 1;
5705 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
5707 #define _IOCAF0 0x01
5708 #define _IOCAF1 0x02
5709 #define _IOCAF2 0x04
5710 #define _IOCAF3 0x08
5711 #define _IOCAF4 0x10
5712 #define _IOCAF5 0x20
5713 #define _IOCAF6 0x40
5714 #define _IOCAF7 0x80
5716 //==============================================================================
5719 //==============================================================================
5722 extern __at(0x0394) __sfr IOCBP
;
5726 unsigned IOCBP0
: 1;
5727 unsigned IOCBP1
: 1;
5728 unsigned IOCBP2
: 1;
5729 unsigned IOCBP3
: 1;
5730 unsigned IOCBP4
: 1;
5731 unsigned IOCBP5
: 1;
5732 unsigned IOCBP6
: 1;
5733 unsigned IOCBP7
: 1;
5736 extern __at(0x0394) volatile __IOCBPbits_t IOCBPbits
;
5738 #define _IOCBP0 0x01
5739 #define _IOCBP1 0x02
5740 #define _IOCBP2 0x04
5741 #define _IOCBP3 0x08
5742 #define _IOCBP4 0x10
5743 #define _IOCBP5 0x20
5744 #define _IOCBP6 0x40
5745 #define _IOCBP7 0x80
5747 //==============================================================================
5750 //==============================================================================
5753 extern __at(0x0395) __sfr IOCBN
;
5757 unsigned IOCBN0
: 1;
5758 unsigned IOCBN1
: 1;
5759 unsigned IOCBN2
: 1;
5760 unsigned IOCBN3
: 1;
5761 unsigned IOCBN4
: 1;
5762 unsigned IOCBN5
: 1;
5763 unsigned IOCBN6
: 1;
5764 unsigned IOCBN7
: 1;
5767 extern __at(0x0395) volatile __IOCBNbits_t IOCBNbits
;
5769 #define _IOCBN0 0x01
5770 #define _IOCBN1 0x02
5771 #define _IOCBN2 0x04
5772 #define _IOCBN3 0x08
5773 #define _IOCBN4 0x10
5774 #define _IOCBN5 0x20
5775 #define _IOCBN6 0x40
5776 #define _IOCBN7 0x80
5778 //==============================================================================
5781 //==============================================================================
5784 extern __at(0x0396) __sfr IOCBF
;
5788 unsigned IOCBF0
: 1;
5789 unsigned IOCBF1
: 1;
5790 unsigned IOCBF2
: 1;
5791 unsigned IOCBF3
: 1;
5792 unsigned IOCBF4
: 1;
5793 unsigned IOCBF5
: 1;
5794 unsigned IOCBF6
: 1;
5795 unsigned IOCBF7
: 1;
5798 extern __at(0x0396) volatile __IOCBFbits_t IOCBFbits
;
5800 #define _IOCBF0 0x01
5801 #define _IOCBF1 0x02
5802 #define _IOCBF2 0x04
5803 #define _IOCBF3 0x08
5804 #define _IOCBF4 0x10
5805 #define _IOCBF5 0x20
5806 #define _IOCBF6 0x40
5807 #define _IOCBF7 0x80
5809 //==============================================================================
5812 //==============================================================================
5815 extern __at(0x0397) __sfr IOCCP
;
5819 unsigned IOCCP0
: 1;
5820 unsigned IOCCP1
: 1;
5821 unsigned IOCCP2
: 1;
5822 unsigned IOCCP3
: 1;
5823 unsigned IOCCP4
: 1;
5824 unsigned IOCCP5
: 1;
5825 unsigned IOCCP6
: 1;
5826 unsigned IOCCP7
: 1;
5829 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
5831 #define _IOCCP0 0x01
5832 #define _IOCCP1 0x02
5833 #define _IOCCP2 0x04
5834 #define _IOCCP3 0x08
5835 #define _IOCCP4 0x10
5836 #define _IOCCP5 0x20
5837 #define _IOCCP6 0x40
5838 #define _IOCCP7 0x80
5840 //==============================================================================
5843 //==============================================================================
5846 extern __at(0x0398) __sfr IOCCN
;
5850 unsigned IOCCN0
: 1;
5851 unsigned IOCCN1
: 1;
5852 unsigned IOCCN2
: 1;
5853 unsigned IOCCN3
: 1;
5854 unsigned IOCCN4
: 1;
5855 unsigned IOCCN5
: 1;
5856 unsigned IOCCN6
: 1;
5857 unsigned IOCCN7
: 1;
5860 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
5862 #define _IOCCN0 0x01
5863 #define _IOCCN1 0x02
5864 #define _IOCCN2 0x04
5865 #define _IOCCN3 0x08
5866 #define _IOCCN4 0x10
5867 #define _IOCCN5 0x20
5868 #define _IOCCN6 0x40
5869 #define _IOCCN7 0x80
5871 //==============================================================================
5874 //==============================================================================
5877 extern __at(0x0399) __sfr IOCCF
;
5881 unsigned IOCCF0
: 1;
5882 unsigned IOCCF1
: 1;
5883 unsigned IOCCF2
: 1;
5884 unsigned IOCCF3
: 1;
5885 unsigned IOCCF4
: 1;
5886 unsigned IOCCF5
: 1;
5887 unsigned IOCCF6
: 1;
5888 unsigned IOCCF7
: 1;
5891 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
5893 #define _IOCCF0 0x01
5894 #define _IOCCF1 0x02
5895 #define _IOCCF2 0x04
5896 #define _IOCCF3 0x08
5897 #define _IOCCF4 0x10
5898 #define _IOCCF5 0x20
5899 #define _IOCCF6 0x40
5900 #define _IOCCF7 0x80
5902 //==============================================================================
5905 //==============================================================================
5908 extern __at(0x039D) __sfr IOCEP
;
5915 unsigned IOCEP3
: 1;
5922 extern __at(0x039D) volatile __IOCEPbits_t IOCEPbits
;
5924 #define _IOCEP3 0x08
5926 //==============================================================================
5929 //==============================================================================
5932 extern __at(0x039E) __sfr IOCEN
;
5939 unsigned IOCEN3
: 1;
5946 extern __at(0x039E) volatile __IOCENbits_t IOCENbits
;
5948 #define _IOCEN3 0x08
5950 //==============================================================================
5953 //==============================================================================
5956 extern __at(0x039F) __sfr IOCEF
;
5963 unsigned IOCEF3
: 1;
5970 extern __at(0x039F) volatile __IOCEFbits_t IOCEFbits
;
5972 #define _IOCEF3 0x08
5974 //==============================================================================
5977 //==============================================================================
5980 extern __at(0x040D) __sfr HIDRVB
;
6003 extern __at(0x040D) volatile __HIDRVBbits_t HIDRVBbits
;
6008 //==============================================================================
6010 extern __at(0x040F) __sfr TMR5
;
6011 extern __at(0x040F) __sfr TMR5L
;
6012 extern __at(0x0410) __sfr TMR5H
;
6014 //==============================================================================
6017 extern __at(0x0411) __sfr T5CON
;
6025 unsigned NOT_SYNC
: 1;
6038 unsigned SOSCEN
: 1;
6039 unsigned T5CKPS0
: 1;
6040 unsigned T5CKPS1
: 1;
6047 unsigned TMR5ON
: 1;
6049 unsigned NOT_T5SYNC
: 1;
6050 unsigned T5OSCEN
: 1;
6053 unsigned TMR5CS0
: 1;
6054 unsigned TMR5CS1
: 1;
6072 unsigned T5CKPS
: 2;
6086 unsigned TMR5CS
: 2;
6102 extern __at(0x0411) volatile __T5CONbits_t T5CONbits
;
6104 #define _T5CON_ON 0x01
6105 #define _T5CON_TMRON 0x01
6106 #define _T5CON_TMR5ON 0x01
6107 #define _T5CON_T5ON 0x01
6108 #define _T5CON_NOT_SYNC 0x04
6109 #define _T5CON_SYNC 0x04
6110 #define _T5CON_NOT_T5SYNC 0x04
6111 #define _T5CON_OSCEN 0x08
6112 #define _T5CON_SOSCEN 0x08
6113 #define _T5CON_T5OSCEN 0x08
6114 #define _T5CON_CKPS0 0x10
6115 #define _T5CON_T5CKPS0 0x10
6116 #define _T5CON_CKPS1 0x20
6117 #define _T5CON_T5CKPS1 0x20
6118 #define _T5CON_CS0 0x40
6119 #define _T5CON_T5CS0 0x40
6120 #define _T5CON_TMR5CS0 0x40
6121 #define _T5CON_CS1 0x80
6122 #define _T5CON_T5CS1 0x80
6123 #define _T5CON_TMR5CS1 0x80
6125 //==============================================================================
6128 //==============================================================================
6131 extern __at(0x0412) __sfr T5GCON
;
6140 unsigned GGO_NOT_DONE
: 1;
6149 unsigned T5GSS0
: 1;
6150 unsigned T5GSS1
: 1;
6151 unsigned T5GVAL
: 1;
6152 unsigned T5GGO_NOT_DONE
: 1;
6153 unsigned T5GSPM
: 1;
6155 unsigned T5GPOL
: 1;
6168 unsigned TMR5GE
: 1;
6184 extern __at(0x0412) volatile __T5GCONbits_t T5GCONbits
;
6186 #define _T5GCON_GSS0 0x01
6187 #define _T5GCON_T5GSS0 0x01
6188 #define _T5GCON_GSS1 0x02
6189 #define _T5GCON_T5GSS1 0x02
6190 #define _T5GCON_GVAL 0x04
6191 #define _T5GCON_T5GVAL 0x04
6192 #define _T5GCON_GGO_NOT_DONE 0x08
6193 #define _T5GCON_T5GGO_NOT_DONE 0x08
6194 #define _T5GCON_GSPM 0x10
6195 #define _T5GCON_T5GSPM 0x10
6196 #define _T5GCON_GTM 0x20
6197 #define _T5GCON_T5GTM 0x20
6198 #define _T5GCON_GPOL 0x40
6199 #define _T5GCON_T5GPOL 0x40
6200 #define _T5GCON_GE 0x80
6201 #define _T5GCON_T5GE 0x80
6202 #define _T5GCON_TMR5GE 0x80
6204 //==============================================================================
6206 extern __at(0x0413) __sfr T4TMR
;
6207 extern __at(0x0413) __sfr TMR4
;
6208 extern __at(0x0414) __sfr PR4
;
6209 extern __at(0x0414) __sfr T4PR
;
6211 //==============================================================================
6214 extern __at(0x0415) __sfr T4CON
;
6220 unsigned OUTPS0
: 1;
6221 unsigned OUTPS1
: 1;
6222 unsigned OUTPS2
: 1;
6223 unsigned OUTPS3
: 1;
6232 unsigned T4OUTPS0
: 1;
6233 unsigned T4OUTPS1
: 1;
6234 unsigned T4OUTPS2
: 1;
6235 unsigned T4OUTPS3
: 1;
6236 unsigned T4CKPS0
: 1;
6237 unsigned T4CKPS1
: 1;
6238 unsigned T4CKPS2
: 1;
6251 unsigned TMR4ON
: 1;
6256 unsigned T4OUTPS
: 4;
6276 unsigned T4CKPS
: 3;
6281 extern __at(0x0415) volatile __T4CONbits_t T4CONbits
;
6283 #define _T4CON_OUTPS0 0x01
6284 #define _T4CON_T4OUTPS0 0x01
6285 #define _T4CON_OUTPS1 0x02
6286 #define _T4CON_T4OUTPS1 0x02
6287 #define _T4CON_OUTPS2 0x04
6288 #define _T4CON_T4OUTPS2 0x04
6289 #define _T4CON_OUTPS3 0x08
6290 #define _T4CON_T4OUTPS3 0x08
6291 #define _T4CON_CKPS0 0x10
6292 #define _T4CON_T4CKPS0 0x10
6293 #define _T4CON_CKPS1 0x20
6294 #define _T4CON_T4CKPS1 0x20
6295 #define _T4CON_CKPS2 0x40
6296 #define _T4CON_T4CKPS2 0x40
6297 #define _T4CON_ON 0x80
6298 #define _T4CON_T4ON 0x80
6299 #define _T4CON_TMR4ON 0x80
6301 //==============================================================================
6304 //==============================================================================
6307 extern __at(0x0416) __sfr T4HLT
;
6318 unsigned CKSYNC
: 1;
6325 unsigned T4MODE0
: 1;
6326 unsigned T4MODE1
: 1;
6327 unsigned T4MODE2
: 1;
6328 unsigned T4MODE3
: 1;
6329 unsigned T4MODE4
: 1;
6330 unsigned T4CKSYNC
: 1;
6331 unsigned T4CKPOL
: 1;
6332 unsigned T4PSYNC
: 1;
6343 unsigned T4MODE
: 5;
6348 extern __at(0x0416) volatile __T4HLTbits_t T4HLTbits
;
6350 #define _T4HLT_MODE0 0x01
6351 #define _T4HLT_T4MODE0 0x01
6352 #define _T4HLT_MODE1 0x02
6353 #define _T4HLT_T4MODE1 0x02
6354 #define _T4HLT_MODE2 0x04
6355 #define _T4HLT_T4MODE2 0x04
6356 #define _T4HLT_MODE3 0x08
6357 #define _T4HLT_T4MODE3 0x08
6358 #define _T4HLT_MODE4 0x10
6359 #define _T4HLT_T4MODE4 0x10
6360 #define _T4HLT_CKSYNC 0x20
6361 #define _T4HLT_T4CKSYNC 0x20
6362 #define _T4HLT_CKPOL 0x40
6363 #define _T4HLT_T4CKPOL 0x40
6364 #define _T4HLT_PSYNC 0x80
6365 #define _T4HLT_T4PSYNC 0x80
6367 //==============================================================================
6370 //==============================================================================
6373 extern __at(0x0417) __sfr T4CLKCON
;
6414 extern __at(0x0417) volatile __T4CLKCONbits_t T4CLKCONbits
;
6416 #define _T4CLKCON_CS0 0x01
6417 #define _T4CLKCON_T4CS0 0x01
6418 #define _T4CLKCON_CS1 0x02
6419 #define _T4CLKCON_T4CS1 0x02
6420 #define _T4CLKCON_CS2 0x04
6421 #define _T4CLKCON_T4CS2 0x04
6422 #define _T4CLKCON_CS3 0x08
6423 #define _T4CLKCON_T4CS3 0x08
6425 //==============================================================================
6428 //==============================================================================
6431 extern __at(0x0418) __sfr T4RST
;
6449 unsigned T4RSEL0
: 1;
6450 unsigned T4RSEL1
: 1;
6451 unsigned T4RSEL2
: 1;
6452 unsigned T4RSEL3
: 1;
6453 unsigned T4RSEL4
: 1;
6461 unsigned T4RSEL
: 5;
6472 extern __at(0x0418) volatile __T4RSTbits_t T4RSTbits
;
6474 #define _T4RST_RSEL0 0x01
6475 #define _T4RST_T4RSEL0 0x01
6476 #define _T4RST_RSEL1 0x02
6477 #define _T4RST_T4RSEL1 0x02
6478 #define _T4RST_RSEL2 0x04
6479 #define _T4RST_T4RSEL2 0x04
6480 #define _T4RST_RSEL3 0x08
6481 #define _T4RST_T4RSEL3 0x08
6482 #define _T4RST_RSEL4 0x10
6483 #define _T4RST_T4RSEL4 0x10
6485 //==============================================================================
6487 extern __at(0x041A) __sfr T6TMR
;
6488 extern __at(0x041A) __sfr TMR6
;
6489 extern __at(0x041B) __sfr PR6
;
6490 extern __at(0x041B) __sfr T6PR
;
6492 //==============================================================================
6495 extern __at(0x041C) __sfr T6CON
;
6501 unsigned OUTPS0
: 1;
6502 unsigned OUTPS1
: 1;
6503 unsigned OUTPS2
: 1;
6504 unsigned OUTPS3
: 1;
6513 unsigned T6OUTPS0
: 1;
6514 unsigned T6OUTPS1
: 1;
6515 unsigned T6OUTPS2
: 1;
6516 unsigned T6OUTPS3
: 1;
6517 unsigned T6CKPS0
: 1;
6518 unsigned T6CKPS1
: 1;
6519 unsigned T6CKPS2
: 1;
6532 unsigned TMR6ON
: 1;
6543 unsigned T6OUTPS
: 4;
6557 unsigned T6CKPS
: 3;
6562 extern __at(0x041C) volatile __T6CONbits_t T6CONbits
;
6564 #define _T6CON_OUTPS0 0x01
6565 #define _T6CON_T6OUTPS0 0x01
6566 #define _T6CON_OUTPS1 0x02
6567 #define _T6CON_T6OUTPS1 0x02
6568 #define _T6CON_OUTPS2 0x04
6569 #define _T6CON_T6OUTPS2 0x04
6570 #define _T6CON_OUTPS3 0x08
6571 #define _T6CON_T6OUTPS3 0x08
6572 #define _T6CON_CKPS0 0x10
6573 #define _T6CON_T6CKPS0 0x10
6574 #define _T6CON_CKPS1 0x20
6575 #define _T6CON_T6CKPS1 0x20
6576 #define _T6CON_CKPS2 0x40
6577 #define _T6CON_T6CKPS2 0x40
6578 #define _T6CON_ON 0x80
6579 #define _T6CON_T6ON 0x80
6580 #define _T6CON_TMR6ON 0x80
6582 //==============================================================================
6585 //==============================================================================
6588 extern __at(0x041D) __sfr T6HLT
;
6599 unsigned CKSYNC
: 1;
6606 unsigned T6MODE0
: 1;
6607 unsigned T6MODE1
: 1;
6608 unsigned T6MODE2
: 1;
6609 unsigned T6MODE3
: 1;
6610 unsigned T6MODE4
: 1;
6611 unsigned T6CKSYNC
: 1;
6612 unsigned T6CKPOL
: 1;
6613 unsigned T6PSYNC
: 1;
6624 unsigned T6MODE
: 5;
6629 extern __at(0x041D) volatile __T6HLTbits_t T6HLTbits
;
6631 #define _T6HLT_MODE0 0x01
6632 #define _T6HLT_T6MODE0 0x01
6633 #define _T6HLT_MODE1 0x02
6634 #define _T6HLT_T6MODE1 0x02
6635 #define _T6HLT_MODE2 0x04
6636 #define _T6HLT_T6MODE2 0x04
6637 #define _T6HLT_MODE3 0x08
6638 #define _T6HLT_T6MODE3 0x08
6639 #define _T6HLT_MODE4 0x10
6640 #define _T6HLT_T6MODE4 0x10
6641 #define _T6HLT_CKSYNC 0x20
6642 #define _T6HLT_T6CKSYNC 0x20
6643 #define _T6HLT_CKPOL 0x40
6644 #define _T6HLT_T6CKPOL 0x40
6645 #define _T6HLT_PSYNC 0x80
6646 #define _T6HLT_T6PSYNC 0x80
6648 //==============================================================================
6651 //==============================================================================
6654 extern __at(0x041E) __sfr T6CLKCON
;
6695 extern __at(0x041E) volatile __T6CLKCONbits_t T6CLKCONbits
;
6697 #define _T6CLKCON_CS0 0x01
6698 #define _T6CLKCON_T6CS0 0x01
6699 #define _T6CLKCON_CS1 0x02
6700 #define _T6CLKCON_T6CS1 0x02
6701 #define _T6CLKCON_CS2 0x04
6702 #define _T6CLKCON_T6CS2 0x04
6703 #define _T6CLKCON_CS3 0x08
6704 #define _T6CLKCON_T6CS3 0x08
6706 //==============================================================================
6709 //==============================================================================
6712 extern __at(0x041F) __sfr T6RST
;
6730 unsigned T6RSEL0
: 1;
6731 unsigned T6RSEL1
: 1;
6732 unsigned T6RSEL2
: 1;
6733 unsigned T6RSEL3
: 1;
6734 unsigned T6RSEL4
: 1;
6748 unsigned T6RSEL
: 5;
6753 extern __at(0x041F) volatile __T6RSTbits_t T6RSTbits
;
6755 #define _T6RST_RSEL0 0x01
6756 #define _T6RST_T6RSEL0 0x01
6757 #define _T6RST_RSEL1 0x02
6758 #define _T6RST_T6RSEL1 0x02
6759 #define _T6RST_RSEL2 0x04
6760 #define _T6RST_T6RSEL2 0x04
6761 #define _T6RST_RSEL3 0x08
6762 #define _T6RST_T6RSEL3 0x08
6763 #define _T6RST_RSEL4 0x10
6764 #define _T6RST_T6RSEL4 0x10
6766 //==============================================================================
6768 extern __at(0x048E) __sfr ADRESL
;
6769 extern __at(0x048F) __sfr ADRESH
;
6771 //==============================================================================
6774 extern __at(0x0490) __sfr ADCON0
;
6788 extern __at(0x0490) volatile __ADCON0bits_t ADCON0bits
;
6793 //==============================================================================
6796 //==============================================================================
6799 extern __at(0x0491) __sfr ADCON1
;
6805 unsigned ADNREF
: 1;
6813 extern __at(0x0491) volatile __ADCON1bits_t ADCON1bits
;
6815 #define _ADNREF 0x04
6818 //==============================================================================
6820 extern __at(0x0492) __sfr ADCON2
;
6821 extern __at(0x0493) __sfr T2TMR
;
6822 extern __at(0x0493) __sfr TMR2
;
6823 extern __at(0x0494) __sfr PR2
;
6824 extern __at(0x0494) __sfr T2PR
;
6826 //==============================================================================
6829 extern __at(0x0495) __sfr T2CON
;
6835 unsigned OUTPS0
: 1;
6836 unsigned OUTPS1
: 1;
6837 unsigned OUTPS2
: 1;
6838 unsigned OUTPS3
: 1;
6847 unsigned T2OUTPS0
: 1;
6848 unsigned T2OUTPS1
: 1;
6849 unsigned T2OUTPS2
: 1;
6850 unsigned T2OUTPS3
: 1;
6851 unsigned T2CKPS0
: 1;
6852 unsigned T2CKPS1
: 1;
6853 unsigned T2CKPS2
: 1;
6866 unsigned TMR2ON
: 1;
6871 unsigned T2OUTPS
: 4;
6891 unsigned T2CKPS
: 3;
6896 extern __at(0x0495) volatile __T2CONbits_t T2CONbits
;
6898 #define _T2CON_OUTPS0 0x01
6899 #define _T2CON_T2OUTPS0 0x01
6900 #define _T2CON_OUTPS1 0x02
6901 #define _T2CON_T2OUTPS1 0x02
6902 #define _T2CON_OUTPS2 0x04
6903 #define _T2CON_T2OUTPS2 0x04
6904 #define _T2CON_OUTPS3 0x08
6905 #define _T2CON_T2OUTPS3 0x08
6906 #define _T2CON_CKPS0 0x10
6907 #define _T2CON_T2CKPS0 0x10
6908 #define _T2CON_CKPS1 0x20
6909 #define _T2CON_T2CKPS1 0x20
6910 #define _T2CON_CKPS2 0x40
6911 #define _T2CON_T2CKPS2 0x40
6912 #define _T2CON_ON 0x80
6913 #define _T2CON_T2ON 0x80
6914 #define _T2CON_TMR2ON 0x80
6916 //==============================================================================
6919 //==============================================================================
6922 extern __at(0x0496) __sfr T2HLT
;
6933 unsigned CKSYNC
: 1;
6940 unsigned T2MODE0
: 1;
6941 unsigned T2MODE1
: 1;
6942 unsigned T2MODE2
: 1;
6943 unsigned T2MODE3
: 1;
6944 unsigned T2MODE4
: 1;
6945 unsigned T2CKSYNC
: 1;
6946 unsigned T2CKPOL
: 1;
6947 unsigned T2PSYNC
: 1;
6952 unsigned T2MODE
: 5;
6963 extern __at(0x0496) volatile __T2HLTbits_t T2HLTbits
;
6965 #define _T2HLT_MODE0 0x01
6966 #define _T2HLT_T2MODE0 0x01
6967 #define _T2HLT_MODE1 0x02
6968 #define _T2HLT_T2MODE1 0x02
6969 #define _T2HLT_MODE2 0x04
6970 #define _T2HLT_T2MODE2 0x04
6971 #define _T2HLT_MODE3 0x08
6972 #define _T2HLT_T2MODE3 0x08
6973 #define _T2HLT_MODE4 0x10
6974 #define _T2HLT_T2MODE4 0x10
6975 #define _T2HLT_CKSYNC 0x20
6976 #define _T2HLT_T2CKSYNC 0x20
6977 #define _T2HLT_CKPOL 0x40
6978 #define _T2HLT_T2CKPOL 0x40
6979 #define _T2HLT_PSYNC 0x80
6980 #define _T2HLT_T2PSYNC 0x80
6982 //==============================================================================
6985 //==============================================================================
6988 extern __at(0x0497) __sfr T2CLKCON
;
7029 extern __at(0x0497) volatile __T2CLKCONbits_t T2CLKCONbits
;
7031 #define _T2CLKCON_CS0 0x01
7032 #define _T2CLKCON_T2CS0 0x01
7033 #define _T2CLKCON_CS1 0x02
7034 #define _T2CLKCON_T2CS1 0x02
7035 #define _T2CLKCON_CS2 0x04
7036 #define _T2CLKCON_T2CS2 0x04
7037 #define _T2CLKCON_CS3 0x08
7038 #define _T2CLKCON_T2CS3 0x08
7040 //==============================================================================
7043 //==============================================================================
7046 extern __at(0x0498) __sfr T2RST
;
7064 unsigned T2RSEL0
: 1;
7065 unsigned T2RSEL1
: 1;
7066 unsigned T2RSEL2
: 1;
7067 unsigned T2RSEL3
: 1;
7068 unsigned T2RSEL4
: 1;
7082 unsigned T2RSEL
: 5;
7087 extern __at(0x0498) volatile __T2RSTbits_t T2RSTbits
;
7090 #define _T2RSEL0 0x01
7092 #define _T2RSEL1 0x02
7094 #define _T2RSEL2 0x04
7096 #define _T2RSEL3 0x08
7098 #define _T2RSEL4 0x10
7100 //==============================================================================
7102 extern __at(0x049A) __sfr T8TMR
;
7103 extern __at(0x049A) __sfr TMR8
;
7104 extern __at(0x049B) __sfr PR8
;
7105 extern __at(0x049B) __sfr T8PR
;
7107 //==============================================================================
7110 extern __at(0x049C) __sfr T8CON
;
7116 unsigned OUTPS0
: 1;
7117 unsigned OUTPS1
: 1;
7118 unsigned OUTPS2
: 1;
7119 unsigned OUTPS3
: 1;
7128 unsigned T8OUTPS0
: 1;
7129 unsigned T8OUTPS1
: 1;
7130 unsigned T8OUTPS2
: 1;
7131 unsigned T8OUTPS3
: 1;
7132 unsigned T8CKPS0
: 1;
7133 unsigned T8CKPS1
: 1;
7134 unsigned T8CKPS2
: 1;
7147 unsigned TMR8ON
: 1;
7152 unsigned T8OUTPS
: 4;
7165 unsigned T8CKPS
: 3;
7177 extern __at(0x049C) volatile __T8CONbits_t T8CONbits
;
7179 #define _T8CON_OUTPS0 0x01
7180 #define _T8CON_T8OUTPS0 0x01
7181 #define _T8CON_OUTPS1 0x02
7182 #define _T8CON_T8OUTPS1 0x02
7183 #define _T8CON_OUTPS2 0x04
7184 #define _T8CON_T8OUTPS2 0x04
7185 #define _T8CON_OUTPS3 0x08
7186 #define _T8CON_T8OUTPS3 0x08
7187 #define _T8CON_CKPS0 0x10
7188 #define _T8CON_T8CKPS0 0x10
7189 #define _T8CON_CKPS1 0x20
7190 #define _T8CON_T8CKPS1 0x20
7191 #define _T8CON_CKPS2 0x40
7192 #define _T8CON_T8CKPS2 0x40
7193 #define _T8CON_ON 0x80
7194 #define _T8CON_T8ON 0x80
7195 #define _T8CON_TMR8ON 0x80
7197 //==============================================================================
7200 //==============================================================================
7203 extern __at(0x049D) __sfr T8HLT
;
7214 unsigned CKSYNC
: 1;
7221 unsigned T8MODE0
: 1;
7222 unsigned T8MODE1
: 1;
7223 unsigned T8MODE2
: 1;
7224 unsigned T8MODE3
: 1;
7225 unsigned T8MODE4
: 1;
7226 unsigned T8CKSYNC
: 1;
7227 unsigned T8CKPOL
: 1;
7228 unsigned T8PSYNC
: 1;
7239 unsigned T8MODE
: 5;
7244 extern __at(0x049D) volatile __T8HLTbits_t T8HLTbits
;
7246 #define _T8HLT_MODE0 0x01
7247 #define _T8HLT_T8MODE0 0x01
7248 #define _T8HLT_MODE1 0x02
7249 #define _T8HLT_T8MODE1 0x02
7250 #define _T8HLT_MODE2 0x04
7251 #define _T8HLT_T8MODE2 0x04
7252 #define _T8HLT_MODE3 0x08
7253 #define _T8HLT_T8MODE3 0x08
7254 #define _T8HLT_MODE4 0x10
7255 #define _T8HLT_T8MODE4 0x10
7256 #define _T8HLT_CKSYNC 0x20
7257 #define _T8HLT_T8CKSYNC 0x20
7258 #define _T8HLT_CKPOL 0x40
7259 #define _T8HLT_T8CKPOL 0x40
7260 #define _T8HLT_PSYNC 0x80
7261 #define _T8HLT_T8PSYNC 0x80
7263 //==============================================================================
7266 //==============================================================================
7269 extern __at(0x049E) __sfr T8CLKCON
;
7310 extern __at(0x049E) volatile __T8CLKCONbits_t T8CLKCONbits
;
7312 #define _T8CLKCON_CS0 0x01
7313 #define _T8CLKCON_T8CS0 0x01
7314 #define _T8CLKCON_CS1 0x02
7315 #define _T8CLKCON_T8CS1 0x02
7316 #define _T8CLKCON_CS2 0x04
7317 #define _T8CLKCON_T8CS2 0x04
7318 #define _T8CLKCON_CS3 0x08
7319 #define _T8CLKCON_T8CS3 0x08
7321 //==============================================================================
7324 //==============================================================================
7327 extern __at(0x049F) __sfr T8RST
;
7345 unsigned T8RSEL0
: 1;
7346 unsigned T8RSEL1
: 1;
7347 unsigned T8RSEL2
: 1;
7348 unsigned T8RSEL3
: 1;
7349 unsigned T8RSEL4
: 1;
7357 unsigned T8RSEL
: 5;
7368 extern __at(0x049F) volatile __T8RSTbits_t T8RSTbits
;
7370 #define _T8RST_RSEL0 0x01
7371 #define _T8RST_T8RSEL0 0x01
7372 #define _T8RST_RSEL1 0x02
7373 #define _T8RST_T8RSEL1 0x02
7374 #define _T8RST_RSEL2 0x04
7375 #define _T8RST_T8RSEL2 0x04
7376 #define _T8RST_RSEL3 0x08
7377 #define _T8RST_T8RSEL3 0x08
7378 #define _T8RST_RSEL4 0x10
7379 #define _T8RST_T8RSEL4 0x10
7381 //==============================================================================
7383 extern __at(0x050F) __sfr OPA1NCHS
;
7384 extern __at(0x0510) __sfr OPA1PCHS
;
7386 //==============================================================================
7389 extern __at(0x0511) __sfr OPA1CON
;
7407 unsigned OPA1ORM0
: 1;
7408 unsigned OPA1ORM1
: 1;
7409 unsigned OPA1ORPOL
: 1;
7411 unsigned OPA1UG
: 1;
7414 unsigned OPA1EN
: 1;
7419 unsigned OPA1ORM
: 2;
7430 extern __at(0x0511) volatile __OPA1CONbits_t OPA1CONbits
;
7432 #define _OPA1CON_ORM0 0x01
7433 #define _OPA1CON_OPA1ORM0 0x01
7434 #define _OPA1CON_ORM1 0x02
7435 #define _OPA1CON_OPA1ORM1 0x02
7436 #define _OPA1CON_ORPOL 0x04
7437 #define _OPA1CON_OPA1ORPOL 0x04
7438 #define _OPA1CON_UG 0x10
7439 #define _OPA1CON_OPA1UG 0x10
7440 #define _OPA1CON_EN 0x80
7441 #define _OPA1CON_OPA1EN 0x80
7443 //==============================================================================
7445 extern __at(0x0512) __sfr OPA1ORS
;
7446 extern __at(0x0513) __sfr OPA2NCHS
;
7447 extern __at(0x0514) __sfr OPA2PCHS
;
7449 //==============================================================================
7452 extern __at(0x0515) __sfr OPA2CON
;
7470 unsigned OPA2ORM0
: 1;
7471 unsigned OPA2ORM1
: 1;
7472 unsigned OPA2ORPOL
: 1;
7474 unsigned OPA2UG
: 1;
7477 unsigned OPA2EN
: 1;
7482 unsigned OPA2ORM
: 2;
7493 extern __at(0x0515) volatile __OPA2CONbits_t OPA2CONbits
;
7495 #define _OPA2CON_ORM0 0x01
7496 #define _OPA2CON_OPA2ORM0 0x01
7497 #define _OPA2CON_ORM1 0x02
7498 #define _OPA2CON_OPA2ORM1 0x02
7499 #define _OPA2CON_ORPOL 0x04
7500 #define _OPA2CON_OPA2ORPOL 0x04
7501 #define _OPA2CON_UG 0x10
7502 #define _OPA2CON_OPA2UG 0x10
7503 #define _OPA2CON_EN 0x80
7504 #define _OPA2CON_OPA2EN 0x80
7506 //==============================================================================
7508 extern __at(0x0516) __sfr OPA2ORS
;
7509 extern __at(0x0517) __sfr OPA3NCHS
;
7510 extern __at(0x0518) __sfr OPA3PCHS
;
7512 //==============================================================================
7515 extern __at(0x0519) __sfr OPA3CON
;
7533 unsigned OPA3ORM0
: 1;
7534 unsigned OPA3ORM1
: 1;
7535 unsigned OPA3ORPOL
: 1;
7537 unsigned OPA3UG
: 1;
7539 unsigned OPA3SP
: 1;
7540 unsigned OPA3EN
: 1;
7545 unsigned OPA3ORM
: 2;
7556 extern __at(0x0519) volatile __OPA3CONbits_t OPA3CONbits
;
7558 #define _OPA3CON_ORM0 0x01
7559 #define _OPA3CON_OPA3ORM0 0x01
7560 #define _OPA3CON_ORM1 0x02
7561 #define _OPA3CON_OPA3ORM1 0x02
7562 #define _OPA3CON_ORPOL 0x04
7563 #define _OPA3CON_OPA3ORPOL 0x04
7564 #define _OPA3CON_UG 0x10
7565 #define _OPA3CON_OPA3UG 0x10
7566 #define _OPA3CON_SP 0x40
7567 #define _OPA3CON_OPA3SP 0x40
7568 #define _OPA3CON_EN 0x80
7569 #define _OPA3CON_OPA3EN 0x80
7571 //==============================================================================
7573 extern __at(0x051A) __sfr OPA3ORS
;
7575 //==============================================================================
7578 extern __at(0x058D) __sfr DACLD
;
7582 unsigned DAC1LD
: 1;
7583 unsigned DAC2LD
: 1;
7586 unsigned DAC5LD
: 1;
7592 extern __at(0x058D) volatile __DACLDbits_t DACLDbits
;
7594 #define _DAC1LD 0x01
7595 #define _DAC2LD 0x02
7596 #define _DAC5LD 0x10
7598 //==============================================================================
7601 //==============================================================================
7604 extern __at(0x058E) __sfr DAC1CON0
;
7622 unsigned DACNSS0
: 1;
7623 unsigned DACNSS1
: 1;
7624 unsigned DACPSS0
: 1;
7625 unsigned DACPSS1
: 1;
7626 unsigned DACOE2
: 1;
7634 unsigned DAC1NSS0
: 1;
7635 unsigned DAC1NSS1
: 1;
7636 unsigned DAC1PSS0
: 1;
7637 unsigned DAC1PSS1
: 1;
7638 unsigned DAC1OE2
: 1;
7639 unsigned DACOE1
: 1;
7640 unsigned DAC1FM
: 1;
7641 unsigned DAC1EN
: 1;
7663 unsigned DAC1OE1
: 1;
7670 unsigned DAC1NSS
: 2;
7676 unsigned DACNSS
: 2;
7689 unsigned DAC1PSS
: 2;
7696 unsigned DACPSS
: 2;
7708 extern __at(0x058E) volatile __DAC1CON0bits_t DAC1CON0bits
;
7710 #define _DAC1CON0_NSS0 0x01
7711 #define _DAC1CON0_DACNSS0 0x01
7712 #define _DAC1CON0_DAC1NSS0 0x01
7713 #define _DAC1CON0_NSS1 0x02
7714 #define _DAC1CON0_DACNSS1 0x02
7715 #define _DAC1CON0_DAC1NSS1 0x02
7716 #define _DAC1CON0_PSS0 0x04
7717 #define _DAC1CON0_DACPSS0 0x04
7718 #define _DAC1CON0_DAC1PSS0 0x04
7719 #define _DAC1CON0_PSS1 0x08
7720 #define _DAC1CON0_DACPSS1 0x08
7721 #define _DAC1CON0_DAC1PSS1 0x08
7722 #define _DAC1CON0_OE2 0x10
7723 #define _DAC1CON0_DACOE2 0x10
7724 #define _DAC1CON0_DAC1OE2 0x10
7725 #define _DAC1CON0_OE1 0x20
7726 #define _DAC1CON0_OE 0x20
7727 #define _DAC1CON0_DACOE1 0x20
7728 #define _DAC1CON0_DACOE 0x20
7729 #define _DAC1CON0_DAC1OE1 0x20
7730 #define _DAC1CON0_FM 0x40
7731 #define _DAC1CON0_DACFM 0x40
7732 #define _DAC1CON0_DAC1FM 0x40
7733 #define _DAC1CON0_EN 0x80
7734 #define _DAC1CON0_DACEN 0x80
7735 #define _DAC1CON0_DAC1EN 0x80
7737 //==============================================================================
7740 //==============================================================================
7743 extern __at(0x058F) __sfr DAC1CON1
;
7761 unsigned DAC1REF0
: 1;
7762 unsigned DAC1REF1
: 1;
7763 unsigned DAC1REF2
: 1;
7764 unsigned DAC1REF3
: 1;
7765 unsigned DAC1REF4
: 1;
7766 unsigned DAC1REF5
: 1;
7767 unsigned DAC1REF6
: 1;
7768 unsigned DAC1REF7
: 1;
7785 unsigned DAC1R0
: 1;
7786 unsigned DAC1R1
: 1;
7787 unsigned DAC1R2
: 1;
7788 unsigned DAC1R3
: 1;
7789 unsigned DAC1R4
: 1;
7790 unsigned DAC1R5
: 1;
7791 unsigned DAC1R6
: 1;
7792 unsigned DAC1R7
: 1;
7796 extern __at(0x058F) volatile __DAC1CON1bits_t DAC1CON1bits
;
7799 #define _DAC1REF0 0x01
7801 #define _DAC1R0 0x01
7803 #define _DAC1REF1 0x02
7805 #define _DAC1R1 0x02
7807 #define _DAC1REF2 0x04
7809 #define _DAC1R2 0x04
7811 #define _DAC1REF3 0x08
7813 #define _DAC1R3 0x08
7815 #define _DAC1REF4 0x10
7817 #define _DAC1R4 0x10
7819 #define _DAC1REF5 0x20
7821 #define _DAC1R5 0x20
7823 #define _DAC1REF6 0x40
7825 #define _DAC1R6 0x40
7827 #define _DAC1REF7 0x80
7829 #define _DAC1R7 0x80
7831 //==============================================================================
7833 extern __at(0x058F) __sfr DAC1REF
;
7835 //==============================================================================
7838 extern __at(0x058F) __sfr DAC1REFL
;
7856 unsigned DAC1REF0
: 1;
7857 unsigned DAC1REF1
: 1;
7858 unsigned DAC1REF2
: 1;
7859 unsigned DAC1REF3
: 1;
7860 unsigned DAC1REF4
: 1;
7861 unsigned DAC1REF5
: 1;
7862 unsigned DAC1REF6
: 1;
7863 unsigned DAC1REF7
: 1;
7880 unsigned DAC1R0
: 1;
7881 unsigned DAC1R1
: 1;
7882 unsigned DAC1R2
: 1;
7883 unsigned DAC1R3
: 1;
7884 unsigned DAC1R4
: 1;
7885 unsigned DAC1R5
: 1;
7886 unsigned DAC1R6
: 1;
7887 unsigned DAC1R7
: 1;
7891 extern __at(0x058F) volatile __DAC1REFLbits_t DAC1REFLbits
;
7893 #define _DAC1REFL_REF0 0x01
7894 #define _DAC1REFL_DAC1REF0 0x01
7895 #define _DAC1REFL_R0 0x01
7896 #define _DAC1REFL_DAC1R0 0x01
7897 #define _DAC1REFL_REF1 0x02
7898 #define _DAC1REFL_DAC1REF1 0x02
7899 #define _DAC1REFL_R1 0x02
7900 #define _DAC1REFL_DAC1R1 0x02
7901 #define _DAC1REFL_REF2 0x04
7902 #define _DAC1REFL_DAC1REF2 0x04
7903 #define _DAC1REFL_R2 0x04
7904 #define _DAC1REFL_DAC1R2 0x04
7905 #define _DAC1REFL_REF3 0x08
7906 #define _DAC1REFL_DAC1REF3 0x08
7907 #define _DAC1REFL_R3 0x08
7908 #define _DAC1REFL_DAC1R3 0x08
7909 #define _DAC1REFL_REF4 0x10
7910 #define _DAC1REFL_DAC1REF4 0x10
7911 #define _DAC1REFL_R4 0x10
7912 #define _DAC1REFL_DAC1R4 0x10
7913 #define _DAC1REFL_REF5 0x20
7914 #define _DAC1REFL_DAC1REF5 0x20
7915 #define _DAC1REFL_R5 0x20
7916 #define _DAC1REFL_DAC1R5 0x20
7917 #define _DAC1REFL_REF6 0x40
7918 #define _DAC1REFL_DAC1REF6 0x40
7919 #define _DAC1REFL_R6 0x40
7920 #define _DAC1REFL_DAC1R6 0x40
7921 #define _DAC1REFL_REF7 0x80
7922 #define _DAC1REFL_DAC1REF7 0x80
7923 #define _DAC1REFL_R7 0x80
7924 #define _DAC1REFL_DAC1R7 0x80
7926 //==============================================================================
7929 //==============================================================================
7932 extern __at(0x0590) __sfr DAC1CON2
;
7950 unsigned DAC1REF8
: 1;
7951 unsigned DAC1REF9
: 1;
7952 unsigned DAC1REF10
: 1;
7953 unsigned DAC1REF11
: 1;
7954 unsigned DAC1REF12
: 1;
7955 unsigned DAC1REF13
: 1;
7956 unsigned DAC1REF14
: 1;
7957 unsigned DAC1REF15
: 1;
7974 unsigned DAC1R8
: 1;
7975 unsigned DAC1R9
: 1;
7976 unsigned DAC1R10
: 1;
7977 unsigned DAC1R11
: 1;
7978 unsigned DAC1R12
: 1;
7979 unsigned DAC1R13
: 1;
7980 unsigned DAC1R14
: 1;
7981 unsigned DAC1R15
: 1;
7985 extern __at(0x0590) volatile __DAC1CON2bits_t DAC1CON2bits
;
7988 #define _DAC1REF8 0x01
7990 #define _DAC1R8 0x01
7992 #define _DAC1REF9 0x02
7994 #define _DAC1R9 0x02
7996 #define _DAC1REF10 0x04
7998 #define _DAC1R10 0x04
8000 #define _DAC1REF11 0x08
8002 #define _DAC1R11 0x08
8004 #define _DAC1REF12 0x10
8006 #define _DAC1R12 0x10
8008 #define _DAC1REF13 0x20
8010 #define _DAC1R13 0x20
8012 #define _DAC1REF14 0x40
8014 #define _DAC1R14 0x40
8016 #define _DAC1REF15 0x80
8018 #define _DAC1R15 0x80
8020 //==============================================================================
8023 //==============================================================================
8026 extern __at(0x0590) __sfr DAC1REFH
;
8044 unsigned DAC1REF8
: 1;
8045 unsigned DAC1REF9
: 1;
8046 unsigned DAC1REF10
: 1;
8047 unsigned DAC1REF11
: 1;
8048 unsigned DAC1REF12
: 1;
8049 unsigned DAC1REF13
: 1;
8050 unsigned DAC1REF14
: 1;
8051 unsigned DAC1REF15
: 1;
8068 unsigned DAC1R8
: 1;
8069 unsigned DAC1R9
: 1;
8070 unsigned DAC1R10
: 1;
8071 unsigned DAC1R11
: 1;
8072 unsigned DAC1R12
: 1;
8073 unsigned DAC1R13
: 1;
8074 unsigned DAC1R14
: 1;
8075 unsigned DAC1R15
: 1;
8079 extern __at(0x0590) volatile __DAC1REFHbits_t DAC1REFHbits
;
8081 #define _DAC1REFH_REF8 0x01
8082 #define _DAC1REFH_DAC1REF8 0x01
8083 #define _DAC1REFH_R8 0x01
8084 #define _DAC1REFH_DAC1R8 0x01
8085 #define _DAC1REFH_REF9 0x02
8086 #define _DAC1REFH_DAC1REF9 0x02
8087 #define _DAC1REFH_R9 0x02
8088 #define _DAC1REFH_DAC1R9 0x02
8089 #define _DAC1REFH_REF10 0x04
8090 #define _DAC1REFH_DAC1REF10 0x04
8091 #define _DAC1REFH_R10 0x04
8092 #define _DAC1REFH_DAC1R10 0x04
8093 #define _DAC1REFH_REF11 0x08
8094 #define _DAC1REFH_DAC1REF11 0x08
8095 #define _DAC1REFH_R11 0x08
8096 #define _DAC1REFH_DAC1R11 0x08
8097 #define _DAC1REFH_REF12 0x10
8098 #define _DAC1REFH_DAC1REF12 0x10
8099 #define _DAC1REFH_R12 0x10
8100 #define _DAC1REFH_DAC1R12 0x10
8101 #define _DAC1REFH_REF13 0x20
8102 #define _DAC1REFH_DAC1REF13 0x20
8103 #define _DAC1REFH_R13 0x20
8104 #define _DAC1REFH_DAC1R13 0x20
8105 #define _DAC1REFH_REF14 0x40
8106 #define _DAC1REFH_DAC1REF14 0x40
8107 #define _DAC1REFH_R14 0x40
8108 #define _DAC1REFH_DAC1R14 0x40
8109 #define _DAC1REFH_REF15 0x80
8110 #define _DAC1REFH_DAC1REF15 0x80
8111 #define _DAC1REFH_R15 0x80
8112 #define _DAC1REFH_DAC1R15 0x80
8114 //==============================================================================
8117 //==============================================================================
8120 extern __at(0x0591) __sfr DAC2CON0
;
8138 unsigned DACNSS0
: 1;
8139 unsigned DACNSS1
: 1;
8140 unsigned DACPSS0
: 1;
8141 unsigned DACPSS1
: 1;
8142 unsigned DACOE2
: 1;
8150 unsigned DAC2NSS0
: 1;
8151 unsigned DAC2NSS1
: 1;
8152 unsigned DAC2PSS0
: 1;
8153 unsigned DAC2PSS1
: 1;
8154 unsigned DAC2OE2
: 1;
8155 unsigned DACOE1
: 1;
8156 unsigned DAC2FM
: 1;
8157 unsigned DAC2EN
: 1;
8179 unsigned DAC2OE1
: 1;
8186 unsigned DAC2NSS
: 2;
8192 unsigned DACNSS
: 2;
8212 unsigned DACPSS
: 2;
8219 unsigned DAC2PSS
: 2;
8224 extern __at(0x0591) volatile __DAC2CON0bits_t DAC2CON0bits
;
8226 #define _DAC2CON0_NSS0 0x01
8227 #define _DAC2CON0_DACNSS0 0x01
8228 #define _DAC2CON0_DAC2NSS0 0x01
8229 #define _DAC2CON0_NSS1 0x02
8230 #define _DAC2CON0_DACNSS1 0x02
8231 #define _DAC2CON0_DAC2NSS1 0x02
8232 #define _DAC2CON0_PSS0 0x04
8233 #define _DAC2CON0_DACPSS0 0x04
8234 #define _DAC2CON0_DAC2PSS0 0x04
8235 #define _DAC2CON0_PSS1 0x08
8236 #define _DAC2CON0_DACPSS1 0x08
8237 #define _DAC2CON0_DAC2PSS1 0x08
8238 #define _DAC2CON0_OE2 0x10
8239 #define _DAC2CON0_DACOE2 0x10
8240 #define _DAC2CON0_DAC2OE2 0x10
8241 #define _DAC2CON0_OE1 0x20
8242 #define _DAC2CON0_OE 0x20
8243 #define _DAC2CON0_DACOE1 0x20
8244 #define _DAC2CON0_DACOE 0x20
8245 #define _DAC2CON0_DAC2OE1 0x20
8246 #define _DAC2CON0_FM 0x40
8247 #define _DAC2CON0_DACFM 0x40
8248 #define _DAC2CON0_DAC2FM 0x40
8249 #define _DAC2CON0_EN 0x80
8250 #define _DAC2CON0_DACEN 0x80
8251 #define _DAC2CON0_DAC2EN 0x80
8253 //==============================================================================
8256 //==============================================================================
8259 extern __at(0x0592) __sfr DAC2CON1
;
8277 unsigned DAC2REF0
: 1;
8278 unsigned DAC2REF1
: 1;
8279 unsigned DAC2REF2
: 1;
8280 unsigned DAC2REF3
: 1;
8281 unsigned DAC2REF4
: 1;
8282 unsigned DAC2REF5
: 1;
8283 unsigned DAC2REF6
: 1;
8284 unsigned DAC2REF7
: 1;
8301 unsigned DAC2R0
: 1;
8302 unsigned DAC2R1
: 1;
8303 unsigned DAC2R2
: 1;
8304 unsigned DAC2R3
: 1;
8305 unsigned DAC2R4
: 1;
8306 unsigned DAC2R5
: 1;
8307 unsigned DAC2R6
: 1;
8308 unsigned DAC2R7
: 1;
8312 extern __at(0x0592) volatile __DAC2CON1bits_t DAC2CON1bits
;
8314 #define _DAC2CON1_REF0 0x01
8315 #define _DAC2CON1_DAC2REF0 0x01
8316 #define _DAC2CON1_R0 0x01
8317 #define _DAC2CON1_DAC2R0 0x01
8318 #define _DAC2CON1_REF1 0x02
8319 #define _DAC2CON1_DAC2REF1 0x02
8320 #define _DAC2CON1_R1 0x02
8321 #define _DAC2CON1_DAC2R1 0x02
8322 #define _DAC2CON1_REF2 0x04
8323 #define _DAC2CON1_DAC2REF2 0x04
8324 #define _DAC2CON1_R2 0x04
8325 #define _DAC2CON1_DAC2R2 0x04
8326 #define _DAC2CON1_REF3 0x08
8327 #define _DAC2CON1_DAC2REF3 0x08
8328 #define _DAC2CON1_R3 0x08
8329 #define _DAC2CON1_DAC2R3 0x08
8330 #define _DAC2CON1_REF4 0x10
8331 #define _DAC2CON1_DAC2REF4 0x10
8332 #define _DAC2CON1_R4 0x10
8333 #define _DAC2CON1_DAC2R4 0x10
8334 #define _DAC2CON1_REF5 0x20
8335 #define _DAC2CON1_DAC2REF5 0x20
8336 #define _DAC2CON1_R5 0x20
8337 #define _DAC2CON1_DAC2R5 0x20
8338 #define _DAC2CON1_REF6 0x40
8339 #define _DAC2CON1_DAC2REF6 0x40
8340 #define _DAC2CON1_R6 0x40
8341 #define _DAC2CON1_DAC2R6 0x40
8342 #define _DAC2CON1_REF7 0x80
8343 #define _DAC2CON1_DAC2REF7 0x80
8344 #define _DAC2CON1_R7 0x80
8345 #define _DAC2CON1_DAC2R7 0x80
8347 //==============================================================================
8349 extern __at(0x0592) __sfr DAC2REF
;
8351 //==============================================================================
8354 extern __at(0x0592) __sfr DAC2REFL
;
8372 unsigned DAC2REF0
: 1;
8373 unsigned DAC2REF1
: 1;
8374 unsigned DAC2REF2
: 1;
8375 unsigned DAC2REF3
: 1;
8376 unsigned DAC2REF4
: 1;
8377 unsigned DAC2REF5
: 1;
8378 unsigned DAC2REF6
: 1;
8379 unsigned DAC2REF7
: 1;
8396 unsigned DAC2R0
: 1;
8397 unsigned DAC2R1
: 1;
8398 unsigned DAC2R2
: 1;
8399 unsigned DAC2R3
: 1;
8400 unsigned DAC2R4
: 1;
8401 unsigned DAC2R5
: 1;
8402 unsigned DAC2R6
: 1;
8403 unsigned DAC2R7
: 1;
8407 extern __at(0x0592) volatile __DAC2REFLbits_t DAC2REFLbits
;
8409 #define _DAC2REFL_REF0 0x01
8410 #define _DAC2REFL_DAC2REF0 0x01
8411 #define _DAC2REFL_R0 0x01
8412 #define _DAC2REFL_DAC2R0 0x01
8413 #define _DAC2REFL_REF1 0x02
8414 #define _DAC2REFL_DAC2REF1 0x02
8415 #define _DAC2REFL_R1 0x02
8416 #define _DAC2REFL_DAC2R1 0x02
8417 #define _DAC2REFL_REF2 0x04
8418 #define _DAC2REFL_DAC2REF2 0x04
8419 #define _DAC2REFL_R2 0x04
8420 #define _DAC2REFL_DAC2R2 0x04
8421 #define _DAC2REFL_REF3 0x08
8422 #define _DAC2REFL_DAC2REF3 0x08
8423 #define _DAC2REFL_R3 0x08
8424 #define _DAC2REFL_DAC2R3 0x08
8425 #define _DAC2REFL_REF4 0x10
8426 #define _DAC2REFL_DAC2REF4 0x10
8427 #define _DAC2REFL_R4 0x10
8428 #define _DAC2REFL_DAC2R4 0x10
8429 #define _DAC2REFL_REF5 0x20
8430 #define _DAC2REFL_DAC2REF5 0x20
8431 #define _DAC2REFL_R5 0x20
8432 #define _DAC2REFL_DAC2R5 0x20
8433 #define _DAC2REFL_REF6 0x40
8434 #define _DAC2REFL_DAC2REF6 0x40
8435 #define _DAC2REFL_R6 0x40
8436 #define _DAC2REFL_DAC2R6 0x40
8437 #define _DAC2REFL_REF7 0x80
8438 #define _DAC2REFL_DAC2REF7 0x80
8439 #define _DAC2REFL_R7 0x80
8440 #define _DAC2REFL_DAC2R7 0x80
8442 //==============================================================================
8445 //==============================================================================
8448 extern __at(0x0593) __sfr DAC2CON2
;
8466 unsigned DAC2REF8
: 1;
8467 unsigned DAC2REF9
: 1;
8468 unsigned DAC2REF10
: 1;
8469 unsigned DAC2REF11
: 1;
8470 unsigned DAC2REF12
: 1;
8471 unsigned DAC2REF13
: 1;
8472 unsigned DAC2REF14
: 1;
8473 unsigned DAC2REF15
: 1;
8490 unsigned DAC2R8
: 1;
8491 unsigned DAC2R9
: 1;
8492 unsigned DAC2R10
: 1;
8493 unsigned DAC2R11
: 1;
8494 unsigned DAC2R12
: 1;
8495 unsigned DAC2R13
: 1;
8496 unsigned DAC2R14
: 1;
8497 unsigned DAC2R15
: 1;
8501 extern __at(0x0593) volatile __DAC2CON2bits_t DAC2CON2bits
;
8503 #define _DAC2CON2_REF8 0x01
8504 #define _DAC2CON2_DAC2REF8 0x01
8505 #define _DAC2CON2_R8 0x01
8506 #define _DAC2CON2_DAC2R8 0x01
8507 #define _DAC2CON2_REF9 0x02
8508 #define _DAC2CON2_DAC2REF9 0x02
8509 #define _DAC2CON2_R9 0x02
8510 #define _DAC2CON2_DAC2R9 0x02
8511 #define _DAC2CON2_REF10 0x04
8512 #define _DAC2CON2_DAC2REF10 0x04
8513 #define _DAC2CON2_R10 0x04
8514 #define _DAC2CON2_DAC2R10 0x04
8515 #define _DAC2CON2_REF11 0x08
8516 #define _DAC2CON2_DAC2REF11 0x08
8517 #define _DAC2CON2_R11 0x08
8518 #define _DAC2CON2_DAC2R11 0x08
8519 #define _DAC2CON2_REF12 0x10
8520 #define _DAC2CON2_DAC2REF12 0x10
8521 #define _DAC2CON2_R12 0x10
8522 #define _DAC2CON2_DAC2R12 0x10
8523 #define _DAC2CON2_REF13 0x20
8524 #define _DAC2CON2_DAC2REF13 0x20
8525 #define _DAC2CON2_R13 0x20
8526 #define _DAC2CON2_DAC2R13 0x20
8527 #define _DAC2CON2_REF14 0x40
8528 #define _DAC2CON2_DAC2REF14 0x40
8529 #define _DAC2CON2_R14 0x40
8530 #define _DAC2CON2_DAC2R14 0x40
8531 #define _DAC2CON2_REF15 0x80
8532 #define _DAC2CON2_DAC2REF15 0x80
8533 #define _DAC2CON2_R15 0x80
8534 #define _DAC2CON2_DAC2R15 0x80
8536 //==============================================================================
8539 //==============================================================================
8542 extern __at(0x0593) __sfr DAC2REFH
;
8560 unsigned DAC2REF8
: 1;
8561 unsigned DAC2REF9
: 1;
8562 unsigned DAC2REF10
: 1;
8563 unsigned DAC2REF11
: 1;
8564 unsigned DAC2REF12
: 1;
8565 unsigned DAC2REF13
: 1;
8566 unsigned DAC2REF14
: 1;
8567 unsigned DAC2REF15
: 1;
8584 unsigned DAC2R8
: 1;
8585 unsigned DAC2R9
: 1;
8586 unsigned DAC2R10
: 1;
8587 unsigned DAC2R11
: 1;
8588 unsigned DAC2R12
: 1;
8589 unsigned DAC2R13
: 1;
8590 unsigned DAC2R14
: 1;
8591 unsigned DAC2R15
: 1;
8595 extern __at(0x0593) volatile __DAC2REFHbits_t DAC2REFHbits
;
8597 #define _DAC2REFH_REF8 0x01
8598 #define _DAC2REFH_DAC2REF8 0x01
8599 #define _DAC2REFH_R8 0x01
8600 #define _DAC2REFH_DAC2R8 0x01
8601 #define _DAC2REFH_REF9 0x02
8602 #define _DAC2REFH_DAC2REF9 0x02
8603 #define _DAC2REFH_R9 0x02
8604 #define _DAC2REFH_DAC2R9 0x02
8605 #define _DAC2REFH_REF10 0x04
8606 #define _DAC2REFH_DAC2REF10 0x04
8607 #define _DAC2REFH_R10 0x04
8608 #define _DAC2REFH_DAC2R10 0x04
8609 #define _DAC2REFH_REF11 0x08
8610 #define _DAC2REFH_DAC2REF11 0x08
8611 #define _DAC2REFH_R11 0x08
8612 #define _DAC2REFH_DAC2R11 0x08
8613 #define _DAC2REFH_REF12 0x10
8614 #define _DAC2REFH_DAC2REF12 0x10
8615 #define _DAC2REFH_R12 0x10
8616 #define _DAC2REFH_DAC2R12 0x10
8617 #define _DAC2REFH_REF13 0x20
8618 #define _DAC2REFH_DAC2REF13 0x20
8619 #define _DAC2REFH_R13 0x20
8620 #define _DAC2REFH_DAC2R13 0x20
8621 #define _DAC2REFH_REF14 0x40
8622 #define _DAC2REFH_DAC2REF14 0x40
8623 #define _DAC2REFH_R14 0x40
8624 #define _DAC2REFH_DAC2R14 0x40
8625 #define _DAC2REFH_REF15 0x80
8626 #define _DAC2REFH_DAC2REF15 0x80
8627 #define _DAC2REFH_R15 0x80
8628 #define _DAC2REFH_DAC2R15 0x80
8630 //==============================================================================
8633 //==============================================================================
8636 extern __at(0x0594) __sfr DAC3CON0
;
8654 unsigned DACNSS0
: 1;
8655 unsigned DACNSS1
: 1;
8656 unsigned DACPSS0
: 1;
8657 unsigned DACPSS1
: 1;
8658 unsigned DACOE2
: 1;
8659 unsigned DACOE1
: 1;
8666 unsigned DAC3NSS0
: 1;
8667 unsigned DAC3NSS1
: 1;
8668 unsigned DAC3PSS0
: 1;
8669 unsigned DAC3PSS1
: 1;
8670 unsigned DAC3OE2
: 1;
8671 unsigned DAC3OE1
: 1;
8673 unsigned DAC3EN
: 1;
8684 unsigned DACNSS
: 2;
8690 unsigned DAC3NSS
: 2;
8697 unsigned DAC3PSS
: 2;
8704 unsigned DACPSS
: 2;
8716 extern __at(0x0594) volatile __DAC3CON0bits_t DAC3CON0bits
;
8718 #define _DAC3CON0_NSS0 0x01
8719 #define _DAC3CON0_DACNSS0 0x01
8720 #define _DAC3CON0_DAC3NSS0 0x01
8721 #define _DAC3CON0_NSS1 0x02
8722 #define _DAC3CON0_DACNSS1 0x02
8723 #define _DAC3CON0_DAC3NSS1 0x02
8724 #define _DAC3CON0_PSS0 0x04
8725 #define _DAC3CON0_DACPSS0 0x04
8726 #define _DAC3CON0_DAC3PSS0 0x04
8727 #define _DAC3CON0_PSS1 0x08
8728 #define _DAC3CON0_DACPSS1 0x08
8729 #define _DAC3CON0_DAC3PSS1 0x08
8730 #define _DAC3CON0_OE2 0x10
8731 #define _DAC3CON0_DACOE2 0x10
8732 #define _DAC3CON0_DAC3OE2 0x10
8733 #define _DAC3CON0_OE1 0x20
8734 #define _DAC3CON0_DACOE1 0x20
8735 #define _DAC3CON0_DAC3OE1 0x20
8736 #define _DAC3CON0_EN 0x80
8737 #define _DAC3CON0_DACEN 0x80
8738 #define _DAC3CON0_DAC3EN 0x80
8740 //==============================================================================
8743 //==============================================================================
8746 extern __at(0x0595) __sfr DAC3CON1
;
8776 unsigned DAC3R0
: 1;
8777 unsigned DAC3R1
: 1;
8778 unsigned DAC3R2
: 1;
8779 unsigned DAC3R3
: 1;
8780 unsigned DAC3R4
: 1;
8800 unsigned DAC3REF0
: 1;
8801 unsigned DAC3REF1
: 1;
8802 unsigned DAC3REF2
: 1;
8803 unsigned DAC3REF3
: 1;
8804 unsigned DAC3REF4
: 1;
8812 unsigned DAC3REF
: 5;
8841 extern __at(0x0595) volatile __DAC3CON1bits_t DAC3CON1bits
;
8843 #define _DAC3CON1_DACR0 0x01
8844 #define _DAC3CON1_R0 0x01
8845 #define _DAC3CON1_DAC3R0 0x01
8846 #define _DAC3CON1_REF0 0x01
8847 #define _DAC3CON1_DAC3REF0 0x01
8848 #define _DAC3CON1_DACR1 0x02
8849 #define _DAC3CON1_R1 0x02
8850 #define _DAC3CON1_DAC3R1 0x02
8851 #define _DAC3CON1_REF1 0x02
8852 #define _DAC3CON1_DAC3REF1 0x02
8853 #define _DAC3CON1_DACR2 0x04
8854 #define _DAC3CON1_R2 0x04
8855 #define _DAC3CON1_DAC3R2 0x04
8856 #define _DAC3CON1_REF2 0x04
8857 #define _DAC3CON1_DAC3REF2 0x04
8858 #define _DAC3CON1_DACR3 0x08
8859 #define _DAC3CON1_R3 0x08
8860 #define _DAC3CON1_DAC3R3 0x08
8861 #define _DAC3CON1_REF3 0x08
8862 #define _DAC3CON1_DAC3REF3 0x08
8863 #define _DAC3CON1_DACR4 0x10
8864 #define _DAC3CON1_R4 0x10
8865 #define _DAC3CON1_DAC3R4 0x10
8866 #define _DAC3CON1_REF4 0x10
8867 #define _DAC3CON1_DAC3REF4 0x10
8869 //==============================================================================
8872 //==============================================================================
8875 extern __at(0x0595) __sfr DAC3REF
;
8905 unsigned DAC3R0
: 1;
8906 unsigned DAC3R1
: 1;
8907 unsigned DAC3R2
: 1;
8908 unsigned DAC3R3
: 1;
8909 unsigned DAC3R4
: 1;
8929 unsigned DAC3REF0
: 1;
8930 unsigned DAC3REF1
: 1;
8931 unsigned DAC3REF2
: 1;
8932 unsigned DAC3REF3
: 1;
8933 unsigned DAC3REF4
: 1;
8959 unsigned DAC3REF
: 5;
8970 extern __at(0x0595) volatile __DAC3REFbits_t DAC3REFbits
;
8972 #define _DAC3REF_DACR0 0x01
8973 #define _DAC3REF_R0 0x01
8974 #define _DAC3REF_DAC3R0 0x01
8975 #define _DAC3REF_REF0 0x01
8976 #define _DAC3REF_DAC3REF0 0x01
8977 #define _DAC3REF_DACR1 0x02
8978 #define _DAC3REF_R1 0x02
8979 #define _DAC3REF_DAC3R1 0x02
8980 #define _DAC3REF_REF1 0x02
8981 #define _DAC3REF_DAC3REF1 0x02
8982 #define _DAC3REF_DACR2 0x04
8983 #define _DAC3REF_R2 0x04
8984 #define _DAC3REF_DAC3R2 0x04
8985 #define _DAC3REF_REF2 0x04
8986 #define _DAC3REF_DAC3REF2 0x04
8987 #define _DAC3REF_DACR3 0x08
8988 #define _DAC3REF_R3 0x08
8989 #define _DAC3REF_DAC3R3 0x08
8990 #define _DAC3REF_REF3 0x08
8991 #define _DAC3REF_DAC3REF3 0x08
8992 #define _DAC3REF_DACR4 0x10
8993 #define _DAC3REF_R4 0x10
8994 #define _DAC3REF_DAC3R4 0x10
8995 #define _DAC3REF_REF4 0x10
8996 #define _DAC3REF_DAC3REF4 0x10
8998 //==============================================================================
9001 //==============================================================================
9004 extern __at(0x0596) __sfr DAC4CON0
;
9022 unsigned DACNSS0
: 1;
9023 unsigned DACNSS1
: 1;
9024 unsigned DACPSS0
: 1;
9025 unsigned DACPSS1
: 1;
9026 unsigned DACOE2
: 1;
9027 unsigned DACOE1
: 1;
9034 unsigned DAC4NSS0
: 1;
9035 unsigned DAC4NSS1
: 1;
9036 unsigned DAC4PSS0
: 1;
9037 unsigned DAC4PSS1
: 1;
9038 unsigned DAC4OE2
: 1;
9039 unsigned DAC4OE1
: 1;
9041 unsigned DAC4EN
: 1;
9046 unsigned DACNSS
: 2;
9058 unsigned DAC4NSS
: 2;
9072 unsigned DACPSS
: 2;
9079 unsigned DAC4PSS
: 2;
9084 extern __at(0x0596) volatile __DAC4CON0bits_t DAC4CON0bits
;
9086 #define _DAC4CON0_NSS0 0x01
9087 #define _DAC4CON0_DACNSS0 0x01
9088 #define _DAC4CON0_DAC4NSS0 0x01
9089 #define _DAC4CON0_NSS1 0x02
9090 #define _DAC4CON0_DACNSS1 0x02
9091 #define _DAC4CON0_DAC4NSS1 0x02
9092 #define _DAC4CON0_PSS0 0x04
9093 #define _DAC4CON0_DACPSS0 0x04
9094 #define _DAC4CON0_DAC4PSS0 0x04
9095 #define _DAC4CON0_PSS1 0x08
9096 #define _DAC4CON0_DACPSS1 0x08
9097 #define _DAC4CON0_DAC4PSS1 0x08
9098 #define _DAC4CON0_OE2 0x10
9099 #define _DAC4CON0_DACOE2 0x10
9100 #define _DAC4CON0_DAC4OE2 0x10
9101 #define _DAC4CON0_OE1 0x20
9102 #define _DAC4CON0_DACOE1 0x20
9103 #define _DAC4CON0_DAC4OE1 0x20
9104 #define _DAC4CON0_EN 0x80
9105 #define _DAC4CON0_DACEN 0x80
9106 #define _DAC4CON0_DAC4EN 0x80
9108 //==============================================================================
9111 //==============================================================================
9114 extern __at(0x0597) __sfr DAC4CON1
;
9144 unsigned DAC4R0
: 1;
9145 unsigned DAC4R1
: 1;
9146 unsigned DAC4R2
: 1;
9147 unsigned DAC4R3
: 1;
9148 unsigned DAC4R4
: 1;
9168 unsigned DAC4REF0
: 1;
9169 unsigned DAC4REF1
: 1;
9170 unsigned DAC4REF2
: 1;
9171 unsigned DAC4REF3
: 1;
9172 unsigned DAC4REF4
: 1;
9198 unsigned DAC4REF
: 5;
9209 extern __at(0x0597) volatile __DAC4CON1bits_t DAC4CON1bits
;
9211 #define _DAC4CON1_DACR0 0x01
9212 #define _DAC4CON1_R0 0x01
9213 #define _DAC4CON1_DAC4R0 0x01
9214 #define _DAC4CON1_REF0 0x01
9215 #define _DAC4CON1_DAC4REF0 0x01
9216 #define _DAC4CON1_DACR1 0x02
9217 #define _DAC4CON1_R1 0x02
9218 #define _DAC4CON1_DAC4R1 0x02
9219 #define _DAC4CON1_REF1 0x02
9220 #define _DAC4CON1_DAC4REF1 0x02
9221 #define _DAC4CON1_DACR2 0x04
9222 #define _DAC4CON1_R2 0x04
9223 #define _DAC4CON1_DAC4R2 0x04
9224 #define _DAC4CON1_REF2 0x04
9225 #define _DAC4CON1_DAC4REF2 0x04
9226 #define _DAC4CON1_DACR3 0x08
9227 #define _DAC4CON1_R3 0x08
9228 #define _DAC4CON1_DAC4R3 0x08
9229 #define _DAC4CON1_REF3 0x08
9230 #define _DAC4CON1_DAC4REF3 0x08
9231 #define _DAC4CON1_DACR4 0x10
9232 #define _DAC4CON1_R4 0x10
9233 #define _DAC4CON1_DAC4R4 0x10
9234 #define _DAC4CON1_REF4 0x10
9235 #define _DAC4CON1_DAC4REF4 0x10
9237 //==============================================================================
9240 //==============================================================================
9243 extern __at(0x0597) __sfr DAC4REF
;
9273 unsigned DAC4R0
: 1;
9274 unsigned DAC4R1
: 1;
9275 unsigned DAC4R2
: 1;
9276 unsigned DAC4R3
: 1;
9277 unsigned DAC4R4
: 1;
9297 unsigned DAC4REF0
: 1;
9298 unsigned DAC4REF1
: 1;
9299 unsigned DAC4REF2
: 1;
9300 unsigned DAC4REF3
: 1;
9301 unsigned DAC4REF4
: 1;
9315 unsigned DAC4REF
: 5;
9338 extern __at(0x0597) volatile __DAC4REFbits_t DAC4REFbits
;
9340 #define _DAC4REF_DACR0 0x01
9341 #define _DAC4REF_R0 0x01
9342 #define _DAC4REF_DAC4R0 0x01
9343 #define _DAC4REF_REF0 0x01
9344 #define _DAC4REF_DAC4REF0 0x01
9345 #define _DAC4REF_DACR1 0x02
9346 #define _DAC4REF_R1 0x02
9347 #define _DAC4REF_DAC4R1 0x02
9348 #define _DAC4REF_REF1 0x02
9349 #define _DAC4REF_DAC4REF1 0x02
9350 #define _DAC4REF_DACR2 0x04
9351 #define _DAC4REF_R2 0x04
9352 #define _DAC4REF_DAC4R2 0x04
9353 #define _DAC4REF_REF2 0x04
9354 #define _DAC4REF_DAC4REF2 0x04
9355 #define _DAC4REF_DACR3 0x08
9356 #define _DAC4REF_R3 0x08
9357 #define _DAC4REF_DAC4R3 0x08
9358 #define _DAC4REF_REF3 0x08
9359 #define _DAC4REF_DAC4REF3 0x08
9360 #define _DAC4REF_DACR4 0x10
9361 #define _DAC4REF_R4 0x10
9362 #define _DAC4REF_DAC4R4 0x10
9363 #define _DAC4REF_REF4 0x10
9364 #define _DAC4REF_DAC4REF4 0x10
9366 //==============================================================================
9369 //==============================================================================
9372 extern __at(0x0598) __sfr DAC5CON0
;
9390 unsigned DACNSS0
: 1;
9391 unsigned DACNSS1
: 1;
9392 unsigned DACPSS0
: 1;
9393 unsigned DACPSS1
: 1;
9394 unsigned DACOE2
: 1;
9402 unsigned DAC5NSS0
: 1;
9403 unsigned DAC5NSS1
: 1;
9404 unsigned DAC5PSS0
: 1;
9405 unsigned DAC5PSS1
: 1;
9406 unsigned DAC5OE2
: 1;
9407 unsigned DACOE1
: 1;
9408 unsigned DAC5FM
: 1;
9409 unsigned DAC5EN
: 1;
9431 unsigned DAC5OE1
: 1;
9438 unsigned DAC5NSS
: 2;
9450 unsigned DACNSS
: 2;
9464 unsigned DACPSS
: 2;
9471 unsigned DAC5PSS
: 2;
9476 extern __at(0x0598) volatile __DAC5CON0bits_t DAC5CON0bits
;
9478 #define _DAC5CON0_NSS0 0x01
9479 #define _DAC5CON0_DACNSS0 0x01
9480 #define _DAC5CON0_DAC5NSS0 0x01
9481 #define _DAC5CON0_NSS1 0x02
9482 #define _DAC5CON0_DACNSS1 0x02
9483 #define _DAC5CON0_DAC5NSS1 0x02
9484 #define _DAC5CON0_PSS0 0x04
9485 #define _DAC5CON0_DACPSS0 0x04
9486 #define _DAC5CON0_DAC5PSS0 0x04
9487 #define _DAC5CON0_PSS1 0x08
9488 #define _DAC5CON0_DACPSS1 0x08
9489 #define _DAC5CON0_DAC5PSS1 0x08
9490 #define _DAC5CON0_OE2 0x10
9491 #define _DAC5CON0_DACOE2 0x10
9492 #define _DAC5CON0_DAC5OE2 0x10
9493 #define _DAC5CON0_OE1 0x20
9494 #define _DAC5CON0_OE 0x20
9495 #define _DAC5CON0_DACOE1 0x20
9496 #define _DAC5CON0_DACOE 0x20
9497 #define _DAC5CON0_DAC5OE1 0x20
9498 #define _DAC5CON0_FM 0x40
9499 #define _DAC5CON0_DACFM 0x40
9500 #define _DAC5CON0_DAC5FM 0x40
9501 #define _DAC5CON0_EN 0x80
9502 #define _DAC5CON0_DACEN 0x80
9503 #define _DAC5CON0_DAC5EN 0x80
9505 //==============================================================================
9508 //==============================================================================
9511 extern __at(0x0599) __sfr DAC5CON1
;
9529 unsigned DAC5REF0
: 1;
9530 unsigned DAC5REF1
: 1;
9531 unsigned DAC5REF2
: 1;
9532 unsigned DAC5REF3
: 1;
9533 unsigned DAC5REF4
: 1;
9534 unsigned DAC5REF5
: 1;
9535 unsigned DAC5REF6
: 1;
9536 unsigned DAC5REF7
: 1;
9553 unsigned DAC5R0
: 1;
9554 unsigned DAC5R1
: 1;
9555 unsigned DAC5R2
: 1;
9556 unsigned DAC5R3
: 1;
9557 unsigned DAC5R4
: 1;
9558 unsigned DAC5R5
: 1;
9559 unsigned DAC5R6
: 1;
9560 unsigned DAC5R7
: 1;
9564 extern __at(0x0599) volatile __DAC5CON1bits_t DAC5CON1bits
;
9566 #define _DAC5CON1_REF0 0x01
9567 #define _DAC5CON1_DAC5REF0 0x01
9568 #define _DAC5CON1_R0 0x01
9569 #define _DAC5CON1_DAC5R0 0x01
9570 #define _DAC5CON1_REF1 0x02
9571 #define _DAC5CON1_DAC5REF1 0x02
9572 #define _DAC5CON1_R1 0x02
9573 #define _DAC5CON1_DAC5R1 0x02
9574 #define _DAC5CON1_REF2 0x04
9575 #define _DAC5CON1_DAC5REF2 0x04
9576 #define _DAC5CON1_R2 0x04
9577 #define _DAC5CON1_DAC5R2 0x04
9578 #define _DAC5CON1_REF3 0x08
9579 #define _DAC5CON1_DAC5REF3 0x08
9580 #define _DAC5CON1_R3 0x08
9581 #define _DAC5CON1_DAC5R3 0x08
9582 #define _DAC5CON1_REF4 0x10
9583 #define _DAC5CON1_DAC5REF4 0x10
9584 #define _DAC5CON1_R4 0x10
9585 #define _DAC5CON1_DAC5R4 0x10
9586 #define _DAC5CON1_REF5 0x20
9587 #define _DAC5CON1_DAC5REF5 0x20
9588 #define _DAC5CON1_R5 0x20
9589 #define _DAC5CON1_DAC5R5 0x20
9590 #define _DAC5CON1_REF6 0x40
9591 #define _DAC5CON1_DAC5REF6 0x40
9592 #define _DAC5CON1_R6 0x40
9593 #define _DAC5CON1_DAC5R6 0x40
9594 #define _DAC5CON1_REF7 0x80
9595 #define _DAC5CON1_DAC5REF7 0x80
9596 #define _DAC5CON1_R7 0x80
9597 #define _DAC5CON1_DAC5R7 0x80
9599 //==============================================================================
9601 extern __at(0x0599) __sfr DAC5REF
;
9603 //==============================================================================
9606 extern __at(0x0599) __sfr DAC5REFL
;
9624 unsigned DAC5REF0
: 1;
9625 unsigned DAC5REF1
: 1;
9626 unsigned DAC5REF2
: 1;
9627 unsigned DAC5REF3
: 1;
9628 unsigned DAC5REF4
: 1;
9629 unsigned DAC5REF5
: 1;
9630 unsigned DAC5REF6
: 1;
9631 unsigned DAC5REF7
: 1;
9648 unsigned DAC5R0
: 1;
9649 unsigned DAC5R1
: 1;
9650 unsigned DAC5R2
: 1;
9651 unsigned DAC5R3
: 1;
9652 unsigned DAC5R4
: 1;
9653 unsigned DAC5R5
: 1;
9654 unsigned DAC5R6
: 1;
9655 unsigned DAC5R7
: 1;
9659 extern __at(0x0599) volatile __DAC5REFLbits_t DAC5REFLbits
;
9661 #define _DAC5REFL_REF0 0x01
9662 #define _DAC5REFL_DAC5REF0 0x01
9663 #define _DAC5REFL_R0 0x01
9664 #define _DAC5REFL_DAC5R0 0x01
9665 #define _DAC5REFL_REF1 0x02
9666 #define _DAC5REFL_DAC5REF1 0x02
9667 #define _DAC5REFL_R1 0x02
9668 #define _DAC5REFL_DAC5R1 0x02
9669 #define _DAC5REFL_REF2 0x04
9670 #define _DAC5REFL_DAC5REF2 0x04
9671 #define _DAC5REFL_R2 0x04
9672 #define _DAC5REFL_DAC5R2 0x04
9673 #define _DAC5REFL_REF3 0x08
9674 #define _DAC5REFL_DAC5REF3 0x08
9675 #define _DAC5REFL_R3 0x08
9676 #define _DAC5REFL_DAC5R3 0x08
9677 #define _DAC5REFL_REF4 0x10
9678 #define _DAC5REFL_DAC5REF4 0x10
9679 #define _DAC5REFL_R4 0x10
9680 #define _DAC5REFL_DAC5R4 0x10
9681 #define _DAC5REFL_REF5 0x20
9682 #define _DAC5REFL_DAC5REF5 0x20
9683 #define _DAC5REFL_R5 0x20
9684 #define _DAC5REFL_DAC5R5 0x20
9685 #define _DAC5REFL_REF6 0x40
9686 #define _DAC5REFL_DAC5REF6 0x40
9687 #define _DAC5REFL_R6 0x40
9688 #define _DAC5REFL_DAC5R6 0x40
9689 #define _DAC5REFL_REF7 0x80
9690 #define _DAC5REFL_DAC5REF7 0x80
9691 #define _DAC5REFL_R7 0x80
9692 #define _DAC5REFL_DAC5R7 0x80
9694 //==============================================================================
9697 //==============================================================================
9700 extern __at(0x059A) __sfr DAC5CON2
;
9718 unsigned DAC5REF8
: 1;
9719 unsigned DAC5REF9
: 1;
9720 unsigned DAC5REF10
: 1;
9721 unsigned DAC5REF11
: 1;
9722 unsigned DAC5REF12
: 1;
9723 unsigned DAC5REF13
: 1;
9724 unsigned DAC5REF14
: 1;
9725 unsigned DAC5REF15
: 1;
9742 unsigned DAC5R8
: 1;
9743 unsigned DAC5R9
: 1;
9744 unsigned DAC5R10
: 1;
9745 unsigned DAC5R11
: 1;
9746 unsigned DAC5R12
: 1;
9747 unsigned DAC5R13
: 1;
9748 unsigned DAC5R14
: 1;
9749 unsigned DAC5R15
: 1;
9753 extern __at(0x059A) volatile __DAC5CON2bits_t DAC5CON2bits
;
9755 #define _DAC5CON2_REF8 0x01
9756 #define _DAC5CON2_DAC5REF8 0x01
9757 #define _DAC5CON2_R8 0x01
9758 #define _DAC5CON2_DAC5R8 0x01
9759 #define _DAC5CON2_REF9 0x02
9760 #define _DAC5CON2_DAC5REF9 0x02
9761 #define _DAC5CON2_R9 0x02
9762 #define _DAC5CON2_DAC5R9 0x02
9763 #define _DAC5CON2_REF10 0x04
9764 #define _DAC5CON2_DAC5REF10 0x04
9765 #define _DAC5CON2_R10 0x04
9766 #define _DAC5CON2_DAC5R10 0x04
9767 #define _DAC5CON2_REF11 0x08
9768 #define _DAC5CON2_DAC5REF11 0x08
9769 #define _DAC5CON2_R11 0x08
9770 #define _DAC5CON2_DAC5R11 0x08
9771 #define _DAC5CON2_REF12 0x10
9772 #define _DAC5CON2_DAC5REF12 0x10
9773 #define _DAC5CON2_R12 0x10
9774 #define _DAC5CON2_DAC5R12 0x10
9775 #define _DAC5CON2_REF13 0x20
9776 #define _DAC5CON2_DAC5REF13 0x20
9777 #define _DAC5CON2_R13 0x20
9778 #define _DAC5CON2_DAC5R13 0x20
9779 #define _DAC5CON2_REF14 0x40
9780 #define _DAC5CON2_DAC5REF14 0x40
9781 #define _DAC5CON2_R14 0x40
9782 #define _DAC5CON2_DAC5R14 0x40
9783 #define _DAC5CON2_REF15 0x80
9784 #define _DAC5CON2_DAC5REF15 0x80
9785 #define _DAC5CON2_R15 0x80
9786 #define _DAC5CON2_DAC5R15 0x80
9788 //==============================================================================
9791 //==============================================================================
9794 extern __at(0x059A) __sfr DAC5REFH
;
9812 unsigned DAC5REF8
: 1;
9813 unsigned DAC5REF9
: 1;
9814 unsigned DAC5REF10
: 1;
9815 unsigned DAC5REF11
: 1;
9816 unsigned DAC5REF12
: 1;
9817 unsigned DAC5REF13
: 1;
9818 unsigned DAC5REF14
: 1;
9819 unsigned DAC5REF15
: 1;
9836 unsigned DAC5R8
: 1;
9837 unsigned DAC5R9
: 1;
9838 unsigned DAC5R10
: 1;
9839 unsigned DAC5R11
: 1;
9840 unsigned DAC5R12
: 1;
9841 unsigned DAC5R13
: 1;
9842 unsigned DAC5R14
: 1;
9843 unsigned DAC5R15
: 1;
9847 extern __at(0x059A) volatile __DAC5REFHbits_t DAC5REFHbits
;
9849 #define _DAC5REFH_REF8 0x01
9850 #define _DAC5REFH_DAC5REF8 0x01
9851 #define _DAC5REFH_R8 0x01
9852 #define _DAC5REFH_DAC5R8 0x01
9853 #define _DAC5REFH_REF9 0x02
9854 #define _DAC5REFH_DAC5REF9 0x02
9855 #define _DAC5REFH_R9 0x02
9856 #define _DAC5REFH_DAC5R9 0x02
9857 #define _DAC5REFH_REF10 0x04
9858 #define _DAC5REFH_DAC5REF10 0x04
9859 #define _DAC5REFH_R10 0x04
9860 #define _DAC5REFH_DAC5R10 0x04
9861 #define _DAC5REFH_REF11 0x08
9862 #define _DAC5REFH_DAC5REF11 0x08
9863 #define _DAC5REFH_R11 0x08
9864 #define _DAC5REFH_DAC5R11 0x08
9865 #define _DAC5REFH_REF12 0x10
9866 #define _DAC5REFH_DAC5REF12 0x10
9867 #define _DAC5REFH_R12 0x10
9868 #define _DAC5REFH_DAC5R12 0x10
9869 #define _DAC5REFH_REF13 0x20
9870 #define _DAC5REFH_DAC5REF13 0x20
9871 #define _DAC5REFH_R13 0x20
9872 #define _DAC5REFH_DAC5R13 0x20
9873 #define _DAC5REFH_REF14 0x40
9874 #define _DAC5REFH_DAC5REF14 0x40
9875 #define _DAC5REFH_R14 0x40
9876 #define _DAC5REFH_DAC5R14 0x40
9877 #define _DAC5REFH_REF15 0x80
9878 #define _DAC5REFH_DAC5REF15 0x80
9879 #define _DAC5REFH_R15 0x80
9880 #define _DAC5REFH_DAC5R15 0x80
9882 //==============================================================================
9885 //==============================================================================
9888 extern __at(0x059E) __sfr DAC7CON0
;
9906 unsigned DACNSS0
: 1;
9907 unsigned DACNSS1
: 1;
9908 unsigned DACPSS0
: 1;
9909 unsigned DACPSS1
: 1;
9910 unsigned DACOE2
: 1;
9911 unsigned DACOE1
: 1;
9918 unsigned DAC7NSS0
: 1;
9919 unsigned DAC7NSS1
: 1;
9920 unsigned DAC7PSS0
: 1;
9921 unsigned DAC7PSS1
: 1;
9922 unsigned DAC7OE2
: 1;
9923 unsigned DAC7OE1
: 1;
9925 unsigned DAC7EN
: 1;
9930 unsigned DACNSS
: 2;
9942 unsigned DAC7NSS
: 2;
9949 unsigned DAC7PSS
: 2;
9956 unsigned DACPSS
: 2;
9968 extern __at(0x059E) volatile __DAC7CON0bits_t DAC7CON0bits
;
9970 #define _DAC7CON0_NSS0 0x01
9971 #define _DAC7CON0_DACNSS0 0x01
9972 #define _DAC7CON0_DAC7NSS0 0x01
9973 #define _DAC7CON0_NSS1 0x02
9974 #define _DAC7CON0_DACNSS1 0x02
9975 #define _DAC7CON0_DAC7NSS1 0x02
9976 #define _DAC7CON0_PSS0 0x04
9977 #define _DAC7CON0_DACPSS0 0x04
9978 #define _DAC7CON0_DAC7PSS0 0x04
9979 #define _DAC7CON0_PSS1 0x08
9980 #define _DAC7CON0_DACPSS1 0x08
9981 #define _DAC7CON0_DAC7PSS1 0x08
9982 #define _DAC7CON0_OE2 0x10
9983 #define _DAC7CON0_DACOE2 0x10
9984 #define _DAC7CON0_DAC7OE2 0x10
9985 #define _DAC7CON0_OE1 0x20
9986 #define _DAC7CON0_DACOE1 0x20
9987 #define _DAC7CON0_DAC7OE1 0x20
9988 #define _DAC7CON0_EN 0x80
9989 #define _DAC7CON0_DACEN 0x80
9990 #define _DAC7CON0_DAC7EN 0x80
9992 //==============================================================================
9995 //==============================================================================
9998 extern __at(0x059F) __sfr DAC7CON1
;
10004 unsigned DACR0
: 1;
10005 unsigned DACR1
: 1;
10006 unsigned DACR2
: 1;
10007 unsigned DACR3
: 1;
10008 unsigned DACR4
: 1;
10028 unsigned DAC7R0
: 1;
10029 unsigned DAC7R1
: 1;
10030 unsigned DAC7R2
: 1;
10031 unsigned DAC7R3
: 1;
10032 unsigned DAC7R4
: 1;
10052 unsigned DAC7REF0
: 1;
10053 unsigned DAC7REF1
: 1;
10054 unsigned DAC7REF2
: 1;
10055 unsigned DAC7REF3
: 1;
10056 unsigned DAC7REF4
: 1;
10070 unsigned DAC7REF
: 5;
10076 unsigned DAC7R
: 5;
10091 } __DAC7CON1bits_t
;
10093 extern __at(0x059F) volatile __DAC7CON1bits_t DAC7CON1bits
;
10095 #define _DAC7CON1_DACR0 0x01
10096 #define _DAC7CON1_R0 0x01
10097 #define _DAC7CON1_DAC7R0 0x01
10098 #define _DAC7CON1_REF0 0x01
10099 #define _DAC7CON1_DAC7REF0 0x01
10100 #define _DAC7CON1_DACR1 0x02
10101 #define _DAC7CON1_R1 0x02
10102 #define _DAC7CON1_DAC7R1 0x02
10103 #define _DAC7CON1_REF1 0x02
10104 #define _DAC7CON1_DAC7REF1 0x02
10105 #define _DAC7CON1_DACR2 0x04
10106 #define _DAC7CON1_R2 0x04
10107 #define _DAC7CON1_DAC7R2 0x04
10108 #define _DAC7CON1_REF2 0x04
10109 #define _DAC7CON1_DAC7REF2 0x04
10110 #define _DAC7CON1_DACR3 0x08
10111 #define _DAC7CON1_R3 0x08
10112 #define _DAC7CON1_DAC7R3 0x08
10113 #define _DAC7CON1_REF3 0x08
10114 #define _DAC7CON1_DAC7REF3 0x08
10115 #define _DAC7CON1_DACR4 0x10
10116 #define _DAC7CON1_R4 0x10
10117 #define _DAC7CON1_DAC7R4 0x10
10118 #define _DAC7CON1_REF4 0x10
10119 #define _DAC7CON1_DAC7REF4 0x10
10121 //==============================================================================
10124 //==============================================================================
10127 extern __at(0x059F) __sfr DAC7REF
;
10133 unsigned DACR0
: 1;
10134 unsigned DACR1
: 1;
10135 unsigned DACR2
: 1;
10136 unsigned DACR3
: 1;
10137 unsigned DACR4
: 1;
10157 unsigned DAC7R0
: 1;
10158 unsigned DAC7R1
: 1;
10159 unsigned DAC7R2
: 1;
10160 unsigned DAC7R3
: 1;
10161 unsigned DAC7R4
: 1;
10181 unsigned DAC7REF0
: 1;
10182 unsigned DAC7REF1
: 1;
10183 unsigned DAC7REF2
: 1;
10184 unsigned DAC7REF3
: 1;
10185 unsigned DAC7REF4
: 1;
10199 unsigned DAC7REF
: 5;
10205 unsigned DAC7R
: 5;
10222 extern __at(0x059F) volatile __DAC7REFbits_t DAC7REFbits
;
10224 #define _DAC7REF_DACR0 0x01
10225 #define _DAC7REF_R0 0x01
10226 #define _DAC7REF_DAC7R0 0x01
10227 #define _DAC7REF_REF0 0x01
10228 #define _DAC7REF_DAC7REF0 0x01
10229 #define _DAC7REF_DACR1 0x02
10230 #define _DAC7REF_R1 0x02
10231 #define _DAC7REF_DAC7R1 0x02
10232 #define _DAC7REF_REF1 0x02
10233 #define _DAC7REF_DAC7REF1 0x02
10234 #define _DAC7REF_DACR2 0x04
10235 #define _DAC7REF_R2 0x04
10236 #define _DAC7REF_DAC7R2 0x04
10237 #define _DAC7REF_REF2 0x04
10238 #define _DAC7REF_DAC7REF2 0x04
10239 #define _DAC7REF_DACR3 0x08
10240 #define _DAC7REF_R3 0x08
10241 #define _DAC7REF_DAC7R3 0x08
10242 #define _DAC7REF_REF3 0x08
10243 #define _DAC7REF_DAC7REF3 0x08
10244 #define _DAC7REF_DACR4 0x10
10245 #define _DAC7REF_R4 0x10
10246 #define _DAC7REF_DAC7R4 0x10
10247 #define _DAC7REF_REF4 0x10
10248 #define _DAC7REF_DAC7REF4 0x10
10250 //==============================================================================
10253 //==============================================================================
10256 extern __at(0x0614) __sfr PWM3DCL
;
10280 unsigned PWM3DC0
: 1;
10281 unsigned PWM3DC1
: 1;
10292 unsigned PWMPW0
: 1;
10293 unsigned PWMPW1
: 1;
10299 unsigned PWM3DC
: 2;
10305 unsigned PWMPW
: 2;
10315 extern __at(0x0614) volatile __PWM3DCLbits_t PWM3DCLbits
;
10318 #define _PWM3DC0 0x40
10319 #define _PWMPW0 0x40
10321 #define _PWM3DC1 0x80
10322 #define _PWMPW1 0x80
10324 //==============================================================================
10327 //==============================================================================
10330 extern __at(0x0615) __sfr PWM3DCH
;
10348 unsigned PWM3DC2
: 1;
10349 unsigned PWM3DC3
: 1;
10350 unsigned PWM3DC4
: 1;
10351 unsigned PWM3DC5
: 1;
10352 unsigned PWM3DC6
: 1;
10353 unsigned PWM3DC7
: 1;
10354 unsigned PWM3DC8
: 1;
10355 unsigned PWM3DC9
: 1;
10360 unsigned PWMPW2
: 1;
10361 unsigned PWMPW3
: 1;
10362 unsigned PWMPW4
: 1;
10363 unsigned PWMPW5
: 1;
10364 unsigned PWMPW6
: 1;
10365 unsigned PWMPW7
: 1;
10366 unsigned PWMPW8
: 1;
10367 unsigned PWMPW9
: 1;
10371 extern __at(0x0615) volatile __PWM3DCHbits_t PWM3DCHbits
;
10374 #define _PWM3DC2 0x01
10375 #define _PWMPW2 0x01
10377 #define _PWM3DC3 0x02
10378 #define _PWMPW3 0x02
10380 #define _PWM3DC4 0x04
10381 #define _PWMPW4 0x04
10383 #define _PWM3DC5 0x08
10384 #define _PWMPW5 0x08
10386 #define _PWM3DC6 0x10
10387 #define _PWMPW6 0x10
10389 #define _PWM3DC7 0x20
10390 #define _PWMPW7 0x20
10392 #define _PWM3DC8 0x40
10393 #define _PWMPW8 0x40
10395 #define _PWM3DC9 0x80
10396 #define _PWMPW9 0x80
10398 //==============================================================================
10401 //==============================================================================
10404 extern __at(0x0616) __sfr PWM3CON
;
10426 unsigned PWM3POL
: 1;
10427 unsigned PWM3OUT
: 1;
10429 unsigned PWM3EN
: 1;
10433 extern __at(0x0616) volatile __PWM3CONbits_t PWM3CONbits
;
10435 #define _PWM3CON_POL 0x10
10436 #define _PWM3CON_PWM3POL 0x10
10437 #define _PWM3CON_OUT 0x20
10438 #define _PWM3CON_PWM3OUT 0x20
10439 #define _PWM3CON_EN 0x80
10440 #define _PWM3CON_PWM3EN 0x80
10442 //==============================================================================
10445 //==============================================================================
10448 extern __at(0x0617) __sfr PWM4DCL
;
10472 unsigned PWM4DC0
: 1;
10473 unsigned PWM4DC1
: 1;
10484 unsigned PWMPW0
: 1;
10485 unsigned PWMPW1
: 1;
10491 unsigned PWMPW
: 2;
10503 unsigned PWM4DC
: 2;
10507 extern __at(0x0617) volatile __PWM4DCLbits_t PWM4DCLbits
;
10509 #define _PWM4DCL_DC0 0x40
10510 #define _PWM4DCL_PWM4DC0 0x40
10511 #define _PWM4DCL_PWMPW0 0x40
10512 #define _PWM4DCL_DC1 0x80
10513 #define _PWM4DCL_PWM4DC1 0x80
10514 #define _PWM4DCL_PWMPW1 0x80
10516 //==============================================================================
10519 //==============================================================================
10522 extern __at(0x0618) __sfr PWM4DCH
;
10540 unsigned PWM4DC2
: 1;
10541 unsigned PWM4DC3
: 1;
10542 unsigned PWM4DC4
: 1;
10543 unsigned PWM4DC5
: 1;
10544 unsigned PWM4DC6
: 1;
10545 unsigned PWM4DC7
: 1;
10546 unsigned PWM4DC8
: 1;
10547 unsigned PWM4DC9
: 1;
10552 unsigned PWMPW2
: 1;
10553 unsigned PWMPW3
: 1;
10554 unsigned PWMPW4
: 1;
10555 unsigned PWMPW5
: 1;
10556 unsigned PWMPW6
: 1;
10557 unsigned PWMPW7
: 1;
10558 unsigned PWMPW8
: 1;
10559 unsigned PWMPW9
: 1;
10563 extern __at(0x0618) volatile __PWM4DCHbits_t PWM4DCHbits
;
10565 #define _PWM4DCH_DC2 0x01
10566 #define _PWM4DCH_PWM4DC2 0x01
10567 #define _PWM4DCH_PWMPW2 0x01
10568 #define _PWM4DCH_DC3 0x02
10569 #define _PWM4DCH_PWM4DC3 0x02
10570 #define _PWM4DCH_PWMPW3 0x02
10571 #define _PWM4DCH_DC4 0x04
10572 #define _PWM4DCH_PWM4DC4 0x04
10573 #define _PWM4DCH_PWMPW4 0x04
10574 #define _PWM4DCH_DC5 0x08
10575 #define _PWM4DCH_PWM4DC5 0x08
10576 #define _PWM4DCH_PWMPW5 0x08
10577 #define _PWM4DCH_DC6 0x10
10578 #define _PWM4DCH_PWM4DC6 0x10
10579 #define _PWM4DCH_PWMPW6 0x10
10580 #define _PWM4DCH_DC7 0x20
10581 #define _PWM4DCH_PWM4DC7 0x20
10582 #define _PWM4DCH_PWMPW7 0x20
10583 #define _PWM4DCH_DC8 0x40
10584 #define _PWM4DCH_PWM4DC8 0x40
10585 #define _PWM4DCH_PWMPW8 0x40
10586 #define _PWM4DCH_DC9 0x80
10587 #define _PWM4DCH_PWM4DC9 0x80
10588 #define _PWM4DCH_PWMPW9 0x80
10590 //==============================================================================
10593 //==============================================================================
10596 extern __at(0x0619) __sfr PWM4CON
;
10618 unsigned PWM4POL
: 1;
10619 unsigned PWM4OUT
: 1;
10621 unsigned PWM4EN
: 1;
10625 extern __at(0x0619) volatile __PWM4CONbits_t PWM4CONbits
;
10627 #define _PWM4CON_POL 0x10
10628 #define _PWM4CON_PWM4POL 0x10
10629 #define _PWM4CON_OUT 0x20
10630 #define _PWM4CON_PWM4OUT 0x20
10631 #define _PWM4CON_EN 0x80
10632 #define _PWM4CON_PWM4EN 0x80
10634 //==============================================================================
10637 //==============================================================================
10640 extern __at(0x061A) __sfr PWM9DCL
;
10664 unsigned PWM9DC0
: 1;
10665 unsigned PWM9DC1
: 1;
10676 unsigned PWMPW0
: 1;
10677 unsigned PWMPW1
: 1;
10689 unsigned PWMPW
: 2;
10695 unsigned PWM9DC
: 2;
10699 extern __at(0x061A) volatile __PWM9DCLbits_t PWM9DCLbits
;
10701 #define _PWM9DCL_DC0 0x40
10702 #define _PWM9DCL_PWM9DC0 0x40
10703 #define _PWM9DCL_PWMPW0 0x40
10704 #define _PWM9DCL_DC1 0x80
10705 #define _PWM9DCL_PWM9DC1 0x80
10706 #define _PWM9DCL_PWMPW1 0x80
10708 //==============================================================================
10711 //==============================================================================
10714 extern __at(0x061B) __sfr PWM9DCH
;
10732 unsigned PWM9DC2
: 1;
10733 unsigned PWM9DC3
: 1;
10734 unsigned PWM9DC4
: 1;
10735 unsigned PWM9DC5
: 1;
10736 unsigned PWM9DC6
: 1;
10737 unsigned PWM9DC7
: 1;
10738 unsigned PWM9DC8
: 1;
10739 unsigned PWM9DC9
: 1;
10744 unsigned PWMPW2
: 1;
10745 unsigned PWMPW3
: 1;
10746 unsigned PWMPW4
: 1;
10747 unsigned PWMPW5
: 1;
10748 unsigned PWMPW6
: 1;
10749 unsigned PWMPW7
: 1;
10750 unsigned PWMPW8
: 1;
10751 unsigned PWMPW9
: 1;
10755 extern __at(0x061B) volatile __PWM9DCHbits_t PWM9DCHbits
;
10757 #define _PWM9DCH_DC2 0x01
10758 #define _PWM9DCH_PWM9DC2 0x01
10759 #define _PWM9DCH_PWMPW2 0x01
10760 #define _PWM9DCH_DC3 0x02
10761 #define _PWM9DCH_PWM9DC3 0x02
10762 #define _PWM9DCH_PWMPW3 0x02
10763 #define _PWM9DCH_DC4 0x04
10764 #define _PWM9DCH_PWM9DC4 0x04
10765 #define _PWM9DCH_PWMPW4 0x04
10766 #define _PWM9DCH_DC5 0x08
10767 #define _PWM9DCH_PWM9DC5 0x08
10768 #define _PWM9DCH_PWMPW5 0x08
10769 #define _PWM9DCH_DC6 0x10
10770 #define _PWM9DCH_PWM9DC6 0x10
10771 #define _PWM9DCH_PWMPW6 0x10
10772 #define _PWM9DCH_DC7 0x20
10773 #define _PWM9DCH_PWM9DC7 0x20
10774 #define _PWM9DCH_PWMPW7 0x20
10775 #define _PWM9DCH_DC8 0x40
10776 #define _PWM9DCH_PWM9DC8 0x40
10777 #define _PWM9DCH_PWMPW8 0x40
10778 #define _PWM9DCH_DC9 0x80
10779 #define _PWM9DCH_PWM9DC9 0x80
10780 #define _PWM9DCH_PWMPW9 0x80
10782 //==============================================================================
10785 //==============================================================================
10788 extern __at(0x061C) __sfr PWM9CON
;
10810 unsigned PWM9POL
: 1;
10811 unsigned PWM9OUT
: 1;
10812 unsigned PWM9OE
: 1;
10813 unsigned PWM9EN
: 1;
10817 extern __at(0x061C) volatile __PWM9CONbits_t PWM9CONbits
;
10819 #define _PWM9CON_POL 0x10
10820 #define _PWM9CON_PWM9POL 0x10
10821 #define _PWM9CON_OUT 0x20
10822 #define _PWM9CON_PWM9OUT 0x20
10823 #define _PWM9CON_OE 0x40
10824 #define _PWM9CON_PWM9OE 0x40
10825 #define _PWM9CON_EN 0x80
10826 #define _PWM9CON_PWM9EN 0x80
10828 //==============================================================================
10831 //==============================================================================
10834 extern __at(0x068D) __sfr COG1PHR
;
10852 unsigned G1PHR0
: 1;
10853 unsigned G1PHR1
: 1;
10854 unsigned G1PHR2
: 1;
10855 unsigned G1PHR3
: 1;
10856 unsigned G1PHR4
: 1;
10857 unsigned G1PHR5
: 1;
10864 unsigned G1PHR
: 6;
10875 extern __at(0x068D) volatile __COG1PHRbits_t COG1PHRbits
;
10878 #define _G1PHR0 0x01
10880 #define _G1PHR1 0x02
10882 #define _G1PHR2 0x04
10884 #define _G1PHR3 0x08
10886 #define _G1PHR4 0x10
10888 #define _G1PHR5 0x20
10890 //==============================================================================
10893 //==============================================================================
10896 extern __at(0x068E) __sfr COG1PHF
;
10914 unsigned G1PHF0
: 1;
10915 unsigned G1PHF1
: 1;
10916 unsigned G1PHF2
: 1;
10917 unsigned G1PHF3
: 1;
10918 unsigned G1PHF4
: 1;
10919 unsigned G1PHF5
: 1;
10926 unsigned G1PHF
: 6;
10937 extern __at(0x068E) volatile __COG1PHFbits_t COG1PHFbits
;
10940 #define _G1PHF0 0x01
10942 #define _G1PHF1 0x02
10944 #define _G1PHF2 0x04
10946 #define _G1PHF3 0x08
10948 #define _G1PHF4 0x10
10950 #define _G1PHF5 0x20
10952 //==============================================================================
10955 //==============================================================================
10958 extern __at(0x068F) __sfr COG1BLKR
;
10964 unsigned BLKR0
: 1;
10965 unsigned BLKR1
: 1;
10966 unsigned BLKR2
: 1;
10967 unsigned BLKR3
: 1;
10968 unsigned BLKR4
: 1;
10969 unsigned BLKR5
: 1;
10976 unsigned G1BLKR0
: 1;
10977 unsigned G1BLKR1
: 1;
10978 unsigned G1BLKR2
: 1;
10979 unsigned G1BLKR3
: 1;
10980 unsigned G1BLKR4
: 1;
10981 unsigned G1BLKR5
: 1;
10988 unsigned G1BLKR
: 6;
10997 } __COG1BLKRbits_t
;
10999 extern __at(0x068F) volatile __COG1BLKRbits_t COG1BLKRbits
;
11001 #define _BLKR0 0x01
11002 #define _G1BLKR0 0x01
11003 #define _BLKR1 0x02
11004 #define _G1BLKR1 0x02
11005 #define _BLKR2 0x04
11006 #define _G1BLKR2 0x04
11007 #define _BLKR3 0x08
11008 #define _G1BLKR3 0x08
11009 #define _BLKR4 0x10
11010 #define _G1BLKR4 0x10
11011 #define _BLKR5 0x20
11012 #define _G1BLKR5 0x20
11014 //==============================================================================
11017 //==============================================================================
11020 extern __at(0x0690) __sfr COG1BLKF
;
11026 unsigned BLKF0
: 1;
11027 unsigned BLKF1
: 1;
11028 unsigned BLKF2
: 1;
11029 unsigned BLKF3
: 1;
11030 unsigned BLKF4
: 1;
11031 unsigned BLKF5
: 1;
11038 unsigned G1BLKF0
: 1;
11039 unsigned G1BLKF1
: 1;
11040 unsigned G1BLKF2
: 1;
11041 unsigned G1BLKF3
: 1;
11042 unsigned G1BLKF4
: 1;
11043 unsigned G1BLKF5
: 1;
11056 unsigned G1BLKF
: 6;
11059 } __COG1BLKFbits_t
;
11061 extern __at(0x0690) volatile __COG1BLKFbits_t COG1BLKFbits
;
11063 #define _BLKF0 0x01
11064 #define _G1BLKF0 0x01
11065 #define _BLKF1 0x02
11066 #define _G1BLKF1 0x02
11067 #define _BLKF2 0x04
11068 #define _G1BLKF2 0x04
11069 #define _BLKF3 0x08
11070 #define _G1BLKF3 0x08
11071 #define _BLKF4 0x10
11072 #define _G1BLKF4 0x10
11073 #define _BLKF5 0x20
11074 #define _G1BLKF5 0x20
11076 //==============================================================================
11079 //==============================================================================
11082 extern __at(0x0691) __sfr COG1DBR
;
11100 unsigned G1DBR0
: 1;
11101 unsigned G1DBR1
: 1;
11102 unsigned G1DBR2
: 1;
11103 unsigned G1DBR3
: 1;
11104 unsigned G1DBR4
: 1;
11105 unsigned G1DBR5
: 1;
11118 unsigned G1DBR
: 6;
11123 extern __at(0x0691) volatile __COG1DBRbits_t COG1DBRbits
;
11126 #define _G1DBR0 0x01
11128 #define _G1DBR1 0x02
11130 #define _G1DBR2 0x04
11132 #define _G1DBR3 0x08
11134 #define _G1DBR4 0x10
11136 #define _G1DBR5 0x20
11138 //==============================================================================
11141 //==============================================================================
11144 extern __at(0x0692) __sfr COG1DBF
;
11162 unsigned G1DBF0
: 1;
11163 unsigned G1DBF1
: 1;
11164 unsigned G1DBF2
: 1;
11165 unsigned G1DBF3
: 1;
11166 unsigned G1DBF4
: 1;
11167 unsigned G1DBF5
: 1;
11174 unsigned G1DBF
: 6;
11185 extern __at(0x0692) volatile __COG1DBFbits_t COG1DBFbits
;
11188 #define _G1DBF0 0x01
11190 #define _G1DBF1 0x02
11192 #define _G1DBF2 0x04
11194 #define _G1DBF3 0x08
11196 #define _G1DBF4 0x10
11198 #define _G1DBF5 0x20
11200 //==============================================================================
11203 //==============================================================================
11206 extern __at(0x0693) __sfr COG1CON0
;
11224 unsigned G1MD0
: 1;
11225 unsigned G1MD1
: 1;
11226 unsigned G1MD2
: 1;
11227 unsigned G1CS0
: 1;
11228 unsigned G1CS1
: 1;
11259 } __COG1CON0bits_t
;
11261 extern __at(0x0693) volatile __COG1CON0bits_t COG1CON0bits
;
11263 #define _COG1CON0_MD0 0x01
11264 #define _COG1CON0_G1MD0 0x01
11265 #define _COG1CON0_MD1 0x02
11266 #define _COG1CON0_G1MD1 0x02
11267 #define _COG1CON0_MD2 0x04
11268 #define _COG1CON0_G1MD2 0x04
11269 #define _COG1CON0_CS0 0x08
11270 #define _COG1CON0_G1CS0 0x08
11271 #define _COG1CON0_CS1 0x10
11272 #define _COG1CON0_G1CS1 0x10
11273 #define _COG1CON0_LD 0x40
11274 #define _COG1CON0_G1LD 0x40
11275 #define _COG1CON0_EN 0x80
11276 #define _COG1CON0_G1EN 0x80
11278 //==============================================================================
11281 //==============================================================================
11284 extern __at(0x0694) __sfr COG1CON1
;
11302 unsigned G1POLA
: 1;
11303 unsigned G1POLB
: 1;
11304 unsigned G1POLC
: 1;
11305 unsigned G1POLD
: 1;
11308 unsigned G1FDBS
: 1;
11309 unsigned G1RDBS
: 1;
11311 } __COG1CON1bits_t
;
11313 extern __at(0x0694) volatile __COG1CON1bits_t COG1CON1bits
;
11316 #define _G1POLA 0x01
11318 #define _G1POLB 0x02
11320 #define _G1POLC 0x04
11322 #define _G1POLD 0x08
11324 #define _G1FDBS 0x40
11326 #define _G1RDBS 0x80
11328 //==============================================================================
11331 //==============================================================================
11334 extern __at(0x0695) __sfr COG1RIS0
;
11352 unsigned G1RIS0
: 1;
11353 unsigned G1RIS1
: 1;
11354 unsigned G1RIS2
: 1;
11355 unsigned G1RIS3
: 1;
11356 unsigned G1RIS4
: 1;
11357 unsigned G1RIS5
: 1;
11358 unsigned G1RIS6
: 1;
11359 unsigned G1RIS7
: 1;
11361 } __COG1RIS0bits_t
;
11363 extern __at(0x0695) volatile __COG1RIS0bits_t COG1RIS0bits
;
11366 #define _G1RIS0 0x01
11368 #define _G1RIS1 0x02
11370 #define _G1RIS2 0x04
11372 #define _G1RIS3 0x08
11374 #define _G1RIS4 0x10
11376 #define _G1RIS5 0x20
11378 #define _G1RIS6 0x40
11380 #define _G1RIS7 0x80
11382 //==============================================================================
11385 //==============================================================================
11388 extern __at(0x0696) __sfr COG1RIS1
;
11396 unsigned RIS10
: 1;
11397 unsigned RIS11
: 1;
11398 unsigned RIS12
: 1;
11399 unsigned RIS13
: 1;
11400 unsigned RIS14
: 1;
11401 unsigned RIS15
: 1;
11406 unsigned G1RIS8
: 1;
11407 unsigned G1RIS9
: 1;
11408 unsigned G1RIS10
: 1;
11409 unsigned G1RIS11
: 1;
11410 unsigned G1RIS12
: 1;
11411 unsigned G1RIS13
: 1;
11412 unsigned G1RIS14
: 1;
11413 unsigned G1RIS15
: 1;
11415 } __COG1RIS1bits_t
;
11417 extern __at(0x0696) volatile __COG1RIS1bits_t COG1RIS1bits
;
11420 #define _G1RIS8 0x01
11422 #define _G1RIS9 0x02
11423 #define _RIS10 0x04
11424 #define _G1RIS10 0x04
11425 #define _RIS11 0x08
11426 #define _G1RIS11 0x08
11427 #define _RIS12 0x10
11428 #define _G1RIS12 0x10
11429 #define _RIS13 0x20
11430 #define _G1RIS13 0x20
11431 #define _RIS14 0x40
11432 #define _G1RIS14 0x40
11433 #define _RIS15 0x80
11434 #define _G1RIS15 0x80
11436 //==============================================================================
11439 //==============================================================================
11442 extern __at(0x0697) __sfr COG1RSIM0
;
11448 unsigned RSIM0
: 1;
11449 unsigned RSIM1
: 1;
11450 unsigned RSIM2
: 1;
11451 unsigned RSIM3
: 1;
11452 unsigned RSIM4
: 1;
11453 unsigned RSIM5
: 1;
11454 unsigned RSIM6
: 1;
11455 unsigned RSIM7
: 1;
11460 unsigned G1RSIM0
: 1;
11461 unsigned G1RSIM1
: 1;
11462 unsigned G1RSIM2
: 1;
11463 unsigned G1RSIM3
: 1;
11464 unsigned G1RSIM4
: 1;
11465 unsigned G1RSIM5
: 1;
11466 unsigned G1RSIM6
: 1;
11467 unsigned G1RSIM7
: 1;
11469 } __COG1RSIM0bits_t
;
11471 extern __at(0x0697) volatile __COG1RSIM0bits_t COG1RSIM0bits
;
11473 #define _RSIM0 0x01
11474 #define _G1RSIM0 0x01
11475 #define _RSIM1 0x02
11476 #define _G1RSIM1 0x02
11477 #define _RSIM2 0x04
11478 #define _G1RSIM2 0x04
11479 #define _RSIM3 0x08
11480 #define _G1RSIM3 0x08
11481 #define _RSIM4 0x10
11482 #define _G1RSIM4 0x10
11483 #define _RSIM5 0x20
11484 #define _G1RSIM5 0x20
11485 #define _RSIM6 0x40
11486 #define _G1RSIM6 0x40
11487 #define _RSIM7 0x80
11488 #define _G1RSIM7 0x80
11490 //==============================================================================
11493 //==============================================================================
11496 extern __at(0x0698) __sfr COG1RSIM1
;
11502 unsigned RSIM8
: 1;
11503 unsigned RSIM9
: 1;
11504 unsigned RSIM10
: 1;
11505 unsigned RSIM11
: 1;
11506 unsigned RSIM12
: 1;
11507 unsigned RSIM13
: 1;
11508 unsigned RSIM14
: 1;
11509 unsigned RSIM15
: 1;
11514 unsigned G1RSIM8
: 1;
11515 unsigned G1RSIM9
: 1;
11516 unsigned G1RSIM10
: 1;
11517 unsigned G1RSIM11
: 1;
11518 unsigned G1RSIM12
: 1;
11519 unsigned G1RSIM13
: 1;
11520 unsigned G1RSIM14
: 1;
11521 unsigned G1RSIM15
: 1;
11523 } __COG1RSIM1bits_t
;
11525 extern __at(0x0698) volatile __COG1RSIM1bits_t COG1RSIM1bits
;
11527 #define _RSIM8 0x01
11528 #define _G1RSIM8 0x01
11529 #define _RSIM9 0x02
11530 #define _G1RSIM9 0x02
11531 #define _RSIM10 0x04
11532 #define _G1RSIM10 0x04
11533 #define _RSIM11 0x08
11534 #define _G1RSIM11 0x08
11535 #define _RSIM12 0x10
11536 #define _G1RSIM12 0x10
11537 #define _RSIM13 0x20
11538 #define _G1RSIM13 0x20
11539 #define _RSIM14 0x40
11540 #define _G1RSIM14 0x40
11541 #define _RSIM15 0x80
11542 #define _G1RSIM15 0x80
11544 //==============================================================================
11547 //==============================================================================
11550 extern __at(0x0699) __sfr COG1FIS0
;
11568 unsigned G1FIS0
: 1;
11569 unsigned G1FIS1
: 1;
11570 unsigned G1FIS2
: 1;
11571 unsigned G1FIS3
: 1;
11572 unsigned G1FIS4
: 1;
11573 unsigned G1FIS5
: 1;
11574 unsigned G1FIS6
: 1;
11575 unsigned G1FIS7
: 1;
11577 } __COG1FIS0bits_t
;
11579 extern __at(0x0699) volatile __COG1FIS0bits_t COG1FIS0bits
;
11582 #define _G1FIS0 0x01
11584 #define _G1FIS1 0x02
11586 #define _G1FIS2 0x04
11588 #define _G1FIS3 0x08
11590 #define _G1FIS4 0x10
11592 #define _G1FIS5 0x20
11594 #define _G1FIS6 0x40
11596 #define _G1FIS7 0x80
11598 //==============================================================================
11601 //==============================================================================
11604 extern __at(0x069A) __sfr COG1FIS1
;
11612 unsigned FIS10
: 1;
11613 unsigned FIS11
: 1;
11614 unsigned FIS12
: 1;
11615 unsigned FIS13
: 1;
11616 unsigned FIS14
: 1;
11617 unsigned FIS15
: 1;
11622 unsigned G1FIS8
: 1;
11623 unsigned G1FIS9
: 1;
11624 unsigned G1FIS10
: 1;
11625 unsigned G1FIS11
: 1;
11626 unsigned G1FIS12
: 1;
11627 unsigned G1FIS13
: 1;
11628 unsigned G1FIS14
: 1;
11629 unsigned G1FIS15
: 1;
11631 } __COG1FIS1bits_t
;
11633 extern __at(0x069A) volatile __COG1FIS1bits_t COG1FIS1bits
;
11636 #define _G1FIS8 0x01
11638 #define _G1FIS9 0x02
11639 #define _FIS10 0x04
11640 #define _G1FIS10 0x04
11641 #define _FIS11 0x08
11642 #define _G1FIS11 0x08
11643 #define _FIS12 0x10
11644 #define _G1FIS12 0x10
11645 #define _FIS13 0x20
11646 #define _G1FIS13 0x20
11647 #define _FIS14 0x40
11648 #define _G1FIS14 0x40
11649 #define _FIS15 0x80
11650 #define _G1FIS15 0x80
11652 //==============================================================================
11655 //==============================================================================
11658 extern __at(0x069B) __sfr COG1FSIM0
;
11664 unsigned FSIM0
: 1;
11665 unsigned FSIM1
: 1;
11666 unsigned FSIM2
: 1;
11667 unsigned FSIM3
: 1;
11668 unsigned FSIM4
: 1;
11669 unsigned FSIM5
: 1;
11670 unsigned FSIM6
: 1;
11671 unsigned FSIM7
: 1;
11676 unsigned G1FSIM0
: 1;
11677 unsigned G1FSIM1
: 1;
11678 unsigned G1FSIM2
: 1;
11679 unsigned G1FSIM3
: 1;
11680 unsigned G1FSIM4
: 1;
11681 unsigned G1FSIM5
: 1;
11682 unsigned G1FSIM6
: 1;
11683 unsigned G1FSIM7
: 1;
11685 } __COG1FSIM0bits_t
;
11687 extern __at(0x069B) volatile __COG1FSIM0bits_t COG1FSIM0bits
;
11689 #define _FSIM0 0x01
11690 #define _G1FSIM0 0x01
11691 #define _FSIM1 0x02
11692 #define _G1FSIM1 0x02
11693 #define _FSIM2 0x04
11694 #define _G1FSIM2 0x04
11695 #define _FSIM3 0x08
11696 #define _G1FSIM3 0x08
11697 #define _FSIM4 0x10
11698 #define _G1FSIM4 0x10
11699 #define _FSIM5 0x20
11700 #define _G1FSIM5 0x20
11701 #define _FSIM6 0x40
11702 #define _G1FSIM6 0x40
11703 #define _FSIM7 0x80
11704 #define _G1FSIM7 0x80
11706 //==============================================================================
11709 //==============================================================================
11712 extern __at(0x069C) __sfr COG1FSIM1
;
11718 unsigned FSIM8
: 1;
11719 unsigned FSIM9
: 1;
11720 unsigned FSIM10
: 1;
11721 unsigned FSIM11
: 1;
11722 unsigned FSIM12
: 1;
11723 unsigned FSIM13
: 1;
11724 unsigned FSIM14
: 1;
11725 unsigned FSIM15
: 1;
11730 unsigned G1FSIM8
: 1;
11731 unsigned G1FSIM9
: 1;
11732 unsigned G1FSIM10
: 1;
11733 unsigned G1FSIM11
: 1;
11734 unsigned G1FSIM12
: 1;
11735 unsigned G1FSIM13
: 1;
11736 unsigned G1FSIM14
: 1;
11737 unsigned G1FSIM15
: 1;
11739 } __COG1FSIM1bits_t
;
11741 extern __at(0x069C) volatile __COG1FSIM1bits_t COG1FSIM1bits
;
11743 #define _FSIM8 0x01
11744 #define _G1FSIM8 0x01
11745 #define _FSIM9 0x02
11746 #define _G1FSIM9 0x02
11747 #define _FSIM10 0x04
11748 #define _G1FSIM10 0x04
11749 #define _FSIM11 0x08
11750 #define _G1FSIM11 0x08
11751 #define _FSIM12 0x10
11752 #define _G1FSIM12 0x10
11753 #define _FSIM13 0x20
11754 #define _G1FSIM13 0x20
11755 #define _FSIM14 0x40
11756 #define _G1FSIM14 0x40
11757 #define _FSIM15 0x80
11758 #define _G1FSIM15 0x80
11760 //==============================================================================
11763 //==============================================================================
11766 extern __at(0x069D) __sfr COG1ASD0
;
11774 unsigned ASDAC0
: 1;
11775 unsigned ASDAC1
: 1;
11776 unsigned ASDBD0
: 1;
11777 unsigned ASDBD1
: 1;
11778 unsigned ASREN
: 1;
11786 unsigned G1ASDAC0
: 1;
11787 unsigned G1ASDAC1
: 1;
11788 unsigned G1ASDBD0
: 1;
11789 unsigned G1ASDBD1
: 1;
11790 unsigned ARSEN
: 1;
11791 unsigned G1ASE
: 1;
11802 unsigned G1ARSEN
: 1;
11814 unsigned G1ASREN
: 1;
11821 unsigned ASDAC
: 2;
11828 unsigned G1ASDAC
: 2;
11835 unsigned G1ASDBD
: 2;
11842 unsigned ASDBD
: 2;
11845 } __COG1ASD0bits_t
;
11847 extern __at(0x069D) volatile __COG1ASD0bits_t COG1ASD0bits
;
11849 #define _ASDAC0 0x04
11850 #define _G1ASDAC0 0x04
11851 #define _ASDAC1 0x08
11852 #define _G1ASDAC1 0x08
11853 #define _ASDBD0 0x10
11854 #define _G1ASDBD0 0x10
11855 #define _ASDBD1 0x20
11856 #define _G1ASDBD1 0x20
11857 #define _ASREN 0x40
11858 #define _ARSEN 0x40
11859 #define _G1ARSEN 0x40
11860 #define _G1ASREN 0x40
11862 #define _G1ASE 0x80
11864 //==============================================================================
11867 //==============================================================================
11870 extern __at(0x069E) __sfr COG1ASD1
;
11888 unsigned G1AS0E
: 1;
11889 unsigned G1AS1E
: 1;
11890 unsigned G1AS2E
: 1;
11891 unsigned G1AS3E
: 1;
11892 unsigned G1AS4E
: 1;
11893 unsigned G1AS5E
: 1;
11894 unsigned G1AS6E
: 1;
11895 unsigned G1AS7E
: 1;
11897 } __COG1ASD1bits_t
;
11899 extern __at(0x069E) volatile __COG1ASD1bits_t COG1ASD1bits
;
11902 #define _G1AS0E 0x01
11904 #define _G1AS1E 0x02
11906 #define _G1AS2E 0x04
11908 #define _G1AS3E 0x08
11910 #define _G1AS4E 0x10
11912 #define _G1AS5E 0x20
11914 #define _G1AS6E 0x40
11916 #define _G1AS7E 0x80
11918 //==============================================================================
11921 //==============================================================================
11924 extern __at(0x069F) __sfr COG1STR
;
11934 unsigned SDATA
: 1;
11935 unsigned SDATB
: 1;
11936 unsigned SDATC
: 1;
11937 unsigned SDATD
: 1;
11942 unsigned G1STRA
: 1;
11943 unsigned G1STRB
: 1;
11944 unsigned G1STRC
: 1;
11945 unsigned G1STRD
: 1;
11946 unsigned G1SDATA
: 1;
11947 unsigned G1SDATB
: 1;
11948 unsigned G1SDATC
: 1;
11949 unsigned G1SDATD
: 1;
11953 extern __at(0x069F) volatile __COG1STRbits_t COG1STRbits
;
11956 #define _G1STRA 0x01
11958 #define _G1STRB 0x02
11960 #define _G1STRC 0x04
11962 #define _G1STRD 0x08
11963 #define _SDATA 0x10
11964 #define _G1SDATA 0x10
11965 #define _SDATB 0x20
11966 #define _G1SDATB 0x20
11967 #define _SDATC 0x40
11968 #define _G1SDATC 0x40
11969 #define _SDATD 0x80
11970 #define _G1SDATD 0x80
11972 //==============================================================================
11975 //==============================================================================
11978 extern __at(0x070D) __sfr COG2PHR
;
11996 unsigned G2PHR0
: 1;
11997 unsigned G2PHR1
: 1;
11998 unsigned G2PHR2
: 1;
11999 unsigned G2PHR3
: 1;
12000 unsigned G2PHR4
: 1;
12001 unsigned G2PHR5
: 1;
12014 unsigned G2PHR
: 6;
12019 extern __at(0x070D) volatile __COG2PHRbits_t COG2PHRbits
;
12021 #define _COG2PHR_PHR0 0x01
12022 #define _COG2PHR_G2PHR0 0x01
12023 #define _COG2PHR_PHR1 0x02
12024 #define _COG2PHR_G2PHR1 0x02
12025 #define _COG2PHR_PHR2 0x04
12026 #define _COG2PHR_G2PHR2 0x04
12027 #define _COG2PHR_PHR3 0x08
12028 #define _COG2PHR_G2PHR3 0x08
12029 #define _COG2PHR_PHR4 0x10
12030 #define _COG2PHR_G2PHR4 0x10
12031 #define _COG2PHR_PHR5 0x20
12032 #define _COG2PHR_G2PHR5 0x20
12034 //==============================================================================
12037 //==============================================================================
12040 extern __at(0x070E) __sfr COG2PHF
;
12058 unsigned G2PHF0
: 1;
12059 unsigned G2PHF1
: 1;
12060 unsigned G2PHF2
: 1;
12061 unsigned G2PHF3
: 1;
12062 unsigned G2PHF4
: 1;
12063 unsigned G2PHF5
: 1;
12076 unsigned G2PHF
: 6;
12081 extern __at(0x070E) volatile __COG2PHFbits_t COG2PHFbits
;
12083 #define _COG2PHF_PHF0 0x01
12084 #define _COG2PHF_G2PHF0 0x01
12085 #define _COG2PHF_PHF1 0x02
12086 #define _COG2PHF_G2PHF1 0x02
12087 #define _COG2PHF_PHF2 0x04
12088 #define _COG2PHF_G2PHF2 0x04
12089 #define _COG2PHF_PHF3 0x08
12090 #define _COG2PHF_G2PHF3 0x08
12091 #define _COG2PHF_PHF4 0x10
12092 #define _COG2PHF_G2PHF4 0x10
12093 #define _COG2PHF_PHF5 0x20
12094 #define _COG2PHF_G2PHF5 0x20
12096 //==============================================================================
12099 //==============================================================================
12102 extern __at(0x070F) __sfr COG2BLKR
;
12108 unsigned BLKR0
: 1;
12109 unsigned BLKR1
: 1;
12110 unsigned BLKR2
: 1;
12111 unsigned BLKR3
: 1;
12112 unsigned BLKR4
: 1;
12113 unsigned BLKR5
: 1;
12120 unsigned G2BLKR0
: 1;
12121 unsigned G2BLKR1
: 1;
12122 unsigned G2BLKR2
: 1;
12123 unsigned G2BLKR3
: 1;
12124 unsigned G2BLKR4
: 1;
12125 unsigned G2BLKR5
: 1;
12138 unsigned G2BLKR
: 6;
12141 } __COG2BLKRbits_t
;
12143 extern __at(0x070F) volatile __COG2BLKRbits_t COG2BLKRbits
;
12145 #define _COG2BLKR_BLKR0 0x01
12146 #define _COG2BLKR_G2BLKR0 0x01
12147 #define _COG2BLKR_BLKR1 0x02
12148 #define _COG2BLKR_G2BLKR1 0x02
12149 #define _COG2BLKR_BLKR2 0x04
12150 #define _COG2BLKR_G2BLKR2 0x04
12151 #define _COG2BLKR_BLKR3 0x08
12152 #define _COG2BLKR_G2BLKR3 0x08
12153 #define _COG2BLKR_BLKR4 0x10
12154 #define _COG2BLKR_G2BLKR4 0x10
12155 #define _COG2BLKR_BLKR5 0x20
12156 #define _COG2BLKR_G2BLKR5 0x20
12158 //==============================================================================
12161 //==============================================================================
12164 extern __at(0x0710) __sfr COG2BLKF
;
12170 unsigned BLKF0
: 1;
12171 unsigned BLKF1
: 1;
12172 unsigned BLKF2
: 1;
12173 unsigned BLKF3
: 1;
12174 unsigned BLKF4
: 1;
12175 unsigned BLKF5
: 1;
12182 unsigned G2BLKF0
: 1;
12183 unsigned G2BLKF1
: 1;
12184 unsigned G2BLKF2
: 1;
12185 unsigned G2BLKF3
: 1;
12186 unsigned G2BLKF4
: 1;
12187 unsigned G2BLKF5
: 1;
12200 unsigned G2BLKF
: 6;
12203 } __COG2BLKFbits_t
;
12205 extern __at(0x0710) volatile __COG2BLKFbits_t COG2BLKFbits
;
12207 #define _COG2BLKF_BLKF0 0x01
12208 #define _COG2BLKF_G2BLKF0 0x01
12209 #define _COG2BLKF_BLKF1 0x02
12210 #define _COG2BLKF_G2BLKF1 0x02
12211 #define _COG2BLKF_BLKF2 0x04
12212 #define _COG2BLKF_G2BLKF2 0x04
12213 #define _COG2BLKF_BLKF3 0x08
12214 #define _COG2BLKF_G2BLKF3 0x08
12215 #define _COG2BLKF_BLKF4 0x10
12216 #define _COG2BLKF_G2BLKF4 0x10
12217 #define _COG2BLKF_BLKF5 0x20
12218 #define _COG2BLKF_G2BLKF5 0x20
12220 //==============================================================================
12223 //==============================================================================
12226 extern __at(0x0711) __sfr COG2DBR
;
12244 unsigned G2DBR0
: 1;
12245 unsigned G2DBR1
: 1;
12246 unsigned G2DBR2
: 1;
12247 unsigned G2DBR3
: 1;
12248 unsigned G2DBR4
: 1;
12249 unsigned G2DBR5
: 1;
12262 unsigned G2DBR
: 6;
12267 extern __at(0x0711) volatile __COG2DBRbits_t COG2DBRbits
;
12269 #define _COG2DBR_DBR0 0x01
12270 #define _COG2DBR_G2DBR0 0x01
12271 #define _COG2DBR_DBR1 0x02
12272 #define _COG2DBR_G2DBR1 0x02
12273 #define _COG2DBR_DBR2 0x04
12274 #define _COG2DBR_G2DBR2 0x04
12275 #define _COG2DBR_DBR3 0x08
12276 #define _COG2DBR_G2DBR3 0x08
12277 #define _COG2DBR_DBR4 0x10
12278 #define _COG2DBR_G2DBR4 0x10
12279 #define _COG2DBR_DBR5 0x20
12280 #define _COG2DBR_G2DBR5 0x20
12282 //==============================================================================
12285 //==============================================================================
12288 extern __at(0x0712) __sfr COG2DBF
;
12306 unsigned G2DBF0
: 1;
12307 unsigned G2DBF1
: 1;
12308 unsigned G2DBF2
: 1;
12309 unsigned G2DBF3
: 1;
12310 unsigned G2DBF4
: 1;
12311 unsigned G2DBF5
: 1;
12324 unsigned G2DBF
: 6;
12329 extern __at(0x0712) volatile __COG2DBFbits_t COG2DBFbits
;
12331 #define _COG2DBF_DBF0 0x01
12332 #define _COG2DBF_G2DBF0 0x01
12333 #define _COG2DBF_DBF1 0x02
12334 #define _COG2DBF_G2DBF1 0x02
12335 #define _COG2DBF_DBF2 0x04
12336 #define _COG2DBF_G2DBF2 0x04
12337 #define _COG2DBF_DBF3 0x08
12338 #define _COG2DBF_G2DBF3 0x08
12339 #define _COG2DBF_DBF4 0x10
12340 #define _COG2DBF_G2DBF4 0x10
12341 #define _COG2DBF_DBF5 0x20
12342 #define _COG2DBF_G2DBF5 0x20
12344 //==============================================================================
12347 //==============================================================================
12350 extern __at(0x0713) __sfr COG2CON0
;
12368 unsigned G2MD0
: 1;
12369 unsigned G2MD1
: 1;
12370 unsigned G2MD2
: 1;
12371 unsigned G2CS0
: 1;
12372 unsigned G2CS1
: 1;
12403 } __COG2CON0bits_t
;
12405 extern __at(0x0713) volatile __COG2CON0bits_t COG2CON0bits
;
12407 #define _COG2CON0_MD0 0x01
12408 #define _COG2CON0_G2MD0 0x01
12409 #define _COG2CON0_MD1 0x02
12410 #define _COG2CON0_G2MD1 0x02
12411 #define _COG2CON0_MD2 0x04
12412 #define _COG2CON0_G2MD2 0x04
12413 #define _COG2CON0_CS0 0x08
12414 #define _COG2CON0_G2CS0 0x08
12415 #define _COG2CON0_CS1 0x10
12416 #define _COG2CON0_G2CS1 0x10
12417 #define _COG2CON0_LD 0x40
12418 #define _COG2CON0_G2LD 0x40
12419 #define _COG2CON0_EN 0x80
12420 #define _COG2CON0_G2EN 0x80
12422 //==============================================================================
12425 //==============================================================================
12428 extern __at(0x0714) __sfr COG2CON1
;
12446 unsigned G2POLA
: 1;
12447 unsigned G2POLB
: 1;
12448 unsigned G2POLC
: 1;
12449 unsigned G2POLD
: 1;
12452 unsigned G2FDBS
: 1;
12453 unsigned G2RDBS
: 1;
12455 } __COG2CON1bits_t
;
12457 extern __at(0x0714) volatile __COG2CON1bits_t COG2CON1bits
;
12459 #define _COG2CON1_POLA 0x01
12460 #define _COG2CON1_G2POLA 0x01
12461 #define _COG2CON1_POLB 0x02
12462 #define _COG2CON1_G2POLB 0x02
12463 #define _COG2CON1_POLC 0x04
12464 #define _COG2CON1_G2POLC 0x04
12465 #define _COG2CON1_POLD 0x08
12466 #define _COG2CON1_G2POLD 0x08
12467 #define _COG2CON1_FDBS 0x40
12468 #define _COG2CON1_G2FDBS 0x40
12469 #define _COG2CON1_RDBS 0x80
12470 #define _COG2CON1_G2RDBS 0x80
12472 //==============================================================================
12475 //==============================================================================
12478 extern __at(0x0715) __sfr COG2RIS0
;
12496 unsigned G2RIS0
: 1;
12497 unsigned G2RIS1
: 1;
12498 unsigned G2RIS2
: 1;
12499 unsigned G2RIS3
: 1;
12500 unsigned G2RIS4
: 1;
12501 unsigned G2RIS5
: 1;
12502 unsigned G2RIS6
: 1;
12503 unsigned G2RIS7
: 1;
12505 } __COG2RIS0bits_t
;
12507 extern __at(0x0715) volatile __COG2RIS0bits_t COG2RIS0bits
;
12509 #define _COG2RIS0_RIS0 0x01
12510 #define _COG2RIS0_G2RIS0 0x01
12511 #define _COG2RIS0_RIS1 0x02
12512 #define _COG2RIS0_G2RIS1 0x02
12513 #define _COG2RIS0_RIS2 0x04
12514 #define _COG2RIS0_G2RIS2 0x04
12515 #define _COG2RIS0_RIS3 0x08
12516 #define _COG2RIS0_G2RIS3 0x08
12517 #define _COG2RIS0_RIS4 0x10
12518 #define _COG2RIS0_G2RIS4 0x10
12519 #define _COG2RIS0_RIS5 0x20
12520 #define _COG2RIS0_G2RIS5 0x20
12521 #define _COG2RIS0_RIS6 0x40
12522 #define _COG2RIS0_G2RIS6 0x40
12523 #define _COG2RIS0_RIS7 0x80
12524 #define _COG2RIS0_G2RIS7 0x80
12526 //==============================================================================
12529 //==============================================================================
12532 extern __at(0x0716) __sfr COG2RIS1
;
12540 unsigned RIS10
: 1;
12541 unsigned RIS11
: 1;
12542 unsigned RIS12
: 1;
12543 unsigned RIS13
: 1;
12544 unsigned RIS14
: 1;
12545 unsigned RIS15
: 1;
12550 unsigned G2RIS8
: 1;
12551 unsigned G2RIS9
: 1;
12552 unsigned G2RIS10
: 1;
12553 unsigned G2RIS11
: 1;
12554 unsigned G2RIS12
: 1;
12555 unsigned G2RIS13
: 1;
12556 unsigned G2RIS14
: 1;
12557 unsigned G2RIS15
: 1;
12559 } __COG2RIS1bits_t
;
12561 extern __at(0x0716) volatile __COG2RIS1bits_t COG2RIS1bits
;
12563 #define _COG2RIS1_RIS8 0x01
12564 #define _COG2RIS1_G2RIS8 0x01
12565 #define _COG2RIS1_RIS9 0x02
12566 #define _COG2RIS1_G2RIS9 0x02
12567 #define _COG2RIS1_RIS10 0x04
12568 #define _COG2RIS1_G2RIS10 0x04
12569 #define _COG2RIS1_RIS11 0x08
12570 #define _COG2RIS1_G2RIS11 0x08
12571 #define _COG2RIS1_RIS12 0x10
12572 #define _COG2RIS1_G2RIS12 0x10
12573 #define _COG2RIS1_RIS13 0x20
12574 #define _COG2RIS1_G2RIS13 0x20
12575 #define _COG2RIS1_RIS14 0x40
12576 #define _COG2RIS1_G2RIS14 0x40
12577 #define _COG2RIS1_RIS15 0x80
12578 #define _COG2RIS1_G2RIS15 0x80
12580 //==============================================================================
12583 //==============================================================================
12586 extern __at(0x0717) __sfr COG2RSIM0
;
12592 unsigned RSIM0
: 1;
12593 unsigned RSIM1
: 1;
12594 unsigned RSIM2
: 1;
12595 unsigned RSIM3
: 1;
12596 unsigned RSIM4
: 1;
12597 unsigned RSIM5
: 1;
12598 unsigned RSIM6
: 1;
12599 unsigned RSIM7
: 1;
12604 unsigned G2RSIM0
: 1;
12605 unsigned G2RSIM1
: 1;
12606 unsigned G2RSIM2
: 1;
12607 unsigned G2RSIM3
: 1;
12608 unsigned G2RSIM4
: 1;
12609 unsigned G2RSIM5
: 1;
12610 unsigned G2RSIM6
: 1;
12611 unsigned G2RSIM7
: 1;
12613 } __COG2RSIM0bits_t
;
12615 extern __at(0x0717) volatile __COG2RSIM0bits_t COG2RSIM0bits
;
12617 #define _COG2RSIM0_RSIM0 0x01
12618 #define _COG2RSIM0_G2RSIM0 0x01
12619 #define _COG2RSIM0_RSIM1 0x02
12620 #define _COG2RSIM0_G2RSIM1 0x02
12621 #define _COG2RSIM0_RSIM2 0x04
12622 #define _COG2RSIM0_G2RSIM2 0x04
12623 #define _COG2RSIM0_RSIM3 0x08
12624 #define _COG2RSIM0_G2RSIM3 0x08
12625 #define _COG2RSIM0_RSIM4 0x10
12626 #define _COG2RSIM0_G2RSIM4 0x10
12627 #define _COG2RSIM0_RSIM5 0x20
12628 #define _COG2RSIM0_G2RSIM5 0x20
12629 #define _COG2RSIM0_RSIM6 0x40
12630 #define _COG2RSIM0_G2RSIM6 0x40
12631 #define _COG2RSIM0_RSIM7 0x80
12632 #define _COG2RSIM0_G2RSIM7 0x80
12634 //==============================================================================
12637 //==============================================================================
12640 extern __at(0x0718) __sfr COG2RSIM1
;
12646 unsigned RSIM8
: 1;
12647 unsigned RSIM9
: 1;
12648 unsigned RSIM10
: 1;
12649 unsigned RSIM11
: 1;
12650 unsigned RSIM12
: 1;
12651 unsigned RSIM13
: 1;
12652 unsigned RSIM14
: 1;
12653 unsigned RSIM15
: 1;
12658 unsigned G2RSIM8
: 1;
12659 unsigned G2RSIM9
: 1;
12660 unsigned G2RSIM10
: 1;
12661 unsigned G2RSIM11
: 1;
12662 unsigned G2RSIM12
: 1;
12663 unsigned G2RSIM13
: 1;
12664 unsigned G2RSIM14
: 1;
12665 unsigned G2RSIM15
: 1;
12667 } __COG2RSIM1bits_t
;
12669 extern __at(0x0718) volatile __COG2RSIM1bits_t COG2RSIM1bits
;
12671 #define _COG2RSIM1_RSIM8 0x01
12672 #define _COG2RSIM1_G2RSIM8 0x01
12673 #define _COG2RSIM1_RSIM9 0x02
12674 #define _COG2RSIM1_G2RSIM9 0x02
12675 #define _COG2RSIM1_RSIM10 0x04
12676 #define _COG2RSIM1_G2RSIM10 0x04
12677 #define _COG2RSIM1_RSIM11 0x08
12678 #define _COG2RSIM1_G2RSIM11 0x08
12679 #define _COG2RSIM1_RSIM12 0x10
12680 #define _COG2RSIM1_G2RSIM12 0x10
12681 #define _COG2RSIM1_RSIM13 0x20
12682 #define _COG2RSIM1_G2RSIM13 0x20
12683 #define _COG2RSIM1_RSIM14 0x40
12684 #define _COG2RSIM1_G2RSIM14 0x40
12685 #define _COG2RSIM1_RSIM15 0x80
12686 #define _COG2RSIM1_G2RSIM15 0x80
12688 //==============================================================================
12691 //==============================================================================
12694 extern __at(0x0719) __sfr COG2FIS0
;
12712 unsigned G2FIS0
: 1;
12713 unsigned G2FIS1
: 1;
12714 unsigned G2FIS2
: 1;
12715 unsigned G2FIS3
: 1;
12716 unsigned G2FIS4
: 1;
12717 unsigned G2FIS5
: 1;
12718 unsigned G2FIS6
: 1;
12719 unsigned G2FIS7
: 1;
12721 } __COG2FIS0bits_t
;
12723 extern __at(0x0719) volatile __COG2FIS0bits_t COG2FIS0bits
;
12725 #define _COG2FIS0_FIS0 0x01
12726 #define _COG2FIS0_G2FIS0 0x01
12727 #define _COG2FIS0_FIS1 0x02
12728 #define _COG2FIS0_G2FIS1 0x02
12729 #define _COG2FIS0_FIS2 0x04
12730 #define _COG2FIS0_G2FIS2 0x04
12731 #define _COG2FIS0_FIS3 0x08
12732 #define _COG2FIS0_G2FIS3 0x08
12733 #define _COG2FIS0_FIS4 0x10
12734 #define _COG2FIS0_G2FIS4 0x10
12735 #define _COG2FIS0_FIS5 0x20
12736 #define _COG2FIS0_G2FIS5 0x20
12737 #define _COG2FIS0_FIS6 0x40
12738 #define _COG2FIS0_G2FIS6 0x40
12739 #define _COG2FIS0_FIS7 0x80
12740 #define _COG2FIS0_G2FIS7 0x80
12742 //==============================================================================
12745 //==============================================================================
12748 extern __at(0x071A) __sfr COG2FIS1
;
12756 unsigned FIS10
: 1;
12757 unsigned FIS11
: 1;
12758 unsigned FIS12
: 1;
12759 unsigned FIS13
: 1;
12760 unsigned FIS14
: 1;
12761 unsigned FIS15
: 1;
12766 unsigned G2FIS8
: 1;
12767 unsigned G2FIS9
: 1;
12768 unsigned G2FIS10
: 1;
12769 unsigned G2FIS11
: 1;
12770 unsigned G2FIS12
: 1;
12771 unsigned G2FIS13
: 1;
12772 unsigned G2FIS14
: 1;
12773 unsigned G2FIS15
: 1;
12775 } __COG2FIS1bits_t
;
12777 extern __at(0x071A) volatile __COG2FIS1bits_t COG2FIS1bits
;
12779 #define _COG2FIS1_FIS8 0x01
12780 #define _COG2FIS1_G2FIS8 0x01
12781 #define _COG2FIS1_FIS9 0x02
12782 #define _COG2FIS1_G2FIS9 0x02
12783 #define _COG2FIS1_FIS10 0x04
12784 #define _COG2FIS1_G2FIS10 0x04
12785 #define _COG2FIS1_FIS11 0x08
12786 #define _COG2FIS1_G2FIS11 0x08
12787 #define _COG2FIS1_FIS12 0x10
12788 #define _COG2FIS1_G2FIS12 0x10
12789 #define _COG2FIS1_FIS13 0x20
12790 #define _COG2FIS1_G2FIS13 0x20
12791 #define _COG2FIS1_FIS14 0x40
12792 #define _COG2FIS1_G2FIS14 0x40
12793 #define _COG2FIS1_FIS15 0x80
12794 #define _COG2FIS1_G2FIS15 0x80
12796 //==============================================================================
12799 //==============================================================================
12802 extern __at(0x071B) __sfr COG2FSIM0
;
12808 unsigned FSIM0
: 1;
12809 unsigned FSIM1
: 1;
12810 unsigned FSIM2
: 1;
12811 unsigned FSIM3
: 1;
12812 unsigned FSIM4
: 1;
12813 unsigned FSIM5
: 1;
12814 unsigned FSIM6
: 1;
12815 unsigned FSIM7
: 1;
12820 unsigned G2FSIM0
: 1;
12821 unsigned G2FSIM1
: 1;
12822 unsigned G2FSIM2
: 1;
12823 unsigned G2FSIM3
: 1;
12824 unsigned G2FSIM4
: 1;
12825 unsigned G2FSIM5
: 1;
12826 unsigned G2FSIM6
: 1;
12827 unsigned G2FSIM7
: 1;
12829 } __COG2FSIM0bits_t
;
12831 extern __at(0x071B) volatile __COG2FSIM0bits_t COG2FSIM0bits
;
12833 #define _COG2FSIM0_FSIM0 0x01
12834 #define _COG2FSIM0_G2FSIM0 0x01
12835 #define _COG2FSIM0_FSIM1 0x02
12836 #define _COG2FSIM0_G2FSIM1 0x02
12837 #define _COG2FSIM0_FSIM2 0x04
12838 #define _COG2FSIM0_G2FSIM2 0x04
12839 #define _COG2FSIM0_FSIM3 0x08
12840 #define _COG2FSIM0_G2FSIM3 0x08
12841 #define _COG2FSIM0_FSIM4 0x10
12842 #define _COG2FSIM0_G2FSIM4 0x10
12843 #define _COG2FSIM0_FSIM5 0x20
12844 #define _COG2FSIM0_G2FSIM5 0x20
12845 #define _COG2FSIM0_FSIM6 0x40
12846 #define _COG2FSIM0_G2FSIM6 0x40
12847 #define _COG2FSIM0_FSIM7 0x80
12848 #define _COG2FSIM0_G2FSIM7 0x80
12850 //==============================================================================
12853 //==============================================================================
12856 extern __at(0x071C) __sfr COG2FSIM1
;
12862 unsigned FSIM8
: 1;
12863 unsigned FSIM9
: 1;
12864 unsigned FSIM10
: 1;
12865 unsigned FSIM11
: 1;
12866 unsigned FSIM12
: 1;
12867 unsigned FSIM13
: 1;
12868 unsigned FSIM14
: 1;
12869 unsigned FSIM15
: 1;
12874 unsigned G2FSIM8
: 1;
12875 unsigned G2FSIM9
: 1;
12876 unsigned G2FSIM10
: 1;
12877 unsigned G2FSIM11
: 1;
12878 unsigned G2FSIM12
: 1;
12879 unsigned G2FSIM13
: 1;
12880 unsigned G2FSIM14
: 1;
12881 unsigned G2FSIM15
: 1;
12883 } __COG2FSIM1bits_t
;
12885 extern __at(0x071C) volatile __COG2FSIM1bits_t COG2FSIM1bits
;
12887 #define _COG2FSIM1_FSIM8 0x01
12888 #define _COG2FSIM1_G2FSIM8 0x01
12889 #define _COG2FSIM1_FSIM9 0x02
12890 #define _COG2FSIM1_G2FSIM9 0x02
12891 #define _COG2FSIM1_FSIM10 0x04
12892 #define _COG2FSIM1_G2FSIM10 0x04
12893 #define _COG2FSIM1_FSIM11 0x08
12894 #define _COG2FSIM1_G2FSIM11 0x08
12895 #define _COG2FSIM1_FSIM12 0x10
12896 #define _COG2FSIM1_G2FSIM12 0x10
12897 #define _COG2FSIM1_FSIM13 0x20
12898 #define _COG2FSIM1_G2FSIM13 0x20
12899 #define _COG2FSIM1_FSIM14 0x40
12900 #define _COG2FSIM1_G2FSIM14 0x40
12901 #define _COG2FSIM1_FSIM15 0x80
12902 #define _COG2FSIM1_G2FSIM15 0x80
12904 //==============================================================================
12907 //==============================================================================
12910 extern __at(0x071D) __sfr COG2ASD0
;
12918 unsigned ASDAC0
: 1;
12919 unsigned ASDAC1
: 1;
12920 unsigned ASDBD0
: 1;
12921 unsigned ASDBD1
: 1;
12922 unsigned ASREN
: 1;
12930 unsigned G2ASDAC0
: 1;
12931 unsigned G2ASDAC1
: 1;
12932 unsigned G2ASDBD0
: 1;
12933 unsigned G2ASDBD1
: 1;
12934 unsigned ARSEN
: 1;
12935 unsigned G2ASE
: 1;
12946 unsigned G2ARSEN
: 1;
12958 unsigned G2ASREN
: 1;
12965 unsigned ASDAC
: 2;
12972 unsigned G2ASDAC
: 2;
12979 unsigned ASDBD
: 2;
12986 unsigned G2ASDBD
: 2;
12989 } __COG2ASD0bits_t
;
12991 extern __at(0x071D) volatile __COG2ASD0bits_t COG2ASD0bits
;
12993 #define _COG2ASD0_ASDAC0 0x04
12994 #define _COG2ASD0_G2ASDAC0 0x04
12995 #define _COG2ASD0_ASDAC1 0x08
12996 #define _COG2ASD0_G2ASDAC1 0x08
12997 #define _COG2ASD0_ASDBD0 0x10
12998 #define _COG2ASD0_G2ASDBD0 0x10
12999 #define _COG2ASD0_ASDBD1 0x20
13000 #define _COG2ASD0_G2ASDBD1 0x20
13001 #define _COG2ASD0_ASREN 0x40
13002 #define _COG2ASD0_ARSEN 0x40
13003 #define _COG2ASD0_G2ARSEN 0x40
13004 #define _COG2ASD0_G2ASREN 0x40
13005 #define _COG2ASD0_ASE 0x80
13006 #define _COG2ASD0_G2ASE 0x80
13008 //==============================================================================
13011 //==============================================================================
13014 extern __at(0x071E) __sfr COG2ASD1
;
13032 unsigned G2AS0E
: 1;
13033 unsigned G2AS1E
: 1;
13034 unsigned G2AS2E
: 1;
13035 unsigned G2AS3E
: 1;
13036 unsigned G2AS4E
: 1;
13037 unsigned G2AS5E
: 1;
13038 unsigned G2AS6E
: 1;
13039 unsigned G2AS7E
: 1;
13041 } __COG2ASD1bits_t
;
13043 extern __at(0x071E) volatile __COG2ASD1bits_t COG2ASD1bits
;
13045 #define _COG2ASD1_AS0E 0x01
13046 #define _COG2ASD1_G2AS0E 0x01
13047 #define _COG2ASD1_AS1E 0x02
13048 #define _COG2ASD1_G2AS1E 0x02
13049 #define _COG2ASD1_AS2E 0x04
13050 #define _COG2ASD1_G2AS2E 0x04
13051 #define _COG2ASD1_AS3E 0x08
13052 #define _COG2ASD1_G2AS3E 0x08
13053 #define _COG2ASD1_AS4E 0x10
13054 #define _COG2ASD1_G2AS4E 0x10
13055 #define _COG2ASD1_AS5E 0x20
13056 #define _COG2ASD1_G2AS5E 0x20
13057 #define _COG2ASD1_AS6E 0x40
13058 #define _COG2ASD1_G2AS6E 0x40
13059 #define _COG2ASD1_AS7E 0x80
13060 #define _COG2ASD1_G2AS7E 0x80
13062 //==============================================================================
13065 //==============================================================================
13068 extern __at(0x071F) __sfr COG2STR
;
13078 unsigned SDATA
: 1;
13079 unsigned SDATB
: 1;
13080 unsigned SDATC
: 1;
13081 unsigned SDATD
: 1;
13086 unsigned G2STRA
: 1;
13087 unsigned G2STRB
: 1;
13088 unsigned G2STRC
: 1;
13089 unsigned G2STRD
: 1;
13090 unsigned G2SDATA
: 1;
13091 unsigned G2SDATB
: 1;
13092 unsigned G2SDATC
: 1;
13093 unsigned G2SDATD
: 1;
13097 extern __at(0x071F) volatile __COG2STRbits_t COG2STRbits
;
13099 #define _COG2STR_STRA 0x01
13100 #define _COG2STR_G2STRA 0x01
13101 #define _COG2STR_STRB 0x02
13102 #define _COG2STR_G2STRB 0x02
13103 #define _COG2STR_STRC 0x04
13104 #define _COG2STR_G2STRC 0x04
13105 #define _COG2STR_STRD 0x08
13106 #define _COG2STR_G2STRD 0x08
13107 #define _COG2STR_SDATA 0x10
13108 #define _COG2STR_G2SDATA 0x10
13109 #define _COG2STR_SDATB 0x20
13110 #define _COG2STR_G2SDATB 0x20
13111 #define _COG2STR_SDATC 0x40
13112 #define _COG2STR_G2SDATC 0x40
13113 #define _COG2STR_SDATD 0x80
13114 #define _COG2STR_G2SDATD 0x80
13116 //==============================================================================
13119 //==============================================================================
13122 extern __at(0x078E) __sfr PRG1RTSS
;
13128 unsigned RTSS0
: 1;
13129 unsigned RTSS1
: 1;
13130 unsigned RTSS2
: 1;
13131 unsigned RTSS3
: 1;
13140 unsigned RG1RTSS0
: 1;
13141 unsigned RG1RTSS1
: 1;
13142 unsigned RG1RTSS2
: 1;
13143 unsigned RG1RTSS3
: 1;
13158 unsigned RG1RTSS
: 4;
13161 } __PRG1RTSSbits_t
;
13163 extern __at(0x078E) volatile __PRG1RTSSbits_t PRG1RTSSbits
;
13165 #define _RTSS0 0x01
13166 #define _RG1RTSS0 0x01
13167 #define _RTSS1 0x02
13168 #define _RG1RTSS1 0x02
13169 #define _RTSS2 0x04
13170 #define _RG1RTSS2 0x04
13171 #define _RTSS3 0x08
13172 #define _RG1RTSS3 0x08
13174 //==============================================================================
13177 //==============================================================================
13180 extern __at(0x078F) __sfr PRG1FTSS
;
13186 unsigned FTSS0
: 1;
13187 unsigned FTSS1
: 1;
13188 unsigned FTSS2
: 1;
13189 unsigned FTSS3
: 1;
13198 unsigned RG1FTSS0
: 1;
13199 unsigned RG1FTSS1
: 1;
13200 unsigned RG1FTSS2
: 1;
13201 unsigned RG1FTSS3
: 1;
13210 unsigned RG1FTSS
: 4;
13219 } __PRG1FTSSbits_t
;
13221 extern __at(0x078F) volatile __PRG1FTSSbits_t PRG1FTSSbits
;
13223 #define _FTSS0 0x01
13224 #define _RG1FTSS0 0x01
13225 #define _FTSS1 0x02
13226 #define _RG1FTSS1 0x02
13227 #define _FTSS2 0x04
13228 #define _RG1FTSS2 0x04
13229 #define _FTSS3 0x08
13230 #define _RG1FTSS3 0x08
13232 //==============================================================================
13235 //==============================================================================
13238 extern __at(0x0790) __sfr PRG1INS
;
13256 unsigned RG1INS0
: 1;
13257 unsigned RG1INS1
: 1;
13258 unsigned RG1INS2
: 1;
13259 unsigned RG1INS3
: 1;
13274 unsigned RG1INS
: 4;
13279 extern __at(0x0790) volatile __PRG1INSbits_t PRG1INSbits
;
13282 #define _RG1INS0 0x01
13284 #define _RG1INS1 0x02
13286 #define _RG1INS2 0x04
13288 #define _RG1INS3 0x08
13290 //==============================================================================
13293 //==============================================================================
13296 extern __at(0x0791) __sfr PRG1CON0
;
13304 unsigned MODE0
: 1;
13305 unsigned MODE1
: 1;
13314 unsigned RG1GO
: 1;
13315 unsigned RG1OS
: 1;
13316 unsigned RG1MODE0
: 1;
13317 unsigned RG1MODE1
: 1;
13318 unsigned RG1REDG
: 1;
13319 unsigned RG1FEDG
: 1;
13321 unsigned RG1EN
: 1;
13334 unsigned RG1MODE
: 2;
13337 } __PRG1CON0bits_t
;
13339 extern __at(0x0791) volatile __PRG1CON0bits_t PRG1CON0bits
;
13341 #define _PRG1CON0_GO 0x01
13342 #define _PRG1CON0_RG1GO 0x01
13343 #define _PRG1CON0_OS 0x02
13344 #define _PRG1CON0_RG1OS 0x02
13345 #define _PRG1CON0_MODE0 0x04
13346 #define _PRG1CON0_RG1MODE0 0x04
13347 #define _PRG1CON0_MODE1 0x08
13348 #define _PRG1CON0_RG1MODE1 0x08
13349 #define _PRG1CON0_REDG 0x10
13350 #define _PRG1CON0_RG1REDG 0x10
13351 #define _PRG1CON0_FEDG 0x20
13352 #define _PRG1CON0_RG1FEDG 0x20
13353 #define _PRG1CON0_EN 0x80
13354 #define _PRG1CON0_RG1EN 0x80
13356 //==============================================================================
13359 //==============================================================================
13362 extern __at(0x0792) __sfr PRG1CON1
;
13380 unsigned RG1RPOL
: 1;
13381 unsigned RG1FPOL
: 1;
13382 unsigned RG1RDY
: 1;
13389 } __PRG1CON1bits_t
;
13391 extern __at(0x0792) volatile __PRG1CON1bits_t PRG1CON1bits
;
13394 #define _RG1RPOL 0x01
13396 #define _RG1FPOL 0x02
13398 #define _RG1RDY 0x04
13400 //==============================================================================
13403 //==============================================================================
13406 extern __at(0x0793) __sfr PRG1CON2
;
13412 unsigned ISET0
: 1;
13413 unsigned ISET1
: 1;
13414 unsigned ISET2
: 1;
13415 unsigned ISET3
: 1;
13416 unsigned ISET4
: 1;
13424 unsigned RG1ISET0
: 1;
13425 unsigned RG1ISET1
: 1;
13426 unsigned RG1ISET2
: 1;
13427 unsigned RG1ISET3
: 1;
13428 unsigned RG1ISET4
: 1;
13442 unsigned RG1ISET
: 5;
13445 } __PRG1CON2bits_t
;
13447 extern __at(0x0793) volatile __PRG1CON2bits_t PRG1CON2bits
;
13449 #define _ISET0 0x01
13450 #define _RG1ISET0 0x01
13451 #define _ISET1 0x02
13452 #define _RG1ISET1 0x02
13453 #define _ISET2 0x04
13454 #define _RG1ISET2 0x04
13455 #define _ISET3 0x08
13456 #define _RG1ISET3 0x08
13457 #define _ISET4 0x10
13458 #define _RG1ISET4 0x10
13460 //==============================================================================
13463 //==============================================================================
13466 extern __at(0x0794) __sfr PRG2RTSS
;
13472 unsigned RTSS0
: 1;
13473 unsigned RTSS1
: 1;
13474 unsigned RTSS2
: 1;
13475 unsigned RTSS3
: 1;
13484 unsigned RG2RTSS0
: 1;
13485 unsigned RG2RTSS1
: 1;
13486 unsigned RG2RTSS2
: 1;
13487 unsigned RG2RTSS3
: 1;
13502 unsigned RG2RTSS
: 4;
13505 } __PRG2RTSSbits_t
;
13507 extern __at(0x0794) volatile __PRG2RTSSbits_t PRG2RTSSbits
;
13509 #define _PRG2RTSS_RTSS0 0x01
13510 #define _PRG2RTSS_RG2RTSS0 0x01
13511 #define _PRG2RTSS_RTSS1 0x02
13512 #define _PRG2RTSS_RG2RTSS1 0x02
13513 #define _PRG2RTSS_RTSS2 0x04
13514 #define _PRG2RTSS_RG2RTSS2 0x04
13515 #define _PRG2RTSS_RTSS3 0x08
13516 #define _PRG2RTSS_RG2RTSS3 0x08
13518 //==============================================================================
13521 //==============================================================================
13524 extern __at(0x0795) __sfr PRG2FTSS
;
13530 unsigned FTSS0
: 1;
13531 unsigned FTSS1
: 1;
13532 unsigned FTSS2
: 1;
13533 unsigned FTSS3
: 1;
13542 unsigned RG2FTSS0
: 1;
13543 unsigned RG2FTSS1
: 1;
13544 unsigned RG2FTSS2
: 1;
13545 unsigned RG2FTSS3
: 1;
13560 unsigned RG2FTSS
: 4;
13563 } __PRG2FTSSbits_t
;
13565 extern __at(0x0795) volatile __PRG2FTSSbits_t PRG2FTSSbits
;
13567 #define _PRG2FTSS_FTSS0 0x01
13568 #define _PRG2FTSS_RG2FTSS0 0x01
13569 #define _PRG2FTSS_FTSS1 0x02
13570 #define _PRG2FTSS_RG2FTSS1 0x02
13571 #define _PRG2FTSS_FTSS2 0x04
13572 #define _PRG2FTSS_RG2FTSS2 0x04
13573 #define _PRG2FTSS_FTSS3 0x08
13574 #define _PRG2FTSS_RG2FTSS3 0x08
13576 //==============================================================================
13579 //==============================================================================
13582 extern __at(0x0796) __sfr PRG2INS
;
13600 unsigned RG2INS0
: 1;
13601 unsigned RG2INS1
: 1;
13602 unsigned RG2INS2
: 1;
13603 unsigned RG2INS3
: 1;
13618 unsigned RG2INS
: 4;
13623 extern __at(0x0796) volatile __PRG2INSbits_t PRG2INSbits
;
13625 #define _PRG2INS_INS0 0x01
13626 #define _PRG2INS_RG2INS0 0x01
13627 #define _PRG2INS_INS1 0x02
13628 #define _PRG2INS_RG2INS1 0x02
13629 #define _PRG2INS_INS2 0x04
13630 #define _PRG2INS_RG2INS2 0x04
13631 #define _PRG2INS_INS3 0x08
13632 #define _PRG2INS_RG2INS3 0x08
13634 //==============================================================================
13637 //==============================================================================
13640 extern __at(0x0797) __sfr PRG2CON0
;
13648 unsigned MODE0
: 1;
13649 unsigned MODE1
: 1;
13658 unsigned RG2GO
: 1;
13659 unsigned RG2OS
: 1;
13660 unsigned RG2MODE0
: 1;
13661 unsigned RG2MODE1
: 1;
13662 unsigned RG2REDG
: 1;
13663 unsigned RG2FEDG
: 1;
13665 unsigned RG2EN
: 1;
13678 unsigned RG2MODE
: 2;
13681 } __PRG2CON0bits_t
;
13683 extern __at(0x0797) volatile __PRG2CON0bits_t PRG2CON0bits
;
13685 #define _PRG2CON0_GO 0x01
13686 #define _PRG2CON0_RG2GO 0x01
13687 #define _PRG2CON0_OS 0x02
13688 #define _PRG2CON0_RG2OS 0x02
13689 #define _PRG2CON0_MODE0 0x04
13690 #define _PRG2CON0_RG2MODE0 0x04
13691 #define _PRG2CON0_MODE1 0x08
13692 #define _PRG2CON0_RG2MODE1 0x08
13693 #define _PRG2CON0_REDG 0x10
13694 #define _PRG2CON0_RG2REDG 0x10
13695 #define _PRG2CON0_FEDG 0x20
13696 #define _PRG2CON0_RG2FEDG 0x20
13697 #define _PRG2CON0_EN 0x80
13698 #define _PRG2CON0_RG2EN 0x80
13700 //==============================================================================
13703 //==============================================================================
13706 extern __at(0x0798) __sfr PRG2CON1
;
13724 unsigned RG2RPOL
: 1;
13725 unsigned RG2FPOL
: 1;
13726 unsigned RG2RDY
: 1;
13733 } __PRG2CON1bits_t
;
13735 extern __at(0x0798) volatile __PRG2CON1bits_t PRG2CON1bits
;
13737 #define _PRG2CON1_RPOL 0x01
13738 #define _PRG2CON1_RG2RPOL 0x01
13739 #define _PRG2CON1_FPOL 0x02
13740 #define _PRG2CON1_RG2FPOL 0x02
13741 #define _PRG2CON1_RDY 0x04
13742 #define _PRG2CON1_RG2RDY 0x04
13744 //==============================================================================
13747 //==============================================================================
13750 extern __at(0x0799) __sfr PRG2CON2
;
13756 unsigned ISET0
: 1;
13757 unsigned ISET1
: 1;
13758 unsigned ISET2
: 1;
13759 unsigned ISET3
: 1;
13760 unsigned ISET4
: 1;
13768 unsigned RG2ISET0
: 1;
13769 unsigned RG2ISET1
: 1;
13770 unsigned RG2ISET2
: 1;
13771 unsigned RG2ISET3
: 1;
13772 unsigned RG2ISET4
: 1;
13786 unsigned RG2ISET
: 5;
13789 } __PRG2CON2bits_t
;
13791 extern __at(0x0799) volatile __PRG2CON2bits_t PRG2CON2bits
;
13793 #define _PRG2CON2_ISET0 0x01
13794 #define _PRG2CON2_RG2ISET0 0x01
13795 #define _PRG2CON2_ISET1 0x02
13796 #define _PRG2CON2_RG2ISET1 0x02
13797 #define _PRG2CON2_ISET2 0x04
13798 #define _PRG2CON2_RG2ISET2 0x04
13799 #define _PRG2CON2_ISET3 0x08
13800 #define _PRG2CON2_RG2ISET3 0x08
13801 #define _PRG2CON2_ISET4 0x10
13802 #define _PRG2CON2_RG2ISET4 0x10
13804 //==============================================================================
13807 //==============================================================================
13810 extern __at(0x079A) __sfr PRG3RTSS
;
13816 unsigned RTSS0
: 1;
13817 unsigned RTSS1
: 1;
13818 unsigned RTSS2
: 1;
13819 unsigned RTSS3
: 1;
13828 unsigned RG3RTSS0
: 1;
13829 unsigned RG3RTSS1
: 1;
13830 unsigned RG3RTSS2
: 1;
13831 unsigned RG3RTSS3
: 1;
13840 unsigned RG3RTSS
: 4;
13849 } __PRG3RTSSbits_t
;
13851 extern __at(0x079A) volatile __PRG3RTSSbits_t PRG3RTSSbits
;
13853 #define _PRG3RTSS_RTSS0 0x01
13854 #define _PRG3RTSS_RG3RTSS0 0x01
13855 #define _PRG3RTSS_RTSS1 0x02
13856 #define _PRG3RTSS_RG3RTSS1 0x02
13857 #define _PRG3RTSS_RTSS2 0x04
13858 #define _PRG3RTSS_RG3RTSS2 0x04
13859 #define _PRG3RTSS_RTSS3 0x08
13860 #define _PRG3RTSS_RG3RTSS3 0x08
13862 //==============================================================================
13865 //==============================================================================
13868 extern __at(0x079B) __sfr PRG3FTSS
;
13874 unsigned FTSS0
: 1;
13875 unsigned FTSS1
: 1;
13876 unsigned FTSS2
: 1;
13877 unsigned FTSS3
: 1;
13886 unsigned RG3FTSS0
: 1;
13887 unsigned RG3FTSS1
: 1;
13888 unsigned RG3FTSS2
: 1;
13889 unsigned RG3FTSS3
: 1;
13898 unsigned RG3FTSS
: 4;
13907 } __PRG3FTSSbits_t
;
13909 extern __at(0x079B) volatile __PRG3FTSSbits_t PRG3FTSSbits
;
13911 #define _PRG3FTSS_FTSS0 0x01
13912 #define _PRG3FTSS_RG3FTSS0 0x01
13913 #define _PRG3FTSS_FTSS1 0x02
13914 #define _PRG3FTSS_RG3FTSS1 0x02
13915 #define _PRG3FTSS_FTSS2 0x04
13916 #define _PRG3FTSS_RG3FTSS2 0x04
13917 #define _PRG3FTSS_FTSS3 0x08
13918 #define _PRG3FTSS_RG3FTSS3 0x08
13920 //==============================================================================
13923 //==============================================================================
13926 extern __at(0x079C) __sfr PRG3INS
;
13944 unsigned RG3INS0
: 1;
13945 unsigned RG3INS1
: 1;
13946 unsigned RG3INS2
: 1;
13947 unsigned RG3INS3
: 1;
13962 unsigned RG3INS
: 4;
13967 extern __at(0x079C) volatile __PRG3INSbits_t PRG3INSbits
;
13969 #define _PRG3INS_INS0 0x01
13970 #define _PRG3INS_RG3INS0 0x01
13971 #define _PRG3INS_INS1 0x02
13972 #define _PRG3INS_RG3INS1 0x02
13973 #define _PRG3INS_INS2 0x04
13974 #define _PRG3INS_RG3INS2 0x04
13975 #define _PRG3INS_INS3 0x08
13976 #define _PRG3INS_RG3INS3 0x08
13978 //==============================================================================
13981 //==============================================================================
13984 extern __at(0x079D) __sfr PRG3CON0
;
13992 unsigned MODE0
: 1;
13993 unsigned MODE1
: 1;
14002 unsigned RG3GO
: 1;
14003 unsigned RG3OS
: 1;
14004 unsigned RG3MODE0
: 1;
14005 unsigned RG3MODE1
: 1;
14006 unsigned RG3REDG
: 1;
14007 unsigned RG3FEDG
: 1;
14009 unsigned RG3EN
: 1;
14015 unsigned RG3MODE
: 2;
14025 } __PRG3CON0bits_t
;
14027 extern __at(0x079D) volatile __PRG3CON0bits_t PRG3CON0bits
;
14029 #define _PRG3CON0_GO 0x01
14030 #define _PRG3CON0_RG3GO 0x01
14031 #define _PRG3CON0_OS 0x02
14032 #define _PRG3CON0_RG3OS 0x02
14033 #define _PRG3CON0_MODE0 0x04
14034 #define _PRG3CON0_RG3MODE0 0x04
14035 #define _PRG3CON0_MODE1 0x08
14036 #define _PRG3CON0_RG3MODE1 0x08
14037 #define _PRG3CON0_REDG 0x10
14038 #define _PRG3CON0_RG3REDG 0x10
14039 #define _PRG3CON0_FEDG 0x20
14040 #define _PRG3CON0_RG3FEDG 0x20
14041 #define _PRG3CON0_EN 0x80
14042 #define _PRG3CON0_RG3EN 0x80
14044 //==============================================================================
14047 //==============================================================================
14050 extern __at(0x079E) __sfr PRG3CON1
;
14068 unsigned RG3RPOL
: 1;
14069 unsigned RG3FPOL
: 1;
14070 unsigned RG3RDY
: 1;
14077 } __PRG3CON1bits_t
;
14079 extern __at(0x079E) volatile __PRG3CON1bits_t PRG3CON1bits
;
14081 #define _PRG3CON1_RPOL 0x01
14082 #define _PRG3CON1_RG3RPOL 0x01
14083 #define _PRG3CON1_FPOL 0x02
14084 #define _PRG3CON1_RG3FPOL 0x02
14085 #define _PRG3CON1_RDY 0x04
14086 #define _PRG3CON1_RG3RDY 0x04
14088 //==============================================================================
14091 //==============================================================================
14094 extern __at(0x079F) __sfr PRG3CON2
;
14100 unsigned ISET0
: 1;
14101 unsigned ISET1
: 1;
14102 unsigned ISET2
: 1;
14103 unsigned ISET3
: 1;
14104 unsigned ISET4
: 1;
14112 unsigned RG3ISET0
: 1;
14113 unsigned RG3ISET1
: 1;
14114 unsigned RG3ISET2
: 1;
14115 unsigned RG3ISET3
: 1;
14116 unsigned RG3ISET4
: 1;
14130 unsigned RG3ISET
: 5;
14133 } __PRG3CON2bits_t
;
14135 extern __at(0x079F) volatile __PRG3CON2bits_t PRG3CON2bits
;
14137 #define _PRG3CON2_ISET0 0x01
14138 #define _PRG3CON2_RG3ISET0 0x01
14139 #define _PRG3CON2_ISET1 0x02
14140 #define _PRG3CON2_RG3ISET1 0x02
14141 #define _PRG3CON2_ISET2 0x04
14142 #define _PRG3CON2_RG3ISET2 0x04
14143 #define _PRG3CON2_ISET3 0x08
14144 #define _PRG3CON2_RG3ISET3 0x08
14145 #define _PRG3CON2_ISET4 0x10
14146 #define _PRG3CON2_RG3ISET4 0x10
14148 //==============================================================================
14151 //==============================================================================
14154 extern __at(0x080D) __sfr COG3PHR
;
14172 unsigned G3PHR0
: 1;
14173 unsigned G3PHR1
: 1;
14174 unsigned G3PHR2
: 1;
14175 unsigned G3PHR3
: 1;
14176 unsigned G3PHR4
: 1;
14177 unsigned G3PHR5
: 1;
14190 unsigned G3PHR
: 6;
14195 extern __at(0x080D) volatile __COG3PHRbits_t COG3PHRbits
;
14197 #define _COG3PHR_PHR0 0x01
14198 #define _COG3PHR_G3PHR0 0x01
14199 #define _COG3PHR_PHR1 0x02
14200 #define _COG3PHR_G3PHR1 0x02
14201 #define _COG3PHR_PHR2 0x04
14202 #define _COG3PHR_G3PHR2 0x04
14203 #define _COG3PHR_PHR3 0x08
14204 #define _COG3PHR_G3PHR3 0x08
14205 #define _COG3PHR_PHR4 0x10
14206 #define _COG3PHR_G3PHR4 0x10
14207 #define _COG3PHR_PHR5 0x20
14208 #define _COG3PHR_G3PHR5 0x20
14210 //==============================================================================
14213 //==============================================================================
14216 extern __at(0x080E) __sfr COG3PHF
;
14234 unsigned G3PHF0
: 1;
14235 unsigned G3PHF1
: 1;
14236 unsigned G3PHF2
: 1;
14237 unsigned G3PHF3
: 1;
14238 unsigned G3PHF4
: 1;
14239 unsigned G3PHF5
: 1;
14252 unsigned G3PHF
: 6;
14257 extern __at(0x080E) volatile __COG3PHFbits_t COG3PHFbits
;
14259 #define _COG3PHF_PHF0 0x01
14260 #define _COG3PHF_G3PHF0 0x01
14261 #define _COG3PHF_PHF1 0x02
14262 #define _COG3PHF_G3PHF1 0x02
14263 #define _COG3PHF_PHF2 0x04
14264 #define _COG3PHF_G3PHF2 0x04
14265 #define _COG3PHF_PHF3 0x08
14266 #define _COG3PHF_G3PHF3 0x08
14267 #define _COG3PHF_PHF4 0x10
14268 #define _COG3PHF_G3PHF4 0x10
14269 #define _COG3PHF_PHF5 0x20
14270 #define _COG3PHF_G3PHF5 0x20
14272 //==============================================================================
14275 //==============================================================================
14278 extern __at(0x080F) __sfr COG3BLKR
;
14284 unsigned BLKR0
: 1;
14285 unsigned BLKR1
: 1;
14286 unsigned BLKR2
: 1;
14287 unsigned BLKR3
: 1;
14288 unsigned BLKR4
: 1;
14289 unsigned BLKR5
: 1;
14296 unsigned G3BLKR0
: 1;
14297 unsigned G3BLKR1
: 1;
14298 unsigned G3BLKR2
: 1;
14299 unsigned G3BLKR3
: 1;
14300 unsigned G3BLKR4
: 1;
14301 unsigned G3BLKR5
: 1;
14308 unsigned G3BLKR
: 6;
14317 } __COG3BLKRbits_t
;
14319 extern __at(0x080F) volatile __COG3BLKRbits_t COG3BLKRbits
;
14321 #define _COG3BLKR_BLKR0 0x01
14322 #define _COG3BLKR_G3BLKR0 0x01
14323 #define _COG3BLKR_BLKR1 0x02
14324 #define _COG3BLKR_G3BLKR1 0x02
14325 #define _COG3BLKR_BLKR2 0x04
14326 #define _COG3BLKR_G3BLKR2 0x04
14327 #define _COG3BLKR_BLKR3 0x08
14328 #define _COG3BLKR_G3BLKR3 0x08
14329 #define _COG3BLKR_BLKR4 0x10
14330 #define _COG3BLKR_G3BLKR4 0x10
14331 #define _COG3BLKR_BLKR5 0x20
14332 #define _COG3BLKR_G3BLKR5 0x20
14334 //==============================================================================
14337 //==============================================================================
14340 extern __at(0x0810) __sfr COG3BLKF
;
14346 unsigned BLKF0
: 1;
14347 unsigned BLKF1
: 1;
14348 unsigned BLKF2
: 1;
14349 unsigned BLKF3
: 1;
14350 unsigned BLKF4
: 1;
14351 unsigned BLKF5
: 1;
14358 unsigned G3BLKF0
: 1;
14359 unsigned G3BLKF1
: 1;
14360 unsigned G3BLKF2
: 1;
14361 unsigned G3BLKF3
: 1;
14362 unsigned G3BLKF4
: 1;
14363 unsigned G3BLKF5
: 1;
14370 unsigned G3BLKF
: 6;
14379 } __COG3BLKFbits_t
;
14381 extern __at(0x0810) volatile __COG3BLKFbits_t COG3BLKFbits
;
14383 #define _COG3BLKF_BLKF0 0x01
14384 #define _COG3BLKF_G3BLKF0 0x01
14385 #define _COG3BLKF_BLKF1 0x02
14386 #define _COG3BLKF_G3BLKF1 0x02
14387 #define _COG3BLKF_BLKF2 0x04
14388 #define _COG3BLKF_G3BLKF2 0x04
14389 #define _COG3BLKF_BLKF3 0x08
14390 #define _COG3BLKF_G3BLKF3 0x08
14391 #define _COG3BLKF_BLKF4 0x10
14392 #define _COG3BLKF_G3BLKF4 0x10
14393 #define _COG3BLKF_BLKF5 0x20
14394 #define _COG3BLKF_G3BLKF5 0x20
14396 //==============================================================================
14399 //==============================================================================
14402 extern __at(0x0811) __sfr COG3DBR
;
14420 unsigned G3DBR0
: 1;
14421 unsigned G3DBR1
: 1;
14422 unsigned G3DBR2
: 1;
14423 unsigned G3DBR3
: 1;
14424 unsigned G3DBR4
: 1;
14425 unsigned G3DBR5
: 1;
14432 unsigned G3DBR
: 6;
14443 extern __at(0x0811) volatile __COG3DBRbits_t COG3DBRbits
;
14445 #define _COG3DBR_DBR0 0x01
14446 #define _COG3DBR_G3DBR0 0x01
14447 #define _COG3DBR_DBR1 0x02
14448 #define _COG3DBR_G3DBR1 0x02
14449 #define _COG3DBR_DBR2 0x04
14450 #define _COG3DBR_G3DBR2 0x04
14451 #define _COG3DBR_DBR3 0x08
14452 #define _COG3DBR_G3DBR3 0x08
14453 #define _COG3DBR_DBR4 0x10
14454 #define _COG3DBR_G3DBR4 0x10
14455 #define _COG3DBR_DBR5 0x20
14456 #define _COG3DBR_G3DBR5 0x20
14458 //==============================================================================
14461 //==============================================================================
14464 extern __at(0x0812) __sfr COG3DBF
;
14482 unsigned G3DBF0
: 1;
14483 unsigned G3DBF1
: 1;
14484 unsigned G3DBF2
: 1;
14485 unsigned G3DBF3
: 1;
14486 unsigned G3DBF4
: 1;
14487 unsigned G3DBF5
: 1;
14500 unsigned G3DBF
: 6;
14505 extern __at(0x0812) volatile __COG3DBFbits_t COG3DBFbits
;
14507 #define _COG3DBF_DBF0 0x01
14508 #define _COG3DBF_G3DBF0 0x01
14509 #define _COG3DBF_DBF1 0x02
14510 #define _COG3DBF_G3DBF1 0x02
14511 #define _COG3DBF_DBF2 0x04
14512 #define _COG3DBF_G3DBF2 0x04
14513 #define _COG3DBF_DBF3 0x08
14514 #define _COG3DBF_G3DBF3 0x08
14515 #define _COG3DBF_DBF4 0x10
14516 #define _COG3DBF_G3DBF4 0x10
14517 #define _COG3DBF_DBF5 0x20
14518 #define _COG3DBF_G3DBF5 0x20
14520 //==============================================================================
14523 //==============================================================================
14526 extern __at(0x0813) __sfr COG3CON0
;
14544 unsigned G3MD0
: 1;
14545 unsigned G3MD1
: 1;
14546 unsigned G3MD2
: 1;
14547 unsigned G3CS0
: 1;
14548 unsigned G3CS1
: 1;
14579 } __COG3CON0bits_t
;
14581 extern __at(0x0813) volatile __COG3CON0bits_t COG3CON0bits
;
14583 #define _COG3CON0_MD0 0x01
14584 #define _COG3CON0_G3MD0 0x01
14585 #define _COG3CON0_MD1 0x02
14586 #define _COG3CON0_G3MD1 0x02
14587 #define _COG3CON0_MD2 0x04
14588 #define _COG3CON0_G3MD2 0x04
14589 #define _COG3CON0_CS0 0x08
14590 #define _COG3CON0_G3CS0 0x08
14591 #define _COG3CON0_CS1 0x10
14592 #define _COG3CON0_G3CS1 0x10
14593 #define _COG3CON0_LD 0x40
14594 #define _COG3CON0_G3LD 0x40
14595 #define _COG3CON0_EN 0x80
14596 #define _COG3CON0_G3EN 0x80
14598 //==============================================================================
14601 //==============================================================================
14604 extern __at(0x0814) __sfr COG3CON1
;
14622 unsigned G3POLA
: 1;
14623 unsigned G3POLB
: 1;
14624 unsigned G3POLC
: 1;
14625 unsigned G3POLD
: 1;
14628 unsigned G3FDBS
: 1;
14629 unsigned G3RDBS
: 1;
14631 } __COG3CON1bits_t
;
14633 extern __at(0x0814) volatile __COG3CON1bits_t COG3CON1bits
;
14635 #define _COG3CON1_POLA 0x01
14636 #define _COG3CON1_G3POLA 0x01
14637 #define _COG3CON1_POLB 0x02
14638 #define _COG3CON1_G3POLB 0x02
14639 #define _COG3CON1_POLC 0x04
14640 #define _COG3CON1_G3POLC 0x04
14641 #define _COG3CON1_POLD 0x08
14642 #define _COG3CON1_G3POLD 0x08
14643 #define _COG3CON1_FDBS 0x40
14644 #define _COG3CON1_G3FDBS 0x40
14645 #define _COG3CON1_RDBS 0x80
14646 #define _COG3CON1_G3RDBS 0x80
14648 //==============================================================================
14651 //==============================================================================
14654 extern __at(0x0815) __sfr COG3RIS0
;
14672 unsigned G3RIS0
: 1;
14673 unsigned G3RIS1
: 1;
14674 unsigned G3RIS2
: 1;
14675 unsigned G3RIS3
: 1;
14676 unsigned G3RIS4
: 1;
14677 unsigned G3RIS5
: 1;
14678 unsigned G3RIS6
: 1;
14679 unsigned G3RIS7
: 1;
14681 } __COG3RIS0bits_t
;
14683 extern __at(0x0815) volatile __COG3RIS0bits_t COG3RIS0bits
;
14685 #define _COG3RIS0_RIS0 0x01
14686 #define _COG3RIS0_G3RIS0 0x01
14687 #define _COG3RIS0_RIS1 0x02
14688 #define _COG3RIS0_G3RIS1 0x02
14689 #define _COG3RIS0_RIS2 0x04
14690 #define _COG3RIS0_G3RIS2 0x04
14691 #define _COG3RIS0_RIS3 0x08
14692 #define _COG3RIS0_G3RIS3 0x08
14693 #define _COG3RIS0_RIS4 0x10
14694 #define _COG3RIS0_G3RIS4 0x10
14695 #define _COG3RIS0_RIS5 0x20
14696 #define _COG3RIS0_G3RIS5 0x20
14697 #define _COG3RIS0_RIS6 0x40
14698 #define _COG3RIS0_G3RIS6 0x40
14699 #define _COG3RIS0_RIS7 0x80
14700 #define _COG3RIS0_G3RIS7 0x80
14702 //==============================================================================
14705 //==============================================================================
14708 extern __at(0x0816) __sfr COG3RIS1
;
14717 unsigned RIS11
: 1;
14718 unsigned RIS12
: 1;
14719 unsigned RIS13
: 1;
14720 unsigned RIS14
: 1;
14721 unsigned RIS15
: 1;
14727 unsigned G3RIS9
: 1;
14729 unsigned G3RIS11
: 1;
14730 unsigned G3RIS12
: 1;
14731 unsigned G3RIS13
: 1;
14732 unsigned G3RIS14
: 1;
14733 unsigned G3RIS15
: 1;
14735 } __COG3RIS1bits_t
;
14737 extern __at(0x0816) volatile __COG3RIS1bits_t COG3RIS1bits
;
14739 #define _COG3RIS1_RIS9 0x02
14740 #define _COG3RIS1_G3RIS9 0x02
14741 #define _COG3RIS1_RIS11 0x08
14742 #define _COG3RIS1_G3RIS11 0x08
14743 #define _COG3RIS1_RIS12 0x10
14744 #define _COG3RIS1_G3RIS12 0x10
14745 #define _COG3RIS1_RIS13 0x20
14746 #define _COG3RIS1_G3RIS13 0x20
14747 #define _COG3RIS1_RIS14 0x40
14748 #define _COG3RIS1_G3RIS14 0x40
14749 #define _COG3RIS1_RIS15 0x80
14750 #define _COG3RIS1_G3RIS15 0x80
14752 //==============================================================================
14755 //==============================================================================
14758 extern __at(0x0817) __sfr COG3RSIM0
;
14764 unsigned RSIM0
: 1;
14765 unsigned RSIM1
: 1;
14766 unsigned RSIM2
: 1;
14767 unsigned RSIM3
: 1;
14768 unsigned RSIM4
: 1;
14769 unsigned RSIM5
: 1;
14770 unsigned RSIM6
: 1;
14771 unsigned RSIM7
: 1;
14776 unsigned G3RSIM0
: 1;
14777 unsigned G3RSIM1
: 1;
14778 unsigned G3RSIM2
: 1;
14779 unsigned G3RSIM3
: 1;
14780 unsigned G3RSIM4
: 1;
14781 unsigned G3RSIM5
: 1;
14782 unsigned G3RSIM6
: 1;
14783 unsigned G3RSIM7
: 1;
14785 } __COG3RSIM0bits_t
;
14787 extern __at(0x0817) volatile __COG3RSIM0bits_t COG3RSIM0bits
;
14789 #define _COG3RSIM0_RSIM0 0x01
14790 #define _COG3RSIM0_G3RSIM0 0x01
14791 #define _COG3RSIM0_RSIM1 0x02
14792 #define _COG3RSIM0_G3RSIM1 0x02
14793 #define _COG3RSIM0_RSIM2 0x04
14794 #define _COG3RSIM0_G3RSIM2 0x04
14795 #define _COG3RSIM0_RSIM3 0x08
14796 #define _COG3RSIM0_G3RSIM3 0x08
14797 #define _COG3RSIM0_RSIM4 0x10
14798 #define _COG3RSIM0_G3RSIM4 0x10
14799 #define _COG3RSIM0_RSIM5 0x20
14800 #define _COG3RSIM0_G3RSIM5 0x20
14801 #define _COG3RSIM0_RSIM6 0x40
14802 #define _COG3RSIM0_G3RSIM6 0x40
14803 #define _COG3RSIM0_RSIM7 0x80
14804 #define _COG3RSIM0_G3RSIM7 0x80
14806 //==============================================================================
14809 //==============================================================================
14812 extern __at(0x0818) __sfr COG3RSIM1
;
14819 unsigned RSIM9
: 1;
14821 unsigned RSIM11
: 1;
14822 unsigned RSIM12
: 1;
14823 unsigned RSIM13
: 1;
14824 unsigned RSIM14
: 1;
14825 unsigned RSIM15
: 1;
14831 unsigned G3RSIM9
: 1;
14833 unsigned G3RSIM11
: 1;
14834 unsigned G3RSIM12
: 1;
14835 unsigned G3RSIM13
: 1;
14836 unsigned G3RSIM14
: 1;
14837 unsigned G3RSIM15
: 1;
14839 } __COG3RSIM1bits_t
;
14841 extern __at(0x0818) volatile __COG3RSIM1bits_t COG3RSIM1bits
;
14843 #define _COG3RSIM1_RSIM9 0x02
14844 #define _COG3RSIM1_G3RSIM9 0x02
14845 #define _COG3RSIM1_RSIM11 0x08
14846 #define _COG3RSIM1_G3RSIM11 0x08
14847 #define _COG3RSIM1_RSIM12 0x10
14848 #define _COG3RSIM1_G3RSIM12 0x10
14849 #define _COG3RSIM1_RSIM13 0x20
14850 #define _COG3RSIM1_G3RSIM13 0x20
14851 #define _COG3RSIM1_RSIM14 0x40
14852 #define _COG3RSIM1_G3RSIM14 0x40
14853 #define _COG3RSIM1_RSIM15 0x80
14854 #define _COG3RSIM1_G3RSIM15 0x80
14856 //==============================================================================
14859 //==============================================================================
14862 extern __at(0x0819) __sfr COG3FIS0
;
14880 unsigned G3FIS0
: 1;
14881 unsigned G3FIS1
: 1;
14882 unsigned G3FIS2
: 1;
14883 unsigned G3FIS3
: 1;
14884 unsigned G3FIS4
: 1;
14885 unsigned G3FIS5
: 1;
14886 unsigned G3FIS6
: 1;
14887 unsigned G3FIS7
: 1;
14889 } __COG3FIS0bits_t
;
14891 extern __at(0x0819) volatile __COG3FIS0bits_t COG3FIS0bits
;
14893 #define _COG3FIS0_FIS0 0x01
14894 #define _COG3FIS0_G3FIS0 0x01
14895 #define _COG3FIS0_FIS1 0x02
14896 #define _COG3FIS0_G3FIS1 0x02
14897 #define _COG3FIS0_FIS2 0x04
14898 #define _COG3FIS0_G3FIS2 0x04
14899 #define _COG3FIS0_FIS3 0x08
14900 #define _COG3FIS0_G3FIS3 0x08
14901 #define _COG3FIS0_FIS4 0x10
14902 #define _COG3FIS0_G3FIS4 0x10
14903 #define _COG3FIS0_FIS5 0x20
14904 #define _COG3FIS0_G3FIS5 0x20
14905 #define _COG3FIS0_FIS6 0x40
14906 #define _COG3FIS0_G3FIS6 0x40
14907 #define _COG3FIS0_FIS7 0x80
14908 #define _COG3FIS0_G3FIS7 0x80
14910 //==============================================================================
14913 //==============================================================================
14916 extern __at(0x081A) __sfr COG3FIS1
;
14925 unsigned FIS11
: 1;
14926 unsigned FIS12
: 1;
14927 unsigned FIS13
: 1;
14928 unsigned FIS14
: 1;
14929 unsigned FIS15
: 1;
14935 unsigned G3FIS9
: 1;
14937 unsigned G3FIS11
: 1;
14938 unsigned G3FIS12
: 1;
14939 unsigned G3FIS13
: 1;
14940 unsigned G3FIS14
: 1;
14941 unsigned G3FIS15
: 1;
14943 } __COG3FIS1bits_t
;
14945 extern __at(0x081A) volatile __COG3FIS1bits_t COG3FIS1bits
;
14947 #define _COG3FIS1_FIS9 0x02
14948 #define _COG3FIS1_G3FIS9 0x02
14949 #define _COG3FIS1_FIS11 0x08
14950 #define _COG3FIS1_G3FIS11 0x08
14951 #define _COG3FIS1_FIS12 0x10
14952 #define _COG3FIS1_G3FIS12 0x10
14953 #define _COG3FIS1_FIS13 0x20
14954 #define _COG3FIS1_G3FIS13 0x20
14955 #define _COG3FIS1_FIS14 0x40
14956 #define _COG3FIS1_G3FIS14 0x40
14957 #define _COG3FIS1_FIS15 0x80
14958 #define _COG3FIS1_G3FIS15 0x80
14960 //==============================================================================
14963 //==============================================================================
14966 extern __at(0x081B) __sfr COG3FSIM0
;
14972 unsigned FSIM0
: 1;
14973 unsigned FSIM1
: 1;
14974 unsigned FSIM2
: 1;
14975 unsigned FSIM3
: 1;
14976 unsigned FSIM4
: 1;
14977 unsigned FSIM5
: 1;
14978 unsigned FSIM6
: 1;
14979 unsigned FSIM7
: 1;
14984 unsigned G3FSIM0
: 1;
14985 unsigned G3FSIM1
: 1;
14986 unsigned G3FSIM2
: 1;
14987 unsigned G3FSIM3
: 1;
14988 unsigned G3FSIM4
: 1;
14989 unsigned G3FSIM5
: 1;
14990 unsigned G3FSIM6
: 1;
14991 unsigned G3FSIM7
: 1;
14993 } __COG3FSIM0bits_t
;
14995 extern __at(0x081B) volatile __COG3FSIM0bits_t COG3FSIM0bits
;
14997 #define _COG3FSIM0_FSIM0 0x01
14998 #define _COG3FSIM0_G3FSIM0 0x01
14999 #define _COG3FSIM0_FSIM1 0x02
15000 #define _COG3FSIM0_G3FSIM1 0x02
15001 #define _COG3FSIM0_FSIM2 0x04
15002 #define _COG3FSIM0_G3FSIM2 0x04
15003 #define _COG3FSIM0_FSIM3 0x08
15004 #define _COG3FSIM0_G3FSIM3 0x08
15005 #define _COG3FSIM0_FSIM4 0x10
15006 #define _COG3FSIM0_G3FSIM4 0x10
15007 #define _COG3FSIM0_FSIM5 0x20
15008 #define _COG3FSIM0_G3FSIM5 0x20
15009 #define _COG3FSIM0_FSIM6 0x40
15010 #define _COG3FSIM0_G3FSIM6 0x40
15011 #define _COG3FSIM0_FSIM7 0x80
15012 #define _COG3FSIM0_G3FSIM7 0x80
15014 //==============================================================================
15017 //==============================================================================
15020 extern __at(0x081C) __sfr COG3FSIM1
;
15027 unsigned FSIM9
: 1;
15029 unsigned FSIM11
: 1;
15030 unsigned FSIM12
: 1;
15031 unsigned FSIM13
: 1;
15032 unsigned FSIM14
: 1;
15033 unsigned FSIM15
: 1;
15039 unsigned G3FSIM9
: 1;
15041 unsigned G3FSIM11
: 1;
15042 unsigned G3FSIM12
: 1;
15043 unsigned G3FSIM13
: 1;
15044 unsigned G3FSIM14
: 1;
15045 unsigned G3FSIM15
: 1;
15047 } __COG3FSIM1bits_t
;
15049 extern __at(0x081C) volatile __COG3FSIM1bits_t COG3FSIM1bits
;
15051 #define _COG3FSIM1_FSIM9 0x02
15052 #define _COG3FSIM1_G3FSIM9 0x02
15053 #define _COG3FSIM1_FSIM11 0x08
15054 #define _COG3FSIM1_G3FSIM11 0x08
15055 #define _COG3FSIM1_FSIM12 0x10
15056 #define _COG3FSIM1_G3FSIM12 0x10
15057 #define _COG3FSIM1_FSIM13 0x20
15058 #define _COG3FSIM1_G3FSIM13 0x20
15059 #define _COG3FSIM1_FSIM14 0x40
15060 #define _COG3FSIM1_G3FSIM14 0x40
15061 #define _COG3FSIM1_FSIM15 0x80
15062 #define _COG3FSIM1_G3FSIM15 0x80
15064 //==============================================================================
15067 //==============================================================================
15070 extern __at(0x081D) __sfr COG3ASD0
;
15078 unsigned ASDAC0
: 1;
15079 unsigned ASDAC1
: 1;
15080 unsigned ASDBD0
: 1;
15081 unsigned ASDBD1
: 1;
15082 unsigned ASREN
: 1;
15090 unsigned G3ASDAC0
: 1;
15091 unsigned G3ASDAC1
: 1;
15092 unsigned G3ASDBD0
: 1;
15093 unsigned G3ASDBD1
: 1;
15094 unsigned ARSEN
: 1;
15095 unsigned G3ASE
: 1;
15106 unsigned G3ARSEN
: 1;
15118 unsigned G3ASREN
: 1;
15125 unsigned ASDAC
: 2;
15132 unsigned G3ASDAC
: 2;
15139 unsigned G3ASDBD
: 2;
15146 unsigned ASDBD
: 2;
15149 } __COG3ASD0bits_t
;
15151 extern __at(0x081D) volatile __COG3ASD0bits_t COG3ASD0bits
;
15153 #define _COG3ASD0_ASDAC0 0x04
15154 #define _COG3ASD0_G3ASDAC0 0x04
15155 #define _COG3ASD0_ASDAC1 0x08
15156 #define _COG3ASD0_G3ASDAC1 0x08
15157 #define _COG3ASD0_ASDBD0 0x10
15158 #define _COG3ASD0_G3ASDBD0 0x10
15159 #define _COG3ASD0_ASDBD1 0x20
15160 #define _COG3ASD0_G3ASDBD1 0x20
15161 #define _COG3ASD0_ASREN 0x40
15162 #define _COG3ASD0_ARSEN 0x40
15163 #define _COG3ASD0_G3ARSEN 0x40
15164 #define _COG3ASD0_G3ASREN 0x40
15165 #define _COG3ASD0_ASE 0x80
15166 #define _COG3ASD0_G3ASE 0x80
15168 //==============================================================================
15171 //==============================================================================
15174 extern __at(0x081E) __sfr COG3ASD1
;
15192 unsigned G3AS0E
: 1;
15193 unsigned G3AS1E
: 1;
15194 unsigned G3AS2E
: 1;
15195 unsigned G3AS3E
: 1;
15196 unsigned G3AS4E
: 1;
15197 unsigned G3AS5E
: 1;
15198 unsigned G3AS6E
: 1;
15199 unsigned G3AS7E
: 1;
15201 } __COG3ASD1bits_t
;
15203 extern __at(0x081E) volatile __COG3ASD1bits_t COG3ASD1bits
;
15205 #define _COG3ASD1_AS0E 0x01
15206 #define _COG3ASD1_G3AS0E 0x01
15207 #define _COG3ASD1_AS1E 0x02
15208 #define _COG3ASD1_G3AS1E 0x02
15209 #define _COG3ASD1_AS2E 0x04
15210 #define _COG3ASD1_G3AS2E 0x04
15211 #define _COG3ASD1_AS3E 0x08
15212 #define _COG3ASD1_G3AS3E 0x08
15213 #define _COG3ASD1_AS4E 0x10
15214 #define _COG3ASD1_G3AS4E 0x10
15215 #define _COG3ASD1_AS5E 0x20
15216 #define _COG3ASD1_G3AS5E 0x20
15217 #define _COG3ASD1_AS6E 0x40
15218 #define _COG3ASD1_G3AS6E 0x40
15219 #define _COG3ASD1_AS7E 0x80
15220 #define _COG3ASD1_G3AS7E 0x80
15222 //==============================================================================
15225 //==============================================================================
15228 extern __at(0x081F) __sfr COG3STR
;
15238 unsigned SDATA
: 1;
15239 unsigned SDATB
: 1;
15240 unsigned SDATC
: 1;
15241 unsigned SDATD
: 1;
15246 unsigned G3STRA
: 1;
15247 unsigned G3STRB
: 1;
15248 unsigned G3STRC
: 1;
15249 unsigned G3STRD
: 1;
15250 unsigned G3SDATA
: 1;
15251 unsigned G3SDATB
: 1;
15252 unsigned G3SDATC
: 1;
15253 unsigned G3SDATD
: 1;
15257 extern __at(0x081F) volatile __COG3STRbits_t COG3STRbits
;
15259 #define _COG3STR_STRA 0x01
15260 #define _COG3STR_G3STRA 0x01
15261 #define _COG3STR_STRB 0x02
15262 #define _COG3STR_G3STRB 0x02
15263 #define _COG3STR_STRC 0x04
15264 #define _COG3STR_G3STRC 0x04
15265 #define _COG3STR_STRD 0x08
15266 #define _COG3STR_G3STRD 0x08
15267 #define _COG3STR_SDATA 0x10
15268 #define _COG3STR_G3SDATA 0x10
15269 #define _COG3STR_SDATB 0x20
15270 #define _COG3STR_G3SDATB 0x20
15271 #define _COG3STR_SDATC 0x40
15272 #define _COG3STR_G3SDATC 0x40
15273 #define _COG3STR_SDATD 0x80
15274 #define _COG3STR_G3SDATD 0x80
15276 //==============================================================================
15279 //==============================================================================
15282 extern __at(0x090C) __sfr CM4CON0
;
15290 unsigned Reserved
: 1;
15300 unsigned C4SYNC
: 1;
15301 unsigned C4HYS
: 1;
15303 unsigned C4ZLF
: 1;
15304 unsigned C4POL
: 1;
15306 unsigned C4OUT
: 1;
15311 extern __at(0x090C) volatile __CM4CON0bits_t CM4CON0bits
;
15313 #define _CM4CON0_SYNC 0x01
15314 #define _CM4CON0_C4SYNC 0x01
15315 #define _CM4CON0_HYS 0x02
15316 #define _CM4CON0_C4HYS 0x02
15317 #define _CM4CON0_Reserved 0x04
15318 #define _CM4CON0_C4SP 0x04
15319 #define _CM4CON0_ZLF 0x08
15320 #define _CM4CON0_C4ZLF 0x08
15321 #define _CM4CON0_POL 0x10
15322 #define _CM4CON0_C4POL 0x10
15323 #define _CM4CON0_OUT 0x40
15324 #define _CM4CON0_C4OUT 0x40
15325 #define _CM4CON0_ON 0x80
15326 #define _CM4CON0_C4ON 0x80
15328 //==============================================================================
15331 //==============================================================================
15334 extern __at(0x090D) __sfr CM4CON1
;
15352 unsigned C4INTN
: 1;
15353 unsigned C4INTP
: 1;
15363 extern __at(0x090D) volatile __CM4CON1bits_t CM4CON1bits
;
15365 #define _CM4CON1_INTN 0x01
15366 #define _CM4CON1_C4INTN 0x01
15367 #define _CM4CON1_INTP 0x02
15368 #define _CM4CON1_C4INTP 0x02
15370 //==============================================================================
15373 //==============================================================================
15376 extern __at(0x090E) __sfr CM4NSEL
;
15382 unsigned C4NCH0
: 1;
15383 unsigned C4NCH1
: 1;
15384 unsigned C4NCH2
: 1;
15385 unsigned C4NCH3
: 1;
15394 unsigned C4NCH
: 4;
15399 extern __at(0x090E) volatile __CM4NSELbits_t CM4NSELbits
;
15401 #define _C4NCH0 0x01
15402 #define _C4NCH1 0x02
15403 #define _C4NCH2 0x04
15404 #define _C4NCH3 0x08
15406 //==============================================================================
15409 //==============================================================================
15412 extern __at(0x090F) __sfr CM4PSEL
;
15430 unsigned C4PCH0
: 1;
15431 unsigned C4PCH1
: 1;
15432 unsigned C4PCH2
: 1;
15433 unsigned C4PCH3
: 1;
15448 unsigned C4PCH
: 4;
15453 extern __at(0x090F) volatile __CM4PSELbits_t CM4PSELbits
;
15455 #define _CM4PSEL_PCH0 0x01
15456 #define _CM4PSEL_C4PCH0 0x01
15457 #define _CM4PSEL_PCH1 0x02
15458 #define _CM4PSEL_C4PCH1 0x02
15459 #define _CM4PSEL_PCH2 0x04
15460 #define _CM4PSEL_C4PCH2 0x04
15461 #define _CM4PSEL_PCH3 0x08
15462 #define _CM4PSEL_C4PCH3 0x08
15464 //==============================================================================
15467 //==============================================================================
15470 extern __at(0x0910) __sfr CM5CON0
;
15478 unsigned Reserved
: 1;
15488 unsigned C5SYNC
: 1;
15489 unsigned C5HYS
: 1;
15491 unsigned C5ZLF
: 1;
15492 unsigned C5POL
: 1;
15494 unsigned C5OUT
: 1;
15499 extern __at(0x0910) volatile __CM5CON0bits_t CM5CON0bits
;
15501 #define _CM5CON0_SYNC 0x01
15502 #define _CM5CON0_C5SYNC 0x01
15503 #define _CM5CON0_HYS 0x02
15504 #define _CM5CON0_C5HYS 0x02
15505 #define _CM5CON0_Reserved 0x04
15506 #define _CM5CON0_C5SP 0x04
15507 #define _CM5CON0_ZLF 0x08
15508 #define _CM5CON0_C5ZLF 0x08
15509 #define _CM5CON0_POL 0x10
15510 #define _CM5CON0_C5POL 0x10
15511 #define _CM5CON0_OUT 0x40
15512 #define _CM5CON0_C5OUT 0x40
15513 #define _CM5CON0_ON 0x80
15514 #define _CM5CON0_C5ON 0x80
15516 //==============================================================================
15519 //==============================================================================
15522 extern __at(0x0911) __sfr CM5CON1
;
15540 unsigned C5INTN
: 1;
15541 unsigned C5INTP
: 1;
15551 extern __at(0x0911) volatile __CM5CON1bits_t CM5CON1bits
;
15553 #define _CM5CON1_INTN 0x01
15554 #define _CM5CON1_C5INTN 0x01
15555 #define _CM5CON1_INTP 0x02
15556 #define _CM5CON1_C5INTP 0x02
15558 //==============================================================================
15561 //==============================================================================
15564 extern __at(0x0912) __sfr CM5NSEL
;
15570 unsigned C5NCH0
: 1;
15571 unsigned C5NCH1
: 1;
15572 unsigned C5NCH2
: 1;
15573 unsigned C5NCH3
: 1;
15582 unsigned C5NCH
: 4;
15587 extern __at(0x0912) volatile __CM5NSELbits_t CM5NSELbits
;
15589 #define _C5NCH0 0x01
15590 #define _C5NCH1 0x02
15591 #define _C5NCH2 0x04
15592 #define _C5NCH3 0x08
15594 //==============================================================================
15597 //==============================================================================
15600 extern __at(0x0913) __sfr CM5PSEL
;
15618 unsigned C5PCH0
: 1;
15619 unsigned C5PCH1
: 1;
15620 unsigned C5PCH2
: 1;
15621 unsigned C5PCH3
: 1;
15636 unsigned C5PCH
: 4;
15641 extern __at(0x0913) volatile __CM5PSELbits_t CM5PSELbits
;
15643 #define _CM5PSEL_PCH0 0x01
15644 #define _CM5PSEL_C5PCH0 0x01
15645 #define _CM5PSEL_PCH1 0x02
15646 #define _CM5PSEL_C5PCH1 0x02
15647 #define _CM5PSEL_PCH2 0x04
15648 #define _CM5PSEL_C5PCH2 0x04
15649 #define _CM5PSEL_PCH3 0x08
15650 #define _CM5PSEL_C5PCH3 0x08
15652 //==============================================================================
15655 //==============================================================================
15658 extern __at(0x0914) __sfr CM6CON0
;
15666 unsigned Reserved
: 1;
15676 unsigned C6SYNC
: 1;
15677 unsigned C6HYS
: 1;
15679 unsigned C6ZLF
: 1;
15680 unsigned C6POL
: 1;
15682 unsigned C6OUT
: 1;
15687 extern __at(0x0914) volatile __CM6CON0bits_t CM6CON0bits
;
15689 #define _CM6CON0_SYNC 0x01
15690 #define _CM6CON0_C6SYNC 0x01
15691 #define _CM6CON0_HYS 0x02
15692 #define _CM6CON0_C6HYS 0x02
15693 #define _CM6CON0_Reserved 0x04
15694 #define _CM6CON0_C6SP 0x04
15695 #define _CM6CON0_ZLF 0x08
15696 #define _CM6CON0_C6ZLF 0x08
15697 #define _CM6CON0_POL 0x10
15698 #define _CM6CON0_C6POL 0x10
15699 #define _CM6CON0_OUT 0x40
15700 #define _CM6CON0_C6OUT 0x40
15701 #define _CM6CON0_ON 0x80
15702 #define _CM6CON0_C6ON 0x80
15704 //==============================================================================
15707 //==============================================================================
15710 extern __at(0x0915) __sfr CM6CON1
;
15728 unsigned C6INTN
: 1;
15729 unsigned C6INTP
: 1;
15739 extern __at(0x0915) volatile __CM6CON1bits_t CM6CON1bits
;
15741 #define _CM6CON1_INTN 0x01
15742 #define _CM6CON1_C6INTN 0x01
15743 #define _CM6CON1_INTP 0x02
15744 #define _CM6CON1_C6INTP 0x02
15746 //==============================================================================
15749 //==============================================================================
15752 extern __at(0x0916) __sfr CM6NSEL
;
15758 unsigned C6NCH0
: 1;
15759 unsigned C6NCH1
: 1;
15760 unsigned C6NCH2
: 1;
15761 unsigned C6NCH3
: 1;
15770 unsigned C6NCH
: 4;
15775 extern __at(0x0916) volatile __CM6NSELbits_t CM6NSELbits
;
15777 #define _C6NCH0 0x01
15778 #define _C6NCH1 0x02
15779 #define _C6NCH2 0x04
15780 #define _C6NCH3 0x08
15782 //==============================================================================
15785 //==============================================================================
15788 extern __at(0x0917) __sfr CM6PSEL
;
15806 unsigned C6PCH0
: 1;
15807 unsigned C6PCH1
: 1;
15808 unsigned C6PCH2
: 1;
15809 unsigned C6PCH3
: 1;
15824 unsigned C6PCH
: 4;
15829 extern __at(0x0917) volatile __CM6PSELbits_t CM6PSELbits
;
15831 #define _CM6PSEL_PCH0 0x01
15832 #define _CM6PSEL_C6PCH0 0x01
15833 #define _CM6PSEL_PCH1 0x02
15834 #define _CM6PSEL_C6PCH1 0x02
15835 #define _CM6PSEL_PCH2 0x04
15836 #define _CM6PSEL_C6PCH2 0x04
15837 #define _CM6PSEL_PCH3 0x08
15838 #define _CM6PSEL_C6PCH3 0x08
15840 //==============================================================================
15843 //==============================================================================
15846 extern __at(0x0D8E) __sfr PWMEN
;
15850 unsigned MPWM5EN
: 1;
15851 unsigned MPWM6EN
: 1;
15852 unsigned MPWM11EN
: 1;
15860 extern __at(0x0D8E) volatile __PWMENbits_t PWMENbits
;
15862 #define _MPWM5EN 0x01
15863 #define _MPWM6EN 0x02
15864 #define _MPWM11EN 0x04
15866 //==============================================================================
15869 //==============================================================================
15872 extern __at(0x0D8F) __sfr PWMLD
;
15876 unsigned MPWM5LD
: 1;
15877 unsigned MPWM6LD
: 1;
15878 unsigned MPWM11LD
: 1;
15886 extern __at(0x0D8F) volatile __PWMLDbits_t PWMLDbits
;
15888 #define _MPWM5LD 0x01
15889 #define _MPWM6LD 0x02
15890 #define _MPWM11LD 0x04
15892 //==============================================================================
15895 //==============================================================================
15898 extern __at(0x0D90) __sfr PWMOUT
;
15902 unsigned MPWM5OUT
: 1;
15903 unsigned MPWM6OUT
: 1;
15904 unsigned MPWM11OUT
: 1;
15912 extern __at(0x0D90) volatile __PWMOUTbits_t PWMOUTbits
;
15914 #define _MPWM5OUT 0x01
15915 #define _MPWM6OUT 0x02
15916 #define _MPWM11OUT 0x04
15918 //==============================================================================
15920 extern __at(0x0D91) __sfr PWM5PH
;
15922 //==============================================================================
15925 extern __at(0x0D91) __sfr PWM5PHL
;
15929 unsigned PWM5PHL0
: 1;
15930 unsigned PWM5PHL1
: 1;
15931 unsigned PWM5PHL2
: 1;
15932 unsigned PWM5PHL3
: 1;
15933 unsigned PWM5PHL4
: 1;
15934 unsigned PWM5PHL5
: 1;
15935 unsigned PWM5PHL6
: 1;
15936 unsigned PWM5PHL7
: 1;
15939 extern __at(0x0D91) volatile __PWM5PHLbits_t PWM5PHLbits
;
15941 #define _PWM5PHL0 0x01
15942 #define _PWM5PHL1 0x02
15943 #define _PWM5PHL2 0x04
15944 #define _PWM5PHL3 0x08
15945 #define _PWM5PHL4 0x10
15946 #define _PWM5PHL5 0x20
15947 #define _PWM5PHL6 0x40
15948 #define _PWM5PHL7 0x80
15950 //==============================================================================
15953 //==============================================================================
15956 extern __at(0x0D92) __sfr PWM5PHH
;
15960 unsigned PWM5PHH0
: 1;
15961 unsigned PWM5PHH1
: 1;
15962 unsigned PWM5PHH2
: 1;
15963 unsigned PWM5PHH3
: 1;
15964 unsigned PWM5PHH4
: 1;
15965 unsigned PWM5PHH5
: 1;
15966 unsigned PWM5PHH6
: 1;
15967 unsigned PWM5PHH7
: 1;
15970 extern __at(0x0D92) volatile __PWM5PHHbits_t PWM5PHHbits
;
15972 #define _PWM5PHH0 0x01
15973 #define _PWM5PHH1 0x02
15974 #define _PWM5PHH2 0x04
15975 #define _PWM5PHH3 0x08
15976 #define _PWM5PHH4 0x10
15977 #define _PWM5PHH5 0x20
15978 #define _PWM5PHH6 0x40
15979 #define _PWM5PHH7 0x80
15981 //==============================================================================
15983 extern __at(0x0D93) __sfr PWM5DC
;
15985 //==============================================================================
15988 extern __at(0x0D93) __sfr PWM5DCL
;
15992 unsigned PWM5DCL0
: 1;
15993 unsigned PWM5DCL1
: 1;
15994 unsigned PWM5DCL2
: 1;
15995 unsigned PWM5DCL3
: 1;
15996 unsigned PWM5DCL4
: 1;
15997 unsigned PWM5DCL5
: 1;
15998 unsigned PWM5DCL6
: 1;
15999 unsigned PWM5DCL7
: 1;
16002 extern __at(0x0D93) volatile __PWM5DCLbits_t PWM5DCLbits
;
16004 #define _PWM5DCL0 0x01
16005 #define _PWM5DCL1 0x02
16006 #define _PWM5DCL2 0x04
16007 #define _PWM5DCL3 0x08
16008 #define _PWM5DCL4 0x10
16009 #define _PWM5DCL5 0x20
16010 #define _PWM5DCL6 0x40
16011 #define _PWM5DCL7 0x80
16013 //==============================================================================
16016 //==============================================================================
16019 extern __at(0x0D94) __sfr PWM5DCH
;
16023 unsigned PWM5DCH0
: 1;
16024 unsigned PWM5DCH1
: 1;
16025 unsigned PWM5DCH2
: 1;
16026 unsigned PWM5DCH3
: 1;
16027 unsigned PWM5DCH4
: 1;
16028 unsigned PWM5DCH5
: 1;
16029 unsigned PWM5DCH6
: 1;
16030 unsigned PWM5DCH7
: 1;
16033 extern __at(0x0D94) volatile __PWM5DCHbits_t PWM5DCHbits
;
16035 #define _PWM5DCH0 0x01
16036 #define _PWM5DCH1 0x02
16037 #define _PWM5DCH2 0x04
16038 #define _PWM5DCH3 0x08
16039 #define _PWM5DCH4 0x10
16040 #define _PWM5DCH5 0x20
16041 #define _PWM5DCH6 0x40
16042 #define _PWM5DCH7 0x80
16044 //==============================================================================
16046 extern __at(0x0D95) __sfr PWM5PR
;
16048 //==============================================================================
16051 extern __at(0x0D95) __sfr PWM5PRL
;
16055 unsigned PWM5PRL0
: 1;
16056 unsigned PWM5PRL1
: 1;
16057 unsigned PWM5PRL2
: 1;
16058 unsigned PWM5PRL3
: 1;
16059 unsigned PWM5PRL4
: 1;
16060 unsigned PWM5PRL5
: 1;
16061 unsigned PWM5PRL6
: 1;
16062 unsigned PWM5PRL7
: 1;
16065 extern __at(0x0D95) volatile __PWM5PRLbits_t PWM5PRLbits
;
16067 #define _PWM5PRL0 0x01
16068 #define _PWM5PRL1 0x02
16069 #define _PWM5PRL2 0x04
16070 #define _PWM5PRL3 0x08
16071 #define _PWM5PRL4 0x10
16072 #define _PWM5PRL5 0x20
16073 #define _PWM5PRL6 0x40
16074 #define _PWM5PRL7 0x80
16076 //==============================================================================
16079 //==============================================================================
16082 extern __at(0x0D96) __sfr PWM5PRH
;
16086 unsigned PWM5PRH0
: 1;
16087 unsigned PWM5PRH1
: 1;
16088 unsigned PWM5PRH2
: 1;
16089 unsigned PWM5PRH3
: 1;
16090 unsigned PWM5PRH4
: 1;
16091 unsigned PWM5PRH5
: 1;
16092 unsigned PWM5PRH6
: 1;
16093 unsigned PWM5PRH7
: 1;
16096 extern __at(0x0D96) volatile __PWM5PRHbits_t PWM5PRHbits
;
16098 #define _PWM5PRH0 0x01
16099 #define _PWM5PRH1 0x02
16100 #define _PWM5PRH2 0x04
16101 #define _PWM5PRH3 0x08
16102 #define _PWM5PRH4 0x10
16103 #define _PWM5PRH5 0x20
16104 #define _PWM5PRH6 0x40
16105 #define _PWM5PRH7 0x80
16107 //==============================================================================
16109 extern __at(0x0D97) __sfr PWM5OF
;
16111 //==============================================================================
16114 extern __at(0x0D97) __sfr PWM5OFL
;
16118 unsigned PWM5OFL0
: 1;
16119 unsigned PWM5OFL1
: 1;
16120 unsigned PWM5OFL2
: 1;
16121 unsigned PWM5OFL3
: 1;
16122 unsigned PWM5OFL4
: 1;
16123 unsigned PWM5OFL5
: 1;
16124 unsigned PWM5OFL6
: 1;
16125 unsigned PWM5OFL7
: 1;
16128 extern __at(0x0D97) volatile __PWM5OFLbits_t PWM5OFLbits
;
16130 #define _PWM5OFL0 0x01
16131 #define _PWM5OFL1 0x02
16132 #define _PWM5OFL2 0x04
16133 #define _PWM5OFL3 0x08
16134 #define _PWM5OFL4 0x10
16135 #define _PWM5OFL5 0x20
16136 #define _PWM5OFL6 0x40
16137 #define _PWM5OFL7 0x80
16139 //==============================================================================
16142 //==============================================================================
16145 extern __at(0x0D98) __sfr PWM5OFH
;
16149 unsigned PWM5OFH0
: 1;
16150 unsigned PWM5OFH1
: 1;
16151 unsigned PWM5OFH2
: 1;
16152 unsigned PWM5OFH3
: 1;
16153 unsigned PWM5OFH4
: 1;
16154 unsigned PWM5OFH5
: 1;
16155 unsigned PWM5OFH6
: 1;
16156 unsigned PWM5OFH7
: 1;
16159 extern __at(0x0D98) volatile __PWM5OFHbits_t PWM5OFHbits
;
16161 #define _PWM5OFH0 0x01
16162 #define _PWM5OFH1 0x02
16163 #define _PWM5OFH2 0x04
16164 #define _PWM5OFH3 0x08
16165 #define _PWM5OFH4 0x10
16166 #define _PWM5OFH5 0x20
16167 #define _PWM5OFH6 0x40
16168 #define _PWM5OFH7 0x80
16170 //==============================================================================
16172 extern __at(0x0D99) __sfr PWM5TMR
;
16174 //==============================================================================
16177 extern __at(0x0D99) __sfr PWM5TMRL
;
16181 unsigned PWM5TMRL0
: 1;
16182 unsigned PWM5TMRL1
: 1;
16183 unsigned PWM5TMRL2
: 1;
16184 unsigned PWM5TMRL3
: 1;
16185 unsigned PWM5TMRL4
: 1;
16186 unsigned PWM5TMRL5
: 1;
16187 unsigned PWM5TMRL6
: 1;
16188 unsigned PWM5TMRL7
: 1;
16189 } __PWM5TMRLbits_t
;
16191 extern __at(0x0D99) volatile __PWM5TMRLbits_t PWM5TMRLbits
;
16193 #define _PWM5TMRL0 0x01
16194 #define _PWM5TMRL1 0x02
16195 #define _PWM5TMRL2 0x04
16196 #define _PWM5TMRL3 0x08
16197 #define _PWM5TMRL4 0x10
16198 #define _PWM5TMRL5 0x20
16199 #define _PWM5TMRL6 0x40
16200 #define _PWM5TMRL7 0x80
16202 //==============================================================================
16205 //==============================================================================
16208 extern __at(0x0D9A) __sfr PWM5TMRH
;
16212 unsigned PWM5TMRH0
: 1;
16213 unsigned PWM5TMRH1
: 1;
16214 unsigned PWM5TMRH2
: 1;
16215 unsigned PWM5TMRH3
: 1;
16216 unsigned PWM5TMRH4
: 1;
16217 unsigned PWM5TMRH5
: 1;
16218 unsigned PWM5TMRH6
: 1;
16219 unsigned PWM5TMRH7
: 1;
16220 } __PWM5TMRHbits_t
;
16222 extern __at(0x0D9A) volatile __PWM5TMRHbits_t PWM5TMRHbits
;
16224 #define _PWM5TMRH0 0x01
16225 #define _PWM5TMRH1 0x02
16226 #define _PWM5TMRH2 0x04
16227 #define _PWM5TMRH3 0x08
16228 #define _PWM5TMRH4 0x10
16229 #define _PWM5TMRH5 0x20
16230 #define _PWM5TMRH6 0x40
16231 #define _PWM5TMRH7 0x80
16233 //==============================================================================
16236 //==============================================================================
16239 extern __at(0x0D9B) __sfr PWM5CON
;
16247 unsigned PWM5MODE0
: 1;
16248 unsigned PWM5MODE1
: 1;
16259 unsigned MODE0
: 1;
16260 unsigned MODE1
: 1;
16261 unsigned PWM5POL
: 1;
16262 unsigned PWM5OUT
: 1;
16264 unsigned PWM5EN
: 1;
16277 unsigned PWM5MODE
: 2;
16282 extern __at(0x0D9B) volatile __PWM5CONbits_t PWM5CONbits
;
16284 #define _PWM5CON_PWM5MODE0 0x04
16285 #define _PWM5CON_MODE0 0x04
16286 #define _PWM5CON_PWM5MODE1 0x08
16287 #define _PWM5CON_MODE1 0x08
16288 #define _PWM5CON_POL 0x10
16289 #define _PWM5CON_PWM5POL 0x10
16290 #define _PWM5CON_OUT 0x20
16291 #define _PWM5CON_PWM5OUT 0x20
16292 #define _PWM5CON_EN 0x80
16293 #define _PWM5CON_PWM5EN 0x80
16295 //==============================================================================
16298 //==============================================================================
16301 extern __at(0x0D9C) __sfr PWM5INTCON
;
16319 unsigned PWM5PRIE
: 1;
16320 unsigned PWM5DCIE
: 1;
16321 unsigned PWM5PHIE
: 1;
16322 unsigned PWM5OFIE
: 1;
16328 } __PWM5INTCONbits_t
;
16330 extern __at(0x0D9C) volatile __PWM5INTCONbits_t PWM5INTCONbits
;
16333 #define _PWM5PRIE 0x01
16335 #define _PWM5DCIE 0x02
16337 #define _PWM5PHIE 0x04
16339 #define _PWM5OFIE 0x08
16341 //==============================================================================
16344 //==============================================================================
16347 extern __at(0x0D9C) __sfr PWM5INTE
;
16365 unsigned PWM5PRIE
: 1;
16366 unsigned PWM5DCIE
: 1;
16367 unsigned PWM5PHIE
: 1;
16368 unsigned PWM5OFIE
: 1;
16374 } __PWM5INTEbits_t
;
16376 extern __at(0x0D9C) volatile __PWM5INTEbits_t PWM5INTEbits
;
16378 #define _PWM5INTE_PRIE 0x01
16379 #define _PWM5INTE_PWM5PRIE 0x01
16380 #define _PWM5INTE_DCIE 0x02
16381 #define _PWM5INTE_PWM5DCIE 0x02
16382 #define _PWM5INTE_PHIE 0x04
16383 #define _PWM5INTE_PWM5PHIE 0x04
16384 #define _PWM5INTE_OFIE 0x08
16385 #define _PWM5INTE_PWM5OFIE 0x08
16387 //==============================================================================
16390 //==============================================================================
16393 extern __at(0x0D9D) __sfr PWM5INTF
;
16411 unsigned PWM5PRIF
: 1;
16412 unsigned PWM5DCIF
: 1;
16413 unsigned PWM5PHIF
: 1;
16414 unsigned PWM5OFIF
: 1;
16420 } __PWM5INTFbits_t
;
16422 extern __at(0x0D9D) volatile __PWM5INTFbits_t PWM5INTFbits
;
16425 #define _PWM5PRIF 0x01
16427 #define _PWM5DCIF 0x02
16429 #define _PWM5PHIF 0x04
16431 #define _PWM5OFIF 0x08
16433 //==============================================================================
16436 //==============================================================================
16439 extern __at(0x0D9D) __sfr PWM5INTFLG
;
16457 unsigned PWM5PRIF
: 1;
16458 unsigned PWM5DCIF
: 1;
16459 unsigned PWM5PHIF
: 1;
16460 unsigned PWM5OFIF
: 1;
16466 } __PWM5INTFLGbits_t
;
16468 extern __at(0x0D9D) volatile __PWM5INTFLGbits_t PWM5INTFLGbits
;
16470 #define _PWM5INTFLG_PRIF 0x01
16471 #define _PWM5INTFLG_PWM5PRIF 0x01
16472 #define _PWM5INTFLG_DCIF 0x02
16473 #define _PWM5INTFLG_PWM5DCIF 0x02
16474 #define _PWM5INTFLG_PHIF 0x04
16475 #define _PWM5INTFLG_PWM5PHIF 0x04
16476 #define _PWM5INTFLG_OFIF 0x08
16477 #define _PWM5INTFLG_PWM5OFIF 0x08
16479 //==============================================================================
16482 //==============================================================================
16485 extern __at(0x0D9E) __sfr PWM5CLKCON
;
16491 unsigned PWM5CS0
: 1;
16492 unsigned PWM5CS1
: 1;
16493 unsigned PWM5CS2
: 1;
16495 unsigned PWM5PS0
: 1;
16496 unsigned PWM5PS1
: 1;
16497 unsigned PWM5PS2
: 1;
16521 unsigned PWM5CS
: 3;
16528 unsigned PWM5PS
: 3;
16538 } __PWM5CLKCONbits_t
;
16540 extern __at(0x0D9E) volatile __PWM5CLKCONbits_t PWM5CLKCONbits
;
16542 #define _PWM5CLKCON_PWM5CS0 0x01
16543 #define _PWM5CLKCON_CS0 0x01
16544 #define _PWM5CLKCON_PWM5CS1 0x02
16545 #define _PWM5CLKCON_CS1 0x02
16546 #define _PWM5CLKCON_PWM5CS2 0x04
16547 #define _PWM5CLKCON_CS2 0x04
16548 #define _PWM5CLKCON_PWM5PS0 0x10
16549 #define _PWM5CLKCON_PS0 0x10
16550 #define _PWM5CLKCON_PWM5PS1 0x20
16551 #define _PWM5CLKCON_PS1 0x20
16552 #define _PWM5CLKCON_PWM5PS2 0x40
16553 #define _PWM5CLKCON_PS2 0x40
16555 //==============================================================================
16558 //==============================================================================
16561 extern __at(0x0D9F) __sfr PWM5LDCON
;
16567 unsigned PWM5LDS0
: 1;
16568 unsigned PWM5LDS1
: 1;
16585 unsigned PWM5LDM
: 1;
16586 unsigned PWM5LD
: 1;
16597 unsigned PWM5LDS
: 2;
16600 } __PWM5LDCONbits_t
;
16602 extern __at(0x0D9F) volatile __PWM5LDCONbits_t PWM5LDCONbits
;
16604 #define _PWM5LDS0 0x01
16606 #define _PWM5LDS1 0x02
16609 #define _PWM5LDM 0x40
16611 #define _PWM5LD 0x80
16613 //==============================================================================
16616 //==============================================================================
16619 extern __at(0x0DA0) __sfr PWM5OFCON
;
16625 unsigned PWM5OFS0
: 1;
16626 unsigned PWM5OFS1
: 1;
16630 unsigned PWM5OFM0
: 1;
16631 unsigned PWM5OFM1
: 1;
16641 unsigned PWM5OFMC
: 1;
16655 unsigned PWM5OFS
: 2;
16669 unsigned PWM5OFM
: 2;
16672 } __PWM5OFCONbits_t
;
16674 extern __at(0x0DA0) volatile __PWM5OFCONbits_t PWM5OFCONbits
;
16676 #define _PWM5OFS0 0x01
16678 #define _PWM5OFS1 0x02
16681 #define _PWM5OFMC 0x10
16682 #define _PWM5OFM0 0x20
16684 #define _PWM5OFM1 0x40
16687 //==============================================================================
16689 extern __at(0x0DA1) __sfr PWM6PH
;
16691 //==============================================================================
16694 extern __at(0x0DA1) __sfr PWM6PHL
;
16698 unsigned PWM6PHL0
: 1;
16699 unsigned PWM6PHL1
: 1;
16700 unsigned PWM6PHL2
: 1;
16701 unsigned PWM6PHL3
: 1;
16702 unsigned PWM6PHL4
: 1;
16703 unsigned PWM6PHL5
: 1;
16704 unsigned PWM6PHL6
: 1;
16705 unsigned PWM6PHL7
: 1;
16708 extern __at(0x0DA1) volatile __PWM6PHLbits_t PWM6PHLbits
;
16710 #define _PWM6PHL0 0x01
16711 #define _PWM6PHL1 0x02
16712 #define _PWM6PHL2 0x04
16713 #define _PWM6PHL3 0x08
16714 #define _PWM6PHL4 0x10
16715 #define _PWM6PHL5 0x20
16716 #define _PWM6PHL6 0x40
16717 #define _PWM6PHL7 0x80
16719 //==============================================================================
16722 //==============================================================================
16725 extern __at(0x0DA2) __sfr PWM6PHH
;
16729 unsigned PWM6PHH0
: 1;
16730 unsigned PWM6PHH1
: 1;
16731 unsigned PWM6PHH2
: 1;
16732 unsigned PWM6PHH3
: 1;
16733 unsigned PWM6PHH4
: 1;
16734 unsigned PWM6PHH5
: 1;
16735 unsigned PWM6PHH6
: 1;
16736 unsigned PWM6PHH7
: 1;
16739 extern __at(0x0DA2) volatile __PWM6PHHbits_t PWM6PHHbits
;
16741 #define _PWM6PHH0 0x01
16742 #define _PWM6PHH1 0x02
16743 #define _PWM6PHH2 0x04
16744 #define _PWM6PHH3 0x08
16745 #define _PWM6PHH4 0x10
16746 #define _PWM6PHH5 0x20
16747 #define _PWM6PHH6 0x40
16748 #define _PWM6PHH7 0x80
16750 //==============================================================================
16752 extern __at(0x0DA3) __sfr PWM6DC
;
16754 //==============================================================================
16757 extern __at(0x0DA3) __sfr PWM6DCL
;
16761 unsigned PWM6DCL0
: 1;
16762 unsigned PWM6DCL1
: 1;
16763 unsigned PWM6DCL2
: 1;
16764 unsigned PWM6DCL3
: 1;
16765 unsigned PWM6DCL4
: 1;
16766 unsigned PWM6DCL5
: 1;
16767 unsigned PWM6DCL6
: 1;
16768 unsigned PWM6DCL7
: 1;
16771 extern __at(0x0DA3) volatile __PWM6DCLbits_t PWM6DCLbits
;
16773 #define _PWM6DCL0 0x01
16774 #define _PWM6DCL1 0x02
16775 #define _PWM6DCL2 0x04
16776 #define _PWM6DCL3 0x08
16777 #define _PWM6DCL4 0x10
16778 #define _PWM6DCL5 0x20
16779 #define _PWM6DCL6 0x40
16780 #define _PWM6DCL7 0x80
16782 //==============================================================================
16785 //==============================================================================
16788 extern __at(0x0DA4) __sfr PWM6DCH
;
16792 unsigned PWM6DCH0
: 1;
16793 unsigned PWM6DCH1
: 1;
16794 unsigned PWM6DCH2
: 1;
16795 unsigned PWM6DCH3
: 1;
16796 unsigned PWM6DCH4
: 1;
16797 unsigned PWM6DCH5
: 1;
16798 unsigned PWM6DCH6
: 1;
16799 unsigned PWM6DCH7
: 1;
16802 extern __at(0x0DA4) volatile __PWM6DCHbits_t PWM6DCHbits
;
16804 #define _PWM6DCH0 0x01
16805 #define _PWM6DCH1 0x02
16806 #define _PWM6DCH2 0x04
16807 #define _PWM6DCH3 0x08
16808 #define _PWM6DCH4 0x10
16809 #define _PWM6DCH5 0x20
16810 #define _PWM6DCH6 0x40
16811 #define _PWM6DCH7 0x80
16813 //==============================================================================
16815 extern __at(0x0DA5) __sfr PWM6PR
;
16817 //==============================================================================
16820 extern __at(0x0DA5) __sfr PWM6PRL
;
16824 unsigned PWM6PRL0
: 1;
16825 unsigned PWM6PRL1
: 1;
16826 unsigned PWM6PRL2
: 1;
16827 unsigned PWM6PRL3
: 1;
16828 unsigned PWM6PRL4
: 1;
16829 unsigned PWM6PRL5
: 1;
16830 unsigned PWM6PRL6
: 1;
16831 unsigned PWM6PRL7
: 1;
16834 extern __at(0x0DA5) volatile __PWM6PRLbits_t PWM6PRLbits
;
16836 #define _PWM6PRL0 0x01
16837 #define _PWM6PRL1 0x02
16838 #define _PWM6PRL2 0x04
16839 #define _PWM6PRL3 0x08
16840 #define _PWM6PRL4 0x10
16841 #define _PWM6PRL5 0x20
16842 #define _PWM6PRL6 0x40
16843 #define _PWM6PRL7 0x80
16845 //==============================================================================
16848 //==============================================================================
16851 extern __at(0x0DA6) __sfr PWM6PRH
;
16855 unsigned PWM6PRH0
: 1;
16856 unsigned PWM6PRH1
: 1;
16857 unsigned PWM6PRH2
: 1;
16858 unsigned PWM6PRH3
: 1;
16859 unsigned PWM6PRH4
: 1;
16860 unsigned PWM6PRH5
: 1;
16861 unsigned PWM6PRH6
: 1;
16862 unsigned PWM6PRH7
: 1;
16865 extern __at(0x0DA6) volatile __PWM6PRHbits_t PWM6PRHbits
;
16867 #define _PWM6PRH0 0x01
16868 #define _PWM6PRH1 0x02
16869 #define _PWM6PRH2 0x04
16870 #define _PWM6PRH3 0x08
16871 #define _PWM6PRH4 0x10
16872 #define _PWM6PRH5 0x20
16873 #define _PWM6PRH6 0x40
16874 #define _PWM6PRH7 0x80
16876 //==============================================================================
16878 extern __at(0x0DA7) __sfr PWM6OF
;
16880 //==============================================================================
16883 extern __at(0x0DA7) __sfr PWM6OFL
;
16887 unsigned PWM6OFL0
: 1;
16888 unsigned PWM6OFL1
: 1;
16889 unsigned PWM6OFL2
: 1;
16890 unsigned PWM6OFL3
: 1;
16891 unsigned PWM6OFL4
: 1;
16892 unsigned PWM6OFL5
: 1;
16893 unsigned PWM6OFL6
: 1;
16894 unsigned PWM6OFL7
: 1;
16897 extern __at(0x0DA7) volatile __PWM6OFLbits_t PWM6OFLbits
;
16899 #define _PWM6OFL0 0x01
16900 #define _PWM6OFL1 0x02
16901 #define _PWM6OFL2 0x04
16902 #define _PWM6OFL3 0x08
16903 #define _PWM6OFL4 0x10
16904 #define _PWM6OFL5 0x20
16905 #define _PWM6OFL6 0x40
16906 #define _PWM6OFL7 0x80
16908 //==============================================================================
16911 //==============================================================================
16914 extern __at(0x0DA8) __sfr PWM6OFH
;
16918 unsigned PWM6OFH0
: 1;
16919 unsigned PWM6OFH1
: 1;
16920 unsigned PWM6OFH2
: 1;
16921 unsigned PWM6OFH3
: 1;
16922 unsigned PWM6OFH4
: 1;
16923 unsigned PWM6OFH5
: 1;
16924 unsigned PWM6OFH6
: 1;
16925 unsigned PWM6OFH7
: 1;
16928 extern __at(0x0DA8) volatile __PWM6OFHbits_t PWM6OFHbits
;
16930 #define _PWM6OFH0 0x01
16931 #define _PWM6OFH1 0x02
16932 #define _PWM6OFH2 0x04
16933 #define _PWM6OFH3 0x08
16934 #define _PWM6OFH4 0x10
16935 #define _PWM6OFH5 0x20
16936 #define _PWM6OFH6 0x40
16937 #define _PWM6OFH7 0x80
16939 //==============================================================================
16941 extern __at(0x0DA9) __sfr PWM6TMR
;
16943 //==============================================================================
16946 extern __at(0x0DA9) __sfr PWM6TMRL
;
16950 unsigned PWM6TMRL0
: 1;
16951 unsigned PWM6TMRL1
: 1;
16952 unsigned PWM6TMRL2
: 1;
16953 unsigned PWM6TMRL3
: 1;
16954 unsigned PWM6TMRL4
: 1;
16955 unsigned PWM6TMRL5
: 1;
16956 unsigned PWM6TMRL6
: 1;
16957 unsigned PWM6TMRL7
: 1;
16958 } __PWM6TMRLbits_t
;
16960 extern __at(0x0DA9) volatile __PWM6TMRLbits_t PWM6TMRLbits
;
16962 #define _PWM6TMRL0 0x01
16963 #define _PWM6TMRL1 0x02
16964 #define _PWM6TMRL2 0x04
16965 #define _PWM6TMRL3 0x08
16966 #define _PWM6TMRL4 0x10
16967 #define _PWM6TMRL5 0x20
16968 #define _PWM6TMRL6 0x40
16969 #define _PWM6TMRL7 0x80
16971 //==============================================================================
16974 //==============================================================================
16977 extern __at(0x0DAA) __sfr PWM6TMRH
;
16981 unsigned PWM6TMRH0
: 1;
16982 unsigned PWM6TMRH1
: 1;
16983 unsigned PWM6TMRH2
: 1;
16984 unsigned PWM6TMRH3
: 1;
16985 unsigned PWM6TMRH4
: 1;
16986 unsigned PWM6TMRH5
: 1;
16987 unsigned PWM6TMRH6
: 1;
16988 unsigned PWM6TMRH7
: 1;
16989 } __PWM6TMRHbits_t
;
16991 extern __at(0x0DAA) volatile __PWM6TMRHbits_t PWM6TMRHbits
;
16993 #define _PWM6TMRH0 0x01
16994 #define _PWM6TMRH1 0x02
16995 #define _PWM6TMRH2 0x04
16996 #define _PWM6TMRH3 0x08
16997 #define _PWM6TMRH4 0x10
16998 #define _PWM6TMRH5 0x20
16999 #define _PWM6TMRH6 0x40
17000 #define _PWM6TMRH7 0x80
17002 //==============================================================================
17005 //==============================================================================
17008 extern __at(0x0DAB) __sfr PWM6CON
;
17016 unsigned PWM6MODE0
: 1;
17017 unsigned PWM6MODE1
: 1;
17028 unsigned MODE0
: 1;
17029 unsigned MODE1
: 1;
17030 unsigned PWM6POL
: 1;
17031 unsigned PWM6OUT
: 1;
17033 unsigned PWM6EN
: 1;
17046 unsigned PWM6MODE
: 2;
17051 extern __at(0x0DAB) volatile __PWM6CONbits_t PWM6CONbits
;
17053 #define _PWM6CON_PWM6MODE0 0x04
17054 #define _PWM6CON_MODE0 0x04
17055 #define _PWM6CON_PWM6MODE1 0x08
17056 #define _PWM6CON_MODE1 0x08
17057 #define _PWM6CON_POL 0x10
17058 #define _PWM6CON_PWM6POL 0x10
17059 #define _PWM6CON_OUT 0x20
17060 #define _PWM6CON_PWM6OUT 0x20
17061 #define _PWM6CON_EN 0x80
17062 #define _PWM6CON_PWM6EN 0x80
17064 //==============================================================================
17067 //==============================================================================
17070 extern __at(0x0DAC) __sfr PWM6INTCON
;
17088 unsigned PWM6PRIE
: 1;
17089 unsigned PWM6DCIE
: 1;
17090 unsigned PWM6PHIE
: 1;
17091 unsigned PWM6OFIE
: 1;
17097 } __PWM6INTCONbits_t
;
17099 extern __at(0x0DAC) volatile __PWM6INTCONbits_t PWM6INTCONbits
;
17101 #define _PWM6INTCON_PRIE 0x01
17102 #define _PWM6INTCON_PWM6PRIE 0x01
17103 #define _PWM6INTCON_DCIE 0x02
17104 #define _PWM6INTCON_PWM6DCIE 0x02
17105 #define _PWM6INTCON_PHIE 0x04
17106 #define _PWM6INTCON_PWM6PHIE 0x04
17107 #define _PWM6INTCON_OFIE 0x08
17108 #define _PWM6INTCON_PWM6OFIE 0x08
17110 //==============================================================================
17113 //==============================================================================
17116 extern __at(0x0DAC) __sfr PWM6INTE
;
17134 unsigned PWM6PRIE
: 1;
17135 unsigned PWM6DCIE
: 1;
17136 unsigned PWM6PHIE
: 1;
17137 unsigned PWM6OFIE
: 1;
17143 } __PWM6INTEbits_t
;
17145 extern __at(0x0DAC) volatile __PWM6INTEbits_t PWM6INTEbits
;
17147 #define _PWM6INTE_PRIE 0x01
17148 #define _PWM6INTE_PWM6PRIE 0x01
17149 #define _PWM6INTE_DCIE 0x02
17150 #define _PWM6INTE_PWM6DCIE 0x02
17151 #define _PWM6INTE_PHIE 0x04
17152 #define _PWM6INTE_PWM6PHIE 0x04
17153 #define _PWM6INTE_OFIE 0x08
17154 #define _PWM6INTE_PWM6OFIE 0x08
17156 //==============================================================================
17159 //==============================================================================
17162 extern __at(0x0DAD) __sfr PWM6INTF
;
17180 unsigned PWM6PRIF
: 1;
17181 unsigned PWM6DCIF
: 1;
17182 unsigned PWM6PHIF
: 1;
17183 unsigned PWM6OFIF
: 1;
17189 } __PWM6INTFbits_t
;
17191 extern __at(0x0DAD) volatile __PWM6INTFbits_t PWM6INTFbits
;
17193 #define _PWM6INTF_PRIF 0x01
17194 #define _PWM6INTF_PWM6PRIF 0x01
17195 #define _PWM6INTF_DCIF 0x02
17196 #define _PWM6INTF_PWM6DCIF 0x02
17197 #define _PWM6INTF_PHIF 0x04
17198 #define _PWM6INTF_PWM6PHIF 0x04
17199 #define _PWM6INTF_OFIF 0x08
17200 #define _PWM6INTF_PWM6OFIF 0x08
17202 //==============================================================================
17205 //==============================================================================
17208 extern __at(0x0DAD) __sfr PWM6INTFLG
;
17226 unsigned PWM6PRIF
: 1;
17227 unsigned PWM6DCIF
: 1;
17228 unsigned PWM6PHIF
: 1;
17229 unsigned PWM6OFIF
: 1;
17235 } __PWM6INTFLGbits_t
;
17237 extern __at(0x0DAD) volatile __PWM6INTFLGbits_t PWM6INTFLGbits
;
17239 #define _PWM6INTFLG_PRIF 0x01
17240 #define _PWM6INTFLG_PWM6PRIF 0x01
17241 #define _PWM6INTFLG_DCIF 0x02
17242 #define _PWM6INTFLG_PWM6DCIF 0x02
17243 #define _PWM6INTFLG_PHIF 0x04
17244 #define _PWM6INTFLG_PWM6PHIF 0x04
17245 #define _PWM6INTFLG_OFIF 0x08
17246 #define _PWM6INTFLG_PWM6OFIF 0x08
17248 //==============================================================================
17251 //==============================================================================
17254 extern __at(0x0DAE) __sfr PWM6CLKCON
;
17260 unsigned PWM6CS0
: 1;
17261 unsigned PWM6CS1
: 1;
17262 unsigned PWM6CS2
: 1;
17264 unsigned PWM6PS0
: 1;
17265 unsigned PWM6PS1
: 1;
17266 unsigned PWM6PS2
: 1;
17290 unsigned PWM6CS
: 3;
17297 unsigned PWM6PS
: 3;
17307 } __PWM6CLKCONbits_t
;
17309 extern __at(0x0DAE) volatile __PWM6CLKCONbits_t PWM6CLKCONbits
;
17311 #define _PWM6CLKCON_PWM6CS0 0x01
17312 #define _PWM6CLKCON_CS0 0x01
17313 #define _PWM6CLKCON_PWM6CS1 0x02
17314 #define _PWM6CLKCON_CS1 0x02
17315 #define _PWM6CLKCON_PWM6CS2 0x04
17316 #define _PWM6CLKCON_CS2 0x04
17317 #define _PWM6CLKCON_PWM6PS0 0x10
17318 #define _PWM6CLKCON_PS0 0x10
17319 #define _PWM6CLKCON_PWM6PS1 0x20
17320 #define _PWM6CLKCON_PS1 0x20
17321 #define _PWM6CLKCON_PWM6PS2 0x40
17322 #define _PWM6CLKCON_PS2 0x40
17324 //==============================================================================
17327 //==============================================================================
17330 extern __at(0x0DAF) __sfr PWM6LDCON
;
17336 unsigned PWM6LDS0
: 1;
17337 unsigned PWM6LDS1
: 1;
17354 unsigned PWM6LDM
: 1;
17355 unsigned PWM6LD
: 1;
17360 unsigned PWM6LDS
: 2;
17369 } __PWM6LDCONbits_t
;
17371 extern __at(0x0DAF) volatile __PWM6LDCONbits_t PWM6LDCONbits
;
17373 #define _PWM6LDCON_PWM6LDS0 0x01
17374 #define _PWM6LDCON_LDS0 0x01
17375 #define _PWM6LDCON_PWM6LDS1 0x02
17376 #define _PWM6LDCON_LDS1 0x02
17377 #define _PWM6LDCON_LDT 0x40
17378 #define _PWM6LDCON_PWM6LDM 0x40
17379 #define _PWM6LDCON_LDA 0x80
17380 #define _PWM6LDCON_PWM6LD 0x80
17382 //==============================================================================
17385 //==============================================================================
17388 extern __at(0x0DB0) __sfr PWM6OFCON
;
17394 unsigned PWM6OFS0
: 1;
17395 unsigned PWM6OFS1
: 1;
17399 unsigned PWM6OFM0
: 1;
17400 unsigned PWM6OFM1
: 1;
17410 unsigned PWM6OFMC
: 1;
17418 unsigned PWM6OFS
: 2;
17438 unsigned PWM6OFM
: 2;
17441 } __PWM6OFCONbits_t
;
17443 extern __at(0x0DB0) volatile __PWM6OFCONbits_t PWM6OFCONbits
;
17445 #define _PWM6OFCON_PWM6OFS0 0x01
17446 #define _PWM6OFCON_OFS0 0x01
17447 #define _PWM6OFCON_PWM6OFS1 0x02
17448 #define _PWM6OFCON_OFS1 0x02
17449 #define _PWM6OFCON_OFO 0x10
17450 #define _PWM6OFCON_PWM6OFMC 0x10
17451 #define _PWM6OFCON_PWM6OFM0 0x20
17452 #define _PWM6OFCON_OFM0 0x20
17453 #define _PWM6OFCON_PWM6OFM1 0x40
17454 #define _PWM6OFCON_OFM1 0x40
17456 //==============================================================================
17458 extern __at(0x0DB1) __sfr PWM11PH
;
17460 //==============================================================================
17463 extern __at(0x0DB1) __sfr PWM11PHL
;
17467 unsigned PWM11PHL0
: 1;
17468 unsigned PWM11PHL1
: 1;
17469 unsigned PWM11PHL2
: 1;
17470 unsigned PWM11PHL3
: 1;
17471 unsigned PWM11PHL4
: 1;
17472 unsigned PWM11PHL5
: 1;
17473 unsigned PWM11PHL6
: 1;
17474 unsigned PWM11PHL7
: 1;
17475 } __PWM11PHLbits_t
;
17477 extern __at(0x0DB1) volatile __PWM11PHLbits_t PWM11PHLbits
;
17479 #define _PWM11PHL0 0x01
17480 #define _PWM11PHL1 0x02
17481 #define _PWM11PHL2 0x04
17482 #define _PWM11PHL3 0x08
17483 #define _PWM11PHL4 0x10
17484 #define _PWM11PHL5 0x20
17485 #define _PWM11PHL6 0x40
17486 #define _PWM11PHL7 0x80
17488 //==============================================================================
17491 //==============================================================================
17494 extern __at(0x0DB2) __sfr PWM11PHH
;
17498 unsigned PWM11PHH0
: 1;
17499 unsigned PWM11PHH1
: 1;
17500 unsigned PWM11PHH2
: 1;
17501 unsigned PWM11PHH3
: 1;
17502 unsigned PWM11PHH4
: 1;
17503 unsigned PWM11PHH5
: 1;
17504 unsigned PWM11PHH6
: 1;
17505 unsigned PWM11PHH7
: 1;
17506 } __PWM11PHHbits_t
;
17508 extern __at(0x0DB2) volatile __PWM11PHHbits_t PWM11PHHbits
;
17510 #define _PWM11PHH0 0x01
17511 #define _PWM11PHH1 0x02
17512 #define _PWM11PHH2 0x04
17513 #define _PWM11PHH3 0x08
17514 #define _PWM11PHH4 0x10
17515 #define _PWM11PHH5 0x20
17516 #define _PWM11PHH6 0x40
17517 #define _PWM11PHH7 0x80
17519 //==============================================================================
17521 extern __at(0x0DB3) __sfr PWM11DC
;
17523 //==============================================================================
17526 extern __at(0x0DB3) __sfr PWM11DCL
;
17530 unsigned PWM11DCL0
: 1;
17531 unsigned PWM11DCL1
: 1;
17532 unsigned PWM11DCL2
: 1;
17533 unsigned PWM11DCL3
: 1;
17534 unsigned PWM11DCL4
: 1;
17535 unsigned PWM11DCL5
: 1;
17536 unsigned PWM11DCL6
: 1;
17537 unsigned PWM11DCL7
: 1;
17538 } __PWM11DCLbits_t
;
17540 extern __at(0x0DB3) volatile __PWM11DCLbits_t PWM11DCLbits
;
17542 #define _PWM11DCL0 0x01
17543 #define _PWM11DCL1 0x02
17544 #define _PWM11DCL2 0x04
17545 #define _PWM11DCL3 0x08
17546 #define _PWM11DCL4 0x10
17547 #define _PWM11DCL5 0x20
17548 #define _PWM11DCL6 0x40
17549 #define _PWM11DCL7 0x80
17551 //==============================================================================
17554 //==============================================================================
17557 extern __at(0x0DB4) __sfr PWM11DCH
;
17561 unsigned PWM11DCH0
: 1;
17562 unsigned PWM11DCH1
: 1;
17563 unsigned PWM11DCH2
: 1;
17564 unsigned PWM11DCH3
: 1;
17565 unsigned PWM11DCH4
: 1;
17566 unsigned PWM11DCH5
: 1;
17567 unsigned PWM11DCH6
: 1;
17568 unsigned PWM11DCH7
: 1;
17569 } __PWM11DCHbits_t
;
17571 extern __at(0x0DB4) volatile __PWM11DCHbits_t PWM11DCHbits
;
17573 #define _PWM11DCH0 0x01
17574 #define _PWM11DCH1 0x02
17575 #define _PWM11DCH2 0x04
17576 #define _PWM11DCH3 0x08
17577 #define _PWM11DCH4 0x10
17578 #define _PWM11DCH5 0x20
17579 #define _PWM11DCH6 0x40
17580 #define _PWM11DCH7 0x80
17582 //==============================================================================
17584 extern __at(0x0DB5) __sfr PWM11PR
;
17586 //==============================================================================
17589 extern __at(0x0DB5) __sfr PWM11PRL
;
17593 unsigned PWM11PRL0
: 1;
17594 unsigned PWM11PRL1
: 1;
17595 unsigned PWM11PRL2
: 1;
17596 unsigned PWM11PRL3
: 1;
17597 unsigned PWM11PRL4
: 1;
17598 unsigned PWM11PRL5
: 1;
17599 unsigned PWM11PRL6
: 1;
17600 unsigned PWM11PRL7
: 1;
17601 } __PWM11PRLbits_t
;
17603 extern __at(0x0DB5) volatile __PWM11PRLbits_t PWM11PRLbits
;
17605 #define _PWM11PRL0 0x01
17606 #define _PWM11PRL1 0x02
17607 #define _PWM11PRL2 0x04
17608 #define _PWM11PRL3 0x08
17609 #define _PWM11PRL4 0x10
17610 #define _PWM11PRL5 0x20
17611 #define _PWM11PRL6 0x40
17612 #define _PWM11PRL7 0x80
17614 //==============================================================================
17617 //==============================================================================
17620 extern __at(0x0DB6) __sfr PWM11PRH
;
17624 unsigned PWM11PRH0
: 1;
17625 unsigned PWM11PRH1
: 1;
17626 unsigned PWM11PRH2
: 1;
17627 unsigned PWM11PRH3
: 1;
17628 unsigned PWM11PRH4
: 1;
17629 unsigned PWM11PRH5
: 1;
17630 unsigned PWM11PRH6
: 1;
17631 unsigned PWM11PRH7
: 1;
17632 } __PWM11PRHbits_t
;
17634 extern __at(0x0DB6) volatile __PWM11PRHbits_t PWM11PRHbits
;
17636 #define _PWM11PRH0 0x01
17637 #define _PWM11PRH1 0x02
17638 #define _PWM11PRH2 0x04
17639 #define _PWM11PRH3 0x08
17640 #define _PWM11PRH4 0x10
17641 #define _PWM11PRH5 0x20
17642 #define _PWM11PRH6 0x40
17643 #define _PWM11PRH7 0x80
17645 //==============================================================================
17647 extern __at(0x0DB7) __sfr PWM11OF
;
17649 //==============================================================================
17652 extern __at(0x0DB7) __sfr PWM11OFL
;
17656 unsigned PWM11OFL0
: 1;
17657 unsigned PWM11OFL1
: 1;
17658 unsigned PWM11OFL2
: 1;
17659 unsigned PWM11OFL3
: 1;
17660 unsigned PWM11OFL4
: 1;
17661 unsigned PWM11OFL5
: 1;
17662 unsigned PWM11OFL6
: 1;
17663 unsigned PWM11OFL7
: 1;
17664 } __PWM11OFLbits_t
;
17666 extern __at(0x0DB7) volatile __PWM11OFLbits_t PWM11OFLbits
;
17668 #define _PWM11OFL0 0x01
17669 #define _PWM11OFL1 0x02
17670 #define _PWM11OFL2 0x04
17671 #define _PWM11OFL3 0x08
17672 #define _PWM11OFL4 0x10
17673 #define _PWM11OFL5 0x20
17674 #define _PWM11OFL6 0x40
17675 #define _PWM11OFL7 0x80
17677 //==============================================================================
17680 //==============================================================================
17683 extern __at(0x0DB8) __sfr PWM11OFH
;
17687 unsigned PWM11OFH0
: 1;
17688 unsigned PWM11OFH1
: 1;
17689 unsigned PWM11OFH2
: 1;
17690 unsigned PWM11OFH3
: 1;
17691 unsigned PWM11OFH4
: 1;
17692 unsigned PWM11OFH5
: 1;
17693 unsigned PWM11OFH6
: 1;
17694 unsigned PWM11OFH7
: 1;
17695 } __PWM11OFHbits_t
;
17697 extern __at(0x0DB8) volatile __PWM11OFHbits_t PWM11OFHbits
;
17699 #define _PWM11OFH0 0x01
17700 #define _PWM11OFH1 0x02
17701 #define _PWM11OFH2 0x04
17702 #define _PWM11OFH3 0x08
17703 #define _PWM11OFH4 0x10
17704 #define _PWM11OFH5 0x20
17705 #define _PWM11OFH6 0x40
17706 #define _PWM11OFH7 0x80
17708 //==============================================================================
17710 extern __at(0x0DB9) __sfr PWM11TMR
;
17712 //==============================================================================
17715 extern __at(0x0DB9) __sfr PWM11TMRL
;
17719 unsigned PWM11TMRL0
: 1;
17720 unsigned PWM11TMRL1
: 1;
17721 unsigned PWM11TMRL2
: 1;
17722 unsigned PWM11TMRL3
: 1;
17723 unsigned PWM11TMRL4
: 1;
17724 unsigned PWM11TMRL5
: 1;
17725 unsigned PWM11TMRL6
: 1;
17726 unsigned PWM11TMRL7
: 1;
17727 } __PWM11TMRLbits_t
;
17729 extern __at(0x0DB9) volatile __PWM11TMRLbits_t PWM11TMRLbits
;
17731 #define _PWM11TMRL0 0x01
17732 #define _PWM11TMRL1 0x02
17733 #define _PWM11TMRL2 0x04
17734 #define _PWM11TMRL3 0x08
17735 #define _PWM11TMRL4 0x10
17736 #define _PWM11TMRL5 0x20
17737 #define _PWM11TMRL6 0x40
17738 #define _PWM11TMRL7 0x80
17740 //==============================================================================
17743 //==============================================================================
17746 extern __at(0x0DBA) __sfr PWM11TMRH
;
17750 unsigned PWM11TMRH0
: 1;
17751 unsigned PWM11TMRH1
: 1;
17752 unsigned PWM11TMRH2
: 1;
17753 unsigned PWM11TMRH3
: 1;
17754 unsigned PWM11TMRH4
: 1;
17755 unsigned PWM11TMRH5
: 1;
17756 unsigned PWM11TMRH6
: 1;
17757 unsigned PWM11TMRH7
: 1;
17758 } __PWM11TMRHbits_t
;
17760 extern __at(0x0DBA) volatile __PWM11TMRHbits_t PWM11TMRHbits
;
17762 #define _PWM11TMRH0 0x01
17763 #define _PWM11TMRH1 0x02
17764 #define _PWM11TMRH2 0x04
17765 #define _PWM11TMRH3 0x08
17766 #define _PWM11TMRH4 0x10
17767 #define _PWM11TMRH5 0x20
17768 #define _PWM11TMRH6 0x40
17769 #define _PWM11TMRH7 0x80
17771 //==============================================================================
17774 //==============================================================================
17777 extern __at(0x0DBB) __sfr PWM11CON
;
17785 unsigned PWM11MODE0
: 1;
17786 unsigned PWM11MODE1
: 1;
17797 unsigned MODE0
: 1;
17798 unsigned MODE1
: 1;
17799 unsigned PWM11POL
: 1;
17800 unsigned PWM11OUT
: 1;
17802 unsigned PWM11EN
: 1;
17808 unsigned PWM11MODE
: 2;
17818 } __PWM11CONbits_t
;
17820 extern __at(0x0DBB) volatile __PWM11CONbits_t PWM11CONbits
;
17822 #define _PWM11CON_PWM11MODE0 0x04
17823 #define _PWM11CON_MODE0 0x04
17824 #define _PWM11CON_PWM11MODE1 0x08
17825 #define _PWM11CON_MODE1 0x08
17826 #define _PWM11CON_POL 0x10
17827 #define _PWM11CON_PWM11POL 0x10
17828 #define _PWM11CON_OUT 0x20
17829 #define _PWM11CON_PWM11OUT 0x20
17830 #define _PWM11CON_EN 0x80
17831 #define _PWM11CON_PWM11EN 0x80
17833 //==============================================================================
17836 //==============================================================================
17837 // PWM11INTCON Bits
17839 extern __at(0x0DBC) __sfr PWM11INTCON
;
17857 unsigned PWM11PRIE
: 1;
17858 unsigned PWM11DCIE
: 1;
17859 unsigned PWM11PHIE
: 1;
17860 unsigned PWM11OFIE
: 1;
17866 } __PWM11INTCONbits_t
;
17868 extern __at(0x0DBC) volatile __PWM11INTCONbits_t PWM11INTCONbits
;
17870 #define _PWM11INTCON_PRIE 0x01
17871 #define _PWM11INTCON_PWM11PRIE 0x01
17872 #define _PWM11INTCON_DCIE 0x02
17873 #define _PWM11INTCON_PWM11DCIE 0x02
17874 #define _PWM11INTCON_PHIE 0x04
17875 #define _PWM11INTCON_PWM11PHIE 0x04
17876 #define _PWM11INTCON_OFIE 0x08
17877 #define _PWM11INTCON_PWM11OFIE 0x08
17879 //==============================================================================
17882 //==============================================================================
17885 extern __at(0x0DBC) __sfr PWM11INTE
;
17903 unsigned PWM11PRIE
: 1;
17904 unsigned PWM11DCIE
: 1;
17905 unsigned PWM11PHIE
: 1;
17906 unsigned PWM11OFIE
: 1;
17912 } __PWM11INTEbits_t
;
17914 extern __at(0x0DBC) volatile __PWM11INTEbits_t PWM11INTEbits
;
17916 #define _PWM11INTE_PRIE 0x01
17917 #define _PWM11INTE_PWM11PRIE 0x01
17918 #define _PWM11INTE_DCIE 0x02
17919 #define _PWM11INTE_PWM11DCIE 0x02
17920 #define _PWM11INTE_PHIE 0x04
17921 #define _PWM11INTE_PWM11PHIE 0x04
17922 #define _PWM11INTE_OFIE 0x08
17923 #define _PWM11INTE_PWM11OFIE 0x08
17925 //==============================================================================
17928 //==============================================================================
17931 extern __at(0x0DBD) __sfr PWM11INTF
;
17949 unsigned PWM11PRIF
: 1;
17950 unsigned PWM11DCIF
: 1;
17951 unsigned PWM11PHIF
: 1;
17952 unsigned PWM11OFIF
: 1;
17958 } __PWM11INTFbits_t
;
17960 extern __at(0x0DBD) volatile __PWM11INTFbits_t PWM11INTFbits
;
17962 #define _PWM11INTF_PRIF 0x01
17963 #define _PWM11INTF_PWM11PRIF 0x01
17964 #define _PWM11INTF_DCIF 0x02
17965 #define _PWM11INTF_PWM11DCIF 0x02
17966 #define _PWM11INTF_PHIF 0x04
17967 #define _PWM11INTF_PWM11PHIF 0x04
17968 #define _PWM11INTF_OFIF 0x08
17969 #define _PWM11INTF_PWM11OFIF 0x08
17971 //==============================================================================
17974 //==============================================================================
17975 // PWM11INTFLG Bits
17977 extern __at(0x0DBD) __sfr PWM11INTFLG
;
17995 unsigned PWM11PRIF
: 1;
17996 unsigned PWM11DCIF
: 1;
17997 unsigned PWM11PHIF
: 1;
17998 unsigned PWM11OFIF
: 1;
18004 } __PWM11INTFLGbits_t
;
18006 extern __at(0x0DBD) volatile __PWM11INTFLGbits_t PWM11INTFLGbits
;
18008 #define _PWM11INTFLG_PRIF 0x01
18009 #define _PWM11INTFLG_PWM11PRIF 0x01
18010 #define _PWM11INTFLG_DCIF 0x02
18011 #define _PWM11INTFLG_PWM11DCIF 0x02
18012 #define _PWM11INTFLG_PHIF 0x04
18013 #define _PWM11INTFLG_PWM11PHIF 0x04
18014 #define _PWM11INTFLG_OFIF 0x08
18015 #define _PWM11INTFLG_PWM11OFIF 0x08
18017 //==============================================================================
18020 //==============================================================================
18021 // PWM11CLKCON Bits
18023 extern __at(0x0DBE) __sfr PWM11CLKCON
;
18029 unsigned PWM11CS0
: 1;
18030 unsigned PWM11CS1
: 1;
18031 unsigned PWM11CS2
: 1;
18033 unsigned PWM11PS0
: 1;
18034 unsigned PWM11PS1
: 1;
18035 unsigned PWM11PS2
: 1;
18053 unsigned PWM11CS
: 3;
18073 unsigned PWM11PS
: 3;
18076 } __PWM11CLKCONbits_t
;
18078 extern __at(0x0DBE) volatile __PWM11CLKCONbits_t PWM11CLKCONbits
;
18080 #define _PWM11CLKCON_PWM11CS0 0x01
18081 #define _PWM11CLKCON_CS0 0x01
18082 #define _PWM11CLKCON_PWM11CS1 0x02
18083 #define _PWM11CLKCON_CS1 0x02
18084 #define _PWM11CLKCON_PWM11CS2 0x04
18085 #define _PWM11CLKCON_CS2 0x04
18086 #define _PWM11CLKCON_PWM11PS0 0x10
18087 #define _PWM11CLKCON_PS0 0x10
18088 #define _PWM11CLKCON_PWM11PS1 0x20
18089 #define _PWM11CLKCON_PS1 0x20
18090 #define _PWM11CLKCON_PWM11PS2 0x40
18091 #define _PWM11CLKCON_PS2 0x40
18093 //==============================================================================
18096 //==============================================================================
18099 extern __at(0x0DBF) __sfr PWM11LDCON
;
18105 unsigned PWM11LDS0
: 1;
18106 unsigned PWM11LDS1
: 1;
18123 unsigned PWM11LDM
: 1;
18124 unsigned PWM11LD
: 1;
18129 unsigned PWM11LDS
: 2;
18138 } __PWM11LDCONbits_t
;
18140 extern __at(0x0DBF) volatile __PWM11LDCONbits_t PWM11LDCONbits
;
18142 #define _PWM11LDCON_PWM11LDS0 0x01
18143 #define _PWM11LDCON_LDS0 0x01
18144 #define _PWM11LDCON_PWM11LDS1 0x02
18145 #define _PWM11LDCON_LDS1 0x02
18146 #define _PWM11LDCON_LDT 0x40
18147 #define _PWM11LDCON_PWM11LDM 0x40
18148 #define _PWM11LDCON_LDA 0x80
18149 #define _PWM11LDCON_PWM11LD 0x80
18151 //==============================================================================
18154 //==============================================================================
18157 extern __at(0x0DC0) __sfr PWM11OFCON
;
18163 unsigned PWM11OFS0
: 1;
18164 unsigned PWM11OFS1
: 1;
18168 unsigned PWM11OFM0
: 1;
18169 unsigned PWM11OFM1
: 1;
18179 unsigned PWM11OFMC
: 1;
18187 unsigned PWM11OFS
: 2;
18200 unsigned PWM11OFM
: 2;
18210 } __PWM11OFCONbits_t
;
18212 extern __at(0x0DC0) volatile __PWM11OFCONbits_t PWM11OFCONbits
;
18214 #define _PWM11OFCON_PWM11OFS0 0x01
18215 #define _PWM11OFCON_OFS0 0x01
18216 #define _PWM11OFCON_PWM11OFS1 0x02
18217 #define _PWM11OFCON_OFS1 0x02
18218 #define _PWM11OFCON_OFO 0x10
18219 #define _PWM11OFCON_PWM11OFMC 0x10
18220 #define _PWM11OFCON_PWM11OFM0 0x20
18221 #define _PWM11OFCON_OFM0 0x20
18222 #define _PWM11OFCON_PWM11OFM1 0x40
18223 #define _PWM11OFCON_OFM1 0x40
18225 //==============================================================================
18228 //==============================================================================
18231 extern __at(0x0E0C) __sfr PPSLOCK
;
18235 unsigned PPSLOCKED
: 1;
18245 extern __at(0x0E0C) volatile __PPSLOCKbits_t PPSLOCKbits
;
18247 #define _PPSLOCKED 0x01
18249 //==============================================================================
18251 extern __at(0x0E0D) __sfr INTPPS
;
18252 extern __at(0x0E0E) __sfr T0CKIPPS
;
18253 extern __at(0x0E0F) __sfr T1CKIPPS
;
18254 extern __at(0x0E10) __sfr T1GPPS
;
18255 extern __at(0x0E11) __sfr T3CKIPPS
;
18256 extern __at(0x0E12) __sfr T3GPPS
;
18257 extern __at(0x0E13) __sfr T5CKIPPS
;
18258 extern __at(0x0E14) __sfr T5GPPS
;
18259 extern __at(0x0E15) __sfr T2CKIPPS
;
18260 extern __at(0x0E16) __sfr T4CKIPPS
;
18261 extern __at(0x0E17) __sfr T6CKIPPS
;
18262 extern __at(0x0E18) __sfr T8CKIPPS
;
18263 extern __at(0x0E19) __sfr CCP1PPS
;
18264 extern __at(0x0E1A) __sfr CCP2PPS
;
18265 extern __at(0x0E1B) __sfr CCP7PPS
;
18266 extern __at(0x0E1D) __sfr COG1INPPS
;
18267 extern __at(0x0E1E) __sfr COG2INPPS
;
18268 extern __at(0x0E1F) __sfr COG3INPPS
;
18269 extern __at(0x0E21) __sfr MD1CLPPS
;
18270 extern __at(0x0E22) __sfr MD1CHPPS
;
18271 extern __at(0x0E23) __sfr MD1MODPPS
;
18272 extern __at(0x0E24) __sfr MD2CLPPS
;
18273 extern __at(0x0E25) __sfr MD2CHPPS
;
18274 extern __at(0x0E26) __sfr MD2MODPPS
;
18275 extern __at(0x0E27) __sfr MD3CLPPS
;
18276 extern __at(0x0E28) __sfr MD3CHPPS
;
18277 extern __at(0x0E29) __sfr MD3MODPPS
;
18278 extern __at(0x0E2D) __sfr PRG1RPPS
;
18279 extern __at(0x0E2E) __sfr PRG1FPPS
;
18280 extern __at(0x0E2F) __sfr PRG2RPPS
;
18281 extern __at(0x0E30) __sfr PRG2FPPS
;
18282 extern __at(0x0E31) __sfr PRG3RPPS
;
18283 extern __at(0x0E32) __sfr PRG3FPPS
;
18284 extern __at(0x0E35) __sfr CLCIN0PPS
;
18285 extern __at(0x0E36) __sfr CLCIN1PPS
;
18286 extern __at(0x0E37) __sfr CLCIN2PPS
;
18287 extern __at(0x0E38) __sfr CLCIN3PPS
;
18288 extern __at(0x0E39) __sfr ADCACTPPS
;
18289 extern __at(0x0E3A) __sfr SSPCLKPPS
;
18290 extern __at(0x0E3B) __sfr SSPDATPPS
;
18291 extern __at(0x0E3C) __sfr SSPSSPPS
;
18292 extern __at(0x0E3D) __sfr RXPPS
;
18293 extern __at(0x0E3E) __sfr CKPPS
;
18294 extern __at(0x0E90) __sfr RA0PPS
;
18295 extern __at(0x0E91) __sfr RA1PPS
;
18296 extern __at(0x0E92) __sfr RA2PPS
;
18297 extern __at(0x0E93) __sfr RA3PPS
;
18298 extern __at(0x0E94) __sfr RA4PPS
;
18299 extern __at(0x0E95) __sfr RA5PPS
;
18300 extern __at(0x0E96) __sfr RA6PPS
;
18301 extern __at(0x0E97) __sfr RA7PPS
;
18302 extern __at(0x0E98) __sfr RB0PPS
;
18303 extern __at(0x0E99) __sfr RB1PPS
;
18304 extern __at(0x0E9A) __sfr RB2PPS
;
18305 extern __at(0x0E9B) __sfr RB3PPS
;
18306 extern __at(0x0E9C) __sfr RB4PPS
;
18307 extern __at(0x0E9D) __sfr RB5PPS
;
18308 extern __at(0x0E9E) __sfr RB6PPS
;
18309 extern __at(0x0E9F) __sfr RB7PPS
;
18310 extern __at(0x0EA0) __sfr RC0PPS
;
18311 extern __at(0x0EA1) __sfr RC1PPS
;
18312 extern __at(0x0EA2) __sfr RC2PPS
;
18313 extern __at(0x0EA3) __sfr RC3PPS
;
18314 extern __at(0x0EA4) __sfr RC4PPS
;
18315 extern __at(0x0EA5) __sfr RC5PPS
;
18316 extern __at(0x0EA6) __sfr RC6PPS
;
18317 extern __at(0x0EA7) __sfr RC7PPS
;
18319 //==============================================================================
18322 extern __at(0x0F0F) __sfr CLCDATA
;
18326 unsigned MCLC1OUT
: 1;
18327 unsigned MCLC2OUT
: 1;
18328 unsigned MCLC3OUT
: 1;
18329 unsigned MLC4OUT
: 1;
18336 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
18338 #define _MCLC1OUT 0x01
18339 #define _MCLC2OUT 0x02
18340 #define _MCLC3OUT 0x04
18341 #define _MLC4OUT 0x08
18343 //==============================================================================
18346 //==============================================================================
18349 extern __at(0x0F10) __sfr CLC1CON
;
18355 unsigned LC1MODE0
: 1;
18356 unsigned LC1MODE1
: 1;
18357 unsigned LC1MODE2
: 1;
18358 unsigned LC1INTN
: 1;
18359 unsigned LC1INTP
: 1;
18360 unsigned LC1OUT
: 1;
18362 unsigned LC1EN
: 1;
18367 unsigned MODE0
: 1;
18368 unsigned MODE1
: 1;
18369 unsigned MODE2
: 1;
18385 unsigned LC1MODE
: 3;
18390 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
18392 #define _CLC1CON_LC1MODE0 0x01
18393 #define _CLC1CON_MODE0 0x01
18394 #define _CLC1CON_LC1MODE1 0x02
18395 #define _CLC1CON_MODE1 0x02
18396 #define _CLC1CON_LC1MODE2 0x04
18397 #define _CLC1CON_MODE2 0x04
18398 #define _CLC1CON_LC1INTN 0x08
18399 #define _CLC1CON_INTN 0x08
18400 #define _CLC1CON_LC1INTP 0x10
18401 #define _CLC1CON_INTP 0x10
18402 #define _CLC1CON_LC1OUT 0x20
18403 #define _CLC1CON_OUT 0x20
18404 #define _CLC1CON_LC1EN 0x80
18405 #define _CLC1CON_EN 0x80
18407 //==============================================================================
18410 //==============================================================================
18413 extern __at(0x0F11) __sfr CLC1POL
;
18419 unsigned LC1G1POL
: 1;
18420 unsigned LC1G2POL
: 1;
18421 unsigned LC1G3POL
: 1;
18422 unsigned LC1G4POL
: 1;
18426 unsigned LC1POL
: 1;
18431 unsigned G1POL
: 1;
18432 unsigned G2POL
: 1;
18433 unsigned G3POL
: 1;
18434 unsigned G4POL
: 1;
18442 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
18444 #define _LC1G1POL 0x01
18445 #define _G1POL 0x01
18446 #define _LC1G2POL 0x02
18447 #define _G2POL 0x02
18448 #define _LC1G3POL 0x04
18449 #define _G3POL 0x04
18450 #define _LC1G4POL 0x08
18451 #define _G4POL 0x08
18452 #define _LC1POL 0x80
18455 //==============================================================================
18458 //==============================================================================
18461 extern __at(0x0F12) __sfr CLC1SEL0
;
18467 unsigned LC1D1S0
: 1;
18468 unsigned LC1D1S1
: 1;
18469 unsigned LC1D1S2
: 1;
18470 unsigned LC1D1S3
: 1;
18471 unsigned LC1D1S4
: 1;
18472 unsigned LC1D1S5
: 1;
18491 unsigned LC1D1S
: 6;
18500 } __CLC1SEL0bits_t
;
18502 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
18504 #define _LC1D1S0 0x01
18506 #define _LC1D1S1 0x02
18508 #define _LC1D1S2 0x04
18510 #define _LC1D1S3 0x08
18512 #define _LC1D1S4 0x10
18514 #define _LC1D1S5 0x20
18517 //==============================================================================
18520 //==============================================================================
18523 extern __at(0x0F13) __sfr CLC1SEL1
;
18529 unsigned LC1D2S0
: 1;
18530 unsigned LC1D2S1
: 1;
18531 unsigned LC1D2S2
: 1;
18532 unsigned LC1D2S3
: 1;
18533 unsigned LC1D2S4
: 1;
18534 unsigned LC1D2S5
: 1;
18559 unsigned LC1D2S
: 6;
18562 } __CLC1SEL1bits_t
;
18564 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
18566 #define _LC1D2S0 0x01
18568 #define _LC1D2S1 0x02
18570 #define _LC1D2S2 0x04
18572 #define _LC1D2S3 0x08
18574 #define _LC1D2S4 0x10
18576 #define _LC1D2S5 0x20
18579 //==============================================================================
18582 //==============================================================================
18585 extern __at(0x0F14) __sfr CLC1SEL2
;
18591 unsigned LC1D3S0
: 1;
18592 unsigned LC1D3S1
: 1;
18593 unsigned LC1D3S2
: 1;
18594 unsigned LC1D3S3
: 1;
18595 unsigned LC1D3S4
: 1;
18596 unsigned LC1D3S5
: 1;
18615 unsigned LC1D3S
: 6;
18624 } __CLC1SEL2bits_t
;
18626 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
18628 #define _LC1D3S0 0x01
18630 #define _LC1D3S1 0x02
18632 #define _LC1D3S2 0x04
18634 #define _LC1D3S3 0x08
18636 #define _LC1D3S4 0x10
18638 #define _LC1D3S5 0x20
18641 //==============================================================================
18644 //==============================================================================
18647 extern __at(0x0F15) __sfr CLC1SEL3
;
18653 unsigned LC1D4S0
: 1;
18654 unsigned LC1D4S1
: 1;
18655 unsigned LC1D4S2
: 1;
18656 unsigned LC1D4S3
: 1;
18657 unsigned LC1D4S4
: 1;
18658 unsigned LC1D4S5
: 1;
18677 unsigned LC1D4S
: 6;
18686 } __CLC1SEL3bits_t
;
18688 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
18690 #define _LC1D4S0 0x01
18692 #define _LC1D4S1 0x02
18694 #define _LC1D4S2 0x04
18696 #define _LC1D4S3 0x08
18698 #define _LC1D4S4 0x10
18700 #define _LC1D4S5 0x20
18703 //==============================================================================
18706 //==============================================================================
18709 extern __at(0x0F16) __sfr CLC1GLS0
;
18715 unsigned LC1G1D1N
: 1;
18716 unsigned LC1G1D1T
: 1;
18717 unsigned LC1G1D2N
: 1;
18718 unsigned LC1G1D2T
: 1;
18719 unsigned LC1G1D3N
: 1;
18720 unsigned LC1G1D3T
: 1;
18721 unsigned LC1G1D4N
: 1;
18722 unsigned LC1G1D4T
: 1;
18736 } __CLC1GLS0bits_t
;
18738 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
18740 #define _LC1G1D1N 0x01
18742 #define _LC1G1D1T 0x02
18744 #define _LC1G1D2N 0x04
18746 #define _LC1G1D2T 0x08
18748 #define _LC1G1D3N 0x10
18750 #define _LC1G1D3T 0x20
18752 #define _LC1G1D4N 0x40
18754 #define _LC1G1D4T 0x80
18757 //==============================================================================
18760 //==============================================================================
18763 extern __at(0x0F17) __sfr CLC1GLS1
;
18769 unsigned LC1G2D1N
: 1;
18770 unsigned LC1G2D1T
: 1;
18771 unsigned LC1G2D2N
: 1;
18772 unsigned LC1G2D2T
: 1;
18773 unsigned LC1G2D3N
: 1;
18774 unsigned LC1G2D3T
: 1;
18775 unsigned LC1G2D4N
: 1;
18776 unsigned LC1G2D4T
: 1;
18790 } __CLC1GLS1bits_t
;
18792 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
18794 #define _CLC1GLS1_LC1G2D1N 0x01
18795 #define _CLC1GLS1_D1N 0x01
18796 #define _CLC1GLS1_LC1G2D1T 0x02
18797 #define _CLC1GLS1_D1T 0x02
18798 #define _CLC1GLS1_LC1G2D2N 0x04
18799 #define _CLC1GLS1_D2N 0x04
18800 #define _CLC1GLS1_LC1G2D2T 0x08
18801 #define _CLC1GLS1_D2T 0x08
18802 #define _CLC1GLS1_LC1G2D3N 0x10
18803 #define _CLC1GLS1_D3N 0x10
18804 #define _CLC1GLS1_LC1G2D3T 0x20
18805 #define _CLC1GLS1_D3T 0x20
18806 #define _CLC1GLS1_LC1G2D4N 0x40
18807 #define _CLC1GLS1_D4N 0x40
18808 #define _CLC1GLS1_LC1G2D4T 0x80
18809 #define _CLC1GLS1_D4T 0x80
18811 //==============================================================================
18814 //==============================================================================
18817 extern __at(0x0F18) __sfr CLC1GLS2
;
18823 unsigned LC1G3D1N
: 1;
18824 unsigned LC1G3D1T
: 1;
18825 unsigned LC1G3D2N
: 1;
18826 unsigned LC1G3D2T
: 1;
18827 unsigned LC1G3D3N
: 1;
18828 unsigned LC1G3D3T
: 1;
18829 unsigned LC1G3D4N
: 1;
18830 unsigned LC1G3D4T
: 1;
18844 } __CLC1GLS2bits_t
;
18846 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
18848 #define _CLC1GLS2_LC1G3D1N 0x01
18849 #define _CLC1GLS2_D1N 0x01
18850 #define _CLC1GLS2_LC1G3D1T 0x02
18851 #define _CLC1GLS2_D1T 0x02
18852 #define _CLC1GLS2_LC1G3D2N 0x04
18853 #define _CLC1GLS2_D2N 0x04
18854 #define _CLC1GLS2_LC1G3D2T 0x08
18855 #define _CLC1GLS2_D2T 0x08
18856 #define _CLC1GLS2_LC1G3D3N 0x10
18857 #define _CLC1GLS2_D3N 0x10
18858 #define _CLC1GLS2_LC1G3D3T 0x20
18859 #define _CLC1GLS2_D3T 0x20
18860 #define _CLC1GLS2_LC1G3D4N 0x40
18861 #define _CLC1GLS2_D4N 0x40
18862 #define _CLC1GLS2_LC1G3D4T 0x80
18863 #define _CLC1GLS2_D4T 0x80
18865 //==============================================================================
18868 //==============================================================================
18871 extern __at(0x0F19) __sfr CLC1GLS3
;
18877 unsigned LC1G4D1N
: 1;
18878 unsigned LC1G4D1T
: 1;
18879 unsigned LC1G4D2N
: 1;
18880 unsigned LC1G4D2T
: 1;
18881 unsigned LC1G4D3N
: 1;
18882 unsigned LC1G4D3T
: 1;
18883 unsigned LC1G4D4N
: 1;
18884 unsigned LC1G4D4T
: 1;
18889 unsigned G4D1N
: 1;
18890 unsigned G4D1T
: 1;
18891 unsigned G4D2N
: 1;
18892 unsigned G4D2T
: 1;
18893 unsigned G4D3N
: 1;
18894 unsigned G4D3T
: 1;
18895 unsigned G4D4N
: 1;
18896 unsigned G4D4T
: 1;
18898 } __CLC1GLS3bits_t
;
18900 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
18902 #define _LC1G4D1N 0x01
18903 #define _G4D1N 0x01
18904 #define _LC1G4D1T 0x02
18905 #define _G4D1T 0x02
18906 #define _LC1G4D2N 0x04
18907 #define _G4D2N 0x04
18908 #define _LC1G4D2T 0x08
18909 #define _G4D2T 0x08
18910 #define _LC1G4D3N 0x10
18911 #define _G4D3N 0x10
18912 #define _LC1G4D3T 0x20
18913 #define _G4D3T 0x20
18914 #define _LC1G4D4N 0x40
18915 #define _G4D4N 0x40
18916 #define _LC1G4D4T 0x80
18917 #define _G4D4T 0x80
18919 //==============================================================================
18922 //==============================================================================
18925 extern __at(0x0F1A) __sfr CLC2CON
;
18931 unsigned LC2MODE0
: 1;
18932 unsigned LC2MODE1
: 1;
18933 unsigned LC2MODE2
: 1;
18934 unsigned LC2INTN
: 1;
18935 unsigned LC2INTP
: 1;
18936 unsigned LC2OUT
: 1;
18938 unsigned LC2EN
: 1;
18943 unsigned MODE0
: 1;
18944 unsigned MODE1
: 1;
18945 unsigned MODE2
: 1;
18955 unsigned LC2MODE
: 3;
18966 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
18968 #define _CLC2CON_LC2MODE0 0x01
18969 #define _CLC2CON_MODE0 0x01
18970 #define _CLC2CON_LC2MODE1 0x02
18971 #define _CLC2CON_MODE1 0x02
18972 #define _CLC2CON_LC2MODE2 0x04
18973 #define _CLC2CON_MODE2 0x04
18974 #define _CLC2CON_LC2INTN 0x08
18975 #define _CLC2CON_INTN 0x08
18976 #define _CLC2CON_LC2INTP 0x10
18977 #define _CLC2CON_INTP 0x10
18978 #define _CLC2CON_LC2OUT 0x20
18979 #define _CLC2CON_OUT 0x20
18980 #define _CLC2CON_LC2EN 0x80
18981 #define _CLC2CON_EN 0x80
18983 //==============================================================================
18986 //==============================================================================
18989 extern __at(0x0F1B) __sfr CLC2POL
;
18995 unsigned LC2G1POL
: 1;
18996 unsigned LC2G2POL
: 1;
18997 unsigned LC2G3POL
: 1;
18998 unsigned LC2G4POL
: 1;
19002 unsigned LC2POL
: 1;
19007 unsigned G1POL
: 1;
19008 unsigned G2POL
: 1;
19009 unsigned G3POL
: 1;
19010 unsigned G4POL
: 1;
19018 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
19020 #define _CLC2POL_LC2G1POL 0x01
19021 #define _CLC2POL_G1POL 0x01
19022 #define _CLC2POL_LC2G2POL 0x02
19023 #define _CLC2POL_G2POL 0x02
19024 #define _CLC2POL_LC2G3POL 0x04
19025 #define _CLC2POL_G3POL 0x04
19026 #define _CLC2POL_LC2G4POL 0x08
19027 #define _CLC2POL_G4POL 0x08
19028 #define _CLC2POL_LC2POL 0x80
19029 #define _CLC2POL_POL 0x80
19031 //==============================================================================
19034 //==============================================================================
19037 extern __at(0x0F1C) __sfr CLC2SEL0
;
19043 unsigned LC2D1S0
: 1;
19044 unsigned LC2D1S1
: 1;
19045 unsigned LC2D1S2
: 1;
19046 unsigned LC2D1S3
: 1;
19047 unsigned LC2D1S4
: 1;
19048 unsigned LC2D1S5
: 1;
19073 unsigned LC2D1S
: 6;
19076 } __CLC2SEL0bits_t
;
19078 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
19080 #define _CLC2SEL0_LC2D1S0 0x01
19081 #define _CLC2SEL0_D1S0 0x01
19082 #define _CLC2SEL0_LC2D1S1 0x02
19083 #define _CLC2SEL0_D1S1 0x02
19084 #define _CLC2SEL0_LC2D1S2 0x04
19085 #define _CLC2SEL0_D1S2 0x04
19086 #define _CLC2SEL0_LC2D1S3 0x08
19087 #define _CLC2SEL0_D1S3 0x08
19088 #define _CLC2SEL0_LC2D1S4 0x10
19089 #define _CLC2SEL0_D1S4 0x10
19090 #define _CLC2SEL0_LC2D1S5 0x20
19091 #define _CLC2SEL0_D1S5 0x20
19093 //==============================================================================
19096 //==============================================================================
19099 extern __at(0x0F1D) __sfr CLC2SEL1
;
19105 unsigned LC2D2S0
: 1;
19106 unsigned LC2D2S1
: 1;
19107 unsigned LC2D2S2
: 1;
19108 unsigned LC2D2S3
: 1;
19109 unsigned LC2D2S4
: 1;
19110 unsigned LC2D2S5
: 1;
19129 unsigned LC2D2S
: 6;
19138 } __CLC2SEL1bits_t
;
19140 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
19142 #define _CLC2SEL1_LC2D2S0 0x01
19143 #define _CLC2SEL1_D2S0 0x01
19144 #define _CLC2SEL1_LC2D2S1 0x02
19145 #define _CLC2SEL1_D2S1 0x02
19146 #define _CLC2SEL1_LC2D2S2 0x04
19147 #define _CLC2SEL1_D2S2 0x04
19148 #define _CLC2SEL1_LC2D2S3 0x08
19149 #define _CLC2SEL1_D2S3 0x08
19150 #define _CLC2SEL1_LC2D2S4 0x10
19151 #define _CLC2SEL1_D2S4 0x10
19152 #define _CLC2SEL1_LC2D2S5 0x20
19153 #define _CLC2SEL1_D2S5 0x20
19155 //==============================================================================
19158 //==============================================================================
19161 extern __at(0x0F1E) __sfr CLC2SEL2
;
19167 unsigned LC2D3S0
: 1;
19168 unsigned LC2D3S1
: 1;
19169 unsigned LC2D3S2
: 1;
19170 unsigned LC2D3S3
: 1;
19171 unsigned LC2D3S4
: 1;
19172 unsigned LC2D3S5
: 1;
19197 unsigned LC2D3S
: 6;
19200 } __CLC2SEL2bits_t
;
19202 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
19204 #define _CLC2SEL2_LC2D3S0 0x01
19205 #define _CLC2SEL2_D3S0 0x01
19206 #define _CLC2SEL2_LC2D3S1 0x02
19207 #define _CLC2SEL2_D3S1 0x02
19208 #define _CLC2SEL2_LC2D3S2 0x04
19209 #define _CLC2SEL2_D3S2 0x04
19210 #define _CLC2SEL2_LC2D3S3 0x08
19211 #define _CLC2SEL2_D3S3 0x08
19212 #define _CLC2SEL2_LC2D3S4 0x10
19213 #define _CLC2SEL2_D3S4 0x10
19214 #define _CLC2SEL2_LC2D3S5 0x20
19215 #define _CLC2SEL2_D3S5 0x20
19217 //==============================================================================
19220 //==============================================================================
19223 extern __at(0x0F1F) __sfr CLC2SEL3
;
19229 unsigned LC2D4S0
: 1;
19230 unsigned LC2D4S1
: 1;
19231 unsigned LC2D4S2
: 1;
19232 unsigned LC2D4S3
: 1;
19233 unsigned LC2D4S4
: 1;
19234 unsigned LC2D4S5
: 1;
19259 unsigned LC2D4S
: 6;
19262 } __CLC2SEL3bits_t
;
19264 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
19266 #define _CLC2SEL3_LC2D4S0 0x01
19267 #define _CLC2SEL3_D4S0 0x01
19268 #define _CLC2SEL3_LC2D4S1 0x02
19269 #define _CLC2SEL3_D4S1 0x02
19270 #define _CLC2SEL3_LC2D4S2 0x04
19271 #define _CLC2SEL3_D4S2 0x04
19272 #define _CLC2SEL3_LC2D4S3 0x08
19273 #define _CLC2SEL3_D4S3 0x08
19274 #define _CLC2SEL3_LC2D4S4 0x10
19275 #define _CLC2SEL3_D4S4 0x10
19276 #define _CLC2SEL3_LC2D4S5 0x20
19277 #define _CLC2SEL3_D4S5 0x20
19279 //==============================================================================
19282 //==============================================================================
19285 extern __at(0x0F20) __sfr CLC2GLS0
;
19291 unsigned LC2G1D1N
: 1;
19292 unsigned LC2G1D1T
: 1;
19293 unsigned LC2G1D2N
: 1;
19294 unsigned LC2G1D2T
: 1;
19295 unsigned LC2G1D3N
: 1;
19296 unsigned LC2G1D3T
: 1;
19297 unsigned LC2G1D4N
: 1;
19298 unsigned LC2G1D4T
: 1;
19312 } __CLC2GLS0bits_t
;
19314 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
19316 #define _CLC2GLS0_LC2G1D1N 0x01
19317 #define _CLC2GLS0_D1N 0x01
19318 #define _CLC2GLS0_LC2G1D1T 0x02
19319 #define _CLC2GLS0_D1T 0x02
19320 #define _CLC2GLS0_LC2G1D2N 0x04
19321 #define _CLC2GLS0_D2N 0x04
19322 #define _CLC2GLS0_LC2G1D2T 0x08
19323 #define _CLC2GLS0_D2T 0x08
19324 #define _CLC2GLS0_LC2G1D3N 0x10
19325 #define _CLC2GLS0_D3N 0x10
19326 #define _CLC2GLS0_LC2G1D3T 0x20
19327 #define _CLC2GLS0_D3T 0x20
19328 #define _CLC2GLS0_LC2G1D4N 0x40
19329 #define _CLC2GLS0_D4N 0x40
19330 #define _CLC2GLS0_LC2G1D4T 0x80
19331 #define _CLC2GLS0_D4T 0x80
19333 //==============================================================================
19336 //==============================================================================
19339 extern __at(0x0F21) __sfr CLC2GLS1
;
19345 unsigned LC2G2D1N
: 1;
19346 unsigned LC2G2D1T
: 1;
19347 unsigned LC2G2D2N
: 1;
19348 unsigned LC2G2D2T
: 1;
19349 unsigned LC2G2D3N
: 1;
19350 unsigned LC2G2D3T
: 1;
19351 unsigned LC2G2D4N
: 1;
19352 unsigned LC2G2D4T
: 1;
19366 } __CLC2GLS1bits_t
;
19368 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
19370 #define _CLC2GLS1_LC2G2D1N 0x01
19371 #define _CLC2GLS1_D1N 0x01
19372 #define _CLC2GLS1_LC2G2D1T 0x02
19373 #define _CLC2GLS1_D1T 0x02
19374 #define _CLC2GLS1_LC2G2D2N 0x04
19375 #define _CLC2GLS1_D2N 0x04
19376 #define _CLC2GLS1_LC2G2D2T 0x08
19377 #define _CLC2GLS1_D2T 0x08
19378 #define _CLC2GLS1_LC2G2D3N 0x10
19379 #define _CLC2GLS1_D3N 0x10
19380 #define _CLC2GLS1_LC2G2D3T 0x20
19381 #define _CLC2GLS1_D3T 0x20
19382 #define _CLC2GLS1_LC2G2D4N 0x40
19383 #define _CLC2GLS1_D4N 0x40
19384 #define _CLC2GLS1_LC2G2D4T 0x80
19385 #define _CLC2GLS1_D4T 0x80
19387 //==============================================================================
19390 //==============================================================================
19393 extern __at(0x0F22) __sfr CLC2GLS2
;
19399 unsigned LC2G3D1N
: 1;
19400 unsigned LC2G3D1T
: 1;
19401 unsigned LC2G3D2N
: 1;
19402 unsigned LC2G3D2T
: 1;
19403 unsigned LC2G3D3N
: 1;
19404 unsigned LC2G3D3T
: 1;
19405 unsigned LC2G3D4N
: 1;
19406 unsigned LC2G3D4T
: 1;
19420 } __CLC2GLS2bits_t
;
19422 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
19424 #define _CLC2GLS2_LC2G3D1N 0x01
19425 #define _CLC2GLS2_D1N 0x01
19426 #define _CLC2GLS2_LC2G3D1T 0x02
19427 #define _CLC2GLS2_D1T 0x02
19428 #define _CLC2GLS2_LC2G3D2N 0x04
19429 #define _CLC2GLS2_D2N 0x04
19430 #define _CLC2GLS2_LC2G3D2T 0x08
19431 #define _CLC2GLS2_D2T 0x08
19432 #define _CLC2GLS2_LC2G3D3N 0x10
19433 #define _CLC2GLS2_D3N 0x10
19434 #define _CLC2GLS2_LC2G3D3T 0x20
19435 #define _CLC2GLS2_D3T 0x20
19436 #define _CLC2GLS2_LC2G3D4N 0x40
19437 #define _CLC2GLS2_D4N 0x40
19438 #define _CLC2GLS2_LC2G3D4T 0x80
19439 #define _CLC2GLS2_D4T 0x80
19441 //==============================================================================
19444 //==============================================================================
19447 extern __at(0x0F23) __sfr CLC2GLS3
;
19453 unsigned LC2G4D1N
: 1;
19454 unsigned LC2G4D1T
: 1;
19455 unsigned LC2G4D2N
: 1;
19456 unsigned LC2G4D2T
: 1;
19457 unsigned LC2G4D3N
: 1;
19458 unsigned LC2G4D3T
: 1;
19459 unsigned LC2G4D4N
: 1;
19460 unsigned LC2G4D4T
: 1;
19465 unsigned G4D1N
: 1;
19466 unsigned G4D1T
: 1;
19467 unsigned G4D2N
: 1;
19468 unsigned G4D2T
: 1;
19469 unsigned G4D3N
: 1;
19470 unsigned G4D3T
: 1;
19471 unsigned G4D4N
: 1;
19472 unsigned G4D4T
: 1;
19474 } __CLC2GLS3bits_t
;
19476 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
19478 #define _CLC2GLS3_LC2G4D1N 0x01
19479 #define _CLC2GLS3_G4D1N 0x01
19480 #define _CLC2GLS3_LC2G4D1T 0x02
19481 #define _CLC2GLS3_G4D1T 0x02
19482 #define _CLC2GLS3_LC2G4D2N 0x04
19483 #define _CLC2GLS3_G4D2N 0x04
19484 #define _CLC2GLS3_LC2G4D2T 0x08
19485 #define _CLC2GLS3_G4D2T 0x08
19486 #define _CLC2GLS3_LC2G4D3N 0x10
19487 #define _CLC2GLS3_G4D3N 0x10
19488 #define _CLC2GLS3_LC2G4D3T 0x20
19489 #define _CLC2GLS3_G4D3T 0x20
19490 #define _CLC2GLS3_LC2G4D4N 0x40
19491 #define _CLC2GLS3_G4D4N 0x40
19492 #define _CLC2GLS3_LC2G4D4T 0x80
19493 #define _CLC2GLS3_G4D4T 0x80
19495 //==============================================================================
19498 //==============================================================================
19501 extern __at(0x0F24) __sfr CLC3CON
;
19507 unsigned LC3MODE0
: 1;
19508 unsigned LC3MODE1
: 1;
19509 unsigned LC3MODE2
: 1;
19510 unsigned LC3INTN
: 1;
19511 unsigned LC3INTP
: 1;
19512 unsigned LC3OUT
: 1;
19514 unsigned LC3EN
: 1;
19519 unsigned MODE0
: 1;
19520 unsigned MODE1
: 1;
19521 unsigned MODE2
: 1;
19531 unsigned LC3MODE
: 3;
19542 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
19544 #define _CLC3CON_LC3MODE0 0x01
19545 #define _CLC3CON_MODE0 0x01
19546 #define _CLC3CON_LC3MODE1 0x02
19547 #define _CLC3CON_MODE1 0x02
19548 #define _CLC3CON_LC3MODE2 0x04
19549 #define _CLC3CON_MODE2 0x04
19550 #define _CLC3CON_LC3INTN 0x08
19551 #define _CLC3CON_INTN 0x08
19552 #define _CLC3CON_LC3INTP 0x10
19553 #define _CLC3CON_INTP 0x10
19554 #define _CLC3CON_LC3OUT 0x20
19555 #define _CLC3CON_OUT 0x20
19556 #define _CLC3CON_LC3EN 0x80
19557 #define _CLC3CON_EN 0x80
19559 //==============================================================================
19562 //==============================================================================
19565 extern __at(0x0F25) __sfr CLC3POL
;
19571 unsigned LC3G1POL
: 1;
19572 unsigned LC3G2POL
: 1;
19573 unsigned LC3G3POL
: 1;
19574 unsigned LC3G4POL
: 1;
19578 unsigned LC3POL
: 1;
19583 unsigned G1POL
: 1;
19584 unsigned G2POL
: 1;
19585 unsigned G3POL
: 1;
19586 unsigned G4POL
: 1;
19594 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
19596 #define _CLC3POL_LC3G1POL 0x01
19597 #define _CLC3POL_G1POL 0x01
19598 #define _CLC3POL_LC3G2POL 0x02
19599 #define _CLC3POL_G2POL 0x02
19600 #define _CLC3POL_LC3G3POL 0x04
19601 #define _CLC3POL_G3POL 0x04
19602 #define _CLC3POL_LC3G4POL 0x08
19603 #define _CLC3POL_G4POL 0x08
19604 #define _CLC3POL_LC3POL 0x80
19605 #define _CLC3POL_POL 0x80
19607 //==============================================================================
19610 //==============================================================================
19613 extern __at(0x0F26) __sfr CLC3SEL0
;
19619 unsigned LC3D1S0
: 1;
19620 unsigned LC3D1S1
: 1;
19621 unsigned LC3D1S2
: 1;
19622 unsigned LC3D1S3
: 1;
19623 unsigned LC3D1S4
: 1;
19624 unsigned LC3D1S5
: 1;
19643 unsigned LC3D1S
: 6;
19652 } __CLC3SEL0bits_t
;
19654 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
19656 #define _CLC3SEL0_LC3D1S0 0x01
19657 #define _CLC3SEL0_D1S0 0x01
19658 #define _CLC3SEL0_LC3D1S1 0x02
19659 #define _CLC3SEL0_D1S1 0x02
19660 #define _CLC3SEL0_LC3D1S2 0x04
19661 #define _CLC3SEL0_D1S2 0x04
19662 #define _CLC3SEL0_LC3D1S3 0x08
19663 #define _CLC3SEL0_D1S3 0x08
19664 #define _CLC3SEL0_LC3D1S4 0x10
19665 #define _CLC3SEL0_D1S4 0x10
19666 #define _CLC3SEL0_LC3D1S5 0x20
19667 #define _CLC3SEL0_D1S5 0x20
19669 //==============================================================================
19672 //==============================================================================
19675 extern __at(0x0F27) __sfr CLC3SEL1
;
19681 unsigned LC3D2S0
: 1;
19682 unsigned LC3D2S1
: 1;
19683 unsigned LC3D2S2
: 1;
19684 unsigned LC3D2S3
: 1;
19685 unsigned LC3D2S4
: 1;
19686 unsigned LC3D2S5
: 1;
19711 unsigned LC3D2S
: 6;
19714 } __CLC3SEL1bits_t
;
19716 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
19718 #define _CLC3SEL1_LC3D2S0 0x01
19719 #define _CLC3SEL1_D2S0 0x01
19720 #define _CLC3SEL1_LC3D2S1 0x02
19721 #define _CLC3SEL1_D2S1 0x02
19722 #define _CLC3SEL1_LC3D2S2 0x04
19723 #define _CLC3SEL1_D2S2 0x04
19724 #define _CLC3SEL1_LC3D2S3 0x08
19725 #define _CLC3SEL1_D2S3 0x08
19726 #define _CLC3SEL1_LC3D2S4 0x10
19727 #define _CLC3SEL1_D2S4 0x10
19728 #define _CLC3SEL1_LC3D2S5 0x20
19729 #define _CLC3SEL1_D2S5 0x20
19731 //==============================================================================
19734 //==============================================================================
19737 extern __at(0x0F28) __sfr CLC3SEL2
;
19743 unsigned LC3D3S0
: 1;
19744 unsigned LC3D3S1
: 1;
19745 unsigned LC3D3S2
: 1;
19746 unsigned LC3D3S3
: 1;
19747 unsigned LC3D3S4
: 1;
19748 unsigned LC3D3S5
: 1;
19767 unsigned LC3D3S
: 6;
19776 } __CLC3SEL2bits_t
;
19778 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
19780 #define _CLC3SEL2_LC3D3S0 0x01
19781 #define _CLC3SEL2_D3S0 0x01
19782 #define _CLC3SEL2_LC3D3S1 0x02
19783 #define _CLC3SEL2_D3S1 0x02
19784 #define _CLC3SEL2_LC3D3S2 0x04
19785 #define _CLC3SEL2_D3S2 0x04
19786 #define _CLC3SEL2_LC3D3S3 0x08
19787 #define _CLC3SEL2_D3S3 0x08
19788 #define _CLC3SEL2_LC3D3S4 0x10
19789 #define _CLC3SEL2_D3S4 0x10
19790 #define _CLC3SEL2_LC3D3S5 0x20
19791 #define _CLC3SEL2_D3S5 0x20
19793 //==============================================================================
19796 //==============================================================================
19799 extern __at(0x0F29) __sfr CLC3SEL3
;
19805 unsigned LC3D4S0
: 1;
19806 unsigned LC3D4S1
: 1;
19807 unsigned LC3D4S2
: 1;
19808 unsigned LC3D4S3
: 1;
19809 unsigned LC3D4S4
: 1;
19810 unsigned LC3D4S5
: 1;
19829 unsigned LC3D4S
: 6;
19838 } __CLC3SEL3bits_t
;
19840 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
19842 #define _CLC3SEL3_LC3D4S0 0x01
19843 #define _CLC3SEL3_D4S0 0x01
19844 #define _CLC3SEL3_LC3D4S1 0x02
19845 #define _CLC3SEL3_D4S1 0x02
19846 #define _CLC3SEL3_LC3D4S2 0x04
19847 #define _CLC3SEL3_D4S2 0x04
19848 #define _CLC3SEL3_LC3D4S3 0x08
19849 #define _CLC3SEL3_D4S3 0x08
19850 #define _CLC3SEL3_LC3D4S4 0x10
19851 #define _CLC3SEL3_D4S4 0x10
19852 #define _CLC3SEL3_LC3D4S5 0x20
19853 #define _CLC3SEL3_D4S5 0x20
19855 //==============================================================================
19858 //==============================================================================
19861 extern __at(0x0F2A) __sfr CLC3GLS0
;
19867 unsigned LC3G1D1N
: 1;
19868 unsigned LC3G1D1T
: 1;
19869 unsigned LC3G1D2N
: 1;
19870 unsigned LC3G1D2T
: 1;
19871 unsigned LC3G1D3N
: 1;
19872 unsigned LC3G1D3T
: 1;
19873 unsigned LC3G1D4N
: 1;
19874 unsigned LC3G1D4T
: 1;
19888 } __CLC3GLS0bits_t
;
19890 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
19892 #define _CLC3GLS0_LC3G1D1N 0x01
19893 #define _CLC3GLS0_D1N 0x01
19894 #define _CLC3GLS0_LC3G1D1T 0x02
19895 #define _CLC3GLS0_D1T 0x02
19896 #define _CLC3GLS0_LC3G1D2N 0x04
19897 #define _CLC3GLS0_D2N 0x04
19898 #define _CLC3GLS0_LC3G1D2T 0x08
19899 #define _CLC3GLS0_D2T 0x08
19900 #define _CLC3GLS0_LC3G1D3N 0x10
19901 #define _CLC3GLS0_D3N 0x10
19902 #define _CLC3GLS0_LC3G1D3T 0x20
19903 #define _CLC3GLS0_D3T 0x20
19904 #define _CLC3GLS0_LC3G1D4N 0x40
19905 #define _CLC3GLS0_D4N 0x40
19906 #define _CLC3GLS0_LC3G1D4T 0x80
19907 #define _CLC3GLS0_D4T 0x80
19909 //==============================================================================
19912 //==============================================================================
19915 extern __at(0x0F2B) __sfr CLC3GLS1
;
19921 unsigned LC3G2D1N
: 1;
19922 unsigned LC3G2D1T
: 1;
19923 unsigned LC3G2D2N
: 1;
19924 unsigned LC3G2D2T
: 1;
19925 unsigned LC3G2D3N
: 1;
19926 unsigned LC3G2D3T
: 1;
19927 unsigned LC3G2D4N
: 1;
19928 unsigned LC3G2D4T
: 1;
19942 } __CLC3GLS1bits_t
;
19944 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
19946 #define _CLC3GLS1_LC3G2D1N 0x01
19947 #define _CLC3GLS1_D1N 0x01
19948 #define _CLC3GLS1_LC3G2D1T 0x02
19949 #define _CLC3GLS1_D1T 0x02
19950 #define _CLC3GLS1_LC3G2D2N 0x04
19951 #define _CLC3GLS1_D2N 0x04
19952 #define _CLC3GLS1_LC3G2D2T 0x08
19953 #define _CLC3GLS1_D2T 0x08
19954 #define _CLC3GLS1_LC3G2D3N 0x10
19955 #define _CLC3GLS1_D3N 0x10
19956 #define _CLC3GLS1_LC3G2D3T 0x20
19957 #define _CLC3GLS1_D3T 0x20
19958 #define _CLC3GLS1_LC3G2D4N 0x40
19959 #define _CLC3GLS1_D4N 0x40
19960 #define _CLC3GLS1_LC3G2D4T 0x80
19961 #define _CLC3GLS1_D4T 0x80
19963 //==============================================================================
19966 //==============================================================================
19969 extern __at(0x0F2C) __sfr CLC3GLS2
;
19975 unsigned LC3G3D1N
: 1;
19976 unsigned LC3G3D1T
: 1;
19977 unsigned LC3G3D2N
: 1;
19978 unsigned LC3G3D2T
: 1;
19979 unsigned LC3G3D3N
: 1;
19980 unsigned LC3G3D3T
: 1;
19981 unsigned LC3G3D4N
: 1;
19982 unsigned LC3G3D4T
: 1;
19996 } __CLC3GLS2bits_t
;
19998 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
20000 #define _CLC3GLS2_LC3G3D1N 0x01
20001 #define _CLC3GLS2_D1N 0x01
20002 #define _CLC3GLS2_LC3G3D1T 0x02
20003 #define _CLC3GLS2_D1T 0x02
20004 #define _CLC3GLS2_LC3G3D2N 0x04
20005 #define _CLC3GLS2_D2N 0x04
20006 #define _CLC3GLS2_LC3G3D2T 0x08
20007 #define _CLC3GLS2_D2T 0x08
20008 #define _CLC3GLS2_LC3G3D3N 0x10
20009 #define _CLC3GLS2_D3N 0x10
20010 #define _CLC3GLS2_LC3G3D3T 0x20
20011 #define _CLC3GLS2_D3T 0x20
20012 #define _CLC3GLS2_LC3G3D4N 0x40
20013 #define _CLC3GLS2_D4N 0x40
20014 #define _CLC3GLS2_LC3G3D4T 0x80
20015 #define _CLC3GLS2_D4T 0x80
20017 //==============================================================================
20020 //==============================================================================
20023 extern __at(0x0F2D) __sfr CLC3GLS3
;
20029 unsigned LC3G4D1N
: 1;
20030 unsigned LC3G4D1T
: 1;
20031 unsigned LC3G4D2N
: 1;
20032 unsigned LC3G4D2T
: 1;
20033 unsigned LC3G4D3N
: 1;
20034 unsigned LC3G4D3T
: 1;
20035 unsigned LC3G4D4N
: 1;
20036 unsigned LC3G4D4T
: 1;
20041 unsigned G4D1N
: 1;
20042 unsigned G4D1T
: 1;
20043 unsigned G4D2N
: 1;
20044 unsigned G4D2T
: 1;
20045 unsigned G4D3N
: 1;
20046 unsigned G4D3T
: 1;
20047 unsigned G4D4N
: 1;
20048 unsigned G4D4T
: 1;
20050 } __CLC3GLS3bits_t
;
20052 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
20054 #define _CLC3GLS3_LC3G4D1N 0x01
20055 #define _CLC3GLS3_G4D1N 0x01
20056 #define _CLC3GLS3_LC3G4D1T 0x02
20057 #define _CLC3GLS3_G4D1T 0x02
20058 #define _CLC3GLS3_LC3G4D2N 0x04
20059 #define _CLC3GLS3_G4D2N 0x04
20060 #define _CLC3GLS3_LC3G4D2T 0x08
20061 #define _CLC3GLS3_G4D2T 0x08
20062 #define _CLC3GLS3_LC3G4D3N 0x10
20063 #define _CLC3GLS3_G4D3N 0x10
20064 #define _CLC3GLS3_LC3G4D3T 0x20
20065 #define _CLC3GLS3_G4D3T 0x20
20066 #define _CLC3GLS3_LC3G4D4N 0x40
20067 #define _CLC3GLS3_G4D4N 0x40
20068 #define _CLC3GLS3_LC3G4D4T 0x80
20069 #define _CLC3GLS3_G4D4T 0x80
20071 //==============================================================================
20074 //==============================================================================
20077 extern __at(0x0F2E) __sfr CLC4CON
;
20083 unsigned LC4MODE0
: 1;
20084 unsigned LC4MODE1
: 1;
20085 unsigned LC4MODE2
: 1;
20086 unsigned LC4INTN
: 1;
20087 unsigned LC4INTP
: 1;
20088 unsigned LC4OUT
: 1;
20090 unsigned LC4EN
: 1;
20095 unsigned MODE0
: 1;
20096 unsigned MODE1
: 1;
20097 unsigned MODE2
: 1;
20107 unsigned LC4MODE
: 3;
20118 extern __at(0x0F2E) volatile __CLC4CONbits_t CLC4CONbits
;
20120 #define _CLC4CON_LC4MODE0 0x01
20121 #define _CLC4CON_MODE0 0x01
20122 #define _CLC4CON_LC4MODE1 0x02
20123 #define _CLC4CON_MODE1 0x02
20124 #define _CLC4CON_LC4MODE2 0x04
20125 #define _CLC4CON_MODE2 0x04
20126 #define _CLC4CON_LC4INTN 0x08
20127 #define _CLC4CON_INTN 0x08
20128 #define _CLC4CON_LC4INTP 0x10
20129 #define _CLC4CON_INTP 0x10
20130 #define _CLC4CON_LC4OUT 0x20
20131 #define _CLC4CON_OUT 0x20
20132 #define _CLC4CON_LC4EN 0x80
20133 #define _CLC4CON_EN 0x80
20135 //==============================================================================
20138 //==============================================================================
20141 extern __at(0x0F2F) __sfr CLC4POL
;
20147 unsigned LC4G1POL
: 1;
20148 unsigned LC4G2POL
: 1;
20149 unsigned LC4G3POL
: 1;
20150 unsigned LC4G4POL
: 1;
20154 unsigned LC4POL
: 1;
20159 unsigned G1POL
: 1;
20160 unsigned G2POL
: 1;
20161 unsigned G3POL
: 1;
20162 unsigned G4POL
: 1;
20170 extern __at(0x0F2F) volatile __CLC4POLbits_t CLC4POLbits
;
20172 #define _CLC4POL_LC4G1POL 0x01
20173 #define _CLC4POL_G1POL 0x01
20174 #define _CLC4POL_LC4G2POL 0x02
20175 #define _CLC4POL_G2POL 0x02
20176 #define _CLC4POL_LC4G3POL 0x04
20177 #define _CLC4POL_G3POL 0x04
20178 #define _CLC4POL_LC4G4POL 0x08
20179 #define _CLC4POL_G4POL 0x08
20180 #define _CLC4POL_LC4POL 0x80
20181 #define _CLC4POL_POL 0x80
20183 //==============================================================================
20186 //==============================================================================
20189 extern __at(0x0F30) __sfr CLC4SEL0
;
20195 unsigned LC4D1S0
: 1;
20196 unsigned LC4D1S1
: 1;
20197 unsigned LC4D1S2
: 1;
20198 unsigned LC4D1S3
: 1;
20199 unsigned LC4D1S4
: 1;
20200 unsigned LC4D1S5
: 1;
20219 unsigned LC4D1S
: 6;
20228 } __CLC4SEL0bits_t
;
20230 extern __at(0x0F30) volatile __CLC4SEL0bits_t CLC4SEL0bits
;
20232 #define _CLC4SEL0_LC4D1S0 0x01
20233 #define _CLC4SEL0_D1S0 0x01
20234 #define _CLC4SEL0_LC4D1S1 0x02
20235 #define _CLC4SEL0_D1S1 0x02
20236 #define _CLC4SEL0_LC4D1S2 0x04
20237 #define _CLC4SEL0_D1S2 0x04
20238 #define _CLC4SEL0_LC4D1S3 0x08
20239 #define _CLC4SEL0_D1S3 0x08
20240 #define _CLC4SEL0_LC4D1S4 0x10
20241 #define _CLC4SEL0_D1S4 0x10
20242 #define _CLC4SEL0_LC4D1S5 0x20
20243 #define _CLC4SEL0_D1S5 0x20
20245 //==============================================================================
20248 //==============================================================================
20251 extern __at(0x0F31) __sfr CLC4SEL1
;
20257 unsigned LC4D2S0
: 1;
20258 unsigned LC4D2S1
: 1;
20259 unsigned LC4D2S2
: 1;
20260 unsigned LC4D2S3
: 1;
20261 unsigned LC4D2S4
: 1;
20262 unsigned LC4D2S5
: 1;
20287 unsigned LC4D2S
: 6;
20290 } __CLC4SEL1bits_t
;
20292 extern __at(0x0F31) volatile __CLC4SEL1bits_t CLC4SEL1bits
;
20294 #define _CLC4SEL1_LC4D2S0 0x01
20295 #define _CLC4SEL1_D2S0 0x01
20296 #define _CLC4SEL1_LC4D2S1 0x02
20297 #define _CLC4SEL1_D2S1 0x02
20298 #define _CLC4SEL1_LC4D2S2 0x04
20299 #define _CLC4SEL1_D2S2 0x04
20300 #define _CLC4SEL1_LC4D2S3 0x08
20301 #define _CLC4SEL1_D2S3 0x08
20302 #define _CLC4SEL1_LC4D2S4 0x10
20303 #define _CLC4SEL1_D2S4 0x10
20304 #define _CLC4SEL1_LC4D2S5 0x20
20305 #define _CLC4SEL1_D2S5 0x20
20307 //==============================================================================
20310 //==============================================================================
20313 extern __at(0x0F32) __sfr CLC4SEL2
;
20319 unsigned LC4D3S0
: 1;
20320 unsigned LC4D3S1
: 1;
20321 unsigned LC4D3S2
: 1;
20322 unsigned LC4D3S3
: 1;
20323 unsigned LC4D3S4
: 1;
20324 unsigned LC4D3S5
: 1;
20349 unsigned LC4D3S
: 6;
20352 } __CLC4SEL2bits_t
;
20354 extern __at(0x0F32) volatile __CLC4SEL2bits_t CLC4SEL2bits
;
20356 #define _CLC4SEL2_LC4D3S0 0x01
20357 #define _CLC4SEL2_D3S0 0x01
20358 #define _CLC4SEL2_LC4D3S1 0x02
20359 #define _CLC4SEL2_D3S1 0x02
20360 #define _CLC4SEL2_LC4D3S2 0x04
20361 #define _CLC4SEL2_D3S2 0x04
20362 #define _CLC4SEL2_LC4D3S3 0x08
20363 #define _CLC4SEL2_D3S3 0x08
20364 #define _CLC4SEL2_LC4D3S4 0x10
20365 #define _CLC4SEL2_D3S4 0x10
20366 #define _CLC4SEL2_LC4D3S5 0x20
20367 #define _CLC4SEL2_D3S5 0x20
20369 //==============================================================================
20372 //==============================================================================
20375 extern __at(0x0F33) __sfr CLC4SEL3
;
20381 unsigned LC4D4S0
: 1;
20382 unsigned LC4D4S1
: 1;
20383 unsigned LC4D4S2
: 1;
20384 unsigned LC4D4S3
: 1;
20385 unsigned LC4D4S4
: 1;
20386 unsigned LC4D4S5
: 1;
20405 unsigned LC4D4S
: 6;
20414 } __CLC4SEL3bits_t
;
20416 extern __at(0x0F33) volatile __CLC4SEL3bits_t CLC4SEL3bits
;
20418 #define _CLC4SEL3_LC4D4S0 0x01
20419 #define _CLC4SEL3_D4S0 0x01
20420 #define _CLC4SEL3_LC4D4S1 0x02
20421 #define _CLC4SEL3_D4S1 0x02
20422 #define _CLC4SEL3_LC4D4S2 0x04
20423 #define _CLC4SEL3_D4S2 0x04
20424 #define _CLC4SEL3_LC4D4S3 0x08
20425 #define _CLC4SEL3_D4S3 0x08
20426 #define _CLC4SEL3_LC4D4S4 0x10
20427 #define _CLC4SEL3_D4S4 0x10
20428 #define _CLC4SEL3_LC4D4S5 0x20
20429 #define _CLC4SEL3_D4S5 0x20
20431 //==============================================================================
20434 //==============================================================================
20437 extern __at(0x0F34) __sfr CLC4GLS0
;
20443 unsigned LC4G1D1N
: 1;
20444 unsigned LC4G1D1T
: 1;
20445 unsigned LC4G1D2N
: 1;
20446 unsigned LC4G1D2T
: 1;
20447 unsigned LC4G1D3N
: 1;
20448 unsigned LC4G1D3T
: 1;
20449 unsigned LC4G1D4N
: 1;
20450 unsigned LC4G1D4T
: 1;
20464 } __CLC4GLS0bits_t
;
20466 extern __at(0x0F34) volatile __CLC4GLS0bits_t CLC4GLS0bits
;
20468 #define _CLC4GLS0_LC4G1D1N 0x01
20469 #define _CLC4GLS0_D1N 0x01
20470 #define _CLC4GLS0_LC4G1D1T 0x02
20471 #define _CLC4GLS0_D1T 0x02
20472 #define _CLC4GLS0_LC4G1D2N 0x04
20473 #define _CLC4GLS0_D2N 0x04
20474 #define _CLC4GLS0_LC4G1D2T 0x08
20475 #define _CLC4GLS0_D2T 0x08
20476 #define _CLC4GLS0_LC4G1D3N 0x10
20477 #define _CLC4GLS0_D3N 0x10
20478 #define _CLC4GLS0_LC4G1D3T 0x20
20479 #define _CLC4GLS0_D3T 0x20
20480 #define _CLC4GLS0_LC4G1D4N 0x40
20481 #define _CLC4GLS0_D4N 0x40
20482 #define _CLC4GLS0_LC4G1D4T 0x80
20483 #define _CLC4GLS0_D4T 0x80
20485 //==============================================================================
20488 //==============================================================================
20491 extern __at(0x0F35) __sfr CLC4GLS1
;
20497 unsigned LC4G2D1N
: 1;
20498 unsigned LC4G2D1T
: 1;
20499 unsigned LC4G2D2N
: 1;
20500 unsigned LC4G2D2T
: 1;
20501 unsigned LC4G2D3N
: 1;
20502 unsigned LC4G2D3T
: 1;
20503 unsigned LC4G2D4N
: 1;
20504 unsigned LC4G2D4T
: 1;
20518 } __CLC4GLS1bits_t
;
20520 extern __at(0x0F35) volatile __CLC4GLS1bits_t CLC4GLS1bits
;
20522 #define _CLC4GLS1_LC4G2D1N 0x01
20523 #define _CLC4GLS1_D1N 0x01
20524 #define _CLC4GLS1_LC4G2D1T 0x02
20525 #define _CLC4GLS1_D1T 0x02
20526 #define _CLC4GLS1_LC4G2D2N 0x04
20527 #define _CLC4GLS1_D2N 0x04
20528 #define _CLC4GLS1_LC4G2D2T 0x08
20529 #define _CLC4GLS1_D2T 0x08
20530 #define _CLC4GLS1_LC4G2D3N 0x10
20531 #define _CLC4GLS1_D3N 0x10
20532 #define _CLC4GLS1_LC4G2D3T 0x20
20533 #define _CLC4GLS1_D3T 0x20
20534 #define _CLC4GLS1_LC4G2D4N 0x40
20535 #define _CLC4GLS1_D4N 0x40
20536 #define _CLC4GLS1_LC4G2D4T 0x80
20537 #define _CLC4GLS1_D4T 0x80
20539 //==============================================================================
20542 //==============================================================================
20545 extern __at(0x0F36) __sfr CLC4GLS2
;
20551 unsigned LC4G3D1N
: 1;
20552 unsigned LC4G3D1T
: 1;
20553 unsigned LC4G3D2N
: 1;
20554 unsigned LC4G3D2T
: 1;
20555 unsigned LC4G3D3N
: 1;
20556 unsigned LC4G3D3T
: 1;
20557 unsigned LC4G3D4N
: 1;
20558 unsigned LC4G3D4T
: 1;
20572 } __CLC4GLS2bits_t
;
20574 extern __at(0x0F36) volatile __CLC4GLS2bits_t CLC4GLS2bits
;
20576 #define _CLC4GLS2_LC4G3D1N 0x01
20577 #define _CLC4GLS2_D1N 0x01
20578 #define _CLC4GLS2_LC4G3D1T 0x02
20579 #define _CLC4GLS2_D1T 0x02
20580 #define _CLC4GLS2_LC4G3D2N 0x04
20581 #define _CLC4GLS2_D2N 0x04
20582 #define _CLC4GLS2_LC4G3D2T 0x08
20583 #define _CLC4GLS2_D2T 0x08
20584 #define _CLC4GLS2_LC4G3D3N 0x10
20585 #define _CLC4GLS2_D3N 0x10
20586 #define _CLC4GLS2_LC4G3D3T 0x20
20587 #define _CLC4GLS2_D3T 0x20
20588 #define _CLC4GLS2_LC4G3D4N 0x40
20589 #define _CLC4GLS2_D4N 0x40
20590 #define _CLC4GLS2_LC4G3D4T 0x80
20591 #define _CLC4GLS2_D4T 0x80
20593 //==============================================================================
20596 //==============================================================================
20599 extern __at(0x0F37) __sfr CLC4GLS3
;
20605 unsigned LC4G4D1N
: 1;
20606 unsigned LC4G4D1T
: 1;
20607 unsigned LC4G4D2N
: 1;
20608 unsigned LC4G4D2T
: 1;
20609 unsigned LC4G4D3N
: 1;
20610 unsigned LC4G4D3T
: 1;
20611 unsigned LC4G4D4N
: 1;
20612 unsigned LC4G4D4T
: 1;
20617 unsigned G4D1N
: 1;
20618 unsigned G4D1T
: 1;
20619 unsigned G4D2N
: 1;
20620 unsigned G4D2T
: 1;
20621 unsigned G4D3N
: 1;
20622 unsigned G4D3T
: 1;
20623 unsigned G4D4N
: 1;
20624 unsigned G4D4T
: 1;
20626 } __CLC4GLS3bits_t
;
20628 extern __at(0x0F37) volatile __CLC4GLS3bits_t CLC4GLS3bits
;
20630 #define _CLC4GLS3_LC4G4D1N 0x01
20631 #define _CLC4GLS3_G4D1N 0x01
20632 #define _CLC4GLS3_LC4G4D1T 0x02
20633 #define _CLC4GLS3_G4D1T 0x02
20634 #define _CLC4GLS3_LC4G4D2N 0x04
20635 #define _CLC4GLS3_G4D2N 0x04
20636 #define _CLC4GLS3_LC4G4D2T 0x08
20637 #define _CLC4GLS3_G4D2T 0x08
20638 #define _CLC4GLS3_LC4G4D3N 0x10
20639 #define _CLC4GLS3_G4D3N 0x10
20640 #define _CLC4GLS3_LC4G4D3T 0x20
20641 #define _CLC4GLS3_G4D3T 0x20
20642 #define _CLC4GLS3_LC4G4D4N 0x40
20643 #define _CLC4GLS3_G4D4N 0x40
20644 #define _CLC4GLS3_LC4G4D4T 0x80
20645 #define _CLC4GLS3_G4D4T 0x80
20647 //==============================================================================
20650 //==============================================================================
20651 // STATUS_SHAD Bits
20653 extern __at(0x0FE4) __sfr STATUS_SHAD
;
20657 unsigned C_SHAD
: 1;
20658 unsigned DC_SHAD
: 1;
20659 unsigned Z_SHAD
: 1;
20665 } __STATUS_SHADbits_t
;
20667 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
20669 #define _C_SHAD 0x01
20670 #define _DC_SHAD 0x02
20671 #define _Z_SHAD 0x04
20673 //==============================================================================
20675 extern __at(0x0FE5) __sfr WREG_SHAD
;
20676 extern __at(0x0FE6) __sfr BSR_SHAD
;
20677 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
20678 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
20679 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
20680 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
20681 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
20682 extern __at(0x0FED) __sfr STKPTR
;
20683 extern __at(0x0FEE) __sfr TOSL
;
20684 extern __at(0x0FEF) __sfr TOSH
;
20686 //==============================================================================
20688 // Configuration Bits
20690 //==============================================================================
20692 #define _CONFIG1 0x8007
20693 #define _CONFIG2 0x8008
20695 //----------------------------- CONFIG1 Options -------------------------------
20697 #define _FOSC_LP 0x3FF8 // LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins.
20698 #define _FOSC_XT 0x3FF9 // XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins.
20699 #define _FOSC_HS 0x3FFA // HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins.
20700 #define _FOSC_EXTRC 0x3FFB // EXTRC oscillator: External RC circuit connected to CLKIN pin.
20701 #define _FOSC_INTOSC 0x3FFC // INTOSC oscillator: I/O function on CLKIN pin.
20702 #define _FOSC_ECL 0x3FFD // ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pins.
20703 #define _FOSC_ECM 0x3FFE // ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pins.
20704 #define _FOSC_ECH 0x3FFF // ECH, External Clock, High Power Mode (4-20 MHz): device clock supplied to CLKIN pins.
20705 #define _WDTE_OFF 0x3FE7 // WDT disabled.
20706 #define _WDTE_SWDTEN 0x3FEF // WDT controlled by the SWDTEN bit in the WDTCON register.
20707 #define _WDTE_NSLEEP 0x3FF7 // WDT enabled while running and disabled in Sleep.
20708 #define _WDTE_ON 0x3FFF // WDT enabled.
20709 #define _PWRTE_ON 0x3FDF // PWRT enabled.
20710 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
20711 #define _MCLRE_OFF 0x3FBF // MCLR/VPP pin function is digital input.
20712 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR.
20713 #define _CP_ON 0x3F7F // Program memory code protection is enabled.
20714 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
20715 #define _BOREN_OFF 0x39FF // Brown-out Reset disabled.
20716 #define _BOREN_SBODEN 0x3BFF // Brown-out Reset controlled by the SBOREN bit in the BORCON register.
20717 #define _BOREN_NSLEEP 0x3DFF // Brown-out Reset enabled while running and disabled in Sleep.
20718 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled.
20719 #define _CLKOUTEN_ON 0x37FF // CLKOUT function is enabled on the CLKOUT pin.
20720 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
20721 #define _IESO_OFF 0x2FFF // Internal/External Switchover Mode is disabled.
20722 #define _IESO_ON 0x3FFF // Internal/External Switchover Mode is enabled.
20723 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
20724 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
20726 //----------------------------- CONFIG2 Options -------------------------------
20728 #define _WRT_ALL 0x3FFC // 000h to 1FFFh write protected, no addresses may be modified by EECON control.
20729 #define _WRT_HALF 0x3FFD // 000h to FFFh write protected, 1000h to 1FFFh may be modified by EECON control.
20730 #define _WRT_BOOT 0x3FFE // 000h to 1FFh write protected, 200h to 1FFFh may be modified by EECON control.
20731 #define _WRT_OFF 0x3FFF // Write protection off.
20732 #define _PPS1WAY_OFF 0x3FFB // The PPSLOCK bit can be set and cleared repeatedly by software.
20733 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit cannot be cleared once it is set by software.
20734 #define _ZCD_ON 0x3F7F // Zero-cross detect circuit is enabled at POR.
20735 #define _ZCD_OFF 0x3FFF // Zero-cross detect circuit is disabled at POR.
20736 #define _PLLEN_OFF 0x3EFF // 4x PLL is enabled when software sets the SPLLEN bit.
20737 #define _PLLEN_ON 0x3FFF // 4x PLL is always enabled.
20738 #define _STVREN_OFF 0x3DFF // Stack Overflow or Underflow will not cause a Reset.
20739 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
20740 #define _BORV_HI 0x3BFF // Brown-out Reset Voltage (Vbor), high trip point selected.
20741 #define _BORV_LO 0x3FFF // Brown-out Reset Voltage (Vbor), low trip point selected.
20742 #define _LPBOR_ON 0x37FF // Low-Power BOR is enabled.
20743 #define _LPBOR_OFF 0x3FFF // Low-Power BOR is disabled.
20744 #define _DEBUG_ON 0x2FFF // In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger.
20745 #define _DEBUG_OFF 0x3FFF // In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins.
20746 #define _LVP_OFF 0x1FFF // High-voltage on MCLR/VPP must be used for programming.
20747 #define _LVP_ON 0x3FFF // Low-voltage programming enabled.
20749 //==============================================================================
20751 #define _DEVID1 0x8006
20753 #define _IDLOC0 0x8000
20754 #define _IDLOC1 0x8001
20755 #define _IDLOC2 0x8002
20756 #define _IDLOC3 0x8003
20758 //==============================================================================
20760 #ifndef NO_BIT_DEFINES
20762 #define ADON ADCON0bits.ADON // bit 0
20763 #define GO ADCON0bits.GO // bit 1
20765 #define ADNREF ADCON1bits.ADNREF // bit 2
20766 #define ADFM ADCON1bits.ADFM // bit 7
20768 #define ANSA0 ANSELAbits.ANSA0 // bit 0
20769 #define ANSA1 ANSELAbits.ANSA1 // bit 1
20770 #define ANSA2 ANSELAbits.ANSA2 // bit 2
20771 #define ANSA3 ANSELAbits.ANSA3 // bit 3
20772 #define ANSA4 ANSELAbits.ANSA4 // bit 4
20773 #define ANSA5 ANSELAbits.ANSA5 // bit 5
20775 #define ANSB0 ANSELBbits.ANSB0 // bit 0
20776 #define ANSB1 ANSELBbits.ANSB1 // bit 1
20777 #define ANSB2 ANSELBbits.ANSB2 // bit 2
20778 #define ANSB3 ANSELBbits.ANSB3 // bit 3
20779 #define ANSB4 ANSELBbits.ANSB4 // bit 4
20780 #define ANSB5 ANSELBbits.ANSB5 // bit 5
20782 #define ANSC2 ANSELCbits.ANSC2 // bit 2
20783 #define ANSC3 ANSELCbits.ANSC3 // bit 3
20784 #define ANSC4 ANSELCbits.ANSC4 // bit 4
20785 #define ANSC5 ANSELCbits.ANSC5 // bit 5
20786 #define ANSC6 ANSELCbits.ANSC6 // bit 6
20787 #define ANSC7 ANSELCbits.ANSC7 // bit 7
20789 #define ABDEN BAUD1CONbits.ABDEN // bit 0
20790 #define WUE BAUD1CONbits.WUE // bit 1
20791 #define BRG16 BAUD1CONbits.BRG16 // bit 3
20792 #define SCKP BAUD1CONbits.SCKP // bit 4
20793 #define RCIDL BAUD1CONbits.RCIDL // bit 6
20794 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
20796 #define BORRDY BORCONbits.BORRDY // bit 0
20797 #define BORFS BORCONbits.BORFS // bit 6
20798 #define SBOREN BORCONbits.SBOREN // bit 7
20800 #define BSR0 BSRbits.BSR0 // bit 0
20801 #define BSR1 BSRbits.BSR1 // bit 1
20802 #define BSR2 BSRbits.BSR2 // bit 2
20803 #define BSR3 BSRbits.BSR3 // bit 3
20804 #define BSR4 BSRbits.BSR4 // bit 4
20806 #define CTS0 CCP1CAPbits.CTS0 // bit 0, shadows bit in CCP1CAPbits
20807 #define CCP1CTS0 CCP1CAPbits.CCP1CTS0 // bit 0, shadows bit in CCP1CAPbits
20808 #define CTS1 CCP1CAPbits.CTS1 // bit 1, shadows bit in CCP1CAPbits
20809 #define CCP1CTS1 CCP1CAPbits.CCP1CTS1 // bit 1, shadows bit in CCP1CAPbits
20810 #define CTS2 CCP1CAPbits.CTS2 // bit 2, shadows bit in CCP1CAPbits
20811 #define CCP1CTS2 CCP1CAPbits.CCP1CTS2 // bit 2, shadows bit in CCP1CAPbits
20812 #define CTS3 CCP1CAPbits.CTS3 // bit 3, shadows bit in CCP1CAPbits
20813 #define CCP1CTS3 CCP1CAPbits.CCP1CTS3 // bit 3, shadows bit in CCP1CAPbits
20815 #define MODE0 CCP1CONbits.MODE0 // bit 0, shadows bit in CCP1CONbits
20816 #define CCP1MODE0 CCP1CONbits.CCP1MODE0 // bit 0, shadows bit in CCP1CONbits
20817 #define MODE1 CCP1CONbits.MODE1 // bit 1, shadows bit in CCP1CONbits
20818 #define CCP1MODE1 CCP1CONbits.CCP1MODE1 // bit 1, shadows bit in CCP1CONbits
20819 #define MODE2 CCP1CONbits.MODE2 // bit 2, shadows bit in CCP1CONbits
20820 #define CCP1MODE2 CCP1CONbits.CCP1MODE2 // bit 2, shadows bit in CCP1CONbits
20821 #define MODE3 CCP1CONbits.MODE3 // bit 3, shadows bit in CCP1CONbits
20822 #define CCP1MODE3 CCP1CONbits.CCP1MODE3 // bit 3, shadows bit in CCP1CONbits
20823 #define FMT CCP1CONbits.FMT // bit 4, shadows bit in CCP1CONbits
20824 #define CCP1FMT CCP1CONbits.CCP1FMT // bit 4, shadows bit in CCP1CONbits
20825 #define OUT CCP1CONbits.OUT // bit 5, shadows bit in CCP1CONbits
20826 #define CCP1OUT CCP1CONbits.CCP1OUT // bit 5, shadows bit in CCP1CONbits
20827 #define EN CCP1CONbits.EN // bit 7, shadows bit in CCP1CONbits
20828 #define CCP1EN CCP1CONbits.CCP1EN // bit 7, shadows bit in CCP1CONbits
20830 #define C1TSEL0 CCPTMRS1bits.C1TSEL0 // bit 0
20831 #define C1TSEL1 CCPTMRS1bits.C1TSEL1 // bit 1
20832 #define C2TSEL0 CCPTMRS1bits.C2TSEL0 // bit 2
20833 #define C2TSEL1 CCPTMRS1bits.C2TSEL1 // bit 3
20834 #define C7TSEL0 CCPTMRS1bits.C7TSEL0 // bit 4
20835 #define C7TSEL1 CCPTMRS1bits.C7TSEL1 // bit 5
20837 #define P3TSEL0 CCPTMRS2bits.P3TSEL0 // bit 0
20838 #define P3TSEL1 CCPTMRS2bits.P3TSEL1 // bit 1
20839 #define P4TSEL0 CCPTMRS2bits.P4TSEL0 // bit 2
20840 #define P4TSEL1 CCPTMRS2bits.P4TSEL1 // bit 3
20841 #define P9TSEL0 CCPTMRS2bits.P9TSEL0 // bit 4
20842 #define P9TSEL1 CCPTMRS2bits.P9TSEL1 // bit 5
20844 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
20845 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
20846 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
20847 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
20848 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
20849 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
20850 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
20851 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
20852 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
20853 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
20854 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
20855 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
20856 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
20857 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
20858 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
20859 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
20861 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
20862 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
20863 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
20864 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
20865 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
20866 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
20867 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
20868 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
20869 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
20870 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
20871 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
20872 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
20873 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
20874 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
20875 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
20876 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
20878 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
20879 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
20880 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
20881 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
20882 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
20883 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
20884 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
20885 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
20886 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
20887 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
20889 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
20890 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
20891 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
20892 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
20893 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
20894 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
20895 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
20896 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
20897 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
20898 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
20899 #define LC1D1S5 CLC1SEL0bits.LC1D1S5 // bit 5, shadows bit in CLC1SEL0bits
20900 #define D1S5 CLC1SEL0bits.D1S5 // bit 5, shadows bit in CLC1SEL0bits
20902 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
20903 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
20904 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
20905 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
20906 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
20907 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
20908 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
20909 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
20910 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
20911 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
20912 #define LC1D2S5 CLC1SEL1bits.LC1D2S5 // bit 5, shadows bit in CLC1SEL1bits
20913 #define D2S5 CLC1SEL1bits.D2S5 // bit 5, shadows bit in CLC1SEL1bits
20915 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
20916 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
20917 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
20918 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
20919 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
20920 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
20921 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
20922 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
20923 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
20924 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
20925 #define LC1D3S5 CLC1SEL2bits.LC1D3S5 // bit 5, shadows bit in CLC1SEL2bits
20926 #define D3S5 CLC1SEL2bits.D3S5 // bit 5, shadows bit in CLC1SEL2bits
20928 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
20929 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
20930 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
20931 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
20932 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
20933 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
20934 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
20935 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
20936 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
20937 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
20938 #define LC1D4S5 CLC1SEL3bits.LC1D4S5 // bit 5, shadows bit in CLC1SEL3bits
20939 #define D4S5 CLC1SEL3bits.D4S5 // bit 5, shadows bit in CLC1SEL3bits
20941 #define MCLC1OUT CLCDATAbits.MCLC1OUT // bit 0
20942 #define MCLC2OUT CLCDATAbits.MCLC2OUT // bit 1
20943 #define MCLC3OUT CLCDATAbits.MCLC3OUT // bit 2
20944 #define MLC4OUT CLCDATAbits.MLC4OUT // bit 3
20946 #define C1NCH0 CM1NSELbits.C1NCH0 // bit 0
20947 #define C1NCH1 CM1NSELbits.C1NCH1 // bit 1
20948 #define C1NCH2 CM1NSELbits.C1NCH2 // bit 2
20949 #define C1NCH3 CM1NSELbits.C1NCH3 // bit 3
20951 #define PCH0 CM1PSELbits.PCH0 // bit 0, shadows bit in CM1PSELbits
20952 #define C1PCH0 CM1PSELbits.C1PCH0 // bit 0, shadows bit in CM1PSELbits
20953 #define PCH1 CM1PSELbits.PCH1 // bit 1, shadows bit in CM1PSELbits
20954 #define C1PCH1 CM1PSELbits.C1PCH1 // bit 1, shadows bit in CM1PSELbits
20955 #define PCH2 CM1PSELbits.PCH2 // bit 2, shadows bit in CM1PSELbits
20956 #define C1PCH2 CM1PSELbits.C1PCH2 // bit 2, shadows bit in CM1PSELbits
20957 #define PCH3 CM1PSELbits.PCH3 // bit 3, shadows bit in CM1PSELbits
20958 #define C1PCH3 CM1PSELbits.C1PCH3 // bit 3, shadows bit in CM1PSELbits
20960 #define C2NCH0 CM2NSELbits.C2NCH0 // bit 0
20961 #define C2NCH1 CM2NSELbits.C2NCH1 // bit 1
20962 #define C2NCH2 CM2NSELbits.C2NCH2 // bit 2
20963 #define C2NCH3 CM2NSELbits.C2NCH3 // bit 3
20965 #define C3NCH0 CM3NSELbits.C3NCH0 // bit 0
20966 #define C3NCH1 CM3NSELbits.C3NCH1 // bit 1
20967 #define C3NCH2 CM3NSELbits.C3NCH2 // bit 2
20968 #define C3NCH3 CM3NSELbits.C3NCH3 // bit 3
20970 #define C4NCH0 CM4NSELbits.C4NCH0 // bit 0
20971 #define C4NCH1 CM4NSELbits.C4NCH1 // bit 1
20972 #define C4NCH2 CM4NSELbits.C4NCH2 // bit 2
20973 #define C4NCH3 CM4NSELbits.C4NCH3 // bit 3
20975 #define C5NCH0 CM5NSELbits.C5NCH0 // bit 0
20976 #define C5NCH1 CM5NSELbits.C5NCH1 // bit 1
20977 #define C5NCH2 CM5NSELbits.C5NCH2 // bit 2
20978 #define C5NCH3 CM5NSELbits.C5NCH3 // bit 3
20980 #define C6NCH0 CM6NSELbits.C6NCH0 // bit 0
20981 #define C6NCH1 CM6NSELbits.C6NCH1 // bit 1
20982 #define C6NCH2 CM6NSELbits.C6NCH2 // bit 2
20983 #define C6NCH3 CM6NSELbits.C6NCH3 // bit 3
20985 #define MC1OUT CMOUTbits.MC1OUT // bit 0
20986 #define MC2OUT CMOUTbits.MC2OUT // bit 1
20987 #define MC3OUT CMOUTbits.MC3OUT // bit 2
20988 #define MC4OUT CMOUTbits.MC4OUT // bit 3
20989 #define MC5OUT CMOUTbits.MC5OUT // bit 4
20990 #define MC6OUT CMOUTbits.MC6OUT // bit 5
20992 #define ASDAC0 COG1ASD0bits.ASDAC0 // bit 2, shadows bit in COG1ASD0bits
20993 #define G1ASDAC0 COG1ASD0bits.G1ASDAC0 // bit 2, shadows bit in COG1ASD0bits
20994 #define ASDAC1 COG1ASD0bits.ASDAC1 // bit 3, shadows bit in COG1ASD0bits
20995 #define G1ASDAC1 COG1ASD0bits.G1ASDAC1 // bit 3, shadows bit in COG1ASD0bits
20996 #define ASDBD0 COG1ASD0bits.ASDBD0 // bit 4, shadows bit in COG1ASD0bits
20997 #define G1ASDBD0 COG1ASD0bits.G1ASDBD0 // bit 4, shadows bit in COG1ASD0bits
20998 #define ASDBD1 COG1ASD0bits.ASDBD1 // bit 5, shadows bit in COG1ASD0bits
20999 #define G1ASDBD1 COG1ASD0bits.G1ASDBD1 // bit 5, shadows bit in COG1ASD0bits
21000 #define ASREN COG1ASD0bits.ASREN // bit 6, shadows bit in COG1ASD0bits
21001 #define ARSEN COG1ASD0bits.ARSEN // bit 6, shadows bit in COG1ASD0bits
21002 #define G1ARSEN COG1ASD0bits.G1ARSEN // bit 6, shadows bit in COG1ASD0bits
21003 #define G1ASREN COG1ASD0bits.G1ASREN // bit 6, shadows bit in COG1ASD0bits
21004 #define ASE COG1ASD0bits.ASE // bit 7, shadows bit in COG1ASD0bits
21005 #define G1ASE COG1ASD0bits.G1ASE // bit 7, shadows bit in COG1ASD0bits
21007 #define AS0E COG1ASD1bits.AS0E // bit 0, shadows bit in COG1ASD1bits
21008 #define G1AS0E COG1ASD1bits.G1AS0E // bit 0, shadows bit in COG1ASD1bits
21009 #define AS1E COG1ASD1bits.AS1E // bit 1, shadows bit in COG1ASD1bits
21010 #define G1AS1E COG1ASD1bits.G1AS1E // bit 1, shadows bit in COG1ASD1bits
21011 #define AS2E COG1ASD1bits.AS2E // bit 2, shadows bit in COG1ASD1bits
21012 #define G1AS2E COG1ASD1bits.G1AS2E // bit 2, shadows bit in COG1ASD1bits
21013 #define AS3E COG1ASD1bits.AS3E // bit 3, shadows bit in COG1ASD1bits
21014 #define G1AS3E COG1ASD1bits.G1AS3E // bit 3, shadows bit in COG1ASD1bits
21015 #define AS4E COG1ASD1bits.AS4E // bit 4, shadows bit in COG1ASD1bits
21016 #define G1AS4E COG1ASD1bits.G1AS4E // bit 4, shadows bit in COG1ASD1bits
21017 #define AS5E COG1ASD1bits.AS5E // bit 5, shadows bit in COG1ASD1bits
21018 #define G1AS5E COG1ASD1bits.G1AS5E // bit 5, shadows bit in COG1ASD1bits
21019 #define AS6E COG1ASD1bits.AS6E // bit 6, shadows bit in COG1ASD1bits
21020 #define G1AS6E COG1ASD1bits.G1AS6E // bit 6, shadows bit in COG1ASD1bits
21021 #define AS7E COG1ASD1bits.AS7E // bit 7, shadows bit in COG1ASD1bits
21022 #define G1AS7E COG1ASD1bits.G1AS7E // bit 7, shadows bit in COG1ASD1bits
21024 #define BLKF0 COG1BLKFbits.BLKF0 // bit 0, shadows bit in COG1BLKFbits
21025 #define G1BLKF0 COG1BLKFbits.G1BLKF0 // bit 0, shadows bit in COG1BLKFbits
21026 #define BLKF1 COG1BLKFbits.BLKF1 // bit 1, shadows bit in COG1BLKFbits
21027 #define G1BLKF1 COG1BLKFbits.G1BLKF1 // bit 1, shadows bit in COG1BLKFbits
21028 #define BLKF2 COG1BLKFbits.BLKF2 // bit 2, shadows bit in COG1BLKFbits
21029 #define G1BLKF2 COG1BLKFbits.G1BLKF2 // bit 2, shadows bit in COG1BLKFbits
21030 #define BLKF3 COG1BLKFbits.BLKF3 // bit 3, shadows bit in COG1BLKFbits
21031 #define G1BLKF3 COG1BLKFbits.G1BLKF3 // bit 3, shadows bit in COG1BLKFbits
21032 #define BLKF4 COG1BLKFbits.BLKF4 // bit 4, shadows bit in COG1BLKFbits
21033 #define G1BLKF4 COG1BLKFbits.G1BLKF4 // bit 4, shadows bit in COG1BLKFbits
21034 #define BLKF5 COG1BLKFbits.BLKF5 // bit 5, shadows bit in COG1BLKFbits
21035 #define G1BLKF5 COG1BLKFbits.G1BLKF5 // bit 5, shadows bit in COG1BLKFbits
21037 #define BLKR0 COG1BLKRbits.BLKR0 // bit 0, shadows bit in COG1BLKRbits
21038 #define G1BLKR0 COG1BLKRbits.G1BLKR0 // bit 0, shadows bit in COG1BLKRbits
21039 #define BLKR1 COG1BLKRbits.BLKR1 // bit 1, shadows bit in COG1BLKRbits
21040 #define G1BLKR1 COG1BLKRbits.G1BLKR1 // bit 1, shadows bit in COG1BLKRbits
21041 #define BLKR2 COG1BLKRbits.BLKR2 // bit 2, shadows bit in COG1BLKRbits
21042 #define G1BLKR2 COG1BLKRbits.G1BLKR2 // bit 2, shadows bit in COG1BLKRbits
21043 #define BLKR3 COG1BLKRbits.BLKR3 // bit 3, shadows bit in COG1BLKRbits
21044 #define G1BLKR3 COG1BLKRbits.G1BLKR3 // bit 3, shadows bit in COG1BLKRbits
21045 #define BLKR4 COG1BLKRbits.BLKR4 // bit 4, shadows bit in COG1BLKRbits
21046 #define G1BLKR4 COG1BLKRbits.G1BLKR4 // bit 4, shadows bit in COG1BLKRbits
21047 #define BLKR5 COG1BLKRbits.BLKR5 // bit 5, shadows bit in COG1BLKRbits
21048 #define G1BLKR5 COG1BLKRbits.G1BLKR5 // bit 5, shadows bit in COG1BLKRbits
21050 #define POLA COG1CON1bits.POLA // bit 0, shadows bit in COG1CON1bits
21051 #define G1POLA COG1CON1bits.G1POLA // bit 0, shadows bit in COG1CON1bits
21052 #define POLB COG1CON1bits.POLB // bit 1, shadows bit in COG1CON1bits
21053 #define G1POLB COG1CON1bits.G1POLB // bit 1, shadows bit in COG1CON1bits
21054 #define POLC COG1CON1bits.POLC // bit 2, shadows bit in COG1CON1bits
21055 #define G1POLC COG1CON1bits.G1POLC // bit 2, shadows bit in COG1CON1bits
21056 #define POLD COG1CON1bits.POLD // bit 3, shadows bit in COG1CON1bits
21057 #define G1POLD COG1CON1bits.G1POLD // bit 3, shadows bit in COG1CON1bits
21058 #define FDBS COG1CON1bits.FDBS // bit 6, shadows bit in COG1CON1bits
21059 #define G1FDBS COG1CON1bits.G1FDBS // bit 6, shadows bit in COG1CON1bits
21060 #define RDBS COG1CON1bits.RDBS // bit 7, shadows bit in COG1CON1bits
21061 #define G1RDBS COG1CON1bits.G1RDBS // bit 7, shadows bit in COG1CON1bits
21063 #define DBF0 COG1DBFbits.DBF0 // bit 0, shadows bit in COG1DBFbits
21064 #define G1DBF0 COG1DBFbits.G1DBF0 // bit 0, shadows bit in COG1DBFbits
21065 #define DBF1 COG1DBFbits.DBF1 // bit 1, shadows bit in COG1DBFbits
21066 #define G1DBF1 COG1DBFbits.G1DBF1 // bit 1, shadows bit in COG1DBFbits
21067 #define DBF2 COG1DBFbits.DBF2 // bit 2, shadows bit in COG1DBFbits
21068 #define G1DBF2 COG1DBFbits.G1DBF2 // bit 2, shadows bit in COG1DBFbits
21069 #define DBF3 COG1DBFbits.DBF3 // bit 3, shadows bit in COG1DBFbits
21070 #define G1DBF3 COG1DBFbits.G1DBF3 // bit 3, shadows bit in COG1DBFbits
21071 #define DBF4 COG1DBFbits.DBF4 // bit 4, shadows bit in COG1DBFbits
21072 #define G1DBF4 COG1DBFbits.G1DBF4 // bit 4, shadows bit in COG1DBFbits
21073 #define DBF5 COG1DBFbits.DBF5 // bit 5, shadows bit in COG1DBFbits
21074 #define G1DBF5 COG1DBFbits.G1DBF5 // bit 5, shadows bit in COG1DBFbits
21076 #define DBR0 COG1DBRbits.DBR0 // bit 0, shadows bit in COG1DBRbits
21077 #define G1DBR0 COG1DBRbits.G1DBR0 // bit 0, shadows bit in COG1DBRbits
21078 #define DBR1 COG1DBRbits.DBR1 // bit 1, shadows bit in COG1DBRbits
21079 #define G1DBR1 COG1DBRbits.G1DBR1 // bit 1, shadows bit in COG1DBRbits
21080 #define DBR2 COG1DBRbits.DBR2 // bit 2, shadows bit in COG1DBRbits
21081 #define G1DBR2 COG1DBRbits.G1DBR2 // bit 2, shadows bit in COG1DBRbits
21082 #define DBR3 COG1DBRbits.DBR3 // bit 3, shadows bit in COG1DBRbits
21083 #define G1DBR3 COG1DBRbits.G1DBR3 // bit 3, shadows bit in COG1DBRbits
21084 #define DBR4 COG1DBRbits.DBR4 // bit 4, shadows bit in COG1DBRbits
21085 #define G1DBR4 COG1DBRbits.G1DBR4 // bit 4, shadows bit in COG1DBRbits
21086 #define DBR5 COG1DBRbits.DBR5 // bit 5, shadows bit in COG1DBRbits
21087 #define G1DBR5 COG1DBRbits.G1DBR5 // bit 5, shadows bit in COG1DBRbits
21089 #define FIS0 COG1FIS0bits.FIS0 // bit 0, shadows bit in COG1FIS0bits
21090 #define G1FIS0 COG1FIS0bits.G1FIS0 // bit 0, shadows bit in COG1FIS0bits
21091 #define FIS1 COG1FIS0bits.FIS1 // bit 1, shadows bit in COG1FIS0bits
21092 #define G1FIS1 COG1FIS0bits.G1FIS1 // bit 1, shadows bit in COG1FIS0bits
21093 #define FIS2 COG1FIS0bits.FIS2 // bit 2, shadows bit in COG1FIS0bits
21094 #define G1FIS2 COG1FIS0bits.G1FIS2 // bit 2, shadows bit in COG1FIS0bits
21095 #define FIS3 COG1FIS0bits.FIS3 // bit 3, shadows bit in COG1FIS0bits
21096 #define G1FIS3 COG1FIS0bits.G1FIS3 // bit 3, shadows bit in COG1FIS0bits
21097 #define FIS4 COG1FIS0bits.FIS4 // bit 4, shadows bit in COG1FIS0bits
21098 #define G1FIS4 COG1FIS0bits.G1FIS4 // bit 4, shadows bit in COG1FIS0bits
21099 #define FIS5 COG1FIS0bits.FIS5 // bit 5, shadows bit in COG1FIS0bits
21100 #define G1FIS5 COG1FIS0bits.G1FIS5 // bit 5, shadows bit in COG1FIS0bits
21101 #define FIS6 COG1FIS0bits.FIS6 // bit 6, shadows bit in COG1FIS0bits
21102 #define G1FIS6 COG1FIS0bits.G1FIS6 // bit 6, shadows bit in COG1FIS0bits
21103 #define FIS7 COG1FIS0bits.FIS7 // bit 7, shadows bit in COG1FIS0bits
21104 #define G1FIS7 COG1FIS0bits.G1FIS7 // bit 7, shadows bit in COG1FIS0bits
21106 #define FIS8 COG1FIS1bits.FIS8 // bit 0, shadows bit in COG1FIS1bits
21107 #define G1FIS8 COG1FIS1bits.G1FIS8 // bit 0, shadows bit in COG1FIS1bits
21108 #define FIS9 COG1FIS1bits.FIS9 // bit 1, shadows bit in COG1FIS1bits
21109 #define G1FIS9 COG1FIS1bits.G1FIS9 // bit 1, shadows bit in COG1FIS1bits
21110 #define FIS10 COG1FIS1bits.FIS10 // bit 2, shadows bit in COG1FIS1bits
21111 #define G1FIS10 COG1FIS1bits.G1FIS10 // bit 2, shadows bit in COG1FIS1bits
21112 #define FIS11 COG1FIS1bits.FIS11 // bit 3, shadows bit in COG1FIS1bits
21113 #define G1FIS11 COG1FIS1bits.G1FIS11 // bit 3, shadows bit in COG1FIS1bits
21114 #define FIS12 COG1FIS1bits.FIS12 // bit 4, shadows bit in COG1FIS1bits
21115 #define G1FIS12 COG1FIS1bits.G1FIS12 // bit 4, shadows bit in COG1FIS1bits
21116 #define FIS13 COG1FIS1bits.FIS13 // bit 5, shadows bit in COG1FIS1bits
21117 #define G1FIS13 COG1FIS1bits.G1FIS13 // bit 5, shadows bit in COG1FIS1bits
21118 #define FIS14 COG1FIS1bits.FIS14 // bit 6, shadows bit in COG1FIS1bits
21119 #define G1FIS14 COG1FIS1bits.G1FIS14 // bit 6, shadows bit in COG1FIS1bits
21120 #define FIS15 COG1FIS1bits.FIS15 // bit 7, shadows bit in COG1FIS1bits
21121 #define G1FIS15 COG1FIS1bits.G1FIS15 // bit 7, shadows bit in COG1FIS1bits
21123 #define FSIM0 COG1FSIM0bits.FSIM0 // bit 0, shadows bit in COG1FSIM0bits
21124 #define G1FSIM0 COG1FSIM0bits.G1FSIM0 // bit 0, shadows bit in COG1FSIM0bits
21125 #define FSIM1 COG1FSIM0bits.FSIM1 // bit 1, shadows bit in COG1FSIM0bits
21126 #define G1FSIM1 COG1FSIM0bits.G1FSIM1 // bit 1, shadows bit in COG1FSIM0bits
21127 #define FSIM2 COG1FSIM0bits.FSIM2 // bit 2, shadows bit in COG1FSIM0bits
21128 #define G1FSIM2 COG1FSIM0bits.G1FSIM2 // bit 2, shadows bit in COG1FSIM0bits
21129 #define FSIM3 COG1FSIM0bits.FSIM3 // bit 3, shadows bit in COG1FSIM0bits
21130 #define G1FSIM3 COG1FSIM0bits.G1FSIM3 // bit 3, shadows bit in COG1FSIM0bits
21131 #define FSIM4 COG1FSIM0bits.FSIM4 // bit 4, shadows bit in COG1FSIM0bits
21132 #define G1FSIM4 COG1FSIM0bits.G1FSIM4 // bit 4, shadows bit in COG1FSIM0bits
21133 #define FSIM5 COG1FSIM0bits.FSIM5 // bit 5, shadows bit in COG1FSIM0bits
21134 #define G1FSIM5 COG1FSIM0bits.G1FSIM5 // bit 5, shadows bit in COG1FSIM0bits
21135 #define FSIM6 COG1FSIM0bits.FSIM6 // bit 6, shadows bit in COG1FSIM0bits
21136 #define G1FSIM6 COG1FSIM0bits.G1FSIM6 // bit 6, shadows bit in COG1FSIM0bits
21137 #define FSIM7 COG1FSIM0bits.FSIM7 // bit 7, shadows bit in COG1FSIM0bits
21138 #define G1FSIM7 COG1FSIM0bits.G1FSIM7 // bit 7, shadows bit in COG1FSIM0bits
21140 #define FSIM8 COG1FSIM1bits.FSIM8 // bit 0, shadows bit in COG1FSIM1bits
21141 #define G1FSIM8 COG1FSIM1bits.G1FSIM8 // bit 0, shadows bit in COG1FSIM1bits
21142 #define FSIM9 COG1FSIM1bits.FSIM9 // bit 1, shadows bit in COG1FSIM1bits
21143 #define G1FSIM9 COG1FSIM1bits.G1FSIM9 // bit 1, shadows bit in COG1FSIM1bits
21144 #define FSIM10 COG1FSIM1bits.FSIM10 // bit 2, shadows bit in COG1FSIM1bits
21145 #define G1FSIM10 COG1FSIM1bits.G1FSIM10 // bit 2, shadows bit in COG1FSIM1bits
21146 #define FSIM11 COG1FSIM1bits.FSIM11 // bit 3, shadows bit in COG1FSIM1bits
21147 #define G1FSIM11 COG1FSIM1bits.G1FSIM11 // bit 3, shadows bit in COG1FSIM1bits
21148 #define FSIM12 COG1FSIM1bits.FSIM12 // bit 4, shadows bit in COG1FSIM1bits
21149 #define G1FSIM12 COG1FSIM1bits.G1FSIM12 // bit 4, shadows bit in COG1FSIM1bits
21150 #define FSIM13 COG1FSIM1bits.FSIM13 // bit 5, shadows bit in COG1FSIM1bits
21151 #define G1FSIM13 COG1FSIM1bits.G1FSIM13 // bit 5, shadows bit in COG1FSIM1bits
21152 #define FSIM14 COG1FSIM1bits.FSIM14 // bit 6, shadows bit in COG1FSIM1bits
21153 #define G1FSIM14 COG1FSIM1bits.G1FSIM14 // bit 6, shadows bit in COG1FSIM1bits
21154 #define FSIM15 COG1FSIM1bits.FSIM15 // bit 7, shadows bit in COG1FSIM1bits
21155 #define G1FSIM15 COG1FSIM1bits.G1FSIM15 // bit 7, shadows bit in COG1FSIM1bits
21157 #define PHF0 COG1PHFbits.PHF0 // bit 0, shadows bit in COG1PHFbits
21158 #define G1PHF0 COG1PHFbits.G1PHF0 // bit 0, shadows bit in COG1PHFbits
21159 #define PHF1 COG1PHFbits.PHF1 // bit 1, shadows bit in COG1PHFbits
21160 #define G1PHF1 COG1PHFbits.G1PHF1 // bit 1, shadows bit in COG1PHFbits
21161 #define PHF2 COG1PHFbits.PHF2 // bit 2, shadows bit in COG1PHFbits
21162 #define G1PHF2 COG1PHFbits.G1PHF2 // bit 2, shadows bit in COG1PHFbits
21163 #define PHF3 COG1PHFbits.PHF3 // bit 3, shadows bit in COG1PHFbits
21164 #define G1PHF3 COG1PHFbits.G1PHF3 // bit 3, shadows bit in COG1PHFbits
21165 #define PHF4 COG1PHFbits.PHF4 // bit 4, shadows bit in COG1PHFbits
21166 #define G1PHF4 COG1PHFbits.G1PHF4 // bit 4, shadows bit in COG1PHFbits
21167 #define PHF5 COG1PHFbits.PHF5 // bit 5, shadows bit in COG1PHFbits
21168 #define G1PHF5 COG1PHFbits.G1PHF5 // bit 5, shadows bit in COG1PHFbits
21170 #define PHR0 COG1PHRbits.PHR0 // bit 0, shadows bit in COG1PHRbits
21171 #define G1PHR0 COG1PHRbits.G1PHR0 // bit 0, shadows bit in COG1PHRbits
21172 #define PHR1 COG1PHRbits.PHR1 // bit 1, shadows bit in COG1PHRbits
21173 #define G1PHR1 COG1PHRbits.G1PHR1 // bit 1, shadows bit in COG1PHRbits
21174 #define PHR2 COG1PHRbits.PHR2 // bit 2, shadows bit in COG1PHRbits
21175 #define G1PHR2 COG1PHRbits.G1PHR2 // bit 2, shadows bit in COG1PHRbits
21176 #define PHR3 COG1PHRbits.PHR3 // bit 3, shadows bit in COG1PHRbits
21177 #define G1PHR3 COG1PHRbits.G1PHR3 // bit 3, shadows bit in COG1PHRbits
21178 #define PHR4 COG1PHRbits.PHR4 // bit 4, shadows bit in COG1PHRbits
21179 #define G1PHR4 COG1PHRbits.G1PHR4 // bit 4, shadows bit in COG1PHRbits
21180 #define PHR5 COG1PHRbits.PHR5 // bit 5, shadows bit in COG1PHRbits
21181 #define G1PHR5 COG1PHRbits.G1PHR5 // bit 5, shadows bit in COG1PHRbits
21183 #define RIS0 COG1RIS0bits.RIS0 // bit 0, shadows bit in COG1RIS0bits
21184 #define G1RIS0 COG1RIS0bits.G1RIS0 // bit 0, shadows bit in COG1RIS0bits
21185 #define RIS1 COG1RIS0bits.RIS1 // bit 1, shadows bit in COG1RIS0bits
21186 #define G1RIS1 COG1RIS0bits.G1RIS1 // bit 1, shadows bit in COG1RIS0bits
21187 #define RIS2 COG1RIS0bits.RIS2 // bit 2, shadows bit in COG1RIS0bits
21188 #define G1RIS2 COG1RIS0bits.G1RIS2 // bit 2, shadows bit in COG1RIS0bits
21189 #define RIS3 COG1RIS0bits.RIS3 // bit 3, shadows bit in COG1RIS0bits
21190 #define G1RIS3 COG1RIS0bits.G1RIS3 // bit 3, shadows bit in COG1RIS0bits
21191 #define RIS4 COG1RIS0bits.RIS4 // bit 4, shadows bit in COG1RIS0bits
21192 #define G1RIS4 COG1RIS0bits.G1RIS4 // bit 4, shadows bit in COG1RIS0bits
21193 #define RIS5 COG1RIS0bits.RIS5 // bit 5, shadows bit in COG1RIS0bits
21194 #define G1RIS5 COG1RIS0bits.G1RIS5 // bit 5, shadows bit in COG1RIS0bits
21195 #define RIS6 COG1RIS0bits.RIS6 // bit 6, shadows bit in COG1RIS0bits
21196 #define G1RIS6 COG1RIS0bits.G1RIS6 // bit 6, shadows bit in COG1RIS0bits
21197 #define RIS7 COG1RIS0bits.RIS7 // bit 7, shadows bit in COG1RIS0bits
21198 #define G1RIS7 COG1RIS0bits.G1RIS7 // bit 7, shadows bit in COG1RIS0bits
21200 #define RIS8 COG1RIS1bits.RIS8 // bit 0, shadows bit in COG1RIS1bits
21201 #define G1RIS8 COG1RIS1bits.G1RIS8 // bit 0, shadows bit in COG1RIS1bits
21202 #define RIS9 COG1RIS1bits.RIS9 // bit 1, shadows bit in COG1RIS1bits
21203 #define G1RIS9 COG1RIS1bits.G1RIS9 // bit 1, shadows bit in COG1RIS1bits
21204 #define RIS10 COG1RIS1bits.RIS10 // bit 2, shadows bit in COG1RIS1bits
21205 #define G1RIS10 COG1RIS1bits.G1RIS10 // bit 2, shadows bit in COG1RIS1bits
21206 #define RIS11 COG1RIS1bits.RIS11 // bit 3, shadows bit in COG1RIS1bits
21207 #define G1RIS11 COG1RIS1bits.G1RIS11 // bit 3, shadows bit in COG1RIS1bits
21208 #define RIS12 COG1RIS1bits.RIS12 // bit 4, shadows bit in COG1RIS1bits
21209 #define G1RIS12 COG1RIS1bits.G1RIS12 // bit 4, shadows bit in COG1RIS1bits
21210 #define RIS13 COG1RIS1bits.RIS13 // bit 5, shadows bit in COG1RIS1bits
21211 #define G1RIS13 COG1RIS1bits.G1RIS13 // bit 5, shadows bit in COG1RIS1bits
21212 #define RIS14 COG1RIS1bits.RIS14 // bit 6, shadows bit in COG1RIS1bits
21213 #define G1RIS14 COG1RIS1bits.G1RIS14 // bit 6, shadows bit in COG1RIS1bits
21214 #define RIS15 COG1RIS1bits.RIS15 // bit 7, shadows bit in COG1RIS1bits
21215 #define G1RIS15 COG1RIS1bits.G1RIS15 // bit 7, shadows bit in COG1RIS1bits
21217 #define RSIM0 COG1RSIM0bits.RSIM0 // bit 0, shadows bit in COG1RSIM0bits
21218 #define G1RSIM0 COG1RSIM0bits.G1RSIM0 // bit 0, shadows bit in COG1RSIM0bits
21219 #define RSIM1 COG1RSIM0bits.RSIM1 // bit 1, shadows bit in COG1RSIM0bits
21220 #define G1RSIM1 COG1RSIM0bits.G1RSIM1 // bit 1, shadows bit in COG1RSIM0bits
21221 #define RSIM2 COG1RSIM0bits.RSIM2 // bit 2, shadows bit in COG1RSIM0bits
21222 #define G1RSIM2 COG1RSIM0bits.G1RSIM2 // bit 2, shadows bit in COG1RSIM0bits
21223 #define RSIM3 COG1RSIM0bits.RSIM3 // bit 3, shadows bit in COG1RSIM0bits
21224 #define G1RSIM3 COG1RSIM0bits.G1RSIM3 // bit 3, shadows bit in COG1RSIM0bits
21225 #define RSIM4 COG1RSIM0bits.RSIM4 // bit 4, shadows bit in COG1RSIM0bits
21226 #define G1RSIM4 COG1RSIM0bits.G1RSIM4 // bit 4, shadows bit in COG1RSIM0bits
21227 #define RSIM5 COG1RSIM0bits.RSIM5 // bit 5, shadows bit in COG1RSIM0bits
21228 #define G1RSIM5 COG1RSIM0bits.G1RSIM5 // bit 5, shadows bit in COG1RSIM0bits
21229 #define RSIM6 COG1RSIM0bits.RSIM6 // bit 6, shadows bit in COG1RSIM0bits
21230 #define G1RSIM6 COG1RSIM0bits.G1RSIM6 // bit 6, shadows bit in COG1RSIM0bits
21231 #define RSIM7 COG1RSIM0bits.RSIM7 // bit 7, shadows bit in COG1RSIM0bits
21232 #define G1RSIM7 COG1RSIM0bits.G1RSIM7 // bit 7, shadows bit in COG1RSIM0bits
21234 #define RSIM8 COG1RSIM1bits.RSIM8 // bit 0, shadows bit in COG1RSIM1bits
21235 #define G1RSIM8 COG1RSIM1bits.G1RSIM8 // bit 0, shadows bit in COG1RSIM1bits
21236 #define RSIM9 COG1RSIM1bits.RSIM9 // bit 1, shadows bit in COG1RSIM1bits
21237 #define G1RSIM9 COG1RSIM1bits.G1RSIM9 // bit 1, shadows bit in COG1RSIM1bits
21238 #define RSIM10 COG1RSIM1bits.RSIM10 // bit 2, shadows bit in COG1RSIM1bits
21239 #define G1RSIM10 COG1RSIM1bits.G1RSIM10 // bit 2, shadows bit in COG1RSIM1bits
21240 #define RSIM11 COG1RSIM1bits.RSIM11 // bit 3, shadows bit in COG1RSIM1bits
21241 #define G1RSIM11 COG1RSIM1bits.G1RSIM11 // bit 3, shadows bit in COG1RSIM1bits
21242 #define RSIM12 COG1RSIM1bits.RSIM12 // bit 4, shadows bit in COG1RSIM1bits
21243 #define G1RSIM12 COG1RSIM1bits.G1RSIM12 // bit 4, shadows bit in COG1RSIM1bits
21244 #define RSIM13 COG1RSIM1bits.RSIM13 // bit 5, shadows bit in COG1RSIM1bits
21245 #define G1RSIM13 COG1RSIM1bits.G1RSIM13 // bit 5, shadows bit in COG1RSIM1bits
21246 #define RSIM14 COG1RSIM1bits.RSIM14 // bit 6, shadows bit in COG1RSIM1bits
21247 #define G1RSIM14 COG1RSIM1bits.G1RSIM14 // bit 6, shadows bit in COG1RSIM1bits
21248 #define RSIM15 COG1RSIM1bits.RSIM15 // bit 7, shadows bit in COG1RSIM1bits
21249 #define G1RSIM15 COG1RSIM1bits.G1RSIM15 // bit 7, shadows bit in COG1RSIM1bits
21251 #define STRA COG1STRbits.STRA // bit 0, shadows bit in COG1STRbits
21252 #define G1STRA COG1STRbits.G1STRA // bit 0, shadows bit in COG1STRbits
21253 #define STRB COG1STRbits.STRB // bit 1, shadows bit in COG1STRbits
21254 #define G1STRB COG1STRbits.G1STRB // bit 1, shadows bit in COG1STRbits
21255 #define STRC COG1STRbits.STRC // bit 2, shadows bit in COG1STRbits
21256 #define G1STRC COG1STRbits.G1STRC // bit 2, shadows bit in COG1STRbits
21257 #define STRD COG1STRbits.STRD // bit 3, shadows bit in COG1STRbits
21258 #define G1STRD COG1STRbits.G1STRD // bit 3, shadows bit in COG1STRbits
21259 #define SDATA COG1STRbits.SDATA // bit 4, shadows bit in COG1STRbits
21260 #define G1SDATA COG1STRbits.G1SDATA // bit 4, shadows bit in COG1STRbits
21261 #define SDATB COG1STRbits.SDATB // bit 5, shadows bit in COG1STRbits
21262 #define G1SDATB COG1STRbits.G1SDATB // bit 5, shadows bit in COG1STRbits
21263 #define SDATC COG1STRbits.SDATC // bit 6, shadows bit in COG1STRbits
21264 #define G1SDATC COG1STRbits.G1SDATC // bit 6, shadows bit in COG1STRbits
21265 #define SDATD COG1STRbits.SDATD // bit 7, shadows bit in COG1STRbits
21266 #define G1SDATD COG1STRbits.G1SDATD // bit 7, shadows bit in COG1STRbits
21268 #define REF0 DAC1CON1bits.REF0 // bit 0, shadows bit in DAC1CON1bits
21269 #define DAC1REF0 DAC1CON1bits.DAC1REF0 // bit 0, shadows bit in DAC1CON1bits
21270 #define R0 DAC1CON1bits.R0 // bit 0, shadows bit in DAC1CON1bits
21271 #define DAC1R0 DAC1CON1bits.DAC1R0 // bit 0, shadows bit in DAC1CON1bits
21272 #define REF1 DAC1CON1bits.REF1 // bit 1, shadows bit in DAC1CON1bits
21273 #define DAC1REF1 DAC1CON1bits.DAC1REF1 // bit 1, shadows bit in DAC1CON1bits
21274 #define R1 DAC1CON1bits.R1 // bit 1, shadows bit in DAC1CON1bits
21275 #define DAC1R1 DAC1CON1bits.DAC1R1 // bit 1, shadows bit in DAC1CON1bits
21276 #define REF2 DAC1CON1bits.REF2 // bit 2, shadows bit in DAC1CON1bits
21277 #define DAC1REF2 DAC1CON1bits.DAC1REF2 // bit 2, shadows bit in DAC1CON1bits
21278 #define R2 DAC1CON1bits.R2 // bit 2, shadows bit in DAC1CON1bits
21279 #define DAC1R2 DAC1CON1bits.DAC1R2 // bit 2, shadows bit in DAC1CON1bits
21280 #define REF3 DAC1CON1bits.REF3 // bit 3, shadows bit in DAC1CON1bits
21281 #define DAC1REF3 DAC1CON1bits.DAC1REF3 // bit 3, shadows bit in DAC1CON1bits
21282 #define R3 DAC1CON1bits.R3 // bit 3, shadows bit in DAC1CON1bits
21283 #define DAC1R3 DAC1CON1bits.DAC1R3 // bit 3, shadows bit in DAC1CON1bits
21284 #define REF4 DAC1CON1bits.REF4 // bit 4, shadows bit in DAC1CON1bits
21285 #define DAC1REF4 DAC1CON1bits.DAC1REF4 // bit 4, shadows bit in DAC1CON1bits
21286 #define R4 DAC1CON1bits.R4 // bit 4, shadows bit in DAC1CON1bits
21287 #define DAC1R4 DAC1CON1bits.DAC1R4 // bit 4, shadows bit in DAC1CON1bits
21288 #define REF5 DAC1CON1bits.REF5 // bit 5, shadows bit in DAC1CON1bits
21289 #define DAC1REF5 DAC1CON1bits.DAC1REF5 // bit 5, shadows bit in DAC1CON1bits
21290 #define R5 DAC1CON1bits.R5 // bit 5, shadows bit in DAC1CON1bits
21291 #define DAC1R5 DAC1CON1bits.DAC1R5 // bit 5, shadows bit in DAC1CON1bits
21292 #define REF6 DAC1CON1bits.REF6 // bit 6, shadows bit in DAC1CON1bits
21293 #define DAC1REF6 DAC1CON1bits.DAC1REF6 // bit 6, shadows bit in DAC1CON1bits
21294 #define R6 DAC1CON1bits.R6 // bit 6, shadows bit in DAC1CON1bits
21295 #define DAC1R6 DAC1CON1bits.DAC1R6 // bit 6, shadows bit in DAC1CON1bits
21296 #define REF7 DAC1CON1bits.REF7 // bit 7, shadows bit in DAC1CON1bits
21297 #define DAC1REF7 DAC1CON1bits.DAC1REF7 // bit 7, shadows bit in DAC1CON1bits
21298 #define R7 DAC1CON1bits.R7 // bit 7, shadows bit in DAC1CON1bits
21299 #define DAC1R7 DAC1CON1bits.DAC1R7 // bit 7, shadows bit in DAC1CON1bits
21301 #define REF8 DAC1CON2bits.REF8 // bit 0, shadows bit in DAC1CON2bits
21302 #define DAC1REF8 DAC1CON2bits.DAC1REF8 // bit 0, shadows bit in DAC1CON2bits
21303 #define R8 DAC1CON2bits.R8 // bit 0, shadows bit in DAC1CON2bits
21304 #define DAC1R8 DAC1CON2bits.DAC1R8 // bit 0, shadows bit in DAC1CON2bits
21305 #define REF9 DAC1CON2bits.REF9 // bit 1, shadows bit in DAC1CON2bits
21306 #define DAC1REF9 DAC1CON2bits.DAC1REF9 // bit 1, shadows bit in DAC1CON2bits
21307 #define R9 DAC1CON2bits.R9 // bit 1, shadows bit in DAC1CON2bits
21308 #define DAC1R9 DAC1CON2bits.DAC1R9 // bit 1, shadows bit in DAC1CON2bits
21309 #define REF10 DAC1CON2bits.REF10 // bit 2, shadows bit in DAC1CON2bits
21310 #define DAC1REF10 DAC1CON2bits.DAC1REF10 // bit 2, shadows bit in DAC1CON2bits
21311 #define R10 DAC1CON2bits.R10 // bit 2, shadows bit in DAC1CON2bits
21312 #define DAC1R10 DAC1CON2bits.DAC1R10 // bit 2, shadows bit in DAC1CON2bits
21313 #define REF11 DAC1CON2bits.REF11 // bit 3, shadows bit in DAC1CON2bits
21314 #define DAC1REF11 DAC1CON2bits.DAC1REF11 // bit 3, shadows bit in DAC1CON2bits
21315 #define R11 DAC1CON2bits.R11 // bit 3, shadows bit in DAC1CON2bits
21316 #define DAC1R11 DAC1CON2bits.DAC1R11 // bit 3, shadows bit in DAC1CON2bits
21317 #define REF12 DAC1CON2bits.REF12 // bit 4, shadows bit in DAC1CON2bits
21318 #define DAC1REF12 DAC1CON2bits.DAC1REF12 // bit 4, shadows bit in DAC1CON2bits
21319 #define R12 DAC1CON2bits.R12 // bit 4, shadows bit in DAC1CON2bits
21320 #define DAC1R12 DAC1CON2bits.DAC1R12 // bit 4, shadows bit in DAC1CON2bits
21321 #define REF13 DAC1CON2bits.REF13 // bit 5, shadows bit in DAC1CON2bits
21322 #define DAC1REF13 DAC1CON2bits.DAC1REF13 // bit 5, shadows bit in DAC1CON2bits
21323 #define R13 DAC1CON2bits.R13 // bit 5, shadows bit in DAC1CON2bits
21324 #define DAC1R13 DAC1CON2bits.DAC1R13 // bit 5, shadows bit in DAC1CON2bits
21325 #define REF14 DAC1CON2bits.REF14 // bit 6, shadows bit in DAC1CON2bits
21326 #define DAC1REF14 DAC1CON2bits.DAC1REF14 // bit 6, shadows bit in DAC1CON2bits
21327 #define R14 DAC1CON2bits.R14 // bit 6, shadows bit in DAC1CON2bits
21328 #define DAC1R14 DAC1CON2bits.DAC1R14 // bit 6, shadows bit in DAC1CON2bits
21329 #define REF15 DAC1CON2bits.REF15 // bit 7, shadows bit in DAC1CON2bits
21330 #define DAC1REF15 DAC1CON2bits.DAC1REF15 // bit 7, shadows bit in DAC1CON2bits
21331 #define R15 DAC1CON2bits.R15 // bit 7, shadows bit in DAC1CON2bits
21332 #define DAC1R15 DAC1CON2bits.DAC1R15 // bit 7, shadows bit in DAC1CON2bits
21334 #define DAC1LD DACLDbits.DAC1LD // bit 0
21335 #define DAC2LD DACLDbits.DAC2LD // bit 1
21336 #define DAC5LD DACLDbits.DAC5LD // bit 4
21338 #define TSRNG FVRCONbits.TSRNG // bit 4
21339 #define TSEN FVRCONbits.TSEN // bit 5
21340 #define FVRRDY FVRCONbits.FVRRDY // bit 6
21341 #define FVREN FVRCONbits.FVREN // bit 7
21343 #define HIDB0 HIDRVBbits.HIDB0 // bit 0
21344 #define HIDB1 HIDRVBbits.HIDB1 // bit 1
21346 #define INLVE3 INLVEbits.INLVE3 // bit 3
21348 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
21349 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
21350 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
21351 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
21352 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
21353 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
21354 #define INLVA6 INLVLAbits.INLVA6 // bit 6
21355 #define INLVA7 INLVLAbits.INLVA7 // bit 7
21357 #define INLVB0 INLVLBbits.INLVB0 // bit 0
21358 #define INLVB1 INLVLBbits.INLVB1 // bit 1
21359 #define INLVB2 INLVLBbits.INLVB2 // bit 2
21360 #define INLVB3 INLVLBbits.INLVB3 // bit 3
21361 #define INLVLB4 INLVLBbits.INLVLB4 // bit 4
21362 #define INLVLB5 INLVLBbits.INLVLB5 // bit 5
21363 #define INLVLB6 INLVLBbits.INLVLB6 // bit 6
21364 #define INLVLB7 INLVLBbits.INLVLB7 // bit 7
21366 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
21367 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
21368 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
21369 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
21370 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
21371 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
21372 #define INLVLC6 INLVLCbits.INLVLC6 // bit 6
21373 #define INLVLC7 INLVLCbits.INLVLC7 // bit 7
21375 #define IOCIF INTCONbits.IOCIF // bit 0
21376 #define INTF INTCONbits.INTF // bit 1
21377 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
21378 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
21379 #define IOCIE INTCONbits.IOCIE // bit 3
21380 #define INTE INTCONbits.INTE // bit 4
21381 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
21382 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
21383 #define PEIE INTCONbits.PEIE // bit 6
21384 #define GIE INTCONbits.GIE // bit 7
21386 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
21387 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
21388 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
21389 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
21390 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
21391 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
21392 #define IOCAF6 IOCAFbits.IOCAF6 // bit 6
21393 #define IOCAF7 IOCAFbits.IOCAF7 // bit 7
21395 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
21396 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
21397 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
21398 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
21399 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
21400 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
21401 #define IOCAN6 IOCANbits.IOCAN6 // bit 6
21402 #define IOCAN7 IOCANbits.IOCAN7 // bit 7
21404 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
21405 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
21406 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
21407 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
21408 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
21409 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
21410 #define IOCAP6 IOCAPbits.IOCAP6 // bit 6
21411 #define IOCAP7 IOCAPbits.IOCAP7 // bit 7
21413 #define IOCBF0 IOCBFbits.IOCBF0 // bit 0
21414 #define IOCBF1 IOCBFbits.IOCBF1 // bit 1
21415 #define IOCBF2 IOCBFbits.IOCBF2 // bit 2
21416 #define IOCBF3 IOCBFbits.IOCBF3 // bit 3
21417 #define IOCBF4 IOCBFbits.IOCBF4 // bit 4
21418 #define IOCBF5 IOCBFbits.IOCBF5 // bit 5
21419 #define IOCBF6 IOCBFbits.IOCBF6 // bit 6
21420 #define IOCBF7 IOCBFbits.IOCBF7 // bit 7
21422 #define IOCBN0 IOCBNbits.IOCBN0 // bit 0
21423 #define IOCBN1 IOCBNbits.IOCBN1 // bit 1
21424 #define IOCBN2 IOCBNbits.IOCBN2 // bit 2
21425 #define IOCBN3 IOCBNbits.IOCBN3 // bit 3
21426 #define IOCBN4 IOCBNbits.IOCBN4 // bit 4
21427 #define IOCBN5 IOCBNbits.IOCBN5 // bit 5
21428 #define IOCBN6 IOCBNbits.IOCBN6 // bit 6
21429 #define IOCBN7 IOCBNbits.IOCBN7 // bit 7
21431 #define IOCBP0 IOCBPbits.IOCBP0 // bit 0
21432 #define IOCBP1 IOCBPbits.IOCBP1 // bit 1
21433 #define IOCBP2 IOCBPbits.IOCBP2 // bit 2
21434 #define IOCBP3 IOCBPbits.IOCBP3 // bit 3
21435 #define IOCBP4 IOCBPbits.IOCBP4 // bit 4
21436 #define IOCBP5 IOCBPbits.IOCBP5 // bit 5
21437 #define IOCBP6 IOCBPbits.IOCBP6 // bit 6
21438 #define IOCBP7 IOCBPbits.IOCBP7 // bit 7
21440 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
21441 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
21442 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
21443 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
21444 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
21445 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
21446 #define IOCCF6 IOCCFbits.IOCCF6 // bit 6
21447 #define IOCCF7 IOCCFbits.IOCCF7 // bit 7
21449 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
21450 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
21451 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
21452 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
21453 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
21454 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
21455 #define IOCCN6 IOCCNbits.IOCCN6 // bit 6
21456 #define IOCCN7 IOCCNbits.IOCCN7 // bit 7
21458 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
21459 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
21460 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
21461 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
21462 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
21463 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
21464 #define IOCCP6 IOCCPbits.IOCCP6 // bit 6
21465 #define IOCCP7 IOCCPbits.IOCCP7 // bit 7
21467 #define IOCEF3 IOCEFbits.IOCEF3 // bit 3
21469 #define IOCEN3 IOCENbits.IOCEN3 // bit 3
21471 #define IOCEP3 IOCEPbits.IOCEP3 // bit 3
21473 #define LATA0 LATAbits.LATA0 // bit 0
21474 #define LATA1 LATAbits.LATA1 // bit 1
21475 #define LATA2 LATAbits.LATA2 // bit 2
21476 #define LATA3 LATAbits.LATA3 // bit 3
21477 #define LATA4 LATAbits.LATA4 // bit 4
21478 #define LATA5 LATAbits.LATA5 // bit 5
21479 #define LATA6 LATAbits.LATA6 // bit 6
21480 #define LATA7 LATAbits.LATA7 // bit 7
21482 #define LATB0 LATBbits.LATB0 // bit 0
21483 #define LATB1 LATBbits.LATB1 // bit 1
21484 #define LATB2 LATBbits.LATB2 // bit 2
21485 #define LATB3 LATBbits.LATB3 // bit 3
21486 #define LATB4 LATBbits.LATB4 // bit 4
21487 #define LATB5 LATBbits.LATB5 // bit 5
21488 #define LATB6 LATBbits.LATB6 // bit 6
21489 #define LATB7 LATBbits.LATB7 // bit 7
21491 #define LATC0 LATCbits.LATC0 // bit 0
21492 #define LATC1 LATCbits.LATC1 // bit 1
21493 #define LATC2 LATCbits.LATC2 // bit 2
21494 #define LATC3 LATCbits.LATC3 // bit 3
21495 #define LATC4 LATCbits.LATC4 // bit 4
21496 #define LATC5 LATCbits.LATC5 // bit 5
21497 #define LATC6 LATCbits.LATC6 // bit 6
21498 #define LATC7 LATCbits.LATC7 // bit 7
21500 #define CH0 MD1CARHbits.CH0 // bit 0, shadows bit in MD1CARHbits
21501 #define MD1CH0 MD1CARHbits.MD1CH0 // bit 0, shadows bit in MD1CARHbits
21502 #define CH1 MD1CARHbits.CH1 // bit 1, shadows bit in MD1CARHbits
21503 #define MD1CH1 MD1CARHbits.MD1CH1 // bit 1, shadows bit in MD1CARHbits
21504 #define CH2 MD1CARHbits.CH2 // bit 2, shadows bit in MD1CARHbits
21505 #define MD1CH2 MD1CARHbits.MD1CH2 // bit 2, shadows bit in MD1CARHbits
21506 #define CH3 MD1CARHbits.CH3 // bit 3, shadows bit in MD1CARHbits
21507 #define MD1CH3 MD1CARHbits.MD1CH3 // bit 3, shadows bit in MD1CARHbits
21508 #define CH4 MD1CARHbits.CH4 // bit 4
21510 #define CL0 MD1CARLbits.CL0 // bit 0, shadows bit in MD1CARLbits
21511 #define MD1CL0 MD1CARLbits.MD1CL0 // bit 0, shadows bit in MD1CARLbits
21512 #define CL1 MD1CARLbits.CL1 // bit 1, shadows bit in MD1CARLbits
21513 #define MD1CL1 MD1CARLbits.MD1CL1 // bit 1, shadows bit in MD1CARLbits
21514 #define CL2 MD1CARLbits.CL2 // bit 2, shadows bit in MD1CARLbits
21515 #define MD1CL2 MD1CARLbits.MD1CL2 // bit 2, shadows bit in MD1CARLbits
21516 #define CL3 MD1CARLbits.CL3 // bit 3, shadows bit in MD1CARLbits
21517 #define MD1CL3 MD1CARLbits.MD1CL3 // bit 3, shadows bit in MD1CARLbits
21518 #define CL4 MD1CARLbits.CL4 // bit 4
21520 #define CLSYNC MD1CON1bits.CLSYNC // bit 0, shadows bit in MD1CON1bits
21521 #define MD1CLSYNC MD1CON1bits.MD1CLSYNC // bit 0, shadows bit in MD1CON1bits
21522 #define CLPOL MD1CON1bits.CLPOL // bit 1, shadows bit in MD1CON1bits
21523 #define MD1CLPOL MD1CON1bits.MD1CLPOL // bit 1, shadows bit in MD1CON1bits
21524 #define CHSYNC MD1CON1bits.CHSYNC // bit 4, shadows bit in MD1CON1bits
21525 #define MD1CHSYNC MD1CON1bits.MD1CHSYNC // bit 4, shadows bit in MD1CON1bits
21526 #define CHPOL MD1CON1bits.CHPOL // bit 5, shadows bit in MD1CON1bits
21527 #define MD1CHPOL MD1CON1bits.MD1CHPOL // bit 5, shadows bit in MD1CON1bits
21529 #define MS0 MD1SRCbits.MS0 // bit 0, shadows bit in MD1SRCbits
21530 #define MD1MS0 MD1SRCbits.MD1MS0 // bit 0, shadows bit in MD1SRCbits
21531 #define MS1 MD1SRCbits.MS1 // bit 1, shadows bit in MD1SRCbits
21532 #define MD1MS1 MD1SRCbits.MD1MS1 // bit 1, shadows bit in MD1SRCbits
21533 #define MS2 MD1SRCbits.MS2 // bit 2, shadows bit in MD1SRCbits
21534 #define MD1MS2 MD1SRCbits.MD1MS2 // bit 2, shadows bit in MD1SRCbits
21535 #define MS3 MD1SRCbits.MS3 // bit 3, shadows bit in MD1SRCbits
21536 #define MD1MS3 MD1SRCbits.MD1MS3 // bit 3, shadows bit in MD1SRCbits
21537 #define MS4 MD1SRCbits.MS4 // bit 4, shadows bit in MD1SRCbits
21538 #define MD1MS4 MD1SRCbits.MD1MS4 // bit 4, shadows bit in MD1SRCbits
21540 #define ODA0 ODCONAbits.ODA0 // bit 0
21541 #define ODA1 ODCONAbits.ODA1 // bit 1
21542 #define ODA2 ODCONAbits.ODA2 // bit 2
21543 #define ODA3 ODCONAbits.ODA3 // bit 3
21544 #define ODA4 ODCONAbits.ODA4 // bit 4
21545 #define ODA5 ODCONAbits.ODA5 // bit 5
21546 #define ODA6 ODCONAbits.ODA6 // bit 6
21547 #define ODA7 ODCONAbits.ODA7 // bit 7
21549 #define ODC0 ODCONCbits.ODC0 // bit 0
21550 #define ODC1 ODCONCbits.ODC1 // bit 1
21551 #define ODC2 ODCONCbits.ODC2 // bit 2
21552 #define ODC3 ODCONCbits.ODC3 // bit 3
21553 #define ODC4 ODCONCbits.ODC4 // bit 4
21554 #define ODC5 ODCONCbits.ODC5 // bit 5
21555 #define ODC6 ODCONCbits.ODC6 // bit 6
21556 #define ODC7 ODCONCbits.ODC7 // bit 7
21558 #define PS0 OPTION_REGbits.PS0 // bit 0
21559 #define PS1 OPTION_REGbits.PS1 // bit 1
21560 #define PS2 OPTION_REGbits.PS2 // bit 2
21561 #define PSA OPTION_REGbits.PSA // bit 3
21562 #define TMR0SE OPTION_REGbits.TMR0SE // bit 4, shadows bit in OPTION_REGbits
21563 #define T0SE OPTION_REGbits.T0SE // bit 4, shadows bit in OPTION_REGbits
21564 #define TMR0CS OPTION_REGbits.TMR0CS // bit 5, shadows bit in OPTION_REGbits
21565 #define T0CS OPTION_REGbits.T0CS // bit 5, shadows bit in OPTION_REGbits
21566 #define INTEDG OPTION_REGbits.INTEDG // bit 6
21567 #define NOT_WPUEN OPTION_REGbits.NOT_WPUEN // bit 7
21569 #define SCS0 OSCCONbits.SCS0 // bit 0
21570 #define SCS1 OSCCONbits.SCS1 // bit 1
21571 #define IRCF0 OSCCONbits.IRCF0 // bit 3
21572 #define IRCF1 OSCCONbits.IRCF1 // bit 4
21573 #define IRCF2 OSCCONbits.IRCF2 // bit 5
21574 #define IRCF3 OSCCONbits.IRCF3 // bit 6
21575 #define SPLLEN OSCCONbits.SPLLEN // bit 7
21577 #define HFIOFS OSCSTATbits.HFIOFS // bit 0
21578 #define LFIOFR OSCSTATbits.LFIOFR // bit 1
21579 #define MFIOFR OSCSTATbits.MFIOFR // bit 2
21580 #define HFIOFL OSCSTATbits.HFIOFL // bit 3
21581 #define HFIOFR OSCSTATbits.HFIOFR // bit 4
21582 #define OSTS OSCSTATbits.OSTS // bit 5
21583 #define PLLR OSCSTATbits.PLLR // bit 6
21584 #define SOSCR OSCSTATbits.SOSCR // bit 7
21586 #define TUN0 OSCTUNEbits.TUN0 // bit 0
21587 #define TUN1 OSCTUNEbits.TUN1 // bit 1
21588 #define TUN2 OSCTUNEbits.TUN2 // bit 2
21589 #define TUN3 OSCTUNEbits.TUN3 // bit 3
21590 #define TUN4 OSCTUNEbits.TUN4 // bit 4
21591 #define TUN5 OSCTUNEbits.TUN5 // bit 5
21593 #define NOT_BOR PCONbits.NOT_BOR // bit 0
21594 #define NOT_POR PCONbits.NOT_POR // bit 1
21595 #define NOT_RI PCONbits.NOT_RI // bit 2
21596 #define NOT_RMCLR PCONbits.NOT_RMCLR // bit 3
21597 #define NOT_RWDT PCONbits.NOT_RWDT // bit 4
21598 #define STKUNF PCONbits.STKUNF // bit 6
21599 #define STKOVF PCONbits.STKOVF // bit 7
21601 #define TMR1IE PIE1bits.TMR1IE // bit 0
21602 #define TMR2IE PIE1bits.TMR2IE // bit 1
21603 #define CCP1IE PIE1bits.CCP1IE // bit 2, shadows bit in PIE1bits
21604 #define CCPIE PIE1bits.CCPIE // bit 2, shadows bit in PIE1bits
21605 #define SSP1IE PIE1bits.SSP1IE // bit 3
21606 #define TXIE PIE1bits.TXIE // bit 4
21607 #define RCIE PIE1bits.RCIE // bit 5
21608 #define ADIE PIE1bits.ADIE // bit 6
21609 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
21611 #define CCP2IE PIE2bits.CCP2IE // bit 0
21612 #define C3IE PIE2bits.C3IE // bit 1
21613 #define C4IE PIE2bits.C4IE // bit 2
21614 #define BCL1IE PIE2bits.BCL1IE // bit 3
21615 #define COGIE PIE2bits.COGIE // bit 4
21616 #define C1IE PIE2bits.C1IE // bit 5
21617 #define C2IE PIE2bits.C2IE // bit 6
21618 #define OSFIE PIE2bits.OSFIE // bit 7
21620 #define CLC1IE PIE3bits.CLC1IE // bit 0
21621 #define CLC2IE PIE3bits.CLC2IE // bit 1
21622 #define CLC3IE PIE3bits.CLC3IE // bit 2
21623 #define CLC4IE PIE3bits.CLC4IE // bit 3
21624 #define ZCDIE PIE3bits.ZCDIE // bit 4
21625 #define COG2IE PIE3bits.COG2IE // bit 5
21627 #define TMR4IE PIE4bits.TMR4IE // bit 0
21628 #define TMR6IE PIE4bits.TMR6IE // bit 1
21629 #define TMR3IE PIE4bits.TMR3IE // bit 2
21630 #define TMR3GIE PIE4bits.TMR3GIE // bit 3
21631 #define TMR5IE PIE4bits.TMR5IE // bit 4
21632 #define TMR5GIE PIE4bits.TMR5GIE // bit 5
21633 #define TMR8IE PIE4bits.TMR8IE // bit 6
21635 #define C5IE PIE5bits.C5IE // bit 0
21636 #define C6IE PIE5bits.C6IE // bit 1
21637 #define COG3IE PIE5bits.COG3IE // bit 4
21638 #define CCP7IE PIE5bits.CCP7IE // bit 6
21640 #define PWM5IE PIE6bits.PWM5IE // bit 0
21641 #define PWM6IE PIE6bits.PWM6IE // bit 1
21642 #define PWM11IE PIE6bits.PWM11IE // bit 2
21644 #define TMR1IF PIR1bits.TMR1IF // bit 0
21645 #define TMR2IF PIR1bits.TMR2IF // bit 1
21646 #define CCP1IF PIR1bits.CCP1IF // bit 2, shadows bit in PIR1bits
21647 #define CCPIF PIR1bits.CCPIF // bit 2, shadows bit in PIR1bits
21648 #define SSP1IF PIR1bits.SSP1IF // bit 3
21649 #define TXIF PIR1bits.TXIF // bit 4
21650 #define RCIF PIR1bits.RCIF // bit 5
21651 #define ADIF PIR1bits.ADIF // bit 6
21652 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
21654 #define CCP2IF PIR2bits.CCP2IF // bit 0
21655 #define C3IF PIR2bits.C3IF // bit 1
21656 #define C4IF PIR2bits.C4IF // bit 2
21657 #define BCL1IF PIR2bits.BCL1IF // bit 3
21658 #define COG1IF PIR2bits.COG1IF // bit 4
21659 #define C1IF PIR2bits.C1IF // bit 5
21660 #define C2IF PIR2bits.C2IF // bit 6
21661 #define OSFIF PIR2bits.OSFIF // bit 7
21663 #define CLC1IF PIR3bits.CLC1IF // bit 0
21664 #define CLC2IF PIR3bits.CLC2IF // bit 1
21665 #define CLC3IF PIR3bits.CLC3IF // bit 2
21666 #define CLC4IF PIR3bits.CLC4IF // bit 3
21667 #define ZCDIF PIR3bits.ZCDIF // bit 4
21668 #define COG2IF PIR3bits.COG2IF // bit 5
21670 #define TMR4IF PIR4bits.TMR4IF // bit 0
21671 #define TMR6IF PIR4bits.TMR6IF // bit 1
21672 #define TMR3IF PIR4bits.TMR3IF // bit 2
21673 #define TMR3GIF PIR4bits.TMR3GIF // bit 3
21674 #define TMR5IF PIR4bits.TMR5IF // bit 4
21675 #define TMR5GIF PIR4bits.TMR5GIF // bit 5
21676 #define TMR8IF PIR4bits.TMR8IF // bit 6
21678 #define C5IF PIR5bits.C5IF // bit 0
21679 #define C6IF PIR5bits.C6IF // bit 1
21680 #define COG3IF PIR5bits.COG3IF // bit 4
21681 #define CCP7IF PIR5bits.CCP7IF // bit 6
21683 #define PWM5IF PIR6bits.PWM5IF // bit 0
21684 #define PWM6IF PIR6bits.PWM6IF // bit 1
21685 #define PWM11IF PIR6bits.PWM11IF // bit 2
21687 #define RD PMCON1bits.RD // bit 0
21688 #define WR PMCON1bits.WR // bit 1
21689 #define WREN PMCON1bits.WREN // bit 2
21690 #define WRERR PMCON1bits.WRERR // bit 3
21691 #define FREE PMCON1bits.FREE // bit 4
21692 #define LWLO PMCON1bits.LWLO // bit 5
21693 #define CFGS PMCON1bits.CFGS // bit 6
21695 #define RA0 PORTAbits.RA0 // bit 0
21696 #define RA1 PORTAbits.RA1 // bit 1
21697 #define RA2 PORTAbits.RA2 // bit 2
21698 #define RA3 PORTAbits.RA3 // bit 3
21699 #define RA4 PORTAbits.RA4 // bit 4
21700 #define RA5 PORTAbits.RA5 // bit 5
21701 #define RA6 PORTAbits.RA6 // bit 6
21702 #define RA7 PORTAbits.RA7 // bit 7
21704 #define RB0 PORTBbits.RB0 // bit 0
21705 #define RB1 PORTBbits.RB1 // bit 1
21706 #define RB2 PORTBbits.RB2 // bit 2
21707 #define RB3 PORTBbits.RB3 // bit 3
21708 #define RB4 PORTBbits.RB4 // bit 4
21709 #define RB5 PORTBbits.RB5 // bit 5
21710 #define RB6 PORTBbits.RB6 // bit 6
21711 #define RB7 PORTBbits.RB7 // bit 7
21713 #define RC0 PORTCbits.RC0 // bit 0
21714 #define RC1 PORTCbits.RC1 // bit 1
21715 #define RC2 PORTCbits.RC2 // bit 2
21716 #define RC3 PORTCbits.RC3 // bit 3
21717 #define RC4 PORTCbits.RC4 // bit 4
21718 #define RC5 PORTCbits.RC5 // bit 5
21719 #define RC6 PORTCbits.RC6 // bit 6
21720 #define RC7 PORTCbits.RC7 // bit 7
21722 #define RE3 PORTEbits.RE3 // bit 3
21724 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
21726 #define RPOL PRG1CON1bits.RPOL // bit 0, shadows bit in PRG1CON1bits
21727 #define RG1RPOL PRG1CON1bits.RG1RPOL // bit 0, shadows bit in PRG1CON1bits
21728 #define FPOL PRG1CON1bits.FPOL // bit 1, shadows bit in PRG1CON1bits
21729 #define RG1FPOL PRG1CON1bits.RG1FPOL // bit 1, shadows bit in PRG1CON1bits
21730 #define RDY PRG1CON1bits.RDY // bit 2, shadows bit in PRG1CON1bits
21731 #define RG1RDY PRG1CON1bits.RG1RDY // bit 2, shadows bit in PRG1CON1bits
21733 #define ISET0 PRG1CON2bits.ISET0 // bit 0, shadows bit in PRG1CON2bits
21734 #define RG1ISET0 PRG1CON2bits.RG1ISET0 // bit 0, shadows bit in PRG1CON2bits
21735 #define ISET1 PRG1CON2bits.ISET1 // bit 1, shadows bit in PRG1CON2bits
21736 #define RG1ISET1 PRG1CON2bits.RG1ISET1 // bit 1, shadows bit in PRG1CON2bits
21737 #define ISET2 PRG1CON2bits.ISET2 // bit 2, shadows bit in PRG1CON2bits
21738 #define RG1ISET2 PRG1CON2bits.RG1ISET2 // bit 2, shadows bit in PRG1CON2bits
21739 #define ISET3 PRG1CON2bits.ISET3 // bit 3, shadows bit in PRG1CON2bits
21740 #define RG1ISET3 PRG1CON2bits.RG1ISET3 // bit 3, shadows bit in PRG1CON2bits
21741 #define ISET4 PRG1CON2bits.ISET4 // bit 4, shadows bit in PRG1CON2bits
21742 #define RG1ISET4 PRG1CON2bits.RG1ISET4 // bit 4, shadows bit in PRG1CON2bits
21744 #define FTSS0 PRG1FTSSbits.FTSS0 // bit 0, shadows bit in PRG1FTSSbits
21745 #define RG1FTSS0 PRG1FTSSbits.RG1FTSS0 // bit 0, shadows bit in PRG1FTSSbits
21746 #define FTSS1 PRG1FTSSbits.FTSS1 // bit 1, shadows bit in PRG1FTSSbits
21747 #define RG1FTSS1 PRG1FTSSbits.RG1FTSS1 // bit 1, shadows bit in PRG1FTSSbits
21748 #define FTSS2 PRG1FTSSbits.FTSS2 // bit 2, shadows bit in PRG1FTSSbits
21749 #define RG1FTSS2 PRG1FTSSbits.RG1FTSS2 // bit 2, shadows bit in PRG1FTSSbits
21750 #define FTSS3 PRG1FTSSbits.FTSS3 // bit 3, shadows bit in PRG1FTSSbits
21751 #define RG1FTSS3 PRG1FTSSbits.RG1FTSS3 // bit 3, shadows bit in PRG1FTSSbits
21753 #define INS0 PRG1INSbits.INS0 // bit 0, shadows bit in PRG1INSbits
21754 #define RG1INS0 PRG1INSbits.RG1INS0 // bit 0, shadows bit in PRG1INSbits
21755 #define INS1 PRG1INSbits.INS1 // bit 1, shadows bit in PRG1INSbits
21756 #define RG1INS1 PRG1INSbits.RG1INS1 // bit 1, shadows bit in PRG1INSbits
21757 #define INS2 PRG1INSbits.INS2 // bit 2, shadows bit in PRG1INSbits
21758 #define RG1INS2 PRG1INSbits.RG1INS2 // bit 2, shadows bit in PRG1INSbits
21759 #define INS3 PRG1INSbits.INS3 // bit 3, shadows bit in PRG1INSbits
21760 #define RG1INS3 PRG1INSbits.RG1INS3 // bit 3, shadows bit in PRG1INSbits
21762 #define RTSS0 PRG1RTSSbits.RTSS0 // bit 0, shadows bit in PRG1RTSSbits
21763 #define RG1RTSS0 PRG1RTSSbits.RG1RTSS0 // bit 0, shadows bit in PRG1RTSSbits
21764 #define RTSS1 PRG1RTSSbits.RTSS1 // bit 1, shadows bit in PRG1RTSSbits
21765 #define RG1RTSS1 PRG1RTSSbits.RG1RTSS1 // bit 1, shadows bit in PRG1RTSSbits
21766 #define RTSS2 PRG1RTSSbits.RTSS2 // bit 2, shadows bit in PRG1RTSSbits
21767 #define RG1RTSS2 PRG1RTSSbits.RG1RTSS2 // bit 2, shadows bit in PRG1RTSSbits
21768 #define RTSS3 PRG1RTSSbits.RTSS3 // bit 3, shadows bit in PRG1RTSSbits
21769 #define RG1RTSS3 PRG1RTSSbits.RG1RTSS3 // bit 3, shadows bit in PRG1RTSSbits
21771 #define DC2 PWM3DCHbits.DC2 // bit 0, shadows bit in PWM3DCHbits
21772 #define PWM3DC2 PWM3DCHbits.PWM3DC2 // bit 0, shadows bit in PWM3DCHbits
21773 #define PWMPW2 PWM3DCHbits.PWMPW2 // bit 0, shadows bit in PWM3DCHbits
21774 #define DC3 PWM3DCHbits.DC3 // bit 1, shadows bit in PWM3DCHbits
21775 #define PWM3DC3 PWM3DCHbits.PWM3DC3 // bit 1, shadows bit in PWM3DCHbits
21776 #define PWMPW3 PWM3DCHbits.PWMPW3 // bit 1, shadows bit in PWM3DCHbits
21777 #define DC4 PWM3DCHbits.DC4 // bit 2, shadows bit in PWM3DCHbits
21778 #define PWM3DC4 PWM3DCHbits.PWM3DC4 // bit 2, shadows bit in PWM3DCHbits
21779 #define PWMPW4 PWM3DCHbits.PWMPW4 // bit 2, shadows bit in PWM3DCHbits
21780 #define DC5 PWM3DCHbits.DC5 // bit 3, shadows bit in PWM3DCHbits
21781 #define PWM3DC5 PWM3DCHbits.PWM3DC5 // bit 3, shadows bit in PWM3DCHbits
21782 #define PWMPW5 PWM3DCHbits.PWMPW5 // bit 3, shadows bit in PWM3DCHbits
21783 #define DC6 PWM3DCHbits.DC6 // bit 4, shadows bit in PWM3DCHbits
21784 #define PWM3DC6 PWM3DCHbits.PWM3DC6 // bit 4, shadows bit in PWM3DCHbits
21785 #define PWMPW6 PWM3DCHbits.PWMPW6 // bit 4, shadows bit in PWM3DCHbits
21786 #define DC7 PWM3DCHbits.DC7 // bit 5, shadows bit in PWM3DCHbits
21787 #define PWM3DC7 PWM3DCHbits.PWM3DC7 // bit 5, shadows bit in PWM3DCHbits
21788 #define PWMPW7 PWM3DCHbits.PWMPW7 // bit 5, shadows bit in PWM3DCHbits
21789 #define DC8 PWM3DCHbits.DC8 // bit 6, shadows bit in PWM3DCHbits
21790 #define PWM3DC8 PWM3DCHbits.PWM3DC8 // bit 6, shadows bit in PWM3DCHbits
21791 #define PWMPW8 PWM3DCHbits.PWMPW8 // bit 6, shadows bit in PWM3DCHbits
21792 #define DC9 PWM3DCHbits.DC9 // bit 7, shadows bit in PWM3DCHbits
21793 #define PWM3DC9 PWM3DCHbits.PWM3DC9 // bit 7, shadows bit in PWM3DCHbits
21794 #define PWMPW9 PWM3DCHbits.PWMPW9 // bit 7, shadows bit in PWM3DCHbits
21796 #define DC0 PWM3DCLbits.DC0 // bit 6, shadows bit in PWM3DCLbits
21797 #define PWM3DC0 PWM3DCLbits.PWM3DC0 // bit 6, shadows bit in PWM3DCLbits
21798 #define PWMPW0 PWM3DCLbits.PWMPW0 // bit 6, shadows bit in PWM3DCLbits
21799 #define DC1 PWM3DCLbits.DC1 // bit 7, shadows bit in PWM3DCLbits
21800 #define PWM3DC1 PWM3DCLbits.PWM3DC1 // bit 7, shadows bit in PWM3DCLbits
21801 #define PWMPW1 PWM3DCLbits.PWMPW1 // bit 7, shadows bit in PWM3DCLbits
21803 #define PWM5DCH0 PWM5DCHbits.PWM5DCH0 // bit 0
21804 #define PWM5DCH1 PWM5DCHbits.PWM5DCH1 // bit 1
21805 #define PWM5DCH2 PWM5DCHbits.PWM5DCH2 // bit 2
21806 #define PWM5DCH3 PWM5DCHbits.PWM5DCH3 // bit 3
21807 #define PWM5DCH4 PWM5DCHbits.PWM5DCH4 // bit 4
21808 #define PWM5DCH5 PWM5DCHbits.PWM5DCH5 // bit 5
21809 #define PWM5DCH6 PWM5DCHbits.PWM5DCH6 // bit 6
21810 #define PWM5DCH7 PWM5DCHbits.PWM5DCH7 // bit 7
21812 #define PWM5DCL0 PWM5DCLbits.PWM5DCL0 // bit 0
21813 #define PWM5DCL1 PWM5DCLbits.PWM5DCL1 // bit 1
21814 #define PWM5DCL2 PWM5DCLbits.PWM5DCL2 // bit 2
21815 #define PWM5DCL3 PWM5DCLbits.PWM5DCL3 // bit 3
21816 #define PWM5DCL4 PWM5DCLbits.PWM5DCL4 // bit 4
21817 #define PWM5DCL5 PWM5DCLbits.PWM5DCL5 // bit 5
21818 #define PWM5DCL6 PWM5DCLbits.PWM5DCL6 // bit 6
21819 #define PWM5DCL7 PWM5DCLbits.PWM5DCL7 // bit 7
21821 #define PRIE PWM5INTCONbits.PRIE // bit 0, shadows bit in PWM5INTCONbits
21822 #define PWM5PRIE PWM5INTCONbits.PWM5PRIE // bit 0, shadows bit in PWM5INTCONbits
21823 #define DCIE PWM5INTCONbits.DCIE // bit 1, shadows bit in PWM5INTCONbits
21824 #define PWM5DCIE PWM5INTCONbits.PWM5DCIE // bit 1, shadows bit in PWM5INTCONbits
21825 #define PHIE PWM5INTCONbits.PHIE // bit 2, shadows bit in PWM5INTCONbits
21826 #define PWM5PHIE PWM5INTCONbits.PWM5PHIE // bit 2, shadows bit in PWM5INTCONbits
21827 #define OFIE PWM5INTCONbits.OFIE // bit 3, shadows bit in PWM5INTCONbits
21828 #define PWM5OFIE PWM5INTCONbits.PWM5OFIE // bit 3, shadows bit in PWM5INTCONbits
21830 #define PRIF PWM5INTFbits.PRIF // bit 0, shadows bit in PWM5INTFbits
21831 #define PWM5PRIF PWM5INTFbits.PWM5PRIF // bit 0, shadows bit in PWM5INTFbits
21832 #define DCIF PWM5INTFbits.DCIF // bit 1, shadows bit in PWM5INTFbits
21833 #define PWM5DCIF PWM5INTFbits.PWM5DCIF // bit 1, shadows bit in PWM5INTFbits
21834 #define PHIF PWM5INTFbits.PHIF // bit 2, shadows bit in PWM5INTFbits
21835 #define PWM5PHIF PWM5INTFbits.PWM5PHIF // bit 2, shadows bit in PWM5INTFbits
21836 #define OFIF PWM5INTFbits.OFIF // bit 3, shadows bit in PWM5INTFbits
21837 #define PWM5OFIF PWM5INTFbits.PWM5OFIF // bit 3, shadows bit in PWM5INTFbits
21839 #define PWM5LDS0 PWM5LDCONbits.PWM5LDS0 // bit 0, shadows bit in PWM5LDCONbits
21840 #define LDS0 PWM5LDCONbits.LDS0 // bit 0, shadows bit in PWM5LDCONbits
21841 #define PWM5LDS1 PWM5LDCONbits.PWM5LDS1 // bit 1, shadows bit in PWM5LDCONbits
21842 #define LDS1 PWM5LDCONbits.LDS1 // bit 1, shadows bit in PWM5LDCONbits
21843 #define LDT PWM5LDCONbits.LDT // bit 6, shadows bit in PWM5LDCONbits
21844 #define PWM5LDM PWM5LDCONbits.PWM5LDM // bit 6, shadows bit in PWM5LDCONbits
21845 #define LDA PWM5LDCONbits.LDA // bit 7, shadows bit in PWM5LDCONbits
21846 #define PWM5LD PWM5LDCONbits.PWM5LD // bit 7, shadows bit in PWM5LDCONbits
21848 #define PWM5OFS0 PWM5OFCONbits.PWM5OFS0 // bit 0, shadows bit in PWM5OFCONbits
21849 #define OFS0 PWM5OFCONbits.OFS0 // bit 0, shadows bit in PWM5OFCONbits
21850 #define PWM5OFS1 PWM5OFCONbits.PWM5OFS1 // bit 1, shadows bit in PWM5OFCONbits
21851 #define OFS1 PWM5OFCONbits.OFS1 // bit 1, shadows bit in PWM5OFCONbits
21852 #define OFO PWM5OFCONbits.OFO // bit 4, shadows bit in PWM5OFCONbits
21853 #define PWM5OFMC PWM5OFCONbits.PWM5OFMC // bit 4, shadows bit in PWM5OFCONbits
21854 #define PWM5OFM0 PWM5OFCONbits.PWM5OFM0 // bit 5, shadows bit in PWM5OFCONbits
21855 #define OFM0 PWM5OFCONbits.OFM0 // bit 5, shadows bit in PWM5OFCONbits
21856 #define PWM5OFM1 PWM5OFCONbits.PWM5OFM1 // bit 6, shadows bit in PWM5OFCONbits
21857 #define OFM1 PWM5OFCONbits.OFM1 // bit 6, shadows bit in PWM5OFCONbits
21859 #define PWM5OFH0 PWM5OFHbits.PWM5OFH0 // bit 0
21860 #define PWM5OFH1 PWM5OFHbits.PWM5OFH1 // bit 1
21861 #define PWM5OFH2 PWM5OFHbits.PWM5OFH2 // bit 2
21862 #define PWM5OFH3 PWM5OFHbits.PWM5OFH3 // bit 3
21863 #define PWM5OFH4 PWM5OFHbits.PWM5OFH4 // bit 4
21864 #define PWM5OFH5 PWM5OFHbits.PWM5OFH5 // bit 5
21865 #define PWM5OFH6 PWM5OFHbits.PWM5OFH6 // bit 6
21866 #define PWM5OFH7 PWM5OFHbits.PWM5OFH7 // bit 7
21868 #define PWM5OFL0 PWM5OFLbits.PWM5OFL0 // bit 0
21869 #define PWM5OFL1 PWM5OFLbits.PWM5OFL1 // bit 1
21870 #define PWM5OFL2 PWM5OFLbits.PWM5OFL2 // bit 2
21871 #define PWM5OFL3 PWM5OFLbits.PWM5OFL3 // bit 3
21872 #define PWM5OFL4 PWM5OFLbits.PWM5OFL4 // bit 4
21873 #define PWM5OFL5 PWM5OFLbits.PWM5OFL5 // bit 5
21874 #define PWM5OFL6 PWM5OFLbits.PWM5OFL6 // bit 6
21875 #define PWM5OFL7 PWM5OFLbits.PWM5OFL7 // bit 7
21877 #define PWM5PHH0 PWM5PHHbits.PWM5PHH0 // bit 0
21878 #define PWM5PHH1 PWM5PHHbits.PWM5PHH1 // bit 1
21879 #define PWM5PHH2 PWM5PHHbits.PWM5PHH2 // bit 2
21880 #define PWM5PHH3 PWM5PHHbits.PWM5PHH3 // bit 3
21881 #define PWM5PHH4 PWM5PHHbits.PWM5PHH4 // bit 4
21882 #define PWM5PHH5 PWM5PHHbits.PWM5PHH5 // bit 5
21883 #define PWM5PHH6 PWM5PHHbits.PWM5PHH6 // bit 6
21884 #define PWM5PHH7 PWM5PHHbits.PWM5PHH7 // bit 7
21886 #define PWM5PHL0 PWM5PHLbits.PWM5PHL0 // bit 0
21887 #define PWM5PHL1 PWM5PHLbits.PWM5PHL1 // bit 1
21888 #define PWM5PHL2 PWM5PHLbits.PWM5PHL2 // bit 2
21889 #define PWM5PHL3 PWM5PHLbits.PWM5PHL3 // bit 3
21890 #define PWM5PHL4 PWM5PHLbits.PWM5PHL4 // bit 4
21891 #define PWM5PHL5 PWM5PHLbits.PWM5PHL5 // bit 5
21892 #define PWM5PHL6 PWM5PHLbits.PWM5PHL6 // bit 6
21893 #define PWM5PHL7 PWM5PHLbits.PWM5PHL7 // bit 7
21895 #define PWM5PRH0 PWM5PRHbits.PWM5PRH0 // bit 0
21896 #define PWM5PRH1 PWM5PRHbits.PWM5PRH1 // bit 1
21897 #define PWM5PRH2 PWM5PRHbits.PWM5PRH2 // bit 2
21898 #define PWM5PRH3 PWM5PRHbits.PWM5PRH3 // bit 3
21899 #define PWM5PRH4 PWM5PRHbits.PWM5PRH4 // bit 4
21900 #define PWM5PRH5 PWM5PRHbits.PWM5PRH5 // bit 5
21901 #define PWM5PRH6 PWM5PRHbits.PWM5PRH6 // bit 6
21902 #define PWM5PRH7 PWM5PRHbits.PWM5PRH7 // bit 7
21904 #define PWM5PRL0 PWM5PRLbits.PWM5PRL0 // bit 0
21905 #define PWM5PRL1 PWM5PRLbits.PWM5PRL1 // bit 1
21906 #define PWM5PRL2 PWM5PRLbits.PWM5PRL2 // bit 2
21907 #define PWM5PRL3 PWM5PRLbits.PWM5PRL3 // bit 3
21908 #define PWM5PRL4 PWM5PRLbits.PWM5PRL4 // bit 4
21909 #define PWM5PRL5 PWM5PRLbits.PWM5PRL5 // bit 5
21910 #define PWM5PRL6 PWM5PRLbits.PWM5PRL6 // bit 6
21911 #define PWM5PRL7 PWM5PRLbits.PWM5PRL7 // bit 7
21913 #define PWM5TMRH0 PWM5TMRHbits.PWM5TMRH0 // bit 0
21914 #define PWM5TMRH1 PWM5TMRHbits.PWM5TMRH1 // bit 1
21915 #define PWM5TMRH2 PWM5TMRHbits.PWM5TMRH2 // bit 2
21916 #define PWM5TMRH3 PWM5TMRHbits.PWM5TMRH3 // bit 3
21917 #define PWM5TMRH4 PWM5TMRHbits.PWM5TMRH4 // bit 4
21918 #define PWM5TMRH5 PWM5TMRHbits.PWM5TMRH5 // bit 5
21919 #define PWM5TMRH6 PWM5TMRHbits.PWM5TMRH6 // bit 6
21920 #define PWM5TMRH7 PWM5TMRHbits.PWM5TMRH7 // bit 7
21922 #define PWM5TMRL0 PWM5TMRLbits.PWM5TMRL0 // bit 0
21923 #define PWM5TMRL1 PWM5TMRLbits.PWM5TMRL1 // bit 1
21924 #define PWM5TMRL2 PWM5TMRLbits.PWM5TMRL2 // bit 2
21925 #define PWM5TMRL3 PWM5TMRLbits.PWM5TMRL3 // bit 3
21926 #define PWM5TMRL4 PWM5TMRLbits.PWM5TMRL4 // bit 4
21927 #define PWM5TMRL5 PWM5TMRLbits.PWM5TMRL5 // bit 5
21928 #define PWM5TMRL6 PWM5TMRLbits.PWM5TMRL6 // bit 6
21929 #define PWM5TMRL7 PWM5TMRLbits.PWM5TMRL7 // bit 7
21931 #define PWM6DCH0 PWM6DCHbits.PWM6DCH0 // bit 0
21932 #define PWM6DCH1 PWM6DCHbits.PWM6DCH1 // bit 1
21933 #define PWM6DCH2 PWM6DCHbits.PWM6DCH2 // bit 2
21934 #define PWM6DCH3 PWM6DCHbits.PWM6DCH3 // bit 3
21935 #define PWM6DCH4 PWM6DCHbits.PWM6DCH4 // bit 4
21936 #define PWM6DCH5 PWM6DCHbits.PWM6DCH5 // bit 5
21937 #define PWM6DCH6 PWM6DCHbits.PWM6DCH6 // bit 6
21938 #define PWM6DCH7 PWM6DCHbits.PWM6DCH7 // bit 7
21940 #define PWM6DCL0 PWM6DCLbits.PWM6DCL0 // bit 0
21941 #define PWM6DCL1 PWM6DCLbits.PWM6DCL1 // bit 1
21942 #define PWM6DCL2 PWM6DCLbits.PWM6DCL2 // bit 2
21943 #define PWM6DCL3 PWM6DCLbits.PWM6DCL3 // bit 3
21944 #define PWM6DCL4 PWM6DCLbits.PWM6DCL4 // bit 4
21945 #define PWM6DCL5 PWM6DCLbits.PWM6DCL5 // bit 5
21946 #define PWM6DCL6 PWM6DCLbits.PWM6DCL6 // bit 6
21947 #define PWM6DCL7 PWM6DCLbits.PWM6DCL7 // bit 7
21949 #define PWM6OFH0 PWM6OFHbits.PWM6OFH0 // bit 0
21950 #define PWM6OFH1 PWM6OFHbits.PWM6OFH1 // bit 1
21951 #define PWM6OFH2 PWM6OFHbits.PWM6OFH2 // bit 2
21952 #define PWM6OFH3 PWM6OFHbits.PWM6OFH3 // bit 3
21953 #define PWM6OFH4 PWM6OFHbits.PWM6OFH4 // bit 4
21954 #define PWM6OFH5 PWM6OFHbits.PWM6OFH5 // bit 5
21955 #define PWM6OFH6 PWM6OFHbits.PWM6OFH6 // bit 6
21956 #define PWM6OFH7 PWM6OFHbits.PWM6OFH7 // bit 7
21958 #define PWM6OFL0 PWM6OFLbits.PWM6OFL0 // bit 0
21959 #define PWM6OFL1 PWM6OFLbits.PWM6OFL1 // bit 1
21960 #define PWM6OFL2 PWM6OFLbits.PWM6OFL2 // bit 2
21961 #define PWM6OFL3 PWM6OFLbits.PWM6OFL3 // bit 3
21962 #define PWM6OFL4 PWM6OFLbits.PWM6OFL4 // bit 4
21963 #define PWM6OFL5 PWM6OFLbits.PWM6OFL5 // bit 5
21964 #define PWM6OFL6 PWM6OFLbits.PWM6OFL6 // bit 6
21965 #define PWM6OFL7 PWM6OFLbits.PWM6OFL7 // bit 7
21967 #define PWM6PHH0 PWM6PHHbits.PWM6PHH0 // bit 0
21968 #define PWM6PHH1 PWM6PHHbits.PWM6PHH1 // bit 1
21969 #define PWM6PHH2 PWM6PHHbits.PWM6PHH2 // bit 2
21970 #define PWM6PHH3 PWM6PHHbits.PWM6PHH3 // bit 3
21971 #define PWM6PHH4 PWM6PHHbits.PWM6PHH4 // bit 4
21972 #define PWM6PHH5 PWM6PHHbits.PWM6PHH5 // bit 5
21973 #define PWM6PHH6 PWM6PHHbits.PWM6PHH6 // bit 6
21974 #define PWM6PHH7 PWM6PHHbits.PWM6PHH7 // bit 7
21976 #define PWM6PHL0 PWM6PHLbits.PWM6PHL0 // bit 0
21977 #define PWM6PHL1 PWM6PHLbits.PWM6PHL1 // bit 1
21978 #define PWM6PHL2 PWM6PHLbits.PWM6PHL2 // bit 2
21979 #define PWM6PHL3 PWM6PHLbits.PWM6PHL3 // bit 3
21980 #define PWM6PHL4 PWM6PHLbits.PWM6PHL4 // bit 4
21981 #define PWM6PHL5 PWM6PHLbits.PWM6PHL5 // bit 5
21982 #define PWM6PHL6 PWM6PHLbits.PWM6PHL6 // bit 6
21983 #define PWM6PHL7 PWM6PHLbits.PWM6PHL7 // bit 7
21985 #define PWM6PRH0 PWM6PRHbits.PWM6PRH0 // bit 0
21986 #define PWM6PRH1 PWM6PRHbits.PWM6PRH1 // bit 1
21987 #define PWM6PRH2 PWM6PRHbits.PWM6PRH2 // bit 2
21988 #define PWM6PRH3 PWM6PRHbits.PWM6PRH3 // bit 3
21989 #define PWM6PRH4 PWM6PRHbits.PWM6PRH4 // bit 4
21990 #define PWM6PRH5 PWM6PRHbits.PWM6PRH5 // bit 5
21991 #define PWM6PRH6 PWM6PRHbits.PWM6PRH6 // bit 6
21992 #define PWM6PRH7 PWM6PRHbits.PWM6PRH7 // bit 7
21994 #define PWM6PRL0 PWM6PRLbits.PWM6PRL0 // bit 0
21995 #define PWM6PRL1 PWM6PRLbits.PWM6PRL1 // bit 1
21996 #define PWM6PRL2 PWM6PRLbits.PWM6PRL2 // bit 2
21997 #define PWM6PRL3 PWM6PRLbits.PWM6PRL3 // bit 3
21998 #define PWM6PRL4 PWM6PRLbits.PWM6PRL4 // bit 4
21999 #define PWM6PRL5 PWM6PRLbits.PWM6PRL5 // bit 5
22000 #define PWM6PRL6 PWM6PRLbits.PWM6PRL6 // bit 6
22001 #define PWM6PRL7 PWM6PRLbits.PWM6PRL7 // bit 7
22003 #define PWM6TMRH0 PWM6TMRHbits.PWM6TMRH0 // bit 0
22004 #define PWM6TMRH1 PWM6TMRHbits.PWM6TMRH1 // bit 1
22005 #define PWM6TMRH2 PWM6TMRHbits.PWM6TMRH2 // bit 2
22006 #define PWM6TMRH3 PWM6TMRHbits.PWM6TMRH3 // bit 3
22007 #define PWM6TMRH4 PWM6TMRHbits.PWM6TMRH4 // bit 4
22008 #define PWM6TMRH5 PWM6TMRHbits.PWM6TMRH5 // bit 5
22009 #define PWM6TMRH6 PWM6TMRHbits.PWM6TMRH6 // bit 6
22010 #define PWM6TMRH7 PWM6TMRHbits.PWM6TMRH7 // bit 7
22012 #define PWM6TMRL0 PWM6TMRLbits.PWM6TMRL0 // bit 0
22013 #define PWM6TMRL1 PWM6TMRLbits.PWM6TMRL1 // bit 1
22014 #define PWM6TMRL2 PWM6TMRLbits.PWM6TMRL2 // bit 2
22015 #define PWM6TMRL3 PWM6TMRLbits.PWM6TMRL3 // bit 3
22016 #define PWM6TMRL4 PWM6TMRLbits.PWM6TMRL4 // bit 4
22017 #define PWM6TMRL5 PWM6TMRLbits.PWM6TMRL5 // bit 5
22018 #define PWM6TMRL6 PWM6TMRLbits.PWM6TMRL6 // bit 6
22019 #define PWM6TMRL7 PWM6TMRLbits.PWM6TMRL7 // bit 7
22021 #define PWM11DCH0 PWM11DCHbits.PWM11DCH0 // bit 0
22022 #define PWM11DCH1 PWM11DCHbits.PWM11DCH1 // bit 1
22023 #define PWM11DCH2 PWM11DCHbits.PWM11DCH2 // bit 2
22024 #define PWM11DCH3 PWM11DCHbits.PWM11DCH3 // bit 3
22025 #define PWM11DCH4 PWM11DCHbits.PWM11DCH4 // bit 4
22026 #define PWM11DCH5 PWM11DCHbits.PWM11DCH5 // bit 5
22027 #define PWM11DCH6 PWM11DCHbits.PWM11DCH6 // bit 6
22028 #define PWM11DCH7 PWM11DCHbits.PWM11DCH7 // bit 7
22030 #define PWM11DCL0 PWM11DCLbits.PWM11DCL0 // bit 0
22031 #define PWM11DCL1 PWM11DCLbits.PWM11DCL1 // bit 1
22032 #define PWM11DCL2 PWM11DCLbits.PWM11DCL2 // bit 2
22033 #define PWM11DCL3 PWM11DCLbits.PWM11DCL3 // bit 3
22034 #define PWM11DCL4 PWM11DCLbits.PWM11DCL4 // bit 4
22035 #define PWM11DCL5 PWM11DCLbits.PWM11DCL5 // bit 5
22036 #define PWM11DCL6 PWM11DCLbits.PWM11DCL6 // bit 6
22037 #define PWM11DCL7 PWM11DCLbits.PWM11DCL7 // bit 7
22039 #define PWM11OFH0 PWM11OFHbits.PWM11OFH0 // bit 0
22040 #define PWM11OFH1 PWM11OFHbits.PWM11OFH1 // bit 1
22041 #define PWM11OFH2 PWM11OFHbits.PWM11OFH2 // bit 2
22042 #define PWM11OFH3 PWM11OFHbits.PWM11OFH3 // bit 3
22043 #define PWM11OFH4 PWM11OFHbits.PWM11OFH4 // bit 4
22044 #define PWM11OFH5 PWM11OFHbits.PWM11OFH5 // bit 5
22045 #define PWM11OFH6 PWM11OFHbits.PWM11OFH6 // bit 6
22046 #define PWM11OFH7 PWM11OFHbits.PWM11OFH7 // bit 7
22048 #define PWM11OFL0 PWM11OFLbits.PWM11OFL0 // bit 0
22049 #define PWM11OFL1 PWM11OFLbits.PWM11OFL1 // bit 1
22050 #define PWM11OFL2 PWM11OFLbits.PWM11OFL2 // bit 2
22051 #define PWM11OFL3 PWM11OFLbits.PWM11OFL3 // bit 3
22052 #define PWM11OFL4 PWM11OFLbits.PWM11OFL4 // bit 4
22053 #define PWM11OFL5 PWM11OFLbits.PWM11OFL5 // bit 5
22054 #define PWM11OFL6 PWM11OFLbits.PWM11OFL6 // bit 6
22055 #define PWM11OFL7 PWM11OFLbits.PWM11OFL7 // bit 7
22057 #define PWM11PHH0 PWM11PHHbits.PWM11PHH0 // bit 0
22058 #define PWM11PHH1 PWM11PHHbits.PWM11PHH1 // bit 1
22059 #define PWM11PHH2 PWM11PHHbits.PWM11PHH2 // bit 2
22060 #define PWM11PHH3 PWM11PHHbits.PWM11PHH3 // bit 3
22061 #define PWM11PHH4 PWM11PHHbits.PWM11PHH4 // bit 4
22062 #define PWM11PHH5 PWM11PHHbits.PWM11PHH5 // bit 5
22063 #define PWM11PHH6 PWM11PHHbits.PWM11PHH6 // bit 6
22064 #define PWM11PHH7 PWM11PHHbits.PWM11PHH7 // bit 7
22066 #define PWM11PHL0 PWM11PHLbits.PWM11PHL0 // bit 0
22067 #define PWM11PHL1 PWM11PHLbits.PWM11PHL1 // bit 1
22068 #define PWM11PHL2 PWM11PHLbits.PWM11PHL2 // bit 2
22069 #define PWM11PHL3 PWM11PHLbits.PWM11PHL3 // bit 3
22070 #define PWM11PHL4 PWM11PHLbits.PWM11PHL4 // bit 4
22071 #define PWM11PHL5 PWM11PHLbits.PWM11PHL5 // bit 5
22072 #define PWM11PHL6 PWM11PHLbits.PWM11PHL6 // bit 6
22073 #define PWM11PHL7 PWM11PHLbits.PWM11PHL7 // bit 7
22075 #define PWM11PRH0 PWM11PRHbits.PWM11PRH0 // bit 0
22076 #define PWM11PRH1 PWM11PRHbits.PWM11PRH1 // bit 1
22077 #define PWM11PRH2 PWM11PRHbits.PWM11PRH2 // bit 2
22078 #define PWM11PRH3 PWM11PRHbits.PWM11PRH3 // bit 3
22079 #define PWM11PRH4 PWM11PRHbits.PWM11PRH4 // bit 4
22080 #define PWM11PRH5 PWM11PRHbits.PWM11PRH5 // bit 5
22081 #define PWM11PRH6 PWM11PRHbits.PWM11PRH6 // bit 6
22082 #define PWM11PRH7 PWM11PRHbits.PWM11PRH7 // bit 7
22084 #define PWM11PRL0 PWM11PRLbits.PWM11PRL0 // bit 0
22085 #define PWM11PRL1 PWM11PRLbits.PWM11PRL1 // bit 1
22086 #define PWM11PRL2 PWM11PRLbits.PWM11PRL2 // bit 2
22087 #define PWM11PRL3 PWM11PRLbits.PWM11PRL3 // bit 3
22088 #define PWM11PRL4 PWM11PRLbits.PWM11PRL4 // bit 4
22089 #define PWM11PRL5 PWM11PRLbits.PWM11PRL5 // bit 5
22090 #define PWM11PRL6 PWM11PRLbits.PWM11PRL6 // bit 6
22091 #define PWM11PRL7 PWM11PRLbits.PWM11PRL7 // bit 7
22093 #define PWM11TMRH0 PWM11TMRHbits.PWM11TMRH0 // bit 0
22094 #define PWM11TMRH1 PWM11TMRHbits.PWM11TMRH1 // bit 1
22095 #define PWM11TMRH2 PWM11TMRHbits.PWM11TMRH2 // bit 2
22096 #define PWM11TMRH3 PWM11TMRHbits.PWM11TMRH3 // bit 3
22097 #define PWM11TMRH4 PWM11TMRHbits.PWM11TMRH4 // bit 4
22098 #define PWM11TMRH5 PWM11TMRHbits.PWM11TMRH5 // bit 5
22099 #define PWM11TMRH6 PWM11TMRHbits.PWM11TMRH6 // bit 6
22100 #define PWM11TMRH7 PWM11TMRHbits.PWM11TMRH7 // bit 7
22102 #define PWM11TMRL0 PWM11TMRLbits.PWM11TMRL0 // bit 0
22103 #define PWM11TMRL1 PWM11TMRLbits.PWM11TMRL1 // bit 1
22104 #define PWM11TMRL2 PWM11TMRLbits.PWM11TMRL2 // bit 2
22105 #define PWM11TMRL3 PWM11TMRLbits.PWM11TMRL3 // bit 3
22106 #define PWM11TMRL4 PWM11TMRLbits.PWM11TMRL4 // bit 4
22107 #define PWM11TMRL5 PWM11TMRLbits.PWM11TMRL5 // bit 5
22108 #define PWM11TMRL6 PWM11TMRLbits.PWM11TMRL6 // bit 6
22109 #define PWM11TMRL7 PWM11TMRLbits.PWM11TMRL7 // bit 7
22111 #define MPWM5EN PWMENbits.MPWM5EN // bit 0
22112 #define MPWM6EN PWMENbits.MPWM6EN // bit 1
22113 #define MPWM11EN PWMENbits.MPWM11EN // bit 2
22115 #define MPWM5LD PWMLDbits.MPWM5LD // bit 0
22116 #define MPWM6LD PWMLDbits.MPWM6LD // bit 1
22117 #define MPWM11LD PWMLDbits.MPWM11LD // bit 2
22119 #define MPWM5OUT PWMOUTbits.MPWM5OUT // bit 0
22120 #define MPWM6OUT PWMOUTbits.MPWM6OUT // bit 1
22121 #define MPWM11OUT PWMOUTbits.MPWM11OUT // bit 2
22123 #define RX9D RC1STAbits.RX9D // bit 0
22124 #define OERR RC1STAbits.OERR // bit 1
22125 #define FERR RC1STAbits.FERR // bit 2
22126 #define ADDEN RC1STAbits.ADDEN // bit 3
22127 #define CREN RC1STAbits.CREN // bit 4
22128 #define SREN RC1STAbits.SREN // bit 5
22129 #define RX9 RC1STAbits.RX9 // bit 6
22130 #define SPEN RC1STAbits.SPEN // bit 7
22132 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
22133 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
22134 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
22135 #define SLRA3 SLRCONAbits.SLRA3 // bit 3
22136 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
22137 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
22138 #define SLRA6 SLRCONAbits.SLRA6 // bit 6
22139 #define SLRA7 SLRCONAbits.SLRA7 // bit 7
22141 #define SLRB0 SLRCONBbits.SLRB0 // bit 0
22142 #define SLRB1 SLRCONBbits.SLRB1 // bit 1
22143 #define SLRB2 SLRCONBbits.SLRB2 // bit 2
22144 #define SLRB3 SLRCONBbits.SLRB3 // bit 3
22145 #define SLRB4 SLRCONBbits.SLRB4 // bit 4
22146 #define SLRB5 SLRCONBbits.SLRB5 // bit 5
22147 #define SLRB6 SLRCONBbits.SLRB6 // bit 6
22148 #define SLRB7 SLRCONBbits.SLRB7 // bit 7
22150 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
22151 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
22152 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
22153 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
22154 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
22155 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
22156 #define SLRC6 SLRCONCbits.SLRC6 // bit 6
22157 #define SLRC7 SLRCONCbits.SLRC7 // bit 7
22159 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
22160 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
22161 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
22162 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
22163 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
22164 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
22165 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
22166 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
22167 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
22168 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
22169 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
22170 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
22171 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
22172 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
22173 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
22174 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
22176 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
22177 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
22178 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
22179 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
22180 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
22181 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
22182 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
22183 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
22184 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
22185 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
22186 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
22187 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
22188 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
22189 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
22190 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
22191 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
22193 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
22194 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
22195 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
22196 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
22197 #define CKP SSP1CONbits.CKP // bit 4
22198 #define SSPEN SSP1CONbits.SSPEN // bit 5
22199 #define SSPOV SSP1CONbits.SSPOV // bit 6
22200 #define WCOL SSP1CONbits.WCOL // bit 7
22202 #define SEN SSP1CON2bits.SEN // bit 0
22203 #define RSEN SSP1CON2bits.RSEN // bit 1
22204 #define PEN SSP1CON2bits.PEN // bit 2
22205 #define RCEN SSP1CON2bits.RCEN // bit 3
22206 #define ACKEN SSP1CON2bits.ACKEN // bit 4
22207 #define ACKDT SSP1CON2bits.ACKDT // bit 5
22208 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
22209 #define GCEN SSP1CON2bits.GCEN // bit 7
22211 #define DHEN SSP1CON3bits.DHEN // bit 0
22212 #define AHEN SSP1CON3bits.AHEN // bit 1
22213 #define SBCDE SSP1CON3bits.SBCDE // bit 2
22214 #define SDAHT SSP1CON3bits.SDAHT // bit 3
22215 #define BOEN SSP1CON3bits.BOEN // bit 4
22216 #define SCIE SSP1CON3bits.SCIE // bit 5
22217 #define PCIE SSP1CON3bits.PCIE // bit 6
22218 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
22220 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
22221 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
22222 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
22223 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
22224 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
22225 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
22226 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
22227 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
22228 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
22229 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
22230 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
22231 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
22232 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
22233 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
22234 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
22235 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
22237 #define BF SSP1STATbits.BF // bit 0
22238 #define UA SSP1STATbits.UA // bit 1
22239 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
22240 #define S SSP1STATbits.S // bit 3
22241 #define P SSP1STATbits.P // bit 4
22242 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
22243 #define CKE SSP1STATbits.CKE // bit 6
22244 #define SMP SSP1STATbits.SMP // bit 7
22246 #define C STATUSbits.C // bit 0
22247 #define DC STATUSbits.DC // bit 1
22248 #define Z STATUSbits.Z // bit 2
22249 #define NOT_PD STATUSbits.NOT_PD // bit 3
22250 #define NOT_TO STATUSbits.NOT_TO // bit 4
22252 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
22253 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
22254 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
22256 #define GSS0 T1GCONbits.GSS0 // bit 0, shadows bit in T1GCONbits
22257 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0, shadows bit in T1GCONbits
22258 #define GSS1 T1GCONbits.GSS1 // bit 1, shadows bit in T1GCONbits
22259 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1, shadows bit in T1GCONbits
22260 #define GVAL T1GCONbits.GVAL // bit 2, shadows bit in T1GCONbits
22261 #define T1GVAL T1GCONbits.T1GVAL // bit 2, shadows bit in T1GCONbits
22262 #define GGO_NOT_DONE T1GCONbits.GGO_NOT_DONE // bit 3, shadows bit in T1GCONbits
22263 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3, shadows bit in T1GCONbits
22264 #define GSPM T1GCONbits.GSPM // bit 4, shadows bit in T1GCONbits
22265 #define T1GSPM T1GCONbits.T1GSPM // bit 4, shadows bit in T1GCONbits
22266 #define GTM T1GCONbits.GTM // bit 5, shadows bit in T1GCONbits
22267 #define T1GTM T1GCONbits.T1GTM // bit 5, shadows bit in T1GCONbits
22268 #define GPOL T1GCONbits.GPOL // bit 6, shadows bit in T1GCONbits
22269 #define T1GPOL T1GCONbits.T1GPOL // bit 6, shadows bit in T1GCONbits
22270 #define GE T1GCONbits.GE // bit 7, shadows bit in T1GCONbits
22271 #define T1GE T1GCONbits.T1GE // bit 7, shadows bit in T1GCONbits
22272 #define TMR1GE T1GCONbits.TMR1GE // bit 7, shadows bit in T1GCONbits
22274 #define RSEL0 T2RSTbits.RSEL0 // bit 0, shadows bit in T2RSTbits
22275 #define T2RSEL0 T2RSTbits.T2RSEL0 // bit 0, shadows bit in T2RSTbits
22276 #define RSEL1 T2RSTbits.RSEL1 // bit 1, shadows bit in T2RSTbits
22277 #define T2RSEL1 T2RSTbits.T2RSEL1 // bit 1, shadows bit in T2RSTbits
22278 #define RSEL2 T2RSTbits.RSEL2 // bit 2, shadows bit in T2RSTbits
22279 #define T2RSEL2 T2RSTbits.T2RSEL2 // bit 2, shadows bit in T2RSTbits
22280 #define RSEL3 T2RSTbits.RSEL3 // bit 3, shadows bit in T2RSTbits
22281 #define T2RSEL3 T2RSTbits.T2RSEL3 // bit 3, shadows bit in T2RSTbits
22282 #define RSEL4 T2RSTbits.RSEL4 // bit 4, shadows bit in T2RSTbits
22283 #define T2RSEL4 T2RSTbits.T2RSEL4 // bit 4, shadows bit in T2RSTbits
22285 #define TRISA0 TRISAbits.TRISA0 // bit 0
22286 #define TRISA1 TRISAbits.TRISA1 // bit 1
22287 #define TRISA2 TRISAbits.TRISA2 // bit 2
22288 #define TRISA3 TRISAbits.TRISA3 // bit 3
22289 #define TRISA4 TRISAbits.TRISA4 // bit 4
22290 #define TRISA5 TRISAbits.TRISA5 // bit 5
22291 #define TRISA6 TRISAbits.TRISA6 // bit 6
22292 #define TRISA7 TRISAbits.TRISA7 // bit 7
22294 #define TRISB0 TRISBbits.TRISB0 // bit 0
22295 #define TRISB1 TRISBbits.TRISB1 // bit 1
22296 #define TRISB2 TRISBbits.TRISB2 // bit 2
22297 #define TRISB3 TRISBbits.TRISB3 // bit 3
22298 #define TRISB4 TRISBbits.TRISB4 // bit 4
22299 #define TRISB5 TRISBbits.TRISB5 // bit 5
22300 #define TRISB6 TRISBbits.TRISB6 // bit 6
22301 #define TRISB7 TRISBbits.TRISB7 // bit 7
22303 #define TRISC0 TRISCbits.TRISC0 // bit 0
22304 #define TRISC1 TRISCbits.TRISC1 // bit 1
22305 #define TRISC2 TRISCbits.TRISC2 // bit 2
22306 #define TRISC3 TRISCbits.TRISC3 // bit 3
22307 #define TRISC4 TRISCbits.TRISC4 // bit 4
22308 #define TRISC5 TRISCbits.TRISC5 // bit 5
22309 #define TRISC6 TRISCbits.TRISC6 // bit 6
22310 #define TRISC7 TRISCbits.TRISC7 // bit 7
22312 #define TRISE3 TRISEbits.TRISE3 // bit 3
22314 #define SWDTEN WDTCONbits.SWDTEN // bit 0
22315 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
22316 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
22317 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
22318 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
22319 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
22321 #define WPUA0 WPUAbits.WPUA0 // bit 0
22322 #define WPUA1 WPUAbits.WPUA1 // bit 1
22323 #define WPUA2 WPUAbits.WPUA2 // bit 2
22324 #define WPUA3 WPUAbits.WPUA3 // bit 3
22325 #define WPUA4 WPUAbits.WPUA4 // bit 4
22326 #define WPUA5 WPUAbits.WPUA5 // bit 5
22327 #define WPUA6 WPUAbits.WPUA6 // bit 6
22328 #define WPUA7 WPUAbits.WPUA7 // bit 7
22330 #define WPUB0 WPUBbits.WPUB0 // bit 0
22331 #define WPUB1 WPUBbits.WPUB1 // bit 1
22332 #define WPUB2 WPUBbits.WPUB2 // bit 2
22333 #define WPUB3 WPUBbits.WPUB3 // bit 3
22334 #define WPUB4 WPUBbits.WPUB4 // bit 4
22335 #define WPUB5 WPUBbits.WPUB5 // bit 5
22336 #define WPUB6 WPUBbits.WPUB6 // bit 6
22337 #define WPUB7 WPUBbits.WPUB7 // bit 7
22339 #define WPUC0 WPUCbits.WPUC0 // bit 0
22340 #define WPUC1 WPUCbits.WPUC1 // bit 1
22341 #define WPUC2 WPUCbits.WPUC2 // bit 2
22342 #define WPUC3 WPUCbits.WPUC3 // bit 3
22343 #define WPUC4 WPUCbits.WPUC4 // bit 4
22344 #define WPUC5 WPUCbits.WPUC5 // bit 5
22345 #define WPUC6 WPUCbits.WPUC6 // bit 6
22346 #define WPUC7 WPUCbits.WPUC7 // bit 7
22348 #define WPUE3 WPUEbits.WPUE3 // bit 3
22350 #define ZCD1INTN ZCD1CONbits.ZCD1INTN // bit 0
22351 #define ZCD1INTP ZCD1CONbits.ZCD1INTP // bit 1
22352 #define ZCD1POL ZCD1CONbits.ZCD1POL // bit 4
22353 #define ZCD1OUT ZCD1CONbits.ZCD1OUT // bit 5
22354 #define ZCD1EN ZCD1CONbits.ZCD1EN // bit 7
22356 #endif // #ifndef NO_BIT_DEFINES
22358 #endif // #ifndef __PIC16LF1776_H__