2 * This declarations of the PIC16LF18313 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:23 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16LF18313_H__
26 #define __PIC16LF18313_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PIR0_ADDR 0x0010
52 #define PIR1_ADDR 0x0011
53 #define PIR2_ADDR 0x0012
54 #define PIR3_ADDR 0x0013
55 #define PIR4_ADDR 0x0014
56 #define TMR0L_ADDR 0x0015
57 #define TMR0H_ADDR 0x0016
58 #define T0CON0_ADDR 0x0017
59 #define T0CON1_ADDR 0x0018
60 #define TMR1_ADDR 0x0019
61 #define TMR1L_ADDR 0x0019
62 #define TMR1H_ADDR 0x001A
63 #define T1CON_ADDR 0x001B
64 #define T1GCON_ADDR 0x001C
65 #define TMR2_ADDR 0x001D
66 #define PR2_ADDR 0x001E
67 #define T2CON_ADDR 0x001F
68 #define TRISA_ADDR 0x008C
69 #define PIE0_ADDR 0x0090
70 #define PIE1_ADDR 0x0091
71 #define PIE2_ADDR 0x0092
72 #define PIE3_ADDR 0x0093
73 #define PIE4_ADDR 0x0094
74 #define WDTCON_ADDR 0x0097
75 #define ADRES_ADDR 0x009B
76 #define ADRESL_ADDR 0x009B
77 #define ADRESH_ADDR 0x009C
78 #define ADCON0_ADDR 0x009D
79 #define ADCON1_ADDR 0x009E
80 #define ADACT_ADDR 0x009F
81 #define LATA_ADDR 0x010C
82 #define CM1CON0_ADDR 0x0111
83 #define CM1CON1_ADDR 0x0112
84 #define CMOUT_ADDR 0x0115
85 #define BORCON_ADDR 0x0116
86 #define FVRCON_ADDR 0x0117
87 #define DACCON0_ADDR 0x0118
88 #define DACCON1_ADDR 0x0119
89 #define ANSELA_ADDR 0x018C
90 #define RC1REG_ADDR 0x0199
91 #define RCREG_ADDR 0x0199
92 #define RCREG1_ADDR 0x0199
93 #define TX1REG_ADDR 0x019A
94 #define TXREG_ADDR 0x019A
95 #define TXREG1_ADDR 0x019A
96 #define SP1BRG_ADDR 0x019B
97 #define SP1BRGL_ADDR 0x019B
98 #define SPBRG_ADDR 0x019B
99 #define SPBRG1_ADDR 0x019B
100 #define SPBRGL_ADDR 0x019B
101 #define SP1BRGH_ADDR 0x019C
102 #define SPBRGH_ADDR 0x019C
103 #define SPBRGH1_ADDR 0x019C
104 #define RC1STA_ADDR 0x019D
105 #define RCSTA_ADDR 0x019D
106 #define RCSTA1_ADDR 0x019D
107 #define TX1STA_ADDR 0x019E
108 #define TXSTA_ADDR 0x019E
109 #define TXSTA1_ADDR 0x019E
110 #define BAUD1CON_ADDR 0x019F
111 #define BAUDCON_ADDR 0x019F
112 #define BAUDCON1_ADDR 0x019F
113 #define BAUDCTL_ADDR 0x019F
114 #define BAUDCTL1_ADDR 0x019F
115 #define WPUA_ADDR 0x020C
116 #define SSP1BUF_ADDR 0x0211
117 #define SSPBUF_ADDR 0x0211
118 #define SSP1ADD_ADDR 0x0212
119 #define SSPADD_ADDR 0x0212
120 #define SSP1MSK_ADDR 0x0213
121 #define SSPMSK_ADDR 0x0213
122 #define SSP1STAT_ADDR 0x0214
123 #define SSPSTAT_ADDR 0x0214
124 #define SSP1CON_ADDR 0x0215
125 #define SSP1CON1_ADDR 0x0215
126 #define SSPCON_ADDR 0x0215
127 #define SSPCON1_ADDR 0x0215
128 #define SSP1CON2_ADDR 0x0216
129 #define SSPCON2_ADDR 0x0216
130 #define SSP1CON3_ADDR 0x0217
131 #define SSPCON3_ADDR 0x0217
132 #define ODCONA_ADDR 0x028C
133 #define CCPR1_ADDR 0x0291
134 #define CCPR1L_ADDR 0x0291
135 #define CCPR1H_ADDR 0x0292
136 #define CCP1CON_ADDR 0x0293
137 #define CCP1CAP_ADDR 0x0294
138 #define CCPR2_ADDR 0x0295
139 #define CCPR2L_ADDR 0x0295
140 #define CCPR2H_ADDR 0x0296
141 #define CCP2CON_ADDR 0x0297
142 #define CCP2CAP_ADDR 0x0298
143 #define CCPTMRS_ADDR 0x029F
144 #define SLRCONA_ADDR 0x030C
145 #define INLVLA_ADDR 0x038C
146 #define IOCAP_ADDR 0x0391
147 #define IOCAN_ADDR 0x0392
148 #define IOCAF_ADDR 0x0393
149 #define CLKRCON_ADDR 0x039A
150 #define MDCON_ADDR 0x039C
151 #define MDSRC_ADDR 0x039D
152 #define MDCARH_ADDR 0x039E
153 #define MDCARL_ADDR 0x039F
154 #define CCDNA_ADDR 0x040C
155 #define CCDCON_ADDR 0x041F
156 #define CCDPA_ADDR 0x048C
157 #define NCO1ACC_ADDR 0x0498
158 #define NCO1ACCL_ADDR 0x0498
159 #define NCO1ACCH_ADDR 0x0499
160 #define NCO1ACCU_ADDR 0x049A
161 #define NCO1INC_ADDR 0x049B
162 #define NCO1INCL_ADDR 0x049B
163 #define NCO1INCH_ADDR 0x049C
164 #define NCO1INCU_ADDR 0x049D
165 #define NCO1CON_ADDR 0x049E
166 #define NCO1CLK_ADDR 0x049F
167 #define PWM5DCL_ADDR 0x0617
168 #define PWM5DCH_ADDR 0x0618
169 #define PWM5CON_ADDR 0x0619
170 #define PWM5CON0_ADDR 0x0619
171 #define PWM6DCL_ADDR 0x061A
172 #define PWM6DCH_ADDR 0x061B
173 #define PWM6CON_ADDR 0x061C
174 #define PWM6CON0_ADDR 0x061C
175 #define CWG1CLKCON_ADDR 0x0691
176 #define CWG1DAT_ADDR 0x0692
177 #define CWG1DBR_ADDR 0x0693
178 #define CWG1DBF_ADDR 0x0694
179 #define CWG1CON0_ADDR 0x0695
180 #define CWG1CON1_ADDR 0x0696
181 #define CWG1AS0_ADDR 0x0697
182 #define CWG1AS1_ADDR 0x0698
183 #define CWG1STR_ADDR 0x0699
184 #define NVMADR_ADDR 0x0891
185 #define NVMADRL_ADDR 0x0891
186 #define NVMADRH_ADDR 0x0892
187 #define NVMDAT_ADDR 0x0893
188 #define NVMDATL_ADDR 0x0893
189 #define NVMDATH_ADDR 0x0894
190 #define NVMCON1_ADDR 0x0895
191 #define NVMCON2_ADDR 0x0896
192 #define PCON0_ADDR 0x089B
193 #define PMD0_ADDR 0x0911
194 #define PMD1_ADDR 0x0912
195 #define PMD2_ADDR 0x0913
196 #define PMD3_ADDR 0x0914
197 #define PMD4_ADDR 0x0915
198 #define PMD5_ADDR 0x0916
199 #define CPUDOZE_ADDR 0x0918
200 #define OSCCON1_ADDR 0x0919
201 #define OSCCON2_ADDR 0x091A
202 #define OSCCON3_ADDR 0x091B
203 #define OSCSTAT1_ADDR 0x091C
204 #define OSCEN_ADDR 0x091D
205 #define OSCTUNE_ADDR 0x091E
206 #define OSCFRQ_ADDR 0x091F
207 #define PPSLOCK_ADDR 0x0E0F
208 #define INTPPS_ADDR 0x0E10
209 #define T0CKIPPS_ADDR 0x0E11
210 #define T1CKIPPS_ADDR 0x0E12
211 #define T1GPPS_ADDR 0x0E13
212 #define CCP1PPS_ADDR 0x0E14
213 #define CCP2PPS_ADDR 0x0E15
214 #define CWG1PPS_ADDR 0x0E18
215 #define MDCIN1PPS_ADDR 0x0E1A
216 #define MDCIN2PPS_ADDR 0x0E1B
217 #define MDMINPPS_ADDR 0x0E1C
218 #define SSP1CLKPPS_ADDR 0x0E20
219 #define SSP1DATPPS_ADDR 0x0E21
220 #define SSP1SSPPS_ADDR 0x0E22
221 #define RXPPS_ADDR 0x0E24
222 #define TXPPS_ADDR 0x0E25
223 #define CLCIN0PPS_ADDR 0x0E28
224 #define CLCIN1PPS_ADDR 0x0E29
225 #define CLCIN2PPS_ADDR 0x0E2A
226 #define CLCIN3PPS_ADDR 0x0E2B
227 #define RA0PPS_ADDR 0x0E90
228 #define RA1PPS_ADDR 0x0E91
229 #define RA2PPS_ADDR 0x0E92
230 #define RA4PPS_ADDR 0x0E94
231 #define RA5PPS_ADDR 0x0E95
232 #define CLCDATA_ADDR 0x0F0F
233 #define CLC1CON_ADDR 0x0F10
234 #define CLC1POL_ADDR 0x0F11
235 #define CLC1SEL0_ADDR 0x0F12
236 #define CLC1SEL1_ADDR 0x0F13
237 #define CLC1SEL2_ADDR 0x0F14
238 #define CLC1SEL3_ADDR 0x0F15
239 #define CLC1GLS0_ADDR 0x0F16
240 #define CLC1GLS1_ADDR 0x0F17
241 #define CLC1GLS2_ADDR 0x0F18
242 #define CLC1GLS3_ADDR 0x0F19
243 #define CLC2CON_ADDR 0x0F1A
244 #define CLC2POL_ADDR 0x0F1B
245 #define CLC2SEL0_ADDR 0x0F1C
246 #define CLC2SEL1_ADDR 0x0F1D
247 #define CLC2SEL2_ADDR 0x0F1E
248 #define CLC2SEL3_ADDR 0x0F1F
249 #define CLC2GLS0_ADDR 0x0F20
250 #define CLC2GLS1_ADDR 0x0F21
251 #define CLC2GLS2_ADDR 0x0F22
252 #define CLC2GLS3_ADDR 0x0F23
253 #define STATUS_SHAD_ADDR 0x0FE4
254 #define WREG_SHAD_ADDR 0x0FE5
255 #define BSR_SHAD_ADDR 0x0FE6
256 #define PCLATH_SHAD_ADDR 0x0FE7
257 #define FSR0L_SHAD_ADDR 0x0FE8
258 #define FSR0H_SHAD_ADDR 0x0FE9
259 #define FSR1L_SHAD_ADDR 0x0FEA
260 #define FSR1H_SHAD_ADDR 0x0FEB
261 #define STKPTR_ADDR 0x0FED
262 #define TOSL_ADDR 0x0FEE
263 #define TOSH_ADDR 0x0FEF
265 #endif // #ifndef NO_ADDR_DEFINES
267 //==============================================================================
269 // Register Definitions
271 //==============================================================================
273 extern __at(0x0000) __sfr INDF0
;
274 extern __at(0x0001) __sfr INDF1
;
275 extern __at(0x0002) __sfr PCL
;
277 //==============================================================================
280 extern __at(0x0003) __sfr STATUS
;
294 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
302 //==============================================================================
304 extern __at(0x0004) __sfr FSR0
;
305 extern __at(0x0004) __sfr FSR0L
;
306 extern __at(0x0005) __sfr FSR0H
;
307 extern __at(0x0006) __sfr FSR1
;
308 extern __at(0x0006) __sfr FSR1L
;
309 extern __at(0x0007) __sfr FSR1H
;
311 //==============================================================================
314 extern __at(0x0008) __sfr BSR
;
337 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
345 //==============================================================================
347 extern __at(0x0009) __sfr WREG
;
348 extern __at(0x000A) __sfr PCLATH
;
350 //==============================================================================
353 extern __at(0x000B) __sfr INTCON
;
367 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
373 //==============================================================================
376 //==============================================================================
379 extern __at(0x000C) __sfr PORTA
;
402 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
411 //==============================================================================
414 //==============================================================================
417 extern __at(0x0010) __sfr PIR0
;
431 extern __at(0x0010) volatile __PIR0bits_t PIR0bits
;
437 //==============================================================================
440 //==============================================================================
443 extern __at(0x0011) __sfr PIR1
;
454 unsigned TMR1GIF
: 1;
457 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
466 #define _TMR1GIF 0x80
468 //==============================================================================
471 //==============================================================================
474 extern __at(0x0012) __sfr PIR2
;
488 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
494 //==============================================================================
497 //==============================================================================
500 extern __at(0x0013) __sfr PIR3
;
514 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
521 //==============================================================================
524 //==============================================================================
527 extern __at(0x0014) __sfr PIR4
;
541 extern __at(0x0014) volatile __PIR4bits_t PIR4bits
;
547 //==============================================================================
550 //==============================================================================
553 extern __at(0x0015) __sfr TMR0L
;
567 extern __at(0x0015) volatile __TMR0Lbits_t TMR0Lbits
;
578 //==============================================================================
581 //==============================================================================
584 extern __at(0x0016) __sfr TMR0H
;
598 extern __at(0x0016) volatile __TMR0Hbits_t TMR0Hbits
;
609 //==============================================================================
612 //==============================================================================
615 extern __at(0x0017) __sfr T0CON0
;
621 unsigned T0OUTPS0
: 1;
622 unsigned T0OUTPS1
: 1;
623 unsigned T0OUTPS2
: 1;
624 unsigned T0OUTPS3
: 1;
625 unsigned T016BIT
: 1;
633 unsigned T0OUTPS
: 4;
638 extern __at(0x0017) volatile __T0CON0bits_t T0CON0bits
;
640 #define _T0OUTPS0 0x01
641 #define _T0OUTPS1 0x02
642 #define _T0OUTPS2 0x04
643 #define _T0OUTPS3 0x08
644 #define _T016BIT 0x10
648 //==============================================================================
651 //==============================================================================
654 extern __at(0x0018) __sfr T0CON1
;
660 unsigned T0CKPS0
: 1;
661 unsigned T0CKPS1
: 1;
662 unsigned T0CKPS2
: 1;
663 unsigned T0CKPS3
: 1;
664 unsigned T0ASYNC
: 1;
683 extern __at(0x0018) volatile __T0CON1bits_t T0CON1bits
;
685 #define _T0CKPS0 0x01
686 #define _T0CKPS1 0x02
687 #define _T0CKPS2 0x04
688 #define _T0CKPS3 0x08
689 #define _T0ASYNC 0x10
694 //==============================================================================
696 extern __at(0x0019) __sfr TMR1
;
697 extern __at(0x0019) __sfr TMR1L
;
698 extern __at(0x001A) __sfr TMR1H
;
700 //==============================================================================
703 extern __at(0x001B) __sfr T1CON
;
713 unsigned T1CKPS0
: 1;
714 unsigned T1CKPS1
: 1;
715 unsigned TMR1CS0
: 1;
716 unsigned TMR1CS1
: 1;
733 extern __at(0x001B) volatile __T1CONbits_t T1CONbits
;
738 #define _T1CKPS0 0x10
739 #define _T1CKPS1 0x20
740 #define _TMR1CS0 0x40
741 #define _TMR1CS1 0x80
743 //==============================================================================
746 //==============================================================================
749 extern __at(0x001C) __sfr T1GCON
;
758 unsigned T1GGO_NOT_DONE
: 1;
772 extern __at(0x001C) volatile __T1GCONbits_t T1GCONbits
;
777 #define _T1GGO_NOT_DONE 0x08
783 //==============================================================================
785 extern __at(0x001D) __sfr TMR2
;
786 extern __at(0x001E) __sfr PR2
;
788 //==============================================================================
791 extern __at(0x001F) __sfr T2CON
;
797 unsigned T2CKPS0
: 1;
798 unsigned T2CKPS1
: 1;
800 unsigned T2OUTPS0
: 1;
801 unsigned T2OUTPS1
: 1;
802 unsigned T2OUTPS2
: 1;
803 unsigned T2OUTPS3
: 1;
816 unsigned T2OUTPS
: 4;
821 extern __at(0x001F) volatile __T2CONbits_t T2CONbits
;
823 #define _T2CKPS0 0x01
824 #define _T2CKPS1 0x02
826 #define _T2OUTPS0 0x08
827 #define _T2OUTPS1 0x10
828 #define _T2OUTPS2 0x20
829 #define _T2OUTPS3 0x40
831 //==============================================================================
834 //==============================================================================
837 extern __at(0x008C) __sfr TRISA
;
851 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
859 //==============================================================================
862 //==============================================================================
865 extern __at(0x0090) __sfr PIE0
;
879 extern __at(0x0090) volatile __PIE0bits_t PIE0bits
;
885 //==============================================================================
888 //==============================================================================
891 extern __at(0x0091) __sfr PIE1
;
902 unsigned TMR1GIE
: 1;
905 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
914 #define _TMR1GIE 0x80
916 //==============================================================================
919 //==============================================================================
922 extern __at(0x0092) __sfr PIE2
;
936 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
942 //==============================================================================
945 //==============================================================================
948 extern __at(0x0093) __sfr PIE3
;
962 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
969 //==============================================================================
972 //==============================================================================
975 extern __at(0x0094) __sfr PIE4
;
989 extern __at(0x0094) volatile __PIE4bits_t PIE4bits
;
995 //==============================================================================
998 //==============================================================================
1001 extern __at(0x0097) __sfr WDTCON
;
1007 unsigned SWDTEN
: 1;
1008 unsigned WDTPS0
: 1;
1009 unsigned WDTPS1
: 1;
1010 unsigned WDTPS2
: 1;
1011 unsigned WDTPS3
: 1;
1012 unsigned WDTPS4
: 1;
1025 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1027 #define _SWDTEN 0x01
1028 #define _WDTPS0 0x02
1029 #define _WDTPS1 0x04
1030 #define _WDTPS2 0x08
1031 #define _WDTPS3 0x10
1032 #define _WDTPS4 0x20
1034 //==============================================================================
1036 extern __at(0x009B) __sfr ADRES
;
1037 extern __at(0x009B) __sfr ADRESL
;
1038 extern __at(0x009C) __sfr ADRESH
;
1040 //==============================================================================
1043 extern __at(0x009D) __sfr ADCON0
;
1050 unsigned GO_NOT_DONE
: 1;
1090 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1093 #define _GO_NOT_DONE 0x02
1103 //==============================================================================
1106 //==============================================================================
1109 extern __at(0x009E) __sfr ADCON1
;
1115 unsigned ADPREF0
: 1;
1116 unsigned ADPREF1
: 1;
1117 unsigned ADNREF
: 1;
1127 unsigned ADPREF
: 2;
1139 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1141 #define _ADPREF0 0x01
1142 #define _ADPREF1 0x02
1143 #define _ADNREF 0x04
1149 //==============================================================================
1152 //==============================================================================
1155 extern __at(0x009F) __sfr ADACT
;
1161 unsigned ADACT0
: 1;
1162 unsigned ADACT1
: 1;
1163 unsigned ADACT2
: 1;
1164 unsigned ADACT3
: 1;
1178 extern __at(0x009F) volatile __ADACTbits_t ADACTbits
;
1180 #define _ADACT0 0x01
1181 #define _ADACT1 0x02
1182 #define _ADACT2 0x04
1183 #define _ADACT3 0x08
1185 //==============================================================================
1188 //==============================================================================
1191 extern __at(0x010C) __sfr LATA
;
1205 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1213 //==============================================================================
1216 //==============================================================================
1219 extern __at(0x0111) __sfr CM1CON0
;
1223 unsigned C1SYNC
: 1;
1233 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1235 #define _C1SYNC 0x01
1242 //==============================================================================
1245 //==============================================================================
1248 extern __at(0x0112) __sfr CM1CON1
;
1254 unsigned C1NCH0
: 1;
1255 unsigned C1NCH1
: 1;
1256 unsigned C1NCH2
: 1;
1257 unsigned C1PCH0
: 1;
1258 unsigned C1PCH1
: 1;
1259 unsigned C1PCH2
: 1;
1260 unsigned C1INTN
: 1;
1261 unsigned C1INTP
: 1;
1278 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1280 #define _C1NCH0 0x01
1281 #define _C1NCH1 0x02
1282 #define _C1NCH2 0x04
1283 #define _C1PCH0 0x08
1284 #define _C1PCH1 0x10
1285 #define _C1PCH2 0x20
1286 #define _C1INTN 0x40
1287 #define _C1INTP 0x80
1289 //==============================================================================
1292 //==============================================================================
1295 extern __at(0x0115) __sfr CMOUT
;
1299 unsigned MC1OUT
: 1;
1309 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1311 #define _MC1OUT 0x01
1313 //==============================================================================
1316 //==============================================================================
1319 extern __at(0x0116) __sfr BORCON
;
1323 unsigned BORRDY
: 1;
1330 unsigned SBOREN
: 1;
1333 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1335 #define _BORRDY 0x01
1336 #define _SBOREN 0x80
1338 //==============================================================================
1341 //==============================================================================
1344 extern __at(0x0117) __sfr FVRCON
;
1350 unsigned ADFVR0
: 1;
1351 unsigned ADFVR1
: 1;
1352 unsigned CDAFVR0
: 1;
1353 unsigned CDAFVR1
: 1;
1356 unsigned FVRRDY
: 1;
1369 unsigned CDAFVR
: 2;
1374 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1376 #define _ADFVR0 0x01
1377 #define _ADFVR1 0x02
1378 #define _CDAFVR0 0x04
1379 #define _CDAFVR1 0x08
1382 #define _FVRRDY 0x40
1385 //==============================================================================
1388 //==============================================================================
1391 extern __at(0x0118) __sfr DACCON0
;
1397 unsigned DAC1NSS
: 1;
1399 unsigned DAC1PSS0
: 1;
1400 unsigned DAC1PSS1
: 1;
1402 unsigned DAC1OE
: 1;
1404 unsigned DAC1EN
: 1;
1410 unsigned DAC1PSS
: 2;
1415 extern __at(0x0118) volatile __DACCON0bits_t DACCON0bits
;
1417 #define _DAC1NSS 0x01
1418 #define _DAC1PSS0 0x04
1419 #define _DAC1PSS1 0x08
1420 #define _DAC1OE 0x20
1421 #define _DAC1EN 0x80
1423 //==============================================================================
1426 //==============================================================================
1429 extern __at(0x0119) __sfr DACCON1
;
1435 unsigned DAC1R0
: 1;
1436 unsigned DAC1R1
: 1;
1437 unsigned DAC1R2
: 1;
1438 unsigned DAC1R3
: 1;
1439 unsigned DAC1R4
: 1;
1452 extern __at(0x0119) volatile __DACCON1bits_t DACCON1bits
;
1454 #define _DAC1R0 0x01
1455 #define _DAC1R1 0x02
1456 #define _DAC1R2 0x04
1457 #define _DAC1R3 0x08
1458 #define _DAC1R4 0x10
1460 //==============================================================================
1463 //==============================================================================
1466 extern __at(0x018C) __sfr ANSELA
;
1480 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1488 //==============================================================================
1490 extern __at(0x0199) __sfr RC1REG
;
1491 extern __at(0x0199) __sfr RCREG
;
1492 extern __at(0x0199) __sfr RCREG1
;
1493 extern __at(0x019A) __sfr TX1REG
;
1494 extern __at(0x019A) __sfr TXREG
;
1495 extern __at(0x019A) __sfr TXREG1
;
1496 extern __at(0x019B) __sfr SP1BRG
;
1497 extern __at(0x019B) __sfr SP1BRGL
;
1498 extern __at(0x019B) __sfr SPBRG
;
1499 extern __at(0x019B) __sfr SPBRG1
;
1500 extern __at(0x019B) __sfr SPBRGL
;
1501 extern __at(0x019C) __sfr SP1BRGH
;
1502 extern __at(0x019C) __sfr SPBRGH
;
1503 extern __at(0x019C) __sfr SPBRGH1
;
1505 //==============================================================================
1508 extern __at(0x019D) __sfr RC1STA
;
1522 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
1533 //==============================================================================
1536 //==============================================================================
1539 extern __at(0x019D) __sfr RCSTA
;
1553 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
1555 #define _RCSTA_RX9D 0x01
1556 #define _RCSTA_OERR 0x02
1557 #define _RCSTA_FERR 0x04
1558 #define _RCSTA_ADDEN 0x08
1559 #define _RCSTA_CREN 0x10
1560 #define _RCSTA_SREN 0x20
1561 #define _RCSTA_RX9 0x40
1562 #define _RCSTA_SPEN 0x80
1564 //==============================================================================
1567 //==============================================================================
1570 extern __at(0x019D) __sfr RCSTA1
;
1584 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
1586 #define _RCSTA1_RX9D 0x01
1587 #define _RCSTA1_OERR 0x02
1588 #define _RCSTA1_FERR 0x04
1589 #define _RCSTA1_ADDEN 0x08
1590 #define _RCSTA1_CREN 0x10
1591 #define _RCSTA1_SREN 0x20
1592 #define _RCSTA1_RX9 0x40
1593 #define _RCSTA1_SPEN 0x80
1595 //==============================================================================
1598 //==============================================================================
1601 extern __at(0x019E) __sfr TX1STA
;
1615 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
1626 //==============================================================================
1629 //==============================================================================
1632 extern __at(0x019E) __sfr TXSTA
;
1646 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
1648 #define _TXSTA_TX9D 0x01
1649 #define _TXSTA_TRMT 0x02
1650 #define _TXSTA_BRGH 0x04
1651 #define _TXSTA_SENDB 0x08
1652 #define _TXSTA_SYNC 0x10
1653 #define _TXSTA_TXEN 0x20
1654 #define _TXSTA_TX9 0x40
1655 #define _TXSTA_CSRC 0x80
1657 //==============================================================================
1660 //==============================================================================
1663 extern __at(0x019E) __sfr TXSTA1
;
1677 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
1679 #define _TXSTA1_TX9D 0x01
1680 #define _TXSTA1_TRMT 0x02
1681 #define _TXSTA1_BRGH 0x04
1682 #define _TXSTA1_SENDB 0x08
1683 #define _TXSTA1_SYNC 0x10
1684 #define _TXSTA1_TXEN 0x20
1685 #define _TXSTA1_TX9 0x40
1686 #define _TXSTA1_CSRC 0x80
1688 //==============================================================================
1691 //==============================================================================
1694 extern __at(0x019F) __sfr BAUD1CON
;
1705 unsigned ABDOVF
: 1;
1708 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
1715 #define _ABDOVF 0x80
1717 //==============================================================================
1720 //==============================================================================
1723 extern __at(0x019F) __sfr BAUDCON
;
1734 unsigned ABDOVF
: 1;
1737 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
1739 #define _BAUDCON_ABDEN 0x01
1740 #define _BAUDCON_WUE 0x02
1741 #define _BAUDCON_BRG16 0x08
1742 #define _BAUDCON_SCKP 0x10
1743 #define _BAUDCON_RCIDL 0x40
1744 #define _BAUDCON_ABDOVF 0x80
1746 //==============================================================================
1749 //==============================================================================
1752 extern __at(0x019F) __sfr BAUDCON1
;
1763 unsigned ABDOVF
: 1;
1766 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
1768 #define _BAUDCON1_ABDEN 0x01
1769 #define _BAUDCON1_WUE 0x02
1770 #define _BAUDCON1_BRG16 0x08
1771 #define _BAUDCON1_SCKP 0x10
1772 #define _BAUDCON1_RCIDL 0x40
1773 #define _BAUDCON1_ABDOVF 0x80
1775 //==============================================================================
1778 //==============================================================================
1781 extern __at(0x019F) __sfr BAUDCTL
;
1792 unsigned ABDOVF
: 1;
1795 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
1797 #define _BAUDCTL_ABDEN 0x01
1798 #define _BAUDCTL_WUE 0x02
1799 #define _BAUDCTL_BRG16 0x08
1800 #define _BAUDCTL_SCKP 0x10
1801 #define _BAUDCTL_RCIDL 0x40
1802 #define _BAUDCTL_ABDOVF 0x80
1804 //==============================================================================
1807 //==============================================================================
1810 extern __at(0x019F) __sfr BAUDCTL1
;
1821 unsigned ABDOVF
: 1;
1824 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
1826 #define _BAUDCTL1_ABDEN 0x01
1827 #define _BAUDCTL1_WUE 0x02
1828 #define _BAUDCTL1_BRG16 0x08
1829 #define _BAUDCTL1_SCKP 0x10
1830 #define _BAUDCTL1_RCIDL 0x40
1831 #define _BAUDCTL1_ABDOVF 0x80
1833 //==============================================================================
1836 //==============================================================================
1839 extern __at(0x020C) __sfr WPUA
;
1862 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
1871 //==============================================================================
1874 //==============================================================================
1877 extern __at(0x0211) __sfr SSP1BUF
;
1883 unsigned SSP1BUF0
: 1;
1884 unsigned SSP1BUF1
: 1;
1885 unsigned SSP1BUF2
: 1;
1886 unsigned SSP1BUF3
: 1;
1887 unsigned SSP1BUF4
: 1;
1888 unsigned SSP1BUF5
: 1;
1889 unsigned SSP1BUF6
: 1;
1890 unsigned SSP1BUF7
: 1;
1906 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
1908 #define _SSP1BUF0 0x01
1910 #define _SSP1BUF1 0x02
1912 #define _SSP1BUF2 0x04
1914 #define _SSP1BUF3 0x08
1916 #define _SSP1BUF4 0x10
1918 #define _SSP1BUF5 0x20
1920 #define _SSP1BUF6 0x40
1922 #define _SSP1BUF7 0x80
1925 //==============================================================================
1928 //==============================================================================
1931 extern __at(0x0211) __sfr SSPBUF
;
1937 unsigned SSP1BUF0
: 1;
1938 unsigned SSP1BUF1
: 1;
1939 unsigned SSP1BUF2
: 1;
1940 unsigned SSP1BUF3
: 1;
1941 unsigned SSP1BUF4
: 1;
1942 unsigned SSP1BUF5
: 1;
1943 unsigned SSP1BUF6
: 1;
1944 unsigned SSP1BUF7
: 1;
1960 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
1962 #define _SSPBUF_SSP1BUF0 0x01
1963 #define _SSPBUF_BUF0 0x01
1964 #define _SSPBUF_SSP1BUF1 0x02
1965 #define _SSPBUF_BUF1 0x02
1966 #define _SSPBUF_SSP1BUF2 0x04
1967 #define _SSPBUF_BUF2 0x04
1968 #define _SSPBUF_SSP1BUF3 0x08
1969 #define _SSPBUF_BUF3 0x08
1970 #define _SSPBUF_SSP1BUF4 0x10
1971 #define _SSPBUF_BUF4 0x10
1972 #define _SSPBUF_SSP1BUF5 0x20
1973 #define _SSPBUF_BUF5 0x20
1974 #define _SSPBUF_SSP1BUF6 0x40
1975 #define _SSPBUF_BUF6 0x40
1976 #define _SSPBUF_SSP1BUF7 0x80
1977 #define _SSPBUF_BUF7 0x80
1979 //==============================================================================
1982 //==============================================================================
1985 extern __at(0x0212) __sfr SSP1ADD
;
1991 unsigned SSP1ADD0
: 1;
1992 unsigned SSP1ADD1
: 1;
1993 unsigned SSP1ADD2
: 1;
1994 unsigned SSP1ADD3
: 1;
1995 unsigned SSP1ADD4
: 1;
1996 unsigned SSP1ADD5
: 1;
1997 unsigned SSP1ADD6
: 1;
1998 unsigned SSP1ADD7
: 1;
2014 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
2016 #define _SSP1ADD0 0x01
2018 #define _SSP1ADD1 0x02
2020 #define _SSP1ADD2 0x04
2022 #define _SSP1ADD3 0x08
2024 #define _SSP1ADD4 0x10
2026 #define _SSP1ADD5 0x20
2028 #define _SSP1ADD6 0x40
2030 #define _SSP1ADD7 0x80
2033 //==============================================================================
2036 //==============================================================================
2039 extern __at(0x0212) __sfr SSPADD
;
2045 unsigned SSP1ADD0
: 1;
2046 unsigned SSP1ADD1
: 1;
2047 unsigned SSP1ADD2
: 1;
2048 unsigned SSP1ADD3
: 1;
2049 unsigned SSP1ADD4
: 1;
2050 unsigned SSP1ADD5
: 1;
2051 unsigned SSP1ADD6
: 1;
2052 unsigned SSP1ADD7
: 1;
2068 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
2070 #define _SSPADD_SSP1ADD0 0x01
2071 #define _SSPADD_ADD0 0x01
2072 #define _SSPADD_SSP1ADD1 0x02
2073 #define _SSPADD_ADD1 0x02
2074 #define _SSPADD_SSP1ADD2 0x04
2075 #define _SSPADD_ADD2 0x04
2076 #define _SSPADD_SSP1ADD3 0x08
2077 #define _SSPADD_ADD3 0x08
2078 #define _SSPADD_SSP1ADD4 0x10
2079 #define _SSPADD_ADD4 0x10
2080 #define _SSPADD_SSP1ADD5 0x20
2081 #define _SSPADD_ADD5 0x20
2082 #define _SSPADD_SSP1ADD6 0x40
2083 #define _SSPADD_ADD6 0x40
2084 #define _SSPADD_SSP1ADD7 0x80
2085 #define _SSPADD_ADD7 0x80
2087 //==============================================================================
2090 //==============================================================================
2093 extern __at(0x0213) __sfr SSP1MSK
;
2099 unsigned SSP1MSK0
: 1;
2100 unsigned SSP1MSK1
: 1;
2101 unsigned SSP1MSK2
: 1;
2102 unsigned SSP1MSK3
: 1;
2103 unsigned SSP1MSK4
: 1;
2104 unsigned SSP1MSK5
: 1;
2105 unsigned SSP1MSK6
: 1;
2106 unsigned SSP1MSK7
: 1;
2122 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
2124 #define _SSP1MSK0 0x01
2126 #define _SSP1MSK1 0x02
2128 #define _SSP1MSK2 0x04
2130 #define _SSP1MSK3 0x08
2132 #define _SSP1MSK4 0x10
2134 #define _SSP1MSK5 0x20
2136 #define _SSP1MSK6 0x40
2138 #define _SSP1MSK7 0x80
2141 //==============================================================================
2144 //==============================================================================
2147 extern __at(0x0213) __sfr SSPMSK
;
2153 unsigned SSP1MSK0
: 1;
2154 unsigned SSP1MSK1
: 1;
2155 unsigned SSP1MSK2
: 1;
2156 unsigned SSP1MSK3
: 1;
2157 unsigned SSP1MSK4
: 1;
2158 unsigned SSP1MSK5
: 1;
2159 unsigned SSP1MSK6
: 1;
2160 unsigned SSP1MSK7
: 1;
2176 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
2178 #define _SSPMSK_SSP1MSK0 0x01
2179 #define _SSPMSK_MSK0 0x01
2180 #define _SSPMSK_SSP1MSK1 0x02
2181 #define _SSPMSK_MSK1 0x02
2182 #define _SSPMSK_SSP1MSK2 0x04
2183 #define _SSPMSK_MSK2 0x04
2184 #define _SSPMSK_SSP1MSK3 0x08
2185 #define _SSPMSK_MSK3 0x08
2186 #define _SSPMSK_SSP1MSK4 0x10
2187 #define _SSPMSK_MSK4 0x10
2188 #define _SSPMSK_SSP1MSK5 0x20
2189 #define _SSPMSK_MSK5 0x20
2190 #define _SSPMSK_SSP1MSK6 0x40
2191 #define _SSPMSK_MSK6 0x40
2192 #define _SSPMSK_SSP1MSK7 0x80
2193 #define _SSPMSK_MSK7 0x80
2195 //==============================================================================
2198 //==============================================================================
2201 extern __at(0x0214) __sfr SSP1STAT
;
2207 unsigned R_NOT_W
: 1;
2210 unsigned D_NOT_A
: 1;
2215 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
2219 #define _R_NOT_W 0x04
2222 #define _D_NOT_A 0x20
2226 //==============================================================================
2229 //==============================================================================
2232 extern __at(0x0214) __sfr SSPSTAT
;
2238 unsigned R_NOT_W
: 1;
2241 unsigned D_NOT_A
: 1;
2246 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
2248 #define _SSPSTAT_BF 0x01
2249 #define _SSPSTAT_UA 0x02
2250 #define _SSPSTAT_R_NOT_W 0x04
2251 #define _SSPSTAT_S 0x08
2252 #define _SSPSTAT_P 0x10
2253 #define _SSPSTAT_D_NOT_A 0x20
2254 #define _SSPSTAT_CKE 0x40
2255 #define _SSPSTAT_SMP 0x80
2257 //==============================================================================
2260 //==============================================================================
2263 extern __at(0x0215) __sfr SSP1CON
;
2286 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
2297 //==============================================================================
2300 //==============================================================================
2303 extern __at(0x0215) __sfr SSP1CON1
;
2326 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
2328 #define _SSP1CON1_SSPM0 0x01
2329 #define _SSP1CON1_SSPM1 0x02
2330 #define _SSP1CON1_SSPM2 0x04
2331 #define _SSP1CON1_SSPM3 0x08
2332 #define _SSP1CON1_CKP 0x10
2333 #define _SSP1CON1_SSPEN 0x20
2334 #define _SSP1CON1_SSPOV 0x40
2335 #define _SSP1CON1_WCOL 0x80
2337 //==============================================================================
2340 //==============================================================================
2343 extern __at(0x0215) __sfr SSPCON
;
2366 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2368 #define _SSPCON_SSPM0 0x01
2369 #define _SSPCON_SSPM1 0x02
2370 #define _SSPCON_SSPM2 0x04
2371 #define _SSPCON_SSPM3 0x08
2372 #define _SSPCON_CKP 0x10
2373 #define _SSPCON_SSPEN 0x20
2374 #define _SSPCON_SSPOV 0x40
2375 #define _SSPCON_WCOL 0x80
2377 //==============================================================================
2380 //==============================================================================
2383 extern __at(0x0215) __sfr SSPCON1
;
2406 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2408 #define _SSPCON1_SSPM0 0x01
2409 #define _SSPCON1_SSPM1 0x02
2410 #define _SSPCON1_SSPM2 0x04
2411 #define _SSPCON1_SSPM3 0x08
2412 #define _SSPCON1_CKP 0x10
2413 #define _SSPCON1_SSPEN 0x20
2414 #define _SSPCON1_SSPOV 0x40
2415 #define _SSPCON1_WCOL 0x80
2417 //==============================================================================
2420 //==============================================================================
2423 extern __at(0x0216) __sfr SSP1CON2
;
2433 unsigned ACKSTAT
: 1;
2437 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
2445 #define _ACKSTAT 0x40
2448 //==============================================================================
2451 //==============================================================================
2454 extern __at(0x0216) __sfr SSPCON2
;
2464 unsigned ACKSTAT
: 1;
2468 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
2470 #define _SSPCON2_SEN 0x01
2471 #define _SSPCON2_RSEN 0x02
2472 #define _SSPCON2_PEN 0x04
2473 #define _SSPCON2_RCEN 0x08
2474 #define _SSPCON2_ACKEN 0x10
2475 #define _SSPCON2_ACKDT 0x20
2476 #define _SSPCON2_ACKSTAT 0x40
2477 #define _SSPCON2_GCEN 0x80
2479 //==============================================================================
2482 //==============================================================================
2485 extern __at(0x0217) __sfr SSP1CON3
;
2496 unsigned ACKTIM
: 1;
2499 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
2508 #define _ACKTIM 0x80
2510 //==============================================================================
2513 //==============================================================================
2516 extern __at(0x0217) __sfr SSPCON3
;
2527 unsigned ACKTIM
: 1;
2530 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
2532 #define _SSPCON3_DHEN 0x01
2533 #define _SSPCON3_AHEN 0x02
2534 #define _SSPCON3_SBCDE 0x04
2535 #define _SSPCON3_SDAHT 0x08
2536 #define _SSPCON3_BOEN 0x10
2537 #define _SSPCON3_SCIE 0x20
2538 #define _SSPCON3_PCIE 0x40
2539 #define _SSPCON3_ACKTIM 0x80
2541 //==============================================================================
2544 //==============================================================================
2547 extern __at(0x028C) __sfr ODCONA
;
2561 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
2569 //==============================================================================
2571 extern __at(0x0291) __sfr CCPR1
;
2572 extern __at(0x0291) __sfr CCPR1L
;
2573 extern __at(0x0292) __sfr CCPR1H
;
2575 //==============================================================================
2578 extern __at(0x0293) __sfr CCP1CON
;
2584 unsigned CCP1MODE0
: 1;
2585 unsigned CCP1MODE1
: 1;
2586 unsigned CCP1MODE2
: 1;
2587 unsigned CCP1MODE3
: 1;
2588 unsigned CCP1FMT
: 1;
2589 unsigned CCP1OUT
: 1;
2591 unsigned CCP1EN
: 1;
2596 unsigned CCP1MODE
: 4;
2601 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
2603 #define _CCP1MODE0 0x01
2604 #define _CCP1MODE1 0x02
2605 #define _CCP1MODE2 0x04
2606 #define _CCP1MODE3 0x08
2607 #define _CCP1FMT 0x10
2608 #define _CCP1OUT 0x20
2609 #define _CCP1EN 0x80
2611 //==============================================================================
2614 //==============================================================================
2617 extern __at(0x0294) __sfr CCP1CAP
;
2623 unsigned CCP1CTS0
: 1;
2624 unsigned CCP1CTS1
: 1;
2625 unsigned CCP1CTS2
: 1;
2635 unsigned CCP1CTS
: 3;
2640 extern __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits
;
2642 #define _CCP1CTS0 0x01
2643 #define _CCP1CTS1 0x02
2644 #define _CCP1CTS2 0x04
2646 //==============================================================================
2648 extern __at(0x0295) __sfr CCPR2
;
2649 extern __at(0x0295) __sfr CCPR2L
;
2650 extern __at(0x0296) __sfr CCPR2H
;
2652 //==============================================================================
2655 extern __at(0x0297) __sfr CCP2CON
;
2661 unsigned CCP2MODE0
: 1;
2662 unsigned CCP2MODE1
: 1;
2663 unsigned CCP2MODE2
: 1;
2664 unsigned CCP2MODE3
: 1;
2665 unsigned CCP2FMT
: 1;
2666 unsigned CCP2OUT
: 1;
2668 unsigned CCP2EN
: 1;
2673 unsigned CCP2MODE
: 4;
2678 extern __at(0x0297) volatile __CCP2CONbits_t CCP2CONbits
;
2680 #define _CCP2MODE0 0x01
2681 #define _CCP2MODE1 0x02
2682 #define _CCP2MODE2 0x04
2683 #define _CCP2MODE3 0x08
2684 #define _CCP2FMT 0x10
2685 #define _CCP2OUT 0x20
2686 #define _CCP2EN 0x80
2688 //==============================================================================
2691 //==============================================================================
2694 extern __at(0x0298) __sfr CCP2CAP
;
2700 unsigned CCP2CTS0
: 1;
2701 unsigned CCP2CTS1
: 1;
2702 unsigned CCP2CTS2
: 1;
2712 unsigned CCP2CTS
: 3;
2717 extern __at(0x0298) volatile __CCP2CAPbits_t CCP2CAPbits
;
2719 #define _CCP2CTS0 0x01
2720 #define _CCP2CTS1 0x02
2721 #define _CCP2CTS2 0x04
2723 //==============================================================================
2726 //==============================================================================
2729 extern __at(0x029F) __sfr CCPTMRS
;
2733 unsigned C1TSEL
: 1;
2735 unsigned C2TSEL
: 1;
2743 extern __at(0x029F) volatile __CCPTMRSbits_t CCPTMRSbits
;
2745 #define _C1TSEL 0x01
2746 #define _C2TSEL 0x04
2748 //==============================================================================
2751 //==============================================================================
2754 extern __at(0x030C) __sfr SLRCONA
;
2768 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
2776 //==============================================================================
2779 //==============================================================================
2782 extern __at(0x038C) __sfr INLVLA
;
2788 unsigned INLVLA0
: 1;
2789 unsigned INLVLA1
: 1;
2790 unsigned INLVLA2
: 1;
2791 unsigned INLVLA3
: 1;
2792 unsigned INLVLA4
: 1;
2793 unsigned INLVLA5
: 1;
2800 unsigned INLVLA
: 6;
2805 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
2807 #define _INLVLA0 0x01
2808 #define _INLVLA1 0x02
2809 #define _INLVLA2 0x04
2810 #define _INLVLA3 0x08
2811 #define _INLVLA4 0x10
2812 #define _INLVLA5 0x20
2814 //==============================================================================
2817 //==============================================================================
2820 extern __at(0x0391) __sfr IOCAP
;
2826 unsigned IOCAP0
: 1;
2827 unsigned IOCAP1
: 1;
2828 unsigned IOCAP2
: 1;
2829 unsigned IOCAP3
: 1;
2830 unsigned IOCAP4
: 1;
2831 unsigned IOCAP5
: 1;
2843 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
2845 #define _IOCAP0 0x01
2846 #define _IOCAP1 0x02
2847 #define _IOCAP2 0x04
2848 #define _IOCAP3 0x08
2849 #define _IOCAP4 0x10
2850 #define _IOCAP5 0x20
2852 //==============================================================================
2855 //==============================================================================
2858 extern __at(0x0392) __sfr IOCAN
;
2864 unsigned IOCAN0
: 1;
2865 unsigned IOCAN1
: 1;
2866 unsigned IOCAN2
: 1;
2867 unsigned IOCAN3
: 1;
2868 unsigned IOCAN4
: 1;
2869 unsigned IOCAN5
: 1;
2881 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
2883 #define _IOCAN0 0x01
2884 #define _IOCAN1 0x02
2885 #define _IOCAN2 0x04
2886 #define _IOCAN3 0x08
2887 #define _IOCAN4 0x10
2888 #define _IOCAN5 0x20
2890 //==============================================================================
2893 //==============================================================================
2896 extern __at(0x0393) __sfr IOCAF
;
2902 unsigned IOCAF0
: 1;
2903 unsigned IOCAF1
: 1;
2904 unsigned IOCAF2
: 1;
2905 unsigned IOCAF3
: 1;
2906 unsigned IOCAF4
: 1;
2907 unsigned IOCAF5
: 1;
2919 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
2921 #define _IOCAF0 0x01
2922 #define _IOCAF1 0x02
2923 #define _IOCAF2 0x04
2924 #define _IOCAF3 0x08
2925 #define _IOCAF4 0x10
2926 #define _IOCAF5 0x20
2928 //==============================================================================
2931 //==============================================================================
2934 extern __at(0x039A) __sfr CLKRCON
;
2940 unsigned CLKRDIV0
: 1;
2941 unsigned CLKRDIV1
: 1;
2942 unsigned CLKRDIV2
: 1;
2943 unsigned CLKRDC0
: 1;
2944 unsigned CLKRDC1
: 1;
2947 unsigned CLKREN
: 1;
2952 unsigned CLKRDIV
: 3;
2959 unsigned CLKRDC
: 2;
2964 extern __at(0x039A) volatile __CLKRCONbits_t CLKRCONbits
;
2966 #define _CLKRDIV0 0x01
2967 #define _CLKRDIV1 0x02
2968 #define _CLKRDIV2 0x04
2969 #define _CLKRDC0 0x08
2970 #define _CLKRDC1 0x10
2971 #define _CLKREN 0x80
2973 //==============================================================================
2976 //==============================================================================
2979 extern __at(0x039C) __sfr MDCON
;
2987 unsigned MDOPOL
: 1;
2993 extern __at(0x039C) volatile __MDCONbits_t MDCONbits
;
2997 #define _MDOPOL 0x10
3000 //==============================================================================
3003 //==============================================================================
3006 extern __at(0x039D) __sfr MDSRC
;
3029 extern __at(0x039D) volatile __MDSRCbits_t MDSRCbits
;
3036 //==============================================================================
3039 //==============================================================================
3042 extern __at(0x039E) __sfr MDCARH
;
3053 unsigned MDCHSYNC
: 1;
3054 unsigned MDCHPOL
: 1;
3065 extern __at(0x039E) volatile __MDCARHbits_t MDCARHbits
;
3071 #define _MDCHSYNC 0x20
3072 #define _MDCHPOL 0x40
3074 //==============================================================================
3077 //==============================================================================
3080 extern __at(0x039F) __sfr MDCARL
;
3091 unsigned MDCLSYNC
: 1;
3092 unsigned MDCLPOL
: 1;
3103 extern __at(0x039F) volatile __MDCARLbits_t MDCARLbits
;
3109 #define _MDCLSYNC 0x20
3110 #define _MDCLPOL 0x40
3112 //==============================================================================
3115 //==============================================================================
3118 extern __at(0x040C) __sfr CCDNA
;
3122 unsigned CCDNA0
: 1;
3123 unsigned CCDNA1
: 1;
3124 unsigned CCDNA2
: 1;
3126 unsigned CCDNA4
: 1;
3127 unsigned CCDNA5
: 1;
3132 extern __at(0x040C) volatile __CCDNAbits_t CCDNAbits
;
3134 #define _CCDNA0 0x01
3135 #define _CCDNA1 0x02
3136 #define _CCDNA2 0x04
3137 #define _CCDNA4 0x10
3138 #define _CCDNA5 0x20
3140 //==============================================================================
3143 //==============================================================================
3146 extern __at(0x041F) __sfr CCDCON
;
3169 extern __at(0x041F) volatile __CCDCONbits_t CCDCONbits
;
3175 //==============================================================================
3178 //==============================================================================
3181 extern __at(0x048C) __sfr CCDPA
;
3185 unsigned CCDPA0
: 1;
3186 unsigned CCDPA1
: 1;
3187 unsigned CCDPA2
: 1;
3189 unsigned CCDPA4
: 1;
3190 unsigned CCDPA5
: 1;
3195 extern __at(0x048C) volatile __CCDPAbits_t CCDPAbits
;
3197 #define _CCDPA0 0x01
3198 #define _CCDPA1 0x02
3199 #define _CCDPA2 0x04
3200 #define _CCDPA4 0x10
3201 #define _CCDPA5 0x20
3203 //==============================================================================
3205 extern __at(0x0498) __sfr NCO1ACC
;
3206 extern __at(0x0498) __sfr NCO1ACCL
;
3207 extern __at(0x0499) __sfr NCO1ACCH
;
3208 extern __at(0x049A) __sfr NCO1ACCU
;
3209 extern __at(0x049B) __sfr NCO1INC
;
3210 extern __at(0x049B) __sfr NCO1INCL
;
3211 extern __at(0x049C) __sfr NCO1INCH
;
3212 extern __at(0x049D) __sfr NCO1INCU
;
3214 //==============================================================================
3217 extern __at(0x049E) __sfr NCO1CON
;
3231 extern __at(0x049E) volatile __NCO1CONbits_t NCO1CONbits
;
3238 //==============================================================================
3240 extern __at(0x049F) __sfr NCO1CLK
;
3242 //==============================================================================
3245 extern __at(0x0617) __sfr PWM5DCL
;
3257 unsigned PWM5DCL0
: 1;
3258 unsigned PWM5DCL1
: 1;
3264 unsigned PWM5DCL
: 2;
3268 extern __at(0x0617) volatile __PWM5DCLbits_t PWM5DCLbits
;
3270 #define _PWM5DCL0 0x40
3271 #define _PWM5DCL1 0x80
3273 //==============================================================================
3276 //==============================================================================
3279 extern __at(0x0618) __sfr PWM5DCH
;
3283 unsigned PWM5DCH0
: 1;
3284 unsigned PWM5DCH1
: 1;
3285 unsigned PWM5DCH2
: 1;
3286 unsigned PWM5DCH3
: 1;
3287 unsigned PWM5DCH4
: 1;
3288 unsigned PWM5DCH5
: 1;
3289 unsigned PWM5DCH6
: 1;
3290 unsigned PWM5DCH7
: 1;
3293 extern __at(0x0618) volatile __PWM5DCHbits_t PWM5DCHbits
;
3295 #define _PWM5DCH0 0x01
3296 #define _PWM5DCH1 0x02
3297 #define _PWM5DCH2 0x04
3298 #define _PWM5DCH3 0x08
3299 #define _PWM5DCH4 0x10
3300 #define _PWM5DCH5 0x20
3301 #define _PWM5DCH6 0x40
3302 #define _PWM5DCH7 0x80
3304 //==============================================================================
3307 //==============================================================================
3310 extern __at(0x0619) __sfr PWM5CON
;
3318 unsigned PWM5POL
: 1;
3319 unsigned PWM5OUT
: 1;
3321 unsigned PWM5EN
: 1;
3324 extern __at(0x0619) volatile __PWM5CONbits_t PWM5CONbits
;
3326 #define _PWM5POL 0x10
3327 #define _PWM5OUT 0x20
3328 #define _PWM5EN 0x80
3330 //==============================================================================
3333 //==============================================================================
3336 extern __at(0x0619) __sfr PWM5CON0
;
3344 unsigned PWM5POL
: 1;
3345 unsigned PWM5OUT
: 1;
3347 unsigned PWM5EN
: 1;
3350 extern __at(0x0619) volatile __PWM5CON0bits_t PWM5CON0bits
;
3352 #define _PWM5CON0_PWM5POL 0x10
3353 #define _PWM5CON0_PWM5OUT 0x20
3354 #define _PWM5CON0_PWM5EN 0x80
3356 //==============================================================================
3359 //==============================================================================
3362 extern __at(0x061A) __sfr PWM6DCL
;
3374 unsigned PWM6DCL0
: 1;
3375 unsigned PWM6DCL1
: 1;
3381 unsigned PWM6DCL
: 2;
3385 extern __at(0x061A) volatile __PWM6DCLbits_t PWM6DCLbits
;
3387 #define _PWM6DCL0 0x40
3388 #define _PWM6DCL1 0x80
3390 //==============================================================================
3393 //==============================================================================
3396 extern __at(0x061B) __sfr PWM6DCH
;
3400 unsigned PWM6DCH0
: 1;
3401 unsigned PWM6DCH1
: 1;
3402 unsigned PWM6DCH2
: 1;
3403 unsigned PWM6DCH3
: 1;
3404 unsigned PWM6DCH4
: 1;
3405 unsigned PWM6DCH5
: 1;
3406 unsigned PWM6DCH6
: 1;
3407 unsigned PWM6DCH7
: 1;
3410 extern __at(0x061B) volatile __PWM6DCHbits_t PWM6DCHbits
;
3412 #define _PWM6DCH0 0x01
3413 #define _PWM6DCH1 0x02
3414 #define _PWM6DCH2 0x04
3415 #define _PWM6DCH3 0x08
3416 #define _PWM6DCH4 0x10
3417 #define _PWM6DCH5 0x20
3418 #define _PWM6DCH6 0x40
3419 #define _PWM6DCH7 0x80
3421 //==============================================================================
3424 //==============================================================================
3427 extern __at(0x061C) __sfr PWM6CON
;
3435 unsigned PWM6POL
: 1;
3436 unsigned PWM6OUT
: 1;
3438 unsigned PWM6EN
: 1;
3441 extern __at(0x061C) volatile __PWM6CONbits_t PWM6CONbits
;
3443 #define _PWM6POL 0x10
3444 #define _PWM6OUT 0x20
3445 #define _PWM6EN 0x80
3447 //==============================================================================
3450 //==============================================================================
3453 extern __at(0x061C) __sfr PWM6CON0
;
3461 unsigned PWM6POL
: 1;
3462 unsigned PWM6OUT
: 1;
3464 unsigned PWM6EN
: 1;
3467 extern __at(0x061C) volatile __PWM6CON0bits_t PWM6CON0bits
;
3469 #define _PWM6CON0_PWM6POL 0x10
3470 #define _PWM6CON0_PWM6OUT 0x20
3471 #define _PWM6CON0_PWM6EN 0x80
3473 //==============================================================================
3476 //==============================================================================
3479 extern __at(0x0691) __sfr CWG1CLKCON
;
3497 unsigned CWG1CS
: 1;
3506 } __CWG1CLKCONbits_t
;
3508 extern __at(0x0691) volatile __CWG1CLKCONbits_t CWG1CLKCONbits
;
3511 #define _CWG1CS 0x01
3513 //==============================================================================
3516 //==============================================================================
3519 extern __at(0x0692) __sfr CWG1DAT
;
3525 unsigned CWG1DAT0
: 1;
3526 unsigned CWG1DAT1
: 1;
3527 unsigned CWG1DAT2
: 1;
3528 unsigned CWG1DAT3
: 1;
3537 unsigned CWG1DAT
: 4;
3542 extern __at(0x0692) volatile __CWG1DATbits_t CWG1DATbits
;
3544 #define _CWG1DAT0 0x01
3545 #define _CWG1DAT1 0x02
3546 #define _CWG1DAT2 0x04
3547 #define _CWG1DAT3 0x08
3549 //==============================================================================
3552 //==============================================================================
3555 extern __at(0x0693) __sfr CWG1DBR
;
3573 unsigned CWG1DBR0
: 1;
3574 unsigned CWG1DBR1
: 1;
3575 unsigned CWG1DBR2
: 1;
3576 unsigned CWG1DBR3
: 1;
3577 unsigned CWG1DBR4
: 1;
3578 unsigned CWG1DBR5
: 1;
3585 unsigned CWG1DBR
: 6;
3596 extern __at(0x0693) volatile __CWG1DBRbits_t CWG1DBRbits
;
3599 #define _CWG1DBR0 0x01
3601 #define _CWG1DBR1 0x02
3603 #define _CWG1DBR2 0x04
3605 #define _CWG1DBR3 0x08
3607 #define _CWG1DBR4 0x10
3609 #define _CWG1DBR5 0x20
3611 //==============================================================================
3614 //==============================================================================
3617 extern __at(0x0694) __sfr CWG1DBF
;
3635 unsigned CWG1DBF0
: 1;
3636 unsigned CWG1DBF1
: 1;
3637 unsigned CWG1DBF2
: 1;
3638 unsigned CWG1DBF3
: 1;
3639 unsigned CWG1DBF4
: 1;
3640 unsigned CWG1DBF5
: 1;
3653 unsigned CWG1DBF
: 6;
3658 extern __at(0x0694) volatile __CWG1DBFbits_t CWG1DBFbits
;
3661 #define _CWG1DBF0 0x01
3663 #define _CWG1DBF1 0x02
3665 #define _CWG1DBF2 0x04
3667 #define _CWG1DBF3 0x08
3669 #define _CWG1DBF4 0x10
3671 #define _CWG1DBF5 0x20
3673 //==============================================================================
3676 //==============================================================================
3679 extern __at(0x0695) __sfr CWG1CON0
;
3697 unsigned CWG1MODE0
: 1;
3698 unsigned CWG1MODE1
: 1;
3699 unsigned CWG1MODE2
: 1;
3703 unsigned CWG1LD
: 1;
3716 unsigned CWG1EN
: 1;
3721 unsigned CWG1MODE
: 3;
3732 extern __at(0x0695) volatile __CWG1CON0bits_t CWG1CON0bits
;
3734 #define _CWG1CON0_MODE0 0x01
3735 #define _CWG1CON0_CWG1MODE0 0x01
3736 #define _CWG1CON0_MODE1 0x02
3737 #define _CWG1CON0_CWG1MODE1 0x02
3738 #define _CWG1CON0_MODE2 0x04
3739 #define _CWG1CON0_CWG1MODE2 0x04
3740 #define _CWG1CON0_LD 0x40
3741 #define _CWG1CON0_CWG1LD 0x40
3742 #define _CWG1CON0_EN 0x80
3743 #define _CWG1CON0_G1EN 0x80
3744 #define _CWG1CON0_CWG1EN 0x80
3746 //==============================================================================
3749 //==============================================================================
3752 extern __at(0x0696) __sfr CWG1CON1
;
3770 unsigned CWG1POLA
: 1;
3771 unsigned CWG1POLB
: 1;
3772 unsigned CWG1POLC
: 1;
3773 unsigned CWG1POLD
: 1;
3775 unsigned CWG1IN
: 1;
3781 extern __at(0x0696) volatile __CWG1CON1bits_t CWG1CON1bits
;
3784 #define _CWG1POLA 0x01
3786 #define _CWG1POLB 0x02
3788 #define _CWG1POLC 0x04
3790 #define _CWG1POLD 0x08
3792 #define _CWG1IN 0x20
3794 //==============================================================================
3797 //==============================================================================
3800 extern __at(0x0697) __sfr CWG1AS0
;
3813 unsigned SHUTDOWN
: 1;
3820 unsigned CWG1LSAC0
: 1;
3821 unsigned CWG1LSAC1
: 1;
3822 unsigned CWG1LSBD0
: 1;
3823 unsigned CWG1LSBD1
: 1;
3824 unsigned CWG1REN
: 1;
3825 unsigned CWG1SHUTDOWN
: 1;
3831 unsigned CWG1LSAC
: 2;
3852 unsigned CWG1LSBD
: 2;
3857 extern __at(0x0697) volatile __CWG1AS0bits_t CWG1AS0bits
;
3860 #define _CWG1LSAC0 0x04
3862 #define _CWG1LSAC1 0x08
3864 #define _CWG1LSBD0 0x10
3866 #define _CWG1LSBD1 0x20
3868 #define _CWG1REN 0x40
3869 #define _SHUTDOWN 0x80
3870 #define _CWG1SHUTDOWN 0x80
3872 //==============================================================================
3875 //==============================================================================
3878 extern __at(0x0698) __sfr CWG1AS1
;
3892 extern __at(0x0698) volatile __CWG1AS1bits_t CWG1AS1bits
;
3898 //==============================================================================
3901 //==============================================================================
3904 extern __at(0x0699) __sfr CWG1STR
;
3922 unsigned CWG1STRA
: 1;
3923 unsigned CWG1STRB
: 1;
3924 unsigned CWG1STRC
: 1;
3925 unsigned CWG1STRD
: 1;
3926 unsigned CWG1OVRA
: 1;
3927 unsigned CWG1OVRB
: 1;
3928 unsigned CWG1OVRC
: 1;
3929 unsigned CWG1OVRD
: 1;
3933 extern __at(0x0699) volatile __CWG1STRbits_t CWG1STRbits
;
3936 #define _CWG1STRA 0x01
3938 #define _CWG1STRB 0x02
3940 #define _CWG1STRC 0x04
3942 #define _CWG1STRD 0x08
3944 #define _CWG1OVRA 0x10
3946 #define _CWG1OVRB 0x20
3948 #define _CWG1OVRC 0x40
3950 #define _CWG1OVRD 0x80
3952 //==============================================================================
3954 extern __at(0x0891) __sfr NVMADR
;
3956 //==============================================================================
3959 extern __at(0x0891) __sfr NVMADRL
;
3963 unsigned NVMADR0
: 1;
3964 unsigned NVMADR1
: 1;
3965 unsigned NVMADR2
: 1;
3966 unsigned NVMADR3
: 1;
3967 unsigned NVMADR4
: 1;
3968 unsigned NVMADR5
: 1;
3969 unsigned NVMADR6
: 1;
3970 unsigned NVMADR7
: 1;
3973 extern __at(0x0891) volatile __NVMADRLbits_t NVMADRLbits
;
3975 #define _NVMADR0 0x01
3976 #define _NVMADR1 0x02
3977 #define _NVMADR2 0x04
3978 #define _NVMADR3 0x08
3979 #define _NVMADR4 0x10
3980 #define _NVMADR5 0x20
3981 #define _NVMADR6 0x40
3982 #define _NVMADR7 0x80
3984 //==============================================================================
3987 //==============================================================================
3990 extern __at(0x0892) __sfr NVMADRH
;
3994 unsigned NVMADR8
: 1;
3995 unsigned NVMADR9
: 1;
3996 unsigned NVMADR10
: 1;
3997 unsigned NVMADR11
: 1;
3998 unsigned NVMADR12
: 1;
3999 unsigned NVMADR13
: 1;
4000 unsigned NVMADR14
: 1;
4004 extern __at(0x0892) volatile __NVMADRHbits_t NVMADRHbits
;
4006 #define _NVMADR8 0x01
4007 #define _NVMADR9 0x02
4008 #define _NVMADR10 0x04
4009 #define _NVMADR11 0x08
4010 #define _NVMADR12 0x10
4011 #define _NVMADR13 0x20
4012 #define _NVMADR14 0x40
4014 //==============================================================================
4016 extern __at(0x0893) __sfr NVMDAT
;
4018 //==============================================================================
4021 extern __at(0x0893) __sfr NVMDATL
;
4025 unsigned NVMDAT0
: 1;
4026 unsigned NVMDAT1
: 1;
4027 unsigned NVMDAT2
: 1;
4028 unsigned NVMDAT3
: 1;
4029 unsigned NVMDAT4
: 1;
4030 unsigned NVMDAT5
: 1;
4031 unsigned NVMDAT6
: 1;
4032 unsigned NVMDAT7
: 1;
4035 extern __at(0x0893) volatile __NVMDATLbits_t NVMDATLbits
;
4037 #define _NVMDAT0 0x01
4038 #define _NVMDAT1 0x02
4039 #define _NVMDAT2 0x04
4040 #define _NVMDAT3 0x08
4041 #define _NVMDAT4 0x10
4042 #define _NVMDAT5 0x20
4043 #define _NVMDAT6 0x40
4044 #define _NVMDAT7 0x80
4046 //==============================================================================
4049 //==============================================================================
4052 extern __at(0x0894) __sfr NVMDATH
;
4056 unsigned NVMDAT8
: 1;
4057 unsigned NVMDAT9
: 1;
4058 unsigned NVMDAT10
: 1;
4059 unsigned NVMDAT11
: 1;
4060 unsigned NVMDAT12
: 1;
4061 unsigned NVMDAT13
: 1;
4066 extern __at(0x0894) volatile __NVMDATHbits_t NVMDATHbits
;
4068 #define _NVMDAT8 0x01
4069 #define _NVMDAT9 0x02
4070 #define _NVMDAT10 0x04
4071 #define _NVMDAT11 0x08
4072 #define _NVMDAT12 0x10
4073 #define _NVMDAT13 0x20
4075 //==============================================================================
4078 //==============================================================================
4081 extern __at(0x0895) __sfr NVMCON1
;
4091 unsigned NVMREGS
: 1;
4095 extern __at(0x0895) volatile __NVMCON1bits_t NVMCON1bits
;
4103 #define _NVMREGS 0x40
4105 //==============================================================================
4107 extern __at(0x0896) __sfr NVMCON2
;
4109 //==============================================================================
4112 extern __at(0x089B) __sfr PCON0
;
4116 unsigned NOT_BOR
: 1;
4117 unsigned NOT_POR
: 1;
4118 unsigned NOT_RI
: 1;
4119 unsigned NOT_RMCLR
: 1;
4120 unsigned NOT_RWDT
: 1;
4122 unsigned STKUNF
: 1;
4123 unsigned STKOVF
: 1;
4126 extern __at(0x089B) volatile __PCON0bits_t PCON0bits
;
4128 #define _NOT_BOR 0x01
4129 #define _NOT_POR 0x02
4130 #define _NOT_RI 0x04
4131 #define _NOT_RMCLR 0x08
4132 #define _NOT_RWDT 0x10
4133 #define _STKUNF 0x40
4134 #define _STKOVF 0x80
4136 //==============================================================================
4139 //==============================================================================
4142 extern __at(0x0911) __sfr PMD0
;
4147 unsigned CLKRMD
: 1;
4153 unsigned SYSCMD
: 1;
4156 extern __at(0x0911) volatile __PMD0bits_t PMD0bits
;
4159 #define _CLKRMD 0x02
4162 #define _SYSCMD 0x80
4164 //==============================================================================
4167 //==============================================================================
4170 extern __at(0x0912) __sfr PMD1
;
4174 unsigned TMR0MD
: 1;
4175 unsigned TMR1MD
: 1;
4176 unsigned TMR2MD
: 1;
4184 extern __at(0x0912) volatile __PMD1bits_t PMD1bits
;
4186 #define _TMR0MD 0x01
4187 #define _TMR1MD 0x02
4188 #define _TMR2MD 0x04
4191 //==============================================================================
4194 //==============================================================================
4197 extern __at(0x0913) __sfr PMD2
;
4202 unsigned CMP1MD
: 1;
4211 extern __at(0x0913) volatile __PMD2bits_t PMD2bits
;
4213 #define _CMP1MD 0x02
4217 //==============================================================================
4220 //==============================================================================
4223 extern __at(0x0914) __sfr PMD3
;
4227 unsigned CCP1MD
: 1;
4228 unsigned CCP2MD
: 1;
4231 unsigned PWM5MD
: 1;
4232 unsigned PWM6MD
: 1;
4233 unsigned CWG1MD
: 1;
4237 extern __at(0x0914) volatile __PMD3bits_t PMD3bits
;
4239 #define _CCP1MD 0x01
4240 #define _CCP2MD 0x02
4241 #define _PWM5MD 0x10
4242 #define _PWM6MD 0x20
4243 #define _CWG1MD 0x40
4245 //==============================================================================
4248 //==============================================================================
4251 extern __at(0x0915) __sfr PMD4
;
4256 unsigned MSSP1MD
: 1;
4260 unsigned UART1MD
: 1;
4265 extern __at(0x0915) volatile __PMD4bits_t PMD4bits
;
4267 #define _MSSP1MD 0x02
4268 #define _UART1MD 0x20
4270 //==============================================================================
4273 //==============================================================================
4276 extern __at(0x0916) __sfr PMD5
;
4281 unsigned CLC1MD
: 1;
4282 unsigned CLC2MD
: 1;
4290 extern __at(0x0916) volatile __PMD5bits_t PMD5bits
;
4293 #define _CLC1MD 0x02
4294 #define _CLC2MD 0x04
4296 //==============================================================================
4299 //==============================================================================
4302 extern __at(0x0918) __sfr CPUDOZE
;
4325 extern __at(0x0918) volatile __CPUDOZEbits_t CPUDOZEbits
;
4335 //==============================================================================
4338 //==============================================================================
4341 extern __at(0x0919) __sfr OSCCON1
;
4371 extern __at(0x0919) volatile __OSCCON1bits_t OSCCON1bits
;
4381 //==============================================================================
4384 //==============================================================================
4387 extern __at(0x091A) __sfr OSCCON2
;
4417 extern __at(0x091A) volatile __OSCCON2bits_t OSCCON2bits
;
4427 //==============================================================================
4430 //==============================================================================
4433 extern __at(0x091B) __sfr OSCCON3
;
4442 unsigned SOSCBE
: 1;
4443 unsigned SOSCPWR
: 1;
4444 unsigned CSWHOLD
: 1;
4447 extern __at(0x091B) volatile __OSCCON3bits_t OSCCON3bits
;
4451 #define _SOSCBE 0x20
4452 #define _SOSCPWR 0x40
4453 #define _CSWHOLD 0x80
4455 //==============================================================================
4458 //==============================================================================
4461 extern __at(0x091C) __sfr OSCSTAT1
;
4475 extern __at(0x091C) volatile __OSCSTAT1bits_t OSCSTAT1bits
;
4484 //==============================================================================
4487 //==============================================================================
4490 extern __at(0x091D) __sfr OSCEN
;
4497 unsigned SOSCEN
: 1;
4501 unsigned EXTOEN
: 1;
4504 extern __at(0x091D) volatile __OSCENbits_t OSCENbits
;
4507 #define _SOSCEN 0x08
4510 #define _EXTOEN 0x80
4512 //==============================================================================
4515 //==============================================================================
4518 extern __at(0x091E) __sfr OSCTUNE
;
4524 unsigned HFTUN0
: 1;
4525 unsigned HFTUN1
: 1;
4526 unsigned HFTUN2
: 1;
4527 unsigned HFTUN3
: 1;
4528 unsigned HFTUN4
: 1;
4529 unsigned HFTUN5
: 1;
4541 extern __at(0x091E) volatile __OSCTUNEbits_t OSCTUNEbits
;
4543 #define _HFTUN0 0x01
4544 #define _HFTUN1 0x02
4545 #define _HFTUN2 0x04
4546 #define _HFTUN3 0x08
4547 #define _HFTUN4 0x10
4548 #define _HFTUN5 0x20
4550 //==============================================================================
4553 //==============================================================================
4556 extern __at(0x091F) __sfr OSCFRQ
;
4562 unsigned HFFRQ0
: 1;
4563 unsigned HFFRQ1
: 1;
4564 unsigned HFFRQ2
: 1;
4565 unsigned HFFRQ3
: 1;
4579 extern __at(0x091F) volatile __OSCFRQbits_t OSCFRQbits
;
4581 #define _HFFRQ0 0x01
4582 #define _HFFRQ1 0x02
4583 #define _HFFRQ2 0x04
4584 #define _HFFRQ3 0x08
4586 //==============================================================================
4589 //==============================================================================
4592 extern __at(0x0E0F) __sfr PPSLOCK
;
4596 unsigned PPSLOCKED
: 1;
4606 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
4608 #define _PPSLOCKED 0x01
4610 //==============================================================================
4613 //==============================================================================
4616 extern __at(0x0E10) __sfr INTPPS
;
4622 unsigned INTPPS0
: 1;
4623 unsigned INTPPS1
: 1;
4624 unsigned INTPPS2
: 1;
4625 unsigned INTPPS3
: 1;
4626 unsigned INTPPS4
: 1;
4634 unsigned INTPPS
: 5;
4639 extern __at(0x0E10) volatile __INTPPSbits_t INTPPSbits
;
4641 #define _INTPPS0 0x01
4642 #define _INTPPS1 0x02
4643 #define _INTPPS2 0x04
4644 #define _INTPPS3 0x08
4645 #define _INTPPS4 0x10
4647 //==============================================================================
4650 //==============================================================================
4653 extern __at(0x0E11) __sfr T0CKIPPS
;
4659 unsigned T0CKIPPS0
: 1;
4660 unsigned T0CKIPPS1
: 1;
4661 unsigned T0CKIPPS2
: 1;
4662 unsigned T0CKIPPS3
: 1;
4663 unsigned T0CKIPPS4
: 1;
4671 unsigned T0CKIPPS
: 5;
4676 extern __at(0x0E11) volatile __T0CKIPPSbits_t T0CKIPPSbits
;
4678 #define _T0CKIPPS0 0x01
4679 #define _T0CKIPPS1 0x02
4680 #define _T0CKIPPS2 0x04
4681 #define _T0CKIPPS3 0x08
4682 #define _T0CKIPPS4 0x10
4684 //==============================================================================
4687 //==============================================================================
4690 extern __at(0x0E12) __sfr T1CKIPPS
;
4696 unsigned T1CKIPPS0
: 1;
4697 unsigned T1CKIPPS1
: 1;
4698 unsigned T1CKIPPS2
: 1;
4699 unsigned T1CKIPPS3
: 1;
4700 unsigned T1CKIPPS4
: 1;
4708 unsigned T1CKIPPS
: 5;
4713 extern __at(0x0E12) volatile __T1CKIPPSbits_t T1CKIPPSbits
;
4715 #define _T1CKIPPS0 0x01
4716 #define _T1CKIPPS1 0x02
4717 #define _T1CKIPPS2 0x04
4718 #define _T1CKIPPS3 0x08
4719 #define _T1CKIPPS4 0x10
4721 //==============================================================================
4724 //==============================================================================
4727 extern __at(0x0E13) __sfr T1GPPS
;
4733 unsigned T1GPPS0
: 1;
4734 unsigned T1GPPS1
: 1;
4735 unsigned T1GPPS2
: 1;
4736 unsigned T1GPPS3
: 1;
4737 unsigned T1GPPS4
: 1;
4745 unsigned T1GPPS
: 5;
4750 extern __at(0x0E13) volatile __T1GPPSbits_t T1GPPSbits
;
4752 #define _T1GPPS0 0x01
4753 #define _T1GPPS1 0x02
4754 #define _T1GPPS2 0x04
4755 #define _T1GPPS3 0x08
4756 #define _T1GPPS4 0x10
4758 //==============================================================================
4761 //==============================================================================
4764 extern __at(0x0E14) __sfr CCP1PPS
;
4770 unsigned CCP1PPS0
: 1;
4771 unsigned CCP1PPS1
: 1;
4772 unsigned CCP1PPS2
: 1;
4773 unsigned CCP1PPS3
: 1;
4774 unsigned CCP1PPS4
: 1;
4782 unsigned CCP1PPS
: 5;
4787 extern __at(0x0E14) volatile __CCP1PPSbits_t CCP1PPSbits
;
4789 #define _CCP1PPS0 0x01
4790 #define _CCP1PPS1 0x02
4791 #define _CCP1PPS2 0x04
4792 #define _CCP1PPS3 0x08
4793 #define _CCP1PPS4 0x10
4795 //==============================================================================
4798 //==============================================================================
4801 extern __at(0x0E15) __sfr CCP2PPS
;
4807 unsigned CCP2PPS0
: 1;
4808 unsigned CCP2PPS1
: 1;
4809 unsigned CCP2PPS2
: 1;
4810 unsigned CCP2PPS3
: 1;
4811 unsigned CCP2PPS4
: 1;
4819 unsigned CCP2PPS
: 5;
4824 extern __at(0x0E15) volatile __CCP2PPSbits_t CCP2PPSbits
;
4826 #define _CCP2PPS0 0x01
4827 #define _CCP2PPS1 0x02
4828 #define _CCP2PPS2 0x04
4829 #define _CCP2PPS3 0x08
4830 #define _CCP2PPS4 0x10
4832 //==============================================================================
4835 //==============================================================================
4838 extern __at(0x0E18) __sfr CWG1PPS
;
4844 unsigned CWG1PPS0
: 1;
4845 unsigned CWG1PPS1
: 1;
4846 unsigned CWG1PPS2
: 1;
4847 unsigned CWG1PPS3
: 1;
4848 unsigned CWG1PPS4
: 1;
4856 unsigned CWG1PPS
: 5;
4861 extern __at(0x0E18) volatile __CWG1PPSbits_t CWG1PPSbits
;
4863 #define _CWG1PPS0 0x01
4864 #define _CWG1PPS1 0x02
4865 #define _CWG1PPS2 0x04
4866 #define _CWG1PPS3 0x08
4867 #define _CWG1PPS4 0x10
4869 //==============================================================================
4872 //==============================================================================
4875 extern __at(0x0E1A) __sfr MDCIN1PPS
;
4881 unsigned MDCIN1PPS0
: 1;
4882 unsigned MDCIN1PPS1
: 1;
4883 unsigned MDCIN1PPS2
: 1;
4884 unsigned MDCIN1PPS3
: 1;
4885 unsigned MDCIN1PPS4
: 1;
4893 unsigned MDCIN1PPS
: 5;
4896 } __MDCIN1PPSbits_t
;
4898 extern __at(0x0E1A) volatile __MDCIN1PPSbits_t MDCIN1PPSbits
;
4900 #define _MDCIN1PPS0 0x01
4901 #define _MDCIN1PPS1 0x02
4902 #define _MDCIN1PPS2 0x04
4903 #define _MDCIN1PPS3 0x08
4904 #define _MDCIN1PPS4 0x10
4906 //==============================================================================
4909 //==============================================================================
4912 extern __at(0x0E1B) __sfr MDCIN2PPS
;
4918 unsigned MDCIN2PPS0
: 1;
4919 unsigned MDCIN2PPS1
: 1;
4920 unsigned MDCIN2PPS2
: 1;
4921 unsigned MDCIN2PPS3
: 1;
4922 unsigned MDCIN2PPS4
: 1;
4930 unsigned MDCIN2PPS
: 5;
4933 } __MDCIN2PPSbits_t
;
4935 extern __at(0x0E1B) volatile __MDCIN2PPSbits_t MDCIN2PPSbits
;
4937 #define _MDCIN2PPS0 0x01
4938 #define _MDCIN2PPS1 0x02
4939 #define _MDCIN2PPS2 0x04
4940 #define _MDCIN2PPS3 0x08
4941 #define _MDCIN2PPS4 0x10
4943 //==============================================================================
4946 //==============================================================================
4949 extern __at(0x0E1C) __sfr MDMINPPS
;
4955 unsigned MDMINPPS0
: 1;
4956 unsigned MDMINPPS1
: 1;
4957 unsigned MDMINPPS2
: 1;
4958 unsigned MDMINPPS3
: 1;
4959 unsigned MDMINPPS4
: 1;
4967 unsigned MDMINPPS
: 5;
4972 extern __at(0x0E1C) volatile __MDMINPPSbits_t MDMINPPSbits
;
4974 #define _MDMINPPS0 0x01
4975 #define _MDMINPPS1 0x02
4976 #define _MDMINPPS2 0x04
4977 #define _MDMINPPS3 0x08
4978 #define _MDMINPPS4 0x10
4980 //==============================================================================
4983 //==============================================================================
4986 extern __at(0x0E20) __sfr SSP1CLKPPS
;
4992 unsigned SSP1CLKPPS0
: 1;
4993 unsigned SSP1CLKPPS1
: 1;
4994 unsigned SSP1CLKPPS2
: 1;
4995 unsigned SSP1CLKPPS3
: 1;
4996 unsigned SSP1CLKPPS4
: 1;
5004 unsigned SSP1CLKPPS
: 5;
5007 } __SSP1CLKPPSbits_t
;
5009 extern __at(0x0E20) volatile __SSP1CLKPPSbits_t SSP1CLKPPSbits
;
5011 #define _SSP1CLKPPS0 0x01
5012 #define _SSP1CLKPPS1 0x02
5013 #define _SSP1CLKPPS2 0x04
5014 #define _SSP1CLKPPS3 0x08
5015 #define _SSP1CLKPPS4 0x10
5017 //==============================================================================
5020 //==============================================================================
5023 extern __at(0x0E21) __sfr SSP1DATPPS
;
5029 unsigned SSP1DATPPS0
: 1;
5030 unsigned SSP1DATPPS1
: 1;
5031 unsigned SSP1DATPPS2
: 1;
5032 unsigned SSP1DATPPS3
: 1;
5033 unsigned SSP1DATPPS4
: 1;
5041 unsigned SSP1DATPPS
: 5;
5044 } __SSP1DATPPSbits_t
;
5046 extern __at(0x0E21) volatile __SSP1DATPPSbits_t SSP1DATPPSbits
;
5048 #define _SSP1DATPPS0 0x01
5049 #define _SSP1DATPPS1 0x02
5050 #define _SSP1DATPPS2 0x04
5051 #define _SSP1DATPPS3 0x08
5052 #define _SSP1DATPPS4 0x10
5054 //==============================================================================
5057 //==============================================================================
5060 extern __at(0x0E22) __sfr SSP1SSPPS
;
5066 unsigned SSP1SSPPS0
: 1;
5067 unsigned SSP1SSPPS1
: 1;
5068 unsigned SSP1SSPPS2
: 1;
5069 unsigned SSP1SSPPS3
: 1;
5070 unsigned SSP1SSPPS4
: 1;
5078 unsigned SSP1SSPPS
: 5;
5081 } __SSP1SSPPSbits_t
;
5083 extern __at(0x0E22) volatile __SSP1SSPPSbits_t SSP1SSPPSbits
;
5085 #define _SSP1SSPPS0 0x01
5086 #define _SSP1SSPPS1 0x02
5087 #define _SSP1SSPPS2 0x04
5088 #define _SSP1SSPPS3 0x08
5089 #define _SSP1SSPPS4 0x10
5091 //==============================================================================
5094 //==============================================================================
5097 extern __at(0x0E24) __sfr RXPPS
;
5103 unsigned RXPPS0
: 1;
5104 unsigned RXPPS1
: 1;
5105 unsigned RXPPS2
: 1;
5106 unsigned RXPPS3
: 1;
5107 unsigned RXPPS4
: 1;
5120 extern __at(0x0E24) volatile __RXPPSbits_t RXPPSbits
;
5122 #define _RXPPS0 0x01
5123 #define _RXPPS1 0x02
5124 #define _RXPPS2 0x04
5125 #define _RXPPS3 0x08
5126 #define _RXPPS4 0x10
5128 //==============================================================================
5131 //==============================================================================
5134 extern __at(0x0E25) __sfr TXPPS
;
5140 unsigned TXPPS0
: 1;
5141 unsigned TXPPS1
: 1;
5142 unsigned TXPPS2
: 1;
5143 unsigned TXPPS3
: 1;
5144 unsigned TXPPS4
: 1;
5157 extern __at(0x0E25) volatile __TXPPSbits_t TXPPSbits
;
5159 #define _TXPPS0 0x01
5160 #define _TXPPS1 0x02
5161 #define _TXPPS2 0x04
5162 #define _TXPPS3 0x08
5163 #define _TXPPS4 0x10
5165 //==============================================================================
5168 //==============================================================================
5171 extern __at(0x0E28) __sfr CLCIN0PPS
;
5177 unsigned CLCIN0PPS0
: 1;
5178 unsigned CLCIN0PPS1
: 1;
5179 unsigned CLCIN0PPS2
: 1;
5180 unsigned CLCIN0PPS3
: 1;
5181 unsigned CLCIN0PPS4
: 1;
5189 unsigned CLCIN0PPS
: 5;
5192 } __CLCIN0PPSbits_t
;
5194 extern __at(0x0E28) volatile __CLCIN0PPSbits_t CLCIN0PPSbits
;
5196 #define _CLCIN0PPS0 0x01
5197 #define _CLCIN0PPS1 0x02
5198 #define _CLCIN0PPS2 0x04
5199 #define _CLCIN0PPS3 0x08
5200 #define _CLCIN0PPS4 0x10
5202 //==============================================================================
5205 //==============================================================================
5208 extern __at(0x0E29) __sfr CLCIN1PPS
;
5214 unsigned CLCIN1PPS0
: 1;
5215 unsigned CLCIN1PPS1
: 1;
5216 unsigned CLCIN1PPS2
: 1;
5217 unsigned CLCIN1PPS3
: 1;
5218 unsigned CLCIN1PPS4
: 1;
5226 unsigned CLCIN1PPS
: 5;
5229 } __CLCIN1PPSbits_t
;
5231 extern __at(0x0E29) volatile __CLCIN1PPSbits_t CLCIN1PPSbits
;
5233 #define _CLCIN1PPS0 0x01
5234 #define _CLCIN1PPS1 0x02
5235 #define _CLCIN1PPS2 0x04
5236 #define _CLCIN1PPS3 0x08
5237 #define _CLCIN1PPS4 0x10
5239 //==============================================================================
5242 //==============================================================================
5245 extern __at(0x0E2A) __sfr CLCIN2PPS
;
5251 unsigned CLCIN2PPS0
: 1;
5252 unsigned CLCIN2PPS1
: 1;
5253 unsigned CLCIN2PPS2
: 1;
5254 unsigned CLCIN2PPS3
: 1;
5255 unsigned CLCIN2PPS4
: 1;
5263 unsigned CLCIN2PPS
: 5;
5266 } __CLCIN2PPSbits_t
;
5268 extern __at(0x0E2A) volatile __CLCIN2PPSbits_t CLCIN2PPSbits
;
5270 #define _CLCIN2PPS0 0x01
5271 #define _CLCIN2PPS1 0x02
5272 #define _CLCIN2PPS2 0x04
5273 #define _CLCIN2PPS3 0x08
5274 #define _CLCIN2PPS4 0x10
5276 //==============================================================================
5279 //==============================================================================
5282 extern __at(0x0E2B) __sfr CLCIN3PPS
;
5288 unsigned CLCIN3PPS0
: 1;
5289 unsigned CLCIN3PPS1
: 1;
5290 unsigned CLCIN3PPS2
: 1;
5291 unsigned CLCIN3PPS3
: 1;
5292 unsigned CLCIN3PPS4
: 1;
5300 unsigned CLCIN3PPS
: 5;
5303 } __CLCIN3PPSbits_t
;
5305 extern __at(0x0E2B) volatile __CLCIN3PPSbits_t CLCIN3PPSbits
;
5307 #define _CLCIN3PPS0 0x01
5308 #define _CLCIN3PPS1 0x02
5309 #define _CLCIN3PPS2 0x04
5310 #define _CLCIN3PPS3 0x08
5311 #define _CLCIN3PPS4 0x10
5313 //==============================================================================
5316 //==============================================================================
5319 extern __at(0x0E90) __sfr RA0PPS
;
5325 unsigned RA0PPS0
: 1;
5326 unsigned RA0PPS1
: 1;
5327 unsigned RA0PPS2
: 1;
5328 unsigned RA0PPS3
: 1;
5329 unsigned RA0PPS4
: 1;
5337 unsigned RA0PPS
: 5;
5342 extern __at(0x0E90) volatile __RA0PPSbits_t RA0PPSbits
;
5344 #define _RA0PPS0 0x01
5345 #define _RA0PPS1 0x02
5346 #define _RA0PPS2 0x04
5347 #define _RA0PPS3 0x08
5348 #define _RA0PPS4 0x10
5350 //==============================================================================
5353 //==============================================================================
5356 extern __at(0x0E91) __sfr RA1PPS
;
5362 unsigned RA1PPS0
: 1;
5363 unsigned RA1PPS1
: 1;
5364 unsigned RA1PPS2
: 1;
5365 unsigned RA1PPS3
: 1;
5366 unsigned RA1PPS4
: 1;
5374 unsigned RA1PPS
: 5;
5379 extern __at(0x0E91) volatile __RA1PPSbits_t RA1PPSbits
;
5381 #define _RA1PPS0 0x01
5382 #define _RA1PPS1 0x02
5383 #define _RA1PPS2 0x04
5384 #define _RA1PPS3 0x08
5385 #define _RA1PPS4 0x10
5387 //==============================================================================
5390 //==============================================================================
5393 extern __at(0x0E92) __sfr RA2PPS
;
5399 unsigned RA2PPS0
: 1;
5400 unsigned RA2PPS1
: 1;
5401 unsigned RA2PPS2
: 1;
5402 unsigned RA2PPS3
: 1;
5403 unsigned RA2PPS4
: 1;
5411 unsigned RA2PPS
: 5;
5416 extern __at(0x0E92) volatile __RA2PPSbits_t RA2PPSbits
;
5418 #define _RA2PPS0 0x01
5419 #define _RA2PPS1 0x02
5420 #define _RA2PPS2 0x04
5421 #define _RA2PPS3 0x08
5422 #define _RA2PPS4 0x10
5424 //==============================================================================
5427 //==============================================================================
5430 extern __at(0x0E94) __sfr RA4PPS
;
5436 unsigned RA4PPS0
: 1;
5437 unsigned RA4PPS1
: 1;
5438 unsigned RA4PPS2
: 1;
5439 unsigned RA4PPS3
: 1;
5440 unsigned RA4PPS4
: 1;
5448 unsigned RA4PPS
: 5;
5453 extern __at(0x0E94) volatile __RA4PPSbits_t RA4PPSbits
;
5455 #define _RA4PPS0 0x01
5456 #define _RA4PPS1 0x02
5457 #define _RA4PPS2 0x04
5458 #define _RA4PPS3 0x08
5459 #define _RA4PPS4 0x10
5461 //==============================================================================
5464 //==============================================================================
5467 extern __at(0x0E95) __sfr RA5PPS
;
5473 unsigned RA5PPS0
: 1;
5474 unsigned RA5PPS1
: 1;
5475 unsigned RA5PPS2
: 1;
5476 unsigned RA5PPS3
: 1;
5477 unsigned RA5PPS4
: 1;
5485 unsigned RA5PPS
: 5;
5490 extern __at(0x0E95) volatile __RA5PPSbits_t RA5PPSbits
;
5492 #define _RA5PPS0 0x01
5493 #define _RA5PPS1 0x02
5494 #define _RA5PPS2 0x04
5495 #define _RA5PPS3 0x08
5496 #define _RA5PPS4 0x10
5498 //==============================================================================
5501 //==============================================================================
5504 extern __at(0x0F0F) __sfr CLCDATA
;
5508 unsigned MLC1OUT
: 1;
5509 unsigned MLC2OUT
: 1;
5518 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
5520 #define _MLC1OUT 0x01
5521 #define _MLC2OUT 0x02
5523 //==============================================================================
5526 //==============================================================================
5529 extern __at(0x0F10) __sfr CLC1CON
;
5535 unsigned LC1MODE0
: 1;
5536 unsigned LC1MODE1
: 1;
5537 unsigned LC1MODE2
: 1;
5538 unsigned LC1INTN
: 1;
5539 unsigned LC1INTP
: 1;
5540 unsigned LC1OUT
: 1;
5565 unsigned LC1MODE
: 3;
5570 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
5572 #define _LC1MODE0 0x01
5574 #define _LC1MODE1 0x02
5576 #define _LC1MODE2 0x04
5578 #define _LC1INTN 0x08
5580 #define _LC1INTP 0x10
5582 #define _LC1OUT 0x20
5587 //==============================================================================
5590 //==============================================================================
5593 extern __at(0x0F11) __sfr CLC1POL
;
5599 unsigned LC1G1POL
: 1;
5600 unsigned LC1G2POL
: 1;
5601 unsigned LC1G3POL
: 1;
5602 unsigned LC1G4POL
: 1;
5606 unsigned LC1POL
: 1;
5622 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
5624 #define _LC1G1POL 0x01
5626 #define _LC1G2POL 0x02
5628 #define _LC1G3POL 0x04
5630 #define _LC1G4POL 0x08
5632 #define _LC1POL 0x80
5635 //==============================================================================
5638 //==============================================================================
5641 extern __at(0x0F12) __sfr CLC1SEL0
;
5647 unsigned LC1D1S0
: 1;
5648 unsigned LC1D1S1
: 1;
5649 unsigned LC1D1S2
: 1;
5650 unsigned LC1D1S3
: 1;
5651 unsigned LC1D1S4
: 1;
5677 unsigned LC1D1S
: 5;
5682 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
5684 #define _LC1D1S0 0x01
5686 #define _LC1D1S1 0x02
5688 #define _LC1D1S2 0x04
5690 #define _LC1D1S3 0x08
5692 #define _LC1D1S4 0x10
5695 //==============================================================================
5698 //==============================================================================
5701 extern __at(0x0F13) __sfr CLC1SEL1
;
5707 unsigned LC1D2S0
: 1;
5708 unsigned LC1D2S1
: 1;
5709 unsigned LC1D2S2
: 1;
5710 unsigned LC1D2S3
: 1;
5711 unsigned LC1D2S4
: 1;
5731 unsigned LC1D2S
: 5;
5742 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
5744 #define _LC1D2S0 0x01
5746 #define _LC1D2S1 0x02
5748 #define _LC1D2S2 0x04
5750 #define _LC1D2S3 0x08
5752 #define _LC1D2S4 0x10
5755 //==============================================================================
5758 //==============================================================================
5761 extern __at(0x0F14) __sfr CLC1SEL2
;
5767 unsigned LC1D3S0
: 1;
5768 unsigned LC1D3S1
: 1;
5769 unsigned LC1D3S2
: 1;
5770 unsigned LC1D3S3
: 1;
5771 unsigned LC1D3S4
: 1;
5791 unsigned LC1D3S
: 5;
5802 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
5804 #define _LC1D3S0 0x01
5806 #define _LC1D3S1 0x02
5808 #define _LC1D3S2 0x04
5810 #define _LC1D3S3 0x08
5812 #define _LC1D3S4 0x10
5815 //==============================================================================
5818 //==============================================================================
5821 extern __at(0x0F15) __sfr CLC1SEL3
;
5827 unsigned LC1D4S0
: 1;
5828 unsigned LC1D4S1
: 1;
5829 unsigned LC1D4S2
: 1;
5830 unsigned LC1D4S3
: 1;
5831 unsigned LC1D4S4
: 1;
5857 unsigned LC1D4S
: 5;
5862 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
5864 #define _LC1D4S0 0x01
5866 #define _LC1D4S1 0x02
5868 #define _LC1D4S2 0x04
5870 #define _LC1D4S3 0x08
5872 #define _LC1D4S4 0x10
5875 //==============================================================================
5878 //==============================================================================
5881 extern __at(0x0F16) __sfr CLC1GLS0
;
5887 unsigned LC1G1D1N
: 1;
5888 unsigned LC1G1D1T
: 1;
5889 unsigned LC1G1D2N
: 1;
5890 unsigned LC1G1D2T
: 1;
5891 unsigned LC1G1D3N
: 1;
5892 unsigned LC1G1D3T
: 1;
5893 unsigned LC1G1D4N
: 1;
5894 unsigned LC1G1D4T
: 1;
5910 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
5912 #define _LC1G1D1N 0x01
5914 #define _LC1G1D1T 0x02
5916 #define _LC1G1D2N 0x04
5918 #define _LC1G1D2T 0x08
5920 #define _LC1G1D3N 0x10
5922 #define _LC1G1D3T 0x20
5924 #define _LC1G1D4N 0x40
5926 #define _LC1G1D4T 0x80
5929 //==============================================================================
5932 //==============================================================================
5935 extern __at(0x0F17) __sfr CLC1GLS1
;
5941 unsigned LC1G2D1N
: 1;
5942 unsigned LC1G2D1T
: 1;
5943 unsigned LC1G2D2N
: 1;
5944 unsigned LC1G2D2T
: 1;
5945 unsigned LC1G2D3N
: 1;
5946 unsigned LC1G2D3T
: 1;
5947 unsigned LC1G2D4N
: 1;
5948 unsigned LC1G2D4T
: 1;
5964 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
5966 #define _CLC1GLS1_LC1G2D1N 0x01
5967 #define _CLC1GLS1_D1N 0x01
5968 #define _CLC1GLS1_LC1G2D1T 0x02
5969 #define _CLC1GLS1_D1T 0x02
5970 #define _CLC1GLS1_LC1G2D2N 0x04
5971 #define _CLC1GLS1_D2N 0x04
5972 #define _CLC1GLS1_LC1G2D2T 0x08
5973 #define _CLC1GLS1_D2T 0x08
5974 #define _CLC1GLS1_LC1G2D3N 0x10
5975 #define _CLC1GLS1_D3N 0x10
5976 #define _CLC1GLS1_LC1G2D3T 0x20
5977 #define _CLC1GLS1_D3T 0x20
5978 #define _CLC1GLS1_LC1G2D4N 0x40
5979 #define _CLC1GLS1_D4N 0x40
5980 #define _CLC1GLS1_LC1G2D4T 0x80
5981 #define _CLC1GLS1_D4T 0x80
5983 //==============================================================================
5986 //==============================================================================
5989 extern __at(0x0F18) __sfr CLC1GLS2
;
5995 unsigned LC1G3D1N
: 1;
5996 unsigned LC1G3D1T
: 1;
5997 unsigned LC1G3D2N
: 1;
5998 unsigned LC1G3D2T
: 1;
5999 unsigned LC1G3D3N
: 1;
6000 unsigned LC1G3D3T
: 1;
6001 unsigned LC1G3D4N
: 1;
6002 unsigned LC1G3D4T
: 1;
6018 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
6020 #define _CLC1GLS2_LC1G3D1N 0x01
6021 #define _CLC1GLS2_D1N 0x01
6022 #define _CLC1GLS2_LC1G3D1T 0x02
6023 #define _CLC1GLS2_D1T 0x02
6024 #define _CLC1GLS2_LC1G3D2N 0x04
6025 #define _CLC1GLS2_D2N 0x04
6026 #define _CLC1GLS2_LC1G3D2T 0x08
6027 #define _CLC1GLS2_D2T 0x08
6028 #define _CLC1GLS2_LC1G3D3N 0x10
6029 #define _CLC1GLS2_D3N 0x10
6030 #define _CLC1GLS2_LC1G3D3T 0x20
6031 #define _CLC1GLS2_D3T 0x20
6032 #define _CLC1GLS2_LC1G3D4N 0x40
6033 #define _CLC1GLS2_D4N 0x40
6034 #define _CLC1GLS2_LC1G3D4T 0x80
6035 #define _CLC1GLS2_D4T 0x80
6037 //==============================================================================
6040 //==============================================================================
6043 extern __at(0x0F19) __sfr CLC1GLS3
;
6049 unsigned LC1G4D1N
: 1;
6050 unsigned LC1G4D1T
: 1;
6051 unsigned LC1G4D2N
: 1;
6052 unsigned LC1G4D2T
: 1;
6053 unsigned LC1G4D3N
: 1;
6054 unsigned LC1G4D3T
: 1;
6055 unsigned LC1G4D4N
: 1;
6056 unsigned LC1G4D4T
: 1;
6072 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
6074 #define _LC1G4D1N 0x01
6076 #define _LC1G4D1T 0x02
6078 #define _LC1G4D2N 0x04
6080 #define _LC1G4D2T 0x08
6082 #define _LC1G4D3N 0x10
6084 #define _LC1G4D3T 0x20
6086 #define _LC1G4D4N 0x40
6088 #define _LC1G4D4T 0x80
6091 //==============================================================================
6094 //==============================================================================
6097 extern __at(0x0F1A) __sfr CLC2CON
;
6103 unsigned LC2MODE0
: 1;
6104 unsigned LC2MODE1
: 1;
6105 unsigned LC2MODE2
: 1;
6106 unsigned LC2INTN
: 1;
6107 unsigned LC2INTP
: 1;
6108 unsigned LC2OUT
: 1;
6127 unsigned LC2MODE
: 3;
6138 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
6140 #define _CLC2CON_LC2MODE0 0x01
6141 #define _CLC2CON_MODE0 0x01
6142 #define _CLC2CON_LC2MODE1 0x02
6143 #define _CLC2CON_MODE1 0x02
6144 #define _CLC2CON_LC2MODE2 0x04
6145 #define _CLC2CON_MODE2 0x04
6146 #define _CLC2CON_LC2INTN 0x08
6147 #define _CLC2CON_INTN 0x08
6148 #define _CLC2CON_LC2INTP 0x10
6149 #define _CLC2CON_INTP 0x10
6150 #define _CLC2CON_LC2OUT 0x20
6151 #define _CLC2CON_OUT 0x20
6152 #define _CLC2CON_LC2EN 0x80
6153 #define _CLC2CON_EN 0x80
6155 //==============================================================================
6158 //==============================================================================
6161 extern __at(0x0F1B) __sfr CLC2POL
;
6167 unsigned LC2G1POL
: 1;
6168 unsigned LC2G2POL
: 1;
6169 unsigned LC2G3POL
: 1;
6170 unsigned LC2G4POL
: 1;
6174 unsigned LC2POL
: 1;
6190 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
6192 #define _CLC2POL_LC2G1POL 0x01
6193 #define _CLC2POL_G1POL 0x01
6194 #define _CLC2POL_LC2G2POL 0x02
6195 #define _CLC2POL_G2POL 0x02
6196 #define _CLC2POL_LC2G3POL 0x04
6197 #define _CLC2POL_G3POL 0x04
6198 #define _CLC2POL_LC2G4POL 0x08
6199 #define _CLC2POL_G4POL 0x08
6200 #define _CLC2POL_LC2POL 0x80
6201 #define _CLC2POL_POL 0x80
6203 //==============================================================================
6206 //==============================================================================
6209 extern __at(0x0F1C) __sfr CLC2SEL0
;
6215 unsigned LC2D1S0
: 1;
6216 unsigned LC2D1S1
: 1;
6217 unsigned LC2D1S2
: 1;
6218 unsigned LC2D1S3
: 1;
6219 unsigned LC2D1S4
: 1;
6245 unsigned LC2D1S
: 5;
6250 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
6252 #define _CLC2SEL0_LC2D1S0 0x01
6253 #define _CLC2SEL0_D1S0 0x01
6254 #define _CLC2SEL0_LC2D1S1 0x02
6255 #define _CLC2SEL0_D1S1 0x02
6256 #define _CLC2SEL0_LC2D1S2 0x04
6257 #define _CLC2SEL0_D1S2 0x04
6258 #define _CLC2SEL0_LC2D1S3 0x08
6259 #define _CLC2SEL0_D1S3 0x08
6260 #define _CLC2SEL0_LC2D1S4 0x10
6261 #define _CLC2SEL0_D1S4 0x10
6263 //==============================================================================
6266 //==============================================================================
6269 extern __at(0x0F1D) __sfr CLC2SEL1
;
6275 unsigned LC2D2S0
: 1;
6276 unsigned LC2D2S1
: 1;
6277 unsigned LC2D2S2
: 1;
6278 unsigned LC2D2S3
: 1;
6279 unsigned LC2D2S4
: 1;
6305 unsigned LC2D2S
: 5;
6310 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
6312 #define _CLC2SEL1_LC2D2S0 0x01
6313 #define _CLC2SEL1_D2S0 0x01
6314 #define _CLC2SEL1_LC2D2S1 0x02
6315 #define _CLC2SEL1_D2S1 0x02
6316 #define _CLC2SEL1_LC2D2S2 0x04
6317 #define _CLC2SEL1_D2S2 0x04
6318 #define _CLC2SEL1_LC2D2S3 0x08
6319 #define _CLC2SEL1_D2S3 0x08
6320 #define _CLC2SEL1_LC2D2S4 0x10
6321 #define _CLC2SEL1_D2S4 0x10
6323 //==============================================================================
6326 //==============================================================================
6329 extern __at(0x0F1E) __sfr CLC2SEL2
;
6335 unsigned LC2D3S0
: 1;
6336 unsigned LC2D3S1
: 1;
6337 unsigned LC2D3S2
: 1;
6338 unsigned LC2D3S3
: 1;
6339 unsigned LC2D3S4
: 1;
6359 unsigned LC2D3S
: 5;
6370 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
6372 #define _CLC2SEL2_LC2D3S0 0x01
6373 #define _CLC2SEL2_D3S0 0x01
6374 #define _CLC2SEL2_LC2D3S1 0x02
6375 #define _CLC2SEL2_D3S1 0x02
6376 #define _CLC2SEL2_LC2D3S2 0x04
6377 #define _CLC2SEL2_D3S2 0x04
6378 #define _CLC2SEL2_LC2D3S3 0x08
6379 #define _CLC2SEL2_D3S3 0x08
6380 #define _CLC2SEL2_LC2D3S4 0x10
6381 #define _CLC2SEL2_D3S4 0x10
6383 //==============================================================================
6386 //==============================================================================
6389 extern __at(0x0F1F) __sfr CLC2SEL3
;
6395 unsigned LC2D4S0
: 1;
6396 unsigned LC2D4S1
: 1;
6397 unsigned LC2D4S2
: 1;
6398 unsigned LC2D4S3
: 1;
6399 unsigned LC2D4S4
: 1;
6419 unsigned LC2D4S
: 5;
6430 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
6432 #define _CLC2SEL3_LC2D4S0 0x01
6433 #define _CLC2SEL3_D4S0 0x01
6434 #define _CLC2SEL3_LC2D4S1 0x02
6435 #define _CLC2SEL3_D4S1 0x02
6436 #define _CLC2SEL3_LC2D4S2 0x04
6437 #define _CLC2SEL3_D4S2 0x04
6438 #define _CLC2SEL3_LC2D4S3 0x08
6439 #define _CLC2SEL3_D4S3 0x08
6440 #define _CLC2SEL3_LC2D4S4 0x10
6441 #define _CLC2SEL3_D4S4 0x10
6443 //==============================================================================
6446 //==============================================================================
6449 extern __at(0x0F20) __sfr CLC2GLS0
;
6455 unsigned LC2G1D1N
: 1;
6456 unsigned LC2G1D1T
: 1;
6457 unsigned LC2G1D2N
: 1;
6458 unsigned LC2G1D2T
: 1;
6459 unsigned LC2G1D3N
: 1;
6460 unsigned LC2G1D3T
: 1;
6461 unsigned LC2G1D4N
: 1;
6462 unsigned LC2G1D4T
: 1;
6478 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
6480 #define _CLC2GLS0_LC2G1D1N 0x01
6481 #define _CLC2GLS0_D1N 0x01
6482 #define _CLC2GLS0_LC2G1D1T 0x02
6483 #define _CLC2GLS0_D1T 0x02
6484 #define _CLC2GLS0_LC2G1D2N 0x04
6485 #define _CLC2GLS0_D2N 0x04
6486 #define _CLC2GLS0_LC2G1D2T 0x08
6487 #define _CLC2GLS0_D2T 0x08
6488 #define _CLC2GLS0_LC2G1D3N 0x10
6489 #define _CLC2GLS0_D3N 0x10
6490 #define _CLC2GLS0_LC2G1D3T 0x20
6491 #define _CLC2GLS0_D3T 0x20
6492 #define _CLC2GLS0_LC2G1D4N 0x40
6493 #define _CLC2GLS0_D4N 0x40
6494 #define _CLC2GLS0_LC2G1D4T 0x80
6495 #define _CLC2GLS0_D4T 0x80
6497 //==============================================================================
6500 //==============================================================================
6503 extern __at(0x0F21) __sfr CLC2GLS1
;
6509 unsigned LC2G2D1N
: 1;
6510 unsigned LC2G2D1T
: 1;
6511 unsigned LC2G2D2N
: 1;
6512 unsigned LC2G2D2T
: 1;
6513 unsigned LC2G2D3N
: 1;
6514 unsigned LC2G2D3T
: 1;
6515 unsigned LC2G2D4N
: 1;
6516 unsigned LC2G2D4T
: 1;
6532 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
6534 #define _CLC2GLS1_LC2G2D1N 0x01
6535 #define _CLC2GLS1_D1N 0x01
6536 #define _CLC2GLS1_LC2G2D1T 0x02
6537 #define _CLC2GLS1_D1T 0x02
6538 #define _CLC2GLS1_LC2G2D2N 0x04
6539 #define _CLC2GLS1_D2N 0x04
6540 #define _CLC2GLS1_LC2G2D2T 0x08
6541 #define _CLC2GLS1_D2T 0x08
6542 #define _CLC2GLS1_LC2G2D3N 0x10
6543 #define _CLC2GLS1_D3N 0x10
6544 #define _CLC2GLS1_LC2G2D3T 0x20
6545 #define _CLC2GLS1_D3T 0x20
6546 #define _CLC2GLS1_LC2G2D4N 0x40
6547 #define _CLC2GLS1_D4N 0x40
6548 #define _CLC2GLS1_LC2G2D4T 0x80
6549 #define _CLC2GLS1_D4T 0x80
6551 //==============================================================================
6554 //==============================================================================
6557 extern __at(0x0F22) __sfr CLC2GLS2
;
6563 unsigned LC2G3D1N
: 1;
6564 unsigned LC2G3D1T
: 1;
6565 unsigned LC2G3D2N
: 1;
6566 unsigned LC2G3D2T
: 1;
6567 unsigned LC2G3D3N
: 1;
6568 unsigned LC2G3D3T
: 1;
6569 unsigned LC2G3D4N
: 1;
6570 unsigned LC2G3D4T
: 1;
6586 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
6588 #define _CLC2GLS2_LC2G3D1N 0x01
6589 #define _CLC2GLS2_D1N 0x01
6590 #define _CLC2GLS2_LC2G3D1T 0x02
6591 #define _CLC2GLS2_D1T 0x02
6592 #define _CLC2GLS2_LC2G3D2N 0x04
6593 #define _CLC2GLS2_D2N 0x04
6594 #define _CLC2GLS2_LC2G3D2T 0x08
6595 #define _CLC2GLS2_D2T 0x08
6596 #define _CLC2GLS2_LC2G3D3N 0x10
6597 #define _CLC2GLS2_D3N 0x10
6598 #define _CLC2GLS2_LC2G3D3T 0x20
6599 #define _CLC2GLS2_D3T 0x20
6600 #define _CLC2GLS2_LC2G3D4N 0x40
6601 #define _CLC2GLS2_D4N 0x40
6602 #define _CLC2GLS2_LC2G3D4T 0x80
6603 #define _CLC2GLS2_D4T 0x80
6605 //==============================================================================
6608 //==============================================================================
6611 extern __at(0x0F23) __sfr CLC2GLS3
;
6617 unsigned LC2G4D1N
: 1;
6618 unsigned LC2G4D1T
: 1;
6619 unsigned LC2G4D2N
: 1;
6620 unsigned LC2G4D2T
: 1;
6621 unsigned LC2G4D3N
: 1;
6622 unsigned LC2G4D3T
: 1;
6623 unsigned LC2G4D4N
: 1;
6624 unsigned LC2G4D4T
: 1;
6640 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
6642 #define _CLC2GLS3_LC2G4D1N 0x01
6643 #define _CLC2GLS3_G4D1N 0x01
6644 #define _CLC2GLS3_LC2G4D1T 0x02
6645 #define _CLC2GLS3_G4D1T 0x02
6646 #define _CLC2GLS3_LC2G4D2N 0x04
6647 #define _CLC2GLS3_G4D2N 0x04
6648 #define _CLC2GLS3_LC2G4D2T 0x08
6649 #define _CLC2GLS3_G4D2T 0x08
6650 #define _CLC2GLS3_LC2G4D3N 0x10
6651 #define _CLC2GLS3_G4D3N 0x10
6652 #define _CLC2GLS3_LC2G4D3T 0x20
6653 #define _CLC2GLS3_G4D3T 0x20
6654 #define _CLC2GLS3_LC2G4D4N 0x40
6655 #define _CLC2GLS3_G4D4N 0x40
6656 #define _CLC2GLS3_LC2G4D4T 0x80
6657 #define _CLC2GLS3_G4D4T 0x80
6659 //==============================================================================
6662 //==============================================================================
6665 extern __at(0x0FE4) __sfr STATUS_SHAD
;
6669 unsigned C_SHAD
: 1;
6670 unsigned DC_SHAD
: 1;
6671 unsigned Z_SHAD
: 1;
6677 } __STATUS_SHADbits_t
;
6679 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
6681 #define _C_SHAD 0x01
6682 #define _DC_SHAD 0x02
6683 #define _Z_SHAD 0x04
6685 //==============================================================================
6687 extern __at(0x0FE5) __sfr WREG_SHAD
;
6688 extern __at(0x0FE6) __sfr BSR_SHAD
;
6689 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
6690 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
6691 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
6692 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
6693 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
6694 extern __at(0x0FED) __sfr STKPTR
;
6695 extern __at(0x0FEE) __sfr TOSL
;
6696 extern __at(0x0FEF) __sfr TOSH
;
6698 //==============================================================================
6700 // Configuration Bits
6702 //==============================================================================
6704 #define _CONFIG1 0x8007
6705 #define _CONFIG2 0x8008
6706 #define _CONFIG3 0x8009
6707 #define _CONFIG4 0x800A
6709 //----------------------------- CONFIG1 Options -------------------------------
6711 #define _FEXTOSC_LP 0x3FF8 // LP (crystal oscillator) optimized for 32.768 kHz.
6712 #define _FEXTOSC_XT 0x3FF9 // XT (crystal oscillator) from 100 kHz to 4 MHz.
6713 #define _FEXTOSC_HS 0x3FFA // HS (crystal oscillator) above 4 MHz.
6714 #define _FEXTOSC_OFF 0x3FFC // Oscillator not enabled.
6715 #define _FEXTOSC_ECL 0x3FFD // EC (external clock) below 100 kHz.
6716 #define _FEXTOSC_ECM 0x3FFE // EC (external clock) for 100 kHz to 8 MHz.
6717 #define _FEXTOSC_ECH 0x3FFF // EC (external clock) above 8 MHz.
6718 #define _RSTOSC_HFINT32 0x3F8F // HFINTOSC with 2x PLL (32MHz).
6719 #define _RSTOSC_EXT4X 0x3F9F // EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits.
6720 #define _RSTOSC_SOSC 0x3FBF // SOSC (31kHz).
6721 #define _RSTOSC_LFINT 0x3FCF // LFINTOSC (31kHz).
6722 #define _RSTOSC_HFINT1 0x3FEF // HFINTOSC (1MHz).
6723 #define _RSTOSC_EXT1X 0x3FFF // EXTOSC operating per FEXTOSC bits.
6724 #define _CLKOUTEN_ON 0x3EFF // CLKOUT function is enabled; FOSC/4 clock appears at OSC2.
6725 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled; I/O or oscillator function on OSC2.
6726 #define _CSWEN_OFF 0x37FF // The NOSC and NDIV bits cannot be changed by user software.
6727 #define _CSWEN_ON 0x3FFF // Writing to NOSC and NDIV is allowed.
6728 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
6729 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
6731 //----------------------------- CONFIG2 Options -------------------------------
6733 #define _MCLRE_OFF 0x3FFE // MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of port pin's WPU control bit.
6734 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR; Weak pull-up enabled.
6735 #define _PWRTE_ON 0x3FFD // PWRT enabled.
6736 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
6737 #define _WDTE_OFF 0x3FF3 // WDT disabled; SWDTEN is ignored.
6738 #define _WDTE_SWDTEN 0x3FF7 // WDT controlled by the SWDTEN bit in the WDTCON register.
6739 #define _WDTE_SLEEP 0x3FFB // WDT enabled while running and disabled while in SLEEP/IDLE; SWDTEN is ignored.
6740 #define _WDTE_ON 0x3FFF // WDT enabled, SWDTEN is ignored.
6741 #define _LPBOREN_ON 0x3FDF // ULPBOR enabled.
6742 #define _LPBOREN_OFF 0x3FFF // ULPBOR disabled.
6743 #define _BOREN_OFF 0x3F3F // Brown-out Reset disabled.
6744 #define _BOREN_SBOREN 0x3F7F // Brown-out Reset enabled according to SBOREN.
6745 #define _BOREN_SLEEP 0x3FBF // Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored.
6746 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled, SBOREN bit ignored.
6747 #define _BORV_HIGH 0x3DFF // Brown-out voltage (Vbor) set to 2.7V.
6748 #define _BORV_LOW 0x3FFF // Brown-out voltage (Vbor) set to 2.45V.
6749 #define _PPS1WAY_OFF 0x37FF // The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence).
6750 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle.
6751 #define _STVREN_OFF 0x2FFF // Stack Overflow or Underflow will not cause a Reset.
6752 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
6753 #define _DEBUG_ON 0x1FFF // Background debugger enabled.
6754 #define _DEBUG_OFF 0x3FFF // Background debugger disabled.
6756 //----------------------------- CONFIG3 Options -------------------------------
6758 #define _WRT_ALL 0x3FFC // 0000h to 07FFh write protected, no addresses may be modified.
6759 #define _WRT_HALF 0x3FFD // 0000h to 03FFh write-protected, 0400h to 07FFh may be modified.
6760 #define _WRT_BOOT 0x3FFE // 0000h to 01FFh write-protected, 0200h to 07FFh may be modified.
6761 #define _WRT_OFF 0x3FFF // Write protection off.
6762 #define _LVP_OFF 0x1FFF // HV on MCLR/VPP must be used for programming.
6763 #define _LVP_ON 0x3FFF // Low voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.
6765 //----------------------------- CONFIG4 Options -------------------------------
6767 #define _CP_ON 0x3FFE // User NVM code protection enabled.
6768 #define _CP_OFF 0x3FFF // User NVM code protection disabled.
6769 #define _CPD_ON 0x3FFD // Data NVM code protection enabled.
6770 #define _CPD_OFF 0x3FFF // Data NVM code protection disabled.
6772 //==============================================================================
6774 #define _DEVID1 0x8006
6776 #define _IDLOC0 0x8000
6777 #define _IDLOC1 0x8001
6778 #define _IDLOC2 0x8002
6779 #define _IDLOC3 0x8003
6781 //==============================================================================
6783 #ifndef NO_BIT_DEFINES
6785 #define ADACT0 ADACTbits.ADACT0 // bit 0
6786 #define ADACT1 ADACTbits.ADACT1 // bit 1
6787 #define ADACT2 ADACTbits.ADACT2 // bit 2
6788 #define ADACT3 ADACTbits.ADACT3 // bit 3
6790 #define ADON ADCON0bits.ADON // bit 0
6791 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
6792 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
6793 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
6794 #define CHS0 ADCON0bits.CHS0 // bit 2
6795 #define CHS1 ADCON0bits.CHS1 // bit 3
6796 #define CHS2 ADCON0bits.CHS2 // bit 4
6797 #define CHS3 ADCON0bits.CHS3 // bit 5
6798 #define CHS4 ADCON0bits.CHS4 // bit 6
6799 #define CHS5 ADCON0bits.CHS5 // bit 7
6801 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
6802 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
6803 #define ADNREF ADCON1bits.ADNREF // bit 2
6804 #define ADCS0 ADCON1bits.ADCS0 // bit 4
6805 #define ADCS1 ADCON1bits.ADCS1 // bit 5
6806 #define ADCS2 ADCON1bits.ADCS2 // bit 6
6807 #define ADFM ADCON1bits.ADFM // bit 7
6809 #define ANSA0 ANSELAbits.ANSA0 // bit 0
6810 #define ANSA1 ANSELAbits.ANSA1 // bit 1
6811 #define ANSA2 ANSELAbits.ANSA2 // bit 2
6812 #define ANSA4 ANSELAbits.ANSA4 // bit 4
6813 #define ANSA5 ANSELAbits.ANSA5 // bit 5
6815 #define ABDEN BAUD1CONbits.ABDEN // bit 0
6816 #define WUE BAUD1CONbits.WUE // bit 1
6817 #define BRG16 BAUD1CONbits.BRG16 // bit 3
6818 #define SCKP BAUD1CONbits.SCKP // bit 4
6819 #define RCIDL BAUD1CONbits.RCIDL // bit 6
6820 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
6822 #define BORRDY BORCONbits.BORRDY // bit 0
6823 #define SBOREN BORCONbits.SBOREN // bit 7
6825 #define BSR0 BSRbits.BSR0 // bit 0
6826 #define BSR1 BSRbits.BSR1 // bit 1
6827 #define BSR2 BSRbits.BSR2 // bit 2
6828 #define BSR3 BSRbits.BSR3 // bit 3
6829 #define BSR4 BSRbits.BSR4 // bit 4
6831 #define CCDS0 CCDCONbits.CCDS0 // bit 0
6832 #define CCDS1 CCDCONbits.CCDS1 // bit 1
6833 #define CCDEN CCDCONbits.CCDEN // bit 7
6835 #define CCDNA0 CCDNAbits.CCDNA0 // bit 0
6836 #define CCDNA1 CCDNAbits.CCDNA1 // bit 1
6837 #define CCDNA2 CCDNAbits.CCDNA2 // bit 2
6838 #define CCDNA4 CCDNAbits.CCDNA4 // bit 4
6839 #define CCDNA5 CCDNAbits.CCDNA5 // bit 5
6841 #define CCDPA0 CCDPAbits.CCDPA0 // bit 0
6842 #define CCDPA1 CCDPAbits.CCDPA1 // bit 1
6843 #define CCDPA2 CCDPAbits.CCDPA2 // bit 2
6844 #define CCDPA4 CCDPAbits.CCDPA4 // bit 4
6845 #define CCDPA5 CCDPAbits.CCDPA5 // bit 5
6847 #define CCP1CTS0 CCP1CAPbits.CCP1CTS0 // bit 0
6848 #define CCP1CTS1 CCP1CAPbits.CCP1CTS1 // bit 1
6849 #define CCP1CTS2 CCP1CAPbits.CCP1CTS2 // bit 2
6851 #define CCP1MODE0 CCP1CONbits.CCP1MODE0 // bit 0
6852 #define CCP1MODE1 CCP1CONbits.CCP1MODE1 // bit 1
6853 #define CCP1MODE2 CCP1CONbits.CCP1MODE2 // bit 2
6854 #define CCP1MODE3 CCP1CONbits.CCP1MODE3 // bit 3
6855 #define CCP1FMT CCP1CONbits.CCP1FMT // bit 4
6856 #define CCP1OUT CCP1CONbits.CCP1OUT // bit 5
6857 #define CCP1EN CCP1CONbits.CCP1EN // bit 7
6859 #define CCP1PPS0 CCP1PPSbits.CCP1PPS0 // bit 0
6860 #define CCP1PPS1 CCP1PPSbits.CCP1PPS1 // bit 1
6861 #define CCP1PPS2 CCP1PPSbits.CCP1PPS2 // bit 2
6862 #define CCP1PPS3 CCP1PPSbits.CCP1PPS3 // bit 3
6863 #define CCP1PPS4 CCP1PPSbits.CCP1PPS4 // bit 4
6865 #define CCP2CTS0 CCP2CAPbits.CCP2CTS0 // bit 0
6866 #define CCP2CTS1 CCP2CAPbits.CCP2CTS1 // bit 1
6867 #define CCP2CTS2 CCP2CAPbits.CCP2CTS2 // bit 2
6869 #define CCP2MODE0 CCP2CONbits.CCP2MODE0 // bit 0
6870 #define CCP2MODE1 CCP2CONbits.CCP2MODE1 // bit 1
6871 #define CCP2MODE2 CCP2CONbits.CCP2MODE2 // bit 2
6872 #define CCP2MODE3 CCP2CONbits.CCP2MODE3 // bit 3
6873 #define CCP2FMT CCP2CONbits.CCP2FMT // bit 4
6874 #define CCP2OUT CCP2CONbits.CCP2OUT // bit 5
6875 #define CCP2EN CCP2CONbits.CCP2EN // bit 7
6877 #define CCP2PPS0 CCP2PPSbits.CCP2PPS0 // bit 0
6878 #define CCP2PPS1 CCP2PPSbits.CCP2PPS1 // bit 1
6879 #define CCP2PPS2 CCP2PPSbits.CCP2PPS2 // bit 2
6880 #define CCP2PPS3 CCP2PPSbits.CCP2PPS3 // bit 3
6881 #define CCP2PPS4 CCP2PPSbits.CCP2PPS4 // bit 4
6883 #define C1TSEL CCPTMRSbits.C1TSEL // bit 0
6884 #define C2TSEL CCPTMRSbits.C2TSEL // bit 2
6886 #define LC1MODE0 CLC1CONbits.LC1MODE0 // bit 0, shadows bit in CLC1CONbits
6887 #define MODE0 CLC1CONbits.MODE0 // bit 0, shadows bit in CLC1CONbits
6888 #define LC1MODE1 CLC1CONbits.LC1MODE1 // bit 1, shadows bit in CLC1CONbits
6889 #define MODE1 CLC1CONbits.MODE1 // bit 1, shadows bit in CLC1CONbits
6890 #define LC1MODE2 CLC1CONbits.LC1MODE2 // bit 2, shadows bit in CLC1CONbits
6891 #define MODE2 CLC1CONbits.MODE2 // bit 2, shadows bit in CLC1CONbits
6892 #define LC1INTN CLC1CONbits.LC1INTN // bit 3, shadows bit in CLC1CONbits
6893 #define INTN CLC1CONbits.INTN // bit 3, shadows bit in CLC1CONbits
6894 #define LC1INTP CLC1CONbits.LC1INTP // bit 4, shadows bit in CLC1CONbits
6895 #define INTP CLC1CONbits.INTP // bit 4, shadows bit in CLC1CONbits
6896 #define LC1OUT CLC1CONbits.LC1OUT // bit 5, shadows bit in CLC1CONbits
6897 #define OUT CLC1CONbits.OUT // bit 5, shadows bit in CLC1CONbits
6898 #define LC1EN CLC1CONbits.LC1EN // bit 7, shadows bit in CLC1CONbits
6899 #define EN CLC1CONbits.EN // bit 7, shadows bit in CLC1CONbits
6901 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
6902 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
6903 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
6904 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
6905 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
6906 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
6907 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
6908 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
6909 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
6910 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
6911 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
6912 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
6913 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
6914 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
6915 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
6916 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
6918 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
6919 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
6920 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
6921 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
6922 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
6923 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
6924 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
6925 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
6926 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
6927 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
6928 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
6929 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
6930 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
6931 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
6932 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
6933 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
6935 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
6936 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
6937 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
6938 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
6939 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
6940 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
6941 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
6942 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
6943 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
6944 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
6946 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
6947 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
6948 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
6949 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
6950 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
6951 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
6952 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
6953 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
6954 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
6955 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
6957 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
6958 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
6959 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
6960 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
6961 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
6962 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
6963 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
6964 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
6965 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
6966 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
6968 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
6969 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
6970 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
6971 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
6972 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
6973 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
6974 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
6975 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
6976 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
6977 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
6979 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
6980 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
6981 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
6982 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
6983 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
6984 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
6985 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
6986 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
6987 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
6988 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
6990 #define MLC1OUT CLCDATAbits.MLC1OUT // bit 0
6991 #define MLC2OUT CLCDATAbits.MLC2OUT // bit 1
6993 #define CLCIN0PPS0 CLCIN0PPSbits.CLCIN0PPS0 // bit 0
6994 #define CLCIN0PPS1 CLCIN0PPSbits.CLCIN0PPS1 // bit 1
6995 #define CLCIN0PPS2 CLCIN0PPSbits.CLCIN0PPS2 // bit 2
6996 #define CLCIN0PPS3 CLCIN0PPSbits.CLCIN0PPS3 // bit 3
6997 #define CLCIN0PPS4 CLCIN0PPSbits.CLCIN0PPS4 // bit 4
6999 #define CLCIN1PPS0 CLCIN1PPSbits.CLCIN1PPS0 // bit 0
7000 #define CLCIN1PPS1 CLCIN1PPSbits.CLCIN1PPS1 // bit 1
7001 #define CLCIN1PPS2 CLCIN1PPSbits.CLCIN1PPS2 // bit 2
7002 #define CLCIN1PPS3 CLCIN1PPSbits.CLCIN1PPS3 // bit 3
7003 #define CLCIN1PPS4 CLCIN1PPSbits.CLCIN1PPS4 // bit 4
7005 #define CLCIN2PPS0 CLCIN2PPSbits.CLCIN2PPS0 // bit 0
7006 #define CLCIN2PPS1 CLCIN2PPSbits.CLCIN2PPS1 // bit 1
7007 #define CLCIN2PPS2 CLCIN2PPSbits.CLCIN2PPS2 // bit 2
7008 #define CLCIN2PPS3 CLCIN2PPSbits.CLCIN2PPS3 // bit 3
7009 #define CLCIN2PPS4 CLCIN2PPSbits.CLCIN2PPS4 // bit 4
7011 #define CLCIN3PPS0 CLCIN3PPSbits.CLCIN3PPS0 // bit 0
7012 #define CLCIN3PPS1 CLCIN3PPSbits.CLCIN3PPS1 // bit 1
7013 #define CLCIN3PPS2 CLCIN3PPSbits.CLCIN3PPS2 // bit 2
7014 #define CLCIN3PPS3 CLCIN3PPSbits.CLCIN3PPS3 // bit 3
7015 #define CLCIN3PPS4 CLCIN3PPSbits.CLCIN3PPS4 // bit 4
7017 #define CLKRDIV0 CLKRCONbits.CLKRDIV0 // bit 0
7018 #define CLKRDIV1 CLKRCONbits.CLKRDIV1 // bit 1
7019 #define CLKRDIV2 CLKRCONbits.CLKRDIV2 // bit 2
7020 #define CLKRDC0 CLKRCONbits.CLKRDC0 // bit 3
7021 #define CLKRDC1 CLKRCONbits.CLKRDC1 // bit 4
7022 #define CLKREN CLKRCONbits.CLKREN // bit 7
7024 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
7025 #define C1HYS CM1CON0bits.C1HYS // bit 1
7026 #define C1SP CM1CON0bits.C1SP // bit 2
7027 #define C1POL CM1CON0bits.C1POL // bit 4
7028 #define C1OUT CM1CON0bits.C1OUT // bit 6
7029 #define C1ON CM1CON0bits.C1ON // bit 7
7031 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
7032 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
7033 #define C1NCH2 CM1CON1bits.C1NCH2 // bit 2
7034 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 3
7035 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 4
7036 #define C1PCH2 CM1CON1bits.C1PCH2 // bit 5
7037 #define C1INTN CM1CON1bits.C1INTN // bit 6
7038 #define C1INTP CM1CON1bits.C1INTP // bit 7
7040 #define MC1OUT CMOUTbits.MC1OUT // bit 0
7042 #define DOZE0 CPUDOZEbits.DOZE0 // bit 0
7043 #define DOZE1 CPUDOZEbits.DOZE1 // bit 1
7044 #define DOZE2 CPUDOZEbits.DOZE2 // bit 2
7045 #define DOE CPUDOZEbits.DOE // bit 4
7046 #define ROI CPUDOZEbits.ROI // bit 5
7047 #define DOZEN CPUDOZEbits.DOZEN // bit 6
7048 #define IDLEN CPUDOZEbits.IDLEN // bit 7
7050 #define LSAC0 CWG1AS0bits.LSAC0 // bit 2, shadows bit in CWG1AS0bits
7051 #define CWG1LSAC0 CWG1AS0bits.CWG1LSAC0 // bit 2, shadows bit in CWG1AS0bits
7052 #define LSAC1 CWG1AS0bits.LSAC1 // bit 3, shadows bit in CWG1AS0bits
7053 #define CWG1LSAC1 CWG1AS0bits.CWG1LSAC1 // bit 3, shadows bit in CWG1AS0bits
7054 #define LSBD0 CWG1AS0bits.LSBD0 // bit 4, shadows bit in CWG1AS0bits
7055 #define CWG1LSBD0 CWG1AS0bits.CWG1LSBD0 // bit 4, shadows bit in CWG1AS0bits
7056 #define LSBD1 CWG1AS0bits.LSBD1 // bit 5, shadows bit in CWG1AS0bits
7057 #define CWG1LSBD1 CWG1AS0bits.CWG1LSBD1 // bit 5, shadows bit in CWG1AS0bits
7058 #define REN CWG1AS0bits.REN // bit 6, shadows bit in CWG1AS0bits
7059 #define CWG1REN CWG1AS0bits.CWG1REN // bit 6, shadows bit in CWG1AS0bits
7060 #define SHUTDOWN CWG1AS0bits.SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
7061 #define CWG1SHUTDOWN CWG1AS0bits.CWG1SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
7063 #define AS0E CWG1AS1bits.AS0E // bit 0
7064 #define AS1E CWG1AS1bits.AS1E // bit 1
7065 #define AS3E CWG1AS1bits.AS3E // bit 3
7067 #define CS CWG1CLKCONbits.CS // bit 0, shadows bit in CWG1CLKCONbits
7068 #define CWG1CS CWG1CLKCONbits.CWG1CS // bit 0, shadows bit in CWG1CLKCONbits
7070 #define POLA CWG1CON1bits.POLA // bit 0, shadows bit in CWG1CON1bits
7071 #define CWG1POLA CWG1CON1bits.CWG1POLA // bit 0, shadows bit in CWG1CON1bits
7072 #define POLB CWG1CON1bits.POLB // bit 1, shadows bit in CWG1CON1bits
7073 #define CWG1POLB CWG1CON1bits.CWG1POLB // bit 1, shadows bit in CWG1CON1bits
7074 #define POLC CWG1CON1bits.POLC // bit 2, shadows bit in CWG1CON1bits
7075 #define CWG1POLC CWG1CON1bits.CWG1POLC // bit 2, shadows bit in CWG1CON1bits
7076 #define POLD CWG1CON1bits.POLD // bit 3, shadows bit in CWG1CON1bits
7077 #define CWG1POLD CWG1CON1bits.CWG1POLD // bit 3, shadows bit in CWG1CON1bits
7078 #define IN CWG1CON1bits.IN // bit 5, shadows bit in CWG1CON1bits
7079 #define CWG1IN CWG1CON1bits.CWG1IN // bit 5, shadows bit in CWG1CON1bits
7081 #define CWG1DAT0 CWG1DATbits.CWG1DAT0 // bit 0
7082 #define CWG1DAT1 CWG1DATbits.CWG1DAT1 // bit 1
7083 #define CWG1DAT2 CWG1DATbits.CWG1DAT2 // bit 2
7084 #define CWG1DAT3 CWG1DATbits.CWG1DAT3 // bit 3
7086 #define DBF0 CWG1DBFbits.DBF0 // bit 0, shadows bit in CWG1DBFbits
7087 #define CWG1DBF0 CWG1DBFbits.CWG1DBF0 // bit 0, shadows bit in CWG1DBFbits
7088 #define DBF1 CWG1DBFbits.DBF1 // bit 1, shadows bit in CWG1DBFbits
7089 #define CWG1DBF1 CWG1DBFbits.CWG1DBF1 // bit 1, shadows bit in CWG1DBFbits
7090 #define DBF2 CWG1DBFbits.DBF2 // bit 2, shadows bit in CWG1DBFbits
7091 #define CWG1DBF2 CWG1DBFbits.CWG1DBF2 // bit 2, shadows bit in CWG1DBFbits
7092 #define DBF3 CWG1DBFbits.DBF3 // bit 3, shadows bit in CWG1DBFbits
7093 #define CWG1DBF3 CWG1DBFbits.CWG1DBF3 // bit 3, shadows bit in CWG1DBFbits
7094 #define DBF4 CWG1DBFbits.DBF4 // bit 4, shadows bit in CWG1DBFbits
7095 #define CWG1DBF4 CWG1DBFbits.CWG1DBF4 // bit 4, shadows bit in CWG1DBFbits
7096 #define DBF5 CWG1DBFbits.DBF5 // bit 5, shadows bit in CWG1DBFbits
7097 #define CWG1DBF5 CWG1DBFbits.CWG1DBF5 // bit 5, shadows bit in CWG1DBFbits
7099 #define DBR0 CWG1DBRbits.DBR0 // bit 0, shadows bit in CWG1DBRbits
7100 #define CWG1DBR0 CWG1DBRbits.CWG1DBR0 // bit 0, shadows bit in CWG1DBRbits
7101 #define DBR1 CWG1DBRbits.DBR1 // bit 1, shadows bit in CWG1DBRbits
7102 #define CWG1DBR1 CWG1DBRbits.CWG1DBR1 // bit 1, shadows bit in CWG1DBRbits
7103 #define DBR2 CWG1DBRbits.DBR2 // bit 2, shadows bit in CWG1DBRbits
7104 #define CWG1DBR2 CWG1DBRbits.CWG1DBR2 // bit 2, shadows bit in CWG1DBRbits
7105 #define DBR3 CWG1DBRbits.DBR3 // bit 3, shadows bit in CWG1DBRbits
7106 #define CWG1DBR3 CWG1DBRbits.CWG1DBR3 // bit 3, shadows bit in CWG1DBRbits
7107 #define DBR4 CWG1DBRbits.DBR4 // bit 4, shadows bit in CWG1DBRbits
7108 #define CWG1DBR4 CWG1DBRbits.CWG1DBR4 // bit 4, shadows bit in CWG1DBRbits
7109 #define DBR5 CWG1DBRbits.DBR5 // bit 5, shadows bit in CWG1DBRbits
7110 #define CWG1DBR5 CWG1DBRbits.CWG1DBR5 // bit 5, shadows bit in CWG1DBRbits
7112 #define CWG1PPS0 CWG1PPSbits.CWG1PPS0 // bit 0
7113 #define CWG1PPS1 CWG1PPSbits.CWG1PPS1 // bit 1
7114 #define CWG1PPS2 CWG1PPSbits.CWG1PPS2 // bit 2
7115 #define CWG1PPS3 CWG1PPSbits.CWG1PPS3 // bit 3
7116 #define CWG1PPS4 CWG1PPSbits.CWG1PPS4 // bit 4
7118 #define STRA CWG1STRbits.STRA // bit 0, shadows bit in CWG1STRbits
7119 #define CWG1STRA CWG1STRbits.CWG1STRA // bit 0, shadows bit in CWG1STRbits
7120 #define STRB CWG1STRbits.STRB // bit 1, shadows bit in CWG1STRbits
7121 #define CWG1STRB CWG1STRbits.CWG1STRB // bit 1, shadows bit in CWG1STRbits
7122 #define STRC CWG1STRbits.STRC // bit 2, shadows bit in CWG1STRbits
7123 #define CWG1STRC CWG1STRbits.CWG1STRC // bit 2, shadows bit in CWG1STRbits
7124 #define STRD CWG1STRbits.STRD // bit 3, shadows bit in CWG1STRbits
7125 #define CWG1STRD CWG1STRbits.CWG1STRD // bit 3, shadows bit in CWG1STRbits
7126 #define OVRA CWG1STRbits.OVRA // bit 4, shadows bit in CWG1STRbits
7127 #define CWG1OVRA CWG1STRbits.CWG1OVRA // bit 4, shadows bit in CWG1STRbits
7128 #define OVRB CWG1STRbits.OVRB // bit 5, shadows bit in CWG1STRbits
7129 #define CWG1OVRB CWG1STRbits.CWG1OVRB // bit 5, shadows bit in CWG1STRbits
7130 #define OVRC CWG1STRbits.OVRC // bit 6, shadows bit in CWG1STRbits
7131 #define CWG1OVRC CWG1STRbits.CWG1OVRC // bit 6, shadows bit in CWG1STRbits
7132 #define OVRD CWG1STRbits.OVRD // bit 7, shadows bit in CWG1STRbits
7133 #define CWG1OVRD CWG1STRbits.CWG1OVRD // bit 7, shadows bit in CWG1STRbits
7135 #define DAC1NSS DACCON0bits.DAC1NSS // bit 0
7136 #define DAC1PSS0 DACCON0bits.DAC1PSS0 // bit 2
7137 #define DAC1PSS1 DACCON0bits.DAC1PSS1 // bit 3
7138 #define DAC1OE DACCON0bits.DAC1OE // bit 5
7139 #define DAC1EN DACCON0bits.DAC1EN // bit 7
7141 #define DAC1R0 DACCON1bits.DAC1R0 // bit 0
7142 #define DAC1R1 DACCON1bits.DAC1R1 // bit 1
7143 #define DAC1R2 DACCON1bits.DAC1R2 // bit 2
7144 #define DAC1R3 DACCON1bits.DAC1R3 // bit 3
7145 #define DAC1R4 DACCON1bits.DAC1R4 // bit 4
7147 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
7148 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
7149 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
7150 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
7151 #define TSRNG FVRCONbits.TSRNG // bit 4
7152 #define TSEN FVRCONbits.TSEN // bit 5
7153 #define FVRRDY FVRCONbits.FVRRDY // bit 6
7154 #define FVREN FVRCONbits.FVREN // bit 7
7156 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
7157 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
7158 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
7159 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
7160 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
7161 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
7163 #define INTEDG INTCONbits.INTEDG // bit 0
7164 #define PEIE INTCONbits.PEIE // bit 6
7165 #define GIE INTCONbits.GIE // bit 7
7167 #define INTPPS0 INTPPSbits.INTPPS0 // bit 0
7168 #define INTPPS1 INTPPSbits.INTPPS1 // bit 1
7169 #define INTPPS2 INTPPSbits.INTPPS2 // bit 2
7170 #define INTPPS3 INTPPSbits.INTPPS3 // bit 3
7171 #define INTPPS4 INTPPSbits.INTPPS4 // bit 4
7173 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
7174 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
7175 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
7176 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
7177 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
7178 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
7180 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
7181 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
7182 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
7183 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
7184 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
7185 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
7187 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
7188 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
7189 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
7190 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
7191 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
7192 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
7194 #define LATA0 LATAbits.LATA0 // bit 0
7195 #define LATA1 LATAbits.LATA1 // bit 1
7196 #define LATA2 LATAbits.LATA2 // bit 2
7197 #define LATA4 LATAbits.LATA4 // bit 4
7198 #define LATA5 LATAbits.LATA5 // bit 5
7200 #define MDCH0 MDCARHbits.MDCH0 // bit 0
7201 #define MDCH1 MDCARHbits.MDCH1 // bit 1
7202 #define MDCH2 MDCARHbits.MDCH2 // bit 2
7203 #define MDCH3 MDCARHbits.MDCH3 // bit 3
7204 #define MDCHSYNC MDCARHbits.MDCHSYNC // bit 5
7205 #define MDCHPOL MDCARHbits.MDCHPOL // bit 6
7207 #define MDCL0 MDCARLbits.MDCL0 // bit 0
7208 #define MDCL1 MDCARLbits.MDCL1 // bit 1
7209 #define MDCL2 MDCARLbits.MDCL2 // bit 2
7210 #define MDCL3 MDCARLbits.MDCL3 // bit 3
7211 #define MDCLSYNC MDCARLbits.MDCLSYNC // bit 5
7212 #define MDCLPOL MDCARLbits.MDCLPOL // bit 6
7214 #define MDCIN1PPS0 MDCIN1PPSbits.MDCIN1PPS0 // bit 0
7215 #define MDCIN1PPS1 MDCIN1PPSbits.MDCIN1PPS1 // bit 1
7216 #define MDCIN1PPS2 MDCIN1PPSbits.MDCIN1PPS2 // bit 2
7217 #define MDCIN1PPS3 MDCIN1PPSbits.MDCIN1PPS3 // bit 3
7218 #define MDCIN1PPS4 MDCIN1PPSbits.MDCIN1PPS4 // bit 4
7220 #define MDCIN2PPS0 MDCIN2PPSbits.MDCIN2PPS0 // bit 0
7221 #define MDCIN2PPS1 MDCIN2PPSbits.MDCIN2PPS1 // bit 1
7222 #define MDCIN2PPS2 MDCIN2PPSbits.MDCIN2PPS2 // bit 2
7223 #define MDCIN2PPS3 MDCIN2PPSbits.MDCIN2PPS3 // bit 3
7224 #define MDCIN2PPS4 MDCIN2PPSbits.MDCIN2PPS4 // bit 4
7226 #define MDBIT MDCONbits.MDBIT // bit 0
7227 #define MDOUT MDCONbits.MDOUT // bit 3
7228 #define MDOPOL MDCONbits.MDOPOL // bit 4
7229 #define MDEN MDCONbits.MDEN // bit 7
7231 #define MDMINPPS0 MDMINPPSbits.MDMINPPS0 // bit 0
7232 #define MDMINPPS1 MDMINPPSbits.MDMINPPS1 // bit 1
7233 #define MDMINPPS2 MDMINPPSbits.MDMINPPS2 // bit 2
7234 #define MDMINPPS3 MDMINPPSbits.MDMINPPS3 // bit 3
7235 #define MDMINPPS4 MDMINPPSbits.MDMINPPS4 // bit 4
7237 #define MDMS0 MDSRCbits.MDMS0 // bit 0
7238 #define MDMS1 MDSRCbits.MDMS1 // bit 1
7239 #define MDMS2 MDSRCbits.MDMS2 // bit 2
7240 #define MDMS3 MDSRCbits.MDMS3 // bit 3
7242 #define N1PFM NCO1CONbits.N1PFM // bit 0
7243 #define N1POL NCO1CONbits.N1POL // bit 4
7244 #define N1OUT NCO1CONbits.N1OUT // bit 5
7245 #define N1EN NCO1CONbits.N1EN // bit 7
7247 #define NVMADR8 NVMADRHbits.NVMADR8 // bit 0
7248 #define NVMADR9 NVMADRHbits.NVMADR9 // bit 1
7249 #define NVMADR10 NVMADRHbits.NVMADR10 // bit 2
7250 #define NVMADR11 NVMADRHbits.NVMADR11 // bit 3
7251 #define NVMADR12 NVMADRHbits.NVMADR12 // bit 4
7252 #define NVMADR13 NVMADRHbits.NVMADR13 // bit 5
7253 #define NVMADR14 NVMADRHbits.NVMADR14 // bit 6
7255 #define NVMADR0 NVMADRLbits.NVMADR0 // bit 0
7256 #define NVMADR1 NVMADRLbits.NVMADR1 // bit 1
7257 #define NVMADR2 NVMADRLbits.NVMADR2 // bit 2
7258 #define NVMADR3 NVMADRLbits.NVMADR3 // bit 3
7259 #define NVMADR4 NVMADRLbits.NVMADR4 // bit 4
7260 #define NVMADR5 NVMADRLbits.NVMADR5 // bit 5
7261 #define NVMADR6 NVMADRLbits.NVMADR6 // bit 6
7262 #define NVMADR7 NVMADRLbits.NVMADR7 // bit 7
7264 #define RD NVMCON1bits.RD // bit 0
7265 #define WR NVMCON1bits.WR // bit 1
7266 #define WREN NVMCON1bits.WREN // bit 2
7267 #define WRERR NVMCON1bits.WRERR // bit 3
7268 #define FREE NVMCON1bits.FREE // bit 4
7269 #define LWLO NVMCON1bits.LWLO // bit 5
7270 #define NVMREGS NVMCON1bits.NVMREGS // bit 6
7272 #define NVMDAT8 NVMDATHbits.NVMDAT8 // bit 0
7273 #define NVMDAT9 NVMDATHbits.NVMDAT9 // bit 1
7274 #define NVMDAT10 NVMDATHbits.NVMDAT10 // bit 2
7275 #define NVMDAT11 NVMDATHbits.NVMDAT11 // bit 3
7276 #define NVMDAT12 NVMDATHbits.NVMDAT12 // bit 4
7277 #define NVMDAT13 NVMDATHbits.NVMDAT13 // bit 5
7279 #define NVMDAT0 NVMDATLbits.NVMDAT0 // bit 0
7280 #define NVMDAT1 NVMDATLbits.NVMDAT1 // bit 1
7281 #define NVMDAT2 NVMDATLbits.NVMDAT2 // bit 2
7282 #define NVMDAT3 NVMDATLbits.NVMDAT3 // bit 3
7283 #define NVMDAT4 NVMDATLbits.NVMDAT4 // bit 4
7284 #define NVMDAT5 NVMDATLbits.NVMDAT5 // bit 5
7285 #define NVMDAT6 NVMDATLbits.NVMDAT6 // bit 6
7286 #define NVMDAT7 NVMDATLbits.NVMDAT7 // bit 7
7288 #define ODCA0 ODCONAbits.ODCA0 // bit 0
7289 #define ODCA1 ODCONAbits.ODCA1 // bit 1
7290 #define ODCA2 ODCONAbits.ODCA2 // bit 2
7291 #define ODCA4 ODCONAbits.ODCA4 // bit 4
7292 #define ODCA5 ODCONAbits.ODCA5 // bit 5
7294 #define NDIV0 OSCCON1bits.NDIV0 // bit 0
7295 #define NDIV1 OSCCON1bits.NDIV1 // bit 1
7296 #define NDIV2 OSCCON1bits.NDIV2 // bit 2
7297 #define NDIV3 OSCCON1bits.NDIV3 // bit 3
7298 #define NOSC0 OSCCON1bits.NOSC0 // bit 4
7299 #define NOSC1 OSCCON1bits.NOSC1 // bit 5
7300 #define NOSC2 OSCCON1bits.NOSC2 // bit 6
7302 #define CDIV0 OSCCON2bits.CDIV0 // bit 0
7303 #define CDIV1 OSCCON2bits.CDIV1 // bit 1
7304 #define CDIV2 OSCCON2bits.CDIV2 // bit 2
7305 #define CDIV3 OSCCON2bits.CDIV3 // bit 3
7306 #define COSC0 OSCCON2bits.COSC0 // bit 4
7307 #define COSC1 OSCCON2bits.COSC1 // bit 5
7308 #define COSC2 OSCCON2bits.COSC2 // bit 6
7310 #define NOSCR OSCCON3bits.NOSCR // bit 3
7311 #define ORDY OSCCON3bits.ORDY // bit 4
7312 #define SOSCBE OSCCON3bits.SOSCBE // bit 5
7313 #define SOSCPWR OSCCON3bits.SOSCPWR // bit 6
7314 #define CSWHOLD OSCCON3bits.CSWHOLD // bit 7
7316 #define ADOEN OSCENbits.ADOEN // bit 2
7317 #define SOSCEN OSCENbits.SOSCEN // bit 3
7318 #define LFOEN OSCENbits.LFOEN // bit 4
7319 #define HFOEN OSCENbits.HFOEN // bit 6
7320 #define EXTOEN OSCENbits.EXTOEN // bit 7
7322 #define HFFRQ0 OSCFRQbits.HFFRQ0 // bit 0
7323 #define HFFRQ1 OSCFRQbits.HFFRQ1 // bit 1
7324 #define HFFRQ2 OSCFRQbits.HFFRQ2 // bit 2
7325 #define HFFRQ3 OSCFRQbits.HFFRQ3 // bit 3
7327 #define PLLR OSCSTAT1bits.PLLR // bit 0
7328 #define ADOR OSCSTAT1bits.ADOR // bit 2
7329 #define SOR OSCSTAT1bits.SOR // bit 3
7330 #define LFOR OSCSTAT1bits.LFOR // bit 4
7331 #define HFOR OSCSTAT1bits.HFOR // bit 6
7332 #define EXTOR OSCSTAT1bits.EXTOR // bit 7
7334 #define HFTUN0 OSCTUNEbits.HFTUN0 // bit 0
7335 #define HFTUN1 OSCTUNEbits.HFTUN1 // bit 1
7336 #define HFTUN2 OSCTUNEbits.HFTUN2 // bit 2
7337 #define HFTUN3 OSCTUNEbits.HFTUN3 // bit 3
7338 #define HFTUN4 OSCTUNEbits.HFTUN4 // bit 4
7339 #define HFTUN5 OSCTUNEbits.HFTUN5 // bit 5
7341 #define NOT_BOR PCON0bits.NOT_BOR // bit 0
7342 #define NOT_POR PCON0bits.NOT_POR // bit 1
7343 #define NOT_RI PCON0bits.NOT_RI // bit 2
7344 #define NOT_RMCLR PCON0bits.NOT_RMCLR // bit 3
7345 #define NOT_RWDT PCON0bits.NOT_RWDT // bit 4
7346 #define STKUNF PCON0bits.STKUNF // bit 6
7347 #define STKOVF PCON0bits.STKOVF // bit 7
7349 #define INTE PIE0bits.INTE // bit 0
7350 #define IOCIE PIE0bits.IOCIE // bit 4
7351 #define TMR0IE PIE0bits.TMR0IE // bit 5
7353 #define TMR1IE PIE1bits.TMR1IE // bit 0
7354 #define TMR2IE PIE1bits.TMR2IE // bit 1
7355 #define BCL1IE PIE1bits.BCL1IE // bit 2
7356 #define SSP1IE PIE1bits.SSP1IE // bit 3
7357 #define TXIE PIE1bits.TXIE // bit 4
7358 #define RCIE PIE1bits.RCIE // bit 5
7359 #define ADIE PIE1bits.ADIE // bit 6
7360 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
7362 #define NCO1IE PIE2bits.NCO1IE // bit 0
7363 #define NVMIE PIE2bits.NVMIE // bit 4
7364 #define C1IE PIE2bits.C1IE // bit 5
7366 #define CLC1IE PIE3bits.CLC1IE // bit 0
7367 #define CLC2IE PIE3bits.CLC2IE // bit 1
7368 #define CSWIE PIE3bits.CSWIE // bit 6
7369 #define OSFIE PIE3bits.OSFIE // bit 7
7371 #define CCP1IE PIE4bits.CCP1IE // bit 0
7372 #define CCP2IE PIE4bits.CCP2IE // bit 1
7373 #define CWG1IE PIE4bits.CWG1IE // bit 6
7375 #define INTF PIR0bits.INTF // bit 0
7376 #define IOCIF PIR0bits.IOCIF // bit 4
7377 #define TMR0IF PIR0bits.TMR0IF // bit 5
7379 #define TMR1IF PIR1bits.TMR1IF // bit 0
7380 #define TMR2IF PIR1bits.TMR2IF // bit 1
7381 #define BCL1IF PIR1bits.BCL1IF // bit 2
7382 #define SSP1IF PIR1bits.SSP1IF // bit 3
7383 #define TXIF PIR1bits.TXIF // bit 4
7384 #define RCIF PIR1bits.RCIF // bit 5
7385 #define ADIF PIR1bits.ADIF // bit 6
7386 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
7388 #define NCO1IF PIR2bits.NCO1IF // bit 0
7389 #define NVMIF PIR2bits.NVMIF // bit 4
7390 #define C1IF PIR2bits.C1IF // bit 5
7392 #define CLC1IF PIR3bits.CLC1IF // bit 0
7393 #define CLC2IF PIR3bits.CLC2IF // bit 1
7394 #define CSWIF PIR3bits.CSWIF // bit 6
7395 #define OSFIF PIR3bits.OSFIF // bit 7
7397 #define CCP1IF PIR4bits.CCP1IF // bit 0
7398 #define CCP2IF PIR4bits.CCP2IF // bit 1
7399 #define CWG1IF PIR4bits.CWG1IF // bit 6
7401 #define IOCMD PMD0bits.IOCMD // bit 0
7402 #define CLKRMD PMD0bits.CLKRMD // bit 1
7403 #define NVMMD PMD0bits.NVMMD // bit 2
7404 #define FVRMD PMD0bits.FVRMD // bit 6
7405 #define SYSCMD PMD0bits.SYSCMD // bit 7
7407 #define TMR0MD PMD1bits.TMR0MD // bit 0
7408 #define TMR1MD PMD1bits.TMR1MD // bit 1
7409 #define TMR2MD PMD1bits.TMR2MD // bit 2
7410 #define NCOMD PMD1bits.NCOMD // bit 7
7412 #define CMP1MD PMD2bits.CMP1MD // bit 1
7413 #define ADCMD PMD2bits.ADCMD // bit 5
7414 #define DACMD PMD2bits.DACMD // bit 6
7416 #define CCP1MD PMD3bits.CCP1MD // bit 0
7417 #define CCP2MD PMD3bits.CCP2MD // bit 1
7418 #define PWM5MD PMD3bits.PWM5MD // bit 4
7419 #define PWM6MD PMD3bits.PWM6MD // bit 5
7420 #define CWG1MD PMD3bits.CWG1MD // bit 6
7422 #define MSSP1MD PMD4bits.MSSP1MD // bit 1
7423 #define UART1MD PMD4bits.UART1MD // bit 5
7425 #define DSMMD PMD5bits.DSMMD // bit 0
7426 #define CLC1MD PMD5bits.CLC1MD // bit 1
7427 #define CLC2MD PMD5bits.CLC2MD // bit 2
7429 #define RA0 PORTAbits.RA0 // bit 0
7430 #define RA1 PORTAbits.RA1 // bit 1
7431 #define RA2 PORTAbits.RA2 // bit 2
7432 #define RA3 PORTAbits.RA3 // bit 3
7433 #define RA4 PORTAbits.RA4 // bit 4
7434 #define RA5 PORTAbits.RA5 // bit 5
7436 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
7438 #define PWM5POL PWM5CONbits.PWM5POL // bit 4
7439 #define PWM5OUT PWM5CONbits.PWM5OUT // bit 5
7440 #define PWM5EN PWM5CONbits.PWM5EN // bit 7
7442 #define PWM5DCH0 PWM5DCHbits.PWM5DCH0 // bit 0
7443 #define PWM5DCH1 PWM5DCHbits.PWM5DCH1 // bit 1
7444 #define PWM5DCH2 PWM5DCHbits.PWM5DCH2 // bit 2
7445 #define PWM5DCH3 PWM5DCHbits.PWM5DCH3 // bit 3
7446 #define PWM5DCH4 PWM5DCHbits.PWM5DCH4 // bit 4
7447 #define PWM5DCH5 PWM5DCHbits.PWM5DCH5 // bit 5
7448 #define PWM5DCH6 PWM5DCHbits.PWM5DCH6 // bit 6
7449 #define PWM5DCH7 PWM5DCHbits.PWM5DCH7 // bit 7
7451 #define PWM5DCL0 PWM5DCLbits.PWM5DCL0 // bit 6
7452 #define PWM5DCL1 PWM5DCLbits.PWM5DCL1 // bit 7
7454 #define PWM6POL PWM6CONbits.PWM6POL // bit 4
7455 #define PWM6OUT PWM6CONbits.PWM6OUT // bit 5
7456 #define PWM6EN PWM6CONbits.PWM6EN // bit 7
7458 #define PWM6DCH0 PWM6DCHbits.PWM6DCH0 // bit 0
7459 #define PWM6DCH1 PWM6DCHbits.PWM6DCH1 // bit 1
7460 #define PWM6DCH2 PWM6DCHbits.PWM6DCH2 // bit 2
7461 #define PWM6DCH3 PWM6DCHbits.PWM6DCH3 // bit 3
7462 #define PWM6DCH4 PWM6DCHbits.PWM6DCH4 // bit 4
7463 #define PWM6DCH5 PWM6DCHbits.PWM6DCH5 // bit 5
7464 #define PWM6DCH6 PWM6DCHbits.PWM6DCH6 // bit 6
7465 #define PWM6DCH7 PWM6DCHbits.PWM6DCH7 // bit 7
7467 #define PWM6DCL0 PWM6DCLbits.PWM6DCL0 // bit 6
7468 #define PWM6DCL1 PWM6DCLbits.PWM6DCL1 // bit 7
7470 #define RA0PPS0 RA0PPSbits.RA0PPS0 // bit 0
7471 #define RA0PPS1 RA0PPSbits.RA0PPS1 // bit 1
7472 #define RA0PPS2 RA0PPSbits.RA0PPS2 // bit 2
7473 #define RA0PPS3 RA0PPSbits.RA0PPS3 // bit 3
7474 #define RA0PPS4 RA0PPSbits.RA0PPS4 // bit 4
7476 #define RA1PPS0 RA1PPSbits.RA1PPS0 // bit 0
7477 #define RA1PPS1 RA1PPSbits.RA1PPS1 // bit 1
7478 #define RA1PPS2 RA1PPSbits.RA1PPS2 // bit 2
7479 #define RA1PPS3 RA1PPSbits.RA1PPS3 // bit 3
7480 #define RA1PPS4 RA1PPSbits.RA1PPS4 // bit 4
7482 #define RA2PPS0 RA2PPSbits.RA2PPS0 // bit 0
7483 #define RA2PPS1 RA2PPSbits.RA2PPS1 // bit 1
7484 #define RA2PPS2 RA2PPSbits.RA2PPS2 // bit 2
7485 #define RA2PPS3 RA2PPSbits.RA2PPS3 // bit 3
7486 #define RA2PPS4 RA2PPSbits.RA2PPS4 // bit 4
7488 #define RA4PPS0 RA4PPSbits.RA4PPS0 // bit 0
7489 #define RA4PPS1 RA4PPSbits.RA4PPS1 // bit 1
7490 #define RA4PPS2 RA4PPSbits.RA4PPS2 // bit 2
7491 #define RA4PPS3 RA4PPSbits.RA4PPS3 // bit 3
7492 #define RA4PPS4 RA4PPSbits.RA4PPS4 // bit 4
7494 #define RA5PPS0 RA5PPSbits.RA5PPS0 // bit 0
7495 #define RA5PPS1 RA5PPSbits.RA5PPS1 // bit 1
7496 #define RA5PPS2 RA5PPSbits.RA5PPS2 // bit 2
7497 #define RA5PPS3 RA5PPSbits.RA5PPS3 // bit 3
7498 #define RA5PPS4 RA5PPSbits.RA5PPS4 // bit 4
7500 #define RX9D RC1STAbits.RX9D // bit 0
7501 #define OERR RC1STAbits.OERR // bit 1
7502 #define FERR RC1STAbits.FERR // bit 2
7503 #define ADDEN RC1STAbits.ADDEN // bit 3
7504 #define CREN RC1STAbits.CREN // bit 4
7505 #define SREN RC1STAbits.SREN // bit 5
7506 #define RX9 RC1STAbits.RX9 // bit 6
7507 #define SPEN RC1STAbits.SPEN // bit 7
7509 #define RXPPS0 RXPPSbits.RXPPS0 // bit 0
7510 #define RXPPS1 RXPPSbits.RXPPS1 // bit 1
7511 #define RXPPS2 RXPPSbits.RXPPS2 // bit 2
7512 #define RXPPS3 RXPPSbits.RXPPS3 // bit 3
7513 #define RXPPS4 RXPPSbits.RXPPS4 // bit 4
7515 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
7516 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
7517 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
7518 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
7519 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
7521 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
7522 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
7523 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
7524 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
7525 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
7526 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
7527 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
7528 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
7529 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
7530 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
7531 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
7532 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
7533 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
7534 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
7535 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
7536 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
7538 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
7539 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
7540 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
7541 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
7542 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
7543 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
7544 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
7545 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
7546 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
7547 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
7548 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
7549 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
7550 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
7551 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
7552 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
7553 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
7555 #define SSP1CLKPPS0 SSP1CLKPPSbits.SSP1CLKPPS0 // bit 0
7556 #define SSP1CLKPPS1 SSP1CLKPPSbits.SSP1CLKPPS1 // bit 1
7557 #define SSP1CLKPPS2 SSP1CLKPPSbits.SSP1CLKPPS2 // bit 2
7558 #define SSP1CLKPPS3 SSP1CLKPPSbits.SSP1CLKPPS3 // bit 3
7559 #define SSP1CLKPPS4 SSP1CLKPPSbits.SSP1CLKPPS4 // bit 4
7561 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
7562 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
7563 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
7564 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
7565 #define CKP SSP1CONbits.CKP // bit 4
7566 #define SSPEN SSP1CONbits.SSPEN // bit 5
7567 #define SSPOV SSP1CONbits.SSPOV // bit 6
7568 #define WCOL SSP1CONbits.WCOL // bit 7
7570 #define SEN SSP1CON2bits.SEN // bit 0
7571 #define RSEN SSP1CON2bits.RSEN // bit 1
7572 #define PEN SSP1CON2bits.PEN // bit 2
7573 #define RCEN SSP1CON2bits.RCEN // bit 3
7574 #define ACKEN SSP1CON2bits.ACKEN // bit 4
7575 #define ACKDT SSP1CON2bits.ACKDT // bit 5
7576 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
7577 #define GCEN SSP1CON2bits.GCEN // bit 7
7579 #define DHEN SSP1CON3bits.DHEN // bit 0
7580 #define AHEN SSP1CON3bits.AHEN // bit 1
7581 #define SBCDE SSP1CON3bits.SBCDE // bit 2
7582 #define SDAHT SSP1CON3bits.SDAHT // bit 3
7583 #define BOEN SSP1CON3bits.BOEN // bit 4
7584 #define SCIE SSP1CON3bits.SCIE // bit 5
7585 #define PCIE SSP1CON3bits.PCIE // bit 6
7586 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
7588 #define SSP1DATPPS0 SSP1DATPPSbits.SSP1DATPPS0 // bit 0
7589 #define SSP1DATPPS1 SSP1DATPPSbits.SSP1DATPPS1 // bit 1
7590 #define SSP1DATPPS2 SSP1DATPPSbits.SSP1DATPPS2 // bit 2
7591 #define SSP1DATPPS3 SSP1DATPPSbits.SSP1DATPPS3 // bit 3
7592 #define SSP1DATPPS4 SSP1DATPPSbits.SSP1DATPPS4 // bit 4
7594 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
7595 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
7596 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
7597 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
7598 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
7599 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
7600 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
7601 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
7602 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
7603 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
7604 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
7605 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
7606 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
7607 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
7608 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
7609 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
7611 #define SSP1SSPPS0 SSP1SSPPSbits.SSP1SSPPS0 // bit 0
7612 #define SSP1SSPPS1 SSP1SSPPSbits.SSP1SSPPS1 // bit 1
7613 #define SSP1SSPPS2 SSP1SSPPSbits.SSP1SSPPS2 // bit 2
7614 #define SSP1SSPPS3 SSP1SSPPSbits.SSP1SSPPS3 // bit 3
7615 #define SSP1SSPPS4 SSP1SSPPSbits.SSP1SSPPS4 // bit 4
7617 #define BF SSP1STATbits.BF // bit 0
7618 #define UA SSP1STATbits.UA // bit 1
7619 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
7620 #define S SSP1STATbits.S // bit 3
7621 #define P SSP1STATbits.P // bit 4
7622 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
7623 #define CKE SSP1STATbits.CKE // bit 6
7624 #define SMP SSP1STATbits.SMP // bit 7
7626 #define C STATUSbits.C // bit 0
7627 #define DC STATUSbits.DC // bit 1
7628 #define Z STATUSbits.Z // bit 2
7629 #define NOT_PD STATUSbits.NOT_PD // bit 3
7630 #define NOT_TO STATUSbits.NOT_TO // bit 4
7632 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
7633 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
7634 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
7636 #define T0CKIPPS0 T0CKIPPSbits.T0CKIPPS0 // bit 0
7637 #define T0CKIPPS1 T0CKIPPSbits.T0CKIPPS1 // bit 1
7638 #define T0CKIPPS2 T0CKIPPSbits.T0CKIPPS2 // bit 2
7639 #define T0CKIPPS3 T0CKIPPSbits.T0CKIPPS3 // bit 3
7640 #define T0CKIPPS4 T0CKIPPSbits.T0CKIPPS4 // bit 4
7642 #define T0OUTPS0 T0CON0bits.T0OUTPS0 // bit 0
7643 #define T0OUTPS1 T0CON0bits.T0OUTPS1 // bit 1
7644 #define T0OUTPS2 T0CON0bits.T0OUTPS2 // bit 2
7645 #define T0OUTPS3 T0CON0bits.T0OUTPS3 // bit 3
7646 #define T016BIT T0CON0bits.T016BIT // bit 4
7647 #define T0OUT T0CON0bits.T0OUT // bit 5
7648 #define T0EN T0CON0bits.T0EN // bit 7
7650 #define T0CKPS0 T0CON1bits.T0CKPS0 // bit 0
7651 #define T0CKPS1 T0CON1bits.T0CKPS1 // bit 1
7652 #define T0CKPS2 T0CON1bits.T0CKPS2 // bit 2
7653 #define T0CKPS3 T0CON1bits.T0CKPS3 // bit 3
7654 #define T0ASYNC T0CON1bits.T0ASYNC // bit 4
7655 #define T0CS0 T0CON1bits.T0CS0 // bit 5
7656 #define T0CS1 T0CON1bits.T0CS1 // bit 6
7657 #define T0CS2 T0CON1bits.T0CS2 // bit 7
7659 #define T1CKIPPS0 T1CKIPPSbits.T1CKIPPS0 // bit 0
7660 #define T1CKIPPS1 T1CKIPPSbits.T1CKIPPS1 // bit 1
7661 #define T1CKIPPS2 T1CKIPPSbits.T1CKIPPS2 // bit 2
7662 #define T1CKIPPS3 T1CKIPPSbits.T1CKIPPS3 // bit 3
7663 #define T1CKIPPS4 T1CKIPPSbits.T1CKIPPS4 // bit 4
7665 #define TMR1ON T1CONbits.TMR1ON // bit 0
7666 #define T1SYNC T1CONbits.T1SYNC // bit 2
7667 #define T1SOSC T1CONbits.T1SOSC // bit 3
7668 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
7669 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
7670 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
7671 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
7673 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
7674 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
7675 #define T1GVAL T1GCONbits.T1GVAL // bit 2
7676 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3
7677 #define T1GSPM T1GCONbits.T1GSPM // bit 4
7678 #define T1GTM T1GCONbits.T1GTM // bit 5
7679 #define T1GPOL T1GCONbits.T1GPOL // bit 6
7680 #define TMR1GE T1GCONbits.TMR1GE // bit 7
7682 #define T1GPPS0 T1GPPSbits.T1GPPS0 // bit 0
7683 #define T1GPPS1 T1GPPSbits.T1GPPS1 // bit 1
7684 #define T1GPPS2 T1GPPSbits.T1GPPS2 // bit 2
7685 #define T1GPPS3 T1GPPSbits.T1GPPS3 // bit 3
7686 #define T1GPPS4 T1GPPSbits.T1GPPS4 // bit 4
7688 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
7689 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
7690 #define TMR2ON T2CONbits.TMR2ON // bit 2
7691 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
7692 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
7693 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
7694 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
7696 #define TMR08 TMR0Hbits.TMR08 // bit 0
7697 #define TMR09 TMR0Hbits.TMR09 // bit 1
7698 #define TMR010 TMR0Hbits.TMR010 // bit 2
7699 #define TMR011 TMR0Hbits.TMR011 // bit 3
7700 #define TMR012 TMR0Hbits.TMR012 // bit 4
7701 #define TMR013 TMR0Hbits.TMR013 // bit 5
7702 #define TMR014 TMR0Hbits.TMR014 // bit 6
7703 #define TMR015 TMR0Hbits.TMR015 // bit 7
7705 #define TMR00 TMR0Lbits.TMR00 // bit 0
7706 #define TMR01 TMR0Lbits.TMR01 // bit 1
7707 #define TMR02 TMR0Lbits.TMR02 // bit 2
7708 #define TMR03 TMR0Lbits.TMR03 // bit 3
7709 #define TMR04 TMR0Lbits.TMR04 // bit 4
7710 #define TMR05 TMR0Lbits.TMR05 // bit 5
7711 #define TMR06 TMR0Lbits.TMR06 // bit 6
7712 #define TMR07 TMR0Lbits.TMR07 // bit 7
7714 #define TRISA0 TRISAbits.TRISA0 // bit 0
7715 #define TRISA1 TRISAbits.TRISA1 // bit 1
7716 #define TRISA2 TRISAbits.TRISA2 // bit 2
7717 #define TRISA4 TRISAbits.TRISA4 // bit 4
7718 #define TRISA5 TRISAbits.TRISA5 // bit 5
7720 #define TX9D TX1STAbits.TX9D // bit 0
7721 #define TRMT TX1STAbits.TRMT // bit 1
7722 #define BRGH TX1STAbits.BRGH // bit 2
7723 #define SENDB TX1STAbits.SENDB // bit 3
7724 #define SYNC TX1STAbits.SYNC // bit 4
7725 #define TXEN TX1STAbits.TXEN // bit 5
7726 #define TX9 TX1STAbits.TX9 // bit 6
7727 #define CSRC TX1STAbits.CSRC // bit 7
7729 #define TXPPS0 TXPPSbits.TXPPS0 // bit 0
7730 #define TXPPS1 TXPPSbits.TXPPS1 // bit 1
7731 #define TXPPS2 TXPPSbits.TXPPS2 // bit 2
7732 #define TXPPS3 TXPPSbits.TXPPS3 // bit 3
7733 #define TXPPS4 TXPPSbits.TXPPS4 // bit 4
7735 #define SWDTEN WDTCONbits.SWDTEN // bit 0
7736 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
7737 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
7738 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
7739 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
7740 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
7742 #define WPUA0 WPUAbits.WPUA0 // bit 0
7743 #define WPUA1 WPUAbits.WPUA1 // bit 1
7744 #define WPUA2 WPUAbits.WPUA2 // bit 2
7745 #define WPUA3 WPUAbits.WPUA3 // bit 3
7746 #define WPUA4 WPUAbits.WPUA4 // bit 4
7747 #define WPUA5 WPUAbits.WPUA5 // bit 5
7749 #endif // #ifndef NO_BIT_DEFINES
7751 #endif // #ifndef __PIC16LF18313_H__