2 * This declarations of the PIC16LF18324 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:24 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16LF18324_H__
26 #define __PIC16LF18324_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTC_ADDR 0x000E
52 #define PIR0_ADDR 0x0010
53 #define PIR1_ADDR 0x0011
54 #define PIR2_ADDR 0x0012
55 #define PIR3_ADDR 0x0013
56 #define PIR4_ADDR 0x0014
57 #define TMR0L_ADDR 0x0015
58 #define TMR0H_ADDR 0x0016
59 #define T0CON0_ADDR 0x0017
60 #define T0CON1_ADDR 0x0018
61 #define TMR1_ADDR 0x0019
62 #define TMR1L_ADDR 0x0019
63 #define TMR1H_ADDR 0x001A
64 #define T1CON_ADDR 0x001B
65 #define T1GCON_ADDR 0x001C
66 #define TMR2_ADDR 0x001D
67 #define PR2_ADDR 0x001E
68 #define T2CON_ADDR 0x001F
69 #define TRISA_ADDR 0x008C
70 #define TRISC_ADDR 0x008E
71 #define PIE0_ADDR 0x0090
72 #define PIE1_ADDR 0x0091
73 #define PIE2_ADDR 0x0092
74 #define PIE3_ADDR 0x0093
75 #define PIE4_ADDR 0x0094
76 #define WDTCON_ADDR 0x0097
77 #define ADRES_ADDR 0x009B
78 #define ADRESL_ADDR 0x009B
79 #define ADRESH_ADDR 0x009C
80 #define ADCON0_ADDR 0x009D
81 #define ADCON1_ADDR 0x009E
82 #define ADACT_ADDR 0x009F
83 #define LATA_ADDR 0x010C
84 #define LATC_ADDR 0x010E
85 #define CM1CON0_ADDR 0x0111
86 #define CM1CON1_ADDR 0x0112
87 #define CM2CON0_ADDR 0x0113
88 #define CM2CON1_ADDR 0x0114
89 #define CMOUT_ADDR 0x0115
90 #define BORCON_ADDR 0x0116
91 #define FVRCON_ADDR 0x0117
92 #define DACCON0_ADDR 0x0118
93 #define DACCON1_ADDR 0x0119
94 #define ANSELA_ADDR 0x018C
95 #define ANSELC_ADDR 0x018E
96 #define RC1REG_ADDR 0x0199
97 #define RCREG_ADDR 0x0199
98 #define RCREG1_ADDR 0x0199
99 #define TX1REG_ADDR 0x019A
100 #define TXREG_ADDR 0x019A
101 #define TXREG1_ADDR 0x019A
102 #define SP1BRG_ADDR 0x019B
103 #define SP1BRGL_ADDR 0x019B
104 #define SPBRG_ADDR 0x019B
105 #define SPBRG1_ADDR 0x019B
106 #define SPBRGL_ADDR 0x019B
107 #define SP1BRGH_ADDR 0x019C
108 #define SPBRGH_ADDR 0x019C
109 #define SPBRGH1_ADDR 0x019C
110 #define RC1STA_ADDR 0x019D
111 #define RCSTA_ADDR 0x019D
112 #define RCSTA1_ADDR 0x019D
113 #define TX1STA_ADDR 0x019E
114 #define TXSTA_ADDR 0x019E
115 #define TXSTA1_ADDR 0x019E
116 #define BAUD1CON_ADDR 0x019F
117 #define BAUDCON_ADDR 0x019F
118 #define BAUDCON1_ADDR 0x019F
119 #define BAUDCTL_ADDR 0x019F
120 #define BAUDCTL1_ADDR 0x019F
121 #define WPUA_ADDR 0x020C
122 #define WPUC_ADDR 0x020E
123 #define SSP1BUF_ADDR 0x0211
124 #define SSPBUF_ADDR 0x0211
125 #define SSP1ADD_ADDR 0x0212
126 #define SSPADD_ADDR 0x0212
127 #define SSP1MSK_ADDR 0x0213
128 #define SSPMSK_ADDR 0x0213
129 #define SSP1STAT_ADDR 0x0214
130 #define SSPSTAT_ADDR 0x0214
131 #define SSP1CON_ADDR 0x0215
132 #define SSP1CON1_ADDR 0x0215
133 #define SSPCON_ADDR 0x0215
134 #define SSPCON1_ADDR 0x0215
135 #define SSP1CON2_ADDR 0x0216
136 #define SSPCON2_ADDR 0x0216
137 #define SSP1CON3_ADDR 0x0217
138 #define SSPCON3_ADDR 0x0217
139 #define ODCONA_ADDR 0x028C
140 #define ODCONC_ADDR 0x028E
141 #define CCPR1_ADDR 0x0291
142 #define CCPR1L_ADDR 0x0291
143 #define CCPR1H_ADDR 0x0292
144 #define CCP1CON_ADDR 0x0293
145 #define CCP1CAP_ADDR 0x0294
146 #define CCPR2_ADDR 0x0295
147 #define CCPR2L_ADDR 0x0295
148 #define CCPR2H_ADDR 0x0296
149 #define CCP2CON_ADDR 0x0297
150 #define CCP2CAP_ADDR 0x0298
151 #define CCPTMRS_ADDR 0x029F
152 #define SLRCONA_ADDR 0x030C
153 #define SLRCONC_ADDR 0x030E
154 #define CCPR3_ADDR 0x0311
155 #define CCPR3L_ADDR 0x0311
156 #define CCPR3H_ADDR 0x0312
157 #define CCP3CON_ADDR 0x0313
158 #define CCP3CAP_ADDR 0x0314
159 #define CCPR4_ADDR 0x0315
160 #define CCPR4L_ADDR 0x0315
161 #define CCPR4H_ADDR 0x0316
162 #define CCP4CON_ADDR 0x0317
163 #define CCP4CAP_ADDR 0x0318
164 #define INLVLA_ADDR 0x038C
165 #define INLVLC_ADDR 0x038E
166 #define IOCAP_ADDR 0x0391
167 #define IOCAN_ADDR 0x0392
168 #define IOCAF_ADDR 0x0393
169 #define IOCCP_ADDR 0x0397
170 #define IOCCN_ADDR 0x0398
171 #define IOCCF_ADDR 0x0399
172 #define CLKRCON_ADDR 0x039A
173 #define MDCON_ADDR 0x039C
174 #define MDSRC_ADDR 0x039D
175 #define MDCARH_ADDR 0x039E
176 #define MDCARL_ADDR 0x039F
177 #define CCDNA_ADDR 0x040C
178 #define CCDNC_ADDR 0x040E
179 #define TMR3_ADDR 0x0411
180 #define TMR3L_ADDR 0x0411
181 #define TMR3H_ADDR 0x0412
182 #define T3CON_ADDR 0x0413
183 #define T3GCON_ADDR 0x0414
184 #define TMR4_ADDR 0x0415
185 #define PR4_ADDR 0x0416
186 #define T4CON_ADDR 0x0417
187 #define TMR5_ADDR 0x0418
188 #define TMR5L_ADDR 0x0418
189 #define TMR5H_ADDR 0x0419
190 #define T5CON_ADDR 0x041A
191 #define T5GCON_ADDR 0x041B
192 #define TMR6_ADDR 0x041C
193 #define PR6_ADDR 0x041D
194 #define T6CON_ADDR 0x041E
195 #define CCDCON_ADDR 0x041F
196 #define CCDPA_ADDR 0x048C
197 #define CCDPC_ADDR 0x048E
198 #define NCO1ACC_ADDR 0x0498
199 #define NCO1ACCL_ADDR 0x0498
200 #define NCO1ACCH_ADDR 0x0499
201 #define NCO1ACCU_ADDR 0x049A
202 #define NCO1INC_ADDR 0x049B
203 #define NCO1INCL_ADDR 0x049B
204 #define NCO1INCH_ADDR 0x049C
205 #define NCO1INCU_ADDR 0x049D
206 #define NCO1CON_ADDR 0x049E
207 #define NCO1CLK_ADDR 0x049F
208 #define PWM5DCL_ADDR 0x0617
209 #define PWM5DCH_ADDR 0x0618
210 #define PWM5CON_ADDR 0x0619
211 #define PWM5CON0_ADDR 0x0619
212 #define PWM6DCL_ADDR 0x061A
213 #define PWM6DCH_ADDR 0x061B
214 #define PWM6CON_ADDR 0x061C
215 #define PWM6CON0_ADDR 0x061C
216 #define PWMTMRS_ADDR 0x061F
217 #define CWG1CLKCON_ADDR 0x0691
218 #define CWG1DAT_ADDR 0x0692
219 #define CWG1DBR_ADDR 0x0693
220 #define CWG1DBF_ADDR 0x0694
221 #define CWG1CON0_ADDR 0x0695
222 #define CWG1CON1_ADDR 0x0696
223 #define CWG1AS0_ADDR 0x0697
224 #define CWG1AS1_ADDR 0x0698
225 #define CWG1STR_ADDR 0x0699
226 #define CWG2CLKCON_ADDR 0x0711
227 #define CWG2DAT_ADDR 0x0712
228 #define CWG2DBR_ADDR 0x0713
229 #define CWG2DBF_ADDR 0x0714
230 #define CWG2CON0_ADDR 0x0715
231 #define CWG2CON1_ADDR 0x0716
232 #define CWG2AS0_ADDR 0x0717
233 #define CWG2AS1_ADDR 0x0718
234 #define CWG2STR_ADDR 0x0719
235 #define NVMADR_ADDR 0x0891
236 #define NVMADRL_ADDR 0x0891
237 #define NVMADRH_ADDR 0x0892
238 #define NVMDAT_ADDR 0x0893
239 #define NVMDATL_ADDR 0x0893
240 #define NVMDATH_ADDR 0x0894
241 #define NVMCON1_ADDR 0x0895
242 #define NVMCON2_ADDR 0x0896
243 #define PCON0_ADDR 0x089B
244 #define PMD0_ADDR 0x0911
245 #define PMD1_ADDR 0x0912
246 #define PMD2_ADDR 0x0913
247 #define PMD3_ADDR 0x0914
248 #define PMD4_ADDR 0x0915
249 #define PMD5_ADDR 0x0916
250 #define CPUDOZE_ADDR 0x0918
251 #define OSCCON1_ADDR 0x0919
252 #define OSCCON2_ADDR 0x091A
253 #define OSCCON3_ADDR 0x091B
254 #define OSCSTAT1_ADDR 0x091C
255 #define OSCEN_ADDR 0x091D
256 #define OSCTUNE_ADDR 0x091E
257 #define OSCFRQ_ADDR 0x091F
258 #define PPSLOCK_ADDR 0x0E0F
259 #define INTPPS_ADDR 0x0E10
260 #define T0CKIPPS_ADDR 0x0E11
261 #define T1CKIPPS_ADDR 0x0E12
262 #define T1GPPS_ADDR 0x0E13
263 #define CCP1PPS_ADDR 0x0E14
264 #define CCP2PPS_ADDR 0x0E15
265 #define CCP3PPS_ADDR 0x0E16
266 #define CCP4PPS_ADDR 0x0E17
267 #define CWG1PPS_ADDR 0x0E18
268 #define CWG2PPS_ADDR 0x0E19
269 #define MDCIN1PPS_ADDR 0x0E1A
270 #define MDCIN2PPS_ADDR 0x0E1B
271 #define MDMINPPS_ADDR 0x0E1C
272 #define SSP1CLKPPS_ADDR 0x0E20
273 #define SSP1DATPPS_ADDR 0x0E21
274 #define SSP1SSPPS_ADDR 0x0E22
275 #define RXPPS_ADDR 0x0E24
276 #define TXPPS_ADDR 0x0E25
277 #define CLCIN0PPS_ADDR 0x0E28
278 #define CLCIN1PPS_ADDR 0x0E29
279 #define CLCIN2PPS_ADDR 0x0E2A
280 #define CLCIN3PPS_ADDR 0x0E2B
281 #define T3CKIPPS_ADDR 0x0E2C
282 #define T3GPPS_ADDR 0x0E2D
283 #define T5CKIPPS_ADDR 0x0E2E
284 #define T5GPPS_ADDR 0x0E2F
285 #define RA0PPS_ADDR 0x0E90
286 #define RA1PPS_ADDR 0x0E91
287 #define RA2PPS_ADDR 0x0E92
288 #define RA4PPS_ADDR 0x0E94
289 #define RA5PPS_ADDR 0x0E95
290 #define RC0PPS_ADDR 0x0EA0
291 #define RC1PPS_ADDR 0x0EA1
292 #define RC2PPS_ADDR 0x0EA2
293 #define RC3PPS_ADDR 0x0EA3
294 #define RC4PPS_ADDR 0x0EA4
295 #define RC5PPS_ADDR 0x0EA5
296 #define CLCDATA_ADDR 0x0F0F
297 #define CLC1CON_ADDR 0x0F10
298 #define CLC1POL_ADDR 0x0F11
299 #define CLC1SEL0_ADDR 0x0F12
300 #define CLC1SEL1_ADDR 0x0F13
301 #define CLC1SEL2_ADDR 0x0F14
302 #define CLC1SEL3_ADDR 0x0F15
303 #define CLC1GLS0_ADDR 0x0F16
304 #define CLC1GLS1_ADDR 0x0F17
305 #define CLC1GLS2_ADDR 0x0F18
306 #define CLC1GLS3_ADDR 0x0F19
307 #define CLC2CON_ADDR 0x0F1A
308 #define CLC2POL_ADDR 0x0F1B
309 #define CLC2SEL0_ADDR 0x0F1C
310 #define CLC2SEL1_ADDR 0x0F1D
311 #define CLC2SEL2_ADDR 0x0F1E
312 #define CLC2SEL3_ADDR 0x0F1F
313 #define CLC2GLS0_ADDR 0x0F20
314 #define CLC2GLS1_ADDR 0x0F21
315 #define CLC2GLS2_ADDR 0x0F22
316 #define CLC2GLS3_ADDR 0x0F23
317 #define CLC3CON_ADDR 0x0F24
318 #define CLC3POL_ADDR 0x0F25
319 #define CLC3SEL0_ADDR 0x0F26
320 #define CLC3SEL1_ADDR 0x0F27
321 #define CLC3SEL2_ADDR 0x0F28
322 #define CLC3SEL3_ADDR 0x0F29
323 #define CLC3GLS0_ADDR 0x0F2A
324 #define CLC3GLS1_ADDR 0x0F2B
325 #define CLC3GLS2_ADDR 0x0F2C
326 #define CLC3GLS3_ADDR 0x0F2D
327 #define CLC4CON_ADDR 0x0F2E
328 #define CLC4POL_ADDR 0x0F2F
329 #define CLC4SEL0_ADDR 0x0F30
330 #define CLC4SEL1_ADDR 0x0F31
331 #define CLC4SEL2_ADDR 0x0F32
332 #define CLC4SEL3_ADDR 0x0F33
333 #define CLC4GLS0_ADDR 0x0F34
334 #define CLC4GLS1_ADDR 0x0F35
335 #define CLC4GLS2_ADDR 0x0F36
336 #define CLC4GLS3_ADDR 0x0F37
337 #define STATUS_SHAD_ADDR 0x0FE4
338 #define WREG_SHAD_ADDR 0x0FE5
339 #define BSR_SHAD_ADDR 0x0FE6
340 #define PCLATH_SHAD_ADDR 0x0FE7
341 #define FSR0L_SHAD_ADDR 0x0FE8
342 #define FSR0H_SHAD_ADDR 0x0FE9
343 #define FSR1L_SHAD_ADDR 0x0FEA
344 #define FSR1H_SHAD_ADDR 0x0FEB
345 #define STKPTR_ADDR 0x0FED
346 #define TOSL_ADDR 0x0FEE
347 #define TOSH_ADDR 0x0FEF
349 #endif // #ifndef NO_ADDR_DEFINES
351 //==============================================================================
353 // Register Definitions
355 //==============================================================================
357 extern __at(0x0000) __sfr INDF0
;
358 extern __at(0x0001) __sfr INDF1
;
359 extern __at(0x0002) __sfr PCL
;
361 //==============================================================================
364 extern __at(0x0003) __sfr STATUS
;
378 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
386 //==============================================================================
388 extern __at(0x0004) __sfr FSR0
;
389 extern __at(0x0004) __sfr FSR0L
;
390 extern __at(0x0005) __sfr FSR0H
;
391 extern __at(0x0006) __sfr FSR1
;
392 extern __at(0x0006) __sfr FSR1L
;
393 extern __at(0x0007) __sfr FSR1H
;
395 //==============================================================================
398 extern __at(0x0008) __sfr BSR
;
421 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
429 //==============================================================================
431 extern __at(0x0009) __sfr WREG
;
432 extern __at(0x000A) __sfr PCLATH
;
434 //==============================================================================
437 extern __at(0x000B) __sfr INTCON
;
451 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
457 //==============================================================================
460 //==============================================================================
463 extern __at(0x000C) __sfr PORTA
;
486 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
495 //==============================================================================
498 //==============================================================================
501 extern __at(0x000E) __sfr PORTC
;
524 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
533 //==============================================================================
536 //==============================================================================
539 extern __at(0x0010) __sfr PIR0
;
553 extern __at(0x0010) volatile __PIR0bits_t PIR0bits
;
559 //==============================================================================
562 //==============================================================================
565 extern __at(0x0011) __sfr PIR1
;
576 unsigned TMR1GIF
: 1;
579 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
588 #define _TMR1GIF 0x80
590 //==============================================================================
593 //==============================================================================
596 extern __at(0x0012) __sfr PIR2
;
610 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
619 //==============================================================================
622 //==============================================================================
625 extern __at(0x0013) __sfr PIR3
;
634 unsigned TMR3GIF
: 1;
639 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
646 #define _TMR3GIF 0x20
650 //==============================================================================
653 //==============================================================================
656 extern __at(0x0014) __sfr PIR4
;
665 unsigned TMR5GIF
: 1;
670 extern __at(0x0014) volatile __PIR4bits_t PIR4bits
;
677 #define _TMR5GIF 0x20
681 //==============================================================================
684 //==============================================================================
687 extern __at(0x0015) __sfr TMR0L
;
701 extern __at(0x0015) volatile __TMR0Lbits_t TMR0Lbits
;
712 //==============================================================================
715 //==============================================================================
718 extern __at(0x0016) __sfr TMR0H
;
732 extern __at(0x0016) volatile __TMR0Hbits_t TMR0Hbits
;
743 //==============================================================================
746 //==============================================================================
749 extern __at(0x0017) __sfr T0CON0
;
755 unsigned T0OUTPS0
: 1;
756 unsigned T0OUTPS1
: 1;
757 unsigned T0OUTPS2
: 1;
758 unsigned T0OUTPS3
: 1;
759 unsigned T016BIT
: 1;
767 unsigned T0OUTPS
: 4;
772 extern __at(0x0017) volatile __T0CON0bits_t T0CON0bits
;
774 #define _T0OUTPS0 0x01
775 #define _T0OUTPS1 0x02
776 #define _T0OUTPS2 0x04
777 #define _T0OUTPS3 0x08
778 #define _T016BIT 0x10
782 //==============================================================================
785 //==============================================================================
788 extern __at(0x0018) __sfr T0CON1
;
794 unsigned T0CKPS0
: 1;
795 unsigned T0CKPS1
: 1;
796 unsigned T0CKPS2
: 1;
797 unsigned T0CKPS3
: 1;
798 unsigned T0ASYNC
: 1;
817 extern __at(0x0018) volatile __T0CON1bits_t T0CON1bits
;
819 #define _T0CKPS0 0x01
820 #define _T0CKPS1 0x02
821 #define _T0CKPS2 0x04
822 #define _T0CKPS3 0x08
823 #define _T0ASYNC 0x10
828 //==============================================================================
830 extern __at(0x0019) __sfr TMR1
;
831 extern __at(0x0019) __sfr TMR1L
;
832 extern __at(0x001A) __sfr TMR1H
;
834 //==============================================================================
837 extern __at(0x001B) __sfr T1CON
;
847 unsigned T1CKPS0
: 1;
848 unsigned T1CKPS1
: 1;
849 unsigned TMR1CS0
: 1;
850 unsigned TMR1CS1
: 1;
867 extern __at(0x001B) volatile __T1CONbits_t T1CONbits
;
872 #define _T1CKPS0 0x10
873 #define _T1CKPS1 0x20
874 #define _TMR1CS0 0x40
875 #define _TMR1CS1 0x80
877 //==============================================================================
880 //==============================================================================
883 extern __at(0x001C) __sfr T1GCON
;
892 unsigned T1GGO_NOT_DONE
: 1;
906 extern __at(0x001C) volatile __T1GCONbits_t T1GCONbits
;
911 #define _T1GGO_NOT_DONE 0x08
917 //==============================================================================
919 extern __at(0x001D) __sfr TMR2
;
920 extern __at(0x001E) __sfr PR2
;
922 //==============================================================================
925 extern __at(0x001F) __sfr T2CON
;
931 unsigned T2CKPS0
: 1;
932 unsigned T2CKPS1
: 1;
934 unsigned T2OUTPS0
: 1;
935 unsigned T2OUTPS1
: 1;
936 unsigned T2OUTPS2
: 1;
937 unsigned T2OUTPS3
: 1;
950 unsigned T2OUTPS
: 4;
955 extern __at(0x001F) volatile __T2CONbits_t T2CONbits
;
957 #define _T2CKPS0 0x01
958 #define _T2CKPS1 0x02
960 #define _T2OUTPS0 0x08
961 #define _T2OUTPS1 0x10
962 #define _T2OUTPS2 0x20
963 #define _T2OUTPS3 0x40
965 //==============================================================================
968 //==============================================================================
971 extern __at(0x008C) __sfr TRISA
;
985 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
993 //==============================================================================
996 //==============================================================================
999 extern __at(0x008E) __sfr TRISC
;
1005 unsigned TRISC0
: 1;
1006 unsigned TRISC1
: 1;
1007 unsigned TRISC2
: 1;
1008 unsigned TRISC3
: 1;
1009 unsigned TRISC4
: 1;
1010 unsigned TRISC5
: 1;
1022 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
1024 #define _TRISC0 0x01
1025 #define _TRISC1 0x02
1026 #define _TRISC2 0x04
1027 #define _TRISC3 0x08
1028 #define _TRISC4 0x10
1029 #define _TRISC5 0x20
1031 //==============================================================================
1034 //==============================================================================
1037 extern __at(0x0090) __sfr PIE0
;
1046 unsigned TMR0IE
: 1;
1051 extern __at(0x0090) volatile __PIE0bits_t PIE0bits
;
1055 #define _TMR0IE 0x20
1057 //==============================================================================
1060 //==============================================================================
1063 extern __at(0x0091) __sfr PIE1
;
1067 unsigned TMR1IE
: 1;
1068 unsigned TMR2IE
: 1;
1069 unsigned BCL1IE
: 1;
1070 unsigned SSP1IE
: 1;
1074 unsigned TMR1GIE
: 1;
1077 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
1079 #define _TMR1IE 0x01
1080 #define _TMR2IE 0x02
1081 #define _BCL1IE 0x04
1082 #define _SSP1IE 0x08
1086 #define _TMR1GIE 0x80
1088 //==============================================================================
1091 //==============================================================================
1094 extern __at(0x0092) __sfr PIE2
;
1098 unsigned NCO1IE
: 1;
1099 unsigned TMR4IE
: 1;
1105 unsigned TMR6IE
: 1;
1108 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
1110 #define _NCO1IE 0x01
1111 #define _TMR4IE 0x02
1115 #define _TMR6IE 0x80
1117 //==============================================================================
1120 //==============================================================================
1123 extern __at(0x0093) __sfr PIE3
;
1127 unsigned CLC1IE
: 1;
1128 unsigned CLC2IE
: 1;
1129 unsigned CLC3IE
: 1;
1130 unsigned CLC4IE
: 1;
1131 unsigned TMR3IE
: 1;
1132 unsigned TMR3GIE
: 1;
1137 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
1139 #define _CLC1IE 0x01
1140 #define _CLC2IE 0x02
1141 #define _CLC3IE 0x04
1142 #define _CLC4IE 0x08
1143 #define _TMR3IE 0x10
1144 #define _TMR3GIE 0x20
1148 //==============================================================================
1151 //==============================================================================
1154 extern __at(0x0094) __sfr PIE4
;
1158 unsigned CCP1IE
: 1;
1159 unsigned CCP2IE
: 1;
1160 unsigned CCP3IE
: 1;
1161 unsigned CCP4IE
: 1;
1162 unsigned TMR5IE
: 1;
1163 unsigned TMR5GIE
: 1;
1164 unsigned CWG1IE
: 1;
1165 unsigned CWG2IE
: 1;
1168 extern __at(0x0094) volatile __PIE4bits_t PIE4bits
;
1170 #define _CCP1IE 0x01
1171 #define _CCP2IE 0x02
1172 #define _CCP3IE 0x04
1173 #define _CCP4IE 0x08
1174 #define _TMR5IE 0x10
1175 #define _TMR5GIE 0x20
1176 #define _CWG1IE 0x40
1177 #define _CWG2IE 0x80
1179 //==============================================================================
1182 //==============================================================================
1185 extern __at(0x0097) __sfr WDTCON
;
1191 unsigned SWDTEN
: 1;
1192 unsigned WDTPS0
: 1;
1193 unsigned WDTPS1
: 1;
1194 unsigned WDTPS2
: 1;
1195 unsigned WDTPS3
: 1;
1196 unsigned WDTPS4
: 1;
1209 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1211 #define _SWDTEN 0x01
1212 #define _WDTPS0 0x02
1213 #define _WDTPS1 0x04
1214 #define _WDTPS2 0x08
1215 #define _WDTPS3 0x10
1216 #define _WDTPS4 0x20
1218 //==============================================================================
1220 extern __at(0x009B) __sfr ADRES
;
1221 extern __at(0x009B) __sfr ADRESL
;
1222 extern __at(0x009C) __sfr ADRESH
;
1224 //==============================================================================
1227 extern __at(0x009D) __sfr ADCON0
;
1234 unsigned GO_NOT_DONE
: 1;
1274 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1277 #define _GO_NOT_DONE 0x02
1287 //==============================================================================
1290 //==============================================================================
1293 extern __at(0x009E) __sfr ADCON1
;
1299 unsigned ADPREF0
: 1;
1300 unsigned ADPREF1
: 1;
1301 unsigned ADNREF
: 1;
1311 unsigned ADPREF
: 2;
1323 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1325 #define _ADPREF0 0x01
1326 #define _ADPREF1 0x02
1327 #define _ADNREF 0x04
1333 //==============================================================================
1336 //==============================================================================
1339 extern __at(0x009F) __sfr ADACT
;
1345 unsigned ADACT0
: 1;
1346 unsigned ADACT1
: 1;
1347 unsigned ADACT2
: 1;
1348 unsigned ADACT3
: 1;
1349 unsigned ADACT4
: 1;
1362 extern __at(0x009F) volatile __ADACTbits_t ADACTbits
;
1364 #define _ADACT0 0x01
1365 #define _ADACT1 0x02
1366 #define _ADACT2 0x04
1367 #define _ADACT3 0x08
1368 #define _ADACT4 0x10
1370 //==============================================================================
1373 //==============================================================================
1376 extern __at(0x010C) __sfr LATA
;
1390 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1398 //==============================================================================
1401 //==============================================================================
1404 extern __at(0x010E) __sfr LATC
;
1427 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1436 //==============================================================================
1439 //==============================================================================
1442 extern __at(0x0111) __sfr CM1CON0
;
1446 unsigned C1SYNC
: 1;
1456 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1458 #define _C1SYNC 0x01
1465 //==============================================================================
1468 //==============================================================================
1471 extern __at(0x0112) __sfr CM1CON1
;
1477 unsigned C1NCH0
: 1;
1478 unsigned C1NCH1
: 1;
1479 unsigned C1NCH2
: 1;
1480 unsigned C1PCH0
: 1;
1481 unsigned C1PCH1
: 1;
1482 unsigned C1PCH2
: 1;
1483 unsigned C1INTN
: 1;
1484 unsigned C1INTP
: 1;
1501 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1503 #define _C1NCH0 0x01
1504 #define _C1NCH1 0x02
1505 #define _C1NCH2 0x04
1506 #define _C1PCH0 0x08
1507 #define _C1PCH1 0x10
1508 #define _C1PCH2 0x20
1509 #define _C1INTN 0x40
1510 #define _C1INTP 0x80
1512 //==============================================================================
1515 //==============================================================================
1518 extern __at(0x0113) __sfr CM2CON0
;
1522 unsigned C2SYNC
: 1;
1532 extern __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits
;
1534 #define _C2SYNC 0x01
1541 //==============================================================================
1544 //==============================================================================
1547 extern __at(0x0114) __sfr CM2CON1
;
1553 unsigned C2NCH0
: 1;
1554 unsigned C2NCH1
: 1;
1555 unsigned C2NCH2
: 1;
1556 unsigned C2PCH0
: 1;
1557 unsigned C2PCH1
: 1;
1558 unsigned C2PCH2
: 1;
1559 unsigned C2INTN
: 1;
1560 unsigned C2INTP
: 1;
1577 extern __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits
;
1579 #define _C2NCH0 0x01
1580 #define _C2NCH1 0x02
1581 #define _C2NCH2 0x04
1582 #define _C2PCH0 0x08
1583 #define _C2PCH1 0x10
1584 #define _C2PCH2 0x20
1585 #define _C2INTN 0x40
1586 #define _C2INTP 0x80
1588 //==============================================================================
1591 //==============================================================================
1594 extern __at(0x0115) __sfr CMOUT
;
1598 unsigned MC1OUT
: 1;
1599 unsigned MC2OUT
: 1;
1608 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1610 #define _MC1OUT 0x01
1611 #define _MC2OUT 0x02
1613 //==============================================================================
1616 //==============================================================================
1619 extern __at(0x0116) __sfr BORCON
;
1623 unsigned BORRDY
: 1;
1630 unsigned SBOREN
: 1;
1633 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1635 #define _BORRDY 0x01
1636 #define _SBOREN 0x80
1638 //==============================================================================
1641 //==============================================================================
1644 extern __at(0x0117) __sfr FVRCON
;
1650 unsigned ADFVR0
: 1;
1651 unsigned ADFVR1
: 1;
1652 unsigned CDAFVR0
: 1;
1653 unsigned CDAFVR1
: 1;
1656 unsigned FVRRDY
: 1;
1669 unsigned CDAFVR
: 2;
1674 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1676 #define _ADFVR0 0x01
1677 #define _ADFVR1 0x02
1678 #define _CDAFVR0 0x04
1679 #define _CDAFVR1 0x08
1682 #define _FVRRDY 0x40
1685 //==============================================================================
1688 //==============================================================================
1691 extern __at(0x0118) __sfr DACCON0
;
1697 unsigned DAC1NSS
: 1;
1699 unsigned DAC1PSS0
: 1;
1700 unsigned DAC1PSS1
: 1;
1702 unsigned DAC1OE
: 1;
1704 unsigned DAC1EN
: 1;
1710 unsigned DAC1PSS
: 2;
1715 extern __at(0x0118) volatile __DACCON0bits_t DACCON0bits
;
1717 #define _DAC1NSS 0x01
1718 #define _DAC1PSS0 0x04
1719 #define _DAC1PSS1 0x08
1720 #define _DAC1OE 0x20
1721 #define _DAC1EN 0x80
1723 //==============================================================================
1726 //==============================================================================
1729 extern __at(0x0119) __sfr DACCON1
;
1735 unsigned DAC1R0
: 1;
1736 unsigned DAC1R1
: 1;
1737 unsigned DAC1R2
: 1;
1738 unsigned DAC1R3
: 1;
1739 unsigned DAC1R4
: 1;
1752 extern __at(0x0119) volatile __DACCON1bits_t DACCON1bits
;
1754 #define _DAC1R0 0x01
1755 #define _DAC1R1 0x02
1756 #define _DAC1R2 0x04
1757 #define _DAC1R3 0x08
1758 #define _DAC1R4 0x10
1760 //==============================================================================
1763 //==============================================================================
1766 extern __at(0x018C) __sfr ANSELA
;
1780 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1788 //==============================================================================
1791 //==============================================================================
1794 extern __at(0x018E) __sfr ANSELC
;
1817 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
1826 //==============================================================================
1828 extern __at(0x0199) __sfr RC1REG
;
1829 extern __at(0x0199) __sfr RCREG
;
1830 extern __at(0x0199) __sfr RCREG1
;
1831 extern __at(0x019A) __sfr TX1REG
;
1832 extern __at(0x019A) __sfr TXREG
;
1833 extern __at(0x019A) __sfr TXREG1
;
1834 extern __at(0x019B) __sfr SP1BRG
;
1835 extern __at(0x019B) __sfr SP1BRGL
;
1836 extern __at(0x019B) __sfr SPBRG
;
1837 extern __at(0x019B) __sfr SPBRG1
;
1838 extern __at(0x019B) __sfr SPBRGL
;
1839 extern __at(0x019C) __sfr SP1BRGH
;
1840 extern __at(0x019C) __sfr SPBRGH
;
1841 extern __at(0x019C) __sfr SPBRGH1
;
1843 //==============================================================================
1846 extern __at(0x019D) __sfr RC1STA
;
1860 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
1871 //==============================================================================
1874 //==============================================================================
1877 extern __at(0x019D) __sfr RCSTA
;
1891 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
1893 #define _RCSTA_RX9D 0x01
1894 #define _RCSTA_OERR 0x02
1895 #define _RCSTA_FERR 0x04
1896 #define _RCSTA_ADDEN 0x08
1897 #define _RCSTA_CREN 0x10
1898 #define _RCSTA_SREN 0x20
1899 #define _RCSTA_RX9 0x40
1900 #define _RCSTA_SPEN 0x80
1902 //==============================================================================
1905 //==============================================================================
1908 extern __at(0x019D) __sfr RCSTA1
;
1922 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
1924 #define _RCSTA1_RX9D 0x01
1925 #define _RCSTA1_OERR 0x02
1926 #define _RCSTA1_FERR 0x04
1927 #define _RCSTA1_ADDEN 0x08
1928 #define _RCSTA1_CREN 0x10
1929 #define _RCSTA1_SREN 0x20
1930 #define _RCSTA1_RX9 0x40
1931 #define _RCSTA1_SPEN 0x80
1933 //==============================================================================
1936 //==============================================================================
1939 extern __at(0x019E) __sfr TX1STA
;
1953 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
1964 //==============================================================================
1967 //==============================================================================
1970 extern __at(0x019E) __sfr TXSTA
;
1984 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
1986 #define _TXSTA_TX9D 0x01
1987 #define _TXSTA_TRMT 0x02
1988 #define _TXSTA_BRGH 0x04
1989 #define _TXSTA_SENDB 0x08
1990 #define _TXSTA_SYNC 0x10
1991 #define _TXSTA_TXEN 0x20
1992 #define _TXSTA_TX9 0x40
1993 #define _TXSTA_CSRC 0x80
1995 //==============================================================================
1998 //==============================================================================
2001 extern __at(0x019E) __sfr TXSTA1
;
2015 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
2017 #define _TXSTA1_TX9D 0x01
2018 #define _TXSTA1_TRMT 0x02
2019 #define _TXSTA1_BRGH 0x04
2020 #define _TXSTA1_SENDB 0x08
2021 #define _TXSTA1_SYNC 0x10
2022 #define _TXSTA1_TXEN 0x20
2023 #define _TXSTA1_TX9 0x40
2024 #define _TXSTA1_CSRC 0x80
2026 //==============================================================================
2029 //==============================================================================
2032 extern __at(0x019F) __sfr BAUD1CON
;
2043 unsigned ABDOVF
: 1;
2046 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
2053 #define _ABDOVF 0x80
2055 //==============================================================================
2058 //==============================================================================
2061 extern __at(0x019F) __sfr BAUDCON
;
2072 unsigned ABDOVF
: 1;
2075 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
2077 #define _BAUDCON_ABDEN 0x01
2078 #define _BAUDCON_WUE 0x02
2079 #define _BAUDCON_BRG16 0x08
2080 #define _BAUDCON_SCKP 0x10
2081 #define _BAUDCON_RCIDL 0x40
2082 #define _BAUDCON_ABDOVF 0x80
2084 //==============================================================================
2087 //==============================================================================
2090 extern __at(0x019F) __sfr BAUDCON1
;
2101 unsigned ABDOVF
: 1;
2104 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
2106 #define _BAUDCON1_ABDEN 0x01
2107 #define _BAUDCON1_WUE 0x02
2108 #define _BAUDCON1_BRG16 0x08
2109 #define _BAUDCON1_SCKP 0x10
2110 #define _BAUDCON1_RCIDL 0x40
2111 #define _BAUDCON1_ABDOVF 0x80
2113 //==============================================================================
2116 //==============================================================================
2119 extern __at(0x019F) __sfr BAUDCTL
;
2130 unsigned ABDOVF
: 1;
2133 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
2135 #define _BAUDCTL_ABDEN 0x01
2136 #define _BAUDCTL_WUE 0x02
2137 #define _BAUDCTL_BRG16 0x08
2138 #define _BAUDCTL_SCKP 0x10
2139 #define _BAUDCTL_RCIDL 0x40
2140 #define _BAUDCTL_ABDOVF 0x80
2142 //==============================================================================
2145 //==============================================================================
2148 extern __at(0x019F) __sfr BAUDCTL1
;
2159 unsigned ABDOVF
: 1;
2162 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
2164 #define _BAUDCTL1_ABDEN 0x01
2165 #define _BAUDCTL1_WUE 0x02
2166 #define _BAUDCTL1_BRG16 0x08
2167 #define _BAUDCTL1_SCKP 0x10
2168 #define _BAUDCTL1_RCIDL 0x40
2169 #define _BAUDCTL1_ABDOVF 0x80
2171 //==============================================================================
2174 //==============================================================================
2177 extern __at(0x020C) __sfr WPUA
;
2200 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
2209 //==============================================================================
2212 //==============================================================================
2215 extern __at(0x020E) __sfr WPUC
;
2238 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
2247 //==============================================================================
2250 //==============================================================================
2253 extern __at(0x0211) __sfr SSP1BUF
;
2259 unsigned SSP1BUF0
: 1;
2260 unsigned SSP1BUF1
: 1;
2261 unsigned SSP1BUF2
: 1;
2262 unsigned SSP1BUF3
: 1;
2263 unsigned SSP1BUF4
: 1;
2264 unsigned SSP1BUF5
: 1;
2265 unsigned SSP1BUF6
: 1;
2266 unsigned SSP1BUF7
: 1;
2282 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
2284 #define _SSP1BUF0 0x01
2286 #define _SSP1BUF1 0x02
2288 #define _SSP1BUF2 0x04
2290 #define _SSP1BUF3 0x08
2292 #define _SSP1BUF4 0x10
2294 #define _SSP1BUF5 0x20
2296 #define _SSP1BUF6 0x40
2298 #define _SSP1BUF7 0x80
2301 //==============================================================================
2304 //==============================================================================
2307 extern __at(0x0211) __sfr SSPBUF
;
2313 unsigned SSP1BUF0
: 1;
2314 unsigned SSP1BUF1
: 1;
2315 unsigned SSP1BUF2
: 1;
2316 unsigned SSP1BUF3
: 1;
2317 unsigned SSP1BUF4
: 1;
2318 unsigned SSP1BUF5
: 1;
2319 unsigned SSP1BUF6
: 1;
2320 unsigned SSP1BUF7
: 1;
2336 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
2338 #define _SSPBUF_SSP1BUF0 0x01
2339 #define _SSPBUF_BUF0 0x01
2340 #define _SSPBUF_SSP1BUF1 0x02
2341 #define _SSPBUF_BUF1 0x02
2342 #define _SSPBUF_SSP1BUF2 0x04
2343 #define _SSPBUF_BUF2 0x04
2344 #define _SSPBUF_SSP1BUF3 0x08
2345 #define _SSPBUF_BUF3 0x08
2346 #define _SSPBUF_SSP1BUF4 0x10
2347 #define _SSPBUF_BUF4 0x10
2348 #define _SSPBUF_SSP1BUF5 0x20
2349 #define _SSPBUF_BUF5 0x20
2350 #define _SSPBUF_SSP1BUF6 0x40
2351 #define _SSPBUF_BUF6 0x40
2352 #define _SSPBUF_SSP1BUF7 0x80
2353 #define _SSPBUF_BUF7 0x80
2355 //==============================================================================
2358 //==============================================================================
2361 extern __at(0x0212) __sfr SSP1ADD
;
2367 unsigned SSP1ADD0
: 1;
2368 unsigned SSP1ADD1
: 1;
2369 unsigned SSP1ADD2
: 1;
2370 unsigned SSP1ADD3
: 1;
2371 unsigned SSP1ADD4
: 1;
2372 unsigned SSP1ADD5
: 1;
2373 unsigned SSP1ADD6
: 1;
2374 unsigned SSP1ADD7
: 1;
2390 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
2392 #define _SSP1ADD0 0x01
2394 #define _SSP1ADD1 0x02
2396 #define _SSP1ADD2 0x04
2398 #define _SSP1ADD3 0x08
2400 #define _SSP1ADD4 0x10
2402 #define _SSP1ADD5 0x20
2404 #define _SSP1ADD6 0x40
2406 #define _SSP1ADD7 0x80
2409 //==============================================================================
2412 //==============================================================================
2415 extern __at(0x0212) __sfr SSPADD
;
2421 unsigned SSP1ADD0
: 1;
2422 unsigned SSP1ADD1
: 1;
2423 unsigned SSP1ADD2
: 1;
2424 unsigned SSP1ADD3
: 1;
2425 unsigned SSP1ADD4
: 1;
2426 unsigned SSP1ADD5
: 1;
2427 unsigned SSP1ADD6
: 1;
2428 unsigned SSP1ADD7
: 1;
2444 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
2446 #define _SSPADD_SSP1ADD0 0x01
2447 #define _SSPADD_ADD0 0x01
2448 #define _SSPADD_SSP1ADD1 0x02
2449 #define _SSPADD_ADD1 0x02
2450 #define _SSPADD_SSP1ADD2 0x04
2451 #define _SSPADD_ADD2 0x04
2452 #define _SSPADD_SSP1ADD3 0x08
2453 #define _SSPADD_ADD3 0x08
2454 #define _SSPADD_SSP1ADD4 0x10
2455 #define _SSPADD_ADD4 0x10
2456 #define _SSPADD_SSP1ADD5 0x20
2457 #define _SSPADD_ADD5 0x20
2458 #define _SSPADD_SSP1ADD6 0x40
2459 #define _SSPADD_ADD6 0x40
2460 #define _SSPADD_SSP1ADD7 0x80
2461 #define _SSPADD_ADD7 0x80
2463 //==============================================================================
2466 //==============================================================================
2469 extern __at(0x0213) __sfr SSP1MSK
;
2475 unsigned SSP1MSK0
: 1;
2476 unsigned SSP1MSK1
: 1;
2477 unsigned SSP1MSK2
: 1;
2478 unsigned SSP1MSK3
: 1;
2479 unsigned SSP1MSK4
: 1;
2480 unsigned SSP1MSK5
: 1;
2481 unsigned SSP1MSK6
: 1;
2482 unsigned SSP1MSK7
: 1;
2498 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
2500 #define _SSP1MSK0 0x01
2502 #define _SSP1MSK1 0x02
2504 #define _SSP1MSK2 0x04
2506 #define _SSP1MSK3 0x08
2508 #define _SSP1MSK4 0x10
2510 #define _SSP1MSK5 0x20
2512 #define _SSP1MSK6 0x40
2514 #define _SSP1MSK7 0x80
2517 //==============================================================================
2520 //==============================================================================
2523 extern __at(0x0213) __sfr SSPMSK
;
2529 unsigned SSP1MSK0
: 1;
2530 unsigned SSP1MSK1
: 1;
2531 unsigned SSP1MSK2
: 1;
2532 unsigned SSP1MSK3
: 1;
2533 unsigned SSP1MSK4
: 1;
2534 unsigned SSP1MSK5
: 1;
2535 unsigned SSP1MSK6
: 1;
2536 unsigned SSP1MSK7
: 1;
2552 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
2554 #define _SSPMSK_SSP1MSK0 0x01
2555 #define _SSPMSK_MSK0 0x01
2556 #define _SSPMSK_SSP1MSK1 0x02
2557 #define _SSPMSK_MSK1 0x02
2558 #define _SSPMSK_SSP1MSK2 0x04
2559 #define _SSPMSK_MSK2 0x04
2560 #define _SSPMSK_SSP1MSK3 0x08
2561 #define _SSPMSK_MSK3 0x08
2562 #define _SSPMSK_SSP1MSK4 0x10
2563 #define _SSPMSK_MSK4 0x10
2564 #define _SSPMSK_SSP1MSK5 0x20
2565 #define _SSPMSK_MSK5 0x20
2566 #define _SSPMSK_SSP1MSK6 0x40
2567 #define _SSPMSK_MSK6 0x40
2568 #define _SSPMSK_SSP1MSK7 0x80
2569 #define _SSPMSK_MSK7 0x80
2571 //==============================================================================
2574 //==============================================================================
2577 extern __at(0x0214) __sfr SSP1STAT
;
2583 unsigned R_NOT_W
: 1;
2586 unsigned D_NOT_A
: 1;
2591 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
2595 #define _R_NOT_W 0x04
2598 #define _D_NOT_A 0x20
2602 //==============================================================================
2605 //==============================================================================
2608 extern __at(0x0214) __sfr SSPSTAT
;
2614 unsigned R_NOT_W
: 1;
2617 unsigned D_NOT_A
: 1;
2622 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
2624 #define _SSPSTAT_BF 0x01
2625 #define _SSPSTAT_UA 0x02
2626 #define _SSPSTAT_R_NOT_W 0x04
2627 #define _SSPSTAT_S 0x08
2628 #define _SSPSTAT_P 0x10
2629 #define _SSPSTAT_D_NOT_A 0x20
2630 #define _SSPSTAT_CKE 0x40
2631 #define _SSPSTAT_SMP 0x80
2633 //==============================================================================
2636 //==============================================================================
2639 extern __at(0x0215) __sfr SSP1CON
;
2662 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
2673 //==============================================================================
2676 //==============================================================================
2679 extern __at(0x0215) __sfr SSP1CON1
;
2702 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
2704 #define _SSP1CON1_SSPM0 0x01
2705 #define _SSP1CON1_SSPM1 0x02
2706 #define _SSP1CON1_SSPM2 0x04
2707 #define _SSP1CON1_SSPM3 0x08
2708 #define _SSP1CON1_CKP 0x10
2709 #define _SSP1CON1_SSPEN 0x20
2710 #define _SSP1CON1_SSPOV 0x40
2711 #define _SSP1CON1_WCOL 0x80
2713 //==============================================================================
2716 //==============================================================================
2719 extern __at(0x0215) __sfr SSPCON
;
2742 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2744 #define _SSPCON_SSPM0 0x01
2745 #define _SSPCON_SSPM1 0x02
2746 #define _SSPCON_SSPM2 0x04
2747 #define _SSPCON_SSPM3 0x08
2748 #define _SSPCON_CKP 0x10
2749 #define _SSPCON_SSPEN 0x20
2750 #define _SSPCON_SSPOV 0x40
2751 #define _SSPCON_WCOL 0x80
2753 //==============================================================================
2756 //==============================================================================
2759 extern __at(0x0215) __sfr SSPCON1
;
2782 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2784 #define _SSPCON1_SSPM0 0x01
2785 #define _SSPCON1_SSPM1 0x02
2786 #define _SSPCON1_SSPM2 0x04
2787 #define _SSPCON1_SSPM3 0x08
2788 #define _SSPCON1_CKP 0x10
2789 #define _SSPCON1_SSPEN 0x20
2790 #define _SSPCON1_SSPOV 0x40
2791 #define _SSPCON1_WCOL 0x80
2793 //==============================================================================
2796 //==============================================================================
2799 extern __at(0x0216) __sfr SSP1CON2
;
2809 unsigned ACKSTAT
: 1;
2813 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
2821 #define _ACKSTAT 0x40
2824 //==============================================================================
2827 //==============================================================================
2830 extern __at(0x0216) __sfr SSPCON2
;
2840 unsigned ACKSTAT
: 1;
2844 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
2846 #define _SSPCON2_SEN 0x01
2847 #define _SSPCON2_RSEN 0x02
2848 #define _SSPCON2_PEN 0x04
2849 #define _SSPCON2_RCEN 0x08
2850 #define _SSPCON2_ACKEN 0x10
2851 #define _SSPCON2_ACKDT 0x20
2852 #define _SSPCON2_ACKSTAT 0x40
2853 #define _SSPCON2_GCEN 0x80
2855 //==============================================================================
2858 //==============================================================================
2861 extern __at(0x0217) __sfr SSP1CON3
;
2872 unsigned ACKTIM
: 1;
2875 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
2884 #define _ACKTIM 0x80
2886 //==============================================================================
2889 //==============================================================================
2892 extern __at(0x0217) __sfr SSPCON3
;
2903 unsigned ACKTIM
: 1;
2906 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
2908 #define _SSPCON3_DHEN 0x01
2909 #define _SSPCON3_AHEN 0x02
2910 #define _SSPCON3_SBCDE 0x04
2911 #define _SSPCON3_SDAHT 0x08
2912 #define _SSPCON3_BOEN 0x10
2913 #define _SSPCON3_SCIE 0x20
2914 #define _SSPCON3_PCIE 0x40
2915 #define _SSPCON3_ACKTIM 0x80
2917 //==============================================================================
2920 //==============================================================================
2923 extern __at(0x028C) __sfr ODCONA
;
2937 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
2945 //==============================================================================
2948 //==============================================================================
2951 extern __at(0x028E) __sfr ODCONC
;
2974 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
2983 //==============================================================================
2985 extern __at(0x0291) __sfr CCPR1
;
2986 extern __at(0x0291) __sfr CCPR1L
;
2987 extern __at(0x0292) __sfr CCPR1H
;
2989 //==============================================================================
2992 extern __at(0x0293) __sfr CCP1CON
;
2998 unsigned CCP1MODE0
: 1;
2999 unsigned CCP1MODE1
: 1;
3000 unsigned CCP1MODE2
: 1;
3001 unsigned CCP1MODE3
: 1;
3002 unsigned CCP1FMT
: 1;
3003 unsigned CCP1OUT
: 1;
3005 unsigned CCP1EN
: 1;
3010 unsigned CCP1MODE
: 4;
3015 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
3017 #define _CCP1MODE0 0x01
3018 #define _CCP1MODE1 0x02
3019 #define _CCP1MODE2 0x04
3020 #define _CCP1MODE3 0x08
3021 #define _CCP1FMT 0x10
3022 #define _CCP1OUT 0x20
3023 #define _CCP1EN 0x80
3025 //==============================================================================
3028 //==============================================================================
3031 extern __at(0x0294) __sfr CCP1CAP
;
3037 unsigned CCP1CTS0
: 1;
3038 unsigned CCP1CTS1
: 1;
3039 unsigned CCP1CTS2
: 1;
3040 unsigned CCP1CTS3
: 1;
3049 unsigned CCP1CTS
: 4;
3054 extern __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits
;
3056 #define _CCP1CTS0 0x01
3057 #define _CCP1CTS1 0x02
3058 #define _CCP1CTS2 0x04
3059 #define _CCP1CTS3 0x08
3061 //==============================================================================
3063 extern __at(0x0295) __sfr CCPR2
;
3064 extern __at(0x0295) __sfr CCPR2L
;
3065 extern __at(0x0296) __sfr CCPR2H
;
3067 //==============================================================================
3070 extern __at(0x0297) __sfr CCP2CON
;
3076 unsigned CCP2MODE0
: 1;
3077 unsigned CCP2MODE1
: 1;
3078 unsigned CCP2MODE2
: 1;
3079 unsigned CCP2MODE3
: 1;
3080 unsigned CCP2FMT
: 1;
3081 unsigned CCP2OUT
: 1;
3083 unsigned CCP2EN
: 1;
3088 unsigned CCP2MODE
: 4;
3093 extern __at(0x0297) volatile __CCP2CONbits_t CCP2CONbits
;
3095 #define _CCP2MODE0 0x01
3096 #define _CCP2MODE1 0x02
3097 #define _CCP2MODE2 0x04
3098 #define _CCP2MODE3 0x08
3099 #define _CCP2FMT 0x10
3100 #define _CCP2OUT 0x20
3101 #define _CCP2EN 0x80
3103 //==============================================================================
3106 //==============================================================================
3109 extern __at(0x0298) __sfr CCP2CAP
;
3115 unsigned CCP2CTS0
: 1;
3116 unsigned CCP2CTS1
: 1;
3117 unsigned CCP2CTS2
: 1;
3118 unsigned CCP2CTS3
: 1;
3127 unsigned CCP2CTS
: 4;
3132 extern __at(0x0298) volatile __CCP2CAPbits_t CCP2CAPbits
;
3134 #define _CCP2CTS0 0x01
3135 #define _CCP2CTS1 0x02
3136 #define _CCP2CTS2 0x04
3137 #define _CCP2CTS3 0x08
3139 //==============================================================================
3142 //==============================================================================
3145 extern __at(0x029F) __sfr CCPTMRS
;
3151 unsigned C1TSEL0
: 1;
3152 unsigned C1TSEL1
: 1;
3153 unsigned C2TSEL0
: 1;
3154 unsigned C2TSEL1
: 1;
3155 unsigned C3TSEL0
: 1;
3156 unsigned C3TSEL1
: 1;
3157 unsigned C4TSEL0
: 1;
3158 unsigned C4TSEL1
: 1;
3163 unsigned C1TSEL
: 2;
3170 unsigned C2TSEL
: 2;
3177 unsigned C3TSEL
: 2;
3184 unsigned C4TSEL
: 2;
3188 extern __at(0x029F) volatile __CCPTMRSbits_t CCPTMRSbits
;
3190 #define _C1TSEL0 0x01
3191 #define _C1TSEL1 0x02
3192 #define _C2TSEL0 0x04
3193 #define _C2TSEL1 0x08
3194 #define _C3TSEL0 0x10
3195 #define _C3TSEL1 0x20
3196 #define _C4TSEL0 0x40
3197 #define _C4TSEL1 0x80
3199 //==============================================================================
3202 //==============================================================================
3205 extern __at(0x030C) __sfr SLRCONA
;
3219 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
3227 //==============================================================================
3230 //==============================================================================
3233 extern __at(0x030E) __sfr SLRCONC
;
3256 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
3265 //==============================================================================
3267 extern __at(0x0311) __sfr CCPR3
;
3268 extern __at(0x0311) __sfr CCPR3L
;
3269 extern __at(0x0312) __sfr CCPR3H
;
3271 //==============================================================================
3274 extern __at(0x0313) __sfr CCP3CON
;
3280 unsigned CCP3MODE0
: 1;
3281 unsigned CCP3MODE1
: 1;
3282 unsigned CCP3MODE2
: 1;
3283 unsigned CCP3MODE3
: 1;
3284 unsigned CCP3FMT
: 1;
3285 unsigned CCP3OUT
: 1;
3287 unsigned CCP3EN
: 1;
3292 unsigned CCP3MODE
: 4;
3297 extern __at(0x0313) volatile __CCP3CONbits_t CCP3CONbits
;
3299 #define _CCP3MODE0 0x01
3300 #define _CCP3MODE1 0x02
3301 #define _CCP3MODE2 0x04
3302 #define _CCP3MODE3 0x08
3303 #define _CCP3FMT 0x10
3304 #define _CCP3OUT 0x20
3305 #define _CCP3EN 0x80
3307 //==============================================================================
3310 //==============================================================================
3313 extern __at(0x0314) __sfr CCP3CAP
;
3319 unsigned CCP3CTS0
: 1;
3320 unsigned CCP3CTS1
: 1;
3321 unsigned CCP3CTS2
: 1;
3322 unsigned CCP3CTS3
: 1;
3331 unsigned CCP3CTS
: 4;
3336 extern __at(0x0314) volatile __CCP3CAPbits_t CCP3CAPbits
;
3338 #define _CCP3CTS0 0x01
3339 #define _CCP3CTS1 0x02
3340 #define _CCP3CTS2 0x04
3341 #define _CCP3CTS3 0x08
3343 //==============================================================================
3345 extern __at(0x0315) __sfr CCPR4
;
3346 extern __at(0x0315) __sfr CCPR4L
;
3347 extern __at(0x0316) __sfr CCPR4H
;
3349 //==============================================================================
3352 extern __at(0x0317) __sfr CCP4CON
;
3358 unsigned CCP4MODE0
: 1;
3359 unsigned CCP4MODE1
: 1;
3360 unsigned CCP4MODE2
: 1;
3361 unsigned CCP4MODE3
: 1;
3362 unsigned CCP4FMT
: 1;
3363 unsigned CCP4OUT
: 1;
3365 unsigned CCP4EN
: 1;
3370 unsigned CCP4MODE
: 4;
3375 extern __at(0x0317) volatile __CCP4CONbits_t CCP4CONbits
;
3377 #define _CCP4MODE0 0x01
3378 #define _CCP4MODE1 0x02
3379 #define _CCP4MODE2 0x04
3380 #define _CCP4MODE3 0x08
3381 #define _CCP4FMT 0x10
3382 #define _CCP4OUT 0x20
3383 #define _CCP4EN 0x80
3385 //==============================================================================
3388 //==============================================================================
3391 extern __at(0x0318) __sfr CCP4CAP
;
3397 unsigned CCP4CTS0
: 1;
3398 unsigned CCP4CTS1
: 1;
3399 unsigned CCP4CTS2
: 1;
3400 unsigned CCP4CTS3
: 1;
3409 unsigned CCP4CTS
: 4;
3414 extern __at(0x0318) volatile __CCP4CAPbits_t CCP4CAPbits
;
3416 #define _CCP4CTS0 0x01
3417 #define _CCP4CTS1 0x02
3418 #define _CCP4CTS2 0x04
3419 #define _CCP4CTS3 0x08
3421 //==============================================================================
3424 //==============================================================================
3427 extern __at(0x038C) __sfr INLVLA
;
3433 unsigned INLVLA0
: 1;
3434 unsigned INLVLA1
: 1;
3435 unsigned INLVLA2
: 1;
3436 unsigned INLVLA3
: 1;
3437 unsigned INLVLA4
: 1;
3438 unsigned INLVLA5
: 1;
3445 unsigned INLVLA
: 6;
3450 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
3452 #define _INLVLA0 0x01
3453 #define _INLVLA1 0x02
3454 #define _INLVLA2 0x04
3455 #define _INLVLA3 0x08
3456 #define _INLVLA4 0x10
3457 #define _INLVLA5 0x20
3459 //==============================================================================
3462 //==============================================================================
3465 extern __at(0x038E) __sfr INLVLC
;
3471 unsigned INLVLC0
: 1;
3472 unsigned INLVLC1
: 1;
3473 unsigned INLVLC2
: 1;
3474 unsigned INLVLC3
: 1;
3475 unsigned INLVLC4
: 1;
3476 unsigned INLVLC5
: 1;
3483 unsigned INLVLC
: 6;
3488 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
3490 #define _INLVLC0 0x01
3491 #define _INLVLC1 0x02
3492 #define _INLVLC2 0x04
3493 #define _INLVLC3 0x08
3494 #define _INLVLC4 0x10
3495 #define _INLVLC5 0x20
3497 //==============================================================================
3500 //==============================================================================
3503 extern __at(0x0391) __sfr IOCAP
;
3509 unsigned IOCAP0
: 1;
3510 unsigned IOCAP1
: 1;
3511 unsigned IOCAP2
: 1;
3512 unsigned IOCAP3
: 1;
3513 unsigned IOCAP4
: 1;
3514 unsigned IOCAP5
: 1;
3526 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
3528 #define _IOCAP0 0x01
3529 #define _IOCAP1 0x02
3530 #define _IOCAP2 0x04
3531 #define _IOCAP3 0x08
3532 #define _IOCAP4 0x10
3533 #define _IOCAP5 0x20
3535 //==============================================================================
3538 //==============================================================================
3541 extern __at(0x0392) __sfr IOCAN
;
3547 unsigned IOCAN0
: 1;
3548 unsigned IOCAN1
: 1;
3549 unsigned IOCAN2
: 1;
3550 unsigned IOCAN3
: 1;
3551 unsigned IOCAN4
: 1;
3552 unsigned IOCAN5
: 1;
3564 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
3566 #define _IOCAN0 0x01
3567 #define _IOCAN1 0x02
3568 #define _IOCAN2 0x04
3569 #define _IOCAN3 0x08
3570 #define _IOCAN4 0x10
3571 #define _IOCAN5 0x20
3573 //==============================================================================
3576 //==============================================================================
3579 extern __at(0x0393) __sfr IOCAF
;
3585 unsigned IOCAF0
: 1;
3586 unsigned IOCAF1
: 1;
3587 unsigned IOCAF2
: 1;
3588 unsigned IOCAF3
: 1;
3589 unsigned IOCAF4
: 1;
3590 unsigned IOCAF5
: 1;
3602 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
3604 #define _IOCAF0 0x01
3605 #define _IOCAF1 0x02
3606 #define _IOCAF2 0x04
3607 #define _IOCAF3 0x08
3608 #define _IOCAF4 0x10
3609 #define _IOCAF5 0x20
3611 //==============================================================================
3614 //==============================================================================
3617 extern __at(0x0397) __sfr IOCCP
;
3623 unsigned IOCCP0
: 1;
3624 unsigned IOCCP1
: 1;
3625 unsigned IOCCP2
: 1;
3626 unsigned IOCCP3
: 1;
3627 unsigned IOCCP4
: 1;
3628 unsigned IOCCP5
: 1;
3640 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
3642 #define _IOCCP0 0x01
3643 #define _IOCCP1 0x02
3644 #define _IOCCP2 0x04
3645 #define _IOCCP3 0x08
3646 #define _IOCCP4 0x10
3647 #define _IOCCP5 0x20
3649 //==============================================================================
3652 //==============================================================================
3655 extern __at(0x0398) __sfr IOCCN
;
3661 unsigned IOCCN0
: 1;
3662 unsigned IOCCN1
: 1;
3663 unsigned IOCCN2
: 1;
3664 unsigned IOCCN3
: 1;
3665 unsigned IOCCN4
: 1;
3666 unsigned IOCCN5
: 1;
3678 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
3680 #define _IOCCN0 0x01
3681 #define _IOCCN1 0x02
3682 #define _IOCCN2 0x04
3683 #define _IOCCN3 0x08
3684 #define _IOCCN4 0x10
3685 #define _IOCCN5 0x20
3687 //==============================================================================
3690 //==============================================================================
3693 extern __at(0x0399) __sfr IOCCF
;
3699 unsigned IOCCF0
: 1;
3700 unsigned IOCCF1
: 1;
3701 unsigned IOCCF2
: 1;
3702 unsigned IOCCF3
: 1;
3703 unsigned IOCCF4
: 1;
3704 unsigned IOCCF5
: 1;
3716 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
3718 #define _IOCCF0 0x01
3719 #define _IOCCF1 0x02
3720 #define _IOCCF2 0x04
3721 #define _IOCCF3 0x08
3722 #define _IOCCF4 0x10
3723 #define _IOCCF5 0x20
3725 //==============================================================================
3728 //==============================================================================
3731 extern __at(0x039A) __sfr CLKRCON
;
3737 unsigned CLKRDIV0
: 1;
3738 unsigned CLKRDIV1
: 1;
3739 unsigned CLKRDIV2
: 1;
3740 unsigned CLKRDC0
: 1;
3741 unsigned CLKRDC1
: 1;
3744 unsigned CLKREN
: 1;
3749 unsigned CLKRDIV
: 3;
3756 unsigned CLKRDC
: 2;
3761 extern __at(0x039A) volatile __CLKRCONbits_t CLKRCONbits
;
3763 #define _CLKRDIV0 0x01
3764 #define _CLKRDIV1 0x02
3765 #define _CLKRDIV2 0x04
3766 #define _CLKRDC0 0x08
3767 #define _CLKRDC1 0x10
3768 #define _CLKREN 0x80
3770 //==============================================================================
3773 //==============================================================================
3776 extern __at(0x039C) __sfr MDCON
;
3784 unsigned MDOPOL
: 1;
3790 extern __at(0x039C) volatile __MDCONbits_t MDCONbits
;
3794 #define _MDOPOL 0x10
3797 //==============================================================================
3800 //==============================================================================
3803 extern __at(0x039D) __sfr MDSRC
;
3826 extern __at(0x039D) volatile __MDSRCbits_t MDSRCbits
;
3833 //==============================================================================
3836 //==============================================================================
3839 extern __at(0x039E) __sfr MDCARH
;
3850 unsigned MDCHSYNC
: 1;
3851 unsigned MDCHPOL
: 1;
3862 extern __at(0x039E) volatile __MDCARHbits_t MDCARHbits
;
3868 #define _MDCHSYNC 0x20
3869 #define _MDCHPOL 0x40
3871 //==============================================================================
3874 //==============================================================================
3877 extern __at(0x039F) __sfr MDCARL
;
3888 unsigned MDCLSYNC
: 1;
3889 unsigned MDCLPOL
: 1;
3900 extern __at(0x039F) volatile __MDCARLbits_t MDCARLbits
;
3906 #define _MDCLSYNC 0x20
3907 #define _MDCLPOL 0x40
3909 //==============================================================================
3912 //==============================================================================
3915 extern __at(0x040C) __sfr CCDNA
;
3919 unsigned CCDNA0
: 1;
3920 unsigned CCDNA1
: 1;
3921 unsigned CCDNA2
: 1;
3923 unsigned CCDNA4
: 1;
3924 unsigned CCDNA5
: 1;
3929 extern __at(0x040C) volatile __CCDNAbits_t CCDNAbits
;
3931 #define _CCDNA0 0x01
3932 #define _CCDNA1 0x02
3933 #define _CCDNA2 0x04
3934 #define _CCDNA4 0x10
3935 #define _CCDNA5 0x20
3937 //==============================================================================
3940 //==============================================================================
3943 extern __at(0x040E) __sfr CCDNC
;
3949 unsigned CCDNC0
: 1;
3950 unsigned CCDNC1
: 1;
3951 unsigned CCDNC2
: 1;
3952 unsigned CCDNC3
: 1;
3953 unsigned CCDNC4
: 1;
3954 unsigned CCDNC5
: 1;
3966 extern __at(0x040E) volatile __CCDNCbits_t CCDNCbits
;
3968 #define _CCDNC0 0x01
3969 #define _CCDNC1 0x02
3970 #define _CCDNC2 0x04
3971 #define _CCDNC3 0x08
3972 #define _CCDNC4 0x10
3973 #define _CCDNC5 0x20
3975 //==============================================================================
3977 extern __at(0x0411) __sfr TMR3
;
3978 extern __at(0x0411) __sfr TMR3L
;
3979 extern __at(0x0412) __sfr TMR3H
;
3981 //==============================================================================
3984 extern __at(0x0413) __sfr T3CON
;
3990 unsigned TMR3ON
: 1;
3992 unsigned T3SYNC
: 1;
3993 unsigned T3SOSC
: 1;
3994 unsigned T3CKPS0
: 1;
3995 unsigned T3CKPS1
: 1;
3996 unsigned TMR3CS0
: 1;
3997 unsigned TMR3CS1
: 1;
4003 unsigned T3CKPS
: 2;
4010 unsigned TMR3CS
: 2;
4014 extern __at(0x0413) volatile __T3CONbits_t T3CONbits
;
4016 #define _TMR3ON 0x01
4017 #define _T3SYNC 0x04
4018 #define _T3SOSC 0x08
4019 #define _T3CKPS0 0x10
4020 #define _T3CKPS1 0x20
4021 #define _TMR3CS0 0x40
4022 #define _TMR3CS1 0x80
4024 //==============================================================================
4027 //==============================================================================
4030 extern __at(0x0414) __sfr T3GCON
;
4036 unsigned T3GSS0
: 1;
4037 unsigned T3GSS1
: 1;
4038 unsigned T3GVAL
: 1;
4039 unsigned T3GGO_NOT_DONE
: 1;
4040 unsigned T3GSPM
: 1;
4042 unsigned T3GPOL
: 1;
4043 unsigned TMR3GE
: 1;
4053 extern __at(0x0414) volatile __T3GCONbits_t T3GCONbits
;
4055 #define _T3GSS0 0x01
4056 #define _T3GSS1 0x02
4057 #define _T3GVAL 0x04
4058 #define _T3GGO_NOT_DONE 0x08
4059 #define _T3GSPM 0x10
4061 #define _T3GPOL 0x40
4062 #define _TMR3GE 0x80
4064 //==============================================================================
4066 extern __at(0x0415) __sfr TMR4
;
4067 extern __at(0x0416) __sfr PR4
;
4069 //==============================================================================
4072 extern __at(0x0417) __sfr T4CON
;
4078 unsigned T4CKPS0
: 1;
4079 unsigned T4CKPS1
: 1;
4080 unsigned TMR4ON
: 1;
4081 unsigned T4OUTPS0
: 1;
4082 unsigned T4OUTPS1
: 1;
4083 unsigned T4OUTPS2
: 1;
4084 unsigned T4OUTPS3
: 1;
4090 unsigned T4CKPS
: 2;
4097 unsigned T4OUTPS
: 4;
4102 extern __at(0x0417) volatile __T4CONbits_t T4CONbits
;
4104 #define _T4CKPS0 0x01
4105 #define _T4CKPS1 0x02
4106 #define _TMR4ON 0x04
4107 #define _T4OUTPS0 0x08
4108 #define _T4OUTPS1 0x10
4109 #define _T4OUTPS2 0x20
4110 #define _T4OUTPS3 0x40
4112 //==============================================================================
4114 extern __at(0x0418) __sfr TMR5
;
4115 extern __at(0x0418) __sfr TMR5L
;
4116 extern __at(0x0419) __sfr TMR5H
;
4118 //==============================================================================
4121 extern __at(0x041A) __sfr T5CON
;
4127 unsigned TMR5ON
: 1;
4129 unsigned T5SYNC
: 1;
4130 unsigned T5SOSC
: 1;
4131 unsigned T5CKPS0
: 1;
4132 unsigned T5CKPS1
: 1;
4133 unsigned TMR5CS0
: 1;
4134 unsigned TMR5CS1
: 1;
4140 unsigned T5CKPS
: 2;
4147 unsigned TMR5CS
: 2;
4151 extern __at(0x041A) volatile __T5CONbits_t T5CONbits
;
4153 #define _TMR5ON 0x01
4154 #define _T5SYNC 0x04
4155 #define _T5SOSC 0x08
4156 #define _T5CKPS0 0x10
4157 #define _T5CKPS1 0x20
4158 #define _TMR5CS0 0x40
4159 #define _TMR5CS1 0x80
4161 //==============================================================================
4164 //==============================================================================
4167 extern __at(0x041B) __sfr T5GCON
;
4173 unsigned T5GSS0
: 1;
4174 unsigned T5GSS1
: 1;
4175 unsigned T5GVAL
: 1;
4176 unsigned T5GGO_NOT_DONE
: 1;
4177 unsigned T5GSPM
: 1;
4179 unsigned T5GPOL
: 1;
4180 unsigned TMR5GE
: 1;
4190 extern __at(0x041B) volatile __T5GCONbits_t T5GCONbits
;
4192 #define _T5GSS0 0x01
4193 #define _T5GSS1 0x02
4194 #define _T5GVAL 0x04
4195 #define _T5GGO_NOT_DONE 0x08
4196 #define _T5GSPM 0x10
4198 #define _T5GPOL 0x40
4199 #define _TMR5GE 0x80
4201 //==============================================================================
4203 extern __at(0x041C) __sfr TMR6
;
4204 extern __at(0x041D) __sfr PR6
;
4206 //==============================================================================
4209 extern __at(0x041E) __sfr T6CON
;
4215 unsigned T6CKPS0
: 1;
4216 unsigned T6CKPS1
: 1;
4217 unsigned TMR6ON
: 1;
4218 unsigned T6OUTPS0
: 1;
4219 unsigned T6OUTPS1
: 1;
4220 unsigned T6OUTPS2
: 1;
4221 unsigned T6OUTPS3
: 1;
4227 unsigned T6CKPS
: 2;
4234 unsigned T6OUTPS
: 4;
4239 extern __at(0x041E) volatile __T6CONbits_t T6CONbits
;
4241 #define _T6CKPS0 0x01
4242 #define _T6CKPS1 0x02
4243 #define _TMR6ON 0x04
4244 #define _T6OUTPS0 0x08
4245 #define _T6OUTPS1 0x10
4246 #define _T6OUTPS2 0x20
4247 #define _T6OUTPS3 0x40
4249 //==============================================================================
4252 //==============================================================================
4255 extern __at(0x041F) __sfr CCDCON
;
4278 extern __at(0x041F) volatile __CCDCONbits_t CCDCONbits
;
4284 //==============================================================================
4287 //==============================================================================
4290 extern __at(0x048C) __sfr CCDPA
;
4294 unsigned CCDPA0
: 1;
4295 unsigned CCDPA1
: 1;
4296 unsigned CCDPA2
: 1;
4298 unsigned CCDPA4
: 1;
4299 unsigned CCDPA5
: 1;
4304 extern __at(0x048C) volatile __CCDPAbits_t CCDPAbits
;
4306 #define _CCDPA0 0x01
4307 #define _CCDPA1 0x02
4308 #define _CCDPA2 0x04
4309 #define _CCDPA4 0x10
4310 #define _CCDPA5 0x20
4312 //==============================================================================
4315 //==============================================================================
4318 extern __at(0x048E) __sfr CCDPC
;
4324 unsigned CCDPC0
: 1;
4325 unsigned CCDPC1
: 1;
4326 unsigned CCDPC2
: 1;
4327 unsigned CCDPC3
: 1;
4328 unsigned CCDPC4
: 1;
4329 unsigned CCDPC5
: 1;
4341 extern __at(0x048E) volatile __CCDPCbits_t CCDPCbits
;
4343 #define _CCDPC0 0x01
4344 #define _CCDPC1 0x02
4345 #define _CCDPC2 0x04
4346 #define _CCDPC3 0x08
4347 #define _CCDPC4 0x10
4348 #define _CCDPC5 0x20
4350 //==============================================================================
4352 extern __at(0x0498) __sfr NCO1ACC
;
4353 extern __at(0x0498) __sfr NCO1ACCL
;
4354 extern __at(0x0499) __sfr NCO1ACCH
;
4355 extern __at(0x049A) __sfr NCO1ACCU
;
4356 extern __at(0x049B) __sfr NCO1INC
;
4357 extern __at(0x049B) __sfr NCO1INCL
;
4358 extern __at(0x049C) __sfr NCO1INCH
;
4359 extern __at(0x049D) __sfr NCO1INCU
;
4361 //==============================================================================
4364 extern __at(0x049E) __sfr NCO1CON
;
4378 extern __at(0x049E) volatile __NCO1CONbits_t NCO1CONbits
;
4385 //==============================================================================
4387 extern __at(0x049F) __sfr NCO1CLK
;
4389 //==============================================================================
4392 extern __at(0x0617) __sfr PWM5DCL
;
4404 unsigned PWM5DCL0
: 1;
4405 unsigned PWM5DCL1
: 1;
4411 unsigned PWM5DCL
: 2;
4415 extern __at(0x0617) volatile __PWM5DCLbits_t PWM5DCLbits
;
4417 #define _PWM5DCL0 0x40
4418 #define _PWM5DCL1 0x80
4420 //==============================================================================
4423 //==============================================================================
4426 extern __at(0x0618) __sfr PWM5DCH
;
4430 unsigned PWM5DCH0
: 1;
4431 unsigned PWM5DCH1
: 1;
4432 unsigned PWM5DCH2
: 1;
4433 unsigned PWM5DCH3
: 1;
4434 unsigned PWM5DCH4
: 1;
4435 unsigned PWM5DCH5
: 1;
4436 unsigned PWM5DCH6
: 1;
4437 unsigned PWM5DCH7
: 1;
4440 extern __at(0x0618) volatile __PWM5DCHbits_t PWM5DCHbits
;
4442 #define _PWM5DCH0 0x01
4443 #define _PWM5DCH1 0x02
4444 #define _PWM5DCH2 0x04
4445 #define _PWM5DCH3 0x08
4446 #define _PWM5DCH4 0x10
4447 #define _PWM5DCH5 0x20
4448 #define _PWM5DCH6 0x40
4449 #define _PWM5DCH7 0x80
4451 //==============================================================================
4454 //==============================================================================
4457 extern __at(0x0619) __sfr PWM5CON
;
4465 unsigned PWM5POL
: 1;
4466 unsigned PWM5OUT
: 1;
4468 unsigned PWM5EN
: 1;
4471 extern __at(0x0619) volatile __PWM5CONbits_t PWM5CONbits
;
4473 #define _PWM5POL 0x10
4474 #define _PWM5OUT 0x20
4475 #define _PWM5EN 0x80
4477 //==============================================================================
4480 //==============================================================================
4483 extern __at(0x0619) __sfr PWM5CON0
;
4491 unsigned PWM5POL
: 1;
4492 unsigned PWM5OUT
: 1;
4494 unsigned PWM5EN
: 1;
4497 extern __at(0x0619) volatile __PWM5CON0bits_t PWM5CON0bits
;
4499 #define _PWM5CON0_PWM5POL 0x10
4500 #define _PWM5CON0_PWM5OUT 0x20
4501 #define _PWM5CON0_PWM5EN 0x80
4503 //==============================================================================
4506 //==============================================================================
4509 extern __at(0x061A) __sfr PWM6DCL
;
4521 unsigned PWM6DCL0
: 1;
4522 unsigned PWM6DCL1
: 1;
4528 unsigned PWM6DCL
: 2;
4532 extern __at(0x061A) volatile __PWM6DCLbits_t PWM6DCLbits
;
4534 #define _PWM6DCL0 0x40
4535 #define _PWM6DCL1 0x80
4537 //==============================================================================
4540 //==============================================================================
4543 extern __at(0x061B) __sfr PWM6DCH
;
4547 unsigned PWM6DCH0
: 1;
4548 unsigned PWM6DCH1
: 1;
4549 unsigned PWM6DCH2
: 1;
4550 unsigned PWM6DCH3
: 1;
4551 unsigned PWM6DCH4
: 1;
4552 unsigned PWM6DCH5
: 1;
4553 unsigned PWM6DCH6
: 1;
4554 unsigned PWM6DCH7
: 1;
4557 extern __at(0x061B) volatile __PWM6DCHbits_t PWM6DCHbits
;
4559 #define _PWM6DCH0 0x01
4560 #define _PWM6DCH1 0x02
4561 #define _PWM6DCH2 0x04
4562 #define _PWM6DCH3 0x08
4563 #define _PWM6DCH4 0x10
4564 #define _PWM6DCH5 0x20
4565 #define _PWM6DCH6 0x40
4566 #define _PWM6DCH7 0x80
4568 //==============================================================================
4571 //==============================================================================
4574 extern __at(0x061C) __sfr PWM6CON
;
4582 unsigned PWM6POL
: 1;
4583 unsigned PWM6OUT
: 1;
4585 unsigned PWM6EN
: 1;
4588 extern __at(0x061C) volatile __PWM6CONbits_t PWM6CONbits
;
4590 #define _PWM6POL 0x10
4591 #define _PWM6OUT 0x20
4592 #define _PWM6EN 0x80
4594 //==============================================================================
4597 //==============================================================================
4600 extern __at(0x061C) __sfr PWM6CON0
;
4608 unsigned PWM6POL
: 1;
4609 unsigned PWM6OUT
: 1;
4611 unsigned PWM6EN
: 1;
4614 extern __at(0x061C) volatile __PWM6CON0bits_t PWM6CON0bits
;
4616 #define _PWM6CON0_PWM6POL 0x10
4617 #define _PWM6CON0_PWM6OUT 0x20
4618 #define _PWM6CON0_PWM6EN 0x80
4620 //==============================================================================
4623 //==============================================================================
4626 extern __at(0x061F) __sfr PWMTMRS
;
4632 unsigned P5TSEL0
: 1;
4633 unsigned P5TSEL1
: 1;
4634 unsigned P6TSEL0
: 1;
4635 unsigned P6TSEL1
: 1;
4644 unsigned P5TSEL
: 2;
4651 unsigned P6TSEL
: 2;
4656 extern __at(0x061F) volatile __PWMTMRSbits_t PWMTMRSbits
;
4658 #define _P5TSEL0 0x01
4659 #define _P5TSEL1 0x02
4660 #define _P6TSEL0 0x04
4661 #define _P6TSEL1 0x08
4663 //==============================================================================
4666 //==============================================================================
4669 extern __at(0x0691) __sfr CWG1CLKCON
;
4687 unsigned CWG1CS
: 1;
4696 } __CWG1CLKCONbits_t
;
4698 extern __at(0x0691) volatile __CWG1CLKCONbits_t CWG1CLKCONbits
;
4701 #define _CWG1CS 0x01
4703 //==============================================================================
4706 //==============================================================================
4709 extern __at(0x0692) __sfr CWG1DAT
;
4715 unsigned CWG1DAT0
: 1;
4716 unsigned CWG1DAT1
: 1;
4717 unsigned CWG1DAT2
: 1;
4718 unsigned CWG1DAT3
: 1;
4727 unsigned CWG1DAT
: 4;
4732 extern __at(0x0692) volatile __CWG1DATbits_t CWG1DATbits
;
4734 #define _CWG1DAT0 0x01
4735 #define _CWG1DAT1 0x02
4736 #define _CWG1DAT2 0x04
4737 #define _CWG1DAT3 0x08
4739 //==============================================================================
4742 //==============================================================================
4745 extern __at(0x0693) __sfr CWG1DBR
;
4763 unsigned CWG1DBR0
: 1;
4764 unsigned CWG1DBR1
: 1;
4765 unsigned CWG1DBR2
: 1;
4766 unsigned CWG1DBR3
: 1;
4767 unsigned CWG1DBR4
: 1;
4768 unsigned CWG1DBR5
: 1;
4781 unsigned CWG1DBR
: 6;
4786 extern __at(0x0693) volatile __CWG1DBRbits_t CWG1DBRbits
;
4789 #define _CWG1DBR0 0x01
4791 #define _CWG1DBR1 0x02
4793 #define _CWG1DBR2 0x04
4795 #define _CWG1DBR3 0x08
4797 #define _CWG1DBR4 0x10
4799 #define _CWG1DBR5 0x20
4801 //==============================================================================
4804 //==============================================================================
4807 extern __at(0x0694) __sfr CWG1DBF
;
4825 unsigned CWG1DBF0
: 1;
4826 unsigned CWG1DBF1
: 1;
4827 unsigned CWG1DBF2
: 1;
4828 unsigned CWG1DBF3
: 1;
4829 unsigned CWG1DBF4
: 1;
4830 unsigned CWG1DBF5
: 1;
4843 unsigned CWG1DBF
: 6;
4848 extern __at(0x0694) volatile __CWG1DBFbits_t CWG1DBFbits
;
4851 #define _CWG1DBF0 0x01
4853 #define _CWG1DBF1 0x02
4855 #define _CWG1DBF2 0x04
4857 #define _CWG1DBF3 0x08
4859 #define _CWG1DBF4 0x10
4861 #define _CWG1DBF5 0x20
4863 //==============================================================================
4866 //==============================================================================
4869 extern __at(0x0695) __sfr CWG1CON0
;
4887 unsigned CWG1MODE0
: 1;
4888 unsigned CWG1MODE1
: 1;
4889 unsigned CWG1MODE2
: 1;
4893 unsigned CWG1LD
: 1;
4906 unsigned CWG1EN
: 1;
4911 unsigned CWG1MODE
: 3;
4922 extern __at(0x0695) volatile __CWG1CON0bits_t CWG1CON0bits
;
4924 #define _CWG1CON0_MODE0 0x01
4925 #define _CWG1CON0_CWG1MODE0 0x01
4926 #define _CWG1CON0_MODE1 0x02
4927 #define _CWG1CON0_CWG1MODE1 0x02
4928 #define _CWG1CON0_MODE2 0x04
4929 #define _CWG1CON0_CWG1MODE2 0x04
4930 #define _CWG1CON0_LD 0x40
4931 #define _CWG1CON0_CWG1LD 0x40
4932 #define _CWG1CON0_EN 0x80
4933 #define _CWG1CON0_G1EN 0x80
4934 #define _CWG1CON0_CWG1EN 0x80
4936 //==============================================================================
4939 //==============================================================================
4942 extern __at(0x0696) __sfr CWG1CON1
;
4960 unsigned CWG1POLA
: 1;
4961 unsigned CWG1POLB
: 1;
4962 unsigned CWG1POLC
: 1;
4963 unsigned CWG1POLD
: 1;
4965 unsigned CWG1IN
: 1;
4971 extern __at(0x0696) volatile __CWG1CON1bits_t CWG1CON1bits
;
4974 #define _CWG1POLA 0x01
4976 #define _CWG1POLB 0x02
4978 #define _CWG1POLC 0x04
4980 #define _CWG1POLD 0x08
4982 #define _CWG1IN 0x20
4984 //==============================================================================
4987 //==============================================================================
4990 extern __at(0x0697) __sfr CWG1AS0
;
5003 unsigned SHUTDOWN
: 1;
5010 unsigned CWG1LSAC0
: 1;
5011 unsigned CWG1LSAC1
: 1;
5012 unsigned CWG1LSBD0
: 1;
5013 unsigned CWG1LSBD1
: 1;
5014 unsigned CWG1REN
: 1;
5015 unsigned CWG1SHUTDOWN
: 1;
5028 unsigned CWG1LSAC
: 2;
5042 unsigned CWG1LSBD
: 2;
5047 extern __at(0x0697) volatile __CWG1AS0bits_t CWG1AS0bits
;
5050 #define _CWG1LSAC0 0x04
5052 #define _CWG1LSAC1 0x08
5054 #define _CWG1LSBD0 0x10
5056 #define _CWG1LSBD1 0x20
5058 #define _CWG1REN 0x40
5059 #define _SHUTDOWN 0x80
5060 #define _CWG1SHUTDOWN 0x80
5062 //==============================================================================
5065 //==============================================================================
5068 extern __at(0x0698) __sfr CWG1AS1
;
5082 extern __at(0x0698) volatile __CWG1AS1bits_t CWG1AS1bits
;
5090 //==============================================================================
5093 //==============================================================================
5096 extern __at(0x0699) __sfr CWG1STR
;
5114 unsigned CWG1STRA
: 1;
5115 unsigned CWG1STRB
: 1;
5116 unsigned CWG1STRC
: 1;
5117 unsigned CWG1STRD
: 1;
5118 unsigned CWG1OVRA
: 1;
5119 unsigned CWG1OVRB
: 1;
5120 unsigned CWG1OVRC
: 1;
5121 unsigned CWG1OVRD
: 1;
5125 extern __at(0x0699) volatile __CWG1STRbits_t CWG1STRbits
;
5128 #define _CWG1STRA 0x01
5130 #define _CWG1STRB 0x02
5132 #define _CWG1STRC 0x04
5134 #define _CWG1STRD 0x08
5136 #define _CWG1OVRA 0x10
5138 #define _CWG1OVRB 0x20
5140 #define _CWG1OVRC 0x40
5142 #define _CWG1OVRD 0x80
5144 //==============================================================================
5147 //==============================================================================
5150 extern __at(0x0711) __sfr CWG2CLKCON
;
5168 unsigned CWG2CS
: 1;
5177 } __CWG2CLKCONbits_t
;
5179 extern __at(0x0711) volatile __CWG2CLKCONbits_t CWG2CLKCONbits
;
5181 #define _CWG2CLKCON_CS 0x01
5182 #define _CWG2CLKCON_CWG2CS 0x01
5184 //==============================================================================
5187 //==============================================================================
5190 extern __at(0x0712) __sfr CWG2DAT
;
5196 unsigned CWG2DAT0
: 1;
5197 unsigned CWG2DAT1
: 1;
5198 unsigned CWG2DAT2
: 1;
5199 unsigned CWG2DAT3
: 1;
5208 unsigned CWG2DAT
: 4;
5213 extern __at(0x0712) volatile __CWG2DATbits_t CWG2DATbits
;
5215 #define _CWG2DAT0 0x01
5216 #define _CWG2DAT1 0x02
5217 #define _CWG2DAT2 0x04
5218 #define _CWG2DAT3 0x08
5220 //==============================================================================
5223 //==============================================================================
5226 extern __at(0x0713) __sfr CWG2DBR
;
5244 unsigned CWG2DBR0
: 1;
5245 unsigned CWG2DBR1
: 1;
5246 unsigned CWG2DBR2
: 1;
5247 unsigned CWG2DBR3
: 1;
5248 unsigned CWG2DBR4
: 1;
5249 unsigned CWG2DBR5
: 1;
5262 unsigned CWG2DBR
: 6;
5267 extern __at(0x0713) volatile __CWG2DBRbits_t CWG2DBRbits
;
5269 #define _CWG2DBR_DBR0 0x01
5270 #define _CWG2DBR_CWG2DBR0 0x01
5271 #define _CWG2DBR_DBR1 0x02
5272 #define _CWG2DBR_CWG2DBR1 0x02
5273 #define _CWG2DBR_DBR2 0x04
5274 #define _CWG2DBR_CWG2DBR2 0x04
5275 #define _CWG2DBR_DBR3 0x08
5276 #define _CWG2DBR_CWG2DBR3 0x08
5277 #define _CWG2DBR_DBR4 0x10
5278 #define _CWG2DBR_CWG2DBR4 0x10
5279 #define _CWG2DBR_DBR5 0x20
5280 #define _CWG2DBR_CWG2DBR5 0x20
5282 //==============================================================================
5285 //==============================================================================
5288 extern __at(0x0714) __sfr CWG2DBF
;
5306 unsigned CWG2DBF0
: 1;
5307 unsigned CWG2DBF1
: 1;
5308 unsigned CWG2DBF2
: 1;
5309 unsigned CWG2DBF3
: 1;
5310 unsigned CWG2DBF4
: 1;
5311 unsigned CWG2DBF5
: 1;
5318 unsigned CWG2DBF
: 6;
5329 extern __at(0x0714) volatile __CWG2DBFbits_t CWG2DBFbits
;
5331 #define _CWG2DBF_DBF0 0x01
5332 #define _CWG2DBF_CWG2DBF0 0x01
5333 #define _CWG2DBF_DBF1 0x02
5334 #define _CWG2DBF_CWG2DBF1 0x02
5335 #define _CWG2DBF_DBF2 0x04
5336 #define _CWG2DBF_CWG2DBF2 0x04
5337 #define _CWG2DBF_DBF3 0x08
5338 #define _CWG2DBF_CWG2DBF3 0x08
5339 #define _CWG2DBF_DBF4 0x10
5340 #define _CWG2DBF_CWG2DBF4 0x10
5341 #define _CWG2DBF_DBF5 0x20
5342 #define _CWG2DBF_CWG2DBF5 0x20
5344 //==============================================================================
5347 //==============================================================================
5350 extern __at(0x0715) __sfr CWG2CON0
;
5368 unsigned CWG2MODE0
: 1;
5369 unsigned CWG2MODE1
: 1;
5370 unsigned CWG2MODE2
: 1;
5374 unsigned CWG2LD
: 1;
5387 unsigned CWG2EN
: 1;
5392 unsigned CWG2MODE
: 3;
5403 extern __at(0x0715) volatile __CWG2CON0bits_t CWG2CON0bits
;
5405 #define _CWG2CON0_MODE0 0x01
5406 #define _CWG2CON0_CWG2MODE0 0x01
5407 #define _CWG2CON0_MODE1 0x02
5408 #define _CWG2CON0_CWG2MODE1 0x02
5409 #define _CWG2CON0_MODE2 0x04
5410 #define _CWG2CON0_CWG2MODE2 0x04
5411 #define _CWG2CON0_LD 0x40
5412 #define _CWG2CON0_CWG2LD 0x40
5413 #define _CWG2CON0_EN 0x80
5414 #define _CWG2CON0_G2EN 0x80
5415 #define _CWG2CON0_CWG2EN 0x80
5417 //==============================================================================
5420 //==============================================================================
5423 extern __at(0x0716) __sfr CWG2CON1
;
5441 unsigned CWG2POLA
: 1;
5442 unsigned CWG2POLB
: 1;
5443 unsigned CWG2POLC
: 1;
5444 unsigned CWG2POLD
: 1;
5446 unsigned CWG2IN
: 1;
5452 extern __at(0x0716) volatile __CWG2CON1bits_t CWG2CON1bits
;
5454 #define _CWG2CON1_POLA 0x01
5455 #define _CWG2CON1_CWG2POLA 0x01
5456 #define _CWG2CON1_POLB 0x02
5457 #define _CWG2CON1_CWG2POLB 0x02
5458 #define _CWG2CON1_POLC 0x04
5459 #define _CWG2CON1_CWG2POLC 0x04
5460 #define _CWG2CON1_POLD 0x08
5461 #define _CWG2CON1_CWG2POLD 0x08
5462 #define _CWG2CON1_IN 0x20
5463 #define _CWG2CON1_CWG2IN 0x20
5465 //==============================================================================
5468 //==============================================================================
5471 extern __at(0x0717) __sfr CWG2AS0
;
5484 unsigned SHUTDOWN
: 1;
5491 unsigned CWG2LSAC0
: 1;
5492 unsigned CWG2LSAC1
: 1;
5493 unsigned CWG2LSBD0
: 1;
5494 unsigned CWG2LSBD1
: 1;
5495 unsigned CWG2REN
: 1;
5496 unsigned CWG2SHUTDOWN
: 1;
5509 unsigned CWG2LSAC
: 2;
5523 unsigned CWG2LSBD
: 2;
5528 extern __at(0x0717) volatile __CWG2AS0bits_t CWG2AS0bits
;
5530 #define _CWG2AS0_LSAC0 0x04
5531 #define _CWG2AS0_CWG2LSAC0 0x04
5532 #define _CWG2AS0_LSAC1 0x08
5533 #define _CWG2AS0_CWG2LSAC1 0x08
5534 #define _CWG2AS0_LSBD0 0x10
5535 #define _CWG2AS0_CWG2LSBD0 0x10
5536 #define _CWG2AS0_LSBD1 0x20
5537 #define _CWG2AS0_CWG2LSBD1 0x20
5538 #define _CWG2AS0_REN 0x40
5539 #define _CWG2AS0_CWG2REN 0x40
5540 #define _CWG2AS0_SHUTDOWN 0x80
5541 #define _CWG2AS0_CWG2SHUTDOWN 0x80
5543 //==============================================================================
5546 //==============================================================================
5549 extern __at(0x0718) __sfr CWG2AS1
;
5563 extern __at(0x0718) volatile __CWG2AS1bits_t CWG2AS1bits
;
5565 #define _CWG2AS1_AS0E 0x01
5566 #define _CWG2AS1_AS1E 0x02
5567 #define _CWG2AS1_AS2E 0x04
5568 #define _CWG2AS1_AS3E 0x08
5569 #define _CWG2AS1_AS4E 0x10
5571 //==============================================================================
5574 //==============================================================================
5577 extern __at(0x0719) __sfr CWG2STR
;
5595 unsigned CWG2STRA
: 1;
5596 unsigned CWG2STRB
: 1;
5597 unsigned CWG2STRC
: 1;
5598 unsigned CWG2STRD
: 1;
5599 unsigned CWG2OVRA
: 1;
5600 unsigned CWG2OVRB
: 1;
5601 unsigned CWG2OVRC
: 1;
5602 unsigned CWG2OVRD
: 1;
5606 extern __at(0x0719) volatile __CWG2STRbits_t CWG2STRbits
;
5608 #define _CWG2STR_STRA 0x01
5609 #define _CWG2STR_CWG2STRA 0x01
5610 #define _CWG2STR_STRB 0x02
5611 #define _CWG2STR_CWG2STRB 0x02
5612 #define _CWG2STR_STRC 0x04
5613 #define _CWG2STR_CWG2STRC 0x04
5614 #define _CWG2STR_STRD 0x08
5615 #define _CWG2STR_CWG2STRD 0x08
5616 #define _CWG2STR_OVRA 0x10
5617 #define _CWG2STR_CWG2OVRA 0x10
5618 #define _CWG2STR_OVRB 0x20
5619 #define _CWG2STR_CWG2OVRB 0x20
5620 #define _CWG2STR_OVRC 0x40
5621 #define _CWG2STR_CWG2OVRC 0x40
5622 #define _CWG2STR_OVRD 0x80
5623 #define _CWG2STR_CWG2OVRD 0x80
5625 //==============================================================================
5627 extern __at(0x0891) __sfr NVMADR
;
5629 //==============================================================================
5632 extern __at(0x0891) __sfr NVMADRL
;
5636 unsigned NVMADR0
: 1;
5637 unsigned NVMADR1
: 1;
5638 unsigned NVMADR2
: 1;
5639 unsigned NVMADR3
: 1;
5640 unsigned NVMADR4
: 1;
5641 unsigned NVMADR5
: 1;
5642 unsigned NVMADR6
: 1;
5643 unsigned NVMADR7
: 1;
5646 extern __at(0x0891) volatile __NVMADRLbits_t NVMADRLbits
;
5648 #define _NVMADR0 0x01
5649 #define _NVMADR1 0x02
5650 #define _NVMADR2 0x04
5651 #define _NVMADR3 0x08
5652 #define _NVMADR4 0x10
5653 #define _NVMADR5 0x20
5654 #define _NVMADR6 0x40
5655 #define _NVMADR7 0x80
5657 //==============================================================================
5660 //==============================================================================
5663 extern __at(0x0892) __sfr NVMADRH
;
5667 unsigned NVMADR8
: 1;
5668 unsigned NVMADR9
: 1;
5669 unsigned NVMADR10
: 1;
5670 unsigned NVMADR11
: 1;
5671 unsigned NVMADR12
: 1;
5672 unsigned NVMADR13
: 1;
5673 unsigned NVMADR14
: 1;
5677 extern __at(0x0892) volatile __NVMADRHbits_t NVMADRHbits
;
5679 #define _NVMADR8 0x01
5680 #define _NVMADR9 0x02
5681 #define _NVMADR10 0x04
5682 #define _NVMADR11 0x08
5683 #define _NVMADR12 0x10
5684 #define _NVMADR13 0x20
5685 #define _NVMADR14 0x40
5687 //==============================================================================
5689 extern __at(0x0893) __sfr NVMDAT
;
5691 //==============================================================================
5694 extern __at(0x0893) __sfr NVMDATL
;
5698 unsigned NVMDAT0
: 1;
5699 unsigned NVMDAT1
: 1;
5700 unsigned NVMDAT2
: 1;
5701 unsigned NVMDAT3
: 1;
5702 unsigned NVMDAT4
: 1;
5703 unsigned NVMDAT5
: 1;
5704 unsigned NVMDAT6
: 1;
5705 unsigned NVMDAT7
: 1;
5708 extern __at(0x0893) volatile __NVMDATLbits_t NVMDATLbits
;
5710 #define _NVMDAT0 0x01
5711 #define _NVMDAT1 0x02
5712 #define _NVMDAT2 0x04
5713 #define _NVMDAT3 0x08
5714 #define _NVMDAT4 0x10
5715 #define _NVMDAT5 0x20
5716 #define _NVMDAT6 0x40
5717 #define _NVMDAT7 0x80
5719 //==============================================================================
5722 //==============================================================================
5725 extern __at(0x0894) __sfr NVMDATH
;
5729 unsigned NVMDAT8
: 1;
5730 unsigned NVMDAT9
: 1;
5731 unsigned NVMDAT10
: 1;
5732 unsigned NVMDAT11
: 1;
5733 unsigned NVMDAT12
: 1;
5734 unsigned NVMDAT13
: 1;
5739 extern __at(0x0894) volatile __NVMDATHbits_t NVMDATHbits
;
5741 #define _NVMDAT8 0x01
5742 #define _NVMDAT9 0x02
5743 #define _NVMDAT10 0x04
5744 #define _NVMDAT11 0x08
5745 #define _NVMDAT12 0x10
5746 #define _NVMDAT13 0x20
5748 //==============================================================================
5751 //==============================================================================
5754 extern __at(0x0895) __sfr NVMCON1
;
5764 unsigned NVMREGS
: 1;
5768 extern __at(0x0895) volatile __NVMCON1bits_t NVMCON1bits
;
5776 #define _NVMREGS 0x40
5778 //==============================================================================
5780 extern __at(0x0896) __sfr NVMCON2
;
5782 //==============================================================================
5785 extern __at(0x089B) __sfr PCON0
;
5789 unsigned NOT_BOR
: 1;
5790 unsigned NOT_POR
: 1;
5791 unsigned NOT_RI
: 1;
5792 unsigned NOT_RMCLR
: 1;
5793 unsigned NOT_RWDT
: 1;
5795 unsigned STKUNF
: 1;
5796 unsigned STKOVF
: 1;
5799 extern __at(0x089B) volatile __PCON0bits_t PCON0bits
;
5801 #define _NOT_BOR 0x01
5802 #define _NOT_POR 0x02
5803 #define _NOT_RI 0x04
5804 #define _NOT_RMCLR 0x08
5805 #define _NOT_RWDT 0x10
5806 #define _STKUNF 0x40
5807 #define _STKOVF 0x80
5809 //==============================================================================
5812 //==============================================================================
5815 extern __at(0x0911) __sfr PMD0
;
5820 unsigned CLKRMD
: 1;
5826 unsigned SYSCMD
: 1;
5829 extern __at(0x0911) volatile __PMD0bits_t PMD0bits
;
5832 #define _CLKRMD 0x02
5835 #define _SYSCMD 0x80
5837 //==============================================================================
5840 //==============================================================================
5843 extern __at(0x0912) __sfr PMD1
;
5847 unsigned TMR0MD
: 1;
5848 unsigned TMR1MD
: 1;
5849 unsigned TMR2MD
: 1;
5850 unsigned TMR3MD
: 1;
5851 unsigned TMR4MD
: 1;
5852 unsigned TMR5MD
: 1;
5853 unsigned TMR6MD
: 1;
5857 extern __at(0x0912) volatile __PMD1bits_t PMD1bits
;
5859 #define _TMR0MD 0x01
5860 #define _TMR1MD 0x02
5861 #define _TMR2MD 0x04
5862 #define _TMR3MD 0x08
5863 #define _TMR4MD 0x10
5864 #define _TMR5MD 0x20
5865 #define _TMR6MD 0x40
5868 //==============================================================================
5871 //==============================================================================
5874 extern __at(0x0913) __sfr PMD2
;
5879 unsigned CMP1MD
: 1;
5880 unsigned CMP2MD
: 1;
5888 extern __at(0x0913) volatile __PMD2bits_t PMD2bits
;
5890 #define _CMP1MD 0x02
5891 #define _CMP2MD 0x04
5895 //==============================================================================
5898 //==============================================================================
5901 extern __at(0x0914) __sfr PMD3
;
5905 unsigned CCP1MD
: 1;
5906 unsigned CCP2MD
: 1;
5907 unsigned CCP3MD
: 1;
5908 unsigned CCP4MD
: 1;
5909 unsigned PWM5MD
: 1;
5910 unsigned PWM6MD
: 1;
5911 unsigned CWG1MD
: 1;
5912 unsigned CWG2MD
: 1;
5915 extern __at(0x0914) volatile __PMD3bits_t PMD3bits
;
5917 #define _CCP1MD 0x01
5918 #define _CCP2MD 0x02
5919 #define _CCP3MD 0x04
5920 #define _CCP4MD 0x08
5921 #define _PWM5MD 0x10
5922 #define _PWM6MD 0x20
5923 #define _CWG1MD 0x40
5924 #define _CWG2MD 0x80
5926 //==============================================================================
5929 //==============================================================================
5932 extern __at(0x0915) __sfr PMD4
;
5937 unsigned MSSP1MD
: 1;
5941 unsigned UART1MD
: 1;
5946 extern __at(0x0915) volatile __PMD4bits_t PMD4bits
;
5948 #define _MSSP1MD 0x02
5949 #define _UART1MD 0x20
5951 //==============================================================================
5954 //==============================================================================
5957 extern __at(0x0916) __sfr PMD5
;
5962 unsigned CLC1MD
: 1;
5963 unsigned CLC2MD
: 1;
5964 unsigned CLC3MD
: 1;
5965 unsigned CLC4MD
: 1;
5971 extern __at(0x0916) volatile __PMD5bits_t PMD5bits
;
5974 #define _CLC1MD 0x02
5975 #define _CLC2MD 0x04
5976 #define _CLC3MD 0x08
5977 #define _CLC4MD 0x10
5979 //==============================================================================
5982 //==============================================================================
5985 extern __at(0x0918) __sfr CPUDOZE
;
6008 extern __at(0x0918) volatile __CPUDOZEbits_t CPUDOZEbits
;
6018 //==============================================================================
6021 //==============================================================================
6024 extern __at(0x0919) __sfr OSCCON1
;
6054 extern __at(0x0919) volatile __OSCCON1bits_t OSCCON1bits
;
6064 //==============================================================================
6067 //==============================================================================
6070 extern __at(0x091A) __sfr OSCCON2
;
6100 extern __at(0x091A) volatile __OSCCON2bits_t OSCCON2bits
;
6110 //==============================================================================
6113 //==============================================================================
6116 extern __at(0x091B) __sfr OSCCON3
;
6125 unsigned SOSCBE
: 1;
6126 unsigned SOSCPWR
: 1;
6127 unsigned CSWHOLD
: 1;
6130 extern __at(0x091B) volatile __OSCCON3bits_t OSCCON3bits
;
6134 #define _SOSCBE 0x20
6135 #define _SOSCPWR 0x40
6136 #define _CSWHOLD 0x80
6138 //==============================================================================
6141 //==============================================================================
6144 extern __at(0x091C) __sfr OSCSTAT1
;
6158 extern __at(0x091C) volatile __OSCSTAT1bits_t OSCSTAT1bits
;
6167 //==============================================================================
6170 //==============================================================================
6173 extern __at(0x091D) __sfr OSCEN
;
6180 unsigned SOSCEN
: 1;
6184 unsigned EXTOEN
: 1;
6187 extern __at(0x091D) volatile __OSCENbits_t OSCENbits
;
6190 #define _SOSCEN 0x08
6193 #define _EXTOEN 0x80
6195 //==============================================================================
6198 //==============================================================================
6201 extern __at(0x091E) __sfr OSCTUNE
;
6207 unsigned HFTUN0
: 1;
6208 unsigned HFTUN1
: 1;
6209 unsigned HFTUN2
: 1;
6210 unsigned HFTUN3
: 1;
6211 unsigned HFTUN4
: 1;
6212 unsigned HFTUN5
: 1;
6224 extern __at(0x091E) volatile __OSCTUNEbits_t OSCTUNEbits
;
6226 #define _HFTUN0 0x01
6227 #define _HFTUN1 0x02
6228 #define _HFTUN2 0x04
6229 #define _HFTUN3 0x08
6230 #define _HFTUN4 0x10
6231 #define _HFTUN5 0x20
6233 //==============================================================================
6236 //==============================================================================
6239 extern __at(0x091F) __sfr OSCFRQ
;
6245 unsigned HFFRQ0
: 1;
6246 unsigned HFFRQ1
: 1;
6247 unsigned HFFRQ2
: 1;
6248 unsigned HFFRQ3
: 1;
6262 extern __at(0x091F) volatile __OSCFRQbits_t OSCFRQbits
;
6264 #define _HFFRQ0 0x01
6265 #define _HFFRQ1 0x02
6266 #define _HFFRQ2 0x04
6267 #define _HFFRQ3 0x08
6269 //==============================================================================
6272 //==============================================================================
6275 extern __at(0x0E0F) __sfr PPSLOCK
;
6279 unsigned PPSLOCKED
: 1;
6289 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
6291 #define _PPSLOCKED 0x01
6293 //==============================================================================
6296 //==============================================================================
6299 extern __at(0x0E10) __sfr INTPPS
;
6305 unsigned INTPPS0
: 1;
6306 unsigned INTPPS1
: 1;
6307 unsigned INTPPS2
: 1;
6308 unsigned INTPPS3
: 1;
6309 unsigned INTPPS4
: 1;
6317 unsigned INTPPS
: 5;
6322 extern __at(0x0E10) volatile __INTPPSbits_t INTPPSbits
;
6324 #define _INTPPS0 0x01
6325 #define _INTPPS1 0x02
6326 #define _INTPPS2 0x04
6327 #define _INTPPS3 0x08
6328 #define _INTPPS4 0x10
6330 //==============================================================================
6333 //==============================================================================
6336 extern __at(0x0E11) __sfr T0CKIPPS
;
6342 unsigned T0CKIPPS0
: 1;
6343 unsigned T0CKIPPS1
: 1;
6344 unsigned T0CKIPPS2
: 1;
6345 unsigned T0CKIPPS3
: 1;
6346 unsigned T0CKIPPS4
: 1;
6354 unsigned T0CKIPPS
: 5;
6359 extern __at(0x0E11) volatile __T0CKIPPSbits_t T0CKIPPSbits
;
6361 #define _T0CKIPPS0 0x01
6362 #define _T0CKIPPS1 0x02
6363 #define _T0CKIPPS2 0x04
6364 #define _T0CKIPPS3 0x08
6365 #define _T0CKIPPS4 0x10
6367 //==============================================================================
6370 //==============================================================================
6373 extern __at(0x0E12) __sfr T1CKIPPS
;
6379 unsigned T1CKIPPS0
: 1;
6380 unsigned T1CKIPPS1
: 1;
6381 unsigned T1CKIPPS2
: 1;
6382 unsigned T1CKIPPS3
: 1;
6383 unsigned T1CKIPPS4
: 1;
6391 unsigned T1CKIPPS
: 5;
6396 extern __at(0x0E12) volatile __T1CKIPPSbits_t T1CKIPPSbits
;
6398 #define _T1CKIPPS0 0x01
6399 #define _T1CKIPPS1 0x02
6400 #define _T1CKIPPS2 0x04
6401 #define _T1CKIPPS3 0x08
6402 #define _T1CKIPPS4 0x10
6404 //==============================================================================
6407 //==============================================================================
6410 extern __at(0x0E13) __sfr T1GPPS
;
6416 unsigned T1GPPS0
: 1;
6417 unsigned T1GPPS1
: 1;
6418 unsigned T1GPPS2
: 1;
6419 unsigned T1GPPS3
: 1;
6420 unsigned T1GPPS4
: 1;
6428 unsigned T1GPPS
: 5;
6433 extern __at(0x0E13) volatile __T1GPPSbits_t T1GPPSbits
;
6435 #define _T1GPPS0 0x01
6436 #define _T1GPPS1 0x02
6437 #define _T1GPPS2 0x04
6438 #define _T1GPPS3 0x08
6439 #define _T1GPPS4 0x10
6441 //==============================================================================
6444 //==============================================================================
6447 extern __at(0x0E14) __sfr CCP1PPS
;
6453 unsigned CCP1PPS0
: 1;
6454 unsigned CCP1PPS1
: 1;
6455 unsigned CCP1PPS2
: 1;
6456 unsigned CCP1PPS3
: 1;
6457 unsigned CCP1PPS4
: 1;
6465 unsigned CCP1PPS
: 5;
6470 extern __at(0x0E14) volatile __CCP1PPSbits_t CCP1PPSbits
;
6472 #define _CCP1PPS0 0x01
6473 #define _CCP1PPS1 0x02
6474 #define _CCP1PPS2 0x04
6475 #define _CCP1PPS3 0x08
6476 #define _CCP1PPS4 0x10
6478 //==============================================================================
6481 //==============================================================================
6484 extern __at(0x0E15) __sfr CCP2PPS
;
6490 unsigned CCP2PPS0
: 1;
6491 unsigned CCP2PPS1
: 1;
6492 unsigned CCP2PPS2
: 1;
6493 unsigned CCP2PPS3
: 1;
6494 unsigned CCP2PPS4
: 1;
6502 unsigned CCP2PPS
: 5;
6507 extern __at(0x0E15) volatile __CCP2PPSbits_t CCP2PPSbits
;
6509 #define _CCP2PPS0 0x01
6510 #define _CCP2PPS1 0x02
6511 #define _CCP2PPS2 0x04
6512 #define _CCP2PPS3 0x08
6513 #define _CCP2PPS4 0x10
6515 //==============================================================================
6518 //==============================================================================
6521 extern __at(0x0E16) __sfr CCP3PPS
;
6527 unsigned CCP3PPS0
: 1;
6528 unsigned CCP3PPS1
: 1;
6529 unsigned CCP3PPS2
: 1;
6530 unsigned CCP3PPS3
: 1;
6531 unsigned CCP3PPS4
: 1;
6539 unsigned CCP3PPS
: 5;
6544 extern __at(0x0E16) volatile __CCP3PPSbits_t CCP3PPSbits
;
6546 #define _CCP3PPS0 0x01
6547 #define _CCP3PPS1 0x02
6548 #define _CCP3PPS2 0x04
6549 #define _CCP3PPS3 0x08
6550 #define _CCP3PPS4 0x10
6552 //==============================================================================
6555 //==============================================================================
6558 extern __at(0x0E17) __sfr CCP4PPS
;
6564 unsigned CCP4PPS0
: 1;
6565 unsigned CCP4PPS1
: 1;
6566 unsigned CCP4PPS2
: 1;
6567 unsigned CCP4PPS3
: 1;
6568 unsigned CCP4PPS4
: 1;
6576 unsigned CCP4PPS
: 5;
6581 extern __at(0x0E17) volatile __CCP4PPSbits_t CCP4PPSbits
;
6583 #define _CCP4PPS0 0x01
6584 #define _CCP4PPS1 0x02
6585 #define _CCP4PPS2 0x04
6586 #define _CCP4PPS3 0x08
6587 #define _CCP4PPS4 0x10
6589 //==============================================================================
6592 //==============================================================================
6595 extern __at(0x0E18) __sfr CWG1PPS
;
6601 unsigned CWG1PPS0
: 1;
6602 unsigned CWG1PPS1
: 1;
6603 unsigned CWG1PPS2
: 1;
6604 unsigned CWG1PPS3
: 1;
6605 unsigned CWG1PPS4
: 1;
6613 unsigned CWG1PPS
: 5;
6618 extern __at(0x0E18) volatile __CWG1PPSbits_t CWG1PPSbits
;
6620 #define _CWG1PPS0 0x01
6621 #define _CWG1PPS1 0x02
6622 #define _CWG1PPS2 0x04
6623 #define _CWG1PPS3 0x08
6624 #define _CWG1PPS4 0x10
6626 //==============================================================================
6629 //==============================================================================
6632 extern __at(0x0E19) __sfr CWG2PPS
;
6638 unsigned CWG2PPS0
: 1;
6639 unsigned CWG2PPS1
: 1;
6640 unsigned CWG2PPS2
: 1;
6641 unsigned CWG2PPS3
: 1;
6642 unsigned CWG2PPS4
: 1;
6650 unsigned CWG2PPS
: 5;
6655 extern __at(0x0E19) volatile __CWG2PPSbits_t CWG2PPSbits
;
6657 #define _CWG2PPS0 0x01
6658 #define _CWG2PPS1 0x02
6659 #define _CWG2PPS2 0x04
6660 #define _CWG2PPS3 0x08
6661 #define _CWG2PPS4 0x10
6663 //==============================================================================
6666 //==============================================================================
6669 extern __at(0x0E1A) __sfr MDCIN1PPS
;
6675 unsigned MDCIN1PPS0
: 1;
6676 unsigned MDCIN1PPS1
: 1;
6677 unsigned MDCIN1PPS2
: 1;
6678 unsigned MDCIN1PPS3
: 1;
6679 unsigned MDCIN1PPS4
: 1;
6687 unsigned MDCIN1PPS
: 5;
6690 } __MDCIN1PPSbits_t
;
6692 extern __at(0x0E1A) volatile __MDCIN1PPSbits_t MDCIN1PPSbits
;
6694 #define _MDCIN1PPS0 0x01
6695 #define _MDCIN1PPS1 0x02
6696 #define _MDCIN1PPS2 0x04
6697 #define _MDCIN1PPS3 0x08
6698 #define _MDCIN1PPS4 0x10
6700 //==============================================================================
6703 //==============================================================================
6706 extern __at(0x0E1B) __sfr MDCIN2PPS
;
6712 unsigned MDCIN2PPS0
: 1;
6713 unsigned MDCIN2PPS1
: 1;
6714 unsigned MDCIN2PPS2
: 1;
6715 unsigned MDCIN2PPS3
: 1;
6716 unsigned MDCIN2PPS4
: 1;
6724 unsigned MDCIN2PPS
: 5;
6727 } __MDCIN2PPSbits_t
;
6729 extern __at(0x0E1B) volatile __MDCIN2PPSbits_t MDCIN2PPSbits
;
6731 #define _MDCIN2PPS0 0x01
6732 #define _MDCIN2PPS1 0x02
6733 #define _MDCIN2PPS2 0x04
6734 #define _MDCIN2PPS3 0x08
6735 #define _MDCIN2PPS4 0x10
6737 //==============================================================================
6740 //==============================================================================
6743 extern __at(0x0E1C) __sfr MDMINPPS
;
6749 unsigned MDMINPPS0
: 1;
6750 unsigned MDMINPPS1
: 1;
6751 unsigned MDMINPPS2
: 1;
6752 unsigned MDMINPPS3
: 1;
6753 unsigned MDMINPPS4
: 1;
6761 unsigned MDMINPPS
: 5;
6766 extern __at(0x0E1C) volatile __MDMINPPSbits_t MDMINPPSbits
;
6768 #define _MDMINPPS0 0x01
6769 #define _MDMINPPS1 0x02
6770 #define _MDMINPPS2 0x04
6771 #define _MDMINPPS3 0x08
6772 #define _MDMINPPS4 0x10
6774 //==============================================================================
6777 //==============================================================================
6780 extern __at(0x0E20) __sfr SSP1CLKPPS
;
6786 unsigned SSP1CLKPPS0
: 1;
6787 unsigned SSP1CLKPPS1
: 1;
6788 unsigned SSP1CLKPPS2
: 1;
6789 unsigned SSP1CLKPPS3
: 1;
6790 unsigned SSP1CLKPPS4
: 1;
6798 unsigned SSP1CLKPPS
: 5;
6801 } __SSP1CLKPPSbits_t
;
6803 extern __at(0x0E20) volatile __SSP1CLKPPSbits_t SSP1CLKPPSbits
;
6805 #define _SSP1CLKPPS0 0x01
6806 #define _SSP1CLKPPS1 0x02
6807 #define _SSP1CLKPPS2 0x04
6808 #define _SSP1CLKPPS3 0x08
6809 #define _SSP1CLKPPS4 0x10
6811 //==============================================================================
6814 //==============================================================================
6817 extern __at(0x0E21) __sfr SSP1DATPPS
;
6823 unsigned SSP1DATPPS0
: 1;
6824 unsigned SSP1DATPPS1
: 1;
6825 unsigned SSP1DATPPS2
: 1;
6826 unsigned SSP1DATPPS3
: 1;
6827 unsigned SSP1DATPPS4
: 1;
6835 unsigned SSP1DATPPS
: 5;
6838 } __SSP1DATPPSbits_t
;
6840 extern __at(0x0E21) volatile __SSP1DATPPSbits_t SSP1DATPPSbits
;
6842 #define _SSP1DATPPS0 0x01
6843 #define _SSP1DATPPS1 0x02
6844 #define _SSP1DATPPS2 0x04
6845 #define _SSP1DATPPS3 0x08
6846 #define _SSP1DATPPS4 0x10
6848 //==============================================================================
6851 //==============================================================================
6854 extern __at(0x0E22) __sfr SSP1SSPPS
;
6860 unsigned SSP1SSPPS0
: 1;
6861 unsigned SSP1SSPPS1
: 1;
6862 unsigned SSP1SSPPS2
: 1;
6863 unsigned SSP1SSPPS3
: 1;
6864 unsigned SSP1SSPPS4
: 1;
6872 unsigned SSP1SSPPS
: 5;
6875 } __SSP1SSPPSbits_t
;
6877 extern __at(0x0E22) volatile __SSP1SSPPSbits_t SSP1SSPPSbits
;
6879 #define _SSP1SSPPS0 0x01
6880 #define _SSP1SSPPS1 0x02
6881 #define _SSP1SSPPS2 0x04
6882 #define _SSP1SSPPS3 0x08
6883 #define _SSP1SSPPS4 0x10
6885 //==============================================================================
6888 //==============================================================================
6891 extern __at(0x0E24) __sfr RXPPS
;
6897 unsigned RXDTPPS0
: 1;
6898 unsigned RXDTPPS1
: 1;
6899 unsigned RXDTPPS2
: 1;
6900 unsigned RXDTPPS3
: 1;
6901 unsigned RXDTPPS4
: 1;
6909 unsigned RXDTPPS
: 5;
6914 extern __at(0x0E24) volatile __RXPPSbits_t RXPPSbits
;
6916 #define _RXDTPPS0 0x01
6917 #define _RXDTPPS1 0x02
6918 #define _RXDTPPS2 0x04
6919 #define _RXDTPPS3 0x08
6920 #define _RXDTPPS4 0x10
6922 //==============================================================================
6925 //==============================================================================
6928 extern __at(0x0E25) __sfr TXPPS
;
6934 unsigned TXCKPPS0
: 1;
6935 unsigned TXCKPPS1
: 1;
6936 unsigned TXCKPPS2
: 1;
6937 unsigned TXCKPPS3
: 1;
6938 unsigned TXCKPPS4
: 1;
6946 unsigned TXCKPPS
: 5;
6951 extern __at(0x0E25) volatile __TXPPSbits_t TXPPSbits
;
6953 #define _TXCKPPS0 0x01
6954 #define _TXCKPPS1 0x02
6955 #define _TXCKPPS2 0x04
6956 #define _TXCKPPS3 0x08
6957 #define _TXCKPPS4 0x10
6959 //==============================================================================
6962 //==============================================================================
6965 extern __at(0x0E28) __sfr CLCIN0PPS
;
6971 unsigned CLCIN0PPS0
: 1;
6972 unsigned CLCIN0PPS1
: 1;
6973 unsigned CLCIN0PPS2
: 1;
6974 unsigned CLCIN0PPS3
: 1;
6975 unsigned CLCIN0PPS4
: 1;
6983 unsigned CLCIN0PPS
: 5;
6986 } __CLCIN0PPSbits_t
;
6988 extern __at(0x0E28) volatile __CLCIN0PPSbits_t CLCIN0PPSbits
;
6990 #define _CLCIN0PPS0 0x01
6991 #define _CLCIN0PPS1 0x02
6992 #define _CLCIN0PPS2 0x04
6993 #define _CLCIN0PPS3 0x08
6994 #define _CLCIN0PPS4 0x10
6996 //==============================================================================
6999 //==============================================================================
7002 extern __at(0x0E29) __sfr CLCIN1PPS
;
7008 unsigned CLCIN1PPS0
: 1;
7009 unsigned CLCIN1PPS1
: 1;
7010 unsigned CLCIN1PPS2
: 1;
7011 unsigned CLCIN1PPS3
: 1;
7012 unsigned CLCIN1PPS4
: 1;
7020 unsigned CLCIN1PPS
: 5;
7023 } __CLCIN1PPSbits_t
;
7025 extern __at(0x0E29) volatile __CLCIN1PPSbits_t CLCIN1PPSbits
;
7027 #define _CLCIN1PPS0 0x01
7028 #define _CLCIN1PPS1 0x02
7029 #define _CLCIN1PPS2 0x04
7030 #define _CLCIN1PPS3 0x08
7031 #define _CLCIN1PPS4 0x10
7033 //==============================================================================
7036 //==============================================================================
7039 extern __at(0x0E2A) __sfr CLCIN2PPS
;
7045 unsigned CLCIN2PPS0
: 1;
7046 unsigned CLCIN2PPS1
: 1;
7047 unsigned CLCIN2PPS2
: 1;
7048 unsigned CLCIN2PPS3
: 1;
7049 unsigned CLCIN2PPS4
: 1;
7057 unsigned CLCIN2PPS
: 5;
7060 } __CLCIN2PPSbits_t
;
7062 extern __at(0x0E2A) volatile __CLCIN2PPSbits_t CLCIN2PPSbits
;
7064 #define _CLCIN2PPS0 0x01
7065 #define _CLCIN2PPS1 0x02
7066 #define _CLCIN2PPS2 0x04
7067 #define _CLCIN2PPS3 0x08
7068 #define _CLCIN2PPS4 0x10
7070 //==============================================================================
7073 //==============================================================================
7076 extern __at(0x0E2B) __sfr CLCIN3PPS
;
7082 unsigned CLCIN3PPS0
: 1;
7083 unsigned CLCIN3PPS1
: 1;
7084 unsigned CLCIN3PPS2
: 1;
7085 unsigned CLCIN3PPS3
: 1;
7086 unsigned CLCIN3PPS4
: 1;
7094 unsigned CLCIN3PPS
: 5;
7097 } __CLCIN3PPSbits_t
;
7099 extern __at(0x0E2B) volatile __CLCIN3PPSbits_t CLCIN3PPSbits
;
7101 #define _CLCIN3PPS0 0x01
7102 #define _CLCIN3PPS1 0x02
7103 #define _CLCIN3PPS2 0x04
7104 #define _CLCIN3PPS3 0x08
7105 #define _CLCIN3PPS4 0x10
7107 //==============================================================================
7109 extern __at(0x0E2C) __sfr T3CKIPPS
;
7110 extern __at(0x0E2D) __sfr T3GPPS
;
7111 extern __at(0x0E2E) __sfr T5CKIPPS
;
7112 extern __at(0x0E2F) __sfr T5GPPS
;
7114 //==============================================================================
7117 extern __at(0x0E90) __sfr RA0PPS
;
7123 unsigned RA0PPS0
: 1;
7124 unsigned RA0PPS1
: 1;
7125 unsigned RA0PPS2
: 1;
7126 unsigned RA0PPS3
: 1;
7127 unsigned RA0PPS4
: 1;
7135 unsigned RA0PPS
: 5;
7140 extern __at(0x0E90) volatile __RA0PPSbits_t RA0PPSbits
;
7142 #define _RA0PPS0 0x01
7143 #define _RA0PPS1 0x02
7144 #define _RA0PPS2 0x04
7145 #define _RA0PPS3 0x08
7146 #define _RA0PPS4 0x10
7148 //==============================================================================
7151 //==============================================================================
7154 extern __at(0x0E91) __sfr RA1PPS
;
7160 unsigned RA1PPS0
: 1;
7161 unsigned RA1PPS1
: 1;
7162 unsigned RA1PPS2
: 1;
7163 unsigned RA1PPS3
: 1;
7164 unsigned RA1PPS4
: 1;
7172 unsigned RA1PPS
: 5;
7177 extern __at(0x0E91) volatile __RA1PPSbits_t RA1PPSbits
;
7179 #define _RA1PPS0 0x01
7180 #define _RA1PPS1 0x02
7181 #define _RA1PPS2 0x04
7182 #define _RA1PPS3 0x08
7183 #define _RA1PPS4 0x10
7185 //==============================================================================
7188 //==============================================================================
7191 extern __at(0x0E92) __sfr RA2PPS
;
7197 unsigned RA2PPS0
: 1;
7198 unsigned RA2PPS1
: 1;
7199 unsigned RA2PPS2
: 1;
7200 unsigned RA2PPS3
: 1;
7201 unsigned RA2PPS4
: 1;
7209 unsigned RA2PPS
: 5;
7214 extern __at(0x0E92) volatile __RA2PPSbits_t RA2PPSbits
;
7216 #define _RA2PPS0 0x01
7217 #define _RA2PPS1 0x02
7218 #define _RA2PPS2 0x04
7219 #define _RA2PPS3 0x08
7220 #define _RA2PPS4 0x10
7222 //==============================================================================
7225 //==============================================================================
7228 extern __at(0x0E94) __sfr RA4PPS
;
7234 unsigned RA4PPS0
: 1;
7235 unsigned RA4PPS1
: 1;
7236 unsigned RA4PPS2
: 1;
7237 unsigned RA4PPS3
: 1;
7238 unsigned RA4PPS4
: 1;
7246 unsigned RA4PPS
: 5;
7251 extern __at(0x0E94) volatile __RA4PPSbits_t RA4PPSbits
;
7253 #define _RA4PPS0 0x01
7254 #define _RA4PPS1 0x02
7255 #define _RA4PPS2 0x04
7256 #define _RA4PPS3 0x08
7257 #define _RA4PPS4 0x10
7259 //==============================================================================
7262 //==============================================================================
7265 extern __at(0x0E95) __sfr RA5PPS
;
7271 unsigned RA5PPS0
: 1;
7272 unsigned RA5PPS1
: 1;
7273 unsigned RA5PPS2
: 1;
7274 unsigned RA5PPS3
: 1;
7275 unsigned RA5PPS4
: 1;
7283 unsigned RA5PPS
: 5;
7288 extern __at(0x0E95) volatile __RA5PPSbits_t RA5PPSbits
;
7290 #define _RA5PPS0 0x01
7291 #define _RA5PPS1 0x02
7292 #define _RA5PPS2 0x04
7293 #define _RA5PPS3 0x08
7294 #define _RA5PPS4 0x10
7296 //==============================================================================
7299 //==============================================================================
7302 extern __at(0x0EA0) __sfr RC0PPS
;
7308 unsigned RC0PPS0
: 1;
7309 unsigned RC0PPS1
: 1;
7310 unsigned RC0PPS2
: 1;
7311 unsigned RC0PPS3
: 1;
7312 unsigned RC0PPS4
: 1;
7320 unsigned RC0PPS
: 5;
7325 extern __at(0x0EA0) volatile __RC0PPSbits_t RC0PPSbits
;
7327 #define _RC0PPS0 0x01
7328 #define _RC0PPS1 0x02
7329 #define _RC0PPS2 0x04
7330 #define _RC0PPS3 0x08
7331 #define _RC0PPS4 0x10
7333 //==============================================================================
7336 //==============================================================================
7339 extern __at(0x0EA1) __sfr RC1PPS
;
7345 unsigned RC1PPS0
: 1;
7346 unsigned RC1PPS1
: 1;
7347 unsigned RC1PPS2
: 1;
7348 unsigned RC1PPS3
: 1;
7349 unsigned RC1PPS4
: 1;
7357 unsigned RC1PPS
: 5;
7362 extern __at(0x0EA1) volatile __RC1PPSbits_t RC1PPSbits
;
7364 #define _RC1PPS0 0x01
7365 #define _RC1PPS1 0x02
7366 #define _RC1PPS2 0x04
7367 #define _RC1PPS3 0x08
7368 #define _RC1PPS4 0x10
7370 //==============================================================================
7373 //==============================================================================
7376 extern __at(0x0EA2) __sfr RC2PPS
;
7382 unsigned RC2PPS0
: 1;
7383 unsigned RC2PPS1
: 1;
7384 unsigned RC2PPS2
: 1;
7385 unsigned RC2PPS3
: 1;
7386 unsigned RC2PPS4
: 1;
7394 unsigned RC2PPS
: 5;
7399 extern __at(0x0EA2) volatile __RC2PPSbits_t RC2PPSbits
;
7401 #define _RC2PPS0 0x01
7402 #define _RC2PPS1 0x02
7403 #define _RC2PPS2 0x04
7404 #define _RC2PPS3 0x08
7405 #define _RC2PPS4 0x10
7407 //==============================================================================
7410 //==============================================================================
7413 extern __at(0x0EA3) __sfr RC3PPS
;
7419 unsigned RC3PPS0
: 1;
7420 unsigned RC3PPS1
: 1;
7421 unsigned RC3PPS2
: 1;
7422 unsigned RC3PPS3
: 1;
7423 unsigned RC3PPS4
: 1;
7431 unsigned RC3PPS
: 5;
7436 extern __at(0x0EA3) volatile __RC3PPSbits_t RC3PPSbits
;
7438 #define _RC3PPS0 0x01
7439 #define _RC3PPS1 0x02
7440 #define _RC3PPS2 0x04
7441 #define _RC3PPS3 0x08
7442 #define _RC3PPS4 0x10
7444 //==============================================================================
7447 //==============================================================================
7450 extern __at(0x0EA4) __sfr RC4PPS
;
7456 unsigned RC4PPS0
: 1;
7457 unsigned RC4PPS1
: 1;
7458 unsigned RC4PPS2
: 1;
7459 unsigned RC4PPS3
: 1;
7460 unsigned RC4PPS4
: 1;
7468 unsigned RC4PPS
: 5;
7473 extern __at(0x0EA4) volatile __RC4PPSbits_t RC4PPSbits
;
7475 #define _RC4PPS0 0x01
7476 #define _RC4PPS1 0x02
7477 #define _RC4PPS2 0x04
7478 #define _RC4PPS3 0x08
7479 #define _RC4PPS4 0x10
7481 //==============================================================================
7484 //==============================================================================
7487 extern __at(0x0EA5) __sfr RC5PPS
;
7493 unsigned RC5PPS0
: 1;
7494 unsigned RC5PPS1
: 1;
7495 unsigned RC5PPS2
: 1;
7496 unsigned RC5PPS3
: 1;
7497 unsigned RC5PPS4
: 1;
7505 unsigned RC5PPS
: 5;
7510 extern __at(0x0EA5) volatile __RC5PPSbits_t RC5PPSbits
;
7512 #define _RC5PPS0 0x01
7513 #define _RC5PPS1 0x02
7514 #define _RC5PPS2 0x04
7515 #define _RC5PPS3 0x08
7516 #define _RC5PPS4 0x10
7518 //==============================================================================
7521 //==============================================================================
7524 extern __at(0x0F0F) __sfr CLCDATA
;
7528 unsigned MLC1OUT
: 1;
7529 unsigned MLC2OUT
: 1;
7530 unsigned MLC3OUT
: 1;
7531 unsigned MLC4OUT
: 1;
7538 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
7540 #define _MLC1OUT 0x01
7541 #define _MLC2OUT 0x02
7542 #define _MLC3OUT 0x04
7543 #define _MLC4OUT 0x08
7545 //==============================================================================
7548 //==============================================================================
7551 extern __at(0x0F10) __sfr CLC1CON
;
7557 unsigned LC1MODE0
: 1;
7558 unsigned LC1MODE1
: 1;
7559 unsigned LC1MODE2
: 1;
7560 unsigned LC1INTN
: 1;
7561 unsigned LC1INTP
: 1;
7562 unsigned LC1OUT
: 1;
7581 unsigned LC1MODE
: 3;
7592 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
7594 #define _LC1MODE0 0x01
7596 #define _LC1MODE1 0x02
7598 #define _LC1MODE2 0x04
7600 #define _LC1INTN 0x08
7602 #define _LC1INTP 0x10
7604 #define _LC1OUT 0x20
7609 //==============================================================================
7612 //==============================================================================
7615 extern __at(0x0F11) __sfr CLC1POL
;
7621 unsigned LC1G1POL
: 1;
7622 unsigned LC1G2POL
: 1;
7623 unsigned LC1G3POL
: 1;
7624 unsigned LC1G4POL
: 1;
7628 unsigned LC1POL
: 1;
7644 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
7646 #define _LC1G1POL 0x01
7648 #define _LC1G2POL 0x02
7650 #define _LC1G3POL 0x04
7652 #define _LC1G4POL 0x08
7654 #define _LC1POL 0x80
7657 //==============================================================================
7660 //==============================================================================
7663 extern __at(0x0F12) __sfr CLC1SEL0
;
7669 unsigned LC1D1S0
: 1;
7670 unsigned LC1D1S1
: 1;
7671 unsigned LC1D1S2
: 1;
7672 unsigned LC1D1S3
: 1;
7673 unsigned LC1D1S4
: 1;
7674 unsigned LC1D1S5
: 1;
7699 unsigned LC1D1S
: 6;
7704 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
7706 #define _LC1D1S0 0x01
7708 #define _LC1D1S1 0x02
7710 #define _LC1D1S2 0x04
7712 #define _LC1D1S3 0x08
7714 #define _LC1D1S4 0x10
7716 #define _LC1D1S5 0x20
7719 //==============================================================================
7722 //==============================================================================
7725 extern __at(0x0F13) __sfr CLC1SEL1
;
7731 unsigned LC1D2S0
: 1;
7732 unsigned LC1D2S1
: 1;
7733 unsigned LC1D2S2
: 1;
7734 unsigned LC1D2S3
: 1;
7735 unsigned LC1D2S4
: 1;
7736 unsigned LC1D2S5
: 1;
7755 unsigned LC1D2S
: 6;
7766 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
7768 #define _LC1D2S0 0x01
7770 #define _LC1D2S1 0x02
7772 #define _LC1D2S2 0x04
7774 #define _LC1D2S3 0x08
7776 #define _LC1D2S4 0x10
7778 #define _LC1D2S5 0x20
7781 //==============================================================================
7784 //==============================================================================
7787 extern __at(0x0F14) __sfr CLC1SEL2
;
7793 unsigned LC1D3S0
: 1;
7794 unsigned LC1D3S1
: 1;
7795 unsigned LC1D3S2
: 1;
7796 unsigned LC1D3S3
: 1;
7797 unsigned LC1D3S4
: 1;
7798 unsigned LC1D3S5
: 1;
7823 unsigned LC1D3S
: 6;
7828 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
7830 #define _LC1D3S0 0x01
7832 #define _LC1D3S1 0x02
7834 #define _LC1D3S2 0x04
7836 #define _LC1D3S3 0x08
7838 #define _LC1D3S4 0x10
7840 #define _LC1D3S5 0x20
7843 //==============================================================================
7846 //==============================================================================
7849 extern __at(0x0F15) __sfr CLC1SEL3
;
7855 unsigned LC1D4S0
: 1;
7856 unsigned LC1D4S1
: 1;
7857 unsigned LC1D4S2
: 1;
7858 unsigned LC1D4S3
: 1;
7859 unsigned LC1D4S4
: 1;
7860 unsigned LC1D4S5
: 1;
7879 unsigned LC1D4S
: 6;
7890 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
7892 #define _LC1D4S0 0x01
7894 #define _LC1D4S1 0x02
7896 #define _LC1D4S2 0x04
7898 #define _LC1D4S3 0x08
7900 #define _LC1D4S4 0x10
7902 #define _LC1D4S5 0x20
7905 //==============================================================================
7908 //==============================================================================
7911 extern __at(0x0F16) __sfr CLC1GLS0
;
7917 unsigned LC1G1D1N
: 1;
7918 unsigned LC1G1D1T
: 1;
7919 unsigned LC1G1D2N
: 1;
7920 unsigned LC1G1D2T
: 1;
7921 unsigned LC1G1D3N
: 1;
7922 unsigned LC1G1D3T
: 1;
7923 unsigned LC1G1D4N
: 1;
7924 unsigned LC1G1D4T
: 1;
7940 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
7942 #define _LC1G1D1N 0x01
7944 #define _LC1G1D1T 0x02
7946 #define _LC1G1D2N 0x04
7948 #define _LC1G1D2T 0x08
7950 #define _LC1G1D3N 0x10
7952 #define _LC1G1D3T 0x20
7954 #define _LC1G1D4N 0x40
7956 #define _LC1G1D4T 0x80
7959 //==============================================================================
7962 //==============================================================================
7965 extern __at(0x0F17) __sfr CLC1GLS1
;
7971 unsigned LC1G2D1N
: 1;
7972 unsigned LC1G2D1T
: 1;
7973 unsigned LC1G2D2N
: 1;
7974 unsigned LC1G2D2T
: 1;
7975 unsigned LC1G2D3N
: 1;
7976 unsigned LC1G2D3T
: 1;
7977 unsigned LC1G2D4N
: 1;
7978 unsigned LC1G2D4T
: 1;
7994 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
7996 #define _CLC1GLS1_LC1G2D1N 0x01
7997 #define _CLC1GLS1_D1N 0x01
7998 #define _CLC1GLS1_LC1G2D1T 0x02
7999 #define _CLC1GLS1_D1T 0x02
8000 #define _CLC1GLS1_LC1G2D2N 0x04
8001 #define _CLC1GLS1_D2N 0x04
8002 #define _CLC1GLS1_LC1G2D2T 0x08
8003 #define _CLC1GLS1_D2T 0x08
8004 #define _CLC1GLS1_LC1G2D3N 0x10
8005 #define _CLC1GLS1_D3N 0x10
8006 #define _CLC1GLS1_LC1G2D3T 0x20
8007 #define _CLC1GLS1_D3T 0x20
8008 #define _CLC1GLS1_LC1G2D4N 0x40
8009 #define _CLC1GLS1_D4N 0x40
8010 #define _CLC1GLS1_LC1G2D4T 0x80
8011 #define _CLC1GLS1_D4T 0x80
8013 //==============================================================================
8016 //==============================================================================
8019 extern __at(0x0F18) __sfr CLC1GLS2
;
8025 unsigned LC1G3D1N
: 1;
8026 unsigned LC1G3D1T
: 1;
8027 unsigned LC1G3D2N
: 1;
8028 unsigned LC1G3D2T
: 1;
8029 unsigned LC1G3D3N
: 1;
8030 unsigned LC1G3D3T
: 1;
8031 unsigned LC1G3D4N
: 1;
8032 unsigned LC1G3D4T
: 1;
8048 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
8050 #define _CLC1GLS2_LC1G3D1N 0x01
8051 #define _CLC1GLS2_D1N 0x01
8052 #define _CLC1GLS2_LC1G3D1T 0x02
8053 #define _CLC1GLS2_D1T 0x02
8054 #define _CLC1GLS2_LC1G3D2N 0x04
8055 #define _CLC1GLS2_D2N 0x04
8056 #define _CLC1GLS2_LC1G3D2T 0x08
8057 #define _CLC1GLS2_D2T 0x08
8058 #define _CLC1GLS2_LC1G3D3N 0x10
8059 #define _CLC1GLS2_D3N 0x10
8060 #define _CLC1GLS2_LC1G3D3T 0x20
8061 #define _CLC1GLS2_D3T 0x20
8062 #define _CLC1GLS2_LC1G3D4N 0x40
8063 #define _CLC1GLS2_D4N 0x40
8064 #define _CLC1GLS2_LC1G3D4T 0x80
8065 #define _CLC1GLS2_D4T 0x80
8067 //==============================================================================
8070 //==============================================================================
8073 extern __at(0x0F19) __sfr CLC1GLS3
;
8079 unsigned LC1G4D1N
: 1;
8080 unsigned LC1G4D1T
: 1;
8081 unsigned LC1G4D2N
: 1;
8082 unsigned LC1G4D2T
: 1;
8083 unsigned LC1G4D3N
: 1;
8084 unsigned LC1G4D3T
: 1;
8085 unsigned LC1G4D4N
: 1;
8086 unsigned LC1G4D4T
: 1;
8102 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
8104 #define _LC1G4D1N 0x01
8106 #define _LC1G4D1T 0x02
8108 #define _LC1G4D2N 0x04
8110 #define _LC1G4D2T 0x08
8112 #define _LC1G4D3N 0x10
8114 #define _LC1G4D3T 0x20
8116 #define _LC1G4D4N 0x40
8118 #define _LC1G4D4T 0x80
8121 //==============================================================================
8124 //==============================================================================
8127 extern __at(0x0F1A) __sfr CLC2CON
;
8133 unsigned LC2MODE0
: 1;
8134 unsigned LC2MODE1
: 1;
8135 unsigned LC2MODE2
: 1;
8136 unsigned LC2INTN
: 1;
8137 unsigned LC2INTP
: 1;
8138 unsigned LC2OUT
: 1;
8157 unsigned LC2MODE
: 3;
8168 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
8170 #define _CLC2CON_LC2MODE0 0x01
8171 #define _CLC2CON_MODE0 0x01
8172 #define _CLC2CON_LC2MODE1 0x02
8173 #define _CLC2CON_MODE1 0x02
8174 #define _CLC2CON_LC2MODE2 0x04
8175 #define _CLC2CON_MODE2 0x04
8176 #define _CLC2CON_LC2INTN 0x08
8177 #define _CLC2CON_INTN 0x08
8178 #define _CLC2CON_LC2INTP 0x10
8179 #define _CLC2CON_INTP 0x10
8180 #define _CLC2CON_LC2OUT 0x20
8181 #define _CLC2CON_OUT 0x20
8182 #define _CLC2CON_LC2EN 0x80
8183 #define _CLC2CON_EN 0x80
8185 //==============================================================================
8188 //==============================================================================
8191 extern __at(0x0F1B) __sfr CLC2POL
;
8197 unsigned LC2G1POL
: 1;
8198 unsigned LC2G2POL
: 1;
8199 unsigned LC2G3POL
: 1;
8200 unsigned LC2G4POL
: 1;
8204 unsigned LC2POL
: 1;
8220 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
8222 #define _CLC2POL_LC2G1POL 0x01
8223 #define _CLC2POL_G1POL 0x01
8224 #define _CLC2POL_LC2G2POL 0x02
8225 #define _CLC2POL_G2POL 0x02
8226 #define _CLC2POL_LC2G3POL 0x04
8227 #define _CLC2POL_G3POL 0x04
8228 #define _CLC2POL_LC2G4POL 0x08
8229 #define _CLC2POL_G4POL 0x08
8230 #define _CLC2POL_LC2POL 0x80
8231 #define _CLC2POL_POL 0x80
8233 //==============================================================================
8236 //==============================================================================
8239 extern __at(0x0F1C) __sfr CLC2SEL0
;
8245 unsigned LC2D1S0
: 1;
8246 unsigned LC2D1S1
: 1;
8247 unsigned LC2D1S2
: 1;
8248 unsigned LC2D1S3
: 1;
8249 unsigned LC2D1S4
: 1;
8250 unsigned LC2D1S5
: 1;
8275 unsigned LC2D1S
: 6;
8280 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
8282 #define _CLC2SEL0_LC2D1S0 0x01
8283 #define _CLC2SEL0_D1S0 0x01
8284 #define _CLC2SEL0_LC2D1S1 0x02
8285 #define _CLC2SEL0_D1S1 0x02
8286 #define _CLC2SEL0_LC2D1S2 0x04
8287 #define _CLC2SEL0_D1S2 0x04
8288 #define _CLC2SEL0_LC2D1S3 0x08
8289 #define _CLC2SEL0_D1S3 0x08
8290 #define _CLC2SEL0_LC2D1S4 0x10
8291 #define _CLC2SEL0_D1S4 0x10
8292 #define _CLC2SEL0_LC2D1S5 0x20
8293 #define _CLC2SEL0_D1S5 0x20
8295 //==============================================================================
8298 //==============================================================================
8301 extern __at(0x0F1D) __sfr CLC2SEL1
;
8307 unsigned LC2D2S0
: 1;
8308 unsigned LC2D2S1
: 1;
8309 unsigned LC2D2S2
: 1;
8310 unsigned LC2D2S3
: 1;
8311 unsigned LC2D2S4
: 1;
8312 unsigned LC2D2S5
: 1;
8331 unsigned LC2D2S
: 6;
8342 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
8344 #define _CLC2SEL1_LC2D2S0 0x01
8345 #define _CLC2SEL1_D2S0 0x01
8346 #define _CLC2SEL1_LC2D2S1 0x02
8347 #define _CLC2SEL1_D2S1 0x02
8348 #define _CLC2SEL1_LC2D2S2 0x04
8349 #define _CLC2SEL1_D2S2 0x04
8350 #define _CLC2SEL1_LC2D2S3 0x08
8351 #define _CLC2SEL1_D2S3 0x08
8352 #define _CLC2SEL1_LC2D2S4 0x10
8353 #define _CLC2SEL1_D2S4 0x10
8354 #define _CLC2SEL1_LC2D2S5 0x20
8355 #define _CLC2SEL1_D2S5 0x20
8357 //==============================================================================
8360 //==============================================================================
8363 extern __at(0x0F1E) __sfr CLC2SEL2
;
8369 unsigned LC2D3S0
: 1;
8370 unsigned LC2D3S1
: 1;
8371 unsigned LC2D3S2
: 1;
8372 unsigned LC2D3S3
: 1;
8373 unsigned LC2D3S4
: 1;
8374 unsigned LC2D3S5
: 1;
8399 unsigned LC2D3S
: 6;
8404 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
8406 #define _CLC2SEL2_LC2D3S0 0x01
8407 #define _CLC2SEL2_D3S0 0x01
8408 #define _CLC2SEL2_LC2D3S1 0x02
8409 #define _CLC2SEL2_D3S1 0x02
8410 #define _CLC2SEL2_LC2D3S2 0x04
8411 #define _CLC2SEL2_D3S2 0x04
8412 #define _CLC2SEL2_LC2D3S3 0x08
8413 #define _CLC2SEL2_D3S3 0x08
8414 #define _CLC2SEL2_LC2D3S4 0x10
8415 #define _CLC2SEL2_D3S4 0x10
8416 #define _CLC2SEL2_LC2D3S5 0x20
8417 #define _CLC2SEL2_D3S5 0x20
8419 //==============================================================================
8422 //==============================================================================
8425 extern __at(0x0F1F) __sfr CLC2SEL3
;
8431 unsigned LC2D4S0
: 1;
8432 unsigned LC2D4S1
: 1;
8433 unsigned LC2D4S2
: 1;
8434 unsigned LC2D4S3
: 1;
8435 unsigned LC2D4S4
: 1;
8436 unsigned LC2D4S5
: 1;
8455 unsigned LC2D4S
: 6;
8466 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
8468 #define _CLC2SEL3_LC2D4S0 0x01
8469 #define _CLC2SEL3_D4S0 0x01
8470 #define _CLC2SEL3_LC2D4S1 0x02
8471 #define _CLC2SEL3_D4S1 0x02
8472 #define _CLC2SEL3_LC2D4S2 0x04
8473 #define _CLC2SEL3_D4S2 0x04
8474 #define _CLC2SEL3_LC2D4S3 0x08
8475 #define _CLC2SEL3_D4S3 0x08
8476 #define _CLC2SEL3_LC2D4S4 0x10
8477 #define _CLC2SEL3_D4S4 0x10
8478 #define _CLC2SEL3_LC2D4S5 0x20
8479 #define _CLC2SEL3_D4S5 0x20
8481 //==============================================================================
8484 //==============================================================================
8487 extern __at(0x0F20) __sfr CLC2GLS0
;
8493 unsigned LC2G1D1N
: 1;
8494 unsigned LC2G1D1T
: 1;
8495 unsigned LC2G1D2N
: 1;
8496 unsigned LC2G1D2T
: 1;
8497 unsigned LC2G1D3N
: 1;
8498 unsigned LC2G1D3T
: 1;
8499 unsigned LC2G1D4N
: 1;
8500 unsigned LC2G1D4T
: 1;
8516 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
8518 #define _CLC2GLS0_LC2G1D1N 0x01
8519 #define _CLC2GLS0_D1N 0x01
8520 #define _CLC2GLS0_LC2G1D1T 0x02
8521 #define _CLC2GLS0_D1T 0x02
8522 #define _CLC2GLS0_LC2G1D2N 0x04
8523 #define _CLC2GLS0_D2N 0x04
8524 #define _CLC2GLS0_LC2G1D2T 0x08
8525 #define _CLC2GLS0_D2T 0x08
8526 #define _CLC2GLS0_LC2G1D3N 0x10
8527 #define _CLC2GLS0_D3N 0x10
8528 #define _CLC2GLS0_LC2G1D3T 0x20
8529 #define _CLC2GLS0_D3T 0x20
8530 #define _CLC2GLS0_LC2G1D4N 0x40
8531 #define _CLC2GLS0_D4N 0x40
8532 #define _CLC2GLS0_LC2G1D4T 0x80
8533 #define _CLC2GLS0_D4T 0x80
8535 //==============================================================================
8538 //==============================================================================
8541 extern __at(0x0F21) __sfr CLC2GLS1
;
8547 unsigned LC2G2D1N
: 1;
8548 unsigned LC2G2D1T
: 1;
8549 unsigned LC2G2D2N
: 1;
8550 unsigned LC2G2D2T
: 1;
8551 unsigned LC2G2D3N
: 1;
8552 unsigned LC2G2D3T
: 1;
8553 unsigned LC2G2D4N
: 1;
8554 unsigned LC2G2D4T
: 1;
8570 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
8572 #define _CLC2GLS1_LC2G2D1N 0x01
8573 #define _CLC2GLS1_D1N 0x01
8574 #define _CLC2GLS1_LC2G2D1T 0x02
8575 #define _CLC2GLS1_D1T 0x02
8576 #define _CLC2GLS1_LC2G2D2N 0x04
8577 #define _CLC2GLS1_D2N 0x04
8578 #define _CLC2GLS1_LC2G2D2T 0x08
8579 #define _CLC2GLS1_D2T 0x08
8580 #define _CLC2GLS1_LC2G2D3N 0x10
8581 #define _CLC2GLS1_D3N 0x10
8582 #define _CLC2GLS1_LC2G2D3T 0x20
8583 #define _CLC2GLS1_D3T 0x20
8584 #define _CLC2GLS1_LC2G2D4N 0x40
8585 #define _CLC2GLS1_D4N 0x40
8586 #define _CLC2GLS1_LC2G2D4T 0x80
8587 #define _CLC2GLS1_D4T 0x80
8589 //==============================================================================
8592 //==============================================================================
8595 extern __at(0x0F22) __sfr CLC2GLS2
;
8601 unsigned LC2G3D1N
: 1;
8602 unsigned LC2G3D1T
: 1;
8603 unsigned LC2G3D2N
: 1;
8604 unsigned LC2G3D2T
: 1;
8605 unsigned LC2G3D3N
: 1;
8606 unsigned LC2G3D3T
: 1;
8607 unsigned LC2G3D4N
: 1;
8608 unsigned LC2G3D4T
: 1;
8624 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
8626 #define _CLC2GLS2_LC2G3D1N 0x01
8627 #define _CLC2GLS2_D1N 0x01
8628 #define _CLC2GLS2_LC2G3D1T 0x02
8629 #define _CLC2GLS2_D1T 0x02
8630 #define _CLC2GLS2_LC2G3D2N 0x04
8631 #define _CLC2GLS2_D2N 0x04
8632 #define _CLC2GLS2_LC2G3D2T 0x08
8633 #define _CLC2GLS2_D2T 0x08
8634 #define _CLC2GLS2_LC2G3D3N 0x10
8635 #define _CLC2GLS2_D3N 0x10
8636 #define _CLC2GLS2_LC2G3D3T 0x20
8637 #define _CLC2GLS2_D3T 0x20
8638 #define _CLC2GLS2_LC2G3D4N 0x40
8639 #define _CLC2GLS2_D4N 0x40
8640 #define _CLC2GLS2_LC2G3D4T 0x80
8641 #define _CLC2GLS2_D4T 0x80
8643 //==============================================================================
8646 //==============================================================================
8649 extern __at(0x0F23) __sfr CLC2GLS3
;
8655 unsigned LC2G4D1N
: 1;
8656 unsigned LC2G4D1T
: 1;
8657 unsigned LC2G4D2N
: 1;
8658 unsigned LC2G4D2T
: 1;
8659 unsigned LC2G4D3N
: 1;
8660 unsigned LC2G4D3T
: 1;
8661 unsigned LC2G4D4N
: 1;
8662 unsigned LC2G4D4T
: 1;
8678 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
8680 #define _CLC2GLS3_LC2G4D1N 0x01
8681 #define _CLC2GLS3_G4D1N 0x01
8682 #define _CLC2GLS3_LC2G4D1T 0x02
8683 #define _CLC2GLS3_G4D1T 0x02
8684 #define _CLC2GLS3_LC2G4D2N 0x04
8685 #define _CLC2GLS3_G4D2N 0x04
8686 #define _CLC2GLS3_LC2G4D2T 0x08
8687 #define _CLC2GLS3_G4D2T 0x08
8688 #define _CLC2GLS3_LC2G4D3N 0x10
8689 #define _CLC2GLS3_G4D3N 0x10
8690 #define _CLC2GLS3_LC2G4D3T 0x20
8691 #define _CLC2GLS3_G4D3T 0x20
8692 #define _CLC2GLS3_LC2G4D4N 0x40
8693 #define _CLC2GLS3_G4D4N 0x40
8694 #define _CLC2GLS3_LC2G4D4T 0x80
8695 #define _CLC2GLS3_G4D4T 0x80
8697 //==============================================================================
8700 //==============================================================================
8703 extern __at(0x0F24) __sfr CLC3CON
;
8709 unsigned LC3MODE0
: 1;
8710 unsigned LC3MODE1
: 1;
8711 unsigned LC3MODE2
: 1;
8712 unsigned LC3INTN
: 1;
8713 unsigned LC3INTP
: 1;
8714 unsigned LC3OUT
: 1;
8733 unsigned LC3MODE
: 3;
8744 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
8746 #define _CLC3CON_LC3MODE0 0x01
8747 #define _CLC3CON_MODE0 0x01
8748 #define _CLC3CON_LC3MODE1 0x02
8749 #define _CLC3CON_MODE1 0x02
8750 #define _CLC3CON_LC3MODE2 0x04
8751 #define _CLC3CON_MODE2 0x04
8752 #define _CLC3CON_LC3INTN 0x08
8753 #define _CLC3CON_INTN 0x08
8754 #define _CLC3CON_LC3INTP 0x10
8755 #define _CLC3CON_INTP 0x10
8756 #define _CLC3CON_LC3OUT 0x20
8757 #define _CLC3CON_OUT 0x20
8758 #define _CLC3CON_LC3EN 0x80
8759 #define _CLC3CON_EN 0x80
8761 //==============================================================================
8764 //==============================================================================
8767 extern __at(0x0F25) __sfr CLC3POL
;
8773 unsigned LC3G1POL
: 1;
8774 unsigned LC3G2POL
: 1;
8775 unsigned LC3G3POL
: 1;
8776 unsigned LC3G4POL
: 1;
8780 unsigned LC3POL
: 1;
8796 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
8798 #define _CLC3POL_LC3G1POL 0x01
8799 #define _CLC3POL_G1POL 0x01
8800 #define _CLC3POL_LC3G2POL 0x02
8801 #define _CLC3POL_G2POL 0x02
8802 #define _CLC3POL_LC3G3POL 0x04
8803 #define _CLC3POL_G3POL 0x04
8804 #define _CLC3POL_LC3G4POL 0x08
8805 #define _CLC3POL_G4POL 0x08
8806 #define _CLC3POL_LC3POL 0x80
8807 #define _CLC3POL_POL 0x80
8809 //==============================================================================
8812 //==============================================================================
8815 extern __at(0x0F26) __sfr CLC3SEL0
;
8821 unsigned LC3D1S0
: 1;
8822 unsigned LC3D1S1
: 1;
8823 unsigned LC3D1S2
: 1;
8824 unsigned LC3D1S3
: 1;
8825 unsigned LC3D1S4
: 1;
8826 unsigned LC3D1S5
: 1;
8851 unsigned LC3D1S
: 6;
8856 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
8858 #define _CLC3SEL0_LC3D1S0 0x01
8859 #define _CLC3SEL0_D1S0 0x01
8860 #define _CLC3SEL0_LC3D1S1 0x02
8861 #define _CLC3SEL0_D1S1 0x02
8862 #define _CLC3SEL0_LC3D1S2 0x04
8863 #define _CLC3SEL0_D1S2 0x04
8864 #define _CLC3SEL0_LC3D1S3 0x08
8865 #define _CLC3SEL0_D1S3 0x08
8866 #define _CLC3SEL0_LC3D1S4 0x10
8867 #define _CLC3SEL0_D1S4 0x10
8868 #define _CLC3SEL0_LC3D1S5 0x20
8869 #define _CLC3SEL0_D1S5 0x20
8871 //==============================================================================
8874 //==============================================================================
8877 extern __at(0x0F27) __sfr CLC3SEL1
;
8883 unsigned LC3D2S0
: 1;
8884 unsigned LC3D2S1
: 1;
8885 unsigned LC3D2S2
: 1;
8886 unsigned LC3D2S3
: 1;
8887 unsigned LC3D2S4
: 1;
8888 unsigned LC3D2S5
: 1;
8913 unsigned LC3D2S
: 6;
8918 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
8920 #define _CLC3SEL1_LC3D2S0 0x01
8921 #define _CLC3SEL1_D2S0 0x01
8922 #define _CLC3SEL1_LC3D2S1 0x02
8923 #define _CLC3SEL1_D2S1 0x02
8924 #define _CLC3SEL1_LC3D2S2 0x04
8925 #define _CLC3SEL1_D2S2 0x04
8926 #define _CLC3SEL1_LC3D2S3 0x08
8927 #define _CLC3SEL1_D2S3 0x08
8928 #define _CLC3SEL1_LC3D2S4 0x10
8929 #define _CLC3SEL1_D2S4 0x10
8930 #define _CLC3SEL1_LC3D2S5 0x20
8931 #define _CLC3SEL1_D2S5 0x20
8933 //==============================================================================
8936 //==============================================================================
8939 extern __at(0x0F28) __sfr CLC3SEL2
;
8945 unsigned LC3D3S0
: 1;
8946 unsigned LC3D3S1
: 1;
8947 unsigned LC3D3S2
: 1;
8948 unsigned LC3D3S3
: 1;
8949 unsigned LC3D3S4
: 1;
8950 unsigned LC3D3S5
: 1;
8969 unsigned LC3D3S
: 6;
8980 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
8982 #define _CLC3SEL2_LC3D3S0 0x01
8983 #define _CLC3SEL2_D3S0 0x01
8984 #define _CLC3SEL2_LC3D3S1 0x02
8985 #define _CLC3SEL2_D3S1 0x02
8986 #define _CLC3SEL2_LC3D3S2 0x04
8987 #define _CLC3SEL2_D3S2 0x04
8988 #define _CLC3SEL2_LC3D3S3 0x08
8989 #define _CLC3SEL2_D3S3 0x08
8990 #define _CLC3SEL2_LC3D3S4 0x10
8991 #define _CLC3SEL2_D3S4 0x10
8992 #define _CLC3SEL2_LC3D3S5 0x20
8993 #define _CLC3SEL2_D3S5 0x20
8995 //==============================================================================
8998 //==============================================================================
9001 extern __at(0x0F29) __sfr CLC3SEL3
;
9007 unsigned LC3D4S0
: 1;
9008 unsigned LC3D4S1
: 1;
9009 unsigned LC3D4S2
: 1;
9010 unsigned LC3D4S3
: 1;
9011 unsigned LC3D4S4
: 1;
9012 unsigned LC3D4S5
: 1;
9037 unsigned LC3D4S
: 6;
9042 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
9044 #define _CLC3SEL3_LC3D4S0 0x01
9045 #define _CLC3SEL3_D4S0 0x01
9046 #define _CLC3SEL3_LC3D4S1 0x02
9047 #define _CLC3SEL3_D4S1 0x02
9048 #define _CLC3SEL3_LC3D4S2 0x04
9049 #define _CLC3SEL3_D4S2 0x04
9050 #define _CLC3SEL3_LC3D4S3 0x08
9051 #define _CLC3SEL3_D4S3 0x08
9052 #define _CLC3SEL3_LC3D4S4 0x10
9053 #define _CLC3SEL3_D4S4 0x10
9054 #define _CLC3SEL3_LC3D4S5 0x20
9055 #define _CLC3SEL3_D4S5 0x20
9057 //==============================================================================
9060 //==============================================================================
9063 extern __at(0x0F2A) __sfr CLC3GLS0
;
9069 unsigned LC3G1D1N
: 1;
9070 unsigned LC3G1D1T
: 1;
9071 unsigned LC3G1D2N
: 1;
9072 unsigned LC3G1D2T
: 1;
9073 unsigned LC3G1D3N
: 1;
9074 unsigned LC3G1D3T
: 1;
9075 unsigned LC3G1D4N
: 1;
9076 unsigned LC3G1D4T
: 1;
9092 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
9094 #define _CLC3GLS0_LC3G1D1N 0x01
9095 #define _CLC3GLS0_D1N 0x01
9096 #define _CLC3GLS0_LC3G1D1T 0x02
9097 #define _CLC3GLS0_D1T 0x02
9098 #define _CLC3GLS0_LC3G1D2N 0x04
9099 #define _CLC3GLS0_D2N 0x04
9100 #define _CLC3GLS0_LC3G1D2T 0x08
9101 #define _CLC3GLS0_D2T 0x08
9102 #define _CLC3GLS0_LC3G1D3N 0x10
9103 #define _CLC3GLS0_D3N 0x10
9104 #define _CLC3GLS0_LC3G1D3T 0x20
9105 #define _CLC3GLS0_D3T 0x20
9106 #define _CLC3GLS0_LC3G1D4N 0x40
9107 #define _CLC3GLS0_D4N 0x40
9108 #define _CLC3GLS0_LC3G1D4T 0x80
9109 #define _CLC3GLS0_D4T 0x80
9111 //==============================================================================
9114 //==============================================================================
9117 extern __at(0x0F2B) __sfr CLC3GLS1
;
9123 unsigned LC3G2D1N
: 1;
9124 unsigned LC3G2D1T
: 1;
9125 unsigned LC3G2D2N
: 1;
9126 unsigned LC3G2D2T
: 1;
9127 unsigned LC3G2D3N
: 1;
9128 unsigned LC3G2D3T
: 1;
9129 unsigned LC3G2D4N
: 1;
9130 unsigned LC3G2D4T
: 1;
9146 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
9148 #define _CLC3GLS1_LC3G2D1N 0x01
9149 #define _CLC3GLS1_D1N 0x01
9150 #define _CLC3GLS1_LC3G2D1T 0x02
9151 #define _CLC3GLS1_D1T 0x02
9152 #define _CLC3GLS1_LC3G2D2N 0x04
9153 #define _CLC3GLS1_D2N 0x04
9154 #define _CLC3GLS1_LC3G2D2T 0x08
9155 #define _CLC3GLS1_D2T 0x08
9156 #define _CLC3GLS1_LC3G2D3N 0x10
9157 #define _CLC3GLS1_D3N 0x10
9158 #define _CLC3GLS1_LC3G2D3T 0x20
9159 #define _CLC3GLS1_D3T 0x20
9160 #define _CLC3GLS1_LC3G2D4N 0x40
9161 #define _CLC3GLS1_D4N 0x40
9162 #define _CLC3GLS1_LC3G2D4T 0x80
9163 #define _CLC3GLS1_D4T 0x80
9165 //==============================================================================
9168 //==============================================================================
9171 extern __at(0x0F2C) __sfr CLC3GLS2
;
9177 unsigned LC3G3D1N
: 1;
9178 unsigned LC3G3D1T
: 1;
9179 unsigned LC3G3D2N
: 1;
9180 unsigned LC3G3D2T
: 1;
9181 unsigned LC3G3D3N
: 1;
9182 unsigned LC3G3D3T
: 1;
9183 unsigned LC3G3D4N
: 1;
9184 unsigned LC3G3D4T
: 1;
9200 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
9202 #define _CLC3GLS2_LC3G3D1N 0x01
9203 #define _CLC3GLS2_D1N 0x01
9204 #define _CLC3GLS2_LC3G3D1T 0x02
9205 #define _CLC3GLS2_D1T 0x02
9206 #define _CLC3GLS2_LC3G3D2N 0x04
9207 #define _CLC3GLS2_D2N 0x04
9208 #define _CLC3GLS2_LC3G3D2T 0x08
9209 #define _CLC3GLS2_D2T 0x08
9210 #define _CLC3GLS2_LC3G3D3N 0x10
9211 #define _CLC3GLS2_D3N 0x10
9212 #define _CLC3GLS2_LC3G3D3T 0x20
9213 #define _CLC3GLS2_D3T 0x20
9214 #define _CLC3GLS2_LC3G3D4N 0x40
9215 #define _CLC3GLS2_D4N 0x40
9216 #define _CLC3GLS2_LC3G3D4T 0x80
9217 #define _CLC3GLS2_D4T 0x80
9219 //==============================================================================
9222 //==============================================================================
9225 extern __at(0x0F2D) __sfr CLC3GLS3
;
9231 unsigned LC3G4D1N
: 1;
9232 unsigned LC3G4D1T
: 1;
9233 unsigned LC3G4D2N
: 1;
9234 unsigned LC3G4D2T
: 1;
9235 unsigned LC3G4D3N
: 1;
9236 unsigned LC3G4D3T
: 1;
9237 unsigned LC3G4D4N
: 1;
9238 unsigned LC3G4D4T
: 1;
9254 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
9256 #define _CLC3GLS3_LC3G4D1N 0x01
9257 #define _CLC3GLS3_G4D1N 0x01
9258 #define _CLC3GLS3_LC3G4D1T 0x02
9259 #define _CLC3GLS3_G4D1T 0x02
9260 #define _CLC3GLS3_LC3G4D2N 0x04
9261 #define _CLC3GLS3_G4D2N 0x04
9262 #define _CLC3GLS3_LC3G4D2T 0x08
9263 #define _CLC3GLS3_G4D2T 0x08
9264 #define _CLC3GLS3_LC3G4D3N 0x10
9265 #define _CLC3GLS3_G4D3N 0x10
9266 #define _CLC3GLS3_LC3G4D3T 0x20
9267 #define _CLC3GLS3_G4D3T 0x20
9268 #define _CLC3GLS3_LC3G4D4N 0x40
9269 #define _CLC3GLS3_G4D4N 0x40
9270 #define _CLC3GLS3_LC3G4D4T 0x80
9271 #define _CLC3GLS3_G4D4T 0x80
9273 //==============================================================================
9276 //==============================================================================
9279 extern __at(0x0F2E) __sfr CLC4CON
;
9285 unsigned LC4MODE0
: 1;
9286 unsigned LC4MODE1
: 1;
9287 unsigned LC4MODE2
: 1;
9288 unsigned LC4INTN
: 1;
9289 unsigned LC4INTP
: 1;
9290 unsigned LC4OUT
: 1;
9315 unsigned LC4MODE
: 3;
9320 extern __at(0x0F2E) volatile __CLC4CONbits_t CLC4CONbits
;
9322 #define _CLC4CON_LC4MODE0 0x01
9323 #define _CLC4CON_MODE0 0x01
9324 #define _CLC4CON_LC4MODE1 0x02
9325 #define _CLC4CON_MODE1 0x02
9326 #define _CLC4CON_LC4MODE2 0x04
9327 #define _CLC4CON_MODE2 0x04
9328 #define _CLC4CON_LC4INTN 0x08
9329 #define _CLC4CON_INTN 0x08
9330 #define _CLC4CON_LC4INTP 0x10
9331 #define _CLC4CON_INTP 0x10
9332 #define _CLC4CON_LC4OUT 0x20
9333 #define _CLC4CON_OUT 0x20
9334 #define _CLC4CON_LC4EN 0x80
9335 #define _CLC4CON_EN 0x80
9337 //==============================================================================
9340 //==============================================================================
9343 extern __at(0x0F2F) __sfr CLC4POL
;
9349 unsigned LC4G1POL
: 1;
9350 unsigned LC4G2POL
: 1;
9351 unsigned LC4G3POL
: 1;
9352 unsigned LC4G4POL
: 1;
9356 unsigned LC4POL
: 1;
9372 extern __at(0x0F2F) volatile __CLC4POLbits_t CLC4POLbits
;
9374 #define _CLC4POL_LC4G1POL 0x01
9375 #define _CLC4POL_G1POL 0x01
9376 #define _CLC4POL_LC4G2POL 0x02
9377 #define _CLC4POL_G2POL 0x02
9378 #define _CLC4POL_LC4G3POL 0x04
9379 #define _CLC4POL_G3POL 0x04
9380 #define _CLC4POL_LC4G4POL 0x08
9381 #define _CLC4POL_G4POL 0x08
9382 #define _CLC4POL_LC4POL 0x80
9383 #define _CLC4POL_POL 0x80
9385 //==============================================================================
9388 //==============================================================================
9391 extern __at(0x0F30) __sfr CLC4SEL0
;
9397 unsigned LC4D1S0
: 1;
9398 unsigned LC4D1S1
: 1;
9399 unsigned LC4D1S2
: 1;
9400 unsigned LC4D1S3
: 1;
9401 unsigned LC4D1S4
: 1;
9402 unsigned LC4D1S5
: 1;
9421 unsigned LC4D1S
: 6;
9432 extern __at(0x0F30) volatile __CLC4SEL0bits_t CLC4SEL0bits
;
9434 #define _CLC4SEL0_LC4D1S0 0x01
9435 #define _CLC4SEL0_D1S0 0x01
9436 #define _CLC4SEL0_LC4D1S1 0x02
9437 #define _CLC4SEL0_D1S1 0x02
9438 #define _CLC4SEL0_LC4D1S2 0x04
9439 #define _CLC4SEL0_D1S2 0x04
9440 #define _CLC4SEL0_LC4D1S3 0x08
9441 #define _CLC4SEL0_D1S3 0x08
9442 #define _CLC4SEL0_LC4D1S4 0x10
9443 #define _CLC4SEL0_D1S4 0x10
9444 #define _CLC4SEL0_LC4D1S5 0x20
9445 #define _CLC4SEL0_D1S5 0x20
9447 //==============================================================================
9450 //==============================================================================
9453 extern __at(0x0F31) __sfr CLC4SEL1
;
9459 unsigned LC4D2S0
: 1;
9460 unsigned LC4D2S1
: 1;
9461 unsigned LC4D2S2
: 1;
9462 unsigned LC4D2S3
: 1;
9463 unsigned LC4D2S4
: 1;
9464 unsigned LC4D2S5
: 1;
9489 unsigned LC4D2S
: 6;
9494 extern __at(0x0F31) volatile __CLC4SEL1bits_t CLC4SEL1bits
;
9496 #define _CLC4SEL1_LC4D2S0 0x01
9497 #define _CLC4SEL1_D2S0 0x01
9498 #define _CLC4SEL1_LC4D2S1 0x02
9499 #define _CLC4SEL1_D2S1 0x02
9500 #define _CLC4SEL1_LC4D2S2 0x04
9501 #define _CLC4SEL1_D2S2 0x04
9502 #define _CLC4SEL1_LC4D2S3 0x08
9503 #define _CLC4SEL1_D2S3 0x08
9504 #define _CLC4SEL1_LC4D2S4 0x10
9505 #define _CLC4SEL1_D2S4 0x10
9506 #define _CLC4SEL1_LC4D2S5 0x20
9507 #define _CLC4SEL1_D2S5 0x20
9509 //==============================================================================
9512 //==============================================================================
9515 extern __at(0x0F32) __sfr CLC4SEL2
;
9521 unsigned LC4D3S0
: 1;
9522 unsigned LC4D3S1
: 1;
9523 unsigned LC4D3S2
: 1;
9524 unsigned LC4D3S3
: 1;
9525 unsigned LC4D3S4
: 1;
9526 unsigned LC4D3S5
: 1;
9545 unsigned LC4D3S
: 6;
9556 extern __at(0x0F32) volatile __CLC4SEL2bits_t CLC4SEL2bits
;
9558 #define _CLC4SEL2_LC4D3S0 0x01
9559 #define _CLC4SEL2_D3S0 0x01
9560 #define _CLC4SEL2_LC4D3S1 0x02
9561 #define _CLC4SEL2_D3S1 0x02
9562 #define _CLC4SEL2_LC4D3S2 0x04
9563 #define _CLC4SEL2_D3S2 0x04
9564 #define _CLC4SEL2_LC4D3S3 0x08
9565 #define _CLC4SEL2_D3S3 0x08
9566 #define _CLC4SEL2_LC4D3S4 0x10
9567 #define _CLC4SEL2_D3S4 0x10
9568 #define _CLC4SEL2_LC4D3S5 0x20
9569 #define _CLC4SEL2_D3S5 0x20
9571 //==============================================================================
9574 //==============================================================================
9577 extern __at(0x0F33) __sfr CLC4SEL3
;
9583 unsigned LC4D4S0
: 1;
9584 unsigned LC4D4S1
: 1;
9585 unsigned LC4D4S2
: 1;
9586 unsigned LC4D4S3
: 1;
9587 unsigned LC4D4S4
: 1;
9588 unsigned LC4D4S5
: 1;
9607 unsigned LC4D4S
: 6;
9618 extern __at(0x0F33) volatile __CLC4SEL3bits_t CLC4SEL3bits
;
9620 #define _CLC4SEL3_LC4D4S0 0x01
9621 #define _CLC4SEL3_D4S0 0x01
9622 #define _CLC4SEL3_LC4D4S1 0x02
9623 #define _CLC4SEL3_D4S1 0x02
9624 #define _CLC4SEL3_LC4D4S2 0x04
9625 #define _CLC4SEL3_D4S2 0x04
9626 #define _CLC4SEL3_LC4D4S3 0x08
9627 #define _CLC4SEL3_D4S3 0x08
9628 #define _CLC4SEL3_LC4D4S4 0x10
9629 #define _CLC4SEL3_D4S4 0x10
9630 #define _CLC4SEL3_LC4D4S5 0x20
9631 #define _CLC4SEL3_D4S5 0x20
9633 //==============================================================================
9636 //==============================================================================
9639 extern __at(0x0F34) __sfr CLC4GLS0
;
9645 unsigned LC4G1D1N
: 1;
9646 unsigned LC4G1D1T
: 1;
9647 unsigned LC4G1D2N
: 1;
9648 unsigned LC4G1D2T
: 1;
9649 unsigned LC4G1D3N
: 1;
9650 unsigned LC4G1D3T
: 1;
9651 unsigned LC4G1D4N
: 1;
9652 unsigned LC4G1D4T
: 1;
9668 extern __at(0x0F34) volatile __CLC4GLS0bits_t CLC4GLS0bits
;
9670 #define _CLC4GLS0_LC4G1D1N 0x01
9671 #define _CLC4GLS0_D1N 0x01
9672 #define _CLC4GLS0_LC4G1D1T 0x02
9673 #define _CLC4GLS0_D1T 0x02
9674 #define _CLC4GLS0_LC4G1D2N 0x04
9675 #define _CLC4GLS0_D2N 0x04
9676 #define _CLC4GLS0_LC4G1D2T 0x08
9677 #define _CLC4GLS0_D2T 0x08
9678 #define _CLC4GLS0_LC4G1D3N 0x10
9679 #define _CLC4GLS0_D3N 0x10
9680 #define _CLC4GLS0_LC4G1D3T 0x20
9681 #define _CLC4GLS0_D3T 0x20
9682 #define _CLC4GLS0_LC4G1D4N 0x40
9683 #define _CLC4GLS0_D4N 0x40
9684 #define _CLC4GLS0_LC4G1D4T 0x80
9685 #define _CLC4GLS0_D4T 0x80
9687 //==============================================================================
9690 //==============================================================================
9693 extern __at(0x0F35) __sfr CLC4GLS1
;
9699 unsigned LC4G2D1N
: 1;
9700 unsigned LC4G2D1T
: 1;
9701 unsigned LC4G2D2N
: 1;
9702 unsigned LC4G2D2T
: 1;
9703 unsigned LC4G2D3N
: 1;
9704 unsigned LC4G2D3T
: 1;
9705 unsigned LC4G2D4N
: 1;
9706 unsigned LC4G2D4T
: 1;
9722 extern __at(0x0F35) volatile __CLC4GLS1bits_t CLC4GLS1bits
;
9724 #define _CLC4GLS1_LC4G2D1N 0x01
9725 #define _CLC4GLS1_D1N 0x01
9726 #define _CLC4GLS1_LC4G2D1T 0x02
9727 #define _CLC4GLS1_D1T 0x02
9728 #define _CLC4GLS1_LC4G2D2N 0x04
9729 #define _CLC4GLS1_D2N 0x04
9730 #define _CLC4GLS1_LC4G2D2T 0x08
9731 #define _CLC4GLS1_D2T 0x08
9732 #define _CLC4GLS1_LC4G2D3N 0x10
9733 #define _CLC4GLS1_D3N 0x10
9734 #define _CLC4GLS1_LC4G2D3T 0x20
9735 #define _CLC4GLS1_D3T 0x20
9736 #define _CLC4GLS1_LC4G2D4N 0x40
9737 #define _CLC4GLS1_D4N 0x40
9738 #define _CLC4GLS1_LC4G2D4T 0x80
9739 #define _CLC4GLS1_D4T 0x80
9741 //==============================================================================
9744 //==============================================================================
9747 extern __at(0x0F36) __sfr CLC4GLS2
;
9753 unsigned LC4G3D1N
: 1;
9754 unsigned LC4G3D1T
: 1;
9755 unsigned LC4G3D2N
: 1;
9756 unsigned LC4G3D2T
: 1;
9757 unsigned LC4G3D3N
: 1;
9758 unsigned LC4G3D3T
: 1;
9759 unsigned LC4G3D4N
: 1;
9760 unsigned LC4G3D4T
: 1;
9776 extern __at(0x0F36) volatile __CLC4GLS2bits_t CLC4GLS2bits
;
9778 #define _CLC4GLS2_LC4G3D1N 0x01
9779 #define _CLC4GLS2_D1N 0x01
9780 #define _CLC4GLS2_LC4G3D1T 0x02
9781 #define _CLC4GLS2_D1T 0x02
9782 #define _CLC4GLS2_LC4G3D2N 0x04
9783 #define _CLC4GLS2_D2N 0x04
9784 #define _CLC4GLS2_LC4G3D2T 0x08
9785 #define _CLC4GLS2_D2T 0x08
9786 #define _CLC4GLS2_LC4G3D3N 0x10
9787 #define _CLC4GLS2_D3N 0x10
9788 #define _CLC4GLS2_LC4G3D3T 0x20
9789 #define _CLC4GLS2_D3T 0x20
9790 #define _CLC4GLS2_LC4G3D4N 0x40
9791 #define _CLC4GLS2_D4N 0x40
9792 #define _CLC4GLS2_LC4G3D4T 0x80
9793 #define _CLC4GLS2_D4T 0x80
9795 //==============================================================================
9798 //==============================================================================
9801 extern __at(0x0F37) __sfr CLC4GLS3
;
9807 unsigned LC4G4D1N
: 1;
9808 unsigned LC4G4D1T
: 1;
9809 unsigned LC4G4D2N
: 1;
9810 unsigned LC4G4D2T
: 1;
9811 unsigned LC4G4D3N
: 1;
9812 unsigned LC4G4D3T
: 1;
9813 unsigned LC4G4D4N
: 1;
9814 unsigned LC4G4D4T
: 1;
9830 extern __at(0x0F37) volatile __CLC4GLS3bits_t CLC4GLS3bits
;
9832 #define _CLC4GLS3_LC4G4D1N 0x01
9833 #define _CLC4GLS3_G4D1N 0x01
9834 #define _CLC4GLS3_LC4G4D1T 0x02
9835 #define _CLC4GLS3_G4D1T 0x02
9836 #define _CLC4GLS3_LC4G4D2N 0x04
9837 #define _CLC4GLS3_G4D2N 0x04
9838 #define _CLC4GLS3_LC4G4D2T 0x08
9839 #define _CLC4GLS3_G4D2T 0x08
9840 #define _CLC4GLS3_LC4G4D3N 0x10
9841 #define _CLC4GLS3_G4D3N 0x10
9842 #define _CLC4GLS3_LC4G4D3T 0x20
9843 #define _CLC4GLS3_G4D3T 0x20
9844 #define _CLC4GLS3_LC4G4D4N 0x40
9845 #define _CLC4GLS3_G4D4N 0x40
9846 #define _CLC4GLS3_LC4G4D4T 0x80
9847 #define _CLC4GLS3_G4D4T 0x80
9849 //==============================================================================
9852 //==============================================================================
9855 extern __at(0x0FE4) __sfr STATUS_SHAD
;
9859 unsigned C_SHAD
: 1;
9860 unsigned DC_SHAD
: 1;
9861 unsigned Z_SHAD
: 1;
9867 } __STATUS_SHADbits_t
;
9869 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
9871 #define _C_SHAD 0x01
9872 #define _DC_SHAD 0x02
9873 #define _Z_SHAD 0x04
9875 //==============================================================================
9877 extern __at(0x0FE5) __sfr WREG_SHAD
;
9878 extern __at(0x0FE6) __sfr BSR_SHAD
;
9879 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
9880 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
9881 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
9882 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
9883 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
9884 extern __at(0x0FED) __sfr STKPTR
;
9885 extern __at(0x0FEE) __sfr TOSL
;
9886 extern __at(0x0FEF) __sfr TOSH
;
9888 //==============================================================================
9890 // Configuration Bits
9892 //==============================================================================
9894 #define _CONFIG1 0x8007
9895 #define _CONFIG2 0x8008
9896 #define _CONFIG3 0x8009
9897 #define _CONFIG4 0x800A
9899 //----------------------------- CONFIG1 Options -------------------------------
9901 #define _FEXTOSC_LP 0x3FF8 // LP (crystal oscillator) optimized for 32.768 kHz.
9902 #define _FEXTOSC_XT 0x3FF9 // XT (crystal oscillator) from 100 kHz to 4 MHz.
9903 #define _FEXTOSC_HS 0x3FFA // HS (crystal oscillator) above 4 MHz.
9904 #define _FEXTOSC_OFF 0x3FFC // Oscillator not enabled.
9905 #define _FEXTOSC_ECL 0x3FFD // EC (external clock) below 100 kHz.
9906 #define _FEXTOSC_ECM 0x3FFE // EC (external clock) for 100 kHz to 8 MHz.
9907 #define _FEXTOSC_ECH 0x3FFF // EC (external clock) above 8 MHz.
9908 #define _RSTOSC_HFINT32 0x3F8F // HFINTOSC with 2x PLL (32MHz).
9909 #define _RSTOSC_EXT4X 0x3F9F // EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits.
9910 #define _RSTOSC_SOSC 0x3FBF // SOSC (31kHz).
9911 #define _RSTOSC_LFINT 0x3FCF // LFINTOSC (31kHz).
9912 #define _RSTOSC_HFINT1 0x3FEF // HFINTOSC (1MHz).
9913 #define _RSTOSC_EXT1X 0x3FFF // EXTOSC operating per FEXTOSC bits.
9914 #define _CLKOUTEN_ON 0x3EFF // CLKOUT function is enabled; FOSC/4 clock appears at OSC2.
9915 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled; I/O or oscillator function on OSC2.
9916 #define _CSWEN_OFF 0x37FF // The NOSC and NDIV bits cannot be changed by user software.
9917 #define _CSWEN_ON 0x3FFF // Writing to NOSC and NDIV is allowed.
9918 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
9919 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
9921 //----------------------------- CONFIG2 Options -------------------------------
9923 #define _MCLRE_OFF 0x3FFE // MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of port pin's WPU control bit.
9924 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR; Weak pull-up enabled.
9925 #define _PWRTE_ON 0x3FFD // PWRT enabled.
9926 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
9927 #define _WDTE_OFF 0x3FF3 // WDT disabled; SWDTEN is ignored.
9928 #define _WDTE_SWDTEN 0x3FF7 // WDT controlled by the SWDTEN bit in the WDTCON register.
9929 #define _WDTE_SLEEP 0x3FFB // WDT enabled while running and disabled in SLEEP/IDLE; SWDTEN is ignored.
9930 #define _WDTE_ON 0x3FFF // WDT enabled, SWDTEN is ignored.
9931 #define _LPBOREN_ON 0x3FDF // ULPBOR enabled.
9932 #define _LPBOREN_OFF 0x3FFF // ULPBOR disabled.
9933 #define _BOREN_OFF 0x3F3F // Brown-out Reset disabled.
9934 #define _BOREN_SBOREN 0x3F7F // Brown-out Reset enabled according to SBOREN.
9935 #define _BOREN_SLEEP 0x3FBF // Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored.
9936 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled, SBOREN bit ignored.
9937 #define _BORV_HIGH 0x3DFF // Brown-out voltage (Vbor) set to 2.7V.
9938 #define _BORV_LOW 0x3FFF // Brown-out voltage (Vbor) set to 2.45V.
9939 #define _PPS1WAY_OFF 0x37FF // The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence).
9940 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle.
9941 #define _STVREN_OFF 0x2FFF // Stack Overflow or Underflow will not cause a Reset.
9942 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
9943 #define _DEBUG_ON 0x1FFF // Background debugger enabled.
9944 #define _DEBUG_OFF 0x3FFF // Background debugger disabled.
9946 //----------------------------- CONFIG3 Options -------------------------------
9948 #define _WRT_ALL 0x3FFC // 0000h to 0FFFh write protected, no addresses may be modified.
9949 #define _WRT_HALF 0x3FFD // 0000h to 03FFh write-protected, 0400h to 0FFFh may be modified.
9950 #define _WRT_BOOT 0x3FFE // 0000h to 01FFh write-protected, 0200h to 0FFFh may be modified.
9951 #define _WRT_OFF 0x3FFF // Write protection off.
9952 #define _LVP_OFF 0x1FFF // High Voltage on MCLR/VPP must be used for programming.
9953 #define _LVP_ON 0x3FFF // Low Voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.
9955 //----------------------------- CONFIG4 Options -------------------------------
9957 #define _CP_ON 0x3FFE // User NVM code protection enabled.
9958 #define _CP_OFF 0x3FFF // User NVM code protection disabled.
9959 #define _CPD_ON 0x3FFD // Data NVM code protection enabled.
9960 #define _CPD_OFF 0x3FFF // Data NVM code protection disabled.
9962 //==============================================================================
9964 #define _DEVID1 0x8006
9966 #define _IDLOC0 0x8000
9967 #define _IDLOC1 0x8001
9968 #define _IDLOC2 0x8002
9969 #define _IDLOC3 0x8003
9971 //==============================================================================
9973 #ifndef NO_BIT_DEFINES
9975 #define ADACT0 ADACTbits.ADACT0 // bit 0
9976 #define ADACT1 ADACTbits.ADACT1 // bit 1
9977 #define ADACT2 ADACTbits.ADACT2 // bit 2
9978 #define ADACT3 ADACTbits.ADACT3 // bit 3
9979 #define ADACT4 ADACTbits.ADACT4 // bit 4
9981 #define ADON ADCON0bits.ADON // bit 0
9982 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
9983 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
9984 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
9985 #define CHS0 ADCON0bits.CHS0 // bit 2
9986 #define CHS1 ADCON0bits.CHS1 // bit 3
9987 #define CHS2 ADCON0bits.CHS2 // bit 4
9988 #define CHS3 ADCON0bits.CHS3 // bit 5
9989 #define CHS4 ADCON0bits.CHS4 // bit 6
9990 #define CHS5 ADCON0bits.CHS5 // bit 7
9992 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
9993 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
9994 #define ADNREF ADCON1bits.ADNREF // bit 2
9995 #define ADCS0 ADCON1bits.ADCS0 // bit 4
9996 #define ADCS1 ADCON1bits.ADCS1 // bit 5
9997 #define ADCS2 ADCON1bits.ADCS2 // bit 6
9998 #define ADFM ADCON1bits.ADFM // bit 7
10000 #define ANSA0 ANSELAbits.ANSA0 // bit 0
10001 #define ANSA1 ANSELAbits.ANSA1 // bit 1
10002 #define ANSA2 ANSELAbits.ANSA2 // bit 2
10003 #define ANSA4 ANSELAbits.ANSA4 // bit 4
10004 #define ANSA5 ANSELAbits.ANSA5 // bit 5
10006 #define ANSC0 ANSELCbits.ANSC0 // bit 0
10007 #define ANSC1 ANSELCbits.ANSC1 // bit 1
10008 #define ANSC2 ANSELCbits.ANSC2 // bit 2
10009 #define ANSC3 ANSELCbits.ANSC3 // bit 3
10010 #define ANSC4 ANSELCbits.ANSC4 // bit 4
10011 #define ANSC5 ANSELCbits.ANSC5 // bit 5
10013 #define ABDEN BAUD1CONbits.ABDEN // bit 0
10014 #define WUE BAUD1CONbits.WUE // bit 1
10015 #define BRG16 BAUD1CONbits.BRG16 // bit 3
10016 #define SCKP BAUD1CONbits.SCKP // bit 4
10017 #define RCIDL BAUD1CONbits.RCIDL // bit 6
10018 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
10020 #define BORRDY BORCONbits.BORRDY // bit 0
10021 #define SBOREN BORCONbits.SBOREN // bit 7
10023 #define BSR0 BSRbits.BSR0 // bit 0
10024 #define BSR1 BSRbits.BSR1 // bit 1
10025 #define BSR2 BSRbits.BSR2 // bit 2
10026 #define BSR3 BSRbits.BSR3 // bit 3
10027 #define BSR4 BSRbits.BSR4 // bit 4
10029 #define CCDS0 CCDCONbits.CCDS0 // bit 0
10030 #define CCDS1 CCDCONbits.CCDS1 // bit 1
10031 #define CCDEN CCDCONbits.CCDEN // bit 7
10033 #define CCDNA0 CCDNAbits.CCDNA0 // bit 0
10034 #define CCDNA1 CCDNAbits.CCDNA1 // bit 1
10035 #define CCDNA2 CCDNAbits.CCDNA2 // bit 2
10036 #define CCDNA4 CCDNAbits.CCDNA4 // bit 4
10037 #define CCDNA5 CCDNAbits.CCDNA5 // bit 5
10039 #define CCDNC0 CCDNCbits.CCDNC0 // bit 0
10040 #define CCDNC1 CCDNCbits.CCDNC1 // bit 1
10041 #define CCDNC2 CCDNCbits.CCDNC2 // bit 2
10042 #define CCDNC3 CCDNCbits.CCDNC3 // bit 3
10043 #define CCDNC4 CCDNCbits.CCDNC4 // bit 4
10044 #define CCDNC5 CCDNCbits.CCDNC5 // bit 5
10046 #define CCDPA0 CCDPAbits.CCDPA0 // bit 0
10047 #define CCDPA1 CCDPAbits.CCDPA1 // bit 1
10048 #define CCDPA2 CCDPAbits.CCDPA2 // bit 2
10049 #define CCDPA4 CCDPAbits.CCDPA4 // bit 4
10050 #define CCDPA5 CCDPAbits.CCDPA5 // bit 5
10052 #define CCDPC0 CCDPCbits.CCDPC0 // bit 0
10053 #define CCDPC1 CCDPCbits.CCDPC1 // bit 1
10054 #define CCDPC2 CCDPCbits.CCDPC2 // bit 2
10055 #define CCDPC3 CCDPCbits.CCDPC3 // bit 3
10056 #define CCDPC4 CCDPCbits.CCDPC4 // bit 4
10057 #define CCDPC5 CCDPCbits.CCDPC5 // bit 5
10059 #define CCP1CTS0 CCP1CAPbits.CCP1CTS0 // bit 0
10060 #define CCP1CTS1 CCP1CAPbits.CCP1CTS1 // bit 1
10061 #define CCP1CTS2 CCP1CAPbits.CCP1CTS2 // bit 2
10062 #define CCP1CTS3 CCP1CAPbits.CCP1CTS3 // bit 3
10064 #define CCP1MODE0 CCP1CONbits.CCP1MODE0 // bit 0
10065 #define CCP1MODE1 CCP1CONbits.CCP1MODE1 // bit 1
10066 #define CCP1MODE2 CCP1CONbits.CCP1MODE2 // bit 2
10067 #define CCP1MODE3 CCP1CONbits.CCP1MODE3 // bit 3
10068 #define CCP1FMT CCP1CONbits.CCP1FMT // bit 4
10069 #define CCP1OUT CCP1CONbits.CCP1OUT // bit 5
10070 #define CCP1EN CCP1CONbits.CCP1EN // bit 7
10072 #define CCP1PPS0 CCP1PPSbits.CCP1PPS0 // bit 0
10073 #define CCP1PPS1 CCP1PPSbits.CCP1PPS1 // bit 1
10074 #define CCP1PPS2 CCP1PPSbits.CCP1PPS2 // bit 2
10075 #define CCP1PPS3 CCP1PPSbits.CCP1PPS3 // bit 3
10076 #define CCP1PPS4 CCP1PPSbits.CCP1PPS4 // bit 4
10078 #define CCP2CTS0 CCP2CAPbits.CCP2CTS0 // bit 0
10079 #define CCP2CTS1 CCP2CAPbits.CCP2CTS1 // bit 1
10080 #define CCP2CTS2 CCP2CAPbits.CCP2CTS2 // bit 2
10081 #define CCP2CTS3 CCP2CAPbits.CCP2CTS3 // bit 3
10083 #define CCP2MODE0 CCP2CONbits.CCP2MODE0 // bit 0
10084 #define CCP2MODE1 CCP2CONbits.CCP2MODE1 // bit 1
10085 #define CCP2MODE2 CCP2CONbits.CCP2MODE2 // bit 2
10086 #define CCP2MODE3 CCP2CONbits.CCP2MODE3 // bit 3
10087 #define CCP2FMT CCP2CONbits.CCP2FMT // bit 4
10088 #define CCP2OUT CCP2CONbits.CCP2OUT // bit 5
10089 #define CCP2EN CCP2CONbits.CCP2EN // bit 7
10091 #define CCP2PPS0 CCP2PPSbits.CCP2PPS0 // bit 0
10092 #define CCP2PPS1 CCP2PPSbits.CCP2PPS1 // bit 1
10093 #define CCP2PPS2 CCP2PPSbits.CCP2PPS2 // bit 2
10094 #define CCP2PPS3 CCP2PPSbits.CCP2PPS3 // bit 3
10095 #define CCP2PPS4 CCP2PPSbits.CCP2PPS4 // bit 4
10097 #define CCP3CTS0 CCP3CAPbits.CCP3CTS0 // bit 0
10098 #define CCP3CTS1 CCP3CAPbits.CCP3CTS1 // bit 1
10099 #define CCP3CTS2 CCP3CAPbits.CCP3CTS2 // bit 2
10100 #define CCP3CTS3 CCP3CAPbits.CCP3CTS3 // bit 3
10102 #define CCP3MODE0 CCP3CONbits.CCP3MODE0 // bit 0
10103 #define CCP3MODE1 CCP3CONbits.CCP3MODE1 // bit 1
10104 #define CCP3MODE2 CCP3CONbits.CCP3MODE2 // bit 2
10105 #define CCP3MODE3 CCP3CONbits.CCP3MODE3 // bit 3
10106 #define CCP3FMT CCP3CONbits.CCP3FMT // bit 4
10107 #define CCP3OUT CCP3CONbits.CCP3OUT // bit 5
10108 #define CCP3EN CCP3CONbits.CCP3EN // bit 7
10110 #define CCP3PPS0 CCP3PPSbits.CCP3PPS0 // bit 0
10111 #define CCP3PPS1 CCP3PPSbits.CCP3PPS1 // bit 1
10112 #define CCP3PPS2 CCP3PPSbits.CCP3PPS2 // bit 2
10113 #define CCP3PPS3 CCP3PPSbits.CCP3PPS3 // bit 3
10114 #define CCP3PPS4 CCP3PPSbits.CCP3PPS4 // bit 4
10116 #define CCP4CTS0 CCP4CAPbits.CCP4CTS0 // bit 0
10117 #define CCP4CTS1 CCP4CAPbits.CCP4CTS1 // bit 1
10118 #define CCP4CTS2 CCP4CAPbits.CCP4CTS2 // bit 2
10119 #define CCP4CTS3 CCP4CAPbits.CCP4CTS3 // bit 3
10121 #define CCP4MODE0 CCP4CONbits.CCP4MODE0 // bit 0
10122 #define CCP4MODE1 CCP4CONbits.CCP4MODE1 // bit 1
10123 #define CCP4MODE2 CCP4CONbits.CCP4MODE2 // bit 2
10124 #define CCP4MODE3 CCP4CONbits.CCP4MODE3 // bit 3
10125 #define CCP4FMT CCP4CONbits.CCP4FMT // bit 4
10126 #define CCP4OUT CCP4CONbits.CCP4OUT // bit 5
10127 #define CCP4EN CCP4CONbits.CCP4EN // bit 7
10129 #define CCP4PPS0 CCP4PPSbits.CCP4PPS0 // bit 0
10130 #define CCP4PPS1 CCP4PPSbits.CCP4PPS1 // bit 1
10131 #define CCP4PPS2 CCP4PPSbits.CCP4PPS2 // bit 2
10132 #define CCP4PPS3 CCP4PPSbits.CCP4PPS3 // bit 3
10133 #define CCP4PPS4 CCP4PPSbits.CCP4PPS4 // bit 4
10135 #define C1TSEL0 CCPTMRSbits.C1TSEL0 // bit 0
10136 #define C1TSEL1 CCPTMRSbits.C1TSEL1 // bit 1
10137 #define C2TSEL0 CCPTMRSbits.C2TSEL0 // bit 2
10138 #define C2TSEL1 CCPTMRSbits.C2TSEL1 // bit 3
10139 #define C3TSEL0 CCPTMRSbits.C3TSEL0 // bit 4
10140 #define C3TSEL1 CCPTMRSbits.C3TSEL1 // bit 5
10141 #define C4TSEL0 CCPTMRSbits.C4TSEL0 // bit 6
10142 #define C4TSEL1 CCPTMRSbits.C4TSEL1 // bit 7
10144 #define LC1MODE0 CLC1CONbits.LC1MODE0 // bit 0, shadows bit in CLC1CONbits
10145 #define MODE0 CLC1CONbits.MODE0 // bit 0, shadows bit in CLC1CONbits
10146 #define LC1MODE1 CLC1CONbits.LC1MODE1 // bit 1, shadows bit in CLC1CONbits
10147 #define MODE1 CLC1CONbits.MODE1 // bit 1, shadows bit in CLC1CONbits
10148 #define LC1MODE2 CLC1CONbits.LC1MODE2 // bit 2, shadows bit in CLC1CONbits
10149 #define MODE2 CLC1CONbits.MODE2 // bit 2, shadows bit in CLC1CONbits
10150 #define LC1INTN CLC1CONbits.LC1INTN // bit 3, shadows bit in CLC1CONbits
10151 #define INTN CLC1CONbits.INTN // bit 3, shadows bit in CLC1CONbits
10152 #define LC1INTP CLC1CONbits.LC1INTP // bit 4, shadows bit in CLC1CONbits
10153 #define INTP CLC1CONbits.INTP // bit 4, shadows bit in CLC1CONbits
10154 #define LC1OUT CLC1CONbits.LC1OUT // bit 5, shadows bit in CLC1CONbits
10155 #define OUT CLC1CONbits.OUT // bit 5, shadows bit in CLC1CONbits
10156 #define LC1EN CLC1CONbits.LC1EN // bit 7, shadows bit in CLC1CONbits
10157 #define EN CLC1CONbits.EN // bit 7, shadows bit in CLC1CONbits
10159 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
10160 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
10161 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
10162 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
10163 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
10164 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
10165 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
10166 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
10167 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
10168 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
10169 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
10170 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
10171 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
10172 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
10173 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
10174 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
10176 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
10177 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
10178 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
10179 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
10180 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
10181 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
10182 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
10183 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
10184 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
10185 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
10186 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
10187 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
10188 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
10189 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
10190 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
10191 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
10193 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
10194 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
10195 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
10196 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
10197 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
10198 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
10199 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
10200 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
10201 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
10202 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
10204 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
10205 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
10206 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
10207 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
10208 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
10209 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
10210 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
10211 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
10212 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
10213 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
10214 #define LC1D1S5 CLC1SEL0bits.LC1D1S5 // bit 5, shadows bit in CLC1SEL0bits
10215 #define D1S5 CLC1SEL0bits.D1S5 // bit 5, shadows bit in CLC1SEL0bits
10217 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
10218 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
10219 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
10220 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
10221 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
10222 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
10223 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
10224 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
10225 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
10226 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
10227 #define LC1D2S5 CLC1SEL1bits.LC1D2S5 // bit 5, shadows bit in CLC1SEL1bits
10228 #define D2S5 CLC1SEL1bits.D2S5 // bit 5, shadows bit in CLC1SEL1bits
10230 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
10231 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
10232 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
10233 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
10234 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
10235 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
10236 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
10237 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
10238 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
10239 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
10240 #define LC1D3S5 CLC1SEL2bits.LC1D3S5 // bit 5, shadows bit in CLC1SEL2bits
10241 #define D3S5 CLC1SEL2bits.D3S5 // bit 5, shadows bit in CLC1SEL2bits
10243 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
10244 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
10245 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
10246 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
10247 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
10248 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
10249 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
10250 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
10251 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
10252 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
10253 #define LC1D4S5 CLC1SEL3bits.LC1D4S5 // bit 5, shadows bit in CLC1SEL3bits
10254 #define D4S5 CLC1SEL3bits.D4S5 // bit 5, shadows bit in CLC1SEL3bits
10256 #define MLC1OUT CLCDATAbits.MLC1OUT // bit 0
10257 #define MLC2OUT CLCDATAbits.MLC2OUT // bit 1
10258 #define MLC3OUT CLCDATAbits.MLC3OUT // bit 2
10259 #define MLC4OUT CLCDATAbits.MLC4OUT // bit 3
10261 #define CLCIN0PPS0 CLCIN0PPSbits.CLCIN0PPS0 // bit 0
10262 #define CLCIN0PPS1 CLCIN0PPSbits.CLCIN0PPS1 // bit 1
10263 #define CLCIN0PPS2 CLCIN0PPSbits.CLCIN0PPS2 // bit 2
10264 #define CLCIN0PPS3 CLCIN0PPSbits.CLCIN0PPS3 // bit 3
10265 #define CLCIN0PPS4 CLCIN0PPSbits.CLCIN0PPS4 // bit 4
10267 #define CLCIN1PPS0 CLCIN1PPSbits.CLCIN1PPS0 // bit 0
10268 #define CLCIN1PPS1 CLCIN1PPSbits.CLCIN1PPS1 // bit 1
10269 #define CLCIN1PPS2 CLCIN1PPSbits.CLCIN1PPS2 // bit 2
10270 #define CLCIN1PPS3 CLCIN1PPSbits.CLCIN1PPS3 // bit 3
10271 #define CLCIN1PPS4 CLCIN1PPSbits.CLCIN1PPS4 // bit 4
10273 #define CLCIN2PPS0 CLCIN2PPSbits.CLCIN2PPS0 // bit 0
10274 #define CLCIN2PPS1 CLCIN2PPSbits.CLCIN2PPS1 // bit 1
10275 #define CLCIN2PPS2 CLCIN2PPSbits.CLCIN2PPS2 // bit 2
10276 #define CLCIN2PPS3 CLCIN2PPSbits.CLCIN2PPS3 // bit 3
10277 #define CLCIN2PPS4 CLCIN2PPSbits.CLCIN2PPS4 // bit 4
10279 #define CLCIN3PPS0 CLCIN3PPSbits.CLCIN3PPS0 // bit 0
10280 #define CLCIN3PPS1 CLCIN3PPSbits.CLCIN3PPS1 // bit 1
10281 #define CLCIN3PPS2 CLCIN3PPSbits.CLCIN3PPS2 // bit 2
10282 #define CLCIN3PPS3 CLCIN3PPSbits.CLCIN3PPS3 // bit 3
10283 #define CLCIN3PPS4 CLCIN3PPSbits.CLCIN3PPS4 // bit 4
10285 #define CLKRDIV0 CLKRCONbits.CLKRDIV0 // bit 0
10286 #define CLKRDIV1 CLKRCONbits.CLKRDIV1 // bit 1
10287 #define CLKRDIV2 CLKRCONbits.CLKRDIV2 // bit 2
10288 #define CLKRDC0 CLKRCONbits.CLKRDC0 // bit 3
10289 #define CLKRDC1 CLKRCONbits.CLKRDC1 // bit 4
10290 #define CLKREN CLKRCONbits.CLKREN // bit 7
10292 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
10293 #define C1HYS CM1CON0bits.C1HYS // bit 1
10294 #define C1SP CM1CON0bits.C1SP // bit 2
10295 #define C1POL CM1CON0bits.C1POL // bit 4
10296 #define C1OUT CM1CON0bits.C1OUT // bit 6
10297 #define C1ON CM1CON0bits.C1ON // bit 7
10299 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
10300 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
10301 #define C1NCH2 CM1CON1bits.C1NCH2 // bit 2
10302 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 3
10303 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 4
10304 #define C1PCH2 CM1CON1bits.C1PCH2 // bit 5
10305 #define C1INTN CM1CON1bits.C1INTN // bit 6
10306 #define C1INTP CM1CON1bits.C1INTP // bit 7
10308 #define C2SYNC CM2CON0bits.C2SYNC // bit 0
10309 #define C2HYS CM2CON0bits.C2HYS // bit 1
10310 #define C2SP CM2CON0bits.C2SP // bit 2
10311 #define C2POL CM2CON0bits.C2POL // bit 4
10312 #define C2OUT CM2CON0bits.C2OUT // bit 6
10313 #define C2ON CM2CON0bits.C2ON // bit 7
10315 #define C2NCH0 CM2CON1bits.C2NCH0 // bit 0
10316 #define C2NCH1 CM2CON1bits.C2NCH1 // bit 1
10317 #define C2NCH2 CM2CON1bits.C2NCH2 // bit 2
10318 #define C2PCH0 CM2CON1bits.C2PCH0 // bit 3
10319 #define C2PCH1 CM2CON1bits.C2PCH1 // bit 4
10320 #define C2PCH2 CM2CON1bits.C2PCH2 // bit 5
10321 #define C2INTN CM2CON1bits.C2INTN // bit 6
10322 #define C2INTP CM2CON1bits.C2INTP // bit 7
10324 #define MC1OUT CMOUTbits.MC1OUT // bit 0
10325 #define MC2OUT CMOUTbits.MC2OUT // bit 1
10327 #define DOZE0 CPUDOZEbits.DOZE0 // bit 0
10328 #define DOZE1 CPUDOZEbits.DOZE1 // bit 1
10329 #define DOZE2 CPUDOZEbits.DOZE2 // bit 2
10330 #define DOE CPUDOZEbits.DOE // bit 4
10331 #define ROI CPUDOZEbits.ROI // bit 5
10332 #define DOZEN CPUDOZEbits.DOZEN // bit 6
10333 #define IDLEN CPUDOZEbits.IDLEN // bit 7
10335 #define LSAC0 CWG1AS0bits.LSAC0 // bit 2, shadows bit in CWG1AS0bits
10336 #define CWG1LSAC0 CWG1AS0bits.CWG1LSAC0 // bit 2, shadows bit in CWG1AS0bits
10337 #define LSAC1 CWG1AS0bits.LSAC1 // bit 3, shadows bit in CWG1AS0bits
10338 #define CWG1LSAC1 CWG1AS0bits.CWG1LSAC1 // bit 3, shadows bit in CWG1AS0bits
10339 #define LSBD0 CWG1AS0bits.LSBD0 // bit 4, shadows bit in CWG1AS0bits
10340 #define CWG1LSBD0 CWG1AS0bits.CWG1LSBD0 // bit 4, shadows bit in CWG1AS0bits
10341 #define LSBD1 CWG1AS0bits.LSBD1 // bit 5, shadows bit in CWG1AS0bits
10342 #define CWG1LSBD1 CWG1AS0bits.CWG1LSBD1 // bit 5, shadows bit in CWG1AS0bits
10343 #define REN CWG1AS0bits.REN // bit 6, shadows bit in CWG1AS0bits
10344 #define CWG1REN CWG1AS0bits.CWG1REN // bit 6, shadows bit in CWG1AS0bits
10345 #define SHUTDOWN CWG1AS0bits.SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
10346 #define CWG1SHUTDOWN CWG1AS0bits.CWG1SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
10348 #define AS0E CWG1AS1bits.AS0E // bit 0
10349 #define AS1E CWG1AS1bits.AS1E // bit 1
10350 #define AS2E CWG1AS1bits.AS2E // bit 2
10351 #define AS3E CWG1AS1bits.AS3E // bit 3
10352 #define AS4E CWG1AS1bits.AS4E // bit 4
10354 #define CS CWG1CLKCONbits.CS // bit 0, shadows bit in CWG1CLKCONbits
10355 #define CWG1CS CWG1CLKCONbits.CWG1CS // bit 0, shadows bit in CWG1CLKCONbits
10357 #define POLA CWG1CON1bits.POLA // bit 0, shadows bit in CWG1CON1bits
10358 #define CWG1POLA CWG1CON1bits.CWG1POLA // bit 0, shadows bit in CWG1CON1bits
10359 #define POLB CWG1CON1bits.POLB // bit 1, shadows bit in CWG1CON1bits
10360 #define CWG1POLB CWG1CON1bits.CWG1POLB // bit 1, shadows bit in CWG1CON1bits
10361 #define POLC CWG1CON1bits.POLC // bit 2, shadows bit in CWG1CON1bits
10362 #define CWG1POLC CWG1CON1bits.CWG1POLC // bit 2, shadows bit in CWG1CON1bits
10363 #define POLD CWG1CON1bits.POLD // bit 3, shadows bit in CWG1CON1bits
10364 #define CWG1POLD CWG1CON1bits.CWG1POLD // bit 3, shadows bit in CWG1CON1bits
10365 #define IN CWG1CON1bits.IN // bit 5, shadows bit in CWG1CON1bits
10366 #define CWG1IN CWG1CON1bits.CWG1IN // bit 5, shadows bit in CWG1CON1bits
10368 #define CWG1DAT0 CWG1DATbits.CWG1DAT0 // bit 0
10369 #define CWG1DAT1 CWG1DATbits.CWG1DAT1 // bit 1
10370 #define CWG1DAT2 CWG1DATbits.CWG1DAT2 // bit 2
10371 #define CWG1DAT3 CWG1DATbits.CWG1DAT3 // bit 3
10373 #define DBF0 CWG1DBFbits.DBF0 // bit 0, shadows bit in CWG1DBFbits
10374 #define CWG1DBF0 CWG1DBFbits.CWG1DBF0 // bit 0, shadows bit in CWG1DBFbits
10375 #define DBF1 CWG1DBFbits.DBF1 // bit 1, shadows bit in CWG1DBFbits
10376 #define CWG1DBF1 CWG1DBFbits.CWG1DBF1 // bit 1, shadows bit in CWG1DBFbits
10377 #define DBF2 CWG1DBFbits.DBF2 // bit 2, shadows bit in CWG1DBFbits
10378 #define CWG1DBF2 CWG1DBFbits.CWG1DBF2 // bit 2, shadows bit in CWG1DBFbits
10379 #define DBF3 CWG1DBFbits.DBF3 // bit 3, shadows bit in CWG1DBFbits
10380 #define CWG1DBF3 CWG1DBFbits.CWG1DBF3 // bit 3, shadows bit in CWG1DBFbits
10381 #define DBF4 CWG1DBFbits.DBF4 // bit 4, shadows bit in CWG1DBFbits
10382 #define CWG1DBF4 CWG1DBFbits.CWG1DBF4 // bit 4, shadows bit in CWG1DBFbits
10383 #define DBF5 CWG1DBFbits.DBF5 // bit 5, shadows bit in CWG1DBFbits
10384 #define CWG1DBF5 CWG1DBFbits.CWG1DBF5 // bit 5, shadows bit in CWG1DBFbits
10386 #define DBR0 CWG1DBRbits.DBR0 // bit 0, shadows bit in CWG1DBRbits
10387 #define CWG1DBR0 CWG1DBRbits.CWG1DBR0 // bit 0, shadows bit in CWG1DBRbits
10388 #define DBR1 CWG1DBRbits.DBR1 // bit 1, shadows bit in CWG1DBRbits
10389 #define CWG1DBR1 CWG1DBRbits.CWG1DBR1 // bit 1, shadows bit in CWG1DBRbits
10390 #define DBR2 CWG1DBRbits.DBR2 // bit 2, shadows bit in CWG1DBRbits
10391 #define CWG1DBR2 CWG1DBRbits.CWG1DBR2 // bit 2, shadows bit in CWG1DBRbits
10392 #define DBR3 CWG1DBRbits.DBR3 // bit 3, shadows bit in CWG1DBRbits
10393 #define CWG1DBR3 CWG1DBRbits.CWG1DBR3 // bit 3, shadows bit in CWG1DBRbits
10394 #define DBR4 CWG1DBRbits.DBR4 // bit 4, shadows bit in CWG1DBRbits
10395 #define CWG1DBR4 CWG1DBRbits.CWG1DBR4 // bit 4, shadows bit in CWG1DBRbits
10396 #define DBR5 CWG1DBRbits.DBR5 // bit 5, shadows bit in CWG1DBRbits
10397 #define CWG1DBR5 CWG1DBRbits.CWG1DBR5 // bit 5, shadows bit in CWG1DBRbits
10399 #define CWG1PPS0 CWG1PPSbits.CWG1PPS0 // bit 0
10400 #define CWG1PPS1 CWG1PPSbits.CWG1PPS1 // bit 1
10401 #define CWG1PPS2 CWG1PPSbits.CWG1PPS2 // bit 2
10402 #define CWG1PPS3 CWG1PPSbits.CWG1PPS3 // bit 3
10403 #define CWG1PPS4 CWG1PPSbits.CWG1PPS4 // bit 4
10405 #define STRA CWG1STRbits.STRA // bit 0, shadows bit in CWG1STRbits
10406 #define CWG1STRA CWG1STRbits.CWG1STRA // bit 0, shadows bit in CWG1STRbits
10407 #define STRB CWG1STRbits.STRB // bit 1, shadows bit in CWG1STRbits
10408 #define CWG1STRB CWG1STRbits.CWG1STRB // bit 1, shadows bit in CWG1STRbits
10409 #define STRC CWG1STRbits.STRC // bit 2, shadows bit in CWG1STRbits
10410 #define CWG1STRC CWG1STRbits.CWG1STRC // bit 2, shadows bit in CWG1STRbits
10411 #define STRD CWG1STRbits.STRD // bit 3, shadows bit in CWG1STRbits
10412 #define CWG1STRD CWG1STRbits.CWG1STRD // bit 3, shadows bit in CWG1STRbits
10413 #define OVRA CWG1STRbits.OVRA // bit 4, shadows bit in CWG1STRbits
10414 #define CWG1OVRA CWG1STRbits.CWG1OVRA // bit 4, shadows bit in CWG1STRbits
10415 #define OVRB CWG1STRbits.OVRB // bit 5, shadows bit in CWG1STRbits
10416 #define CWG1OVRB CWG1STRbits.CWG1OVRB // bit 5, shadows bit in CWG1STRbits
10417 #define OVRC CWG1STRbits.OVRC // bit 6, shadows bit in CWG1STRbits
10418 #define CWG1OVRC CWG1STRbits.CWG1OVRC // bit 6, shadows bit in CWG1STRbits
10419 #define OVRD CWG1STRbits.OVRD // bit 7, shadows bit in CWG1STRbits
10420 #define CWG1OVRD CWG1STRbits.CWG1OVRD // bit 7, shadows bit in CWG1STRbits
10422 #define CWG2DAT0 CWG2DATbits.CWG2DAT0 // bit 0
10423 #define CWG2DAT1 CWG2DATbits.CWG2DAT1 // bit 1
10424 #define CWG2DAT2 CWG2DATbits.CWG2DAT2 // bit 2
10425 #define CWG2DAT3 CWG2DATbits.CWG2DAT3 // bit 3
10427 #define CWG2PPS0 CWG2PPSbits.CWG2PPS0 // bit 0
10428 #define CWG2PPS1 CWG2PPSbits.CWG2PPS1 // bit 1
10429 #define CWG2PPS2 CWG2PPSbits.CWG2PPS2 // bit 2
10430 #define CWG2PPS3 CWG2PPSbits.CWG2PPS3 // bit 3
10431 #define CWG2PPS4 CWG2PPSbits.CWG2PPS4 // bit 4
10433 #define DAC1NSS DACCON0bits.DAC1NSS // bit 0
10434 #define DAC1PSS0 DACCON0bits.DAC1PSS0 // bit 2
10435 #define DAC1PSS1 DACCON0bits.DAC1PSS1 // bit 3
10436 #define DAC1OE DACCON0bits.DAC1OE // bit 5
10437 #define DAC1EN DACCON0bits.DAC1EN // bit 7
10439 #define DAC1R0 DACCON1bits.DAC1R0 // bit 0
10440 #define DAC1R1 DACCON1bits.DAC1R1 // bit 1
10441 #define DAC1R2 DACCON1bits.DAC1R2 // bit 2
10442 #define DAC1R3 DACCON1bits.DAC1R3 // bit 3
10443 #define DAC1R4 DACCON1bits.DAC1R4 // bit 4
10445 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
10446 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
10447 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
10448 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
10449 #define TSRNG FVRCONbits.TSRNG // bit 4
10450 #define TSEN FVRCONbits.TSEN // bit 5
10451 #define FVRRDY FVRCONbits.FVRRDY // bit 6
10452 #define FVREN FVRCONbits.FVREN // bit 7
10454 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
10455 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
10456 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
10457 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
10458 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
10459 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
10461 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
10462 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
10463 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
10464 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
10465 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
10466 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
10468 #define INTEDG INTCONbits.INTEDG // bit 0
10469 #define PEIE INTCONbits.PEIE // bit 6
10470 #define GIE INTCONbits.GIE // bit 7
10472 #define INTPPS0 INTPPSbits.INTPPS0 // bit 0
10473 #define INTPPS1 INTPPSbits.INTPPS1 // bit 1
10474 #define INTPPS2 INTPPSbits.INTPPS2 // bit 2
10475 #define INTPPS3 INTPPSbits.INTPPS3 // bit 3
10476 #define INTPPS4 INTPPSbits.INTPPS4 // bit 4
10478 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
10479 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
10480 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
10481 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
10482 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
10483 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
10485 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
10486 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
10487 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
10488 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
10489 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
10490 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
10492 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
10493 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
10494 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
10495 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
10496 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
10497 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
10499 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
10500 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
10501 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
10502 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
10503 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
10504 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
10506 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
10507 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
10508 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
10509 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
10510 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
10511 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
10513 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
10514 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
10515 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
10516 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
10517 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
10518 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
10520 #define LATA0 LATAbits.LATA0 // bit 0
10521 #define LATA1 LATAbits.LATA1 // bit 1
10522 #define LATA2 LATAbits.LATA2 // bit 2
10523 #define LATA4 LATAbits.LATA4 // bit 4
10524 #define LATA5 LATAbits.LATA5 // bit 5
10526 #define LATC0 LATCbits.LATC0 // bit 0
10527 #define LATC1 LATCbits.LATC1 // bit 1
10528 #define LATC2 LATCbits.LATC2 // bit 2
10529 #define LATC3 LATCbits.LATC3 // bit 3
10530 #define LATC4 LATCbits.LATC4 // bit 4
10531 #define LATC5 LATCbits.LATC5 // bit 5
10533 #define MDCH0 MDCARHbits.MDCH0 // bit 0
10534 #define MDCH1 MDCARHbits.MDCH1 // bit 1
10535 #define MDCH2 MDCARHbits.MDCH2 // bit 2
10536 #define MDCH3 MDCARHbits.MDCH3 // bit 3
10537 #define MDCHSYNC MDCARHbits.MDCHSYNC // bit 5
10538 #define MDCHPOL MDCARHbits.MDCHPOL // bit 6
10540 #define MDCL0 MDCARLbits.MDCL0 // bit 0
10541 #define MDCL1 MDCARLbits.MDCL1 // bit 1
10542 #define MDCL2 MDCARLbits.MDCL2 // bit 2
10543 #define MDCL3 MDCARLbits.MDCL3 // bit 3
10544 #define MDCLSYNC MDCARLbits.MDCLSYNC // bit 5
10545 #define MDCLPOL MDCARLbits.MDCLPOL // bit 6
10547 #define MDCIN1PPS0 MDCIN1PPSbits.MDCIN1PPS0 // bit 0
10548 #define MDCIN1PPS1 MDCIN1PPSbits.MDCIN1PPS1 // bit 1
10549 #define MDCIN1PPS2 MDCIN1PPSbits.MDCIN1PPS2 // bit 2
10550 #define MDCIN1PPS3 MDCIN1PPSbits.MDCIN1PPS3 // bit 3
10551 #define MDCIN1PPS4 MDCIN1PPSbits.MDCIN1PPS4 // bit 4
10553 #define MDCIN2PPS0 MDCIN2PPSbits.MDCIN2PPS0 // bit 0
10554 #define MDCIN2PPS1 MDCIN2PPSbits.MDCIN2PPS1 // bit 1
10555 #define MDCIN2PPS2 MDCIN2PPSbits.MDCIN2PPS2 // bit 2
10556 #define MDCIN2PPS3 MDCIN2PPSbits.MDCIN2PPS3 // bit 3
10557 #define MDCIN2PPS4 MDCIN2PPSbits.MDCIN2PPS4 // bit 4
10559 #define MDBIT MDCONbits.MDBIT // bit 0
10560 #define MDOUT MDCONbits.MDOUT // bit 3
10561 #define MDOPOL MDCONbits.MDOPOL // bit 4
10562 #define MDEN MDCONbits.MDEN // bit 7
10564 #define MDMINPPS0 MDMINPPSbits.MDMINPPS0 // bit 0
10565 #define MDMINPPS1 MDMINPPSbits.MDMINPPS1 // bit 1
10566 #define MDMINPPS2 MDMINPPSbits.MDMINPPS2 // bit 2
10567 #define MDMINPPS3 MDMINPPSbits.MDMINPPS3 // bit 3
10568 #define MDMINPPS4 MDMINPPSbits.MDMINPPS4 // bit 4
10570 #define MDMS0 MDSRCbits.MDMS0 // bit 0
10571 #define MDMS1 MDSRCbits.MDMS1 // bit 1
10572 #define MDMS2 MDSRCbits.MDMS2 // bit 2
10573 #define MDMS3 MDSRCbits.MDMS3 // bit 3
10575 #define N1PFM NCO1CONbits.N1PFM // bit 0
10576 #define N1POL NCO1CONbits.N1POL // bit 4
10577 #define N1OUT NCO1CONbits.N1OUT // bit 5
10578 #define N1EN NCO1CONbits.N1EN // bit 7
10580 #define NVMADR8 NVMADRHbits.NVMADR8 // bit 0
10581 #define NVMADR9 NVMADRHbits.NVMADR9 // bit 1
10582 #define NVMADR10 NVMADRHbits.NVMADR10 // bit 2
10583 #define NVMADR11 NVMADRHbits.NVMADR11 // bit 3
10584 #define NVMADR12 NVMADRHbits.NVMADR12 // bit 4
10585 #define NVMADR13 NVMADRHbits.NVMADR13 // bit 5
10586 #define NVMADR14 NVMADRHbits.NVMADR14 // bit 6
10588 #define NVMADR0 NVMADRLbits.NVMADR0 // bit 0
10589 #define NVMADR1 NVMADRLbits.NVMADR1 // bit 1
10590 #define NVMADR2 NVMADRLbits.NVMADR2 // bit 2
10591 #define NVMADR3 NVMADRLbits.NVMADR3 // bit 3
10592 #define NVMADR4 NVMADRLbits.NVMADR4 // bit 4
10593 #define NVMADR5 NVMADRLbits.NVMADR5 // bit 5
10594 #define NVMADR6 NVMADRLbits.NVMADR6 // bit 6
10595 #define NVMADR7 NVMADRLbits.NVMADR7 // bit 7
10597 #define RD NVMCON1bits.RD // bit 0
10598 #define WR NVMCON1bits.WR // bit 1
10599 #define WREN NVMCON1bits.WREN // bit 2
10600 #define WRERR NVMCON1bits.WRERR // bit 3
10601 #define FREE NVMCON1bits.FREE // bit 4
10602 #define LWLO NVMCON1bits.LWLO // bit 5
10603 #define NVMREGS NVMCON1bits.NVMREGS // bit 6
10605 #define NVMDAT8 NVMDATHbits.NVMDAT8 // bit 0
10606 #define NVMDAT9 NVMDATHbits.NVMDAT9 // bit 1
10607 #define NVMDAT10 NVMDATHbits.NVMDAT10 // bit 2
10608 #define NVMDAT11 NVMDATHbits.NVMDAT11 // bit 3
10609 #define NVMDAT12 NVMDATHbits.NVMDAT12 // bit 4
10610 #define NVMDAT13 NVMDATHbits.NVMDAT13 // bit 5
10612 #define NVMDAT0 NVMDATLbits.NVMDAT0 // bit 0
10613 #define NVMDAT1 NVMDATLbits.NVMDAT1 // bit 1
10614 #define NVMDAT2 NVMDATLbits.NVMDAT2 // bit 2
10615 #define NVMDAT3 NVMDATLbits.NVMDAT3 // bit 3
10616 #define NVMDAT4 NVMDATLbits.NVMDAT4 // bit 4
10617 #define NVMDAT5 NVMDATLbits.NVMDAT5 // bit 5
10618 #define NVMDAT6 NVMDATLbits.NVMDAT6 // bit 6
10619 #define NVMDAT7 NVMDATLbits.NVMDAT7 // bit 7
10621 #define ODCA0 ODCONAbits.ODCA0 // bit 0
10622 #define ODCA1 ODCONAbits.ODCA1 // bit 1
10623 #define ODCA2 ODCONAbits.ODCA2 // bit 2
10624 #define ODCA4 ODCONAbits.ODCA4 // bit 4
10625 #define ODCA5 ODCONAbits.ODCA5 // bit 5
10627 #define ODCC0 ODCONCbits.ODCC0 // bit 0
10628 #define ODCC1 ODCONCbits.ODCC1 // bit 1
10629 #define ODCC2 ODCONCbits.ODCC2 // bit 2
10630 #define ODCC3 ODCONCbits.ODCC3 // bit 3
10631 #define ODCC4 ODCONCbits.ODCC4 // bit 4
10632 #define ODCC5 ODCONCbits.ODCC5 // bit 5
10634 #define NDIV0 OSCCON1bits.NDIV0 // bit 0
10635 #define NDIV1 OSCCON1bits.NDIV1 // bit 1
10636 #define NDIV2 OSCCON1bits.NDIV2 // bit 2
10637 #define NDIV3 OSCCON1bits.NDIV3 // bit 3
10638 #define NOSC0 OSCCON1bits.NOSC0 // bit 4
10639 #define NOSC1 OSCCON1bits.NOSC1 // bit 5
10640 #define NOSC2 OSCCON1bits.NOSC2 // bit 6
10642 #define CDIV0 OSCCON2bits.CDIV0 // bit 0
10643 #define CDIV1 OSCCON2bits.CDIV1 // bit 1
10644 #define CDIV2 OSCCON2bits.CDIV2 // bit 2
10645 #define CDIV3 OSCCON2bits.CDIV3 // bit 3
10646 #define COSC0 OSCCON2bits.COSC0 // bit 4
10647 #define COSC1 OSCCON2bits.COSC1 // bit 5
10648 #define COSC2 OSCCON2bits.COSC2 // bit 6
10650 #define NOSCR OSCCON3bits.NOSCR // bit 3
10651 #define ORDY OSCCON3bits.ORDY // bit 4
10652 #define SOSCBE OSCCON3bits.SOSCBE // bit 5
10653 #define SOSCPWR OSCCON3bits.SOSCPWR // bit 6
10654 #define CSWHOLD OSCCON3bits.CSWHOLD // bit 7
10656 #define ADOEN OSCENbits.ADOEN // bit 2
10657 #define SOSCEN OSCENbits.SOSCEN // bit 3
10658 #define LFOEN OSCENbits.LFOEN // bit 4
10659 #define HFOEN OSCENbits.HFOEN // bit 6
10660 #define EXTOEN OSCENbits.EXTOEN // bit 7
10662 #define HFFRQ0 OSCFRQbits.HFFRQ0 // bit 0
10663 #define HFFRQ1 OSCFRQbits.HFFRQ1 // bit 1
10664 #define HFFRQ2 OSCFRQbits.HFFRQ2 // bit 2
10665 #define HFFRQ3 OSCFRQbits.HFFRQ3 // bit 3
10667 #define PLLR OSCSTAT1bits.PLLR // bit 0
10668 #define ADOR OSCSTAT1bits.ADOR // bit 2
10669 #define SOR OSCSTAT1bits.SOR // bit 3
10670 #define LFOR OSCSTAT1bits.LFOR // bit 4
10671 #define HFOR OSCSTAT1bits.HFOR // bit 6
10672 #define EXTOR OSCSTAT1bits.EXTOR // bit 7
10674 #define HFTUN0 OSCTUNEbits.HFTUN0 // bit 0
10675 #define HFTUN1 OSCTUNEbits.HFTUN1 // bit 1
10676 #define HFTUN2 OSCTUNEbits.HFTUN2 // bit 2
10677 #define HFTUN3 OSCTUNEbits.HFTUN3 // bit 3
10678 #define HFTUN4 OSCTUNEbits.HFTUN4 // bit 4
10679 #define HFTUN5 OSCTUNEbits.HFTUN5 // bit 5
10681 #define NOT_BOR PCON0bits.NOT_BOR // bit 0
10682 #define NOT_POR PCON0bits.NOT_POR // bit 1
10683 #define NOT_RI PCON0bits.NOT_RI // bit 2
10684 #define NOT_RMCLR PCON0bits.NOT_RMCLR // bit 3
10685 #define NOT_RWDT PCON0bits.NOT_RWDT // bit 4
10686 #define STKUNF PCON0bits.STKUNF // bit 6
10687 #define STKOVF PCON0bits.STKOVF // bit 7
10689 #define INTE PIE0bits.INTE // bit 0
10690 #define IOCIE PIE0bits.IOCIE // bit 4
10691 #define TMR0IE PIE0bits.TMR0IE // bit 5
10693 #define TMR1IE PIE1bits.TMR1IE // bit 0
10694 #define TMR2IE PIE1bits.TMR2IE // bit 1
10695 #define BCL1IE PIE1bits.BCL1IE // bit 2
10696 #define SSP1IE PIE1bits.SSP1IE // bit 3
10697 #define TXIE PIE1bits.TXIE // bit 4
10698 #define RCIE PIE1bits.RCIE // bit 5
10699 #define ADIE PIE1bits.ADIE // bit 6
10700 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
10702 #define NCO1IE PIE2bits.NCO1IE // bit 0
10703 #define TMR4IE PIE2bits.TMR4IE // bit 1
10704 #define NVMIE PIE2bits.NVMIE // bit 4
10705 #define C1IE PIE2bits.C1IE // bit 5
10706 #define C2IE PIE2bits.C2IE // bit 6
10707 #define TMR6IE PIE2bits.TMR6IE // bit 7
10709 #define CLC1IE PIE3bits.CLC1IE // bit 0
10710 #define CLC2IE PIE3bits.CLC2IE // bit 1
10711 #define CLC3IE PIE3bits.CLC3IE // bit 2
10712 #define CLC4IE PIE3bits.CLC4IE // bit 3
10713 #define TMR3IE PIE3bits.TMR3IE // bit 4
10714 #define TMR3GIE PIE3bits.TMR3GIE // bit 5
10715 #define CSWIE PIE3bits.CSWIE // bit 6
10716 #define OSFIE PIE3bits.OSFIE // bit 7
10718 #define CCP1IE PIE4bits.CCP1IE // bit 0
10719 #define CCP2IE PIE4bits.CCP2IE // bit 1
10720 #define CCP3IE PIE4bits.CCP3IE // bit 2
10721 #define CCP4IE PIE4bits.CCP4IE // bit 3
10722 #define TMR5IE PIE4bits.TMR5IE // bit 4
10723 #define TMR5GIE PIE4bits.TMR5GIE // bit 5
10724 #define CWG1IE PIE4bits.CWG1IE // bit 6
10725 #define CWG2IE PIE4bits.CWG2IE // bit 7
10727 #define INTF PIR0bits.INTF // bit 0
10728 #define IOCIF PIR0bits.IOCIF // bit 4
10729 #define TMR0IF PIR0bits.TMR0IF // bit 5
10731 #define TMR1IF PIR1bits.TMR1IF // bit 0
10732 #define TMR2IF PIR1bits.TMR2IF // bit 1
10733 #define BCL1IF PIR1bits.BCL1IF // bit 2
10734 #define SSP1IF PIR1bits.SSP1IF // bit 3
10735 #define TXIF PIR1bits.TXIF // bit 4
10736 #define RCIF PIR1bits.RCIF // bit 5
10737 #define ADIF PIR1bits.ADIF // bit 6
10738 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
10740 #define NCO1IF PIR2bits.NCO1IF // bit 0
10741 #define TMR4IF PIR2bits.TMR4IF // bit 1
10742 #define NVMIF PIR2bits.NVMIF // bit 4
10743 #define C1IF PIR2bits.C1IF // bit 5
10744 #define C2IF PIR2bits.C2IF // bit 6
10745 #define TMR6IF PIR2bits.TMR6IF // bit 7
10747 #define CLC1IF PIR3bits.CLC1IF // bit 0
10748 #define CLC2IF PIR3bits.CLC2IF // bit 1
10749 #define CLC3IF PIR3bits.CLC3IF // bit 2
10750 #define CLC4IF PIR3bits.CLC4IF // bit 3
10751 #define TMR3IF PIR3bits.TMR3IF // bit 4
10752 #define TMR3GIF PIR3bits.TMR3GIF // bit 5
10753 #define CSWIF PIR3bits.CSWIF // bit 6
10754 #define OSFIF PIR3bits.OSFIF // bit 7
10756 #define CCP1IF PIR4bits.CCP1IF // bit 0
10757 #define CCP2IF PIR4bits.CCP2IF // bit 1
10758 #define CCP3IF PIR4bits.CCP3IF // bit 2
10759 #define CCP4IF PIR4bits.CCP4IF // bit 3
10760 #define TMR5IF PIR4bits.TMR5IF // bit 4
10761 #define TMR5GIF PIR4bits.TMR5GIF // bit 5
10762 #define CWG1IF PIR4bits.CWG1IF // bit 6
10763 #define CWG2IF PIR4bits.CWG2IF // bit 7
10765 #define IOCMD PMD0bits.IOCMD // bit 0
10766 #define CLKRMD PMD0bits.CLKRMD // bit 1
10767 #define NVMMD PMD0bits.NVMMD // bit 2
10768 #define FVRMD PMD0bits.FVRMD // bit 6
10769 #define SYSCMD PMD0bits.SYSCMD // bit 7
10771 #define TMR0MD PMD1bits.TMR0MD // bit 0
10772 #define TMR1MD PMD1bits.TMR1MD // bit 1
10773 #define TMR2MD PMD1bits.TMR2MD // bit 2
10774 #define TMR3MD PMD1bits.TMR3MD // bit 3
10775 #define TMR4MD PMD1bits.TMR4MD // bit 4
10776 #define TMR5MD PMD1bits.TMR5MD // bit 5
10777 #define TMR6MD PMD1bits.TMR6MD // bit 6
10778 #define NCOMD PMD1bits.NCOMD // bit 7
10780 #define CMP1MD PMD2bits.CMP1MD // bit 1
10781 #define CMP2MD PMD2bits.CMP2MD // bit 2
10782 #define ADCMD PMD2bits.ADCMD // bit 5
10783 #define DACMD PMD2bits.DACMD // bit 6
10785 #define CCP1MD PMD3bits.CCP1MD // bit 0
10786 #define CCP2MD PMD3bits.CCP2MD // bit 1
10787 #define CCP3MD PMD3bits.CCP3MD // bit 2
10788 #define CCP4MD PMD3bits.CCP4MD // bit 3
10789 #define PWM5MD PMD3bits.PWM5MD // bit 4
10790 #define PWM6MD PMD3bits.PWM6MD // bit 5
10791 #define CWG1MD PMD3bits.CWG1MD // bit 6
10792 #define CWG2MD PMD3bits.CWG2MD // bit 7
10794 #define MSSP1MD PMD4bits.MSSP1MD // bit 1
10795 #define UART1MD PMD4bits.UART1MD // bit 5
10797 #define DSMMD PMD5bits.DSMMD // bit 0
10798 #define CLC1MD PMD5bits.CLC1MD // bit 1
10799 #define CLC2MD PMD5bits.CLC2MD // bit 2
10800 #define CLC3MD PMD5bits.CLC3MD // bit 3
10801 #define CLC4MD PMD5bits.CLC4MD // bit 4
10803 #define RA0 PORTAbits.RA0 // bit 0
10804 #define RA1 PORTAbits.RA1 // bit 1
10805 #define RA2 PORTAbits.RA2 // bit 2
10806 #define RA3 PORTAbits.RA3 // bit 3
10807 #define RA4 PORTAbits.RA4 // bit 4
10808 #define RA5 PORTAbits.RA5 // bit 5
10810 #define RC0 PORTCbits.RC0 // bit 0
10811 #define RC1 PORTCbits.RC1 // bit 1
10812 #define RC2 PORTCbits.RC2 // bit 2
10813 #define RC3 PORTCbits.RC3 // bit 3
10814 #define RC4 PORTCbits.RC4 // bit 4
10815 #define RC5 PORTCbits.RC5 // bit 5
10817 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
10819 #define PWM5POL PWM5CONbits.PWM5POL // bit 4
10820 #define PWM5OUT PWM5CONbits.PWM5OUT // bit 5
10821 #define PWM5EN PWM5CONbits.PWM5EN // bit 7
10823 #define PWM5DCH0 PWM5DCHbits.PWM5DCH0 // bit 0
10824 #define PWM5DCH1 PWM5DCHbits.PWM5DCH1 // bit 1
10825 #define PWM5DCH2 PWM5DCHbits.PWM5DCH2 // bit 2
10826 #define PWM5DCH3 PWM5DCHbits.PWM5DCH3 // bit 3
10827 #define PWM5DCH4 PWM5DCHbits.PWM5DCH4 // bit 4
10828 #define PWM5DCH5 PWM5DCHbits.PWM5DCH5 // bit 5
10829 #define PWM5DCH6 PWM5DCHbits.PWM5DCH6 // bit 6
10830 #define PWM5DCH7 PWM5DCHbits.PWM5DCH7 // bit 7
10832 #define PWM5DCL0 PWM5DCLbits.PWM5DCL0 // bit 6
10833 #define PWM5DCL1 PWM5DCLbits.PWM5DCL1 // bit 7
10835 #define PWM6POL PWM6CONbits.PWM6POL // bit 4
10836 #define PWM6OUT PWM6CONbits.PWM6OUT // bit 5
10837 #define PWM6EN PWM6CONbits.PWM6EN // bit 7
10839 #define PWM6DCH0 PWM6DCHbits.PWM6DCH0 // bit 0
10840 #define PWM6DCH1 PWM6DCHbits.PWM6DCH1 // bit 1
10841 #define PWM6DCH2 PWM6DCHbits.PWM6DCH2 // bit 2
10842 #define PWM6DCH3 PWM6DCHbits.PWM6DCH3 // bit 3
10843 #define PWM6DCH4 PWM6DCHbits.PWM6DCH4 // bit 4
10844 #define PWM6DCH5 PWM6DCHbits.PWM6DCH5 // bit 5
10845 #define PWM6DCH6 PWM6DCHbits.PWM6DCH6 // bit 6
10846 #define PWM6DCH7 PWM6DCHbits.PWM6DCH7 // bit 7
10848 #define PWM6DCL0 PWM6DCLbits.PWM6DCL0 // bit 6
10849 #define PWM6DCL1 PWM6DCLbits.PWM6DCL1 // bit 7
10851 #define P5TSEL0 PWMTMRSbits.P5TSEL0 // bit 0
10852 #define P5TSEL1 PWMTMRSbits.P5TSEL1 // bit 1
10853 #define P6TSEL0 PWMTMRSbits.P6TSEL0 // bit 2
10854 #define P6TSEL1 PWMTMRSbits.P6TSEL1 // bit 3
10856 #define RA0PPS0 RA0PPSbits.RA0PPS0 // bit 0
10857 #define RA0PPS1 RA0PPSbits.RA0PPS1 // bit 1
10858 #define RA0PPS2 RA0PPSbits.RA0PPS2 // bit 2
10859 #define RA0PPS3 RA0PPSbits.RA0PPS3 // bit 3
10860 #define RA0PPS4 RA0PPSbits.RA0PPS4 // bit 4
10862 #define RA1PPS0 RA1PPSbits.RA1PPS0 // bit 0
10863 #define RA1PPS1 RA1PPSbits.RA1PPS1 // bit 1
10864 #define RA1PPS2 RA1PPSbits.RA1PPS2 // bit 2
10865 #define RA1PPS3 RA1PPSbits.RA1PPS3 // bit 3
10866 #define RA1PPS4 RA1PPSbits.RA1PPS4 // bit 4
10868 #define RA2PPS0 RA2PPSbits.RA2PPS0 // bit 0
10869 #define RA2PPS1 RA2PPSbits.RA2PPS1 // bit 1
10870 #define RA2PPS2 RA2PPSbits.RA2PPS2 // bit 2
10871 #define RA2PPS3 RA2PPSbits.RA2PPS3 // bit 3
10872 #define RA2PPS4 RA2PPSbits.RA2PPS4 // bit 4
10874 #define RA4PPS0 RA4PPSbits.RA4PPS0 // bit 0
10875 #define RA4PPS1 RA4PPSbits.RA4PPS1 // bit 1
10876 #define RA4PPS2 RA4PPSbits.RA4PPS2 // bit 2
10877 #define RA4PPS3 RA4PPSbits.RA4PPS3 // bit 3
10878 #define RA4PPS4 RA4PPSbits.RA4PPS4 // bit 4
10880 #define RA5PPS0 RA5PPSbits.RA5PPS0 // bit 0
10881 #define RA5PPS1 RA5PPSbits.RA5PPS1 // bit 1
10882 #define RA5PPS2 RA5PPSbits.RA5PPS2 // bit 2
10883 #define RA5PPS3 RA5PPSbits.RA5PPS3 // bit 3
10884 #define RA5PPS4 RA5PPSbits.RA5PPS4 // bit 4
10886 #define RC0PPS0 RC0PPSbits.RC0PPS0 // bit 0
10887 #define RC0PPS1 RC0PPSbits.RC0PPS1 // bit 1
10888 #define RC0PPS2 RC0PPSbits.RC0PPS2 // bit 2
10889 #define RC0PPS3 RC0PPSbits.RC0PPS3 // bit 3
10890 #define RC0PPS4 RC0PPSbits.RC0PPS4 // bit 4
10892 #define RC1PPS0 RC1PPSbits.RC1PPS0 // bit 0
10893 #define RC1PPS1 RC1PPSbits.RC1PPS1 // bit 1
10894 #define RC1PPS2 RC1PPSbits.RC1PPS2 // bit 2
10895 #define RC1PPS3 RC1PPSbits.RC1PPS3 // bit 3
10896 #define RC1PPS4 RC1PPSbits.RC1PPS4 // bit 4
10898 #define RX9D RC1STAbits.RX9D // bit 0
10899 #define OERR RC1STAbits.OERR // bit 1
10900 #define FERR RC1STAbits.FERR // bit 2
10901 #define ADDEN RC1STAbits.ADDEN // bit 3
10902 #define CREN RC1STAbits.CREN // bit 4
10903 #define SREN RC1STAbits.SREN // bit 5
10904 #define RX9 RC1STAbits.RX9 // bit 6
10905 #define SPEN RC1STAbits.SPEN // bit 7
10907 #define RC2PPS0 RC2PPSbits.RC2PPS0 // bit 0
10908 #define RC2PPS1 RC2PPSbits.RC2PPS1 // bit 1
10909 #define RC2PPS2 RC2PPSbits.RC2PPS2 // bit 2
10910 #define RC2PPS3 RC2PPSbits.RC2PPS3 // bit 3
10911 #define RC2PPS4 RC2PPSbits.RC2PPS4 // bit 4
10913 #define RC3PPS0 RC3PPSbits.RC3PPS0 // bit 0
10914 #define RC3PPS1 RC3PPSbits.RC3PPS1 // bit 1
10915 #define RC3PPS2 RC3PPSbits.RC3PPS2 // bit 2
10916 #define RC3PPS3 RC3PPSbits.RC3PPS3 // bit 3
10917 #define RC3PPS4 RC3PPSbits.RC3PPS4 // bit 4
10919 #define RC4PPS0 RC4PPSbits.RC4PPS0 // bit 0
10920 #define RC4PPS1 RC4PPSbits.RC4PPS1 // bit 1
10921 #define RC4PPS2 RC4PPSbits.RC4PPS2 // bit 2
10922 #define RC4PPS3 RC4PPSbits.RC4PPS3 // bit 3
10923 #define RC4PPS4 RC4PPSbits.RC4PPS4 // bit 4
10925 #define RC5PPS0 RC5PPSbits.RC5PPS0 // bit 0
10926 #define RC5PPS1 RC5PPSbits.RC5PPS1 // bit 1
10927 #define RC5PPS2 RC5PPSbits.RC5PPS2 // bit 2
10928 #define RC5PPS3 RC5PPSbits.RC5PPS3 // bit 3
10929 #define RC5PPS4 RC5PPSbits.RC5PPS4 // bit 4
10931 #define RXDTPPS0 RXPPSbits.RXDTPPS0 // bit 0
10932 #define RXDTPPS1 RXPPSbits.RXDTPPS1 // bit 1
10933 #define RXDTPPS2 RXPPSbits.RXDTPPS2 // bit 2
10934 #define RXDTPPS3 RXPPSbits.RXDTPPS3 // bit 3
10935 #define RXDTPPS4 RXPPSbits.RXDTPPS4 // bit 4
10937 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
10938 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
10939 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
10940 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
10941 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
10943 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
10944 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
10945 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
10946 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
10947 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
10948 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
10950 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
10951 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
10952 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
10953 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
10954 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
10955 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
10956 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
10957 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
10958 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
10959 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
10960 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
10961 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
10962 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
10963 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
10964 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
10965 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
10967 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
10968 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
10969 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
10970 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
10971 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
10972 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
10973 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
10974 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
10975 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
10976 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
10977 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
10978 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
10979 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
10980 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
10981 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
10982 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
10984 #define SSP1CLKPPS0 SSP1CLKPPSbits.SSP1CLKPPS0 // bit 0
10985 #define SSP1CLKPPS1 SSP1CLKPPSbits.SSP1CLKPPS1 // bit 1
10986 #define SSP1CLKPPS2 SSP1CLKPPSbits.SSP1CLKPPS2 // bit 2
10987 #define SSP1CLKPPS3 SSP1CLKPPSbits.SSP1CLKPPS3 // bit 3
10988 #define SSP1CLKPPS4 SSP1CLKPPSbits.SSP1CLKPPS4 // bit 4
10990 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
10991 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
10992 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
10993 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
10994 #define CKP SSP1CONbits.CKP // bit 4
10995 #define SSPEN SSP1CONbits.SSPEN // bit 5
10996 #define SSPOV SSP1CONbits.SSPOV // bit 6
10997 #define WCOL SSP1CONbits.WCOL // bit 7
10999 #define SEN SSP1CON2bits.SEN // bit 0
11000 #define RSEN SSP1CON2bits.RSEN // bit 1
11001 #define PEN SSP1CON2bits.PEN // bit 2
11002 #define RCEN SSP1CON2bits.RCEN // bit 3
11003 #define ACKEN SSP1CON2bits.ACKEN // bit 4
11004 #define ACKDT SSP1CON2bits.ACKDT // bit 5
11005 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
11006 #define GCEN SSP1CON2bits.GCEN // bit 7
11008 #define DHEN SSP1CON3bits.DHEN // bit 0
11009 #define AHEN SSP1CON3bits.AHEN // bit 1
11010 #define SBCDE SSP1CON3bits.SBCDE // bit 2
11011 #define SDAHT SSP1CON3bits.SDAHT // bit 3
11012 #define BOEN SSP1CON3bits.BOEN // bit 4
11013 #define SCIE SSP1CON3bits.SCIE // bit 5
11014 #define PCIE SSP1CON3bits.PCIE // bit 6
11015 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
11017 #define SSP1DATPPS0 SSP1DATPPSbits.SSP1DATPPS0 // bit 0
11018 #define SSP1DATPPS1 SSP1DATPPSbits.SSP1DATPPS1 // bit 1
11019 #define SSP1DATPPS2 SSP1DATPPSbits.SSP1DATPPS2 // bit 2
11020 #define SSP1DATPPS3 SSP1DATPPSbits.SSP1DATPPS3 // bit 3
11021 #define SSP1DATPPS4 SSP1DATPPSbits.SSP1DATPPS4 // bit 4
11023 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
11024 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
11025 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
11026 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
11027 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
11028 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
11029 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
11030 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
11031 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
11032 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
11033 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
11034 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
11035 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
11036 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
11037 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
11038 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
11040 #define SSP1SSPPS0 SSP1SSPPSbits.SSP1SSPPS0 // bit 0
11041 #define SSP1SSPPS1 SSP1SSPPSbits.SSP1SSPPS1 // bit 1
11042 #define SSP1SSPPS2 SSP1SSPPSbits.SSP1SSPPS2 // bit 2
11043 #define SSP1SSPPS3 SSP1SSPPSbits.SSP1SSPPS3 // bit 3
11044 #define SSP1SSPPS4 SSP1SSPPSbits.SSP1SSPPS4 // bit 4
11046 #define BF SSP1STATbits.BF // bit 0
11047 #define UA SSP1STATbits.UA // bit 1
11048 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
11049 #define S SSP1STATbits.S // bit 3
11050 #define P SSP1STATbits.P // bit 4
11051 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
11052 #define CKE SSP1STATbits.CKE // bit 6
11053 #define SMP SSP1STATbits.SMP // bit 7
11055 #define C STATUSbits.C // bit 0
11056 #define DC STATUSbits.DC // bit 1
11057 #define Z STATUSbits.Z // bit 2
11058 #define NOT_PD STATUSbits.NOT_PD // bit 3
11059 #define NOT_TO STATUSbits.NOT_TO // bit 4
11061 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
11062 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
11063 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
11065 #define T0CKIPPS0 T0CKIPPSbits.T0CKIPPS0 // bit 0
11066 #define T0CKIPPS1 T0CKIPPSbits.T0CKIPPS1 // bit 1
11067 #define T0CKIPPS2 T0CKIPPSbits.T0CKIPPS2 // bit 2
11068 #define T0CKIPPS3 T0CKIPPSbits.T0CKIPPS3 // bit 3
11069 #define T0CKIPPS4 T0CKIPPSbits.T0CKIPPS4 // bit 4
11071 #define T0OUTPS0 T0CON0bits.T0OUTPS0 // bit 0
11072 #define T0OUTPS1 T0CON0bits.T0OUTPS1 // bit 1
11073 #define T0OUTPS2 T0CON0bits.T0OUTPS2 // bit 2
11074 #define T0OUTPS3 T0CON0bits.T0OUTPS3 // bit 3
11075 #define T016BIT T0CON0bits.T016BIT // bit 4
11076 #define T0OUT T0CON0bits.T0OUT // bit 5
11077 #define T0EN T0CON0bits.T0EN // bit 7
11079 #define T0CKPS0 T0CON1bits.T0CKPS0 // bit 0
11080 #define T0CKPS1 T0CON1bits.T0CKPS1 // bit 1
11081 #define T0CKPS2 T0CON1bits.T0CKPS2 // bit 2
11082 #define T0CKPS3 T0CON1bits.T0CKPS3 // bit 3
11083 #define T0ASYNC T0CON1bits.T0ASYNC // bit 4
11084 #define T0CS0 T0CON1bits.T0CS0 // bit 5
11085 #define T0CS1 T0CON1bits.T0CS1 // bit 6
11086 #define T0CS2 T0CON1bits.T0CS2 // bit 7
11088 #define T1CKIPPS0 T1CKIPPSbits.T1CKIPPS0 // bit 0
11089 #define T1CKIPPS1 T1CKIPPSbits.T1CKIPPS1 // bit 1
11090 #define T1CKIPPS2 T1CKIPPSbits.T1CKIPPS2 // bit 2
11091 #define T1CKIPPS3 T1CKIPPSbits.T1CKIPPS3 // bit 3
11092 #define T1CKIPPS4 T1CKIPPSbits.T1CKIPPS4 // bit 4
11094 #define TMR1ON T1CONbits.TMR1ON // bit 0
11095 #define T1SYNC T1CONbits.T1SYNC // bit 2
11096 #define T1SOSC T1CONbits.T1SOSC // bit 3
11097 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
11098 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
11099 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
11100 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
11102 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
11103 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
11104 #define T1GVAL T1GCONbits.T1GVAL // bit 2
11105 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3
11106 #define T1GSPM T1GCONbits.T1GSPM // bit 4
11107 #define T1GTM T1GCONbits.T1GTM // bit 5
11108 #define T1GPOL T1GCONbits.T1GPOL // bit 6
11109 #define TMR1GE T1GCONbits.TMR1GE // bit 7
11111 #define T1GPPS0 T1GPPSbits.T1GPPS0 // bit 0
11112 #define T1GPPS1 T1GPPSbits.T1GPPS1 // bit 1
11113 #define T1GPPS2 T1GPPSbits.T1GPPS2 // bit 2
11114 #define T1GPPS3 T1GPPSbits.T1GPPS3 // bit 3
11115 #define T1GPPS4 T1GPPSbits.T1GPPS4 // bit 4
11117 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
11118 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
11119 #define TMR2ON T2CONbits.TMR2ON // bit 2
11120 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
11121 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
11122 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
11123 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
11125 #define TMR3ON T3CONbits.TMR3ON // bit 0
11126 #define T3SYNC T3CONbits.T3SYNC // bit 2
11127 #define T3SOSC T3CONbits.T3SOSC // bit 3
11128 #define T3CKPS0 T3CONbits.T3CKPS0 // bit 4
11129 #define T3CKPS1 T3CONbits.T3CKPS1 // bit 5
11130 #define TMR3CS0 T3CONbits.TMR3CS0 // bit 6
11131 #define TMR3CS1 T3CONbits.TMR3CS1 // bit 7
11133 #define T3GSS0 T3GCONbits.T3GSS0 // bit 0
11134 #define T3GSS1 T3GCONbits.T3GSS1 // bit 1
11135 #define T3GVAL T3GCONbits.T3GVAL // bit 2
11136 #define T3GGO_NOT_DONE T3GCONbits.T3GGO_NOT_DONE // bit 3
11137 #define T3GSPM T3GCONbits.T3GSPM // bit 4
11138 #define T3GTM T3GCONbits.T3GTM // bit 5
11139 #define T3GPOL T3GCONbits.T3GPOL // bit 6
11140 #define TMR3GE T3GCONbits.TMR3GE // bit 7
11142 #define T4CKPS0 T4CONbits.T4CKPS0 // bit 0
11143 #define T4CKPS1 T4CONbits.T4CKPS1 // bit 1
11144 #define TMR4ON T4CONbits.TMR4ON // bit 2
11145 #define T4OUTPS0 T4CONbits.T4OUTPS0 // bit 3
11146 #define T4OUTPS1 T4CONbits.T4OUTPS1 // bit 4
11147 #define T4OUTPS2 T4CONbits.T4OUTPS2 // bit 5
11148 #define T4OUTPS3 T4CONbits.T4OUTPS3 // bit 6
11150 #define TMR5ON T5CONbits.TMR5ON // bit 0
11151 #define T5SYNC T5CONbits.T5SYNC // bit 2
11152 #define T5SOSC T5CONbits.T5SOSC // bit 3
11153 #define T5CKPS0 T5CONbits.T5CKPS0 // bit 4
11154 #define T5CKPS1 T5CONbits.T5CKPS1 // bit 5
11155 #define TMR5CS0 T5CONbits.TMR5CS0 // bit 6
11156 #define TMR5CS1 T5CONbits.TMR5CS1 // bit 7
11158 #define T5GSS0 T5GCONbits.T5GSS0 // bit 0
11159 #define T5GSS1 T5GCONbits.T5GSS1 // bit 1
11160 #define T5GVAL T5GCONbits.T5GVAL // bit 2
11161 #define T5GGO_NOT_DONE T5GCONbits.T5GGO_NOT_DONE // bit 3
11162 #define T5GSPM T5GCONbits.T5GSPM // bit 4
11163 #define T5GTM T5GCONbits.T5GTM // bit 5
11164 #define T5GPOL T5GCONbits.T5GPOL // bit 6
11165 #define TMR5GE T5GCONbits.TMR5GE // bit 7
11167 #define T6CKPS0 T6CONbits.T6CKPS0 // bit 0
11168 #define T6CKPS1 T6CONbits.T6CKPS1 // bit 1
11169 #define TMR6ON T6CONbits.TMR6ON // bit 2
11170 #define T6OUTPS0 T6CONbits.T6OUTPS0 // bit 3
11171 #define T6OUTPS1 T6CONbits.T6OUTPS1 // bit 4
11172 #define T6OUTPS2 T6CONbits.T6OUTPS2 // bit 5
11173 #define T6OUTPS3 T6CONbits.T6OUTPS3 // bit 6
11175 #define TMR08 TMR0Hbits.TMR08 // bit 0
11176 #define TMR09 TMR0Hbits.TMR09 // bit 1
11177 #define TMR010 TMR0Hbits.TMR010 // bit 2
11178 #define TMR011 TMR0Hbits.TMR011 // bit 3
11179 #define TMR012 TMR0Hbits.TMR012 // bit 4
11180 #define TMR013 TMR0Hbits.TMR013 // bit 5
11181 #define TMR014 TMR0Hbits.TMR014 // bit 6
11182 #define TMR015 TMR0Hbits.TMR015 // bit 7
11184 #define TMR00 TMR0Lbits.TMR00 // bit 0
11185 #define TMR01 TMR0Lbits.TMR01 // bit 1
11186 #define TMR02 TMR0Lbits.TMR02 // bit 2
11187 #define TMR03 TMR0Lbits.TMR03 // bit 3
11188 #define TMR04 TMR0Lbits.TMR04 // bit 4
11189 #define TMR05 TMR0Lbits.TMR05 // bit 5
11190 #define TMR06 TMR0Lbits.TMR06 // bit 6
11191 #define TMR07 TMR0Lbits.TMR07 // bit 7
11193 #define TRISA0 TRISAbits.TRISA0 // bit 0
11194 #define TRISA1 TRISAbits.TRISA1 // bit 1
11195 #define TRISA2 TRISAbits.TRISA2 // bit 2
11196 #define TRISA4 TRISAbits.TRISA4 // bit 4
11197 #define TRISA5 TRISAbits.TRISA5 // bit 5
11199 #define TRISC0 TRISCbits.TRISC0 // bit 0
11200 #define TRISC1 TRISCbits.TRISC1 // bit 1
11201 #define TRISC2 TRISCbits.TRISC2 // bit 2
11202 #define TRISC3 TRISCbits.TRISC3 // bit 3
11203 #define TRISC4 TRISCbits.TRISC4 // bit 4
11204 #define TRISC5 TRISCbits.TRISC5 // bit 5
11206 #define TX9D TX1STAbits.TX9D // bit 0
11207 #define TRMT TX1STAbits.TRMT // bit 1
11208 #define BRGH TX1STAbits.BRGH // bit 2
11209 #define SENDB TX1STAbits.SENDB // bit 3
11210 #define SYNC TX1STAbits.SYNC // bit 4
11211 #define TXEN TX1STAbits.TXEN // bit 5
11212 #define TX9 TX1STAbits.TX9 // bit 6
11213 #define CSRC TX1STAbits.CSRC // bit 7
11215 #define TXCKPPS0 TXPPSbits.TXCKPPS0 // bit 0
11216 #define TXCKPPS1 TXPPSbits.TXCKPPS1 // bit 1
11217 #define TXCKPPS2 TXPPSbits.TXCKPPS2 // bit 2
11218 #define TXCKPPS3 TXPPSbits.TXCKPPS3 // bit 3
11219 #define TXCKPPS4 TXPPSbits.TXCKPPS4 // bit 4
11221 #define SWDTEN WDTCONbits.SWDTEN // bit 0
11222 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
11223 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
11224 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
11225 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
11226 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
11228 #define WPUA0 WPUAbits.WPUA0 // bit 0
11229 #define WPUA1 WPUAbits.WPUA1 // bit 1
11230 #define WPUA2 WPUAbits.WPUA2 // bit 2
11231 #define WPUA3 WPUAbits.WPUA3 // bit 3
11232 #define WPUA4 WPUAbits.WPUA4 // bit 4
11233 #define WPUA5 WPUAbits.WPUA5 // bit 5
11235 #define WPUC0 WPUCbits.WPUC0 // bit 0
11236 #define WPUC1 WPUCbits.WPUC1 // bit 1
11237 #define WPUC2 WPUCbits.WPUC2 // bit 2
11238 #define WPUC3 WPUCbits.WPUC3 // bit 3
11239 #define WPUC4 WPUCbits.WPUC4 // bit 4
11240 #define WPUC5 WPUCbits.WPUC5 // bit 5
11242 #endif // #ifndef NO_BIT_DEFINES
11244 #endif // #ifndef __PIC16LF18324_H__