2 * This declarations of the PIC16LF18325 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:24 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16LF18325_H__
26 #define __PIC16LF18325_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTC_ADDR 0x000E
52 #define PIR0_ADDR 0x0010
53 #define PIR1_ADDR 0x0011
54 #define PIR2_ADDR 0x0012
55 #define PIR3_ADDR 0x0013
56 #define PIR4_ADDR 0x0014
57 #define TMR0L_ADDR 0x0015
58 #define TMR0H_ADDR 0x0016
59 #define T0CON0_ADDR 0x0017
60 #define T0CON1_ADDR 0x0018
61 #define TMR1_ADDR 0x0019
62 #define TMR1L_ADDR 0x0019
63 #define TMR1H_ADDR 0x001A
64 #define T1CON_ADDR 0x001B
65 #define T1GCON_ADDR 0x001C
66 #define TMR2_ADDR 0x001D
67 #define PR2_ADDR 0x001E
68 #define T2CON_ADDR 0x001F
69 #define TRISA_ADDR 0x008C
70 #define TRISC_ADDR 0x008E
71 #define PIE0_ADDR 0x0090
72 #define PIE1_ADDR 0x0091
73 #define PIE2_ADDR 0x0092
74 #define PIE3_ADDR 0x0093
75 #define PIE4_ADDR 0x0094
76 #define WDTCON_ADDR 0x0097
77 #define ADRES_ADDR 0x009B
78 #define ADRESL_ADDR 0x009B
79 #define ADRESH_ADDR 0x009C
80 #define ADCON0_ADDR 0x009D
81 #define ADCON1_ADDR 0x009E
82 #define ADACT_ADDR 0x009F
83 #define LATA_ADDR 0x010C
84 #define LATC_ADDR 0x010E
85 #define CM1CON0_ADDR 0x0111
86 #define CM1CON1_ADDR 0x0112
87 #define CM2CON0_ADDR 0x0113
88 #define CM2CON1_ADDR 0x0114
89 #define CMOUT_ADDR 0x0115
90 #define BORCON_ADDR 0x0116
91 #define FVRCON_ADDR 0x0117
92 #define DACCON0_ADDR 0x0118
93 #define DACCON1_ADDR 0x0119
94 #define ANSELA_ADDR 0x018C
95 #define ANSELC_ADDR 0x018E
96 #define RC1REG_ADDR 0x0199
97 #define RCREG_ADDR 0x0199
98 #define RCREG1_ADDR 0x0199
99 #define TX1REG_ADDR 0x019A
100 #define TXREG_ADDR 0x019A
101 #define TXREG1_ADDR 0x019A
102 #define SP1BRG_ADDR 0x019B
103 #define SP1BRGL_ADDR 0x019B
104 #define SPBRG_ADDR 0x019B
105 #define SPBRG1_ADDR 0x019B
106 #define SPBRGL_ADDR 0x019B
107 #define SP1BRGH_ADDR 0x019C
108 #define SPBRGH_ADDR 0x019C
109 #define SPBRGH1_ADDR 0x019C
110 #define RC1STA_ADDR 0x019D
111 #define RCSTA_ADDR 0x019D
112 #define RCSTA1_ADDR 0x019D
113 #define TX1STA_ADDR 0x019E
114 #define TXSTA_ADDR 0x019E
115 #define TXSTA1_ADDR 0x019E
116 #define BAUD1CON_ADDR 0x019F
117 #define BAUDCON_ADDR 0x019F
118 #define BAUDCON1_ADDR 0x019F
119 #define BAUDCTL_ADDR 0x019F
120 #define BAUDCTL1_ADDR 0x019F
121 #define WPUA_ADDR 0x020C
122 #define WPUC_ADDR 0x020E
123 #define SSP1BUF_ADDR 0x0211
124 #define SSPBUF_ADDR 0x0211
125 #define SSP1ADD_ADDR 0x0212
126 #define SSPADD_ADDR 0x0212
127 #define SSP1MSK_ADDR 0x0213
128 #define SSPMSK_ADDR 0x0213
129 #define SSP1STAT_ADDR 0x0214
130 #define SSPSTAT_ADDR 0x0214
131 #define SSP1CON_ADDR 0x0215
132 #define SSP1CON1_ADDR 0x0215
133 #define SSPCON_ADDR 0x0215
134 #define SSPCON1_ADDR 0x0215
135 #define SSP1CON2_ADDR 0x0216
136 #define SSPCON2_ADDR 0x0216
137 #define SSP1CON3_ADDR 0x0217
138 #define SSPCON3_ADDR 0x0217
139 #define SSP2BUF_ADDR 0x0219
140 #define SSP2ADD_ADDR 0x021A
141 #define SSP2MSK_ADDR 0x021B
142 #define SSP2STAT_ADDR 0x021C
143 #define SSP2CON_ADDR 0x021D
144 #define SSP2CON1_ADDR 0x021D
145 #define SSP2CON2_ADDR 0x021E
146 #define SSP2CON3_ADDR 0x021F
147 #define ODCONA_ADDR 0x028C
148 #define ODCONC_ADDR 0x028E
149 #define CCPR1_ADDR 0x0291
150 #define CCPR1L_ADDR 0x0291
151 #define CCPR1H_ADDR 0x0292
152 #define CCP1CON_ADDR 0x0293
153 #define CCP1CAP_ADDR 0x0294
154 #define CCPR2_ADDR 0x0295
155 #define CCPR2L_ADDR 0x0295
156 #define CCPR2H_ADDR 0x0296
157 #define CCP2CON_ADDR 0x0297
158 #define CCP2CAP_ADDR 0x0298
159 #define CCPTMRS_ADDR 0x029F
160 #define SLRCONA_ADDR 0x030C
161 #define SLRCONC_ADDR 0x030E
162 #define CCPR3_ADDR 0x0311
163 #define CCPR3L_ADDR 0x0311
164 #define CCPR3H_ADDR 0x0312
165 #define CCP3CON_ADDR 0x0313
166 #define CCP3CAP_ADDR 0x0314
167 #define CCPR4_ADDR 0x0315
168 #define CCPR4L_ADDR 0x0315
169 #define CCPR4H_ADDR 0x0316
170 #define CCP4CON_ADDR 0x0317
171 #define CCP4CAP_ADDR 0x0318
172 #define INLVLA_ADDR 0x038C
173 #define INLVLC_ADDR 0x038E
174 #define IOCAP_ADDR 0x0391
175 #define IOCAN_ADDR 0x0392
176 #define IOCAF_ADDR 0x0393
177 #define IOCCP_ADDR 0x0397
178 #define IOCCN_ADDR 0x0398
179 #define IOCCF_ADDR 0x0399
180 #define CLKRCON_ADDR 0x039A
181 #define MDCON_ADDR 0x039C
182 #define MDSRC_ADDR 0x039D
183 #define MDCARH_ADDR 0x039E
184 #define MDCARL_ADDR 0x039F
185 #define CCDNA_ADDR 0x040C
186 #define CCDNC_ADDR 0x040E
187 #define TMR3_ADDR 0x0411
188 #define TMR3L_ADDR 0x0411
189 #define TMR3H_ADDR 0x0412
190 #define T3CON_ADDR 0x0413
191 #define T3GCON_ADDR 0x0414
192 #define TMR4_ADDR 0x0415
193 #define PR4_ADDR 0x0416
194 #define T4CON_ADDR 0x0417
195 #define TMR5_ADDR 0x0418
196 #define TMR5L_ADDR 0x0418
197 #define TMR5H_ADDR 0x0419
198 #define T5CON_ADDR 0x041A
199 #define T5GCON_ADDR 0x041B
200 #define TMR6_ADDR 0x041C
201 #define PR6_ADDR 0x041D
202 #define T6CON_ADDR 0x041E
203 #define CCDCON_ADDR 0x041F
204 #define CCDPA_ADDR 0x048C
205 #define CCDPC_ADDR 0x048E
206 #define NCO1ACC_ADDR 0x0498
207 #define NCO1ACCL_ADDR 0x0498
208 #define NCO1ACCH_ADDR 0x0499
209 #define NCO1ACCU_ADDR 0x049A
210 #define NCO1INC_ADDR 0x049B
211 #define NCO1INCL_ADDR 0x049B
212 #define NCO1INCH_ADDR 0x049C
213 #define NCO1INCU_ADDR 0x049D
214 #define NCO1CON_ADDR 0x049E
215 #define NCO1CLK_ADDR 0x049F
216 #define PWM5DCL_ADDR 0x0617
217 #define PWM5DCH_ADDR 0x0618
218 #define PWM5CON_ADDR 0x0619
219 #define PWM5CON0_ADDR 0x0619
220 #define PWM6DCL_ADDR 0x061A
221 #define PWM6DCH_ADDR 0x061B
222 #define PWM6CON_ADDR 0x061C
223 #define PWM6CON0_ADDR 0x061C
224 #define PWMTMRS_ADDR 0x061F
225 #define CWG1CLKCON_ADDR 0x0691
226 #define CWG1DAT_ADDR 0x0692
227 #define CWG1DBR_ADDR 0x0693
228 #define CWG1DBF_ADDR 0x0694
229 #define CWG1CON0_ADDR 0x0695
230 #define CWG1CON1_ADDR 0x0696
231 #define CWG1AS0_ADDR 0x0697
232 #define CWG1AS1_ADDR 0x0698
233 #define CWG1STR_ADDR 0x0699
234 #define CWG2CLKCON_ADDR 0x0711
235 #define CWG2DAT_ADDR 0x0712
236 #define CWG2DBR_ADDR 0x0713
237 #define CWG2DBF_ADDR 0x0714
238 #define CWG2CON0_ADDR 0x0715
239 #define CWG2CON1_ADDR 0x0716
240 #define CWG2AS0_ADDR 0x0717
241 #define CWG2AS1_ADDR 0x0718
242 #define CWG2STR_ADDR 0x0719
243 #define NVMADR_ADDR 0x0891
244 #define NVMADRL_ADDR 0x0891
245 #define NVMADRH_ADDR 0x0892
246 #define NVMDAT_ADDR 0x0893
247 #define NVMDATL_ADDR 0x0893
248 #define NVMDATH_ADDR 0x0894
249 #define NVMCON1_ADDR 0x0895
250 #define NVMCON2_ADDR 0x0896
251 #define PCON0_ADDR 0x089B
252 #define PMD0_ADDR 0x0911
253 #define PMD1_ADDR 0x0912
254 #define PMD2_ADDR 0x0913
255 #define PMD3_ADDR 0x0914
256 #define PMD4_ADDR 0x0915
257 #define PMD5_ADDR 0x0916
258 #define CPUDOZE_ADDR 0x0918
259 #define OSCCON1_ADDR 0x0919
260 #define OSCCON2_ADDR 0x091A
261 #define OSCCON3_ADDR 0x091B
262 #define OSCSTAT1_ADDR 0x091C
263 #define OSCEN_ADDR 0x091D
264 #define OSCTUNE_ADDR 0x091E
265 #define OSCFRQ_ADDR 0x091F
266 #define PPSLOCK_ADDR 0x0E0F
267 #define INTPPS_ADDR 0x0E10
268 #define T0CKIPPS_ADDR 0x0E11
269 #define T1CKIPPS_ADDR 0x0E12
270 #define T1GPPS_ADDR 0x0E13
271 #define CCP1PPS_ADDR 0x0E14
272 #define CCP2PPS_ADDR 0x0E15
273 #define CCP3PPS_ADDR 0x0E16
274 #define CCP4PPS_ADDR 0x0E17
275 #define CWG1PPS_ADDR 0x0E18
276 #define CWG2PPS_ADDR 0x0E19
277 #define MDCIN1PPS_ADDR 0x0E1A
278 #define MDCIN2PPS_ADDR 0x0E1B
279 #define MDMINPPS_ADDR 0x0E1C
280 #define SSP2CLKPPS_ADDR 0x0E1D
281 #define SSP2DATPPS_ADDR 0x0E1E
282 #define SSP2SSPPS_ADDR 0x0E1F
283 #define SSP1CLKPPS_ADDR 0x0E20
284 #define SSP1DATPPS_ADDR 0x0E21
285 #define SSP1SSPPS_ADDR 0x0E22
286 #define RXPPS_ADDR 0x0E24
287 #define TXPPS_ADDR 0x0E25
288 #define CLCIN0PPS_ADDR 0x0E28
289 #define CLCIN1PPS_ADDR 0x0E29
290 #define CLCIN2PPS_ADDR 0x0E2A
291 #define CLCIN3PPS_ADDR 0x0E2B
292 #define T3CKIPPS_ADDR 0x0E2C
293 #define T3GPPS_ADDR 0x0E2D
294 #define T5CKIPPS_ADDR 0x0E2E
295 #define T5GPPS_ADDR 0x0E2F
296 #define RA0PPS_ADDR 0x0E90
297 #define RA1PPS_ADDR 0x0E91
298 #define RA2PPS_ADDR 0x0E92
299 #define RA4PPS_ADDR 0x0E94
300 #define RA5PPS_ADDR 0x0E95
301 #define RC0PPS_ADDR 0x0EA0
302 #define RC1PPS_ADDR 0x0EA1
303 #define RC2PPS_ADDR 0x0EA2
304 #define RC3PPS_ADDR 0x0EA3
305 #define RC4PPS_ADDR 0x0EA4
306 #define RC5PPS_ADDR 0x0EA5
307 #define CLCDATA_ADDR 0x0F0F
308 #define CLC1CON_ADDR 0x0F10
309 #define CLC1POL_ADDR 0x0F11
310 #define CLC1SEL0_ADDR 0x0F12
311 #define CLC1SEL1_ADDR 0x0F13
312 #define CLC1SEL2_ADDR 0x0F14
313 #define CLC1SEL3_ADDR 0x0F15
314 #define CLC1GLS0_ADDR 0x0F16
315 #define CLC1GLS1_ADDR 0x0F17
316 #define CLC1GLS2_ADDR 0x0F18
317 #define CLC1GLS3_ADDR 0x0F19
318 #define CLC2CON_ADDR 0x0F1A
319 #define CLC2POL_ADDR 0x0F1B
320 #define CLC2SEL0_ADDR 0x0F1C
321 #define CLC2SEL1_ADDR 0x0F1D
322 #define CLC2SEL2_ADDR 0x0F1E
323 #define CLC2SEL3_ADDR 0x0F1F
324 #define CLC2GLS0_ADDR 0x0F20
325 #define CLC2GLS1_ADDR 0x0F21
326 #define CLC2GLS2_ADDR 0x0F22
327 #define CLC2GLS3_ADDR 0x0F23
328 #define CLC3CON_ADDR 0x0F24
329 #define CLC3POL_ADDR 0x0F25
330 #define CLC3SEL0_ADDR 0x0F26
331 #define CLC3SEL1_ADDR 0x0F27
332 #define CLC3SEL2_ADDR 0x0F28
333 #define CLC3SEL3_ADDR 0x0F29
334 #define CLC3GLS0_ADDR 0x0F2A
335 #define CLC3GLS1_ADDR 0x0F2B
336 #define CLC3GLS2_ADDR 0x0F2C
337 #define CLC3GLS3_ADDR 0x0F2D
338 #define CLC4CON_ADDR 0x0F2E
339 #define CLC4POL_ADDR 0x0F2F
340 #define CLC4SEL0_ADDR 0x0F30
341 #define CLC4SEL1_ADDR 0x0F31
342 #define CLC4SEL2_ADDR 0x0F32
343 #define CLC4SEL3_ADDR 0x0F33
344 #define CLC4GLS0_ADDR 0x0F34
345 #define CLC4GLS1_ADDR 0x0F35
346 #define CLC4GLS2_ADDR 0x0F36
347 #define CLC4GLS3_ADDR 0x0F37
348 #define STATUS_SHAD_ADDR 0x0FE4
349 #define WREG_SHAD_ADDR 0x0FE5
350 #define BSR_SHAD_ADDR 0x0FE6
351 #define PCLATH_SHAD_ADDR 0x0FE7
352 #define FSR0L_SHAD_ADDR 0x0FE8
353 #define FSR0H_SHAD_ADDR 0x0FE9
354 #define FSR1L_SHAD_ADDR 0x0FEA
355 #define FSR1H_SHAD_ADDR 0x0FEB
356 #define STKPTR_ADDR 0x0FED
357 #define TOSL_ADDR 0x0FEE
358 #define TOSH_ADDR 0x0FEF
360 #endif // #ifndef NO_ADDR_DEFINES
362 //==============================================================================
364 // Register Definitions
366 //==============================================================================
368 extern __at(0x0000) __sfr INDF0
;
369 extern __at(0x0001) __sfr INDF1
;
370 extern __at(0x0002) __sfr PCL
;
372 //==============================================================================
375 extern __at(0x0003) __sfr STATUS
;
389 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
397 //==============================================================================
399 extern __at(0x0004) __sfr FSR0
;
400 extern __at(0x0004) __sfr FSR0L
;
401 extern __at(0x0005) __sfr FSR0H
;
402 extern __at(0x0006) __sfr FSR1
;
403 extern __at(0x0006) __sfr FSR1L
;
404 extern __at(0x0007) __sfr FSR1H
;
406 //==============================================================================
409 extern __at(0x0008) __sfr BSR
;
432 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
440 //==============================================================================
442 extern __at(0x0009) __sfr WREG
;
443 extern __at(0x000A) __sfr PCLATH
;
445 //==============================================================================
448 extern __at(0x000B) __sfr INTCON
;
462 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
468 //==============================================================================
471 //==============================================================================
474 extern __at(0x000C) __sfr PORTA
;
497 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
506 //==============================================================================
509 //==============================================================================
512 extern __at(0x000E) __sfr PORTC
;
535 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
544 //==============================================================================
547 //==============================================================================
550 extern __at(0x0010) __sfr PIR0
;
564 extern __at(0x0010) volatile __PIR0bits_t PIR0bits
;
570 //==============================================================================
573 //==============================================================================
576 extern __at(0x0011) __sfr PIR1
;
587 unsigned TMR1GIF
: 1;
590 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
599 #define _TMR1GIF 0x80
601 //==============================================================================
604 //==============================================================================
607 extern __at(0x0012) __sfr PIR2
;
621 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
632 //==============================================================================
635 //==============================================================================
638 extern __at(0x0013) __sfr PIR3
;
647 unsigned TMR3GIF
: 1;
652 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
659 #define _TMR3GIF 0x20
663 //==============================================================================
666 //==============================================================================
669 extern __at(0x0014) __sfr PIR4
;
678 unsigned TMR5GIF
: 1;
683 extern __at(0x0014) volatile __PIR4bits_t PIR4bits
;
690 #define _TMR5GIF 0x20
694 //==============================================================================
697 //==============================================================================
700 extern __at(0x0015) __sfr TMR0L
;
714 extern __at(0x0015) volatile __TMR0Lbits_t TMR0Lbits
;
725 //==============================================================================
728 //==============================================================================
731 extern __at(0x0016) __sfr TMR0H
;
745 extern __at(0x0016) volatile __TMR0Hbits_t TMR0Hbits
;
756 //==============================================================================
759 //==============================================================================
762 extern __at(0x0017) __sfr T0CON0
;
768 unsigned T0OUTPS0
: 1;
769 unsigned T0OUTPS1
: 1;
770 unsigned T0OUTPS2
: 1;
771 unsigned T0OUTPS3
: 1;
772 unsigned T016BIT
: 1;
780 unsigned T0OUTPS
: 4;
785 extern __at(0x0017) volatile __T0CON0bits_t T0CON0bits
;
787 #define _T0OUTPS0 0x01
788 #define _T0OUTPS1 0x02
789 #define _T0OUTPS2 0x04
790 #define _T0OUTPS3 0x08
791 #define _T016BIT 0x10
795 //==============================================================================
798 //==============================================================================
801 extern __at(0x0018) __sfr T0CON1
;
807 unsigned T0CKPS0
: 1;
808 unsigned T0CKPS1
: 1;
809 unsigned T0CKPS2
: 1;
810 unsigned T0CKPS3
: 1;
811 unsigned T0ASYNC
: 1;
830 extern __at(0x0018) volatile __T0CON1bits_t T0CON1bits
;
832 #define _T0CKPS0 0x01
833 #define _T0CKPS1 0x02
834 #define _T0CKPS2 0x04
835 #define _T0CKPS3 0x08
836 #define _T0ASYNC 0x10
841 //==============================================================================
843 extern __at(0x0019) __sfr TMR1
;
844 extern __at(0x0019) __sfr TMR1L
;
845 extern __at(0x001A) __sfr TMR1H
;
847 //==============================================================================
850 extern __at(0x001B) __sfr T1CON
;
860 unsigned T1CKPS0
: 1;
861 unsigned T1CKPS1
: 1;
862 unsigned TMR1CS0
: 1;
863 unsigned TMR1CS1
: 1;
880 extern __at(0x001B) volatile __T1CONbits_t T1CONbits
;
885 #define _T1CKPS0 0x10
886 #define _T1CKPS1 0x20
887 #define _TMR1CS0 0x40
888 #define _TMR1CS1 0x80
890 //==============================================================================
893 //==============================================================================
896 extern __at(0x001C) __sfr T1GCON
;
905 unsigned T1GGO_NOT_DONE
: 1;
919 extern __at(0x001C) volatile __T1GCONbits_t T1GCONbits
;
924 #define _T1GGO_NOT_DONE 0x08
930 //==============================================================================
932 extern __at(0x001D) __sfr TMR2
;
933 extern __at(0x001E) __sfr PR2
;
935 //==============================================================================
938 extern __at(0x001F) __sfr T2CON
;
944 unsigned T2CKPS0
: 1;
945 unsigned T2CKPS1
: 1;
947 unsigned T2OUTPS0
: 1;
948 unsigned T2OUTPS1
: 1;
949 unsigned T2OUTPS2
: 1;
950 unsigned T2OUTPS3
: 1;
963 unsigned T2OUTPS
: 4;
968 extern __at(0x001F) volatile __T2CONbits_t T2CONbits
;
970 #define _T2CKPS0 0x01
971 #define _T2CKPS1 0x02
973 #define _T2OUTPS0 0x08
974 #define _T2OUTPS1 0x10
975 #define _T2OUTPS2 0x20
976 #define _T2OUTPS3 0x40
978 //==============================================================================
981 //==============================================================================
984 extern __at(0x008C) __sfr TRISA
;
998 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
1000 #define _TRISA0 0x01
1001 #define _TRISA1 0x02
1002 #define _TRISA2 0x04
1003 #define _TRISA4 0x10
1004 #define _TRISA5 0x20
1006 //==============================================================================
1009 //==============================================================================
1012 extern __at(0x008E) __sfr TRISC
;
1018 unsigned TRISC0
: 1;
1019 unsigned TRISC1
: 1;
1020 unsigned TRISC2
: 1;
1021 unsigned TRISC3
: 1;
1022 unsigned TRISC4
: 1;
1023 unsigned TRISC5
: 1;
1035 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
1037 #define _TRISC0 0x01
1038 #define _TRISC1 0x02
1039 #define _TRISC2 0x04
1040 #define _TRISC3 0x08
1041 #define _TRISC4 0x10
1042 #define _TRISC5 0x20
1044 //==============================================================================
1047 //==============================================================================
1050 extern __at(0x0090) __sfr PIE0
;
1059 unsigned TMR0IE
: 1;
1064 extern __at(0x0090) volatile __PIE0bits_t PIE0bits
;
1068 #define _TMR0IE 0x20
1070 //==============================================================================
1073 //==============================================================================
1076 extern __at(0x0091) __sfr PIE1
;
1080 unsigned TMR1IE
: 1;
1081 unsigned TMR2IE
: 1;
1082 unsigned BCL1IE
: 1;
1083 unsigned SSP1IE
: 1;
1087 unsigned TMR1GIE
: 1;
1090 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
1092 #define _TMR1IE 0x01
1093 #define _TMR2IE 0x02
1094 #define _BCL1IE 0x04
1095 #define _SSP1IE 0x08
1099 #define _TMR1GIE 0x80
1101 //==============================================================================
1104 //==============================================================================
1107 extern __at(0x0092) __sfr PIE2
;
1111 unsigned NCO1IE
: 1;
1112 unsigned TMR4IE
: 1;
1113 unsigned BCL2IE
: 1;
1114 unsigned SSP2IE
: 1;
1118 unsigned TMR6IE
: 1;
1121 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
1123 #define _NCO1IE 0x01
1124 #define _TMR4IE 0x02
1125 #define _BCL2IE 0x04
1126 #define _SSP2IE 0x08
1130 #define _TMR6IE 0x80
1132 //==============================================================================
1135 //==============================================================================
1138 extern __at(0x0093) __sfr PIE3
;
1142 unsigned CLC1IE
: 1;
1143 unsigned CLC2IE
: 1;
1144 unsigned CLC3IE
: 1;
1145 unsigned CLC4IE
: 1;
1146 unsigned TMR3IE
: 1;
1147 unsigned TMR3GIE
: 1;
1152 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
1154 #define _CLC1IE 0x01
1155 #define _CLC2IE 0x02
1156 #define _CLC3IE 0x04
1157 #define _CLC4IE 0x08
1158 #define _TMR3IE 0x10
1159 #define _TMR3GIE 0x20
1163 //==============================================================================
1166 //==============================================================================
1169 extern __at(0x0094) __sfr PIE4
;
1173 unsigned CCP1IE
: 1;
1174 unsigned CCP2IE
: 1;
1175 unsigned CCP3IE
: 1;
1176 unsigned CCP4IE
: 1;
1177 unsigned TMR5IE
: 1;
1178 unsigned TMR5GIE
: 1;
1179 unsigned CWG1IE
: 1;
1180 unsigned CWG2IE
: 1;
1183 extern __at(0x0094) volatile __PIE4bits_t PIE4bits
;
1185 #define _CCP1IE 0x01
1186 #define _CCP2IE 0x02
1187 #define _CCP3IE 0x04
1188 #define _CCP4IE 0x08
1189 #define _TMR5IE 0x10
1190 #define _TMR5GIE 0x20
1191 #define _CWG1IE 0x40
1192 #define _CWG2IE 0x80
1194 //==============================================================================
1197 //==============================================================================
1200 extern __at(0x0097) __sfr WDTCON
;
1206 unsigned SWDTEN
: 1;
1207 unsigned WDTPS0
: 1;
1208 unsigned WDTPS1
: 1;
1209 unsigned WDTPS2
: 1;
1210 unsigned WDTPS3
: 1;
1211 unsigned WDTPS4
: 1;
1224 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1226 #define _SWDTEN 0x01
1227 #define _WDTPS0 0x02
1228 #define _WDTPS1 0x04
1229 #define _WDTPS2 0x08
1230 #define _WDTPS3 0x10
1231 #define _WDTPS4 0x20
1233 //==============================================================================
1235 extern __at(0x009B) __sfr ADRES
;
1236 extern __at(0x009B) __sfr ADRESL
;
1237 extern __at(0x009C) __sfr ADRESH
;
1239 //==============================================================================
1242 extern __at(0x009D) __sfr ADCON0
;
1249 unsigned GO_NOT_DONE
: 1;
1289 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1292 #define _GO_NOT_DONE 0x02
1302 //==============================================================================
1305 //==============================================================================
1308 extern __at(0x009E) __sfr ADCON1
;
1314 unsigned ADPREF0
: 1;
1315 unsigned ADPREF1
: 1;
1316 unsigned ADNREF
: 1;
1326 unsigned ADPREF
: 2;
1338 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1340 #define _ADPREF0 0x01
1341 #define _ADPREF1 0x02
1342 #define _ADNREF 0x04
1348 //==============================================================================
1351 //==============================================================================
1354 extern __at(0x009F) __sfr ADACT
;
1360 unsigned ADACT0
: 1;
1361 unsigned ADACT1
: 1;
1362 unsigned ADACT2
: 1;
1363 unsigned ADACT3
: 1;
1364 unsigned ADACT4
: 1;
1377 extern __at(0x009F) volatile __ADACTbits_t ADACTbits
;
1379 #define _ADACT0 0x01
1380 #define _ADACT1 0x02
1381 #define _ADACT2 0x04
1382 #define _ADACT3 0x08
1383 #define _ADACT4 0x10
1385 //==============================================================================
1388 //==============================================================================
1391 extern __at(0x010C) __sfr LATA
;
1405 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1413 //==============================================================================
1416 //==============================================================================
1419 extern __at(0x010E) __sfr LATC
;
1442 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1451 //==============================================================================
1454 //==============================================================================
1457 extern __at(0x0111) __sfr CM1CON0
;
1461 unsigned C1SYNC
: 1;
1471 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1473 #define _C1SYNC 0x01
1480 //==============================================================================
1483 //==============================================================================
1486 extern __at(0x0112) __sfr CM1CON1
;
1492 unsigned C1NCH0
: 1;
1493 unsigned C1NCH1
: 1;
1494 unsigned C1NCH2
: 1;
1495 unsigned C1PCH0
: 1;
1496 unsigned C1PCH1
: 1;
1497 unsigned C1PCH2
: 1;
1498 unsigned C1INTN
: 1;
1499 unsigned C1INTP
: 1;
1516 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1518 #define _C1NCH0 0x01
1519 #define _C1NCH1 0x02
1520 #define _C1NCH2 0x04
1521 #define _C1PCH0 0x08
1522 #define _C1PCH1 0x10
1523 #define _C1PCH2 0x20
1524 #define _C1INTN 0x40
1525 #define _C1INTP 0x80
1527 //==============================================================================
1530 //==============================================================================
1533 extern __at(0x0113) __sfr CM2CON0
;
1537 unsigned C2SYNC
: 1;
1547 extern __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits
;
1549 #define _C2SYNC 0x01
1556 //==============================================================================
1559 //==============================================================================
1562 extern __at(0x0114) __sfr CM2CON1
;
1568 unsigned C2NCH0
: 1;
1569 unsigned C2NCH1
: 1;
1570 unsigned C2NCH2
: 1;
1571 unsigned C2PCH0
: 1;
1572 unsigned C2PCH1
: 1;
1573 unsigned C2PCH2
: 1;
1574 unsigned C2INTN
: 1;
1575 unsigned C2INTP
: 1;
1592 extern __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits
;
1594 #define _C2NCH0 0x01
1595 #define _C2NCH1 0x02
1596 #define _C2NCH2 0x04
1597 #define _C2PCH0 0x08
1598 #define _C2PCH1 0x10
1599 #define _C2PCH2 0x20
1600 #define _C2INTN 0x40
1601 #define _C2INTP 0x80
1603 //==============================================================================
1606 //==============================================================================
1609 extern __at(0x0115) __sfr CMOUT
;
1613 unsigned MC1OUT
: 1;
1614 unsigned MC2OUT
: 1;
1623 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1625 #define _MC1OUT 0x01
1626 #define _MC2OUT 0x02
1628 //==============================================================================
1631 //==============================================================================
1634 extern __at(0x0116) __sfr BORCON
;
1638 unsigned BORRDY
: 1;
1645 unsigned SBOREN
: 1;
1648 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1650 #define _BORRDY 0x01
1651 #define _SBOREN 0x80
1653 //==============================================================================
1656 //==============================================================================
1659 extern __at(0x0117) __sfr FVRCON
;
1665 unsigned ADFVR0
: 1;
1666 unsigned ADFVR1
: 1;
1667 unsigned CDAFVR0
: 1;
1668 unsigned CDAFVR1
: 1;
1671 unsigned FVRRDY
: 1;
1684 unsigned CDAFVR
: 2;
1689 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1691 #define _ADFVR0 0x01
1692 #define _ADFVR1 0x02
1693 #define _CDAFVR0 0x04
1694 #define _CDAFVR1 0x08
1697 #define _FVRRDY 0x40
1700 //==============================================================================
1703 //==============================================================================
1706 extern __at(0x0118) __sfr DACCON0
;
1712 unsigned DAC1NSS
: 1;
1714 unsigned DAC1PSS0
: 1;
1715 unsigned DAC1PSS1
: 1;
1717 unsigned DAC1OE
: 1;
1719 unsigned DAC1EN
: 1;
1725 unsigned DAC1PSS
: 2;
1730 extern __at(0x0118) volatile __DACCON0bits_t DACCON0bits
;
1732 #define _DAC1NSS 0x01
1733 #define _DAC1PSS0 0x04
1734 #define _DAC1PSS1 0x08
1735 #define _DAC1OE 0x20
1736 #define _DAC1EN 0x80
1738 //==============================================================================
1741 //==============================================================================
1744 extern __at(0x0119) __sfr DACCON1
;
1750 unsigned DAC1R0
: 1;
1751 unsigned DAC1R1
: 1;
1752 unsigned DAC1R2
: 1;
1753 unsigned DAC1R3
: 1;
1754 unsigned DAC1R4
: 1;
1767 extern __at(0x0119) volatile __DACCON1bits_t DACCON1bits
;
1769 #define _DAC1R0 0x01
1770 #define _DAC1R1 0x02
1771 #define _DAC1R2 0x04
1772 #define _DAC1R3 0x08
1773 #define _DAC1R4 0x10
1775 //==============================================================================
1778 //==============================================================================
1781 extern __at(0x018C) __sfr ANSELA
;
1795 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1803 //==============================================================================
1806 //==============================================================================
1809 extern __at(0x018E) __sfr ANSELC
;
1832 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
1841 //==============================================================================
1843 extern __at(0x0199) __sfr RC1REG
;
1844 extern __at(0x0199) __sfr RCREG
;
1845 extern __at(0x0199) __sfr RCREG1
;
1846 extern __at(0x019A) __sfr TX1REG
;
1847 extern __at(0x019A) __sfr TXREG
;
1848 extern __at(0x019A) __sfr TXREG1
;
1849 extern __at(0x019B) __sfr SP1BRG
;
1850 extern __at(0x019B) __sfr SP1BRGL
;
1851 extern __at(0x019B) __sfr SPBRG
;
1852 extern __at(0x019B) __sfr SPBRG1
;
1853 extern __at(0x019B) __sfr SPBRGL
;
1854 extern __at(0x019C) __sfr SP1BRGH
;
1855 extern __at(0x019C) __sfr SPBRGH
;
1856 extern __at(0x019C) __sfr SPBRGH1
;
1858 //==============================================================================
1861 extern __at(0x019D) __sfr RC1STA
;
1875 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
1886 //==============================================================================
1889 //==============================================================================
1892 extern __at(0x019D) __sfr RCSTA
;
1906 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
1908 #define _RCSTA_RX9D 0x01
1909 #define _RCSTA_OERR 0x02
1910 #define _RCSTA_FERR 0x04
1911 #define _RCSTA_ADDEN 0x08
1912 #define _RCSTA_CREN 0x10
1913 #define _RCSTA_SREN 0x20
1914 #define _RCSTA_RX9 0x40
1915 #define _RCSTA_SPEN 0x80
1917 //==============================================================================
1920 //==============================================================================
1923 extern __at(0x019D) __sfr RCSTA1
;
1937 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
1939 #define _RCSTA1_RX9D 0x01
1940 #define _RCSTA1_OERR 0x02
1941 #define _RCSTA1_FERR 0x04
1942 #define _RCSTA1_ADDEN 0x08
1943 #define _RCSTA1_CREN 0x10
1944 #define _RCSTA1_SREN 0x20
1945 #define _RCSTA1_RX9 0x40
1946 #define _RCSTA1_SPEN 0x80
1948 //==============================================================================
1951 //==============================================================================
1954 extern __at(0x019E) __sfr TX1STA
;
1968 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
1979 //==============================================================================
1982 //==============================================================================
1985 extern __at(0x019E) __sfr TXSTA
;
1999 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
2001 #define _TXSTA_TX9D 0x01
2002 #define _TXSTA_TRMT 0x02
2003 #define _TXSTA_BRGH 0x04
2004 #define _TXSTA_SENDB 0x08
2005 #define _TXSTA_SYNC 0x10
2006 #define _TXSTA_TXEN 0x20
2007 #define _TXSTA_TX9 0x40
2008 #define _TXSTA_CSRC 0x80
2010 //==============================================================================
2013 //==============================================================================
2016 extern __at(0x019E) __sfr TXSTA1
;
2030 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
2032 #define _TXSTA1_TX9D 0x01
2033 #define _TXSTA1_TRMT 0x02
2034 #define _TXSTA1_BRGH 0x04
2035 #define _TXSTA1_SENDB 0x08
2036 #define _TXSTA1_SYNC 0x10
2037 #define _TXSTA1_TXEN 0x20
2038 #define _TXSTA1_TX9 0x40
2039 #define _TXSTA1_CSRC 0x80
2041 //==============================================================================
2044 //==============================================================================
2047 extern __at(0x019F) __sfr BAUD1CON
;
2058 unsigned ABDOVF
: 1;
2061 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
2068 #define _ABDOVF 0x80
2070 //==============================================================================
2073 //==============================================================================
2076 extern __at(0x019F) __sfr BAUDCON
;
2087 unsigned ABDOVF
: 1;
2090 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
2092 #define _BAUDCON_ABDEN 0x01
2093 #define _BAUDCON_WUE 0x02
2094 #define _BAUDCON_BRG16 0x08
2095 #define _BAUDCON_SCKP 0x10
2096 #define _BAUDCON_RCIDL 0x40
2097 #define _BAUDCON_ABDOVF 0x80
2099 //==============================================================================
2102 //==============================================================================
2105 extern __at(0x019F) __sfr BAUDCON1
;
2116 unsigned ABDOVF
: 1;
2119 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
2121 #define _BAUDCON1_ABDEN 0x01
2122 #define _BAUDCON1_WUE 0x02
2123 #define _BAUDCON1_BRG16 0x08
2124 #define _BAUDCON1_SCKP 0x10
2125 #define _BAUDCON1_RCIDL 0x40
2126 #define _BAUDCON1_ABDOVF 0x80
2128 //==============================================================================
2131 //==============================================================================
2134 extern __at(0x019F) __sfr BAUDCTL
;
2145 unsigned ABDOVF
: 1;
2148 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
2150 #define _BAUDCTL_ABDEN 0x01
2151 #define _BAUDCTL_WUE 0x02
2152 #define _BAUDCTL_BRG16 0x08
2153 #define _BAUDCTL_SCKP 0x10
2154 #define _BAUDCTL_RCIDL 0x40
2155 #define _BAUDCTL_ABDOVF 0x80
2157 //==============================================================================
2160 //==============================================================================
2163 extern __at(0x019F) __sfr BAUDCTL1
;
2174 unsigned ABDOVF
: 1;
2177 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
2179 #define _BAUDCTL1_ABDEN 0x01
2180 #define _BAUDCTL1_WUE 0x02
2181 #define _BAUDCTL1_BRG16 0x08
2182 #define _BAUDCTL1_SCKP 0x10
2183 #define _BAUDCTL1_RCIDL 0x40
2184 #define _BAUDCTL1_ABDOVF 0x80
2186 //==============================================================================
2189 //==============================================================================
2192 extern __at(0x020C) __sfr WPUA
;
2215 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
2224 //==============================================================================
2227 //==============================================================================
2230 extern __at(0x020E) __sfr WPUC
;
2253 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
2262 //==============================================================================
2265 //==============================================================================
2268 extern __at(0x0211) __sfr SSP1BUF
;
2274 unsigned SSP1BUF0
: 1;
2275 unsigned SSP1BUF1
: 1;
2276 unsigned SSP1BUF2
: 1;
2277 unsigned SSP1BUF3
: 1;
2278 unsigned SSP1BUF4
: 1;
2279 unsigned SSP1BUF5
: 1;
2280 unsigned SSP1BUF6
: 1;
2281 unsigned SSP1BUF7
: 1;
2297 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
2299 #define _SSP1BUF0 0x01
2301 #define _SSP1BUF1 0x02
2303 #define _SSP1BUF2 0x04
2305 #define _SSP1BUF3 0x08
2307 #define _SSP1BUF4 0x10
2309 #define _SSP1BUF5 0x20
2311 #define _SSP1BUF6 0x40
2313 #define _SSP1BUF7 0x80
2316 //==============================================================================
2319 //==============================================================================
2322 extern __at(0x0211) __sfr SSPBUF
;
2328 unsigned SSP1BUF0
: 1;
2329 unsigned SSP1BUF1
: 1;
2330 unsigned SSP1BUF2
: 1;
2331 unsigned SSP1BUF3
: 1;
2332 unsigned SSP1BUF4
: 1;
2333 unsigned SSP1BUF5
: 1;
2334 unsigned SSP1BUF6
: 1;
2335 unsigned SSP1BUF7
: 1;
2351 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
2353 #define _SSPBUF_SSP1BUF0 0x01
2354 #define _SSPBUF_BUF0 0x01
2355 #define _SSPBUF_SSP1BUF1 0x02
2356 #define _SSPBUF_BUF1 0x02
2357 #define _SSPBUF_SSP1BUF2 0x04
2358 #define _SSPBUF_BUF2 0x04
2359 #define _SSPBUF_SSP1BUF3 0x08
2360 #define _SSPBUF_BUF3 0x08
2361 #define _SSPBUF_SSP1BUF4 0x10
2362 #define _SSPBUF_BUF4 0x10
2363 #define _SSPBUF_SSP1BUF5 0x20
2364 #define _SSPBUF_BUF5 0x20
2365 #define _SSPBUF_SSP1BUF6 0x40
2366 #define _SSPBUF_BUF6 0x40
2367 #define _SSPBUF_SSP1BUF7 0x80
2368 #define _SSPBUF_BUF7 0x80
2370 //==============================================================================
2373 //==============================================================================
2376 extern __at(0x0212) __sfr SSP1ADD
;
2382 unsigned SSP1ADD0
: 1;
2383 unsigned SSP1ADD1
: 1;
2384 unsigned SSP1ADD2
: 1;
2385 unsigned SSP1ADD3
: 1;
2386 unsigned SSP1ADD4
: 1;
2387 unsigned SSP1ADD5
: 1;
2388 unsigned SSP1ADD6
: 1;
2389 unsigned SSP1ADD7
: 1;
2405 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
2407 #define _SSP1ADD0 0x01
2409 #define _SSP1ADD1 0x02
2411 #define _SSP1ADD2 0x04
2413 #define _SSP1ADD3 0x08
2415 #define _SSP1ADD4 0x10
2417 #define _SSP1ADD5 0x20
2419 #define _SSP1ADD6 0x40
2421 #define _SSP1ADD7 0x80
2424 //==============================================================================
2427 //==============================================================================
2430 extern __at(0x0212) __sfr SSPADD
;
2436 unsigned SSP1ADD0
: 1;
2437 unsigned SSP1ADD1
: 1;
2438 unsigned SSP1ADD2
: 1;
2439 unsigned SSP1ADD3
: 1;
2440 unsigned SSP1ADD4
: 1;
2441 unsigned SSP1ADD5
: 1;
2442 unsigned SSP1ADD6
: 1;
2443 unsigned SSP1ADD7
: 1;
2459 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
2461 #define _SSPADD_SSP1ADD0 0x01
2462 #define _SSPADD_ADD0 0x01
2463 #define _SSPADD_SSP1ADD1 0x02
2464 #define _SSPADD_ADD1 0x02
2465 #define _SSPADD_SSP1ADD2 0x04
2466 #define _SSPADD_ADD2 0x04
2467 #define _SSPADD_SSP1ADD3 0x08
2468 #define _SSPADD_ADD3 0x08
2469 #define _SSPADD_SSP1ADD4 0x10
2470 #define _SSPADD_ADD4 0x10
2471 #define _SSPADD_SSP1ADD5 0x20
2472 #define _SSPADD_ADD5 0x20
2473 #define _SSPADD_SSP1ADD6 0x40
2474 #define _SSPADD_ADD6 0x40
2475 #define _SSPADD_SSP1ADD7 0x80
2476 #define _SSPADD_ADD7 0x80
2478 //==============================================================================
2481 //==============================================================================
2484 extern __at(0x0213) __sfr SSP1MSK
;
2490 unsigned SSP1MSK0
: 1;
2491 unsigned SSP1MSK1
: 1;
2492 unsigned SSP1MSK2
: 1;
2493 unsigned SSP1MSK3
: 1;
2494 unsigned SSP1MSK4
: 1;
2495 unsigned SSP1MSK5
: 1;
2496 unsigned SSP1MSK6
: 1;
2497 unsigned SSP1MSK7
: 1;
2513 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
2515 #define _SSP1MSK0 0x01
2517 #define _SSP1MSK1 0x02
2519 #define _SSP1MSK2 0x04
2521 #define _SSP1MSK3 0x08
2523 #define _SSP1MSK4 0x10
2525 #define _SSP1MSK5 0x20
2527 #define _SSP1MSK6 0x40
2529 #define _SSP1MSK7 0x80
2532 //==============================================================================
2535 //==============================================================================
2538 extern __at(0x0213) __sfr SSPMSK
;
2544 unsigned SSP1MSK0
: 1;
2545 unsigned SSP1MSK1
: 1;
2546 unsigned SSP1MSK2
: 1;
2547 unsigned SSP1MSK3
: 1;
2548 unsigned SSP1MSK4
: 1;
2549 unsigned SSP1MSK5
: 1;
2550 unsigned SSP1MSK6
: 1;
2551 unsigned SSP1MSK7
: 1;
2567 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
2569 #define _SSPMSK_SSP1MSK0 0x01
2570 #define _SSPMSK_MSK0 0x01
2571 #define _SSPMSK_SSP1MSK1 0x02
2572 #define _SSPMSK_MSK1 0x02
2573 #define _SSPMSK_SSP1MSK2 0x04
2574 #define _SSPMSK_MSK2 0x04
2575 #define _SSPMSK_SSP1MSK3 0x08
2576 #define _SSPMSK_MSK3 0x08
2577 #define _SSPMSK_SSP1MSK4 0x10
2578 #define _SSPMSK_MSK4 0x10
2579 #define _SSPMSK_SSP1MSK5 0x20
2580 #define _SSPMSK_MSK5 0x20
2581 #define _SSPMSK_SSP1MSK6 0x40
2582 #define _SSPMSK_MSK6 0x40
2583 #define _SSPMSK_SSP1MSK7 0x80
2584 #define _SSPMSK_MSK7 0x80
2586 //==============================================================================
2589 //==============================================================================
2592 extern __at(0x0214) __sfr SSP1STAT
;
2598 unsigned R_NOT_W
: 1;
2601 unsigned D_NOT_A
: 1;
2606 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
2610 #define _R_NOT_W 0x04
2613 #define _D_NOT_A 0x20
2617 //==============================================================================
2620 //==============================================================================
2623 extern __at(0x0214) __sfr SSPSTAT
;
2629 unsigned R_NOT_W
: 1;
2632 unsigned D_NOT_A
: 1;
2637 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
2639 #define _SSPSTAT_BF 0x01
2640 #define _SSPSTAT_UA 0x02
2641 #define _SSPSTAT_R_NOT_W 0x04
2642 #define _SSPSTAT_S 0x08
2643 #define _SSPSTAT_P 0x10
2644 #define _SSPSTAT_D_NOT_A 0x20
2645 #define _SSPSTAT_CKE 0x40
2646 #define _SSPSTAT_SMP 0x80
2648 //==============================================================================
2651 //==============================================================================
2654 extern __at(0x0215) __sfr SSP1CON
;
2677 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
2688 //==============================================================================
2691 //==============================================================================
2694 extern __at(0x0215) __sfr SSP1CON1
;
2717 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
2719 #define _SSP1CON1_SSPM0 0x01
2720 #define _SSP1CON1_SSPM1 0x02
2721 #define _SSP1CON1_SSPM2 0x04
2722 #define _SSP1CON1_SSPM3 0x08
2723 #define _SSP1CON1_CKP 0x10
2724 #define _SSP1CON1_SSPEN 0x20
2725 #define _SSP1CON1_SSPOV 0x40
2726 #define _SSP1CON1_WCOL 0x80
2728 //==============================================================================
2731 //==============================================================================
2734 extern __at(0x0215) __sfr SSPCON
;
2757 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2759 #define _SSPCON_SSPM0 0x01
2760 #define _SSPCON_SSPM1 0x02
2761 #define _SSPCON_SSPM2 0x04
2762 #define _SSPCON_SSPM3 0x08
2763 #define _SSPCON_CKP 0x10
2764 #define _SSPCON_SSPEN 0x20
2765 #define _SSPCON_SSPOV 0x40
2766 #define _SSPCON_WCOL 0x80
2768 //==============================================================================
2771 //==============================================================================
2774 extern __at(0x0215) __sfr SSPCON1
;
2797 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2799 #define _SSPCON1_SSPM0 0x01
2800 #define _SSPCON1_SSPM1 0x02
2801 #define _SSPCON1_SSPM2 0x04
2802 #define _SSPCON1_SSPM3 0x08
2803 #define _SSPCON1_CKP 0x10
2804 #define _SSPCON1_SSPEN 0x20
2805 #define _SSPCON1_SSPOV 0x40
2806 #define _SSPCON1_WCOL 0x80
2808 //==============================================================================
2811 //==============================================================================
2814 extern __at(0x0216) __sfr SSP1CON2
;
2824 unsigned ACKSTAT
: 1;
2828 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
2836 #define _ACKSTAT 0x40
2839 //==============================================================================
2842 //==============================================================================
2845 extern __at(0x0216) __sfr SSPCON2
;
2855 unsigned ACKSTAT
: 1;
2859 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
2861 #define _SSPCON2_SEN 0x01
2862 #define _SSPCON2_RSEN 0x02
2863 #define _SSPCON2_PEN 0x04
2864 #define _SSPCON2_RCEN 0x08
2865 #define _SSPCON2_ACKEN 0x10
2866 #define _SSPCON2_ACKDT 0x20
2867 #define _SSPCON2_ACKSTAT 0x40
2868 #define _SSPCON2_GCEN 0x80
2870 //==============================================================================
2873 //==============================================================================
2876 extern __at(0x0217) __sfr SSP1CON3
;
2887 unsigned ACKTIM
: 1;
2890 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
2899 #define _ACKTIM 0x80
2901 //==============================================================================
2904 //==============================================================================
2907 extern __at(0x0217) __sfr SSPCON3
;
2918 unsigned ACKTIM
: 1;
2921 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
2923 #define _SSPCON3_DHEN 0x01
2924 #define _SSPCON3_AHEN 0x02
2925 #define _SSPCON3_SBCDE 0x04
2926 #define _SSPCON3_SDAHT 0x08
2927 #define _SSPCON3_BOEN 0x10
2928 #define _SSPCON3_SCIE 0x20
2929 #define _SSPCON3_PCIE 0x40
2930 #define _SSPCON3_ACKTIM 0x80
2932 //==============================================================================
2935 //==============================================================================
2938 extern __at(0x0219) __sfr SSP2BUF
;
2944 unsigned SSP2BUF0
: 1;
2945 unsigned SSP2BUF1
: 1;
2946 unsigned SSP2BUF2
: 1;
2947 unsigned SSP2BUF3
: 1;
2948 unsigned SSP2BUF4
: 1;
2949 unsigned SSP2BUF5
: 1;
2950 unsigned SSP2BUF6
: 1;
2951 unsigned SSP2BUF7
: 1;
2967 extern __at(0x0219) volatile __SSP2BUFbits_t SSP2BUFbits
;
2969 #define _SSP2BUF_SSP2BUF0 0x01
2970 #define _SSP2BUF_BUF0 0x01
2971 #define _SSP2BUF_SSP2BUF1 0x02
2972 #define _SSP2BUF_BUF1 0x02
2973 #define _SSP2BUF_SSP2BUF2 0x04
2974 #define _SSP2BUF_BUF2 0x04
2975 #define _SSP2BUF_SSP2BUF3 0x08
2976 #define _SSP2BUF_BUF3 0x08
2977 #define _SSP2BUF_SSP2BUF4 0x10
2978 #define _SSP2BUF_BUF4 0x10
2979 #define _SSP2BUF_SSP2BUF5 0x20
2980 #define _SSP2BUF_BUF5 0x20
2981 #define _SSP2BUF_SSP2BUF6 0x40
2982 #define _SSP2BUF_BUF6 0x40
2983 #define _SSP2BUF_SSP2BUF7 0x80
2984 #define _SSP2BUF_BUF7 0x80
2986 //==============================================================================
2989 //==============================================================================
2992 extern __at(0x021A) __sfr SSP2ADD
;
2998 unsigned SSP2ADD0
: 1;
2999 unsigned SSP2ADD1
: 1;
3000 unsigned SSP2ADD2
: 1;
3001 unsigned SSP2ADD3
: 1;
3002 unsigned SSP2ADD4
: 1;
3003 unsigned SSP2ADD5
: 1;
3004 unsigned SSP2ADD6
: 1;
3005 unsigned SSP2ADD7
: 1;
3021 extern __at(0x021A) volatile __SSP2ADDbits_t SSP2ADDbits
;
3023 #define _SSP2ADD_SSP2ADD0 0x01
3024 #define _SSP2ADD_ADD0 0x01
3025 #define _SSP2ADD_SSP2ADD1 0x02
3026 #define _SSP2ADD_ADD1 0x02
3027 #define _SSP2ADD_SSP2ADD2 0x04
3028 #define _SSP2ADD_ADD2 0x04
3029 #define _SSP2ADD_SSP2ADD3 0x08
3030 #define _SSP2ADD_ADD3 0x08
3031 #define _SSP2ADD_SSP2ADD4 0x10
3032 #define _SSP2ADD_ADD4 0x10
3033 #define _SSP2ADD_SSP2ADD5 0x20
3034 #define _SSP2ADD_ADD5 0x20
3035 #define _SSP2ADD_SSP2ADD6 0x40
3036 #define _SSP2ADD_ADD6 0x40
3037 #define _SSP2ADD_SSP2ADD7 0x80
3038 #define _SSP2ADD_ADD7 0x80
3040 //==============================================================================
3043 //==============================================================================
3046 extern __at(0x021B) __sfr SSP2MSK
;
3052 unsigned SSP2MSK0
: 1;
3053 unsigned SSP2MSK1
: 1;
3054 unsigned SSP2MSK2
: 1;
3055 unsigned SSP2MSK3
: 1;
3056 unsigned SSP2MSK4
: 1;
3057 unsigned SSP2MSK5
: 1;
3058 unsigned SSP2MSK6
: 1;
3059 unsigned SSP2MSK7
: 1;
3075 extern __at(0x021B) volatile __SSP2MSKbits_t SSP2MSKbits
;
3077 #define _SSP2MSK_SSP2MSK0 0x01
3078 #define _SSP2MSK_MSK0 0x01
3079 #define _SSP2MSK_SSP2MSK1 0x02
3080 #define _SSP2MSK_MSK1 0x02
3081 #define _SSP2MSK_SSP2MSK2 0x04
3082 #define _SSP2MSK_MSK2 0x04
3083 #define _SSP2MSK_SSP2MSK3 0x08
3084 #define _SSP2MSK_MSK3 0x08
3085 #define _SSP2MSK_SSP2MSK4 0x10
3086 #define _SSP2MSK_MSK4 0x10
3087 #define _SSP2MSK_SSP2MSK5 0x20
3088 #define _SSP2MSK_MSK5 0x20
3089 #define _SSP2MSK_SSP2MSK6 0x40
3090 #define _SSP2MSK_MSK6 0x40
3091 #define _SSP2MSK_SSP2MSK7 0x80
3092 #define _SSP2MSK_MSK7 0x80
3094 //==============================================================================
3097 //==============================================================================
3100 extern __at(0x021C) __sfr SSP2STAT
;
3106 unsigned R_NOT_W
: 1;
3109 unsigned D_NOT_A
: 1;
3114 extern __at(0x021C) volatile __SSP2STATbits_t SSP2STATbits
;
3116 #define _SSP2STAT_BF 0x01
3117 #define _SSP2STAT_UA 0x02
3118 #define _SSP2STAT_R_NOT_W 0x04
3119 #define _SSP2STAT_S 0x08
3120 #define _SSP2STAT_P 0x10
3121 #define _SSP2STAT_D_NOT_A 0x20
3122 #define _SSP2STAT_CKE 0x40
3123 #define _SSP2STAT_SMP 0x80
3125 //==============================================================================
3128 //==============================================================================
3131 extern __at(0x021D) __sfr SSP2CON
;
3154 extern __at(0x021D) volatile __SSP2CONbits_t SSP2CONbits
;
3156 #define _SSP2CON_SSPM0 0x01
3157 #define _SSP2CON_SSPM1 0x02
3158 #define _SSP2CON_SSPM2 0x04
3159 #define _SSP2CON_SSPM3 0x08
3160 #define _SSP2CON_CKP 0x10
3161 #define _SSP2CON_SSPEN 0x20
3162 #define _SSP2CON_SSPOV 0x40
3163 #define _SSP2CON_WCOL 0x80
3165 //==============================================================================
3168 //==============================================================================
3171 extern __at(0x021D) __sfr SSP2CON1
;
3194 extern __at(0x021D) volatile __SSP2CON1bits_t SSP2CON1bits
;
3196 #define _SSP2CON1_SSPM0 0x01
3197 #define _SSP2CON1_SSPM1 0x02
3198 #define _SSP2CON1_SSPM2 0x04
3199 #define _SSP2CON1_SSPM3 0x08
3200 #define _SSP2CON1_CKP 0x10
3201 #define _SSP2CON1_SSPEN 0x20
3202 #define _SSP2CON1_SSPOV 0x40
3203 #define _SSP2CON1_WCOL 0x80
3205 //==============================================================================
3208 //==============================================================================
3211 extern __at(0x021E) __sfr SSP2CON2
;
3221 unsigned ACKSTAT
: 1;
3225 extern __at(0x021E) volatile __SSP2CON2bits_t SSP2CON2bits
;
3227 #define _SSP2CON2_SEN 0x01
3228 #define _SSP2CON2_RSEN 0x02
3229 #define _SSP2CON2_PEN 0x04
3230 #define _SSP2CON2_RCEN 0x08
3231 #define _SSP2CON2_ACKEN 0x10
3232 #define _SSP2CON2_ACKDT 0x20
3233 #define _SSP2CON2_ACKSTAT 0x40
3234 #define _SSP2CON2_GCEN 0x80
3236 //==============================================================================
3239 //==============================================================================
3242 extern __at(0x021F) __sfr SSP2CON3
;
3253 unsigned ACKTIM
: 1;
3256 extern __at(0x021F) volatile __SSP2CON3bits_t SSP2CON3bits
;
3258 #define _SSP2CON3_DHEN 0x01
3259 #define _SSP2CON3_AHEN 0x02
3260 #define _SSP2CON3_SBCDE 0x04
3261 #define _SSP2CON3_SDAHT 0x08
3262 #define _SSP2CON3_BOEN 0x10
3263 #define _SSP2CON3_SCIE 0x20
3264 #define _SSP2CON3_PCIE 0x40
3265 #define _SSP2CON3_ACKTIM 0x80
3267 //==============================================================================
3270 //==============================================================================
3273 extern __at(0x028C) __sfr ODCONA
;
3287 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
3295 //==============================================================================
3298 //==============================================================================
3301 extern __at(0x028E) __sfr ODCONC
;
3324 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
3333 //==============================================================================
3335 extern __at(0x0291) __sfr CCPR1
;
3336 extern __at(0x0291) __sfr CCPR1L
;
3337 extern __at(0x0292) __sfr CCPR1H
;
3339 //==============================================================================
3342 extern __at(0x0293) __sfr CCP1CON
;
3348 unsigned CCP1MODE0
: 1;
3349 unsigned CCP1MODE1
: 1;
3350 unsigned CCP1MODE2
: 1;
3351 unsigned CCP1MODE3
: 1;
3352 unsigned CCP1FMT
: 1;
3353 unsigned CCP1OUT
: 1;
3355 unsigned CCP1EN
: 1;
3360 unsigned CCP1MODE
: 4;
3365 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
3367 #define _CCP1MODE0 0x01
3368 #define _CCP1MODE1 0x02
3369 #define _CCP1MODE2 0x04
3370 #define _CCP1MODE3 0x08
3371 #define _CCP1FMT 0x10
3372 #define _CCP1OUT 0x20
3373 #define _CCP1EN 0x80
3375 //==============================================================================
3378 //==============================================================================
3381 extern __at(0x0294) __sfr CCP1CAP
;
3387 unsigned CCP1CTS0
: 1;
3388 unsigned CCP1CTS1
: 1;
3389 unsigned CCP1CTS2
: 1;
3390 unsigned CCP1CTS3
: 1;
3399 unsigned CCP1CTS
: 4;
3404 extern __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits
;
3406 #define _CCP1CTS0 0x01
3407 #define _CCP1CTS1 0x02
3408 #define _CCP1CTS2 0x04
3409 #define _CCP1CTS3 0x08
3411 //==============================================================================
3413 extern __at(0x0295) __sfr CCPR2
;
3414 extern __at(0x0295) __sfr CCPR2L
;
3415 extern __at(0x0296) __sfr CCPR2H
;
3417 //==============================================================================
3420 extern __at(0x0297) __sfr CCP2CON
;
3426 unsigned CCP2MODE0
: 1;
3427 unsigned CCP2MODE1
: 1;
3428 unsigned CCP2MODE2
: 1;
3429 unsigned CCP2MODE3
: 1;
3430 unsigned CCP2FMT
: 1;
3431 unsigned CCP2OUT
: 1;
3433 unsigned CCP2EN
: 1;
3438 unsigned CCP2MODE
: 4;
3443 extern __at(0x0297) volatile __CCP2CONbits_t CCP2CONbits
;
3445 #define _CCP2MODE0 0x01
3446 #define _CCP2MODE1 0x02
3447 #define _CCP2MODE2 0x04
3448 #define _CCP2MODE3 0x08
3449 #define _CCP2FMT 0x10
3450 #define _CCP2OUT 0x20
3451 #define _CCP2EN 0x80
3453 //==============================================================================
3456 //==============================================================================
3459 extern __at(0x0298) __sfr CCP2CAP
;
3465 unsigned CCP2CTS0
: 1;
3466 unsigned CCP2CTS1
: 1;
3467 unsigned CCP2CTS2
: 1;
3468 unsigned CCP2CTS3
: 1;
3477 unsigned CCP2CTS
: 4;
3482 extern __at(0x0298) volatile __CCP2CAPbits_t CCP2CAPbits
;
3484 #define _CCP2CTS0 0x01
3485 #define _CCP2CTS1 0x02
3486 #define _CCP2CTS2 0x04
3487 #define _CCP2CTS3 0x08
3489 //==============================================================================
3492 //==============================================================================
3495 extern __at(0x029F) __sfr CCPTMRS
;
3501 unsigned C1TSEL0
: 1;
3502 unsigned C1TSEL1
: 1;
3503 unsigned C2TSEL0
: 1;
3504 unsigned C2TSEL1
: 1;
3505 unsigned C3TSEL0
: 1;
3506 unsigned C3TSEL1
: 1;
3507 unsigned C4TSEL0
: 1;
3508 unsigned C4TSEL1
: 1;
3513 unsigned C1TSEL
: 2;
3520 unsigned C2TSEL
: 2;
3527 unsigned C3TSEL
: 2;
3534 unsigned C4TSEL
: 2;
3538 extern __at(0x029F) volatile __CCPTMRSbits_t CCPTMRSbits
;
3540 #define _C1TSEL0 0x01
3541 #define _C1TSEL1 0x02
3542 #define _C2TSEL0 0x04
3543 #define _C2TSEL1 0x08
3544 #define _C3TSEL0 0x10
3545 #define _C3TSEL1 0x20
3546 #define _C4TSEL0 0x40
3547 #define _C4TSEL1 0x80
3549 //==============================================================================
3552 //==============================================================================
3555 extern __at(0x030C) __sfr SLRCONA
;
3569 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
3577 //==============================================================================
3580 //==============================================================================
3583 extern __at(0x030E) __sfr SLRCONC
;
3606 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
3615 //==============================================================================
3617 extern __at(0x0311) __sfr CCPR3
;
3618 extern __at(0x0311) __sfr CCPR3L
;
3619 extern __at(0x0312) __sfr CCPR3H
;
3621 //==============================================================================
3624 extern __at(0x0313) __sfr CCP3CON
;
3630 unsigned CCP3MODE0
: 1;
3631 unsigned CCP3MODE1
: 1;
3632 unsigned CCP3MODE2
: 1;
3633 unsigned CCP3MODE3
: 1;
3634 unsigned CCP3FMT
: 1;
3635 unsigned CCP3OUT
: 1;
3637 unsigned CCP3EN
: 1;
3642 unsigned CCP3MODE
: 4;
3647 extern __at(0x0313) volatile __CCP3CONbits_t CCP3CONbits
;
3649 #define _CCP3MODE0 0x01
3650 #define _CCP3MODE1 0x02
3651 #define _CCP3MODE2 0x04
3652 #define _CCP3MODE3 0x08
3653 #define _CCP3FMT 0x10
3654 #define _CCP3OUT 0x20
3655 #define _CCP3EN 0x80
3657 //==============================================================================
3660 //==============================================================================
3663 extern __at(0x0314) __sfr CCP3CAP
;
3686 extern __at(0x0314) volatile __CCP3CAPbits_t CCP3CAPbits
;
3693 //==============================================================================
3695 extern __at(0x0315) __sfr CCPR4
;
3696 extern __at(0x0315) __sfr CCPR4L
;
3697 extern __at(0x0316) __sfr CCPR4H
;
3699 //==============================================================================
3702 extern __at(0x0317) __sfr CCP4CON
;
3708 unsigned CCP4MODE0
: 1;
3709 unsigned CCP4MODE1
: 1;
3710 unsigned CCP4MODE2
: 1;
3711 unsigned CCP4MODE3
: 1;
3712 unsigned CCP4FMT
: 1;
3713 unsigned CCP4OUT
: 1;
3715 unsigned CCP4EN
: 1;
3720 unsigned CCP4MODE
: 4;
3725 extern __at(0x0317) volatile __CCP4CONbits_t CCP4CONbits
;
3727 #define _CCP4MODE0 0x01
3728 #define _CCP4MODE1 0x02
3729 #define _CCP4MODE2 0x04
3730 #define _CCP4MODE3 0x08
3731 #define _CCP4FMT 0x10
3732 #define _CCP4OUT 0x20
3733 #define _CCP4EN 0x80
3735 //==============================================================================
3738 //==============================================================================
3741 extern __at(0x0318) __sfr CCP4CAP
;
3747 unsigned CCP4CTS0
: 1;
3748 unsigned CCP4CTS1
: 1;
3749 unsigned CCP4CTS2
: 1;
3750 unsigned CCP4CTS3
: 1;
3759 unsigned CCP4CTS
: 4;
3764 extern __at(0x0318) volatile __CCP4CAPbits_t CCP4CAPbits
;
3766 #define _CCP4CTS0 0x01
3767 #define _CCP4CTS1 0x02
3768 #define _CCP4CTS2 0x04
3769 #define _CCP4CTS3 0x08
3771 //==============================================================================
3774 //==============================================================================
3777 extern __at(0x038C) __sfr INLVLA
;
3783 unsigned INLVLA0
: 1;
3784 unsigned INLVLA1
: 1;
3785 unsigned INLVLA2
: 1;
3786 unsigned INLVLA3
: 1;
3787 unsigned INLVLA4
: 1;
3788 unsigned INLVLA5
: 1;
3795 unsigned INLVLA
: 6;
3800 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
3802 #define _INLVLA0 0x01
3803 #define _INLVLA1 0x02
3804 #define _INLVLA2 0x04
3805 #define _INLVLA3 0x08
3806 #define _INLVLA4 0x10
3807 #define _INLVLA5 0x20
3809 //==============================================================================
3812 //==============================================================================
3815 extern __at(0x038E) __sfr INLVLC
;
3821 unsigned INLVLC0
: 1;
3822 unsigned INLVLC1
: 1;
3823 unsigned INLVLC2
: 1;
3824 unsigned INLVLC3
: 1;
3825 unsigned INLVLC4
: 1;
3826 unsigned INLVLC5
: 1;
3833 unsigned INLVLC
: 6;
3838 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
3840 #define _INLVLC0 0x01
3841 #define _INLVLC1 0x02
3842 #define _INLVLC2 0x04
3843 #define _INLVLC3 0x08
3844 #define _INLVLC4 0x10
3845 #define _INLVLC5 0x20
3847 //==============================================================================
3850 //==============================================================================
3853 extern __at(0x0391) __sfr IOCAP
;
3859 unsigned IOCAP0
: 1;
3860 unsigned IOCAP1
: 1;
3861 unsigned IOCAP2
: 1;
3862 unsigned IOCAP3
: 1;
3863 unsigned IOCAP4
: 1;
3864 unsigned IOCAP5
: 1;
3876 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
3878 #define _IOCAP0 0x01
3879 #define _IOCAP1 0x02
3880 #define _IOCAP2 0x04
3881 #define _IOCAP3 0x08
3882 #define _IOCAP4 0x10
3883 #define _IOCAP5 0x20
3885 //==============================================================================
3888 //==============================================================================
3891 extern __at(0x0392) __sfr IOCAN
;
3897 unsigned IOCAN0
: 1;
3898 unsigned IOCAN1
: 1;
3899 unsigned IOCAN2
: 1;
3900 unsigned IOCAN3
: 1;
3901 unsigned IOCAN4
: 1;
3902 unsigned IOCAN5
: 1;
3914 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
3916 #define _IOCAN0 0x01
3917 #define _IOCAN1 0x02
3918 #define _IOCAN2 0x04
3919 #define _IOCAN3 0x08
3920 #define _IOCAN4 0x10
3921 #define _IOCAN5 0x20
3923 //==============================================================================
3926 //==============================================================================
3929 extern __at(0x0393) __sfr IOCAF
;
3935 unsigned IOCAF0
: 1;
3936 unsigned IOCAF1
: 1;
3937 unsigned IOCAF2
: 1;
3938 unsigned IOCAF3
: 1;
3939 unsigned IOCAF4
: 1;
3940 unsigned IOCAF5
: 1;
3952 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
3954 #define _IOCAF0 0x01
3955 #define _IOCAF1 0x02
3956 #define _IOCAF2 0x04
3957 #define _IOCAF3 0x08
3958 #define _IOCAF4 0x10
3959 #define _IOCAF5 0x20
3961 //==============================================================================
3964 //==============================================================================
3967 extern __at(0x0397) __sfr IOCCP
;
3973 unsigned IOCCP0
: 1;
3974 unsigned IOCCP1
: 1;
3975 unsigned IOCCP2
: 1;
3976 unsigned IOCCP3
: 1;
3977 unsigned IOCCP4
: 1;
3978 unsigned IOCCP5
: 1;
3990 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
3992 #define _IOCCP0 0x01
3993 #define _IOCCP1 0x02
3994 #define _IOCCP2 0x04
3995 #define _IOCCP3 0x08
3996 #define _IOCCP4 0x10
3997 #define _IOCCP5 0x20
3999 //==============================================================================
4002 //==============================================================================
4005 extern __at(0x0398) __sfr IOCCN
;
4011 unsigned IOCCN0
: 1;
4012 unsigned IOCCN1
: 1;
4013 unsigned IOCCN2
: 1;
4014 unsigned IOCCN3
: 1;
4015 unsigned IOCCN4
: 1;
4016 unsigned IOCCN5
: 1;
4028 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
4030 #define _IOCCN0 0x01
4031 #define _IOCCN1 0x02
4032 #define _IOCCN2 0x04
4033 #define _IOCCN3 0x08
4034 #define _IOCCN4 0x10
4035 #define _IOCCN5 0x20
4037 //==============================================================================
4040 //==============================================================================
4043 extern __at(0x0399) __sfr IOCCF
;
4049 unsigned IOCCF0
: 1;
4050 unsigned IOCCF1
: 1;
4051 unsigned IOCCF2
: 1;
4052 unsigned IOCCF3
: 1;
4053 unsigned IOCCF4
: 1;
4054 unsigned IOCCF5
: 1;
4066 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
4068 #define _IOCCF0 0x01
4069 #define _IOCCF1 0x02
4070 #define _IOCCF2 0x04
4071 #define _IOCCF3 0x08
4072 #define _IOCCF4 0x10
4073 #define _IOCCF5 0x20
4075 //==============================================================================
4078 //==============================================================================
4081 extern __at(0x039A) __sfr CLKRCON
;
4087 unsigned CLKRDIV0
: 1;
4088 unsigned CLKRDIV1
: 1;
4089 unsigned CLKRDIV2
: 1;
4090 unsigned CLKRDC0
: 1;
4091 unsigned CLKRDC1
: 1;
4094 unsigned CLKREN
: 1;
4099 unsigned CLKRDIV
: 3;
4106 unsigned CLKRDC
: 2;
4111 extern __at(0x039A) volatile __CLKRCONbits_t CLKRCONbits
;
4113 #define _CLKRDIV0 0x01
4114 #define _CLKRDIV1 0x02
4115 #define _CLKRDIV2 0x04
4116 #define _CLKRDC0 0x08
4117 #define _CLKRDC1 0x10
4118 #define _CLKREN 0x80
4120 //==============================================================================
4123 //==============================================================================
4126 extern __at(0x039C) __sfr MDCON
;
4134 unsigned MDOPOL
: 1;
4140 extern __at(0x039C) volatile __MDCONbits_t MDCONbits
;
4144 #define _MDOPOL 0x10
4147 //==============================================================================
4150 //==============================================================================
4153 extern __at(0x039D) __sfr MDSRC
;
4176 extern __at(0x039D) volatile __MDSRCbits_t MDSRCbits
;
4183 //==============================================================================
4186 //==============================================================================
4189 extern __at(0x039E) __sfr MDCARH
;
4200 unsigned MDCHSYNC
: 1;
4201 unsigned MDCHPOL
: 1;
4212 extern __at(0x039E) volatile __MDCARHbits_t MDCARHbits
;
4218 #define _MDCHSYNC 0x20
4219 #define _MDCHPOL 0x40
4221 //==============================================================================
4224 //==============================================================================
4227 extern __at(0x039F) __sfr MDCARL
;
4238 unsigned MDCLSYNC
: 1;
4239 unsigned MDCLPOL
: 1;
4250 extern __at(0x039F) volatile __MDCARLbits_t MDCARLbits
;
4256 #define _MDCLSYNC 0x20
4257 #define _MDCLPOL 0x40
4259 //==============================================================================
4262 //==============================================================================
4265 extern __at(0x040C) __sfr CCDNA
;
4269 unsigned CCDNA0
: 1;
4270 unsigned CCDNA1
: 1;
4271 unsigned CCDNA2
: 1;
4273 unsigned CCDNA4
: 1;
4274 unsigned CCDNA5
: 1;
4279 extern __at(0x040C) volatile __CCDNAbits_t CCDNAbits
;
4281 #define _CCDNA0 0x01
4282 #define _CCDNA1 0x02
4283 #define _CCDNA2 0x04
4284 #define _CCDNA4 0x10
4285 #define _CCDNA5 0x20
4287 //==============================================================================
4290 //==============================================================================
4293 extern __at(0x040E) __sfr CCDNC
;
4299 unsigned CCDNC0
: 1;
4300 unsigned CCDNC1
: 1;
4301 unsigned CCDNC2
: 1;
4302 unsigned CCDNC3
: 1;
4303 unsigned CCDNC4
: 1;
4304 unsigned CCDNC5
: 1;
4316 extern __at(0x040E) volatile __CCDNCbits_t CCDNCbits
;
4318 #define _CCDNC0 0x01
4319 #define _CCDNC1 0x02
4320 #define _CCDNC2 0x04
4321 #define _CCDNC3 0x08
4322 #define _CCDNC4 0x10
4323 #define _CCDNC5 0x20
4325 //==============================================================================
4327 extern __at(0x0411) __sfr TMR3
;
4328 extern __at(0x0411) __sfr TMR3L
;
4329 extern __at(0x0412) __sfr TMR3H
;
4331 //==============================================================================
4334 extern __at(0x0413) __sfr T3CON
;
4340 unsigned TMR3ON
: 1;
4342 unsigned T3SYNC
: 1;
4343 unsigned T3SOSC
: 1;
4344 unsigned T3CKPS0
: 1;
4345 unsigned T3CKPS1
: 1;
4346 unsigned TMR3CS0
: 1;
4347 unsigned TMR3CS1
: 1;
4353 unsigned T3CKPS
: 2;
4360 unsigned TMR3CS
: 2;
4364 extern __at(0x0413) volatile __T3CONbits_t T3CONbits
;
4366 #define _TMR3ON 0x01
4367 #define _T3SYNC 0x04
4368 #define _T3SOSC 0x08
4369 #define _T3CKPS0 0x10
4370 #define _T3CKPS1 0x20
4371 #define _TMR3CS0 0x40
4372 #define _TMR3CS1 0x80
4374 //==============================================================================
4377 //==============================================================================
4380 extern __at(0x0414) __sfr T3GCON
;
4386 unsigned T3GSS0
: 1;
4387 unsigned T3GSS1
: 1;
4388 unsigned T3GVAL
: 1;
4389 unsigned T3GGO_NOT_DONE
: 1;
4390 unsigned T3GSPM
: 1;
4392 unsigned T3GPOL
: 1;
4393 unsigned TMR3GE
: 1;
4403 extern __at(0x0414) volatile __T3GCONbits_t T3GCONbits
;
4405 #define _T3GSS0 0x01
4406 #define _T3GSS1 0x02
4407 #define _T3GVAL 0x04
4408 #define _T3GGO_NOT_DONE 0x08
4409 #define _T3GSPM 0x10
4411 #define _T3GPOL 0x40
4412 #define _TMR3GE 0x80
4414 //==============================================================================
4416 extern __at(0x0415) __sfr TMR4
;
4417 extern __at(0x0416) __sfr PR4
;
4419 //==============================================================================
4422 extern __at(0x0417) __sfr T4CON
;
4428 unsigned T4CKPS0
: 1;
4429 unsigned T4CKPS1
: 1;
4430 unsigned TMR4ON
: 1;
4431 unsigned T4OUTPS0
: 1;
4432 unsigned T4OUTPS1
: 1;
4433 unsigned T4OUTPS2
: 1;
4434 unsigned T4OUTPS3
: 1;
4440 unsigned T4CKPS
: 2;
4447 unsigned T4OUTPS
: 4;
4452 extern __at(0x0417) volatile __T4CONbits_t T4CONbits
;
4454 #define _T4CKPS0 0x01
4455 #define _T4CKPS1 0x02
4456 #define _TMR4ON 0x04
4457 #define _T4OUTPS0 0x08
4458 #define _T4OUTPS1 0x10
4459 #define _T4OUTPS2 0x20
4460 #define _T4OUTPS3 0x40
4462 //==============================================================================
4464 extern __at(0x0418) __sfr TMR5
;
4465 extern __at(0x0418) __sfr TMR5L
;
4466 extern __at(0x0419) __sfr TMR5H
;
4468 //==============================================================================
4471 extern __at(0x041A) __sfr T5CON
;
4477 unsigned TMR5ON
: 1;
4479 unsigned T5SYNC
: 1;
4480 unsigned T5SOSC
: 1;
4481 unsigned T5CKPS0
: 1;
4482 unsigned T5CKPS1
: 1;
4483 unsigned TMR5CS0
: 1;
4484 unsigned TMR5CS1
: 1;
4490 unsigned T5CKPS
: 2;
4497 unsigned TMR5CS
: 2;
4501 extern __at(0x041A) volatile __T5CONbits_t T5CONbits
;
4503 #define _TMR5ON 0x01
4504 #define _T5SYNC 0x04
4505 #define _T5SOSC 0x08
4506 #define _T5CKPS0 0x10
4507 #define _T5CKPS1 0x20
4508 #define _TMR5CS0 0x40
4509 #define _TMR5CS1 0x80
4511 //==============================================================================
4514 //==============================================================================
4517 extern __at(0x041B) __sfr T5GCON
;
4523 unsigned T5GSS0
: 1;
4524 unsigned T5GSS1
: 1;
4525 unsigned T5GVAL
: 1;
4526 unsigned T5GGO_NOT_DONE
: 1;
4527 unsigned T5GSPM
: 1;
4529 unsigned T5GPOL
: 1;
4530 unsigned TMR5GE
: 1;
4540 extern __at(0x041B) volatile __T5GCONbits_t T5GCONbits
;
4542 #define _T5GSS0 0x01
4543 #define _T5GSS1 0x02
4544 #define _T5GVAL 0x04
4545 #define _T5GGO_NOT_DONE 0x08
4546 #define _T5GSPM 0x10
4548 #define _T5GPOL 0x40
4549 #define _TMR5GE 0x80
4551 //==============================================================================
4553 extern __at(0x041C) __sfr TMR6
;
4554 extern __at(0x041D) __sfr PR6
;
4556 //==============================================================================
4559 extern __at(0x041E) __sfr T6CON
;
4565 unsigned T6CKPS0
: 1;
4566 unsigned T6CKPS1
: 1;
4567 unsigned TMR6ON
: 1;
4568 unsigned T6OUTPS0
: 1;
4569 unsigned T6OUTPS1
: 1;
4570 unsigned T6OUTPS2
: 1;
4571 unsigned T6OUTPS3
: 1;
4577 unsigned T6CKPS
: 2;
4584 unsigned T6OUTPS
: 4;
4589 extern __at(0x041E) volatile __T6CONbits_t T6CONbits
;
4591 #define _T6CKPS0 0x01
4592 #define _T6CKPS1 0x02
4593 #define _TMR6ON 0x04
4594 #define _T6OUTPS0 0x08
4595 #define _T6OUTPS1 0x10
4596 #define _T6OUTPS2 0x20
4597 #define _T6OUTPS3 0x40
4599 //==============================================================================
4602 //==============================================================================
4605 extern __at(0x041F) __sfr CCDCON
;
4628 extern __at(0x041F) volatile __CCDCONbits_t CCDCONbits
;
4634 //==============================================================================
4637 //==============================================================================
4640 extern __at(0x048C) __sfr CCDPA
;
4644 unsigned CCDPA0
: 1;
4645 unsigned CCDPA1
: 1;
4646 unsigned CCDPA2
: 1;
4648 unsigned CCDPA4
: 1;
4649 unsigned CCDPA5
: 1;
4654 extern __at(0x048C) volatile __CCDPAbits_t CCDPAbits
;
4656 #define _CCDPA0 0x01
4657 #define _CCDPA1 0x02
4658 #define _CCDPA2 0x04
4659 #define _CCDPA4 0x10
4660 #define _CCDPA5 0x20
4662 //==============================================================================
4665 //==============================================================================
4668 extern __at(0x048E) __sfr CCDPC
;
4674 unsigned CCDPC0
: 1;
4675 unsigned CCDPC1
: 1;
4676 unsigned CCDPC2
: 1;
4677 unsigned CCDPC3
: 1;
4678 unsigned CCDPC4
: 1;
4679 unsigned CCDPC5
: 1;
4691 extern __at(0x048E) volatile __CCDPCbits_t CCDPCbits
;
4693 #define _CCDPC0 0x01
4694 #define _CCDPC1 0x02
4695 #define _CCDPC2 0x04
4696 #define _CCDPC3 0x08
4697 #define _CCDPC4 0x10
4698 #define _CCDPC5 0x20
4700 //==============================================================================
4702 extern __at(0x0498) __sfr NCO1ACC
;
4703 extern __at(0x0498) __sfr NCO1ACCL
;
4704 extern __at(0x0499) __sfr NCO1ACCH
;
4705 extern __at(0x049A) __sfr NCO1ACCU
;
4706 extern __at(0x049B) __sfr NCO1INC
;
4707 extern __at(0x049B) __sfr NCO1INCL
;
4708 extern __at(0x049C) __sfr NCO1INCH
;
4709 extern __at(0x049D) __sfr NCO1INCU
;
4711 //==============================================================================
4714 extern __at(0x049E) __sfr NCO1CON
;
4728 extern __at(0x049E) volatile __NCO1CONbits_t NCO1CONbits
;
4735 //==============================================================================
4737 extern __at(0x049F) __sfr NCO1CLK
;
4739 //==============================================================================
4742 extern __at(0x0617) __sfr PWM5DCL
;
4754 unsigned PWM5DCL0
: 1;
4755 unsigned PWM5DCL1
: 1;
4761 unsigned PWM5DCL
: 2;
4765 extern __at(0x0617) volatile __PWM5DCLbits_t PWM5DCLbits
;
4767 #define _PWM5DCL0 0x40
4768 #define _PWM5DCL1 0x80
4770 //==============================================================================
4773 //==============================================================================
4776 extern __at(0x0618) __sfr PWM5DCH
;
4780 unsigned PWM5DCH0
: 1;
4781 unsigned PWM5DCH1
: 1;
4782 unsigned PWM5DCH2
: 1;
4783 unsigned PWM5DCH3
: 1;
4784 unsigned PWM5DCH4
: 1;
4785 unsigned PWM5DCH5
: 1;
4786 unsigned PWM5DCH6
: 1;
4787 unsigned PWM5DCH7
: 1;
4790 extern __at(0x0618) volatile __PWM5DCHbits_t PWM5DCHbits
;
4792 #define _PWM5DCH0 0x01
4793 #define _PWM5DCH1 0x02
4794 #define _PWM5DCH2 0x04
4795 #define _PWM5DCH3 0x08
4796 #define _PWM5DCH4 0x10
4797 #define _PWM5DCH5 0x20
4798 #define _PWM5DCH6 0x40
4799 #define _PWM5DCH7 0x80
4801 //==============================================================================
4804 //==============================================================================
4807 extern __at(0x0619) __sfr PWM5CON
;
4815 unsigned PWM5POL
: 1;
4816 unsigned PWM5OUT
: 1;
4818 unsigned PWM5EN
: 1;
4821 extern __at(0x0619) volatile __PWM5CONbits_t PWM5CONbits
;
4823 #define _PWM5POL 0x10
4824 #define _PWM5OUT 0x20
4825 #define _PWM5EN 0x80
4827 //==============================================================================
4830 //==============================================================================
4833 extern __at(0x0619) __sfr PWM5CON0
;
4841 unsigned PWM5POL
: 1;
4842 unsigned PWM5OUT
: 1;
4844 unsigned PWM5EN
: 1;
4847 extern __at(0x0619) volatile __PWM5CON0bits_t PWM5CON0bits
;
4849 #define _PWM5CON0_PWM5POL 0x10
4850 #define _PWM5CON0_PWM5OUT 0x20
4851 #define _PWM5CON0_PWM5EN 0x80
4853 //==============================================================================
4856 //==============================================================================
4859 extern __at(0x061A) __sfr PWM6DCL
;
4871 unsigned PWM6DCL0
: 1;
4872 unsigned PWM6DCL1
: 1;
4878 unsigned PWM6DCL
: 2;
4882 extern __at(0x061A) volatile __PWM6DCLbits_t PWM6DCLbits
;
4884 #define _PWM6DCL0 0x40
4885 #define _PWM6DCL1 0x80
4887 //==============================================================================
4890 //==============================================================================
4893 extern __at(0x061B) __sfr PWM6DCH
;
4897 unsigned PWM6DCH0
: 1;
4898 unsigned PWM6DCH1
: 1;
4899 unsigned PWM6DCH2
: 1;
4900 unsigned PWM6DCH3
: 1;
4901 unsigned PWM6DCH4
: 1;
4902 unsigned PWM6DCH5
: 1;
4903 unsigned PWM6DCH6
: 1;
4904 unsigned PWM6DCH7
: 1;
4907 extern __at(0x061B) volatile __PWM6DCHbits_t PWM6DCHbits
;
4909 #define _PWM6DCH0 0x01
4910 #define _PWM6DCH1 0x02
4911 #define _PWM6DCH2 0x04
4912 #define _PWM6DCH3 0x08
4913 #define _PWM6DCH4 0x10
4914 #define _PWM6DCH5 0x20
4915 #define _PWM6DCH6 0x40
4916 #define _PWM6DCH7 0x80
4918 //==============================================================================
4921 //==============================================================================
4924 extern __at(0x061C) __sfr PWM6CON
;
4932 unsigned PWM6POL
: 1;
4933 unsigned PWM6OUT
: 1;
4935 unsigned PWM6EN
: 1;
4938 extern __at(0x061C) volatile __PWM6CONbits_t PWM6CONbits
;
4940 #define _PWM6POL 0x10
4941 #define _PWM6OUT 0x20
4942 #define _PWM6EN 0x80
4944 //==============================================================================
4947 //==============================================================================
4950 extern __at(0x061C) __sfr PWM6CON0
;
4958 unsigned PWM6POL
: 1;
4959 unsigned PWM6OUT
: 1;
4961 unsigned PWM6EN
: 1;
4964 extern __at(0x061C) volatile __PWM6CON0bits_t PWM6CON0bits
;
4966 #define _PWM6CON0_PWM6POL 0x10
4967 #define _PWM6CON0_PWM6OUT 0x20
4968 #define _PWM6CON0_PWM6EN 0x80
4970 //==============================================================================
4973 //==============================================================================
4976 extern __at(0x061F) __sfr PWMTMRS
;
4982 unsigned P5TSEL0
: 1;
4983 unsigned P5TSEL1
: 1;
4984 unsigned P6TSEL0
: 1;
4985 unsigned P6TSEL1
: 1;
4994 unsigned P5TSEL
: 2;
5001 unsigned P6TSEL
: 2;
5006 extern __at(0x061F) volatile __PWMTMRSbits_t PWMTMRSbits
;
5008 #define _P5TSEL0 0x01
5009 #define _P5TSEL1 0x02
5010 #define _P6TSEL0 0x04
5011 #define _P6TSEL1 0x08
5013 //==============================================================================
5016 //==============================================================================
5019 extern __at(0x0691) __sfr CWG1CLKCON
;
5037 unsigned CWG1CS
: 1;
5046 } __CWG1CLKCONbits_t
;
5048 extern __at(0x0691) volatile __CWG1CLKCONbits_t CWG1CLKCONbits
;
5051 #define _CWG1CS 0x01
5053 //==============================================================================
5056 //==============================================================================
5059 extern __at(0x0692) __sfr CWG1DAT
;
5065 unsigned CWG1DAT0
: 1;
5066 unsigned CWG1DAT1
: 1;
5067 unsigned CWG1DAT2
: 1;
5068 unsigned CWG1DAT3
: 1;
5077 unsigned CWG1DAT
: 4;
5082 extern __at(0x0692) volatile __CWG1DATbits_t CWG1DATbits
;
5084 #define _CWG1DAT0 0x01
5085 #define _CWG1DAT1 0x02
5086 #define _CWG1DAT2 0x04
5087 #define _CWG1DAT3 0x08
5089 //==============================================================================
5092 //==============================================================================
5095 extern __at(0x0693) __sfr CWG1DBR
;
5113 unsigned CWG1DBR0
: 1;
5114 unsigned CWG1DBR1
: 1;
5115 unsigned CWG1DBR2
: 1;
5116 unsigned CWG1DBR3
: 1;
5117 unsigned CWG1DBR4
: 1;
5118 unsigned CWG1DBR5
: 1;
5125 unsigned CWG1DBR
: 6;
5136 extern __at(0x0693) volatile __CWG1DBRbits_t CWG1DBRbits
;
5139 #define _CWG1DBR0 0x01
5141 #define _CWG1DBR1 0x02
5143 #define _CWG1DBR2 0x04
5145 #define _CWG1DBR3 0x08
5147 #define _CWG1DBR4 0x10
5149 #define _CWG1DBR5 0x20
5151 //==============================================================================
5154 //==============================================================================
5157 extern __at(0x0694) __sfr CWG1DBF
;
5175 unsigned CWG1DBF0
: 1;
5176 unsigned CWG1DBF1
: 1;
5177 unsigned CWG1DBF2
: 1;
5178 unsigned CWG1DBF3
: 1;
5179 unsigned CWG1DBF4
: 1;
5180 unsigned CWG1DBF5
: 1;
5187 unsigned CWG1DBF
: 6;
5198 extern __at(0x0694) volatile __CWG1DBFbits_t CWG1DBFbits
;
5201 #define _CWG1DBF0 0x01
5203 #define _CWG1DBF1 0x02
5205 #define _CWG1DBF2 0x04
5207 #define _CWG1DBF3 0x08
5209 #define _CWG1DBF4 0x10
5211 #define _CWG1DBF5 0x20
5213 //==============================================================================
5216 //==============================================================================
5219 extern __at(0x0695) __sfr CWG1CON0
;
5237 unsigned CWG1MODE0
: 1;
5238 unsigned CWG1MODE1
: 1;
5239 unsigned CWG1MODE2
: 1;
5243 unsigned CWG1LD
: 1;
5256 unsigned CWG1EN
: 1;
5267 unsigned CWG1MODE
: 3;
5272 extern __at(0x0695) volatile __CWG1CON0bits_t CWG1CON0bits
;
5274 #define _CWG1CON0_MODE0 0x01
5275 #define _CWG1CON0_CWG1MODE0 0x01
5276 #define _CWG1CON0_MODE1 0x02
5277 #define _CWG1CON0_CWG1MODE1 0x02
5278 #define _CWG1CON0_MODE2 0x04
5279 #define _CWG1CON0_CWG1MODE2 0x04
5280 #define _CWG1CON0_LD 0x40
5281 #define _CWG1CON0_CWG1LD 0x40
5282 #define _CWG1CON0_EN 0x80
5283 #define _CWG1CON0_G1EN 0x80
5284 #define _CWG1CON0_CWG1EN 0x80
5286 //==============================================================================
5289 //==============================================================================
5292 extern __at(0x0696) __sfr CWG1CON1
;
5310 unsigned CWG1POLA
: 1;
5311 unsigned CWG1POLB
: 1;
5312 unsigned CWG1POLC
: 1;
5313 unsigned CWG1POLD
: 1;
5315 unsigned CWG1IN
: 1;
5321 extern __at(0x0696) volatile __CWG1CON1bits_t CWG1CON1bits
;
5324 #define _CWG1POLA 0x01
5326 #define _CWG1POLB 0x02
5328 #define _CWG1POLC 0x04
5330 #define _CWG1POLD 0x08
5332 #define _CWG1IN 0x20
5334 //==============================================================================
5337 //==============================================================================
5340 extern __at(0x0697) __sfr CWG1AS0
;
5353 unsigned SHUTDOWN
: 1;
5360 unsigned CWG1LSAC0
: 1;
5361 unsigned CWG1LSAC1
: 1;
5362 unsigned CWG1LSBD0
: 1;
5363 unsigned CWG1LSBD1
: 1;
5364 unsigned CWG1REN
: 1;
5365 unsigned CWG1SHUTDOWN
: 1;
5378 unsigned CWG1LSAC
: 2;
5392 unsigned CWG1LSBD
: 2;
5397 extern __at(0x0697) volatile __CWG1AS0bits_t CWG1AS0bits
;
5400 #define _CWG1LSAC0 0x04
5402 #define _CWG1LSAC1 0x08
5404 #define _CWG1LSBD0 0x10
5406 #define _CWG1LSBD1 0x20
5408 #define _CWG1REN 0x40
5409 #define _SHUTDOWN 0x80
5410 #define _CWG1SHUTDOWN 0x80
5412 //==============================================================================
5415 //==============================================================================
5418 extern __at(0x0698) __sfr CWG1AS1
;
5432 extern __at(0x0698) volatile __CWG1AS1bits_t CWG1AS1bits
;
5440 //==============================================================================
5443 //==============================================================================
5446 extern __at(0x0699) __sfr CWG1STR
;
5464 unsigned CWG1STRA
: 1;
5465 unsigned CWG1STRB
: 1;
5466 unsigned CWG1STRC
: 1;
5467 unsigned CWG1STRD
: 1;
5468 unsigned CWG1OVRA
: 1;
5469 unsigned CWG1OVRB
: 1;
5470 unsigned CWG1OVRC
: 1;
5471 unsigned CWG1OVRD
: 1;
5475 extern __at(0x0699) volatile __CWG1STRbits_t CWG1STRbits
;
5478 #define _CWG1STRA 0x01
5480 #define _CWG1STRB 0x02
5482 #define _CWG1STRC 0x04
5484 #define _CWG1STRD 0x08
5486 #define _CWG1OVRA 0x10
5488 #define _CWG1OVRB 0x20
5490 #define _CWG1OVRC 0x40
5492 #define _CWG1OVRD 0x80
5494 //==============================================================================
5497 //==============================================================================
5500 extern __at(0x0711) __sfr CWG2CLKCON
;
5518 unsigned CWG2CS
: 1;
5527 } __CWG2CLKCONbits_t
;
5529 extern __at(0x0711) volatile __CWG2CLKCONbits_t CWG2CLKCONbits
;
5531 #define _CWG2CLKCON_CS 0x01
5532 #define _CWG2CLKCON_CWG2CS 0x01
5534 //==============================================================================
5537 //==============================================================================
5540 extern __at(0x0712) __sfr CWG2DAT
;
5546 unsigned CWG2DAT0
: 1;
5547 unsigned CWG2DAT1
: 1;
5548 unsigned CWG2DAT2
: 1;
5549 unsigned CWG2DAT3
: 1;
5558 unsigned CWG2DAT
: 4;
5563 extern __at(0x0712) volatile __CWG2DATbits_t CWG2DATbits
;
5565 #define _CWG2DAT0 0x01
5566 #define _CWG2DAT1 0x02
5567 #define _CWG2DAT2 0x04
5568 #define _CWG2DAT3 0x08
5570 //==============================================================================
5573 //==============================================================================
5576 extern __at(0x0713) __sfr CWG2DBR
;
5594 unsigned CWG2DBR0
: 1;
5595 unsigned CWG2DBR1
: 1;
5596 unsigned CWG2DBR2
: 1;
5597 unsigned CWG2DBR3
: 1;
5598 unsigned CWG2DBR4
: 1;
5599 unsigned CWG2DBR5
: 1;
5612 unsigned CWG2DBR
: 6;
5617 extern __at(0x0713) volatile __CWG2DBRbits_t CWG2DBRbits
;
5619 #define _CWG2DBR_DBR0 0x01
5620 #define _CWG2DBR_CWG2DBR0 0x01
5621 #define _CWG2DBR_DBR1 0x02
5622 #define _CWG2DBR_CWG2DBR1 0x02
5623 #define _CWG2DBR_DBR2 0x04
5624 #define _CWG2DBR_CWG2DBR2 0x04
5625 #define _CWG2DBR_DBR3 0x08
5626 #define _CWG2DBR_CWG2DBR3 0x08
5627 #define _CWG2DBR_DBR4 0x10
5628 #define _CWG2DBR_CWG2DBR4 0x10
5629 #define _CWG2DBR_DBR5 0x20
5630 #define _CWG2DBR_CWG2DBR5 0x20
5632 //==============================================================================
5635 //==============================================================================
5638 extern __at(0x0714) __sfr CWG2DBF
;
5656 unsigned CWG2DBF0
: 1;
5657 unsigned CWG2DBF1
: 1;
5658 unsigned CWG2DBF2
: 1;
5659 unsigned CWG2DBF3
: 1;
5660 unsigned CWG2DBF4
: 1;
5661 unsigned CWG2DBF5
: 1;
5668 unsigned CWG2DBF
: 6;
5679 extern __at(0x0714) volatile __CWG2DBFbits_t CWG2DBFbits
;
5681 #define _CWG2DBF_DBF0 0x01
5682 #define _CWG2DBF_CWG2DBF0 0x01
5683 #define _CWG2DBF_DBF1 0x02
5684 #define _CWG2DBF_CWG2DBF1 0x02
5685 #define _CWG2DBF_DBF2 0x04
5686 #define _CWG2DBF_CWG2DBF2 0x04
5687 #define _CWG2DBF_DBF3 0x08
5688 #define _CWG2DBF_CWG2DBF3 0x08
5689 #define _CWG2DBF_DBF4 0x10
5690 #define _CWG2DBF_CWG2DBF4 0x10
5691 #define _CWG2DBF_DBF5 0x20
5692 #define _CWG2DBF_CWG2DBF5 0x20
5694 //==============================================================================
5697 //==============================================================================
5700 extern __at(0x0715) __sfr CWG2CON0
;
5718 unsigned CWG2MODE0
: 1;
5719 unsigned CWG2MODE1
: 1;
5720 unsigned CWG2MODE2
: 1;
5724 unsigned CWG2LD
: 1;
5737 unsigned CWG2EN
: 1;
5742 unsigned CWG2MODE
: 3;
5753 extern __at(0x0715) volatile __CWG2CON0bits_t CWG2CON0bits
;
5755 #define _CWG2CON0_MODE0 0x01
5756 #define _CWG2CON0_CWG2MODE0 0x01
5757 #define _CWG2CON0_MODE1 0x02
5758 #define _CWG2CON0_CWG2MODE1 0x02
5759 #define _CWG2CON0_MODE2 0x04
5760 #define _CWG2CON0_CWG2MODE2 0x04
5761 #define _CWG2CON0_LD 0x40
5762 #define _CWG2CON0_CWG2LD 0x40
5763 #define _CWG2CON0_EN 0x80
5764 #define _CWG2CON0_G2EN 0x80
5765 #define _CWG2CON0_CWG2EN 0x80
5767 //==============================================================================
5770 //==============================================================================
5773 extern __at(0x0716) __sfr CWG2CON1
;
5791 unsigned CWG2POLA
: 1;
5792 unsigned CWG2POLB
: 1;
5793 unsigned CWG2POLC
: 1;
5794 unsigned CWG2POLD
: 1;
5796 unsigned CWG2IN
: 1;
5802 extern __at(0x0716) volatile __CWG2CON1bits_t CWG2CON1bits
;
5804 #define _CWG2CON1_POLA 0x01
5805 #define _CWG2CON1_CWG2POLA 0x01
5806 #define _CWG2CON1_POLB 0x02
5807 #define _CWG2CON1_CWG2POLB 0x02
5808 #define _CWG2CON1_POLC 0x04
5809 #define _CWG2CON1_CWG2POLC 0x04
5810 #define _CWG2CON1_POLD 0x08
5811 #define _CWG2CON1_CWG2POLD 0x08
5812 #define _CWG2CON1_IN 0x20
5813 #define _CWG2CON1_CWG2IN 0x20
5815 //==============================================================================
5818 //==============================================================================
5821 extern __at(0x0717) __sfr CWG2AS0
;
5834 unsigned SHUTDOWN
: 1;
5841 unsigned CWG2LSAC0
: 1;
5842 unsigned CWG2LSAC1
: 1;
5843 unsigned CWG2LSBD0
: 1;
5844 unsigned CWG2LSBD1
: 1;
5845 unsigned CWG2REN
: 1;
5846 unsigned CWG2SHUTDOWN
: 1;
5852 unsigned CWG2LSAC
: 2;
5873 unsigned CWG2LSBD
: 2;
5878 extern __at(0x0717) volatile __CWG2AS0bits_t CWG2AS0bits
;
5880 #define _CWG2AS0_LSAC0 0x04
5881 #define _CWG2AS0_CWG2LSAC0 0x04
5882 #define _CWG2AS0_LSAC1 0x08
5883 #define _CWG2AS0_CWG2LSAC1 0x08
5884 #define _CWG2AS0_LSBD0 0x10
5885 #define _CWG2AS0_CWG2LSBD0 0x10
5886 #define _CWG2AS0_LSBD1 0x20
5887 #define _CWG2AS0_CWG2LSBD1 0x20
5888 #define _CWG2AS0_REN 0x40
5889 #define _CWG2AS0_CWG2REN 0x40
5890 #define _CWG2AS0_SHUTDOWN 0x80
5891 #define _CWG2AS0_CWG2SHUTDOWN 0x80
5893 //==============================================================================
5896 //==============================================================================
5899 extern __at(0x0718) __sfr CWG2AS1
;
5913 extern __at(0x0718) volatile __CWG2AS1bits_t CWG2AS1bits
;
5915 #define _CWG2AS1_AS0E 0x01
5916 #define _CWG2AS1_AS1E 0x02
5917 #define _CWG2AS1_AS2E 0x04
5918 #define _CWG2AS1_AS3E 0x08
5919 #define _CWG2AS1_AS4E 0x10
5921 //==============================================================================
5924 //==============================================================================
5927 extern __at(0x0719) __sfr CWG2STR
;
5945 unsigned CWG2STRA
: 1;
5946 unsigned CWG2STRB
: 1;
5947 unsigned CWG2STRC
: 1;
5948 unsigned CWG2STRD
: 1;
5949 unsigned CWG2OVRA
: 1;
5950 unsigned CWG2OVRB
: 1;
5951 unsigned CWG2OVRC
: 1;
5952 unsigned CWG2OVRD
: 1;
5956 extern __at(0x0719) volatile __CWG2STRbits_t CWG2STRbits
;
5958 #define _CWG2STR_STRA 0x01
5959 #define _CWG2STR_CWG2STRA 0x01
5960 #define _CWG2STR_STRB 0x02
5961 #define _CWG2STR_CWG2STRB 0x02
5962 #define _CWG2STR_STRC 0x04
5963 #define _CWG2STR_CWG2STRC 0x04
5964 #define _CWG2STR_STRD 0x08
5965 #define _CWG2STR_CWG2STRD 0x08
5966 #define _CWG2STR_OVRA 0x10
5967 #define _CWG2STR_CWG2OVRA 0x10
5968 #define _CWG2STR_OVRB 0x20
5969 #define _CWG2STR_CWG2OVRB 0x20
5970 #define _CWG2STR_OVRC 0x40
5971 #define _CWG2STR_CWG2OVRC 0x40
5972 #define _CWG2STR_OVRD 0x80
5973 #define _CWG2STR_CWG2OVRD 0x80
5975 //==============================================================================
5977 extern __at(0x0891) __sfr NVMADR
;
5979 //==============================================================================
5982 extern __at(0x0891) __sfr NVMADRL
;
5986 unsigned NVMADR0
: 1;
5987 unsigned NVMADR1
: 1;
5988 unsigned NVMADR2
: 1;
5989 unsigned NVMADR3
: 1;
5990 unsigned NVMADR4
: 1;
5991 unsigned NVMADR5
: 1;
5992 unsigned NVMADR6
: 1;
5993 unsigned NVMADR7
: 1;
5996 extern __at(0x0891) volatile __NVMADRLbits_t NVMADRLbits
;
5998 #define _NVMADR0 0x01
5999 #define _NVMADR1 0x02
6000 #define _NVMADR2 0x04
6001 #define _NVMADR3 0x08
6002 #define _NVMADR4 0x10
6003 #define _NVMADR5 0x20
6004 #define _NVMADR6 0x40
6005 #define _NVMADR7 0x80
6007 //==============================================================================
6010 //==============================================================================
6013 extern __at(0x0892) __sfr NVMADRH
;
6017 unsigned NVMADR8
: 1;
6018 unsigned NVMADR9
: 1;
6019 unsigned NVMADR10
: 1;
6020 unsigned NVMADR11
: 1;
6021 unsigned NVMADR12
: 1;
6022 unsigned NVMADR13
: 1;
6023 unsigned NVMADR14
: 1;
6027 extern __at(0x0892) volatile __NVMADRHbits_t NVMADRHbits
;
6029 #define _NVMADR8 0x01
6030 #define _NVMADR9 0x02
6031 #define _NVMADR10 0x04
6032 #define _NVMADR11 0x08
6033 #define _NVMADR12 0x10
6034 #define _NVMADR13 0x20
6035 #define _NVMADR14 0x40
6037 //==============================================================================
6039 extern __at(0x0893) __sfr NVMDAT
;
6041 //==============================================================================
6044 extern __at(0x0893) __sfr NVMDATL
;
6048 unsigned NVMDAT0
: 1;
6049 unsigned NVMDAT1
: 1;
6050 unsigned NVMDAT2
: 1;
6051 unsigned NVMDAT3
: 1;
6052 unsigned NVMDAT4
: 1;
6053 unsigned NVMDAT5
: 1;
6054 unsigned NVMDAT6
: 1;
6055 unsigned NVMDAT7
: 1;
6058 extern __at(0x0893) volatile __NVMDATLbits_t NVMDATLbits
;
6060 #define _NVMDAT0 0x01
6061 #define _NVMDAT1 0x02
6062 #define _NVMDAT2 0x04
6063 #define _NVMDAT3 0x08
6064 #define _NVMDAT4 0x10
6065 #define _NVMDAT5 0x20
6066 #define _NVMDAT6 0x40
6067 #define _NVMDAT7 0x80
6069 //==============================================================================
6072 //==============================================================================
6075 extern __at(0x0894) __sfr NVMDATH
;
6079 unsigned NVMDAT8
: 1;
6080 unsigned NVMDAT9
: 1;
6081 unsigned NVMDAT10
: 1;
6082 unsigned NVMDAT11
: 1;
6083 unsigned NVMDAT12
: 1;
6084 unsigned NVMDAT13
: 1;
6089 extern __at(0x0894) volatile __NVMDATHbits_t NVMDATHbits
;
6091 #define _NVMDAT8 0x01
6092 #define _NVMDAT9 0x02
6093 #define _NVMDAT10 0x04
6094 #define _NVMDAT11 0x08
6095 #define _NVMDAT12 0x10
6096 #define _NVMDAT13 0x20
6098 //==============================================================================
6101 //==============================================================================
6104 extern __at(0x0895) __sfr NVMCON1
;
6114 unsigned NVMREGS
: 1;
6118 extern __at(0x0895) volatile __NVMCON1bits_t NVMCON1bits
;
6126 #define _NVMREGS 0x40
6128 //==============================================================================
6130 extern __at(0x0896) __sfr NVMCON2
;
6132 //==============================================================================
6135 extern __at(0x089B) __sfr PCON0
;
6139 unsigned NOT_BOR
: 1;
6140 unsigned NOT_POR
: 1;
6141 unsigned NOT_RI
: 1;
6142 unsigned NOT_RMCLR
: 1;
6143 unsigned NOT_RWDT
: 1;
6145 unsigned STKUNF
: 1;
6146 unsigned STKOVF
: 1;
6149 extern __at(0x089B) volatile __PCON0bits_t PCON0bits
;
6151 #define _NOT_BOR 0x01
6152 #define _NOT_POR 0x02
6153 #define _NOT_RI 0x04
6154 #define _NOT_RMCLR 0x08
6155 #define _NOT_RWDT 0x10
6156 #define _STKUNF 0x40
6157 #define _STKOVF 0x80
6159 //==============================================================================
6162 //==============================================================================
6165 extern __at(0x0911) __sfr PMD0
;
6170 unsigned CLKRMD
: 1;
6176 unsigned SYSCMD
: 1;
6179 extern __at(0x0911) volatile __PMD0bits_t PMD0bits
;
6182 #define _CLKRMD 0x02
6185 #define _SYSCMD 0x80
6187 //==============================================================================
6190 //==============================================================================
6193 extern __at(0x0912) __sfr PMD1
;
6197 unsigned TMR0MD
: 1;
6198 unsigned TMR1MD
: 1;
6199 unsigned TMR2MD
: 1;
6200 unsigned TMR3MD
: 1;
6201 unsigned TMR4MD
: 1;
6202 unsigned TMR5MD
: 1;
6203 unsigned TMR6MD
: 1;
6207 extern __at(0x0912) volatile __PMD1bits_t PMD1bits
;
6209 #define _TMR0MD 0x01
6210 #define _TMR1MD 0x02
6211 #define _TMR2MD 0x04
6212 #define _TMR3MD 0x08
6213 #define _TMR4MD 0x10
6214 #define _TMR5MD 0x20
6215 #define _TMR6MD 0x40
6218 //==============================================================================
6221 //==============================================================================
6224 extern __at(0x0913) __sfr PMD2
;
6229 unsigned CMP1MD
: 1;
6230 unsigned CMP2MD
: 1;
6238 extern __at(0x0913) volatile __PMD2bits_t PMD2bits
;
6240 #define _CMP1MD 0x02
6241 #define _CMP2MD 0x04
6245 //==============================================================================
6248 //==============================================================================
6251 extern __at(0x0914) __sfr PMD3
;
6255 unsigned CCP1MD
: 1;
6256 unsigned CCP2MD
: 1;
6257 unsigned CCP3MD
: 1;
6258 unsigned CCP4MD
: 1;
6259 unsigned PWM5MD
: 1;
6260 unsigned PWM6MD
: 1;
6261 unsigned CWG1MD
: 1;
6262 unsigned CWG2MD
: 1;
6265 extern __at(0x0914) volatile __PMD3bits_t PMD3bits
;
6267 #define _CCP1MD 0x01
6268 #define _CCP2MD 0x02
6269 #define _CCP3MD 0x04
6270 #define _CCP4MD 0x08
6271 #define _PWM5MD 0x10
6272 #define _PWM6MD 0x20
6273 #define _CWG1MD 0x40
6274 #define _CWG2MD 0x80
6276 //==============================================================================
6279 //==============================================================================
6282 extern __at(0x0915) __sfr PMD4
;
6287 unsigned MSSP1MD
: 1;
6288 unsigned MSSP2MD
: 1;
6291 unsigned UART1MD
: 1;
6296 extern __at(0x0915) volatile __PMD4bits_t PMD4bits
;
6298 #define _MSSP1MD 0x02
6299 #define _MSSP2MD 0x04
6300 #define _UART1MD 0x20
6302 //==============================================================================
6305 //==============================================================================
6308 extern __at(0x0916) __sfr PMD5
;
6313 unsigned CLC1MD
: 1;
6314 unsigned CLC2MD
: 1;
6315 unsigned CLC3MD
: 1;
6316 unsigned CLC4MD
: 1;
6322 extern __at(0x0916) volatile __PMD5bits_t PMD5bits
;
6325 #define _CLC1MD 0x02
6326 #define _CLC2MD 0x04
6327 #define _CLC3MD 0x08
6328 #define _CLC4MD 0x10
6330 //==============================================================================
6333 //==============================================================================
6336 extern __at(0x0918) __sfr CPUDOZE
;
6359 extern __at(0x0918) volatile __CPUDOZEbits_t CPUDOZEbits
;
6369 //==============================================================================
6372 //==============================================================================
6375 extern __at(0x0919) __sfr OSCCON1
;
6405 extern __at(0x0919) volatile __OSCCON1bits_t OSCCON1bits
;
6415 //==============================================================================
6418 //==============================================================================
6421 extern __at(0x091A) __sfr OSCCON2
;
6451 extern __at(0x091A) volatile __OSCCON2bits_t OSCCON2bits
;
6461 //==============================================================================
6464 //==============================================================================
6467 extern __at(0x091B) __sfr OSCCON3
;
6476 unsigned SOSCBE
: 1;
6477 unsigned SOSCPWR
: 1;
6478 unsigned CSWHOLD
: 1;
6481 extern __at(0x091B) volatile __OSCCON3bits_t OSCCON3bits
;
6485 #define _SOSCBE 0x20
6486 #define _SOSCPWR 0x40
6487 #define _CSWHOLD 0x80
6489 //==============================================================================
6492 //==============================================================================
6495 extern __at(0x091C) __sfr OSCSTAT1
;
6509 extern __at(0x091C) volatile __OSCSTAT1bits_t OSCSTAT1bits
;
6518 //==============================================================================
6521 //==============================================================================
6524 extern __at(0x091D) __sfr OSCEN
;
6531 unsigned SOSCEN
: 1;
6535 unsigned EXTOEN
: 1;
6538 extern __at(0x091D) volatile __OSCENbits_t OSCENbits
;
6541 #define _SOSCEN 0x08
6544 #define _EXTOEN 0x80
6546 //==============================================================================
6549 //==============================================================================
6552 extern __at(0x091E) __sfr OSCTUNE
;
6558 unsigned HFTUN0
: 1;
6559 unsigned HFTUN1
: 1;
6560 unsigned HFTUN2
: 1;
6561 unsigned HFTUN3
: 1;
6562 unsigned HFTUN4
: 1;
6563 unsigned HFTUN5
: 1;
6575 extern __at(0x091E) volatile __OSCTUNEbits_t OSCTUNEbits
;
6577 #define _HFTUN0 0x01
6578 #define _HFTUN1 0x02
6579 #define _HFTUN2 0x04
6580 #define _HFTUN3 0x08
6581 #define _HFTUN4 0x10
6582 #define _HFTUN5 0x20
6584 //==============================================================================
6587 //==============================================================================
6590 extern __at(0x091F) __sfr OSCFRQ
;
6596 unsigned HFFRQ0
: 1;
6597 unsigned HFFRQ1
: 1;
6598 unsigned HFFRQ2
: 1;
6599 unsigned HFFRQ3
: 1;
6613 extern __at(0x091F) volatile __OSCFRQbits_t OSCFRQbits
;
6615 #define _HFFRQ0 0x01
6616 #define _HFFRQ1 0x02
6617 #define _HFFRQ2 0x04
6618 #define _HFFRQ3 0x08
6620 //==============================================================================
6623 //==============================================================================
6626 extern __at(0x0E0F) __sfr PPSLOCK
;
6630 unsigned PPSLOCKED
: 1;
6640 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
6642 #define _PPSLOCKED 0x01
6644 //==============================================================================
6647 //==============================================================================
6650 extern __at(0x0E10) __sfr INTPPS
;
6656 unsigned INTPPS0
: 1;
6657 unsigned INTPPS1
: 1;
6658 unsigned INTPPS2
: 1;
6659 unsigned INTPPS3
: 1;
6660 unsigned INTPPS4
: 1;
6668 unsigned INTPPS
: 5;
6673 extern __at(0x0E10) volatile __INTPPSbits_t INTPPSbits
;
6675 #define _INTPPS0 0x01
6676 #define _INTPPS1 0x02
6677 #define _INTPPS2 0x04
6678 #define _INTPPS3 0x08
6679 #define _INTPPS4 0x10
6681 //==============================================================================
6684 //==============================================================================
6687 extern __at(0x0E11) __sfr T0CKIPPS
;
6693 unsigned T0CKIPPS0
: 1;
6694 unsigned T0CKIPPS1
: 1;
6695 unsigned T0CKIPPS2
: 1;
6696 unsigned T0CKIPPS3
: 1;
6697 unsigned T0CKIPPS4
: 1;
6705 unsigned T0CKIPPS
: 5;
6710 extern __at(0x0E11) volatile __T0CKIPPSbits_t T0CKIPPSbits
;
6712 #define _T0CKIPPS0 0x01
6713 #define _T0CKIPPS1 0x02
6714 #define _T0CKIPPS2 0x04
6715 #define _T0CKIPPS3 0x08
6716 #define _T0CKIPPS4 0x10
6718 //==============================================================================
6721 //==============================================================================
6724 extern __at(0x0E12) __sfr T1CKIPPS
;
6730 unsigned T1CKIPPS0
: 1;
6731 unsigned T1CKIPPS1
: 1;
6732 unsigned T1CKIPPS2
: 1;
6733 unsigned T1CKIPPS3
: 1;
6734 unsigned T1CKIPPS4
: 1;
6742 unsigned T1CKIPPS
: 5;
6747 extern __at(0x0E12) volatile __T1CKIPPSbits_t T1CKIPPSbits
;
6749 #define _T1CKIPPS0 0x01
6750 #define _T1CKIPPS1 0x02
6751 #define _T1CKIPPS2 0x04
6752 #define _T1CKIPPS3 0x08
6753 #define _T1CKIPPS4 0x10
6755 //==============================================================================
6758 //==============================================================================
6761 extern __at(0x0E13) __sfr T1GPPS
;
6767 unsigned T1GPPS0
: 1;
6768 unsigned T1GPPS1
: 1;
6769 unsigned T1GPPS2
: 1;
6770 unsigned T1GPPS3
: 1;
6771 unsigned T1GPPS4
: 1;
6779 unsigned T1GPPS
: 5;
6784 extern __at(0x0E13) volatile __T1GPPSbits_t T1GPPSbits
;
6786 #define _T1GPPS0 0x01
6787 #define _T1GPPS1 0x02
6788 #define _T1GPPS2 0x04
6789 #define _T1GPPS3 0x08
6790 #define _T1GPPS4 0x10
6792 //==============================================================================
6795 //==============================================================================
6798 extern __at(0x0E14) __sfr CCP1PPS
;
6804 unsigned CCP1PPS0
: 1;
6805 unsigned CCP1PPS1
: 1;
6806 unsigned CCP1PPS2
: 1;
6807 unsigned CCP1PPS3
: 1;
6808 unsigned CCP1PPS4
: 1;
6816 unsigned CCP1PPS
: 5;
6821 extern __at(0x0E14) volatile __CCP1PPSbits_t CCP1PPSbits
;
6823 #define _CCP1PPS0 0x01
6824 #define _CCP1PPS1 0x02
6825 #define _CCP1PPS2 0x04
6826 #define _CCP1PPS3 0x08
6827 #define _CCP1PPS4 0x10
6829 //==============================================================================
6832 //==============================================================================
6835 extern __at(0x0E15) __sfr CCP2PPS
;
6841 unsigned CCP2PPS0
: 1;
6842 unsigned CCP2PPS1
: 1;
6843 unsigned CCP2PPS2
: 1;
6844 unsigned CCP2PPS3
: 1;
6845 unsigned CCP2PPS4
: 1;
6853 unsigned CCP2PPS
: 5;
6858 extern __at(0x0E15) volatile __CCP2PPSbits_t CCP2PPSbits
;
6860 #define _CCP2PPS0 0x01
6861 #define _CCP2PPS1 0x02
6862 #define _CCP2PPS2 0x04
6863 #define _CCP2PPS3 0x08
6864 #define _CCP2PPS4 0x10
6866 //==============================================================================
6869 //==============================================================================
6872 extern __at(0x0E16) __sfr CCP3PPS
;
6878 unsigned CCP3PPS0
: 1;
6879 unsigned CCP3PPS1
: 1;
6880 unsigned CCP3PPS2
: 1;
6881 unsigned CCP3PPS3
: 1;
6882 unsigned CCP3PPS4
: 1;
6890 unsigned CCP3PPS
: 5;
6895 extern __at(0x0E16) volatile __CCP3PPSbits_t CCP3PPSbits
;
6897 #define _CCP3PPS0 0x01
6898 #define _CCP3PPS1 0x02
6899 #define _CCP3PPS2 0x04
6900 #define _CCP3PPS3 0x08
6901 #define _CCP3PPS4 0x10
6903 //==============================================================================
6906 //==============================================================================
6909 extern __at(0x0E17) __sfr CCP4PPS
;
6915 unsigned CCP4PPS0
: 1;
6916 unsigned CCP4PPS1
: 1;
6917 unsigned CCP4PPS2
: 1;
6918 unsigned CCP4PPS3
: 1;
6919 unsigned CCP4PPS4
: 1;
6927 unsigned CCP4PPS
: 5;
6932 extern __at(0x0E17) volatile __CCP4PPSbits_t CCP4PPSbits
;
6934 #define _CCP4PPS0 0x01
6935 #define _CCP4PPS1 0x02
6936 #define _CCP4PPS2 0x04
6937 #define _CCP4PPS3 0x08
6938 #define _CCP4PPS4 0x10
6940 //==============================================================================
6943 //==============================================================================
6946 extern __at(0x0E18) __sfr CWG1PPS
;
6952 unsigned CWG1PPS0
: 1;
6953 unsigned CWG1PPS1
: 1;
6954 unsigned CWG1PPS2
: 1;
6955 unsigned CWG1PPS3
: 1;
6956 unsigned CWG1PPS4
: 1;
6964 unsigned CWG1PPS
: 5;
6969 extern __at(0x0E18) volatile __CWG1PPSbits_t CWG1PPSbits
;
6971 #define _CWG1PPS0 0x01
6972 #define _CWG1PPS1 0x02
6973 #define _CWG1PPS2 0x04
6974 #define _CWG1PPS3 0x08
6975 #define _CWG1PPS4 0x10
6977 //==============================================================================
6980 //==============================================================================
6983 extern __at(0x0E19) __sfr CWG2PPS
;
6989 unsigned CWG2PPS0
: 1;
6990 unsigned CWG2PPS1
: 1;
6991 unsigned CWG2PPS2
: 1;
6992 unsigned CWG2PPS3
: 1;
6993 unsigned CWG2PPS4
: 1;
7001 unsigned CWG2PPS
: 5;
7006 extern __at(0x0E19) volatile __CWG2PPSbits_t CWG2PPSbits
;
7008 #define _CWG2PPS0 0x01
7009 #define _CWG2PPS1 0x02
7010 #define _CWG2PPS2 0x04
7011 #define _CWG2PPS3 0x08
7012 #define _CWG2PPS4 0x10
7014 //==============================================================================
7017 //==============================================================================
7020 extern __at(0x0E1A) __sfr MDCIN1PPS
;
7026 unsigned MDCIN1PPS0
: 1;
7027 unsigned MDCIN1PPS1
: 1;
7028 unsigned MDCIN1PPS2
: 1;
7029 unsigned MDCIN1PPS3
: 1;
7030 unsigned MDCIN1PPS4
: 1;
7038 unsigned MDCIN1PPS
: 5;
7041 } __MDCIN1PPSbits_t
;
7043 extern __at(0x0E1A) volatile __MDCIN1PPSbits_t MDCIN1PPSbits
;
7045 #define _MDCIN1PPS0 0x01
7046 #define _MDCIN1PPS1 0x02
7047 #define _MDCIN1PPS2 0x04
7048 #define _MDCIN1PPS3 0x08
7049 #define _MDCIN1PPS4 0x10
7051 //==============================================================================
7054 //==============================================================================
7057 extern __at(0x0E1B) __sfr MDCIN2PPS
;
7063 unsigned MDCIN2PPS0
: 1;
7064 unsigned MDCIN2PPS1
: 1;
7065 unsigned MDCIN2PPS2
: 1;
7066 unsigned MDCIN2PPS3
: 1;
7067 unsigned MDCIN2PPS4
: 1;
7075 unsigned MDCIN2PPS
: 5;
7078 } __MDCIN2PPSbits_t
;
7080 extern __at(0x0E1B) volatile __MDCIN2PPSbits_t MDCIN2PPSbits
;
7082 #define _MDCIN2PPS0 0x01
7083 #define _MDCIN2PPS1 0x02
7084 #define _MDCIN2PPS2 0x04
7085 #define _MDCIN2PPS3 0x08
7086 #define _MDCIN2PPS4 0x10
7088 //==============================================================================
7091 //==============================================================================
7094 extern __at(0x0E1C) __sfr MDMINPPS
;
7100 unsigned MDMINPPS0
: 1;
7101 unsigned MDMINPPS1
: 1;
7102 unsigned MDMINPPS2
: 1;
7103 unsigned MDMINPPS3
: 1;
7104 unsigned MDMINPPS4
: 1;
7112 unsigned MDMINPPS
: 5;
7117 extern __at(0x0E1C) volatile __MDMINPPSbits_t MDMINPPSbits
;
7119 #define _MDMINPPS0 0x01
7120 #define _MDMINPPS1 0x02
7121 #define _MDMINPPS2 0x04
7122 #define _MDMINPPS3 0x08
7123 #define _MDMINPPS4 0x10
7125 //==============================================================================
7128 //==============================================================================
7131 extern __at(0x0E1D) __sfr SSP2CLKPPS
;
7137 unsigned SSP2CLKPPS0
: 1;
7138 unsigned SSP2CLKPPS1
: 1;
7139 unsigned SSP2CLKPPS2
: 1;
7140 unsigned SSP2CLKPPS3
: 1;
7141 unsigned SSP2CLKPPS4
: 1;
7149 unsigned SSP2CLKPPS
: 5;
7152 } __SSP2CLKPPSbits_t
;
7154 extern __at(0x0E1D) volatile __SSP2CLKPPSbits_t SSP2CLKPPSbits
;
7156 #define _SSP2CLKPPS0 0x01
7157 #define _SSP2CLKPPS1 0x02
7158 #define _SSP2CLKPPS2 0x04
7159 #define _SSP2CLKPPS3 0x08
7160 #define _SSP2CLKPPS4 0x10
7162 //==============================================================================
7165 //==============================================================================
7168 extern __at(0x0E1E) __sfr SSP2DATPPS
;
7174 unsigned SSP2DATPPS0
: 1;
7175 unsigned SSP2DATPPS1
: 1;
7176 unsigned SSP2DATPPS2
: 1;
7177 unsigned SSP2DATPPS3
: 1;
7178 unsigned SSP2DATPPS4
: 1;
7186 unsigned SSP2DATPPS
: 5;
7189 } __SSP2DATPPSbits_t
;
7191 extern __at(0x0E1E) volatile __SSP2DATPPSbits_t SSP2DATPPSbits
;
7193 #define _SSP2DATPPS0 0x01
7194 #define _SSP2DATPPS1 0x02
7195 #define _SSP2DATPPS2 0x04
7196 #define _SSP2DATPPS3 0x08
7197 #define _SSP2DATPPS4 0x10
7199 //==============================================================================
7202 //==============================================================================
7205 extern __at(0x0E1F) __sfr SSP2SSPPS
;
7211 unsigned SSP2SSPPS0
: 1;
7212 unsigned SSP2SSPPS1
: 1;
7213 unsigned SSP2SSPPS2
: 1;
7214 unsigned SSP2SSPPS3
: 1;
7215 unsigned SSP2SSPPS4
: 1;
7223 unsigned SSP2SSPPS
: 5;
7226 } __SSP2SSPPSbits_t
;
7228 extern __at(0x0E1F) volatile __SSP2SSPPSbits_t SSP2SSPPSbits
;
7230 #define _SSP2SSPPS0 0x01
7231 #define _SSP2SSPPS1 0x02
7232 #define _SSP2SSPPS2 0x04
7233 #define _SSP2SSPPS3 0x08
7234 #define _SSP2SSPPS4 0x10
7236 //==============================================================================
7239 //==============================================================================
7242 extern __at(0x0E20) __sfr SSP1CLKPPS
;
7248 unsigned SSP1CLKPPS0
: 1;
7249 unsigned SSP1CLKPPS1
: 1;
7250 unsigned SSP1CLKPPS2
: 1;
7251 unsigned SSP1CLKPPS3
: 1;
7252 unsigned SSP1CLKPPS4
: 1;
7260 unsigned SSP1CLKPPS
: 5;
7263 } __SSP1CLKPPSbits_t
;
7265 extern __at(0x0E20) volatile __SSP1CLKPPSbits_t SSP1CLKPPSbits
;
7267 #define _SSP1CLKPPS0 0x01
7268 #define _SSP1CLKPPS1 0x02
7269 #define _SSP1CLKPPS2 0x04
7270 #define _SSP1CLKPPS3 0x08
7271 #define _SSP1CLKPPS4 0x10
7273 //==============================================================================
7276 //==============================================================================
7279 extern __at(0x0E21) __sfr SSP1DATPPS
;
7285 unsigned SSP1DATPPS0
: 1;
7286 unsigned SSP1DATPPS1
: 1;
7287 unsigned SSP1DATPPS2
: 1;
7288 unsigned SSP1DATPPS3
: 1;
7289 unsigned SSP1DATPPS4
: 1;
7297 unsigned SSP1DATPPS
: 5;
7300 } __SSP1DATPPSbits_t
;
7302 extern __at(0x0E21) volatile __SSP1DATPPSbits_t SSP1DATPPSbits
;
7304 #define _SSP1DATPPS0 0x01
7305 #define _SSP1DATPPS1 0x02
7306 #define _SSP1DATPPS2 0x04
7307 #define _SSP1DATPPS3 0x08
7308 #define _SSP1DATPPS4 0x10
7310 //==============================================================================
7313 //==============================================================================
7316 extern __at(0x0E22) __sfr SSP1SSPPS
;
7322 unsigned SSP1SSPPS0
: 1;
7323 unsigned SSP1SSPPS1
: 1;
7324 unsigned SSP1SSPPS2
: 1;
7325 unsigned SSP1SSPPS3
: 1;
7326 unsigned SSP1SSPPS4
: 1;
7334 unsigned SSP1SSPPS
: 5;
7337 } __SSP1SSPPSbits_t
;
7339 extern __at(0x0E22) volatile __SSP1SSPPSbits_t SSP1SSPPSbits
;
7341 #define _SSP1SSPPS0 0x01
7342 #define _SSP1SSPPS1 0x02
7343 #define _SSP1SSPPS2 0x04
7344 #define _SSP1SSPPS3 0x08
7345 #define _SSP1SSPPS4 0x10
7347 //==============================================================================
7350 //==============================================================================
7353 extern __at(0x0E24) __sfr RXPPS
;
7359 unsigned RXDTPPS0
: 1;
7360 unsigned RXDTPPS1
: 1;
7361 unsigned RXDTPPS2
: 1;
7362 unsigned RXDTPPS3
: 1;
7363 unsigned RXDTPPS4
: 1;
7371 unsigned RXDTPPS
: 5;
7376 extern __at(0x0E24) volatile __RXPPSbits_t RXPPSbits
;
7378 #define _RXDTPPS0 0x01
7379 #define _RXDTPPS1 0x02
7380 #define _RXDTPPS2 0x04
7381 #define _RXDTPPS3 0x08
7382 #define _RXDTPPS4 0x10
7384 //==============================================================================
7387 //==============================================================================
7390 extern __at(0x0E25) __sfr TXPPS
;
7396 unsigned TXCKPPS0
: 1;
7397 unsigned TXCKPPS1
: 1;
7398 unsigned TXCKPPS2
: 1;
7399 unsigned TXCKPPS3
: 1;
7400 unsigned TXCKPPS4
: 1;
7408 unsigned TXCKPPS
: 5;
7413 extern __at(0x0E25) volatile __TXPPSbits_t TXPPSbits
;
7415 #define _TXCKPPS0 0x01
7416 #define _TXCKPPS1 0x02
7417 #define _TXCKPPS2 0x04
7418 #define _TXCKPPS3 0x08
7419 #define _TXCKPPS4 0x10
7421 //==============================================================================
7424 //==============================================================================
7427 extern __at(0x0E28) __sfr CLCIN0PPS
;
7433 unsigned CLCIN0PPS0
: 1;
7434 unsigned CLCIN0PPS1
: 1;
7435 unsigned CLCIN0PPS2
: 1;
7436 unsigned CLCIN0PPS3
: 1;
7437 unsigned CLCIN0PPS4
: 1;
7445 unsigned CLCIN0PPS
: 5;
7448 } __CLCIN0PPSbits_t
;
7450 extern __at(0x0E28) volatile __CLCIN0PPSbits_t CLCIN0PPSbits
;
7452 #define _CLCIN0PPS0 0x01
7453 #define _CLCIN0PPS1 0x02
7454 #define _CLCIN0PPS2 0x04
7455 #define _CLCIN0PPS3 0x08
7456 #define _CLCIN0PPS4 0x10
7458 //==============================================================================
7461 //==============================================================================
7464 extern __at(0x0E29) __sfr CLCIN1PPS
;
7470 unsigned CLCIN1PPS0
: 1;
7471 unsigned CLCIN1PPS1
: 1;
7472 unsigned CLCIN1PPS2
: 1;
7473 unsigned CLCIN1PPS3
: 1;
7474 unsigned CLCIN1PPS4
: 1;
7482 unsigned CLCIN1PPS
: 5;
7485 } __CLCIN1PPSbits_t
;
7487 extern __at(0x0E29) volatile __CLCIN1PPSbits_t CLCIN1PPSbits
;
7489 #define _CLCIN1PPS0 0x01
7490 #define _CLCIN1PPS1 0x02
7491 #define _CLCIN1PPS2 0x04
7492 #define _CLCIN1PPS3 0x08
7493 #define _CLCIN1PPS4 0x10
7495 //==============================================================================
7498 //==============================================================================
7501 extern __at(0x0E2A) __sfr CLCIN2PPS
;
7507 unsigned CLCIN2PPS0
: 1;
7508 unsigned CLCIN2PPS1
: 1;
7509 unsigned CLCIN2PPS2
: 1;
7510 unsigned CLCIN2PPS3
: 1;
7511 unsigned CLCIN2PPS4
: 1;
7519 unsigned CLCIN2PPS
: 5;
7522 } __CLCIN2PPSbits_t
;
7524 extern __at(0x0E2A) volatile __CLCIN2PPSbits_t CLCIN2PPSbits
;
7526 #define _CLCIN2PPS0 0x01
7527 #define _CLCIN2PPS1 0x02
7528 #define _CLCIN2PPS2 0x04
7529 #define _CLCIN2PPS3 0x08
7530 #define _CLCIN2PPS4 0x10
7532 //==============================================================================
7535 //==============================================================================
7538 extern __at(0x0E2B) __sfr CLCIN3PPS
;
7544 unsigned CLCIN3PPS0
: 1;
7545 unsigned CLCIN3PPS1
: 1;
7546 unsigned CLCIN3PPS2
: 1;
7547 unsigned CLCIN3PPS3
: 1;
7548 unsigned CLCIN3PPS4
: 1;
7556 unsigned CLCIN3PPS
: 5;
7559 } __CLCIN3PPSbits_t
;
7561 extern __at(0x0E2B) volatile __CLCIN3PPSbits_t CLCIN3PPSbits
;
7563 #define _CLCIN3PPS0 0x01
7564 #define _CLCIN3PPS1 0x02
7565 #define _CLCIN3PPS2 0x04
7566 #define _CLCIN3PPS3 0x08
7567 #define _CLCIN3PPS4 0x10
7569 //==============================================================================
7571 extern __at(0x0E2C) __sfr T3CKIPPS
;
7572 extern __at(0x0E2D) __sfr T3GPPS
;
7573 extern __at(0x0E2E) __sfr T5CKIPPS
;
7574 extern __at(0x0E2F) __sfr T5GPPS
;
7576 //==============================================================================
7579 extern __at(0x0E90) __sfr RA0PPS
;
7585 unsigned RA0PPS0
: 1;
7586 unsigned RA0PPS1
: 1;
7587 unsigned RA0PPS2
: 1;
7588 unsigned RA0PPS3
: 1;
7589 unsigned RA0PPS4
: 1;
7597 unsigned RA0PPS
: 5;
7602 extern __at(0x0E90) volatile __RA0PPSbits_t RA0PPSbits
;
7604 #define _RA0PPS0 0x01
7605 #define _RA0PPS1 0x02
7606 #define _RA0PPS2 0x04
7607 #define _RA0PPS3 0x08
7608 #define _RA0PPS4 0x10
7610 //==============================================================================
7613 //==============================================================================
7616 extern __at(0x0E91) __sfr RA1PPS
;
7622 unsigned RA1PPS0
: 1;
7623 unsigned RA1PPS1
: 1;
7624 unsigned RA1PPS2
: 1;
7625 unsigned RA1PPS3
: 1;
7626 unsigned RA1PPS4
: 1;
7634 unsigned RA1PPS
: 5;
7639 extern __at(0x0E91) volatile __RA1PPSbits_t RA1PPSbits
;
7641 #define _RA1PPS0 0x01
7642 #define _RA1PPS1 0x02
7643 #define _RA1PPS2 0x04
7644 #define _RA1PPS3 0x08
7645 #define _RA1PPS4 0x10
7647 //==============================================================================
7650 //==============================================================================
7653 extern __at(0x0E92) __sfr RA2PPS
;
7659 unsigned RA2PPS0
: 1;
7660 unsigned RA2PPS1
: 1;
7661 unsigned RA2PPS2
: 1;
7662 unsigned RA2PPS3
: 1;
7663 unsigned RA2PPS4
: 1;
7671 unsigned RA2PPS
: 5;
7676 extern __at(0x0E92) volatile __RA2PPSbits_t RA2PPSbits
;
7678 #define _RA2PPS0 0x01
7679 #define _RA2PPS1 0x02
7680 #define _RA2PPS2 0x04
7681 #define _RA2PPS3 0x08
7682 #define _RA2PPS4 0x10
7684 //==============================================================================
7687 //==============================================================================
7690 extern __at(0x0E94) __sfr RA4PPS
;
7696 unsigned RA4PPS0
: 1;
7697 unsigned RA4PPS1
: 1;
7698 unsigned RA4PPS2
: 1;
7699 unsigned RA4PPS3
: 1;
7700 unsigned RA4PPS4
: 1;
7708 unsigned RA4PPS
: 5;
7713 extern __at(0x0E94) volatile __RA4PPSbits_t RA4PPSbits
;
7715 #define _RA4PPS0 0x01
7716 #define _RA4PPS1 0x02
7717 #define _RA4PPS2 0x04
7718 #define _RA4PPS3 0x08
7719 #define _RA4PPS4 0x10
7721 //==============================================================================
7724 //==============================================================================
7727 extern __at(0x0E95) __sfr RA5PPS
;
7733 unsigned RA5PPS0
: 1;
7734 unsigned RA5PPS1
: 1;
7735 unsigned RA5PPS2
: 1;
7736 unsigned RA5PPS3
: 1;
7737 unsigned RA5PPS4
: 1;
7745 unsigned RA5PPS
: 5;
7750 extern __at(0x0E95) volatile __RA5PPSbits_t RA5PPSbits
;
7752 #define _RA5PPS0 0x01
7753 #define _RA5PPS1 0x02
7754 #define _RA5PPS2 0x04
7755 #define _RA5PPS3 0x08
7756 #define _RA5PPS4 0x10
7758 //==============================================================================
7761 //==============================================================================
7764 extern __at(0x0EA0) __sfr RC0PPS
;
7770 unsigned RC0PPS0
: 1;
7771 unsigned RC0PPS1
: 1;
7772 unsigned RC0PPS2
: 1;
7773 unsigned RC0PPS3
: 1;
7774 unsigned RC0PPS4
: 1;
7782 unsigned RC0PPS
: 5;
7787 extern __at(0x0EA0) volatile __RC0PPSbits_t RC0PPSbits
;
7789 #define _RC0PPS0 0x01
7790 #define _RC0PPS1 0x02
7791 #define _RC0PPS2 0x04
7792 #define _RC0PPS3 0x08
7793 #define _RC0PPS4 0x10
7795 //==============================================================================
7798 //==============================================================================
7801 extern __at(0x0EA1) __sfr RC1PPS
;
7807 unsigned RC1PPS0
: 1;
7808 unsigned RC1PPS1
: 1;
7809 unsigned RC1PPS2
: 1;
7810 unsigned RC1PPS3
: 1;
7811 unsigned RC1PPS4
: 1;
7819 unsigned RC1PPS
: 5;
7824 extern __at(0x0EA1) volatile __RC1PPSbits_t RC1PPSbits
;
7826 #define _RC1PPS0 0x01
7827 #define _RC1PPS1 0x02
7828 #define _RC1PPS2 0x04
7829 #define _RC1PPS3 0x08
7830 #define _RC1PPS4 0x10
7832 //==============================================================================
7835 //==============================================================================
7838 extern __at(0x0EA2) __sfr RC2PPS
;
7844 unsigned RC2PPS0
: 1;
7845 unsigned RC2PPS1
: 1;
7846 unsigned RC2PPS2
: 1;
7847 unsigned RC2PPS3
: 1;
7848 unsigned RC2PPS4
: 1;
7856 unsigned RC2PPS
: 5;
7861 extern __at(0x0EA2) volatile __RC2PPSbits_t RC2PPSbits
;
7863 #define _RC2PPS0 0x01
7864 #define _RC2PPS1 0x02
7865 #define _RC2PPS2 0x04
7866 #define _RC2PPS3 0x08
7867 #define _RC2PPS4 0x10
7869 //==============================================================================
7872 //==============================================================================
7875 extern __at(0x0EA3) __sfr RC3PPS
;
7881 unsigned RC3PPS0
: 1;
7882 unsigned RC3PPS1
: 1;
7883 unsigned RC3PPS2
: 1;
7884 unsigned RC3PPS3
: 1;
7885 unsigned RC3PPS4
: 1;
7893 unsigned RC3PPS
: 5;
7898 extern __at(0x0EA3) volatile __RC3PPSbits_t RC3PPSbits
;
7900 #define _RC3PPS0 0x01
7901 #define _RC3PPS1 0x02
7902 #define _RC3PPS2 0x04
7903 #define _RC3PPS3 0x08
7904 #define _RC3PPS4 0x10
7906 //==============================================================================
7909 //==============================================================================
7912 extern __at(0x0EA4) __sfr RC4PPS
;
7918 unsigned RC4PPS0
: 1;
7919 unsigned RC4PPS1
: 1;
7920 unsigned RC4PPS2
: 1;
7921 unsigned RC4PPS3
: 1;
7922 unsigned RC4PPS4
: 1;
7930 unsigned RC4PPS
: 5;
7935 extern __at(0x0EA4) volatile __RC4PPSbits_t RC4PPSbits
;
7937 #define _RC4PPS0 0x01
7938 #define _RC4PPS1 0x02
7939 #define _RC4PPS2 0x04
7940 #define _RC4PPS3 0x08
7941 #define _RC4PPS4 0x10
7943 //==============================================================================
7946 //==============================================================================
7949 extern __at(0x0EA5) __sfr RC5PPS
;
7955 unsigned RC5PPS0
: 1;
7956 unsigned RC5PPS1
: 1;
7957 unsigned RC5PPS2
: 1;
7958 unsigned RC5PPS3
: 1;
7959 unsigned RC5PPS4
: 1;
7967 unsigned RC5PPS
: 5;
7972 extern __at(0x0EA5) volatile __RC5PPSbits_t RC5PPSbits
;
7974 #define _RC5PPS0 0x01
7975 #define _RC5PPS1 0x02
7976 #define _RC5PPS2 0x04
7977 #define _RC5PPS3 0x08
7978 #define _RC5PPS4 0x10
7980 //==============================================================================
7983 //==============================================================================
7986 extern __at(0x0F0F) __sfr CLCDATA
;
7990 unsigned MLC1OUT
: 1;
7991 unsigned MLC2OUT
: 1;
7992 unsigned MLC3OUT
: 1;
7993 unsigned MLC4OUT
: 1;
8000 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
8002 #define _MLC1OUT 0x01
8003 #define _MLC2OUT 0x02
8004 #define _MLC3OUT 0x04
8005 #define _MLC4OUT 0x08
8007 //==============================================================================
8010 //==============================================================================
8013 extern __at(0x0F10) __sfr CLC1CON
;
8019 unsigned LC1MODE0
: 1;
8020 unsigned LC1MODE1
: 1;
8021 unsigned LC1MODE2
: 1;
8022 unsigned LC1INTN
: 1;
8023 unsigned LC1INTP
: 1;
8024 unsigned LC1OUT
: 1;
8049 unsigned LC1MODE
: 3;
8054 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
8056 #define _LC1MODE0 0x01
8058 #define _LC1MODE1 0x02
8060 #define _LC1MODE2 0x04
8062 #define _LC1INTN 0x08
8064 #define _LC1INTP 0x10
8066 #define _LC1OUT 0x20
8071 //==============================================================================
8074 //==============================================================================
8077 extern __at(0x0F11) __sfr CLC1POL
;
8083 unsigned LC1G1POL
: 1;
8084 unsigned LC1G2POL
: 1;
8085 unsigned LC1G3POL
: 1;
8086 unsigned LC1G4POL
: 1;
8090 unsigned LC1POL
: 1;
8106 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
8108 #define _LC1G1POL 0x01
8110 #define _LC1G2POL 0x02
8112 #define _LC1G3POL 0x04
8114 #define _LC1G4POL 0x08
8116 #define _LC1POL 0x80
8119 //==============================================================================
8122 //==============================================================================
8125 extern __at(0x0F12) __sfr CLC1SEL0
;
8131 unsigned LC1D1S0
: 1;
8132 unsigned LC1D1S1
: 1;
8133 unsigned LC1D1S2
: 1;
8134 unsigned LC1D1S3
: 1;
8135 unsigned LC1D1S4
: 1;
8136 unsigned LC1D1S5
: 1;
8155 unsigned LC1D1S
: 6;
8166 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
8168 #define _LC1D1S0 0x01
8170 #define _LC1D1S1 0x02
8172 #define _LC1D1S2 0x04
8174 #define _LC1D1S3 0x08
8176 #define _LC1D1S4 0x10
8178 #define _LC1D1S5 0x20
8181 //==============================================================================
8184 //==============================================================================
8187 extern __at(0x0F13) __sfr CLC1SEL1
;
8193 unsigned LC1D2S0
: 1;
8194 unsigned LC1D2S1
: 1;
8195 unsigned LC1D2S2
: 1;
8196 unsigned LC1D2S3
: 1;
8197 unsigned LC1D2S4
: 1;
8198 unsigned LC1D2S5
: 1;
8223 unsigned LC1D2S
: 6;
8228 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
8230 #define _LC1D2S0 0x01
8232 #define _LC1D2S1 0x02
8234 #define _LC1D2S2 0x04
8236 #define _LC1D2S3 0x08
8238 #define _LC1D2S4 0x10
8240 #define _LC1D2S5 0x20
8243 //==============================================================================
8246 //==============================================================================
8249 extern __at(0x0F14) __sfr CLC1SEL2
;
8255 unsigned LC1D3S0
: 1;
8256 unsigned LC1D3S1
: 1;
8257 unsigned LC1D3S2
: 1;
8258 unsigned LC1D3S3
: 1;
8259 unsigned LC1D3S4
: 1;
8260 unsigned LC1D3S5
: 1;
8279 unsigned LC1D3S
: 6;
8290 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
8292 #define _LC1D3S0 0x01
8294 #define _LC1D3S1 0x02
8296 #define _LC1D3S2 0x04
8298 #define _LC1D3S3 0x08
8300 #define _LC1D3S4 0x10
8302 #define _LC1D3S5 0x20
8305 //==============================================================================
8308 //==============================================================================
8311 extern __at(0x0F15) __sfr CLC1SEL3
;
8317 unsigned LC1D4S0
: 1;
8318 unsigned LC1D4S1
: 1;
8319 unsigned LC1D4S2
: 1;
8320 unsigned LC1D4S3
: 1;
8321 unsigned LC1D4S4
: 1;
8322 unsigned LC1D4S5
: 1;
8341 unsigned LC1D4S
: 6;
8352 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
8354 #define _LC1D4S0 0x01
8356 #define _LC1D4S1 0x02
8358 #define _LC1D4S2 0x04
8360 #define _LC1D4S3 0x08
8362 #define _LC1D4S4 0x10
8364 #define _LC1D4S5 0x20
8367 //==============================================================================
8370 //==============================================================================
8373 extern __at(0x0F16) __sfr CLC1GLS0
;
8379 unsigned LC1G1D1N
: 1;
8380 unsigned LC1G1D1T
: 1;
8381 unsigned LC1G1D2N
: 1;
8382 unsigned LC1G1D2T
: 1;
8383 unsigned LC1G1D3N
: 1;
8384 unsigned LC1G1D3T
: 1;
8385 unsigned LC1G1D4N
: 1;
8386 unsigned LC1G1D4T
: 1;
8402 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
8404 #define _LC1G1D1N 0x01
8406 #define _LC1G1D1T 0x02
8408 #define _LC1G1D2N 0x04
8410 #define _LC1G1D2T 0x08
8412 #define _LC1G1D3N 0x10
8414 #define _LC1G1D3T 0x20
8416 #define _LC1G1D4N 0x40
8418 #define _LC1G1D4T 0x80
8421 //==============================================================================
8424 //==============================================================================
8427 extern __at(0x0F17) __sfr CLC1GLS1
;
8433 unsigned LC1G2D1N
: 1;
8434 unsigned LC1G2D1T
: 1;
8435 unsigned LC1G2D2N
: 1;
8436 unsigned LC1G2D2T
: 1;
8437 unsigned LC1G2D3N
: 1;
8438 unsigned LC1G2D3T
: 1;
8439 unsigned LC1G2D4N
: 1;
8440 unsigned LC1G2D4T
: 1;
8456 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
8458 #define _CLC1GLS1_LC1G2D1N 0x01
8459 #define _CLC1GLS1_D1N 0x01
8460 #define _CLC1GLS1_LC1G2D1T 0x02
8461 #define _CLC1GLS1_D1T 0x02
8462 #define _CLC1GLS1_LC1G2D2N 0x04
8463 #define _CLC1GLS1_D2N 0x04
8464 #define _CLC1GLS1_LC1G2D2T 0x08
8465 #define _CLC1GLS1_D2T 0x08
8466 #define _CLC1GLS1_LC1G2D3N 0x10
8467 #define _CLC1GLS1_D3N 0x10
8468 #define _CLC1GLS1_LC1G2D3T 0x20
8469 #define _CLC1GLS1_D3T 0x20
8470 #define _CLC1GLS1_LC1G2D4N 0x40
8471 #define _CLC1GLS1_D4N 0x40
8472 #define _CLC1GLS1_LC1G2D4T 0x80
8473 #define _CLC1GLS1_D4T 0x80
8475 //==============================================================================
8478 //==============================================================================
8481 extern __at(0x0F18) __sfr CLC1GLS2
;
8487 unsigned LC1G3D1N
: 1;
8488 unsigned LC1G3D1T
: 1;
8489 unsigned LC1G3D2N
: 1;
8490 unsigned LC1G3D2T
: 1;
8491 unsigned LC1G3D3N
: 1;
8492 unsigned LC1G3D3T
: 1;
8493 unsigned LC1G3D4N
: 1;
8494 unsigned LC1G3D4T
: 1;
8510 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
8512 #define _CLC1GLS2_LC1G3D1N 0x01
8513 #define _CLC1GLS2_D1N 0x01
8514 #define _CLC1GLS2_LC1G3D1T 0x02
8515 #define _CLC1GLS2_D1T 0x02
8516 #define _CLC1GLS2_LC1G3D2N 0x04
8517 #define _CLC1GLS2_D2N 0x04
8518 #define _CLC1GLS2_LC1G3D2T 0x08
8519 #define _CLC1GLS2_D2T 0x08
8520 #define _CLC1GLS2_LC1G3D3N 0x10
8521 #define _CLC1GLS2_D3N 0x10
8522 #define _CLC1GLS2_LC1G3D3T 0x20
8523 #define _CLC1GLS2_D3T 0x20
8524 #define _CLC1GLS2_LC1G3D4N 0x40
8525 #define _CLC1GLS2_D4N 0x40
8526 #define _CLC1GLS2_LC1G3D4T 0x80
8527 #define _CLC1GLS2_D4T 0x80
8529 //==============================================================================
8532 //==============================================================================
8535 extern __at(0x0F19) __sfr CLC1GLS3
;
8541 unsigned LC1G4D1N
: 1;
8542 unsigned LC1G4D1T
: 1;
8543 unsigned LC1G4D2N
: 1;
8544 unsigned LC1G4D2T
: 1;
8545 unsigned LC1G4D3N
: 1;
8546 unsigned LC1G4D3T
: 1;
8547 unsigned LC1G4D4N
: 1;
8548 unsigned LC1G4D4T
: 1;
8564 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
8566 #define _LC1G4D1N 0x01
8568 #define _LC1G4D1T 0x02
8570 #define _LC1G4D2N 0x04
8572 #define _LC1G4D2T 0x08
8574 #define _LC1G4D3N 0x10
8576 #define _LC1G4D3T 0x20
8578 #define _LC1G4D4N 0x40
8580 #define _LC1G4D4T 0x80
8583 //==============================================================================
8586 //==============================================================================
8589 extern __at(0x0F1A) __sfr CLC2CON
;
8595 unsigned LC2MODE0
: 1;
8596 unsigned LC2MODE1
: 1;
8597 unsigned LC2MODE2
: 1;
8598 unsigned LC2INTN
: 1;
8599 unsigned LC2INTP
: 1;
8600 unsigned LC2OUT
: 1;
8625 unsigned LC2MODE
: 3;
8630 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
8632 #define _CLC2CON_LC2MODE0 0x01
8633 #define _CLC2CON_MODE0 0x01
8634 #define _CLC2CON_LC2MODE1 0x02
8635 #define _CLC2CON_MODE1 0x02
8636 #define _CLC2CON_LC2MODE2 0x04
8637 #define _CLC2CON_MODE2 0x04
8638 #define _CLC2CON_LC2INTN 0x08
8639 #define _CLC2CON_INTN 0x08
8640 #define _CLC2CON_LC2INTP 0x10
8641 #define _CLC2CON_INTP 0x10
8642 #define _CLC2CON_LC2OUT 0x20
8643 #define _CLC2CON_OUT 0x20
8644 #define _CLC2CON_LC2EN 0x80
8645 #define _CLC2CON_EN 0x80
8647 //==============================================================================
8650 //==============================================================================
8653 extern __at(0x0F1B) __sfr CLC2POL
;
8659 unsigned LC2G1POL
: 1;
8660 unsigned LC2G2POL
: 1;
8661 unsigned LC2G3POL
: 1;
8662 unsigned LC2G4POL
: 1;
8666 unsigned LC2POL
: 1;
8682 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
8684 #define _CLC2POL_LC2G1POL 0x01
8685 #define _CLC2POL_G1POL 0x01
8686 #define _CLC2POL_LC2G2POL 0x02
8687 #define _CLC2POL_G2POL 0x02
8688 #define _CLC2POL_LC2G3POL 0x04
8689 #define _CLC2POL_G3POL 0x04
8690 #define _CLC2POL_LC2G4POL 0x08
8691 #define _CLC2POL_G4POL 0x08
8692 #define _CLC2POL_LC2POL 0x80
8693 #define _CLC2POL_POL 0x80
8695 //==============================================================================
8698 //==============================================================================
8701 extern __at(0x0F1C) __sfr CLC2SEL0
;
8707 unsigned LC2D1S0
: 1;
8708 unsigned LC2D1S1
: 1;
8709 unsigned LC2D1S2
: 1;
8710 unsigned LC2D1S3
: 1;
8711 unsigned LC2D1S4
: 1;
8712 unsigned LC2D1S5
: 1;
8731 unsigned LC2D1S
: 6;
8742 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
8744 #define _CLC2SEL0_LC2D1S0 0x01
8745 #define _CLC2SEL0_D1S0 0x01
8746 #define _CLC2SEL0_LC2D1S1 0x02
8747 #define _CLC2SEL0_D1S1 0x02
8748 #define _CLC2SEL0_LC2D1S2 0x04
8749 #define _CLC2SEL0_D1S2 0x04
8750 #define _CLC2SEL0_LC2D1S3 0x08
8751 #define _CLC2SEL0_D1S3 0x08
8752 #define _CLC2SEL0_LC2D1S4 0x10
8753 #define _CLC2SEL0_D1S4 0x10
8754 #define _CLC2SEL0_LC2D1S5 0x20
8755 #define _CLC2SEL0_D1S5 0x20
8757 //==============================================================================
8760 //==============================================================================
8763 extern __at(0x0F1D) __sfr CLC2SEL1
;
8769 unsigned LC2D2S0
: 1;
8770 unsigned LC2D2S1
: 1;
8771 unsigned LC2D2S2
: 1;
8772 unsigned LC2D2S3
: 1;
8773 unsigned LC2D2S4
: 1;
8774 unsigned LC2D2S5
: 1;
8799 unsigned LC2D2S
: 6;
8804 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
8806 #define _CLC2SEL1_LC2D2S0 0x01
8807 #define _CLC2SEL1_D2S0 0x01
8808 #define _CLC2SEL1_LC2D2S1 0x02
8809 #define _CLC2SEL1_D2S1 0x02
8810 #define _CLC2SEL1_LC2D2S2 0x04
8811 #define _CLC2SEL1_D2S2 0x04
8812 #define _CLC2SEL1_LC2D2S3 0x08
8813 #define _CLC2SEL1_D2S3 0x08
8814 #define _CLC2SEL1_LC2D2S4 0x10
8815 #define _CLC2SEL1_D2S4 0x10
8816 #define _CLC2SEL1_LC2D2S5 0x20
8817 #define _CLC2SEL1_D2S5 0x20
8819 //==============================================================================
8822 //==============================================================================
8825 extern __at(0x0F1E) __sfr CLC2SEL2
;
8831 unsigned LC2D3S0
: 1;
8832 unsigned LC2D3S1
: 1;
8833 unsigned LC2D3S2
: 1;
8834 unsigned LC2D3S3
: 1;
8835 unsigned LC2D3S4
: 1;
8836 unsigned LC2D3S5
: 1;
8855 unsigned LC2D3S
: 6;
8866 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
8868 #define _CLC2SEL2_LC2D3S0 0x01
8869 #define _CLC2SEL2_D3S0 0x01
8870 #define _CLC2SEL2_LC2D3S1 0x02
8871 #define _CLC2SEL2_D3S1 0x02
8872 #define _CLC2SEL2_LC2D3S2 0x04
8873 #define _CLC2SEL2_D3S2 0x04
8874 #define _CLC2SEL2_LC2D3S3 0x08
8875 #define _CLC2SEL2_D3S3 0x08
8876 #define _CLC2SEL2_LC2D3S4 0x10
8877 #define _CLC2SEL2_D3S4 0x10
8878 #define _CLC2SEL2_LC2D3S5 0x20
8879 #define _CLC2SEL2_D3S5 0x20
8881 //==============================================================================
8884 //==============================================================================
8887 extern __at(0x0F1F) __sfr CLC2SEL3
;
8893 unsigned LC2D4S0
: 1;
8894 unsigned LC2D4S1
: 1;
8895 unsigned LC2D4S2
: 1;
8896 unsigned LC2D4S3
: 1;
8897 unsigned LC2D4S4
: 1;
8898 unsigned LC2D4S5
: 1;
8923 unsigned LC2D4S
: 6;
8928 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
8930 #define _CLC2SEL3_LC2D4S0 0x01
8931 #define _CLC2SEL3_D4S0 0x01
8932 #define _CLC2SEL3_LC2D4S1 0x02
8933 #define _CLC2SEL3_D4S1 0x02
8934 #define _CLC2SEL3_LC2D4S2 0x04
8935 #define _CLC2SEL3_D4S2 0x04
8936 #define _CLC2SEL3_LC2D4S3 0x08
8937 #define _CLC2SEL3_D4S3 0x08
8938 #define _CLC2SEL3_LC2D4S4 0x10
8939 #define _CLC2SEL3_D4S4 0x10
8940 #define _CLC2SEL3_LC2D4S5 0x20
8941 #define _CLC2SEL3_D4S5 0x20
8943 //==============================================================================
8946 //==============================================================================
8949 extern __at(0x0F20) __sfr CLC2GLS0
;
8955 unsigned LC2G1D1N
: 1;
8956 unsigned LC2G1D1T
: 1;
8957 unsigned LC2G1D2N
: 1;
8958 unsigned LC2G1D2T
: 1;
8959 unsigned LC2G1D3N
: 1;
8960 unsigned LC2G1D3T
: 1;
8961 unsigned LC2G1D4N
: 1;
8962 unsigned LC2G1D4T
: 1;
8978 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
8980 #define _CLC2GLS0_LC2G1D1N 0x01
8981 #define _CLC2GLS0_D1N 0x01
8982 #define _CLC2GLS0_LC2G1D1T 0x02
8983 #define _CLC2GLS0_D1T 0x02
8984 #define _CLC2GLS0_LC2G1D2N 0x04
8985 #define _CLC2GLS0_D2N 0x04
8986 #define _CLC2GLS0_LC2G1D2T 0x08
8987 #define _CLC2GLS0_D2T 0x08
8988 #define _CLC2GLS0_LC2G1D3N 0x10
8989 #define _CLC2GLS0_D3N 0x10
8990 #define _CLC2GLS0_LC2G1D3T 0x20
8991 #define _CLC2GLS0_D3T 0x20
8992 #define _CLC2GLS0_LC2G1D4N 0x40
8993 #define _CLC2GLS0_D4N 0x40
8994 #define _CLC2GLS0_LC2G1D4T 0x80
8995 #define _CLC2GLS0_D4T 0x80
8997 //==============================================================================
9000 //==============================================================================
9003 extern __at(0x0F21) __sfr CLC2GLS1
;
9009 unsigned LC2G2D1N
: 1;
9010 unsigned LC2G2D1T
: 1;
9011 unsigned LC2G2D2N
: 1;
9012 unsigned LC2G2D2T
: 1;
9013 unsigned LC2G2D3N
: 1;
9014 unsigned LC2G2D3T
: 1;
9015 unsigned LC2G2D4N
: 1;
9016 unsigned LC2G2D4T
: 1;
9032 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
9034 #define _CLC2GLS1_LC2G2D1N 0x01
9035 #define _CLC2GLS1_D1N 0x01
9036 #define _CLC2GLS1_LC2G2D1T 0x02
9037 #define _CLC2GLS1_D1T 0x02
9038 #define _CLC2GLS1_LC2G2D2N 0x04
9039 #define _CLC2GLS1_D2N 0x04
9040 #define _CLC2GLS1_LC2G2D2T 0x08
9041 #define _CLC2GLS1_D2T 0x08
9042 #define _CLC2GLS1_LC2G2D3N 0x10
9043 #define _CLC2GLS1_D3N 0x10
9044 #define _CLC2GLS1_LC2G2D3T 0x20
9045 #define _CLC2GLS1_D3T 0x20
9046 #define _CLC2GLS1_LC2G2D4N 0x40
9047 #define _CLC2GLS1_D4N 0x40
9048 #define _CLC2GLS1_LC2G2D4T 0x80
9049 #define _CLC2GLS1_D4T 0x80
9051 //==============================================================================
9054 //==============================================================================
9057 extern __at(0x0F22) __sfr CLC2GLS2
;
9063 unsigned LC2G3D1N
: 1;
9064 unsigned LC2G3D1T
: 1;
9065 unsigned LC2G3D2N
: 1;
9066 unsigned LC2G3D2T
: 1;
9067 unsigned LC2G3D3N
: 1;
9068 unsigned LC2G3D3T
: 1;
9069 unsigned LC2G3D4N
: 1;
9070 unsigned LC2G3D4T
: 1;
9086 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
9088 #define _CLC2GLS2_LC2G3D1N 0x01
9089 #define _CLC2GLS2_D1N 0x01
9090 #define _CLC2GLS2_LC2G3D1T 0x02
9091 #define _CLC2GLS2_D1T 0x02
9092 #define _CLC2GLS2_LC2G3D2N 0x04
9093 #define _CLC2GLS2_D2N 0x04
9094 #define _CLC2GLS2_LC2G3D2T 0x08
9095 #define _CLC2GLS2_D2T 0x08
9096 #define _CLC2GLS2_LC2G3D3N 0x10
9097 #define _CLC2GLS2_D3N 0x10
9098 #define _CLC2GLS2_LC2G3D3T 0x20
9099 #define _CLC2GLS2_D3T 0x20
9100 #define _CLC2GLS2_LC2G3D4N 0x40
9101 #define _CLC2GLS2_D4N 0x40
9102 #define _CLC2GLS2_LC2G3D4T 0x80
9103 #define _CLC2GLS2_D4T 0x80
9105 //==============================================================================
9108 //==============================================================================
9111 extern __at(0x0F23) __sfr CLC2GLS3
;
9117 unsigned LC2G4D1N
: 1;
9118 unsigned LC2G4D1T
: 1;
9119 unsigned LC2G4D2N
: 1;
9120 unsigned LC2G4D2T
: 1;
9121 unsigned LC2G4D3N
: 1;
9122 unsigned LC2G4D3T
: 1;
9123 unsigned LC2G4D4N
: 1;
9124 unsigned LC2G4D4T
: 1;
9140 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
9142 #define _CLC2GLS3_LC2G4D1N 0x01
9143 #define _CLC2GLS3_G4D1N 0x01
9144 #define _CLC2GLS3_LC2G4D1T 0x02
9145 #define _CLC2GLS3_G4D1T 0x02
9146 #define _CLC2GLS3_LC2G4D2N 0x04
9147 #define _CLC2GLS3_G4D2N 0x04
9148 #define _CLC2GLS3_LC2G4D2T 0x08
9149 #define _CLC2GLS3_G4D2T 0x08
9150 #define _CLC2GLS3_LC2G4D3N 0x10
9151 #define _CLC2GLS3_G4D3N 0x10
9152 #define _CLC2GLS3_LC2G4D3T 0x20
9153 #define _CLC2GLS3_G4D3T 0x20
9154 #define _CLC2GLS3_LC2G4D4N 0x40
9155 #define _CLC2GLS3_G4D4N 0x40
9156 #define _CLC2GLS3_LC2G4D4T 0x80
9157 #define _CLC2GLS3_G4D4T 0x80
9159 //==============================================================================
9162 //==============================================================================
9165 extern __at(0x0F24) __sfr CLC3CON
;
9171 unsigned LC3MODE0
: 1;
9172 unsigned LC3MODE1
: 1;
9173 unsigned LC3MODE2
: 1;
9174 unsigned LC3INTN
: 1;
9175 unsigned LC3INTP
: 1;
9176 unsigned LC3OUT
: 1;
9201 unsigned LC3MODE
: 3;
9206 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
9208 #define _CLC3CON_LC3MODE0 0x01
9209 #define _CLC3CON_MODE0 0x01
9210 #define _CLC3CON_LC3MODE1 0x02
9211 #define _CLC3CON_MODE1 0x02
9212 #define _CLC3CON_LC3MODE2 0x04
9213 #define _CLC3CON_MODE2 0x04
9214 #define _CLC3CON_LC3INTN 0x08
9215 #define _CLC3CON_INTN 0x08
9216 #define _CLC3CON_LC3INTP 0x10
9217 #define _CLC3CON_INTP 0x10
9218 #define _CLC3CON_LC3OUT 0x20
9219 #define _CLC3CON_OUT 0x20
9220 #define _CLC3CON_LC3EN 0x80
9221 #define _CLC3CON_EN 0x80
9223 //==============================================================================
9226 //==============================================================================
9229 extern __at(0x0F25) __sfr CLC3POL
;
9235 unsigned LC3G1POL
: 1;
9236 unsigned LC3G2POL
: 1;
9237 unsigned LC3G3POL
: 1;
9238 unsigned LC3G4POL
: 1;
9242 unsigned LC3POL
: 1;
9258 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
9260 #define _CLC3POL_LC3G1POL 0x01
9261 #define _CLC3POL_G1POL 0x01
9262 #define _CLC3POL_LC3G2POL 0x02
9263 #define _CLC3POL_G2POL 0x02
9264 #define _CLC3POL_LC3G3POL 0x04
9265 #define _CLC3POL_G3POL 0x04
9266 #define _CLC3POL_LC3G4POL 0x08
9267 #define _CLC3POL_G4POL 0x08
9268 #define _CLC3POL_LC3POL 0x80
9269 #define _CLC3POL_POL 0x80
9271 //==============================================================================
9274 //==============================================================================
9277 extern __at(0x0F26) __sfr CLC3SEL0
;
9283 unsigned LC3D1S0
: 1;
9284 unsigned LC3D1S1
: 1;
9285 unsigned LC3D1S2
: 1;
9286 unsigned LC3D1S3
: 1;
9287 unsigned LC3D1S4
: 1;
9288 unsigned LC3D1S5
: 1;
9307 unsigned LC3D1S
: 6;
9318 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
9320 #define _CLC3SEL0_LC3D1S0 0x01
9321 #define _CLC3SEL0_D1S0 0x01
9322 #define _CLC3SEL0_LC3D1S1 0x02
9323 #define _CLC3SEL0_D1S1 0x02
9324 #define _CLC3SEL0_LC3D1S2 0x04
9325 #define _CLC3SEL0_D1S2 0x04
9326 #define _CLC3SEL0_LC3D1S3 0x08
9327 #define _CLC3SEL0_D1S3 0x08
9328 #define _CLC3SEL0_LC3D1S4 0x10
9329 #define _CLC3SEL0_D1S4 0x10
9330 #define _CLC3SEL0_LC3D1S5 0x20
9331 #define _CLC3SEL0_D1S5 0x20
9333 //==============================================================================
9336 //==============================================================================
9339 extern __at(0x0F27) __sfr CLC3SEL1
;
9345 unsigned LC3D2S0
: 1;
9346 unsigned LC3D2S1
: 1;
9347 unsigned LC3D2S2
: 1;
9348 unsigned LC3D2S3
: 1;
9349 unsigned LC3D2S4
: 1;
9350 unsigned LC3D2S5
: 1;
9375 unsigned LC3D2S
: 6;
9380 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
9382 #define _CLC3SEL1_LC3D2S0 0x01
9383 #define _CLC3SEL1_D2S0 0x01
9384 #define _CLC3SEL1_LC3D2S1 0x02
9385 #define _CLC3SEL1_D2S1 0x02
9386 #define _CLC3SEL1_LC3D2S2 0x04
9387 #define _CLC3SEL1_D2S2 0x04
9388 #define _CLC3SEL1_LC3D2S3 0x08
9389 #define _CLC3SEL1_D2S3 0x08
9390 #define _CLC3SEL1_LC3D2S4 0x10
9391 #define _CLC3SEL1_D2S4 0x10
9392 #define _CLC3SEL1_LC3D2S5 0x20
9393 #define _CLC3SEL1_D2S5 0x20
9395 //==============================================================================
9398 //==============================================================================
9401 extern __at(0x0F28) __sfr CLC3SEL2
;
9407 unsigned LC3D3S0
: 1;
9408 unsigned LC3D3S1
: 1;
9409 unsigned LC3D3S2
: 1;
9410 unsigned LC3D3S3
: 1;
9411 unsigned LC3D3S4
: 1;
9412 unsigned LC3D3S5
: 1;
9431 unsigned LC3D3S
: 6;
9442 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
9444 #define _CLC3SEL2_LC3D3S0 0x01
9445 #define _CLC3SEL2_D3S0 0x01
9446 #define _CLC3SEL2_LC3D3S1 0x02
9447 #define _CLC3SEL2_D3S1 0x02
9448 #define _CLC3SEL2_LC3D3S2 0x04
9449 #define _CLC3SEL2_D3S2 0x04
9450 #define _CLC3SEL2_LC3D3S3 0x08
9451 #define _CLC3SEL2_D3S3 0x08
9452 #define _CLC3SEL2_LC3D3S4 0x10
9453 #define _CLC3SEL2_D3S4 0x10
9454 #define _CLC3SEL2_LC3D3S5 0x20
9455 #define _CLC3SEL2_D3S5 0x20
9457 //==============================================================================
9460 //==============================================================================
9463 extern __at(0x0F29) __sfr CLC3SEL3
;
9469 unsigned LC3D4S0
: 1;
9470 unsigned LC3D4S1
: 1;
9471 unsigned LC3D4S2
: 1;
9472 unsigned LC3D4S3
: 1;
9473 unsigned LC3D4S4
: 1;
9474 unsigned LC3D4S5
: 1;
9499 unsigned LC3D4S
: 6;
9504 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
9506 #define _CLC3SEL3_LC3D4S0 0x01
9507 #define _CLC3SEL3_D4S0 0x01
9508 #define _CLC3SEL3_LC3D4S1 0x02
9509 #define _CLC3SEL3_D4S1 0x02
9510 #define _CLC3SEL3_LC3D4S2 0x04
9511 #define _CLC3SEL3_D4S2 0x04
9512 #define _CLC3SEL3_LC3D4S3 0x08
9513 #define _CLC3SEL3_D4S3 0x08
9514 #define _CLC3SEL3_LC3D4S4 0x10
9515 #define _CLC3SEL3_D4S4 0x10
9516 #define _CLC3SEL3_LC3D4S5 0x20
9517 #define _CLC3SEL3_D4S5 0x20
9519 //==============================================================================
9522 //==============================================================================
9525 extern __at(0x0F2A) __sfr CLC3GLS0
;
9531 unsigned LC3G1D1N
: 1;
9532 unsigned LC3G1D1T
: 1;
9533 unsigned LC3G1D2N
: 1;
9534 unsigned LC3G1D2T
: 1;
9535 unsigned LC3G1D3N
: 1;
9536 unsigned LC3G1D3T
: 1;
9537 unsigned LC3G1D4N
: 1;
9538 unsigned LC3G1D4T
: 1;
9554 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
9556 #define _CLC3GLS0_LC3G1D1N 0x01
9557 #define _CLC3GLS0_D1N 0x01
9558 #define _CLC3GLS0_LC3G1D1T 0x02
9559 #define _CLC3GLS0_D1T 0x02
9560 #define _CLC3GLS0_LC3G1D2N 0x04
9561 #define _CLC3GLS0_D2N 0x04
9562 #define _CLC3GLS0_LC3G1D2T 0x08
9563 #define _CLC3GLS0_D2T 0x08
9564 #define _CLC3GLS0_LC3G1D3N 0x10
9565 #define _CLC3GLS0_D3N 0x10
9566 #define _CLC3GLS0_LC3G1D3T 0x20
9567 #define _CLC3GLS0_D3T 0x20
9568 #define _CLC3GLS0_LC3G1D4N 0x40
9569 #define _CLC3GLS0_D4N 0x40
9570 #define _CLC3GLS0_LC3G1D4T 0x80
9571 #define _CLC3GLS0_D4T 0x80
9573 //==============================================================================
9576 //==============================================================================
9579 extern __at(0x0F2B) __sfr CLC3GLS1
;
9585 unsigned LC3G2D1N
: 1;
9586 unsigned LC3G2D1T
: 1;
9587 unsigned LC3G2D2N
: 1;
9588 unsigned LC3G2D2T
: 1;
9589 unsigned LC3G2D3N
: 1;
9590 unsigned LC3G2D3T
: 1;
9591 unsigned LC3G2D4N
: 1;
9592 unsigned LC3G2D4T
: 1;
9608 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
9610 #define _CLC3GLS1_LC3G2D1N 0x01
9611 #define _CLC3GLS1_D1N 0x01
9612 #define _CLC3GLS1_LC3G2D1T 0x02
9613 #define _CLC3GLS1_D1T 0x02
9614 #define _CLC3GLS1_LC3G2D2N 0x04
9615 #define _CLC3GLS1_D2N 0x04
9616 #define _CLC3GLS1_LC3G2D2T 0x08
9617 #define _CLC3GLS1_D2T 0x08
9618 #define _CLC3GLS1_LC3G2D3N 0x10
9619 #define _CLC3GLS1_D3N 0x10
9620 #define _CLC3GLS1_LC3G2D3T 0x20
9621 #define _CLC3GLS1_D3T 0x20
9622 #define _CLC3GLS1_LC3G2D4N 0x40
9623 #define _CLC3GLS1_D4N 0x40
9624 #define _CLC3GLS1_LC3G2D4T 0x80
9625 #define _CLC3GLS1_D4T 0x80
9627 //==============================================================================
9630 //==============================================================================
9633 extern __at(0x0F2C) __sfr CLC3GLS2
;
9639 unsigned LC3G3D1N
: 1;
9640 unsigned LC3G3D1T
: 1;
9641 unsigned LC3G3D2N
: 1;
9642 unsigned LC3G3D2T
: 1;
9643 unsigned LC3G3D3N
: 1;
9644 unsigned LC3G3D3T
: 1;
9645 unsigned LC3G3D4N
: 1;
9646 unsigned LC3G3D4T
: 1;
9662 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
9664 #define _CLC3GLS2_LC3G3D1N 0x01
9665 #define _CLC3GLS2_D1N 0x01
9666 #define _CLC3GLS2_LC3G3D1T 0x02
9667 #define _CLC3GLS2_D1T 0x02
9668 #define _CLC3GLS2_LC3G3D2N 0x04
9669 #define _CLC3GLS2_D2N 0x04
9670 #define _CLC3GLS2_LC3G3D2T 0x08
9671 #define _CLC3GLS2_D2T 0x08
9672 #define _CLC3GLS2_LC3G3D3N 0x10
9673 #define _CLC3GLS2_D3N 0x10
9674 #define _CLC3GLS2_LC3G3D3T 0x20
9675 #define _CLC3GLS2_D3T 0x20
9676 #define _CLC3GLS2_LC3G3D4N 0x40
9677 #define _CLC3GLS2_D4N 0x40
9678 #define _CLC3GLS2_LC3G3D4T 0x80
9679 #define _CLC3GLS2_D4T 0x80
9681 //==============================================================================
9684 //==============================================================================
9687 extern __at(0x0F2D) __sfr CLC3GLS3
;
9693 unsigned LC3G4D1N
: 1;
9694 unsigned LC3G4D1T
: 1;
9695 unsigned LC3G4D2N
: 1;
9696 unsigned LC3G4D2T
: 1;
9697 unsigned LC3G4D3N
: 1;
9698 unsigned LC3G4D3T
: 1;
9699 unsigned LC3G4D4N
: 1;
9700 unsigned LC3G4D4T
: 1;
9716 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
9718 #define _CLC3GLS3_LC3G4D1N 0x01
9719 #define _CLC3GLS3_G4D1N 0x01
9720 #define _CLC3GLS3_LC3G4D1T 0x02
9721 #define _CLC3GLS3_G4D1T 0x02
9722 #define _CLC3GLS3_LC3G4D2N 0x04
9723 #define _CLC3GLS3_G4D2N 0x04
9724 #define _CLC3GLS3_LC3G4D2T 0x08
9725 #define _CLC3GLS3_G4D2T 0x08
9726 #define _CLC3GLS3_LC3G4D3N 0x10
9727 #define _CLC3GLS3_G4D3N 0x10
9728 #define _CLC3GLS3_LC3G4D3T 0x20
9729 #define _CLC3GLS3_G4D3T 0x20
9730 #define _CLC3GLS3_LC3G4D4N 0x40
9731 #define _CLC3GLS3_G4D4N 0x40
9732 #define _CLC3GLS3_LC3G4D4T 0x80
9733 #define _CLC3GLS3_G4D4T 0x80
9735 //==============================================================================
9738 //==============================================================================
9741 extern __at(0x0F2E) __sfr CLC4CON
;
9747 unsigned LC4MODE0
: 1;
9748 unsigned LC4MODE1
: 1;
9749 unsigned LC4MODE2
: 1;
9750 unsigned LC4INTN
: 1;
9751 unsigned LC4INTP
: 1;
9752 unsigned LC4OUT
: 1;
9777 unsigned LC4MODE
: 3;
9782 extern __at(0x0F2E) volatile __CLC4CONbits_t CLC4CONbits
;
9784 #define _CLC4CON_LC4MODE0 0x01
9785 #define _CLC4CON_MODE0 0x01
9786 #define _CLC4CON_LC4MODE1 0x02
9787 #define _CLC4CON_MODE1 0x02
9788 #define _CLC4CON_LC4MODE2 0x04
9789 #define _CLC4CON_MODE2 0x04
9790 #define _CLC4CON_LC4INTN 0x08
9791 #define _CLC4CON_INTN 0x08
9792 #define _CLC4CON_LC4INTP 0x10
9793 #define _CLC4CON_INTP 0x10
9794 #define _CLC4CON_LC4OUT 0x20
9795 #define _CLC4CON_OUT 0x20
9796 #define _CLC4CON_LC4EN 0x80
9797 #define _CLC4CON_EN 0x80
9799 //==============================================================================
9802 //==============================================================================
9805 extern __at(0x0F2F) __sfr CLC4POL
;
9811 unsigned LC4G1POL
: 1;
9812 unsigned LC4G2POL
: 1;
9813 unsigned LC4G3POL
: 1;
9814 unsigned LC4G4POL
: 1;
9818 unsigned LC4POL
: 1;
9834 extern __at(0x0F2F) volatile __CLC4POLbits_t CLC4POLbits
;
9836 #define _CLC4POL_LC4G1POL 0x01
9837 #define _CLC4POL_G1POL 0x01
9838 #define _CLC4POL_LC4G2POL 0x02
9839 #define _CLC4POL_G2POL 0x02
9840 #define _CLC4POL_LC4G3POL 0x04
9841 #define _CLC4POL_G3POL 0x04
9842 #define _CLC4POL_LC4G4POL 0x08
9843 #define _CLC4POL_G4POL 0x08
9844 #define _CLC4POL_LC4POL 0x80
9845 #define _CLC4POL_POL 0x80
9847 //==============================================================================
9850 //==============================================================================
9853 extern __at(0x0F30) __sfr CLC4SEL0
;
9859 unsigned LC4D1S0
: 1;
9860 unsigned LC4D1S1
: 1;
9861 unsigned LC4D1S2
: 1;
9862 unsigned LC4D1S3
: 1;
9863 unsigned LC4D1S4
: 1;
9864 unsigned LC4D1S5
: 1;
9889 unsigned LC4D1S
: 6;
9894 extern __at(0x0F30) volatile __CLC4SEL0bits_t CLC4SEL0bits
;
9896 #define _CLC4SEL0_LC4D1S0 0x01
9897 #define _CLC4SEL0_D1S0 0x01
9898 #define _CLC4SEL0_LC4D1S1 0x02
9899 #define _CLC4SEL0_D1S1 0x02
9900 #define _CLC4SEL0_LC4D1S2 0x04
9901 #define _CLC4SEL0_D1S2 0x04
9902 #define _CLC4SEL0_LC4D1S3 0x08
9903 #define _CLC4SEL0_D1S3 0x08
9904 #define _CLC4SEL0_LC4D1S4 0x10
9905 #define _CLC4SEL0_D1S4 0x10
9906 #define _CLC4SEL0_LC4D1S5 0x20
9907 #define _CLC4SEL0_D1S5 0x20
9909 //==============================================================================
9912 //==============================================================================
9915 extern __at(0x0F31) __sfr CLC4SEL1
;
9921 unsigned LC4D2S0
: 1;
9922 unsigned LC4D2S1
: 1;
9923 unsigned LC4D2S2
: 1;
9924 unsigned LC4D2S3
: 1;
9925 unsigned LC4D2S4
: 1;
9926 unsigned LC4D2S5
: 1;
9951 unsigned LC4D2S
: 6;
9956 extern __at(0x0F31) volatile __CLC4SEL1bits_t CLC4SEL1bits
;
9958 #define _CLC4SEL1_LC4D2S0 0x01
9959 #define _CLC4SEL1_D2S0 0x01
9960 #define _CLC4SEL1_LC4D2S1 0x02
9961 #define _CLC4SEL1_D2S1 0x02
9962 #define _CLC4SEL1_LC4D2S2 0x04
9963 #define _CLC4SEL1_D2S2 0x04
9964 #define _CLC4SEL1_LC4D2S3 0x08
9965 #define _CLC4SEL1_D2S3 0x08
9966 #define _CLC4SEL1_LC4D2S4 0x10
9967 #define _CLC4SEL1_D2S4 0x10
9968 #define _CLC4SEL1_LC4D2S5 0x20
9969 #define _CLC4SEL1_D2S5 0x20
9971 //==============================================================================
9974 //==============================================================================
9977 extern __at(0x0F32) __sfr CLC4SEL2
;
9983 unsigned LC4D3S0
: 1;
9984 unsigned LC4D3S1
: 1;
9985 unsigned LC4D3S2
: 1;
9986 unsigned LC4D3S3
: 1;
9987 unsigned LC4D3S4
: 1;
9988 unsigned LC4D3S5
: 1;
10007 unsigned LC4D3S
: 6;
10016 } __CLC4SEL2bits_t
;
10018 extern __at(0x0F32) volatile __CLC4SEL2bits_t CLC4SEL2bits
;
10020 #define _CLC4SEL2_LC4D3S0 0x01
10021 #define _CLC4SEL2_D3S0 0x01
10022 #define _CLC4SEL2_LC4D3S1 0x02
10023 #define _CLC4SEL2_D3S1 0x02
10024 #define _CLC4SEL2_LC4D3S2 0x04
10025 #define _CLC4SEL2_D3S2 0x04
10026 #define _CLC4SEL2_LC4D3S3 0x08
10027 #define _CLC4SEL2_D3S3 0x08
10028 #define _CLC4SEL2_LC4D3S4 0x10
10029 #define _CLC4SEL2_D3S4 0x10
10030 #define _CLC4SEL2_LC4D3S5 0x20
10031 #define _CLC4SEL2_D3S5 0x20
10033 //==============================================================================
10036 //==============================================================================
10039 extern __at(0x0F33) __sfr CLC4SEL3
;
10045 unsigned LC4D4S0
: 1;
10046 unsigned LC4D4S1
: 1;
10047 unsigned LC4D4S2
: 1;
10048 unsigned LC4D4S3
: 1;
10049 unsigned LC4D4S4
: 1;
10050 unsigned LC4D4S5
: 1;
10075 unsigned LC4D4S
: 6;
10078 } __CLC4SEL3bits_t
;
10080 extern __at(0x0F33) volatile __CLC4SEL3bits_t CLC4SEL3bits
;
10082 #define _CLC4SEL3_LC4D4S0 0x01
10083 #define _CLC4SEL3_D4S0 0x01
10084 #define _CLC4SEL3_LC4D4S1 0x02
10085 #define _CLC4SEL3_D4S1 0x02
10086 #define _CLC4SEL3_LC4D4S2 0x04
10087 #define _CLC4SEL3_D4S2 0x04
10088 #define _CLC4SEL3_LC4D4S3 0x08
10089 #define _CLC4SEL3_D4S3 0x08
10090 #define _CLC4SEL3_LC4D4S4 0x10
10091 #define _CLC4SEL3_D4S4 0x10
10092 #define _CLC4SEL3_LC4D4S5 0x20
10093 #define _CLC4SEL3_D4S5 0x20
10095 //==============================================================================
10098 //==============================================================================
10101 extern __at(0x0F34) __sfr CLC4GLS0
;
10107 unsigned LC4G1D1N
: 1;
10108 unsigned LC4G1D1T
: 1;
10109 unsigned LC4G1D2N
: 1;
10110 unsigned LC4G1D2T
: 1;
10111 unsigned LC4G1D3N
: 1;
10112 unsigned LC4G1D3T
: 1;
10113 unsigned LC4G1D4N
: 1;
10114 unsigned LC4G1D4T
: 1;
10128 } __CLC4GLS0bits_t
;
10130 extern __at(0x0F34) volatile __CLC4GLS0bits_t CLC4GLS0bits
;
10132 #define _CLC4GLS0_LC4G1D1N 0x01
10133 #define _CLC4GLS0_D1N 0x01
10134 #define _CLC4GLS0_LC4G1D1T 0x02
10135 #define _CLC4GLS0_D1T 0x02
10136 #define _CLC4GLS0_LC4G1D2N 0x04
10137 #define _CLC4GLS0_D2N 0x04
10138 #define _CLC4GLS0_LC4G1D2T 0x08
10139 #define _CLC4GLS0_D2T 0x08
10140 #define _CLC4GLS0_LC4G1D3N 0x10
10141 #define _CLC4GLS0_D3N 0x10
10142 #define _CLC4GLS0_LC4G1D3T 0x20
10143 #define _CLC4GLS0_D3T 0x20
10144 #define _CLC4GLS0_LC4G1D4N 0x40
10145 #define _CLC4GLS0_D4N 0x40
10146 #define _CLC4GLS0_LC4G1D4T 0x80
10147 #define _CLC4GLS0_D4T 0x80
10149 //==============================================================================
10152 //==============================================================================
10155 extern __at(0x0F35) __sfr CLC4GLS1
;
10161 unsigned LC4G2D1N
: 1;
10162 unsigned LC4G2D1T
: 1;
10163 unsigned LC4G2D2N
: 1;
10164 unsigned LC4G2D2T
: 1;
10165 unsigned LC4G2D3N
: 1;
10166 unsigned LC4G2D3T
: 1;
10167 unsigned LC4G2D4N
: 1;
10168 unsigned LC4G2D4T
: 1;
10182 } __CLC4GLS1bits_t
;
10184 extern __at(0x0F35) volatile __CLC4GLS1bits_t CLC4GLS1bits
;
10186 #define _CLC4GLS1_LC4G2D1N 0x01
10187 #define _CLC4GLS1_D1N 0x01
10188 #define _CLC4GLS1_LC4G2D1T 0x02
10189 #define _CLC4GLS1_D1T 0x02
10190 #define _CLC4GLS1_LC4G2D2N 0x04
10191 #define _CLC4GLS1_D2N 0x04
10192 #define _CLC4GLS1_LC4G2D2T 0x08
10193 #define _CLC4GLS1_D2T 0x08
10194 #define _CLC4GLS1_LC4G2D3N 0x10
10195 #define _CLC4GLS1_D3N 0x10
10196 #define _CLC4GLS1_LC4G2D3T 0x20
10197 #define _CLC4GLS1_D3T 0x20
10198 #define _CLC4GLS1_LC4G2D4N 0x40
10199 #define _CLC4GLS1_D4N 0x40
10200 #define _CLC4GLS1_LC4G2D4T 0x80
10201 #define _CLC4GLS1_D4T 0x80
10203 //==============================================================================
10206 //==============================================================================
10209 extern __at(0x0F36) __sfr CLC4GLS2
;
10215 unsigned LC4G3D1N
: 1;
10216 unsigned LC4G3D1T
: 1;
10217 unsigned LC4G3D2N
: 1;
10218 unsigned LC4G3D2T
: 1;
10219 unsigned LC4G3D3N
: 1;
10220 unsigned LC4G3D3T
: 1;
10221 unsigned LC4G3D4N
: 1;
10222 unsigned LC4G3D4T
: 1;
10236 } __CLC4GLS2bits_t
;
10238 extern __at(0x0F36) volatile __CLC4GLS2bits_t CLC4GLS2bits
;
10240 #define _CLC4GLS2_LC4G3D1N 0x01
10241 #define _CLC4GLS2_D1N 0x01
10242 #define _CLC4GLS2_LC4G3D1T 0x02
10243 #define _CLC4GLS2_D1T 0x02
10244 #define _CLC4GLS2_LC4G3D2N 0x04
10245 #define _CLC4GLS2_D2N 0x04
10246 #define _CLC4GLS2_LC4G3D2T 0x08
10247 #define _CLC4GLS2_D2T 0x08
10248 #define _CLC4GLS2_LC4G3D3N 0x10
10249 #define _CLC4GLS2_D3N 0x10
10250 #define _CLC4GLS2_LC4G3D3T 0x20
10251 #define _CLC4GLS2_D3T 0x20
10252 #define _CLC4GLS2_LC4G3D4N 0x40
10253 #define _CLC4GLS2_D4N 0x40
10254 #define _CLC4GLS2_LC4G3D4T 0x80
10255 #define _CLC4GLS2_D4T 0x80
10257 //==============================================================================
10260 //==============================================================================
10263 extern __at(0x0F37) __sfr CLC4GLS3
;
10269 unsigned LC4G4D1N
: 1;
10270 unsigned LC4G4D1T
: 1;
10271 unsigned LC4G4D2N
: 1;
10272 unsigned LC4G4D2T
: 1;
10273 unsigned LC4G4D3N
: 1;
10274 unsigned LC4G4D3T
: 1;
10275 unsigned LC4G4D4N
: 1;
10276 unsigned LC4G4D4T
: 1;
10281 unsigned G4D1N
: 1;
10282 unsigned G4D1T
: 1;
10283 unsigned G4D2N
: 1;
10284 unsigned G4D2T
: 1;
10285 unsigned G4D3N
: 1;
10286 unsigned G4D3T
: 1;
10287 unsigned G4D4N
: 1;
10288 unsigned G4D4T
: 1;
10290 } __CLC4GLS3bits_t
;
10292 extern __at(0x0F37) volatile __CLC4GLS3bits_t CLC4GLS3bits
;
10294 #define _CLC4GLS3_LC4G4D1N 0x01
10295 #define _CLC4GLS3_G4D1N 0x01
10296 #define _CLC4GLS3_LC4G4D1T 0x02
10297 #define _CLC4GLS3_G4D1T 0x02
10298 #define _CLC4GLS3_LC4G4D2N 0x04
10299 #define _CLC4GLS3_G4D2N 0x04
10300 #define _CLC4GLS3_LC4G4D2T 0x08
10301 #define _CLC4GLS3_G4D2T 0x08
10302 #define _CLC4GLS3_LC4G4D3N 0x10
10303 #define _CLC4GLS3_G4D3N 0x10
10304 #define _CLC4GLS3_LC4G4D3T 0x20
10305 #define _CLC4GLS3_G4D3T 0x20
10306 #define _CLC4GLS3_LC4G4D4N 0x40
10307 #define _CLC4GLS3_G4D4N 0x40
10308 #define _CLC4GLS3_LC4G4D4T 0x80
10309 #define _CLC4GLS3_G4D4T 0x80
10311 //==============================================================================
10314 //==============================================================================
10315 // STATUS_SHAD Bits
10317 extern __at(0x0FE4) __sfr STATUS_SHAD
;
10321 unsigned C_SHAD
: 1;
10322 unsigned DC_SHAD
: 1;
10323 unsigned Z_SHAD
: 1;
10329 } __STATUS_SHADbits_t
;
10331 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
10333 #define _C_SHAD 0x01
10334 #define _DC_SHAD 0x02
10335 #define _Z_SHAD 0x04
10337 //==============================================================================
10339 extern __at(0x0FE5) __sfr WREG_SHAD
;
10340 extern __at(0x0FE6) __sfr BSR_SHAD
;
10341 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
10342 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
10343 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
10344 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
10345 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
10346 extern __at(0x0FED) __sfr STKPTR
;
10347 extern __at(0x0FEE) __sfr TOSL
;
10348 extern __at(0x0FEF) __sfr TOSH
;
10350 //==============================================================================
10352 // Configuration Bits
10354 //==============================================================================
10356 #define _CONFIG1 0x8007
10357 #define _CONFIG2 0x8008
10358 #define _CONFIG3 0x8009
10359 #define _CONFIG4 0x800A
10361 //----------------------------- CONFIG1 Options -------------------------------
10363 #define _FEXTOSC_LP 0x3FF8 // LP (crystal oscillator) optimized for 32.768 kHz.
10364 #define _FEXTOSC_XT 0x3FF9 // XT (crystal oscillator) from 100 kHz to 4 MHz.
10365 #define _FEXTOSC_HS 0x3FFA // HS (crystal oscillator) above 4 MHz.
10366 #define _FEXTOSC_OFF 0x3FFC // Oscillator not enabled.
10367 #define _FEXTOSC_ECL 0x3FFD // EC (external clock) below 100 kHz.
10368 #define _FEXTOSC_ECM 0x3FFE // EC (external clock) for 100 kHz to 8 MHz.
10369 #define _FEXTOSC_ECH 0x3FFF // EC (external clock) above 8 MHz.
10370 #define _RSTOSC_HFINT32 0x3F8F // HFINTOSC with 2x PLL (32MHz).
10371 #define _RSTOSC_EXT4X 0x3F9F // EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits.
10372 #define _RSTOSC_SOSC 0x3FBF // SOSC (31kHz).
10373 #define _RSTOSC_LFINT 0x3FCF // LFINTOSC (31kHz).
10374 #define _RSTOSC_HFINT1 0x3FEF // HFINTOSC (1MHz).
10375 #define _RSTOSC_EXT1X 0x3FFF // EXTOSC operating per FEXTOSC bits.
10376 #define _CLKOUTEN_ON 0x3EFF // CLKOUT function is enabled; FOSC/4 clock appears at OSC2.
10377 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled; I/O or oscillator function on OSC2.
10378 #define _CSWEN_OFF 0x37FF // The NOSC and NDIV bits cannot be changed by user software.
10379 #define _CSWEN_ON 0x3FFF // Writing to NOSC and NDIV is allowed.
10380 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
10381 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
10383 //----------------------------- CONFIG2 Options -------------------------------
10385 #define _MCLRE_OFF 0x3FFE // MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of port pin's WPU control bit.
10386 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR; Weak pull-up enabled.
10387 #define _PWRTE_ON 0x3FFD // PWRT enabled.
10388 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
10389 #define _WDTE_OFF 0x3FF3 // WDT disabled; SWDTEN is ignored.
10390 #define _WDTE_SWDTEN 0x3FF7 // WDT controlled by the SWDTEN bit in the WDTCON register.
10391 #define _WDTE_SLEEP 0x3FFB // WDT enabled while running and disabled in SLEEP/IDLE; SWDTEN is ignored.
10392 #define _WDTE_ON 0x3FFF // WDT enabled, SWDTEN is ignored.
10393 #define _LPBOREN_ON 0x3FDF // ULPBOR enabled.
10394 #define _LPBOREN_OFF 0x3FFF // ULPBOR disabled.
10395 #define _BOREN_OFF 0x3F3F // Brown-out Reset disabled.
10396 #define _BOREN_SBOREN 0x3F7F // Brown-out Reset enabled according to SBOREN.
10397 #define _BOREN_SLEEP 0x3FBF // Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored.
10398 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled, SBOREN bit ignored.
10399 #define _BORV_HIGH 0x3DFF // Brown-out voltage (Vbor) set to 2.7V.
10400 #define _BORV_LOW 0x3FFF // Brown-out voltage (Vbor) set to 2.45V.
10401 #define _PPS1WAY_OFF 0x37FF // The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence).
10402 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle.
10403 #define _STVREN_OFF 0x2FFF // Stack Overflow or Underflow will not cause a Reset.
10404 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
10405 #define _DEBUG_ON 0x1FFF // Background debugger enabled.
10406 #define _DEBUG_OFF 0x3FFF // Background debugger disabled.
10408 //----------------------------- CONFIG3 Options -------------------------------
10410 #define _WRT_ALL 0x3FFC // 0000h to 1FFFh write protected, no addresses may be modified.
10411 #define _WRT_HALF 0x3FFD // 0000h to 03FFh write-protected, 0400h to 1FFFh may be modified.
10412 #define _WRT_BOOT 0x3FFE // 0000h to 01FFh write-protected, 0200h to 1FFFh may be modified.
10413 #define _WRT_OFF 0x3FFF // Write protection off.
10414 #define _LVP_OFF 0x1FFF // High Voltage on MCLR/VPP must be used for programming.
10415 #define _LVP_ON 0x3FFF // Low Voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.
10417 //----------------------------- CONFIG4 Options -------------------------------
10419 #define _CP_ON 0x3FFE // User NVM code protection enabled.
10420 #define _CP_OFF 0x3FFF // User NVM code protection disabled.
10421 #define _CPD_ON 0x3FFD // Data NVM code protection enabled.
10422 #define _CPD_OFF 0x3FFF // Data NVM code protection disabled.
10424 //==============================================================================
10426 #define _DEVID1 0x8006
10428 #define _IDLOC0 0x8000
10429 #define _IDLOC1 0x8001
10430 #define _IDLOC2 0x8002
10431 #define _IDLOC3 0x8003
10433 //==============================================================================
10435 #ifndef NO_BIT_DEFINES
10437 #define ADACT0 ADACTbits.ADACT0 // bit 0
10438 #define ADACT1 ADACTbits.ADACT1 // bit 1
10439 #define ADACT2 ADACTbits.ADACT2 // bit 2
10440 #define ADACT3 ADACTbits.ADACT3 // bit 3
10441 #define ADACT4 ADACTbits.ADACT4 // bit 4
10443 #define ADON ADCON0bits.ADON // bit 0
10444 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
10445 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
10446 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
10447 #define CHS0 ADCON0bits.CHS0 // bit 2
10448 #define CHS1 ADCON0bits.CHS1 // bit 3
10449 #define CHS2 ADCON0bits.CHS2 // bit 4
10450 #define CHS3 ADCON0bits.CHS3 // bit 5
10451 #define CHS4 ADCON0bits.CHS4 // bit 6
10452 #define CHS5 ADCON0bits.CHS5 // bit 7
10454 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
10455 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
10456 #define ADNREF ADCON1bits.ADNREF // bit 2
10457 #define ADCS0 ADCON1bits.ADCS0 // bit 4
10458 #define ADCS1 ADCON1bits.ADCS1 // bit 5
10459 #define ADCS2 ADCON1bits.ADCS2 // bit 6
10460 #define ADFM ADCON1bits.ADFM // bit 7
10462 #define ANSA0 ANSELAbits.ANSA0 // bit 0
10463 #define ANSA1 ANSELAbits.ANSA1 // bit 1
10464 #define ANSA2 ANSELAbits.ANSA2 // bit 2
10465 #define ANSA4 ANSELAbits.ANSA4 // bit 4
10466 #define ANSA5 ANSELAbits.ANSA5 // bit 5
10468 #define ANSC0 ANSELCbits.ANSC0 // bit 0
10469 #define ANSC1 ANSELCbits.ANSC1 // bit 1
10470 #define ANSC2 ANSELCbits.ANSC2 // bit 2
10471 #define ANSC3 ANSELCbits.ANSC3 // bit 3
10472 #define ANSC4 ANSELCbits.ANSC4 // bit 4
10473 #define ANSC5 ANSELCbits.ANSC5 // bit 5
10475 #define ABDEN BAUD1CONbits.ABDEN // bit 0
10476 #define WUE BAUD1CONbits.WUE // bit 1
10477 #define BRG16 BAUD1CONbits.BRG16 // bit 3
10478 #define SCKP BAUD1CONbits.SCKP // bit 4
10479 #define RCIDL BAUD1CONbits.RCIDL // bit 6
10480 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
10482 #define BORRDY BORCONbits.BORRDY // bit 0
10483 #define SBOREN BORCONbits.SBOREN // bit 7
10485 #define BSR0 BSRbits.BSR0 // bit 0
10486 #define BSR1 BSRbits.BSR1 // bit 1
10487 #define BSR2 BSRbits.BSR2 // bit 2
10488 #define BSR3 BSRbits.BSR3 // bit 3
10489 #define BSR4 BSRbits.BSR4 // bit 4
10491 #define CCDS0 CCDCONbits.CCDS0 // bit 0
10492 #define CCDS1 CCDCONbits.CCDS1 // bit 1
10493 #define CCDEN CCDCONbits.CCDEN // bit 7
10495 #define CCDNA0 CCDNAbits.CCDNA0 // bit 0
10496 #define CCDNA1 CCDNAbits.CCDNA1 // bit 1
10497 #define CCDNA2 CCDNAbits.CCDNA2 // bit 2
10498 #define CCDNA4 CCDNAbits.CCDNA4 // bit 4
10499 #define CCDNA5 CCDNAbits.CCDNA5 // bit 5
10501 #define CCDNC0 CCDNCbits.CCDNC0 // bit 0
10502 #define CCDNC1 CCDNCbits.CCDNC1 // bit 1
10503 #define CCDNC2 CCDNCbits.CCDNC2 // bit 2
10504 #define CCDNC3 CCDNCbits.CCDNC3 // bit 3
10505 #define CCDNC4 CCDNCbits.CCDNC4 // bit 4
10506 #define CCDNC5 CCDNCbits.CCDNC5 // bit 5
10508 #define CCDPA0 CCDPAbits.CCDPA0 // bit 0
10509 #define CCDPA1 CCDPAbits.CCDPA1 // bit 1
10510 #define CCDPA2 CCDPAbits.CCDPA2 // bit 2
10511 #define CCDPA4 CCDPAbits.CCDPA4 // bit 4
10512 #define CCDPA5 CCDPAbits.CCDPA5 // bit 5
10514 #define CCDPC0 CCDPCbits.CCDPC0 // bit 0
10515 #define CCDPC1 CCDPCbits.CCDPC1 // bit 1
10516 #define CCDPC2 CCDPCbits.CCDPC2 // bit 2
10517 #define CCDPC3 CCDPCbits.CCDPC3 // bit 3
10518 #define CCDPC4 CCDPCbits.CCDPC4 // bit 4
10519 #define CCDPC5 CCDPCbits.CCDPC5 // bit 5
10521 #define CCP1CTS0 CCP1CAPbits.CCP1CTS0 // bit 0
10522 #define CCP1CTS1 CCP1CAPbits.CCP1CTS1 // bit 1
10523 #define CCP1CTS2 CCP1CAPbits.CCP1CTS2 // bit 2
10524 #define CCP1CTS3 CCP1CAPbits.CCP1CTS3 // bit 3
10526 #define CCP1MODE0 CCP1CONbits.CCP1MODE0 // bit 0
10527 #define CCP1MODE1 CCP1CONbits.CCP1MODE1 // bit 1
10528 #define CCP1MODE2 CCP1CONbits.CCP1MODE2 // bit 2
10529 #define CCP1MODE3 CCP1CONbits.CCP1MODE3 // bit 3
10530 #define CCP1FMT CCP1CONbits.CCP1FMT // bit 4
10531 #define CCP1OUT CCP1CONbits.CCP1OUT // bit 5
10532 #define CCP1EN CCP1CONbits.CCP1EN // bit 7
10534 #define CCP1PPS0 CCP1PPSbits.CCP1PPS0 // bit 0
10535 #define CCP1PPS1 CCP1PPSbits.CCP1PPS1 // bit 1
10536 #define CCP1PPS2 CCP1PPSbits.CCP1PPS2 // bit 2
10537 #define CCP1PPS3 CCP1PPSbits.CCP1PPS3 // bit 3
10538 #define CCP1PPS4 CCP1PPSbits.CCP1PPS4 // bit 4
10540 #define CCP2CTS0 CCP2CAPbits.CCP2CTS0 // bit 0
10541 #define CCP2CTS1 CCP2CAPbits.CCP2CTS1 // bit 1
10542 #define CCP2CTS2 CCP2CAPbits.CCP2CTS2 // bit 2
10543 #define CCP2CTS3 CCP2CAPbits.CCP2CTS3 // bit 3
10545 #define CCP2MODE0 CCP2CONbits.CCP2MODE0 // bit 0
10546 #define CCP2MODE1 CCP2CONbits.CCP2MODE1 // bit 1
10547 #define CCP2MODE2 CCP2CONbits.CCP2MODE2 // bit 2
10548 #define CCP2MODE3 CCP2CONbits.CCP2MODE3 // bit 3
10549 #define CCP2FMT CCP2CONbits.CCP2FMT // bit 4
10550 #define CCP2OUT CCP2CONbits.CCP2OUT // bit 5
10551 #define CCP2EN CCP2CONbits.CCP2EN // bit 7
10553 #define CCP2PPS0 CCP2PPSbits.CCP2PPS0 // bit 0
10554 #define CCP2PPS1 CCP2PPSbits.CCP2PPS1 // bit 1
10555 #define CCP2PPS2 CCP2PPSbits.CCP2PPS2 // bit 2
10556 #define CCP2PPS3 CCP2PPSbits.CCP2PPS3 // bit 3
10557 #define CCP2PPS4 CCP2PPSbits.CCP2PPS4 // bit 4
10559 #define CCAP0 CCP3CAPbits.CCAP0 // bit 0
10560 #define CCAP1 CCP3CAPbits.CCAP1 // bit 1
10561 #define CCAP2 CCP3CAPbits.CCAP2 // bit 2
10562 #define CCAP3 CCP3CAPbits.CCAP3 // bit 3
10564 #define CCP3MODE0 CCP3CONbits.CCP3MODE0 // bit 0
10565 #define CCP3MODE1 CCP3CONbits.CCP3MODE1 // bit 1
10566 #define CCP3MODE2 CCP3CONbits.CCP3MODE2 // bit 2
10567 #define CCP3MODE3 CCP3CONbits.CCP3MODE3 // bit 3
10568 #define CCP3FMT CCP3CONbits.CCP3FMT // bit 4
10569 #define CCP3OUT CCP3CONbits.CCP3OUT // bit 5
10570 #define CCP3EN CCP3CONbits.CCP3EN // bit 7
10572 #define CCP3PPS0 CCP3PPSbits.CCP3PPS0 // bit 0
10573 #define CCP3PPS1 CCP3PPSbits.CCP3PPS1 // bit 1
10574 #define CCP3PPS2 CCP3PPSbits.CCP3PPS2 // bit 2
10575 #define CCP3PPS3 CCP3PPSbits.CCP3PPS3 // bit 3
10576 #define CCP3PPS4 CCP3PPSbits.CCP3PPS4 // bit 4
10578 #define CCP4CTS0 CCP4CAPbits.CCP4CTS0 // bit 0
10579 #define CCP4CTS1 CCP4CAPbits.CCP4CTS1 // bit 1
10580 #define CCP4CTS2 CCP4CAPbits.CCP4CTS2 // bit 2
10581 #define CCP4CTS3 CCP4CAPbits.CCP4CTS3 // bit 3
10583 #define CCP4MODE0 CCP4CONbits.CCP4MODE0 // bit 0
10584 #define CCP4MODE1 CCP4CONbits.CCP4MODE1 // bit 1
10585 #define CCP4MODE2 CCP4CONbits.CCP4MODE2 // bit 2
10586 #define CCP4MODE3 CCP4CONbits.CCP4MODE3 // bit 3
10587 #define CCP4FMT CCP4CONbits.CCP4FMT // bit 4
10588 #define CCP4OUT CCP4CONbits.CCP4OUT // bit 5
10589 #define CCP4EN CCP4CONbits.CCP4EN // bit 7
10591 #define CCP4PPS0 CCP4PPSbits.CCP4PPS0 // bit 0
10592 #define CCP4PPS1 CCP4PPSbits.CCP4PPS1 // bit 1
10593 #define CCP4PPS2 CCP4PPSbits.CCP4PPS2 // bit 2
10594 #define CCP4PPS3 CCP4PPSbits.CCP4PPS3 // bit 3
10595 #define CCP4PPS4 CCP4PPSbits.CCP4PPS4 // bit 4
10597 #define C1TSEL0 CCPTMRSbits.C1TSEL0 // bit 0
10598 #define C1TSEL1 CCPTMRSbits.C1TSEL1 // bit 1
10599 #define C2TSEL0 CCPTMRSbits.C2TSEL0 // bit 2
10600 #define C2TSEL1 CCPTMRSbits.C2TSEL1 // bit 3
10601 #define C3TSEL0 CCPTMRSbits.C3TSEL0 // bit 4
10602 #define C3TSEL1 CCPTMRSbits.C3TSEL1 // bit 5
10603 #define C4TSEL0 CCPTMRSbits.C4TSEL0 // bit 6
10604 #define C4TSEL1 CCPTMRSbits.C4TSEL1 // bit 7
10606 #define LC1MODE0 CLC1CONbits.LC1MODE0 // bit 0, shadows bit in CLC1CONbits
10607 #define MODE0 CLC1CONbits.MODE0 // bit 0, shadows bit in CLC1CONbits
10608 #define LC1MODE1 CLC1CONbits.LC1MODE1 // bit 1, shadows bit in CLC1CONbits
10609 #define MODE1 CLC1CONbits.MODE1 // bit 1, shadows bit in CLC1CONbits
10610 #define LC1MODE2 CLC1CONbits.LC1MODE2 // bit 2, shadows bit in CLC1CONbits
10611 #define MODE2 CLC1CONbits.MODE2 // bit 2, shadows bit in CLC1CONbits
10612 #define LC1INTN CLC1CONbits.LC1INTN // bit 3, shadows bit in CLC1CONbits
10613 #define INTN CLC1CONbits.INTN // bit 3, shadows bit in CLC1CONbits
10614 #define LC1INTP CLC1CONbits.LC1INTP // bit 4, shadows bit in CLC1CONbits
10615 #define INTP CLC1CONbits.INTP // bit 4, shadows bit in CLC1CONbits
10616 #define LC1OUT CLC1CONbits.LC1OUT // bit 5, shadows bit in CLC1CONbits
10617 #define OUT CLC1CONbits.OUT // bit 5, shadows bit in CLC1CONbits
10618 #define LC1EN CLC1CONbits.LC1EN // bit 7, shadows bit in CLC1CONbits
10619 #define EN CLC1CONbits.EN // bit 7, shadows bit in CLC1CONbits
10621 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
10622 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
10623 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
10624 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
10625 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
10626 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
10627 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
10628 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
10629 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
10630 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
10631 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
10632 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
10633 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
10634 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
10635 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
10636 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
10638 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
10639 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
10640 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
10641 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
10642 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
10643 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
10644 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
10645 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
10646 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
10647 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
10648 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
10649 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
10650 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
10651 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
10652 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
10653 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
10655 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
10656 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
10657 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
10658 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
10659 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
10660 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
10661 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
10662 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
10663 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
10664 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
10666 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
10667 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
10668 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
10669 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
10670 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
10671 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
10672 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
10673 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
10674 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
10675 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
10676 #define LC1D1S5 CLC1SEL0bits.LC1D1S5 // bit 5, shadows bit in CLC1SEL0bits
10677 #define D1S5 CLC1SEL0bits.D1S5 // bit 5, shadows bit in CLC1SEL0bits
10679 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
10680 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
10681 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
10682 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
10683 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
10684 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
10685 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
10686 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
10687 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
10688 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
10689 #define LC1D2S5 CLC1SEL1bits.LC1D2S5 // bit 5, shadows bit in CLC1SEL1bits
10690 #define D2S5 CLC1SEL1bits.D2S5 // bit 5, shadows bit in CLC1SEL1bits
10692 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
10693 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
10694 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
10695 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
10696 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
10697 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
10698 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
10699 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
10700 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
10701 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
10702 #define LC1D3S5 CLC1SEL2bits.LC1D3S5 // bit 5, shadows bit in CLC1SEL2bits
10703 #define D3S5 CLC1SEL2bits.D3S5 // bit 5, shadows bit in CLC1SEL2bits
10705 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
10706 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
10707 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
10708 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
10709 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
10710 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
10711 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
10712 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
10713 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
10714 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
10715 #define LC1D4S5 CLC1SEL3bits.LC1D4S5 // bit 5, shadows bit in CLC1SEL3bits
10716 #define D4S5 CLC1SEL3bits.D4S5 // bit 5, shadows bit in CLC1SEL3bits
10718 #define MLC1OUT CLCDATAbits.MLC1OUT // bit 0
10719 #define MLC2OUT CLCDATAbits.MLC2OUT // bit 1
10720 #define MLC3OUT CLCDATAbits.MLC3OUT // bit 2
10721 #define MLC4OUT CLCDATAbits.MLC4OUT // bit 3
10723 #define CLCIN0PPS0 CLCIN0PPSbits.CLCIN0PPS0 // bit 0
10724 #define CLCIN0PPS1 CLCIN0PPSbits.CLCIN0PPS1 // bit 1
10725 #define CLCIN0PPS2 CLCIN0PPSbits.CLCIN0PPS2 // bit 2
10726 #define CLCIN0PPS3 CLCIN0PPSbits.CLCIN0PPS3 // bit 3
10727 #define CLCIN0PPS4 CLCIN0PPSbits.CLCIN0PPS4 // bit 4
10729 #define CLCIN1PPS0 CLCIN1PPSbits.CLCIN1PPS0 // bit 0
10730 #define CLCIN1PPS1 CLCIN1PPSbits.CLCIN1PPS1 // bit 1
10731 #define CLCIN1PPS2 CLCIN1PPSbits.CLCIN1PPS2 // bit 2
10732 #define CLCIN1PPS3 CLCIN1PPSbits.CLCIN1PPS3 // bit 3
10733 #define CLCIN1PPS4 CLCIN1PPSbits.CLCIN1PPS4 // bit 4
10735 #define CLCIN2PPS0 CLCIN2PPSbits.CLCIN2PPS0 // bit 0
10736 #define CLCIN2PPS1 CLCIN2PPSbits.CLCIN2PPS1 // bit 1
10737 #define CLCIN2PPS2 CLCIN2PPSbits.CLCIN2PPS2 // bit 2
10738 #define CLCIN2PPS3 CLCIN2PPSbits.CLCIN2PPS3 // bit 3
10739 #define CLCIN2PPS4 CLCIN2PPSbits.CLCIN2PPS4 // bit 4
10741 #define CLCIN3PPS0 CLCIN3PPSbits.CLCIN3PPS0 // bit 0
10742 #define CLCIN3PPS1 CLCIN3PPSbits.CLCIN3PPS1 // bit 1
10743 #define CLCIN3PPS2 CLCIN3PPSbits.CLCIN3PPS2 // bit 2
10744 #define CLCIN3PPS3 CLCIN3PPSbits.CLCIN3PPS3 // bit 3
10745 #define CLCIN3PPS4 CLCIN3PPSbits.CLCIN3PPS4 // bit 4
10747 #define CLKRDIV0 CLKRCONbits.CLKRDIV0 // bit 0
10748 #define CLKRDIV1 CLKRCONbits.CLKRDIV1 // bit 1
10749 #define CLKRDIV2 CLKRCONbits.CLKRDIV2 // bit 2
10750 #define CLKRDC0 CLKRCONbits.CLKRDC0 // bit 3
10751 #define CLKRDC1 CLKRCONbits.CLKRDC1 // bit 4
10752 #define CLKREN CLKRCONbits.CLKREN // bit 7
10754 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
10755 #define C1HYS CM1CON0bits.C1HYS // bit 1
10756 #define C1SP CM1CON0bits.C1SP // bit 2
10757 #define C1POL CM1CON0bits.C1POL // bit 4
10758 #define C1OUT CM1CON0bits.C1OUT // bit 6
10759 #define C1ON CM1CON0bits.C1ON // bit 7
10761 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
10762 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
10763 #define C1NCH2 CM1CON1bits.C1NCH2 // bit 2
10764 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 3
10765 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 4
10766 #define C1PCH2 CM1CON1bits.C1PCH2 // bit 5
10767 #define C1INTN CM1CON1bits.C1INTN // bit 6
10768 #define C1INTP CM1CON1bits.C1INTP // bit 7
10770 #define C2SYNC CM2CON0bits.C2SYNC // bit 0
10771 #define C2HYS CM2CON0bits.C2HYS // bit 1
10772 #define C2SP CM2CON0bits.C2SP // bit 2
10773 #define C2POL CM2CON0bits.C2POL // bit 4
10774 #define C2OUT CM2CON0bits.C2OUT // bit 6
10775 #define C2ON CM2CON0bits.C2ON // bit 7
10777 #define C2NCH0 CM2CON1bits.C2NCH0 // bit 0
10778 #define C2NCH1 CM2CON1bits.C2NCH1 // bit 1
10779 #define C2NCH2 CM2CON1bits.C2NCH2 // bit 2
10780 #define C2PCH0 CM2CON1bits.C2PCH0 // bit 3
10781 #define C2PCH1 CM2CON1bits.C2PCH1 // bit 4
10782 #define C2PCH2 CM2CON1bits.C2PCH2 // bit 5
10783 #define C2INTN CM2CON1bits.C2INTN // bit 6
10784 #define C2INTP CM2CON1bits.C2INTP // bit 7
10786 #define MC1OUT CMOUTbits.MC1OUT // bit 0
10787 #define MC2OUT CMOUTbits.MC2OUT // bit 1
10789 #define DOZE0 CPUDOZEbits.DOZE0 // bit 0
10790 #define DOZE1 CPUDOZEbits.DOZE1 // bit 1
10791 #define DOZE2 CPUDOZEbits.DOZE2 // bit 2
10792 #define DOE CPUDOZEbits.DOE // bit 4
10793 #define ROI CPUDOZEbits.ROI // bit 5
10794 #define DOZEN CPUDOZEbits.DOZEN // bit 6
10795 #define IDLEN CPUDOZEbits.IDLEN // bit 7
10797 #define LSAC0 CWG1AS0bits.LSAC0 // bit 2, shadows bit in CWG1AS0bits
10798 #define CWG1LSAC0 CWG1AS0bits.CWG1LSAC0 // bit 2, shadows bit in CWG1AS0bits
10799 #define LSAC1 CWG1AS0bits.LSAC1 // bit 3, shadows bit in CWG1AS0bits
10800 #define CWG1LSAC1 CWG1AS0bits.CWG1LSAC1 // bit 3, shadows bit in CWG1AS0bits
10801 #define LSBD0 CWG1AS0bits.LSBD0 // bit 4, shadows bit in CWG1AS0bits
10802 #define CWG1LSBD0 CWG1AS0bits.CWG1LSBD0 // bit 4, shadows bit in CWG1AS0bits
10803 #define LSBD1 CWG1AS0bits.LSBD1 // bit 5, shadows bit in CWG1AS0bits
10804 #define CWG1LSBD1 CWG1AS0bits.CWG1LSBD1 // bit 5, shadows bit in CWG1AS0bits
10805 #define REN CWG1AS0bits.REN // bit 6, shadows bit in CWG1AS0bits
10806 #define CWG1REN CWG1AS0bits.CWG1REN // bit 6, shadows bit in CWG1AS0bits
10807 #define SHUTDOWN CWG1AS0bits.SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
10808 #define CWG1SHUTDOWN CWG1AS0bits.CWG1SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
10810 #define AS0E CWG1AS1bits.AS0E // bit 0
10811 #define AS1E CWG1AS1bits.AS1E // bit 1
10812 #define AS2E CWG1AS1bits.AS2E // bit 2
10813 #define AS3E CWG1AS1bits.AS3E // bit 3
10814 #define AS4E CWG1AS1bits.AS4E // bit 4
10816 #define CS CWG1CLKCONbits.CS // bit 0, shadows bit in CWG1CLKCONbits
10817 #define CWG1CS CWG1CLKCONbits.CWG1CS // bit 0, shadows bit in CWG1CLKCONbits
10819 #define POLA CWG1CON1bits.POLA // bit 0, shadows bit in CWG1CON1bits
10820 #define CWG1POLA CWG1CON1bits.CWG1POLA // bit 0, shadows bit in CWG1CON1bits
10821 #define POLB CWG1CON1bits.POLB // bit 1, shadows bit in CWG1CON1bits
10822 #define CWG1POLB CWG1CON1bits.CWG1POLB // bit 1, shadows bit in CWG1CON1bits
10823 #define POLC CWG1CON1bits.POLC // bit 2, shadows bit in CWG1CON1bits
10824 #define CWG1POLC CWG1CON1bits.CWG1POLC // bit 2, shadows bit in CWG1CON1bits
10825 #define POLD CWG1CON1bits.POLD // bit 3, shadows bit in CWG1CON1bits
10826 #define CWG1POLD CWG1CON1bits.CWG1POLD // bit 3, shadows bit in CWG1CON1bits
10827 #define IN CWG1CON1bits.IN // bit 5, shadows bit in CWG1CON1bits
10828 #define CWG1IN CWG1CON1bits.CWG1IN // bit 5, shadows bit in CWG1CON1bits
10830 #define CWG1DAT0 CWG1DATbits.CWG1DAT0 // bit 0
10831 #define CWG1DAT1 CWG1DATbits.CWG1DAT1 // bit 1
10832 #define CWG1DAT2 CWG1DATbits.CWG1DAT2 // bit 2
10833 #define CWG1DAT3 CWG1DATbits.CWG1DAT3 // bit 3
10835 #define DBF0 CWG1DBFbits.DBF0 // bit 0, shadows bit in CWG1DBFbits
10836 #define CWG1DBF0 CWG1DBFbits.CWG1DBF0 // bit 0, shadows bit in CWG1DBFbits
10837 #define DBF1 CWG1DBFbits.DBF1 // bit 1, shadows bit in CWG1DBFbits
10838 #define CWG1DBF1 CWG1DBFbits.CWG1DBF1 // bit 1, shadows bit in CWG1DBFbits
10839 #define DBF2 CWG1DBFbits.DBF2 // bit 2, shadows bit in CWG1DBFbits
10840 #define CWG1DBF2 CWG1DBFbits.CWG1DBF2 // bit 2, shadows bit in CWG1DBFbits
10841 #define DBF3 CWG1DBFbits.DBF3 // bit 3, shadows bit in CWG1DBFbits
10842 #define CWG1DBF3 CWG1DBFbits.CWG1DBF3 // bit 3, shadows bit in CWG1DBFbits
10843 #define DBF4 CWG1DBFbits.DBF4 // bit 4, shadows bit in CWG1DBFbits
10844 #define CWG1DBF4 CWG1DBFbits.CWG1DBF4 // bit 4, shadows bit in CWG1DBFbits
10845 #define DBF5 CWG1DBFbits.DBF5 // bit 5, shadows bit in CWG1DBFbits
10846 #define CWG1DBF5 CWG1DBFbits.CWG1DBF5 // bit 5, shadows bit in CWG1DBFbits
10848 #define DBR0 CWG1DBRbits.DBR0 // bit 0, shadows bit in CWG1DBRbits
10849 #define CWG1DBR0 CWG1DBRbits.CWG1DBR0 // bit 0, shadows bit in CWG1DBRbits
10850 #define DBR1 CWG1DBRbits.DBR1 // bit 1, shadows bit in CWG1DBRbits
10851 #define CWG1DBR1 CWG1DBRbits.CWG1DBR1 // bit 1, shadows bit in CWG1DBRbits
10852 #define DBR2 CWG1DBRbits.DBR2 // bit 2, shadows bit in CWG1DBRbits
10853 #define CWG1DBR2 CWG1DBRbits.CWG1DBR2 // bit 2, shadows bit in CWG1DBRbits
10854 #define DBR3 CWG1DBRbits.DBR3 // bit 3, shadows bit in CWG1DBRbits
10855 #define CWG1DBR3 CWG1DBRbits.CWG1DBR3 // bit 3, shadows bit in CWG1DBRbits
10856 #define DBR4 CWG1DBRbits.DBR4 // bit 4, shadows bit in CWG1DBRbits
10857 #define CWG1DBR4 CWG1DBRbits.CWG1DBR4 // bit 4, shadows bit in CWG1DBRbits
10858 #define DBR5 CWG1DBRbits.DBR5 // bit 5, shadows bit in CWG1DBRbits
10859 #define CWG1DBR5 CWG1DBRbits.CWG1DBR5 // bit 5, shadows bit in CWG1DBRbits
10861 #define CWG1PPS0 CWG1PPSbits.CWG1PPS0 // bit 0
10862 #define CWG1PPS1 CWG1PPSbits.CWG1PPS1 // bit 1
10863 #define CWG1PPS2 CWG1PPSbits.CWG1PPS2 // bit 2
10864 #define CWG1PPS3 CWG1PPSbits.CWG1PPS3 // bit 3
10865 #define CWG1PPS4 CWG1PPSbits.CWG1PPS4 // bit 4
10867 #define STRA CWG1STRbits.STRA // bit 0, shadows bit in CWG1STRbits
10868 #define CWG1STRA CWG1STRbits.CWG1STRA // bit 0, shadows bit in CWG1STRbits
10869 #define STRB CWG1STRbits.STRB // bit 1, shadows bit in CWG1STRbits
10870 #define CWG1STRB CWG1STRbits.CWG1STRB // bit 1, shadows bit in CWG1STRbits
10871 #define STRC CWG1STRbits.STRC // bit 2, shadows bit in CWG1STRbits
10872 #define CWG1STRC CWG1STRbits.CWG1STRC // bit 2, shadows bit in CWG1STRbits
10873 #define STRD CWG1STRbits.STRD // bit 3, shadows bit in CWG1STRbits
10874 #define CWG1STRD CWG1STRbits.CWG1STRD // bit 3, shadows bit in CWG1STRbits
10875 #define OVRA CWG1STRbits.OVRA // bit 4, shadows bit in CWG1STRbits
10876 #define CWG1OVRA CWG1STRbits.CWG1OVRA // bit 4, shadows bit in CWG1STRbits
10877 #define OVRB CWG1STRbits.OVRB // bit 5, shadows bit in CWG1STRbits
10878 #define CWG1OVRB CWG1STRbits.CWG1OVRB // bit 5, shadows bit in CWG1STRbits
10879 #define OVRC CWG1STRbits.OVRC // bit 6, shadows bit in CWG1STRbits
10880 #define CWG1OVRC CWG1STRbits.CWG1OVRC // bit 6, shadows bit in CWG1STRbits
10881 #define OVRD CWG1STRbits.OVRD // bit 7, shadows bit in CWG1STRbits
10882 #define CWG1OVRD CWG1STRbits.CWG1OVRD // bit 7, shadows bit in CWG1STRbits
10884 #define CWG2DAT0 CWG2DATbits.CWG2DAT0 // bit 0
10885 #define CWG2DAT1 CWG2DATbits.CWG2DAT1 // bit 1
10886 #define CWG2DAT2 CWG2DATbits.CWG2DAT2 // bit 2
10887 #define CWG2DAT3 CWG2DATbits.CWG2DAT3 // bit 3
10889 #define CWG2PPS0 CWG2PPSbits.CWG2PPS0 // bit 0
10890 #define CWG2PPS1 CWG2PPSbits.CWG2PPS1 // bit 1
10891 #define CWG2PPS2 CWG2PPSbits.CWG2PPS2 // bit 2
10892 #define CWG2PPS3 CWG2PPSbits.CWG2PPS3 // bit 3
10893 #define CWG2PPS4 CWG2PPSbits.CWG2PPS4 // bit 4
10895 #define DAC1NSS DACCON0bits.DAC1NSS // bit 0
10896 #define DAC1PSS0 DACCON0bits.DAC1PSS0 // bit 2
10897 #define DAC1PSS1 DACCON0bits.DAC1PSS1 // bit 3
10898 #define DAC1OE DACCON0bits.DAC1OE // bit 5
10899 #define DAC1EN DACCON0bits.DAC1EN // bit 7
10901 #define DAC1R0 DACCON1bits.DAC1R0 // bit 0
10902 #define DAC1R1 DACCON1bits.DAC1R1 // bit 1
10903 #define DAC1R2 DACCON1bits.DAC1R2 // bit 2
10904 #define DAC1R3 DACCON1bits.DAC1R3 // bit 3
10905 #define DAC1R4 DACCON1bits.DAC1R4 // bit 4
10907 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
10908 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
10909 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
10910 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
10911 #define TSRNG FVRCONbits.TSRNG // bit 4
10912 #define TSEN FVRCONbits.TSEN // bit 5
10913 #define FVRRDY FVRCONbits.FVRRDY // bit 6
10914 #define FVREN FVRCONbits.FVREN // bit 7
10916 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
10917 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
10918 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
10919 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
10920 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
10921 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
10923 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
10924 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
10925 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
10926 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
10927 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
10928 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
10930 #define INTEDG INTCONbits.INTEDG // bit 0
10931 #define PEIE INTCONbits.PEIE // bit 6
10932 #define GIE INTCONbits.GIE // bit 7
10934 #define INTPPS0 INTPPSbits.INTPPS0 // bit 0
10935 #define INTPPS1 INTPPSbits.INTPPS1 // bit 1
10936 #define INTPPS2 INTPPSbits.INTPPS2 // bit 2
10937 #define INTPPS3 INTPPSbits.INTPPS3 // bit 3
10938 #define INTPPS4 INTPPSbits.INTPPS4 // bit 4
10940 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
10941 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
10942 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
10943 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
10944 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
10945 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
10947 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
10948 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
10949 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
10950 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
10951 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
10952 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
10954 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
10955 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
10956 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
10957 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
10958 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
10959 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
10961 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
10962 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
10963 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
10964 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
10965 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
10966 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
10968 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
10969 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
10970 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
10971 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
10972 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
10973 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
10975 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
10976 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
10977 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
10978 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
10979 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
10980 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
10982 #define LATA0 LATAbits.LATA0 // bit 0
10983 #define LATA1 LATAbits.LATA1 // bit 1
10984 #define LATA2 LATAbits.LATA2 // bit 2
10985 #define LATA4 LATAbits.LATA4 // bit 4
10986 #define LATA5 LATAbits.LATA5 // bit 5
10988 #define LATC0 LATCbits.LATC0 // bit 0
10989 #define LATC1 LATCbits.LATC1 // bit 1
10990 #define LATC2 LATCbits.LATC2 // bit 2
10991 #define LATC3 LATCbits.LATC3 // bit 3
10992 #define LATC4 LATCbits.LATC4 // bit 4
10993 #define LATC5 LATCbits.LATC5 // bit 5
10995 #define MDCH0 MDCARHbits.MDCH0 // bit 0
10996 #define MDCH1 MDCARHbits.MDCH1 // bit 1
10997 #define MDCH2 MDCARHbits.MDCH2 // bit 2
10998 #define MDCH3 MDCARHbits.MDCH3 // bit 3
10999 #define MDCHSYNC MDCARHbits.MDCHSYNC // bit 5
11000 #define MDCHPOL MDCARHbits.MDCHPOL // bit 6
11002 #define MDCL0 MDCARLbits.MDCL0 // bit 0
11003 #define MDCL1 MDCARLbits.MDCL1 // bit 1
11004 #define MDCL2 MDCARLbits.MDCL2 // bit 2
11005 #define MDCL3 MDCARLbits.MDCL3 // bit 3
11006 #define MDCLSYNC MDCARLbits.MDCLSYNC // bit 5
11007 #define MDCLPOL MDCARLbits.MDCLPOL // bit 6
11009 #define MDCIN1PPS0 MDCIN1PPSbits.MDCIN1PPS0 // bit 0
11010 #define MDCIN1PPS1 MDCIN1PPSbits.MDCIN1PPS1 // bit 1
11011 #define MDCIN1PPS2 MDCIN1PPSbits.MDCIN1PPS2 // bit 2
11012 #define MDCIN1PPS3 MDCIN1PPSbits.MDCIN1PPS3 // bit 3
11013 #define MDCIN1PPS4 MDCIN1PPSbits.MDCIN1PPS4 // bit 4
11015 #define MDCIN2PPS0 MDCIN2PPSbits.MDCIN2PPS0 // bit 0
11016 #define MDCIN2PPS1 MDCIN2PPSbits.MDCIN2PPS1 // bit 1
11017 #define MDCIN2PPS2 MDCIN2PPSbits.MDCIN2PPS2 // bit 2
11018 #define MDCIN2PPS3 MDCIN2PPSbits.MDCIN2PPS3 // bit 3
11019 #define MDCIN2PPS4 MDCIN2PPSbits.MDCIN2PPS4 // bit 4
11021 #define MDBIT MDCONbits.MDBIT // bit 0
11022 #define MDOUT MDCONbits.MDOUT // bit 3
11023 #define MDOPOL MDCONbits.MDOPOL // bit 4
11024 #define MDEN MDCONbits.MDEN // bit 7
11026 #define MDMINPPS0 MDMINPPSbits.MDMINPPS0 // bit 0
11027 #define MDMINPPS1 MDMINPPSbits.MDMINPPS1 // bit 1
11028 #define MDMINPPS2 MDMINPPSbits.MDMINPPS2 // bit 2
11029 #define MDMINPPS3 MDMINPPSbits.MDMINPPS3 // bit 3
11030 #define MDMINPPS4 MDMINPPSbits.MDMINPPS4 // bit 4
11032 #define MDMS0 MDSRCbits.MDMS0 // bit 0
11033 #define MDMS1 MDSRCbits.MDMS1 // bit 1
11034 #define MDMS2 MDSRCbits.MDMS2 // bit 2
11035 #define MDMS3 MDSRCbits.MDMS3 // bit 3
11037 #define N1PFM NCO1CONbits.N1PFM // bit 0
11038 #define N1POL NCO1CONbits.N1POL // bit 4
11039 #define N1OUT NCO1CONbits.N1OUT // bit 5
11040 #define N1EN NCO1CONbits.N1EN // bit 7
11042 #define NVMADR8 NVMADRHbits.NVMADR8 // bit 0
11043 #define NVMADR9 NVMADRHbits.NVMADR9 // bit 1
11044 #define NVMADR10 NVMADRHbits.NVMADR10 // bit 2
11045 #define NVMADR11 NVMADRHbits.NVMADR11 // bit 3
11046 #define NVMADR12 NVMADRHbits.NVMADR12 // bit 4
11047 #define NVMADR13 NVMADRHbits.NVMADR13 // bit 5
11048 #define NVMADR14 NVMADRHbits.NVMADR14 // bit 6
11050 #define NVMADR0 NVMADRLbits.NVMADR0 // bit 0
11051 #define NVMADR1 NVMADRLbits.NVMADR1 // bit 1
11052 #define NVMADR2 NVMADRLbits.NVMADR2 // bit 2
11053 #define NVMADR3 NVMADRLbits.NVMADR3 // bit 3
11054 #define NVMADR4 NVMADRLbits.NVMADR4 // bit 4
11055 #define NVMADR5 NVMADRLbits.NVMADR5 // bit 5
11056 #define NVMADR6 NVMADRLbits.NVMADR6 // bit 6
11057 #define NVMADR7 NVMADRLbits.NVMADR7 // bit 7
11059 #define RD NVMCON1bits.RD // bit 0
11060 #define WR NVMCON1bits.WR // bit 1
11061 #define WREN NVMCON1bits.WREN // bit 2
11062 #define WRERR NVMCON1bits.WRERR // bit 3
11063 #define FREE NVMCON1bits.FREE // bit 4
11064 #define LWLO NVMCON1bits.LWLO // bit 5
11065 #define NVMREGS NVMCON1bits.NVMREGS // bit 6
11067 #define NVMDAT8 NVMDATHbits.NVMDAT8 // bit 0
11068 #define NVMDAT9 NVMDATHbits.NVMDAT9 // bit 1
11069 #define NVMDAT10 NVMDATHbits.NVMDAT10 // bit 2
11070 #define NVMDAT11 NVMDATHbits.NVMDAT11 // bit 3
11071 #define NVMDAT12 NVMDATHbits.NVMDAT12 // bit 4
11072 #define NVMDAT13 NVMDATHbits.NVMDAT13 // bit 5
11074 #define NVMDAT0 NVMDATLbits.NVMDAT0 // bit 0
11075 #define NVMDAT1 NVMDATLbits.NVMDAT1 // bit 1
11076 #define NVMDAT2 NVMDATLbits.NVMDAT2 // bit 2
11077 #define NVMDAT3 NVMDATLbits.NVMDAT3 // bit 3
11078 #define NVMDAT4 NVMDATLbits.NVMDAT4 // bit 4
11079 #define NVMDAT5 NVMDATLbits.NVMDAT5 // bit 5
11080 #define NVMDAT6 NVMDATLbits.NVMDAT6 // bit 6
11081 #define NVMDAT7 NVMDATLbits.NVMDAT7 // bit 7
11083 #define ODCA0 ODCONAbits.ODCA0 // bit 0
11084 #define ODCA1 ODCONAbits.ODCA1 // bit 1
11085 #define ODCA2 ODCONAbits.ODCA2 // bit 2
11086 #define ODCA4 ODCONAbits.ODCA4 // bit 4
11087 #define ODCA5 ODCONAbits.ODCA5 // bit 5
11089 #define ODCC0 ODCONCbits.ODCC0 // bit 0
11090 #define ODCC1 ODCONCbits.ODCC1 // bit 1
11091 #define ODCC2 ODCONCbits.ODCC2 // bit 2
11092 #define ODCC3 ODCONCbits.ODCC3 // bit 3
11093 #define ODCC4 ODCONCbits.ODCC4 // bit 4
11094 #define ODCC5 ODCONCbits.ODCC5 // bit 5
11096 #define NDIV0 OSCCON1bits.NDIV0 // bit 0
11097 #define NDIV1 OSCCON1bits.NDIV1 // bit 1
11098 #define NDIV2 OSCCON1bits.NDIV2 // bit 2
11099 #define NDIV3 OSCCON1bits.NDIV3 // bit 3
11100 #define NOSC0 OSCCON1bits.NOSC0 // bit 4
11101 #define NOSC1 OSCCON1bits.NOSC1 // bit 5
11102 #define NOSC2 OSCCON1bits.NOSC2 // bit 6
11104 #define CDIV0 OSCCON2bits.CDIV0 // bit 0
11105 #define CDIV1 OSCCON2bits.CDIV1 // bit 1
11106 #define CDIV2 OSCCON2bits.CDIV2 // bit 2
11107 #define CDIV3 OSCCON2bits.CDIV3 // bit 3
11108 #define COSC0 OSCCON2bits.COSC0 // bit 4
11109 #define COSC1 OSCCON2bits.COSC1 // bit 5
11110 #define COSC2 OSCCON2bits.COSC2 // bit 6
11112 #define NOSCR OSCCON3bits.NOSCR // bit 3
11113 #define ORDY OSCCON3bits.ORDY // bit 4
11114 #define SOSCBE OSCCON3bits.SOSCBE // bit 5
11115 #define SOSCPWR OSCCON3bits.SOSCPWR // bit 6
11116 #define CSWHOLD OSCCON3bits.CSWHOLD // bit 7
11118 #define ADOEN OSCENbits.ADOEN // bit 2
11119 #define SOSCEN OSCENbits.SOSCEN // bit 3
11120 #define LFOEN OSCENbits.LFOEN // bit 4
11121 #define HFOEN OSCENbits.HFOEN // bit 6
11122 #define EXTOEN OSCENbits.EXTOEN // bit 7
11124 #define HFFRQ0 OSCFRQbits.HFFRQ0 // bit 0
11125 #define HFFRQ1 OSCFRQbits.HFFRQ1 // bit 1
11126 #define HFFRQ2 OSCFRQbits.HFFRQ2 // bit 2
11127 #define HFFRQ3 OSCFRQbits.HFFRQ3 // bit 3
11129 #define PLLR OSCSTAT1bits.PLLR // bit 0
11130 #define ADOR OSCSTAT1bits.ADOR // bit 2
11131 #define SOR OSCSTAT1bits.SOR // bit 3
11132 #define LFOR OSCSTAT1bits.LFOR // bit 4
11133 #define HFOR OSCSTAT1bits.HFOR // bit 6
11134 #define EXTOR OSCSTAT1bits.EXTOR // bit 7
11136 #define HFTUN0 OSCTUNEbits.HFTUN0 // bit 0
11137 #define HFTUN1 OSCTUNEbits.HFTUN1 // bit 1
11138 #define HFTUN2 OSCTUNEbits.HFTUN2 // bit 2
11139 #define HFTUN3 OSCTUNEbits.HFTUN3 // bit 3
11140 #define HFTUN4 OSCTUNEbits.HFTUN4 // bit 4
11141 #define HFTUN5 OSCTUNEbits.HFTUN5 // bit 5
11143 #define NOT_BOR PCON0bits.NOT_BOR // bit 0
11144 #define NOT_POR PCON0bits.NOT_POR // bit 1
11145 #define NOT_RI PCON0bits.NOT_RI // bit 2
11146 #define NOT_RMCLR PCON0bits.NOT_RMCLR // bit 3
11147 #define NOT_RWDT PCON0bits.NOT_RWDT // bit 4
11148 #define STKUNF PCON0bits.STKUNF // bit 6
11149 #define STKOVF PCON0bits.STKOVF // bit 7
11151 #define INTE PIE0bits.INTE // bit 0
11152 #define IOCIE PIE0bits.IOCIE // bit 4
11153 #define TMR0IE PIE0bits.TMR0IE // bit 5
11155 #define TMR1IE PIE1bits.TMR1IE // bit 0
11156 #define TMR2IE PIE1bits.TMR2IE // bit 1
11157 #define BCL1IE PIE1bits.BCL1IE // bit 2
11158 #define SSP1IE PIE1bits.SSP1IE // bit 3
11159 #define TXIE PIE1bits.TXIE // bit 4
11160 #define RCIE PIE1bits.RCIE // bit 5
11161 #define ADIE PIE1bits.ADIE // bit 6
11162 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
11164 #define NCO1IE PIE2bits.NCO1IE // bit 0
11165 #define TMR4IE PIE2bits.TMR4IE // bit 1
11166 #define BCL2IE PIE2bits.BCL2IE // bit 2
11167 #define SSP2IE PIE2bits.SSP2IE // bit 3
11168 #define NVMIE PIE2bits.NVMIE // bit 4
11169 #define C1IE PIE2bits.C1IE // bit 5
11170 #define C2IE PIE2bits.C2IE // bit 6
11171 #define TMR6IE PIE2bits.TMR6IE // bit 7
11173 #define CLC1IE PIE3bits.CLC1IE // bit 0
11174 #define CLC2IE PIE3bits.CLC2IE // bit 1
11175 #define CLC3IE PIE3bits.CLC3IE // bit 2
11176 #define CLC4IE PIE3bits.CLC4IE // bit 3
11177 #define TMR3IE PIE3bits.TMR3IE // bit 4
11178 #define TMR3GIE PIE3bits.TMR3GIE // bit 5
11179 #define CSWIE PIE3bits.CSWIE // bit 6
11180 #define OSFIE PIE3bits.OSFIE // bit 7
11182 #define CCP1IE PIE4bits.CCP1IE // bit 0
11183 #define CCP2IE PIE4bits.CCP2IE // bit 1
11184 #define CCP3IE PIE4bits.CCP3IE // bit 2
11185 #define CCP4IE PIE4bits.CCP4IE // bit 3
11186 #define TMR5IE PIE4bits.TMR5IE // bit 4
11187 #define TMR5GIE PIE4bits.TMR5GIE // bit 5
11188 #define CWG1IE PIE4bits.CWG1IE // bit 6
11189 #define CWG2IE PIE4bits.CWG2IE // bit 7
11191 #define INTF PIR0bits.INTF // bit 0
11192 #define IOCIF PIR0bits.IOCIF // bit 4
11193 #define TMR0IF PIR0bits.TMR0IF // bit 5
11195 #define TMR1IF PIR1bits.TMR1IF // bit 0
11196 #define TMR2IF PIR1bits.TMR2IF // bit 1
11197 #define BCL1IF PIR1bits.BCL1IF // bit 2
11198 #define SSP1IF PIR1bits.SSP1IF // bit 3
11199 #define TXIF PIR1bits.TXIF // bit 4
11200 #define RCIF PIR1bits.RCIF // bit 5
11201 #define ADIF PIR1bits.ADIF // bit 6
11202 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
11204 #define NCO1IF PIR2bits.NCO1IF // bit 0
11205 #define TMR4IF PIR2bits.TMR4IF // bit 1
11206 #define BCL2IF PIR2bits.BCL2IF // bit 2
11207 #define SSP2IF PIR2bits.SSP2IF // bit 3
11208 #define NVMIF PIR2bits.NVMIF // bit 4
11209 #define C1IF PIR2bits.C1IF // bit 5
11210 #define C2IF PIR2bits.C2IF // bit 6
11211 #define TMR6IF PIR2bits.TMR6IF // bit 7
11213 #define CLC1IF PIR3bits.CLC1IF // bit 0
11214 #define CLC2IF PIR3bits.CLC2IF // bit 1
11215 #define CLC3IF PIR3bits.CLC3IF // bit 2
11216 #define CLC4IF PIR3bits.CLC4IF // bit 3
11217 #define TMR3IF PIR3bits.TMR3IF // bit 4
11218 #define TMR3GIF PIR3bits.TMR3GIF // bit 5
11219 #define CSWIF PIR3bits.CSWIF // bit 6
11220 #define OSFIF PIR3bits.OSFIF // bit 7
11222 #define CCP1IF PIR4bits.CCP1IF // bit 0
11223 #define CCP2IF PIR4bits.CCP2IF // bit 1
11224 #define CCP3IF PIR4bits.CCP3IF // bit 2
11225 #define CCP4IF PIR4bits.CCP4IF // bit 3
11226 #define TMR5IF PIR4bits.TMR5IF // bit 4
11227 #define TMR5GIF PIR4bits.TMR5GIF // bit 5
11228 #define CWG1IF PIR4bits.CWG1IF // bit 6
11229 #define CWG2IF PIR4bits.CWG2IF // bit 7
11231 #define IOCMD PMD0bits.IOCMD // bit 0
11232 #define CLKRMD PMD0bits.CLKRMD // bit 1
11233 #define NVMMD PMD0bits.NVMMD // bit 2
11234 #define FVRMD PMD0bits.FVRMD // bit 6
11235 #define SYSCMD PMD0bits.SYSCMD // bit 7
11237 #define TMR0MD PMD1bits.TMR0MD // bit 0
11238 #define TMR1MD PMD1bits.TMR1MD // bit 1
11239 #define TMR2MD PMD1bits.TMR2MD // bit 2
11240 #define TMR3MD PMD1bits.TMR3MD // bit 3
11241 #define TMR4MD PMD1bits.TMR4MD // bit 4
11242 #define TMR5MD PMD1bits.TMR5MD // bit 5
11243 #define TMR6MD PMD1bits.TMR6MD // bit 6
11244 #define NCOMD PMD1bits.NCOMD // bit 7
11246 #define CMP1MD PMD2bits.CMP1MD // bit 1
11247 #define CMP2MD PMD2bits.CMP2MD // bit 2
11248 #define ADCMD PMD2bits.ADCMD // bit 5
11249 #define DACMD PMD2bits.DACMD // bit 6
11251 #define CCP1MD PMD3bits.CCP1MD // bit 0
11252 #define CCP2MD PMD3bits.CCP2MD // bit 1
11253 #define CCP3MD PMD3bits.CCP3MD // bit 2
11254 #define CCP4MD PMD3bits.CCP4MD // bit 3
11255 #define PWM5MD PMD3bits.PWM5MD // bit 4
11256 #define PWM6MD PMD3bits.PWM6MD // bit 5
11257 #define CWG1MD PMD3bits.CWG1MD // bit 6
11258 #define CWG2MD PMD3bits.CWG2MD // bit 7
11260 #define MSSP1MD PMD4bits.MSSP1MD // bit 1
11261 #define MSSP2MD PMD4bits.MSSP2MD // bit 2
11262 #define UART1MD PMD4bits.UART1MD // bit 5
11264 #define DSMMD PMD5bits.DSMMD // bit 0
11265 #define CLC1MD PMD5bits.CLC1MD // bit 1
11266 #define CLC2MD PMD5bits.CLC2MD // bit 2
11267 #define CLC3MD PMD5bits.CLC3MD // bit 3
11268 #define CLC4MD PMD5bits.CLC4MD // bit 4
11270 #define RA0 PORTAbits.RA0 // bit 0
11271 #define RA1 PORTAbits.RA1 // bit 1
11272 #define RA2 PORTAbits.RA2 // bit 2
11273 #define RA3 PORTAbits.RA3 // bit 3
11274 #define RA4 PORTAbits.RA4 // bit 4
11275 #define RA5 PORTAbits.RA5 // bit 5
11277 #define RC0 PORTCbits.RC0 // bit 0
11278 #define RC1 PORTCbits.RC1 // bit 1
11279 #define RC2 PORTCbits.RC2 // bit 2
11280 #define RC3 PORTCbits.RC3 // bit 3
11281 #define RC4 PORTCbits.RC4 // bit 4
11282 #define RC5 PORTCbits.RC5 // bit 5
11284 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
11286 #define PWM5POL PWM5CONbits.PWM5POL // bit 4
11287 #define PWM5OUT PWM5CONbits.PWM5OUT // bit 5
11288 #define PWM5EN PWM5CONbits.PWM5EN // bit 7
11290 #define PWM5DCH0 PWM5DCHbits.PWM5DCH0 // bit 0
11291 #define PWM5DCH1 PWM5DCHbits.PWM5DCH1 // bit 1
11292 #define PWM5DCH2 PWM5DCHbits.PWM5DCH2 // bit 2
11293 #define PWM5DCH3 PWM5DCHbits.PWM5DCH3 // bit 3
11294 #define PWM5DCH4 PWM5DCHbits.PWM5DCH4 // bit 4
11295 #define PWM5DCH5 PWM5DCHbits.PWM5DCH5 // bit 5
11296 #define PWM5DCH6 PWM5DCHbits.PWM5DCH6 // bit 6
11297 #define PWM5DCH7 PWM5DCHbits.PWM5DCH7 // bit 7
11299 #define PWM5DCL0 PWM5DCLbits.PWM5DCL0 // bit 6
11300 #define PWM5DCL1 PWM5DCLbits.PWM5DCL1 // bit 7
11302 #define PWM6POL PWM6CONbits.PWM6POL // bit 4
11303 #define PWM6OUT PWM6CONbits.PWM6OUT // bit 5
11304 #define PWM6EN PWM6CONbits.PWM6EN // bit 7
11306 #define PWM6DCH0 PWM6DCHbits.PWM6DCH0 // bit 0
11307 #define PWM6DCH1 PWM6DCHbits.PWM6DCH1 // bit 1
11308 #define PWM6DCH2 PWM6DCHbits.PWM6DCH2 // bit 2
11309 #define PWM6DCH3 PWM6DCHbits.PWM6DCH3 // bit 3
11310 #define PWM6DCH4 PWM6DCHbits.PWM6DCH4 // bit 4
11311 #define PWM6DCH5 PWM6DCHbits.PWM6DCH5 // bit 5
11312 #define PWM6DCH6 PWM6DCHbits.PWM6DCH6 // bit 6
11313 #define PWM6DCH7 PWM6DCHbits.PWM6DCH7 // bit 7
11315 #define PWM6DCL0 PWM6DCLbits.PWM6DCL0 // bit 6
11316 #define PWM6DCL1 PWM6DCLbits.PWM6DCL1 // bit 7
11318 #define P5TSEL0 PWMTMRSbits.P5TSEL0 // bit 0
11319 #define P5TSEL1 PWMTMRSbits.P5TSEL1 // bit 1
11320 #define P6TSEL0 PWMTMRSbits.P6TSEL0 // bit 2
11321 #define P6TSEL1 PWMTMRSbits.P6TSEL1 // bit 3
11323 #define RA0PPS0 RA0PPSbits.RA0PPS0 // bit 0
11324 #define RA0PPS1 RA0PPSbits.RA0PPS1 // bit 1
11325 #define RA0PPS2 RA0PPSbits.RA0PPS2 // bit 2
11326 #define RA0PPS3 RA0PPSbits.RA0PPS3 // bit 3
11327 #define RA0PPS4 RA0PPSbits.RA0PPS4 // bit 4
11329 #define RA1PPS0 RA1PPSbits.RA1PPS0 // bit 0
11330 #define RA1PPS1 RA1PPSbits.RA1PPS1 // bit 1
11331 #define RA1PPS2 RA1PPSbits.RA1PPS2 // bit 2
11332 #define RA1PPS3 RA1PPSbits.RA1PPS3 // bit 3
11333 #define RA1PPS4 RA1PPSbits.RA1PPS4 // bit 4
11335 #define RA2PPS0 RA2PPSbits.RA2PPS0 // bit 0
11336 #define RA2PPS1 RA2PPSbits.RA2PPS1 // bit 1
11337 #define RA2PPS2 RA2PPSbits.RA2PPS2 // bit 2
11338 #define RA2PPS3 RA2PPSbits.RA2PPS3 // bit 3
11339 #define RA2PPS4 RA2PPSbits.RA2PPS4 // bit 4
11341 #define RA4PPS0 RA4PPSbits.RA4PPS0 // bit 0
11342 #define RA4PPS1 RA4PPSbits.RA4PPS1 // bit 1
11343 #define RA4PPS2 RA4PPSbits.RA4PPS2 // bit 2
11344 #define RA4PPS3 RA4PPSbits.RA4PPS3 // bit 3
11345 #define RA4PPS4 RA4PPSbits.RA4PPS4 // bit 4
11347 #define RA5PPS0 RA5PPSbits.RA5PPS0 // bit 0
11348 #define RA5PPS1 RA5PPSbits.RA5PPS1 // bit 1
11349 #define RA5PPS2 RA5PPSbits.RA5PPS2 // bit 2
11350 #define RA5PPS3 RA5PPSbits.RA5PPS3 // bit 3
11351 #define RA5PPS4 RA5PPSbits.RA5PPS4 // bit 4
11353 #define RC0PPS0 RC0PPSbits.RC0PPS0 // bit 0
11354 #define RC0PPS1 RC0PPSbits.RC0PPS1 // bit 1
11355 #define RC0PPS2 RC0PPSbits.RC0PPS2 // bit 2
11356 #define RC0PPS3 RC0PPSbits.RC0PPS3 // bit 3
11357 #define RC0PPS4 RC0PPSbits.RC0PPS4 // bit 4
11359 #define RC1PPS0 RC1PPSbits.RC1PPS0 // bit 0
11360 #define RC1PPS1 RC1PPSbits.RC1PPS1 // bit 1
11361 #define RC1PPS2 RC1PPSbits.RC1PPS2 // bit 2
11362 #define RC1PPS3 RC1PPSbits.RC1PPS3 // bit 3
11363 #define RC1PPS4 RC1PPSbits.RC1PPS4 // bit 4
11365 #define RX9D RC1STAbits.RX9D // bit 0
11366 #define OERR RC1STAbits.OERR // bit 1
11367 #define FERR RC1STAbits.FERR // bit 2
11368 #define ADDEN RC1STAbits.ADDEN // bit 3
11369 #define CREN RC1STAbits.CREN // bit 4
11370 #define SREN RC1STAbits.SREN // bit 5
11371 #define RX9 RC1STAbits.RX9 // bit 6
11372 #define SPEN RC1STAbits.SPEN // bit 7
11374 #define RC2PPS0 RC2PPSbits.RC2PPS0 // bit 0
11375 #define RC2PPS1 RC2PPSbits.RC2PPS1 // bit 1
11376 #define RC2PPS2 RC2PPSbits.RC2PPS2 // bit 2
11377 #define RC2PPS3 RC2PPSbits.RC2PPS3 // bit 3
11378 #define RC2PPS4 RC2PPSbits.RC2PPS4 // bit 4
11380 #define RC3PPS0 RC3PPSbits.RC3PPS0 // bit 0
11381 #define RC3PPS1 RC3PPSbits.RC3PPS1 // bit 1
11382 #define RC3PPS2 RC3PPSbits.RC3PPS2 // bit 2
11383 #define RC3PPS3 RC3PPSbits.RC3PPS3 // bit 3
11384 #define RC3PPS4 RC3PPSbits.RC3PPS4 // bit 4
11386 #define RC4PPS0 RC4PPSbits.RC4PPS0 // bit 0
11387 #define RC4PPS1 RC4PPSbits.RC4PPS1 // bit 1
11388 #define RC4PPS2 RC4PPSbits.RC4PPS2 // bit 2
11389 #define RC4PPS3 RC4PPSbits.RC4PPS3 // bit 3
11390 #define RC4PPS4 RC4PPSbits.RC4PPS4 // bit 4
11392 #define RC5PPS0 RC5PPSbits.RC5PPS0 // bit 0
11393 #define RC5PPS1 RC5PPSbits.RC5PPS1 // bit 1
11394 #define RC5PPS2 RC5PPSbits.RC5PPS2 // bit 2
11395 #define RC5PPS3 RC5PPSbits.RC5PPS3 // bit 3
11396 #define RC5PPS4 RC5PPSbits.RC5PPS4 // bit 4
11398 #define RXDTPPS0 RXPPSbits.RXDTPPS0 // bit 0
11399 #define RXDTPPS1 RXPPSbits.RXDTPPS1 // bit 1
11400 #define RXDTPPS2 RXPPSbits.RXDTPPS2 // bit 2
11401 #define RXDTPPS3 RXPPSbits.RXDTPPS3 // bit 3
11402 #define RXDTPPS4 RXPPSbits.RXDTPPS4 // bit 4
11404 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
11405 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
11406 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
11407 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
11408 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
11410 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
11411 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
11412 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
11413 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
11414 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
11415 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
11417 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
11418 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
11419 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
11420 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
11421 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
11422 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
11423 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
11424 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
11425 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
11426 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
11427 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
11428 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
11429 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
11430 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
11431 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
11432 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
11434 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
11435 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
11436 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
11437 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
11438 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
11439 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
11440 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
11441 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
11442 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
11443 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
11444 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
11445 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
11446 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
11447 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
11448 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
11449 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
11451 #define SSP1CLKPPS0 SSP1CLKPPSbits.SSP1CLKPPS0 // bit 0
11452 #define SSP1CLKPPS1 SSP1CLKPPSbits.SSP1CLKPPS1 // bit 1
11453 #define SSP1CLKPPS2 SSP1CLKPPSbits.SSP1CLKPPS2 // bit 2
11454 #define SSP1CLKPPS3 SSP1CLKPPSbits.SSP1CLKPPS3 // bit 3
11455 #define SSP1CLKPPS4 SSP1CLKPPSbits.SSP1CLKPPS4 // bit 4
11457 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
11458 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
11459 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
11460 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
11461 #define CKP SSP1CONbits.CKP // bit 4
11462 #define SSPEN SSP1CONbits.SSPEN // bit 5
11463 #define SSPOV SSP1CONbits.SSPOV // bit 6
11464 #define WCOL SSP1CONbits.WCOL // bit 7
11466 #define SEN SSP1CON2bits.SEN // bit 0
11467 #define RSEN SSP1CON2bits.RSEN // bit 1
11468 #define PEN SSP1CON2bits.PEN // bit 2
11469 #define RCEN SSP1CON2bits.RCEN // bit 3
11470 #define ACKEN SSP1CON2bits.ACKEN // bit 4
11471 #define ACKDT SSP1CON2bits.ACKDT // bit 5
11472 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
11473 #define GCEN SSP1CON2bits.GCEN // bit 7
11475 #define DHEN SSP1CON3bits.DHEN // bit 0
11476 #define AHEN SSP1CON3bits.AHEN // bit 1
11477 #define SBCDE SSP1CON3bits.SBCDE // bit 2
11478 #define SDAHT SSP1CON3bits.SDAHT // bit 3
11479 #define BOEN SSP1CON3bits.BOEN // bit 4
11480 #define SCIE SSP1CON3bits.SCIE // bit 5
11481 #define PCIE SSP1CON3bits.PCIE // bit 6
11482 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
11484 #define SSP1DATPPS0 SSP1DATPPSbits.SSP1DATPPS0 // bit 0
11485 #define SSP1DATPPS1 SSP1DATPPSbits.SSP1DATPPS1 // bit 1
11486 #define SSP1DATPPS2 SSP1DATPPSbits.SSP1DATPPS2 // bit 2
11487 #define SSP1DATPPS3 SSP1DATPPSbits.SSP1DATPPS3 // bit 3
11488 #define SSP1DATPPS4 SSP1DATPPSbits.SSP1DATPPS4 // bit 4
11490 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
11491 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
11492 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
11493 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
11494 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
11495 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
11496 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
11497 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
11498 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
11499 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
11500 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
11501 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
11502 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
11503 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
11504 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
11505 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
11507 #define SSP1SSPPS0 SSP1SSPPSbits.SSP1SSPPS0 // bit 0
11508 #define SSP1SSPPS1 SSP1SSPPSbits.SSP1SSPPS1 // bit 1
11509 #define SSP1SSPPS2 SSP1SSPPSbits.SSP1SSPPS2 // bit 2
11510 #define SSP1SSPPS3 SSP1SSPPSbits.SSP1SSPPS3 // bit 3
11511 #define SSP1SSPPS4 SSP1SSPPSbits.SSP1SSPPS4 // bit 4
11513 #define BF SSP1STATbits.BF // bit 0
11514 #define UA SSP1STATbits.UA // bit 1
11515 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
11516 #define S SSP1STATbits.S // bit 3
11517 #define P SSP1STATbits.P // bit 4
11518 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
11519 #define CKE SSP1STATbits.CKE // bit 6
11520 #define SMP SSP1STATbits.SMP // bit 7
11522 #define SSP2CLKPPS0 SSP2CLKPPSbits.SSP2CLKPPS0 // bit 0
11523 #define SSP2CLKPPS1 SSP2CLKPPSbits.SSP2CLKPPS1 // bit 1
11524 #define SSP2CLKPPS2 SSP2CLKPPSbits.SSP2CLKPPS2 // bit 2
11525 #define SSP2CLKPPS3 SSP2CLKPPSbits.SSP2CLKPPS3 // bit 3
11526 #define SSP2CLKPPS4 SSP2CLKPPSbits.SSP2CLKPPS4 // bit 4
11528 #define SSP2DATPPS0 SSP2DATPPSbits.SSP2DATPPS0 // bit 0
11529 #define SSP2DATPPS1 SSP2DATPPSbits.SSP2DATPPS1 // bit 1
11530 #define SSP2DATPPS2 SSP2DATPPSbits.SSP2DATPPS2 // bit 2
11531 #define SSP2DATPPS3 SSP2DATPPSbits.SSP2DATPPS3 // bit 3
11532 #define SSP2DATPPS4 SSP2DATPPSbits.SSP2DATPPS4 // bit 4
11534 #define SSP2SSPPS0 SSP2SSPPSbits.SSP2SSPPS0 // bit 0
11535 #define SSP2SSPPS1 SSP2SSPPSbits.SSP2SSPPS1 // bit 1
11536 #define SSP2SSPPS2 SSP2SSPPSbits.SSP2SSPPS2 // bit 2
11537 #define SSP2SSPPS3 SSP2SSPPSbits.SSP2SSPPS3 // bit 3
11538 #define SSP2SSPPS4 SSP2SSPPSbits.SSP2SSPPS4 // bit 4
11540 #define C STATUSbits.C // bit 0
11541 #define DC STATUSbits.DC // bit 1
11542 #define Z STATUSbits.Z // bit 2
11543 #define NOT_PD STATUSbits.NOT_PD // bit 3
11544 #define NOT_TO STATUSbits.NOT_TO // bit 4
11546 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
11547 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
11548 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
11550 #define T0CKIPPS0 T0CKIPPSbits.T0CKIPPS0 // bit 0
11551 #define T0CKIPPS1 T0CKIPPSbits.T0CKIPPS1 // bit 1
11552 #define T0CKIPPS2 T0CKIPPSbits.T0CKIPPS2 // bit 2
11553 #define T0CKIPPS3 T0CKIPPSbits.T0CKIPPS3 // bit 3
11554 #define T0CKIPPS4 T0CKIPPSbits.T0CKIPPS4 // bit 4
11556 #define T0OUTPS0 T0CON0bits.T0OUTPS0 // bit 0
11557 #define T0OUTPS1 T0CON0bits.T0OUTPS1 // bit 1
11558 #define T0OUTPS2 T0CON0bits.T0OUTPS2 // bit 2
11559 #define T0OUTPS3 T0CON0bits.T0OUTPS3 // bit 3
11560 #define T016BIT T0CON0bits.T016BIT // bit 4
11561 #define T0OUT T0CON0bits.T0OUT // bit 5
11562 #define T0EN T0CON0bits.T0EN // bit 7
11564 #define T0CKPS0 T0CON1bits.T0CKPS0 // bit 0
11565 #define T0CKPS1 T0CON1bits.T0CKPS1 // bit 1
11566 #define T0CKPS2 T0CON1bits.T0CKPS2 // bit 2
11567 #define T0CKPS3 T0CON1bits.T0CKPS3 // bit 3
11568 #define T0ASYNC T0CON1bits.T0ASYNC // bit 4
11569 #define T0CS0 T0CON1bits.T0CS0 // bit 5
11570 #define T0CS1 T0CON1bits.T0CS1 // bit 6
11571 #define T0CS2 T0CON1bits.T0CS2 // bit 7
11573 #define T1CKIPPS0 T1CKIPPSbits.T1CKIPPS0 // bit 0
11574 #define T1CKIPPS1 T1CKIPPSbits.T1CKIPPS1 // bit 1
11575 #define T1CKIPPS2 T1CKIPPSbits.T1CKIPPS2 // bit 2
11576 #define T1CKIPPS3 T1CKIPPSbits.T1CKIPPS3 // bit 3
11577 #define T1CKIPPS4 T1CKIPPSbits.T1CKIPPS4 // bit 4
11579 #define TMR1ON T1CONbits.TMR1ON // bit 0
11580 #define T1SYNC T1CONbits.T1SYNC // bit 2
11581 #define T1SOSC T1CONbits.T1SOSC // bit 3
11582 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
11583 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
11584 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
11585 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
11587 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
11588 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
11589 #define T1GVAL T1GCONbits.T1GVAL // bit 2
11590 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3
11591 #define T1GSPM T1GCONbits.T1GSPM // bit 4
11592 #define T1GTM T1GCONbits.T1GTM // bit 5
11593 #define T1GPOL T1GCONbits.T1GPOL // bit 6
11594 #define TMR1GE T1GCONbits.TMR1GE // bit 7
11596 #define T1GPPS0 T1GPPSbits.T1GPPS0 // bit 0
11597 #define T1GPPS1 T1GPPSbits.T1GPPS1 // bit 1
11598 #define T1GPPS2 T1GPPSbits.T1GPPS2 // bit 2
11599 #define T1GPPS3 T1GPPSbits.T1GPPS3 // bit 3
11600 #define T1GPPS4 T1GPPSbits.T1GPPS4 // bit 4
11602 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
11603 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
11604 #define TMR2ON T2CONbits.TMR2ON // bit 2
11605 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
11606 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
11607 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
11608 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
11610 #define TMR3ON T3CONbits.TMR3ON // bit 0
11611 #define T3SYNC T3CONbits.T3SYNC // bit 2
11612 #define T3SOSC T3CONbits.T3SOSC // bit 3
11613 #define T3CKPS0 T3CONbits.T3CKPS0 // bit 4
11614 #define T3CKPS1 T3CONbits.T3CKPS1 // bit 5
11615 #define TMR3CS0 T3CONbits.TMR3CS0 // bit 6
11616 #define TMR3CS1 T3CONbits.TMR3CS1 // bit 7
11618 #define T3GSS0 T3GCONbits.T3GSS0 // bit 0
11619 #define T3GSS1 T3GCONbits.T3GSS1 // bit 1
11620 #define T3GVAL T3GCONbits.T3GVAL // bit 2
11621 #define T3GGO_NOT_DONE T3GCONbits.T3GGO_NOT_DONE // bit 3
11622 #define T3GSPM T3GCONbits.T3GSPM // bit 4
11623 #define T3GTM T3GCONbits.T3GTM // bit 5
11624 #define T3GPOL T3GCONbits.T3GPOL // bit 6
11625 #define TMR3GE T3GCONbits.TMR3GE // bit 7
11627 #define T4CKPS0 T4CONbits.T4CKPS0 // bit 0
11628 #define T4CKPS1 T4CONbits.T4CKPS1 // bit 1
11629 #define TMR4ON T4CONbits.TMR4ON // bit 2
11630 #define T4OUTPS0 T4CONbits.T4OUTPS0 // bit 3
11631 #define T4OUTPS1 T4CONbits.T4OUTPS1 // bit 4
11632 #define T4OUTPS2 T4CONbits.T4OUTPS2 // bit 5
11633 #define T4OUTPS3 T4CONbits.T4OUTPS3 // bit 6
11635 #define TMR5ON T5CONbits.TMR5ON // bit 0
11636 #define T5SYNC T5CONbits.T5SYNC // bit 2
11637 #define T5SOSC T5CONbits.T5SOSC // bit 3
11638 #define T5CKPS0 T5CONbits.T5CKPS0 // bit 4
11639 #define T5CKPS1 T5CONbits.T5CKPS1 // bit 5
11640 #define TMR5CS0 T5CONbits.TMR5CS0 // bit 6
11641 #define TMR5CS1 T5CONbits.TMR5CS1 // bit 7
11643 #define T5GSS0 T5GCONbits.T5GSS0 // bit 0
11644 #define T5GSS1 T5GCONbits.T5GSS1 // bit 1
11645 #define T5GVAL T5GCONbits.T5GVAL // bit 2
11646 #define T5GGO_NOT_DONE T5GCONbits.T5GGO_NOT_DONE // bit 3
11647 #define T5GSPM T5GCONbits.T5GSPM // bit 4
11648 #define T5GTM T5GCONbits.T5GTM // bit 5
11649 #define T5GPOL T5GCONbits.T5GPOL // bit 6
11650 #define TMR5GE T5GCONbits.TMR5GE // bit 7
11652 #define T6CKPS0 T6CONbits.T6CKPS0 // bit 0
11653 #define T6CKPS1 T6CONbits.T6CKPS1 // bit 1
11654 #define TMR6ON T6CONbits.TMR6ON // bit 2
11655 #define T6OUTPS0 T6CONbits.T6OUTPS0 // bit 3
11656 #define T6OUTPS1 T6CONbits.T6OUTPS1 // bit 4
11657 #define T6OUTPS2 T6CONbits.T6OUTPS2 // bit 5
11658 #define T6OUTPS3 T6CONbits.T6OUTPS3 // bit 6
11660 #define TMR08 TMR0Hbits.TMR08 // bit 0
11661 #define TMR09 TMR0Hbits.TMR09 // bit 1
11662 #define TMR010 TMR0Hbits.TMR010 // bit 2
11663 #define TMR011 TMR0Hbits.TMR011 // bit 3
11664 #define TMR012 TMR0Hbits.TMR012 // bit 4
11665 #define TMR013 TMR0Hbits.TMR013 // bit 5
11666 #define TMR014 TMR0Hbits.TMR014 // bit 6
11667 #define TMR015 TMR0Hbits.TMR015 // bit 7
11669 #define TMR00 TMR0Lbits.TMR00 // bit 0
11670 #define TMR01 TMR0Lbits.TMR01 // bit 1
11671 #define TMR02 TMR0Lbits.TMR02 // bit 2
11672 #define TMR03 TMR0Lbits.TMR03 // bit 3
11673 #define TMR04 TMR0Lbits.TMR04 // bit 4
11674 #define TMR05 TMR0Lbits.TMR05 // bit 5
11675 #define TMR06 TMR0Lbits.TMR06 // bit 6
11676 #define TMR07 TMR0Lbits.TMR07 // bit 7
11678 #define TRISA0 TRISAbits.TRISA0 // bit 0
11679 #define TRISA1 TRISAbits.TRISA1 // bit 1
11680 #define TRISA2 TRISAbits.TRISA2 // bit 2
11681 #define TRISA4 TRISAbits.TRISA4 // bit 4
11682 #define TRISA5 TRISAbits.TRISA5 // bit 5
11684 #define TRISC0 TRISCbits.TRISC0 // bit 0
11685 #define TRISC1 TRISCbits.TRISC1 // bit 1
11686 #define TRISC2 TRISCbits.TRISC2 // bit 2
11687 #define TRISC3 TRISCbits.TRISC3 // bit 3
11688 #define TRISC4 TRISCbits.TRISC4 // bit 4
11689 #define TRISC5 TRISCbits.TRISC5 // bit 5
11691 #define TX9D TX1STAbits.TX9D // bit 0
11692 #define TRMT TX1STAbits.TRMT // bit 1
11693 #define BRGH TX1STAbits.BRGH // bit 2
11694 #define SENDB TX1STAbits.SENDB // bit 3
11695 #define SYNC TX1STAbits.SYNC // bit 4
11696 #define TXEN TX1STAbits.TXEN // bit 5
11697 #define TX9 TX1STAbits.TX9 // bit 6
11698 #define CSRC TX1STAbits.CSRC // bit 7
11700 #define TXCKPPS0 TXPPSbits.TXCKPPS0 // bit 0
11701 #define TXCKPPS1 TXPPSbits.TXCKPPS1 // bit 1
11702 #define TXCKPPS2 TXPPSbits.TXCKPPS2 // bit 2
11703 #define TXCKPPS3 TXPPSbits.TXCKPPS3 // bit 3
11704 #define TXCKPPS4 TXPPSbits.TXCKPPS4 // bit 4
11706 #define SWDTEN WDTCONbits.SWDTEN // bit 0
11707 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
11708 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
11709 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
11710 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
11711 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
11713 #define WPUA0 WPUAbits.WPUA0 // bit 0
11714 #define WPUA1 WPUAbits.WPUA1 // bit 1
11715 #define WPUA2 WPUAbits.WPUA2 // bit 2
11716 #define WPUA3 WPUAbits.WPUA3 // bit 3
11717 #define WPUA4 WPUAbits.WPUA4 // bit 4
11718 #define WPUA5 WPUAbits.WPUA5 // bit 5
11720 #define WPUC0 WPUCbits.WPUC0 // bit 0
11721 #define WPUC1 WPUCbits.WPUC1 // bit 1
11722 #define WPUC2 WPUCbits.WPUC2 // bit 2
11723 #define WPUC3 WPUCbits.WPUC3 // bit 3
11724 #define WPUC4 WPUCbits.WPUC4 // bit 4
11725 #define WPUC5 WPUCbits.WPUC5 // bit 5
11727 #endif // #ifndef NO_BIT_DEFINES
11729 #endif // #ifndef __PIC16LF18325_H__