2 * This declarations of the PIC16LF18345 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:24 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16LF18345_H__
26 #define __PIC16LF18345_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTB_ADDR 0x000D
52 #define PORTC_ADDR 0x000E
53 #define PIR0_ADDR 0x0010
54 #define PIR1_ADDR 0x0011
55 #define PIR2_ADDR 0x0012
56 #define PIR3_ADDR 0x0013
57 #define PIR4_ADDR 0x0014
58 #define TMR0L_ADDR 0x0015
59 #define TMR0H_ADDR 0x0016
60 #define T0CON0_ADDR 0x0017
61 #define T0CON1_ADDR 0x0018
62 #define TMR1_ADDR 0x0019
63 #define TMR1L_ADDR 0x0019
64 #define TMR1H_ADDR 0x001A
65 #define T1CON_ADDR 0x001B
66 #define T1GCON_ADDR 0x001C
67 #define TMR2_ADDR 0x001D
68 #define PR2_ADDR 0x001E
69 #define T2CON_ADDR 0x001F
70 #define TRISA_ADDR 0x008C
71 #define TRISB_ADDR 0x008D
72 #define TRISC_ADDR 0x008E
73 #define PIE0_ADDR 0x0090
74 #define PIE1_ADDR 0x0091
75 #define PIE2_ADDR 0x0092
76 #define PIE3_ADDR 0x0093
77 #define PIE4_ADDR 0x0094
78 #define WDTCON_ADDR 0x0097
79 #define ADRES_ADDR 0x009B
80 #define ADRESL_ADDR 0x009B
81 #define ADRESH_ADDR 0x009C
82 #define ADCON0_ADDR 0x009D
83 #define ADCON1_ADDR 0x009E
84 #define ADACT_ADDR 0x009F
85 #define LATA_ADDR 0x010C
86 #define LATB_ADDR 0x010D
87 #define LATC_ADDR 0x010E
88 #define CM1CON0_ADDR 0x0111
89 #define CM1CON1_ADDR 0x0112
90 #define CM2CON0_ADDR 0x0113
91 #define CM2CON1_ADDR 0x0114
92 #define CMOUT_ADDR 0x0115
93 #define BORCON_ADDR 0x0116
94 #define FVRCON_ADDR 0x0117
95 #define DACCON0_ADDR 0x0118
96 #define DACCON1_ADDR 0x0119
97 #define ANSELA_ADDR 0x018C
98 #define ANSELB_ADDR 0x018D
99 #define ANSELC_ADDR 0x018E
100 #define RC1REG_ADDR 0x0199
101 #define RCREG_ADDR 0x0199
102 #define RCREG1_ADDR 0x0199
103 #define TX1REG_ADDR 0x019A
104 #define TXREG_ADDR 0x019A
105 #define TXREG1_ADDR 0x019A
106 #define SP1BRG_ADDR 0x019B
107 #define SP1BRGL_ADDR 0x019B
108 #define SPBRG_ADDR 0x019B
109 #define SPBRG1_ADDR 0x019B
110 #define SPBRGL_ADDR 0x019B
111 #define SP1BRGH_ADDR 0x019C
112 #define SPBRGH_ADDR 0x019C
113 #define SPBRGH1_ADDR 0x019C
114 #define RC1STA_ADDR 0x019D
115 #define RCSTA_ADDR 0x019D
116 #define RCSTA1_ADDR 0x019D
117 #define TX1STA_ADDR 0x019E
118 #define TXSTA_ADDR 0x019E
119 #define TXSTA1_ADDR 0x019E
120 #define BAUD1CON_ADDR 0x019F
121 #define BAUDCON_ADDR 0x019F
122 #define BAUDCON1_ADDR 0x019F
123 #define BAUDCTL_ADDR 0x019F
124 #define BAUDCTL1_ADDR 0x019F
125 #define WPUA_ADDR 0x020C
126 #define WPUB_ADDR 0x020D
127 #define WPUC_ADDR 0x020E
128 #define SSP1BUF_ADDR 0x0211
129 #define SSPBUF_ADDR 0x0211
130 #define SSP1ADD_ADDR 0x0212
131 #define SSPADD_ADDR 0x0212
132 #define SSP1MSK_ADDR 0x0213
133 #define SSPMSK_ADDR 0x0213
134 #define SSP1STAT_ADDR 0x0214
135 #define SSPSTAT_ADDR 0x0214
136 #define SSP1CON_ADDR 0x0215
137 #define SSP1CON1_ADDR 0x0215
138 #define SSPCON_ADDR 0x0215
139 #define SSPCON1_ADDR 0x0215
140 #define SSP1CON2_ADDR 0x0216
141 #define SSPCON2_ADDR 0x0216
142 #define SSP1CON3_ADDR 0x0217
143 #define SSPCON3_ADDR 0x0217
144 #define SSP2BUF_ADDR 0x0219
145 #define SSP2ADD_ADDR 0x021A
146 #define SSP2MSK_ADDR 0x021B
147 #define SSP2STAT_ADDR 0x021C
148 #define SSP2CON_ADDR 0x021D
149 #define SSP2CON1_ADDR 0x021D
150 #define SSP2CON2_ADDR 0x021E
151 #define SSP2CON3_ADDR 0x021F
152 #define ODCONA_ADDR 0x028C
153 #define ODCONB_ADDR 0x028D
154 #define ODCONC_ADDR 0x028E
155 #define CCPR1_ADDR 0x0291
156 #define CCPR1L_ADDR 0x0291
157 #define CCPR1H_ADDR 0x0292
158 #define CCP1CON_ADDR 0x0293
159 #define CCP1CAP_ADDR 0x0294
160 #define CCPR2_ADDR 0x0295
161 #define CCPR2L_ADDR 0x0295
162 #define CCPR2H_ADDR 0x0296
163 #define CCP2CON_ADDR 0x0297
164 #define CCP2CAP_ADDR 0x0298
165 #define CCPTMRS_ADDR 0x029F
166 #define SLRCONA_ADDR 0x030C
167 #define SLRCONB_ADDR 0x030D
168 #define SLRCONC_ADDR 0x030E
169 #define CCPR3_ADDR 0x0311
170 #define CCPR3L_ADDR 0x0311
171 #define CCPR3H_ADDR 0x0312
172 #define CCP3CON_ADDR 0x0313
173 #define CCP3CAP_ADDR 0x0314
174 #define CCPR4_ADDR 0x0315
175 #define CCPR4L_ADDR 0x0315
176 #define CCPR4H_ADDR 0x0316
177 #define CCP4CON_ADDR 0x0317
178 #define CCP4CAP_ADDR 0x0318
179 #define INLVLA_ADDR 0x038C
180 #define INLVLB_ADDR 0x038D
181 #define INLVLC_ADDR 0x038E
182 #define IOCAP_ADDR 0x0391
183 #define IOCAN_ADDR 0x0392
184 #define IOCAF_ADDR 0x0393
185 #define IOCBP_ADDR 0x0394
186 #define IOCBN_ADDR 0x0395
187 #define IOCBF_ADDR 0x0396
188 #define IOCCP_ADDR 0x0397
189 #define IOCCN_ADDR 0x0398
190 #define IOCCF_ADDR 0x0399
191 #define CLKRCON_ADDR 0x039A
192 #define MDCON_ADDR 0x039C
193 #define MDSRC_ADDR 0x039D
194 #define MDCARH_ADDR 0x039E
195 #define MDCARL_ADDR 0x039F
196 #define CCDNA_ADDR 0x040C
197 #define CCDNB_ADDR 0x040D
198 #define CCDNC_ADDR 0x040E
199 #define TMR3_ADDR 0x0411
200 #define TMR3L_ADDR 0x0411
201 #define TMR3H_ADDR 0x0412
202 #define T3CON_ADDR 0x0413
203 #define T3GCON_ADDR 0x0414
204 #define TMR4_ADDR 0x0415
205 #define PR4_ADDR 0x0416
206 #define T4CON_ADDR 0x0417
207 #define TMR5_ADDR 0x0418
208 #define TMR5L_ADDR 0x0418
209 #define TMR5H_ADDR 0x0419
210 #define T5CON_ADDR 0x041A
211 #define T5GCON_ADDR 0x041B
212 #define TMR6_ADDR 0x041C
213 #define PR6_ADDR 0x041D
214 #define T6CON_ADDR 0x041E
215 #define CCDCON_ADDR 0x041F
216 #define CCDPA_ADDR 0x048C
217 #define CCDPB_ADDR 0x048D
218 #define CCDPC_ADDR 0x048E
219 #define NCO1ACC_ADDR 0x0498
220 #define NCO1ACCL_ADDR 0x0498
221 #define NCO1ACCH_ADDR 0x0499
222 #define NCO1ACCU_ADDR 0x049A
223 #define NCO1INC_ADDR 0x049B
224 #define NCO1INCL_ADDR 0x049B
225 #define NCO1INCH_ADDR 0x049C
226 #define NCO1INCU_ADDR 0x049D
227 #define NCO1CON_ADDR 0x049E
228 #define NCO1CLK_ADDR 0x049F
229 #define PWM5DCL_ADDR 0x0617
230 #define PWM5DCH_ADDR 0x0618
231 #define PWM5CON_ADDR 0x0619
232 #define PWM5CON0_ADDR 0x0619
233 #define PWM6DCL_ADDR 0x061A
234 #define PWM6DCH_ADDR 0x061B
235 #define PWM6CON_ADDR 0x061C
236 #define PWM6CON0_ADDR 0x061C
237 #define PWMTMRS_ADDR 0x061F
238 #define CWG1CLKCON_ADDR 0x0691
239 #define CWG1DAT_ADDR 0x0692
240 #define CWG1DBR_ADDR 0x0693
241 #define CWG1DBF_ADDR 0x0694
242 #define CWG1CON0_ADDR 0x0695
243 #define CWG1CON1_ADDR 0x0696
244 #define CWG1AS0_ADDR 0x0697
245 #define CWG1AS1_ADDR 0x0698
246 #define CWG1STR_ADDR 0x0699
247 #define CWG2CLKCON_ADDR 0x0711
248 #define CWG2DAT_ADDR 0x0712
249 #define CWG2DBR_ADDR 0x0713
250 #define CWG2DBF_ADDR 0x0714
251 #define CWG2CON0_ADDR 0x0715
252 #define CWG2CON1_ADDR 0x0716
253 #define CWG2AS0_ADDR 0x0717
254 #define CWG2AS1_ADDR 0x0718
255 #define CWG2STR_ADDR 0x0719
256 #define NVMADR_ADDR 0x0891
257 #define NVMADRL_ADDR 0x0891
258 #define NVMADRH_ADDR 0x0892
259 #define NVMDAT_ADDR 0x0893
260 #define NVMDATL_ADDR 0x0893
261 #define NVMDATH_ADDR 0x0894
262 #define NVMCON1_ADDR 0x0895
263 #define NVMCON2_ADDR 0x0896
264 #define PCON0_ADDR 0x089B
265 #define PMD0_ADDR 0x0911
266 #define PMD1_ADDR 0x0912
267 #define PMD2_ADDR 0x0913
268 #define PMD3_ADDR 0x0914
269 #define PMD4_ADDR 0x0915
270 #define PMD5_ADDR 0x0916
271 #define CPUDOZE_ADDR 0x0918
272 #define OSCCON1_ADDR 0x0919
273 #define OSCCON2_ADDR 0x091A
274 #define OSCCON3_ADDR 0x091B
275 #define OSCSTAT1_ADDR 0x091C
276 #define OSCEN_ADDR 0x091D
277 #define OSCTUNE_ADDR 0x091E
278 #define OSCFRQ_ADDR 0x091F
279 #define PPSLOCK_ADDR 0x0E0F
280 #define INTPPS_ADDR 0x0E10
281 #define T0CKIPPS_ADDR 0x0E11
282 #define T1CKIPPS_ADDR 0x0E12
283 #define T1GPPS_ADDR 0x0E13
284 #define CCP1PPS_ADDR 0x0E14
285 #define CCP2PPS_ADDR 0x0E15
286 #define CCP3PPS_ADDR 0x0E16
287 #define CCP4PPS_ADDR 0x0E17
288 #define CWG1PPS_ADDR 0x0E18
289 #define CWG2PPS_ADDR 0x0E19
290 #define MDCIN1PPS_ADDR 0x0E1A
291 #define MDCIN2PPS_ADDR 0x0E1B
292 #define MDMINPPS_ADDR 0x0E1C
293 #define SSP2CLKPPS_ADDR 0x0E1D
294 #define SSP2DATPPS_ADDR 0x0E1E
295 #define SSP2SSPPS_ADDR 0x0E1F
296 #define SSP1CLKPPS_ADDR 0x0E20
297 #define SSP1DATPPS_ADDR 0x0E21
298 #define SSP1SSPPS_ADDR 0x0E22
299 #define RXPPS_ADDR 0x0E24
300 #define TXPPS_ADDR 0x0E25
301 #define CLCIN0PPS_ADDR 0x0E28
302 #define CLCIN1PPS_ADDR 0x0E29
303 #define CLCIN2PPS_ADDR 0x0E2A
304 #define CLCIN3PPS_ADDR 0x0E2B
305 #define T3CKIPPS_ADDR 0x0E2C
306 #define T3GPPS_ADDR 0x0E2D
307 #define T5CKIPPS_ADDR 0x0E2E
308 #define T5GPPS_ADDR 0x0E2F
309 #define RA0PPS_ADDR 0x0E90
310 #define RA1PPS_ADDR 0x0E91
311 #define RA2PPS_ADDR 0x0E92
312 #define RA4PPS_ADDR 0x0E94
313 #define RA5PPS_ADDR 0x0E95
314 #define RB4PPS_ADDR 0x0E9C
315 #define RB5PPS_ADDR 0x0E9D
316 #define RB6PPS_ADDR 0x0E9E
317 #define RB7PPS_ADDR 0x0E9F
318 #define RC0PPS_ADDR 0x0EA0
319 #define RC1PPS_ADDR 0x0EA1
320 #define RC2PPS_ADDR 0x0EA2
321 #define RC3PPS_ADDR 0x0EA3
322 #define RC4PPS_ADDR 0x0EA4
323 #define RC5PPS_ADDR 0x0EA5
324 #define RC6PPS_ADDR 0x0EA6
325 #define RC7PPS_ADDR 0x0EA7
326 #define CLCDATA_ADDR 0x0F0F
327 #define CLC1CON_ADDR 0x0F10
328 #define CLC1POL_ADDR 0x0F11
329 #define CLC1SEL0_ADDR 0x0F12
330 #define CLC1SEL1_ADDR 0x0F13
331 #define CLC1SEL2_ADDR 0x0F14
332 #define CLC1SEL3_ADDR 0x0F15
333 #define CLC1GLS0_ADDR 0x0F16
334 #define CLC1GLS1_ADDR 0x0F17
335 #define CLC1GLS2_ADDR 0x0F18
336 #define CLC1GLS3_ADDR 0x0F19
337 #define CLC2CON_ADDR 0x0F1A
338 #define CLC2POL_ADDR 0x0F1B
339 #define CLC2SEL0_ADDR 0x0F1C
340 #define CLC2SEL1_ADDR 0x0F1D
341 #define CLC2SEL2_ADDR 0x0F1E
342 #define CLC2SEL3_ADDR 0x0F1F
343 #define CLC2GLS0_ADDR 0x0F20
344 #define CLC2GLS1_ADDR 0x0F21
345 #define CLC2GLS2_ADDR 0x0F22
346 #define CLC2GLS3_ADDR 0x0F23
347 #define CLC3CON_ADDR 0x0F24
348 #define CLC3POL_ADDR 0x0F25
349 #define CLC3SEL0_ADDR 0x0F26
350 #define CLC3SEL1_ADDR 0x0F27
351 #define CLC3SEL2_ADDR 0x0F28
352 #define CLC3SEL3_ADDR 0x0F29
353 #define CLC3GLS0_ADDR 0x0F2A
354 #define CLC3GLS1_ADDR 0x0F2B
355 #define CLC3GLS2_ADDR 0x0F2C
356 #define CLC3GLS3_ADDR 0x0F2D
357 #define CLC4CON_ADDR 0x0F2E
358 #define CLC4POL_ADDR 0x0F2F
359 #define CLC4SEL0_ADDR 0x0F30
360 #define CLC4SEL1_ADDR 0x0F31
361 #define CLC4SEL2_ADDR 0x0F32
362 #define CLC4SEL3_ADDR 0x0F33
363 #define CLC4GLS0_ADDR 0x0F34
364 #define CLC4GLS1_ADDR 0x0F35
365 #define CLC4GLS2_ADDR 0x0F36
366 #define CLC4GLS3_ADDR 0x0F37
367 #define STATUS_SHAD_ADDR 0x0FE4
368 #define WREG_SHAD_ADDR 0x0FE5
369 #define BSR_SHAD_ADDR 0x0FE6
370 #define PCLATH_SHAD_ADDR 0x0FE7
371 #define FSR0L_SHAD_ADDR 0x0FE8
372 #define FSR0H_SHAD_ADDR 0x0FE9
373 #define FSR1L_SHAD_ADDR 0x0FEA
374 #define FSR1H_SHAD_ADDR 0x0FEB
375 #define STKPTR_ADDR 0x0FED
376 #define TOSL_ADDR 0x0FEE
377 #define TOSH_ADDR 0x0FEF
379 #endif // #ifndef NO_ADDR_DEFINES
381 //==============================================================================
383 // Register Definitions
385 //==============================================================================
387 extern __at(0x0000) __sfr INDF0
;
388 extern __at(0x0001) __sfr INDF1
;
389 extern __at(0x0002) __sfr PCL
;
391 //==============================================================================
394 extern __at(0x0003) __sfr STATUS
;
408 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
416 //==============================================================================
418 extern __at(0x0004) __sfr FSR0
;
419 extern __at(0x0004) __sfr FSR0L
;
420 extern __at(0x0005) __sfr FSR0H
;
421 extern __at(0x0006) __sfr FSR1
;
422 extern __at(0x0006) __sfr FSR1L
;
423 extern __at(0x0007) __sfr FSR1H
;
425 //==============================================================================
428 extern __at(0x0008) __sfr BSR
;
451 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
459 //==============================================================================
461 extern __at(0x0009) __sfr WREG
;
462 extern __at(0x000A) __sfr PCLATH
;
464 //==============================================================================
467 extern __at(0x000B) __sfr INTCON
;
481 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
487 //==============================================================================
490 //==============================================================================
493 extern __at(0x000C) __sfr PORTA
;
516 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
525 //==============================================================================
528 //==============================================================================
531 extern __at(0x000D) __sfr PORTB
;
545 extern __at(0x000D) volatile __PORTBbits_t PORTBbits
;
552 //==============================================================================
555 //==============================================================================
558 extern __at(0x000E) __sfr PORTC
;
572 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
583 //==============================================================================
586 //==============================================================================
589 extern __at(0x0010) __sfr PIR0
;
603 extern __at(0x0010) volatile __PIR0bits_t PIR0bits
;
609 //==============================================================================
612 //==============================================================================
615 extern __at(0x0011) __sfr PIR1
;
626 unsigned TMR1GIF
: 1;
629 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
638 #define _TMR1GIF 0x80
640 //==============================================================================
643 //==============================================================================
646 extern __at(0x0012) __sfr PIR2
;
660 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
671 //==============================================================================
674 //==============================================================================
677 extern __at(0x0013) __sfr PIR3
;
686 unsigned TMR3GIF
: 1;
691 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
698 #define _TMR3GIF 0x20
702 //==============================================================================
705 //==============================================================================
708 extern __at(0x0014) __sfr PIR4
;
717 unsigned TMR5GIF
: 1;
722 extern __at(0x0014) volatile __PIR4bits_t PIR4bits
;
729 #define _TMR5GIF 0x20
733 //==============================================================================
736 //==============================================================================
739 extern __at(0x0015) __sfr TMR0L
;
753 extern __at(0x0015) volatile __TMR0Lbits_t TMR0Lbits
;
764 //==============================================================================
767 //==============================================================================
770 extern __at(0x0016) __sfr TMR0H
;
784 extern __at(0x0016) volatile __TMR0Hbits_t TMR0Hbits
;
795 //==============================================================================
798 //==============================================================================
801 extern __at(0x0017) __sfr T0CON0
;
807 unsigned T0OUTPS0
: 1;
808 unsigned T0OUTPS1
: 1;
809 unsigned T0OUTPS2
: 1;
810 unsigned T0OUTPS3
: 1;
811 unsigned T016BIT
: 1;
819 unsigned T0OUTPS
: 4;
824 extern __at(0x0017) volatile __T0CON0bits_t T0CON0bits
;
826 #define _T0OUTPS0 0x01
827 #define _T0OUTPS1 0x02
828 #define _T0OUTPS2 0x04
829 #define _T0OUTPS3 0x08
830 #define _T016BIT 0x10
834 //==============================================================================
837 //==============================================================================
840 extern __at(0x0018) __sfr T0CON1
;
846 unsigned T0CKPS0
: 1;
847 unsigned T0CKPS1
: 1;
848 unsigned T0CKPS2
: 1;
849 unsigned T0CKPS3
: 1;
850 unsigned T0ASYNC
: 1;
869 extern __at(0x0018) volatile __T0CON1bits_t T0CON1bits
;
871 #define _T0CKPS0 0x01
872 #define _T0CKPS1 0x02
873 #define _T0CKPS2 0x04
874 #define _T0CKPS3 0x08
875 #define _T0ASYNC 0x10
880 //==============================================================================
882 extern __at(0x0019) __sfr TMR1
;
883 extern __at(0x0019) __sfr TMR1L
;
884 extern __at(0x001A) __sfr TMR1H
;
886 //==============================================================================
889 extern __at(0x001B) __sfr T1CON
;
899 unsigned T1CKPS0
: 1;
900 unsigned T1CKPS1
: 1;
901 unsigned TMR1CS0
: 1;
902 unsigned TMR1CS1
: 1;
919 extern __at(0x001B) volatile __T1CONbits_t T1CONbits
;
924 #define _T1CKPS0 0x10
925 #define _T1CKPS1 0x20
926 #define _TMR1CS0 0x40
927 #define _TMR1CS1 0x80
929 //==============================================================================
932 //==============================================================================
935 extern __at(0x001C) __sfr T1GCON
;
944 unsigned T1GGO_NOT_DONE
: 1;
958 extern __at(0x001C) volatile __T1GCONbits_t T1GCONbits
;
963 #define _T1GGO_NOT_DONE 0x08
969 //==============================================================================
971 extern __at(0x001D) __sfr TMR2
;
972 extern __at(0x001E) __sfr PR2
;
974 //==============================================================================
977 extern __at(0x001F) __sfr T2CON
;
983 unsigned T2CKPS0
: 1;
984 unsigned T2CKPS1
: 1;
986 unsigned T2OUTPS0
: 1;
987 unsigned T2OUTPS1
: 1;
988 unsigned T2OUTPS2
: 1;
989 unsigned T2OUTPS3
: 1;
1002 unsigned T2OUTPS
: 4;
1007 extern __at(0x001F) volatile __T2CONbits_t T2CONbits
;
1009 #define _T2CKPS0 0x01
1010 #define _T2CKPS1 0x02
1011 #define _TMR2ON 0x04
1012 #define _T2OUTPS0 0x08
1013 #define _T2OUTPS1 0x10
1014 #define _T2OUTPS2 0x20
1015 #define _T2OUTPS3 0x40
1017 //==============================================================================
1020 //==============================================================================
1023 extern __at(0x008C) __sfr TRISA
;
1027 unsigned TRISA0
: 1;
1028 unsigned TRISA1
: 1;
1029 unsigned TRISA2
: 1;
1031 unsigned TRISA4
: 1;
1032 unsigned TRISA5
: 1;
1037 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
1039 #define _TRISA0 0x01
1040 #define _TRISA1 0x02
1041 #define _TRISA2 0x04
1042 #define _TRISA4 0x10
1043 #define _TRISA5 0x20
1045 //==============================================================================
1048 //==============================================================================
1051 extern __at(0x008D) __sfr TRISB
;
1059 unsigned TRISB4
: 1;
1060 unsigned TRISB5
: 1;
1061 unsigned TRISB6
: 1;
1062 unsigned TRISB7
: 1;
1065 extern __at(0x008D) volatile __TRISBbits_t TRISBbits
;
1067 #define _TRISB4 0x10
1068 #define _TRISB5 0x20
1069 #define _TRISB6 0x40
1070 #define _TRISB7 0x80
1072 //==============================================================================
1075 //==============================================================================
1078 extern __at(0x008E) __sfr TRISC
;
1082 unsigned TRISC0
: 1;
1083 unsigned TRISC1
: 1;
1084 unsigned TRISC2
: 1;
1085 unsigned TRISC3
: 1;
1086 unsigned TRISC4
: 1;
1087 unsigned TRISC5
: 1;
1088 unsigned TRISC6
: 1;
1089 unsigned TRISC7
: 1;
1092 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
1094 #define _TRISC0 0x01
1095 #define _TRISC1 0x02
1096 #define _TRISC2 0x04
1097 #define _TRISC3 0x08
1098 #define _TRISC4 0x10
1099 #define _TRISC5 0x20
1100 #define _TRISC6 0x40
1101 #define _TRISC7 0x80
1103 //==============================================================================
1106 //==============================================================================
1109 extern __at(0x0090) __sfr PIE0
;
1118 unsigned TMR0IE
: 1;
1123 extern __at(0x0090) volatile __PIE0bits_t PIE0bits
;
1127 #define _TMR0IE 0x20
1129 //==============================================================================
1132 //==============================================================================
1135 extern __at(0x0091) __sfr PIE1
;
1139 unsigned TMR1IE
: 1;
1140 unsigned TMR2IE
: 1;
1141 unsigned BCL1IE
: 1;
1142 unsigned SSP1IE
: 1;
1146 unsigned TMR1GIE
: 1;
1149 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
1151 #define _TMR1IE 0x01
1152 #define _TMR2IE 0x02
1153 #define _BCL1IE 0x04
1154 #define _SSP1IE 0x08
1158 #define _TMR1GIE 0x80
1160 //==============================================================================
1163 //==============================================================================
1166 extern __at(0x0092) __sfr PIE2
;
1170 unsigned NCO1IE
: 1;
1171 unsigned TMR4IE
: 1;
1172 unsigned BCL2IE
: 1;
1173 unsigned SSP2IE
: 1;
1177 unsigned TMR6IE
: 1;
1180 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
1182 #define _NCO1IE 0x01
1183 #define _TMR4IE 0x02
1184 #define _BCL2IE 0x04
1185 #define _SSP2IE 0x08
1189 #define _TMR6IE 0x80
1191 //==============================================================================
1194 //==============================================================================
1197 extern __at(0x0093) __sfr PIE3
;
1201 unsigned CLC1IE
: 1;
1202 unsigned CLC2IE
: 1;
1203 unsigned CLC3IE
: 1;
1204 unsigned CLC4IE
: 1;
1205 unsigned TMR3IE
: 1;
1206 unsigned TMR3GIE
: 1;
1211 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
1213 #define _CLC1IE 0x01
1214 #define _CLC2IE 0x02
1215 #define _CLC3IE 0x04
1216 #define _CLC4IE 0x08
1217 #define _TMR3IE 0x10
1218 #define _TMR3GIE 0x20
1222 //==============================================================================
1225 //==============================================================================
1228 extern __at(0x0094) __sfr PIE4
;
1232 unsigned CCP1IE
: 1;
1233 unsigned CCP2IE
: 1;
1234 unsigned CCP3IE
: 1;
1235 unsigned CCP4IE
: 1;
1236 unsigned TMR5IE
: 1;
1237 unsigned TMR5GIE
: 1;
1238 unsigned CWG1IE
: 1;
1239 unsigned CWG2IE
: 1;
1242 extern __at(0x0094) volatile __PIE4bits_t PIE4bits
;
1244 #define _CCP1IE 0x01
1245 #define _CCP2IE 0x02
1246 #define _CCP3IE 0x04
1247 #define _CCP4IE 0x08
1248 #define _TMR5IE 0x10
1249 #define _TMR5GIE 0x20
1250 #define _CWG1IE 0x40
1251 #define _CWG2IE 0x80
1253 //==============================================================================
1256 //==============================================================================
1259 extern __at(0x0097) __sfr WDTCON
;
1265 unsigned SWDTEN
: 1;
1266 unsigned WDTPS0
: 1;
1267 unsigned WDTPS1
: 1;
1268 unsigned WDTPS2
: 1;
1269 unsigned WDTPS3
: 1;
1270 unsigned WDTPS4
: 1;
1283 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1285 #define _SWDTEN 0x01
1286 #define _WDTPS0 0x02
1287 #define _WDTPS1 0x04
1288 #define _WDTPS2 0x08
1289 #define _WDTPS3 0x10
1290 #define _WDTPS4 0x20
1292 //==============================================================================
1294 extern __at(0x009B) __sfr ADRES
;
1295 extern __at(0x009B) __sfr ADRESL
;
1296 extern __at(0x009C) __sfr ADRESH
;
1298 //==============================================================================
1301 extern __at(0x009D) __sfr ADCON0
;
1308 unsigned GO_NOT_DONE
: 1;
1348 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1351 #define _GO_NOT_DONE 0x02
1361 //==============================================================================
1364 //==============================================================================
1367 extern __at(0x009E) __sfr ADCON1
;
1373 unsigned ADPREF0
: 1;
1374 unsigned ADPREF1
: 1;
1375 unsigned ADNREF
: 1;
1385 unsigned ADPREF
: 2;
1397 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1399 #define _ADPREF0 0x01
1400 #define _ADPREF1 0x02
1401 #define _ADNREF 0x04
1407 //==============================================================================
1410 //==============================================================================
1413 extern __at(0x009F) __sfr ADACT
;
1419 unsigned ADACT0
: 1;
1420 unsigned ADACT1
: 1;
1421 unsigned ADACT2
: 1;
1422 unsigned ADACT3
: 1;
1423 unsigned ADACT4
: 1;
1436 extern __at(0x009F) volatile __ADACTbits_t ADACTbits
;
1438 #define _ADACT0 0x01
1439 #define _ADACT1 0x02
1440 #define _ADACT2 0x04
1441 #define _ADACT3 0x08
1442 #define _ADACT4 0x10
1444 //==============================================================================
1447 //==============================================================================
1450 extern __at(0x010C) __sfr LATA
;
1464 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1472 //==============================================================================
1475 //==============================================================================
1478 extern __at(0x010D) __sfr LATB
;
1492 extern __at(0x010D) volatile __LATBbits_t LATBbits
;
1499 //==============================================================================
1502 //==============================================================================
1505 extern __at(0x010E) __sfr LATC
;
1519 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1530 //==============================================================================
1533 //==============================================================================
1536 extern __at(0x0111) __sfr CM1CON0
;
1540 unsigned C1SYNC
: 1;
1550 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1552 #define _C1SYNC 0x01
1559 //==============================================================================
1562 //==============================================================================
1565 extern __at(0x0112) __sfr CM1CON1
;
1571 unsigned C1NCH0
: 1;
1572 unsigned C1NCH1
: 1;
1573 unsigned C1NCH2
: 1;
1574 unsigned C1PCH0
: 1;
1575 unsigned C1PCH1
: 1;
1576 unsigned C1PCH2
: 1;
1577 unsigned C1INTN
: 1;
1578 unsigned C1INTP
: 1;
1595 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1597 #define _C1NCH0 0x01
1598 #define _C1NCH1 0x02
1599 #define _C1NCH2 0x04
1600 #define _C1PCH0 0x08
1601 #define _C1PCH1 0x10
1602 #define _C1PCH2 0x20
1603 #define _C1INTN 0x40
1604 #define _C1INTP 0x80
1606 //==============================================================================
1609 //==============================================================================
1612 extern __at(0x0113) __sfr CM2CON0
;
1616 unsigned C2SYNC
: 1;
1626 extern __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits
;
1628 #define _C2SYNC 0x01
1635 //==============================================================================
1638 //==============================================================================
1641 extern __at(0x0114) __sfr CM2CON1
;
1647 unsigned C2NCH0
: 1;
1648 unsigned C2NCH1
: 1;
1649 unsigned C2NCH2
: 1;
1650 unsigned C2PCH0
: 1;
1651 unsigned C2PCH1
: 1;
1652 unsigned C2PCH2
: 1;
1653 unsigned C2INTN
: 1;
1654 unsigned C2INTP
: 1;
1671 extern __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits
;
1673 #define _C2NCH0 0x01
1674 #define _C2NCH1 0x02
1675 #define _C2NCH2 0x04
1676 #define _C2PCH0 0x08
1677 #define _C2PCH1 0x10
1678 #define _C2PCH2 0x20
1679 #define _C2INTN 0x40
1680 #define _C2INTP 0x80
1682 //==============================================================================
1685 //==============================================================================
1688 extern __at(0x0115) __sfr CMOUT
;
1692 unsigned MC1OUT
: 1;
1693 unsigned MC2OUT
: 1;
1702 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1704 #define _MC1OUT 0x01
1705 #define _MC2OUT 0x02
1707 //==============================================================================
1710 //==============================================================================
1713 extern __at(0x0116) __sfr BORCON
;
1717 unsigned BORRDY
: 1;
1724 unsigned SBOREN
: 1;
1727 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1729 #define _BORRDY 0x01
1730 #define _SBOREN 0x80
1732 //==============================================================================
1735 //==============================================================================
1738 extern __at(0x0117) __sfr FVRCON
;
1744 unsigned ADFVR0
: 1;
1745 unsigned ADFVR1
: 1;
1746 unsigned CDAFVR0
: 1;
1747 unsigned CDAFVR1
: 1;
1750 unsigned FVRRDY
: 1;
1763 unsigned CDAFVR
: 2;
1768 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1770 #define _ADFVR0 0x01
1771 #define _ADFVR1 0x02
1772 #define _CDAFVR0 0x04
1773 #define _CDAFVR1 0x08
1776 #define _FVRRDY 0x40
1779 //==============================================================================
1782 //==============================================================================
1785 extern __at(0x0118) __sfr DACCON0
;
1791 unsigned DAC1NSS
: 1;
1793 unsigned DAC1PSS0
: 1;
1794 unsigned DAC1PSS1
: 1;
1796 unsigned DAC1OE
: 1;
1798 unsigned DAC1EN
: 1;
1804 unsigned DAC1PSS
: 2;
1809 extern __at(0x0118) volatile __DACCON0bits_t DACCON0bits
;
1811 #define _DAC1NSS 0x01
1812 #define _DAC1PSS0 0x04
1813 #define _DAC1PSS1 0x08
1814 #define _DAC1OE 0x20
1815 #define _DAC1EN 0x80
1817 //==============================================================================
1820 //==============================================================================
1823 extern __at(0x0119) __sfr DACCON1
;
1829 unsigned DAC1R0
: 1;
1830 unsigned DAC1R1
: 1;
1831 unsigned DAC1R2
: 1;
1832 unsigned DAC1R3
: 1;
1833 unsigned DAC1R4
: 1;
1846 extern __at(0x0119) volatile __DACCON1bits_t DACCON1bits
;
1848 #define _DAC1R0 0x01
1849 #define _DAC1R1 0x02
1850 #define _DAC1R2 0x04
1851 #define _DAC1R3 0x08
1852 #define _DAC1R4 0x10
1854 //==============================================================================
1857 //==============================================================================
1860 extern __at(0x018C) __sfr ANSELA
;
1874 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1882 //==============================================================================
1885 //==============================================================================
1888 extern __at(0x018D) __sfr ANSELB
;
1902 extern __at(0x018D) volatile __ANSELBbits_t ANSELBbits
;
1909 //==============================================================================
1912 //==============================================================================
1915 extern __at(0x018E) __sfr ANSELC
;
1929 extern __at(0x018E) volatile __ANSELCbits_t ANSELCbits
;
1940 //==============================================================================
1942 extern __at(0x0199) __sfr RC1REG
;
1943 extern __at(0x0199) __sfr RCREG
;
1944 extern __at(0x0199) __sfr RCREG1
;
1945 extern __at(0x019A) __sfr TX1REG
;
1946 extern __at(0x019A) __sfr TXREG
;
1947 extern __at(0x019A) __sfr TXREG1
;
1948 extern __at(0x019B) __sfr SP1BRG
;
1949 extern __at(0x019B) __sfr SP1BRGL
;
1950 extern __at(0x019B) __sfr SPBRG
;
1951 extern __at(0x019B) __sfr SPBRG1
;
1952 extern __at(0x019B) __sfr SPBRGL
;
1953 extern __at(0x019C) __sfr SP1BRGH
;
1954 extern __at(0x019C) __sfr SPBRGH
;
1955 extern __at(0x019C) __sfr SPBRGH1
;
1957 //==============================================================================
1960 extern __at(0x019D) __sfr RC1STA
;
1974 extern __at(0x019D) volatile __RC1STAbits_t RC1STAbits
;
1985 //==============================================================================
1988 //==============================================================================
1991 extern __at(0x019D) __sfr RCSTA
;
2005 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
2007 #define _RCSTA_RX9D 0x01
2008 #define _RCSTA_OERR 0x02
2009 #define _RCSTA_FERR 0x04
2010 #define _RCSTA_ADDEN 0x08
2011 #define _RCSTA_CREN 0x10
2012 #define _RCSTA_SREN 0x20
2013 #define _RCSTA_RX9 0x40
2014 #define _RCSTA_SPEN 0x80
2016 //==============================================================================
2019 //==============================================================================
2022 extern __at(0x019D) __sfr RCSTA1
;
2036 extern __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits
;
2038 #define _RCSTA1_RX9D 0x01
2039 #define _RCSTA1_OERR 0x02
2040 #define _RCSTA1_FERR 0x04
2041 #define _RCSTA1_ADDEN 0x08
2042 #define _RCSTA1_CREN 0x10
2043 #define _RCSTA1_SREN 0x20
2044 #define _RCSTA1_RX9 0x40
2045 #define _RCSTA1_SPEN 0x80
2047 //==============================================================================
2050 //==============================================================================
2053 extern __at(0x019E) __sfr TX1STA
;
2067 extern __at(0x019E) volatile __TX1STAbits_t TX1STAbits
;
2078 //==============================================================================
2081 //==============================================================================
2084 extern __at(0x019E) __sfr TXSTA
;
2098 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
2100 #define _TXSTA_TX9D 0x01
2101 #define _TXSTA_TRMT 0x02
2102 #define _TXSTA_BRGH 0x04
2103 #define _TXSTA_SENDB 0x08
2104 #define _TXSTA_SYNC 0x10
2105 #define _TXSTA_TXEN 0x20
2106 #define _TXSTA_TX9 0x40
2107 #define _TXSTA_CSRC 0x80
2109 //==============================================================================
2112 //==============================================================================
2115 extern __at(0x019E) __sfr TXSTA1
;
2129 extern __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits
;
2131 #define _TXSTA1_TX9D 0x01
2132 #define _TXSTA1_TRMT 0x02
2133 #define _TXSTA1_BRGH 0x04
2134 #define _TXSTA1_SENDB 0x08
2135 #define _TXSTA1_SYNC 0x10
2136 #define _TXSTA1_TXEN 0x20
2137 #define _TXSTA1_TX9 0x40
2138 #define _TXSTA1_CSRC 0x80
2140 //==============================================================================
2143 //==============================================================================
2146 extern __at(0x019F) __sfr BAUD1CON
;
2157 unsigned ABDOVF
: 1;
2160 extern __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits
;
2167 #define _ABDOVF 0x80
2169 //==============================================================================
2172 //==============================================================================
2175 extern __at(0x019F) __sfr BAUDCON
;
2186 unsigned ABDOVF
: 1;
2189 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
2191 #define _BAUDCON_ABDEN 0x01
2192 #define _BAUDCON_WUE 0x02
2193 #define _BAUDCON_BRG16 0x08
2194 #define _BAUDCON_SCKP 0x10
2195 #define _BAUDCON_RCIDL 0x40
2196 #define _BAUDCON_ABDOVF 0x80
2198 //==============================================================================
2201 //==============================================================================
2204 extern __at(0x019F) __sfr BAUDCON1
;
2215 unsigned ABDOVF
: 1;
2218 extern __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits
;
2220 #define _BAUDCON1_ABDEN 0x01
2221 #define _BAUDCON1_WUE 0x02
2222 #define _BAUDCON1_BRG16 0x08
2223 #define _BAUDCON1_SCKP 0x10
2224 #define _BAUDCON1_RCIDL 0x40
2225 #define _BAUDCON1_ABDOVF 0x80
2227 //==============================================================================
2230 //==============================================================================
2233 extern __at(0x019F) __sfr BAUDCTL
;
2244 unsigned ABDOVF
: 1;
2247 extern __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits
;
2249 #define _BAUDCTL_ABDEN 0x01
2250 #define _BAUDCTL_WUE 0x02
2251 #define _BAUDCTL_BRG16 0x08
2252 #define _BAUDCTL_SCKP 0x10
2253 #define _BAUDCTL_RCIDL 0x40
2254 #define _BAUDCTL_ABDOVF 0x80
2256 //==============================================================================
2259 //==============================================================================
2262 extern __at(0x019F) __sfr BAUDCTL1
;
2273 unsigned ABDOVF
: 1;
2276 extern __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits
;
2278 #define _BAUDCTL1_ABDEN 0x01
2279 #define _BAUDCTL1_WUE 0x02
2280 #define _BAUDCTL1_BRG16 0x08
2281 #define _BAUDCTL1_SCKP 0x10
2282 #define _BAUDCTL1_RCIDL 0x40
2283 #define _BAUDCTL1_ABDOVF 0x80
2285 //==============================================================================
2288 //==============================================================================
2291 extern __at(0x020C) __sfr WPUA
;
2314 extern __at(0x020C) volatile __WPUAbits_t WPUAbits
;
2323 //==============================================================================
2326 //==============================================================================
2329 extern __at(0x020D) __sfr WPUB
;
2343 extern __at(0x020D) volatile __WPUBbits_t WPUBbits
;
2350 //==============================================================================
2353 //==============================================================================
2356 extern __at(0x020E) __sfr WPUC
;
2370 extern __at(0x020E) volatile __WPUCbits_t WPUCbits
;
2381 //==============================================================================
2384 //==============================================================================
2387 extern __at(0x0211) __sfr SSP1BUF
;
2393 unsigned SSP1BUF0
: 1;
2394 unsigned SSP1BUF1
: 1;
2395 unsigned SSP1BUF2
: 1;
2396 unsigned SSP1BUF3
: 1;
2397 unsigned SSP1BUF4
: 1;
2398 unsigned SSP1BUF5
: 1;
2399 unsigned SSP1BUF6
: 1;
2400 unsigned SSP1BUF7
: 1;
2416 extern __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits
;
2418 #define _SSP1BUF0 0x01
2420 #define _SSP1BUF1 0x02
2422 #define _SSP1BUF2 0x04
2424 #define _SSP1BUF3 0x08
2426 #define _SSP1BUF4 0x10
2428 #define _SSP1BUF5 0x20
2430 #define _SSP1BUF6 0x40
2432 #define _SSP1BUF7 0x80
2435 //==============================================================================
2438 //==============================================================================
2441 extern __at(0x0211) __sfr SSPBUF
;
2447 unsigned SSP1BUF0
: 1;
2448 unsigned SSP1BUF1
: 1;
2449 unsigned SSP1BUF2
: 1;
2450 unsigned SSP1BUF3
: 1;
2451 unsigned SSP1BUF4
: 1;
2452 unsigned SSP1BUF5
: 1;
2453 unsigned SSP1BUF6
: 1;
2454 unsigned SSP1BUF7
: 1;
2470 extern __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits
;
2472 #define _SSPBUF_SSP1BUF0 0x01
2473 #define _SSPBUF_BUF0 0x01
2474 #define _SSPBUF_SSP1BUF1 0x02
2475 #define _SSPBUF_BUF1 0x02
2476 #define _SSPBUF_SSP1BUF2 0x04
2477 #define _SSPBUF_BUF2 0x04
2478 #define _SSPBUF_SSP1BUF3 0x08
2479 #define _SSPBUF_BUF3 0x08
2480 #define _SSPBUF_SSP1BUF4 0x10
2481 #define _SSPBUF_BUF4 0x10
2482 #define _SSPBUF_SSP1BUF5 0x20
2483 #define _SSPBUF_BUF5 0x20
2484 #define _SSPBUF_SSP1BUF6 0x40
2485 #define _SSPBUF_BUF6 0x40
2486 #define _SSPBUF_SSP1BUF7 0x80
2487 #define _SSPBUF_BUF7 0x80
2489 //==============================================================================
2492 //==============================================================================
2495 extern __at(0x0212) __sfr SSP1ADD
;
2501 unsigned SSP1ADD0
: 1;
2502 unsigned SSP1ADD1
: 1;
2503 unsigned SSP1ADD2
: 1;
2504 unsigned SSP1ADD3
: 1;
2505 unsigned SSP1ADD4
: 1;
2506 unsigned SSP1ADD5
: 1;
2507 unsigned SSP1ADD6
: 1;
2508 unsigned SSP1ADD7
: 1;
2524 extern __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits
;
2526 #define _SSP1ADD0 0x01
2528 #define _SSP1ADD1 0x02
2530 #define _SSP1ADD2 0x04
2532 #define _SSP1ADD3 0x08
2534 #define _SSP1ADD4 0x10
2536 #define _SSP1ADD5 0x20
2538 #define _SSP1ADD6 0x40
2540 #define _SSP1ADD7 0x80
2543 //==============================================================================
2546 //==============================================================================
2549 extern __at(0x0212) __sfr SSPADD
;
2555 unsigned SSP1ADD0
: 1;
2556 unsigned SSP1ADD1
: 1;
2557 unsigned SSP1ADD2
: 1;
2558 unsigned SSP1ADD3
: 1;
2559 unsigned SSP1ADD4
: 1;
2560 unsigned SSP1ADD5
: 1;
2561 unsigned SSP1ADD6
: 1;
2562 unsigned SSP1ADD7
: 1;
2578 extern __at(0x0212) volatile __SSPADDbits_t SSPADDbits
;
2580 #define _SSPADD_SSP1ADD0 0x01
2581 #define _SSPADD_ADD0 0x01
2582 #define _SSPADD_SSP1ADD1 0x02
2583 #define _SSPADD_ADD1 0x02
2584 #define _SSPADD_SSP1ADD2 0x04
2585 #define _SSPADD_ADD2 0x04
2586 #define _SSPADD_SSP1ADD3 0x08
2587 #define _SSPADD_ADD3 0x08
2588 #define _SSPADD_SSP1ADD4 0x10
2589 #define _SSPADD_ADD4 0x10
2590 #define _SSPADD_SSP1ADD5 0x20
2591 #define _SSPADD_ADD5 0x20
2592 #define _SSPADD_SSP1ADD6 0x40
2593 #define _SSPADD_ADD6 0x40
2594 #define _SSPADD_SSP1ADD7 0x80
2595 #define _SSPADD_ADD7 0x80
2597 //==============================================================================
2600 //==============================================================================
2603 extern __at(0x0213) __sfr SSP1MSK
;
2609 unsigned SSP1MSK0
: 1;
2610 unsigned SSP1MSK1
: 1;
2611 unsigned SSP1MSK2
: 1;
2612 unsigned SSP1MSK3
: 1;
2613 unsigned SSP1MSK4
: 1;
2614 unsigned SSP1MSK5
: 1;
2615 unsigned SSP1MSK6
: 1;
2616 unsigned SSP1MSK7
: 1;
2632 extern __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits
;
2634 #define _SSP1MSK0 0x01
2636 #define _SSP1MSK1 0x02
2638 #define _SSP1MSK2 0x04
2640 #define _SSP1MSK3 0x08
2642 #define _SSP1MSK4 0x10
2644 #define _SSP1MSK5 0x20
2646 #define _SSP1MSK6 0x40
2648 #define _SSP1MSK7 0x80
2651 //==============================================================================
2654 //==============================================================================
2657 extern __at(0x0213) __sfr SSPMSK
;
2663 unsigned SSP1MSK0
: 1;
2664 unsigned SSP1MSK1
: 1;
2665 unsigned SSP1MSK2
: 1;
2666 unsigned SSP1MSK3
: 1;
2667 unsigned SSP1MSK4
: 1;
2668 unsigned SSP1MSK5
: 1;
2669 unsigned SSP1MSK6
: 1;
2670 unsigned SSP1MSK7
: 1;
2686 extern __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits
;
2688 #define _SSPMSK_SSP1MSK0 0x01
2689 #define _SSPMSK_MSK0 0x01
2690 #define _SSPMSK_SSP1MSK1 0x02
2691 #define _SSPMSK_MSK1 0x02
2692 #define _SSPMSK_SSP1MSK2 0x04
2693 #define _SSPMSK_MSK2 0x04
2694 #define _SSPMSK_SSP1MSK3 0x08
2695 #define _SSPMSK_MSK3 0x08
2696 #define _SSPMSK_SSP1MSK4 0x10
2697 #define _SSPMSK_MSK4 0x10
2698 #define _SSPMSK_SSP1MSK5 0x20
2699 #define _SSPMSK_MSK5 0x20
2700 #define _SSPMSK_SSP1MSK6 0x40
2701 #define _SSPMSK_MSK6 0x40
2702 #define _SSPMSK_SSP1MSK7 0x80
2703 #define _SSPMSK_MSK7 0x80
2705 //==============================================================================
2708 //==============================================================================
2711 extern __at(0x0214) __sfr SSP1STAT
;
2717 unsigned R_NOT_W
: 1;
2720 unsigned D_NOT_A
: 1;
2725 extern __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits
;
2729 #define _R_NOT_W 0x04
2732 #define _D_NOT_A 0x20
2736 //==============================================================================
2739 //==============================================================================
2742 extern __at(0x0214) __sfr SSPSTAT
;
2748 unsigned R_NOT_W
: 1;
2751 unsigned D_NOT_A
: 1;
2756 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
2758 #define _SSPSTAT_BF 0x01
2759 #define _SSPSTAT_UA 0x02
2760 #define _SSPSTAT_R_NOT_W 0x04
2761 #define _SSPSTAT_S 0x08
2762 #define _SSPSTAT_P 0x10
2763 #define _SSPSTAT_D_NOT_A 0x20
2764 #define _SSPSTAT_CKE 0x40
2765 #define _SSPSTAT_SMP 0x80
2767 //==============================================================================
2770 //==============================================================================
2773 extern __at(0x0215) __sfr SSP1CON
;
2796 extern __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits
;
2807 //==============================================================================
2810 //==============================================================================
2813 extern __at(0x0215) __sfr SSP1CON1
;
2836 extern __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits
;
2838 #define _SSP1CON1_SSPM0 0x01
2839 #define _SSP1CON1_SSPM1 0x02
2840 #define _SSP1CON1_SSPM2 0x04
2841 #define _SSP1CON1_SSPM3 0x08
2842 #define _SSP1CON1_CKP 0x10
2843 #define _SSP1CON1_SSPEN 0x20
2844 #define _SSP1CON1_SSPOV 0x40
2845 #define _SSP1CON1_WCOL 0x80
2847 //==============================================================================
2850 //==============================================================================
2853 extern __at(0x0215) __sfr SSPCON
;
2876 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2878 #define _SSPCON_SSPM0 0x01
2879 #define _SSPCON_SSPM1 0x02
2880 #define _SSPCON_SSPM2 0x04
2881 #define _SSPCON_SSPM3 0x08
2882 #define _SSPCON_CKP 0x10
2883 #define _SSPCON_SSPEN 0x20
2884 #define _SSPCON_SSPOV 0x40
2885 #define _SSPCON_WCOL 0x80
2887 //==============================================================================
2890 //==============================================================================
2893 extern __at(0x0215) __sfr SSPCON1
;
2916 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2918 #define _SSPCON1_SSPM0 0x01
2919 #define _SSPCON1_SSPM1 0x02
2920 #define _SSPCON1_SSPM2 0x04
2921 #define _SSPCON1_SSPM3 0x08
2922 #define _SSPCON1_CKP 0x10
2923 #define _SSPCON1_SSPEN 0x20
2924 #define _SSPCON1_SSPOV 0x40
2925 #define _SSPCON1_WCOL 0x80
2927 //==============================================================================
2930 //==============================================================================
2933 extern __at(0x0216) __sfr SSP1CON2
;
2943 unsigned ACKSTAT
: 1;
2947 extern __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits
;
2955 #define _ACKSTAT 0x40
2958 //==============================================================================
2961 //==============================================================================
2964 extern __at(0x0216) __sfr SSPCON2
;
2974 unsigned ACKSTAT
: 1;
2978 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
2980 #define _SSPCON2_SEN 0x01
2981 #define _SSPCON2_RSEN 0x02
2982 #define _SSPCON2_PEN 0x04
2983 #define _SSPCON2_RCEN 0x08
2984 #define _SSPCON2_ACKEN 0x10
2985 #define _SSPCON2_ACKDT 0x20
2986 #define _SSPCON2_ACKSTAT 0x40
2987 #define _SSPCON2_GCEN 0x80
2989 //==============================================================================
2992 //==============================================================================
2995 extern __at(0x0217) __sfr SSP1CON3
;
3006 unsigned ACKTIM
: 1;
3009 extern __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits
;
3018 #define _ACKTIM 0x80
3020 //==============================================================================
3023 //==============================================================================
3026 extern __at(0x0217) __sfr SSPCON3
;
3037 unsigned ACKTIM
: 1;
3040 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
3042 #define _SSPCON3_DHEN 0x01
3043 #define _SSPCON3_AHEN 0x02
3044 #define _SSPCON3_SBCDE 0x04
3045 #define _SSPCON3_SDAHT 0x08
3046 #define _SSPCON3_BOEN 0x10
3047 #define _SSPCON3_SCIE 0x20
3048 #define _SSPCON3_PCIE 0x40
3049 #define _SSPCON3_ACKTIM 0x80
3051 //==============================================================================
3054 //==============================================================================
3057 extern __at(0x0219) __sfr SSP2BUF
;
3063 unsigned SSP2BUF0
: 1;
3064 unsigned SSP2BUF1
: 1;
3065 unsigned SSP2BUF2
: 1;
3066 unsigned SSP2BUF3
: 1;
3067 unsigned SSP2BUF4
: 1;
3068 unsigned SSP2BUF5
: 1;
3069 unsigned SSP2BUF6
: 1;
3070 unsigned SSP2BUF7
: 1;
3086 extern __at(0x0219) volatile __SSP2BUFbits_t SSP2BUFbits
;
3088 #define _SSP2BUF_SSP2BUF0 0x01
3089 #define _SSP2BUF_BUF0 0x01
3090 #define _SSP2BUF_SSP2BUF1 0x02
3091 #define _SSP2BUF_BUF1 0x02
3092 #define _SSP2BUF_SSP2BUF2 0x04
3093 #define _SSP2BUF_BUF2 0x04
3094 #define _SSP2BUF_SSP2BUF3 0x08
3095 #define _SSP2BUF_BUF3 0x08
3096 #define _SSP2BUF_SSP2BUF4 0x10
3097 #define _SSP2BUF_BUF4 0x10
3098 #define _SSP2BUF_SSP2BUF5 0x20
3099 #define _SSP2BUF_BUF5 0x20
3100 #define _SSP2BUF_SSP2BUF6 0x40
3101 #define _SSP2BUF_BUF6 0x40
3102 #define _SSP2BUF_SSP2BUF7 0x80
3103 #define _SSP2BUF_BUF7 0x80
3105 //==============================================================================
3108 //==============================================================================
3111 extern __at(0x021A) __sfr SSP2ADD
;
3117 unsigned SSP2ADD0
: 1;
3118 unsigned SSP2ADD1
: 1;
3119 unsigned SSP2ADD2
: 1;
3120 unsigned SSP2ADD3
: 1;
3121 unsigned SSP2ADD4
: 1;
3122 unsigned SSP2ADD5
: 1;
3123 unsigned SSP2ADD6
: 1;
3124 unsigned SSP2ADD7
: 1;
3140 extern __at(0x021A) volatile __SSP2ADDbits_t SSP2ADDbits
;
3142 #define _SSP2ADD_SSP2ADD0 0x01
3143 #define _SSP2ADD_ADD0 0x01
3144 #define _SSP2ADD_SSP2ADD1 0x02
3145 #define _SSP2ADD_ADD1 0x02
3146 #define _SSP2ADD_SSP2ADD2 0x04
3147 #define _SSP2ADD_ADD2 0x04
3148 #define _SSP2ADD_SSP2ADD3 0x08
3149 #define _SSP2ADD_ADD3 0x08
3150 #define _SSP2ADD_SSP2ADD4 0x10
3151 #define _SSP2ADD_ADD4 0x10
3152 #define _SSP2ADD_SSP2ADD5 0x20
3153 #define _SSP2ADD_ADD5 0x20
3154 #define _SSP2ADD_SSP2ADD6 0x40
3155 #define _SSP2ADD_ADD6 0x40
3156 #define _SSP2ADD_SSP2ADD7 0x80
3157 #define _SSP2ADD_ADD7 0x80
3159 //==============================================================================
3162 //==============================================================================
3165 extern __at(0x021B) __sfr SSP2MSK
;
3171 unsigned SSP2MSK0
: 1;
3172 unsigned SSP2MSK1
: 1;
3173 unsigned SSP2MSK2
: 1;
3174 unsigned SSP2MSK3
: 1;
3175 unsigned SSP2MSK4
: 1;
3176 unsigned SSP2MSK5
: 1;
3177 unsigned SSP2MSK6
: 1;
3178 unsigned SSP2MSK7
: 1;
3194 extern __at(0x021B) volatile __SSP2MSKbits_t SSP2MSKbits
;
3196 #define _SSP2MSK_SSP2MSK0 0x01
3197 #define _SSP2MSK_MSK0 0x01
3198 #define _SSP2MSK_SSP2MSK1 0x02
3199 #define _SSP2MSK_MSK1 0x02
3200 #define _SSP2MSK_SSP2MSK2 0x04
3201 #define _SSP2MSK_MSK2 0x04
3202 #define _SSP2MSK_SSP2MSK3 0x08
3203 #define _SSP2MSK_MSK3 0x08
3204 #define _SSP2MSK_SSP2MSK4 0x10
3205 #define _SSP2MSK_MSK4 0x10
3206 #define _SSP2MSK_SSP2MSK5 0x20
3207 #define _SSP2MSK_MSK5 0x20
3208 #define _SSP2MSK_SSP2MSK6 0x40
3209 #define _SSP2MSK_MSK6 0x40
3210 #define _SSP2MSK_SSP2MSK7 0x80
3211 #define _SSP2MSK_MSK7 0x80
3213 //==============================================================================
3216 //==============================================================================
3219 extern __at(0x021C) __sfr SSP2STAT
;
3225 unsigned R_NOT_W
: 1;
3228 unsigned D_NOT_A
: 1;
3233 extern __at(0x021C) volatile __SSP2STATbits_t SSP2STATbits
;
3235 #define _SSP2STAT_BF 0x01
3236 #define _SSP2STAT_UA 0x02
3237 #define _SSP2STAT_R_NOT_W 0x04
3238 #define _SSP2STAT_S 0x08
3239 #define _SSP2STAT_P 0x10
3240 #define _SSP2STAT_D_NOT_A 0x20
3241 #define _SSP2STAT_CKE 0x40
3242 #define _SSP2STAT_SMP 0x80
3244 //==============================================================================
3247 //==============================================================================
3250 extern __at(0x021D) __sfr SSP2CON
;
3273 extern __at(0x021D) volatile __SSP2CONbits_t SSP2CONbits
;
3275 #define _SSP2CON_SSPM0 0x01
3276 #define _SSP2CON_SSPM1 0x02
3277 #define _SSP2CON_SSPM2 0x04
3278 #define _SSP2CON_SSPM3 0x08
3279 #define _SSP2CON_CKP 0x10
3280 #define _SSP2CON_SSPEN 0x20
3281 #define _SSP2CON_SSPOV 0x40
3282 #define _SSP2CON_WCOL 0x80
3284 //==============================================================================
3287 //==============================================================================
3290 extern __at(0x021D) __sfr SSP2CON1
;
3313 extern __at(0x021D) volatile __SSP2CON1bits_t SSP2CON1bits
;
3315 #define _SSP2CON1_SSPM0 0x01
3316 #define _SSP2CON1_SSPM1 0x02
3317 #define _SSP2CON1_SSPM2 0x04
3318 #define _SSP2CON1_SSPM3 0x08
3319 #define _SSP2CON1_CKP 0x10
3320 #define _SSP2CON1_SSPEN 0x20
3321 #define _SSP2CON1_SSPOV 0x40
3322 #define _SSP2CON1_WCOL 0x80
3324 //==============================================================================
3327 //==============================================================================
3330 extern __at(0x021E) __sfr SSP2CON2
;
3340 unsigned ACKSTAT
: 1;
3344 extern __at(0x021E) volatile __SSP2CON2bits_t SSP2CON2bits
;
3346 #define _SSP2CON2_SEN 0x01
3347 #define _SSP2CON2_RSEN 0x02
3348 #define _SSP2CON2_PEN 0x04
3349 #define _SSP2CON2_RCEN 0x08
3350 #define _SSP2CON2_ACKEN 0x10
3351 #define _SSP2CON2_ACKDT 0x20
3352 #define _SSP2CON2_ACKSTAT 0x40
3353 #define _SSP2CON2_GCEN 0x80
3355 //==============================================================================
3358 //==============================================================================
3361 extern __at(0x021F) __sfr SSP2CON3
;
3372 unsigned ACKTIM
: 1;
3375 extern __at(0x021F) volatile __SSP2CON3bits_t SSP2CON3bits
;
3377 #define _SSP2CON3_DHEN 0x01
3378 #define _SSP2CON3_AHEN 0x02
3379 #define _SSP2CON3_SBCDE 0x04
3380 #define _SSP2CON3_SDAHT 0x08
3381 #define _SSP2CON3_BOEN 0x10
3382 #define _SSP2CON3_SCIE 0x20
3383 #define _SSP2CON3_PCIE 0x40
3384 #define _SSP2CON3_ACKTIM 0x80
3386 //==============================================================================
3389 //==============================================================================
3392 extern __at(0x028C) __sfr ODCONA
;
3406 extern __at(0x028C) volatile __ODCONAbits_t ODCONAbits
;
3414 //==============================================================================
3417 //==============================================================================
3420 extern __at(0x028D) __sfr ODCONB
;
3434 extern __at(0x028D) volatile __ODCONBbits_t ODCONBbits
;
3441 //==============================================================================
3444 //==============================================================================
3447 extern __at(0x028E) __sfr ODCONC
;
3461 extern __at(0x028E) volatile __ODCONCbits_t ODCONCbits
;
3472 //==============================================================================
3474 extern __at(0x0291) __sfr CCPR1
;
3475 extern __at(0x0291) __sfr CCPR1L
;
3476 extern __at(0x0292) __sfr CCPR1H
;
3478 //==============================================================================
3481 extern __at(0x0293) __sfr CCP1CON
;
3487 unsigned CCP1MODE0
: 1;
3488 unsigned CCP1MODE1
: 1;
3489 unsigned CCP1MODE2
: 1;
3490 unsigned CCP1MODE3
: 1;
3491 unsigned CCP1FMT
: 1;
3492 unsigned CCP1OUT
: 1;
3494 unsigned CCP1EN
: 1;
3499 unsigned CCP1MODE
: 4;
3504 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
3506 #define _CCP1MODE0 0x01
3507 #define _CCP1MODE1 0x02
3508 #define _CCP1MODE2 0x04
3509 #define _CCP1MODE3 0x08
3510 #define _CCP1FMT 0x10
3511 #define _CCP1OUT 0x20
3512 #define _CCP1EN 0x80
3514 //==============================================================================
3517 //==============================================================================
3520 extern __at(0x0294) __sfr CCP1CAP
;
3526 unsigned CCP1CTS0
: 1;
3527 unsigned CCP1CTS1
: 1;
3528 unsigned CCP1CTS2
: 1;
3529 unsigned CCP1CTS3
: 1;
3538 unsigned CCP1CTS
: 4;
3543 extern __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits
;
3545 #define _CCP1CTS0 0x01
3546 #define _CCP1CTS1 0x02
3547 #define _CCP1CTS2 0x04
3548 #define _CCP1CTS3 0x08
3550 //==============================================================================
3552 extern __at(0x0295) __sfr CCPR2
;
3553 extern __at(0x0295) __sfr CCPR2L
;
3554 extern __at(0x0296) __sfr CCPR2H
;
3556 //==============================================================================
3559 extern __at(0x0297) __sfr CCP2CON
;
3565 unsigned CCP2MODE0
: 1;
3566 unsigned CCP2MODE1
: 1;
3567 unsigned CCP2MODE2
: 1;
3568 unsigned CCP2MODE3
: 1;
3569 unsigned CCP2FMT
: 1;
3570 unsigned CCP2OUT
: 1;
3572 unsigned CCP2EN
: 1;
3577 unsigned CCP2MODE
: 4;
3582 extern __at(0x0297) volatile __CCP2CONbits_t CCP2CONbits
;
3584 #define _CCP2MODE0 0x01
3585 #define _CCP2MODE1 0x02
3586 #define _CCP2MODE2 0x04
3587 #define _CCP2MODE3 0x08
3588 #define _CCP2FMT 0x10
3589 #define _CCP2OUT 0x20
3590 #define _CCP2EN 0x80
3592 //==============================================================================
3595 //==============================================================================
3598 extern __at(0x0298) __sfr CCP2CAP
;
3604 unsigned CCP2CTS0
: 1;
3605 unsigned CCP2CTS1
: 1;
3606 unsigned CCP2CTS2
: 1;
3607 unsigned CCP2CTS3
: 1;
3616 unsigned CCP2CTS
: 4;
3621 extern __at(0x0298) volatile __CCP2CAPbits_t CCP2CAPbits
;
3623 #define _CCP2CTS0 0x01
3624 #define _CCP2CTS1 0x02
3625 #define _CCP2CTS2 0x04
3626 #define _CCP2CTS3 0x08
3628 //==============================================================================
3631 //==============================================================================
3634 extern __at(0x029F) __sfr CCPTMRS
;
3640 unsigned C1TSEL0
: 1;
3641 unsigned C1TSEL1
: 1;
3642 unsigned C2TSEL0
: 1;
3643 unsigned C2TSEL1
: 1;
3644 unsigned C3TSEL0
: 1;
3645 unsigned C3TSEL1
: 1;
3646 unsigned C4TSEL0
: 1;
3647 unsigned C4TSEL1
: 1;
3652 unsigned C1TSEL
: 2;
3659 unsigned C2TSEL
: 2;
3666 unsigned C3TSEL
: 2;
3673 unsigned C4TSEL
: 2;
3677 extern __at(0x029F) volatile __CCPTMRSbits_t CCPTMRSbits
;
3679 #define _C1TSEL0 0x01
3680 #define _C1TSEL1 0x02
3681 #define _C2TSEL0 0x04
3682 #define _C2TSEL1 0x08
3683 #define _C3TSEL0 0x10
3684 #define _C3TSEL1 0x20
3685 #define _C4TSEL0 0x40
3686 #define _C4TSEL1 0x80
3688 //==============================================================================
3691 //==============================================================================
3694 extern __at(0x030C) __sfr SLRCONA
;
3708 extern __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits
;
3716 //==============================================================================
3719 //==============================================================================
3722 extern __at(0x030D) __sfr SLRCONB
;
3736 extern __at(0x030D) volatile __SLRCONBbits_t SLRCONBbits
;
3743 //==============================================================================
3746 //==============================================================================
3749 extern __at(0x030E) __sfr SLRCONC
;
3763 extern __at(0x030E) volatile __SLRCONCbits_t SLRCONCbits
;
3774 //==============================================================================
3776 extern __at(0x0311) __sfr CCPR3
;
3777 extern __at(0x0311) __sfr CCPR3L
;
3778 extern __at(0x0312) __sfr CCPR3H
;
3780 //==============================================================================
3783 extern __at(0x0313) __sfr CCP3CON
;
3789 unsigned CCP3MODE0
: 1;
3790 unsigned CCP3MODE1
: 1;
3791 unsigned CCP3MODE2
: 1;
3792 unsigned CCP3MODE3
: 1;
3793 unsigned CCP3FMT
: 1;
3794 unsigned CCP3OUT
: 1;
3796 unsigned CCP3EN
: 1;
3801 unsigned CCP3MODE
: 4;
3806 extern __at(0x0313) volatile __CCP3CONbits_t CCP3CONbits
;
3808 #define _CCP3MODE0 0x01
3809 #define _CCP3MODE1 0x02
3810 #define _CCP3MODE2 0x04
3811 #define _CCP3MODE3 0x08
3812 #define _CCP3FMT 0x10
3813 #define _CCP3OUT 0x20
3814 #define _CCP3EN 0x80
3816 //==============================================================================
3819 //==============================================================================
3822 extern __at(0x0314) __sfr CCP3CAP
;
3828 unsigned CCP3CTS0
: 1;
3829 unsigned CCP3CTS1
: 1;
3830 unsigned CCP3CTS2
: 1;
3831 unsigned CCP3CTS3
: 1;
3840 unsigned CCP3CTS
: 4;
3845 extern __at(0x0314) volatile __CCP3CAPbits_t CCP3CAPbits
;
3847 #define _CCP3CTS0 0x01
3848 #define _CCP3CTS1 0x02
3849 #define _CCP3CTS2 0x04
3850 #define _CCP3CTS3 0x08
3852 //==============================================================================
3854 extern __at(0x0315) __sfr CCPR4
;
3855 extern __at(0x0315) __sfr CCPR4L
;
3856 extern __at(0x0316) __sfr CCPR4H
;
3858 //==============================================================================
3861 extern __at(0x0317) __sfr CCP4CON
;
3867 unsigned CCP4MODE0
: 1;
3868 unsigned CCP4MODE1
: 1;
3869 unsigned CCP4MODE2
: 1;
3870 unsigned CCP4MODE3
: 1;
3871 unsigned CCP4FMT
: 1;
3872 unsigned CCP4OUT
: 1;
3874 unsigned CCP4EN
: 1;
3879 unsigned CCP4MODE
: 4;
3884 extern __at(0x0317) volatile __CCP4CONbits_t CCP4CONbits
;
3886 #define _CCP4MODE0 0x01
3887 #define _CCP4MODE1 0x02
3888 #define _CCP4MODE2 0x04
3889 #define _CCP4MODE3 0x08
3890 #define _CCP4FMT 0x10
3891 #define _CCP4OUT 0x20
3892 #define _CCP4EN 0x80
3894 //==============================================================================
3897 //==============================================================================
3900 extern __at(0x0318) __sfr CCP4CAP
;
3906 unsigned CCP4CTS0
: 1;
3907 unsigned CCP4CTS1
: 1;
3908 unsigned CCP4CTS2
: 1;
3909 unsigned CCP4CTS3
: 1;
3918 unsigned CCP4CTS
: 4;
3923 extern __at(0x0318) volatile __CCP4CAPbits_t CCP4CAPbits
;
3925 #define _CCP4CTS0 0x01
3926 #define _CCP4CTS1 0x02
3927 #define _CCP4CTS2 0x04
3928 #define _CCP4CTS3 0x08
3930 //==============================================================================
3933 //==============================================================================
3936 extern __at(0x038C) __sfr INLVLA
;
3942 unsigned INLVLA0
: 1;
3943 unsigned INLVLA1
: 1;
3944 unsigned INLVLA2
: 1;
3945 unsigned INLVLA3
: 1;
3946 unsigned INLVLA4
: 1;
3947 unsigned INLVLA5
: 1;
3954 unsigned INLVLA
: 6;
3959 extern __at(0x038C) volatile __INLVLAbits_t INLVLAbits
;
3961 #define _INLVLA0 0x01
3962 #define _INLVLA1 0x02
3963 #define _INLVLA2 0x04
3964 #define _INLVLA3 0x08
3965 #define _INLVLA4 0x10
3966 #define _INLVLA5 0x20
3968 //==============================================================================
3971 //==============================================================================
3974 extern __at(0x038D) __sfr INLVLB
;
3982 unsigned INLVLB4
: 1;
3983 unsigned INLVLB5
: 1;
3984 unsigned INLVLB6
: 1;
3985 unsigned INLVLB7
: 1;
3988 extern __at(0x038D) volatile __INLVLBbits_t INLVLBbits
;
3990 #define _INLVLB4 0x10
3991 #define _INLVLB5 0x20
3992 #define _INLVLB6 0x40
3993 #define _INLVLB7 0x80
3995 //==============================================================================
3998 //==============================================================================
4001 extern __at(0x038E) __sfr INLVLC
;
4005 unsigned INLVLC0
: 1;
4006 unsigned INLVLC1
: 1;
4007 unsigned INLVLC2
: 1;
4008 unsigned INLVLC3
: 1;
4009 unsigned INLVLC4
: 1;
4010 unsigned INLVLC5
: 1;
4011 unsigned INLVLC6
: 1;
4012 unsigned INLVLC7
: 1;
4015 extern __at(0x038E) volatile __INLVLCbits_t INLVLCbits
;
4017 #define _INLVLC0 0x01
4018 #define _INLVLC1 0x02
4019 #define _INLVLC2 0x04
4020 #define _INLVLC3 0x08
4021 #define _INLVLC4 0x10
4022 #define _INLVLC5 0x20
4023 #define _INLVLC6 0x40
4024 #define _INLVLC7 0x80
4026 //==============================================================================
4029 //==============================================================================
4032 extern __at(0x0391) __sfr IOCAP
;
4038 unsigned IOCAP0
: 1;
4039 unsigned IOCAP1
: 1;
4040 unsigned IOCAP2
: 1;
4041 unsigned IOCAP3
: 1;
4042 unsigned IOCAP4
: 1;
4043 unsigned IOCAP5
: 1;
4055 extern __at(0x0391) volatile __IOCAPbits_t IOCAPbits
;
4057 #define _IOCAP0 0x01
4058 #define _IOCAP1 0x02
4059 #define _IOCAP2 0x04
4060 #define _IOCAP3 0x08
4061 #define _IOCAP4 0x10
4062 #define _IOCAP5 0x20
4064 //==============================================================================
4067 //==============================================================================
4070 extern __at(0x0392) __sfr IOCAN
;
4076 unsigned IOCAN0
: 1;
4077 unsigned IOCAN1
: 1;
4078 unsigned IOCAN2
: 1;
4079 unsigned IOCAN3
: 1;
4080 unsigned IOCAN4
: 1;
4081 unsigned IOCAN5
: 1;
4093 extern __at(0x0392) volatile __IOCANbits_t IOCANbits
;
4095 #define _IOCAN0 0x01
4096 #define _IOCAN1 0x02
4097 #define _IOCAN2 0x04
4098 #define _IOCAN3 0x08
4099 #define _IOCAN4 0x10
4100 #define _IOCAN5 0x20
4102 //==============================================================================
4105 //==============================================================================
4108 extern __at(0x0393) __sfr IOCAF
;
4114 unsigned IOCAF0
: 1;
4115 unsigned IOCAF1
: 1;
4116 unsigned IOCAF2
: 1;
4117 unsigned IOCAF3
: 1;
4118 unsigned IOCAF4
: 1;
4119 unsigned IOCAF5
: 1;
4131 extern __at(0x0393) volatile __IOCAFbits_t IOCAFbits
;
4133 #define _IOCAF0 0x01
4134 #define _IOCAF1 0x02
4135 #define _IOCAF2 0x04
4136 #define _IOCAF3 0x08
4137 #define _IOCAF4 0x10
4138 #define _IOCAF5 0x20
4140 //==============================================================================
4143 //==============================================================================
4146 extern __at(0x0394) __sfr IOCBP
;
4154 unsigned IOCBP4
: 1;
4155 unsigned IOCBP5
: 1;
4156 unsigned IOCBP6
: 1;
4157 unsigned IOCBP7
: 1;
4160 extern __at(0x0394) volatile __IOCBPbits_t IOCBPbits
;
4162 #define _IOCBP4 0x10
4163 #define _IOCBP5 0x20
4164 #define _IOCBP6 0x40
4165 #define _IOCBP7 0x80
4167 //==============================================================================
4170 //==============================================================================
4173 extern __at(0x0395) __sfr IOCBN
;
4181 unsigned IOCBN4
: 1;
4182 unsigned IOCBN5
: 1;
4183 unsigned IOCBN6
: 1;
4184 unsigned IOCBN7
: 1;
4187 extern __at(0x0395) volatile __IOCBNbits_t IOCBNbits
;
4189 #define _IOCBN4 0x10
4190 #define _IOCBN5 0x20
4191 #define _IOCBN6 0x40
4192 #define _IOCBN7 0x80
4194 //==============================================================================
4197 //==============================================================================
4200 extern __at(0x0396) __sfr IOCBF
;
4208 unsigned IOCBF4
: 1;
4209 unsigned IOCBF5
: 1;
4210 unsigned IOCBF6
: 1;
4211 unsigned IOCBF7
: 1;
4214 extern __at(0x0396) volatile __IOCBFbits_t IOCBFbits
;
4216 #define _IOCBF4 0x10
4217 #define _IOCBF5 0x20
4218 #define _IOCBF6 0x40
4219 #define _IOCBF7 0x80
4221 //==============================================================================
4224 //==============================================================================
4227 extern __at(0x0397) __sfr IOCCP
;
4231 unsigned IOCCP0
: 1;
4232 unsigned IOCCP1
: 1;
4233 unsigned IOCCP2
: 1;
4234 unsigned IOCCP3
: 1;
4235 unsigned IOCCP4
: 1;
4236 unsigned IOCCP5
: 1;
4237 unsigned IOCCP6
: 1;
4238 unsigned IOCCP7
: 1;
4241 extern __at(0x0397) volatile __IOCCPbits_t IOCCPbits
;
4243 #define _IOCCP0 0x01
4244 #define _IOCCP1 0x02
4245 #define _IOCCP2 0x04
4246 #define _IOCCP3 0x08
4247 #define _IOCCP4 0x10
4248 #define _IOCCP5 0x20
4249 #define _IOCCP6 0x40
4250 #define _IOCCP7 0x80
4252 //==============================================================================
4255 //==============================================================================
4258 extern __at(0x0398) __sfr IOCCN
;
4262 unsigned IOCCN0
: 1;
4263 unsigned IOCCN1
: 1;
4264 unsigned IOCCN2
: 1;
4265 unsigned IOCCN3
: 1;
4266 unsigned IOCCN4
: 1;
4267 unsigned IOCCN5
: 1;
4268 unsigned IOCCN6
: 1;
4269 unsigned IOCCN7
: 1;
4272 extern __at(0x0398) volatile __IOCCNbits_t IOCCNbits
;
4274 #define _IOCCN0 0x01
4275 #define _IOCCN1 0x02
4276 #define _IOCCN2 0x04
4277 #define _IOCCN3 0x08
4278 #define _IOCCN4 0x10
4279 #define _IOCCN5 0x20
4280 #define _IOCCN6 0x40
4281 #define _IOCCN7 0x80
4283 //==============================================================================
4286 //==============================================================================
4289 extern __at(0x0399) __sfr IOCCF
;
4293 unsigned IOCCF0
: 1;
4294 unsigned IOCCF1
: 1;
4295 unsigned IOCCF2
: 1;
4296 unsigned IOCCF3
: 1;
4297 unsigned IOCCF4
: 1;
4298 unsigned IOCCF5
: 1;
4299 unsigned IOCCF6
: 1;
4300 unsigned IOCCF7
: 1;
4303 extern __at(0x0399) volatile __IOCCFbits_t IOCCFbits
;
4305 #define _IOCCF0 0x01
4306 #define _IOCCF1 0x02
4307 #define _IOCCF2 0x04
4308 #define _IOCCF3 0x08
4309 #define _IOCCF4 0x10
4310 #define _IOCCF5 0x20
4311 #define _IOCCF6 0x40
4312 #define _IOCCF7 0x80
4314 //==============================================================================
4317 //==============================================================================
4320 extern __at(0x039A) __sfr CLKRCON
;
4326 unsigned CLKRDIV0
: 1;
4327 unsigned CLKRDIV1
: 1;
4328 unsigned CLKRDIV2
: 1;
4329 unsigned CLKRDC0
: 1;
4330 unsigned CLKRDC1
: 1;
4333 unsigned CLKREN
: 1;
4338 unsigned CLKRDIV
: 3;
4345 unsigned CLKRDC
: 2;
4350 extern __at(0x039A) volatile __CLKRCONbits_t CLKRCONbits
;
4352 #define _CLKRDIV0 0x01
4353 #define _CLKRDIV1 0x02
4354 #define _CLKRDIV2 0x04
4355 #define _CLKRDC0 0x08
4356 #define _CLKRDC1 0x10
4357 #define _CLKREN 0x80
4359 //==============================================================================
4362 //==============================================================================
4365 extern __at(0x039C) __sfr MDCON
;
4373 unsigned MDOPOL
: 1;
4379 extern __at(0x039C) volatile __MDCONbits_t MDCONbits
;
4383 #define _MDOPOL 0x10
4386 //==============================================================================
4389 //==============================================================================
4392 extern __at(0x039D) __sfr MDSRC
;
4415 extern __at(0x039D) volatile __MDSRCbits_t MDSRCbits
;
4422 //==============================================================================
4425 //==============================================================================
4428 extern __at(0x039E) __sfr MDCARH
;
4439 unsigned MDCHSYNC
: 1;
4440 unsigned MDCHPOL
: 1;
4451 extern __at(0x039E) volatile __MDCARHbits_t MDCARHbits
;
4457 #define _MDCHSYNC 0x20
4458 #define _MDCHPOL 0x40
4460 //==============================================================================
4463 //==============================================================================
4466 extern __at(0x039F) __sfr MDCARL
;
4477 unsigned MDCLSYNC
: 1;
4478 unsigned MDCLPOL
: 1;
4489 extern __at(0x039F) volatile __MDCARLbits_t MDCARLbits
;
4495 #define _MDCLSYNC 0x20
4496 #define _MDCLPOL 0x40
4498 //==============================================================================
4501 //==============================================================================
4504 extern __at(0x040C) __sfr CCDNA
;
4508 unsigned CCDNA0
: 1;
4509 unsigned CCDNA1
: 1;
4510 unsigned CCDNA2
: 1;
4512 unsigned CCDNA4
: 1;
4513 unsigned CCDNA5
: 1;
4518 extern __at(0x040C) volatile __CCDNAbits_t CCDNAbits
;
4520 #define _CCDNA0 0x01
4521 #define _CCDNA1 0x02
4522 #define _CCDNA2 0x04
4523 #define _CCDNA4 0x10
4524 #define _CCDNA5 0x20
4526 //==============================================================================
4529 //==============================================================================
4532 extern __at(0x040D) __sfr CCDNB
;
4540 unsigned CCDNB4
: 1;
4541 unsigned CCDNB5
: 1;
4542 unsigned CCDNB6
: 1;
4543 unsigned CCDNB7
: 1;
4546 extern __at(0x040D) volatile __CCDNBbits_t CCDNBbits
;
4548 #define _CCDNB4 0x10
4549 #define _CCDNB5 0x20
4550 #define _CCDNB6 0x40
4551 #define _CCDNB7 0x80
4553 //==============================================================================
4556 //==============================================================================
4559 extern __at(0x040E) __sfr CCDNC
;
4563 unsigned CCDNC0
: 1;
4564 unsigned CCDNC1
: 1;
4565 unsigned CCDNC2
: 1;
4566 unsigned CCDNC3
: 1;
4567 unsigned CCDNC4
: 1;
4568 unsigned CCDNC5
: 1;
4569 unsigned CCDNC6
: 1;
4570 unsigned CCDNC7
: 1;
4573 extern __at(0x040E) volatile __CCDNCbits_t CCDNCbits
;
4575 #define _CCDNC0 0x01
4576 #define _CCDNC1 0x02
4577 #define _CCDNC2 0x04
4578 #define _CCDNC3 0x08
4579 #define _CCDNC4 0x10
4580 #define _CCDNC5 0x20
4581 #define _CCDNC6 0x40
4582 #define _CCDNC7 0x80
4584 //==============================================================================
4586 extern __at(0x0411) __sfr TMR3
;
4587 extern __at(0x0411) __sfr TMR3L
;
4588 extern __at(0x0412) __sfr TMR3H
;
4590 //==============================================================================
4593 extern __at(0x0413) __sfr T3CON
;
4599 unsigned TMR3ON
: 1;
4601 unsigned T3SYNC
: 1;
4602 unsigned T3SOSC
: 1;
4603 unsigned T3CKPS0
: 1;
4604 unsigned T3CKPS1
: 1;
4605 unsigned TMR3CS0
: 1;
4606 unsigned TMR3CS1
: 1;
4612 unsigned T3CKPS
: 2;
4619 unsigned TMR3CS
: 2;
4623 extern __at(0x0413) volatile __T3CONbits_t T3CONbits
;
4625 #define _TMR3ON 0x01
4626 #define _T3SYNC 0x04
4627 #define _T3SOSC 0x08
4628 #define _T3CKPS0 0x10
4629 #define _T3CKPS1 0x20
4630 #define _TMR3CS0 0x40
4631 #define _TMR3CS1 0x80
4633 //==============================================================================
4636 //==============================================================================
4639 extern __at(0x0414) __sfr T3GCON
;
4645 unsigned T3GSS0
: 1;
4646 unsigned T3GSS1
: 1;
4647 unsigned T3GVAL
: 1;
4648 unsigned T3GGO_NOT_DONE
: 1;
4649 unsigned T3GSPM
: 1;
4651 unsigned T3GPOL
: 1;
4652 unsigned TMR3GE
: 1;
4662 extern __at(0x0414) volatile __T3GCONbits_t T3GCONbits
;
4664 #define _T3GSS0 0x01
4665 #define _T3GSS1 0x02
4666 #define _T3GVAL 0x04
4667 #define _T3GGO_NOT_DONE 0x08
4668 #define _T3GSPM 0x10
4670 #define _T3GPOL 0x40
4671 #define _TMR3GE 0x80
4673 //==============================================================================
4675 extern __at(0x0415) __sfr TMR4
;
4676 extern __at(0x0416) __sfr PR4
;
4678 //==============================================================================
4681 extern __at(0x0417) __sfr T4CON
;
4687 unsigned T3CKPS0
: 1;
4688 unsigned T3CKPS1
: 1;
4689 unsigned TMR4ON
: 1;
4690 unsigned TOUTPS0
: 1;
4691 unsigned TOUTPS1
: 1;
4692 unsigned TOUTPS2
: 1;
4693 unsigned TOUTPS3
: 1;
4699 unsigned T3CKPS
: 2;
4706 unsigned TOUTPS
: 4;
4711 extern __at(0x0417) volatile __T4CONbits_t T4CONbits
;
4713 #define _T4CON_T3CKPS0 0x01
4714 #define _T4CON_T3CKPS1 0x02
4715 #define _T4CON_TMR4ON 0x04
4716 #define _T4CON_TOUTPS0 0x08
4717 #define _T4CON_TOUTPS1 0x10
4718 #define _T4CON_TOUTPS2 0x20
4719 #define _T4CON_TOUTPS3 0x40
4721 //==============================================================================
4723 extern __at(0x0418) __sfr TMR5
;
4724 extern __at(0x0418) __sfr TMR5L
;
4725 extern __at(0x0419) __sfr TMR5H
;
4727 //==============================================================================
4730 extern __at(0x041A) __sfr T5CON
;
4736 unsigned TMR5ON
: 1;
4738 unsigned T5SYNC
: 1;
4739 unsigned T5SOSC
: 1;
4740 unsigned T5CKPS0
: 1;
4741 unsigned T5CKPS1
: 1;
4742 unsigned TMR5CS0
: 1;
4743 unsigned TMR5CS1
: 1;
4749 unsigned T5CKPS
: 2;
4756 unsigned TMR5CS
: 2;
4760 extern __at(0x041A) volatile __T5CONbits_t T5CONbits
;
4762 #define _TMR5ON 0x01
4763 #define _T5SYNC 0x04
4764 #define _T5SOSC 0x08
4765 #define _T5CKPS0 0x10
4766 #define _T5CKPS1 0x20
4767 #define _TMR5CS0 0x40
4768 #define _TMR5CS1 0x80
4770 //==============================================================================
4773 //==============================================================================
4776 extern __at(0x041B) __sfr T5GCON
;
4782 unsigned T5GSS0
: 1;
4783 unsigned T5GSS1
: 1;
4784 unsigned T5GVAL
: 1;
4785 unsigned T5GGO_NOT_DONE
: 1;
4786 unsigned T5GSPM
: 1;
4788 unsigned T5GPOL
: 1;
4789 unsigned TMR5GE
: 1;
4799 extern __at(0x041B) volatile __T5GCONbits_t T5GCONbits
;
4801 #define _T5GSS0 0x01
4802 #define _T5GSS1 0x02
4803 #define _T5GVAL 0x04
4804 #define _T5GGO_NOT_DONE 0x08
4805 #define _T5GSPM 0x10
4807 #define _T5GPOL 0x40
4808 #define _TMR5GE 0x80
4810 //==============================================================================
4812 extern __at(0x041C) __sfr TMR6
;
4813 extern __at(0x041D) __sfr PR6
;
4815 //==============================================================================
4818 extern __at(0x041E) __sfr T6CON
;
4824 unsigned T6CKPS0
: 1;
4825 unsigned T6CKPS1
: 1;
4826 unsigned TMR6ON
: 1;
4827 unsigned TOUTPS0
: 1;
4828 unsigned TOUTPS1
: 1;
4829 unsigned TOUTPS2
: 1;
4830 unsigned TOUTPS3
: 1;
4836 unsigned T6CKPS
: 2;
4843 unsigned TOUTPS
: 4;
4848 extern __at(0x041E) volatile __T6CONbits_t T6CONbits
;
4850 #define _T6CON_T6CKPS0 0x01
4851 #define _T6CON_T6CKPS1 0x02
4852 #define _T6CON_TMR6ON 0x04
4853 #define _T6CON_TOUTPS0 0x08
4854 #define _T6CON_TOUTPS1 0x10
4855 #define _T6CON_TOUTPS2 0x20
4856 #define _T6CON_TOUTPS3 0x40
4858 //==============================================================================
4861 //==============================================================================
4864 extern __at(0x041F) __sfr CCDCON
;
4887 extern __at(0x041F) volatile __CCDCONbits_t CCDCONbits
;
4893 //==============================================================================
4896 //==============================================================================
4899 extern __at(0x048C) __sfr CCDPA
;
4903 unsigned CCDPA0
: 1;
4904 unsigned CCDPA1
: 1;
4905 unsigned CCDPA2
: 1;
4907 unsigned CCDPA4
: 1;
4908 unsigned CCDPA5
: 1;
4913 extern __at(0x048C) volatile __CCDPAbits_t CCDPAbits
;
4915 #define _CCDPA0 0x01
4916 #define _CCDPA1 0x02
4917 #define _CCDPA2 0x04
4918 #define _CCDPA4 0x10
4919 #define _CCDPA5 0x20
4921 //==============================================================================
4924 //==============================================================================
4927 extern __at(0x048D) __sfr CCDPB
;
4935 unsigned CCDPB4
: 1;
4936 unsigned CCDPB5
: 1;
4937 unsigned CCDPB6
: 1;
4938 unsigned CCDPB7
: 1;
4941 extern __at(0x048D) volatile __CCDPBbits_t CCDPBbits
;
4943 #define _CCDPB4 0x10
4944 #define _CCDPB5 0x20
4945 #define _CCDPB6 0x40
4946 #define _CCDPB7 0x80
4948 //==============================================================================
4951 //==============================================================================
4954 extern __at(0x048E) __sfr CCDPC
;
4958 unsigned CCDPC0
: 1;
4959 unsigned CCDPC1
: 1;
4960 unsigned CCDPC2
: 1;
4961 unsigned CCDPC3
: 1;
4962 unsigned CCDPC4
: 1;
4963 unsigned CCDPC5
: 1;
4964 unsigned CCDPC6
: 1;
4965 unsigned CCDPC7
: 1;
4968 extern __at(0x048E) volatile __CCDPCbits_t CCDPCbits
;
4970 #define _CCDPC0 0x01
4971 #define _CCDPC1 0x02
4972 #define _CCDPC2 0x04
4973 #define _CCDPC3 0x08
4974 #define _CCDPC4 0x10
4975 #define _CCDPC5 0x20
4976 #define _CCDPC6 0x40
4977 #define _CCDPC7 0x80
4979 //==============================================================================
4981 extern __at(0x0498) __sfr NCO1ACC
;
4982 extern __at(0x0498) __sfr NCO1ACCL
;
4983 extern __at(0x0499) __sfr NCO1ACCH
;
4984 extern __at(0x049A) __sfr NCO1ACCU
;
4985 extern __at(0x049B) __sfr NCO1INC
;
4986 extern __at(0x049B) __sfr NCO1INCL
;
4987 extern __at(0x049C) __sfr NCO1INCH
;
4988 extern __at(0x049D) __sfr NCO1INCU
;
4990 //==============================================================================
4993 extern __at(0x049E) __sfr NCO1CON
;
5007 extern __at(0x049E) volatile __NCO1CONbits_t NCO1CONbits
;
5014 //==============================================================================
5016 extern __at(0x049F) __sfr NCO1CLK
;
5018 //==============================================================================
5021 extern __at(0x0617) __sfr PWM5DCL
;
5033 unsigned PWM5DCL0
: 1;
5034 unsigned PWM5DCL1
: 1;
5040 unsigned PWM5DCL
: 2;
5044 extern __at(0x0617) volatile __PWM5DCLbits_t PWM5DCLbits
;
5046 #define _PWM5DCL0 0x40
5047 #define _PWM5DCL1 0x80
5049 //==============================================================================
5052 //==============================================================================
5055 extern __at(0x0618) __sfr PWM5DCH
;
5059 unsigned PWM5DCH0
: 1;
5060 unsigned PWM5DCH1
: 1;
5061 unsigned PWM5DCH2
: 1;
5062 unsigned PWM5DCH3
: 1;
5063 unsigned PWM5DCH4
: 1;
5064 unsigned PWM5DCH5
: 1;
5065 unsigned PWM5DCH6
: 1;
5066 unsigned PWM5DCH7
: 1;
5069 extern __at(0x0618) volatile __PWM5DCHbits_t PWM5DCHbits
;
5071 #define _PWM5DCH0 0x01
5072 #define _PWM5DCH1 0x02
5073 #define _PWM5DCH2 0x04
5074 #define _PWM5DCH3 0x08
5075 #define _PWM5DCH4 0x10
5076 #define _PWM5DCH5 0x20
5077 #define _PWM5DCH6 0x40
5078 #define _PWM5DCH7 0x80
5080 //==============================================================================
5083 //==============================================================================
5086 extern __at(0x0619) __sfr PWM5CON
;
5094 unsigned PWM5POL
: 1;
5095 unsigned PWM5OUT
: 1;
5097 unsigned PWM5EN
: 1;
5100 extern __at(0x0619) volatile __PWM5CONbits_t PWM5CONbits
;
5102 #define _PWM5POL 0x10
5103 #define _PWM5OUT 0x20
5104 #define _PWM5EN 0x80
5106 //==============================================================================
5109 //==============================================================================
5112 extern __at(0x0619) __sfr PWM5CON0
;
5120 unsigned PWM5POL
: 1;
5121 unsigned PWM5OUT
: 1;
5123 unsigned PWM5EN
: 1;
5126 extern __at(0x0619) volatile __PWM5CON0bits_t PWM5CON0bits
;
5128 #define _PWM5CON0_PWM5POL 0x10
5129 #define _PWM5CON0_PWM5OUT 0x20
5130 #define _PWM5CON0_PWM5EN 0x80
5132 //==============================================================================
5135 //==============================================================================
5138 extern __at(0x061A) __sfr PWM6DCL
;
5150 unsigned PWM6DCL0
: 1;
5151 unsigned PWM6DCL1
: 1;
5157 unsigned PWM6DCL
: 2;
5161 extern __at(0x061A) volatile __PWM6DCLbits_t PWM6DCLbits
;
5163 #define _PWM6DCL0 0x40
5164 #define _PWM6DCL1 0x80
5166 //==============================================================================
5169 //==============================================================================
5172 extern __at(0x061B) __sfr PWM6DCH
;
5176 unsigned PWM6DCH0
: 1;
5177 unsigned PWM6DCH1
: 1;
5178 unsigned PWM6DCH2
: 1;
5179 unsigned PWM6DCH3
: 1;
5180 unsigned PWM6DCH4
: 1;
5181 unsigned PWM6DCH5
: 1;
5182 unsigned PWM6DCH6
: 1;
5183 unsigned PWM6DCH7
: 1;
5186 extern __at(0x061B) volatile __PWM6DCHbits_t PWM6DCHbits
;
5188 #define _PWM6DCH0 0x01
5189 #define _PWM6DCH1 0x02
5190 #define _PWM6DCH2 0x04
5191 #define _PWM6DCH3 0x08
5192 #define _PWM6DCH4 0x10
5193 #define _PWM6DCH5 0x20
5194 #define _PWM6DCH6 0x40
5195 #define _PWM6DCH7 0x80
5197 //==============================================================================
5200 //==============================================================================
5203 extern __at(0x061C) __sfr PWM6CON
;
5211 unsigned PWM6POL
: 1;
5212 unsigned PWM6OUT
: 1;
5214 unsigned PWM6EN
: 1;
5217 extern __at(0x061C) volatile __PWM6CONbits_t PWM6CONbits
;
5219 #define _PWM6POL 0x10
5220 #define _PWM6OUT 0x20
5221 #define _PWM6EN 0x80
5223 //==============================================================================
5226 //==============================================================================
5229 extern __at(0x061C) __sfr PWM6CON0
;
5237 unsigned PWM6POL
: 1;
5238 unsigned PWM6OUT
: 1;
5240 unsigned PWM6EN
: 1;
5243 extern __at(0x061C) volatile __PWM6CON0bits_t PWM6CON0bits
;
5245 #define _PWM6CON0_PWM6POL 0x10
5246 #define _PWM6CON0_PWM6OUT 0x20
5247 #define _PWM6CON0_PWM6EN 0x80
5249 //==============================================================================
5252 //==============================================================================
5255 extern __at(0x061F) __sfr PWMTMRS
;
5261 unsigned P5TSEL0
: 1;
5262 unsigned P5TSEL1
: 1;
5263 unsigned P6TSEL0
: 1;
5264 unsigned P6TSEL1
: 1;
5273 unsigned P5TSEL
: 2;
5280 unsigned P6TSEL
: 2;
5285 extern __at(0x061F) volatile __PWMTMRSbits_t PWMTMRSbits
;
5287 #define _P5TSEL0 0x01
5288 #define _P5TSEL1 0x02
5289 #define _P6TSEL0 0x04
5290 #define _P6TSEL1 0x08
5292 //==============================================================================
5295 //==============================================================================
5298 extern __at(0x0691) __sfr CWG1CLKCON
;
5316 unsigned CWG1CS
: 1;
5325 } __CWG1CLKCONbits_t
;
5327 extern __at(0x0691) volatile __CWG1CLKCONbits_t CWG1CLKCONbits
;
5330 #define _CWG1CS 0x01
5332 //==============================================================================
5335 //==============================================================================
5338 extern __at(0x0692) __sfr CWG1DAT
;
5344 unsigned CWG1DAT0
: 1;
5345 unsigned CWG1DAT1
: 1;
5346 unsigned CWG1DAT2
: 1;
5347 unsigned CWG1DAT3
: 1;
5356 unsigned CWG1DAT
: 4;
5361 extern __at(0x0692) volatile __CWG1DATbits_t CWG1DATbits
;
5363 #define _CWG1DAT0 0x01
5364 #define _CWG1DAT1 0x02
5365 #define _CWG1DAT2 0x04
5366 #define _CWG1DAT3 0x08
5368 //==============================================================================
5371 //==============================================================================
5374 extern __at(0x0693) __sfr CWG1DBR
;
5392 unsigned CWG1DBR0
: 1;
5393 unsigned CWG1DBR1
: 1;
5394 unsigned CWG1DBR2
: 1;
5395 unsigned CWG1DBR3
: 1;
5396 unsigned CWG1DBR4
: 1;
5397 unsigned CWG1DBR5
: 1;
5410 unsigned CWG1DBR
: 6;
5415 extern __at(0x0693) volatile __CWG1DBRbits_t CWG1DBRbits
;
5418 #define _CWG1DBR0 0x01
5420 #define _CWG1DBR1 0x02
5422 #define _CWG1DBR2 0x04
5424 #define _CWG1DBR3 0x08
5426 #define _CWG1DBR4 0x10
5428 #define _CWG1DBR5 0x20
5430 //==============================================================================
5433 //==============================================================================
5436 extern __at(0x0694) __sfr CWG1DBF
;
5454 unsigned CWG1DBF0
: 1;
5455 unsigned CWG1DBF1
: 1;
5456 unsigned CWG1DBF2
: 1;
5457 unsigned CWG1DBF3
: 1;
5458 unsigned CWG1DBF4
: 1;
5459 unsigned CWG1DBF5
: 1;
5466 unsigned CWG1DBF
: 6;
5477 extern __at(0x0694) volatile __CWG1DBFbits_t CWG1DBFbits
;
5480 #define _CWG1DBF0 0x01
5482 #define _CWG1DBF1 0x02
5484 #define _CWG1DBF2 0x04
5486 #define _CWG1DBF3 0x08
5488 #define _CWG1DBF4 0x10
5490 #define _CWG1DBF5 0x20
5492 //==============================================================================
5495 //==============================================================================
5498 extern __at(0x0695) __sfr CWG1CON0
;
5516 unsigned CWG1MODE0
: 1;
5517 unsigned CWG1MODE1
: 1;
5518 unsigned CWG1MODE2
: 1;
5522 unsigned CWG1LD
: 1;
5535 unsigned CWG1EN
: 1;
5546 unsigned CWG1MODE
: 3;
5551 extern __at(0x0695) volatile __CWG1CON0bits_t CWG1CON0bits
;
5553 #define _CWG1CON0_MODE0 0x01
5554 #define _CWG1CON0_CWG1MODE0 0x01
5555 #define _CWG1CON0_MODE1 0x02
5556 #define _CWG1CON0_CWG1MODE1 0x02
5557 #define _CWG1CON0_MODE2 0x04
5558 #define _CWG1CON0_CWG1MODE2 0x04
5559 #define _CWG1CON0_LD 0x40
5560 #define _CWG1CON0_CWG1LD 0x40
5561 #define _CWG1CON0_EN 0x80
5562 #define _CWG1CON0_G1EN 0x80
5563 #define _CWG1CON0_CWG1EN 0x80
5565 //==============================================================================
5568 //==============================================================================
5571 extern __at(0x0696) __sfr CWG1CON1
;
5589 unsigned CWG1POLA
: 1;
5590 unsigned CWG1POLB
: 1;
5591 unsigned CWG1POLC
: 1;
5592 unsigned CWG1POLD
: 1;
5594 unsigned CWG1IN
: 1;
5600 extern __at(0x0696) volatile __CWG1CON1bits_t CWG1CON1bits
;
5603 #define _CWG1POLA 0x01
5605 #define _CWG1POLB 0x02
5607 #define _CWG1POLC 0x04
5609 #define _CWG1POLD 0x08
5611 #define _CWG1IN 0x20
5613 //==============================================================================
5616 //==============================================================================
5619 extern __at(0x0697) __sfr CWG1AS0
;
5632 unsigned SHUTDOWN
: 1;
5639 unsigned CWG1LSAC0
: 1;
5640 unsigned CWG1LSAC1
: 1;
5641 unsigned CWG1LSBD0
: 1;
5642 unsigned CWG1LSBD1
: 1;
5643 unsigned CWG1REN
: 1;
5644 unsigned CWG1SHUTDOWN
: 1;
5657 unsigned CWG1LSAC
: 2;
5664 unsigned CWG1LSBD
: 2;
5676 extern __at(0x0697) volatile __CWG1AS0bits_t CWG1AS0bits
;
5679 #define _CWG1LSAC0 0x04
5681 #define _CWG1LSAC1 0x08
5683 #define _CWG1LSBD0 0x10
5685 #define _CWG1LSBD1 0x20
5687 #define _CWG1REN 0x40
5688 #define _SHUTDOWN 0x80
5689 #define _CWG1SHUTDOWN 0x80
5691 //==============================================================================
5694 //==============================================================================
5697 extern __at(0x0698) __sfr CWG1AS1
;
5711 extern __at(0x0698) volatile __CWG1AS1bits_t CWG1AS1bits
;
5719 //==============================================================================
5722 //==============================================================================
5725 extern __at(0x0699) __sfr CWG1STR
;
5743 unsigned CWG1STRA
: 1;
5744 unsigned CWG1STRB
: 1;
5745 unsigned CWG1STRC
: 1;
5746 unsigned CWG1STRD
: 1;
5747 unsigned CWG1OVRA
: 1;
5748 unsigned CWG1OVRB
: 1;
5749 unsigned CWG1OVRC
: 1;
5750 unsigned CWG1OVRD
: 1;
5754 extern __at(0x0699) volatile __CWG1STRbits_t CWG1STRbits
;
5757 #define _CWG1STRA 0x01
5759 #define _CWG1STRB 0x02
5761 #define _CWG1STRC 0x04
5763 #define _CWG1STRD 0x08
5765 #define _CWG1OVRA 0x10
5767 #define _CWG1OVRB 0x20
5769 #define _CWG1OVRC 0x40
5771 #define _CWG1OVRD 0x80
5773 //==============================================================================
5776 //==============================================================================
5779 extern __at(0x0711) __sfr CWG2CLKCON
;
5797 unsigned CWG2CS
: 1;
5806 } __CWG2CLKCONbits_t
;
5808 extern __at(0x0711) volatile __CWG2CLKCONbits_t CWG2CLKCONbits
;
5810 #define _CWG2CLKCON_CS 0x01
5811 #define _CWG2CLKCON_CWG2CS 0x01
5813 //==============================================================================
5816 //==============================================================================
5819 extern __at(0x0712) __sfr CWG2DAT
;
5825 unsigned CWG2DAT0
: 1;
5826 unsigned CWG2DAT1
: 1;
5827 unsigned CWG2DAT2
: 1;
5828 unsigned CWG2DAT3
: 1;
5837 unsigned CWG2DAT
: 4;
5842 extern __at(0x0712) volatile __CWG2DATbits_t CWG2DATbits
;
5844 #define _CWG2DAT0 0x01
5845 #define _CWG2DAT1 0x02
5846 #define _CWG2DAT2 0x04
5847 #define _CWG2DAT3 0x08
5849 //==============================================================================
5852 //==============================================================================
5855 extern __at(0x0713) __sfr CWG2DBR
;
5873 unsigned CWG2DBR0
: 1;
5874 unsigned CWG2DBR1
: 1;
5875 unsigned CWG2DBR2
: 1;
5876 unsigned CWG2DBR3
: 1;
5877 unsigned CWG2DBR4
: 1;
5878 unsigned CWG2DBR5
: 1;
5885 unsigned CWG2DBR
: 6;
5896 extern __at(0x0713) volatile __CWG2DBRbits_t CWG2DBRbits
;
5898 #define _CWG2DBR_DBR0 0x01
5899 #define _CWG2DBR_CWG2DBR0 0x01
5900 #define _CWG2DBR_DBR1 0x02
5901 #define _CWG2DBR_CWG2DBR1 0x02
5902 #define _CWG2DBR_DBR2 0x04
5903 #define _CWG2DBR_CWG2DBR2 0x04
5904 #define _CWG2DBR_DBR3 0x08
5905 #define _CWG2DBR_CWG2DBR3 0x08
5906 #define _CWG2DBR_DBR4 0x10
5907 #define _CWG2DBR_CWG2DBR4 0x10
5908 #define _CWG2DBR_DBR5 0x20
5909 #define _CWG2DBR_CWG2DBR5 0x20
5911 //==============================================================================
5914 //==============================================================================
5917 extern __at(0x0714) __sfr CWG2DBF
;
5935 unsigned CWG2DBF0
: 1;
5936 unsigned CWG2DBF1
: 1;
5937 unsigned CWG2DBF2
: 1;
5938 unsigned CWG2DBF3
: 1;
5939 unsigned CWG2DBF4
: 1;
5940 unsigned CWG2DBF5
: 1;
5953 unsigned CWG2DBF
: 6;
5958 extern __at(0x0714) volatile __CWG2DBFbits_t CWG2DBFbits
;
5960 #define _CWG2DBF_DBF0 0x01
5961 #define _CWG2DBF_CWG2DBF0 0x01
5962 #define _CWG2DBF_DBF1 0x02
5963 #define _CWG2DBF_CWG2DBF1 0x02
5964 #define _CWG2DBF_DBF2 0x04
5965 #define _CWG2DBF_CWG2DBF2 0x04
5966 #define _CWG2DBF_DBF3 0x08
5967 #define _CWG2DBF_CWG2DBF3 0x08
5968 #define _CWG2DBF_DBF4 0x10
5969 #define _CWG2DBF_CWG2DBF4 0x10
5970 #define _CWG2DBF_DBF5 0x20
5971 #define _CWG2DBF_CWG2DBF5 0x20
5973 //==============================================================================
5976 //==============================================================================
5979 extern __at(0x0715) __sfr CWG2CON0
;
5997 unsigned CWG2MODE0
: 1;
5998 unsigned CWG2MODE1
: 1;
5999 unsigned CWG2MODE2
: 1;
6003 unsigned CWG2LD
: 1;
6016 unsigned CWG2EN
: 1;
6021 unsigned CWG2MODE
: 3;
6032 extern __at(0x0715) volatile __CWG2CON0bits_t CWG2CON0bits
;
6034 #define _CWG2CON0_MODE0 0x01
6035 #define _CWG2CON0_CWG2MODE0 0x01
6036 #define _CWG2CON0_MODE1 0x02
6037 #define _CWG2CON0_CWG2MODE1 0x02
6038 #define _CWG2CON0_MODE2 0x04
6039 #define _CWG2CON0_CWG2MODE2 0x04
6040 #define _CWG2CON0_LD 0x40
6041 #define _CWG2CON0_CWG2LD 0x40
6042 #define _CWG2CON0_EN 0x80
6043 #define _CWG2CON0_G2EN 0x80
6044 #define _CWG2CON0_CWG2EN 0x80
6046 //==============================================================================
6049 //==============================================================================
6052 extern __at(0x0716) __sfr CWG2CON1
;
6070 unsigned CWG2POLA
: 1;
6071 unsigned CWG2POLB
: 1;
6072 unsigned CWG2POLC
: 1;
6073 unsigned CWG2POLD
: 1;
6075 unsigned CWG2IN
: 1;
6081 extern __at(0x0716) volatile __CWG2CON1bits_t CWG2CON1bits
;
6083 #define _CWG2CON1_POLA 0x01
6084 #define _CWG2CON1_CWG2POLA 0x01
6085 #define _CWG2CON1_POLB 0x02
6086 #define _CWG2CON1_CWG2POLB 0x02
6087 #define _CWG2CON1_POLC 0x04
6088 #define _CWG2CON1_CWG2POLC 0x04
6089 #define _CWG2CON1_POLD 0x08
6090 #define _CWG2CON1_CWG2POLD 0x08
6091 #define _CWG2CON1_IN 0x20
6092 #define _CWG2CON1_CWG2IN 0x20
6094 //==============================================================================
6097 //==============================================================================
6100 extern __at(0x0717) __sfr CWG2AS0
;
6113 unsigned SHUTDOWN
: 1;
6120 unsigned CWG2LSAC0
: 1;
6121 unsigned CWG2LSAC1
: 1;
6122 unsigned CWG2LSBD0
: 1;
6123 unsigned CWG2LSBD1
: 1;
6124 unsigned CWG2REN
: 1;
6125 unsigned CWG2SHUTDOWN
: 1;
6138 unsigned CWG2LSAC
: 2;
6145 unsigned CWG2LSBD
: 2;
6157 extern __at(0x0717) volatile __CWG2AS0bits_t CWG2AS0bits
;
6159 #define _CWG2AS0_LSAC0 0x04
6160 #define _CWG2AS0_CWG2LSAC0 0x04
6161 #define _CWG2AS0_LSAC1 0x08
6162 #define _CWG2AS0_CWG2LSAC1 0x08
6163 #define _CWG2AS0_LSBD0 0x10
6164 #define _CWG2AS0_CWG2LSBD0 0x10
6165 #define _CWG2AS0_LSBD1 0x20
6166 #define _CWG2AS0_CWG2LSBD1 0x20
6167 #define _CWG2AS0_REN 0x40
6168 #define _CWG2AS0_CWG2REN 0x40
6169 #define _CWG2AS0_SHUTDOWN 0x80
6170 #define _CWG2AS0_CWG2SHUTDOWN 0x80
6172 //==============================================================================
6175 //==============================================================================
6178 extern __at(0x0718) __sfr CWG2AS1
;
6192 extern __at(0x0718) volatile __CWG2AS1bits_t CWG2AS1bits
;
6194 #define _CWG2AS1_AS0E 0x01
6195 #define _CWG2AS1_AS1E 0x02
6196 #define _CWG2AS1_AS2E 0x04
6197 #define _CWG2AS1_AS3E 0x08
6198 #define _CWG2AS1_AS4E 0x10
6200 //==============================================================================
6203 //==============================================================================
6206 extern __at(0x0719) __sfr CWG2STR
;
6224 unsigned CWG2STRA
: 1;
6225 unsigned CWG2STRB
: 1;
6226 unsigned CWG2STRC
: 1;
6227 unsigned CWG2STRD
: 1;
6228 unsigned CWG2OVRA
: 1;
6229 unsigned CWG2OVRB
: 1;
6230 unsigned CWG2OVRC
: 1;
6231 unsigned CWG2OVRD
: 1;
6235 extern __at(0x0719) volatile __CWG2STRbits_t CWG2STRbits
;
6237 #define _CWG2STR_STRA 0x01
6238 #define _CWG2STR_CWG2STRA 0x01
6239 #define _CWG2STR_STRB 0x02
6240 #define _CWG2STR_CWG2STRB 0x02
6241 #define _CWG2STR_STRC 0x04
6242 #define _CWG2STR_CWG2STRC 0x04
6243 #define _CWG2STR_STRD 0x08
6244 #define _CWG2STR_CWG2STRD 0x08
6245 #define _CWG2STR_OVRA 0x10
6246 #define _CWG2STR_CWG2OVRA 0x10
6247 #define _CWG2STR_OVRB 0x20
6248 #define _CWG2STR_CWG2OVRB 0x20
6249 #define _CWG2STR_OVRC 0x40
6250 #define _CWG2STR_CWG2OVRC 0x40
6251 #define _CWG2STR_OVRD 0x80
6252 #define _CWG2STR_CWG2OVRD 0x80
6254 //==============================================================================
6256 extern __at(0x0891) __sfr NVMADR
;
6258 //==============================================================================
6261 extern __at(0x0891) __sfr NVMADRL
;
6265 unsigned NVMADR0
: 1;
6266 unsigned NVMADR1
: 1;
6267 unsigned NVMADR2
: 1;
6268 unsigned NVMADR3
: 1;
6269 unsigned NVMADR4
: 1;
6270 unsigned NVMADR5
: 1;
6271 unsigned NVMADR6
: 1;
6272 unsigned NVMADR7
: 1;
6275 extern __at(0x0891) volatile __NVMADRLbits_t NVMADRLbits
;
6277 #define _NVMADR0 0x01
6278 #define _NVMADR1 0x02
6279 #define _NVMADR2 0x04
6280 #define _NVMADR3 0x08
6281 #define _NVMADR4 0x10
6282 #define _NVMADR5 0x20
6283 #define _NVMADR6 0x40
6284 #define _NVMADR7 0x80
6286 //==============================================================================
6289 //==============================================================================
6292 extern __at(0x0892) __sfr NVMADRH
;
6296 unsigned NVMADR8
: 1;
6297 unsigned NVMADR9
: 1;
6298 unsigned NVMADR10
: 1;
6299 unsigned NVMADR11
: 1;
6300 unsigned NVMADR12
: 1;
6301 unsigned NVMADR13
: 1;
6302 unsigned NVMADR14
: 1;
6306 extern __at(0x0892) volatile __NVMADRHbits_t NVMADRHbits
;
6308 #define _NVMADR8 0x01
6309 #define _NVMADR9 0x02
6310 #define _NVMADR10 0x04
6311 #define _NVMADR11 0x08
6312 #define _NVMADR12 0x10
6313 #define _NVMADR13 0x20
6314 #define _NVMADR14 0x40
6316 //==============================================================================
6318 extern __at(0x0893) __sfr NVMDAT
;
6320 //==============================================================================
6323 extern __at(0x0893) __sfr NVMDATL
;
6327 unsigned NVMDAT0
: 1;
6328 unsigned NVMDAT1
: 1;
6329 unsigned NVMDAT2
: 1;
6330 unsigned NVMDAT3
: 1;
6331 unsigned NVMDAT4
: 1;
6332 unsigned NVMDAT5
: 1;
6333 unsigned NVMDAT6
: 1;
6334 unsigned NVMDAT7
: 1;
6337 extern __at(0x0893) volatile __NVMDATLbits_t NVMDATLbits
;
6339 #define _NVMDAT0 0x01
6340 #define _NVMDAT1 0x02
6341 #define _NVMDAT2 0x04
6342 #define _NVMDAT3 0x08
6343 #define _NVMDAT4 0x10
6344 #define _NVMDAT5 0x20
6345 #define _NVMDAT6 0x40
6346 #define _NVMDAT7 0x80
6348 //==============================================================================
6351 //==============================================================================
6354 extern __at(0x0894) __sfr NVMDATH
;
6358 unsigned NVMDAT8
: 1;
6359 unsigned NVMDAT9
: 1;
6360 unsigned NVMDAT10
: 1;
6361 unsigned NVMDAT11
: 1;
6362 unsigned NVMDAT12
: 1;
6363 unsigned NVMDAT13
: 1;
6368 extern __at(0x0894) volatile __NVMDATHbits_t NVMDATHbits
;
6370 #define _NVMDAT8 0x01
6371 #define _NVMDAT9 0x02
6372 #define _NVMDAT10 0x04
6373 #define _NVMDAT11 0x08
6374 #define _NVMDAT12 0x10
6375 #define _NVMDAT13 0x20
6377 //==============================================================================
6380 //==============================================================================
6383 extern __at(0x0895) __sfr NVMCON1
;
6393 unsigned NVMREGS
: 1;
6397 extern __at(0x0895) volatile __NVMCON1bits_t NVMCON1bits
;
6405 #define _NVMREGS 0x40
6407 //==============================================================================
6409 extern __at(0x0896) __sfr NVMCON2
;
6411 //==============================================================================
6414 extern __at(0x089B) __sfr PCON0
;
6418 unsigned NOT_BOR
: 1;
6419 unsigned NOT_POR
: 1;
6420 unsigned NOT_RI
: 1;
6421 unsigned NOT_RMCLR
: 1;
6422 unsigned NOT_RWDT
: 1;
6424 unsigned STKUNF
: 1;
6425 unsigned STKOVF
: 1;
6428 extern __at(0x089B) volatile __PCON0bits_t PCON0bits
;
6430 #define _NOT_BOR 0x01
6431 #define _NOT_POR 0x02
6432 #define _NOT_RI 0x04
6433 #define _NOT_RMCLR 0x08
6434 #define _NOT_RWDT 0x10
6435 #define _STKUNF 0x40
6436 #define _STKOVF 0x80
6438 //==============================================================================
6441 //==============================================================================
6444 extern __at(0x0911) __sfr PMD0
;
6449 unsigned CLKRMD
: 1;
6455 unsigned SYSCMD
: 1;
6458 extern __at(0x0911) volatile __PMD0bits_t PMD0bits
;
6461 #define _CLKRMD 0x02
6464 #define _SYSCMD 0x80
6466 //==============================================================================
6469 //==============================================================================
6472 extern __at(0x0912) __sfr PMD1
;
6476 unsigned TMR0MD
: 1;
6477 unsigned TMR1MD
: 1;
6478 unsigned TMR2MD
: 1;
6479 unsigned TMR3MD
: 1;
6480 unsigned TMR4MD
: 1;
6481 unsigned TMR5MD
: 1;
6482 unsigned TMR6MD
: 1;
6486 extern __at(0x0912) volatile __PMD1bits_t PMD1bits
;
6488 #define _TMR0MD 0x01
6489 #define _TMR1MD 0x02
6490 #define _TMR2MD 0x04
6491 #define _TMR3MD 0x08
6492 #define _TMR4MD 0x10
6493 #define _TMR5MD 0x20
6494 #define _TMR6MD 0x40
6497 //==============================================================================
6500 //==============================================================================
6503 extern __at(0x0913) __sfr PMD2
;
6508 unsigned CMP1MD
: 1;
6509 unsigned CMP2MD
: 1;
6517 extern __at(0x0913) volatile __PMD2bits_t PMD2bits
;
6519 #define _CMP1MD 0x02
6520 #define _CMP2MD 0x04
6524 //==============================================================================
6527 //==============================================================================
6530 extern __at(0x0914) __sfr PMD3
;
6534 unsigned CCP1MD
: 1;
6535 unsigned CCP2MD
: 1;
6536 unsigned CCP3MD
: 1;
6537 unsigned CCP4MD
: 1;
6538 unsigned PWM5MD
: 1;
6539 unsigned PWM6MD
: 1;
6540 unsigned CWG1MD
: 1;
6541 unsigned CWG2MD
: 1;
6544 extern __at(0x0914) volatile __PMD3bits_t PMD3bits
;
6546 #define _CCP1MD 0x01
6547 #define _CCP2MD 0x02
6548 #define _CCP3MD 0x04
6549 #define _CCP4MD 0x08
6550 #define _PWM5MD 0x10
6551 #define _PWM6MD 0x20
6552 #define _CWG1MD 0x40
6553 #define _CWG2MD 0x80
6555 //==============================================================================
6558 //==============================================================================
6561 extern __at(0x0915) __sfr PMD4
;
6566 unsigned MSSP1MD
: 1;
6567 unsigned MSSP2MD
: 1;
6570 unsigned UART1MD
: 1;
6575 extern __at(0x0915) volatile __PMD4bits_t PMD4bits
;
6577 #define _MSSP1MD 0x02
6578 #define _MSSP2MD 0x04
6579 #define _UART1MD 0x20
6581 //==============================================================================
6584 //==============================================================================
6587 extern __at(0x0916) __sfr PMD5
;
6592 unsigned CLC1MD
: 1;
6593 unsigned CLC2MD
: 1;
6594 unsigned CLC3MD
: 1;
6595 unsigned CLC4MD
: 1;
6601 extern __at(0x0916) volatile __PMD5bits_t PMD5bits
;
6604 #define _CLC1MD 0x02
6605 #define _CLC2MD 0x04
6606 #define _CLC3MD 0x08
6607 #define _CLC4MD 0x10
6609 //==============================================================================
6612 //==============================================================================
6615 extern __at(0x0918) __sfr CPUDOZE
;
6638 extern __at(0x0918) volatile __CPUDOZEbits_t CPUDOZEbits
;
6648 //==============================================================================
6651 //==============================================================================
6654 extern __at(0x0919) __sfr OSCCON1
;
6684 extern __at(0x0919) volatile __OSCCON1bits_t OSCCON1bits
;
6694 //==============================================================================
6697 //==============================================================================
6700 extern __at(0x091A) __sfr OSCCON2
;
6730 extern __at(0x091A) volatile __OSCCON2bits_t OSCCON2bits
;
6740 //==============================================================================
6743 //==============================================================================
6746 extern __at(0x091B) __sfr OSCCON3
;
6755 unsigned SOSCBE
: 1;
6756 unsigned SOSCPWR
: 1;
6757 unsigned CSWHOLD
: 1;
6760 extern __at(0x091B) volatile __OSCCON3bits_t OSCCON3bits
;
6764 #define _SOSCBE 0x20
6765 #define _SOSCPWR 0x40
6766 #define _CSWHOLD 0x80
6768 //==============================================================================
6771 //==============================================================================
6774 extern __at(0x091C) __sfr OSCSTAT1
;
6788 extern __at(0x091C) volatile __OSCSTAT1bits_t OSCSTAT1bits
;
6797 //==============================================================================
6800 //==============================================================================
6803 extern __at(0x091D) __sfr OSCEN
;
6810 unsigned SOSCEN
: 1;
6814 unsigned EXTOEN
: 1;
6817 extern __at(0x091D) volatile __OSCENbits_t OSCENbits
;
6820 #define _SOSCEN 0x08
6823 #define _EXTOEN 0x80
6825 //==============================================================================
6828 //==============================================================================
6831 extern __at(0x091E) __sfr OSCTUNE
;
6837 unsigned HFTUN0
: 1;
6838 unsigned HFTUN1
: 1;
6839 unsigned HFTUN2
: 1;
6840 unsigned HFTUN3
: 1;
6841 unsigned HFTUN4
: 1;
6842 unsigned HFTUN5
: 1;
6854 extern __at(0x091E) volatile __OSCTUNEbits_t OSCTUNEbits
;
6856 #define _HFTUN0 0x01
6857 #define _HFTUN1 0x02
6858 #define _HFTUN2 0x04
6859 #define _HFTUN3 0x08
6860 #define _HFTUN4 0x10
6861 #define _HFTUN5 0x20
6863 //==============================================================================
6866 //==============================================================================
6869 extern __at(0x091F) __sfr OSCFRQ
;
6875 unsigned HFFRQ0
: 1;
6876 unsigned HFFRQ1
: 1;
6877 unsigned HFFRQ2
: 1;
6878 unsigned HFFRQ3
: 1;
6892 extern __at(0x091F) volatile __OSCFRQbits_t OSCFRQbits
;
6894 #define _HFFRQ0 0x01
6895 #define _HFFRQ1 0x02
6896 #define _HFFRQ2 0x04
6897 #define _HFFRQ3 0x08
6899 //==============================================================================
6902 //==============================================================================
6905 extern __at(0x0E0F) __sfr PPSLOCK
;
6909 unsigned PPSLOCKED
: 1;
6919 extern __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits
;
6921 #define _PPSLOCKED 0x01
6923 //==============================================================================
6926 //==============================================================================
6929 extern __at(0x0E10) __sfr INTPPS
;
6935 unsigned INTPPS0
: 1;
6936 unsigned INTPPS1
: 1;
6937 unsigned INTPPS2
: 1;
6938 unsigned INTPPS3
: 1;
6939 unsigned INTPPS4
: 1;
6947 unsigned INTPPS
: 5;
6952 extern __at(0x0E10) volatile __INTPPSbits_t INTPPSbits
;
6954 #define _INTPPS0 0x01
6955 #define _INTPPS1 0x02
6956 #define _INTPPS2 0x04
6957 #define _INTPPS3 0x08
6958 #define _INTPPS4 0x10
6960 //==============================================================================
6963 //==============================================================================
6966 extern __at(0x0E11) __sfr T0CKIPPS
;
6972 unsigned T0CKIPPS0
: 1;
6973 unsigned T0CKIPPS1
: 1;
6974 unsigned T0CKIPPS2
: 1;
6975 unsigned T0CKIPPS3
: 1;
6976 unsigned T0CKIPPS4
: 1;
6984 unsigned T0CKIPPS
: 5;
6989 extern __at(0x0E11) volatile __T0CKIPPSbits_t T0CKIPPSbits
;
6991 #define _T0CKIPPS0 0x01
6992 #define _T0CKIPPS1 0x02
6993 #define _T0CKIPPS2 0x04
6994 #define _T0CKIPPS3 0x08
6995 #define _T0CKIPPS4 0x10
6997 //==============================================================================
7000 //==============================================================================
7003 extern __at(0x0E12) __sfr T1CKIPPS
;
7009 unsigned T1CKIPPS0
: 1;
7010 unsigned T1CKIPPS1
: 1;
7011 unsigned T1CKIPPS2
: 1;
7012 unsigned T1CKIPPS3
: 1;
7013 unsigned T1CKIPPS4
: 1;
7021 unsigned T1CKIPPS
: 5;
7026 extern __at(0x0E12) volatile __T1CKIPPSbits_t T1CKIPPSbits
;
7028 #define _T1CKIPPS0 0x01
7029 #define _T1CKIPPS1 0x02
7030 #define _T1CKIPPS2 0x04
7031 #define _T1CKIPPS3 0x08
7032 #define _T1CKIPPS4 0x10
7034 //==============================================================================
7037 //==============================================================================
7040 extern __at(0x0E13) __sfr T1GPPS
;
7046 unsigned T1GPPS0
: 1;
7047 unsigned T1GPPS1
: 1;
7048 unsigned T1GPPS2
: 1;
7049 unsigned T1GPPS3
: 1;
7050 unsigned T1GPPS4
: 1;
7058 unsigned T1GPPS
: 5;
7063 extern __at(0x0E13) volatile __T1GPPSbits_t T1GPPSbits
;
7065 #define _T1GPPS0 0x01
7066 #define _T1GPPS1 0x02
7067 #define _T1GPPS2 0x04
7068 #define _T1GPPS3 0x08
7069 #define _T1GPPS4 0x10
7071 //==============================================================================
7074 //==============================================================================
7077 extern __at(0x0E14) __sfr CCP1PPS
;
7083 unsigned CCP1PPS0
: 1;
7084 unsigned CCP1PPS1
: 1;
7085 unsigned CCP1PPS2
: 1;
7086 unsigned CCP1PPS3
: 1;
7087 unsigned CCP1PPS4
: 1;
7095 unsigned CCP1PPS
: 5;
7100 extern __at(0x0E14) volatile __CCP1PPSbits_t CCP1PPSbits
;
7102 #define _CCP1PPS0 0x01
7103 #define _CCP1PPS1 0x02
7104 #define _CCP1PPS2 0x04
7105 #define _CCP1PPS3 0x08
7106 #define _CCP1PPS4 0x10
7108 //==============================================================================
7111 //==============================================================================
7114 extern __at(0x0E15) __sfr CCP2PPS
;
7120 unsigned CCP2PPS0
: 1;
7121 unsigned CCP2PPS1
: 1;
7122 unsigned CCP2PPS2
: 1;
7123 unsigned CCP2PPS3
: 1;
7124 unsigned CCP2PPS4
: 1;
7132 unsigned CCP2PPS
: 5;
7137 extern __at(0x0E15) volatile __CCP2PPSbits_t CCP2PPSbits
;
7139 #define _CCP2PPS0 0x01
7140 #define _CCP2PPS1 0x02
7141 #define _CCP2PPS2 0x04
7142 #define _CCP2PPS3 0x08
7143 #define _CCP2PPS4 0x10
7145 //==============================================================================
7148 //==============================================================================
7151 extern __at(0x0E16) __sfr CCP3PPS
;
7157 unsigned CCP3PPS0
: 1;
7158 unsigned CCP3PPS1
: 1;
7159 unsigned CCP3PPS2
: 1;
7160 unsigned CCP3PPS3
: 1;
7161 unsigned CCP3PPS4
: 1;
7169 unsigned CCP3PPS
: 5;
7174 extern __at(0x0E16) volatile __CCP3PPSbits_t CCP3PPSbits
;
7176 #define _CCP3PPS0 0x01
7177 #define _CCP3PPS1 0x02
7178 #define _CCP3PPS2 0x04
7179 #define _CCP3PPS3 0x08
7180 #define _CCP3PPS4 0x10
7182 //==============================================================================
7185 //==============================================================================
7188 extern __at(0x0E17) __sfr CCP4PPS
;
7194 unsigned CCP4PPS0
: 1;
7195 unsigned CCP4PPS1
: 1;
7196 unsigned CCP4PPS2
: 1;
7197 unsigned CCP4PPS3
: 1;
7198 unsigned CCP4PPS4
: 1;
7206 unsigned CCP4PPS
: 5;
7211 extern __at(0x0E17) volatile __CCP4PPSbits_t CCP4PPSbits
;
7213 #define _CCP4PPS0 0x01
7214 #define _CCP4PPS1 0x02
7215 #define _CCP4PPS2 0x04
7216 #define _CCP4PPS3 0x08
7217 #define _CCP4PPS4 0x10
7219 //==============================================================================
7222 //==============================================================================
7225 extern __at(0x0E18) __sfr CWG1PPS
;
7231 unsigned CWG1PPS0
: 1;
7232 unsigned CWG1PPS1
: 1;
7233 unsigned CWG1PPS2
: 1;
7234 unsigned CWG1PPS3
: 1;
7235 unsigned CWG1PPS4
: 1;
7243 unsigned CWG1PPS
: 5;
7248 extern __at(0x0E18) volatile __CWG1PPSbits_t CWG1PPSbits
;
7250 #define _CWG1PPS0 0x01
7251 #define _CWG1PPS1 0x02
7252 #define _CWG1PPS2 0x04
7253 #define _CWG1PPS3 0x08
7254 #define _CWG1PPS4 0x10
7256 //==============================================================================
7259 //==============================================================================
7262 extern __at(0x0E19) __sfr CWG2PPS
;
7268 unsigned CWG2PPS0
: 1;
7269 unsigned CWG2PPS1
: 1;
7270 unsigned CWG2PPS2
: 1;
7271 unsigned CWG2PPS3
: 1;
7272 unsigned CWG2PPS4
: 1;
7280 unsigned CWG2PPS
: 5;
7285 extern __at(0x0E19) volatile __CWG2PPSbits_t CWG2PPSbits
;
7287 #define _CWG2PPS0 0x01
7288 #define _CWG2PPS1 0x02
7289 #define _CWG2PPS2 0x04
7290 #define _CWG2PPS3 0x08
7291 #define _CWG2PPS4 0x10
7293 //==============================================================================
7296 //==============================================================================
7299 extern __at(0x0E1A) __sfr MDCIN1PPS
;
7305 unsigned MDCIN1PPS0
: 1;
7306 unsigned MDCIN1PPS1
: 1;
7307 unsigned MDCIN1PPS2
: 1;
7308 unsigned MDCIN1PPS3
: 1;
7309 unsigned MDCIN1PPS4
: 1;
7317 unsigned MDCIN1PPS
: 5;
7320 } __MDCIN1PPSbits_t
;
7322 extern __at(0x0E1A) volatile __MDCIN1PPSbits_t MDCIN1PPSbits
;
7324 #define _MDCIN1PPS0 0x01
7325 #define _MDCIN1PPS1 0x02
7326 #define _MDCIN1PPS2 0x04
7327 #define _MDCIN1PPS3 0x08
7328 #define _MDCIN1PPS4 0x10
7330 //==============================================================================
7333 //==============================================================================
7336 extern __at(0x0E1B) __sfr MDCIN2PPS
;
7342 unsigned MDCIN2PPS0
: 1;
7343 unsigned MDCIN2PPS1
: 1;
7344 unsigned MDCIN2PPS2
: 1;
7345 unsigned MDCIN2PPS3
: 1;
7346 unsigned MDCIN2PPS4
: 1;
7354 unsigned MDCIN2PPS
: 5;
7357 } __MDCIN2PPSbits_t
;
7359 extern __at(0x0E1B) volatile __MDCIN2PPSbits_t MDCIN2PPSbits
;
7361 #define _MDCIN2PPS0 0x01
7362 #define _MDCIN2PPS1 0x02
7363 #define _MDCIN2PPS2 0x04
7364 #define _MDCIN2PPS3 0x08
7365 #define _MDCIN2PPS4 0x10
7367 //==============================================================================
7370 //==============================================================================
7373 extern __at(0x0E1C) __sfr MDMINPPS
;
7379 unsigned MDMINPPS0
: 1;
7380 unsigned MDMINPPS1
: 1;
7381 unsigned MDMINPPS2
: 1;
7382 unsigned MDMINPPS3
: 1;
7383 unsigned MDMINPPS4
: 1;
7391 unsigned MDMINPPS
: 5;
7396 extern __at(0x0E1C) volatile __MDMINPPSbits_t MDMINPPSbits
;
7398 #define _MDMINPPS0 0x01
7399 #define _MDMINPPS1 0x02
7400 #define _MDMINPPS2 0x04
7401 #define _MDMINPPS3 0x08
7402 #define _MDMINPPS4 0x10
7404 //==============================================================================
7407 //==============================================================================
7410 extern __at(0x0E1D) __sfr SSP2CLKPPS
;
7416 unsigned SSP2CLKPPS0
: 1;
7417 unsigned SSP2CLKPPS1
: 1;
7418 unsigned SSP2CLKPPS2
: 1;
7419 unsigned SSP2CLKPPS3
: 1;
7420 unsigned SSP2CLKPPS4
: 1;
7428 unsigned SSP2CLKPPS
: 5;
7431 } __SSP2CLKPPSbits_t
;
7433 extern __at(0x0E1D) volatile __SSP2CLKPPSbits_t SSP2CLKPPSbits
;
7435 #define _SSP2CLKPPS0 0x01
7436 #define _SSP2CLKPPS1 0x02
7437 #define _SSP2CLKPPS2 0x04
7438 #define _SSP2CLKPPS3 0x08
7439 #define _SSP2CLKPPS4 0x10
7441 //==============================================================================
7444 //==============================================================================
7447 extern __at(0x0E1E) __sfr SSP2DATPPS
;
7453 unsigned SSP2DATPPS0
: 1;
7454 unsigned SSP2DATPPS1
: 1;
7455 unsigned SSP2DATPPS2
: 1;
7456 unsigned SSP2DATPPS3
: 1;
7457 unsigned SSP2DATPPS4
: 1;
7465 unsigned SSP2DATPPS
: 5;
7468 } __SSP2DATPPSbits_t
;
7470 extern __at(0x0E1E) volatile __SSP2DATPPSbits_t SSP2DATPPSbits
;
7472 #define _SSP2DATPPS0 0x01
7473 #define _SSP2DATPPS1 0x02
7474 #define _SSP2DATPPS2 0x04
7475 #define _SSP2DATPPS3 0x08
7476 #define _SSP2DATPPS4 0x10
7478 //==============================================================================
7481 //==============================================================================
7484 extern __at(0x0E1F) __sfr SSP2SSPPS
;
7490 unsigned SSP2SSPPS0
: 1;
7491 unsigned SSP2SSPPS1
: 1;
7492 unsigned SSP2SSPPS2
: 1;
7493 unsigned SSP2SSPPS3
: 1;
7494 unsigned SSP2SSPPS4
: 1;
7502 unsigned SSP2SSPPS
: 5;
7505 } __SSP2SSPPSbits_t
;
7507 extern __at(0x0E1F) volatile __SSP2SSPPSbits_t SSP2SSPPSbits
;
7509 #define _SSP2SSPPS0 0x01
7510 #define _SSP2SSPPS1 0x02
7511 #define _SSP2SSPPS2 0x04
7512 #define _SSP2SSPPS3 0x08
7513 #define _SSP2SSPPS4 0x10
7515 //==============================================================================
7518 //==============================================================================
7521 extern __at(0x0E20) __sfr SSP1CLKPPS
;
7527 unsigned SSP1CLKPPS0
: 1;
7528 unsigned SSP1CLKPPS1
: 1;
7529 unsigned SSP1CLKPPS2
: 1;
7530 unsigned SSP1CLKPPS3
: 1;
7531 unsigned SSP1CLKPPS4
: 1;
7539 unsigned SSP1CLKPPS
: 5;
7542 } __SSP1CLKPPSbits_t
;
7544 extern __at(0x0E20) volatile __SSP1CLKPPSbits_t SSP1CLKPPSbits
;
7546 #define _SSP1CLKPPS0 0x01
7547 #define _SSP1CLKPPS1 0x02
7548 #define _SSP1CLKPPS2 0x04
7549 #define _SSP1CLKPPS3 0x08
7550 #define _SSP1CLKPPS4 0x10
7552 //==============================================================================
7555 //==============================================================================
7558 extern __at(0x0E21) __sfr SSP1DATPPS
;
7564 unsigned SSP1DATPPS0
: 1;
7565 unsigned SSP1DATPPS1
: 1;
7566 unsigned SSP1DATPPS2
: 1;
7567 unsigned SSP1DATPPS3
: 1;
7568 unsigned SSP1DATPPS4
: 1;
7576 unsigned SSP1DATPPS
: 5;
7579 } __SSP1DATPPSbits_t
;
7581 extern __at(0x0E21) volatile __SSP1DATPPSbits_t SSP1DATPPSbits
;
7583 #define _SSP1DATPPS0 0x01
7584 #define _SSP1DATPPS1 0x02
7585 #define _SSP1DATPPS2 0x04
7586 #define _SSP1DATPPS3 0x08
7587 #define _SSP1DATPPS4 0x10
7589 //==============================================================================
7592 //==============================================================================
7595 extern __at(0x0E22) __sfr SSP1SSPPS
;
7601 unsigned SSP1SSPPS0
: 1;
7602 unsigned SSP1SSPPS1
: 1;
7603 unsigned SSP1SSPPS2
: 1;
7604 unsigned SSP1SSPPS3
: 1;
7605 unsigned SSP1SSPPS4
: 1;
7613 unsigned SSP1SSPPS
: 5;
7616 } __SSP1SSPPSbits_t
;
7618 extern __at(0x0E22) volatile __SSP1SSPPSbits_t SSP1SSPPSbits
;
7620 #define _SSP1SSPPS0 0x01
7621 #define _SSP1SSPPS1 0x02
7622 #define _SSP1SSPPS2 0x04
7623 #define _SSP1SSPPS3 0x08
7624 #define _SSP1SSPPS4 0x10
7626 //==============================================================================
7629 //==============================================================================
7632 extern __at(0x0E24) __sfr RXPPS
;
7638 unsigned RXDTPPS0
: 1;
7639 unsigned RXDTPPS1
: 1;
7640 unsigned RXDTPPS2
: 1;
7641 unsigned RXDTPPS3
: 1;
7642 unsigned RXDTPPS4
: 1;
7650 unsigned RXDTPPS
: 5;
7655 extern __at(0x0E24) volatile __RXPPSbits_t RXPPSbits
;
7657 #define _RXDTPPS0 0x01
7658 #define _RXDTPPS1 0x02
7659 #define _RXDTPPS2 0x04
7660 #define _RXDTPPS3 0x08
7661 #define _RXDTPPS4 0x10
7663 //==============================================================================
7666 //==============================================================================
7669 extern __at(0x0E25) __sfr TXPPS
;
7675 unsigned TXCKPPS0
: 1;
7676 unsigned TXCKPPS1
: 1;
7677 unsigned TXCKPPS2
: 1;
7678 unsigned TXCKPPS3
: 1;
7679 unsigned TXCKPPS4
: 1;
7687 unsigned TXCKPPS
: 5;
7692 extern __at(0x0E25) volatile __TXPPSbits_t TXPPSbits
;
7694 #define _TXCKPPS0 0x01
7695 #define _TXCKPPS1 0x02
7696 #define _TXCKPPS2 0x04
7697 #define _TXCKPPS3 0x08
7698 #define _TXCKPPS4 0x10
7700 //==============================================================================
7703 //==============================================================================
7706 extern __at(0x0E28) __sfr CLCIN0PPS
;
7712 unsigned CLCIN0PPS0
: 1;
7713 unsigned CLCIN0PPS1
: 1;
7714 unsigned CLCIN0PPS2
: 1;
7715 unsigned CLCIN0PPS3
: 1;
7716 unsigned CLCIN0PPS4
: 1;
7724 unsigned CLCIN0PPS
: 5;
7727 } __CLCIN0PPSbits_t
;
7729 extern __at(0x0E28) volatile __CLCIN0PPSbits_t CLCIN0PPSbits
;
7731 #define _CLCIN0PPS0 0x01
7732 #define _CLCIN0PPS1 0x02
7733 #define _CLCIN0PPS2 0x04
7734 #define _CLCIN0PPS3 0x08
7735 #define _CLCIN0PPS4 0x10
7737 //==============================================================================
7740 //==============================================================================
7743 extern __at(0x0E29) __sfr CLCIN1PPS
;
7749 unsigned CLCIN1PPS0
: 1;
7750 unsigned CLCIN1PPS1
: 1;
7751 unsigned CLCIN1PPS2
: 1;
7752 unsigned CLCIN1PPS3
: 1;
7753 unsigned CLCIN1PPS4
: 1;
7761 unsigned CLCIN1PPS
: 5;
7764 } __CLCIN1PPSbits_t
;
7766 extern __at(0x0E29) volatile __CLCIN1PPSbits_t CLCIN1PPSbits
;
7768 #define _CLCIN1PPS0 0x01
7769 #define _CLCIN1PPS1 0x02
7770 #define _CLCIN1PPS2 0x04
7771 #define _CLCIN1PPS3 0x08
7772 #define _CLCIN1PPS4 0x10
7774 //==============================================================================
7777 //==============================================================================
7780 extern __at(0x0E2A) __sfr CLCIN2PPS
;
7786 unsigned CLCIN2PPS0
: 1;
7787 unsigned CLCIN2PPS1
: 1;
7788 unsigned CLCIN2PPS2
: 1;
7789 unsigned CLCIN2PPS3
: 1;
7790 unsigned CLCIN2PPS4
: 1;
7798 unsigned CLCIN2PPS
: 5;
7801 } __CLCIN2PPSbits_t
;
7803 extern __at(0x0E2A) volatile __CLCIN2PPSbits_t CLCIN2PPSbits
;
7805 #define _CLCIN2PPS0 0x01
7806 #define _CLCIN2PPS1 0x02
7807 #define _CLCIN2PPS2 0x04
7808 #define _CLCIN2PPS3 0x08
7809 #define _CLCIN2PPS4 0x10
7811 //==============================================================================
7814 //==============================================================================
7817 extern __at(0x0E2B) __sfr CLCIN3PPS
;
7823 unsigned CLCIN3PPS0
: 1;
7824 unsigned CLCIN3PPS1
: 1;
7825 unsigned CLCIN3PPS2
: 1;
7826 unsigned CLCIN3PPS3
: 1;
7827 unsigned CLCIN3PPS4
: 1;
7835 unsigned CLCIN3PPS
: 5;
7838 } __CLCIN3PPSbits_t
;
7840 extern __at(0x0E2B) volatile __CLCIN3PPSbits_t CLCIN3PPSbits
;
7842 #define _CLCIN3PPS0 0x01
7843 #define _CLCIN3PPS1 0x02
7844 #define _CLCIN3PPS2 0x04
7845 #define _CLCIN3PPS3 0x08
7846 #define _CLCIN3PPS4 0x10
7848 //==============================================================================
7850 extern __at(0x0E2C) __sfr T3CKIPPS
;
7851 extern __at(0x0E2D) __sfr T3GPPS
;
7852 extern __at(0x0E2E) __sfr T5CKIPPS
;
7853 extern __at(0x0E2F) __sfr T5GPPS
;
7855 //==============================================================================
7858 extern __at(0x0E90) __sfr RA0PPS
;
7864 unsigned RA0PPS0
: 1;
7865 unsigned RA0PPS1
: 1;
7866 unsigned RA0PPS2
: 1;
7867 unsigned RA0PPS3
: 1;
7868 unsigned RA0PPS4
: 1;
7876 unsigned RA0PPS
: 5;
7881 extern __at(0x0E90) volatile __RA0PPSbits_t RA0PPSbits
;
7883 #define _RA0PPS0 0x01
7884 #define _RA0PPS1 0x02
7885 #define _RA0PPS2 0x04
7886 #define _RA0PPS3 0x08
7887 #define _RA0PPS4 0x10
7889 //==============================================================================
7892 //==============================================================================
7895 extern __at(0x0E91) __sfr RA1PPS
;
7901 unsigned RA1PPS0
: 1;
7902 unsigned RA1PPS1
: 1;
7903 unsigned RA1PPS2
: 1;
7904 unsigned RA1PPS3
: 1;
7905 unsigned RA1PPS4
: 1;
7913 unsigned RA1PPS
: 5;
7918 extern __at(0x0E91) volatile __RA1PPSbits_t RA1PPSbits
;
7920 #define _RA1PPS0 0x01
7921 #define _RA1PPS1 0x02
7922 #define _RA1PPS2 0x04
7923 #define _RA1PPS3 0x08
7924 #define _RA1PPS4 0x10
7926 //==============================================================================
7929 //==============================================================================
7932 extern __at(0x0E92) __sfr RA2PPS
;
7938 unsigned RA2PPS0
: 1;
7939 unsigned RA2PPS1
: 1;
7940 unsigned RA2PPS2
: 1;
7941 unsigned RA2PPS3
: 1;
7942 unsigned RA2PPS4
: 1;
7950 unsigned RA2PPS
: 5;
7955 extern __at(0x0E92) volatile __RA2PPSbits_t RA2PPSbits
;
7957 #define _RA2PPS0 0x01
7958 #define _RA2PPS1 0x02
7959 #define _RA2PPS2 0x04
7960 #define _RA2PPS3 0x08
7961 #define _RA2PPS4 0x10
7963 //==============================================================================
7966 //==============================================================================
7969 extern __at(0x0E94) __sfr RA4PPS
;
7975 unsigned RA4PPS0
: 1;
7976 unsigned RA4PPS1
: 1;
7977 unsigned RA4PPS2
: 1;
7978 unsigned RA4PPS3
: 1;
7979 unsigned RA4PPS4
: 1;
7987 unsigned RA4PPS
: 5;
7992 extern __at(0x0E94) volatile __RA4PPSbits_t RA4PPSbits
;
7994 #define _RA4PPS0 0x01
7995 #define _RA4PPS1 0x02
7996 #define _RA4PPS2 0x04
7997 #define _RA4PPS3 0x08
7998 #define _RA4PPS4 0x10
8000 //==============================================================================
8003 //==============================================================================
8006 extern __at(0x0E95) __sfr RA5PPS
;
8012 unsigned RA5PPS0
: 1;
8013 unsigned RA5PPS1
: 1;
8014 unsigned RA5PPS2
: 1;
8015 unsigned RA5PPS3
: 1;
8016 unsigned RA5PPS4
: 1;
8024 unsigned RA5PPS
: 5;
8029 extern __at(0x0E95) volatile __RA5PPSbits_t RA5PPSbits
;
8031 #define _RA5PPS0 0x01
8032 #define _RA5PPS1 0x02
8033 #define _RA5PPS2 0x04
8034 #define _RA5PPS3 0x08
8035 #define _RA5PPS4 0x10
8037 //==============================================================================
8040 //==============================================================================
8043 extern __at(0x0E9C) __sfr RB4PPS
;
8049 unsigned RB4PPS0
: 1;
8050 unsigned RB4PPS1
: 1;
8051 unsigned RB4PPS2
: 1;
8052 unsigned RB4PPS3
: 1;
8053 unsigned RB4PPS4
: 1;
8061 unsigned RB4PPS
: 5;
8066 extern __at(0x0E9C) volatile __RB4PPSbits_t RB4PPSbits
;
8068 #define _RB4PPS0 0x01
8069 #define _RB4PPS1 0x02
8070 #define _RB4PPS2 0x04
8071 #define _RB4PPS3 0x08
8072 #define _RB4PPS4 0x10
8074 //==============================================================================
8077 //==============================================================================
8080 extern __at(0x0E9D) __sfr RB5PPS
;
8086 unsigned RB5PPS0
: 1;
8087 unsigned RB5PPS1
: 1;
8088 unsigned RB5PPS2
: 1;
8089 unsigned RB5PPS3
: 1;
8090 unsigned RB5PPS4
: 1;
8098 unsigned RB5PPS
: 5;
8103 extern __at(0x0E9D) volatile __RB5PPSbits_t RB5PPSbits
;
8105 #define _RB5PPS0 0x01
8106 #define _RB5PPS1 0x02
8107 #define _RB5PPS2 0x04
8108 #define _RB5PPS3 0x08
8109 #define _RB5PPS4 0x10
8111 //==============================================================================
8114 //==============================================================================
8117 extern __at(0x0E9E) __sfr RB6PPS
;
8123 unsigned RB6PPS0
: 1;
8124 unsigned RB6PPS1
: 1;
8125 unsigned RB6PPS2
: 1;
8126 unsigned RB6PPS3
: 1;
8127 unsigned RB6PPS4
: 1;
8135 unsigned RB6PPS
: 5;
8140 extern __at(0x0E9E) volatile __RB6PPSbits_t RB6PPSbits
;
8142 #define _RB6PPS0 0x01
8143 #define _RB6PPS1 0x02
8144 #define _RB6PPS2 0x04
8145 #define _RB6PPS3 0x08
8146 #define _RB6PPS4 0x10
8148 //==============================================================================
8151 //==============================================================================
8154 extern __at(0x0E9F) __sfr RB7PPS
;
8160 unsigned RB7PPS0
: 1;
8161 unsigned RB7PPS1
: 1;
8162 unsigned RB7PPS2
: 1;
8163 unsigned RB7PPS3
: 1;
8164 unsigned RB7PPS4
: 1;
8172 unsigned RB7PPS
: 5;
8177 extern __at(0x0E9F) volatile __RB7PPSbits_t RB7PPSbits
;
8179 #define _RB7PPS0 0x01
8180 #define _RB7PPS1 0x02
8181 #define _RB7PPS2 0x04
8182 #define _RB7PPS3 0x08
8183 #define _RB7PPS4 0x10
8185 //==============================================================================
8188 //==============================================================================
8191 extern __at(0x0EA0) __sfr RC0PPS
;
8197 unsigned RC0PPS0
: 1;
8198 unsigned RC0PPS1
: 1;
8199 unsigned RC0PPS2
: 1;
8200 unsigned RC0PPS3
: 1;
8201 unsigned RC0PPS4
: 1;
8209 unsigned RC0PPS
: 5;
8214 extern __at(0x0EA0) volatile __RC0PPSbits_t RC0PPSbits
;
8216 #define _RC0PPS0 0x01
8217 #define _RC0PPS1 0x02
8218 #define _RC0PPS2 0x04
8219 #define _RC0PPS3 0x08
8220 #define _RC0PPS4 0x10
8222 //==============================================================================
8225 //==============================================================================
8228 extern __at(0x0EA1) __sfr RC1PPS
;
8234 unsigned RC1PPS0
: 1;
8235 unsigned RC1PPS1
: 1;
8236 unsigned RC1PPS2
: 1;
8237 unsigned RC1PPS3
: 1;
8238 unsigned RC1PPS4
: 1;
8246 unsigned RC1PPS
: 5;
8251 extern __at(0x0EA1) volatile __RC1PPSbits_t RC1PPSbits
;
8253 #define _RC1PPS0 0x01
8254 #define _RC1PPS1 0x02
8255 #define _RC1PPS2 0x04
8256 #define _RC1PPS3 0x08
8257 #define _RC1PPS4 0x10
8259 //==============================================================================
8262 //==============================================================================
8265 extern __at(0x0EA2) __sfr RC2PPS
;
8271 unsigned RC2PPS0
: 1;
8272 unsigned RC2PPS1
: 1;
8273 unsigned RC2PPS2
: 1;
8274 unsigned RC2PPS3
: 1;
8275 unsigned RC2PPS4
: 1;
8283 unsigned RC2PPS
: 5;
8288 extern __at(0x0EA2) volatile __RC2PPSbits_t RC2PPSbits
;
8290 #define _RC2PPS0 0x01
8291 #define _RC2PPS1 0x02
8292 #define _RC2PPS2 0x04
8293 #define _RC2PPS3 0x08
8294 #define _RC2PPS4 0x10
8296 //==============================================================================
8299 //==============================================================================
8302 extern __at(0x0EA3) __sfr RC3PPS
;
8308 unsigned RC3PPS0
: 1;
8309 unsigned RC3PPS1
: 1;
8310 unsigned RC3PPS2
: 1;
8311 unsigned RC3PPS3
: 1;
8312 unsigned RC3PPS4
: 1;
8320 unsigned RC3PPS
: 5;
8325 extern __at(0x0EA3) volatile __RC3PPSbits_t RC3PPSbits
;
8327 #define _RC3PPS0 0x01
8328 #define _RC3PPS1 0x02
8329 #define _RC3PPS2 0x04
8330 #define _RC3PPS3 0x08
8331 #define _RC3PPS4 0x10
8333 //==============================================================================
8336 //==============================================================================
8339 extern __at(0x0EA4) __sfr RC4PPS
;
8345 unsigned RC4PPS0
: 1;
8346 unsigned RC4PPS1
: 1;
8347 unsigned RC4PPS2
: 1;
8348 unsigned RC4PPS3
: 1;
8349 unsigned RC4PPS4
: 1;
8357 unsigned RC4PPS
: 5;
8362 extern __at(0x0EA4) volatile __RC4PPSbits_t RC4PPSbits
;
8364 #define _RC4PPS0 0x01
8365 #define _RC4PPS1 0x02
8366 #define _RC4PPS2 0x04
8367 #define _RC4PPS3 0x08
8368 #define _RC4PPS4 0x10
8370 //==============================================================================
8373 //==============================================================================
8376 extern __at(0x0EA5) __sfr RC5PPS
;
8382 unsigned RC5PPS0
: 1;
8383 unsigned RC5PPS1
: 1;
8384 unsigned RC5PPS2
: 1;
8385 unsigned RC5PPS3
: 1;
8386 unsigned RC5PPS4
: 1;
8394 unsigned RC5PPS
: 5;
8399 extern __at(0x0EA5) volatile __RC5PPSbits_t RC5PPSbits
;
8401 #define _RC5PPS0 0x01
8402 #define _RC5PPS1 0x02
8403 #define _RC5PPS2 0x04
8404 #define _RC5PPS3 0x08
8405 #define _RC5PPS4 0x10
8407 //==============================================================================
8410 //==============================================================================
8413 extern __at(0x0EA6) __sfr RC6PPS
;
8419 unsigned RC6PPS0
: 1;
8420 unsigned RC6PPS1
: 1;
8421 unsigned RC6PPS2
: 1;
8422 unsigned RC6PPS3
: 1;
8423 unsigned RC6PPS4
: 1;
8431 unsigned RC6PPS
: 5;
8436 extern __at(0x0EA6) volatile __RC6PPSbits_t RC6PPSbits
;
8438 #define _RC6PPS0 0x01
8439 #define _RC6PPS1 0x02
8440 #define _RC6PPS2 0x04
8441 #define _RC6PPS3 0x08
8442 #define _RC6PPS4 0x10
8444 //==============================================================================
8447 //==============================================================================
8450 extern __at(0x0EA7) __sfr RC7PPS
;
8456 unsigned RC7PPS0
: 1;
8457 unsigned RC7PPS1
: 1;
8458 unsigned RC7PPS2
: 1;
8459 unsigned RC7PPS3
: 1;
8460 unsigned RC7PPS4
: 1;
8468 unsigned RC7PPS
: 5;
8473 extern __at(0x0EA7) volatile __RC7PPSbits_t RC7PPSbits
;
8475 #define _RC7PPS0 0x01
8476 #define _RC7PPS1 0x02
8477 #define _RC7PPS2 0x04
8478 #define _RC7PPS3 0x08
8479 #define _RC7PPS4 0x10
8481 //==============================================================================
8484 //==============================================================================
8487 extern __at(0x0F0F) __sfr CLCDATA
;
8491 unsigned MLC1OUT
: 1;
8492 unsigned MLC2OUT
: 1;
8493 unsigned MLC3OUT
: 1;
8494 unsigned MLC4OUT
: 1;
8501 extern __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits
;
8503 #define _MLC1OUT 0x01
8504 #define _MLC2OUT 0x02
8505 #define _MLC3OUT 0x04
8506 #define _MLC4OUT 0x08
8508 //==============================================================================
8511 //==============================================================================
8514 extern __at(0x0F10) __sfr CLC1CON
;
8520 unsigned LC1MODE0
: 1;
8521 unsigned LC1MODE1
: 1;
8522 unsigned LC1MODE2
: 1;
8523 unsigned LC1INTN
: 1;
8524 unsigned LC1INTP
: 1;
8525 unsigned LC1OUT
: 1;
8550 unsigned LC1MODE
: 3;
8555 extern __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits
;
8557 #define _LC1MODE0 0x01
8559 #define _LC1MODE1 0x02
8561 #define _LC1MODE2 0x04
8563 #define _LC1INTN 0x08
8565 #define _LC1INTP 0x10
8567 #define _LC1OUT 0x20
8572 //==============================================================================
8575 //==============================================================================
8578 extern __at(0x0F11) __sfr CLC1POL
;
8584 unsigned LC1G1POL
: 1;
8585 unsigned LC1G2POL
: 1;
8586 unsigned LC1G3POL
: 1;
8587 unsigned LC1G4POL
: 1;
8591 unsigned LC1POL
: 1;
8607 extern __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits
;
8609 #define _LC1G1POL 0x01
8611 #define _LC1G2POL 0x02
8613 #define _LC1G3POL 0x04
8615 #define _LC1G4POL 0x08
8617 #define _LC1POL 0x80
8620 //==============================================================================
8623 //==============================================================================
8626 extern __at(0x0F12) __sfr CLC1SEL0
;
8632 unsigned LC1D1S0
: 1;
8633 unsigned LC1D1S1
: 1;
8634 unsigned LC1D1S2
: 1;
8635 unsigned LC1D1S3
: 1;
8636 unsigned LC1D1S4
: 1;
8637 unsigned LC1D1S5
: 1;
8662 unsigned LC1D1S
: 6;
8667 extern __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits
;
8669 #define _LC1D1S0 0x01
8671 #define _LC1D1S1 0x02
8673 #define _LC1D1S2 0x04
8675 #define _LC1D1S3 0x08
8677 #define _LC1D1S4 0x10
8679 #define _LC1D1S5 0x20
8682 //==============================================================================
8685 //==============================================================================
8688 extern __at(0x0F13) __sfr CLC1SEL1
;
8694 unsigned LC1D2S0
: 1;
8695 unsigned LC1D2S1
: 1;
8696 unsigned LC1D2S2
: 1;
8697 unsigned LC1D2S3
: 1;
8698 unsigned LC1D2S4
: 1;
8699 unsigned LC1D2S5
: 1;
8718 unsigned LC1D2S
: 6;
8729 extern __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits
;
8731 #define _LC1D2S0 0x01
8733 #define _LC1D2S1 0x02
8735 #define _LC1D2S2 0x04
8737 #define _LC1D2S3 0x08
8739 #define _LC1D2S4 0x10
8741 #define _LC1D2S5 0x20
8744 //==============================================================================
8747 //==============================================================================
8750 extern __at(0x0F14) __sfr CLC1SEL2
;
8756 unsigned LC1D3S0
: 1;
8757 unsigned LC1D3S1
: 1;
8758 unsigned LC1D3S2
: 1;
8759 unsigned LC1D3S3
: 1;
8760 unsigned LC1D3S4
: 1;
8761 unsigned LC1D3S5
: 1;
8780 unsigned LC1D3S
: 6;
8791 extern __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits
;
8793 #define _LC1D3S0 0x01
8795 #define _LC1D3S1 0x02
8797 #define _LC1D3S2 0x04
8799 #define _LC1D3S3 0x08
8801 #define _LC1D3S4 0x10
8803 #define _LC1D3S5 0x20
8806 //==============================================================================
8809 //==============================================================================
8812 extern __at(0x0F15) __sfr CLC1SEL3
;
8818 unsigned LC1D4S0
: 1;
8819 unsigned LC1D4S1
: 1;
8820 unsigned LC1D4S2
: 1;
8821 unsigned LC1D4S3
: 1;
8822 unsigned LC1D4S4
: 1;
8823 unsigned LC1D4S5
: 1;
8848 unsigned LC1D4S
: 6;
8853 extern __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits
;
8855 #define _LC1D4S0 0x01
8857 #define _LC1D4S1 0x02
8859 #define _LC1D4S2 0x04
8861 #define _LC1D4S3 0x08
8863 #define _LC1D4S4 0x10
8865 #define _LC1D4S5 0x20
8868 //==============================================================================
8871 //==============================================================================
8874 extern __at(0x0F16) __sfr CLC1GLS0
;
8880 unsigned LC1G1D1N
: 1;
8881 unsigned LC1G1D1T
: 1;
8882 unsigned LC1G1D2N
: 1;
8883 unsigned LC1G1D2T
: 1;
8884 unsigned LC1G1D3N
: 1;
8885 unsigned LC1G1D3T
: 1;
8886 unsigned LC1G1D4N
: 1;
8887 unsigned LC1G1D4T
: 1;
8903 extern __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits
;
8905 #define _LC1G1D1N 0x01
8907 #define _LC1G1D1T 0x02
8909 #define _LC1G1D2N 0x04
8911 #define _LC1G1D2T 0x08
8913 #define _LC1G1D3N 0x10
8915 #define _LC1G1D3T 0x20
8917 #define _LC1G1D4N 0x40
8919 #define _LC1G1D4T 0x80
8922 //==============================================================================
8925 //==============================================================================
8928 extern __at(0x0F17) __sfr CLC1GLS1
;
8934 unsigned LC1G2D1N
: 1;
8935 unsigned LC1G2D1T
: 1;
8936 unsigned LC1G2D2N
: 1;
8937 unsigned LC1G2D2T
: 1;
8938 unsigned LC1G2D3N
: 1;
8939 unsigned LC1G2D3T
: 1;
8940 unsigned LC1G2D4N
: 1;
8941 unsigned LC1G2D4T
: 1;
8957 extern __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits
;
8959 #define _CLC1GLS1_LC1G2D1N 0x01
8960 #define _CLC1GLS1_D1N 0x01
8961 #define _CLC1GLS1_LC1G2D1T 0x02
8962 #define _CLC1GLS1_D1T 0x02
8963 #define _CLC1GLS1_LC1G2D2N 0x04
8964 #define _CLC1GLS1_D2N 0x04
8965 #define _CLC1GLS1_LC1G2D2T 0x08
8966 #define _CLC1GLS1_D2T 0x08
8967 #define _CLC1GLS1_LC1G2D3N 0x10
8968 #define _CLC1GLS1_D3N 0x10
8969 #define _CLC1GLS1_LC1G2D3T 0x20
8970 #define _CLC1GLS1_D3T 0x20
8971 #define _CLC1GLS1_LC1G2D4N 0x40
8972 #define _CLC1GLS1_D4N 0x40
8973 #define _CLC1GLS1_LC1G2D4T 0x80
8974 #define _CLC1GLS1_D4T 0x80
8976 //==============================================================================
8979 //==============================================================================
8982 extern __at(0x0F18) __sfr CLC1GLS2
;
8988 unsigned LC1G3D1N
: 1;
8989 unsigned LC1G3D1T
: 1;
8990 unsigned LC1G3D2N
: 1;
8991 unsigned LC1G3D2T
: 1;
8992 unsigned LC1G3D3N
: 1;
8993 unsigned LC1G3D3T
: 1;
8994 unsigned LC1G3D4N
: 1;
8995 unsigned LC1G3D4T
: 1;
9011 extern __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits
;
9013 #define _CLC1GLS2_LC1G3D1N 0x01
9014 #define _CLC1GLS2_D1N 0x01
9015 #define _CLC1GLS2_LC1G3D1T 0x02
9016 #define _CLC1GLS2_D1T 0x02
9017 #define _CLC1GLS2_LC1G3D2N 0x04
9018 #define _CLC1GLS2_D2N 0x04
9019 #define _CLC1GLS2_LC1G3D2T 0x08
9020 #define _CLC1GLS2_D2T 0x08
9021 #define _CLC1GLS2_LC1G3D3N 0x10
9022 #define _CLC1GLS2_D3N 0x10
9023 #define _CLC1GLS2_LC1G3D3T 0x20
9024 #define _CLC1GLS2_D3T 0x20
9025 #define _CLC1GLS2_LC1G3D4N 0x40
9026 #define _CLC1GLS2_D4N 0x40
9027 #define _CLC1GLS2_LC1G3D4T 0x80
9028 #define _CLC1GLS2_D4T 0x80
9030 //==============================================================================
9033 //==============================================================================
9036 extern __at(0x0F19) __sfr CLC1GLS3
;
9042 unsigned LC1G4D1N
: 1;
9043 unsigned LC1G4D1T
: 1;
9044 unsigned LC1G4D2N
: 1;
9045 unsigned LC1G4D2T
: 1;
9046 unsigned LC1G4D3N
: 1;
9047 unsigned LC1G4D3T
: 1;
9048 unsigned LC1G4D4N
: 1;
9049 unsigned LC1G4D4T
: 1;
9065 extern __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits
;
9067 #define _LC1G4D1N 0x01
9069 #define _LC1G4D1T 0x02
9071 #define _LC1G4D2N 0x04
9073 #define _LC1G4D2T 0x08
9075 #define _LC1G4D3N 0x10
9077 #define _LC1G4D3T 0x20
9079 #define _LC1G4D4N 0x40
9081 #define _LC1G4D4T 0x80
9084 //==============================================================================
9087 //==============================================================================
9090 extern __at(0x0F1A) __sfr CLC2CON
;
9096 unsigned LC2MODE0
: 1;
9097 unsigned LC2MODE1
: 1;
9098 unsigned LC2MODE2
: 1;
9099 unsigned LC2INTN
: 1;
9100 unsigned LC2INTP
: 1;
9101 unsigned LC2OUT
: 1;
9126 unsigned LC2MODE
: 3;
9131 extern __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits
;
9133 #define _CLC2CON_LC2MODE0 0x01
9134 #define _CLC2CON_MODE0 0x01
9135 #define _CLC2CON_LC2MODE1 0x02
9136 #define _CLC2CON_MODE1 0x02
9137 #define _CLC2CON_LC2MODE2 0x04
9138 #define _CLC2CON_MODE2 0x04
9139 #define _CLC2CON_LC2INTN 0x08
9140 #define _CLC2CON_INTN 0x08
9141 #define _CLC2CON_LC2INTP 0x10
9142 #define _CLC2CON_INTP 0x10
9143 #define _CLC2CON_LC2OUT 0x20
9144 #define _CLC2CON_OUT 0x20
9145 #define _CLC2CON_LC2EN 0x80
9146 #define _CLC2CON_EN 0x80
9148 //==============================================================================
9151 //==============================================================================
9154 extern __at(0x0F1B) __sfr CLC2POL
;
9160 unsigned LC2G1POL
: 1;
9161 unsigned LC2G2POL
: 1;
9162 unsigned LC2G3POL
: 1;
9163 unsigned LC2G4POL
: 1;
9167 unsigned LC2POL
: 1;
9183 extern __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits
;
9185 #define _CLC2POL_LC2G1POL 0x01
9186 #define _CLC2POL_G1POL 0x01
9187 #define _CLC2POL_LC2G2POL 0x02
9188 #define _CLC2POL_G2POL 0x02
9189 #define _CLC2POL_LC2G3POL 0x04
9190 #define _CLC2POL_G3POL 0x04
9191 #define _CLC2POL_LC2G4POL 0x08
9192 #define _CLC2POL_G4POL 0x08
9193 #define _CLC2POL_LC2POL 0x80
9194 #define _CLC2POL_POL 0x80
9196 //==============================================================================
9199 //==============================================================================
9202 extern __at(0x0F1C) __sfr CLC2SEL0
;
9208 unsigned LC2D1S0
: 1;
9209 unsigned LC2D1S1
: 1;
9210 unsigned LC2D1S2
: 1;
9211 unsigned LC2D1S3
: 1;
9212 unsigned LC2D1S4
: 1;
9213 unsigned LC2D1S5
: 1;
9232 unsigned LC2D1S
: 6;
9243 extern __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits
;
9245 #define _CLC2SEL0_LC2D1S0 0x01
9246 #define _CLC2SEL0_D1S0 0x01
9247 #define _CLC2SEL0_LC2D1S1 0x02
9248 #define _CLC2SEL0_D1S1 0x02
9249 #define _CLC2SEL0_LC2D1S2 0x04
9250 #define _CLC2SEL0_D1S2 0x04
9251 #define _CLC2SEL0_LC2D1S3 0x08
9252 #define _CLC2SEL0_D1S3 0x08
9253 #define _CLC2SEL0_LC2D1S4 0x10
9254 #define _CLC2SEL0_D1S4 0x10
9255 #define _CLC2SEL0_LC2D1S5 0x20
9256 #define _CLC2SEL0_D1S5 0x20
9258 //==============================================================================
9261 //==============================================================================
9264 extern __at(0x0F1D) __sfr CLC2SEL1
;
9270 unsigned LC2D2S0
: 1;
9271 unsigned LC2D2S1
: 1;
9272 unsigned LC2D2S2
: 1;
9273 unsigned LC2D2S3
: 1;
9274 unsigned LC2D2S4
: 1;
9275 unsigned LC2D2S5
: 1;
9294 unsigned LC2D2S
: 6;
9305 extern __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits
;
9307 #define _CLC2SEL1_LC2D2S0 0x01
9308 #define _CLC2SEL1_D2S0 0x01
9309 #define _CLC2SEL1_LC2D2S1 0x02
9310 #define _CLC2SEL1_D2S1 0x02
9311 #define _CLC2SEL1_LC2D2S2 0x04
9312 #define _CLC2SEL1_D2S2 0x04
9313 #define _CLC2SEL1_LC2D2S3 0x08
9314 #define _CLC2SEL1_D2S3 0x08
9315 #define _CLC2SEL1_LC2D2S4 0x10
9316 #define _CLC2SEL1_D2S4 0x10
9317 #define _CLC2SEL1_LC2D2S5 0x20
9318 #define _CLC2SEL1_D2S5 0x20
9320 //==============================================================================
9323 //==============================================================================
9326 extern __at(0x0F1E) __sfr CLC2SEL2
;
9332 unsigned LC2D3S0
: 1;
9333 unsigned LC2D3S1
: 1;
9334 unsigned LC2D3S2
: 1;
9335 unsigned LC2D3S3
: 1;
9336 unsigned LC2D3S4
: 1;
9337 unsigned LC2D3S5
: 1;
9356 unsigned LC2D3S
: 6;
9367 extern __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits
;
9369 #define _CLC2SEL2_LC2D3S0 0x01
9370 #define _CLC2SEL2_D3S0 0x01
9371 #define _CLC2SEL2_LC2D3S1 0x02
9372 #define _CLC2SEL2_D3S1 0x02
9373 #define _CLC2SEL2_LC2D3S2 0x04
9374 #define _CLC2SEL2_D3S2 0x04
9375 #define _CLC2SEL2_LC2D3S3 0x08
9376 #define _CLC2SEL2_D3S3 0x08
9377 #define _CLC2SEL2_LC2D3S4 0x10
9378 #define _CLC2SEL2_D3S4 0x10
9379 #define _CLC2SEL2_LC2D3S5 0x20
9380 #define _CLC2SEL2_D3S5 0x20
9382 //==============================================================================
9385 //==============================================================================
9388 extern __at(0x0F1F) __sfr CLC2SEL3
;
9394 unsigned LC2D4S0
: 1;
9395 unsigned LC2D4S1
: 1;
9396 unsigned LC2D4S2
: 1;
9397 unsigned LC2D4S3
: 1;
9398 unsigned LC2D4S4
: 1;
9399 unsigned LC2D4S5
: 1;
9418 unsigned LC2D4S
: 6;
9429 extern __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits
;
9431 #define _CLC2SEL3_LC2D4S0 0x01
9432 #define _CLC2SEL3_D4S0 0x01
9433 #define _CLC2SEL3_LC2D4S1 0x02
9434 #define _CLC2SEL3_D4S1 0x02
9435 #define _CLC2SEL3_LC2D4S2 0x04
9436 #define _CLC2SEL3_D4S2 0x04
9437 #define _CLC2SEL3_LC2D4S3 0x08
9438 #define _CLC2SEL3_D4S3 0x08
9439 #define _CLC2SEL3_LC2D4S4 0x10
9440 #define _CLC2SEL3_D4S4 0x10
9441 #define _CLC2SEL3_LC2D4S5 0x20
9442 #define _CLC2SEL3_D4S5 0x20
9444 //==============================================================================
9447 //==============================================================================
9450 extern __at(0x0F20) __sfr CLC2GLS0
;
9456 unsigned LC2G1D1N
: 1;
9457 unsigned LC2G1D1T
: 1;
9458 unsigned LC2G1D2N
: 1;
9459 unsigned LC2G1D2T
: 1;
9460 unsigned LC2G1D3N
: 1;
9461 unsigned LC2G1D3T
: 1;
9462 unsigned LC2G1D4N
: 1;
9463 unsigned LC2G1D4T
: 1;
9479 extern __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits
;
9481 #define _CLC2GLS0_LC2G1D1N 0x01
9482 #define _CLC2GLS0_D1N 0x01
9483 #define _CLC2GLS0_LC2G1D1T 0x02
9484 #define _CLC2GLS0_D1T 0x02
9485 #define _CLC2GLS0_LC2G1D2N 0x04
9486 #define _CLC2GLS0_D2N 0x04
9487 #define _CLC2GLS0_LC2G1D2T 0x08
9488 #define _CLC2GLS0_D2T 0x08
9489 #define _CLC2GLS0_LC2G1D3N 0x10
9490 #define _CLC2GLS0_D3N 0x10
9491 #define _CLC2GLS0_LC2G1D3T 0x20
9492 #define _CLC2GLS0_D3T 0x20
9493 #define _CLC2GLS0_LC2G1D4N 0x40
9494 #define _CLC2GLS0_D4N 0x40
9495 #define _CLC2GLS0_LC2G1D4T 0x80
9496 #define _CLC2GLS0_D4T 0x80
9498 //==============================================================================
9501 //==============================================================================
9504 extern __at(0x0F21) __sfr CLC2GLS1
;
9510 unsigned LC2G2D1N
: 1;
9511 unsigned LC2G2D1T
: 1;
9512 unsigned LC2G2D2N
: 1;
9513 unsigned LC2G2D2T
: 1;
9514 unsigned LC2G2D3N
: 1;
9515 unsigned LC2G2D3T
: 1;
9516 unsigned LC2G2D4N
: 1;
9517 unsigned LC2G2D4T
: 1;
9533 extern __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits
;
9535 #define _CLC2GLS1_LC2G2D1N 0x01
9536 #define _CLC2GLS1_D1N 0x01
9537 #define _CLC2GLS1_LC2G2D1T 0x02
9538 #define _CLC2GLS1_D1T 0x02
9539 #define _CLC2GLS1_LC2G2D2N 0x04
9540 #define _CLC2GLS1_D2N 0x04
9541 #define _CLC2GLS1_LC2G2D2T 0x08
9542 #define _CLC2GLS1_D2T 0x08
9543 #define _CLC2GLS1_LC2G2D3N 0x10
9544 #define _CLC2GLS1_D3N 0x10
9545 #define _CLC2GLS1_LC2G2D3T 0x20
9546 #define _CLC2GLS1_D3T 0x20
9547 #define _CLC2GLS1_LC2G2D4N 0x40
9548 #define _CLC2GLS1_D4N 0x40
9549 #define _CLC2GLS1_LC2G2D4T 0x80
9550 #define _CLC2GLS1_D4T 0x80
9552 //==============================================================================
9555 //==============================================================================
9558 extern __at(0x0F22) __sfr CLC2GLS2
;
9564 unsigned LC2G3D1N
: 1;
9565 unsigned LC2G3D1T
: 1;
9566 unsigned LC2G3D2N
: 1;
9567 unsigned LC2G3D2T
: 1;
9568 unsigned LC2G3D3N
: 1;
9569 unsigned LC2G3D3T
: 1;
9570 unsigned LC2G3D4N
: 1;
9571 unsigned LC2G3D4T
: 1;
9587 extern __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits
;
9589 #define _CLC2GLS2_LC2G3D1N 0x01
9590 #define _CLC2GLS2_D1N 0x01
9591 #define _CLC2GLS2_LC2G3D1T 0x02
9592 #define _CLC2GLS2_D1T 0x02
9593 #define _CLC2GLS2_LC2G3D2N 0x04
9594 #define _CLC2GLS2_D2N 0x04
9595 #define _CLC2GLS2_LC2G3D2T 0x08
9596 #define _CLC2GLS2_D2T 0x08
9597 #define _CLC2GLS2_LC2G3D3N 0x10
9598 #define _CLC2GLS2_D3N 0x10
9599 #define _CLC2GLS2_LC2G3D3T 0x20
9600 #define _CLC2GLS2_D3T 0x20
9601 #define _CLC2GLS2_LC2G3D4N 0x40
9602 #define _CLC2GLS2_D4N 0x40
9603 #define _CLC2GLS2_LC2G3D4T 0x80
9604 #define _CLC2GLS2_D4T 0x80
9606 //==============================================================================
9609 //==============================================================================
9612 extern __at(0x0F23) __sfr CLC2GLS3
;
9618 unsigned LC2G4D1N
: 1;
9619 unsigned LC2G4D1T
: 1;
9620 unsigned LC2G4D2N
: 1;
9621 unsigned LC2G4D2T
: 1;
9622 unsigned LC2G4D3N
: 1;
9623 unsigned LC2G4D3T
: 1;
9624 unsigned LC2G4D4N
: 1;
9625 unsigned LC2G4D4T
: 1;
9641 extern __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits
;
9643 #define _CLC2GLS3_LC2G4D1N 0x01
9644 #define _CLC2GLS3_G4D1N 0x01
9645 #define _CLC2GLS3_LC2G4D1T 0x02
9646 #define _CLC2GLS3_G4D1T 0x02
9647 #define _CLC2GLS3_LC2G4D2N 0x04
9648 #define _CLC2GLS3_G4D2N 0x04
9649 #define _CLC2GLS3_LC2G4D2T 0x08
9650 #define _CLC2GLS3_G4D2T 0x08
9651 #define _CLC2GLS3_LC2G4D3N 0x10
9652 #define _CLC2GLS3_G4D3N 0x10
9653 #define _CLC2GLS3_LC2G4D3T 0x20
9654 #define _CLC2GLS3_G4D3T 0x20
9655 #define _CLC2GLS3_LC2G4D4N 0x40
9656 #define _CLC2GLS3_G4D4N 0x40
9657 #define _CLC2GLS3_LC2G4D4T 0x80
9658 #define _CLC2GLS3_G4D4T 0x80
9660 //==============================================================================
9663 //==============================================================================
9666 extern __at(0x0F24) __sfr CLC3CON
;
9672 unsigned LC3MODE0
: 1;
9673 unsigned LC3MODE1
: 1;
9674 unsigned LC3MODE2
: 1;
9675 unsigned LC3INTN
: 1;
9676 unsigned LC3INTP
: 1;
9677 unsigned LC3OUT
: 1;
9702 unsigned LC3MODE
: 3;
9707 extern __at(0x0F24) volatile __CLC3CONbits_t CLC3CONbits
;
9709 #define _CLC3CON_LC3MODE0 0x01
9710 #define _CLC3CON_MODE0 0x01
9711 #define _CLC3CON_LC3MODE1 0x02
9712 #define _CLC3CON_MODE1 0x02
9713 #define _CLC3CON_LC3MODE2 0x04
9714 #define _CLC3CON_MODE2 0x04
9715 #define _CLC3CON_LC3INTN 0x08
9716 #define _CLC3CON_INTN 0x08
9717 #define _CLC3CON_LC3INTP 0x10
9718 #define _CLC3CON_INTP 0x10
9719 #define _CLC3CON_LC3OUT 0x20
9720 #define _CLC3CON_OUT 0x20
9721 #define _CLC3CON_LC3EN 0x80
9722 #define _CLC3CON_EN 0x80
9724 //==============================================================================
9727 //==============================================================================
9730 extern __at(0x0F25) __sfr CLC3POL
;
9736 unsigned LC3G1POL
: 1;
9737 unsigned LC3G2POL
: 1;
9738 unsigned LC3G3POL
: 1;
9739 unsigned LC3G4POL
: 1;
9743 unsigned LC3POL
: 1;
9759 extern __at(0x0F25) volatile __CLC3POLbits_t CLC3POLbits
;
9761 #define _CLC3POL_LC3G1POL 0x01
9762 #define _CLC3POL_G1POL 0x01
9763 #define _CLC3POL_LC3G2POL 0x02
9764 #define _CLC3POL_G2POL 0x02
9765 #define _CLC3POL_LC3G3POL 0x04
9766 #define _CLC3POL_G3POL 0x04
9767 #define _CLC3POL_LC3G4POL 0x08
9768 #define _CLC3POL_G4POL 0x08
9769 #define _CLC3POL_LC3POL 0x80
9770 #define _CLC3POL_POL 0x80
9772 //==============================================================================
9775 //==============================================================================
9778 extern __at(0x0F26) __sfr CLC3SEL0
;
9784 unsigned LC3D1S0
: 1;
9785 unsigned LC3D1S1
: 1;
9786 unsigned LC3D1S2
: 1;
9787 unsigned LC3D1S3
: 1;
9788 unsigned LC3D1S4
: 1;
9789 unsigned LC3D1S5
: 1;
9814 unsigned LC3D1S
: 6;
9819 extern __at(0x0F26) volatile __CLC3SEL0bits_t CLC3SEL0bits
;
9821 #define _CLC3SEL0_LC3D1S0 0x01
9822 #define _CLC3SEL0_D1S0 0x01
9823 #define _CLC3SEL0_LC3D1S1 0x02
9824 #define _CLC3SEL0_D1S1 0x02
9825 #define _CLC3SEL0_LC3D1S2 0x04
9826 #define _CLC3SEL0_D1S2 0x04
9827 #define _CLC3SEL0_LC3D1S3 0x08
9828 #define _CLC3SEL0_D1S3 0x08
9829 #define _CLC3SEL0_LC3D1S4 0x10
9830 #define _CLC3SEL0_D1S4 0x10
9831 #define _CLC3SEL0_LC3D1S5 0x20
9832 #define _CLC3SEL0_D1S5 0x20
9834 //==============================================================================
9837 //==============================================================================
9840 extern __at(0x0F27) __sfr CLC3SEL1
;
9846 unsigned LC3D2S0
: 1;
9847 unsigned LC3D2S1
: 1;
9848 unsigned LC3D2S2
: 1;
9849 unsigned LC3D2S3
: 1;
9850 unsigned LC3D2S4
: 1;
9851 unsigned LC3D2S5
: 1;
9870 unsigned LC3D2S
: 6;
9881 extern __at(0x0F27) volatile __CLC3SEL1bits_t CLC3SEL1bits
;
9883 #define _CLC3SEL1_LC3D2S0 0x01
9884 #define _CLC3SEL1_D2S0 0x01
9885 #define _CLC3SEL1_LC3D2S1 0x02
9886 #define _CLC3SEL1_D2S1 0x02
9887 #define _CLC3SEL1_LC3D2S2 0x04
9888 #define _CLC3SEL1_D2S2 0x04
9889 #define _CLC3SEL1_LC3D2S3 0x08
9890 #define _CLC3SEL1_D2S3 0x08
9891 #define _CLC3SEL1_LC3D2S4 0x10
9892 #define _CLC3SEL1_D2S4 0x10
9893 #define _CLC3SEL1_LC3D2S5 0x20
9894 #define _CLC3SEL1_D2S5 0x20
9896 //==============================================================================
9899 //==============================================================================
9902 extern __at(0x0F28) __sfr CLC3SEL2
;
9908 unsigned LC3D3S0
: 1;
9909 unsigned LC3D3S1
: 1;
9910 unsigned LC3D3S2
: 1;
9911 unsigned LC3D3S3
: 1;
9912 unsigned LC3D3S4
: 1;
9913 unsigned LC3D3S5
: 1;
9938 unsigned LC3D3S
: 6;
9943 extern __at(0x0F28) volatile __CLC3SEL2bits_t CLC3SEL2bits
;
9945 #define _CLC3SEL2_LC3D3S0 0x01
9946 #define _CLC3SEL2_D3S0 0x01
9947 #define _CLC3SEL2_LC3D3S1 0x02
9948 #define _CLC3SEL2_D3S1 0x02
9949 #define _CLC3SEL2_LC3D3S2 0x04
9950 #define _CLC3SEL2_D3S2 0x04
9951 #define _CLC3SEL2_LC3D3S3 0x08
9952 #define _CLC3SEL2_D3S3 0x08
9953 #define _CLC3SEL2_LC3D3S4 0x10
9954 #define _CLC3SEL2_D3S4 0x10
9955 #define _CLC3SEL2_LC3D3S5 0x20
9956 #define _CLC3SEL2_D3S5 0x20
9958 //==============================================================================
9961 //==============================================================================
9964 extern __at(0x0F29) __sfr CLC3SEL3
;
9970 unsigned LC3D4S0
: 1;
9971 unsigned LC3D4S1
: 1;
9972 unsigned LC3D4S2
: 1;
9973 unsigned LC3D4S3
: 1;
9974 unsigned LC3D4S4
: 1;
9975 unsigned LC3D4S5
: 1;
10000 unsigned LC3D4S
: 6;
10003 } __CLC3SEL3bits_t
;
10005 extern __at(0x0F29) volatile __CLC3SEL3bits_t CLC3SEL3bits
;
10007 #define _CLC3SEL3_LC3D4S0 0x01
10008 #define _CLC3SEL3_D4S0 0x01
10009 #define _CLC3SEL3_LC3D4S1 0x02
10010 #define _CLC3SEL3_D4S1 0x02
10011 #define _CLC3SEL3_LC3D4S2 0x04
10012 #define _CLC3SEL3_D4S2 0x04
10013 #define _CLC3SEL3_LC3D4S3 0x08
10014 #define _CLC3SEL3_D4S3 0x08
10015 #define _CLC3SEL3_LC3D4S4 0x10
10016 #define _CLC3SEL3_D4S4 0x10
10017 #define _CLC3SEL3_LC3D4S5 0x20
10018 #define _CLC3SEL3_D4S5 0x20
10020 //==============================================================================
10023 //==============================================================================
10026 extern __at(0x0F2A) __sfr CLC3GLS0
;
10032 unsigned LC3G1D1N
: 1;
10033 unsigned LC3G1D1T
: 1;
10034 unsigned LC3G1D2N
: 1;
10035 unsigned LC3G1D2T
: 1;
10036 unsigned LC3G1D3N
: 1;
10037 unsigned LC3G1D3T
: 1;
10038 unsigned LC3G1D4N
: 1;
10039 unsigned LC3G1D4T
: 1;
10053 } __CLC3GLS0bits_t
;
10055 extern __at(0x0F2A) volatile __CLC3GLS0bits_t CLC3GLS0bits
;
10057 #define _CLC3GLS0_LC3G1D1N 0x01
10058 #define _CLC3GLS0_D1N 0x01
10059 #define _CLC3GLS0_LC3G1D1T 0x02
10060 #define _CLC3GLS0_D1T 0x02
10061 #define _CLC3GLS0_LC3G1D2N 0x04
10062 #define _CLC3GLS0_D2N 0x04
10063 #define _CLC3GLS0_LC3G1D2T 0x08
10064 #define _CLC3GLS0_D2T 0x08
10065 #define _CLC3GLS0_LC3G1D3N 0x10
10066 #define _CLC3GLS0_D3N 0x10
10067 #define _CLC3GLS0_LC3G1D3T 0x20
10068 #define _CLC3GLS0_D3T 0x20
10069 #define _CLC3GLS0_LC3G1D4N 0x40
10070 #define _CLC3GLS0_D4N 0x40
10071 #define _CLC3GLS0_LC3G1D4T 0x80
10072 #define _CLC3GLS0_D4T 0x80
10074 //==============================================================================
10077 //==============================================================================
10080 extern __at(0x0F2B) __sfr CLC3GLS1
;
10086 unsigned LC3G2D1N
: 1;
10087 unsigned LC3G2D1T
: 1;
10088 unsigned LC3G2D2N
: 1;
10089 unsigned LC3G2D2T
: 1;
10090 unsigned LC3G2D3N
: 1;
10091 unsigned LC3G2D3T
: 1;
10092 unsigned LC3G2D4N
: 1;
10093 unsigned LC3G2D4T
: 1;
10107 } __CLC3GLS1bits_t
;
10109 extern __at(0x0F2B) volatile __CLC3GLS1bits_t CLC3GLS1bits
;
10111 #define _CLC3GLS1_LC3G2D1N 0x01
10112 #define _CLC3GLS1_D1N 0x01
10113 #define _CLC3GLS1_LC3G2D1T 0x02
10114 #define _CLC3GLS1_D1T 0x02
10115 #define _CLC3GLS1_LC3G2D2N 0x04
10116 #define _CLC3GLS1_D2N 0x04
10117 #define _CLC3GLS1_LC3G2D2T 0x08
10118 #define _CLC3GLS1_D2T 0x08
10119 #define _CLC3GLS1_LC3G2D3N 0x10
10120 #define _CLC3GLS1_D3N 0x10
10121 #define _CLC3GLS1_LC3G2D3T 0x20
10122 #define _CLC3GLS1_D3T 0x20
10123 #define _CLC3GLS1_LC3G2D4N 0x40
10124 #define _CLC3GLS1_D4N 0x40
10125 #define _CLC3GLS1_LC3G2D4T 0x80
10126 #define _CLC3GLS1_D4T 0x80
10128 //==============================================================================
10131 //==============================================================================
10134 extern __at(0x0F2C) __sfr CLC3GLS2
;
10140 unsigned LC3G3D1N
: 1;
10141 unsigned LC3G3D1T
: 1;
10142 unsigned LC3G3D2N
: 1;
10143 unsigned LC3G3D2T
: 1;
10144 unsigned LC3G3D3N
: 1;
10145 unsigned LC3G3D3T
: 1;
10146 unsigned LC3G3D4N
: 1;
10147 unsigned LC3G3D4T
: 1;
10161 } __CLC3GLS2bits_t
;
10163 extern __at(0x0F2C) volatile __CLC3GLS2bits_t CLC3GLS2bits
;
10165 #define _CLC3GLS2_LC3G3D1N 0x01
10166 #define _CLC3GLS2_D1N 0x01
10167 #define _CLC3GLS2_LC3G3D1T 0x02
10168 #define _CLC3GLS2_D1T 0x02
10169 #define _CLC3GLS2_LC3G3D2N 0x04
10170 #define _CLC3GLS2_D2N 0x04
10171 #define _CLC3GLS2_LC3G3D2T 0x08
10172 #define _CLC3GLS2_D2T 0x08
10173 #define _CLC3GLS2_LC3G3D3N 0x10
10174 #define _CLC3GLS2_D3N 0x10
10175 #define _CLC3GLS2_LC3G3D3T 0x20
10176 #define _CLC3GLS2_D3T 0x20
10177 #define _CLC3GLS2_LC3G3D4N 0x40
10178 #define _CLC3GLS2_D4N 0x40
10179 #define _CLC3GLS2_LC3G3D4T 0x80
10180 #define _CLC3GLS2_D4T 0x80
10182 //==============================================================================
10185 //==============================================================================
10188 extern __at(0x0F2D) __sfr CLC3GLS3
;
10194 unsigned LC3G4D1N
: 1;
10195 unsigned LC3G4D1T
: 1;
10196 unsigned LC3G4D2N
: 1;
10197 unsigned LC3G4D2T
: 1;
10198 unsigned LC3G4D3N
: 1;
10199 unsigned LC3G4D3T
: 1;
10200 unsigned LC3G4D4N
: 1;
10201 unsigned LC3G4D4T
: 1;
10206 unsigned G4D1N
: 1;
10207 unsigned G4D1T
: 1;
10208 unsigned G4D2N
: 1;
10209 unsigned G4D2T
: 1;
10210 unsigned G4D3N
: 1;
10211 unsigned G4D3T
: 1;
10212 unsigned G4D4N
: 1;
10213 unsigned G4D4T
: 1;
10215 } __CLC3GLS3bits_t
;
10217 extern __at(0x0F2D) volatile __CLC3GLS3bits_t CLC3GLS3bits
;
10219 #define _CLC3GLS3_LC3G4D1N 0x01
10220 #define _CLC3GLS3_G4D1N 0x01
10221 #define _CLC3GLS3_LC3G4D1T 0x02
10222 #define _CLC3GLS3_G4D1T 0x02
10223 #define _CLC3GLS3_LC3G4D2N 0x04
10224 #define _CLC3GLS3_G4D2N 0x04
10225 #define _CLC3GLS3_LC3G4D2T 0x08
10226 #define _CLC3GLS3_G4D2T 0x08
10227 #define _CLC3GLS3_LC3G4D3N 0x10
10228 #define _CLC3GLS3_G4D3N 0x10
10229 #define _CLC3GLS3_LC3G4D3T 0x20
10230 #define _CLC3GLS3_G4D3T 0x20
10231 #define _CLC3GLS3_LC3G4D4N 0x40
10232 #define _CLC3GLS3_G4D4N 0x40
10233 #define _CLC3GLS3_LC3G4D4T 0x80
10234 #define _CLC3GLS3_G4D4T 0x80
10236 //==============================================================================
10239 //==============================================================================
10242 extern __at(0x0F2E) __sfr CLC4CON
;
10248 unsigned LC4MODE0
: 1;
10249 unsigned LC4MODE1
: 1;
10250 unsigned LC4MODE2
: 1;
10251 unsigned LC4INTN
: 1;
10252 unsigned LC4INTP
: 1;
10253 unsigned LC4OUT
: 1;
10255 unsigned LC4EN
: 1;
10260 unsigned MODE0
: 1;
10261 unsigned MODE1
: 1;
10262 unsigned MODE2
: 1;
10272 unsigned LC4MODE
: 3;
10283 extern __at(0x0F2E) volatile __CLC4CONbits_t CLC4CONbits
;
10285 #define _CLC4CON_LC4MODE0 0x01
10286 #define _CLC4CON_MODE0 0x01
10287 #define _CLC4CON_LC4MODE1 0x02
10288 #define _CLC4CON_MODE1 0x02
10289 #define _CLC4CON_LC4MODE2 0x04
10290 #define _CLC4CON_MODE2 0x04
10291 #define _CLC4CON_LC4INTN 0x08
10292 #define _CLC4CON_INTN 0x08
10293 #define _CLC4CON_LC4INTP 0x10
10294 #define _CLC4CON_INTP 0x10
10295 #define _CLC4CON_LC4OUT 0x20
10296 #define _CLC4CON_OUT 0x20
10297 #define _CLC4CON_LC4EN 0x80
10298 #define _CLC4CON_EN 0x80
10300 //==============================================================================
10303 //==============================================================================
10306 extern __at(0x0F2F) __sfr CLC4POL
;
10312 unsigned LC4G1POL
: 1;
10313 unsigned LC4G2POL
: 1;
10314 unsigned LC4G3POL
: 1;
10315 unsigned LC4G4POL
: 1;
10319 unsigned LC4POL
: 1;
10324 unsigned G1POL
: 1;
10325 unsigned G2POL
: 1;
10326 unsigned G3POL
: 1;
10327 unsigned G4POL
: 1;
10335 extern __at(0x0F2F) volatile __CLC4POLbits_t CLC4POLbits
;
10337 #define _CLC4POL_LC4G1POL 0x01
10338 #define _CLC4POL_G1POL 0x01
10339 #define _CLC4POL_LC4G2POL 0x02
10340 #define _CLC4POL_G2POL 0x02
10341 #define _CLC4POL_LC4G3POL 0x04
10342 #define _CLC4POL_G3POL 0x04
10343 #define _CLC4POL_LC4G4POL 0x08
10344 #define _CLC4POL_G4POL 0x08
10345 #define _CLC4POL_LC4POL 0x80
10346 #define _CLC4POL_POL 0x80
10348 //==============================================================================
10351 //==============================================================================
10354 extern __at(0x0F30) __sfr CLC4SEL0
;
10360 unsigned LC4D1S0
: 1;
10361 unsigned LC4D1S1
: 1;
10362 unsigned LC4D1S2
: 1;
10363 unsigned LC4D1S3
: 1;
10364 unsigned LC4D1S4
: 1;
10365 unsigned LC4D1S5
: 1;
10384 unsigned LC4D1S
: 6;
10393 } __CLC4SEL0bits_t
;
10395 extern __at(0x0F30) volatile __CLC4SEL0bits_t CLC4SEL0bits
;
10397 #define _CLC4SEL0_LC4D1S0 0x01
10398 #define _CLC4SEL0_D1S0 0x01
10399 #define _CLC4SEL0_LC4D1S1 0x02
10400 #define _CLC4SEL0_D1S1 0x02
10401 #define _CLC4SEL0_LC4D1S2 0x04
10402 #define _CLC4SEL0_D1S2 0x04
10403 #define _CLC4SEL0_LC4D1S3 0x08
10404 #define _CLC4SEL0_D1S3 0x08
10405 #define _CLC4SEL0_LC4D1S4 0x10
10406 #define _CLC4SEL0_D1S4 0x10
10407 #define _CLC4SEL0_LC4D1S5 0x20
10408 #define _CLC4SEL0_D1S5 0x20
10410 //==============================================================================
10413 //==============================================================================
10416 extern __at(0x0F31) __sfr CLC4SEL1
;
10422 unsigned LC4D2S0
: 1;
10423 unsigned LC4D2S1
: 1;
10424 unsigned LC4D2S2
: 1;
10425 unsigned LC4D2S3
: 1;
10426 unsigned LC4D2S4
: 1;
10427 unsigned LC4D2S5
: 1;
10446 unsigned LC4D2S
: 6;
10455 } __CLC4SEL1bits_t
;
10457 extern __at(0x0F31) volatile __CLC4SEL1bits_t CLC4SEL1bits
;
10459 #define _CLC4SEL1_LC4D2S0 0x01
10460 #define _CLC4SEL1_D2S0 0x01
10461 #define _CLC4SEL1_LC4D2S1 0x02
10462 #define _CLC4SEL1_D2S1 0x02
10463 #define _CLC4SEL1_LC4D2S2 0x04
10464 #define _CLC4SEL1_D2S2 0x04
10465 #define _CLC4SEL1_LC4D2S3 0x08
10466 #define _CLC4SEL1_D2S3 0x08
10467 #define _CLC4SEL1_LC4D2S4 0x10
10468 #define _CLC4SEL1_D2S4 0x10
10469 #define _CLC4SEL1_LC4D2S5 0x20
10470 #define _CLC4SEL1_D2S5 0x20
10472 //==============================================================================
10475 //==============================================================================
10478 extern __at(0x0F32) __sfr CLC4SEL2
;
10484 unsigned LC4D3S0
: 1;
10485 unsigned LC4D3S1
: 1;
10486 unsigned LC4D3S2
: 1;
10487 unsigned LC4D3S3
: 1;
10488 unsigned LC4D3S4
: 1;
10489 unsigned LC4D3S5
: 1;
10514 unsigned LC4D3S
: 6;
10517 } __CLC4SEL2bits_t
;
10519 extern __at(0x0F32) volatile __CLC4SEL2bits_t CLC4SEL2bits
;
10521 #define _CLC4SEL2_LC4D3S0 0x01
10522 #define _CLC4SEL2_D3S0 0x01
10523 #define _CLC4SEL2_LC4D3S1 0x02
10524 #define _CLC4SEL2_D3S1 0x02
10525 #define _CLC4SEL2_LC4D3S2 0x04
10526 #define _CLC4SEL2_D3S2 0x04
10527 #define _CLC4SEL2_LC4D3S3 0x08
10528 #define _CLC4SEL2_D3S3 0x08
10529 #define _CLC4SEL2_LC4D3S4 0x10
10530 #define _CLC4SEL2_D3S4 0x10
10531 #define _CLC4SEL2_LC4D3S5 0x20
10532 #define _CLC4SEL2_D3S5 0x20
10534 //==============================================================================
10537 //==============================================================================
10540 extern __at(0x0F33) __sfr CLC4SEL3
;
10546 unsigned LC4D4S0
: 1;
10547 unsigned LC4D4S1
: 1;
10548 unsigned LC4D4S2
: 1;
10549 unsigned LC4D4S3
: 1;
10550 unsigned LC4D4S4
: 1;
10551 unsigned LC4D4S5
: 1;
10570 unsigned LC4D4S
: 6;
10579 } __CLC4SEL3bits_t
;
10581 extern __at(0x0F33) volatile __CLC4SEL3bits_t CLC4SEL3bits
;
10583 #define _CLC4SEL3_LC4D4S0 0x01
10584 #define _CLC4SEL3_D4S0 0x01
10585 #define _CLC4SEL3_LC4D4S1 0x02
10586 #define _CLC4SEL3_D4S1 0x02
10587 #define _CLC4SEL3_LC4D4S2 0x04
10588 #define _CLC4SEL3_D4S2 0x04
10589 #define _CLC4SEL3_LC4D4S3 0x08
10590 #define _CLC4SEL3_D4S3 0x08
10591 #define _CLC4SEL3_LC4D4S4 0x10
10592 #define _CLC4SEL3_D4S4 0x10
10593 #define _CLC4SEL3_LC4D4S5 0x20
10594 #define _CLC4SEL3_D4S5 0x20
10596 //==============================================================================
10599 //==============================================================================
10602 extern __at(0x0F34) __sfr CLC4GLS0
;
10608 unsigned LC4G1D1N
: 1;
10609 unsigned LC4G1D1T
: 1;
10610 unsigned LC4G1D2N
: 1;
10611 unsigned LC4G1D2T
: 1;
10612 unsigned LC4G1D3N
: 1;
10613 unsigned LC4G1D3T
: 1;
10614 unsigned LC4G1D4N
: 1;
10615 unsigned LC4G1D4T
: 1;
10629 } __CLC4GLS0bits_t
;
10631 extern __at(0x0F34) volatile __CLC4GLS0bits_t CLC4GLS0bits
;
10633 #define _CLC4GLS0_LC4G1D1N 0x01
10634 #define _CLC4GLS0_D1N 0x01
10635 #define _CLC4GLS0_LC4G1D1T 0x02
10636 #define _CLC4GLS0_D1T 0x02
10637 #define _CLC4GLS0_LC4G1D2N 0x04
10638 #define _CLC4GLS0_D2N 0x04
10639 #define _CLC4GLS0_LC4G1D2T 0x08
10640 #define _CLC4GLS0_D2T 0x08
10641 #define _CLC4GLS0_LC4G1D3N 0x10
10642 #define _CLC4GLS0_D3N 0x10
10643 #define _CLC4GLS0_LC4G1D3T 0x20
10644 #define _CLC4GLS0_D3T 0x20
10645 #define _CLC4GLS0_LC4G1D4N 0x40
10646 #define _CLC4GLS0_D4N 0x40
10647 #define _CLC4GLS0_LC4G1D4T 0x80
10648 #define _CLC4GLS0_D4T 0x80
10650 //==============================================================================
10653 //==============================================================================
10656 extern __at(0x0F35) __sfr CLC4GLS1
;
10662 unsigned LC4G2D1N
: 1;
10663 unsigned LC4G2D1T
: 1;
10664 unsigned LC4G2D2N
: 1;
10665 unsigned LC4G2D2T
: 1;
10666 unsigned LC4G2D3N
: 1;
10667 unsigned LC4G2D3T
: 1;
10668 unsigned LC4G2D4N
: 1;
10669 unsigned LC4G2D4T
: 1;
10683 } __CLC4GLS1bits_t
;
10685 extern __at(0x0F35) volatile __CLC4GLS1bits_t CLC4GLS1bits
;
10687 #define _CLC4GLS1_LC4G2D1N 0x01
10688 #define _CLC4GLS1_D1N 0x01
10689 #define _CLC4GLS1_LC4G2D1T 0x02
10690 #define _CLC4GLS1_D1T 0x02
10691 #define _CLC4GLS1_LC4G2D2N 0x04
10692 #define _CLC4GLS1_D2N 0x04
10693 #define _CLC4GLS1_LC4G2D2T 0x08
10694 #define _CLC4GLS1_D2T 0x08
10695 #define _CLC4GLS1_LC4G2D3N 0x10
10696 #define _CLC4GLS1_D3N 0x10
10697 #define _CLC4GLS1_LC4G2D3T 0x20
10698 #define _CLC4GLS1_D3T 0x20
10699 #define _CLC4GLS1_LC4G2D4N 0x40
10700 #define _CLC4GLS1_D4N 0x40
10701 #define _CLC4GLS1_LC4G2D4T 0x80
10702 #define _CLC4GLS1_D4T 0x80
10704 //==============================================================================
10707 //==============================================================================
10710 extern __at(0x0F36) __sfr CLC4GLS2
;
10716 unsigned LC4G3D1N
: 1;
10717 unsigned LC4G3D1T
: 1;
10718 unsigned LC4G3D2N
: 1;
10719 unsigned LC4G3D2T
: 1;
10720 unsigned LC4G3D3N
: 1;
10721 unsigned LC4G3D3T
: 1;
10722 unsigned LC4G3D4N
: 1;
10723 unsigned LC4G3D4T
: 1;
10737 } __CLC4GLS2bits_t
;
10739 extern __at(0x0F36) volatile __CLC4GLS2bits_t CLC4GLS2bits
;
10741 #define _CLC4GLS2_LC4G3D1N 0x01
10742 #define _CLC4GLS2_D1N 0x01
10743 #define _CLC4GLS2_LC4G3D1T 0x02
10744 #define _CLC4GLS2_D1T 0x02
10745 #define _CLC4GLS2_LC4G3D2N 0x04
10746 #define _CLC4GLS2_D2N 0x04
10747 #define _CLC4GLS2_LC4G3D2T 0x08
10748 #define _CLC4GLS2_D2T 0x08
10749 #define _CLC4GLS2_LC4G3D3N 0x10
10750 #define _CLC4GLS2_D3N 0x10
10751 #define _CLC4GLS2_LC4G3D3T 0x20
10752 #define _CLC4GLS2_D3T 0x20
10753 #define _CLC4GLS2_LC4G3D4N 0x40
10754 #define _CLC4GLS2_D4N 0x40
10755 #define _CLC4GLS2_LC4G3D4T 0x80
10756 #define _CLC4GLS2_D4T 0x80
10758 //==============================================================================
10761 //==============================================================================
10764 extern __at(0x0F37) __sfr CLC4GLS3
;
10770 unsigned LC4G4D1N
: 1;
10771 unsigned LC4G4D1T
: 1;
10772 unsigned LC4G4D2N
: 1;
10773 unsigned LC4G4D2T
: 1;
10774 unsigned LC4G4D3N
: 1;
10775 unsigned LC4G4D3T
: 1;
10776 unsigned LC4G4D4N
: 1;
10777 unsigned LC4G4D4T
: 1;
10782 unsigned G4D1N
: 1;
10783 unsigned G4D1T
: 1;
10784 unsigned G4D2N
: 1;
10785 unsigned G4D2T
: 1;
10786 unsigned G4D3N
: 1;
10787 unsigned G4D3T
: 1;
10788 unsigned G4D4N
: 1;
10789 unsigned G4D4T
: 1;
10791 } __CLC4GLS3bits_t
;
10793 extern __at(0x0F37) volatile __CLC4GLS3bits_t CLC4GLS3bits
;
10795 #define _CLC4GLS3_LC4G4D1N 0x01
10796 #define _CLC4GLS3_G4D1N 0x01
10797 #define _CLC4GLS3_LC4G4D1T 0x02
10798 #define _CLC4GLS3_G4D1T 0x02
10799 #define _CLC4GLS3_LC4G4D2N 0x04
10800 #define _CLC4GLS3_G4D2N 0x04
10801 #define _CLC4GLS3_LC4G4D2T 0x08
10802 #define _CLC4GLS3_G4D2T 0x08
10803 #define _CLC4GLS3_LC4G4D3N 0x10
10804 #define _CLC4GLS3_G4D3N 0x10
10805 #define _CLC4GLS3_LC4G4D3T 0x20
10806 #define _CLC4GLS3_G4D3T 0x20
10807 #define _CLC4GLS3_LC4G4D4N 0x40
10808 #define _CLC4GLS3_G4D4N 0x40
10809 #define _CLC4GLS3_LC4G4D4T 0x80
10810 #define _CLC4GLS3_G4D4T 0x80
10812 //==============================================================================
10815 //==============================================================================
10816 // STATUS_SHAD Bits
10818 extern __at(0x0FE4) __sfr STATUS_SHAD
;
10822 unsigned C_SHAD
: 1;
10823 unsigned DC_SHAD
: 1;
10824 unsigned Z_SHAD
: 1;
10830 } __STATUS_SHADbits_t
;
10832 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
10834 #define _C_SHAD 0x01
10835 #define _DC_SHAD 0x02
10836 #define _Z_SHAD 0x04
10838 //==============================================================================
10840 extern __at(0x0FE5) __sfr WREG_SHAD
;
10841 extern __at(0x0FE6) __sfr BSR_SHAD
;
10842 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
10843 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
10844 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
10845 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
10846 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
10847 extern __at(0x0FED) __sfr STKPTR
;
10848 extern __at(0x0FEE) __sfr TOSL
;
10849 extern __at(0x0FEF) __sfr TOSH
;
10851 //==============================================================================
10853 // Configuration Bits
10855 //==============================================================================
10857 #define _CONFIG1 0x8007
10858 #define _CONFIG2 0x8008
10859 #define _CONFIG3 0x8009
10860 #define _CONFIG4 0x800A
10862 //----------------------------- CONFIG1 Options -------------------------------
10864 #define _FEXTOSC_LP 0x3FF8 // LP (crystal oscillator) optimized for 32.768 kHz.
10865 #define _FEXTOSC_XT 0x3FF9 // XT (crystal oscillator) from 100 kHz to 4 MHz.
10866 #define _FEXTOSC_HS 0x3FFA // HS (crystal oscillator) above 4 MHz.
10867 #define _FEXTOSC_OFF 0x3FFC // Oscillator not enabled.
10868 #define _FEXTOSC_ECL 0x3FFD // EC (external clock) below 100 kHz.
10869 #define _FEXTOSC_ECM 0x3FFE // EC (external clock) for 100 kHz to 8 MHz.
10870 #define _FEXTOSC_ECH 0x3FFF // EC (external clock) above 8 MHz.
10871 #define _RSTOSC_HFINT32 0x3F8F // HFINTOSC with 2x PLL (32MHz).
10872 #define _RSTOSC_EXT4X 0x3F9F // EXTOSC with 4x PLL, with EXTOSC operating per FEXTOSC bits.
10873 #define _RSTOSC_SOSC 0x3FBF // SOSC (31kHz).
10874 #define _RSTOSC_LFINT 0x3FCF // LFINTOSC (31kHz).
10875 #define _RSTOSC_HFINT1 0x3FEF // HFINTOSC (1MHz).
10876 #define _RSTOSC_EXT1X 0x3FFF // EXTOSC operating per FEXTOSC bits.
10877 #define _CLKOUTEN_ON 0x3EFF // CLKOUT function is enabled; FOSC/4 clock appears at OSC2.
10878 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled; I/O or oscillator function on OSC2.
10879 #define _CSWEN_OFF 0x37FF // The NOSC and NDIV bits cannot be changed by user software.
10880 #define _CSWEN_ON 0x3FFF // Writing to NOSC and NDIV is allowed.
10881 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
10882 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
10884 //----------------------------- CONFIG2 Options -------------------------------
10886 #define _MCLRE_OFF 0x3FFE // MCLR/VPP pin function is digital input; MCLR internally disabled; Weak pull-up under control of port pin's WPU control bit.
10887 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR; Weak pull-up enabled.
10888 #define _PWRTE_ON 0x3FFD // PWRT enabled.
10889 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
10890 #define _WDTE_OFF 0x3FF3 // WDT disabled; SWDTEN is ignored.
10891 #define _WDTE_SWDTEN 0x3FF7 // WDT controlled by the SWDTEN bit in the WDTCON register.
10892 #define _WDTE_SLEEP 0x3FFB // WDT enabled while running and disabled in SLEEP/IDLE; SWDTEN is ignored.
10893 #define _WDTE_ON 0x3FFF // WDT enabled, SWDTEN is ignored.
10894 #define _LPBOREN_ON 0x3FDF // ULPBOR enabled.
10895 #define _LPBOREN_OFF 0x3FFF // ULPBOR disabled.
10896 #define _BOREN_OFF 0x3F3F // Brown-out Reset disabled.
10897 #define _BOREN_SBOREN 0x3F7F // Brown-out Reset enabled according to SBOREN.
10898 #define _BOREN_SLEEP 0x3FBF // Brown-out Reset enabled while running, disabled in Sleep; SBOREN is ignored.
10899 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled, SBOREN bit ignored.
10900 #define _BORV_HIGH 0x3DFF // Brown-out voltage (Vbor) set to 2.7V.
10901 #define _BORV_LOW 0x3FFF // Brown-out voltage (Vbor) set to 2.45V.
10902 #define _PPS1WAY_OFF 0x37FF // The PPSLOCK bit can be set and cleared repeatedly (subject to the unlock sequence).
10903 #define _PPS1WAY_ON 0x3FFF // The PPSLOCK bit can be cleared and set only once; PPS registers remain locked after one clear/set cycle.
10904 #define _STVREN_OFF 0x2FFF // Stack Overflow or Underflow will not cause a Reset.
10905 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
10906 #define _DEBUG_ON 0x1FFF // Background debugger enabled.
10907 #define _DEBUG_OFF 0x3FFF // Background debugger disabled.
10909 //----------------------------- CONFIG3 Options -------------------------------
10911 #define _WRT_ALL 0x3FFC // 0000h to 1FFFh write protected, no addresses may be modified.
10912 #define _WRT_HALF 0x3FFD // 0000h to 03FFh write-protected, 0400h to 1FFFh may be modified.
10913 #define _WRT_BOOT 0x3FFE // 0000h to 01FFh write-protected, 0200h to 1FFFh may be modified.
10914 #define _WRT_OFF 0x3FFF // Write protection off.
10915 #define _LVP_OFF 0x1FFF // High Voltage on MCLR/VPP must be used for programming.
10916 #define _LVP_ON 0x3FFF // Low Voltage programming enabled. MCLR/VPP pin function is MCLR. MCLRE configuration bit is ignored.
10918 //----------------------------- CONFIG4 Options -------------------------------
10920 #define _CP_ON 0x3FFE // User NVM code protection enabled.
10921 #define _CP_OFF 0x3FFF // User NVM code protection disabled.
10922 #define _CPD_ON 0x3FFD // Data NVM code protection enabled.
10923 #define _CPD_OFF 0x3FFF // Data NVM code protection disabled.
10925 //==============================================================================
10927 #define _DEVID1 0x8006
10929 #define _IDLOC0 0x8000
10930 #define _IDLOC1 0x8001
10931 #define _IDLOC2 0x8002
10932 #define _IDLOC3 0x8003
10934 //==============================================================================
10936 #ifndef NO_BIT_DEFINES
10938 #define ADACT0 ADACTbits.ADACT0 // bit 0
10939 #define ADACT1 ADACTbits.ADACT1 // bit 1
10940 #define ADACT2 ADACTbits.ADACT2 // bit 2
10941 #define ADACT3 ADACTbits.ADACT3 // bit 3
10942 #define ADACT4 ADACTbits.ADACT4 // bit 4
10944 #define ADON ADCON0bits.ADON // bit 0
10945 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
10946 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
10947 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
10948 #define CHS0 ADCON0bits.CHS0 // bit 2
10949 #define CHS1 ADCON0bits.CHS1 // bit 3
10950 #define CHS2 ADCON0bits.CHS2 // bit 4
10951 #define CHS3 ADCON0bits.CHS3 // bit 5
10952 #define CHS4 ADCON0bits.CHS4 // bit 6
10953 #define CHS5 ADCON0bits.CHS5 // bit 7
10955 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
10956 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
10957 #define ADNREF ADCON1bits.ADNREF // bit 2
10958 #define ADCS0 ADCON1bits.ADCS0 // bit 4
10959 #define ADCS1 ADCON1bits.ADCS1 // bit 5
10960 #define ADCS2 ADCON1bits.ADCS2 // bit 6
10961 #define ADFM ADCON1bits.ADFM // bit 7
10963 #define ANSA0 ANSELAbits.ANSA0 // bit 0
10964 #define ANSA1 ANSELAbits.ANSA1 // bit 1
10965 #define ANSA2 ANSELAbits.ANSA2 // bit 2
10966 #define ANSA4 ANSELAbits.ANSA4 // bit 4
10967 #define ANSA5 ANSELAbits.ANSA5 // bit 5
10969 #define ANSB4 ANSELBbits.ANSB4 // bit 4
10970 #define ANSB5 ANSELBbits.ANSB5 // bit 5
10971 #define ANSB6 ANSELBbits.ANSB6 // bit 6
10972 #define ANSB7 ANSELBbits.ANSB7 // bit 7
10974 #define ANSC0 ANSELCbits.ANSC0 // bit 0
10975 #define ANSC1 ANSELCbits.ANSC1 // bit 1
10976 #define ANSC2 ANSELCbits.ANSC2 // bit 2
10977 #define ANSC3 ANSELCbits.ANSC3 // bit 3
10978 #define ANSC4 ANSELCbits.ANSC4 // bit 4
10979 #define ANSC5 ANSELCbits.ANSC5 // bit 5
10980 #define ANSC6 ANSELCbits.ANSC6 // bit 6
10981 #define ANSC7 ANSELCbits.ANSC7 // bit 7
10983 #define ABDEN BAUD1CONbits.ABDEN // bit 0
10984 #define WUE BAUD1CONbits.WUE // bit 1
10985 #define BRG16 BAUD1CONbits.BRG16 // bit 3
10986 #define SCKP BAUD1CONbits.SCKP // bit 4
10987 #define RCIDL BAUD1CONbits.RCIDL // bit 6
10988 #define ABDOVF BAUD1CONbits.ABDOVF // bit 7
10990 #define BORRDY BORCONbits.BORRDY // bit 0
10991 #define SBOREN BORCONbits.SBOREN // bit 7
10993 #define BSR0 BSRbits.BSR0 // bit 0
10994 #define BSR1 BSRbits.BSR1 // bit 1
10995 #define BSR2 BSRbits.BSR2 // bit 2
10996 #define BSR3 BSRbits.BSR3 // bit 3
10997 #define BSR4 BSRbits.BSR4 // bit 4
10999 #define CCDS0 CCDCONbits.CCDS0 // bit 0
11000 #define CCDS1 CCDCONbits.CCDS1 // bit 1
11001 #define CCDEN CCDCONbits.CCDEN // bit 7
11003 #define CCDNA0 CCDNAbits.CCDNA0 // bit 0
11004 #define CCDNA1 CCDNAbits.CCDNA1 // bit 1
11005 #define CCDNA2 CCDNAbits.CCDNA2 // bit 2
11006 #define CCDNA4 CCDNAbits.CCDNA4 // bit 4
11007 #define CCDNA5 CCDNAbits.CCDNA5 // bit 5
11009 #define CCDNB4 CCDNBbits.CCDNB4 // bit 4
11010 #define CCDNB5 CCDNBbits.CCDNB5 // bit 5
11011 #define CCDNB6 CCDNBbits.CCDNB6 // bit 6
11012 #define CCDNB7 CCDNBbits.CCDNB7 // bit 7
11014 #define CCDNC0 CCDNCbits.CCDNC0 // bit 0
11015 #define CCDNC1 CCDNCbits.CCDNC1 // bit 1
11016 #define CCDNC2 CCDNCbits.CCDNC2 // bit 2
11017 #define CCDNC3 CCDNCbits.CCDNC3 // bit 3
11018 #define CCDNC4 CCDNCbits.CCDNC4 // bit 4
11019 #define CCDNC5 CCDNCbits.CCDNC5 // bit 5
11020 #define CCDNC6 CCDNCbits.CCDNC6 // bit 6
11021 #define CCDNC7 CCDNCbits.CCDNC7 // bit 7
11023 #define CCDPA0 CCDPAbits.CCDPA0 // bit 0
11024 #define CCDPA1 CCDPAbits.CCDPA1 // bit 1
11025 #define CCDPA2 CCDPAbits.CCDPA2 // bit 2
11026 #define CCDPA4 CCDPAbits.CCDPA4 // bit 4
11027 #define CCDPA5 CCDPAbits.CCDPA5 // bit 5
11029 #define CCDPB4 CCDPBbits.CCDPB4 // bit 4
11030 #define CCDPB5 CCDPBbits.CCDPB5 // bit 5
11031 #define CCDPB6 CCDPBbits.CCDPB6 // bit 6
11032 #define CCDPB7 CCDPBbits.CCDPB7 // bit 7
11034 #define CCDPC0 CCDPCbits.CCDPC0 // bit 0
11035 #define CCDPC1 CCDPCbits.CCDPC1 // bit 1
11036 #define CCDPC2 CCDPCbits.CCDPC2 // bit 2
11037 #define CCDPC3 CCDPCbits.CCDPC3 // bit 3
11038 #define CCDPC4 CCDPCbits.CCDPC4 // bit 4
11039 #define CCDPC5 CCDPCbits.CCDPC5 // bit 5
11040 #define CCDPC6 CCDPCbits.CCDPC6 // bit 6
11041 #define CCDPC7 CCDPCbits.CCDPC7 // bit 7
11043 #define CCP1CTS0 CCP1CAPbits.CCP1CTS0 // bit 0
11044 #define CCP1CTS1 CCP1CAPbits.CCP1CTS1 // bit 1
11045 #define CCP1CTS2 CCP1CAPbits.CCP1CTS2 // bit 2
11046 #define CCP1CTS3 CCP1CAPbits.CCP1CTS3 // bit 3
11048 #define CCP1MODE0 CCP1CONbits.CCP1MODE0 // bit 0
11049 #define CCP1MODE1 CCP1CONbits.CCP1MODE1 // bit 1
11050 #define CCP1MODE2 CCP1CONbits.CCP1MODE2 // bit 2
11051 #define CCP1MODE3 CCP1CONbits.CCP1MODE3 // bit 3
11052 #define CCP1FMT CCP1CONbits.CCP1FMT // bit 4
11053 #define CCP1OUT CCP1CONbits.CCP1OUT // bit 5
11054 #define CCP1EN CCP1CONbits.CCP1EN // bit 7
11056 #define CCP1PPS0 CCP1PPSbits.CCP1PPS0 // bit 0
11057 #define CCP1PPS1 CCP1PPSbits.CCP1PPS1 // bit 1
11058 #define CCP1PPS2 CCP1PPSbits.CCP1PPS2 // bit 2
11059 #define CCP1PPS3 CCP1PPSbits.CCP1PPS3 // bit 3
11060 #define CCP1PPS4 CCP1PPSbits.CCP1PPS4 // bit 4
11062 #define CCP2CTS0 CCP2CAPbits.CCP2CTS0 // bit 0
11063 #define CCP2CTS1 CCP2CAPbits.CCP2CTS1 // bit 1
11064 #define CCP2CTS2 CCP2CAPbits.CCP2CTS2 // bit 2
11065 #define CCP2CTS3 CCP2CAPbits.CCP2CTS3 // bit 3
11067 #define CCP2MODE0 CCP2CONbits.CCP2MODE0 // bit 0
11068 #define CCP2MODE1 CCP2CONbits.CCP2MODE1 // bit 1
11069 #define CCP2MODE2 CCP2CONbits.CCP2MODE2 // bit 2
11070 #define CCP2MODE3 CCP2CONbits.CCP2MODE3 // bit 3
11071 #define CCP2FMT CCP2CONbits.CCP2FMT // bit 4
11072 #define CCP2OUT CCP2CONbits.CCP2OUT // bit 5
11073 #define CCP2EN CCP2CONbits.CCP2EN // bit 7
11075 #define CCP2PPS0 CCP2PPSbits.CCP2PPS0 // bit 0
11076 #define CCP2PPS1 CCP2PPSbits.CCP2PPS1 // bit 1
11077 #define CCP2PPS2 CCP2PPSbits.CCP2PPS2 // bit 2
11078 #define CCP2PPS3 CCP2PPSbits.CCP2PPS3 // bit 3
11079 #define CCP2PPS4 CCP2PPSbits.CCP2PPS4 // bit 4
11081 #define CCP3CTS0 CCP3CAPbits.CCP3CTS0 // bit 0
11082 #define CCP3CTS1 CCP3CAPbits.CCP3CTS1 // bit 1
11083 #define CCP3CTS2 CCP3CAPbits.CCP3CTS2 // bit 2
11084 #define CCP3CTS3 CCP3CAPbits.CCP3CTS3 // bit 3
11086 #define CCP3MODE0 CCP3CONbits.CCP3MODE0 // bit 0
11087 #define CCP3MODE1 CCP3CONbits.CCP3MODE1 // bit 1
11088 #define CCP3MODE2 CCP3CONbits.CCP3MODE2 // bit 2
11089 #define CCP3MODE3 CCP3CONbits.CCP3MODE3 // bit 3
11090 #define CCP3FMT CCP3CONbits.CCP3FMT // bit 4
11091 #define CCP3OUT CCP3CONbits.CCP3OUT // bit 5
11092 #define CCP3EN CCP3CONbits.CCP3EN // bit 7
11094 #define CCP3PPS0 CCP3PPSbits.CCP3PPS0 // bit 0
11095 #define CCP3PPS1 CCP3PPSbits.CCP3PPS1 // bit 1
11096 #define CCP3PPS2 CCP3PPSbits.CCP3PPS2 // bit 2
11097 #define CCP3PPS3 CCP3PPSbits.CCP3PPS3 // bit 3
11098 #define CCP3PPS4 CCP3PPSbits.CCP3PPS4 // bit 4
11100 #define CCP4CTS0 CCP4CAPbits.CCP4CTS0 // bit 0
11101 #define CCP4CTS1 CCP4CAPbits.CCP4CTS1 // bit 1
11102 #define CCP4CTS2 CCP4CAPbits.CCP4CTS2 // bit 2
11103 #define CCP4CTS3 CCP4CAPbits.CCP4CTS3 // bit 3
11105 #define CCP4MODE0 CCP4CONbits.CCP4MODE0 // bit 0
11106 #define CCP4MODE1 CCP4CONbits.CCP4MODE1 // bit 1
11107 #define CCP4MODE2 CCP4CONbits.CCP4MODE2 // bit 2
11108 #define CCP4MODE3 CCP4CONbits.CCP4MODE3 // bit 3
11109 #define CCP4FMT CCP4CONbits.CCP4FMT // bit 4
11110 #define CCP4OUT CCP4CONbits.CCP4OUT // bit 5
11111 #define CCP4EN CCP4CONbits.CCP4EN // bit 7
11113 #define CCP4PPS0 CCP4PPSbits.CCP4PPS0 // bit 0
11114 #define CCP4PPS1 CCP4PPSbits.CCP4PPS1 // bit 1
11115 #define CCP4PPS2 CCP4PPSbits.CCP4PPS2 // bit 2
11116 #define CCP4PPS3 CCP4PPSbits.CCP4PPS3 // bit 3
11117 #define CCP4PPS4 CCP4PPSbits.CCP4PPS4 // bit 4
11119 #define C1TSEL0 CCPTMRSbits.C1TSEL0 // bit 0
11120 #define C1TSEL1 CCPTMRSbits.C1TSEL1 // bit 1
11121 #define C2TSEL0 CCPTMRSbits.C2TSEL0 // bit 2
11122 #define C2TSEL1 CCPTMRSbits.C2TSEL1 // bit 3
11123 #define C3TSEL0 CCPTMRSbits.C3TSEL0 // bit 4
11124 #define C3TSEL1 CCPTMRSbits.C3TSEL1 // bit 5
11125 #define C4TSEL0 CCPTMRSbits.C4TSEL0 // bit 6
11126 #define C4TSEL1 CCPTMRSbits.C4TSEL1 // bit 7
11128 #define LC1MODE0 CLC1CONbits.LC1MODE0 // bit 0, shadows bit in CLC1CONbits
11129 #define MODE0 CLC1CONbits.MODE0 // bit 0, shadows bit in CLC1CONbits
11130 #define LC1MODE1 CLC1CONbits.LC1MODE1 // bit 1, shadows bit in CLC1CONbits
11131 #define MODE1 CLC1CONbits.MODE1 // bit 1, shadows bit in CLC1CONbits
11132 #define LC1MODE2 CLC1CONbits.LC1MODE2 // bit 2, shadows bit in CLC1CONbits
11133 #define MODE2 CLC1CONbits.MODE2 // bit 2, shadows bit in CLC1CONbits
11134 #define LC1INTN CLC1CONbits.LC1INTN // bit 3, shadows bit in CLC1CONbits
11135 #define INTN CLC1CONbits.INTN // bit 3, shadows bit in CLC1CONbits
11136 #define LC1INTP CLC1CONbits.LC1INTP // bit 4, shadows bit in CLC1CONbits
11137 #define INTP CLC1CONbits.INTP // bit 4, shadows bit in CLC1CONbits
11138 #define LC1OUT CLC1CONbits.LC1OUT // bit 5, shadows bit in CLC1CONbits
11139 #define OUT CLC1CONbits.OUT // bit 5, shadows bit in CLC1CONbits
11140 #define LC1EN CLC1CONbits.LC1EN // bit 7, shadows bit in CLC1CONbits
11141 #define EN CLC1CONbits.EN // bit 7, shadows bit in CLC1CONbits
11143 #define LC1G1D1N CLC1GLS0bits.LC1G1D1N // bit 0, shadows bit in CLC1GLS0bits
11144 #define D1N CLC1GLS0bits.D1N // bit 0, shadows bit in CLC1GLS0bits
11145 #define LC1G1D1T CLC1GLS0bits.LC1G1D1T // bit 1, shadows bit in CLC1GLS0bits
11146 #define D1T CLC1GLS0bits.D1T // bit 1, shadows bit in CLC1GLS0bits
11147 #define LC1G1D2N CLC1GLS0bits.LC1G1D2N // bit 2, shadows bit in CLC1GLS0bits
11148 #define D2N CLC1GLS0bits.D2N // bit 2, shadows bit in CLC1GLS0bits
11149 #define LC1G1D2T CLC1GLS0bits.LC1G1D2T // bit 3, shadows bit in CLC1GLS0bits
11150 #define D2T CLC1GLS0bits.D2T // bit 3, shadows bit in CLC1GLS0bits
11151 #define LC1G1D3N CLC1GLS0bits.LC1G1D3N // bit 4, shadows bit in CLC1GLS0bits
11152 #define D3N CLC1GLS0bits.D3N // bit 4, shadows bit in CLC1GLS0bits
11153 #define LC1G1D3T CLC1GLS0bits.LC1G1D3T // bit 5, shadows bit in CLC1GLS0bits
11154 #define D3T CLC1GLS0bits.D3T // bit 5, shadows bit in CLC1GLS0bits
11155 #define LC1G1D4N CLC1GLS0bits.LC1G1D4N // bit 6, shadows bit in CLC1GLS0bits
11156 #define D4N CLC1GLS0bits.D4N // bit 6, shadows bit in CLC1GLS0bits
11157 #define LC1G1D4T CLC1GLS0bits.LC1G1D4T // bit 7, shadows bit in CLC1GLS0bits
11158 #define D4T CLC1GLS0bits.D4T // bit 7, shadows bit in CLC1GLS0bits
11160 #define LC1G4D1N CLC1GLS3bits.LC1G4D1N // bit 0, shadows bit in CLC1GLS3bits
11161 #define G4D1N CLC1GLS3bits.G4D1N // bit 0, shadows bit in CLC1GLS3bits
11162 #define LC1G4D1T CLC1GLS3bits.LC1G4D1T // bit 1, shadows bit in CLC1GLS3bits
11163 #define G4D1T CLC1GLS3bits.G4D1T // bit 1, shadows bit in CLC1GLS3bits
11164 #define LC1G4D2N CLC1GLS3bits.LC1G4D2N // bit 2, shadows bit in CLC1GLS3bits
11165 #define G4D2N CLC1GLS3bits.G4D2N // bit 2, shadows bit in CLC1GLS3bits
11166 #define LC1G4D2T CLC1GLS3bits.LC1G4D2T // bit 3, shadows bit in CLC1GLS3bits
11167 #define G4D2T CLC1GLS3bits.G4D2T // bit 3, shadows bit in CLC1GLS3bits
11168 #define LC1G4D3N CLC1GLS3bits.LC1G4D3N // bit 4, shadows bit in CLC1GLS3bits
11169 #define G4D3N CLC1GLS3bits.G4D3N // bit 4, shadows bit in CLC1GLS3bits
11170 #define LC1G4D3T CLC1GLS3bits.LC1G4D3T // bit 5, shadows bit in CLC1GLS3bits
11171 #define G4D3T CLC1GLS3bits.G4D3T // bit 5, shadows bit in CLC1GLS3bits
11172 #define LC1G4D4N CLC1GLS3bits.LC1G4D4N // bit 6, shadows bit in CLC1GLS3bits
11173 #define G4D4N CLC1GLS3bits.G4D4N // bit 6, shadows bit in CLC1GLS3bits
11174 #define LC1G4D4T CLC1GLS3bits.LC1G4D4T // bit 7, shadows bit in CLC1GLS3bits
11175 #define G4D4T CLC1GLS3bits.G4D4T // bit 7, shadows bit in CLC1GLS3bits
11177 #define LC1G1POL CLC1POLbits.LC1G1POL // bit 0, shadows bit in CLC1POLbits
11178 #define G1POL CLC1POLbits.G1POL // bit 0, shadows bit in CLC1POLbits
11179 #define LC1G2POL CLC1POLbits.LC1G2POL // bit 1, shadows bit in CLC1POLbits
11180 #define G2POL CLC1POLbits.G2POL // bit 1, shadows bit in CLC1POLbits
11181 #define LC1G3POL CLC1POLbits.LC1G3POL // bit 2, shadows bit in CLC1POLbits
11182 #define G3POL CLC1POLbits.G3POL // bit 2, shadows bit in CLC1POLbits
11183 #define LC1G4POL CLC1POLbits.LC1G4POL // bit 3, shadows bit in CLC1POLbits
11184 #define G4POL CLC1POLbits.G4POL // bit 3, shadows bit in CLC1POLbits
11185 #define LC1POL CLC1POLbits.LC1POL // bit 7, shadows bit in CLC1POLbits
11186 #define POL CLC1POLbits.POL // bit 7, shadows bit in CLC1POLbits
11188 #define LC1D1S0 CLC1SEL0bits.LC1D1S0 // bit 0, shadows bit in CLC1SEL0bits
11189 #define D1S0 CLC1SEL0bits.D1S0 // bit 0, shadows bit in CLC1SEL0bits
11190 #define LC1D1S1 CLC1SEL0bits.LC1D1S1 // bit 1, shadows bit in CLC1SEL0bits
11191 #define D1S1 CLC1SEL0bits.D1S1 // bit 1, shadows bit in CLC1SEL0bits
11192 #define LC1D1S2 CLC1SEL0bits.LC1D1S2 // bit 2, shadows bit in CLC1SEL0bits
11193 #define D1S2 CLC1SEL0bits.D1S2 // bit 2, shadows bit in CLC1SEL0bits
11194 #define LC1D1S3 CLC1SEL0bits.LC1D1S3 // bit 3, shadows bit in CLC1SEL0bits
11195 #define D1S3 CLC1SEL0bits.D1S3 // bit 3, shadows bit in CLC1SEL0bits
11196 #define LC1D1S4 CLC1SEL0bits.LC1D1S4 // bit 4, shadows bit in CLC1SEL0bits
11197 #define D1S4 CLC1SEL0bits.D1S4 // bit 4, shadows bit in CLC1SEL0bits
11198 #define LC1D1S5 CLC1SEL0bits.LC1D1S5 // bit 5, shadows bit in CLC1SEL0bits
11199 #define D1S5 CLC1SEL0bits.D1S5 // bit 5, shadows bit in CLC1SEL0bits
11201 #define LC1D2S0 CLC1SEL1bits.LC1D2S0 // bit 0, shadows bit in CLC1SEL1bits
11202 #define D2S0 CLC1SEL1bits.D2S0 // bit 0, shadows bit in CLC1SEL1bits
11203 #define LC1D2S1 CLC1SEL1bits.LC1D2S1 // bit 1, shadows bit in CLC1SEL1bits
11204 #define D2S1 CLC1SEL1bits.D2S1 // bit 1, shadows bit in CLC1SEL1bits
11205 #define LC1D2S2 CLC1SEL1bits.LC1D2S2 // bit 2, shadows bit in CLC1SEL1bits
11206 #define D2S2 CLC1SEL1bits.D2S2 // bit 2, shadows bit in CLC1SEL1bits
11207 #define LC1D2S3 CLC1SEL1bits.LC1D2S3 // bit 3, shadows bit in CLC1SEL1bits
11208 #define D2S3 CLC1SEL1bits.D2S3 // bit 3, shadows bit in CLC1SEL1bits
11209 #define LC1D2S4 CLC1SEL1bits.LC1D2S4 // bit 4, shadows bit in CLC1SEL1bits
11210 #define D2S4 CLC1SEL1bits.D2S4 // bit 4, shadows bit in CLC1SEL1bits
11211 #define LC1D2S5 CLC1SEL1bits.LC1D2S5 // bit 5, shadows bit in CLC1SEL1bits
11212 #define D2S5 CLC1SEL1bits.D2S5 // bit 5, shadows bit in CLC1SEL1bits
11214 #define LC1D3S0 CLC1SEL2bits.LC1D3S0 // bit 0, shadows bit in CLC1SEL2bits
11215 #define D3S0 CLC1SEL2bits.D3S0 // bit 0, shadows bit in CLC1SEL2bits
11216 #define LC1D3S1 CLC1SEL2bits.LC1D3S1 // bit 1, shadows bit in CLC1SEL2bits
11217 #define D3S1 CLC1SEL2bits.D3S1 // bit 1, shadows bit in CLC1SEL2bits
11218 #define LC1D3S2 CLC1SEL2bits.LC1D3S2 // bit 2, shadows bit in CLC1SEL2bits
11219 #define D3S2 CLC1SEL2bits.D3S2 // bit 2, shadows bit in CLC1SEL2bits
11220 #define LC1D3S3 CLC1SEL2bits.LC1D3S3 // bit 3, shadows bit in CLC1SEL2bits
11221 #define D3S3 CLC1SEL2bits.D3S3 // bit 3, shadows bit in CLC1SEL2bits
11222 #define LC1D3S4 CLC1SEL2bits.LC1D3S4 // bit 4, shadows bit in CLC1SEL2bits
11223 #define D3S4 CLC1SEL2bits.D3S4 // bit 4, shadows bit in CLC1SEL2bits
11224 #define LC1D3S5 CLC1SEL2bits.LC1D3S5 // bit 5, shadows bit in CLC1SEL2bits
11225 #define D3S5 CLC1SEL2bits.D3S5 // bit 5, shadows bit in CLC1SEL2bits
11227 #define LC1D4S0 CLC1SEL3bits.LC1D4S0 // bit 0, shadows bit in CLC1SEL3bits
11228 #define D4S0 CLC1SEL3bits.D4S0 // bit 0, shadows bit in CLC1SEL3bits
11229 #define LC1D4S1 CLC1SEL3bits.LC1D4S1 // bit 1, shadows bit in CLC1SEL3bits
11230 #define D4S1 CLC1SEL3bits.D4S1 // bit 1, shadows bit in CLC1SEL3bits
11231 #define LC1D4S2 CLC1SEL3bits.LC1D4S2 // bit 2, shadows bit in CLC1SEL3bits
11232 #define D4S2 CLC1SEL3bits.D4S2 // bit 2, shadows bit in CLC1SEL3bits
11233 #define LC1D4S3 CLC1SEL3bits.LC1D4S3 // bit 3, shadows bit in CLC1SEL3bits
11234 #define D4S3 CLC1SEL3bits.D4S3 // bit 3, shadows bit in CLC1SEL3bits
11235 #define LC1D4S4 CLC1SEL3bits.LC1D4S4 // bit 4, shadows bit in CLC1SEL3bits
11236 #define D4S4 CLC1SEL3bits.D4S4 // bit 4, shadows bit in CLC1SEL3bits
11237 #define LC1D4S5 CLC1SEL3bits.LC1D4S5 // bit 5, shadows bit in CLC1SEL3bits
11238 #define D4S5 CLC1SEL3bits.D4S5 // bit 5, shadows bit in CLC1SEL3bits
11240 #define MLC1OUT CLCDATAbits.MLC1OUT // bit 0
11241 #define MLC2OUT CLCDATAbits.MLC2OUT // bit 1
11242 #define MLC3OUT CLCDATAbits.MLC3OUT // bit 2
11243 #define MLC4OUT CLCDATAbits.MLC4OUT // bit 3
11245 #define CLCIN0PPS0 CLCIN0PPSbits.CLCIN0PPS0 // bit 0
11246 #define CLCIN0PPS1 CLCIN0PPSbits.CLCIN0PPS1 // bit 1
11247 #define CLCIN0PPS2 CLCIN0PPSbits.CLCIN0PPS2 // bit 2
11248 #define CLCIN0PPS3 CLCIN0PPSbits.CLCIN0PPS3 // bit 3
11249 #define CLCIN0PPS4 CLCIN0PPSbits.CLCIN0PPS4 // bit 4
11251 #define CLCIN1PPS0 CLCIN1PPSbits.CLCIN1PPS0 // bit 0
11252 #define CLCIN1PPS1 CLCIN1PPSbits.CLCIN1PPS1 // bit 1
11253 #define CLCIN1PPS2 CLCIN1PPSbits.CLCIN1PPS2 // bit 2
11254 #define CLCIN1PPS3 CLCIN1PPSbits.CLCIN1PPS3 // bit 3
11255 #define CLCIN1PPS4 CLCIN1PPSbits.CLCIN1PPS4 // bit 4
11257 #define CLCIN2PPS0 CLCIN2PPSbits.CLCIN2PPS0 // bit 0
11258 #define CLCIN2PPS1 CLCIN2PPSbits.CLCIN2PPS1 // bit 1
11259 #define CLCIN2PPS2 CLCIN2PPSbits.CLCIN2PPS2 // bit 2
11260 #define CLCIN2PPS3 CLCIN2PPSbits.CLCIN2PPS3 // bit 3
11261 #define CLCIN2PPS4 CLCIN2PPSbits.CLCIN2PPS4 // bit 4
11263 #define CLCIN3PPS0 CLCIN3PPSbits.CLCIN3PPS0 // bit 0
11264 #define CLCIN3PPS1 CLCIN3PPSbits.CLCIN3PPS1 // bit 1
11265 #define CLCIN3PPS2 CLCIN3PPSbits.CLCIN3PPS2 // bit 2
11266 #define CLCIN3PPS3 CLCIN3PPSbits.CLCIN3PPS3 // bit 3
11267 #define CLCIN3PPS4 CLCIN3PPSbits.CLCIN3PPS4 // bit 4
11269 #define CLKRDIV0 CLKRCONbits.CLKRDIV0 // bit 0
11270 #define CLKRDIV1 CLKRCONbits.CLKRDIV1 // bit 1
11271 #define CLKRDIV2 CLKRCONbits.CLKRDIV2 // bit 2
11272 #define CLKRDC0 CLKRCONbits.CLKRDC0 // bit 3
11273 #define CLKRDC1 CLKRCONbits.CLKRDC1 // bit 4
11274 #define CLKREN CLKRCONbits.CLKREN // bit 7
11276 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
11277 #define C1HYS CM1CON0bits.C1HYS // bit 1
11278 #define C1SP CM1CON0bits.C1SP // bit 2
11279 #define C1POL CM1CON0bits.C1POL // bit 4
11280 #define C1OUT CM1CON0bits.C1OUT // bit 6
11281 #define C1ON CM1CON0bits.C1ON // bit 7
11283 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
11284 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
11285 #define C1NCH2 CM1CON1bits.C1NCH2 // bit 2
11286 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 3
11287 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 4
11288 #define C1PCH2 CM1CON1bits.C1PCH2 // bit 5
11289 #define C1INTN CM1CON1bits.C1INTN // bit 6
11290 #define C1INTP CM1CON1bits.C1INTP // bit 7
11292 #define C2SYNC CM2CON0bits.C2SYNC // bit 0
11293 #define C2HYS CM2CON0bits.C2HYS // bit 1
11294 #define C2SP CM2CON0bits.C2SP // bit 2
11295 #define C2POL CM2CON0bits.C2POL // bit 4
11296 #define C2OUT CM2CON0bits.C2OUT // bit 6
11297 #define C2ON CM2CON0bits.C2ON // bit 7
11299 #define C2NCH0 CM2CON1bits.C2NCH0 // bit 0
11300 #define C2NCH1 CM2CON1bits.C2NCH1 // bit 1
11301 #define C2NCH2 CM2CON1bits.C2NCH2 // bit 2
11302 #define C2PCH0 CM2CON1bits.C2PCH0 // bit 3
11303 #define C2PCH1 CM2CON1bits.C2PCH1 // bit 4
11304 #define C2PCH2 CM2CON1bits.C2PCH2 // bit 5
11305 #define C2INTN CM2CON1bits.C2INTN // bit 6
11306 #define C2INTP CM2CON1bits.C2INTP // bit 7
11308 #define MC1OUT CMOUTbits.MC1OUT // bit 0
11309 #define MC2OUT CMOUTbits.MC2OUT // bit 1
11311 #define DOZE0 CPUDOZEbits.DOZE0 // bit 0
11312 #define DOZE1 CPUDOZEbits.DOZE1 // bit 1
11313 #define DOZE2 CPUDOZEbits.DOZE2 // bit 2
11314 #define DOE CPUDOZEbits.DOE // bit 4
11315 #define ROI CPUDOZEbits.ROI // bit 5
11316 #define DOZEN CPUDOZEbits.DOZEN // bit 6
11317 #define IDLEN CPUDOZEbits.IDLEN // bit 7
11319 #define LSAC0 CWG1AS0bits.LSAC0 // bit 2, shadows bit in CWG1AS0bits
11320 #define CWG1LSAC0 CWG1AS0bits.CWG1LSAC0 // bit 2, shadows bit in CWG1AS0bits
11321 #define LSAC1 CWG1AS0bits.LSAC1 // bit 3, shadows bit in CWG1AS0bits
11322 #define CWG1LSAC1 CWG1AS0bits.CWG1LSAC1 // bit 3, shadows bit in CWG1AS0bits
11323 #define LSBD0 CWG1AS0bits.LSBD0 // bit 4, shadows bit in CWG1AS0bits
11324 #define CWG1LSBD0 CWG1AS0bits.CWG1LSBD0 // bit 4, shadows bit in CWG1AS0bits
11325 #define LSBD1 CWG1AS0bits.LSBD1 // bit 5, shadows bit in CWG1AS0bits
11326 #define CWG1LSBD1 CWG1AS0bits.CWG1LSBD1 // bit 5, shadows bit in CWG1AS0bits
11327 #define REN CWG1AS0bits.REN // bit 6, shadows bit in CWG1AS0bits
11328 #define CWG1REN CWG1AS0bits.CWG1REN // bit 6, shadows bit in CWG1AS0bits
11329 #define SHUTDOWN CWG1AS0bits.SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
11330 #define CWG1SHUTDOWN CWG1AS0bits.CWG1SHUTDOWN // bit 7, shadows bit in CWG1AS0bits
11332 #define AS0E CWG1AS1bits.AS0E // bit 0
11333 #define AS1E CWG1AS1bits.AS1E // bit 1
11334 #define AS2E CWG1AS1bits.AS2E // bit 2
11335 #define AS3E CWG1AS1bits.AS3E // bit 3
11336 #define AS4E CWG1AS1bits.AS4E // bit 4
11338 #define CS CWG1CLKCONbits.CS // bit 0, shadows bit in CWG1CLKCONbits
11339 #define CWG1CS CWG1CLKCONbits.CWG1CS // bit 0, shadows bit in CWG1CLKCONbits
11341 #define POLA CWG1CON1bits.POLA // bit 0, shadows bit in CWG1CON1bits
11342 #define CWG1POLA CWG1CON1bits.CWG1POLA // bit 0, shadows bit in CWG1CON1bits
11343 #define POLB CWG1CON1bits.POLB // bit 1, shadows bit in CWG1CON1bits
11344 #define CWG1POLB CWG1CON1bits.CWG1POLB // bit 1, shadows bit in CWG1CON1bits
11345 #define POLC CWG1CON1bits.POLC // bit 2, shadows bit in CWG1CON1bits
11346 #define CWG1POLC CWG1CON1bits.CWG1POLC // bit 2, shadows bit in CWG1CON1bits
11347 #define POLD CWG1CON1bits.POLD // bit 3, shadows bit in CWG1CON1bits
11348 #define CWG1POLD CWG1CON1bits.CWG1POLD // bit 3, shadows bit in CWG1CON1bits
11349 #define IN CWG1CON1bits.IN // bit 5, shadows bit in CWG1CON1bits
11350 #define CWG1IN CWG1CON1bits.CWG1IN // bit 5, shadows bit in CWG1CON1bits
11352 #define CWG1DAT0 CWG1DATbits.CWG1DAT0 // bit 0
11353 #define CWG1DAT1 CWG1DATbits.CWG1DAT1 // bit 1
11354 #define CWG1DAT2 CWG1DATbits.CWG1DAT2 // bit 2
11355 #define CWG1DAT3 CWG1DATbits.CWG1DAT3 // bit 3
11357 #define DBF0 CWG1DBFbits.DBF0 // bit 0, shadows bit in CWG1DBFbits
11358 #define CWG1DBF0 CWG1DBFbits.CWG1DBF0 // bit 0, shadows bit in CWG1DBFbits
11359 #define DBF1 CWG1DBFbits.DBF1 // bit 1, shadows bit in CWG1DBFbits
11360 #define CWG1DBF1 CWG1DBFbits.CWG1DBF1 // bit 1, shadows bit in CWG1DBFbits
11361 #define DBF2 CWG1DBFbits.DBF2 // bit 2, shadows bit in CWG1DBFbits
11362 #define CWG1DBF2 CWG1DBFbits.CWG1DBF2 // bit 2, shadows bit in CWG1DBFbits
11363 #define DBF3 CWG1DBFbits.DBF3 // bit 3, shadows bit in CWG1DBFbits
11364 #define CWG1DBF3 CWG1DBFbits.CWG1DBF3 // bit 3, shadows bit in CWG1DBFbits
11365 #define DBF4 CWG1DBFbits.DBF4 // bit 4, shadows bit in CWG1DBFbits
11366 #define CWG1DBF4 CWG1DBFbits.CWG1DBF4 // bit 4, shadows bit in CWG1DBFbits
11367 #define DBF5 CWG1DBFbits.DBF5 // bit 5, shadows bit in CWG1DBFbits
11368 #define CWG1DBF5 CWG1DBFbits.CWG1DBF5 // bit 5, shadows bit in CWG1DBFbits
11370 #define DBR0 CWG1DBRbits.DBR0 // bit 0, shadows bit in CWG1DBRbits
11371 #define CWG1DBR0 CWG1DBRbits.CWG1DBR0 // bit 0, shadows bit in CWG1DBRbits
11372 #define DBR1 CWG1DBRbits.DBR1 // bit 1, shadows bit in CWG1DBRbits
11373 #define CWG1DBR1 CWG1DBRbits.CWG1DBR1 // bit 1, shadows bit in CWG1DBRbits
11374 #define DBR2 CWG1DBRbits.DBR2 // bit 2, shadows bit in CWG1DBRbits
11375 #define CWG1DBR2 CWG1DBRbits.CWG1DBR2 // bit 2, shadows bit in CWG1DBRbits
11376 #define DBR3 CWG1DBRbits.DBR3 // bit 3, shadows bit in CWG1DBRbits
11377 #define CWG1DBR3 CWG1DBRbits.CWG1DBR3 // bit 3, shadows bit in CWG1DBRbits
11378 #define DBR4 CWG1DBRbits.DBR4 // bit 4, shadows bit in CWG1DBRbits
11379 #define CWG1DBR4 CWG1DBRbits.CWG1DBR4 // bit 4, shadows bit in CWG1DBRbits
11380 #define DBR5 CWG1DBRbits.DBR5 // bit 5, shadows bit in CWG1DBRbits
11381 #define CWG1DBR5 CWG1DBRbits.CWG1DBR5 // bit 5, shadows bit in CWG1DBRbits
11383 #define CWG1PPS0 CWG1PPSbits.CWG1PPS0 // bit 0
11384 #define CWG1PPS1 CWG1PPSbits.CWG1PPS1 // bit 1
11385 #define CWG1PPS2 CWG1PPSbits.CWG1PPS2 // bit 2
11386 #define CWG1PPS3 CWG1PPSbits.CWG1PPS3 // bit 3
11387 #define CWG1PPS4 CWG1PPSbits.CWG1PPS4 // bit 4
11389 #define STRA CWG1STRbits.STRA // bit 0, shadows bit in CWG1STRbits
11390 #define CWG1STRA CWG1STRbits.CWG1STRA // bit 0, shadows bit in CWG1STRbits
11391 #define STRB CWG1STRbits.STRB // bit 1, shadows bit in CWG1STRbits
11392 #define CWG1STRB CWG1STRbits.CWG1STRB // bit 1, shadows bit in CWG1STRbits
11393 #define STRC CWG1STRbits.STRC // bit 2, shadows bit in CWG1STRbits
11394 #define CWG1STRC CWG1STRbits.CWG1STRC // bit 2, shadows bit in CWG1STRbits
11395 #define STRD CWG1STRbits.STRD // bit 3, shadows bit in CWG1STRbits
11396 #define CWG1STRD CWG1STRbits.CWG1STRD // bit 3, shadows bit in CWG1STRbits
11397 #define OVRA CWG1STRbits.OVRA // bit 4, shadows bit in CWG1STRbits
11398 #define CWG1OVRA CWG1STRbits.CWG1OVRA // bit 4, shadows bit in CWG1STRbits
11399 #define OVRB CWG1STRbits.OVRB // bit 5, shadows bit in CWG1STRbits
11400 #define CWG1OVRB CWG1STRbits.CWG1OVRB // bit 5, shadows bit in CWG1STRbits
11401 #define OVRC CWG1STRbits.OVRC // bit 6, shadows bit in CWG1STRbits
11402 #define CWG1OVRC CWG1STRbits.CWG1OVRC // bit 6, shadows bit in CWG1STRbits
11403 #define OVRD CWG1STRbits.OVRD // bit 7, shadows bit in CWG1STRbits
11404 #define CWG1OVRD CWG1STRbits.CWG1OVRD // bit 7, shadows bit in CWG1STRbits
11406 #define CWG2DAT0 CWG2DATbits.CWG2DAT0 // bit 0
11407 #define CWG2DAT1 CWG2DATbits.CWG2DAT1 // bit 1
11408 #define CWG2DAT2 CWG2DATbits.CWG2DAT2 // bit 2
11409 #define CWG2DAT3 CWG2DATbits.CWG2DAT3 // bit 3
11411 #define CWG2PPS0 CWG2PPSbits.CWG2PPS0 // bit 0
11412 #define CWG2PPS1 CWG2PPSbits.CWG2PPS1 // bit 1
11413 #define CWG2PPS2 CWG2PPSbits.CWG2PPS2 // bit 2
11414 #define CWG2PPS3 CWG2PPSbits.CWG2PPS3 // bit 3
11415 #define CWG2PPS4 CWG2PPSbits.CWG2PPS4 // bit 4
11417 #define DAC1NSS DACCON0bits.DAC1NSS // bit 0
11418 #define DAC1PSS0 DACCON0bits.DAC1PSS0 // bit 2
11419 #define DAC1PSS1 DACCON0bits.DAC1PSS1 // bit 3
11420 #define DAC1OE DACCON0bits.DAC1OE // bit 5
11421 #define DAC1EN DACCON0bits.DAC1EN // bit 7
11423 #define DAC1R0 DACCON1bits.DAC1R0 // bit 0
11424 #define DAC1R1 DACCON1bits.DAC1R1 // bit 1
11425 #define DAC1R2 DACCON1bits.DAC1R2 // bit 2
11426 #define DAC1R3 DACCON1bits.DAC1R3 // bit 3
11427 #define DAC1R4 DACCON1bits.DAC1R4 // bit 4
11429 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
11430 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
11431 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
11432 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
11433 #define TSRNG FVRCONbits.TSRNG // bit 4
11434 #define TSEN FVRCONbits.TSEN // bit 5
11435 #define FVRRDY FVRCONbits.FVRRDY // bit 6
11436 #define FVREN FVRCONbits.FVREN // bit 7
11438 #define INLVLA0 INLVLAbits.INLVLA0 // bit 0
11439 #define INLVLA1 INLVLAbits.INLVLA1 // bit 1
11440 #define INLVLA2 INLVLAbits.INLVLA2 // bit 2
11441 #define INLVLA3 INLVLAbits.INLVLA3 // bit 3
11442 #define INLVLA4 INLVLAbits.INLVLA4 // bit 4
11443 #define INLVLA5 INLVLAbits.INLVLA5 // bit 5
11445 #define INLVLB4 INLVLBbits.INLVLB4 // bit 4
11446 #define INLVLB5 INLVLBbits.INLVLB5 // bit 5
11447 #define INLVLB6 INLVLBbits.INLVLB6 // bit 6
11448 #define INLVLB7 INLVLBbits.INLVLB7 // bit 7
11450 #define INLVLC0 INLVLCbits.INLVLC0 // bit 0
11451 #define INLVLC1 INLVLCbits.INLVLC1 // bit 1
11452 #define INLVLC2 INLVLCbits.INLVLC2 // bit 2
11453 #define INLVLC3 INLVLCbits.INLVLC3 // bit 3
11454 #define INLVLC4 INLVLCbits.INLVLC4 // bit 4
11455 #define INLVLC5 INLVLCbits.INLVLC5 // bit 5
11456 #define INLVLC6 INLVLCbits.INLVLC6 // bit 6
11457 #define INLVLC7 INLVLCbits.INLVLC7 // bit 7
11459 #define INTEDG INTCONbits.INTEDG // bit 0
11460 #define PEIE INTCONbits.PEIE // bit 6
11461 #define GIE INTCONbits.GIE // bit 7
11463 #define INTPPS0 INTPPSbits.INTPPS0 // bit 0
11464 #define INTPPS1 INTPPSbits.INTPPS1 // bit 1
11465 #define INTPPS2 INTPPSbits.INTPPS2 // bit 2
11466 #define INTPPS3 INTPPSbits.INTPPS3 // bit 3
11467 #define INTPPS4 INTPPSbits.INTPPS4 // bit 4
11469 #define IOCAF0 IOCAFbits.IOCAF0 // bit 0
11470 #define IOCAF1 IOCAFbits.IOCAF1 // bit 1
11471 #define IOCAF2 IOCAFbits.IOCAF2 // bit 2
11472 #define IOCAF3 IOCAFbits.IOCAF3 // bit 3
11473 #define IOCAF4 IOCAFbits.IOCAF4 // bit 4
11474 #define IOCAF5 IOCAFbits.IOCAF5 // bit 5
11476 #define IOCAN0 IOCANbits.IOCAN0 // bit 0
11477 #define IOCAN1 IOCANbits.IOCAN1 // bit 1
11478 #define IOCAN2 IOCANbits.IOCAN2 // bit 2
11479 #define IOCAN3 IOCANbits.IOCAN3 // bit 3
11480 #define IOCAN4 IOCANbits.IOCAN4 // bit 4
11481 #define IOCAN5 IOCANbits.IOCAN5 // bit 5
11483 #define IOCAP0 IOCAPbits.IOCAP0 // bit 0
11484 #define IOCAP1 IOCAPbits.IOCAP1 // bit 1
11485 #define IOCAP2 IOCAPbits.IOCAP2 // bit 2
11486 #define IOCAP3 IOCAPbits.IOCAP3 // bit 3
11487 #define IOCAP4 IOCAPbits.IOCAP4 // bit 4
11488 #define IOCAP5 IOCAPbits.IOCAP5 // bit 5
11490 #define IOCBF4 IOCBFbits.IOCBF4 // bit 4
11491 #define IOCBF5 IOCBFbits.IOCBF5 // bit 5
11492 #define IOCBF6 IOCBFbits.IOCBF6 // bit 6
11493 #define IOCBF7 IOCBFbits.IOCBF7 // bit 7
11495 #define IOCBN4 IOCBNbits.IOCBN4 // bit 4
11496 #define IOCBN5 IOCBNbits.IOCBN5 // bit 5
11497 #define IOCBN6 IOCBNbits.IOCBN6 // bit 6
11498 #define IOCBN7 IOCBNbits.IOCBN7 // bit 7
11500 #define IOCBP4 IOCBPbits.IOCBP4 // bit 4
11501 #define IOCBP5 IOCBPbits.IOCBP5 // bit 5
11502 #define IOCBP6 IOCBPbits.IOCBP6 // bit 6
11503 #define IOCBP7 IOCBPbits.IOCBP7 // bit 7
11505 #define IOCCF0 IOCCFbits.IOCCF0 // bit 0
11506 #define IOCCF1 IOCCFbits.IOCCF1 // bit 1
11507 #define IOCCF2 IOCCFbits.IOCCF2 // bit 2
11508 #define IOCCF3 IOCCFbits.IOCCF3 // bit 3
11509 #define IOCCF4 IOCCFbits.IOCCF4 // bit 4
11510 #define IOCCF5 IOCCFbits.IOCCF5 // bit 5
11511 #define IOCCF6 IOCCFbits.IOCCF6 // bit 6
11512 #define IOCCF7 IOCCFbits.IOCCF7 // bit 7
11514 #define IOCCN0 IOCCNbits.IOCCN0 // bit 0
11515 #define IOCCN1 IOCCNbits.IOCCN1 // bit 1
11516 #define IOCCN2 IOCCNbits.IOCCN2 // bit 2
11517 #define IOCCN3 IOCCNbits.IOCCN3 // bit 3
11518 #define IOCCN4 IOCCNbits.IOCCN4 // bit 4
11519 #define IOCCN5 IOCCNbits.IOCCN5 // bit 5
11520 #define IOCCN6 IOCCNbits.IOCCN6 // bit 6
11521 #define IOCCN7 IOCCNbits.IOCCN7 // bit 7
11523 #define IOCCP0 IOCCPbits.IOCCP0 // bit 0
11524 #define IOCCP1 IOCCPbits.IOCCP1 // bit 1
11525 #define IOCCP2 IOCCPbits.IOCCP2 // bit 2
11526 #define IOCCP3 IOCCPbits.IOCCP3 // bit 3
11527 #define IOCCP4 IOCCPbits.IOCCP4 // bit 4
11528 #define IOCCP5 IOCCPbits.IOCCP5 // bit 5
11529 #define IOCCP6 IOCCPbits.IOCCP6 // bit 6
11530 #define IOCCP7 IOCCPbits.IOCCP7 // bit 7
11532 #define LATA0 LATAbits.LATA0 // bit 0
11533 #define LATA1 LATAbits.LATA1 // bit 1
11534 #define LATA2 LATAbits.LATA2 // bit 2
11535 #define LATA4 LATAbits.LATA4 // bit 4
11536 #define LATA5 LATAbits.LATA5 // bit 5
11538 #define LATB4 LATBbits.LATB4 // bit 4
11539 #define LATB5 LATBbits.LATB5 // bit 5
11540 #define LATB6 LATBbits.LATB6 // bit 6
11541 #define LATB7 LATBbits.LATB7 // bit 7
11543 #define LATC0 LATCbits.LATC0 // bit 0
11544 #define LATC1 LATCbits.LATC1 // bit 1
11545 #define LATC2 LATCbits.LATC2 // bit 2
11546 #define LATC3 LATCbits.LATC3 // bit 3
11547 #define LATC4 LATCbits.LATC4 // bit 4
11548 #define LATC5 LATCbits.LATC5 // bit 5
11549 #define LATC6 LATCbits.LATC6 // bit 6
11550 #define LATC7 LATCbits.LATC7 // bit 7
11552 #define MDCH0 MDCARHbits.MDCH0 // bit 0
11553 #define MDCH1 MDCARHbits.MDCH1 // bit 1
11554 #define MDCH2 MDCARHbits.MDCH2 // bit 2
11555 #define MDCH3 MDCARHbits.MDCH3 // bit 3
11556 #define MDCHSYNC MDCARHbits.MDCHSYNC // bit 5
11557 #define MDCHPOL MDCARHbits.MDCHPOL // bit 6
11559 #define MDCL0 MDCARLbits.MDCL0 // bit 0
11560 #define MDCL1 MDCARLbits.MDCL1 // bit 1
11561 #define MDCL2 MDCARLbits.MDCL2 // bit 2
11562 #define MDCL3 MDCARLbits.MDCL3 // bit 3
11563 #define MDCLSYNC MDCARLbits.MDCLSYNC // bit 5
11564 #define MDCLPOL MDCARLbits.MDCLPOL // bit 6
11566 #define MDCIN1PPS0 MDCIN1PPSbits.MDCIN1PPS0 // bit 0
11567 #define MDCIN1PPS1 MDCIN1PPSbits.MDCIN1PPS1 // bit 1
11568 #define MDCIN1PPS2 MDCIN1PPSbits.MDCIN1PPS2 // bit 2
11569 #define MDCIN1PPS3 MDCIN1PPSbits.MDCIN1PPS3 // bit 3
11570 #define MDCIN1PPS4 MDCIN1PPSbits.MDCIN1PPS4 // bit 4
11572 #define MDCIN2PPS0 MDCIN2PPSbits.MDCIN2PPS0 // bit 0
11573 #define MDCIN2PPS1 MDCIN2PPSbits.MDCIN2PPS1 // bit 1
11574 #define MDCIN2PPS2 MDCIN2PPSbits.MDCIN2PPS2 // bit 2
11575 #define MDCIN2PPS3 MDCIN2PPSbits.MDCIN2PPS3 // bit 3
11576 #define MDCIN2PPS4 MDCIN2PPSbits.MDCIN2PPS4 // bit 4
11578 #define MDBIT MDCONbits.MDBIT // bit 0
11579 #define MDOUT MDCONbits.MDOUT // bit 3
11580 #define MDOPOL MDCONbits.MDOPOL // bit 4
11581 #define MDEN MDCONbits.MDEN // bit 7
11583 #define MDMINPPS0 MDMINPPSbits.MDMINPPS0 // bit 0
11584 #define MDMINPPS1 MDMINPPSbits.MDMINPPS1 // bit 1
11585 #define MDMINPPS2 MDMINPPSbits.MDMINPPS2 // bit 2
11586 #define MDMINPPS3 MDMINPPSbits.MDMINPPS3 // bit 3
11587 #define MDMINPPS4 MDMINPPSbits.MDMINPPS4 // bit 4
11589 #define MDMS0 MDSRCbits.MDMS0 // bit 0
11590 #define MDMS1 MDSRCbits.MDMS1 // bit 1
11591 #define MDMS2 MDSRCbits.MDMS2 // bit 2
11592 #define MDMS3 MDSRCbits.MDMS3 // bit 3
11594 #define N1PFM NCO1CONbits.N1PFM // bit 0
11595 #define N1POL NCO1CONbits.N1POL // bit 4
11596 #define N1OUT NCO1CONbits.N1OUT // bit 5
11597 #define N1EN NCO1CONbits.N1EN // bit 7
11599 #define NVMADR8 NVMADRHbits.NVMADR8 // bit 0
11600 #define NVMADR9 NVMADRHbits.NVMADR9 // bit 1
11601 #define NVMADR10 NVMADRHbits.NVMADR10 // bit 2
11602 #define NVMADR11 NVMADRHbits.NVMADR11 // bit 3
11603 #define NVMADR12 NVMADRHbits.NVMADR12 // bit 4
11604 #define NVMADR13 NVMADRHbits.NVMADR13 // bit 5
11605 #define NVMADR14 NVMADRHbits.NVMADR14 // bit 6
11607 #define NVMADR0 NVMADRLbits.NVMADR0 // bit 0
11608 #define NVMADR1 NVMADRLbits.NVMADR1 // bit 1
11609 #define NVMADR2 NVMADRLbits.NVMADR2 // bit 2
11610 #define NVMADR3 NVMADRLbits.NVMADR3 // bit 3
11611 #define NVMADR4 NVMADRLbits.NVMADR4 // bit 4
11612 #define NVMADR5 NVMADRLbits.NVMADR5 // bit 5
11613 #define NVMADR6 NVMADRLbits.NVMADR6 // bit 6
11614 #define NVMADR7 NVMADRLbits.NVMADR7 // bit 7
11616 #define RD NVMCON1bits.RD // bit 0
11617 #define WR NVMCON1bits.WR // bit 1
11618 #define WREN NVMCON1bits.WREN // bit 2
11619 #define WRERR NVMCON1bits.WRERR // bit 3
11620 #define FREE NVMCON1bits.FREE // bit 4
11621 #define LWLO NVMCON1bits.LWLO // bit 5
11622 #define NVMREGS NVMCON1bits.NVMREGS // bit 6
11624 #define NVMDAT8 NVMDATHbits.NVMDAT8 // bit 0
11625 #define NVMDAT9 NVMDATHbits.NVMDAT9 // bit 1
11626 #define NVMDAT10 NVMDATHbits.NVMDAT10 // bit 2
11627 #define NVMDAT11 NVMDATHbits.NVMDAT11 // bit 3
11628 #define NVMDAT12 NVMDATHbits.NVMDAT12 // bit 4
11629 #define NVMDAT13 NVMDATHbits.NVMDAT13 // bit 5
11631 #define NVMDAT0 NVMDATLbits.NVMDAT0 // bit 0
11632 #define NVMDAT1 NVMDATLbits.NVMDAT1 // bit 1
11633 #define NVMDAT2 NVMDATLbits.NVMDAT2 // bit 2
11634 #define NVMDAT3 NVMDATLbits.NVMDAT3 // bit 3
11635 #define NVMDAT4 NVMDATLbits.NVMDAT4 // bit 4
11636 #define NVMDAT5 NVMDATLbits.NVMDAT5 // bit 5
11637 #define NVMDAT6 NVMDATLbits.NVMDAT6 // bit 6
11638 #define NVMDAT7 NVMDATLbits.NVMDAT7 // bit 7
11640 #define ODCA0 ODCONAbits.ODCA0 // bit 0
11641 #define ODCA1 ODCONAbits.ODCA1 // bit 1
11642 #define ODCA2 ODCONAbits.ODCA2 // bit 2
11643 #define ODCA4 ODCONAbits.ODCA4 // bit 4
11644 #define ODCA5 ODCONAbits.ODCA5 // bit 5
11646 #define ODCB4 ODCONBbits.ODCB4 // bit 4
11647 #define ODCB5 ODCONBbits.ODCB5 // bit 5
11648 #define ODCB6 ODCONBbits.ODCB6 // bit 6
11649 #define ODCB7 ODCONBbits.ODCB7 // bit 7
11651 #define ODCC0 ODCONCbits.ODCC0 // bit 0
11652 #define ODCC1 ODCONCbits.ODCC1 // bit 1
11653 #define ODCC2 ODCONCbits.ODCC2 // bit 2
11654 #define ODCC3 ODCONCbits.ODCC3 // bit 3
11655 #define ODCC4 ODCONCbits.ODCC4 // bit 4
11656 #define ODCC5 ODCONCbits.ODCC5 // bit 5
11657 #define ODCC6 ODCONCbits.ODCC6 // bit 6
11658 #define ODCC7 ODCONCbits.ODCC7 // bit 7
11660 #define NDIV0 OSCCON1bits.NDIV0 // bit 0
11661 #define NDIV1 OSCCON1bits.NDIV1 // bit 1
11662 #define NDIV2 OSCCON1bits.NDIV2 // bit 2
11663 #define NDIV3 OSCCON1bits.NDIV3 // bit 3
11664 #define NOSC0 OSCCON1bits.NOSC0 // bit 4
11665 #define NOSC1 OSCCON1bits.NOSC1 // bit 5
11666 #define NOSC2 OSCCON1bits.NOSC2 // bit 6
11668 #define CDIV0 OSCCON2bits.CDIV0 // bit 0
11669 #define CDIV1 OSCCON2bits.CDIV1 // bit 1
11670 #define CDIV2 OSCCON2bits.CDIV2 // bit 2
11671 #define CDIV3 OSCCON2bits.CDIV3 // bit 3
11672 #define COSC0 OSCCON2bits.COSC0 // bit 4
11673 #define COSC1 OSCCON2bits.COSC1 // bit 5
11674 #define COSC2 OSCCON2bits.COSC2 // bit 6
11676 #define NOSCR OSCCON3bits.NOSCR // bit 3
11677 #define ORDY OSCCON3bits.ORDY // bit 4
11678 #define SOSCBE OSCCON3bits.SOSCBE // bit 5
11679 #define SOSCPWR OSCCON3bits.SOSCPWR // bit 6
11680 #define CSWHOLD OSCCON3bits.CSWHOLD // bit 7
11682 #define ADOEN OSCENbits.ADOEN // bit 2
11683 #define SOSCEN OSCENbits.SOSCEN // bit 3
11684 #define LFOEN OSCENbits.LFOEN // bit 4
11685 #define HFOEN OSCENbits.HFOEN // bit 6
11686 #define EXTOEN OSCENbits.EXTOEN // bit 7
11688 #define HFFRQ0 OSCFRQbits.HFFRQ0 // bit 0
11689 #define HFFRQ1 OSCFRQbits.HFFRQ1 // bit 1
11690 #define HFFRQ2 OSCFRQbits.HFFRQ2 // bit 2
11691 #define HFFRQ3 OSCFRQbits.HFFRQ3 // bit 3
11693 #define PLLR OSCSTAT1bits.PLLR // bit 0
11694 #define ADOR OSCSTAT1bits.ADOR // bit 2
11695 #define SOR OSCSTAT1bits.SOR // bit 3
11696 #define LFOR OSCSTAT1bits.LFOR // bit 4
11697 #define HFOR OSCSTAT1bits.HFOR // bit 6
11698 #define EXTOR OSCSTAT1bits.EXTOR // bit 7
11700 #define HFTUN0 OSCTUNEbits.HFTUN0 // bit 0
11701 #define HFTUN1 OSCTUNEbits.HFTUN1 // bit 1
11702 #define HFTUN2 OSCTUNEbits.HFTUN2 // bit 2
11703 #define HFTUN3 OSCTUNEbits.HFTUN3 // bit 3
11704 #define HFTUN4 OSCTUNEbits.HFTUN4 // bit 4
11705 #define HFTUN5 OSCTUNEbits.HFTUN5 // bit 5
11707 #define NOT_BOR PCON0bits.NOT_BOR // bit 0
11708 #define NOT_POR PCON0bits.NOT_POR // bit 1
11709 #define NOT_RI PCON0bits.NOT_RI // bit 2
11710 #define NOT_RMCLR PCON0bits.NOT_RMCLR // bit 3
11711 #define NOT_RWDT PCON0bits.NOT_RWDT // bit 4
11712 #define STKUNF PCON0bits.STKUNF // bit 6
11713 #define STKOVF PCON0bits.STKOVF // bit 7
11715 #define INTE PIE0bits.INTE // bit 0
11716 #define IOCIE PIE0bits.IOCIE // bit 4
11717 #define TMR0IE PIE0bits.TMR0IE // bit 5
11719 #define TMR1IE PIE1bits.TMR1IE // bit 0
11720 #define TMR2IE PIE1bits.TMR2IE // bit 1
11721 #define BCL1IE PIE1bits.BCL1IE // bit 2
11722 #define SSP1IE PIE1bits.SSP1IE // bit 3
11723 #define TXIE PIE1bits.TXIE // bit 4
11724 #define RCIE PIE1bits.RCIE // bit 5
11725 #define ADIE PIE1bits.ADIE // bit 6
11726 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
11728 #define NCO1IE PIE2bits.NCO1IE // bit 0
11729 #define TMR4IE PIE2bits.TMR4IE // bit 1
11730 #define BCL2IE PIE2bits.BCL2IE // bit 2
11731 #define SSP2IE PIE2bits.SSP2IE // bit 3
11732 #define NVMIE PIE2bits.NVMIE // bit 4
11733 #define C1IE PIE2bits.C1IE // bit 5
11734 #define C2IE PIE2bits.C2IE // bit 6
11735 #define TMR6IE PIE2bits.TMR6IE // bit 7
11737 #define CLC1IE PIE3bits.CLC1IE // bit 0
11738 #define CLC2IE PIE3bits.CLC2IE // bit 1
11739 #define CLC3IE PIE3bits.CLC3IE // bit 2
11740 #define CLC4IE PIE3bits.CLC4IE // bit 3
11741 #define TMR3IE PIE3bits.TMR3IE // bit 4
11742 #define TMR3GIE PIE3bits.TMR3GIE // bit 5
11743 #define CSWIE PIE3bits.CSWIE // bit 6
11744 #define OSFIE PIE3bits.OSFIE // bit 7
11746 #define CCP1IE PIE4bits.CCP1IE // bit 0
11747 #define CCP2IE PIE4bits.CCP2IE // bit 1
11748 #define CCP3IE PIE4bits.CCP3IE // bit 2
11749 #define CCP4IE PIE4bits.CCP4IE // bit 3
11750 #define TMR5IE PIE4bits.TMR5IE // bit 4
11751 #define TMR5GIE PIE4bits.TMR5GIE // bit 5
11752 #define CWG1IE PIE4bits.CWG1IE // bit 6
11753 #define CWG2IE PIE4bits.CWG2IE // bit 7
11755 #define INTF PIR0bits.INTF // bit 0
11756 #define IOCIF PIR0bits.IOCIF // bit 4
11757 #define TMR0IF PIR0bits.TMR0IF // bit 5
11759 #define TMR1IF PIR1bits.TMR1IF // bit 0
11760 #define TMR2IF PIR1bits.TMR2IF // bit 1
11761 #define BCL1IF PIR1bits.BCL1IF // bit 2
11762 #define SSP1IF PIR1bits.SSP1IF // bit 3
11763 #define TXIF PIR1bits.TXIF // bit 4
11764 #define RCIF PIR1bits.RCIF // bit 5
11765 #define ADIF PIR1bits.ADIF // bit 6
11766 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
11768 #define NCO1IF PIR2bits.NCO1IF // bit 0
11769 #define TMR4IF PIR2bits.TMR4IF // bit 1
11770 #define BCL2IF PIR2bits.BCL2IF // bit 2
11771 #define SSP2IF PIR2bits.SSP2IF // bit 3
11772 #define NVMIF PIR2bits.NVMIF // bit 4
11773 #define C1IF PIR2bits.C1IF // bit 5
11774 #define C2IF PIR2bits.C2IF // bit 6
11775 #define TMR6IF PIR2bits.TMR6IF // bit 7
11777 #define CLC1IF PIR3bits.CLC1IF // bit 0
11778 #define CLC2IF PIR3bits.CLC2IF // bit 1
11779 #define CLC3IF PIR3bits.CLC3IF // bit 2
11780 #define CLC4IF PIR3bits.CLC4IF // bit 3
11781 #define TMR3IF PIR3bits.TMR3IF // bit 4
11782 #define TMR3GIF PIR3bits.TMR3GIF // bit 5
11783 #define CSWIF PIR3bits.CSWIF // bit 6
11784 #define OSFIF PIR3bits.OSFIF // bit 7
11786 #define CCP1IF PIR4bits.CCP1IF // bit 0
11787 #define CCP2IF PIR4bits.CCP2IF // bit 1
11788 #define CCP3IF PIR4bits.CCP3IF // bit 2
11789 #define CCP4IF PIR4bits.CCP4IF // bit 3
11790 #define TMR5IF PIR4bits.TMR5IF // bit 4
11791 #define TMR5GIF PIR4bits.TMR5GIF // bit 5
11792 #define CWG1IF PIR4bits.CWG1IF // bit 6
11793 #define CWG2IF PIR4bits.CWG2IF // bit 7
11795 #define IOCMD PMD0bits.IOCMD // bit 0
11796 #define CLKRMD PMD0bits.CLKRMD // bit 1
11797 #define NVMMD PMD0bits.NVMMD // bit 2
11798 #define FVRMD PMD0bits.FVRMD // bit 6
11799 #define SYSCMD PMD0bits.SYSCMD // bit 7
11801 #define TMR0MD PMD1bits.TMR0MD // bit 0
11802 #define TMR1MD PMD1bits.TMR1MD // bit 1
11803 #define TMR2MD PMD1bits.TMR2MD // bit 2
11804 #define TMR3MD PMD1bits.TMR3MD // bit 3
11805 #define TMR4MD PMD1bits.TMR4MD // bit 4
11806 #define TMR5MD PMD1bits.TMR5MD // bit 5
11807 #define TMR6MD PMD1bits.TMR6MD // bit 6
11808 #define NCOMD PMD1bits.NCOMD // bit 7
11810 #define CMP1MD PMD2bits.CMP1MD // bit 1
11811 #define CMP2MD PMD2bits.CMP2MD // bit 2
11812 #define ADCMD PMD2bits.ADCMD // bit 5
11813 #define DACMD PMD2bits.DACMD // bit 6
11815 #define CCP1MD PMD3bits.CCP1MD // bit 0
11816 #define CCP2MD PMD3bits.CCP2MD // bit 1
11817 #define CCP3MD PMD3bits.CCP3MD // bit 2
11818 #define CCP4MD PMD3bits.CCP4MD // bit 3
11819 #define PWM5MD PMD3bits.PWM5MD // bit 4
11820 #define PWM6MD PMD3bits.PWM6MD // bit 5
11821 #define CWG1MD PMD3bits.CWG1MD // bit 6
11822 #define CWG2MD PMD3bits.CWG2MD // bit 7
11824 #define MSSP1MD PMD4bits.MSSP1MD // bit 1
11825 #define MSSP2MD PMD4bits.MSSP2MD // bit 2
11826 #define UART1MD PMD4bits.UART1MD // bit 5
11828 #define DSMMD PMD5bits.DSMMD // bit 0
11829 #define CLC1MD PMD5bits.CLC1MD // bit 1
11830 #define CLC2MD PMD5bits.CLC2MD // bit 2
11831 #define CLC3MD PMD5bits.CLC3MD // bit 3
11832 #define CLC4MD PMD5bits.CLC4MD // bit 4
11834 #define RA0 PORTAbits.RA0 // bit 0
11835 #define RA1 PORTAbits.RA1 // bit 1
11836 #define RA2 PORTAbits.RA2 // bit 2
11837 #define RA3 PORTAbits.RA3 // bit 3
11838 #define RA4 PORTAbits.RA4 // bit 4
11839 #define RA5 PORTAbits.RA5 // bit 5
11841 #define RB4 PORTBbits.RB4 // bit 4
11842 #define RB5 PORTBbits.RB5 // bit 5
11843 #define RB6 PORTBbits.RB6 // bit 6
11844 #define RB7 PORTBbits.RB7 // bit 7
11846 #define RC0 PORTCbits.RC0 // bit 0
11847 #define RC1 PORTCbits.RC1 // bit 1
11848 #define RC2 PORTCbits.RC2 // bit 2
11849 #define RC3 PORTCbits.RC3 // bit 3
11850 #define RC4 PORTCbits.RC4 // bit 4
11851 #define RC5 PORTCbits.RC5 // bit 5
11852 #define RC6 PORTCbits.RC6 // bit 6
11853 #define RC7 PORTCbits.RC7 // bit 7
11855 #define PPSLOCKED PPSLOCKbits.PPSLOCKED // bit 0
11857 #define PWM5POL PWM5CONbits.PWM5POL // bit 4
11858 #define PWM5OUT PWM5CONbits.PWM5OUT // bit 5
11859 #define PWM5EN PWM5CONbits.PWM5EN // bit 7
11861 #define PWM5DCH0 PWM5DCHbits.PWM5DCH0 // bit 0
11862 #define PWM5DCH1 PWM5DCHbits.PWM5DCH1 // bit 1
11863 #define PWM5DCH2 PWM5DCHbits.PWM5DCH2 // bit 2
11864 #define PWM5DCH3 PWM5DCHbits.PWM5DCH3 // bit 3
11865 #define PWM5DCH4 PWM5DCHbits.PWM5DCH4 // bit 4
11866 #define PWM5DCH5 PWM5DCHbits.PWM5DCH5 // bit 5
11867 #define PWM5DCH6 PWM5DCHbits.PWM5DCH6 // bit 6
11868 #define PWM5DCH7 PWM5DCHbits.PWM5DCH7 // bit 7
11870 #define PWM5DCL0 PWM5DCLbits.PWM5DCL0 // bit 6
11871 #define PWM5DCL1 PWM5DCLbits.PWM5DCL1 // bit 7
11873 #define PWM6POL PWM6CONbits.PWM6POL // bit 4
11874 #define PWM6OUT PWM6CONbits.PWM6OUT // bit 5
11875 #define PWM6EN PWM6CONbits.PWM6EN // bit 7
11877 #define PWM6DCH0 PWM6DCHbits.PWM6DCH0 // bit 0
11878 #define PWM6DCH1 PWM6DCHbits.PWM6DCH1 // bit 1
11879 #define PWM6DCH2 PWM6DCHbits.PWM6DCH2 // bit 2
11880 #define PWM6DCH3 PWM6DCHbits.PWM6DCH3 // bit 3
11881 #define PWM6DCH4 PWM6DCHbits.PWM6DCH4 // bit 4
11882 #define PWM6DCH5 PWM6DCHbits.PWM6DCH5 // bit 5
11883 #define PWM6DCH6 PWM6DCHbits.PWM6DCH6 // bit 6
11884 #define PWM6DCH7 PWM6DCHbits.PWM6DCH7 // bit 7
11886 #define PWM6DCL0 PWM6DCLbits.PWM6DCL0 // bit 6
11887 #define PWM6DCL1 PWM6DCLbits.PWM6DCL1 // bit 7
11889 #define P5TSEL0 PWMTMRSbits.P5TSEL0 // bit 0
11890 #define P5TSEL1 PWMTMRSbits.P5TSEL1 // bit 1
11891 #define P6TSEL0 PWMTMRSbits.P6TSEL0 // bit 2
11892 #define P6TSEL1 PWMTMRSbits.P6TSEL1 // bit 3
11894 #define RA0PPS0 RA0PPSbits.RA0PPS0 // bit 0
11895 #define RA0PPS1 RA0PPSbits.RA0PPS1 // bit 1
11896 #define RA0PPS2 RA0PPSbits.RA0PPS2 // bit 2
11897 #define RA0PPS3 RA0PPSbits.RA0PPS3 // bit 3
11898 #define RA0PPS4 RA0PPSbits.RA0PPS4 // bit 4
11900 #define RA1PPS0 RA1PPSbits.RA1PPS0 // bit 0
11901 #define RA1PPS1 RA1PPSbits.RA1PPS1 // bit 1
11902 #define RA1PPS2 RA1PPSbits.RA1PPS2 // bit 2
11903 #define RA1PPS3 RA1PPSbits.RA1PPS3 // bit 3
11904 #define RA1PPS4 RA1PPSbits.RA1PPS4 // bit 4
11906 #define RA2PPS0 RA2PPSbits.RA2PPS0 // bit 0
11907 #define RA2PPS1 RA2PPSbits.RA2PPS1 // bit 1
11908 #define RA2PPS2 RA2PPSbits.RA2PPS2 // bit 2
11909 #define RA2PPS3 RA2PPSbits.RA2PPS3 // bit 3
11910 #define RA2PPS4 RA2PPSbits.RA2PPS4 // bit 4
11912 #define RA4PPS0 RA4PPSbits.RA4PPS0 // bit 0
11913 #define RA4PPS1 RA4PPSbits.RA4PPS1 // bit 1
11914 #define RA4PPS2 RA4PPSbits.RA4PPS2 // bit 2
11915 #define RA4PPS3 RA4PPSbits.RA4PPS3 // bit 3
11916 #define RA4PPS4 RA4PPSbits.RA4PPS4 // bit 4
11918 #define RA5PPS0 RA5PPSbits.RA5PPS0 // bit 0
11919 #define RA5PPS1 RA5PPSbits.RA5PPS1 // bit 1
11920 #define RA5PPS2 RA5PPSbits.RA5PPS2 // bit 2
11921 #define RA5PPS3 RA5PPSbits.RA5PPS3 // bit 3
11922 #define RA5PPS4 RA5PPSbits.RA5PPS4 // bit 4
11924 #define RB4PPS0 RB4PPSbits.RB4PPS0 // bit 0
11925 #define RB4PPS1 RB4PPSbits.RB4PPS1 // bit 1
11926 #define RB4PPS2 RB4PPSbits.RB4PPS2 // bit 2
11927 #define RB4PPS3 RB4PPSbits.RB4PPS3 // bit 3
11928 #define RB4PPS4 RB4PPSbits.RB4PPS4 // bit 4
11930 #define RB5PPS0 RB5PPSbits.RB5PPS0 // bit 0
11931 #define RB5PPS1 RB5PPSbits.RB5PPS1 // bit 1
11932 #define RB5PPS2 RB5PPSbits.RB5PPS2 // bit 2
11933 #define RB5PPS3 RB5PPSbits.RB5PPS3 // bit 3
11934 #define RB5PPS4 RB5PPSbits.RB5PPS4 // bit 4
11936 #define RB6PPS0 RB6PPSbits.RB6PPS0 // bit 0
11937 #define RB6PPS1 RB6PPSbits.RB6PPS1 // bit 1
11938 #define RB6PPS2 RB6PPSbits.RB6PPS2 // bit 2
11939 #define RB6PPS3 RB6PPSbits.RB6PPS3 // bit 3
11940 #define RB6PPS4 RB6PPSbits.RB6PPS4 // bit 4
11942 #define RB7PPS0 RB7PPSbits.RB7PPS0 // bit 0
11943 #define RB7PPS1 RB7PPSbits.RB7PPS1 // bit 1
11944 #define RB7PPS2 RB7PPSbits.RB7PPS2 // bit 2
11945 #define RB7PPS3 RB7PPSbits.RB7PPS3 // bit 3
11946 #define RB7PPS4 RB7PPSbits.RB7PPS4 // bit 4
11948 #define RC0PPS0 RC0PPSbits.RC0PPS0 // bit 0
11949 #define RC0PPS1 RC0PPSbits.RC0PPS1 // bit 1
11950 #define RC0PPS2 RC0PPSbits.RC0PPS2 // bit 2
11951 #define RC0PPS3 RC0PPSbits.RC0PPS3 // bit 3
11952 #define RC0PPS4 RC0PPSbits.RC0PPS4 // bit 4
11954 #define RC1PPS0 RC1PPSbits.RC1PPS0 // bit 0
11955 #define RC1PPS1 RC1PPSbits.RC1PPS1 // bit 1
11956 #define RC1PPS2 RC1PPSbits.RC1PPS2 // bit 2
11957 #define RC1PPS3 RC1PPSbits.RC1PPS3 // bit 3
11958 #define RC1PPS4 RC1PPSbits.RC1PPS4 // bit 4
11960 #define RX9D RC1STAbits.RX9D // bit 0
11961 #define OERR RC1STAbits.OERR // bit 1
11962 #define FERR RC1STAbits.FERR // bit 2
11963 #define ADDEN RC1STAbits.ADDEN // bit 3
11964 #define CREN RC1STAbits.CREN // bit 4
11965 #define SREN RC1STAbits.SREN // bit 5
11966 #define RX9 RC1STAbits.RX9 // bit 6
11967 #define SPEN RC1STAbits.SPEN // bit 7
11969 #define RC2PPS0 RC2PPSbits.RC2PPS0 // bit 0
11970 #define RC2PPS1 RC2PPSbits.RC2PPS1 // bit 1
11971 #define RC2PPS2 RC2PPSbits.RC2PPS2 // bit 2
11972 #define RC2PPS3 RC2PPSbits.RC2PPS3 // bit 3
11973 #define RC2PPS4 RC2PPSbits.RC2PPS4 // bit 4
11975 #define RC3PPS0 RC3PPSbits.RC3PPS0 // bit 0
11976 #define RC3PPS1 RC3PPSbits.RC3PPS1 // bit 1
11977 #define RC3PPS2 RC3PPSbits.RC3PPS2 // bit 2
11978 #define RC3PPS3 RC3PPSbits.RC3PPS3 // bit 3
11979 #define RC3PPS4 RC3PPSbits.RC3PPS4 // bit 4
11981 #define RC4PPS0 RC4PPSbits.RC4PPS0 // bit 0
11982 #define RC4PPS1 RC4PPSbits.RC4PPS1 // bit 1
11983 #define RC4PPS2 RC4PPSbits.RC4PPS2 // bit 2
11984 #define RC4PPS3 RC4PPSbits.RC4PPS3 // bit 3
11985 #define RC4PPS4 RC4PPSbits.RC4PPS4 // bit 4
11987 #define RC5PPS0 RC5PPSbits.RC5PPS0 // bit 0
11988 #define RC5PPS1 RC5PPSbits.RC5PPS1 // bit 1
11989 #define RC5PPS2 RC5PPSbits.RC5PPS2 // bit 2
11990 #define RC5PPS3 RC5PPSbits.RC5PPS3 // bit 3
11991 #define RC5PPS4 RC5PPSbits.RC5PPS4 // bit 4
11993 #define RC6PPS0 RC6PPSbits.RC6PPS0 // bit 0
11994 #define RC6PPS1 RC6PPSbits.RC6PPS1 // bit 1
11995 #define RC6PPS2 RC6PPSbits.RC6PPS2 // bit 2
11996 #define RC6PPS3 RC6PPSbits.RC6PPS3 // bit 3
11997 #define RC6PPS4 RC6PPSbits.RC6PPS4 // bit 4
11999 #define RC7PPS0 RC7PPSbits.RC7PPS0 // bit 0
12000 #define RC7PPS1 RC7PPSbits.RC7PPS1 // bit 1
12001 #define RC7PPS2 RC7PPSbits.RC7PPS2 // bit 2
12002 #define RC7PPS3 RC7PPSbits.RC7PPS3 // bit 3
12003 #define RC7PPS4 RC7PPSbits.RC7PPS4 // bit 4
12005 #define RXDTPPS0 RXPPSbits.RXDTPPS0 // bit 0
12006 #define RXDTPPS1 RXPPSbits.RXDTPPS1 // bit 1
12007 #define RXDTPPS2 RXPPSbits.RXDTPPS2 // bit 2
12008 #define RXDTPPS3 RXPPSbits.RXDTPPS3 // bit 3
12009 #define RXDTPPS4 RXPPSbits.RXDTPPS4 // bit 4
12011 #define SLRA0 SLRCONAbits.SLRA0 // bit 0
12012 #define SLRA1 SLRCONAbits.SLRA1 // bit 1
12013 #define SLRA2 SLRCONAbits.SLRA2 // bit 2
12014 #define SLRA4 SLRCONAbits.SLRA4 // bit 4
12015 #define SLRA5 SLRCONAbits.SLRA5 // bit 5
12017 #define SLRB4 SLRCONBbits.SLRB4 // bit 4
12018 #define SLRB5 SLRCONBbits.SLRB5 // bit 5
12019 #define SLRB6 SLRCONBbits.SLRB6 // bit 6
12020 #define SLRB7 SLRCONBbits.SLRB7 // bit 7
12022 #define SLRC0 SLRCONCbits.SLRC0 // bit 0
12023 #define SLRC1 SLRCONCbits.SLRC1 // bit 1
12024 #define SLRC2 SLRCONCbits.SLRC2 // bit 2
12025 #define SLRC3 SLRCONCbits.SLRC3 // bit 3
12026 #define SLRC4 SLRCONCbits.SLRC4 // bit 4
12027 #define SLRC5 SLRCONCbits.SLRC5 // bit 5
12028 #define SLRC6 SLRCONCbits.SLRC6 // bit 6
12029 #define SLRC7 SLRCONCbits.SLRC7 // bit 7
12031 #define SSP1ADD0 SSP1ADDbits.SSP1ADD0 // bit 0, shadows bit in SSP1ADDbits
12032 #define ADD0 SSP1ADDbits.ADD0 // bit 0, shadows bit in SSP1ADDbits
12033 #define SSP1ADD1 SSP1ADDbits.SSP1ADD1 // bit 1, shadows bit in SSP1ADDbits
12034 #define ADD1 SSP1ADDbits.ADD1 // bit 1, shadows bit in SSP1ADDbits
12035 #define SSP1ADD2 SSP1ADDbits.SSP1ADD2 // bit 2, shadows bit in SSP1ADDbits
12036 #define ADD2 SSP1ADDbits.ADD2 // bit 2, shadows bit in SSP1ADDbits
12037 #define SSP1ADD3 SSP1ADDbits.SSP1ADD3 // bit 3, shadows bit in SSP1ADDbits
12038 #define ADD3 SSP1ADDbits.ADD3 // bit 3, shadows bit in SSP1ADDbits
12039 #define SSP1ADD4 SSP1ADDbits.SSP1ADD4 // bit 4, shadows bit in SSP1ADDbits
12040 #define ADD4 SSP1ADDbits.ADD4 // bit 4, shadows bit in SSP1ADDbits
12041 #define SSP1ADD5 SSP1ADDbits.SSP1ADD5 // bit 5, shadows bit in SSP1ADDbits
12042 #define ADD5 SSP1ADDbits.ADD5 // bit 5, shadows bit in SSP1ADDbits
12043 #define SSP1ADD6 SSP1ADDbits.SSP1ADD6 // bit 6, shadows bit in SSP1ADDbits
12044 #define ADD6 SSP1ADDbits.ADD6 // bit 6, shadows bit in SSP1ADDbits
12045 #define SSP1ADD7 SSP1ADDbits.SSP1ADD7 // bit 7, shadows bit in SSP1ADDbits
12046 #define ADD7 SSP1ADDbits.ADD7 // bit 7, shadows bit in SSP1ADDbits
12048 #define SSP1BUF0 SSP1BUFbits.SSP1BUF0 // bit 0, shadows bit in SSP1BUFbits
12049 #define BUF0 SSP1BUFbits.BUF0 // bit 0, shadows bit in SSP1BUFbits
12050 #define SSP1BUF1 SSP1BUFbits.SSP1BUF1 // bit 1, shadows bit in SSP1BUFbits
12051 #define BUF1 SSP1BUFbits.BUF1 // bit 1, shadows bit in SSP1BUFbits
12052 #define SSP1BUF2 SSP1BUFbits.SSP1BUF2 // bit 2, shadows bit in SSP1BUFbits
12053 #define BUF2 SSP1BUFbits.BUF2 // bit 2, shadows bit in SSP1BUFbits
12054 #define SSP1BUF3 SSP1BUFbits.SSP1BUF3 // bit 3, shadows bit in SSP1BUFbits
12055 #define BUF3 SSP1BUFbits.BUF3 // bit 3, shadows bit in SSP1BUFbits
12056 #define SSP1BUF4 SSP1BUFbits.SSP1BUF4 // bit 4, shadows bit in SSP1BUFbits
12057 #define BUF4 SSP1BUFbits.BUF4 // bit 4, shadows bit in SSP1BUFbits
12058 #define SSP1BUF5 SSP1BUFbits.SSP1BUF5 // bit 5, shadows bit in SSP1BUFbits
12059 #define BUF5 SSP1BUFbits.BUF5 // bit 5, shadows bit in SSP1BUFbits
12060 #define SSP1BUF6 SSP1BUFbits.SSP1BUF6 // bit 6, shadows bit in SSP1BUFbits
12061 #define BUF6 SSP1BUFbits.BUF6 // bit 6, shadows bit in SSP1BUFbits
12062 #define SSP1BUF7 SSP1BUFbits.SSP1BUF7 // bit 7, shadows bit in SSP1BUFbits
12063 #define BUF7 SSP1BUFbits.BUF7 // bit 7, shadows bit in SSP1BUFbits
12065 #define SSP1CLKPPS0 SSP1CLKPPSbits.SSP1CLKPPS0 // bit 0
12066 #define SSP1CLKPPS1 SSP1CLKPPSbits.SSP1CLKPPS1 // bit 1
12067 #define SSP1CLKPPS2 SSP1CLKPPSbits.SSP1CLKPPS2 // bit 2
12068 #define SSP1CLKPPS3 SSP1CLKPPSbits.SSP1CLKPPS3 // bit 3
12069 #define SSP1CLKPPS4 SSP1CLKPPSbits.SSP1CLKPPS4 // bit 4
12071 #define SSPM0 SSP1CONbits.SSPM0 // bit 0
12072 #define SSPM1 SSP1CONbits.SSPM1 // bit 1
12073 #define SSPM2 SSP1CONbits.SSPM2 // bit 2
12074 #define SSPM3 SSP1CONbits.SSPM3 // bit 3
12075 #define CKP SSP1CONbits.CKP // bit 4
12076 #define SSPEN SSP1CONbits.SSPEN // bit 5
12077 #define SSPOV SSP1CONbits.SSPOV // bit 6
12078 #define WCOL SSP1CONbits.WCOL // bit 7
12080 #define SEN SSP1CON2bits.SEN // bit 0
12081 #define RSEN SSP1CON2bits.RSEN // bit 1
12082 #define PEN SSP1CON2bits.PEN // bit 2
12083 #define RCEN SSP1CON2bits.RCEN // bit 3
12084 #define ACKEN SSP1CON2bits.ACKEN // bit 4
12085 #define ACKDT SSP1CON2bits.ACKDT // bit 5
12086 #define ACKSTAT SSP1CON2bits.ACKSTAT // bit 6
12087 #define GCEN SSP1CON2bits.GCEN // bit 7
12089 #define DHEN SSP1CON3bits.DHEN // bit 0
12090 #define AHEN SSP1CON3bits.AHEN // bit 1
12091 #define SBCDE SSP1CON3bits.SBCDE // bit 2
12092 #define SDAHT SSP1CON3bits.SDAHT // bit 3
12093 #define BOEN SSP1CON3bits.BOEN // bit 4
12094 #define SCIE SSP1CON3bits.SCIE // bit 5
12095 #define PCIE SSP1CON3bits.PCIE // bit 6
12096 #define ACKTIM SSP1CON3bits.ACKTIM // bit 7
12098 #define SSP1DATPPS0 SSP1DATPPSbits.SSP1DATPPS0 // bit 0
12099 #define SSP1DATPPS1 SSP1DATPPSbits.SSP1DATPPS1 // bit 1
12100 #define SSP1DATPPS2 SSP1DATPPSbits.SSP1DATPPS2 // bit 2
12101 #define SSP1DATPPS3 SSP1DATPPSbits.SSP1DATPPS3 // bit 3
12102 #define SSP1DATPPS4 SSP1DATPPSbits.SSP1DATPPS4 // bit 4
12104 #define SSP1MSK0 SSP1MSKbits.SSP1MSK0 // bit 0, shadows bit in SSP1MSKbits
12105 #define MSK0 SSP1MSKbits.MSK0 // bit 0, shadows bit in SSP1MSKbits
12106 #define SSP1MSK1 SSP1MSKbits.SSP1MSK1 // bit 1, shadows bit in SSP1MSKbits
12107 #define MSK1 SSP1MSKbits.MSK1 // bit 1, shadows bit in SSP1MSKbits
12108 #define SSP1MSK2 SSP1MSKbits.SSP1MSK2 // bit 2, shadows bit in SSP1MSKbits
12109 #define MSK2 SSP1MSKbits.MSK2 // bit 2, shadows bit in SSP1MSKbits
12110 #define SSP1MSK3 SSP1MSKbits.SSP1MSK3 // bit 3, shadows bit in SSP1MSKbits
12111 #define MSK3 SSP1MSKbits.MSK3 // bit 3, shadows bit in SSP1MSKbits
12112 #define SSP1MSK4 SSP1MSKbits.SSP1MSK4 // bit 4, shadows bit in SSP1MSKbits
12113 #define MSK4 SSP1MSKbits.MSK4 // bit 4, shadows bit in SSP1MSKbits
12114 #define SSP1MSK5 SSP1MSKbits.SSP1MSK5 // bit 5, shadows bit in SSP1MSKbits
12115 #define MSK5 SSP1MSKbits.MSK5 // bit 5, shadows bit in SSP1MSKbits
12116 #define SSP1MSK6 SSP1MSKbits.SSP1MSK6 // bit 6, shadows bit in SSP1MSKbits
12117 #define MSK6 SSP1MSKbits.MSK6 // bit 6, shadows bit in SSP1MSKbits
12118 #define SSP1MSK7 SSP1MSKbits.SSP1MSK7 // bit 7, shadows bit in SSP1MSKbits
12119 #define MSK7 SSP1MSKbits.MSK7 // bit 7, shadows bit in SSP1MSKbits
12121 #define SSP1SSPPS0 SSP1SSPPSbits.SSP1SSPPS0 // bit 0
12122 #define SSP1SSPPS1 SSP1SSPPSbits.SSP1SSPPS1 // bit 1
12123 #define SSP1SSPPS2 SSP1SSPPSbits.SSP1SSPPS2 // bit 2
12124 #define SSP1SSPPS3 SSP1SSPPSbits.SSP1SSPPS3 // bit 3
12125 #define SSP1SSPPS4 SSP1SSPPSbits.SSP1SSPPS4 // bit 4
12127 #define BF SSP1STATbits.BF // bit 0
12128 #define UA SSP1STATbits.UA // bit 1
12129 #define R_NOT_W SSP1STATbits.R_NOT_W // bit 2
12130 #define S SSP1STATbits.S // bit 3
12131 #define P SSP1STATbits.P // bit 4
12132 #define D_NOT_A SSP1STATbits.D_NOT_A // bit 5
12133 #define CKE SSP1STATbits.CKE // bit 6
12134 #define SMP SSP1STATbits.SMP // bit 7
12136 #define SSP2CLKPPS0 SSP2CLKPPSbits.SSP2CLKPPS0 // bit 0
12137 #define SSP2CLKPPS1 SSP2CLKPPSbits.SSP2CLKPPS1 // bit 1
12138 #define SSP2CLKPPS2 SSP2CLKPPSbits.SSP2CLKPPS2 // bit 2
12139 #define SSP2CLKPPS3 SSP2CLKPPSbits.SSP2CLKPPS3 // bit 3
12140 #define SSP2CLKPPS4 SSP2CLKPPSbits.SSP2CLKPPS4 // bit 4
12142 #define SSP2DATPPS0 SSP2DATPPSbits.SSP2DATPPS0 // bit 0
12143 #define SSP2DATPPS1 SSP2DATPPSbits.SSP2DATPPS1 // bit 1
12144 #define SSP2DATPPS2 SSP2DATPPSbits.SSP2DATPPS2 // bit 2
12145 #define SSP2DATPPS3 SSP2DATPPSbits.SSP2DATPPS3 // bit 3
12146 #define SSP2DATPPS4 SSP2DATPPSbits.SSP2DATPPS4 // bit 4
12148 #define SSP2SSPPS0 SSP2SSPPSbits.SSP2SSPPS0 // bit 0
12149 #define SSP2SSPPS1 SSP2SSPPSbits.SSP2SSPPS1 // bit 1
12150 #define SSP2SSPPS2 SSP2SSPPSbits.SSP2SSPPS2 // bit 2
12151 #define SSP2SSPPS3 SSP2SSPPSbits.SSP2SSPPS3 // bit 3
12152 #define SSP2SSPPS4 SSP2SSPPSbits.SSP2SSPPS4 // bit 4
12154 #define C STATUSbits.C // bit 0
12155 #define DC STATUSbits.DC // bit 1
12156 #define Z STATUSbits.Z // bit 2
12157 #define NOT_PD STATUSbits.NOT_PD // bit 3
12158 #define NOT_TO STATUSbits.NOT_TO // bit 4
12160 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
12161 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
12162 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
12164 #define T0CKIPPS0 T0CKIPPSbits.T0CKIPPS0 // bit 0
12165 #define T0CKIPPS1 T0CKIPPSbits.T0CKIPPS1 // bit 1
12166 #define T0CKIPPS2 T0CKIPPSbits.T0CKIPPS2 // bit 2
12167 #define T0CKIPPS3 T0CKIPPSbits.T0CKIPPS3 // bit 3
12168 #define T0CKIPPS4 T0CKIPPSbits.T0CKIPPS4 // bit 4
12170 #define T0OUTPS0 T0CON0bits.T0OUTPS0 // bit 0
12171 #define T0OUTPS1 T0CON0bits.T0OUTPS1 // bit 1
12172 #define T0OUTPS2 T0CON0bits.T0OUTPS2 // bit 2
12173 #define T0OUTPS3 T0CON0bits.T0OUTPS3 // bit 3
12174 #define T016BIT T0CON0bits.T016BIT // bit 4
12175 #define T0OUT T0CON0bits.T0OUT // bit 5
12176 #define T0EN T0CON0bits.T0EN // bit 7
12178 #define T0CKPS0 T0CON1bits.T0CKPS0 // bit 0
12179 #define T0CKPS1 T0CON1bits.T0CKPS1 // bit 1
12180 #define T0CKPS2 T0CON1bits.T0CKPS2 // bit 2
12181 #define T0CKPS3 T0CON1bits.T0CKPS3 // bit 3
12182 #define T0ASYNC T0CON1bits.T0ASYNC // bit 4
12183 #define T0CS0 T0CON1bits.T0CS0 // bit 5
12184 #define T0CS1 T0CON1bits.T0CS1 // bit 6
12185 #define T0CS2 T0CON1bits.T0CS2 // bit 7
12187 #define T1CKIPPS0 T1CKIPPSbits.T1CKIPPS0 // bit 0
12188 #define T1CKIPPS1 T1CKIPPSbits.T1CKIPPS1 // bit 1
12189 #define T1CKIPPS2 T1CKIPPSbits.T1CKIPPS2 // bit 2
12190 #define T1CKIPPS3 T1CKIPPSbits.T1CKIPPS3 // bit 3
12191 #define T1CKIPPS4 T1CKIPPSbits.T1CKIPPS4 // bit 4
12193 #define TMR1ON T1CONbits.TMR1ON // bit 0
12194 #define T1SYNC T1CONbits.T1SYNC // bit 2
12195 #define T1SOSC T1CONbits.T1SOSC // bit 3
12196 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
12197 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
12198 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
12199 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
12201 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
12202 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
12203 #define T1GVAL T1GCONbits.T1GVAL // bit 2
12204 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3
12205 #define T1GSPM T1GCONbits.T1GSPM // bit 4
12206 #define T1GTM T1GCONbits.T1GTM // bit 5
12207 #define T1GPOL T1GCONbits.T1GPOL // bit 6
12208 #define TMR1GE T1GCONbits.TMR1GE // bit 7
12210 #define T1GPPS0 T1GPPSbits.T1GPPS0 // bit 0
12211 #define T1GPPS1 T1GPPSbits.T1GPPS1 // bit 1
12212 #define T1GPPS2 T1GPPSbits.T1GPPS2 // bit 2
12213 #define T1GPPS3 T1GPPSbits.T1GPPS3 // bit 3
12214 #define T1GPPS4 T1GPPSbits.T1GPPS4 // bit 4
12216 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
12217 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
12218 #define TMR2ON T2CONbits.TMR2ON // bit 2
12219 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
12220 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
12221 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
12222 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
12224 #define TMR3ON T3CONbits.TMR3ON // bit 0
12225 #define T3SYNC T3CONbits.T3SYNC // bit 2
12226 #define T3SOSC T3CONbits.T3SOSC // bit 3
12227 #define T3CKPS0 T3CONbits.T3CKPS0 // bit 4
12228 #define T3CKPS1 T3CONbits.T3CKPS1 // bit 5
12229 #define TMR3CS0 T3CONbits.TMR3CS0 // bit 6
12230 #define TMR3CS1 T3CONbits.TMR3CS1 // bit 7
12232 #define T3GSS0 T3GCONbits.T3GSS0 // bit 0
12233 #define T3GSS1 T3GCONbits.T3GSS1 // bit 1
12234 #define T3GVAL T3GCONbits.T3GVAL // bit 2
12235 #define T3GGO_NOT_DONE T3GCONbits.T3GGO_NOT_DONE // bit 3
12236 #define T3GSPM T3GCONbits.T3GSPM // bit 4
12237 #define T3GTM T3GCONbits.T3GTM // bit 5
12238 #define T3GPOL T3GCONbits.T3GPOL // bit 6
12239 #define TMR3GE T3GCONbits.TMR3GE // bit 7
12241 #define TMR5ON T5CONbits.TMR5ON // bit 0
12242 #define T5SYNC T5CONbits.T5SYNC // bit 2
12243 #define T5SOSC T5CONbits.T5SOSC // bit 3
12244 #define T5CKPS0 T5CONbits.T5CKPS0 // bit 4
12245 #define T5CKPS1 T5CONbits.T5CKPS1 // bit 5
12246 #define TMR5CS0 T5CONbits.TMR5CS0 // bit 6
12247 #define TMR5CS1 T5CONbits.TMR5CS1 // bit 7
12249 #define T5GSS0 T5GCONbits.T5GSS0 // bit 0
12250 #define T5GSS1 T5GCONbits.T5GSS1 // bit 1
12251 #define T5GVAL T5GCONbits.T5GVAL // bit 2
12252 #define T5GGO_NOT_DONE T5GCONbits.T5GGO_NOT_DONE // bit 3
12253 #define T5GSPM T5GCONbits.T5GSPM // bit 4
12254 #define T5GTM T5GCONbits.T5GTM // bit 5
12255 #define T5GPOL T5GCONbits.T5GPOL // bit 6
12256 #define TMR5GE T5GCONbits.TMR5GE // bit 7
12258 #define TMR08 TMR0Hbits.TMR08 // bit 0
12259 #define TMR09 TMR0Hbits.TMR09 // bit 1
12260 #define TMR010 TMR0Hbits.TMR010 // bit 2
12261 #define TMR011 TMR0Hbits.TMR011 // bit 3
12262 #define TMR012 TMR0Hbits.TMR012 // bit 4
12263 #define TMR013 TMR0Hbits.TMR013 // bit 5
12264 #define TMR014 TMR0Hbits.TMR014 // bit 6
12265 #define TMR015 TMR0Hbits.TMR015 // bit 7
12267 #define TMR00 TMR0Lbits.TMR00 // bit 0
12268 #define TMR01 TMR0Lbits.TMR01 // bit 1
12269 #define TMR02 TMR0Lbits.TMR02 // bit 2
12270 #define TMR03 TMR0Lbits.TMR03 // bit 3
12271 #define TMR04 TMR0Lbits.TMR04 // bit 4
12272 #define TMR05 TMR0Lbits.TMR05 // bit 5
12273 #define TMR06 TMR0Lbits.TMR06 // bit 6
12274 #define TMR07 TMR0Lbits.TMR07 // bit 7
12276 #define TRISA0 TRISAbits.TRISA0 // bit 0
12277 #define TRISA1 TRISAbits.TRISA1 // bit 1
12278 #define TRISA2 TRISAbits.TRISA2 // bit 2
12279 #define TRISA4 TRISAbits.TRISA4 // bit 4
12280 #define TRISA5 TRISAbits.TRISA5 // bit 5
12282 #define TRISB4 TRISBbits.TRISB4 // bit 4
12283 #define TRISB5 TRISBbits.TRISB5 // bit 5
12284 #define TRISB6 TRISBbits.TRISB6 // bit 6
12285 #define TRISB7 TRISBbits.TRISB7 // bit 7
12287 #define TRISC0 TRISCbits.TRISC0 // bit 0
12288 #define TRISC1 TRISCbits.TRISC1 // bit 1
12289 #define TRISC2 TRISCbits.TRISC2 // bit 2
12290 #define TRISC3 TRISCbits.TRISC3 // bit 3
12291 #define TRISC4 TRISCbits.TRISC4 // bit 4
12292 #define TRISC5 TRISCbits.TRISC5 // bit 5
12293 #define TRISC6 TRISCbits.TRISC6 // bit 6
12294 #define TRISC7 TRISCbits.TRISC7 // bit 7
12296 #define TX9D TX1STAbits.TX9D // bit 0
12297 #define TRMT TX1STAbits.TRMT // bit 1
12298 #define BRGH TX1STAbits.BRGH // bit 2
12299 #define SENDB TX1STAbits.SENDB // bit 3
12300 #define SYNC TX1STAbits.SYNC // bit 4
12301 #define TXEN TX1STAbits.TXEN // bit 5
12302 #define TX9 TX1STAbits.TX9 // bit 6
12303 #define CSRC TX1STAbits.CSRC // bit 7
12305 #define TXCKPPS0 TXPPSbits.TXCKPPS0 // bit 0
12306 #define TXCKPPS1 TXPPSbits.TXCKPPS1 // bit 1
12307 #define TXCKPPS2 TXPPSbits.TXCKPPS2 // bit 2
12308 #define TXCKPPS3 TXPPSbits.TXCKPPS3 // bit 3
12309 #define TXCKPPS4 TXPPSbits.TXCKPPS4 // bit 4
12311 #define SWDTEN WDTCONbits.SWDTEN // bit 0
12312 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
12313 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
12314 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
12315 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
12316 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
12318 #define WPUA0 WPUAbits.WPUA0 // bit 0
12319 #define WPUA1 WPUAbits.WPUA1 // bit 1
12320 #define WPUA2 WPUAbits.WPUA2 // bit 2
12321 #define WPUA3 WPUAbits.WPUA3 // bit 3
12322 #define WPUA4 WPUAbits.WPUA4 // bit 4
12323 #define WPUA5 WPUAbits.WPUA5 // bit 5
12325 #define WPUB4 WPUBbits.WPUB4 // bit 4
12326 #define WPUB5 WPUBbits.WPUB5 // bit 5
12327 #define WPUB6 WPUBbits.WPUB6 // bit 6
12328 #define WPUB7 WPUBbits.WPUB7 // bit 7
12330 #define WPUC0 WPUCbits.WPUC0 // bit 0
12331 #define WPUC1 WPUCbits.WPUC1 // bit 1
12332 #define WPUC2 WPUCbits.WPUC2 // bit 2
12333 #define WPUC3 WPUCbits.WPUC3 // bit 3
12334 #define WPUC4 WPUCbits.WPUC4 // bit 4
12335 #define WPUC5 WPUCbits.WPUC5 // bit 5
12336 #define WPUC6 WPUCbits.WPUC6 // bit 6
12337 #define WPUC7 WPUCbits.WPUC7 // bit 7
12339 #endif // #ifndef NO_BIT_DEFINES
12341 #endif // #ifndef __PIC16LF18345_H__