2 * This declarations of the PIC16LF1933 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:21 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16LF1933_H__
26 #define __PIC16LF1933_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTB_ADDR 0x000D
52 #define PORTC_ADDR 0x000E
53 #define PORTE_ADDR 0x0010
54 #define PIR1_ADDR 0x0011
55 #define PIR2_ADDR 0x0012
56 #define PIR3_ADDR 0x0013
57 #define TMR0_ADDR 0x0015
58 #define TMR1_ADDR 0x0016
59 #define TMR1L_ADDR 0x0016
60 #define TMR1H_ADDR 0x0017
61 #define T1CON_ADDR 0x0018
62 #define T1GCON_ADDR 0x0019
63 #define TMR2_ADDR 0x001A
64 #define PR2_ADDR 0x001B
65 #define T2CON_ADDR 0x001C
66 #define CPSCON0_ADDR 0x001E
67 #define CPSCON1_ADDR 0x001F
68 #define TRISA_ADDR 0x008C
69 #define TRISB_ADDR 0x008D
70 #define TRISC_ADDR 0x008E
71 #define TRISE_ADDR 0x0090
72 #define PIE1_ADDR 0x0091
73 #define PIE2_ADDR 0x0092
74 #define PIE3_ADDR 0x0093
75 #define OPTION_REG_ADDR 0x0095
76 #define PCON_ADDR 0x0096
77 #define WDTCON_ADDR 0x0097
78 #define OSCTUNE_ADDR 0x0098
79 #define OSCCON_ADDR 0x0099
80 #define OSCSTAT_ADDR 0x009A
81 #define ADRES_ADDR 0x009B
82 #define ADRESL_ADDR 0x009B
83 #define ADRESH_ADDR 0x009C
84 #define ADCON0_ADDR 0x009D
85 #define ADCON1_ADDR 0x009E
86 #define LATA_ADDR 0x010C
87 #define LATB_ADDR 0x010D
88 #define LATC_ADDR 0x010E
89 #define LATE_ADDR 0x0110
90 #define CM1CON0_ADDR 0x0111
91 #define CM1CON1_ADDR 0x0112
92 #define CM2CON0_ADDR 0x0113
93 #define CM2CON1_ADDR 0x0114
94 #define CMOUT_ADDR 0x0115
95 #define BORCON_ADDR 0x0116
96 #define FVRCON_ADDR 0x0117
97 #define DACCON0_ADDR 0x0118
98 #define DACCON1_ADDR 0x0119
99 #define SRCON0_ADDR 0x011A
100 #define SRCON1_ADDR 0x011B
101 #define APFCON_ADDR 0x011D
102 #define ANSELA_ADDR 0x018C
103 #define ANSELB_ADDR 0x018D
104 #define EEADR_ADDR 0x0191
105 #define EEADRL_ADDR 0x0191
106 #define EEADRH_ADDR 0x0192
107 #define EEDAT_ADDR 0x0193
108 #define EEDATL_ADDR 0x0193
109 #define EEDATH_ADDR 0x0194
110 #define EECON1_ADDR 0x0195
111 #define EECON2_ADDR 0x0196
112 #define RCREG_ADDR 0x0199
113 #define TXREG_ADDR 0x019A
114 #define SP1BRG_ADDR 0x019B
115 #define SP1BRGL_ADDR 0x019B
116 #define SPBRG_ADDR 0x019B
117 #define SPBRGL_ADDR 0x019B
118 #define SP1BRGH_ADDR 0x019C
119 #define SPBRGH_ADDR 0x019C
120 #define RCSTA_ADDR 0x019D
121 #define TXSTA_ADDR 0x019E
122 #define BAUDCON_ADDR 0x019F
123 #define WPUB_ADDR 0x020D
124 #define WPUE_ADDR 0x0210
125 #define SSPBUF_ADDR 0x0211
126 #define SSPADD_ADDR 0x0212
127 #define SSPMSK_ADDR 0x0213
128 #define SSPSTAT_ADDR 0x0214
129 #define SSPCON_ADDR 0x0215
130 #define SSPCON1_ADDR 0x0215
131 #define SSPCON2_ADDR 0x0216
132 #define SSPCON3_ADDR 0x0217
133 #define CCPR1_ADDR 0x0291
134 #define CCPR1L_ADDR 0x0291
135 #define CCPR1H_ADDR 0x0292
136 #define CCP1CON_ADDR 0x0293
137 #define PWM1CON_ADDR 0x0294
138 #define CCP1AS_ADDR 0x0295
139 #define ECCP1AS_ADDR 0x0295
140 #define PSTR1CON_ADDR 0x0296
141 #define CCPR2_ADDR 0x0298
142 #define CCPR2L_ADDR 0x0298
143 #define CCPR2H_ADDR 0x0299
144 #define CCP2CON_ADDR 0x029A
145 #define PWM2CON_ADDR 0x029B
146 #define CCP2AS_ADDR 0x029C
147 #define ECCP2AS_ADDR 0x029C
148 #define PSTR2CON_ADDR 0x029D
149 #define CCPTMRS0_ADDR 0x029E
150 #define CCPTMRS1_ADDR 0x029F
151 #define CCPR3_ADDR 0x0311
152 #define CCPR3L_ADDR 0x0311
153 #define CCPR3H_ADDR 0x0312
154 #define CCP3CON_ADDR 0x0313
155 #define PWM3CON_ADDR 0x0314
156 #define CCP3AS_ADDR 0x0315
157 #define ECCP3AS_ADDR 0x0315
158 #define PSTR3CON_ADDR 0x0316
159 #define CCPR4_ADDR 0x0318
160 #define CCPR4L_ADDR 0x0318
161 #define CCPR4H_ADDR 0x0319
162 #define CCP4CON_ADDR 0x031A
163 #define CCPR5_ADDR 0x031C
164 #define CCPR5L_ADDR 0x031C
165 #define CCPR5H_ADDR 0x031D
166 #define CCP5CON_ADDR 0x031E
167 #define IOCBP_ADDR 0x0394
168 #define IOCBN_ADDR 0x0395
169 #define IOCBF_ADDR 0x0396
170 #define TMR4_ADDR 0x0415
171 #define PR4_ADDR 0x0416
172 #define T4CON_ADDR 0x0417
173 #define TMR6_ADDR 0x041C
174 #define PR6_ADDR 0x041D
175 #define T6CON_ADDR 0x041E
176 #define LCDCON_ADDR 0x0791
177 #define LCDPS_ADDR 0x0792
178 #define LCDREF_ADDR 0x0793
179 #define LCDCST_ADDR 0x0794
180 #define LCDRL_ADDR 0x0795
181 #define LCDSE0_ADDR 0x0798
182 #define LCDSE1_ADDR 0x0799
183 #define LCDDATA0_ADDR 0x07A0
184 #define LCDDATA1_ADDR 0x07A1
185 #define LCDDATA3_ADDR 0x07A3
186 #define LCDDATA4_ADDR 0x07A4
187 #define LCDDATA6_ADDR 0x07A6
188 #define LCDDATA7_ADDR 0x07A7
189 #define LCDDATA9_ADDR 0x07A9
190 #define LCDDATA10_ADDR 0x07AA
191 #define STATUS_SHAD_ADDR 0x0FE4
192 #define WREG_SHAD_ADDR 0x0FE5
193 #define BSR_SHAD_ADDR 0x0FE6
194 #define PCLATH_SHAD_ADDR 0x0FE7
195 #define FSR0L_SHAD_ADDR 0x0FE8
196 #define FSR0H_SHAD_ADDR 0x0FE9
197 #define FSR1L_SHAD_ADDR 0x0FEA
198 #define FSR1H_SHAD_ADDR 0x0FEB
199 #define STKPTR_ADDR 0x0FED
200 #define TOSL_ADDR 0x0FEE
201 #define TOSH_ADDR 0x0FEF
203 #endif // #ifndef NO_ADDR_DEFINES
205 //==============================================================================
207 // Register Definitions
209 //==============================================================================
211 extern __at(0x0000) __sfr INDF0
;
212 extern __at(0x0001) __sfr INDF1
;
213 extern __at(0x0002) __sfr PCL
;
215 //==============================================================================
218 extern __at(0x0003) __sfr STATUS
;
232 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
240 //==============================================================================
242 extern __at(0x0004) __sfr FSR0
;
243 extern __at(0x0004) __sfr FSR0L
;
244 extern __at(0x0005) __sfr FSR0H
;
245 extern __at(0x0006) __sfr FSR1
;
246 extern __at(0x0006) __sfr FSR1L
;
247 extern __at(0x0007) __sfr FSR1H
;
249 //==============================================================================
252 extern __at(0x0008) __sfr BSR
;
275 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
283 //==============================================================================
285 extern __at(0x0009) __sfr WREG
;
286 extern __at(0x000A) __sfr PCLATH
;
288 //==============================================================================
291 extern __at(0x000B) __sfr INTCON
;
320 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
333 //==============================================================================
336 //==============================================================================
339 extern __at(0x000C) __sfr PORTA
;
353 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
364 //==============================================================================
367 //==============================================================================
370 extern __at(0x000D) __sfr PORTB
;
384 extern __at(0x000D) volatile __PORTBbits_t PORTBbits
;
395 //==============================================================================
398 //==============================================================================
401 extern __at(0x000E) __sfr PORTC
;
415 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
426 //==============================================================================
429 //==============================================================================
432 extern __at(0x0010) __sfr PORTE
;
446 extern __at(0x0010) volatile __PORTEbits_t PORTEbits
;
450 //==============================================================================
453 //==============================================================================
456 extern __at(0x0011) __sfr PIR1
;
467 unsigned TMR1GIF
: 1;
470 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
479 #define _TMR1GIF 0x80
481 //==============================================================================
484 //==============================================================================
487 extern __at(0x0012) __sfr PIR2
;
501 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
511 //==============================================================================
514 //==============================================================================
517 extern __at(0x0013) __sfr PIR3
;
531 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
539 //==============================================================================
541 extern __at(0x0015) __sfr TMR0
;
542 extern __at(0x0016) __sfr TMR1
;
543 extern __at(0x0016) __sfr TMR1L
;
544 extern __at(0x0017) __sfr TMR1H
;
546 //==============================================================================
549 extern __at(0x0018) __sfr T1CON
;
557 unsigned NOT_T1SYNC
: 1;
558 unsigned T1OSCEN
: 1;
559 unsigned T1CKPS0
: 1;
560 unsigned T1CKPS1
: 1;
561 unsigned TMR1CS0
: 1;
562 unsigned TMR1CS1
: 1;
579 extern __at(0x0018) volatile __T1CONbits_t T1CONbits
;
582 #define _NOT_T1SYNC 0x04
583 #define _T1OSCEN 0x08
584 #define _T1CKPS0 0x10
585 #define _T1CKPS1 0x20
586 #define _TMR1CS0 0x40
587 #define _TMR1CS1 0x80
589 //==============================================================================
592 //==============================================================================
595 extern __at(0x0019) __sfr T1GCON
;
604 unsigned T1GGO_NOT_DONE
: 1;
630 extern __at(0x0019) volatile __T1GCONbits_t T1GCONbits
;
635 #define _T1GGO_NOT_DONE 0x08
642 //==============================================================================
644 extern __at(0x001A) __sfr TMR2
;
645 extern __at(0x001B) __sfr PR2
;
647 //==============================================================================
650 extern __at(0x001C) __sfr T2CON
;
656 unsigned T2CKPS0
: 1;
657 unsigned T2CKPS1
: 1;
659 unsigned T2OUTPS0
: 1;
660 unsigned T2OUTPS1
: 1;
661 unsigned T2OUTPS2
: 1;
662 unsigned T2OUTPS3
: 1;
675 unsigned T2OUTPS
: 4;
680 extern __at(0x001C) volatile __T2CONbits_t T2CONbits
;
682 #define _T2CKPS0 0x01
683 #define _T2CKPS1 0x02
685 #define _T2OUTPS0 0x08
686 #define _T2OUTPS1 0x10
687 #define _T2OUTPS2 0x20
688 #define _T2OUTPS3 0x40
690 //==============================================================================
693 //==============================================================================
696 extern __at(0x001E) __sfr CPSCON0
;
704 unsigned CPSRNG0
: 1;
705 unsigned CPSRNG1
: 1;
720 extern __at(0x001E) volatile __CPSCON0bits_t CPSCON0bits
;
724 #define _CPSRNG0 0x04
725 #define _CPSRNG1 0x08
729 //==============================================================================
732 //==============================================================================
735 extern __at(0x001F) __sfr CPSCON1
;
758 extern __at(0x001F) volatile __CPSCON1bits_t CPSCON1bits
;
764 //==============================================================================
767 //==============================================================================
770 extern __at(0x008C) __sfr TRISA
;
784 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
795 //==============================================================================
798 //==============================================================================
801 extern __at(0x008D) __sfr TRISB
;
815 extern __at(0x008D) volatile __TRISBbits_t TRISBbits
;
826 //==============================================================================
829 //==============================================================================
832 extern __at(0x008E) __sfr TRISC
;
846 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
857 //==============================================================================
860 //==============================================================================
863 extern __at(0x0090) __sfr TRISE
;
877 extern __at(0x0090) volatile __TRISEbits_t TRISEbits
;
881 //==============================================================================
884 //==============================================================================
887 extern __at(0x0091) __sfr PIE1
;
898 unsigned TMR1GIE
: 1;
901 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
910 #define _TMR1GIE 0x80
912 //==============================================================================
915 //==============================================================================
918 extern __at(0x0092) __sfr PIE2
;
932 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
942 //==============================================================================
945 //==============================================================================
948 extern __at(0x0093) __sfr PIE3
;
962 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
970 //==============================================================================
973 //==============================================================================
976 extern __at(0x0095) __sfr OPTION_REG
;
989 unsigned NOT_WPUEN
: 1;
1009 } __OPTION_REGbits_t
;
1011 extern __at(0x0095) volatile __OPTION_REGbits_t OPTION_REGbits
;
1017 #define _TMR0SE 0x10
1019 #define _TMR0CS 0x20
1021 #define _INTEDG 0x40
1022 #define _NOT_WPUEN 0x80
1024 //==============================================================================
1027 //==============================================================================
1030 extern __at(0x0096) __sfr PCON
;
1034 unsigned NOT_BOR
: 1;
1035 unsigned NOT_POR
: 1;
1036 unsigned NOT_RI
: 1;
1037 unsigned NOT_RMCLR
: 1;
1040 unsigned STKUNF
: 1;
1041 unsigned STKOVF
: 1;
1044 extern __at(0x0096) volatile __PCONbits_t PCONbits
;
1046 #define _NOT_BOR 0x01
1047 #define _NOT_POR 0x02
1048 #define _NOT_RI 0x04
1049 #define _NOT_RMCLR 0x08
1050 #define _STKUNF 0x40
1051 #define _STKOVF 0x80
1053 //==============================================================================
1056 //==============================================================================
1059 extern __at(0x0097) __sfr WDTCON
;
1065 unsigned SWDTEN
: 1;
1066 unsigned WDTPS0
: 1;
1067 unsigned WDTPS1
: 1;
1068 unsigned WDTPS2
: 1;
1069 unsigned WDTPS3
: 1;
1070 unsigned WDTPS4
: 1;
1083 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1085 #define _SWDTEN 0x01
1086 #define _WDTPS0 0x02
1087 #define _WDTPS1 0x04
1088 #define _WDTPS2 0x08
1089 #define _WDTPS3 0x10
1090 #define _WDTPS4 0x20
1092 //==============================================================================
1095 //==============================================================================
1098 extern __at(0x0098) __sfr OSCTUNE
;
1121 extern __at(0x0098) volatile __OSCTUNEbits_t OSCTUNEbits
;
1130 //==============================================================================
1133 //==============================================================================
1136 extern __at(0x0099) __sfr OSCCON
;
1149 unsigned SPLLEN
: 1;
1166 extern __at(0x0099) volatile __OSCCONbits_t OSCCONbits
;
1174 #define _SPLLEN 0x80
1176 //==============================================================================
1179 //==============================================================================
1182 extern __at(0x009A) __sfr OSCSTAT
;
1186 unsigned HFIOFS
: 1;
1187 unsigned LFIOFR
: 1;
1188 unsigned MFIOFR
: 1;
1189 unsigned HFIOFL
: 1;
1190 unsigned HFIOFR
: 1;
1193 unsigned T1OSCR
: 1;
1196 extern __at(0x009A) volatile __OSCSTATbits_t OSCSTATbits
;
1198 #define _HFIOFS 0x01
1199 #define _LFIOFR 0x02
1200 #define _MFIOFR 0x04
1201 #define _HFIOFL 0x08
1202 #define _HFIOFR 0x10
1205 #define _T1OSCR 0x80
1207 //==============================================================================
1209 extern __at(0x009B) __sfr ADRES
;
1210 extern __at(0x009B) __sfr ADRESL
;
1211 extern __at(0x009C) __sfr ADRESH
;
1213 //==============================================================================
1216 extern __at(0x009D) __sfr ADCON0
;
1223 unsigned GO_NOT_DONE
: 1;
1259 unsigned NOT_DONE
: 1;
1276 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1279 #define _GO_NOT_DONE 0x02
1282 #define _NOT_DONE 0x02
1289 //==============================================================================
1292 //==============================================================================
1295 extern __at(0x009E) __sfr ADCON1
;
1301 unsigned ADPREF0
: 1;
1302 unsigned ADPREF1
: 1;
1303 unsigned ADNREF
: 1;
1313 unsigned ADPREF
: 2;
1325 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1327 #define _ADPREF0 0x01
1328 #define _ADPREF1 0x02
1329 #define _ADNREF 0x04
1335 //==============================================================================
1338 //==============================================================================
1341 extern __at(0x010C) __sfr LATA
;
1355 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1366 //==============================================================================
1369 //==============================================================================
1372 extern __at(0x010D) __sfr LATB
;
1386 extern __at(0x010D) volatile __LATBbits_t LATBbits
;
1397 //==============================================================================
1400 //==============================================================================
1403 extern __at(0x010E) __sfr LATC
;
1417 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1428 //==============================================================================
1431 //==============================================================================
1434 extern __at(0x0110) __sfr LATE
;
1448 extern __at(0x0110) volatile __LATEbits_t LATEbits
;
1452 //==============================================================================
1455 //==============================================================================
1458 extern __at(0x0111) __sfr CM1CON0
;
1462 unsigned C1SYNC
: 1;
1472 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1474 #define _C1SYNC 0x01
1482 //==============================================================================
1485 //==============================================================================
1488 extern __at(0x0112) __sfr CM1CON1
;
1494 unsigned C1NCH0
: 1;
1495 unsigned C1NCH1
: 1;
1498 unsigned C1PCH0
: 1;
1499 unsigned C1PCH1
: 1;
1500 unsigned C1INTN
: 1;
1501 unsigned C1INTP
: 1;
1518 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1520 #define _C1NCH0 0x01
1521 #define _C1NCH1 0x02
1522 #define _C1PCH0 0x10
1523 #define _C1PCH1 0x20
1524 #define _C1INTN 0x40
1525 #define _C1INTP 0x80
1527 //==============================================================================
1530 //==============================================================================
1533 extern __at(0x0113) __sfr CM2CON0
;
1537 unsigned C2SYNC
: 1;
1547 extern __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits
;
1549 #define _C2SYNC 0x01
1557 //==============================================================================
1560 //==============================================================================
1563 extern __at(0x0114) __sfr CM2CON1
;
1569 unsigned C2NCH0
: 1;
1570 unsigned C2NCH1
: 1;
1573 unsigned C2PCH0
: 1;
1574 unsigned C2PCH1
: 1;
1575 unsigned C2INTN
: 1;
1576 unsigned C2INTP
: 1;
1593 extern __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits
;
1595 #define _C2NCH0 0x01
1596 #define _C2NCH1 0x02
1597 #define _C2PCH0 0x10
1598 #define _C2PCH1 0x20
1599 #define _C2INTN 0x40
1600 #define _C2INTP 0x80
1602 //==============================================================================
1605 //==============================================================================
1608 extern __at(0x0115) __sfr CMOUT
;
1612 unsigned MC1OUT
: 1;
1613 unsigned MC2OUT
: 1;
1622 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1624 #define _MC1OUT 0x01
1625 #define _MC2OUT 0x02
1627 //==============================================================================
1630 //==============================================================================
1633 extern __at(0x0116) __sfr BORCON
;
1637 unsigned BORRDY
: 1;
1644 unsigned SBOREN
: 1;
1647 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1649 #define _BORRDY 0x01
1650 #define _SBOREN 0x80
1652 //==============================================================================
1655 //==============================================================================
1658 extern __at(0x0117) __sfr FVRCON
;
1664 unsigned ADFVR0
: 1;
1665 unsigned ADFVR1
: 1;
1666 unsigned CDAFVR0
: 1;
1667 unsigned CDAFVR1
: 1;
1670 unsigned FVRRDY
: 1;
1683 unsigned CDAFVR
: 2;
1688 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1690 #define _ADFVR0 0x01
1691 #define _ADFVR1 0x02
1692 #define _CDAFVR0 0x04
1693 #define _CDAFVR1 0x08
1696 #define _FVRRDY 0x40
1699 //==============================================================================
1702 //==============================================================================
1705 extern __at(0x0118) __sfr DACCON0
;
1711 unsigned DACNSS
: 1;
1713 unsigned DACPSS0
: 1;
1714 unsigned DACPSS1
: 1;
1717 unsigned DACLPS
: 1;
1724 unsigned DACPSS
: 2;
1729 extern __at(0x0118) volatile __DACCON0bits_t DACCON0bits
;
1731 #define _DACNSS 0x01
1732 #define _DACPSS0 0x04
1733 #define _DACPSS1 0x08
1735 #define _DACLPS 0x40
1738 //==============================================================================
1741 //==============================================================================
1744 extern __at(0x0119) __sfr DACCON1
;
1767 extern __at(0x0119) volatile __DACCON1bits_t DACCON1bits
;
1775 //==============================================================================
1778 //==============================================================================
1781 extern __at(0x011A) __sfr SRCON0
;
1789 unsigned SRNQEN
: 1;
1791 unsigned SRCLK0
: 1;
1792 unsigned SRCLK1
: 1;
1793 unsigned SRCLK2
: 1;
1805 extern __at(0x011A) volatile __SRCON0bits_t SRCON0bits
;
1809 #define _SRNQEN 0x04
1811 #define _SRCLK0 0x10
1812 #define _SRCLK1 0x20
1813 #define _SRCLK2 0x40
1816 //==============================================================================
1819 //==============================================================================
1822 extern __at(0x011B) __sfr SRCON1
;
1826 unsigned SRRC1E
: 1;
1827 unsigned SRRC2E
: 1;
1828 unsigned SRRCKE
: 1;
1830 unsigned SRSC1E
: 1;
1831 unsigned SRSC2E
: 1;
1832 unsigned SRSCKE
: 1;
1836 extern __at(0x011B) volatile __SRCON1bits_t SRCON1bits
;
1838 #define _SRRC1E 0x01
1839 #define _SRRC2E 0x02
1840 #define _SRRCKE 0x04
1842 #define _SRSC1E 0x10
1843 #define _SRSC2E 0x20
1844 #define _SRSCKE 0x40
1847 //==============================================================================
1850 //==============================================================================
1853 extern __at(0x011D) __sfr APFCON
;
1857 unsigned CCP2SEL
: 1;
1859 unsigned C2OUTSEL
: 1;
1860 unsigned SRNQSEL
: 1;
1861 unsigned P2BSEL
: 1;
1862 unsigned T1GSEL
: 1;
1863 unsigned CCP3SEL
: 1;
1867 extern __at(0x011D) volatile __APFCONbits_t APFCONbits
;
1869 #define _CCP2SEL 0x01
1871 #define _C2OUTSEL 0x04
1872 #define _SRNQSEL 0x08
1873 #define _P2BSEL 0x10
1874 #define _T1GSEL 0x20
1875 #define _CCP3SEL 0x40
1877 //==============================================================================
1880 //==============================================================================
1883 extern __at(0x018C) __sfr ANSELA
;
1906 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
1915 //==============================================================================
1918 //==============================================================================
1921 extern __at(0x018D) __sfr ANSELB
;
1944 extern __at(0x018D) volatile __ANSELBbits_t ANSELBbits
;
1953 //==============================================================================
1955 extern __at(0x0191) __sfr EEADR
;
1956 extern __at(0x0191) __sfr EEADRL
;
1957 extern __at(0x0192) __sfr EEADRH
;
1958 extern __at(0x0193) __sfr EEDAT
;
1959 extern __at(0x0193) __sfr EEDATL
;
1960 extern __at(0x0194) __sfr EEDATH
;
1962 //==============================================================================
1965 extern __at(0x0195) __sfr EECON1
;
1979 extern __at(0x0195) volatile __EECON1bits_t EECON1bits
;
1990 //==============================================================================
1992 extern __at(0x0196) __sfr EECON2
;
1993 extern __at(0x0199) __sfr RCREG
;
1994 extern __at(0x019A) __sfr TXREG
;
1995 extern __at(0x019B) __sfr SP1BRG
;
1996 extern __at(0x019B) __sfr SP1BRGL
;
1997 extern __at(0x019B) __sfr SPBRG
;
1998 extern __at(0x019B) __sfr SPBRGL
;
1999 extern __at(0x019C) __sfr SP1BRGH
;
2000 extern __at(0x019C) __sfr SPBRGH
;
2002 //==============================================================================
2005 extern __at(0x019D) __sfr RCSTA
;
2019 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
2030 //==============================================================================
2033 //==============================================================================
2036 extern __at(0x019E) __sfr TXSTA
;
2050 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
2061 //==============================================================================
2064 //==============================================================================
2067 extern __at(0x019F) __sfr BAUDCON
;
2078 unsigned ABDOVF
: 1;
2081 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
2088 #define _ABDOVF 0x80
2090 //==============================================================================
2093 //==============================================================================
2096 extern __at(0x020D) __sfr WPUB
;
2110 extern __at(0x020D) volatile __WPUBbits_t WPUBbits
;
2121 //==============================================================================
2124 //==============================================================================
2127 extern __at(0x0210) __sfr WPUE
;
2141 extern __at(0x0210) volatile __WPUEbits_t WPUEbits
;
2145 //==============================================================================
2147 extern __at(0x0211) __sfr SSPBUF
;
2148 extern __at(0x0212) __sfr SSPADD
;
2149 extern __at(0x0213) __sfr SSPMSK
;
2151 //==============================================================================
2154 extern __at(0x0214) __sfr SSPSTAT
;
2160 unsigned R_NOT_W
: 1;
2163 unsigned D_NOT_A
: 1;
2168 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
2172 #define _R_NOT_W 0x04
2175 #define _D_NOT_A 0x20
2179 //==============================================================================
2182 //==============================================================================
2185 extern __at(0x0215) __sfr SSPCON
;
2208 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2219 //==============================================================================
2222 //==============================================================================
2225 extern __at(0x0215) __sfr SSPCON1
;
2248 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2250 #define _SSPCON1_SSPM0 0x01
2251 #define _SSPCON1_SSPM1 0x02
2252 #define _SSPCON1_SSPM2 0x04
2253 #define _SSPCON1_SSPM3 0x08
2254 #define _SSPCON1_CKP 0x10
2255 #define _SSPCON1_SSPEN 0x20
2256 #define _SSPCON1_SSPOV 0x40
2257 #define _SSPCON1_WCOL 0x80
2259 //==============================================================================
2262 //==============================================================================
2265 extern __at(0x0216) __sfr SSPCON2
;
2275 unsigned ACKSTAT
: 1;
2279 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
2287 #define _ACKSTAT 0x40
2290 //==============================================================================
2293 //==============================================================================
2296 extern __at(0x0217) __sfr SSPCON3
;
2307 unsigned ACKTIM
: 1;
2310 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
2319 #define _ACKTIM 0x80
2321 //==============================================================================
2323 extern __at(0x0291) __sfr CCPR1
;
2324 extern __at(0x0291) __sfr CCPR1L
;
2325 extern __at(0x0292) __sfr CCPR1H
;
2327 //==============================================================================
2330 extern __at(0x0293) __sfr CCP1CON
;
2336 unsigned CCP1M0
: 1;
2337 unsigned CCP1M1
: 1;
2338 unsigned CCP1M2
: 1;
2339 unsigned CCP1M3
: 1;
2366 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
2368 #define _CCP1M0 0x01
2369 #define _CCP1M1 0x02
2370 #define _CCP1M2 0x04
2371 #define _CCP1M3 0x08
2377 //==============================================================================
2380 //==============================================================================
2383 extern __at(0x0294) __sfr PWM1CON
;
2396 unsigned P1RSEN
: 1;
2406 extern __at(0x0294) volatile __PWM1CONbits_t PWM1CONbits
;
2415 #define _P1RSEN 0x80
2417 //==============================================================================
2420 //==============================================================================
2423 extern __at(0x0295) __sfr CCP1AS
;
2429 unsigned PSS1BD0
: 1;
2430 unsigned PSS1BD1
: 1;
2431 unsigned PSS1AC0
: 1;
2432 unsigned PSS1AC1
: 1;
2433 unsigned CCP1AS0
: 1;
2434 unsigned CCP1AS1
: 1;
2435 unsigned CCP1AS2
: 1;
2436 unsigned CCP1ASE
: 1;
2441 unsigned PSS1BD
: 2;
2448 unsigned PSS1AC
: 2;
2455 unsigned CCP1AS
: 3;
2460 extern __at(0x0295) volatile __CCP1ASbits_t CCP1ASbits
;
2462 #define _PSS1BD0 0x01
2463 #define _PSS1BD1 0x02
2464 #define _PSS1AC0 0x04
2465 #define _PSS1AC1 0x08
2466 #define _CCP1AS0 0x10
2467 #define _CCP1AS1 0x20
2468 #define _CCP1AS2 0x40
2469 #define _CCP1ASE 0x80
2471 //==============================================================================
2474 //==============================================================================
2477 extern __at(0x0295) __sfr ECCP1AS
;
2483 unsigned PSS1BD0
: 1;
2484 unsigned PSS1BD1
: 1;
2485 unsigned PSS1AC0
: 1;
2486 unsigned PSS1AC1
: 1;
2487 unsigned CCP1AS0
: 1;
2488 unsigned CCP1AS1
: 1;
2489 unsigned CCP1AS2
: 1;
2490 unsigned CCP1ASE
: 1;
2495 unsigned PSS1BD
: 2;
2502 unsigned PSS1AC
: 2;
2509 unsigned CCP1AS
: 3;
2514 extern __at(0x0295) volatile __ECCP1ASbits_t ECCP1ASbits
;
2516 #define _ECCP1AS_PSS1BD0 0x01
2517 #define _ECCP1AS_PSS1BD1 0x02
2518 #define _ECCP1AS_PSS1AC0 0x04
2519 #define _ECCP1AS_PSS1AC1 0x08
2520 #define _ECCP1AS_CCP1AS0 0x10
2521 #define _ECCP1AS_CCP1AS1 0x20
2522 #define _ECCP1AS_CCP1AS2 0x40
2523 #define _ECCP1AS_CCP1ASE 0x80
2525 //==============================================================================
2528 //==============================================================================
2531 extern __at(0x0296) __sfr PSTR1CON
;
2539 unsigned STR1SYNC
: 1;
2545 extern __at(0x0296) volatile __PSTR1CONbits_t PSTR1CONbits
;
2551 #define _STR1SYNC 0x10
2553 //==============================================================================
2555 extern __at(0x0298) __sfr CCPR2
;
2556 extern __at(0x0298) __sfr CCPR2L
;
2557 extern __at(0x0299) __sfr CCPR2H
;
2559 //==============================================================================
2562 extern __at(0x029A) __sfr CCP2CON
;
2568 unsigned CCP2M0
: 1;
2569 unsigned CCP2M1
: 1;
2570 unsigned CCP2M2
: 1;
2571 unsigned CCP2M3
: 1;
2598 extern __at(0x029A) volatile __CCP2CONbits_t CCP2CONbits
;
2600 #define _CCP2M0 0x01
2601 #define _CCP2M1 0x02
2602 #define _CCP2M2 0x04
2603 #define _CCP2M3 0x08
2609 //==============================================================================
2612 //==============================================================================
2615 extern __at(0x029B) __sfr PWM2CON
;
2628 unsigned P2RSEN
: 1;
2638 extern __at(0x029B) volatile __PWM2CONbits_t PWM2CONbits
;
2647 #define _P2RSEN 0x80
2649 //==============================================================================
2652 //==============================================================================
2655 extern __at(0x029C) __sfr CCP2AS
;
2661 unsigned PSS2BD0
: 1;
2662 unsigned PSS2BD1
: 1;
2663 unsigned PSS2AC0
: 1;
2664 unsigned PSS2AC1
: 1;
2665 unsigned CCP2AS0
: 1;
2666 unsigned CCP2AS1
: 1;
2667 unsigned CCP2AS2
: 1;
2668 unsigned CCP2ASE
: 1;
2673 unsigned PSS2BD
: 2;
2680 unsigned PSS2AC
: 2;
2687 unsigned CCP2AS
: 3;
2692 extern __at(0x029C) volatile __CCP2ASbits_t CCP2ASbits
;
2694 #define _PSS2BD0 0x01
2695 #define _PSS2BD1 0x02
2696 #define _PSS2AC0 0x04
2697 #define _PSS2AC1 0x08
2698 #define _CCP2AS0 0x10
2699 #define _CCP2AS1 0x20
2700 #define _CCP2AS2 0x40
2701 #define _CCP2ASE 0x80
2703 //==============================================================================
2706 //==============================================================================
2709 extern __at(0x029C) __sfr ECCP2AS
;
2715 unsigned PSS2BD0
: 1;
2716 unsigned PSS2BD1
: 1;
2717 unsigned PSS2AC0
: 1;
2718 unsigned PSS2AC1
: 1;
2719 unsigned CCP2AS0
: 1;
2720 unsigned CCP2AS1
: 1;
2721 unsigned CCP2AS2
: 1;
2722 unsigned CCP2ASE
: 1;
2727 unsigned PSS2BD
: 2;
2734 unsigned PSS2AC
: 2;
2741 unsigned CCP2AS
: 3;
2746 extern __at(0x029C) volatile __ECCP2ASbits_t ECCP2ASbits
;
2748 #define _ECCP2AS_PSS2BD0 0x01
2749 #define _ECCP2AS_PSS2BD1 0x02
2750 #define _ECCP2AS_PSS2AC0 0x04
2751 #define _ECCP2AS_PSS2AC1 0x08
2752 #define _ECCP2AS_CCP2AS0 0x10
2753 #define _ECCP2AS_CCP2AS1 0x20
2754 #define _ECCP2AS_CCP2AS2 0x40
2755 #define _ECCP2AS_CCP2ASE 0x80
2757 //==============================================================================
2760 //==============================================================================
2763 extern __at(0x029D) __sfr PSTR2CON
;
2771 unsigned STR2SYNC
: 1;
2777 extern __at(0x029D) volatile __PSTR2CONbits_t PSTR2CONbits
;
2783 #define _STR2SYNC 0x10
2785 //==============================================================================
2788 //==============================================================================
2791 extern __at(0x029E) __sfr CCPTMRS0
;
2797 unsigned C1TSEL0
: 1;
2798 unsigned C1TSEL1
: 1;
2799 unsigned C2TSEL0
: 1;
2800 unsigned C2TSEL1
: 1;
2801 unsigned C3TSEL0
: 1;
2802 unsigned C3TSEL1
: 1;
2803 unsigned C4TSEL0
: 1;
2804 unsigned C4TSEL1
: 1;
2809 unsigned C1TSEL
: 2;
2816 unsigned C2TSEL
: 2;
2823 unsigned C3TSEL
: 2;
2830 unsigned C4TSEL
: 2;
2834 extern __at(0x029E) volatile __CCPTMRS0bits_t CCPTMRS0bits
;
2836 #define _C1TSEL0 0x01
2837 #define _C1TSEL1 0x02
2838 #define _C2TSEL0 0x04
2839 #define _C2TSEL1 0x08
2840 #define _C3TSEL0 0x10
2841 #define _C3TSEL1 0x20
2842 #define _C4TSEL0 0x40
2843 #define _C4TSEL1 0x80
2845 //==============================================================================
2848 //==============================================================================
2851 extern __at(0x029F) __sfr CCPTMRS1
;
2857 unsigned C5TSEL0
: 1;
2858 unsigned C5TSEL1
: 1;
2869 unsigned C5TSEL
: 2;
2874 extern __at(0x029F) volatile __CCPTMRS1bits_t CCPTMRS1bits
;
2876 #define _C5TSEL0 0x01
2877 #define _C5TSEL1 0x02
2879 //==============================================================================
2881 extern __at(0x0311) __sfr CCPR3
;
2882 extern __at(0x0311) __sfr CCPR3L
;
2883 extern __at(0x0312) __sfr CCPR3H
;
2885 //==============================================================================
2888 extern __at(0x0313) __sfr CCP3CON
;
2894 unsigned CCP3M0
: 1;
2895 unsigned CCP3M1
: 1;
2896 unsigned CCP3M2
: 1;
2897 unsigned CCP3M3
: 1;
2924 extern __at(0x0313) volatile __CCP3CONbits_t CCP3CONbits
;
2926 #define _CCP3M0 0x01
2927 #define _CCP3M1 0x02
2928 #define _CCP3M2 0x04
2929 #define _CCP3M3 0x08
2935 //==============================================================================
2938 //==============================================================================
2941 extern __at(0x0314) __sfr PWM3CON
;
2954 unsigned P3RSEN
: 1;
2964 extern __at(0x0314) volatile __PWM3CONbits_t PWM3CONbits
;
2973 #define _P3RSEN 0x80
2975 //==============================================================================
2978 //==============================================================================
2981 extern __at(0x0315) __sfr CCP3AS
;
2987 unsigned PSS3BD0
: 1;
2988 unsigned PSS3BD1
: 1;
2989 unsigned PSS3AC0
: 1;
2990 unsigned PSS3AC1
: 1;
2991 unsigned CCP3AS0
: 1;
2992 unsigned CCP3AS1
: 1;
2993 unsigned CCP3AS2
: 1;
2994 unsigned CCP3ASE
: 1;
2999 unsigned PSS3BD
: 2;
3006 unsigned PSS3AC
: 2;
3013 unsigned CCP3AS
: 3;
3018 extern __at(0x0315) volatile __CCP3ASbits_t CCP3ASbits
;
3020 #define _PSS3BD0 0x01
3021 #define _PSS3BD1 0x02
3022 #define _PSS3AC0 0x04
3023 #define _PSS3AC1 0x08
3024 #define _CCP3AS0 0x10
3025 #define _CCP3AS1 0x20
3026 #define _CCP3AS2 0x40
3027 #define _CCP3ASE 0x80
3029 //==============================================================================
3032 //==============================================================================
3035 extern __at(0x0315) __sfr ECCP3AS
;
3041 unsigned PSS3BD0
: 1;
3042 unsigned PSS3BD1
: 1;
3043 unsigned PSS3AC0
: 1;
3044 unsigned PSS3AC1
: 1;
3045 unsigned CCP3AS0
: 1;
3046 unsigned CCP3AS1
: 1;
3047 unsigned CCP3AS2
: 1;
3048 unsigned CCP3ASE
: 1;
3053 unsigned PSS3BD
: 2;
3060 unsigned PSS3AC
: 2;
3067 unsigned CCP3AS
: 3;
3072 extern __at(0x0315) volatile __ECCP3ASbits_t ECCP3ASbits
;
3074 #define _ECCP3AS_PSS3BD0 0x01
3075 #define _ECCP3AS_PSS3BD1 0x02
3076 #define _ECCP3AS_PSS3AC0 0x04
3077 #define _ECCP3AS_PSS3AC1 0x08
3078 #define _ECCP3AS_CCP3AS0 0x10
3079 #define _ECCP3AS_CCP3AS1 0x20
3080 #define _ECCP3AS_CCP3AS2 0x40
3081 #define _ECCP3AS_CCP3ASE 0x80
3083 //==============================================================================
3086 //==============================================================================
3089 extern __at(0x0316) __sfr PSTR3CON
;
3097 unsigned STR3SYNC
: 1;
3103 extern __at(0x0316) volatile __PSTR3CONbits_t PSTR3CONbits
;
3109 #define _STR3SYNC 0x10
3111 //==============================================================================
3113 extern __at(0x0318) __sfr CCPR4
;
3114 extern __at(0x0318) __sfr CCPR4L
;
3115 extern __at(0x0319) __sfr CCPR4H
;
3117 //==============================================================================
3120 extern __at(0x031A) __sfr CCP4CON
;
3126 unsigned CCP4M0
: 1;
3127 unsigned CCP4M1
: 1;
3128 unsigned CCP4M2
: 1;
3129 unsigned CCP4M3
: 1;
3150 extern __at(0x031A) volatile __CCP4CONbits_t CCP4CONbits
;
3152 #define _CCP4M0 0x01
3153 #define _CCP4M1 0x02
3154 #define _CCP4M2 0x04
3155 #define _CCP4M3 0x08
3159 //==============================================================================
3161 extern __at(0x031C) __sfr CCPR5
;
3162 extern __at(0x031C) __sfr CCPR5L
;
3163 extern __at(0x031D) __sfr CCPR5H
;
3165 //==============================================================================
3168 extern __at(0x031E) __sfr CCP5CON
;
3174 unsigned CCP5M0
: 1;
3175 unsigned CCP5M1
: 1;
3176 unsigned CCP5M2
: 1;
3177 unsigned CCP5M3
: 1;
3198 extern __at(0x031E) volatile __CCP5CONbits_t CCP5CONbits
;
3200 #define _CCP5M0 0x01
3201 #define _CCP5M1 0x02
3202 #define _CCP5M2 0x04
3203 #define _CCP5M3 0x08
3207 //==============================================================================
3210 //==============================================================================
3213 extern __at(0x0394) __sfr IOCBP
;
3217 unsigned IOCBP0
: 1;
3218 unsigned IOCBP1
: 1;
3219 unsigned IOCBP2
: 1;
3220 unsigned IOCBP3
: 1;
3221 unsigned IOCBP4
: 1;
3222 unsigned IOCBP5
: 1;
3223 unsigned IOCBP6
: 1;
3224 unsigned IOCBP7
: 1;
3227 extern __at(0x0394) volatile __IOCBPbits_t IOCBPbits
;
3229 #define _IOCBP0 0x01
3230 #define _IOCBP1 0x02
3231 #define _IOCBP2 0x04
3232 #define _IOCBP3 0x08
3233 #define _IOCBP4 0x10
3234 #define _IOCBP5 0x20
3235 #define _IOCBP6 0x40
3236 #define _IOCBP7 0x80
3238 //==============================================================================
3241 //==============================================================================
3244 extern __at(0x0395) __sfr IOCBN
;
3248 unsigned IOCBN0
: 1;
3249 unsigned IOCBN1
: 1;
3250 unsigned IOCBN2
: 1;
3251 unsigned IOCBN3
: 1;
3252 unsigned IOCBN4
: 1;
3253 unsigned IOCBN5
: 1;
3254 unsigned IOCBN6
: 1;
3255 unsigned IOCBN7
: 1;
3258 extern __at(0x0395) volatile __IOCBNbits_t IOCBNbits
;
3260 #define _IOCBN0 0x01
3261 #define _IOCBN1 0x02
3262 #define _IOCBN2 0x04
3263 #define _IOCBN3 0x08
3264 #define _IOCBN4 0x10
3265 #define _IOCBN5 0x20
3266 #define _IOCBN6 0x40
3267 #define _IOCBN7 0x80
3269 //==============================================================================
3272 //==============================================================================
3275 extern __at(0x0396) __sfr IOCBF
;
3279 unsigned IOCBF0
: 1;
3280 unsigned IOCBF1
: 1;
3281 unsigned IOCBF2
: 1;
3282 unsigned IOCBF3
: 1;
3283 unsigned IOCBF4
: 1;
3284 unsigned IOCBF5
: 1;
3285 unsigned IOCBF6
: 1;
3286 unsigned IOCBF7
: 1;
3289 extern __at(0x0396) volatile __IOCBFbits_t IOCBFbits
;
3291 #define _IOCBF0 0x01
3292 #define _IOCBF1 0x02
3293 #define _IOCBF2 0x04
3294 #define _IOCBF3 0x08
3295 #define _IOCBF4 0x10
3296 #define _IOCBF5 0x20
3297 #define _IOCBF6 0x40
3298 #define _IOCBF7 0x80
3300 //==============================================================================
3302 extern __at(0x0415) __sfr TMR4
;
3303 extern __at(0x0416) __sfr PR4
;
3305 //==============================================================================
3308 extern __at(0x0417) __sfr T4CON
;
3314 unsigned T4CKPS0
: 1;
3315 unsigned T4CKPS1
: 1;
3316 unsigned TMR4ON
: 1;
3317 unsigned T4OUTPS0
: 1;
3318 unsigned T4OUTPS1
: 1;
3319 unsigned T4OUTPS2
: 1;
3320 unsigned T4OUTPS3
: 1;
3326 unsigned T4CKPS
: 2;
3333 unsigned T4OUTPS
: 4;
3338 extern __at(0x0417) volatile __T4CONbits_t T4CONbits
;
3340 #define _T4CKPS0 0x01
3341 #define _T4CKPS1 0x02
3342 #define _TMR4ON 0x04
3343 #define _T4OUTPS0 0x08
3344 #define _T4OUTPS1 0x10
3345 #define _T4OUTPS2 0x20
3346 #define _T4OUTPS3 0x40
3348 //==============================================================================
3350 extern __at(0x041C) __sfr TMR6
;
3351 extern __at(0x041D) __sfr PR6
;
3353 //==============================================================================
3356 extern __at(0x041E) __sfr T6CON
;
3362 unsigned T6CKPS0
: 1;
3363 unsigned T6CKPS1
: 1;
3364 unsigned TMR6ON
: 1;
3365 unsigned T6OUTPS0
: 1;
3366 unsigned T6OUTPS1
: 1;
3367 unsigned T6OUTPS2
: 1;
3368 unsigned T6OUTPS3
: 1;
3374 unsigned T6CKPS
: 2;
3381 unsigned T6OUTPS
: 4;
3386 extern __at(0x041E) volatile __T6CONbits_t T6CONbits
;
3388 #define _T6CKPS0 0x01
3389 #define _T6CKPS1 0x02
3390 #define _TMR6ON 0x04
3391 #define _T6OUTPS0 0x08
3392 #define _T6OUTPS1 0x10
3393 #define _T6OUTPS2 0x20
3394 #define _T6OUTPS3 0x40
3396 //==============================================================================
3399 //==============================================================================
3402 extern __at(0x0791) __sfr LCDCON
;
3432 extern __at(0x0791) volatile __LCDCONbits_t LCDCONbits
;
3442 //==============================================================================
3445 //==============================================================================
3448 extern __at(0x0792) __sfr LCDPS
;
3460 unsigned BIASMD
: 1;
3471 extern __at(0x0792) volatile __LCDPSbits_t LCDPSbits
;
3479 #define _BIASMD 0x40
3482 //==============================================================================
3485 //==============================================================================
3488 extern __at(0x0793) __sfr LCDREF
;
3493 unsigned VLCD1PE
: 1;
3494 unsigned VLCD2PE
: 1;
3495 unsigned VLCD3PE
: 1;
3497 unsigned LCDIRI
: 1;
3498 unsigned LCDIRS
: 1;
3499 unsigned LCDIRE
: 1;
3502 extern __at(0x0793) volatile __LCDREFbits_t LCDREFbits
;
3504 #define _VLCD1PE 0x02
3505 #define _VLCD2PE 0x04
3506 #define _VLCD3PE 0x08
3507 #define _LCDIRI 0x20
3508 #define _LCDIRS 0x40
3509 #define _LCDIRE 0x80
3511 //==============================================================================
3514 //==============================================================================
3517 extern __at(0x0794) __sfr LCDCST
;
3523 unsigned LCDCST0
: 1;
3524 unsigned LCDCST1
: 1;
3525 unsigned LCDCST2
: 1;
3535 unsigned LCDCST
: 3;
3540 extern __at(0x0794) volatile __LCDCSTbits_t LCDCSTbits
;
3542 #define _LCDCST0 0x01
3543 #define _LCDCST1 0x02
3544 #define _LCDCST2 0x04
3546 //==============================================================================
3549 //==============================================================================
3552 extern __at(0x0795) __sfr LCDRL
;
3558 unsigned LRLAT0
: 1;
3559 unsigned LRLAT1
: 1;
3560 unsigned LRLAT2
: 1;
3562 unsigned LRLBP0
: 1;
3563 unsigned LRLBP1
: 1;
3564 unsigned LRLAP0
: 1;
3565 unsigned LRLAP1
: 1;
3588 extern __at(0x0795) volatile __LCDRLbits_t LCDRLbits
;
3590 #define _LRLAT0 0x01
3591 #define _LRLAT1 0x02
3592 #define _LRLAT2 0x04
3593 #define _LRLBP0 0x10
3594 #define _LRLBP1 0x20
3595 #define _LRLAP0 0x40
3596 #define _LRLAP1 0x80
3598 //==============================================================================
3601 //==============================================================================
3604 extern __at(0x0798) __sfr LCDSE0
;
3618 extern __at(0x0798) volatile __LCDSE0bits_t LCDSE0bits
;
3629 //==============================================================================
3632 //==============================================================================
3635 extern __at(0x0799) __sfr LCDSE1
;
3649 extern __at(0x0799) volatile __LCDSE1bits_t LCDSE1bits
;
3660 //==============================================================================
3663 //==============================================================================
3666 extern __at(0x07A0) __sfr LCDDATA0
;
3670 unsigned SEG0COM0
: 1;
3671 unsigned SEG1COM0
: 1;
3672 unsigned SEG2COM0
: 1;
3673 unsigned SEG3COM0
: 1;
3674 unsigned SEG4COM0
: 1;
3675 unsigned SEG5COM0
: 1;
3676 unsigned SEG6COM0
: 1;
3677 unsigned SEG7COM0
: 1;
3680 extern __at(0x07A0) volatile __LCDDATA0bits_t LCDDATA0bits
;
3682 #define _SEG0COM0 0x01
3683 #define _SEG1COM0 0x02
3684 #define _SEG2COM0 0x04
3685 #define _SEG3COM0 0x08
3686 #define _SEG4COM0 0x10
3687 #define _SEG5COM0 0x20
3688 #define _SEG6COM0 0x40
3689 #define _SEG7COM0 0x80
3691 //==============================================================================
3694 //==============================================================================
3697 extern __at(0x07A1) __sfr LCDDATA1
;
3701 unsigned SEG8COM0
: 1;
3702 unsigned SEG9COM0
: 1;
3703 unsigned SEG10COM0
: 1;
3704 unsigned SEG11COM0
: 1;
3705 unsigned SEG12COM0
: 1;
3706 unsigned SEG13COM0
: 1;
3707 unsigned SEG14COM0
: 1;
3708 unsigned SEG15COM0
: 1;
3711 extern __at(0x07A1) volatile __LCDDATA1bits_t LCDDATA1bits
;
3713 #define _SEG8COM0 0x01
3714 #define _SEG9COM0 0x02
3715 #define _SEG10COM0 0x04
3716 #define _SEG11COM0 0x08
3717 #define _SEG12COM0 0x10
3718 #define _SEG13COM0 0x20
3719 #define _SEG14COM0 0x40
3720 #define _SEG15COM0 0x80
3722 //==============================================================================
3725 //==============================================================================
3728 extern __at(0x07A3) __sfr LCDDATA3
;
3732 unsigned SEG0COM1
: 1;
3733 unsigned SEG1COM1
: 1;
3734 unsigned SEG2COM1
: 1;
3735 unsigned SEG3COM1
: 1;
3736 unsigned SEG4COM1
: 1;
3737 unsigned SEG5COM1
: 1;
3738 unsigned SEG6COM1
: 1;
3739 unsigned SEG7COM1
: 1;
3742 extern __at(0x07A3) volatile __LCDDATA3bits_t LCDDATA3bits
;
3744 #define _SEG0COM1 0x01
3745 #define _SEG1COM1 0x02
3746 #define _SEG2COM1 0x04
3747 #define _SEG3COM1 0x08
3748 #define _SEG4COM1 0x10
3749 #define _SEG5COM1 0x20
3750 #define _SEG6COM1 0x40
3751 #define _SEG7COM1 0x80
3753 //==============================================================================
3756 //==============================================================================
3759 extern __at(0x07A4) __sfr LCDDATA4
;
3763 unsigned SEG8COM1
: 1;
3764 unsigned SEG9COM1
: 1;
3765 unsigned SEG10COM1
: 1;
3766 unsigned SEG11COM1
: 1;
3767 unsigned SEG12COM1
: 1;
3768 unsigned SEG13COM1
: 1;
3769 unsigned SEG14COM1
: 1;
3770 unsigned SEG15COM1
: 1;
3773 extern __at(0x07A4) volatile __LCDDATA4bits_t LCDDATA4bits
;
3775 #define _SEG8COM1 0x01
3776 #define _SEG9COM1 0x02
3777 #define _SEG10COM1 0x04
3778 #define _SEG11COM1 0x08
3779 #define _SEG12COM1 0x10
3780 #define _SEG13COM1 0x20
3781 #define _SEG14COM1 0x40
3782 #define _SEG15COM1 0x80
3784 //==============================================================================
3787 //==============================================================================
3790 extern __at(0x07A6) __sfr LCDDATA6
;
3794 unsigned SEG0COM2
: 1;
3795 unsigned SEG1COM2
: 1;
3796 unsigned SEG2COM2
: 1;
3797 unsigned SEG3COM2
: 1;
3798 unsigned SEG4COM2
: 1;
3799 unsigned SEG5COM2
: 1;
3800 unsigned SEG6COM2
: 1;
3801 unsigned SEG7COM2
: 1;
3804 extern __at(0x07A6) volatile __LCDDATA6bits_t LCDDATA6bits
;
3806 #define _SEG0COM2 0x01
3807 #define _SEG1COM2 0x02
3808 #define _SEG2COM2 0x04
3809 #define _SEG3COM2 0x08
3810 #define _SEG4COM2 0x10
3811 #define _SEG5COM2 0x20
3812 #define _SEG6COM2 0x40
3813 #define _SEG7COM2 0x80
3815 //==============================================================================
3818 //==============================================================================
3821 extern __at(0x07A7) __sfr LCDDATA7
;
3825 unsigned SEG8COM2
: 1;
3826 unsigned SEG9COM2
: 1;
3827 unsigned SEG10COM2
: 1;
3828 unsigned SEG11COM2
: 1;
3829 unsigned SEG12COM2
: 1;
3830 unsigned SEG13COM2
: 1;
3831 unsigned SEG14COM2
: 1;
3832 unsigned SEG15COM2
: 1;
3835 extern __at(0x07A7) volatile __LCDDATA7bits_t LCDDATA7bits
;
3837 #define _SEG8COM2 0x01
3838 #define _SEG9COM2 0x02
3839 #define _SEG10COM2 0x04
3840 #define _SEG11COM2 0x08
3841 #define _SEG12COM2 0x10
3842 #define _SEG13COM2 0x20
3843 #define _SEG14COM2 0x40
3844 #define _SEG15COM2 0x80
3846 //==============================================================================
3849 //==============================================================================
3852 extern __at(0x07A9) __sfr LCDDATA9
;
3856 unsigned SEG0COM3
: 1;
3857 unsigned SEG1COM3
: 1;
3858 unsigned SEG2COM3
: 1;
3859 unsigned SEG3COM3
: 1;
3860 unsigned SEG4COM3
: 1;
3861 unsigned SEG5COM3
: 1;
3862 unsigned SEG6COM3
: 1;
3863 unsigned SEG7COM3
: 1;
3866 extern __at(0x07A9) volatile __LCDDATA9bits_t LCDDATA9bits
;
3868 #define _SEG0COM3 0x01
3869 #define _SEG1COM3 0x02
3870 #define _SEG2COM3 0x04
3871 #define _SEG3COM3 0x08
3872 #define _SEG4COM3 0x10
3873 #define _SEG5COM3 0x20
3874 #define _SEG6COM3 0x40
3875 #define _SEG7COM3 0x80
3877 //==============================================================================
3880 //==============================================================================
3883 extern __at(0x07AA) __sfr LCDDATA10
;
3887 unsigned SEG8COM3
: 1;
3888 unsigned SEG9COM3
: 1;
3889 unsigned SEG10COM3
: 1;
3890 unsigned SEG11COM3
: 1;
3891 unsigned SEG12COM3
: 1;
3892 unsigned SEG13COM3
: 1;
3893 unsigned SEG14COM3
: 1;
3894 unsigned SEG15COM3
: 1;
3895 } __LCDDATA10bits_t
;
3897 extern __at(0x07AA) volatile __LCDDATA10bits_t LCDDATA10bits
;
3899 #define _SEG8COM3 0x01
3900 #define _SEG9COM3 0x02
3901 #define _SEG10COM3 0x04
3902 #define _SEG11COM3 0x08
3903 #define _SEG12COM3 0x10
3904 #define _SEG13COM3 0x20
3905 #define _SEG14COM3 0x40
3906 #define _SEG15COM3 0x80
3908 //==============================================================================
3911 //==============================================================================
3914 extern __at(0x0FE4) __sfr STATUS_SHAD
;
3918 unsigned C_SHAD
: 1;
3919 unsigned DC_SHAD
: 1;
3920 unsigned Z_SHAD
: 1;
3926 } __STATUS_SHADbits_t
;
3928 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
3930 #define _C_SHAD 0x01
3931 #define _DC_SHAD 0x02
3932 #define _Z_SHAD 0x04
3934 //==============================================================================
3936 extern __at(0x0FE5) __sfr WREG_SHAD
;
3937 extern __at(0x0FE6) __sfr BSR_SHAD
;
3938 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
3939 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
3940 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
3941 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
3942 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
3943 extern __at(0x0FED) __sfr STKPTR
;
3944 extern __at(0x0FEE) __sfr TOSL
;
3945 extern __at(0x0FEF) __sfr TOSH
;
3947 //==============================================================================
3949 // Configuration Bits
3951 //==============================================================================
3953 #define _CONFIG1 0x8007
3954 #define _CONFIG2 0x8008
3956 //----------------------------- CONFIG1 Options -------------------------------
3958 #define _FOSC_LP 0x3FF8 // LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins.
3959 #define _FOSC_XT 0x3FF9 // XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins.
3960 #define _FOSC_HS 0x3FFA // HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins.
3961 #define _FOSC_EXTRC 0x3FFB // EXTRC oscillator: External RC circuit connected to CLKIN pin.
3962 #define _FOSC_INTOSC 0x3FFC // INTOSC oscillator: I/O function on CLKIN pin.
3963 #define _FOSC_ECL 0x3FFD // ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pin.
3964 #define _FOSC_ECM 0x3FFE // ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pin.
3965 #define _FOSC_ECH 0x3FFF // ECH, External Clock, High Power Mode (4-32 MHz): device clock supplied to CLKIN pin.
3966 #define _WDTE_OFF 0x3FE7 // WDT disabled.
3967 #define _WDTE_SWDTEN 0x3FEF // WDT controlled by the SWDTEN bit in the WDTCON register.
3968 #define _WDTE_NSLEEP 0x3FF7 // WDT enabled while running and disabled in Sleep.
3969 #define _WDTE_ON 0x3FFF // WDT enabled.
3970 #define _PWRTE_ON 0x3FDF // PWRT enabled.
3971 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
3972 #define _MCLRE_OFF 0x3FBF // MCLR/VPP pin function is digital input.
3973 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR.
3974 #define _CP_ON 0x3F7F // Program memory code protection is enabled.
3975 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
3976 #define _CPD_ON 0x3EFF // Data memory code protection is enabled.
3977 #define _CPD_OFF 0x3FFF // Data memory code protection is disabled.
3978 #define _BOREN_OFF 0x39FF // Brown-out Reset disabled.
3979 #define _BOREN_SBODEN 0x3BFF // Brown-out Reset controlled by the SBOREN bit in the BORCON register.
3980 #define _BOREN_NSLEEP 0x3DFF // Brown-out Reset enabled while running and disabled in Sleep.
3981 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled.
3982 #define _CLKOUTEN_ON 0x37FF // CLKOUT function is enabled on the CLKOUT pin.
3983 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
3984 #define _IESO_OFF 0x2FFF // Internal/External Switchover mode is disabled.
3985 #define _IESO_ON 0x3FFF // Internal/External Switchover mode is enabled.
3986 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
3987 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
3989 //----------------------------- CONFIG2 Options -------------------------------
3991 #define _WRT_ALL 0x3FFC // 000h to FFFh write protected, no addresses may be modified by EECON control.
3992 #define _WRT_HALF 0x3FFD // 000h to 7FFh write protected, 800h to FFFh may be modified by EECON control.
3993 #define _WRT_BOOT 0x3FFE // 000h to 1FFh write protected, 200h to FFFh may be modified by EECON control.
3994 #define _WRT_OFF 0x3FFF // Write protection off.
3995 #define _PLLEN_OFF 0x3EFF // 4x PLL disabled.
3996 #define _PLLEN_ON 0x3FFF // 4x PLL enabled.
3997 #define _STVREN_OFF 0x3DFF // Stack Overflow or Underflow will not cause a Reset.
3998 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
3999 #define _BORV_HI 0x3BFF // Brown-out Reset Voltage (Vbor), high trip point selected.
4000 #define _BORV_25 0x3BFF // Brown-out Reset Voltage (Vbor), high trip point selected.
4001 #define _BORV_LO 0x3FFF // Brown-out Reset Voltage (Vbor), low trip point selected.
4002 #define _BORV_19 0x3FFF // Brown-out Reset Voltage (Vbor), low trip point selected.
4003 #define _DEBUG_ON 0x2FFF // In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger.
4004 #define _DEBUG_OFF 0x3FFF // In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins.
4005 #define _LVP_OFF 0x1FFF // High-voltage on MCLR/VPP must be used for programming.
4006 #define _LVP_ON 0x3FFF // Low-voltage programming enabled.
4008 //==============================================================================
4010 #define _DEVID1 0x8006
4012 #define _IDLOC0 0x8000
4013 #define _IDLOC1 0x8001
4014 #define _IDLOC2 0x8002
4015 #define _IDLOC3 0x8003
4017 //==============================================================================
4019 #ifndef NO_BIT_DEFINES
4021 #define ADON ADCON0bits.ADON // bit 0
4022 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
4023 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
4024 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
4025 #define NOT_DONE ADCON0bits.NOT_DONE // bit 1, shadows bit in ADCON0bits
4026 #define CHS0 ADCON0bits.CHS0 // bit 2
4027 #define CHS1 ADCON0bits.CHS1 // bit 3
4028 #define CHS2 ADCON0bits.CHS2 // bit 4
4029 #define CHS3 ADCON0bits.CHS3 // bit 5
4030 #define CHS4 ADCON0bits.CHS4 // bit 6
4032 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
4033 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
4034 #define ADNREF ADCON1bits.ADNREF // bit 2
4035 #define ADCS0 ADCON1bits.ADCS0 // bit 4
4036 #define ADCS1 ADCON1bits.ADCS1 // bit 5
4037 #define ADCS2 ADCON1bits.ADCS2 // bit 6
4038 #define ADFM ADCON1bits.ADFM // bit 7
4040 #define ANSA0 ANSELAbits.ANSA0 // bit 0
4041 #define ANSA1 ANSELAbits.ANSA1 // bit 1
4042 #define ANSA2 ANSELAbits.ANSA2 // bit 2
4043 #define ANSA3 ANSELAbits.ANSA3 // bit 3
4044 #define ANSA4 ANSELAbits.ANSA4 // bit 4
4045 #define ANSA5 ANSELAbits.ANSA5 // bit 5
4047 #define ANSB0 ANSELBbits.ANSB0 // bit 0
4048 #define ANSB1 ANSELBbits.ANSB1 // bit 1
4049 #define ANSB2 ANSELBbits.ANSB2 // bit 2
4050 #define ANSB3 ANSELBbits.ANSB3 // bit 3
4051 #define ANSB4 ANSELBbits.ANSB4 // bit 4
4052 #define ANSB5 ANSELBbits.ANSB5 // bit 5
4054 #define CCP2SEL APFCONbits.CCP2SEL // bit 0
4055 #define SSSEL APFCONbits.SSSEL // bit 1
4056 #define C2OUTSEL APFCONbits.C2OUTSEL // bit 2
4057 #define SRNQSEL APFCONbits.SRNQSEL // bit 3
4058 #define P2BSEL APFCONbits.P2BSEL // bit 4
4059 #define T1GSEL APFCONbits.T1GSEL // bit 5
4060 #define CCP3SEL APFCONbits.CCP3SEL // bit 6
4062 #define ABDEN BAUDCONbits.ABDEN // bit 0
4063 #define WUE BAUDCONbits.WUE // bit 1
4064 #define BRG16 BAUDCONbits.BRG16 // bit 3
4065 #define SCKP BAUDCONbits.SCKP // bit 4
4066 #define RCIDL BAUDCONbits.RCIDL // bit 6
4067 #define ABDOVF BAUDCONbits.ABDOVF // bit 7
4069 #define BORRDY BORCONbits.BORRDY // bit 0
4070 #define SBOREN BORCONbits.SBOREN // bit 7
4072 #define BSR0 BSRbits.BSR0 // bit 0
4073 #define BSR1 BSRbits.BSR1 // bit 1
4074 #define BSR2 BSRbits.BSR2 // bit 2
4075 #define BSR3 BSRbits.BSR3 // bit 3
4076 #define BSR4 BSRbits.BSR4 // bit 4
4078 #define PSS1BD0 CCP1ASbits.PSS1BD0 // bit 0
4079 #define PSS1BD1 CCP1ASbits.PSS1BD1 // bit 1
4080 #define PSS1AC0 CCP1ASbits.PSS1AC0 // bit 2
4081 #define PSS1AC1 CCP1ASbits.PSS1AC1 // bit 3
4082 #define CCP1AS0 CCP1ASbits.CCP1AS0 // bit 4
4083 #define CCP1AS1 CCP1ASbits.CCP1AS1 // bit 5
4084 #define CCP1AS2 CCP1ASbits.CCP1AS2 // bit 6
4085 #define CCP1ASE CCP1ASbits.CCP1ASE // bit 7
4087 #define CCP1M0 CCP1CONbits.CCP1M0 // bit 0
4088 #define CCP1M1 CCP1CONbits.CCP1M1 // bit 1
4089 #define CCP1M2 CCP1CONbits.CCP1M2 // bit 2
4090 #define CCP1M3 CCP1CONbits.CCP1M3 // bit 3
4091 #define DC1B0 CCP1CONbits.DC1B0 // bit 4
4092 #define DC1B1 CCP1CONbits.DC1B1 // bit 5
4093 #define P1M0 CCP1CONbits.P1M0 // bit 6
4094 #define P1M1 CCP1CONbits.P1M1 // bit 7
4096 #define PSS2BD0 CCP2ASbits.PSS2BD0 // bit 0
4097 #define PSS2BD1 CCP2ASbits.PSS2BD1 // bit 1
4098 #define PSS2AC0 CCP2ASbits.PSS2AC0 // bit 2
4099 #define PSS2AC1 CCP2ASbits.PSS2AC1 // bit 3
4100 #define CCP2AS0 CCP2ASbits.CCP2AS0 // bit 4
4101 #define CCP2AS1 CCP2ASbits.CCP2AS1 // bit 5
4102 #define CCP2AS2 CCP2ASbits.CCP2AS2 // bit 6
4103 #define CCP2ASE CCP2ASbits.CCP2ASE // bit 7
4105 #define CCP2M0 CCP2CONbits.CCP2M0 // bit 0
4106 #define CCP2M1 CCP2CONbits.CCP2M1 // bit 1
4107 #define CCP2M2 CCP2CONbits.CCP2M2 // bit 2
4108 #define CCP2M3 CCP2CONbits.CCP2M3 // bit 3
4109 #define DC2B0 CCP2CONbits.DC2B0 // bit 4
4110 #define DC2B1 CCP2CONbits.DC2B1 // bit 5
4111 #define P2M0 CCP2CONbits.P2M0 // bit 6
4112 #define P2M1 CCP2CONbits.P2M1 // bit 7
4114 #define PSS3BD0 CCP3ASbits.PSS3BD0 // bit 0
4115 #define PSS3BD1 CCP3ASbits.PSS3BD1 // bit 1
4116 #define PSS3AC0 CCP3ASbits.PSS3AC0 // bit 2
4117 #define PSS3AC1 CCP3ASbits.PSS3AC1 // bit 3
4118 #define CCP3AS0 CCP3ASbits.CCP3AS0 // bit 4
4119 #define CCP3AS1 CCP3ASbits.CCP3AS1 // bit 5
4120 #define CCP3AS2 CCP3ASbits.CCP3AS2 // bit 6
4121 #define CCP3ASE CCP3ASbits.CCP3ASE // bit 7
4123 #define CCP3M0 CCP3CONbits.CCP3M0 // bit 0
4124 #define CCP3M1 CCP3CONbits.CCP3M1 // bit 1
4125 #define CCP3M2 CCP3CONbits.CCP3M2 // bit 2
4126 #define CCP3M3 CCP3CONbits.CCP3M3 // bit 3
4127 #define DC3B0 CCP3CONbits.DC3B0 // bit 4
4128 #define DC3B1 CCP3CONbits.DC3B1 // bit 5
4129 #define P3M0 CCP3CONbits.P3M0 // bit 6
4130 #define P3M1 CCP3CONbits.P3M1 // bit 7
4132 #define CCP4M0 CCP4CONbits.CCP4M0 // bit 0
4133 #define CCP4M1 CCP4CONbits.CCP4M1 // bit 1
4134 #define CCP4M2 CCP4CONbits.CCP4M2 // bit 2
4135 #define CCP4M3 CCP4CONbits.CCP4M3 // bit 3
4136 #define DC4B0 CCP4CONbits.DC4B0 // bit 4
4137 #define DC4B1 CCP4CONbits.DC4B1 // bit 5
4139 #define CCP5M0 CCP5CONbits.CCP5M0 // bit 0
4140 #define CCP5M1 CCP5CONbits.CCP5M1 // bit 1
4141 #define CCP5M2 CCP5CONbits.CCP5M2 // bit 2
4142 #define CCP5M3 CCP5CONbits.CCP5M3 // bit 3
4143 #define DC5B0 CCP5CONbits.DC5B0 // bit 4
4144 #define DC5B1 CCP5CONbits.DC5B1 // bit 5
4146 #define C1TSEL0 CCPTMRS0bits.C1TSEL0 // bit 0
4147 #define C1TSEL1 CCPTMRS0bits.C1TSEL1 // bit 1
4148 #define C2TSEL0 CCPTMRS0bits.C2TSEL0 // bit 2
4149 #define C2TSEL1 CCPTMRS0bits.C2TSEL1 // bit 3
4150 #define C3TSEL0 CCPTMRS0bits.C3TSEL0 // bit 4
4151 #define C3TSEL1 CCPTMRS0bits.C3TSEL1 // bit 5
4152 #define C4TSEL0 CCPTMRS0bits.C4TSEL0 // bit 6
4153 #define C4TSEL1 CCPTMRS0bits.C4TSEL1 // bit 7
4155 #define C5TSEL0 CCPTMRS1bits.C5TSEL0 // bit 0
4156 #define C5TSEL1 CCPTMRS1bits.C5TSEL1 // bit 1
4158 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
4159 #define C1HYS CM1CON0bits.C1HYS // bit 1
4160 #define C1SP CM1CON0bits.C1SP // bit 2
4161 #define C1POL CM1CON0bits.C1POL // bit 4
4162 #define C1OE CM1CON0bits.C1OE // bit 5
4163 #define C1OUT CM1CON0bits.C1OUT // bit 6
4164 #define C1ON CM1CON0bits.C1ON // bit 7
4166 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
4167 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
4168 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 4
4169 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 5
4170 #define C1INTN CM1CON1bits.C1INTN // bit 6
4171 #define C1INTP CM1CON1bits.C1INTP // bit 7
4173 #define C2SYNC CM2CON0bits.C2SYNC // bit 0
4174 #define C2HYS CM2CON0bits.C2HYS // bit 1
4175 #define C2SP CM2CON0bits.C2SP // bit 2
4176 #define C2POL CM2CON0bits.C2POL // bit 4
4177 #define C2OE CM2CON0bits.C2OE // bit 5
4178 #define C2OUT CM2CON0bits.C2OUT // bit 6
4179 #define C2ON CM2CON0bits.C2ON // bit 7
4181 #define C2NCH0 CM2CON1bits.C2NCH0 // bit 0
4182 #define C2NCH1 CM2CON1bits.C2NCH1 // bit 1
4183 #define C2PCH0 CM2CON1bits.C2PCH0 // bit 4
4184 #define C2PCH1 CM2CON1bits.C2PCH1 // bit 5
4185 #define C2INTN CM2CON1bits.C2INTN // bit 6
4186 #define C2INTP CM2CON1bits.C2INTP // bit 7
4188 #define MC1OUT CMOUTbits.MC1OUT // bit 0
4189 #define MC2OUT CMOUTbits.MC2OUT // bit 1
4191 #define T0XCS CPSCON0bits.T0XCS // bit 0
4192 #define CPSOUT CPSCON0bits.CPSOUT // bit 1
4193 #define CPSRNG0 CPSCON0bits.CPSRNG0 // bit 2
4194 #define CPSRNG1 CPSCON0bits.CPSRNG1 // bit 3
4195 #define CPSRM CPSCON0bits.CPSRM // bit 6
4196 #define CPSON CPSCON0bits.CPSON // bit 7
4198 #define CPSCH0 CPSCON1bits.CPSCH0 // bit 0
4199 #define CPSCH1 CPSCON1bits.CPSCH1 // bit 1
4200 #define CPSCH2 CPSCON1bits.CPSCH2 // bit 2
4202 #define DACNSS DACCON0bits.DACNSS // bit 0
4203 #define DACPSS0 DACCON0bits.DACPSS0 // bit 2
4204 #define DACPSS1 DACCON0bits.DACPSS1 // bit 3
4205 #define DACOE DACCON0bits.DACOE // bit 5
4206 #define DACLPS DACCON0bits.DACLPS // bit 6
4207 #define DACEN DACCON0bits.DACEN // bit 7
4209 #define DACR0 DACCON1bits.DACR0 // bit 0
4210 #define DACR1 DACCON1bits.DACR1 // bit 1
4211 #define DACR2 DACCON1bits.DACR2 // bit 2
4212 #define DACR3 DACCON1bits.DACR3 // bit 3
4213 #define DACR4 DACCON1bits.DACR4 // bit 4
4215 #define RD EECON1bits.RD // bit 0
4216 #define WR EECON1bits.WR // bit 1
4217 #define WREN EECON1bits.WREN // bit 2
4218 #define WRERR EECON1bits.WRERR // bit 3
4219 #define FREE EECON1bits.FREE // bit 4
4220 #define LWLO EECON1bits.LWLO // bit 5
4221 #define CFGS EECON1bits.CFGS // bit 6
4222 #define EEPGD EECON1bits.EEPGD // bit 7
4224 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
4225 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
4226 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
4227 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
4228 #define TSRNG FVRCONbits.TSRNG // bit 4
4229 #define TSEN FVRCONbits.TSEN // bit 5
4230 #define FVRRDY FVRCONbits.FVRRDY // bit 6
4231 #define FVREN FVRCONbits.FVREN // bit 7
4233 #define IOCIF INTCONbits.IOCIF // bit 0
4234 #define INTF INTCONbits.INTF // bit 1
4235 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
4236 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
4237 #define IOCIE INTCONbits.IOCIE // bit 3
4238 #define INTE INTCONbits.INTE // bit 4
4239 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
4240 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
4241 #define PEIE INTCONbits.PEIE // bit 6
4242 #define GIE INTCONbits.GIE // bit 7
4244 #define IOCBF0 IOCBFbits.IOCBF0 // bit 0
4245 #define IOCBF1 IOCBFbits.IOCBF1 // bit 1
4246 #define IOCBF2 IOCBFbits.IOCBF2 // bit 2
4247 #define IOCBF3 IOCBFbits.IOCBF3 // bit 3
4248 #define IOCBF4 IOCBFbits.IOCBF4 // bit 4
4249 #define IOCBF5 IOCBFbits.IOCBF5 // bit 5
4250 #define IOCBF6 IOCBFbits.IOCBF6 // bit 6
4251 #define IOCBF7 IOCBFbits.IOCBF7 // bit 7
4253 #define IOCBN0 IOCBNbits.IOCBN0 // bit 0
4254 #define IOCBN1 IOCBNbits.IOCBN1 // bit 1
4255 #define IOCBN2 IOCBNbits.IOCBN2 // bit 2
4256 #define IOCBN3 IOCBNbits.IOCBN3 // bit 3
4257 #define IOCBN4 IOCBNbits.IOCBN4 // bit 4
4258 #define IOCBN5 IOCBNbits.IOCBN5 // bit 5
4259 #define IOCBN6 IOCBNbits.IOCBN6 // bit 6
4260 #define IOCBN7 IOCBNbits.IOCBN7 // bit 7
4262 #define IOCBP0 IOCBPbits.IOCBP0 // bit 0
4263 #define IOCBP1 IOCBPbits.IOCBP1 // bit 1
4264 #define IOCBP2 IOCBPbits.IOCBP2 // bit 2
4265 #define IOCBP3 IOCBPbits.IOCBP3 // bit 3
4266 #define IOCBP4 IOCBPbits.IOCBP4 // bit 4
4267 #define IOCBP5 IOCBPbits.IOCBP5 // bit 5
4268 #define IOCBP6 IOCBPbits.IOCBP6 // bit 6
4269 #define IOCBP7 IOCBPbits.IOCBP7 // bit 7
4271 #define LATA0 LATAbits.LATA0 // bit 0
4272 #define LATA1 LATAbits.LATA1 // bit 1
4273 #define LATA2 LATAbits.LATA2 // bit 2
4274 #define LATA3 LATAbits.LATA3 // bit 3
4275 #define LATA4 LATAbits.LATA4 // bit 4
4276 #define LATA5 LATAbits.LATA5 // bit 5
4277 #define LATA6 LATAbits.LATA6 // bit 6
4278 #define LATA7 LATAbits.LATA7 // bit 7
4280 #define LATB0 LATBbits.LATB0 // bit 0
4281 #define LATB1 LATBbits.LATB1 // bit 1
4282 #define LATB2 LATBbits.LATB2 // bit 2
4283 #define LATB3 LATBbits.LATB3 // bit 3
4284 #define LATB4 LATBbits.LATB4 // bit 4
4285 #define LATB5 LATBbits.LATB5 // bit 5
4286 #define LATB6 LATBbits.LATB6 // bit 6
4287 #define LATB7 LATBbits.LATB7 // bit 7
4289 #define LATC0 LATCbits.LATC0 // bit 0
4290 #define LATC1 LATCbits.LATC1 // bit 1
4291 #define LATC2 LATCbits.LATC2 // bit 2
4292 #define LATC3 LATCbits.LATC3 // bit 3
4293 #define LATC4 LATCbits.LATC4 // bit 4
4294 #define LATC5 LATCbits.LATC5 // bit 5
4295 #define LATC6 LATCbits.LATC6 // bit 6
4296 #define LATC7 LATCbits.LATC7 // bit 7
4298 #define LATE3 LATEbits.LATE3 // bit 3
4300 #define LMUX0 LCDCONbits.LMUX0 // bit 0
4301 #define LMUX1 LCDCONbits.LMUX1 // bit 1
4302 #define CS0 LCDCONbits.CS0 // bit 2
4303 #define CS1 LCDCONbits.CS1 // bit 3
4304 #define WERR LCDCONbits.WERR // bit 5
4305 #define SLPEN LCDCONbits.SLPEN // bit 6
4306 #define LCDEN LCDCONbits.LCDEN // bit 7
4308 #define LCDCST0 LCDCSTbits.LCDCST0 // bit 0
4309 #define LCDCST1 LCDCSTbits.LCDCST1 // bit 1
4310 #define LCDCST2 LCDCSTbits.LCDCST2 // bit 2
4312 #define SEG0COM0 LCDDATA0bits.SEG0COM0 // bit 0
4313 #define SEG1COM0 LCDDATA0bits.SEG1COM0 // bit 1
4314 #define SEG2COM0 LCDDATA0bits.SEG2COM0 // bit 2
4315 #define SEG3COM0 LCDDATA0bits.SEG3COM0 // bit 3
4316 #define SEG4COM0 LCDDATA0bits.SEG4COM0 // bit 4
4317 #define SEG5COM0 LCDDATA0bits.SEG5COM0 // bit 5
4318 #define SEG6COM0 LCDDATA0bits.SEG6COM0 // bit 6
4319 #define SEG7COM0 LCDDATA0bits.SEG7COM0 // bit 7
4321 #define SEG8COM0 LCDDATA1bits.SEG8COM0 // bit 0
4322 #define SEG9COM0 LCDDATA1bits.SEG9COM0 // bit 1
4323 #define SEG10COM0 LCDDATA1bits.SEG10COM0 // bit 2
4324 #define SEG11COM0 LCDDATA1bits.SEG11COM0 // bit 3
4325 #define SEG12COM0 LCDDATA1bits.SEG12COM0 // bit 4
4326 #define SEG13COM0 LCDDATA1bits.SEG13COM0 // bit 5
4327 #define SEG14COM0 LCDDATA1bits.SEG14COM0 // bit 6
4328 #define SEG15COM0 LCDDATA1bits.SEG15COM0 // bit 7
4330 #define SEG0COM1 LCDDATA3bits.SEG0COM1 // bit 0
4331 #define SEG1COM1 LCDDATA3bits.SEG1COM1 // bit 1
4332 #define SEG2COM1 LCDDATA3bits.SEG2COM1 // bit 2
4333 #define SEG3COM1 LCDDATA3bits.SEG3COM1 // bit 3
4334 #define SEG4COM1 LCDDATA3bits.SEG4COM1 // bit 4
4335 #define SEG5COM1 LCDDATA3bits.SEG5COM1 // bit 5
4336 #define SEG6COM1 LCDDATA3bits.SEG6COM1 // bit 6
4337 #define SEG7COM1 LCDDATA3bits.SEG7COM1 // bit 7
4339 #define SEG8COM1 LCDDATA4bits.SEG8COM1 // bit 0
4340 #define SEG9COM1 LCDDATA4bits.SEG9COM1 // bit 1
4341 #define SEG10COM1 LCDDATA4bits.SEG10COM1 // bit 2
4342 #define SEG11COM1 LCDDATA4bits.SEG11COM1 // bit 3
4343 #define SEG12COM1 LCDDATA4bits.SEG12COM1 // bit 4
4344 #define SEG13COM1 LCDDATA4bits.SEG13COM1 // bit 5
4345 #define SEG14COM1 LCDDATA4bits.SEG14COM1 // bit 6
4346 #define SEG15COM1 LCDDATA4bits.SEG15COM1 // bit 7
4348 #define SEG0COM2 LCDDATA6bits.SEG0COM2 // bit 0
4349 #define SEG1COM2 LCDDATA6bits.SEG1COM2 // bit 1
4350 #define SEG2COM2 LCDDATA6bits.SEG2COM2 // bit 2
4351 #define SEG3COM2 LCDDATA6bits.SEG3COM2 // bit 3
4352 #define SEG4COM2 LCDDATA6bits.SEG4COM2 // bit 4
4353 #define SEG5COM2 LCDDATA6bits.SEG5COM2 // bit 5
4354 #define SEG6COM2 LCDDATA6bits.SEG6COM2 // bit 6
4355 #define SEG7COM2 LCDDATA6bits.SEG7COM2 // bit 7
4357 #define SEG8COM2 LCDDATA7bits.SEG8COM2 // bit 0
4358 #define SEG9COM2 LCDDATA7bits.SEG9COM2 // bit 1
4359 #define SEG10COM2 LCDDATA7bits.SEG10COM2 // bit 2
4360 #define SEG11COM2 LCDDATA7bits.SEG11COM2 // bit 3
4361 #define SEG12COM2 LCDDATA7bits.SEG12COM2 // bit 4
4362 #define SEG13COM2 LCDDATA7bits.SEG13COM2 // bit 5
4363 #define SEG14COM2 LCDDATA7bits.SEG14COM2 // bit 6
4364 #define SEG15COM2 LCDDATA7bits.SEG15COM2 // bit 7
4366 #define SEG0COM3 LCDDATA9bits.SEG0COM3 // bit 0
4367 #define SEG1COM3 LCDDATA9bits.SEG1COM3 // bit 1
4368 #define SEG2COM3 LCDDATA9bits.SEG2COM3 // bit 2
4369 #define SEG3COM3 LCDDATA9bits.SEG3COM3 // bit 3
4370 #define SEG4COM3 LCDDATA9bits.SEG4COM3 // bit 4
4371 #define SEG5COM3 LCDDATA9bits.SEG5COM3 // bit 5
4372 #define SEG6COM3 LCDDATA9bits.SEG6COM3 // bit 6
4373 #define SEG7COM3 LCDDATA9bits.SEG7COM3 // bit 7
4375 #define SEG8COM3 LCDDATA10bits.SEG8COM3 // bit 0
4376 #define SEG9COM3 LCDDATA10bits.SEG9COM3 // bit 1
4377 #define SEG10COM3 LCDDATA10bits.SEG10COM3 // bit 2
4378 #define SEG11COM3 LCDDATA10bits.SEG11COM3 // bit 3
4379 #define SEG12COM3 LCDDATA10bits.SEG12COM3 // bit 4
4380 #define SEG13COM3 LCDDATA10bits.SEG13COM3 // bit 5
4381 #define SEG14COM3 LCDDATA10bits.SEG14COM3 // bit 6
4382 #define SEG15COM3 LCDDATA10bits.SEG15COM3 // bit 7
4384 #define LP0 LCDPSbits.LP0 // bit 0
4385 #define LP1 LCDPSbits.LP1 // bit 1
4386 #define LP2 LCDPSbits.LP2 // bit 2
4387 #define LP3 LCDPSbits.LP3 // bit 3
4388 #define WA LCDPSbits.WA // bit 4
4389 #define LCDA LCDPSbits.LCDA // bit 5
4390 #define BIASMD LCDPSbits.BIASMD // bit 6
4391 #define WFT LCDPSbits.WFT // bit 7
4393 #define VLCD1PE LCDREFbits.VLCD1PE // bit 1
4394 #define VLCD2PE LCDREFbits.VLCD2PE // bit 2
4395 #define VLCD3PE LCDREFbits.VLCD3PE // bit 3
4396 #define LCDIRI LCDREFbits.LCDIRI // bit 5
4397 #define LCDIRS LCDREFbits.LCDIRS // bit 6
4398 #define LCDIRE LCDREFbits.LCDIRE // bit 7
4400 #define LRLAT0 LCDRLbits.LRLAT0 // bit 0
4401 #define LRLAT1 LCDRLbits.LRLAT1 // bit 1
4402 #define LRLAT2 LCDRLbits.LRLAT2 // bit 2
4403 #define LRLBP0 LCDRLbits.LRLBP0 // bit 4
4404 #define LRLBP1 LCDRLbits.LRLBP1 // bit 5
4405 #define LRLAP0 LCDRLbits.LRLAP0 // bit 6
4406 #define LRLAP1 LCDRLbits.LRLAP1 // bit 7
4408 #define SE0 LCDSE0bits.SE0 // bit 0
4409 #define SE1 LCDSE0bits.SE1 // bit 1
4410 #define SE2 LCDSE0bits.SE2 // bit 2
4411 #define SE3 LCDSE0bits.SE3 // bit 3
4412 #define SE4 LCDSE0bits.SE4 // bit 4
4413 #define SE5 LCDSE0bits.SE5 // bit 5
4414 #define SE6 LCDSE0bits.SE6 // bit 6
4415 #define SE7 LCDSE0bits.SE7 // bit 7
4417 #define SE8 LCDSE1bits.SE8 // bit 0
4418 #define SE9 LCDSE1bits.SE9 // bit 1
4419 #define SE10 LCDSE1bits.SE10 // bit 2
4420 #define SE11 LCDSE1bits.SE11 // bit 3
4421 #define SE12 LCDSE1bits.SE12 // bit 4
4422 #define SE13 LCDSE1bits.SE13 // bit 5
4423 #define SE14 LCDSE1bits.SE14 // bit 6
4424 #define SE15 LCDSE1bits.SE15 // bit 7
4426 #define PS0 OPTION_REGbits.PS0 // bit 0
4427 #define PS1 OPTION_REGbits.PS1 // bit 1
4428 #define PS2 OPTION_REGbits.PS2 // bit 2
4429 #define PSA OPTION_REGbits.PSA // bit 3
4430 #define TMR0SE OPTION_REGbits.TMR0SE // bit 4, shadows bit in OPTION_REGbits
4431 #define T0SE OPTION_REGbits.T0SE // bit 4, shadows bit in OPTION_REGbits
4432 #define TMR0CS OPTION_REGbits.TMR0CS // bit 5, shadows bit in OPTION_REGbits
4433 #define T0CS OPTION_REGbits.T0CS // bit 5, shadows bit in OPTION_REGbits
4434 #define INTEDG OPTION_REGbits.INTEDG // bit 6
4435 #define NOT_WPUEN OPTION_REGbits.NOT_WPUEN // bit 7
4437 #define SCS0 OSCCONbits.SCS0 // bit 0
4438 #define SCS1 OSCCONbits.SCS1 // bit 1
4439 #define IRCF0 OSCCONbits.IRCF0 // bit 3
4440 #define IRCF1 OSCCONbits.IRCF1 // bit 4
4441 #define IRCF2 OSCCONbits.IRCF2 // bit 5
4442 #define IRCF3 OSCCONbits.IRCF3 // bit 6
4443 #define SPLLEN OSCCONbits.SPLLEN // bit 7
4445 #define HFIOFS OSCSTATbits.HFIOFS // bit 0
4446 #define LFIOFR OSCSTATbits.LFIOFR // bit 1
4447 #define MFIOFR OSCSTATbits.MFIOFR // bit 2
4448 #define HFIOFL OSCSTATbits.HFIOFL // bit 3
4449 #define HFIOFR OSCSTATbits.HFIOFR // bit 4
4450 #define OSTS OSCSTATbits.OSTS // bit 5
4451 #define PLLR OSCSTATbits.PLLR // bit 6
4452 #define T1OSCR OSCSTATbits.T1OSCR // bit 7
4454 #define TUN0 OSCTUNEbits.TUN0 // bit 0
4455 #define TUN1 OSCTUNEbits.TUN1 // bit 1
4456 #define TUN2 OSCTUNEbits.TUN2 // bit 2
4457 #define TUN3 OSCTUNEbits.TUN3 // bit 3
4458 #define TUN4 OSCTUNEbits.TUN4 // bit 4
4459 #define TUN5 OSCTUNEbits.TUN5 // bit 5
4461 #define NOT_BOR PCONbits.NOT_BOR // bit 0
4462 #define NOT_POR PCONbits.NOT_POR // bit 1
4463 #define NOT_RI PCONbits.NOT_RI // bit 2
4464 #define NOT_RMCLR PCONbits.NOT_RMCLR // bit 3
4465 #define STKUNF PCONbits.STKUNF // bit 6
4466 #define STKOVF PCONbits.STKOVF // bit 7
4468 #define TMR1IE PIE1bits.TMR1IE // bit 0
4469 #define TMR2IE PIE1bits.TMR2IE // bit 1
4470 #define CCP1IE PIE1bits.CCP1IE // bit 2
4471 #define SSPIE PIE1bits.SSPIE // bit 3
4472 #define TXIE PIE1bits.TXIE // bit 4
4473 #define RCIE PIE1bits.RCIE // bit 5
4474 #define ADIE PIE1bits.ADIE // bit 6
4475 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
4477 #define CCP2IE PIE2bits.CCP2IE // bit 0
4478 #define LCDIE PIE2bits.LCDIE // bit 2
4479 #define BCLIE PIE2bits.BCLIE // bit 3
4480 #define EEIE PIE2bits.EEIE // bit 4
4481 #define C1IE PIE2bits.C1IE // bit 5
4482 #define C2IE PIE2bits.C2IE // bit 6
4483 #define OSFIE PIE2bits.OSFIE // bit 7
4485 #define TMR4IE PIE3bits.TMR4IE // bit 1
4486 #define TMR6IE PIE3bits.TMR6IE // bit 3
4487 #define CCP3IE PIE3bits.CCP3IE // bit 4
4488 #define CCP4IE PIE3bits.CCP4IE // bit 5
4489 #define CCP5IE PIE3bits.CCP5IE // bit 6
4491 #define TMR1IF PIR1bits.TMR1IF // bit 0
4492 #define TMR2IF PIR1bits.TMR2IF // bit 1
4493 #define CCP1IF PIR1bits.CCP1IF // bit 2
4494 #define SSPIF PIR1bits.SSPIF // bit 3
4495 #define TXIF PIR1bits.TXIF // bit 4
4496 #define RCIF PIR1bits.RCIF // bit 5
4497 #define ADIF PIR1bits.ADIF // bit 6
4498 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
4500 #define CCP2IF PIR2bits.CCP2IF // bit 0
4501 #define LCDIF PIR2bits.LCDIF // bit 2
4502 #define BCLIF PIR2bits.BCLIF // bit 3
4503 #define EEIF PIR2bits.EEIF // bit 4
4504 #define C1IF PIR2bits.C1IF // bit 5
4505 #define C2IF PIR2bits.C2IF // bit 6
4506 #define OSFIF PIR2bits.OSFIF // bit 7
4508 #define TMR4IF PIR3bits.TMR4IF // bit 1
4509 #define TMR6IF PIR3bits.TMR6IF // bit 3
4510 #define CCP3IF PIR3bits.CCP3IF // bit 4
4511 #define CCP4IF PIR3bits.CCP4IF // bit 5
4512 #define CCP5IF PIR3bits.CCP5IF // bit 6
4514 #define RA0 PORTAbits.RA0 // bit 0
4515 #define RA1 PORTAbits.RA1 // bit 1
4516 #define RA2 PORTAbits.RA2 // bit 2
4517 #define RA3 PORTAbits.RA3 // bit 3
4518 #define RA4 PORTAbits.RA4 // bit 4
4519 #define RA5 PORTAbits.RA5 // bit 5
4520 #define RA6 PORTAbits.RA6 // bit 6
4521 #define RA7 PORTAbits.RA7 // bit 7
4523 #define RB0 PORTBbits.RB0 // bit 0
4524 #define RB1 PORTBbits.RB1 // bit 1
4525 #define RB2 PORTBbits.RB2 // bit 2
4526 #define RB3 PORTBbits.RB3 // bit 3
4527 #define RB4 PORTBbits.RB4 // bit 4
4528 #define RB5 PORTBbits.RB5 // bit 5
4529 #define RB6 PORTBbits.RB6 // bit 6
4530 #define RB7 PORTBbits.RB7 // bit 7
4532 #define RC0 PORTCbits.RC0 // bit 0
4533 #define RC1 PORTCbits.RC1 // bit 1
4534 #define RC2 PORTCbits.RC2 // bit 2
4535 #define RC3 PORTCbits.RC3 // bit 3
4536 #define RC4 PORTCbits.RC4 // bit 4
4537 #define RC5 PORTCbits.RC5 // bit 5
4538 #define RC6 PORTCbits.RC6 // bit 6
4539 #define RC7 PORTCbits.RC7 // bit 7
4541 #define RE3 PORTEbits.RE3 // bit 3
4543 #define STR1A PSTR1CONbits.STR1A // bit 0
4544 #define STR1B PSTR1CONbits.STR1B // bit 1
4545 #define STR1C PSTR1CONbits.STR1C // bit 2
4546 #define STR1D PSTR1CONbits.STR1D // bit 3
4547 #define STR1SYNC PSTR1CONbits.STR1SYNC // bit 4
4549 #define STR2A PSTR2CONbits.STR2A // bit 0
4550 #define STR2B PSTR2CONbits.STR2B // bit 1
4551 #define STR2C PSTR2CONbits.STR2C // bit 2
4552 #define STR2D PSTR2CONbits.STR2D // bit 3
4553 #define STR2SYNC PSTR2CONbits.STR2SYNC // bit 4
4555 #define STR3A PSTR3CONbits.STR3A // bit 0
4556 #define STR3B PSTR3CONbits.STR3B // bit 1
4557 #define STR3C PSTR3CONbits.STR3C // bit 2
4558 #define STR3D PSTR3CONbits.STR3D // bit 3
4559 #define STR3SYNC PSTR3CONbits.STR3SYNC // bit 4
4561 #define P1DC0 PWM1CONbits.P1DC0 // bit 0
4562 #define P1DC1 PWM1CONbits.P1DC1 // bit 1
4563 #define P1DC2 PWM1CONbits.P1DC2 // bit 2
4564 #define P1DC3 PWM1CONbits.P1DC3 // bit 3
4565 #define P1DC4 PWM1CONbits.P1DC4 // bit 4
4566 #define P1DC5 PWM1CONbits.P1DC5 // bit 5
4567 #define P1DC6 PWM1CONbits.P1DC6 // bit 6
4568 #define P1RSEN PWM1CONbits.P1RSEN // bit 7
4570 #define P2DC0 PWM2CONbits.P2DC0 // bit 0
4571 #define P2DC1 PWM2CONbits.P2DC1 // bit 1
4572 #define P2DC2 PWM2CONbits.P2DC2 // bit 2
4573 #define P2DC3 PWM2CONbits.P2DC3 // bit 3
4574 #define P2DC4 PWM2CONbits.P2DC4 // bit 4
4575 #define P2DC5 PWM2CONbits.P2DC5 // bit 5
4576 #define P2DC6 PWM2CONbits.P2DC6 // bit 6
4577 #define P2RSEN PWM2CONbits.P2RSEN // bit 7
4579 #define P3DC0 PWM3CONbits.P3DC0 // bit 0
4580 #define P3DC1 PWM3CONbits.P3DC1 // bit 1
4581 #define P3DC2 PWM3CONbits.P3DC2 // bit 2
4582 #define P3DC3 PWM3CONbits.P3DC3 // bit 3
4583 #define P3DC4 PWM3CONbits.P3DC4 // bit 4
4584 #define P3DC5 PWM3CONbits.P3DC5 // bit 5
4585 #define P3DC6 PWM3CONbits.P3DC6 // bit 6
4586 #define P3RSEN PWM3CONbits.P3RSEN // bit 7
4588 #define RX9D RCSTAbits.RX9D // bit 0
4589 #define OERR RCSTAbits.OERR // bit 1
4590 #define FERR RCSTAbits.FERR // bit 2
4591 #define ADDEN RCSTAbits.ADDEN // bit 3
4592 #define CREN RCSTAbits.CREN // bit 4
4593 #define SREN RCSTAbits.SREN // bit 5
4594 #define RX9 RCSTAbits.RX9 // bit 6
4595 #define SPEN RCSTAbits.SPEN // bit 7
4597 #define SRPR SRCON0bits.SRPR // bit 0
4598 #define SRPS SRCON0bits.SRPS // bit 1
4599 #define SRNQEN SRCON0bits.SRNQEN // bit 2
4600 #define SRQEN SRCON0bits.SRQEN // bit 3
4601 #define SRCLK0 SRCON0bits.SRCLK0 // bit 4
4602 #define SRCLK1 SRCON0bits.SRCLK1 // bit 5
4603 #define SRCLK2 SRCON0bits.SRCLK2 // bit 6
4604 #define SRLEN SRCON0bits.SRLEN // bit 7
4606 #define SRRC1E SRCON1bits.SRRC1E // bit 0
4607 #define SRRC2E SRCON1bits.SRRC2E // bit 1
4608 #define SRRCKE SRCON1bits.SRRCKE // bit 2
4609 #define SRRPE SRCON1bits.SRRPE // bit 3
4610 #define SRSC1E SRCON1bits.SRSC1E // bit 4
4611 #define SRSC2E SRCON1bits.SRSC2E // bit 5
4612 #define SRSCKE SRCON1bits.SRSCKE // bit 6
4613 #define SRSPE SRCON1bits.SRSPE // bit 7
4615 #define SSPM0 SSPCONbits.SSPM0 // bit 0
4616 #define SSPM1 SSPCONbits.SSPM1 // bit 1
4617 #define SSPM2 SSPCONbits.SSPM2 // bit 2
4618 #define SSPM3 SSPCONbits.SSPM3 // bit 3
4619 #define CKP SSPCONbits.CKP // bit 4
4620 #define SSPEN SSPCONbits.SSPEN // bit 5
4621 #define SSPOV SSPCONbits.SSPOV // bit 6
4622 #define WCOL SSPCONbits.WCOL // bit 7
4624 #define SEN SSPCON2bits.SEN // bit 0
4625 #define RSEN SSPCON2bits.RSEN // bit 1
4626 #define PEN SSPCON2bits.PEN // bit 2
4627 #define RCEN SSPCON2bits.RCEN // bit 3
4628 #define ACKEN SSPCON2bits.ACKEN // bit 4
4629 #define ACKDT SSPCON2bits.ACKDT // bit 5
4630 #define ACKSTAT SSPCON2bits.ACKSTAT // bit 6
4631 #define GCEN SSPCON2bits.GCEN // bit 7
4633 #define DHEN SSPCON3bits.DHEN // bit 0
4634 #define AHEN SSPCON3bits.AHEN // bit 1
4635 #define SBCDE SSPCON3bits.SBCDE // bit 2
4636 #define SDAHT SSPCON3bits.SDAHT // bit 3
4637 #define BOEN SSPCON3bits.BOEN // bit 4
4638 #define SCIE SSPCON3bits.SCIE // bit 5
4639 #define PCIE SSPCON3bits.PCIE // bit 6
4640 #define ACKTIM SSPCON3bits.ACKTIM // bit 7
4642 #define BF SSPSTATbits.BF // bit 0
4643 #define UA SSPSTATbits.UA // bit 1
4644 #define R_NOT_W SSPSTATbits.R_NOT_W // bit 2
4645 #define S SSPSTATbits.S // bit 3
4646 #define P SSPSTATbits.P // bit 4
4647 #define D_NOT_A SSPSTATbits.D_NOT_A // bit 5
4648 #define CKE SSPSTATbits.CKE // bit 6
4649 #define SMP SSPSTATbits.SMP // bit 7
4651 #define C STATUSbits.C // bit 0
4652 #define DC STATUSbits.DC // bit 1
4653 #define Z STATUSbits.Z // bit 2
4654 #define NOT_PD STATUSbits.NOT_PD // bit 3
4655 #define NOT_TO STATUSbits.NOT_TO // bit 4
4657 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
4658 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
4659 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
4661 #define TMR1ON T1CONbits.TMR1ON // bit 0
4662 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
4663 #define T1OSCEN T1CONbits.T1OSCEN // bit 3
4664 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
4665 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
4666 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
4667 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
4669 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
4670 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
4671 #define T1GVAL T1GCONbits.T1GVAL // bit 2
4672 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3, shadows bit in T1GCONbits
4673 #define T1GGO T1GCONbits.T1GGO // bit 3, shadows bit in T1GCONbits
4674 #define T1GSPM T1GCONbits.T1GSPM // bit 4
4675 #define T1GTM T1GCONbits.T1GTM // bit 5
4676 #define T1GPOL T1GCONbits.T1GPOL // bit 6
4677 #define TMR1GE T1GCONbits.TMR1GE // bit 7
4679 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
4680 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
4681 #define TMR2ON T2CONbits.TMR2ON // bit 2
4682 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
4683 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
4684 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
4685 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
4687 #define T4CKPS0 T4CONbits.T4CKPS0 // bit 0
4688 #define T4CKPS1 T4CONbits.T4CKPS1 // bit 1
4689 #define TMR4ON T4CONbits.TMR4ON // bit 2
4690 #define T4OUTPS0 T4CONbits.T4OUTPS0 // bit 3
4691 #define T4OUTPS1 T4CONbits.T4OUTPS1 // bit 4
4692 #define T4OUTPS2 T4CONbits.T4OUTPS2 // bit 5
4693 #define T4OUTPS3 T4CONbits.T4OUTPS3 // bit 6
4695 #define T6CKPS0 T6CONbits.T6CKPS0 // bit 0
4696 #define T6CKPS1 T6CONbits.T6CKPS1 // bit 1
4697 #define TMR6ON T6CONbits.TMR6ON // bit 2
4698 #define T6OUTPS0 T6CONbits.T6OUTPS0 // bit 3
4699 #define T6OUTPS1 T6CONbits.T6OUTPS1 // bit 4
4700 #define T6OUTPS2 T6CONbits.T6OUTPS2 // bit 5
4701 #define T6OUTPS3 T6CONbits.T6OUTPS3 // bit 6
4703 #define TRISA0 TRISAbits.TRISA0 // bit 0
4704 #define TRISA1 TRISAbits.TRISA1 // bit 1
4705 #define TRISA2 TRISAbits.TRISA2 // bit 2
4706 #define TRISA3 TRISAbits.TRISA3 // bit 3
4707 #define TRISA4 TRISAbits.TRISA4 // bit 4
4708 #define TRISA5 TRISAbits.TRISA5 // bit 5
4709 #define TRISA6 TRISAbits.TRISA6 // bit 6
4710 #define TRISA7 TRISAbits.TRISA7 // bit 7
4712 #define TRISB0 TRISBbits.TRISB0 // bit 0
4713 #define TRISB1 TRISBbits.TRISB1 // bit 1
4714 #define TRISB2 TRISBbits.TRISB2 // bit 2
4715 #define TRISB3 TRISBbits.TRISB3 // bit 3
4716 #define TRISB4 TRISBbits.TRISB4 // bit 4
4717 #define TRISB5 TRISBbits.TRISB5 // bit 5
4718 #define TRISB6 TRISBbits.TRISB6 // bit 6
4719 #define TRISB7 TRISBbits.TRISB7 // bit 7
4721 #define TRISC0 TRISCbits.TRISC0 // bit 0
4722 #define TRISC1 TRISCbits.TRISC1 // bit 1
4723 #define TRISC2 TRISCbits.TRISC2 // bit 2
4724 #define TRISC3 TRISCbits.TRISC3 // bit 3
4725 #define TRISC4 TRISCbits.TRISC4 // bit 4
4726 #define TRISC5 TRISCbits.TRISC5 // bit 5
4727 #define TRISC6 TRISCbits.TRISC6 // bit 6
4728 #define TRISC7 TRISCbits.TRISC7 // bit 7
4730 #define TRISE3 TRISEbits.TRISE3 // bit 3
4732 #define TX9D TXSTAbits.TX9D // bit 0
4733 #define TRMT TXSTAbits.TRMT // bit 1
4734 #define BRGH TXSTAbits.BRGH // bit 2
4735 #define SENDB TXSTAbits.SENDB // bit 3
4736 #define SYNC TXSTAbits.SYNC // bit 4
4737 #define TXEN TXSTAbits.TXEN // bit 5
4738 #define TX9 TXSTAbits.TX9 // bit 6
4739 #define CSRC TXSTAbits.CSRC // bit 7
4741 #define SWDTEN WDTCONbits.SWDTEN // bit 0
4742 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
4743 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
4744 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
4745 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
4746 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
4748 #define WPUB0 WPUBbits.WPUB0 // bit 0
4749 #define WPUB1 WPUBbits.WPUB1 // bit 1
4750 #define WPUB2 WPUBbits.WPUB2 // bit 2
4751 #define WPUB3 WPUBbits.WPUB3 // bit 3
4752 #define WPUB4 WPUBbits.WPUB4 // bit 4
4753 #define WPUB5 WPUBbits.WPUB5 // bit 5
4754 #define WPUB6 WPUBbits.WPUB6 // bit 6
4755 #define WPUB7 WPUBbits.WPUB7 // bit 7
4757 #define WPUE3 WPUEbits.WPUE3 // bit 3
4759 #endif // #ifndef NO_BIT_DEFINES
4761 #endif // #ifndef __PIC16LF1933_H__