2 * This declarations of the PIC16LF1939 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:22 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC16LF1939_H__
26 #define __PIC16LF1939_H__
28 //==============================================================================
32 //==============================================================================
34 #ifndef NO_ADDR_DEFINES
36 #define INDF0_ADDR 0x0000
37 #define INDF1_ADDR 0x0001
38 #define PCL_ADDR 0x0002
39 #define STATUS_ADDR 0x0003
40 #define FSR0_ADDR 0x0004
41 #define FSR0L_ADDR 0x0004
42 #define FSR0H_ADDR 0x0005
43 #define FSR1_ADDR 0x0006
44 #define FSR1L_ADDR 0x0006
45 #define FSR1H_ADDR 0x0007
46 #define BSR_ADDR 0x0008
47 #define WREG_ADDR 0x0009
48 #define PCLATH_ADDR 0x000A
49 #define INTCON_ADDR 0x000B
50 #define PORTA_ADDR 0x000C
51 #define PORTB_ADDR 0x000D
52 #define PORTC_ADDR 0x000E
53 #define PORTD_ADDR 0x000F
54 #define PORTE_ADDR 0x0010
55 #define PIR1_ADDR 0x0011
56 #define PIR2_ADDR 0x0012
57 #define PIR3_ADDR 0x0013
58 #define TMR0_ADDR 0x0015
59 #define TMR1_ADDR 0x0016
60 #define TMR1L_ADDR 0x0016
61 #define TMR1H_ADDR 0x0017
62 #define T1CON_ADDR 0x0018
63 #define T1GCON_ADDR 0x0019
64 #define TMR2_ADDR 0x001A
65 #define PR2_ADDR 0x001B
66 #define T2CON_ADDR 0x001C
67 #define CPSCON0_ADDR 0x001E
68 #define CPSCON1_ADDR 0x001F
69 #define TRISA_ADDR 0x008C
70 #define TRISB_ADDR 0x008D
71 #define TRISC_ADDR 0x008E
72 #define TRISD_ADDR 0x008F
73 #define TRISE_ADDR 0x0090
74 #define PIE1_ADDR 0x0091
75 #define PIE2_ADDR 0x0092
76 #define PIE3_ADDR 0x0093
77 #define OPTION_REG_ADDR 0x0095
78 #define PCON_ADDR 0x0096
79 #define WDTCON_ADDR 0x0097
80 #define OSCTUNE_ADDR 0x0098
81 #define OSCCON_ADDR 0x0099
82 #define OSCSTAT_ADDR 0x009A
83 #define ADRES_ADDR 0x009B
84 #define ADRESL_ADDR 0x009B
85 #define ADRESH_ADDR 0x009C
86 #define ADCON0_ADDR 0x009D
87 #define ADCON1_ADDR 0x009E
88 #define LATA_ADDR 0x010C
89 #define LATB_ADDR 0x010D
90 #define LATC_ADDR 0x010E
91 #define LATD_ADDR 0x010F
92 #define LATE_ADDR 0x0110
93 #define CM1CON0_ADDR 0x0111
94 #define CM1CON1_ADDR 0x0112
95 #define CM2CON0_ADDR 0x0113
96 #define CM2CON1_ADDR 0x0114
97 #define CMOUT_ADDR 0x0115
98 #define BORCON_ADDR 0x0116
99 #define FVRCON_ADDR 0x0117
100 #define DACCON0_ADDR 0x0118
101 #define DACCON1_ADDR 0x0119
102 #define SRCON0_ADDR 0x011A
103 #define SRCON1_ADDR 0x011B
104 #define APFCON_ADDR 0x011D
105 #define ANSELA_ADDR 0x018C
106 #define ANSELB_ADDR 0x018D
107 #define ANSELD_ADDR 0x018F
108 #define ANSELE_ADDR 0x0190
109 #define EEADR_ADDR 0x0191
110 #define EEADRL_ADDR 0x0191
111 #define EEADRH_ADDR 0x0192
112 #define EEDAT_ADDR 0x0193
113 #define EEDATL_ADDR 0x0193
114 #define EEDATH_ADDR 0x0194
115 #define EECON1_ADDR 0x0195
116 #define EECON2_ADDR 0x0196
117 #define RCREG_ADDR 0x0199
118 #define TXREG_ADDR 0x019A
119 #define SP1BRG_ADDR 0x019B
120 #define SP1BRGL_ADDR 0x019B
121 #define SPBRG_ADDR 0x019B
122 #define SPBRGL_ADDR 0x019B
123 #define SP1BRGH_ADDR 0x019C
124 #define SPBRGH_ADDR 0x019C
125 #define RCSTA_ADDR 0x019D
126 #define TXSTA_ADDR 0x019E
127 #define BAUDCON_ADDR 0x019F
128 #define WPUB_ADDR 0x020D
129 #define WPUE_ADDR 0x0210
130 #define SSPBUF_ADDR 0x0211
131 #define SSPADD_ADDR 0x0212
132 #define SSPMSK_ADDR 0x0213
133 #define SSPSTAT_ADDR 0x0214
134 #define SSPCON_ADDR 0x0215
135 #define SSPCON1_ADDR 0x0215
136 #define SSPCON2_ADDR 0x0216
137 #define SSPCON3_ADDR 0x0217
138 #define CCPR1_ADDR 0x0291
139 #define CCPR1L_ADDR 0x0291
140 #define CCPR1H_ADDR 0x0292
141 #define CCP1CON_ADDR 0x0293
142 #define PWM1CON_ADDR 0x0294
143 #define CCP1AS_ADDR 0x0295
144 #define ECCP1AS_ADDR 0x0295
145 #define PSTR1CON_ADDR 0x0296
146 #define CCPR2_ADDR 0x0298
147 #define CCPR2L_ADDR 0x0298
148 #define CCPR2H_ADDR 0x0299
149 #define CCP2CON_ADDR 0x029A
150 #define PWM2CON_ADDR 0x029B
151 #define CCP2AS_ADDR 0x029C
152 #define ECCP2AS_ADDR 0x029C
153 #define PSTR2CON_ADDR 0x029D
154 #define CCPTMRS0_ADDR 0x029E
155 #define CCPTMRS1_ADDR 0x029F
156 #define CCPR3_ADDR 0x0311
157 #define CCPR3L_ADDR 0x0311
158 #define CCPR3H_ADDR 0x0312
159 #define CCP3CON_ADDR 0x0313
160 #define PWM3CON_ADDR 0x0314
161 #define CCP3AS_ADDR 0x0315
162 #define ECCP3AS_ADDR 0x0315
163 #define PSTR3CON_ADDR 0x0316
164 #define CCPR4_ADDR 0x0318
165 #define CCPR4L_ADDR 0x0318
166 #define CCPR4H_ADDR 0x0319
167 #define CCP4CON_ADDR 0x031A
168 #define CCPR5_ADDR 0x031C
169 #define CCPR5L_ADDR 0x031C
170 #define CCPR5H_ADDR 0x031D
171 #define CCP5CON_ADDR 0x031E
172 #define IOCBP_ADDR 0x0394
173 #define IOCBN_ADDR 0x0395
174 #define IOCBF_ADDR 0x0396
175 #define TMR4_ADDR 0x0415
176 #define PR4_ADDR 0x0416
177 #define T4CON_ADDR 0x0417
178 #define TMR6_ADDR 0x041C
179 #define PR6_ADDR 0x041D
180 #define T6CON_ADDR 0x041E
181 #define LCDCON_ADDR 0x0791
182 #define LCDPS_ADDR 0x0792
183 #define LCDREF_ADDR 0x0793
184 #define LCDCST_ADDR 0x0794
185 #define LCDRL_ADDR 0x0795
186 #define LCDSE0_ADDR 0x0798
187 #define LCDSE1_ADDR 0x0799
188 #define LCDSE2_ADDR 0x079A
189 #define LCDDATA0_ADDR 0x07A0
190 #define LCDDATA1_ADDR 0x07A1
191 #define LCDDATA2_ADDR 0x07A2
192 #define LCDDATA3_ADDR 0x07A3
193 #define LCDDATA4_ADDR 0x07A4
194 #define LCDDATA5_ADDR 0x07A5
195 #define LCDDATA6_ADDR 0x07A6
196 #define LCDDATA7_ADDR 0x07A7
197 #define LCDDATA8_ADDR 0x07A8
198 #define LCDDATA9_ADDR 0x07A9
199 #define LCDDATA10_ADDR 0x07AA
200 #define LCDDATA11_ADDR 0x07AB
201 #define STATUS_SHAD_ADDR 0x0FE4
202 #define WREG_SHAD_ADDR 0x0FE5
203 #define BSR_SHAD_ADDR 0x0FE6
204 #define PCLATH_SHAD_ADDR 0x0FE7
205 #define FSR0L_SHAD_ADDR 0x0FE8
206 #define FSR0H_SHAD_ADDR 0x0FE9
207 #define FSR1L_SHAD_ADDR 0x0FEA
208 #define FSR1H_SHAD_ADDR 0x0FEB
209 #define STKPTR_ADDR 0x0FED
210 #define TOSL_ADDR 0x0FEE
211 #define TOSH_ADDR 0x0FEF
213 #endif // #ifndef NO_ADDR_DEFINES
215 //==============================================================================
217 // Register Definitions
219 //==============================================================================
221 extern __at(0x0000) __sfr INDF0
;
222 extern __at(0x0001) __sfr INDF1
;
223 extern __at(0x0002) __sfr PCL
;
225 //==============================================================================
228 extern __at(0x0003) __sfr STATUS
;
242 extern __at(0x0003) volatile __STATUSbits_t STATUSbits
;
250 //==============================================================================
252 extern __at(0x0004) __sfr FSR0
;
253 extern __at(0x0004) __sfr FSR0L
;
254 extern __at(0x0005) __sfr FSR0H
;
255 extern __at(0x0006) __sfr FSR1
;
256 extern __at(0x0006) __sfr FSR1L
;
257 extern __at(0x0007) __sfr FSR1H
;
259 //==============================================================================
262 extern __at(0x0008) __sfr BSR
;
285 extern __at(0x0008) volatile __BSRbits_t BSRbits
;
293 //==============================================================================
295 extern __at(0x0009) __sfr WREG
;
296 extern __at(0x000A) __sfr PCLATH
;
298 //==============================================================================
301 extern __at(0x000B) __sfr INTCON
;
330 extern __at(0x000B) volatile __INTCONbits_t INTCONbits
;
343 //==============================================================================
346 //==============================================================================
349 extern __at(0x000C) __sfr PORTA
;
363 extern __at(0x000C) volatile __PORTAbits_t PORTAbits
;
374 //==============================================================================
377 //==============================================================================
380 extern __at(0x000D) __sfr PORTB
;
394 extern __at(0x000D) volatile __PORTBbits_t PORTBbits
;
405 //==============================================================================
408 //==============================================================================
411 extern __at(0x000E) __sfr PORTC
;
425 extern __at(0x000E) volatile __PORTCbits_t PORTCbits
;
436 //==============================================================================
439 //==============================================================================
442 extern __at(0x000F) __sfr PORTD
;
456 extern __at(0x000F) volatile __PORTDbits_t PORTDbits
;
467 //==============================================================================
470 //==============================================================================
473 extern __at(0x0010) __sfr PORTE
;
496 extern __at(0x0010) volatile __PORTEbits_t PORTEbits
;
503 //==============================================================================
506 //==============================================================================
509 extern __at(0x0011) __sfr PIR1
;
520 unsigned TMR1GIF
: 1;
523 extern __at(0x0011) volatile __PIR1bits_t PIR1bits
;
532 #define _TMR1GIF 0x80
534 //==============================================================================
537 //==============================================================================
540 extern __at(0x0012) __sfr PIR2
;
554 extern __at(0x0012) volatile __PIR2bits_t PIR2bits
;
564 //==============================================================================
567 //==============================================================================
570 extern __at(0x0013) __sfr PIR3
;
584 extern __at(0x0013) volatile __PIR3bits_t PIR3bits
;
592 //==============================================================================
594 extern __at(0x0015) __sfr TMR0
;
595 extern __at(0x0016) __sfr TMR1
;
596 extern __at(0x0016) __sfr TMR1L
;
597 extern __at(0x0017) __sfr TMR1H
;
599 //==============================================================================
602 extern __at(0x0018) __sfr T1CON
;
610 unsigned NOT_T1SYNC
: 1;
611 unsigned T1OSCEN
: 1;
612 unsigned T1CKPS0
: 1;
613 unsigned T1CKPS1
: 1;
614 unsigned TMR1CS0
: 1;
615 unsigned TMR1CS1
: 1;
632 extern __at(0x0018) volatile __T1CONbits_t T1CONbits
;
635 #define _NOT_T1SYNC 0x04
636 #define _T1OSCEN 0x08
637 #define _T1CKPS0 0x10
638 #define _T1CKPS1 0x20
639 #define _TMR1CS0 0x40
640 #define _TMR1CS1 0x80
642 //==============================================================================
645 //==============================================================================
648 extern __at(0x0019) __sfr T1GCON
;
657 unsigned T1GGO_NOT_DONE
: 1;
683 extern __at(0x0019) volatile __T1GCONbits_t T1GCONbits
;
688 #define _T1GGO_NOT_DONE 0x08
695 //==============================================================================
697 extern __at(0x001A) __sfr TMR2
;
698 extern __at(0x001B) __sfr PR2
;
700 //==============================================================================
703 extern __at(0x001C) __sfr T2CON
;
709 unsigned T2CKPS0
: 1;
710 unsigned T2CKPS1
: 1;
712 unsigned T2OUTPS0
: 1;
713 unsigned T2OUTPS1
: 1;
714 unsigned T2OUTPS2
: 1;
715 unsigned T2OUTPS3
: 1;
728 unsigned T2OUTPS
: 4;
733 extern __at(0x001C) volatile __T2CONbits_t T2CONbits
;
735 #define _T2CKPS0 0x01
736 #define _T2CKPS1 0x02
738 #define _T2OUTPS0 0x08
739 #define _T2OUTPS1 0x10
740 #define _T2OUTPS2 0x20
741 #define _T2OUTPS3 0x40
743 //==============================================================================
746 //==============================================================================
749 extern __at(0x001E) __sfr CPSCON0
;
757 unsigned CPSRNG0
: 1;
758 unsigned CPSRNG1
: 1;
773 extern __at(0x001E) volatile __CPSCON0bits_t CPSCON0bits
;
777 #define _CPSRNG0 0x04
778 #define _CPSRNG1 0x08
782 //==============================================================================
785 //==============================================================================
788 extern __at(0x001F) __sfr CPSCON1
;
811 extern __at(0x001F) volatile __CPSCON1bits_t CPSCON1bits
;
818 //==============================================================================
821 //==============================================================================
824 extern __at(0x008C) __sfr TRISA
;
838 extern __at(0x008C) volatile __TRISAbits_t TRISAbits
;
849 //==============================================================================
852 //==============================================================================
855 extern __at(0x008D) __sfr TRISB
;
869 extern __at(0x008D) volatile __TRISBbits_t TRISBbits
;
880 //==============================================================================
883 //==============================================================================
886 extern __at(0x008E) __sfr TRISC
;
900 extern __at(0x008E) volatile __TRISCbits_t TRISCbits
;
911 //==============================================================================
914 //==============================================================================
917 extern __at(0x008F) __sfr TRISD
;
931 extern __at(0x008F) volatile __TRISDbits_t TRISDbits
;
942 //==============================================================================
945 //==============================================================================
948 extern __at(0x0090) __sfr TRISE
;
971 extern __at(0x0090) volatile __TRISEbits_t TRISEbits
;
978 //==============================================================================
981 //==============================================================================
984 extern __at(0x0091) __sfr PIE1
;
995 unsigned TMR1GIE
: 1;
998 extern __at(0x0091) volatile __PIE1bits_t PIE1bits
;
1000 #define _TMR1IE 0x01
1001 #define _TMR2IE 0x02
1002 #define _CCP1IE 0x04
1007 #define _TMR1GIE 0x80
1009 //==============================================================================
1012 //==============================================================================
1015 extern __at(0x0092) __sfr PIE2
;
1019 unsigned CCP2IE
: 1;
1029 extern __at(0x0092) volatile __PIE2bits_t PIE2bits
;
1031 #define _CCP2IE 0x01
1039 //==============================================================================
1042 //==============================================================================
1045 extern __at(0x0093) __sfr PIE3
;
1050 unsigned TMR4IE
: 1;
1052 unsigned TMR6IE
: 1;
1053 unsigned CCP3IE
: 1;
1054 unsigned CCP4IE
: 1;
1055 unsigned CCP5IE
: 1;
1059 extern __at(0x0093) volatile __PIE3bits_t PIE3bits
;
1061 #define _TMR4IE 0x02
1062 #define _TMR6IE 0x08
1063 #define _CCP3IE 0x10
1064 #define _CCP4IE 0x20
1065 #define _CCP5IE 0x40
1067 //==============================================================================
1070 //==============================================================================
1073 extern __at(0x0095) __sfr OPTION_REG
;
1083 unsigned TMR0SE
: 1;
1084 unsigned TMR0CS
: 1;
1085 unsigned INTEDG
: 1;
1086 unsigned NOT_WPUEN
: 1;
1106 } __OPTION_REGbits_t
;
1108 extern __at(0x0095) volatile __OPTION_REGbits_t OPTION_REGbits
;
1114 #define _TMR0SE 0x10
1116 #define _TMR0CS 0x20
1118 #define _INTEDG 0x40
1119 #define _NOT_WPUEN 0x80
1121 //==============================================================================
1124 //==============================================================================
1127 extern __at(0x0096) __sfr PCON
;
1131 unsigned NOT_BOR
: 1;
1132 unsigned NOT_POR
: 1;
1133 unsigned NOT_RI
: 1;
1134 unsigned NOT_RMCLR
: 1;
1137 unsigned STKUNF
: 1;
1138 unsigned STKOVF
: 1;
1141 extern __at(0x0096) volatile __PCONbits_t PCONbits
;
1143 #define _NOT_BOR 0x01
1144 #define _NOT_POR 0x02
1145 #define _NOT_RI 0x04
1146 #define _NOT_RMCLR 0x08
1147 #define _STKUNF 0x40
1148 #define _STKOVF 0x80
1150 //==============================================================================
1153 //==============================================================================
1156 extern __at(0x0097) __sfr WDTCON
;
1162 unsigned SWDTEN
: 1;
1163 unsigned WDTPS0
: 1;
1164 unsigned WDTPS1
: 1;
1165 unsigned WDTPS2
: 1;
1166 unsigned WDTPS3
: 1;
1167 unsigned WDTPS4
: 1;
1180 extern __at(0x0097) volatile __WDTCONbits_t WDTCONbits
;
1182 #define _SWDTEN 0x01
1183 #define _WDTPS0 0x02
1184 #define _WDTPS1 0x04
1185 #define _WDTPS2 0x08
1186 #define _WDTPS3 0x10
1187 #define _WDTPS4 0x20
1189 //==============================================================================
1192 //==============================================================================
1195 extern __at(0x0098) __sfr OSCTUNE
;
1218 extern __at(0x0098) volatile __OSCTUNEbits_t OSCTUNEbits
;
1227 //==============================================================================
1230 //==============================================================================
1233 extern __at(0x0099) __sfr OSCCON
;
1246 unsigned SPLLEN
: 1;
1263 extern __at(0x0099) volatile __OSCCONbits_t OSCCONbits
;
1271 #define _SPLLEN 0x80
1273 //==============================================================================
1276 //==============================================================================
1279 extern __at(0x009A) __sfr OSCSTAT
;
1283 unsigned HFIOFS
: 1;
1284 unsigned LFIOFR
: 1;
1285 unsigned MFIOFR
: 1;
1286 unsigned HFIOFL
: 1;
1287 unsigned HFIOFR
: 1;
1290 unsigned T1OSCR
: 1;
1293 extern __at(0x009A) volatile __OSCSTATbits_t OSCSTATbits
;
1295 #define _HFIOFS 0x01
1296 #define _LFIOFR 0x02
1297 #define _MFIOFR 0x04
1298 #define _HFIOFL 0x08
1299 #define _HFIOFR 0x10
1302 #define _T1OSCR 0x80
1304 //==============================================================================
1306 extern __at(0x009B) __sfr ADRES
;
1307 extern __at(0x009B) __sfr ADRESL
;
1308 extern __at(0x009C) __sfr ADRESH
;
1310 //==============================================================================
1313 extern __at(0x009D) __sfr ADCON0
;
1320 unsigned GO_NOT_DONE
: 1;
1356 unsigned NOT_DONE
: 1;
1373 extern __at(0x009D) volatile __ADCON0bits_t ADCON0bits
;
1376 #define _GO_NOT_DONE 0x02
1379 #define _NOT_DONE 0x02
1386 //==============================================================================
1389 //==============================================================================
1392 extern __at(0x009E) __sfr ADCON1
;
1398 unsigned ADPREF0
: 1;
1399 unsigned ADPREF1
: 1;
1400 unsigned ADNREF
: 1;
1410 unsigned ADPREF
: 2;
1422 extern __at(0x009E) volatile __ADCON1bits_t ADCON1bits
;
1424 #define _ADPREF0 0x01
1425 #define _ADPREF1 0x02
1426 #define _ADNREF 0x04
1432 //==============================================================================
1435 //==============================================================================
1438 extern __at(0x010C) __sfr LATA
;
1452 extern __at(0x010C) volatile __LATAbits_t LATAbits
;
1463 //==============================================================================
1466 //==============================================================================
1469 extern __at(0x010D) __sfr LATB
;
1483 extern __at(0x010D) volatile __LATBbits_t LATBbits
;
1494 //==============================================================================
1497 //==============================================================================
1500 extern __at(0x010E) __sfr LATC
;
1514 extern __at(0x010E) volatile __LATCbits_t LATCbits
;
1525 //==============================================================================
1528 //==============================================================================
1531 extern __at(0x010F) __sfr LATD
;
1545 extern __at(0x010F) volatile __LATDbits_t LATDbits
;
1556 //==============================================================================
1559 //==============================================================================
1562 extern __at(0x0110) __sfr LATE
;
1585 extern __at(0x0110) volatile __LATEbits_t LATEbits
;
1592 //==============================================================================
1595 //==============================================================================
1598 extern __at(0x0111) __sfr CM1CON0
;
1602 unsigned C1SYNC
: 1;
1612 extern __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits
;
1614 #define _C1SYNC 0x01
1622 //==============================================================================
1625 //==============================================================================
1628 extern __at(0x0112) __sfr CM1CON1
;
1634 unsigned C1NCH0
: 1;
1635 unsigned C1NCH1
: 1;
1638 unsigned C1PCH0
: 1;
1639 unsigned C1PCH1
: 1;
1640 unsigned C1INTN
: 1;
1641 unsigned C1INTP
: 1;
1658 extern __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits
;
1660 #define _C1NCH0 0x01
1661 #define _C1NCH1 0x02
1662 #define _C1PCH0 0x10
1663 #define _C1PCH1 0x20
1664 #define _C1INTN 0x40
1665 #define _C1INTP 0x80
1667 //==============================================================================
1670 //==============================================================================
1673 extern __at(0x0113) __sfr CM2CON0
;
1677 unsigned C2SYNC
: 1;
1687 extern __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits
;
1689 #define _C2SYNC 0x01
1697 //==============================================================================
1700 //==============================================================================
1703 extern __at(0x0114) __sfr CM2CON1
;
1709 unsigned C2NCH0
: 1;
1710 unsigned C2NCH1
: 1;
1713 unsigned C2PCH0
: 1;
1714 unsigned C2PCH1
: 1;
1715 unsigned C2INTN
: 1;
1716 unsigned C2INTP
: 1;
1733 extern __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits
;
1735 #define _C2NCH0 0x01
1736 #define _C2NCH1 0x02
1737 #define _C2PCH0 0x10
1738 #define _C2PCH1 0x20
1739 #define _C2INTN 0x40
1740 #define _C2INTP 0x80
1742 //==============================================================================
1745 //==============================================================================
1748 extern __at(0x0115) __sfr CMOUT
;
1752 unsigned MC1OUT
: 1;
1753 unsigned MC2OUT
: 1;
1762 extern __at(0x0115) volatile __CMOUTbits_t CMOUTbits
;
1764 #define _MC1OUT 0x01
1765 #define _MC2OUT 0x02
1767 //==============================================================================
1770 //==============================================================================
1773 extern __at(0x0116) __sfr BORCON
;
1777 unsigned BORRDY
: 1;
1784 unsigned SBOREN
: 1;
1787 extern __at(0x0116) volatile __BORCONbits_t BORCONbits
;
1789 #define _BORRDY 0x01
1790 #define _SBOREN 0x80
1792 //==============================================================================
1795 //==============================================================================
1798 extern __at(0x0117) __sfr FVRCON
;
1804 unsigned ADFVR0
: 1;
1805 unsigned ADFVR1
: 1;
1806 unsigned CDAFVR0
: 1;
1807 unsigned CDAFVR1
: 1;
1810 unsigned FVRRDY
: 1;
1823 unsigned CDAFVR
: 2;
1828 extern __at(0x0117) volatile __FVRCONbits_t FVRCONbits
;
1830 #define _ADFVR0 0x01
1831 #define _ADFVR1 0x02
1832 #define _CDAFVR0 0x04
1833 #define _CDAFVR1 0x08
1836 #define _FVRRDY 0x40
1839 //==============================================================================
1842 //==============================================================================
1845 extern __at(0x0118) __sfr DACCON0
;
1851 unsigned DACNSS
: 1;
1853 unsigned DACPSS0
: 1;
1854 unsigned DACPSS1
: 1;
1857 unsigned DACLPS
: 1;
1864 unsigned DACPSS
: 2;
1869 extern __at(0x0118) volatile __DACCON0bits_t DACCON0bits
;
1871 #define _DACNSS 0x01
1872 #define _DACPSS0 0x04
1873 #define _DACPSS1 0x08
1875 #define _DACLPS 0x40
1878 //==============================================================================
1881 //==============================================================================
1884 extern __at(0x0119) __sfr DACCON1
;
1907 extern __at(0x0119) volatile __DACCON1bits_t DACCON1bits
;
1915 //==============================================================================
1918 //==============================================================================
1921 extern __at(0x011A) __sfr SRCON0
;
1929 unsigned SRNQEN
: 1;
1931 unsigned SRCLK0
: 1;
1932 unsigned SRCLK1
: 1;
1933 unsigned SRCLK2
: 1;
1945 extern __at(0x011A) volatile __SRCON0bits_t SRCON0bits
;
1949 #define _SRNQEN 0x04
1951 #define _SRCLK0 0x10
1952 #define _SRCLK1 0x20
1953 #define _SRCLK2 0x40
1956 //==============================================================================
1959 //==============================================================================
1962 extern __at(0x011B) __sfr SRCON1
;
1966 unsigned SRRC1E
: 1;
1967 unsigned SRRC2E
: 1;
1968 unsigned SRRCKE
: 1;
1970 unsigned SRSC1E
: 1;
1971 unsigned SRSC2E
: 1;
1972 unsigned SRSCKE
: 1;
1976 extern __at(0x011B) volatile __SRCON1bits_t SRCON1bits
;
1978 #define _SRRC1E 0x01
1979 #define _SRRC2E 0x02
1980 #define _SRRCKE 0x04
1982 #define _SRSC1E 0x10
1983 #define _SRSC2E 0x20
1984 #define _SRSCKE 0x40
1987 //==============================================================================
1990 //==============================================================================
1993 extern __at(0x011D) __sfr APFCON
;
1997 unsigned CCP2SEL
: 1;
1999 unsigned C2OUTSEL
: 1;
2000 unsigned SRNQSEL
: 1;
2001 unsigned P2BSEL
: 1;
2002 unsigned T1GSEL
: 1;
2003 unsigned CCP3SEL
: 1;
2007 extern __at(0x011D) volatile __APFCONbits_t APFCONbits
;
2009 #define _CCP2SEL 0x01
2011 #define _C2OUTSEL 0x04
2012 #define _SRNQSEL 0x08
2013 #define _P2BSEL 0x10
2014 #define _T1GSEL 0x20
2015 #define _CCP3SEL 0x40
2017 //==============================================================================
2020 //==============================================================================
2023 extern __at(0x018C) __sfr ANSELA
;
2046 extern __at(0x018C) volatile __ANSELAbits_t ANSELAbits
;
2055 //==============================================================================
2058 //==============================================================================
2061 extern __at(0x018D) __sfr ANSELB
;
2084 extern __at(0x018D) volatile __ANSELBbits_t ANSELBbits
;
2093 //==============================================================================
2096 //==============================================================================
2099 extern __at(0x018F) __sfr ANSELD
;
2113 extern __at(0x018F) volatile __ANSELDbits_t ANSELDbits
;
2124 //==============================================================================
2127 //==============================================================================
2130 extern __at(0x0190) __sfr ANSELE
;
2153 extern __at(0x0190) volatile __ANSELEbits_t ANSELEbits
;
2159 //==============================================================================
2161 extern __at(0x0191) __sfr EEADR
;
2162 extern __at(0x0191) __sfr EEADRL
;
2163 extern __at(0x0192) __sfr EEADRH
;
2164 extern __at(0x0193) __sfr EEDAT
;
2165 extern __at(0x0193) __sfr EEDATL
;
2166 extern __at(0x0194) __sfr EEDATH
;
2168 //==============================================================================
2171 extern __at(0x0195) __sfr EECON1
;
2185 extern __at(0x0195) volatile __EECON1bits_t EECON1bits
;
2196 //==============================================================================
2198 extern __at(0x0196) __sfr EECON2
;
2199 extern __at(0x0199) __sfr RCREG
;
2200 extern __at(0x019A) __sfr TXREG
;
2201 extern __at(0x019B) __sfr SP1BRG
;
2202 extern __at(0x019B) __sfr SP1BRGL
;
2203 extern __at(0x019B) __sfr SPBRG
;
2204 extern __at(0x019B) __sfr SPBRGL
;
2205 extern __at(0x019C) __sfr SP1BRGH
;
2206 extern __at(0x019C) __sfr SPBRGH
;
2208 //==============================================================================
2211 extern __at(0x019D) __sfr RCSTA
;
2225 extern __at(0x019D) volatile __RCSTAbits_t RCSTAbits
;
2236 //==============================================================================
2239 //==============================================================================
2242 extern __at(0x019E) __sfr TXSTA
;
2256 extern __at(0x019E) volatile __TXSTAbits_t TXSTAbits
;
2267 //==============================================================================
2270 //==============================================================================
2273 extern __at(0x019F) __sfr BAUDCON
;
2284 unsigned ABDOVF
: 1;
2287 extern __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits
;
2294 #define _ABDOVF 0x80
2296 //==============================================================================
2299 //==============================================================================
2302 extern __at(0x020D) __sfr WPUB
;
2316 extern __at(0x020D) volatile __WPUBbits_t WPUBbits
;
2327 //==============================================================================
2330 //==============================================================================
2333 extern __at(0x0210) __sfr WPUE
;
2347 extern __at(0x0210) volatile __WPUEbits_t WPUEbits
;
2351 //==============================================================================
2353 extern __at(0x0211) __sfr SSPBUF
;
2354 extern __at(0x0212) __sfr SSPADD
;
2355 extern __at(0x0213) __sfr SSPMSK
;
2357 //==============================================================================
2360 extern __at(0x0214) __sfr SSPSTAT
;
2366 unsigned R_NOT_W
: 1;
2369 unsigned D_NOT_A
: 1;
2374 extern __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits
;
2378 #define _R_NOT_W 0x04
2381 #define _D_NOT_A 0x20
2385 //==============================================================================
2388 //==============================================================================
2391 extern __at(0x0215) __sfr SSPCON
;
2414 extern __at(0x0215) volatile __SSPCONbits_t SSPCONbits
;
2425 //==============================================================================
2428 //==============================================================================
2431 extern __at(0x0215) __sfr SSPCON1
;
2454 extern __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits
;
2456 #define _SSPCON1_SSPM0 0x01
2457 #define _SSPCON1_SSPM1 0x02
2458 #define _SSPCON1_SSPM2 0x04
2459 #define _SSPCON1_SSPM3 0x08
2460 #define _SSPCON1_CKP 0x10
2461 #define _SSPCON1_SSPEN 0x20
2462 #define _SSPCON1_SSPOV 0x40
2463 #define _SSPCON1_WCOL 0x80
2465 //==============================================================================
2468 //==============================================================================
2471 extern __at(0x0216) __sfr SSPCON2
;
2481 unsigned ACKSTAT
: 1;
2485 extern __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits
;
2493 #define _ACKSTAT 0x40
2496 //==============================================================================
2499 //==============================================================================
2502 extern __at(0x0217) __sfr SSPCON3
;
2513 unsigned ACKTIM
: 1;
2516 extern __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits
;
2525 #define _ACKTIM 0x80
2527 //==============================================================================
2529 extern __at(0x0291) __sfr CCPR1
;
2530 extern __at(0x0291) __sfr CCPR1L
;
2531 extern __at(0x0292) __sfr CCPR1H
;
2533 //==============================================================================
2536 extern __at(0x0293) __sfr CCP1CON
;
2542 unsigned CCP1M0
: 1;
2543 unsigned CCP1M1
: 1;
2544 unsigned CCP1M2
: 1;
2545 unsigned CCP1M3
: 1;
2572 extern __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits
;
2574 #define _CCP1M0 0x01
2575 #define _CCP1M1 0x02
2576 #define _CCP1M2 0x04
2577 #define _CCP1M3 0x08
2583 //==============================================================================
2586 //==============================================================================
2589 extern __at(0x0294) __sfr PWM1CON
;
2602 unsigned P1RSEN
: 1;
2612 extern __at(0x0294) volatile __PWM1CONbits_t PWM1CONbits
;
2621 #define _P1RSEN 0x80
2623 //==============================================================================
2626 //==============================================================================
2629 extern __at(0x0295) __sfr CCP1AS
;
2635 unsigned PSS1BD0
: 1;
2636 unsigned PSS1BD1
: 1;
2637 unsigned PSS1AC0
: 1;
2638 unsigned PSS1AC1
: 1;
2639 unsigned CCP1AS0
: 1;
2640 unsigned CCP1AS1
: 1;
2641 unsigned CCP1AS2
: 1;
2642 unsigned CCP1ASE
: 1;
2647 unsigned PSS1BD
: 2;
2654 unsigned PSS1AC
: 2;
2661 unsigned CCP1AS
: 3;
2666 extern __at(0x0295) volatile __CCP1ASbits_t CCP1ASbits
;
2668 #define _PSS1BD0 0x01
2669 #define _PSS1BD1 0x02
2670 #define _PSS1AC0 0x04
2671 #define _PSS1AC1 0x08
2672 #define _CCP1AS0 0x10
2673 #define _CCP1AS1 0x20
2674 #define _CCP1AS2 0x40
2675 #define _CCP1ASE 0x80
2677 //==============================================================================
2680 //==============================================================================
2683 extern __at(0x0295) __sfr ECCP1AS
;
2689 unsigned PSS1BD0
: 1;
2690 unsigned PSS1BD1
: 1;
2691 unsigned PSS1AC0
: 1;
2692 unsigned PSS1AC1
: 1;
2693 unsigned CCP1AS0
: 1;
2694 unsigned CCP1AS1
: 1;
2695 unsigned CCP1AS2
: 1;
2696 unsigned CCP1ASE
: 1;
2701 unsigned PSS1BD
: 2;
2708 unsigned PSS1AC
: 2;
2715 unsigned CCP1AS
: 3;
2720 extern __at(0x0295) volatile __ECCP1ASbits_t ECCP1ASbits
;
2722 #define _ECCP1AS_PSS1BD0 0x01
2723 #define _ECCP1AS_PSS1BD1 0x02
2724 #define _ECCP1AS_PSS1AC0 0x04
2725 #define _ECCP1AS_PSS1AC1 0x08
2726 #define _ECCP1AS_CCP1AS0 0x10
2727 #define _ECCP1AS_CCP1AS1 0x20
2728 #define _ECCP1AS_CCP1AS2 0x40
2729 #define _ECCP1AS_CCP1ASE 0x80
2731 //==============================================================================
2734 //==============================================================================
2737 extern __at(0x0296) __sfr PSTR1CON
;
2745 unsigned STR1SYNC
: 1;
2751 extern __at(0x0296) volatile __PSTR1CONbits_t PSTR1CONbits
;
2757 #define _STR1SYNC 0x10
2759 //==============================================================================
2761 extern __at(0x0298) __sfr CCPR2
;
2762 extern __at(0x0298) __sfr CCPR2L
;
2763 extern __at(0x0299) __sfr CCPR2H
;
2765 //==============================================================================
2768 extern __at(0x029A) __sfr CCP2CON
;
2774 unsigned CCP2M0
: 1;
2775 unsigned CCP2M1
: 1;
2776 unsigned CCP2M2
: 1;
2777 unsigned CCP2M3
: 1;
2804 extern __at(0x029A) volatile __CCP2CONbits_t CCP2CONbits
;
2806 #define _CCP2M0 0x01
2807 #define _CCP2M1 0x02
2808 #define _CCP2M2 0x04
2809 #define _CCP2M3 0x08
2815 //==============================================================================
2818 //==============================================================================
2821 extern __at(0x029B) __sfr PWM2CON
;
2834 unsigned P2RSEN
: 1;
2844 extern __at(0x029B) volatile __PWM2CONbits_t PWM2CONbits
;
2853 #define _P2RSEN 0x80
2855 //==============================================================================
2858 //==============================================================================
2861 extern __at(0x029C) __sfr CCP2AS
;
2867 unsigned PSS2BD0
: 1;
2868 unsigned PSS2BD1
: 1;
2869 unsigned PSS2AC0
: 1;
2870 unsigned PSS2AC1
: 1;
2871 unsigned CCP2AS0
: 1;
2872 unsigned CCP2AS1
: 1;
2873 unsigned CCP2AS2
: 1;
2874 unsigned CCP2ASE
: 1;
2879 unsigned PSS2BD
: 2;
2886 unsigned PSS2AC
: 2;
2893 unsigned CCP2AS
: 3;
2898 extern __at(0x029C) volatile __CCP2ASbits_t CCP2ASbits
;
2900 #define _PSS2BD0 0x01
2901 #define _PSS2BD1 0x02
2902 #define _PSS2AC0 0x04
2903 #define _PSS2AC1 0x08
2904 #define _CCP2AS0 0x10
2905 #define _CCP2AS1 0x20
2906 #define _CCP2AS2 0x40
2907 #define _CCP2ASE 0x80
2909 //==============================================================================
2912 //==============================================================================
2915 extern __at(0x029C) __sfr ECCP2AS
;
2921 unsigned PSS2BD0
: 1;
2922 unsigned PSS2BD1
: 1;
2923 unsigned PSS2AC0
: 1;
2924 unsigned PSS2AC1
: 1;
2925 unsigned CCP2AS0
: 1;
2926 unsigned CCP2AS1
: 1;
2927 unsigned CCP2AS2
: 1;
2928 unsigned CCP2ASE
: 1;
2933 unsigned PSS2BD
: 2;
2940 unsigned PSS2AC
: 2;
2947 unsigned CCP2AS
: 3;
2952 extern __at(0x029C) volatile __ECCP2ASbits_t ECCP2ASbits
;
2954 #define _ECCP2AS_PSS2BD0 0x01
2955 #define _ECCP2AS_PSS2BD1 0x02
2956 #define _ECCP2AS_PSS2AC0 0x04
2957 #define _ECCP2AS_PSS2AC1 0x08
2958 #define _ECCP2AS_CCP2AS0 0x10
2959 #define _ECCP2AS_CCP2AS1 0x20
2960 #define _ECCP2AS_CCP2AS2 0x40
2961 #define _ECCP2AS_CCP2ASE 0x80
2963 //==============================================================================
2966 //==============================================================================
2969 extern __at(0x029D) __sfr PSTR2CON
;
2977 unsigned STR2SYNC
: 1;
2983 extern __at(0x029D) volatile __PSTR2CONbits_t PSTR2CONbits
;
2989 #define _STR2SYNC 0x10
2991 //==============================================================================
2994 //==============================================================================
2997 extern __at(0x029E) __sfr CCPTMRS0
;
3003 unsigned C1TSEL0
: 1;
3004 unsigned C1TSEL1
: 1;
3005 unsigned C2TSEL0
: 1;
3006 unsigned C2TSEL1
: 1;
3007 unsigned C3TSEL0
: 1;
3008 unsigned C3TSEL1
: 1;
3009 unsigned C4TSEL0
: 1;
3010 unsigned C4TSEL1
: 1;
3015 unsigned C1TSEL
: 2;
3022 unsigned C2TSEL
: 2;
3029 unsigned C3TSEL
: 2;
3036 unsigned C4TSEL
: 2;
3040 extern __at(0x029E) volatile __CCPTMRS0bits_t CCPTMRS0bits
;
3042 #define _C1TSEL0 0x01
3043 #define _C1TSEL1 0x02
3044 #define _C2TSEL0 0x04
3045 #define _C2TSEL1 0x08
3046 #define _C3TSEL0 0x10
3047 #define _C3TSEL1 0x20
3048 #define _C4TSEL0 0x40
3049 #define _C4TSEL1 0x80
3051 //==============================================================================
3054 //==============================================================================
3057 extern __at(0x029F) __sfr CCPTMRS1
;
3063 unsigned C5TSEL0
: 1;
3064 unsigned C5TSEL1
: 1;
3075 unsigned C5TSEL
: 2;
3080 extern __at(0x029F) volatile __CCPTMRS1bits_t CCPTMRS1bits
;
3082 #define _C5TSEL0 0x01
3083 #define _C5TSEL1 0x02
3085 //==============================================================================
3087 extern __at(0x0311) __sfr CCPR3
;
3088 extern __at(0x0311) __sfr CCPR3L
;
3089 extern __at(0x0312) __sfr CCPR3H
;
3091 //==============================================================================
3094 extern __at(0x0313) __sfr CCP3CON
;
3100 unsigned CCP3M0
: 1;
3101 unsigned CCP3M1
: 1;
3102 unsigned CCP3M2
: 1;
3103 unsigned CCP3M3
: 1;
3130 extern __at(0x0313) volatile __CCP3CONbits_t CCP3CONbits
;
3132 #define _CCP3M0 0x01
3133 #define _CCP3M1 0x02
3134 #define _CCP3M2 0x04
3135 #define _CCP3M3 0x08
3141 //==============================================================================
3144 //==============================================================================
3147 extern __at(0x0314) __sfr PWM3CON
;
3160 unsigned P3RSEN
: 1;
3170 extern __at(0x0314) volatile __PWM3CONbits_t PWM3CONbits
;
3179 #define _P3RSEN 0x80
3181 //==============================================================================
3184 //==============================================================================
3187 extern __at(0x0315) __sfr CCP3AS
;
3193 unsigned PSS3BD0
: 1;
3194 unsigned PSS3BD1
: 1;
3195 unsigned PSS3AC0
: 1;
3196 unsigned PSS3AC1
: 1;
3197 unsigned CCP3AS0
: 1;
3198 unsigned CCP3AS1
: 1;
3199 unsigned CCP3AS2
: 1;
3200 unsigned CCP3ASE
: 1;
3205 unsigned PSS3BD
: 2;
3212 unsigned PSS3AC
: 2;
3219 unsigned CCP3AS
: 3;
3224 extern __at(0x0315) volatile __CCP3ASbits_t CCP3ASbits
;
3226 #define _PSS3BD0 0x01
3227 #define _PSS3BD1 0x02
3228 #define _PSS3AC0 0x04
3229 #define _PSS3AC1 0x08
3230 #define _CCP3AS0 0x10
3231 #define _CCP3AS1 0x20
3232 #define _CCP3AS2 0x40
3233 #define _CCP3ASE 0x80
3235 //==============================================================================
3238 //==============================================================================
3241 extern __at(0x0315) __sfr ECCP3AS
;
3247 unsigned PSS3BD0
: 1;
3248 unsigned PSS3BD1
: 1;
3249 unsigned PSS3AC0
: 1;
3250 unsigned PSS3AC1
: 1;
3251 unsigned CCP3AS0
: 1;
3252 unsigned CCP3AS1
: 1;
3253 unsigned CCP3AS2
: 1;
3254 unsigned CCP3ASE
: 1;
3259 unsigned PSS3BD
: 2;
3266 unsigned PSS3AC
: 2;
3273 unsigned CCP3AS
: 3;
3278 extern __at(0x0315) volatile __ECCP3ASbits_t ECCP3ASbits
;
3280 #define _ECCP3AS_PSS3BD0 0x01
3281 #define _ECCP3AS_PSS3BD1 0x02
3282 #define _ECCP3AS_PSS3AC0 0x04
3283 #define _ECCP3AS_PSS3AC1 0x08
3284 #define _ECCP3AS_CCP3AS0 0x10
3285 #define _ECCP3AS_CCP3AS1 0x20
3286 #define _ECCP3AS_CCP3AS2 0x40
3287 #define _ECCP3AS_CCP3ASE 0x80
3289 //==============================================================================
3292 //==============================================================================
3295 extern __at(0x0316) __sfr PSTR3CON
;
3303 unsigned STR3SYNC
: 1;
3309 extern __at(0x0316) volatile __PSTR3CONbits_t PSTR3CONbits
;
3315 #define _STR3SYNC 0x10
3317 //==============================================================================
3319 extern __at(0x0318) __sfr CCPR4
;
3320 extern __at(0x0318) __sfr CCPR4L
;
3321 extern __at(0x0319) __sfr CCPR4H
;
3323 //==============================================================================
3326 extern __at(0x031A) __sfr CCP4CON
;
3332 unsigned CCP4M0
: 1;
3333 unsigned CCP4M1
: 1;
3334 unsigned CCP4M2
: 1;
3335 unsigned CCP4M3
: 1;
3356 extern __at(0x031A) volatile __CCP4CONbits_t CCP4CONbits
;
3358 #define _CCP4M0 0x01
3359 #define _CCP4M1 0x02
3360 #define _CCP4M2 0x04
3361 #define _CCP4M3 0x08
3365 //==============================================================================
3367 extern __at(0x031C) __sfr CCPR5
;
3368 extern __at(0x031C) __sfr CCPR5L
;
3369 extern __at(0x031D) __sfr CCPR5H
;
3371 //==============================================================================
3374 extern __at(0x031E) __sfr CCP5CON
;
3380 unsigned CCP5M0
: 1;
3381 unsigned CCP5M1
: 1;
3382 unsigned CCP5M2
: 1;
3383 unsigned CCP5M3
: 1;
3404 extern __at(0x031E) volatile __CCP5CONbits_t CCP5CONbits
;
3406 #define _CCP5M0 0x01
3407 #define _CCP5M1 0x02
3408 #define _CCP5M2 0x04
3409 #define _CCP5M3 0x08
3413 //==============================================================================
3416 //==============================================================================
3419 extern __at(0x0394) __sfr IOCBP
;
3423 unsigned IOCBP0
: 1;
3424 unsigned IOCBP1
: 1;
3425 unsigned IOCBP2
: 1;
3426 unsigned IOCBP3
: 1;
3427 unsigned IOCBP4
: 1;
3428 unsigned IOCBP5
: 1;
3429 unsigned IOCBP6
: 1;
3430 unsigned IOCBP7
: 1;
3433 extern __at(0x0394) volatile __IOCBPbits_t IOCBPbits
;
3435 #define _IOCBP0 0x01
3436 #define _IOCBP1 0x02
3437 #define _IOCBP2 0x04
3438 #define _IOCBP3 0x08
3439 #define _IOCBP4 0x10
3440 #define _IOCBP5 0x20
3441 #define _IOCBP6 0x40
3442 #define _IOCBP7 0x80
3444 //==============================================================================
3447 //==============================================================================
3450 extern __at(0x0395) __sfr IOCBN
;
3454 unsigned IOCBN0
: 1;
3455 unsigned IOCBN1
: 1;
3456 unsigned IOCBN2
: 1;
3457 unsigned IOCBN3
: 1;
3458 unsigned IOCBN4
: 1;
3459 unsigned IOCBN5
: 1;
3460 unsigned IOCBN6
: 1;
3461 unsigned IOCBN7
: 1;
3464 extern __at(0x0395) volatile __IOCBNbits_t IOCBNbits
;
3466 #define _IOCBN0 0x01
3467 #define _IOCBN1 0x02
3468 #define _IOCBN2 0x04
3469 #define _IOCBN3 0x08
3470 #define _IOCBN4 0x10
3471 #define _IOCBN5 0x20
3472 #define _IOCBN6 0x40
3473 #define _IOCBN7 0x80
3475 //==============================================================================
3478 //==============================================================================
3481 extern __at(0x0396) __sfr IOCBF
;
3485 unsigned IOCBF0
: 1;
3486 unsigned IOCBF1
: 1;
3487 unsigned IOCBF2
: 1;
3488 unsigned IOCBF3
: 1;
3489 unsigned IOCBF4
: 1;
3490 unsigned IOCBF5
: 1;
3491 unsigned IOCBF6
: 1;
3492 unsigned IOCBF7
: 1;
3495 extern __at(0x0396) volatile __IOCBFbits_t IOCBFbits
;
3497 #define _IOCBF0 0x01
3498 #define _IOCBF1 0x02
3499 #define _IOCBF2 0x04
3500 #define _IOCBF3 0x08
3501 #define _IOCBF4 0x10
3502 #define _IOCBF5 0x20
3503 #define _IOCBF6 0x40
3504 #define _IOCBF7 0x80
3506 //==============================================================================
3508 extern __at(0x0415) __sfr TMR4
;
3509 extern __at(0x0416) __sfr PR4
;
3511 //==============================================================================
3514 extern __at(0x0417) __sfr T4CON
;
3520 unsigned T4CKPS0
: 1;
3521 unsigned T4CKPS1
: 1;
3522 unsigned TMR4ON
: 1;
3523 unsigned T4OUTPS0
: 1;
3524 unsigned T4OUTPS1
: 1;
3525 unsigned T4OUTPS2
: 1;
3526 unsigned T4OUTPS3
: 1;
3532 unsigned T4CKPS
: 2;
3539 unsigned T4OUTPS
: 4;
3544 extern __at(0x0417) volatile __T4CONbits_t T4CONbits
;
3546 #define _T4CKPS0 0x01
3547 #define _T4CKPS1 0x02
3548 #define _TMR4ON 0x04
3549 #define _T4OUTPS0 0x08
3550 #define _T4OUTPS1 0x10
3551 #define _T4OUTPS2 0x20
3552 #define _T4OUTPS3 0x40
3554 //==============================================================================
3556 extern __at(0x041C) __sfr TMR6
;
3557 extern __at(0x041D) __sfr PR6
;
3559 //==============================================================================
3562 extern __at(0x041E) __sfr T6CON
;
3568 unsigned T6CKPS0
: 1;
3569 unsigned T6CKPS1
: 1;
3570 unsigned TMR6ON
: 1;
3571 unsigned T6OUTPS0
: 1;
3572 unsigned T6OUTPS1
: 1;
3573 unsigned T6OUTPS2
: 1;
3574 unsigned T6OUTPS3
: 1;
3580 unsigned T6CKPS
: 2;
3587 unsigned T6OUTPS
: 4;
3592 extern __at(0x041E) volatile __T6CONbits_t T6CONbits
;
3594 #define _T6CKPS0 0x01
3595 #define _T6CKPS1 0x02
3596 #define _TMR6ON 0x04
3597 #define _T6OUTPS0 0x08
3598 #define _T6OUTPS1 0x10
3599 #define _T6OUTPS2 0x20
3600 #define _T6OUTPS3 0x40
3602 //==============================================================================
3605 //==============================================================================
3608 extern __at(0x0791) __sfr LCDCON
;
3638 extern __at(0x0791) volatile __LCDCONbits_t LCDCONbits
;
3648 //==============================================================================
3651 //==============================================================================
3654 extern __at(0x0792) __sfr LCDPS
;
3666 unsigned BIASMD
: 1;
3677 extern __at(0x0792) volatile __LCDPSbits_t LCDPSbits
;
3685 #define _BIASMD 0x40
3688 //==============================================================================
3691 //==============================================================================
3694 extern __at(0x0793) __sfr LCDREF
;
3699 unsigned VLCD1PE
: 1;
3700 unsigned VLCD2PE
: 1;
3701 unsigned VLCD3PE
: 1;
3703 unsigned LCDIRI
: 1;
3704 unsigned LCDIRS
: 1;
3705 unsigned LCDIRE
: 1;
3708 extern __at(0x0793) volatile __LCDREFbits_t LCDREFbits
;
3710 #define _VLCD1PE 0x02
3711 #define _VLCD2PE 0x04
3712 #define _VLCD3PE 0x08
3713 #define _LCDIRI 0x20
3714 #define _LCDIRS 0x40
3715 #define _LCDIRE 0x80
3717 //==============================================================================
3720 //==============================================================================
3723 extern __at(0x0794) __sfr LCDCST
;
3729 unsigned LCDCST0
: 1;
3730 unsigned LCDCST1
: 1;
3731 unsigned LCDCST2
: 1;
3741 unsigned LCDCST
: 3;
3746 extern __at(0x0794) volatile __LCDCSTbits_t LCDCSTbits
;
3748 #define _LCDCST0 0x01
3749 #define _LCDCST1 0x02
3750 #define _LCDCST2 0x04
3752 //==============================================================================
3755 //==============================================================================
3758 extern __at(0x0795) __sfr LCDRL
;
3764 unsigned LRLAT0
: 1;
3765 unsigned LRLAT1
: 1;
3766 unsigned LRLAT2
: 1;
3768 unsigned LRLBP0
: 1;
3769 unsigned LRLBP1
: 1;
3770 unsigned LRLAP0
: 1;
3771 unsigned LRLAP1
: 1;
3794 extern __at(0x0795) volatile __LCDRLbits_t LCDRLbits
;
3796 #define _LRLAT0 0x01
3797 #define _LRLAT1 0x02
3798 #define _LRLAT2 0x04
3799 #define _LRLBP0 0x10
3800 #define _LRLBP1 0x20
3801 #define _LRLAP0 0x40
3802 #define _LRLAP1 0x80
3804 //==============================================================================
3807 //==============================================================================
3810 extern __at(0x0798) __sfr LCDSE0
;
3824 extern __at(0x0798) volatile __LCDSE0bits_t LCDSE0bits
;
3835 //==============================================================================
3838 //==============================================================================
3841 extern __at(0x0799) __sfr LCDSE1
;
3855 extern __at(0x0799) volatile __LCDSE1bits_t LCDSE1bits
;
3866 //==============================================================================
3869 //==============================================================================
3872 extern __at(0x079A) __sfr LCDSE2
;
3886 extern __at(0x079A) volatile __LCDSE2bits_t LCDSE2bits
;
3897 //==============================================================================
3900 //==============================================================================
3903 extern __at(0x07A0) __sfr LCDDATA0
;
3907 unsigned SEG0COM0
: 1;
3908 unsigned SEG1COM0
: 1;
3909 unsigned SEG2COM0
: 1;
3910 unsigned SEG3COM0
: 1;
3911 unsigned SEG4COM0
: 1;
3912 unsigned SEG5COM0
: 1;
3913 unsigned SEG6COM0
: 1;
3914 unsigned SEG7COM0
: 1;
3917 extern __at(0x07A0) volatile __LCDDATA0bits_t LCDDATA0bits
;
3919 #define _SEG0COM0 0x01
3920 #define _SEG1COM0 0x02
3921 #define _SEG2COM0 0x04
3922 #define _SEG3COM0 0x08
3923 #define _SEG4COM0 0x10
3924 #define _SEG5COM0 0x20
3925 #define _SEG6COM0 0x40
3926 #define _SEG7COM0 0x80
3928 //==============================================================================
3931 //==============================================================================
3934 extern __at(0x07A1) __sfr LCDDATA1
;
3938 unsigned SEG8COM0
: 1;
3939 unsigned SEG9COM0
: 1;
3940 unsigned SEG10COM0
: 1;
3941 unsigned SEG11COM0
: 1;
3942 unsigned SEG12COM0
: 1;
3943 unsigned SEG13COM0
: 1;
3944 unsigned SEG14COM0
: 1;
3945 unsigned SEG15COM0
: 1;
3948 extern __at(0x07A1) volatile __LCDDATA1bits_t LCDDATA1bits
;
3950 #define _SEG8COM0 0x01
3951 #define _SEG9COM0 0x02
3952 #define _SEG10COM0 0x04
3953 #define _SEG11COM0 0x08
3954 #define _SEG12COM0 0x10
3955 #define _SEG13COM0 0x20
3956 #define _SEG14COM0 0x40
3957 #define _SEG15COM0 0x80
3959 //==============================================================================
3962 //==============================================================================
3965 extern __at(0x07A2) __sfr LCDDATA2
;
3969 unsigned SEG16COM0
: 1;
3970 unsigned SEG17COM0
: 1;
3971 unsigned SEG18COM0
: 1;
3972 unsigned SEG19COM0
: 1;
3973 unsigned SEG20COM0
: 1;
3974 unsigned SEG21COM0
: 1;
3975 unsigned SEG22COM0
: 1;
3976 unsigned SEG23COM0
: 1;
3979 extern __at(0x07A2) volatile __LCDDATA2bits_t LCDDATA2bits
;
3981 #define _SEG16COM0 0x01
3982 #define _SEG17COM0 0x02
3983 #define _SEG18COM0 0x04
3984 #define _SEG19COM0 0x08
3985 #define _SEG20COM0 0x10
3986 #define _SEG21COM0 0x20
3987 #define _SEG22COM0 0x40
3988 #define _SEG23COM0 0x80
3990 //==============================================================================
3993 //==============================================================================
3996 extern __at(0x07A3) __sfr LCDDATA3
;
4000 unsigned SEG0COM1
: 1;
4001 unsigned SEG1COM1
: 1;
4002 unsigned SEG2COM1
: 1;
4003 unsigned SEG3COM1
: 1;
4004 unsigned SEG4COM1
: 1;
4005 unsigned SEG5COM1
: 1;
4006 unsigned SEG6COM1
: 1;
4007 unsigned SEG7COM1
: 1;
4010 extern __at(0x07A3) volatile __LCDDATA3bits_t LCDDATA3bits
;
4012 #define _SEG0COM1 0x01
4013 #define _SEG1COM1 0x02
4014 #define _SEG2COM1 0x04
4015 #define _SEG3COM1 0x08
4016 #define _SEG4COM1 0x10
4017 #define _SEG5COM1 0x20
4018 #define _SEG6COM1 0x40
4019 #define _SEG7COM1 0x80
4021 //==============================================================================
4024 //==============================================================================
4027 extern __at(0x07A4) __sfr LCDDATA4
;
4031 unsigned SEG8COM1
: 1;
4032 unsigned SEG9COM1
: 1;
4033 unsigned SEG10COM1
: 1;
4034 unsigned SEG11COM1
: 1;
4035 unsigned SEG12COM1
: 1;
4036 unsigned SEG13COM1
: 1;
4037 unsigned SEG14COM1
: 1;
4038 unsigned SEG15COM1
: 1;
4041 extern __at(0x07A4) volatile __LCDDATA4bits_t LCDDATA4bits
;
4043 #define _SEG8COM1 0x01
4044 #define _SEG9COM1 0x02
4045 #define _SEG10COM1 0x04
4046 #define _SEG11COM1 0x08
4047 #define _SEG12COM1 0x10
4048 #define _SEG13COM1 0x20
4049 #define _SEG14COM1 0x40
4050 #define _SEG15COM1 0x80
4052 //==============================================================================
4055 //==============================================================================
4058 extern __at(0x07A5) __sfr LCDDATA5
;
4062 unsigned SEG16COM1
: 1;
4063 unsigned SEG17COM1
: 1;
4064 unsigned SEG18COM1
: 1;
4065 unsigned SEG19COM1
: 1;
4066 unsigned SEG20COM1
: 1;
4067 unsigned SEG21COM1
: 1;
4068 unsigned SEG22COM1
: 1;
4069 unsigned SEG23COM1
: 1;
4072 extern __at(0x07A5) volatile __LCDDATA5bits_t LCDDATA5bits
;
4074 #define _SEG16COM1 0x01
4075 #define _SEG17COM1 0x02
4076 #define _SEG18COM1 0x04
4077 #define _SEG19COM1 0x08
4078 #define _SEG20COM1 0x10
4079 #define _SEG21COM1 0x20
4080 #define _SEG22COM1 0x40
4081 #define _SEG23COM1 0x80
4083 //==============================================================================
4086 //==============================================================================
4089 extern __at(0x07A6) __sfr LCDDATA6
;
4093 unsigned SEG0COM2
: 1;
4094 unsigned SEG1COM2
: 1;
4095 unsigned SEG2COM2
: 1;
4096 unsigned SEG3COM2
: 1;
4097 unsigned SEG4COM2
: 1;
4098 unsigned SEG5COM2
: 1;
4099 unsigned SEG6COM2
: 1;
4100 unsigned SEG7COM2
: 1;
4103 extern __at(0x07A6) volatile __LCDDATA6bits_t LCDDATA6bits
;
4105 #define _SEG0COM2 0x01
4106 #define _SEG1COM2 0x02
4107 #define _SEG2COM2 0x04
4108 #define _SEG3COM2 0x08
4109 #define _SEG4COM2 0x10
4110 #define _SEG5COM2 0x20
4111 #define _SEG6COM2 0x40
4112 #define _SEG7COM2 0x80
4114 //==============================================================================
4117 //==============================================================================
4120 extern __at(0x07A7) __sfr LCDDATA7
;
4124 unsigned SEG8COM2
: 1;
4125 unsigned SEG9COM2
: 1;
4126 unsigned SEG10COM2
: 1;
4127 unsigned SEG11COM2
: 1;
4128 unsigned SEG12COM2
: 1;
4129 unsigned SEG13COM2
: 1;
4130 unsigned SEG14COM2
: 1;
4131 unsigned SEG15COM2
: 1;
4134 extern __at(0x07A7) volatile __LCDDATA7bits_t LCDDATA7bits
;
4136 #define _SEG8COM2 0x01
4137 #define _SEG9COM2 0x02
4138 #define _SEG10COM2 0x04
4139 #define _SEG11COM2 0x08
4140 #define _SEG12COM2 0x10
4141 #define _SEG13COM2 0x20
4142 #define _SEG14COM2 0x40
4143 #define _SEG15COM2 0x80
4145 //==============================================================================
4148 //==============================================================================
4151 extern __at(0x07A8) __sfr LCDDATA8
;
4155 unsigned SEG16COM2
: 1;
4156 unsigned SEG17COM2
: 1;
4157 unsigned SEG18COM2
: 1;
4158 unsigned SEG19COM2
: 1;
4159 unsigned SEG20COM2
: 1;
4160 unsigned SEG21COM2
: 1;
4161 unsigned SEG22COM2
: 1;
4162 unsigned SEG23COM2
: 1;
4165 extern __at(0x07A8) volatile __LCDDATA8bits_t LCDDATA8bits
;
4167 #define _SEG16COM2 0x01
4168 #define _SEG17COM2 0x02
4169 #define _SEG18COM2 0x04
4170 #define _SEG19COM2 0x08
4171 #define _SEG20COM2 0x10
4172 #define _SEG21COM2 0x20
4173 #define _SEG22COM2 0x40
4174 #define _SEG23COM2 0x80
4176 //==============================================================================
4179 //==============================================================================
4182 extern __at(0x07A9) __sfr LCDDATA9
;
4186 unsigned SEG0COM3
: 1;
4187 unsigned SEG1COM3
: 1;
4188 unsigned SEG2COM3
: 1;
4189 unsigned SEG3COM3
: 1;
4190 unsigned SEG4COM3
: 1;
4191 unsigned SEG5COM3
: 1;
4192 unsigned SEG6COM3
: 1;
4193 unsigned SEG7COM3
: 1;
4196 extern __at(0x07A9) volatile __LCDDATA9bits_t LCDDATA9bits
;
4198 #define _SEG0COM3 0x01
4199 #define _SEG1COM3 0x02
4200 #define _SEG2COM3 0x04
4201 #define _SEG3COM3 0x08
4202 #define _SEG4COM3 0x10
4203 #define _SEG5COM3 0x20
4204 #define _SEG6COM3 0x40
4205 #define _SEG7COM3 0x80
4207 //==============================================================================
4210 //==============================================================================
4213 extern __at(0x07AA) __sfr LCDDATA10
;
4217 unsigned SEG8COM3
: 1;
4218 unsigned SEG9COM3
: 1;
4219 unsigned SEG10COM3
: 1;
4220 unsigned SEG11COM3
: 1;
4221 unsigned SEG12COM3
: 1;
4222 unsigned SEG13COM3
: 1;
4223 unsigned SEG14COM3
: 1;
4224 unsigned SEG15COM3
: 1;
4225 } __LCDDATA10bits_t
;
4227 extern __at(0x07AA) volatile __LCDDATA10bits_t LCDDATA10bits
;
4229 #define _SEG8COM3 0x01
4230 #define _SEG9COM3 0x02
4231 #define _SEG10COM3 0x04
4232 #define _SEG11COM3 0x08
4233 #define _SEG12COM3 0x10
4234 #define _SEG13COM3 0x20
4235 #define _SEG14COM3 0x40
4236 #define _SEG15COM3 0x80
4238 //==============================================================================
4241 //==============================================================================
4244 extern __at(0x07AB) __sfr LCDDATA11
;
4248 unsigned SEG16COM3
: 1;
4249 unsigned SEG17COM3
: 1;
4250 unsigned SEG18COM3
: 1;
4251 unsigned SEG19COM3
: 1;
4252 unsigned SEG20COM3
: 1;
4253 unsigned SEG21COM3
: 1;
4254 unsigned SEG22COM3
: 1;
4255 unsigned SEG23COM3
: 1;
4256 } __LCDDATA11bits_t
;
4258 extern __at(0x07AB) volatile __LCDDATA11bits_t LCDDATA11bits
;
4260 #define _SEG16COM3 0x01
4261 #define _SEG17COM3 0x02
4262 #define _SEG18COM3 0x04
4263 #define _SEG19COM3 0x08
4264 #define _SEG20COM3 0x10
4265 #define _SEG21COM3 0x20
4266 #define _SEG22COM3 0x40
4267 #define _SEG23COM3 0x80
4269 //==============================================================================
4272 //==============================================================================
4275 extern __at(0x0FE4) __sfr STATUS_SHAD
;
4279 unsigned C_SHAD
: 1;
4280 unsigned DC_SHAD
: 1;
4281 unsigned Z_SHAD
: 1;
4287 } __STATUS_SHADbits_t
;
4289 extern __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits
;
4291 #define _C_SHAD 0x01
4292 #define _DC_SHAD 0x02
4293 #define _Z_SHAD 0x04
4295 //==============================================================================
4297 extern __at(0x0FE5) __sfr WREG_SHAD
;
4298 extern __at(0x0FE6) __sfr BSR_SHAD
;
4299 extern __at(0x0FE7) __sfr PCLATH_SHAD
;
4300 extern __at(0x0FE8) __sfr FSR0L_SHAD
;
4301 extern __at(0x0FE9) __sfr FSR0H_SHAD
;
4302 extern __at(0x0FEA) __sfr FSR1L_SHAD
;
4303 extern __at(0x0FEB) __sfr FSR1H_SHAD
;
4304 extern __at(0x0FED) __sfr STKPTR
;
4305 extern __at(0x0FEE) __sfr TOSL
;
4306 extern __at(0x0FEF) __sfr TOSH
;
4308 //==============================================================================
4310 // Configuration Bits
4312 //==============================================================================
4314 #define _CONFIG1 0x8007
4315 #define _CONFIG2 0x8008
4317 //----------------------------- CONFIG1 Options -------------------------------
4319 #define _FOSC_LP 0x3FF8 // LP Oscillator, Low-power crystal connected between OSC1 and OSC2 pins.
4320 #define _FOSC_XT 0x3FF9 // XT Oscillator, Crystal/resonator connected between OSC1 and OSC2 pins.
4321 #define _FOSC_HS 0x3FFA // HS Oscillator, High-speed crystal/resonator connected between OSC1 and OSC2 pins.
4322 #define _FOSC_EXTRC 0x3FFB // EXTRC oscillator: External RC circuit connected to CLKIN pin.
4323 #define _FOSC_INTOSC 0x3FFC // INTOSC oscillator: I/O function on CLKIN pin.
4324 #define _FOSC_ECL 0x3FFD // ECL, External Clock, Low Power Mode (0-0.5 MHz): device clock supplied to CLKIN pin.
4325 #define _FOSC_ECM 0x3FFE // ECM, External Clock, Medium Power Mode (0.5-4 MHz): device clock supplied to CLKIN pin.
4326 #define _FOSC_ECH 0x3FFF // ECH, External Clock, High Power Mode (4-32 MHz): device clock supplied to CLKIN pin.
4327 #define _WDTE_OFF 0x3FE7 // WDT disabled.
4328 #define _WDTE_SWDTEN 0x3FEF // WDT controlled by the SWDTEN bit in the WDTCON register.
4329 #define _WDTE_NSLEEP 0x3FF7 // WDT enabled while running and disabled in Sleep.
4330 #define _WDTE_ON 0x3FFF // WDT enabled.
4331 #define _PWRTE_ON 0x3FDF // PWRT enabled.
4332 #define _PWRTE_OFF 0x3FFF // PWRT disabled.
4333 #define _MCLRE_OFF 0x3FBF // MCLR/VPP pin function is digital input.
4334 #define _MCLRE_ON 0x3FFF // MCLR/VPP pin function is MCLR.
4335 #define _CP_ON 0x3F7F // Program memory code protection is enabled.
4336 #define _CP_OFF 0x3FFF // Program memory code protection is disabled.
4337 #define _CPD_ON 0x3EFF // Data memory code protection is enabled.
4338 #define _CPD_OFF 0x3FFF // Data memory code protection is disabled.
4339 #define _BOREN_OFF 0x39FF // Brown-out Reset disabled.
4340 #define _BOREN_SBODEN 0x3BFF // Brown-out Reset controlled by the SBOREN bit in the BORCON register.
4341 #define _BOREN_NSLEEP 0x3DFF // Brown-out Reset enabled while running and disabled in Sleep.
4342 #define _BOREN_ON 0x3FFF // Brown-out Reset enabled.
4343 #define _CLKOUTEN_ON 0x37FF // CLKOUT function is enabled on the CLKOUT pin.
4344 #define _CLKOUTEN_OFF 0x3FFF // CLKOUT function is disabled. I/O or oscillator function on the CLKOUT pin.
4345 #define _IESO_OFF 0x2FFF // Internal/External Switchover mode is disabled.
4346 #define _IESO_ON 0x3FFF // Internal/External Switchover mode is enabled.
4347 #define _FCMEN_OFF 0x1FFF // Fail-Safe Clock Monitor is disabled.
4348 #define _FCMEN_ON 0x3FFF // Fail-Safe Clock Monitor is enabled.
4350 //----------------------------- CONFIG2 Options -------------------------------
4352 #define _WRT_ALL 0x3FFC // 000h to 3FFFh write protected, no addresses may be modified by EECON control.
4353 #define _WRT_HALF 0x3FFD // 000h to 1FFFh write protected, 2000h to 3FFFh may be modified by EECON control.
4354 #define _WRT_BOOT 0x3FFE // 000h to 1FFh write protected, 200h to 3FFFh may be modified by EECON control.
4355 #define _WRT_OFF 0x3FFF // Write protection off.
4356 #define _PLLEN_OFF 0x3EFF // 4x PLL disabled.
4357 #define _PLLEN_ON 0x3FFF // 4x PLL enabled.
4358 #define _STVREN_OFF 0x3DFF // Stack Overflow or Underflow will not cause a Reset.
4359 #define _STVREN_ON 0x3FFF // Stack Overflow or Underflow will cause a Reset.
4360 #define _BORV_HI 0x3BFF // Brown-out Reset Voltage (Vbor), high trip point selected.
4361 #define _BORV_25 0x3BFF // Brown-out Reset Voltage (Vbor), high trip point selected.
4362 #define _BORV_LO 0x3FFF // Brown-out Reset Voltage (Vbor), low trip point selected.
4363 #define _BORV_19 0x3FFF // Brown-out Reset Voltage (Vbor), low trip point selected.
4364 #define _DEBUG_ON 0x2FFF // In-Circuit Debugger enabled, ICSPCLK and ICSPDAT are dedicated to the debugger.
4365 #define _DEBUG_OFF 0x3FFF // In-Circuit Debugger disabled, ICSPCLK and ICSPDAT are general purpose I/O pins.
4366 #define _LVP_OFF 0x1FFF // High-voltage on MCLR/VPP must be used for programming.
4367 #define _LVP_ON 0x3FFF // Low-voltage programming enabled.
4369 //==============================================================================
4371 #define _DEVID1 0x8006
4373 #define _IDLOC0 0x8000
4374 #define _IDLOC1 0x8001
4375 #define _IDLOC2 0x8002
4376 #define _IDLOC3 0x8003
4378 //==============================================================================
4380 #ifndef NO_BIT_DEFINES
4382 #define ADON ADCON0bits.ADON // bit 0
4383 #define GO_NOT_DONE ADCON0bits.GO_NOT_DONE // bit 1, shadows bit in ADCON0bits
4384 #define ADGO ADCON0bits.ADGO // bit 1, shadows bit in ADCON0bits
4385 #define GO ADCON0bits.GO // bit 1, shadows bit in ADCON0bits
4386 #define NOT_DONE ADCON0bits.NOT_DONE // bit 1, shadows bit in ADCON0bits
4387 #define CHS0 ADCON0bits.CHS0 // bit 2
4388 #define CHS1 ADCON0bits.CHS1 // bit 3
4389 #define CHS2 ADCON0bits.CHS2 // bit 4
4390 #define CHS3 ADCON0bits.CHS3 // bit 5
4391 #define CHS4 ADCON0bits.CHS4 // bit 6
4393 #define ADPREF0 ADCON1bits.ADPREF0 // bit 0
4394 #define ADPREF1 ADCON1bits.ADPREF1 // bit 1
4395 #define ADNREF ADCON1bits.ADNREF // bit 2
4396 #define ADCS0 ADCON1bits.ADCS0 // bit 4
4397 #define ADCS1 ADCON1bits.ADCS1 // bit 5
4398 #define ADCS2 ADCON1bits.ADCS2 // bit 6
4399 #define ADFM ADCON1bits.ADFM // bit 7
4401 #define ANSA0 ANSELAbits.ANSA0 // bit 0
4402 #define ANSA1 ANSELAbits.ANSA1 // bit 1
4403 #define ANSA2 ANSELAbits.ANSA2 // bit 2
4404 #define ANSA3 ANSELAbits.ANSA3 // bit 3
4405 #define ANSA4 ANSELAbits.ANSA4 // bit 4
4406 #define ANSA5 ANSELAbits.ANSA5 // bit 5
4408 #define ANSB0 ANSELBbits.ANSB0 // bit 0
4409 #define ANSB1 ANSELBbits.ANSB1 // bit 1
4410 #define ANSB2 ANSELBbits.ANSB2 // bit 2
4411 #define ANSB3 ANSELBbits.ANSB3 // bit 3
4412 #define ANSB4 ANSELBbits.ANSB4 // bit 4
4413 #define ANSB5 ANSELBbits.ANSB5 // bit 5
4415 #define ANSD0 ANSELDbits.ANSD0 // bit 0
4416 #define ANSD1 ANSELDbits.ANSD1 // bit 1
4417 #define ANSD2 ANSELDbits.ANSD2 // bit 2
4418 #define ANSD3 ANSELDbits.ANSD3 // bit 3
4419 #define ANSD4 ANSELDbits.ANSD4 // bit 4
4420 #define ANSD5 ANSELDbits.ANSD5 // bit 5
4421 #define ANSD6 ANSELDbits.ANSD6 // bit 6
4422 #define ANSD7 ANSELDbits.ANSD7 // bit 7
4424 #define ANSE0 ANSELEbits.ANSE0 // bit 0
4425 #define ANSE1 ANSELEbits.ANSE1 // bit 1
4426 #define ANSE2 ANSELEbits.ANSE2 // bit 2
4428 #define CCP2SEL APFCONbits.CCP2SEL // bit 0
4429 #define SSSEL APFCONbits.SSSEL // bit 1
4430 #define C2OUTSEL APFCONbits.C2OUTSEL // bit 2
4431 #define SRNQSEL APFCONbits.SRNQSEL // bit 3
4432 #define P2BSEL APFCONbits.P2BSEL // bit 4
4433 #define T1GSEL APFCONbits.T1GSEL // bit 5
4434 #define CCP3SEL APFCONbits.CCP3SEL // bit 6
4436 #define ABDEN BAUDCONbits.ABDEN // bit 0
4437 #define WUE BAUDCONbits.WUE // bit 1
4438 #define BRG16 BAUDCONbits.BRG16 // bit 3
4439 #define SCKP BAUDCONbits.SCKP // bit 4
4440 #define RCIDL BAUDCONbits.RCIDL // bit 6
4441 #define ABDOVF BAUDCONbits.ABDOVF // bit 7
4443 #define BORRDY BORCONbits.BORRDY // bit 0
4444 #define SBOREN BORCONbits.SBOREN // bit 7
4446 #define BSR0 BSRbits.BSR0 // bit 0
4447 #define BSR1 BSRbits.BSR1 // bit 1
4448 #define BSR2 BSRbits.BSR2 // bit 2
4449 #define BSR3 BSRbits.BSR3 // bit 3
4450 #define BSR4 BSRbits.BSR4 // bit 4
4452 #define PSS1BD0 CCP1ASbits.PSS1BD0 // bit 0
4453 #define PSS1BD1 CCP1ASbits.PSS1BD1 // bit 1
4454 #define PSS1AC0 CCP1ASbits.PSS1AC0 // bit 2
4455 #define PSS1AC1 CCP1ASbits.PSS1AC1 // bit 3
4456 #define CCP1AS0 CCP1ASbits.CCP1AS0 // bit 4
4457 #define CCP1AS1 CCP1ASbits.CCP1AS1 // bit 5
4458 #define CCP1AS2 CCP1ASbits.CCP1AS2 // bit 6
4459 #define CCP1ASE CCP1ASbits.CCP1ASE // bit 7
4461 #define CCP1M0 CCP1CONbits.CCP1M0 // bit 0
4462 #define CCP1M1 CCP1CONbits.CCP1M1 // bit 1
4463 #define CCP1M2 CCP1CONbits.CCP1M2 // bit 2
4464 #define CCP1M3 CCP1CONbits.CCP1M3 // bit 3
4465 #define DC1B0 CCP1CONbits.DC1B0 // bit 4
4466 #define DC1B1 CCP1CONbits.DC1B1 // bit 5
4467 #define P1M0 CCP1CONbits.P1M0 // bit 6
4468 #define P1M1 CCP1CONbits.P1M1 // bit 7
4470 #define PSS2BD0 CCP2ASbits.PSS2BD0 // bit 0
4471 #define PSS2BD1 CCP2ASbits.PSS2BD1 // bit 1
4472 #define PSS2AC0 CCP2ASbits.PSS2AC0 // bit 2
4473 #define PSS2AC1 CCP2ASbits.PSS2AC1 // bit 3
4474 #define CCP2AS0 CCP2ASbits.CCP2AS0 // bit 4
4475 #define CCP2AS1 CCP2ASbits.CCP2AS1 // bit 5
4476 #define CCP2AS2 CCP2ASbits.CCP2AS2 // bit 6
4477 #define CCP2ASE CCP2ASbits.CCP2ASE // bit 7
4479 #define CCP2M0 CCP2CONbits.CCP2M0 // bit 0
4480 #define CCP2M1 CCP2CONbits.CCP2M1 // bit 1
4481 #define CCP2M2 CCP2CONbits.CCP2M2 // bit 2
4482 #define CCP2M3 CCP2CONbits.CCP2M3 // bit 3
4483 #define DC2B0 CCP2CONbits.DC2B0 // bit 4
4484 #define DC2B1 CCP2CONbits.DC2B1 // bit 5
4485 #define P2M0 CCP2CONbits.P2M0 // bit 6
4486 #define P2M1 CCP2CONbits.P2M1 // bit 7
4488 #define PSS3BD0 CCP3ASbits.PSS3BD0 // bit 0
4489 #define PSS3BD1 CCP3ASbits.PSS3BD1 // bit 1
4490 #define PSS3AC0 CCP3ASbits.PSS3AC0 // bit 2
4491 #define PSS3AC1 CCP3ASbits.PSS3AC1 // bit 3
4492 #define CCP3AS0 CCP3ASbits.CCP3AS0 // bit 4
4493 #define CCP3AS1 CCP3ASbits.CCP3AS1 // bit 5
4494 #define CCP3AS2 CCP3ASbits.CCP3AS2 // bit 6
4495 #define CCP3ASE CCP3ASbits.CCP3ASE // bit 7
4497 #define CCP3M0 CCP3CONbits.CCP3M0 // bit 0
4498 #define CCP3M1 CCP3CONbits.CCP3M1 // bit 1
4499 #define CCP3M2 CCP3CONbits.CCP3M2 // bit 2
4500 #define CCP3M3 CCP3CONbits.CCP3M3 // bit 3
4501 #define DC3B0 CCP3CONbits.DC3B0 // bit 4
4502 #define DC3B1 CCP3CONbits.DC3B1 // bit 5
4503 #define P3M0 CCP3CONbits.P3M0 // bit 6
4504 #define P3M1 CCP3CONbits.P3M1 // bit 7
4506 #define CCP4M0 CCP4CONbits.CCP4M0 // bit 0
4507 #define CCP4M1 CCP4CONbits.CCP4M1 // bit 1
4508 #define CCP4M2 CCP4CONbits.CCP4M2 // bit 2
4509 #define CCP4M3 CCP4CONbits.CCP4M3 // bit 3
4510 #define DC4B0 CCP4CONbits.DC4B0 // bit 4
4511 #define DC4B1 CCP4CONbits.DC4B1 // bit 5
4513 #define CCP5M0 CCP5CONbits.CCP5M0 // bit 0
4514 #define CCP5M1 CCP5CONbits.CCP5M1 // bit 1
4515 #define CCP5M2 CCP5CONbits.CCP5M2 // bit 2
4516 #define CCP5M3 CCP5CONbits.CCP5M3 // bit 3
4517 #define DC5B0 CCP5CONbits.DC5B0 // bit 4
4518 #define DC5B1 CCP5CONbits.DC5B1 // bit 5
4520 #define C1TSEL0 CCPTMRS0bits.C1TSEL0 // bit 0
4521 #define C1TSEL1 CCPTMRS0bits.C1TSEL1 // bit 1
4522 #define C2TSEL0 CCPTMRS0bits.C2TSEL0 // bit 2
4523 #define C2TSEL1 CCPTMRS0bits.C2TSEL1 // bit 3
4524 #define C3TSEL0 CCPTMRS0bits.C3TSEL0 // bit 4
4525 #define C3TSEL1 CCPTMRS0bits.C3TSEL1 // bit 5
4526 #define C4TSEL0 CCPTMRS0bits.C4TSEL0 // bit 6
4527 #define C4TSEL1 CCPTMRS0bits.C4TSEL1 // bit 7
4529 #define C5TSEL0 CCPTMRS1bits.C5TSEL0 // bit 0
4530 #define C5TSEL1 CCPTMRS1bits.C5TSEL1 // bit 1
4532 #define C1SYNC CM1CON0bits.C1SYNC // bit 0
4533 #define C1HYS CM1CON0bits.C1HYS // bit 1
4534 #define C1SP CM1CON0bits.C1SP // bit 2
4535 #define C1POL CM1CON0bits.C1POL // bit 4
4536 #define C1OE CM1CON0bits.C1OE // bit 5
4537 #define C1OUT CM1CON0bits.C1OUT // bit 6
4538 #define C1ON CM1CON0bits.C1ON // bit 7
4540 #define C1NCH0 CM1CON1bits.C1NCH0 // bit 0
4541 #define C1NCH1 CM1CON1bits.C1NCH1 // bit 1
4542 #define C1PCH0 CM1CON1bits.C1PCH0 // bit 4
4543 #define C1PCH1 CM1CON1bits.C1PCH1 // bit 5
4544 #define C1INTN CM1CON1bits.C1INTN // bit 6
4545 #define C1INTP CM1CON1bits.C1INTP // bit 7
4547 #define C2SYNC CM2CON0bits.C2SYNC // bit 0
4548 #define C2HYS CM2CON0bits.C2HYS // bit 1
4549 #define C2SP CM2CON0bits.C2SP // bit 2
4550 #define C2POL CM2CON0bits.C2POL // bit 4
4551 #define C2OE CM2CON0bits.C2OE // bit 5
4552 #define C2OUT CM2CON0bits.C2OUT // bit 6
4553 #define C2ON CM2CON0bits.C2ON // bit 7
4555 #define C2NCH0 CM2CON1bits.C2NCH0 // bit 0
4556 #define C2NCH1 CM2CON1bits.C2NCH1 // bit 1
4557 #define C2PCH0 CM2CON1bits.C2PCH0 // bit 4
4558 #define C2PCH1 CM2CON1bits.C2PCH1 // bit 5
4559 #define C2INTN CM2CON1bits.C2INTN // bit 6
4560 #define C2INTP CM2CON1bits.C2INTP // bit 7
4562 #define MC1OUT CMOUTbits.MC1OUT // bit 0
4563 #define MC2OUT CMOUTbits.MC2OUT // bit 1
4565 #define T0XCS CPSCON0bits.T0XCS // bit 0
4566 #define CPSOUT CPSCON0bits.CPSOUT // bit 1
4567 #define CPSRNG0 CPSCON0bits.CPSRNG0 // bit 2
4568 #define CPSRNG1 CPSCON0bits.CPSRNG1 // bit 3
4569 #define CPSRM CPSCON0bits.CPSRM // bit 6
4570 #define CPSON CPSCON0bits.CPSON // bit 7
4572 #define CPSCH0 CPSCON1bits.CPSCH0 // bit 0
4573 #define CPSCH1 CPSCON1bits.CPSCH1 // bit 1
4574 #define CPSCH2 CPSCON1bits.CPSCH2 // bit 2
4575 #define CPSCH3 CPSCON1bits.CPSCH3 // bit 3
4577 #define DACNSS DACCON0bits.DACNSS // bit 0
4578 #define DACPSS0 DACCON0bits.DACPSS0 // bit 2
4579 #define DACPSS1 DACCON0bits.DACPSS1 // bit 3
4580 #define DACOE DACCON0bits.DACOE // bit 5
4581 #define DACLPS DACCON0bits.DACLPS // bit 6
4582 #define DACEN DACCON0bits.DACEN // bit 7
4584 #define DACR0 DACCON1bits.DACR0 // bit 0
4585 #define DACR1 DACCON1bits.DACR1 // bit 1
4586 #define DACR2 DACCON1bits.DACR2 // bit 2
4587 #define DACR3 DACCON1bits.DACR3 // bit 3
4588 #define DACR4 DACCON1bits.DACR4 // bit 4
4590 #define RD EECON1bits.RD // bit 0
4591 #define WR EECON1bits.WR // bit 1
4592 #define WREN EECON1bits.WREN // bit 2
4593 #define WRERR EECON1bits.WRERR // bit 3
4594 #define FREE EECON1bits.FREE // bit 4
4595 #define LWLO EECON1bits.LWLO // bit 5
4596 #define CFGS EECON1bits.CFGS // bit 6
4597 #define EEPGD EECON1bits.EEPGD // bit 7
4599 #define ADFVR0 FVRCONbits.ADFVR0 // bit 0
4600 #define ADFVR1 FVRCONbits.ADFVR1 // bit 1
4601 #define CDAFVR0 FVRCONbits.CDAFVR0 // bit 2
4602 #define CDAFVR1 FVRCONbits.CDAFVR1 // bit 3
4603 #define TSRNG FVRCONbits.TSRNG // bit 4
4604 #define TSEN FVRCONbits.TSEN // bit 5
4605 #define FVRRDY FVRCONbits.FVRRDY // bit 6
4606 #define FVREN FVRCONbits.FVREN // bit 7
4608 #define IOCIF INTCONbits.IOCIF // bit 0
4609 #define INTF INTCONbits.INTF // bit 1
4610 #define TMR0IF INTCONbits.TMR0IF // bit 2, shadows bit in INTCONbits
4611 #define T0IF INTCONbits.T0IF // bit 2, shadows bit in INTCONbits
4612 #define IOCIE INTCONbits.IOCIE // bit 3
4613 #define INTE INTCONbits.INTE // bit 4
4614 #define TMR0IE INTCONbits.TMR0IE // bit 5, shadows bit in INTCONbits
4615 #define T0IE INTCONbits.T0IE // bit 5, shadows bit in INTCONbits
4616 #define PEIE INTCONbits.PEIE // bit 6
4617 #define GIE INTCONbits.GIE // bit 7
4619 #define IOCBF0 IOCBFbits.IOCBF0 // bit 0
4620 #define IOCBF1 IOCBFbits.IOCBF1 // bit 1
4621 #define IOCBF2 IOCBFbits.IOCBF2 // bit 2
4622 #define IOCBF3 IOCBFbits.IOCBF3 // bit 3
4623 #define IOCBF4 IOCBFbits.IOCBF4 // bit 4
4624 #define IOCBF5 IOCBFbits.IOCBF5 // bit 5
4625 #define IOCBF6 IOCBFbits.IOCBF6 // bit 6
4626 #define IOCBF7 IOCBFbits.IOCBF7 // bit 7
4628 #define IOCBN0 IOCBNbits.IOCBN0 // bit 0
4629 #define IOCBN1 IOCBNbits.IOCBN1 // bit 1
4630 #define IOCBN2 IOCBNbits.IOCBN2 // bit 2
4631 #define IOCBN3 IOCBNbits.IOCBN3 // bit 3
4632 #define IOCBN4 IOCBNbits.IOCBN4 // bit 4
4633 #define IOCBN5 IOCBNbits.IOCBN5 // bit 5
4634 #define IOCBN6 IOCBNbits.IOCBN6 // bit 6
4635 #define IOCBN7 IOCBNbits.IOCBN7 // bit 7
4637 #define IOCBP0 IOCBPbits.IOCBP0 // bit 0
4638 #define IOCBP1 IOCBPbits.IOCBP1 // bit 1
4639 #define IOCBP2 IOCBPbits.IOCBP2 // bit 2
4640 #define IOCBP3 IOCBPbits.IOCBP3 // bit 3
4641 #define IOCBP4 IOCBPbits.IOCBP4 // bit 4
4642 #define IOCBP5 IOCBPbits.IOCBP5 // bit 5
4643 #define IOCBP6 IOCBPbits.IOCBP6 // bit 6
4644 #define IOCBP7 IOCBPbits.IOCBP7 // bit 7
4646 #define LATA0 LATAbits.LATA0 // bit 0
4647 #define LATA1 LATAbits.LATA1 // bit 1
4648 #define LATA2 LATAbits.LATA2 // bit 2
4649 #define LATA3 LATAbits.LATA3 // bit 3
4650 #define LATA4 LATAbits.LATA4 // bit 4
4651 #define LATA5 LATAbits.LATA5 // bit 5
4652 #define LATA6 LATAbits.LATA6 // bit 6
4653 #define LATA7 LATAbits.LATA7 // bit 7
4655 #define LATB0 LATBbits.LATB0 // bit 0
4656 #define LATB1 LATBbits.LATB1 // bit 1
4657 #define LATB2 LATBbits.LATB2 // bit 2
4658 #define LATB3 LATBbits.LATB3 // bit 3
4659 #define LATB4 LATBbits.LATB4 // bit 4
4660 #define LATB5 LATBbits.LATB5 // bit 5
4661 #define LATB6 LATBbits.LATB6 // bit 6
4662 #define LATB7 LATBbits.LATB7 // bit 7
4664 #define LATC0 LATCbits.LATC0 // bit 0
4665 #define LATC1 LATCbits.LATC1 // bit 1
4666 #define LATC2 LATCbits.LATC2 // bit 2
4667 #define LATC3 LATCbits.LATC3 // bit 3
4668 #define LATC4 LATCbits.LATC4 // bit 4
4669 #define LATC5 LATCbits.LATC5 // bit 5
4670 #define LATC6 LATCbits.LATC6 // bit 6
4671 #define LATC7 LATCbits.LATC7 // bit 7
4673 #define LATD0 LATDbits.LATD0 // bit 0
4674 #define LATD1 LATDbits.LATD1 // bit 1
4675 #define LATD2 LATDbits.LATD2 // bit 2
4676 #define LATD3 LATDbits.LATD3 // bit 3
4677 #define LATD4 LATDbits.LATD4 // bit 4
4678 #define LATD5 LATDbits.LATD5 // bit 5
4679 #define LATD6 LATDbits.LATD6 // bit 6
4680 #define LATD7 LATDbits.LATD7 // bit 7
4682 #define LATE0 LATEbits.LATE0 // bit 0
4683 #define LATE1 LATEbits.LATE1 // bit 1
4684 #define LATE2 LATEbits.LATE2 // bit 2
4685 #define LATE3 LATEbits.LATE3 // bit 3
4687 #define LMUX0 LCDCONbits.LMUX0 // bit 0
4688 #define LMUX1 LCDCONbits.LMUX1 // bit 1
4689 #define CS0 LCDCONbits.CS0 // bit 2
4690 #define CS1 LCDCONbits.CS1 // bit 3
4691 #define WERR LCDCONbits.WERR // bit 5
4692 #define SLPEN LCDCONbits.SLPEN // bit 6
4693 #define LCDEN LCDCONbits.LCDEN // bit 7
4695 #define LCDCST0 LCDCSTbits.LCDCST0 // bit 0
4696 #define LCDCST1 LCDCSTbits.LCDCST1 // bit 1
4697 #define LCDCST2 LCDCSTbits.LCDCST2 // bit 2
4699 #define SEG0COM0 LCDDATA0bits.SEG0COM0 // bit 0
4700 #define SEG1COM0 LCDDATA0bits.SEG1COM0 // bit 1
4701 #define SEG2COM0 LCDDATA0bits.SEG2COM0 // bit 2
4702 #define SEG3COM0 LCDDATA0bits.SEG3COM0 // bit 3
4703 #define SEG4COM0 LCDDATA0bits.SEG4COM0 // bit 4
4704 #define SEG5COM0 LCDDATA0bits.SEG5COM0 // bit 5
4705 #define SEG6COM0 LCDDATA0bits.SEG6COM0 // bit 6
4706 #define SEG7COM0 LCDDATA0bits.SEG7COM0 // bit 7
4708 #define SEG8COM0 LCDDATA1bits.SEG8COM0 // bit 0
4709 #define SEG9COM0 LCDDATA1bits.SEG9COM0 // bit 1
4710 #define SEG10COM0 LCDDATA1bits.SEG10COM0 // bit 2
4711 #define SEG11COM0 LCDDATA1bits.SEG11COM0 // bit 3
4712 #define SEG12COM0 LCDDATA1bits.SEG12COM0 // bit 4
4713 #define SEG13COM0 LCDDATA1bits.SEG13COM0 // bit 5
4714 #define SEG14COM0 LCDDATA1bits.SEG14COM0 // bit 6
4715 #define SEG15COM0 LCDDATA1bits.SEG15COM0 // bit 7
4717 #define SEG16COM0 LCDDATA2bits.SEG16COM0 // bit 0
4718 #define SEG17COM0 LCDDATA2bits.SEG17COM0 // bit 1
4719 #define SEG18COM0 LCDDATA2bits.SEG18COM0 // bit 2
4720 #define SEG19COM0 LCDDATA2bits.SEG19COM0 // bit 3
4721 #define SEG20COM0 LCDDATA2bits.SEG20COM0 // bit 4
4722 #define SEG21COM0 LCDDATA2bits.SEG21COM0 // bit 5
4723 #define SEG22COM0 LCDDATA2bits.SEG22COM0 // bit 6
4724 #define SEG23COM0 LCDDATA2bits.SEG23COM0 // bit 7
4726 #define SEG0COM1 LCDDATA3bits.SEG0COM1 // bit 0
4727 #define SEG1COM1 LCDDATA3bits.SEG1COM1 // bit 1
4728 #define SEG2COM1 LCDDATA3bits.SEG2COM1 // bit 2
4729 #define SEG3COM1 LCDDATA3bits.SEG3COM1 // bit 3
4730 #define SEG4COM1 LCDDATA3bits.SEG4COM1 // bit 4
4731 #define SEG5COM1 LCDDATA3bits.SEG5COM1 // bit 5
4732 #define SEG6COM1 LCDDATA3bits.SEG6COM1 // bit 6
4733 #define SEG7COM1 LCDDATA3bits.SEG7COM1 // bit 7
4735 #define SEG8COM1 LCDDATA4bits.SEG8COM1 // bit 0
4736 #define SEG9COM1 LCDDATA4bits.SEG9COM1 // bit 1
4737 #define SEG10COM1 LCDDATA4bits.SEG10COM1 // bit 2
4738 #define SEG11COM1 LCDDATA4bits.SEG11COM1 // bit 3
4739 #define SEG12COM1 LCDDATA4bits.SEG12COM1 // bit 4
4740 #define SEG13COM1 LCDDATA4bits.SEG13COM1 // bit 5
4741 #define SEG14COM1 LCDDATA4bits.SEG14COM1 // bit 6
4742 #define SEG15COM1 LCDDATA4bits.SEG15COM1 // bit 7
4744 #define SEG16COM1 LCDDATA5bits.SEG16COM1 // bit 0
4745 #define SEG17COM1 LCDDATA5bits.SEG17COM1 // bit 1
4746 #define SEG18COM1 LCDDATA5bits.SEG18COM1 // bit 2
4747 #define SEG19COM1 LCDDATA5bits.SEG19COM1 // bit 3
4748 #define SEG20COM1 LCDDATA5bits.SEG20COM1 // bit 4
4749 #define SEG21COM1 LCDDATA5bits.SEG21COM1 // bit 5
4750 #define SEG22COM1 LCDDATA5bits.SEG22COM1 // bit 6
4751 #define SEG23COM1 LCDDATA5bits.SEG23COM1 // bit 7
4753 #define SEG0COM2 LCDDATA6bits.SEG0COM2 // bit 0
4754 #define SEG1COM2 LCDDATA6bits.SEG1COM2 // bit 1
4755 #define SEG2COM2 LCDDATA6bits.SEG2COM2 // bit 2
4756 #define SEG3COM2 LCDDATA6bits.SEG3COM2 // bit 3
4757 #define SEG4COM2 LCDDATA6bits.SEG4COM2 // bit 4
4758 #define SEG5COM2 LCDDATA6bits.SEG5COM2 // bit 5
4759 #define SEG6COM2 LCDDATA6bits.SEG6COM2 // bit 6
4760 #define SEG7COM2 LCDDATA6bits.SEG7COM2 // bit 7
4762 #define SEG8COM2 LCDDATA7bits.SEG8COM2 // bit 0
4763 #define SEG9COM2 LCDDATA7bits.SEG9COM2 // bit 1
4764 #define SEG10COM2 LCDDATA7bits.SEG10COM2 // bit 2
4765 #define SEG11COM2 LCDDATA7bits.SEG11COM2 // bit 3
4766 #define SEG12COM2 LCDDATA7bits.SEG12COM2 // bit 4
4767 #define SEG13COM2 LCDDATA7bits.SEG13COM2 // bit 5
4768 #define SEG14COM2 LCDDATA7bits.SEG14COM2 // bit 6
4769 #define SEG15COM2 LCDDATA7bits.SEG15COM2 // bit 7
4771 #define SEG16COM2 LCDDATA8bits.SEG16COM2 // bit 0
4772 #define SEG17COM2 LCDDATA8bits.SEG17COM2 // bit 1
4773 #define SEG18COM2 LCDDATA8bits.SEG18COM2 // bit 2
4774 #define SEG19COM2 LCDDATA8bits.SEG19COM2 // bit 3
4775 #define SEG20COM2 LCDDATA8bits.SEG20COM2 // bit 4
4776 #define SEG21COM2 LCDDATA8bits.SEG21COM2 // bit 5
4777 #define SEG22COM2 LCDDATA8bits.SEG22COM2 // bit 6
4778 #define SEG23COM2 LCDDATA8bits.SEG23COM2 // bit 7
4780 #define SEG0COM3 LCDDATA9bits.SEG0COM3 // bit 0
4781 #define SEG1COM3 LCDDATA9bits.SEG1COM3 // bit 1
4782 #define SEG2COM3 LCDDATA9bits.SEG2COM3 // bit 2
4783 #define SEG3COM3 LCDDATA9bits.SEG3COM3 // bit 3
4784 #define SEG4COM3 LCDDATA9bits.SEG4COM3 // bit 4
4785 #define SEG5COM3 LCDDATA9bits.SEG5COM3 // bit 5
4786 #define SEG6COM3 LCDDATA9bits.SEG6COM3 // bit 6
4787 #define SEG7COM3 LCDDATA9bits.SEG7COM3 // bit 7
4789 #define SEG8COM3 LCDDATA10bits.SEG8COM3 // bit 0
4790 #define SEG9COM3 LCDDATA10bits.SEG9COM3 // bit 1
4791 #define SEG10COM3 LCDDATA10bits.SEG10COM3 // bit 2
4792 #define SEG11COM3 LCDDATA10bits.SEG11COM3 // bit 3
4793 #define SEG12COM3 LCDDATA10bits.SEG12COM3 // bit 4
4794 #define SEG13COM3 LCDDATA10bits.SEG13COM3 // bit 5
4795 #define SEG14COM3 LCDDATA10bits.SEG14COM3 // bit 6
4796 #define SEG15COM3 LCDDATA10bits.SEG15COM3 // bit 7
4798 #define SEG16COM3 LCDDATA11bits.SEG16COM3 // bit 0
4799 #define SEG17COM3 LCDDATA11bits.SEG17COM3 // bit 1
4800 #define SEG18COM3 LCDDATA11bits.SEG18COM3 // bit 2
4801 #define SEG19COM3 LCDDATA11bits.SEG19COM3 // bit 3
4802 #define SEG20COM3 LCDDATA11bits.SEG20COM3 // bit 4
4803 #define SEG21COM3 LCDDATA11bits.SEG21COM3 // bit 5
4804 #define SEG22COM3 LCDDATA11bits.SEG22COM3 // bit 6
4805 #define SEG23COM3 LCDDATA11bits.SEG23COM3 // bit 7
4807 #define LP0 LCDPSbits.LP0 // bit 0
4808 #define LP1 LCDPSbits.LP1 // bit 1
4809 #define LP2 LCDPSbits.LP2 // bit 2
4810 #define LP3 LCDPSbits.LP3 // bit 3
4811 #define WA LCDPSbits.WA // bit 4
4812 #define LCDA LCDPSbits.LCDA // bit 5
4813 #define BIASMD LCDPSbits.BIASMD // bit 6
4814 #define WFT LCDPSbits.WFT // bit 7
4816 #define VLCD1PE LCDREFbits.VLCD1PE // bit 1
4817 #define VLCD2PE LCDREFbits.VLCD2PE // bit 2
4818 #define VLCD3PE LCDREFbits.VLCD3PE // bit 3
4819 #define LCDIRI LCDREFbits.LCDIRI // bit 5
4820 #define LCDIRS LCDREFbits.LCDIRS // bit 6
4821 #define LCDIRE LCDREFbits.LCDIRE // bit 7
4823 #define LRLAT0 LCDRLbits.LRLAT0 // bit 0
4824 #define LRLAT1 LCDRLbits.LRLAT1 // bit 1
4825 #define LRLAT2 LCDRLbits.LRLAT2 // bit 2
4826 #define LRLBP0 LCDRLbits.LRLBP0 // bit 4
4827 #define LRLBP1 LCDRLbits.LRLBP1 // bit 5
4828 #define LRLAP0 LCDRLbits.LRLAP0 // bit 6
4829 #define LRLAP1 LCDRLbits.LRLAP1 // bit 7
4831 #define SE0 LCDSE0bits.SE0 // bit 0
4832 #define SE1 LCDSE0bits.SE1 // bit 1
4833 #define SE2 LCDSE0bits.SE2 // bit 2
4834 #define SE3 LCDSE0bits.SE3 // bit 3
4835 #define SE4 LCDSE0bits.SE4 // bit 4
4836 #define SE5 LCDSE0bits.SE5 // bit 5
4837 #define SE6 LCDSE0bits.SE6 // bit 6
4838 #define SE7 LCDSE0bits.SE7 // bit 7
4840 #define SE8 LCDSE1bits.SE8 // bit 0
4841 #define SE9 LCDSE1bits.SE9 // bit 1
4842 #define SE10 LCDSE1bits.SE10 // bit 2
4843 #define SE11 LCDSE1bits.SE11 // bit 3
4844 #define SE12 LCDSE1bits.SE12 // bit 4
4845 #define SE13 LCDSE1bits.SE13 // bit 5
4846 #define SE14 LCDSE1bits.SE14 // bit 6
4847 #define SE15 LCDSE1bits.SE15 // bit 7
4849 #define SE16 LCDSE2bits.SE16 // bit 0
4850 #define SE17 LCDSE2bits.SE17 // bit 1
4851 #define SE18 LCDSE2bits.SE18 // bit 2
4852 #define SE19 LCDSE2bits.SE19 // bit 3
4853 #define SE20 LCDSE2bits.SE20 // bit 4
4854 #define SE21 LCDSE2bits.SE21 // bit 5
4855 #define SE22 LCDSE2bits.SE22 // bit 6
4856 #define SE23 LCDSE2bits.SE23 // bit 7
4858 #define PS0 OPTION_REGbits.PS0 // bit 0
4859 #define PS1 OPTION_REGbits.PS1 // bit 1
4860 #define PS2 OPTION_REGbits.PS2 // bit 2
4861 #define PSA OPTION_REGbits.PSA // bit 3
4862 #define TMR0SE OPTION_REGbits.TMR0SE // bit 4, shadows bit in OPTION_REGbits
4863 #define T0SE OPTION_REGbits.T0SE // bit 4, shadows bit in OPTION_REGbits
4864 #define TMR0CS OPTION_REGbits.TMR0CS // bit 5, shadows bit in OPTION_REGbits
4865 #define T0CS OPTION_REGbits.T0CS // bit 5, shadows bit in OPTION_REGbits
4866 #define INTEDG OPTION_REGbits.INTEDG // bit 6
4867 #define NOT_WPUEN OPTION_REGbits.NOT_WPUEN // bit 7
4869 #define SCS0 OSCCONbits.SCS0 // bit 0
4870 #define SCS1 OSCCONbits.SCS1 // bit 1
4871 #define IRCF0 OSCCONbits.IRCF0 // bit 3
4872 #define IRCF1 OSCCONbits.IRCF1 // bit 4
4873 #define IRCF2 OSCCONbits.IRCF2 // bit 5
4874 #define IRCF3 OSCCONbits.IRCF3 // bit 6
4875 #define SPLLEN OSCCONbits.SPLLEN // bit 7
4877 #define HFIOFS OSCSTATbits.HFIOFS // bit 0
4878 #define LFIOFR OSCSTATbits.LFIOFR // bit 1
4879 #define MFIOFR OSCSTATbits.MFIOFR // bit 2
4880 #define HFIOFL OSCSTATbits.HFIOFL // bit 3
4881 #define HFIOFR OSCSTATbits.HFIOFR // bit 4
4882 #define OSTS OSCSTATbits.OSTS // bit 5
4883 #define PLLR OSCSTATbits.PLLR // bit 6
4884 #define T1OSCR OSCSTATbits.T1OSCR // bit 7
4886 #define TUN0 OSCTUNEbits.TUN0 // bit 0
4887 #define TUN1 OSCTUNEbits.TUN1 // bit 1
4888 #define TUN2 OSCTUNEbits.TUN2 // bit 2
4889 #define TUN3 OSCTUNEbits.TUN3 // bit 3
4890 #define TUN4 OSCTUNEbits.TUN4 // bit 4
4891 #define TUN5 OSCTUNEbits.TUN5 // bit 5
4893 #define NOT_BOR PCONbits.NOT_BOR // bit 0
4894 #define NOT_POR PCONbits.NOT_POR // bit 1
4895 #define NOT_RI PCONbits.NOT_RI // bit 2
4896 #define NOT_RMCLR PCONbits.NOT_RMCLR // bit 3
4897 #define STKUNF PCONbits.STKUNF // bit 6
4898 #define STKOVF PCONbits.STKOVF // bit 7
4900 #define TMR1IE PIE1bits.TMR1IE // bit 0
4901 #define TMR2IE PIE1bits.TMR2IE // bit 1
4902 #define CCP1IE PIE1bits.CCP1IE // bit 2
4903 #define SSPIE PIE1bits.SSPIE // bit 3
4904 #define TXIE PIE1bits.TXIE // bit 4
4905 #define RCIE PIE1bits.RCIE // bit 5
4906 #define ADIE PIE1bits.ADIE // bit 6
4907 #define TMR1GIE PIE1bits.TMR1GIE // bit 7
4909 #define CCP2IE PIE2bits.CCP2IE // bit 0
4910 #define LCDIE PIE2bits.LCDIE // bit 2
4911 #define BCLIE PIE2bits.BCLIE // bit 3
4912 #define EEIE PIE2bits.EEIE // bit 4
4913 #define C1IE PIE2bits.C1IE // bit 5
4914 #define C2IE PIE2bits.C2IE // bit 6
4915 #define OSFIE PIE2bits.OSFIE // bit 7
4917 #define TMR4IE PIE3bits.TMR4IE // bit 1
4918 #define TMR6IE PIE3bits.TMR6IE // bit 3
4919 #define CCP3IE PIE3bits.CCP3IE // bit 4
4920 #define CCP4IE PIE3bits.CCP4IE // bit 5
4921 #define CCP5IE PIE3bits.CCP5IE // bit 6
4923 #define TMR1IF PIR1bits.TMR1IF // bit 0
4924 #define TMR2IF PIR1bits.TMR2IF // bit 1
4925 #define CCP1IF PIR1bits.CCP1IF // bit 2
4926 #define SSPIF PIR1bits.SSPIF // bit 3
4927 #define TXIF PIR1bits.TXIF // bit 4
4928 #define RCIF PIR1bits.RCIF // bit 5
4929 #define ADIF PIR1bits.ADIF // bit 6
4930 #define TMR1GIF PIR1bits.TMR1GIF // bit 7
4932 #define CCP2IF PIR2bits.CCP2IF // bit 0
4933 #define LCDIF PIR2bits.LCDIF // bit 2
4934 #define BCLIF PIR2bits.BCLIF // bit 3
4935 #define EEIF PIR2bits.EEIF // bit 4
4936 #define C1IF PIR2bits.C1IF // bit 5
4937 #define C2IF PIR2bits.C2IF // bit 6
4938 #define OSFIF PIR2bits.OSFIF // bit 7
4940 #define TMR4IF PIR3bits.TMR4IF // bit 1
4941 #define TMR6IF PIR3bits.TMR6IF // bit 3
4942 #define CCP3IF PIR3bits.CCP3IF // bit 4
4943 #define CCP4IF PIR3bits.CCP4IF // bit 5
4944 #define CCP5IF PIR3bits.CCP5IF // bit 6
4946 #define RA0 PORTAbits.RA0 // bit 0
4947 #define RA1 PORTAbits.RA1 // bit 1
4948 #define RA2 PORTAbits.RA2 // bit 2
4949 #define RA3 PORTAbits.RA3 // bit 3
4950 #define RA4 PORTAbits.RA4 // bit 4
4951 #define RA5 PORTAbits.RA5 // bit 5
4952 #define RA6 PORTAbits.RA6 // bit 6
4953 #define RA7 PORTAbits.RA7 // bit 7
4955 #define RB0 PORTBbits.RB0 // bit 0
4956 #define RB1 PORTBbits.RB1 // bit 1
4957 #define RB2 PORTBbits.RB2 // bit 2
4958 #define RB3 PORTBbits.RB3 // bit 3
4959 #define RB4 PORTBbits.RB4 // bit 4
4960 #define RB5 PORTBbits.RB5 // bit 5
4961 #define RB6 PORTBbits.RB6 // bit 6
4962 #define RB7 PORTBbits.RB7 // bit 7
4964 #define RC0 PORTCbits.RC0 // bit 0
4965 #define RC1 PORTCbits.RC1 // bit 1
4966 #define RC2 PORTCbits.RC2 // bit 2
4967 #define RC3 PORTCbits.RC3 // bit 3
4968 #define RC4 PORTCbits.RC4 // bit 4
4969 #define RC5 PORTCbits.RC5 // bit 5
4970 #define RC6 PORTCbits.RC6 // bit 6
4971 #define RC7 PORTCbits.RC7 // bit 7
4973 #define RD0 PORTDbits.RD0 // bit 0
4974 #define RD1 PORTDbits.RD1 // bit 1
4975 #define RD2 PORTDbits.RD2 // bit 2
4976 #define RD3 PORTDbits.RD3 // bit 3
4977 #define RD4 PORTDbits.RD4 // bit 4
4978 #define RD5 PORTDbits.RD5 // bit 5
4979 #define RD6 PORTDbits.RD6 // bit 6
4980 #define RD7 PORTDbits.RD7 // bit 7
4982 #define RE0 PORTEbits.RE0 // bit 0
4983 #define RE1 PORTEbits.RE1 // bit 1
4984 #define RE2 PORTEbits.RE2 // bit 2
4985 #define RE3 PORTEbits.RE3 // bit 3
4987 #define STR1A PSTR1CONbits.STR1A // bit 0
4988 #define STR1B PSTR1CONbits.STR1B // bit 1
4989 #define STR1C PSTR1CONbits.STR1C // bit 2
4990 #define STR1D PSTR1CONbits.STR1D // bit 3
4991 #define STR1SYNC PSTR1CONbits.STR1SYNC // bit 4
4993 #define STR2A PSTR2CONbits.STR2A // bit 0
4994 #define STR2B PSTR2CONbits.STR2B // bit 1
4995 #define STR2C PSTR2CONbits.STR2C // bit 2
4996 #define STR2D PSTR2CONbits.STR2D // bit 3
4997 #define STR2SYNC PSTR2CONbits.STR2SYNC // bit 4
4999 #define STR3A PSTR3CONbits.STR3A // bit 0
5000 #define STR3B PSTR3CONbits.STR3B // bit 1
5001 #define STR3C PSTR3CONbits.STR3C // bit 2
5002 #define STR3D PSTR3CONbits.STR3D // bit 3
5003 #define STR3SYNC PSTR3CONbits.STR3SYNC // bit 4
5005 #define P1DC0 PWM1CONbits.P1DC0 // bit 0
5006 #define P1DC1 PWM1CONbits.P1DC1 // bit 1
5007 #define P1DC2 PWM1CONbits.P1DC2 // bit 2
5008 #define P1DC3 PWM1CONbits.P1DC3 // bit 3
5009 #define P1DC4 PWM1CONbits.P1DC4 // bit 4
5010 #define P1DC5 PWM1CONbits.P1DC5 // bit 5
5011 #define P1DC6 PWM1CONbits.P1DC6 // bit 6
5012 #define P1RSEN PWM1CONbits.P1RSEN // bit 7
5014 #define P2DC0 PWM2CONbits.P2DC0 // bit 0
5015 #define P2DC1 PWM2CONbits.P2DC1 // bit 1
5016 #define P2DC2 PWM2CONbits.P2DC2 // bit 2
5017 #define P2DC3 PWM2CONbits.P2DC3 // bit 3
5018 #define P2DC4 PWM2CONbits.P2DC4 // bit 4
5019 #define P2DC5 PWM2CONbits.P2DC5 // bit 5
5020 #define P2DC6 PWM2CONbits.P2DC6 // bit 6
5021 #define P2RSEN PWM2CONbits.P2RSEN // bit 7
5023 #define P3DC0 PWM3CONbits.P3DC0 // bit 0
5024 #define P3DC1 PWM3CONbits.P3DC1 // bit 1
5025 #define P3DC2 PWM3CONbits.P3DC2 // bit 2
5026 #define P3DC3 PWM3CONbits.P3DC3 // bit 3
5027 #define P3DC4 PWM3CONbits.P3DC4 // bit 4
5028 #define P3DC5 PWM3CONbits.P3DC5 // bit 5
5029 #define P3DC6 PWM3CONbits.P3DC6 // bit 6
5030 #define P3RSEN PWM3CONbits.P3RSEN // bit 7
5032 #define RX9D RCSTAbits.RX9D // bit 0
5033 #define OERR RCSTAbits.OERR // bit 1
5034 #define FERR RCSTAbits.FERR // bit 2
5035 #define ADDEN RCSTAbits.ADDEN // bit 3
5036 #define CREN RCSTAbits.CREN // bit 4
5037 #define SREN RCSTAbits.SREN // bit 5
5038 #define RX9 RCSTAbits.RX9 // bit 6
5039 #define SPEN RCSTAbits.SPEN // bit 7
5041 #define SRPR SRCON0bits.SRPR // bit 0
5042 #define SRPS SRCON0bits.SRPS // bit 1
5043 #define SRNQEN SRCON0bits.SRNQEN // bit 2
5044 #define SRQEN SRCON0bits.SRQEN // bit 3
5045 #define SRCLK0 SRCON0bits.SRCLK0 // bit 4
5046 #define SRCLK1 SRCON0bits.SRCLK1 // bit 5
5047 #define SRCLK2 SRCON0bits.SRCLK2 // bit 6
5048 #define SRLEN SRCON0bits.SRLEN // bit 7
5050 #define SRRC1E SRCON1bits.SRRC1E // bit 0
5051 #define SRRC2E SRCON1bits.SRRC2E // bit 1
5052 #define SRRCKE SRCON1bits.SRRCKE // bit 2
5053 #define SRRPE SRCON1bits.SRRPE // bit 3
5054 #define SRSC1E SRCON1bits.SRSC1E // bit 4
5055 #define SRSC2E SRCON1bits.SRSC2E // bit 5
5056 #define SRSCKE SRCON1bits.SRSCKE // bit 6
5057 #define SRSPE SRCON1bits.SRSPE // bit 7
5059 #define SSPM0 SSPCONbits.SSPM0 // bit 0
5060 #define SSPM1 SSPCONbits.SSPM1 // bit 1
5061 #define SSPM2 SSPCONbits.SSPM2 // bit 2
5062 #define SSPM3 SSPCONbits.SSPM3 // bit 3
5063 #define CKP SSPCONbits.CKP // bit 4
5064 #define SSPEN SSPCONbits.SSPEN // bit 5
5065 #define SSPOV SSPCONbits.SSPOV // bit 6
5066 #define WCOL SSPCONbits.WCOL // bit 7
5068 #define SEN SSPCON2bits.SEN // bit 0
5069 #define RSEN SSPCON2bits.RSEN // bit 1
5070 #define PEN SSPCON2bits.PEN // bit 2
5071 #define RCEN SSPCON2bits.RCEN // bit 3
5072 #define ACKEN SSPCON2bits.ACKEN // bit 4
5073 #define ACKDT SSPCON2bits.ACKDT // bit 5
5074 #define ACKSTAT SSPCON2bits.ACKSTAT // bit 6
5075 #define GCEN SSPCON2bits.GCEN // bit 7
5077 #define DHEN SSPCON3bits.DHEN // bit 0
5078 #define AHEN SSPCON3bits.AHEN // bit 1
5079 #define SBCDE SSPCON3bits.SBCDE // bit 2
5080 #define SDAHT SSPCON3bits.SDAHT // bit 3
5081 #define BOEN SSPCON3bits.BOEN // bit 4
5082 #define SCIE SSPCON3bits.SCIE // bit 5
5083 #define PCIE SSPCON3bits.PCIE // bit 6
5084 #define ACKTIM SSPCON3bits.ACKTIM // bit 7
5086 #define BF SSPSTATbits.BF // bit 0
5087 #define UA SSPSTATbits.UA // bit 1
5088 #define R_NOT_W SSPSTATbits.R_NOT_W // bit 2
5089 #define S SSPSTATbits.S // bit 3
5090 #define P SSPSTATbits.P // bit 4
5091 #define D_NOT_A SSPSTATbits.D_NOT_A // bit 5
5092 #define CKE SSPSTATbits.CKE // bit 6
5093 #define SMP SSPSTATbits.SMP // bit 7
5095 #define C STATUSbits.C // bit 0
5096 #define DC STATUSbits.DC // bit 1
5097 #define Z STATUSbits.Z // bit 2
5098 #define NOT_PD STATUSbits.NOT_PD // bit 3
5099 #define NOT_TO STATUSbits.NOT_TO // bit 4
5101 #define C_SHAD STATUS_SHADbits.C_SHAD // bit 0
5102 #define DC_SHAD STATUS_SHADbits.DC_SHAD // bit 1
5103 #define Z_SHAD STATUS_SHADbits.Z_SHAD // bit 2
5105 #define TMR1ON T1CONbits.TMR1ON // bit 0
5106 #define NOT_T1SYNC T1CONbits.NOT_T1SYNC // bit 2
5107 #define T1OSCEN T1CONbits.T1OSCEN // bit 3
5108 #define T1CKPS0 T1CONbits.T1CKPS0 // bit 4
5109 #define T1CKPS1 T1CONbits.T1CKPS1 // bit 5
5110 #define TMR1CS0 T1CONbits.TMR1CS0 // bit 6
5111 #define TMR1CS1 T1CONbits.TMR1CS1 // bit 7
5113 #define T1GSS0 T1GCONbits.T1GSS0 // bit 0
5114 #define T1GSS1 T1GCONbits.T1GSS1 // bit 1
5115 #define T1GVAL T1GCONbits.T1GVAL // bit 2
5116 #define T1GGO_NOT_DONE T1GCONbits.T1GGO_NOT_DONE // bit 3, shadows bit in T1GCONbits
5117 #define T1GGO T1GCONbits.T1GGO // bit 3, shadows bit in T1GCONbits
5118 #define T1GSPM T1GCONbits.T1GSPM // bit 4
5119 #define T1GTM T1GCONbits.T1GTM // bit 5
5120 #define T1GPOL T1GCONbits.T1GPOL // bit 6
5121 #define TMR1GE T1GCONbits.TMR1GE // bit 7
5123 #define T2CKPS0 T2CONbits.T2CKPS0 // bit 0
5124 #define T2CKPS1 T2CONbits.T2CKPS1 // bit 1
5125 #define TMR2ON T2CONbits.TMR2ON // bit 2
5126 #define T2OUTPS0 T2CONbits.T2OUTPS0 // bit 3
5127 #define T2OUTPS1 T2CONbits.T2OUTPS1 // bit 4
5128 #define T2OUTPS2 T2CONbits.T2OUTPS2 // bit 5
5129 #define T2OUTPS3 T2CONbits.T2OUTPS3 // bit 6
5131 #define T4CKPS0 T4CONbits.T4CKPS0 // bit 0
5132 #define T4CKPS1 T4CONbits.T4CKPS1 // bit 1
5133 #define TMR4ON T4CONbits.TMR4ON // bit 2
5134 #define T4OUTPS0 T4CONbits.T4OUTPS0 // bit 3
5135 #define T4OUTPS1 T4CONbits.T4OUTPS1 // bit 4
5136 #define T4OUTPS2 T4CONbits.T4OUTPS2 // bit 5
5137 #define T4OUTPS3 T4CONbits.T4OUTPS3 // bit 6
5139 #define T6CKPS0 T6CONbits.T6CKPS0 // bit 0
5140 #define T6CKPS1 T6CONbits.T6CKPS1 // bit 1
5141 #define TMR6ON T6CONbits.TMR6ON // bit 2
5142 #define T6OUTPS0 T6CONbits.T6OUTPS0 // bit 3
5143 #define T6OUTPS1 T6CONbits.T6OUTPS1 // bit 4
5144 #define T6OUTPS2 T6CONbits.T6OUTPS2 // bit 5
5145 #define T6OUTPS3 T6CONbits.T6OUTPS3 // bit 6
5147 #define TRISA0 TRISAbits.TRISA0 // bit 0
5148 #define TRISA1 TRISAbits.TRISA1 // bit 1
5149 #define TRISA2 TRISAbits.TRISA2 // bit 2
5150 #define TRISA3 TRISAbits.TRISA3 // bit 3
5151 #define TRISA4 TRISAbits.TRISA4 // bit 4
5152 #define TRISA5 TRISAbits.TRISA5 // bit 5
5153 #define TRISA6 TRISAbits.TRISA6 // bit 6
5154 #define TRISA7 TRISAbits.TRISA7 // bit 7
5156 #define TRISB0 TRISBbits.TRISB0 // bit 0
5157 #define TRISB1 TRISBbits.TRISB1 // bit 1
5158 #define TRISB2 TRISBbits.TRISB2 // bit 2
5159 #define TRISB3 TRISBbits.TRISB3 // bit 3
5160 #define TRISB4 TRISBbits.TRISB4 // bit 4
5161 #define TRISB5 TRISBbits.TRISB5 // bit 5
5162 #define TRISB6 TRISBbits.TRISB6 // bit 6
5163 #define TRISB7 TRISBbits.TRISB7 // bit 7
5165 #define TRISC0 TRISCbits.TRISC0 // bit 0
5166 #define TRISC1 TRISCbits.TRISC1 // bit 1
5167 #define TRISC2 TRISCbits.TRISC2 // bit 2
5168 #define TRISC3 TRISCbits.TRISC3 // bit 3
5169 #define TRISC4 TRISCbits.TRISC4 // bit 4
5170 #define TRISC5 TRISCbits.TRISC5 // bit 5
5171 #define TRISC6 TRISCbits.TRISC6 // bit 6
5172 #define TRISC7 TRISCbits.TRISC7 // bit 7
5174 #define TRISD0 TRISDbits.TRISD0 // bit 0
5175 #define TRISD1 TRISDbits.TRISD1 // bit 1
5176 #define TRISD2 TRISDbits.TRISD2 // bit 2
5177 #define TRISD3 TRISDbits.TRISD3 // bit 3
5178 #define TRISD4 TRISDbits.TRISD4 // bit 4
5179 #define TRISD5 TRISDbits.TRISD5 // bit 5
5180 #define TRISD6 TRISDbits.TRISD6 // bit 6
5181 #define TRISD7 TRISDbits.TRISD7 // bit 7
5183 #define TRISE0 TRISEbits.TRISE0 // bit 0
5184 #define TRISE1 TRISEbits.TRISE1 // bit 1
5185 #define TRISE2 TRISEbits.TRISE2 // bit 2
5186 #define TRISE3 TRISEbits.TRISE3 // bit 3
5188 #define TX9D TXSTAbits.TX9D // bit 0
5189 #define TRMT TXSTAbits.TRMT // bit 1
5190 #define BRGH TXSTAbits.BRGH // bit 2
5191 #define SENDB TXSTAbits.SENDB // bit 3
5192 #define SYNC TXSTAbits.SYNC // bit 4
5193 #define TXEN TXSTAbits.TXEN // bit 5
5194 #define TX9 TXSTAbits.TX9 // bit 6
5195 #define CSRC TXSTAbits.CSRC // bit 7
5197 #define SWDTEN WDTCONbits.SWDTEN // bit 0
5198 #define WDTPS0 WDTCONbits.WDTPS0 // bit 1
5199 #define WDTPS1 WDTCONbits.WDTPS1 // bit 2
5200 #define WDTPS2 WDTCONbits.WDTPS2 // bit 3
5201 #define WDTPS3 WDTCONbits.WDTPS3 // bit 4
5202 #define WDTPS4 WDTCONbits.WDTPS4 // bit 5
5204 #define WPUB0 WPUBbits.WPUB0 // bit 0
5205 #define WPUB1 WPUBbits.WPUB1 // bit 1
5206 #define WPUB2 WPUBbits.WPUB2 // bit 2
5207 #define WPUB3 WPUBbits.WPUB3 // bit 3
5208 #define WPUB4 WPUBbits.WPUB4 // bit 4
5209 #define WPUB5 WPUBbits.WPUB5 // bit 5
5210 #define WPUB6 WPUBbits.WPUB6 // bit 6
5211 #define WPUB7 WPUBbits.WPUB7 // bit 7
5213 #define WPUE3 WPUEbits.WPUE3 // bit 3
5215 #endif // #ifndef NO_BIT_DEFINES
5217 #endif // #ifndef __PIC16LF1939_H__