2 * This declarations of the PIC18LF8720 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:24:09 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #ifndef __PIC18LF8720_H__
26 #define __PIC18LF8720_H__
28 //==============================================================================
30 //==============================================================================
32 // Register Definitions
34 //==============================================================================
37 //==============================================================================
40 extern __at(0x0F6B) __sfr RCSTA2
;
105 extern __at(0x0F6B) volatile __RCSTA2bits_t RCSTA2bits
;
107 #define _RCSTA2_RX9D 0x01
108 #define _RCSTA2_RCD8 0x01
109 #define _RCSTA2_RX9D2 0x01
110 #define _RCSTA2_OERR 0x02
111 #define _RCSTA2_OERR2 0x02
112 #define _RCSTA2_FERR 0x04
113 #define _RCSTA2_FERR2 0x04
114 #define _RCSTA2_ADDEN 0x08
115 #define _RCSTA2_ADEN 0x08
116 #define _RCSTA2_ADDEN2 0x08
117 #define _RCSTA2_CREN 0x10
118 #define _RCSTA2_CREN2 0x10
119 #define _RCSTA2_SREN 0x20
120 #define _RCSTA2_SREN2 0x20
121 #define _RCSTA2_RX9 0x40
122 #define _RCSTA2_RC9 0x40
123 #define _RCSTA2_NOT_RC8 0x40
124 #define _RCSTA2_RC8_9 0x40
125 #define _RCSTA2_RX92 0x40
126 #define _RCSTA2_SPEN 0x80
127 #define _RCSTA2_SPEN2 0x80
129 //==============================================================================
132 //==============================================================================
135 extern __at(0x0F6C) __sfr TXSTA2
;
171 unsigned NOT_TX8
: 1;
188 extern __at(0x0F6C) volatile __TXSTA2bits_t TXSTA2bits
;
190 #define _TXSTA2_TX9D 0x01
191 #define _TXSTA2_TXD8 0x01
192 #define _TXSTA2_TX9D2 0x01
193 #define _TXSTA2_TRMT 0x02
194 #define _TXSTA2_TRMT2 0x02
195 #define _TXSTA2_BRGH 0x04
196 #define _TXSTA2_BRGH2 0x04
197 #define _TXSTA2_SENDB2 0x08
198 #define _TXSTA2_SYNC 0x10
199 #define _TXSTA2_SYNC2 0x10
200 #define _TXSTA2_TXEN 0x20
201 #define _TXSTA2_TXEN2 0x20
202 #define _TXSTA2_TX9 0x40
203 #define _TXSTA2_TX8_9 0x40
204 #define _TXSTA2_NOT_TX8 0x40
205 #define _TXSTA2_TX92 0x40
206 #define _TXSTA2_CSRC 0x80
207 #define _TXSTA2_CSRC2 0x80
209 //==============================================================================
211 extern __at(0x0F6D) __sfr TXREG2
;
212 extern __at(0x0F6E) __sfr RCREG2
;
213 extern __at(0x0F6F) __sfr SPBRG2
;
215 //==============================================================================
218 extern __at(0x0F70) __sfr CCP5CON
;
260 extern __at(0x0F70) volatile __CCP5CONbits_t CCP5CONbits
;
271 //==============================================================================
273 extern __at(0x0F71) __sfr CCPR5
;
274 extern __at(0x0F71) __sfr CCPR5L
;
275 extern __at(0x0F72) __sfr CCPR5H
;
277 //==============================================================================
280 extern __at(0x0F73) __sfr CCP4CON
;
322 extern __at(0x0F73) volatile __CCP4CONbits_t CCP4CONbits
;
333 //==============================================================================
335 extern __at(0x0F74) __sfr CCPR4
;
336 extern __at(0x0F74) __sfr CCPR4L
;
337 extern __at(0x0F75) __sfr CCPR4H
;
339 //==============================================================================
342 extern __at(0x0F76) __sfr T4CON
;
348 unsigned T4CKPS0
: 1;
349 unsigned T4CKPS1
: 1;
351 unsigned T4OUTPS0
: 1;
352 unsigned T4OUTPS1
: 1;
353 unsigned T4OUTPS2
: 1;
354 unsigned T4OUTPS3
: 1;
367 unsigned T4OUTPS
: 4;
372 extern __at(0x0F76) volatile __T4CONbits_t T4CONbits
;
374 #define _T4CKPS0 0x01
375 #define _T4CKPS1 0x02
377 #define _T4OUTPS0 0x08
378 #define _T4OUTPS1 0x10
379 #define _T4OUTPS2 0x20
380 #define _T4OUTPS3 0x40
382 //==============================================================================
384 extern __at(0x0F77) __sfr PR4
;
385 extern __at(0x0F78) __sfr TMR4
;
387 //==============================================================================
390 extern __at(0x0F80) __sfr PORTA
;
437 extern __at(0x0F80) volatile __PORTAbits_t PORTAbits
;
439 #define _PORTA_RA0 0x01
440 #define _PORTA_AN0 0x01
441 #define _PORTA_RA1 0x02
442 #define _PORTA_AN1 0x02
443 #define _PORTA_RA2 0x04
444 #define _PORTA_AN2 0x04
445 #define _PORTA_VREFM 0x04
446 #define _PORTA_RA3 0x08
447 #define _PORTA_AN3 0x08
448 #define _PORTA_VREFP 0x08
449 #define _PORTA_RA4 0x10
450 #define _PORTA_T0CKI 0x10
451 #define _PORTA_RA5 0x20
452 #define _PORTA_AN4 0x20
453 #define _PORTA_LVDIN 0x20
454 #define _PORTA_RA6 0x40
455 #define _PORTA_OSC2 0x40
456 #define _PORTA_CLKO 0x40
458 //==============================================================================
461 //==============================================================================
464 extern __at(0x0F81) __sfr PORTB
;
529 extern __at(0x0F81) volatile __PORTBbits_t PORTBbits
;
531 #define _PORTB_RB0 0x01
532 #define _PORTB_INT0 0x01
533 #define _PORTB_RB1 0x02
534 #define _PORTB_INT1 0x02
535 #define _PORTB_RB2 0x04
536 #define _PORTB_INT2 0x04
537 #define _PORTB_RB3 0x08
538 #define _PORTB_INT3 0x08
539 #define _PORTB_CCP2 0x08
540 #define _PORTB_CCP2A 0x08
541 #define _PORTB_RB4 0x10
542 #define _PORTB_KBI0 0x10
543 #define _PORTB_RB5 0x20
544 #define _PORTB_KBI1 0x20
545 #define _PORTB_PGM 0x20
546 #define _PORTB_RB6 0x40
547 #define _PORTB_KBI2 0x40
548 #define _PORTB_PGC 0x40
549 #define _PORTB_RB7 0x80
550 #define _PORTB_KBI3 0x80
551 #define _PORTB_PGD 0x80
553 //==============================================================================
556 //==============================================================================
559 extern __at(0x0F82) __sfr PORTC
;
612 extern __at(0x0F82) volatile __PORTCbits_t PORTCbits
;
614 #define _PORTC_RC0 0x01
615 #define _PORTC_T1OSO 0x01
616 #define _PORTC_T13CKI 0x01
617 #define _PORTC_RC1 0x02
618 #define _PORTC_T1OSI 0x02
619 #define _PORTC_CCP2 0x02
620 #define _PORTC_CCP2A 0x02
621 #define _PORTC_RC2 0x04
622 #define _PORTC_CCP1 0x04
623 #define _PORTC_RC3 0x08
624 #define _PORTC_SCK 0x08
625 #define _PORTC_SCL 0x08
626 #define _PORTC_RC4 0x10
627 #define _PORTC_SDI 0x10
628 #define _PORTC_SDA 0x10
629 #define _PORTC_RC5 0x20
630 #define _PORTC_SDO 0x20
631 #define _PORTC_RC6 0x40
632 #define _PORTC_TX 0x40
633 #define _PORTC_CK 0x40
634 #define _PORTC_RC7 0x80
635 #define _PORTC_RX 0x80
637 //==============================================================================
640 //==============================================================================
643 extern __at(0x0F83) __sfr PORTD
;
696 extern __at(0x0F83) volatile __PORTDbits_t PORTDbits
;
698 #define _PORTD_RD0 0x01
699 #define _PORTD_PSP0 0x01
700 #define _PORTD_AD0 0x01
701 #define _PORTD_AD00 0x01
702 #define _PORTD_RD1 0x02
703 #define _PORTD_PSP1 0x02
704 #define _PORTD_AD1 0x02
705 #define _PORTD_AD01 0x02
706 #define _PORTD_RD2 0x04
707 #define _PORTD_PSP2 0x04
708 #define _PORTD_AD2 0x04
709 #define _PORTD_AD02 0x04
710 #define _PORTD_RD3 0x08
711 #define _PORTD_PSP3 0x08
712 #define _PORTD_AD3 0x08
713 #define _PORTD_AD03 0x08
714 #define _PORTD_RD4 0x10
715 #define _PORTD_PSP4 0x10
716 #define _PORTD_AD4 0x10
717 #define _PORTD_AD04 0x10
718 #define _PORTD_RD5 0x20
719 #define _PORTD_PSP5 0x20
720 #define _PORTD_AD5 0x20
721 #define _PORTD_AD05 0x20
722 #define _PORTD_RD6 0x40
723 #define _PORTD_PSP6 0x40
724 #define _PORTD_AD6 0x40
725 #define _PORTD_AD06 0x40
726 #define _PORTD_RD7 0x80
727 #define _PORTD_PSP7 0x80
728 #define _PORTD_AD7 0x80
729 #define _PORTD_AD07 0x80
731 //==============================================================================
734 //==============================================================================
737 extern __at(0x0F84) __sfr PORTE
;
790 extern __at(0x0F84) volatile __PORTEbits_t PORTEbits
;
792 #define _PORTE_RE0 0x01
793 #define _PORTE_RD 0x01
794 #define _PORTE_AD8 0x01
795 #define _PORTE_AD08 0x01
796 #define _PORTE_RE1 0x02
797 #define _PORTE_WR 0x02
798 #define _PORTE_AD9 0x02
799 #define _PORTE_AD09 0x02
800 #define _PORTE_RE2 0x04
801 #define _PORTE_CS 0x04
802 #define _PORTE_AD10 0x04
803 #define _PORTE_RE3 0x08
804 #define _PORTE_AD11 0x08
805 #define _PORTE_RE4 0x10
806 #define _PORTE_AD12 0x10
807 #define _PORTE_RE5 0x20
808 #define _PORTE_AD13 0x20
809 #define _PORTE_RE6 0x40
810 #define _PORTE_AD14 0x40
811 #define _PORTE_RE7 0x80
812 #define _PORTE_CCP2 0x80
813 #define _PORTE_AD15 0x80
814 #define _PORTE_CCP2C 0x80
816 //==============================================================================
819 //==============================================================================
822 extern __at(0x0F85) __sfr PORTF
;
863 extern __at(0x0F85) volatile __PORTFbits_t PORTFbits
;
865 #define _PORTF_RF0 0x01
866 #define _PORTF_AN5 0x01
867 #define _PORTF_RF1 0x02
868 #define _PORTF_AN6 0x02
869 #define _PORTF_C2OUT 0x02
870 #define _PORTF_RF2 0x04
871 #define _PORTF_AN7 0x04
872 #define _PORTF_C1OUT 0x04
873 #define _PORTF_RF3 0x08
874 #define _PORTF_AN8 0x08
875 #define _PORTF_RF4 0x10
876 #define _PORTF_AN9 0x10
877 #define _PORTF_RF5 0x20
878 #define _PORTF_AN10 0x20
879 #define _PORTF_CVREF 0x20
880 #define _PORTF_RF6 0x40
881 #define _PORTF_AN11 0x40
882 #define _PORTF_RF7 0x80
883 #define _PORTF_SS 0x80
885 //==============================================================================
888 //==============================================================================
891 extern __at(0x0F86) __sfr PORTG
;
938 extern __at(0x0F86) volatile __PORTGbits_t PORTGbits
;
940 #define _PORTG_RG0 0x01
941 #define _PORTG_CCP3 0x01
942 #define _PORTG_RG1 0x02
943 #define _PORTG_TX2 0x02
944 #define _PORTG_CK2 0x02
945 #define _PORTG_RG2 0x04
946 #define _PORTG_RX2 0x04
947 #define _PORTG_DT2 0x04
948 #define _PORTG_RG3 0x08
949 #define _PORTG_CCP4 0x08
950 #define _PORTG_RG4 0x10
951 #define _PORTG_CCP5 0x10
953 //==============================================================================
956 //==============================================================================
959 extern __at(0x0F87) __sfr PORTH
;
1000 extern __at(0x0F87) volatile __PORTHbits_t PORTHbits
;
1002 #define _PORTH_RH0 0x01
1003 #define _PORTH_A16 0x01
1004 #define _PORTH_AD16 0x01
1005 #define _PORTH_RH1 0x02
1006 #define _PORTH_A17 0x02
1007 #define _PORTH_AD17 0x02
1008 #define _PORTH_RH2 0x04
1009 #define _PORTH_A18 0x04
1010 #define _PORTH_AD18 0x04
1011 #define _PORTH_RH3 0x08
1012 #define _PORTH_A19 0x08
1013 #define _PORTH_AD19 0x08
1014 #define _PORTH_RH4 0x10
1015 #define _PORTH_AN12 0x10
1016 #define _PORTH_RH5 0x20
1017 #define _PORTH_AN13 0x20
1018 #define _PORTH_RH6 0x40
1019 #define _PORTH_AN14 0x40
1020 #define _PORTH_RH7 0x80
1021 #define _PORTH_AN15 0x80
1023 //==============================================================================
1026 //==============================================================================
1029 extern __at(0x0F88) __sfr PORTJ
;
1058 extern __at(0x0F88) volatile __PORTJbits_t PORTJbits
;
1060 #define _PORTJ_RJ0 0x01
1061 #define _PORTJ_ALE 0x01
1062 #define _PORTJ_RJ1 0x02
1063 #define _PORTJ_OE 0x02
1064 #define _PORTJ_RJ2 0x04
1065 #define _PORTJ_WRL 0x04
1066 #define _PORTJ_RJ3 0x08
1067 #define _PORTJ_WRH 0x08
1068 #define _PORTJ_RJ4 0x10
1069 #define _PORTJ_BA0 0x10
1070 #define _PORTJ_RJ5 0x20
1071 #define _PORTJ_CE 0x20
1072 #define _PORTJ_RJ6 0x40
1073 #define _PORTJ_LB 0x40
1074 #define _PORTJ_RJ7 0x80
1075 #define _PORTJ_UB 0x80
1077 //==============================================================================
1080 //==============================================================================
1083 extern __at(0x0F89) __sfr LATA
;
1106 extern __at(0x0F89) volatile __LATAbits_t LATAbits
;
1116 //==============================================================================
1119 //==============================================================================
1122 extern __at(0x0F8A) __sfr LATB
;
1136 extern __at(0x0F8A) volatile __LATBbits_t LATBbits
;
1147 //==============================================================================
1150 //==============================================================================
1153 extern __at(0x0F8B) __sfr LATC
;
1167 extern __at(0x0F8B) volatile __LATCbits_t LATCbits
;
1178 //==============================================================================
1181 //==============================================================================
1184 extern __at(0x0F8C) __sfr LATD
;
1198 extern __at(0x0F8C) volatile __LATDbits_t LATDbits
;
1209 //==============================================================================
1212 //==============================================================================
1215 extern __at(0x0F8D) __sfr LATE
;
1229 extern __at(0x0F8D) volatile __LATEbits_t LATEbits
;
1240 //==============================================================================
1243 //==============================================================================
1246 extern __at(0x0F8E) __sfr LATF
;
1260 extern __at(0x0F8E) volatile __LATFbits_t LATFbits
;
1271 //==============================================================================
1274 //==============================================================================
1277 extern __at(0x0F8F) __sfr LATG
;
1300 extern __at(0x0F8F) volatile __LATGbits_t LATGbits
;
1308 //==============================================================================
1311 //==============================================================================
1314 extern __at(0x0F90) __sfr LATH
;
1328 extern __at(0x0F90) volatile __LATHbits_t LATHbits
;
1339 //==============================================================================
1342 //==============================================================================
1345 extern __at(0x0F91) __sfr LATJ
;
1359 extern __at(0x0F91) volatile __LATJbits_t LATJbits
;
1370 //==============================================================================
1373 //==============================================================================
1376 extern __at(0x0F92) __sfr DDRA
;
1382 unsigned TRISA0
: 1;
1383 unsigned TRISA1
: 1;
1384 unsigned TRISA2
: 1;
1385 unsigned TRISA3
: 1;
1386 unsigned TRISA4
: 1;
1387 unsigned TRISA5
: 1;
1388 unsigned TRISA6
: 1;
1417 extern __at(0x0F92) volatile __DDRAbits_t DDRAbits
;
1419 #define _TRISA0 0x01
1421 #define _TRISA1 0x02
1423 #define _TRISA2 0x04
1425 #define _TRISA3 0x08
1427 #define _TRISA4 0x10
1429 #define _TRISA5 0x20
1431 #define _TRISA6 0x40
1434 //==============================================================================
1437 //==============================================================================
1440 extern __at(0x0F92) __sfr TRISA
;
1446 unsigned TRISA0
: 1;
1447 unsigned TRISA1
: 1;
1448 unsigned TRISA2
: 1;
1449 unsigned TRISA3
: 1;
1450 unsigned TRISA4
: 1;
1451 unsigned TRISA5
: 1;
1452 unsigned TRISA6
: 1;
1481 extern __at(0x0F92) volatile __TRISAbits_t TRISAbits
;
1483 #define _TRISA_TRISA0 0x01
1484 #define _TRISA_RA0 0x01
1485 #define _TRISA_TRISA1 0x02
1486 #define _TRISA_RA1 0x02
1487 #define _TRISA_TRISA2 0x04
1488 #define _TRISA_RA2 0x04
1489 #define _TRISA_TRISA3 0x08
1490 #define _TRISA_RA3 0x08
1491 #define _TRISA_TRISA4 0x10
1492 #define _TRISA_RA4 0x10
1493 #define _TRISA_TRISA5 0x20
1494 #define _TRISA_RA5 0x20
1495 #define _TRISA_TRISA6 0x40
1496 #define _TRISA_RA6 0x40
1498 //==============================================================================
1501 //==============================================================================
1504 extern __at(0x0F93) __sfr DDRB
;
1510 unsigned TRISB0
: 1;
1511 unsigned TRISB1
: 1;
1512 unsigned TRISB2
: 1;
1513 unsigned TRISB3
: 1;
1514 unsigned TRISB4
: 1;
1515 unsigned TRISB5
: 1;
1516 unsigned TRISB6
: 1;
1517 unsigned TRISB7
: 1;
1533 extern __at(0x0F93) volatile __DDRBbits_t DDRBbits
;
1535 #define _TRISB0 0x01
1537 #define _TRISB1 0x02
1539 #define _TRISB2 0x04
1541 #define _TRISB3 0x08
1543 #define _TRISB4 0x10
1545 #define _TRISB5 0x20
1547 #define _TRISB6 0x40
1549 #define _TRISB7 0x80
1552 //==============================================================================
1555 //==============================================================================
1558 extern __at(0x0F93) __sfr TRISB
;
1564 unsigned TRISB0
: 1;
1565 unsigned TRISB1
: 1;
1566 unsigned TRISB2
: 1;
1567 unsigned TRISB3
: 1;
1568 unsigned TRISB4
: 1;
1569 unsigned TRISB5
: 1;
1570 unsigned TRISB6
: 1;
1571 unsigned TRISB7
: 1;
1587 extern __at(0x0F93) volatile __TRISBbits_t TRISBbits
;
1589 #define _TRISB_TRISB0 0x01
1590 #define _TRISB_RB0 0x01
1591 #define _TRISB_TRISB1 0x02
1592 #define _TRISB_RB1 0x02
1593 #define _TRISB_TRISB2 0x04
1594 #define _TRISB_RB2 0x04
1595 #define _TRISB_TRISB3 0x08
1596 #define _TRISB_RB3 0x08
1597 #define _TRISB_TRISB4 0x10
1598 #define _TRISB_RB4 0x10
1599 #define _TRISB_TRISB5 0x20
1600 #define _TRISB_RB5 0x20
1601 #define _TRISB_TRISB6 0x40
1602 #define _TRISB_RB6 0x40
1603 #define _TRISB_TRISB7 0x80
1604 #define _TRISB_RB7 0x80
1606 //==============================================================================
1609 //==============================================================================
1612 extern __at(0x0F94) __sfr DDRC
;
1618 unsigned TRISC0
: 1;
1619 unsigned TRISC1
: 1;
1620 unsigned TRISC2
: 1;
1621 unsigned TRISC3
: 1;
1622 unsigned TRISC4
: 1;
1623 unsigned TRISC5
: 1;
1624 unsigned TRISC6
: 1;
1625 unsigned TRISC7
: 1;
1641 extern __at(0x0F94) volatile __DDRCbits_t DDRCbits
;
1643 #define _TRISC0 0x01
1645 #define _TRISC1 0x02
1647 #define _TRISC2 0x04
1649 #define _TRISC3 0x08
1651 #define _TRISC4 0x10
1653 #define _TRISC5 0x20
1655 #define _TRISC6 0x40
1657 #define _TRISC7 0x80
1660 //==============================================================================
1663 //==============================================================================
1666 extern __at(0x0F94) __sfr TRISC
;
1672 unsigned TRISC0
: 1;
1673 unsigned TRISC1
: 1;
1674 unsigned TRISC2
: 1;
1675 unsigned TRISC3
: 1;
1676 unsigned TRISC4
: 1;
1677 unsigned TRISC5
: 1;
1678 unsigned TRISC6
: 1;
1679 unsigned TRISC7
: 1;
1695 extern __at(0x0F94) volatile __TRISCbits_t TRISCbits
;
1697 #define _TRISC_TRISC0 0x01
1698 #define _TRISC_RC0 0x01
1699 #define _TRISC_TRISC1 0x02
1700 #define _TRISC_RC1 0x02
1701 #define _TRISC_TRISC2 0x04
1702 #define _TRISC_RC2 0x04
1703 #define _TRISC_TRISC3 0x08
1704 #define _TRISC_RC3 0x08
1705 #define _TRISC_TRISC4 0x10
1706 #define _TRISC_RC4 0x10
1707 #define _TRISC_TRISC5 0x20
1708 #define _TRISC_RC5 0x20
1709 #define _TRISC_TRISC6 0x40
1710 #define _TRISC_RC6 0x40
1711 #define _TRISC_TRISC7 0x80
1712 #define _TRISC_RC7 0x80
1714 //==============================================================================
1717 //==============================================================================
1720 extern __at(0x0F95) __sfr DDRD
;
1726 unsigned TRISD0
: 1;
1727 unsigned TRISD1
: 1;
1728 unsigned TRISD2
: 1;
1729 unsigned TRISD3
: 1;
1730 unsigned TRISD4
: 1;
1731 unsigned TRISD5
: 1;
1732 unsigned TRISD6
: 1;
1733 unsigned TRISD7
: 1;
1749 extern __at(0x0F95) volatile __DDRDbits_t DDRDbits
;
1751 #define _TRISD0 0x01
1753 #define _TRISD1 0x02
1755 #define _TRISD2 0x04
1757 #define _TRISD3 0x08
1759 #define _TRISD4 0x10
1761 #define _TRISD5 0x20
1763 #define _TRISD6 0x40
1765 #define _TRISD7 0x80
1768 //==============================================================================
1771 //==============================================================================
1774 extern __at(0x0F95) __sfr TRISD
;
1780 unsigned TRISD0
: 1;
1781 unsigned TRISD1
: 1;
1782 unsigned TRISD2
: 1;
1783 unsigned TRISD3
: 1;
1784 unsigned TRISD4
: 1;
1785 unsigned TRISD5
: 1;
1786 unsigned TRISD6
: 1;
1787 unsigned TRISD7
: 1;
1803 extern __at(0x0F95) volatile __TRISDbits_t TRISDbits
;
1805 #define _TRISD_TRISD0 0x01
1806 #define _TRISD_RD0 0x01
1807 #define _TRISD_TRISD1 0x02
1808 #define _TRISD_RD1 0x02
1809 #define _TRISD_TRISD2 0x04
1810 #define _TRISD_RD2 0x04
1811 #define _TRISD_TRISD3 0x08
1812 #define _TRISD_RD3 0x08
1813 #define _TRISD_TRISD4 0x10
1814 #define _TRISD_RD4 0x10
1815 #define _TRISD_TRISD5 0x20
1816 #define _TRISD_RD5 0x20
1817 #define _TRISD_TRISD6 0x40
1818 #define _TRISD_RD6 0x40
1819 #define _TRISD_TRISD7 0x80
1820 #define _TRISD_RD7 0x80
1822 //==============================================================================
1825 //==============================================================================
1828 extern __at(0x0F96) __sfr DDRE
;
1834 unsigned TRISE0
: 1;
1835 unsigned TRISE1
: 1;
1836 unsigned TRISE2
: 1;
1837 unsigned TRISE3
: 1;
1838 unsigned TRISE4
: 1;
1839 unsigned TRISE5
: 1;
1840 unsigned TRISE6
: 1;
1841 unsigned TRISE7
: 1;
1857 extern __at(0x0F96) volatile __DDREbits_t DDREbits
;
1859 #define _TRISE0 0x01
1861 #define _TRISE1 0x02
1863 #define _TRISE2 0x04
1865 #define _TRISE3 0x08
1867 #define _TRISE4 0x10
1869 #define _TRISE5 0x20
1871 #define _TRISE6 0x40
1873 #define _TRISE7 0x80
1876 //==============================================================================
1879 //==============================================================================
1882 extern __at(0x0F96) __sfr TRISE
;
1888 unsigned TRISE0
: 1;
1889 unsigned TRISE1
: 1;
1890 unsigned TRISE2
: 1;
1891 unsigned TRISE3
: 1;
1892 unsigned TRISE4
: 1;
1893 unsigned TRISE5
: 1;
1894 unsigned TRISE6
: 1;
1895 unsigned TRISE7
: 1;
1911 extern __at(0x0F96) volatile __TRISEbits_t TRISEbits
;
1913 #define _TRISE_TRISE0 0x01
1914 #define _TRISE_RE0 0x01
1915 #define _TRISE_TRISE1 0x02
1916 #define _TRISE_RE1 0x02
1917 #define _TRISE_TRISE2 0x04
1918 #define _TRISE_RE2 0x04
1919 #define _TRISE_TRISE3 0x08
1920 #define _TRISE_RE3 0x08
1921 #define _TRISE_TRISE4 0x10
1922 #define _TRISE_RE4 0x10
1923 #define _TRISE_TRISE5 0x20
1924 #define _TRISE_RE5 0x20
1925 #define _TRISE_TRISE6 0x40
1926 #define _TRISE_RE6 0x40
1927 #define _TRISE_TRISE7 0x80
1928 #define _TRISE_RE7 0x80
1930 //==============================================================================
1933 //==============================================================================
1936 extern __at(0x0F97) __sfr DDRF
;
1942 unsigned TRISF0
: 1;
1943 unsigned TRISF1
: 1;
1944 unsigned TRISF2
: 1;
1945 unsigned TRISF3
: 1;
1946 unsigned TRISF4
: 1;
1947 unsigned TRISF5
: 1;
1948 unsigned TRISF6
: 1;
1949 unsigned TRISF7
: 1;
1965 extern __at(0x0F97) volatile __DDRFbits_t DDRFbits
;
1967 #define _TRISF0 0x01
1969 #define _TRISF1 0x02
1971 #define _TRISF2 0x04
1973 #define _TRISF3 0x08
1975 #define _TRISF4 0x10
1977 #define _TRISF5 0x20
1979 #define _TRISF6 0x40
1981 #define _TRISF7 0x80
1984 //==============================================================================
1987 //==============================================================================
1990 extern __at(0x0F97) __sfr TRISF
;
1996 unsigned TRISF0
: 1;
1997 unsigned TRISF1
: 1;
1998 unsigned TRISF2
: 1;
1999 unsigned TRISF3
: 1;
2000 unsigned TRISF4
: 1;
2001 unsigned TRISF5
: 1;
2002 unsigned TRISF6
: 1;
2003 unsigned TRISF7
: 1;
2019 extern __at(0x0F97) volatile __TRISFbits_t TRISFbits
;
2021 #define _TRISF_TRISF0 0x01
2022 #define _TRISF_RF0 0x01
2023 #define _TRISF_TRISF1 0x02
2024 #define _TRISF_RF1 0x02
2025 #define _TRISF_TRISF2 0x04
2026 #define _TRISF_RF2 0x04
2027 #define _TRISF_TRISF3 0x08
2028 #define _TRISF_RF3 0x08
2029 #define _TRISF_TRISF4 0x10
2030 #define _TRISF_RF4 0x10
2031 #define _TRISF_TRISF5 0x20
2032 #define _TRISF_RF5 0x20
2033 #define _TRISF_TRISF6 0x40
2034 #define _TRISF_RF6 0x40
2035 #define _TRISF_TRISF7 0x80
2036 #define _TRISF_RF7 0x80
2038 //==============================================================================
2041 //==============================================================================
2044 extern __at(0x0F98) __sfr DDRG
;
2050 unsigned TRISG0
: 1;
2051 unsigned TRISG1
: 1;
2052 unsigned TRISG2
: 1;
2053 unsigned TRISG3
: 1;
2054 unsigned TRISG4
: 1;
2085 extern __at(0x0F98) volatile __DDRGbits_t DDRGbits
;
2087 #define _TRISG0 0x01
2089 #define _TRISG1 0x02
2091 #define _TRISG2 0x04
2093 #define _TRISG3 0x08
2095 #define _TRISG4 0x10
2098 //==============================================================================
2101 //==============================================================================
2104 extern __at(0x0F98) __sfr TRISG
;
2110 unsigned TRISG0
: 1;
2111 unsigned TRISG1
: 1;
2112 unsigned TRISG2
: 1;
2113 unsigned TRISG3
: 1;
2114 unsigned TRISG4
: 1;
2145 extern __at(0x0F98) volatile __TRISGbits_t TRISGbits
;
2147 #define _TRISG_TRISG0 0x01
2148 #define _TRISG_RG0 0x01
2149 #define _TRISG_TRISG1 0x02
2150 #define _TRISG_RG1 0x02
2151 #define _TRISG_TRISG2 0x04
2152 #define _TRISG_RG2 0x04
2153 #define _TRISG_TRISG3 0x08
2154 #define _TRISG_RG3 0x08
2155 #define _TRISG_TRISG4 0x10
2156 #define _TRISG_RG4 0x10
2158 //==============================================================================
2161 //==============================================================================
2164 extern __at(0x0F99) __sfr DDRH
;
2170 unsigned TRISH0
: 1;
2171 unsigned TRISH1
: 1;
2172 unsigned TRISH2
: 1;
2173 unsigned TRISH3
: 1;
2174 unsigned TRISH4
: 1;
2175 unsigned TRISH5
: 1;
2176 unsigned TRISH6
: 1;
2177 unsigned TRISH7
: 1;
2193 extern __at(0x0F99) volatile __DDRHbits_t DDRHbits
;
2195 #define _TRISH0 0x01
2197 #define _TRISH1 0x02
2199 #define _TRISH2 0x04
2201 #define _TRISH3 0x08
2203 #define _TRISH4 0x10
2205 #define _TRISH5 0x20
2207 #define _TRISH6 0x40
2209 #define _TRISH7 0x80
2212 //==============================================================================
2215 //==============================================================================
2218 extern __at(0x0F99) __sfr TRISH
;
2224 unsigned TRISH0
: 1;
2225 unsigned TRISH1
: 1;
2226 unsigned TRISH2
: 1;
2227 unsigned TRISH3
: 1;
2228 unsigned TRISH4
: 1;
2229 unsigned TRISH5
: 1;
2230 unsigned TRISH6
: 1;
2231 unsigned TRISH7
: 1;
2247 extern __at(0x0F99) volatile __TRISHbits_t TRISHbits
;
2249 #define _TRISH_TRISH0 0x01
2250 #define _TRISH_RH0 0x01
2251 #define _TRISH_TRISH1 0x02
2252 #define _TRISH_RH1 0x02
2253 #define _TRISH_TRISH2 0x04
2254 #define _TRISH_RH2 0x04
2255 #define _TRISH_TRISH3 0x08
2256 #define _TRISH_RH3 0x08
2257 #define _TRISH_TRISH4 0x10
2258 #define _TRISH_RH4 0x10
2259 #define _TRISH_TRISH5 0x20
2260 #define _TRISH_RH5 0x20
2261 #define _TRISH_TRISH6 0x40
2262 #define _TRISH_RH6 0x40
2263 #define _TRISH_TRISH7 0x80
2264 #define _TRISH_RH7 0x80
2266 //==============================================================================
2269 //==============================================================================
2272 extern __at(0x0F9A) __sfr DDRJ
;
2278 unsigned TRISJ0
: 1;
2279 unsigned TRISJ1
: 1;
2280 unsigned TRISJ2
: 1;
2281 unsigned TRISJ3
: 1;
2282 unsigned TRISJ4
: 1;
2283 unsigned TRISJ5
: 1;
2284 unsigned TRISJ6
: 1;
2285 unsigned TRISJ7
: 1;
2301 extern __at(0x0F9A) volatile __DDRJbits_t DDRJbits
;
2303 #define _TRISJ0 0x01
2305 #define _TRISJ1 0x02
2307 #define _TRISJ2 0x04
2309 #define _TRISJ3 0x08
2311 #define _TRISJ4 0x10
2313 #define _TRISJ5 0x20
2315 #define _TRISJ6 0x40
2317 #define _TRISJ7 0x80
2320 //==============================================================================
2323 //==============================================================================
2326 extern __at(0x0F9A) __sfr TRISJ
;
2332 unsigned TRISJ0
: 1;
2333 unsigned TRISJ1
: 1;
2334 unsigned TRISJ2
: 1;
2335 unsigned TRISJ3
: 1;
2336 unsigned TRISJ4
: 1;
2337 unsigned TRISJ5
: 1;
2338 unsigned TRISJ6
: 1;
2339 unsigned TRISJ7
: 1;
2355 extern __at(0x0F9A) volatile __TRISJbits_t TRISJbits
;
2357 #define _TRISJ_TRISJ0 0x01
2358 #define _TRISJ_RJ0 0x01
2359 #define _TRISJ_TRISJ1 0x02
2360 #define _TRISJ_RJ1 0x02
2361 #define _TRISJ_TRISJ2 0x04
2362 #define _TRISJ_RJ2 0x04
2363 #define _TRISJ_TRISJ3 0x08
2364 #define _TRISJ_RJ3 0x08
2365 #define _TRISJ_TRISJ4 0x10
2366 #define _TRISJ_RJ4 0x10
2367 #define _TRISJ_TRISJ5 0x20
2368 #define _TRISJ_RJ5 0x20
2369 #define _TRISJ_TRISJ6 0x40
2370 #define _TRISJ_RJ6 0x40
2371 #define _TRISJ_TRISJ7 0x80
2372 #define _TRISJ_RJ7 0x80
2374 //==============================================================================
2377 //==============================================================================
2380 extern __at(0x0F9C) __sfr MEMCON
;
2410 extern __at(0x0F9C) volatile __MEMCONbits_t MEMCONbits
;
2418 //==============================================================================
2421 //==============================================================================
2424 extern __at(0x0F9D) __sfr PIE1
;
2430 unsigned TMR1IE
: 1;
2431 unsigned TMR2IE
: 1;
2432 unsigned CCP1IE
: 1;
2453 extern __at(0x0F9D) volatile __PIE1bits_t PIE1bits
;
2455 #define _TMR1IE 0x01
2456 #define _TMR2IE 0x02
2457 #define _CCP1IE 0x04
2466 //==============================================================================
2469 //==============================================================================
2472 extern __at(0x0F9E) __sfr PIR1
;
2478 unsigned TMR1IF
: 1;
2479 unsigned TMR2IF
: 1;
2480 unsigned CCP1IF
: 1;
2501 extern __at(0x0F9E) volatile __PIR1bits_t PIR1bits
;
2503 #define _TMR1IF 0x01
2504 #define _TMR2IF 0x02
2505 #define _CCP1IF 0x04
2514 //==============================================================================
2517 //==============================================================================
2520 extern __at(0x0F9F) __sfr IPR1
;
2526 unsigned TMR1IP
: 1;
2527 unsigned TMR2IP
: 1;
2528 unsigned CCP1IP
: 1;
2549 extern __at(0x0F9F) volatile __IPR1bits_t IPR1bits
;
2551 #define _TMR1IP 0x01
2552 #define _TMR2IP 0x02
2553 #define _CCP1IP 0x04
2562 //==============================================================================
2565 //==============================================================================
2568 extern __at(0x0FA0) __sfr PIE2
;
2572 unsigned CCP2IE
: 1;
2573 unsigned TMR3IE
: 1;
2582 extern __at(0x0FA0) volatile __PIE2bits_t PIE2bits
;
2584 #define _CCP2IE 0x01
2585 #define _TMR3IE 0x02
2591 //==============================================================================
2594 //==============================================================================
2597 extern __at(0x0FA1) __sfr PIR2
;
2601 unsigned CCP2IF
: 1;
2602 unsigned TMR3IF
: 1;
2611 extern __at(0x0FA1) volatile __PIR2bits_t PIR2bits
;
2613 #define _CCP2IF 0x01
2614 #define _TMR3IF 0x02
2620 //==============================================================================
2623 //==============================================================================
2626 extern __at(0x0FA2) __sfr IPR2
;
2630 unsigned CCP2IP
: 1;
2631 unsigned TMR3IP
: 1;
2640 extern __at(0x0FA2) volatile __IPR2bits_t IPR2bits
;
2642 #define _CCP2IP 0x01
2643 #define _TMR3IP 0x02
2649 //==============================================================================
2652 //==============================================================================
2655 extern __at(0x0FA3) __sfr PIE3
;
2659 unsigned CCP3IE
: 1;
2660 unsigned CCP4IE
: 1;
2661 unsigned CCP5IE
: 1;
2662 unsigned TMR4IE
: 1;
2669 extern __at(0x0FA3) volatile __PIE3bits_t PIE3bits
;
2671 #define _CCP3IE 0x01
2672 #define _CCP4IE 0x02
2673 #define _CCP5IE 0x04
2674 #define _TMR4IE 0x08
2678 //==============================================================================
2681 //==============================================================================
2684 extern __at(0x0FA4) __sfr PIR3
;
2688 unsigned CCP3IF
: 1;
2689 unsigned CCP4IF
: 1;
2690 unsigned CCP5IF
: 1;
2691 unsigned TMR4IF
: 1;
2698 extern __at(0x0FA4) volatile __PIR3bits_t PIR3bits
;
2700 #define _CCP3IF 0x01
2701 #define _CCP4IF 0x02
2702 #define _CCP5IF 0x04
2703 #define _TMR4IF 0x08
2707 //==============================================================================
2710 //==============================================================================
2713 extern __at(0x0FA5) __sfr IPR3
;
2717 unsigned CCP3IP
: 1;
2718 unsigned CCP4IP
: 1;
2719 unsigned CCP5IP
: 1;
2720 unsigned TMR4IP
: 1;
2727 extern __at(0x0FA5) volatile __IPR3bits_t IPR3bits
;
2729 #define _CCP3IP 0x01
2730 #define _CCP4IP 0x02
2731 #define _CCP5IP 0x04
2732 #define _TMR4IP 0x08
2736 //==============================================================================
2739 //==============================================================================
2742 extern __at(0x0FA6) __sfr EECON1
;
2771 extern __at(0x0FA6) volatile __EECON1bits_t EECON1bits
;
2782 //==============================================================================
2784 extern __at(0x0FA7) __sfr EECON2
;
2785 extern __at(0x0FA8) __sfr EEDATA
;
2786 extern __at(0x0FA9) __sfr EEADR
;
2787 extern __at(0x0FAA) __sfr EEADRH
;
2789 //==============================================================================
2792 extern __at(0x0FAB) __sfr RCSTA
;
2825 unsigned ADDEN1
: 1;
2828 unsigned NOT_RC8
: 1;
2857 extern __at(0x0FAB) volatile __RCSTAbits_t RCSTAbits
;
2868 #define _ADDEN1 0x08
2875 #define _NOT_RC8 0x40
2881 //==============================================================================
2884 //==============================================================================
2887 extern __at(0x0FAB) __sfr RCSTA1
;
2920 unsigned ADDEN1
: 1;
2923 unsigned NOT_RC8
: 1;
2952 extern __at(0x0FAB) volatile __RCSTA1bits_t RCSTA1bits
;
2954 #define _RCSTA1_RX9D 0x01
2955 #define _RCSTA1_RCD8 0x01
2956 #define _RCSTA1_RX9D1 0x01
2957 #define _RCSTA1_OERR 0x02
2958 #define _RCSTA1_OERR1 0x02
2959 #define _RCSTA1_FERR 0x04
2960 #define _RCSTA1_FERR1 0x04
2961 #define _RCSTA1_ADDEN 0x08
2962 #define _RCSTA1_ADEN 0x08
2963 #define _RCSTA1_ADDEN1 0x08
2964 #define _RCSTA1_CREN 0x10
2965 #define _RCSTA1_CREN1 0x10
2966 #define _RCSTA1_SREN 0x20
2967 #define _RCSTA1_SREN1 0x20
2968 #define _RCSTA1_RX9 0x40
2969 #define _RCSTA1_RC9 0x40
2970 #define _RCSTA1_NOT_RC8 0x40
2971 #define _RCSTA1_RC8_9 0x40
2972 #define _RCSTA1_RX91 0x40
2973 #define _RCSTA1_SPEN 0x80
2974 #define _RCSTA1_SPEN1 0x80
2976 //==============================================================================
2979 //==============================================================================
2982 extern __at(0x0FAC) __sfr TXSTA
;
2991 unsigned SENDB1
: 1;
3018 unsigned NOT_TX8
: 1;
3035 extern __at(0x0FAC) volatile __TXSTAbits_t TXSTAbits
;
3044 #define _SENDB1 0x08
3051 #define _NOT_TX8 0x40
3056 //==============================================================================
3059 //==============================================================================
3062 extern __at(0x0FAC) __sfr TXSTA1
;
3071 unsigned SENDB1
: 1;
3098 unsigned NOT_TX8
: 1;
3115 extern __at(0x0FAC) volatile __TXSTA1bits_t TXSTA1bits
;
3117 #define _TXSTA1_TX9D 0x01
3118 #define _TXSTA1_TXD8 0x01
3119 #define _TXSTA1_TX9D1 0x01
3120 #define _TXSTA1_TRMT 0x02
3121 #define _TXSTA1_TRMT1 0x02
3122 #define _TXSTA1_BRGH 0x04
3123 #define _TXSTA1_BRGH1 0x04
3124 #define _TXSTA1_SENDB1 0x08
3125 #define _TXSTA1_SYNC 0x10
3126 #define _TXSTA1_SYNC1 0x10
3127 #define _TXSTA1_TXEN 0x20
3128 #define _TXSTA1_TXEN1 0x20
3129 #define _TXSTA1_TX9 0x40
3130 #define _TXSTA1_TX8_9 0x40
3131 #define _TXSTA1_NOT_TX8 0x40
3132 #define _TXSTA1_TX91 0x40
3133 #define _TXSTA1_CSRC 0x80
3134 #define _TXSTA1_CSRC1 0x80
3136 //==============================================================================
3138 extern __at(0x0FAD) __sfr TXREG
;
3139 extern __at(0x0FAD) __sfr TXREG1
;
3140 extern __at(0x0FAE) __sfr RCREG
;
3141 extern __at(0x0FAE) __sfr RCREG1
;
3142 extern __at(0x0FAF) __sfr SPBRG
;
3143 extern __at(0x0FAF) __sfr SPBRG1
;
3145 //==============================================================================
3148 extern __at(0x0FB0) __sfr PSPCON
;
3156 unsigned PSPMODE
: 1;
3162 extern __at(0x0FB0) volatile __PSPCONbits_t PSPCONbits
;
3164 #define _PSPMODE 0x10
3169 //==============================================================================
3172 //==============================================================================
3175 extern __at(0x0FB1) __sfr T3CON
;
3181 unsigned TMR3ON
: 1;
3182 unsigned TMR3CS
: 1;
3183 unsigned NOT_T3SYNC
: 1;
3184 unsigned T3CCP1
: 1;
3185 unsigned T3CKPS0
: 1;
3186 unsigned T3CKPS1
: 1;
3187 unsigned T3CCP2
: 1;
3195 unsigned T3SYNC
: 1;
3207 unsigned T3INSYNC
: 1;
3219 unsigned T3NSYNC
: 1;
3230 unsigned T3CKPS
: 2;
3235 extern __at(0x0FB1) volatile __T3CONbits_t T3CONbits
;
3237 #define _T3CON_TMR3ON 0x01
3238 #define _T3CON_TMR3CS 0x02
3239 #define _T3CON_NOT_T3SYNC 0x04
3240 #define _T3CON_T3SYNC 0x04
3241 #define _T3CON_T3INSYNC 0x04
3242 #define _T3CON_T3NSYNC 0x04
3243 #define _T3CON_T3CCP1 0x08
3244 #define _T3CON_T3CKPS0 0x10
3245 #define _T3CON_T3CKPS1 0x20
3246 #define _T3CON_T3CCP2 0x40
3247 #define _T3CON_RD16 0x80
3249 //==============================================================================
3251 extern __at(0x0FB2) __sfr TMR3
;
3252 extern __at(0x0FB2) __sfr TMR3L
;
3253 extern __at(0x0FB3) __sfr TMR3H
;
3255 //==============================================================================
3258 extern __at(0x0FB4) __sfr CMCON
;
3281 extern __at(0x0FB4) volatile __CMCONbits_t CMCONbits
;
3292 //==============================================================================
3295 //==============================================================================
3298 extern __at(0x0FB5) __sfr CVRCON
;
3333 extern __at(0x0FB5) volatile __CVRCONbits_t CVRCONbits
;
3345 //==============================================================================
3348 //==============================================================================
3351 extern __at(0x0FB7) __sfr CCP3CON
;
3357 unsigned CCP3M0
: 1;
3358 unsigned CCP3M1
: 1;
3359 unsigned CCP3M2
: 1;
3360 unsigned CCP3M3
: 1;
3373 unsigned DCCP3Y
: 1;
3374 unsigned DCCP3X
: 1;
3393 extern __at(0x0FB7) volatile __CCP3CONbits_t CCP3CONbits
;
3395 #define _CCP3M0 0x01
3396 #define _CCP3M1 0x02
3397 #define _CCP3M2 0x04
3398 #define _CCP3M3 0x08
3400 #define _DCCP3Y 0x10
3402 #define _DCCP3X 0x20
3404 //==============================================================================
3406 extern __at(0x0FB8) __sfr CCPR3
;
3407 extern __at(0x0FB8) __sfr CCPR3L
;
3408 extern __at(0x0FB9) __sfr CCPR3H
;
3410 //==============================================================================
3413 extern __at(0x0FBA) __sfr CCP2CON
;
3419 unsigned CCP2M0
: 1;
3420 unsigned CCP2M1
: 1;
3421 unsigned CCP2M2
: 1;
3422 unsigned CCP2M3
: 1;
3447 unsigned DCCP2Y
: 1;
3448 unsigned DCCP2X
: 1;
3467 extern __at(0x0FBA) volatile __CCP2CONbits_t CCP2CONbits
;
3469 #define _CCP2M0 0x01
3470 #define _CCP2M1 0x02
3471 #define _CCP2M2 0x04
3472 #define _CCP2M3 0x08
3475 #define _DCCP2Y 0x10
3478 #define _DCCP2X 0x20
3480 //==============================================================================
3482 extern __at(0x0FBB) __sfr CCPR2
;
3483 extern __at(0x0FBB) __sfr CCPR2L
;
3484 extern __at(0x0FBC) __sfr CCPR2H
;
3486 //==============================================================================
3489 extern __at(0x0FBD) __sfr CCP1CON
;
3495 unsigned CCP1M0
: 1;
3496 unsigned CCP1M1
: 1;
3497 unsigned CCP1M2
: 1;
3498 unsigned CCP1M3
: 1;
3523 unsigned DCCP1Y
: 1;
3524 unsigned DCCP1X
: 1;
3543 extern __at(0x0FBD) volatile __CCP1CONbits_t CCP1CONbits
;
3545 #define _CCP1M0 0x01
3546 #define _CCP1M1 0x02
3547 #define _CCP1M2 0x04
3548 #define _CCP1M3 0x08
3551 #define _DCCP1Y 0x10
3554 #define _DCCP1X 0x20
3556 //==============================================================================
3558 extern __at(0x0FBE) __sfr CCPR1
;
3559 extern __at(0x0FBE) __sfr CCPR1L
;
3560 extern __at(0x0FBF) __sfr CCPR1H
;
3562 //==============================================================================
3565 extern __at(0x0FC0) __sfr ADCON2
;
3588 extern __at(0x0FC0) volatile __ADCON2bits_t ADCON2bits
;
3595 //==============================================================================
3598 //==============================================================================
3601 extern __at(0x0FC1) __sfr ADCON1
;
3631 extern __at(0x0FC1) volatile __ADCON1bits_t ADCON1bits
;
3640 //==============================================================================
3643 //==============================================================================
3646 extern __at(0x0FC2) __sfr ADCON0
;
3653 unsigned GO_NOT_DONE
: 1;
3677 unsigned GO_DONE
: 1;
3701 unsigned NOT_DONE
: 1;
3713 unsigned GODONE
: 1;
3730 extern __at(0x0FC2) volatile __ADCON0bits_t ADCON0bits
;
3733 #define _GO_NOT_DONE 0x02
3735 #define _GO_DONE 0x02
3737 #define _NOT_DONE 0x02
3738 #define _GODONE 0x02
3744 //==============================================================================
3746 extern __at(0x0FC3) __sfr ADRES
;
3747 extern __at(0x0FC3) __sfr ADRESL
;
3748 extern __at(0x0FC4) __sfr ADRESH
;
3750 //==============================================================================
3753 extern __at(0x0FC5) __sfr SSPCON2
;
3763 unsigned ACKSTAT
: 1;
3767 extern __at(0x0FC5) volatile __SSPCON2bits_t SSPCON2bits
;
3775 #define _ACKSTAT 0x40
3778 //==============================================================================
3781 //==============================================================================
3784 extern __at(0x0FC6) __sfr SSPCON1
;
3807 extern __at(0x0FC6) volatile __SSPCON1bits_t SSPCON1bits
;
3818 //==============================================================================
3821 //==============================================================================
3824 extern __at(0x0FC7) __sfr SSPSTAT
;
3832 unsigned R_NOT_W
: 1;
3835 unsigned D_NOT_A
: 1;
3845 unsigned I2C_START
: 1;
3846 unsigned I2C_STOP
: 1;
3856 unsigned I2C_READ
: 1;
3859 unsigned I2C_DAT
: 1;
3880 unsigned NOT_WRITE
: 1;
3883 unsigned NOT_ADDRESS
: 1;
3892 unsigned READ_WRITE
: 1;
3895 unsigned DATA_ADDRESS
: 1;
3913 extern __at(0x0FC7) volatile __SSPSTATbits_t SSPSTATbits
;
3917 #define _R_NOT_W 0x04
3919 #define _I2C_READ 0x04
3921 #define _NOT_WRITE 0x04
3922 #define _READ_WRITE 0x04
3925 #define _I2C_START 0x08
3927 #define _I2C_STOP 0x10
3928 #define _D_NOT_A 0x20
3930 #define _I2C_DAT 0x20
3932 #define _NOT_ADDRESS 0x20
3933 #define _DATA_ADDRESS 0x20
3938 //==============================================================================
3940 extern __at(0x0FC8) __sfr SSPADD
;
3941 extern __at(0x0FC9) __sfr SSPBUF
;
3943 //==============================================================================
3946 extern __at(0x0FCA) __sfr T2CON
;
3952 unsigned T2CKPS0
: 1;
3953 unsigned T2CKPS1
: 1;
3954 unsigned TMR2ON
: 1;
3955 unsigned T2OUTPS0
: 1;
3956 unsigned T2OUTPS1
: 1;
3957 unsigned T2OUTPS2
: 1;
3958 unsigned T2OUTPS3
: 1;
3964 unsigned T2CKPS
: 2;
3971 unsigned T2OUTPS
: 4;
3976 extern __at(0x0FCA) volatile __T2CONbits_t T2CONbits
;
3978 #define _T2CKPS0 0x01
3979 #define _T2CKPS1 0x02
3980 #define _TMR2ON 0x04
3981 #define _T2OUTPS0 0x08
3982 #define _T2OUTPS1 0x10
3983 #define _T2OUTPS2 0x20
3984 #define _T2OUTPS3 0x40
3986 //==============================================================================
3988 extern __at(0x0FCB) __sfr PR2
;
3989 extern __at(0x0FCC) __sfr TMR2
;
3991 //==============================================================================
3994 extern __at(0x0FCD) __sfr T1CON
;
4000 unsigned TMR1ON
: 1;
4001 unsigned TMR1CS
: 1;
4002 unsigned NOT_T1SYNC
: 1;
4003 unsigned T1OSCEN
: 1;
4004 unsigned T1CKPS0
: 1;
4005 unsigned T1CKPS1
: 1;
4014 unsigned T1SYNC
: 1;
4026 unsigned T1INSYNC
: 1;
4037 unsigned T1CKPS
: 2;
4042 extern __at(0x0FCD) volatile __T1CONbits_t T1CONbits
;
4044 #define _TMR1ON 0x01
4045 #define _TMR1CS 0x02
4046 #define _NOT_T1SYNC 0x04
4047 #define _T1SYNC 0x04
4048 #define _T1INSYNC 0x04
4049 #define _T1OSCEN 0x08
4050 #define _T1CKPS0 0x10
4051 #define _T1CKPS1 0x20
4054 //==============================================================================
4056 extern __at(0x0FCE) __sfr TMR1
;
4057 extern __at(0x0FCE) __sfr TMR1L
;
4058 extern __at(0x0FCF) __sfr TMR1H
;
4060 //==============================================================================
4063 extern __at(0x0FD0) __sfr RCON
;
4069 unsigned NOT_BOR
: 1;
4070 unsigned NOT_POR
: 1;
4071 unsigned NOT_PD
: 1;
4072 unsigned NOT_TO
: 1;
4073 unsigned NOT_RI
: 1;
4088 unsigned NOT_IPEN
: 1;
4092 extern __at(0x0FD0) volatile __RCONbits_t RCONbits
;
4094 #define _NOT_BOR 0x01
4096 #define _NOT_POR 0x02
4098 #define _NOT_PD 0x04
4100 #define _NOT_TO 0x08
4102 #define _NOT_RI 0x10
4105 #define _NOT_IPEN 0x80
4107 //==============================================================================
4110 //==============================================================================
4113 extern __at(0x0FD1) __sfr WDTCON
;
4119 unsigned SWDTEN
: 1;
4142 extern __at(0x0FD1) volatile __WDTCONbits_t WDTCONbits
;
4144 #define _SWDTEN 0x01
4147 //==============================================================================
4150 //==============================================================================
4153 extern __at(0x0FD2) __sfr LVDCON
;
4194 extern __at(0x0FD2) volatile __LVDCONbits_t LVDCONbits
;
4208 //==============================================================================
4211 //==============================================================================
4214 extern __at(0x0FD3) __sfr OSCCON
;
4228 extern __at(0x0FD3) volatile __OSCCONbits_t OSCCONbits
;
4232 //==============================================================================
4235 //==============================================================================
4238 extern __at(0x0FD5) __sfr T0CON
;
4250 unsigned T08BIT
: 1;
4251 unsigned TMR0ON
: 1;
4261 extern __at(0x0FD5) volatile __T0CONbits_t T0CONbits
;
4269 #define _T08BIT 0x40
4270 #define _TMR0ON 0x80
4272 //==============================================================================
4274 extern __at(0x0FD6) __sfr TMR0
;
4275 extern __at(0x0FD6) __sfr TMR0L
;
4276 extern __at(0x0FD7) __sfr TMR0H
;
4278 //==============================================================================
4281 extern __at(0x0FD8) __sfr STATUS
;
4295 extern __at(0x0FD8) volatile __STATUSbits_t STATUSbits
;
4303 //==============================================================================
4305 extern __at(0x0FD9) __sfr FSR2L
;
4306 extern __at(0x0FDA) __sfr FSR2H
;
4307 extern __at(0x0FDB) __sfr PLUSW2
;
4308 extern __at(0x0FDC) __sfr PREINC2
;
4309 extern __at(0x0FDD) __sfr POSTDEC2
;
4310 extern __at(0x0FDE) __sfr POSTINC2
;
4311 extern __at(0x0FDF) __sfr INDF2
;
4312 extern __at(0x0FE0) __sfr BSR
;
4313 extern __at(0x0FE1) __sfr FSR1L
;
4314 extern __at(0x0FE2) __sfr FSR1H
;
4315 extern __at(0x0FE3) __sfr PLUSW1
;
4316 extern __at(0x0FE4) __sfr PREINC1
;
4317 extern __at(0x0FE5) __sfr POSTDEC1
;
4318 extern __at(0x0FE6) __sfr POSTINC1
;
4319 extern __at(0x0FE7) __sfr INDF1
;
4320 extern __at(0x0FE8) __sfr WREG
;
4321 extern __at(0x0FE9) __sfr FSR0L
;
4322 extern __at(0x0FEA) __sfr FSR0H
;
4323 extern __at(0x0FEB) __sfr PLUSW0
;
4324 extern __at(0x0FEC) __sfr PREINC0
;
4325 extern __at(0x0FED) __sfr POSTDEC0
;
4326 extern __at(0x0FEE) __sfr POSTINC0
;
4327 extern __at(0x0FEF) __sfr INDF0
;
4329 //==============================================================================
4332 extern __at(0x0FF0) __sfr INTCON3
;
4338 unsigned INT1IF
: 1;
4339 unsigned INT2IF
: 1;
4340 unsigned INT3IF
: 1;
4341 unsigned INT1IE
: 1;
4342 unsigned INT2IE
: 1;
4343 unsigned INT3IE
: 1;
4344 unsigned INT1IP
: 1;
4345 unsigned INT2IP
: 1;
4361 extern __at(0x0FF0) volatile __INTCON3bits_t INTCON3bits
;
4363 #define _INT1IF 0x01
4365 #define _INT2IF 0x02
4367 #define _INT3IF 0x04
4369 #define _INT1IE 0x08
4371 #define _INT2IE 0x10
4373 #define _INT3IE 0x20
4375 #define _INT1IP 0x40
4377 #define _INT2IP 0x80
4380 //==============================================================================
4383 //==============================================================================
4386 extern __at(0x0FF1) __sfr INTCON2
;
4393 unsigned INT3IP
: 1;
4394 unsigned TMR0IP
: 1;
4395 unsigned INTEDG3
: 1;
4396 unsigned INTEDG2
: 1;
4397 unsigned INTEDG1
: 1;
4398 unsigned INTEDG0
: 1;
4399 unsigned NOT_RBPU
: 1;
4415 extern __at(0x0FF1) volatile __INTCON2bits_t INTCON2bits
;
4418 #define _INT3IP 0x02
4420 #define _TMR0IP 0x04
4422 #define _INTEDG3 0x08
4423 #define _INTEDG2 0x10
4424 #define _INTEDG1 0x20
4425 #define _INTEDG0 0x40
4426 #define _NOT_RBPU 0x80
4429 //==============================================================================
4432 //==============================================================================
4435 extern __at(0x0FF2) __sfr INTCON
;
4442 unsigned INT0IF
: 1;
4443 unsigned TMR0IF
: 1;
4445 unsigned INT0IE
: 1;
4446 unsigned TMR0IE
: 1;
4447 unsigned PEIE_GIEL
: 1;
4448 unsigned GIE_GIEH
: 1;
4476 extern __at(0x0FF2) volatile __INTCONbits_t INTCONbits
;
4479 #define _INT0IF 0x02
4481 #define _TMR0IF 0x04
4484 #define _INT0IE 0x10
4486 #define _TMR0IE 0x20
4488 #define _PEIE_GIEL 0x40
4491 #define _GIE_GIEH 0x80
4495 //==============================================================================
4498 //==============================================================================
4501 extern __at(0x0FF2) __sfr INTCON1
;
4508 unsigned INT0IF
: 1;
4509 unsigned TMR0IF
: 1;
4511 unsigned INT0IE
: 1;
4512 unsigned TMR0IE
: 1;
4513 unsigned PEIE_GIEL
: 1;
4514 unsigned GIE_GIEH
: 1;
4542 extern __at(0x0FF2) volatile __INTCON1bits_t INTCON1bits
;
4544 #define _INTCON1_RBIF 0x01
4545 #define _INTCON1_INT0IF 0x02
4546 #define _INTCON1_INT0F 0x02
4547 #define _INTCON1_TMR0IF 0x04
4548 #define _INTCON1_T0IF 0x04
4549 #define _INTCON1_RBIE 0x08
4550 #define _INTCON1_INT0IE 0x10
4551 #define _INTCON1_INT0E 0x10
4552 #define _INTCON1_TMR0IE 0x20
4553 #define _INTCON1_T0IE 0x20
4554 #define _INTCON1_PEIE_GIEL 0x40
4555 #define _INTCON1_PEIE 0x40
4556 #define _INTCON1_GIEL 0x40
4557 #define _INTCON1_GIE_GIEH 0x80
4558 #define _INTCON1_GIE 0x80
4559 #define _INTCON1_GIEH 0x80
4561 //==============================================================================
4563 extern __at(0x0FF3) __sfr PROD
;
4564 extern __at(0x0FF3) __sfr PRODL
;
4565 extern __at(0x0FF4) __sfr PRODH
;
4566 extern __at(0x0FF5) __sfr TABLAT
;
4567 extern __at(0x0FF6) __sfr TBLPTR
;
4568 extern __at(0x0FF6) __sfr TBLPTRL
;
4569 extern __at(0x0FF7) __sfr TBLPTRH
;
4570 extern __at(0x0FF8) __sfr TBLPTRU
;
4571 extern __at(0x0FF9) __sfr PC
;
4572 extern __at(0x0FF9) __sfr PCL
;
4573 extern __at(0x0FFA) __sfr PCLATH
;
4574 extern __at(0x0FFB) __sfr PCLATU
;
4576 //==============================================================================
4579 extern __at(0x0FFC) __sfr STKPTR
;
4585 unsigned STKPTR0
: 1;
4586 unsigned STKPTR1
: 1;
4587 unsigned STKPTR2
: 1;
4588 unsigned STKPTR3
: 1;
4589 unsigned STKPTR4
: 1;
4591 unsigned STKUNF
: 1;
4592 unsigned STKFUL
: 1;
4604 unsigned STKOVF
: 1;
4609 unsigned STKPTR
: 5;
4620 extern __at(0x0FFC) volatile __STKPTRbits_t STKPTRbits
;
4622 #define _STKPTR0 0x01
4624 #define _STKPTR1 0x02
4626 #define _STKPTR2 0x04
4628 #define _STKPTR3 0x08
4630 #define _STKPTR4 0x10
4632 #define _STKUNF 0x40
4633 #define _STKFUL 0x80
4634 #define _STKOVF 0x80
4636 //==============================================================================
4638 extern __at(0x0FFD) __sfr TOS
;
4639 extern __at(0x0FFD) __sfr TOSL
;
4640 extern __at(0x0FFE) __sfr TOSH
;
4641 extern __at(0x0FFF) __sfr TOSU
;
4643 //==============================================================================
4645 // Configuration Bits
4647 //==============================================================================
4649 #define __CONFIG1H 0x300001
4650 #define __CONFIG2L 0x300002
4651 #define __CONFIG2H 0x300003
4652 #define __CONFIG3L 0x300004
4653 #define __CONFIG3H 0x300005
4654 #define __CONFIG4L 0x300006
4655 #define __CONFIG5L 0x300008
4656 #define __CONFIG5H 0x300009
4657 #define __CONFIG6L 0x30000A
4658 #define __CONFIG6H 0x30000B
4659 #define __CONFIG7L 0x30000C
4660 #define __CONFIG7H 0x30000D
4662 //----------------------------- CONFIG1H Options -------------------------------
4664 #define _LP_OSC 0xF8 // LP oscillator.
4665 #define _LP_OSC_1H 0xF8 // LP oscillator.
4666 #define _XT_OSC 0xF9 // XT oscillator.
4667 #define _XT_OSC_1H 0xF9 // XT oscillator.
4668 #define _HS_OSC 0xFA // HS oscillator.
4669 #define _HS_OSC_1H 0xFA // HS oscillator.
4670 #define _RC_OSC 0xFB // RC oscillator w/ OSC2 configured as divide-by-4 clock output.
4671 #define _RC_OSC_1H 0xFB // RC oscillator w/ OSC2 configured as divide-by-4 clock output.
4672 #define _EC_OSC 0xFC // EC oscillator w/ OSC2 configured as divide-by-4 clock output.
4673 #define _EC_OSC_1H 0xFC // EC oscillator w/ OSC2 configured as divide-by-4 clock output.
4674 #define _ECIO_OSC 0xFD // EC oscillator w/ OSC2 configured as RA6.
4675 #define _ECIO_OSC_1H 0xFD // EC oscillator w/ OSC2 configured as RA6.
4676 #define _HSPLL_OSC 0xFE // HS oscillator with PLL enabled; clock frequency = (4 x FOSC).
4677 #define _HSPLL_OSC_1H 0xFE // HS oscillator with PLL enabled; clock frequency = (4 x FOSC).
4678 #define _RCIO_OSC 0xFF // RC oscillator w/ OSC2 configured as RA6.
4679 #define _RCIO_OSC_1H 0xFF // RC oscillator w/ OSC2 configured as RA6.
4680 #define _OSCS_ON_1H 0xDF // Timer1 Oscillator system clock switch option is enabled (oscillator switching is enabled).
4681 #define _OSCS_OFF_1H 0xFF // Oscillator system clock switch option is disabled (main oscillator is source).
4683 //----------------------------- CONFIG2L Options -------------------------------
4685 #define _PWRT_ON_2L 0xFE // PWRT enabled.
4686 #define _PWRT_OFF_2L 0xFF // PWRT disabled.
4687 #define _BOR_OFF_2L 0xFD // Brown-out Reset disabled.
4688 #define _BOR_ON_2L 0xFF // Brown-out Reset enabled.
4689 #define _BORV_45_2L 0xF3 // VBOR set to 4.5V.
4690 #define _BORV_42_2L 0xF7 // VBOR set to 4.2V.
4691 #define _BORV_27_2L 0xFB // VBOR set to 2.7V.
4692 #define _BORV_20 0xFF // VBOR set to 2.5V.
4693 #define _BORV_20_2L 0xFF // VBOR set to 2.5V.
4695 //----------------------------- CONFIG2H Options -------------------------------
4697 #define _WDT_OFF_2H 0xFE // WDT disabled (control is placed on the SWDTEN bit).
4698 #define _WDT_ON_2H 0xFF // WDT enabled.
4699 #define _WDTPS_1_2H 0xF1 // 1:1.
4700 #define _WDTPS_2_2H 0xF3 // 1:2.
4701 #define _WDTPS_4_2H 0xF5 // 1:4.
4702 #define _WDTPS_8_2H 0xF7 // 1:8.
4703 #define _WDTPS_16_2H 0xF9 // 1:16.
4704 #define _WDTPS_32_2H 0xFB // 1:32.
4705 #define _WDTPS_64_2H 0xFD // 1:64.
4706 #define _WDTPS_128_2H 0xFF // 1:128.
4708 //----------------------------- CONFIG3L Options -------------------------------
4710 #define _XMC_MODE 0xFC // Extended Microcontroller mode.
4711 #define _XMC_MODE_3L 0xFC // Extended Microcontroller mode.
4712 #define _MPB_MODE 0xFD // Microprocessor with Boot Block mode.
4713 #define _MPB_MODE_3L 0xFD // Microprocessor with Boot Block mode.
4714 #define _MP_MODE 0xFE // Microprocessor mode.
4715 #define _MP_MODE_3L 0xFE // Microprocessor mode.
4716 #define _MC_MODE 0xFF // Microcontroller mode.
4717 #define _MC_MODE_3L 0xFF // Microcontroller mode.
4718 #define _WAIT_ON_3L 0x7F // Wait selections for table reads and table writes are determined by the WAIT1:WAIT0 bits (MEMCOM<5:4>).
4719 #define _WAIT_OFF_3L 0xFF // Wait selections unavailable for table reads and table writes.
4721 //----------------------------- CONFIG3H Options -------------------------------
4723 #define _CCP2MX_OFF 0xFE // CCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode.
4724 #define _CCP2MX_OFF_3H 0xFE // CCP2 is multiplexed with RB3 in Extended Microcontroller, Microprocessor or Microprocessor with Boot Block mode. Or with RE7 in Microcontroller mode.
4725 #define _CCP2MX_ON 0xFF // CCP2 input/output is multiplexed with RC1.
4726 #define _CCP2MX_ON_3H 0xFF // CCP2 input/output is multiplexed with RC1.
4728 //----------------------------- CONFIG4L Options -------------------------------
4730 #define _STVR_OFF_4L 0xFE // Stack full/underflow will not cause Reset.
4731 #define _STVR_ON_4L 0xFF // Stack full/underflow will cause Reset.
4732 #define _LVP_OFF_4L 0xFB // Low-voltage ICSP disabled.
4733 #define _LVP_ON_4L 0xFF // Low-voltage ICSP enabled.
4734 #define _DEBUG_ON_4L 0x7F // Background debugger enabled. RB6 and RB7 are dedicated to In-Circuit Debug.
4735 #define _DEBUG_OFF_4L 0xFF // Background debugger disabled. RB6 and RB7 configured as general purpose I/O pins.
4737 //----------------------------- CONFIG5L Options -------------------------------
4739 #define _CP0_ON_5L 0xFE // Block 0 (000200-003FFFh) code-protected.
4740 #define _CP0_OFF_5L 0xFF // Block 0 (000200-003FFFh) not code-protected.
4741 #define _CP1_ON_5L 0xFD // Block 1 (004000-007FFFh) code-protected.
4742 #define _CP1_OFF_5L 0xFF // Block 1 (004000-007FFFh) not code-protected.
4743 #define _CP2_ON_5L 0xFB // Block 2 (008000-00BFFFh) code-protected.
4744 #define _CP2_OFF_5L 0xFF // Block 2 (008000-00BFFFh) not code-protected.
4745 #define _CP3_ON_5L 0xF7 // Block 3 (00C000-00FFFFh) code-protected.
4746 #define _CP3_OFF_5L 0xFF // Block 3 (00C000-00FFFFh) not code-protected.
4747 #define _CP4_ON_5L 0xEF // Block 4 (010000-013FFFh) code-protected.
4748 #define _CP4_OFF_5L 0xFF // Block 4 (010000-013FFFh) not code-protected.
4749 #define _CP5_ON_5L 0xDF // Block 5 (014000-017FFFh) code-protected.
4750 #define _CP5_OFF_5L 0xFF // Block 5 (014000-017FFFh) not code-protected.
4751 #define _CP6_ON_5L 0xBF // Block 6 (018000-01BFFFh) code-protected.
4752 #define _CP6_OFF_5L 0xFF // Block 6 (018000-01BFFFh) not code-protected.
4753 #define _CP7_ON_5L 0x7F // Block 7 (01C000-01FFFFh) code-protected.
4754 #define _CP7_OFF_5L 0xFF // Block 7 (01C000-01FFFFh) not code-protected.
4756 //----------------------------- CONFIG5H Options -------------------------------
4758 #define _CPB_ON_5H 0xBF // Boot Block (000000-0001FFh) code-protected.
4759 #define _CPB_OFF_5H 0xFF // Boot Block (000000-0001FFh) not code-protected.
4760 #define _CPD_ON_5H 0x7F // Data EEPROM code-protected.
4761 #define _CPD_OFF_5H 0xFF // Data EEPROM not code-protected.
4763 //----------------------------- CONFIG6L Options -------------------------------
4765 #define _WRT0_ON_6L 0xFE // Block 0 (000200-003FFFh) write-protected.
4766 #define _WRT0_OFF_6L 0xFF // Block 0 (000200-003FFFh) not write-protected.
4767 #define _WRT1_ON_6L 0xFD // Block 1 (004000-007FFFh) write-protected.
4768 #define _WRT1_OFF_6L 0xFF // Block 1 (004000-007FFFh) not write-protected.
4769 #define _WRT2_ON_6L 0xFB // Block 2 (008000-00BFFFh) write-protected.
4770 #define _WRT2_OFF_6L 0xFF // Block 2 (008000-00BFFFh) not write-protected.
4771 #define _WRT3_ON_6L 0xF7 // Block 3 (00C000-00FFFFh) write-protected.
4772 #define _WRT3_OFF_6L 0xFF // Block 3 (00C000-00FFFFh) not write-protected.
4773 #define _WRT4_ON_6L 0xEF // Block 4 (010000-013FFFh) write-protected.
4774 #define _WRT4_OFF_6L 0xFF // Block 4 (010000-013FFFh) not write-protected.
4775 #define _WRT5_ON_6L 0xDF // Block 5 (014000-017FFFh) write-protected.
4776 #define _WRT5_OFF_6L 0xFF // Block 5 (014000-017FFFh) not write-protected.
4777 #define _WRT6_ON_6L 0xBF // Block 6 (018000-01BFFFh) write-protected.
4778 #define _WRT6_OFF_6L 0xFF // Block 6 (018000-01BFFFh) not write-protected.
4779 #define _WRT7_ON_6L 0x7F // Block 7 (01C000-01FFFFh) write-protected.
4780 #define _WRT7_OFF_6L 0xFF // Block 7 (01C000-01FFFFh) not write-protected.
4782 //----------------------------- CONFIG6H Options -------------------------------
4784 #define _WRTC_ON_6H 0xDF // Configuration registers (300000-3000FFh) write-protected.
4785 #define _WRTC_OFF_6H 0xFF // Configuration registers (300000-3000FFh) not write-protected.
4786 #define _WRTB_ON_6H 0xBF // Boot Block (000000-0001FFh) write-protected.
4787 #define _WRTB_OFF_6H 0xFF // Boot Block (000000-0001FFh) not write-protected.
4788 #define _WRTD_ON_6H 0x7F // Data EEPROM write-protected.
4789 #define _WRTD_OFF_6H 0xFF // Data EEPROM not write-protected.
4791 //----------------------------- CONFIG7L Options -------------------------------
4793 #define _EBTR0_ON_7L 0xFE // Block 0 (000200-003FFFh) protected from table reads executed in other blocks.
4794 #define _EBTR0_OFF_7L 0xFF // Block 0 (000200-003FFFh) not protected from table reads executed in other blocks.
4795 #define _EBTR1_ON_7L 0xFD // Block 1 (004000-007FFFh) protected from table reads executed in other blocks.
4796 #define _EBTR1_OFF_7L 0xFF // Block 1 (004000-007FFFh) not protected from table reads executed in other blocks.
4797 #define _EBTR2_ON_7L 0xFB // Block 2 (008000-00BFFFh) protected from table reads executed in other blocks.
4798 #define _EBTR2_OFF_7L 0xFF // Block 2 (008000-00BFFFh) not protected from table reads executed in other blocks.
4799 #define _EBTR3_ON_7L 0xF7 // Block 3 (00C000-00FFFFh) protected from table reads executed in other blocks.
4800 #define _EBTR3_OFF_7L 0xFF // Block 3 (00C000-00FFFFh) not protected from table reads executed in other blocks.
4801 #define _EBTR4_ON_7L 0xEF // Block 4 (010000-013FFFh) protected from table reads executed in other blocks.
4802 #define _EBTR4_OFF_7L 0xFF // Block 4 (010000-013FFFh) not protected from table reads executed in other blocks.
4803 #define _EBTR5_ON_7L 0xDF // Block 5 (014000-017FFFh) protected from table reads executed in other blocks.
4804 #define _EBTR5_OFF_7L 0xFF // Block 5 (014000-017FFFh) not protected from table reads executed in other blocks.
4805 #define _EBTR6_ON_7L 0xBF // Block 6 (018000-01BFFFh) protected from table reads executed in other blocks.
4806 #define _EBTR6_OFF_7L 0xFF // Block 6 (018000-01BFFFh) not protected from table reads executed in other blocks.
4807 #define _EBTR7_ON_7L 0x7F // Block 7 (01C000-01FFFFh) protected from table reads executed in other blocks.
4808 #define _EBTR7_OFF_7L 0xFF // Block 7 (01C000-01FFFFh) not protected from table reads executed in other blocks.
4810 //----------------------------- CONFIG7H Options -------------------------------
4812 #define _EBTRB_ON_7H 0xBF // Boot Block (000000-0001FFh) protected from table reads executed in other blocks.
4813 #define _EBTRB_OFF_7H 0xFF // Boot Block (000000-0001FFh) not protected from table reads executed in other blocks.
4815 //==============================================================================
4817 #define __DEVID1 0x3FFFFE
4818 #define __DEVID2 0x3FFFFF
4820 #define __IDLOC0 0x200000
4821 #define __IDLOC1 0x200001
4822 #define __IDLOC2 0x200002
4823 #define __IDLOC3 0x200003
4824 #define __IDLOC4 0x200004
4825 #define __IDLOC5 0x200005
4826 #define __IDLOC6 0x200006
4827 #define __IDLOC7 0x200007
4829 #endif // #ifndef __PIC18LF8720_H__