sdcc/device/non-free/lib/pic14/libdev/pic12f675.c

   1 /*
   2  * This definitions of the PIC12F675 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:04 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic12f675.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0000) __sfr INDF;
  30
  31 __at(0x0001) __sfr TMR0;
  32
  33 __at(0x0002) __sfr PCL;
  34
  35 __at(0x0003) __sfr STATUS;
  36 __at(0x0003) volatile __STATUSbits_t STATUSbits;
  37
  38 __at(0x0004) __sfr FSR;
  39
  40 __at(0x0005) __sfr GPIO;
  41 __at(0x0005) volatile __GPIObits_t GPIObits;
  42
  43 __at(0x000A) __sfr PCLATH;
  44
  45 __at(0x000B) __sfr INTCON;
  46 __at(0x000B) volatile __INTCONbits_t INTCONbits;
  47
  48 __at(0x000C) __sfr PIR1;
  49 __at(0x000C) volatile __PIR1bits_t PIR1bits;
  50
  51 __at(0x000E) __sfr TMR1;
  52
  53 __at(0x000E) __sfr TMR1L;
  54
  55 __at(0x000F) __sfr TMR1H;
  56
  57 __at(0x0010) __sfr T1CON;
  58 __at(0x0010) volatile __T1CONbits_t T1CONbits;
  59
  60 __at(0x0019) __sfr CMCON;
  61 __at(0x0019) volatile __CMCONbits_t CMCONbits;
  62
  63 __at(0x001E) __sfr ADRESH;
  64
  65 __at(0x001F) __sfr ADCON0;
  66 __at(0x001F) volatile __ADCON0bits_t ADCON0bits;
  67
  68 __at(0x0081) __sfr OPTION_REG;
  69 __at(0x0081) volatile __OPTION_REGbits_t OPTION_REGbits;
  70
  71 __at(0x0085) __sfr TRISIO;
  72 __at(0x0085) volatile __TRISIObits_t TRISIObits;
  73
  74 __at(0x008C) __sfr PIE1;
  75 __at(0x008C) volatile __PIE1bits_t PIE1bits;
  76
  77 __at(0x008E) __sfr PCON;
  78 __at(0x008E) volatile __PCONbits_t PCONbits;
  79
  80 __at(0x0090) __sfr OSCCAL;
  81 __at(0x0090) volatile __OSCCALbits_t OSCCALbits;
  82
  83 __at(0x0095) __sfr WPU;
  84 __at(0x0095) volatile __WPUbits_t WPUbits;
  85
  86 __at(0x0096) __sfr IOC;
  87 __at(0x0096) volatile __IOCbits_t IOCbits;
  88
  89 __at(0x0096) __sfr IOCB;
  90 __at(0x0096) volatile __IOCBbits_t IOCBbits;
  91
  92 __at(0x0099) __sfr VRCON;
  93 __at(0x0099) volatile __VRCONbits_t VRCONbits;
  94
  95 __at(0x009A) __sfr EEDAT;
  96
  97 __at(0x009A) __sfr EEDATA;
  98
  99 __at(0x009B) __sfr EEADR;
 100
 101 __at(0x009C) __sfr EECON1;
 102 __at(0x009C) volatile __EECON1bits_t EECON1bits;
 103
 104 __at(0x009D) __sfr EECON2;
 105
 106 __at(0x009E) __sfr ADRESL;
 107
 108 __at(0x009F) __sfr ANSEL;
 109 __at(0x009F) volatile __ANSELbits_t ANSELbits;