2 * This definitions of the PIC12F752 MCU.
4 * This file is part of the GNU PIC library for SDCC, originally
5 * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
7 * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:04 UTC.
9 * SDCC is licensed under the GNU Public license (GPL) v2. Note that
10 * this license covers the code to the compiler and other executables,
11 * but explicitly does not cover any code or objects generated by sdcc.
13 * For pic device libraries and header files which are derived from
14 * Microchip header (.inc) and linker script (.lkr) files Microchip
15 * requires that "The header files should state that they are only to be
16 * used with authentic Microchip devices" which makes them incompatible
17 * with the GPL. Pic device libraries and header files are located at
18 * non-free/lib and non-free/include directories respectively.
19 * Sdcc should be run with the --use-non-free command line option in
20 * order to include non-free header files and libraries.
22 * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
25 #include <pic12f752.h>
27 //==============================================================================
29 __at(0x0000) __sfr INDF
;
31 __at(0x0001) __sfr TMR0
;
33 __at(0x0002) __sfr PCL
;
35 __at(0x0003) __sfr STATUS
;
36 __at(0x0003) volatile __STATUSbits_t STATUSbits
;
38 __at(0x0004) __sfr FSR
;
40 __at(0x0005) __sfr PORTA
;
41 __at(0x0005) volatile __PORTAbits_t PORTAbits
;
43 __at(0x0008) __sfr IOCAF
;
44 __at(0x0008) volatile __IOCAFbits_t IOCAFbits
;
46 __at(0x000A) __sfr PCLATH
;
48 __at(0x000B) __sfr INTCON
;
49 __at(0x000B) volatile __INTCONbits_t INTCONbits
;
51 __at(0x000C) __sfr PIR1
;
52 __at(0x000C) volatile __PIR1bits_t PIR1bits
;
54 __at(0x000D) __sfr PIR2
;
55 __at(0x000D) volatile __PIR2bits_t PIR2bits
;
57 __at(0x000F) __sfr TMR1
;
59 __at(0x000F) __sfr TMR1L
;
61 __at(0x0010) __sfr TMR1H
;
63 __at(0x0011) __sfr T1CON
;
64 __at(0x0011) volatile __T1CONbits_t T1CONbits
;
66 __at(0x0012) __sfr T1GCON
;
67 __at(0x0012) volatile __T1GCONbits_t T1GCONbits
;
69 __at(0x0013) __sfr CCPR1
;
71 __at(0x0013) __sfr CCPR1L
;
73 __at(0x0014) __sfr CCPR1H
;
75 __at(0x0015) __sfr CCP1CON
;
76 __at(0x0015) volatile __CCP1CONbits_t CCP1CONbits
;
78 __at(0x001C) __sfr ADRES
;
80 __at(0x001C) __sfr ADRESL
;
82 __at(0x001D) __sfr ADRESH
;
84 __at(0x001E) __sfr ADCON0
;
85 __at(0x001E) volatile __ADCON0bits_t ADCON0bits
;
87 __at(0x001F) __sfr ADCON1
;
88 __at(0x001F) volatile __ADCON1bits_t ADCON1bits
;
90 __at(0x0081) __sfr OPTION_REG
;
91 __at(0x0081) volatile __OPTION_REGbits_t OPTION_REGbits
;
93 __at(0x0085) __sfr TRISA
;
94 __at(0x0085) volatile __TRISAbits_t TRISAbits
;
96 __at(0x0088) __sfr IOCAP
;
97 __at(0x0088) volatile __IOCAPbits_t IOCAPbits
;
99 __at(0x008C) __sfr PIE1
;
100 __at(0x008C) volatile __PIE1bits_t PIE1bits
;
102 __at(0x008D) __sfr PIE2
;
103 __at(0x008D) volatile __PIE2bits_t PIE2bits
;
105 __at(0x008F) __sfr OSCCON
;
106 __at(0x008F) volatile __OSCCONbits_t OSCCONbits
;
108 __at(0x0090) __sfr FVRCON
;
109 __at(0x0090) volatile __FVRCONbits_t FVRCONbits
;
111 __at(0x0091) __sfr DACCON0
;
112 __at(0x0091) volatile __DACCON0bits_t DACCON0bits
;
114 __at(0x0092) __sfr DACCON1
;
115 __at(0x0092) volatile __DACCON1bits_t DACCON1bits
;
117 __at(0x009B) __sfr C2CON0
;
118 __at(0x009B) volatile __C2CON0bits_t C2CON0bits
;
120 __at(0x009B) __sfr CM2CON0
;
121 __at(0x009B) volatile __CM2CON0bits_t CM2CON0bits
;
123 __at(0x009C) __sfr C2CON1
;
124 __at(0x009C) volatile __C2CON1bits_t C2CON1bits
;
126 __at(0x009C) __sfr CM2CON1
;
127 __at(0x009C) volatile __CM2CON1bits_t CM2CON1bits
;
129 __at(0x009D) __sfr C1CON0
;
130 __at(0x009D) volatile __C1CON0bits_t C1CON0bits
;
132 __at(0x009D) __sfr CM1CON0
;
133 __at(0x009D) volatile __CM1CON0bits_t CM1CON0bits
;
135 __at(0x009E) __sfr C1CON1
;
136 __at(0x009E) volatile __C1CON1bits_t C1CON1bits
;
138 __at(0x009E) __sfr CM1CON1
;
139 __at(0x009E) volatile __CM1CON1bits_t CM1CON1bits
;
141 __at(0x009F) __sfr CMOUT
;
142 __at(0x009F) volatile __CMOUTbits_t CMOUTbits
;
144 __at(0x009F) __sfr MCOUT
;
145 __at(0x009F) volatile __MCOUTbits_t MCOUTbits
;
147 __at(0x0105) __sfr LATA
;
148 __at(0x0105) volatile __LATAbits_t LATAbits
;
150 __at(0x0108) __sfr IOCAN
;
151 __at(0x0108) volatile __IOCANbits_t IOCANbits
;
153 __at(0x010C) __sfr WPUA
;
154 __at(0x010C) volatile __WPUAbits_t WPUAbits
;
156 __at(0x010D) __sfr SLRCONA
;
157 __at(0x010D) volatile __SLRCONAbits_t SLRCONAbits
;
159 __at(0x010F) __sfr PCON
;
160 __at(0x010F) volatile __PCONbits_t PCONbits
;
162 __at(0x0110) __sfr TMR2
;
164 __at(0x0111) __sfr PR2
;
166 __at(0x0112) __sfr T2CON
;
167 __at(0x0112) volatile __T2CONbits_t T2CONbits
;
169 __at(0x0113) __sfr HLTMR1
;
171 __at(0x0114) __sfr HLTPR1
;
173 __at(0x0115) __sfr HLT1CON0
;
174 __at(0x0115) volatile __HLT1CON0bits_t HLT1CON0bits
;
176 __at(0x0116) __sfr HLT1CON1
;
177 __at(0x0116) volatile __HLT1CON1bits_t HLT1CON1bits
;
179 __at(0x0185) __sfr ANSELA
;
180 __at(0x0185) volatile __ANSELAbits_t ANSELAbits
;
182 __at(0x0188) __sfr APFCON
;
183 __at(0x0188) volatile __APFCONbits_t APFCONbits
;
185 __at(0x0189) __sfr OSCTUNE
;
186 __at(0x0189) volatile __OSCTUNEbits_t OSCTUNEbits
;
188 __at(0x018C) __sfr PMCON1
;
189 __at(0x018C) volatile __PMCON1bits_t PMCON1bits
;
191 __at(0x018D) __sfr PMCON2
;
193 __at(0x018E) __sfr PMADR
;
195 __at(0x018E) __sfr PMADRL
;
197 __at(0x018F) __sfr PMADRH
;
199 __at(0x0190) __sfr PMDAT
;
201 __at(0x0190) __sfr PMDATL
;
203 __at(0x0191) __sfr PMDATH
;
205 __at(0x0192) __sfr COG1PH
;
206 __at(0x0192) volatile __COG1PHbits_t COG1PHbits
;
208 __at(0x0193) __sfr COG1BLK
;
209 __at(0x0193) volatile __COG1BLKbits_t COG1BLKbits
;
211 __at(0x0194) __sfr COG1DB
;
212 __at(0x0194) volatile __COG1DBbits_t COG1DBbits
;
214 __at(0x0195) __sfr COG1CON0
;
215 __at(0x0195) volatile __COG1CON0bits_t COG1CON0bits
;
217 __at(0x0196) __sfr COG1CON1
;
218 __at(0x0196) volatile __COG1CON1bits_t COG1CON1bits
;
220 __at(0x0197) __sfr COG1ASD
;
221 __at(0x0197) volatile __COG1ASDbits_t COG1ASDbits
;