sdcc/device/non-free/lib/pic14/libdev/pic12lf1612.c

   1 /*
   2  * This definitions of the PIC12LF1612 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:05 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic12lf1612.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0000) __sfr INDF0;
  30
  31 __at(0x0001) __sfr INDF1;
  32
  33 __at(0x0002) __sfr PCL;
  34
  35 __at(0x0003) __sfr STATUS;
  36 __at(0x0003) volatile __STATUSbits_t STATUSbits;
  37
  38 __at(0x0004) __sfr FSR0;
  39
  40 __at(0x0004) __sfr FSR0L;
  41
  42 __at(0x0005) __sfr FSR0H;
  43
  44 __at(0x0006) __sfr FSR1;
  45
  46 __at(0x0006) __sfr FSR1L;
  47
  48 __at(0x0007) __sfr FSR1H;
  49
  50 __at(0x0008) __sfr BSR;
  51 __at(0x0008) volatile __BSRbits_t BSRbits;
  52
  53 __at(0x0009) __sfr WREG;
  54
  55 __at(0x000A) __sfr PCLATH;
  56
  57 __at(0x000B) __sfr INTCON;
  58 __at(0x000B) volatile __INTCONbits_t INTCONbits;
  59
  60 __at(0x000C) __sfr PORTA;
  61 __at(0x000C) volatile __PORTAbits_t PORTAbits;
  62
  63 __at(0x0011) __sfr PIR1;
  64 __at(0x0011) volatile __PIR1bits_t PIR1bits;
  65
  66 __at(0x0012) __sfr PIR2;
  67 __at(0x0012) volatile __PIR2bits_t PIR2bits;
  68
  69 __at(0x0013) __sfr PIR3;
  70 __at(0x0013) volatile __PIR3bits_t PIR3bits;
  71
  72 __at(0x0014) __sfr PIR4;
  73 __at(0x0014) volatile __PIR4bits_t PIR4bits;
  74
  75 __at(0x0015) __sfr TMR0;
  76
  77 __at(0x0016) __sfr TMR1;
  78
  79 __at(0x0016) __sfr TMR1L;
  80
  81 __at(0x0017) __sfr TMR1H;
  82
  83 __at(0x0018) __sfr T1CON;
  84 __at(0x0018) volatile __T1CONbits_t T1CONbits;
  85
  86 __at(0x0019) __sfr T1GCON;
  87 __at(0x0019) volatile __T1GCONbits_t T1GCONbits;
  88
  89 __at(0x001A) __sfr T2TMR;
  90
  91 __at(0x001A) __sfr TMR2;
  92
  93 __at(0x001B) __sfr PR2;
  94
  95 __at(0x001B) __sfr T2PR;
  96
  97 __at(0x001C) __sfr T2CON;
  98 __at(0x001C) volatile __T2CONbits_t T2CONbits;
  99
 100 __at(0x001D) __sfr T2HLT;
 101 __at(0x001D) volatile __T2HLTbits_t T2HLTbits;
 102
 103 __at(0x001E) __sfr T2CLKCON;
 104 __at(0x001E) volatile __T2CLKCONbits_t T2CLKCONbits;
 105
 106 __at(0x001F) __sfr T2RST;
 107 __at(0x001F) volatile __T2RSTbits_t T2RSTbits;
 108
 109 __at(0x008C) __sfr TRISA;
 110 __at(0x008C) volatile __TRISAbits_t TRISAbits;
 111
 112 __at(0x0091) __sfr PIE1;
 113 __at(0x0091) volatile __PIE1bits_t PIE1bits;
 114
 115 __at(0x0092) __sfr PIE2;
 116 __at(0x0092) volatile __PIE2bits_t PIE2bits;
 117
 118 __at(0x0093) __sfr PIE3;
 119 __at(0x0093) volatile __PIE3bits_t PIE3bits;
 120
 121 __at(0x0094) __sfr PIE4;
 122 __at(0x0094) volatile __PIE4bits_t PIE4bits;
 123
 124 __at(0x0095) __sfr OPTION_REG;
 125 __at(0x0095) volatile __OPTION_REGbits_t OPTION_REGbits;
 126
 127 __at(0x0096) __sfr PCON;
 128 __at(0x0096) volatile __PCONbits_t PCONbits;
 129
 130 __at(0x0098) __sfr OSCTUNE;
 131 __at(0x0098) volatile __OSCTUNEbits_t OSCTUNEbits;
 132
 133 __at(0x0099) __sfr OSCCON;
 134 __at(0x0099) volatile __OSCCONbits_t OSCCONbits;
 135
 136 __at(0x009A) __sfr OSCSTAT;
 137 __at(0x009A) volatile __OSCSTATbits_t OSCSTATbits;
 138
 139 __at(0x009B) __sfr ADRES;
 140
 141 __at(0x009B) __sfr ADRESL;
 142
 143 __at(0x009C) __sfr ADRESH;
 144
 145 __at(0x009D) __sfr ADCON0;
 146 __at(0x009D) volatile __ADCON0bits_t ADCON0bits;
 147
 148 __at(0x009E) __sfr ADCON1;
 149 __at(0x009E) volatile __ADCON1bits_t ADCON1bits;
 150
 151 __at(0x009F) __sfr ADCON2;
 152 __at(0x009F) volatile __ADCON2bits_t ADCON2bits;
 153
 154 __at(0x010C) __sfr LATA;
 155 __at(0x010C) volatile __LATAbits_t LATAbits;
 156
 157 __at(0x0111) __sfr CM1CON0;
 158 __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits;
 159
 160 __at(0x0112) __sfr CM1CON1;
 161 __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits;
 162
 163 __at(0x0115) __sfr CMOUT;
 164 __at(0x0115) volatile __CMOUTbits_t CMOUTbits;
 165
 166 __at(0x0116) __sfr BORCON;
 167 __at(0x0116) volatile __BORCONbits_t BORCONbits;
 168
 169 __at(0x0117) __sfr FVRCON;
 170 __at(0x0117) volatile __FVRCONbits_t FVRCONbits;
 171
 172 __at(0x0118) __sfr DAC1CON0;
 173 __at(0x0118) volatile __DAC1CON0bits_t DAC1CON0bits;
 174
 175 __at(0x0119) __sfr DAC1CON1;
 176 __at(0x0119) volatile __DAC1CON1bits_t DAC1CON1bits;
 177
 178 __at(0x011C) __sfr ZCD1CON;
 179 __at(0x011C) volatile __ZCD1CONbits_t ZCD1CONbits;
 180
 181 __at(0x011D) __sfr APFCON;
 182 __at(0x011D) volatile __APFCONbits_t APFCONbits;
 183
 184 __at(0x018C) __sfr ANSELA;
 185 __at(0x018C) volatile __ANSELAbits_t ANSELAbits;
 186
 187 __at(0x0191) __sfr PMADR;
 188
 189 __at(0x0191) __sfr PMADRL;
 190
 191 __at(0x0192) __sfr PMADRH;
 192
 193 __at(0x0193) __sfr PMDAT;
 194
 195 __at(0x0193) __sfr PMDATL;
 196
 197 __at(0x0194) __sfr PMDATH;
 198
 199 __at(0x0195) __sfr PMCON1;
 200 __at(0x0195) volatile __PMCON1bits_t PMCON1bits;
 201
 202 __at(0x0196) __sfr PMCON2;
 203
 204 __at(0x020C) __sfr WPUA;
 205 __at(0x020C) volatile __WPUAbits_t WPUAbits;
 206
 207 __at(0x028C) __sfr ODCONA;
 208 __at(0x028C) volatile __ODCONAbits_t ODCONAbits;
 209
 210 __at(0x0291) __sfr CCPR1;
 211
 212 __at(0x0291) __sfr CCPR1L;
 213
 214 __at(0x0292) __sfr CCPR1H;
 215
 216 __at(0x0293) __sfr CCP1CON;
 217 __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits;
 218
 219 __at(0x0294) __sfr CCP1CAP;
 220 __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits;
 221
 222 __at(0x0298) __sfr CCPR2;
 223
 224 __at(0x0298) __sfr CCPR2L;
 225
 226 __at(0x0299) __sfr CCPR2H;
 227
 228 __at(0x029A) __sfr CCP2CON;
 229 __at(0x029A) volatile __CCP2CONbits_t CCP2CONbits;
 230
 231 __at(0x029B) __sfr CCP2CAP;
 232 __at(0x029B) volatile __CCP2CAPbits_t CCP2CAPbits;
 233
 234 __at(0x029E) __sfr CCPTMRS;
 235 __at(0x029E) volatile __CCPTMRSbits_t CCPTMRSbits;
 236
 237 __at(0x030C) __sfr SLRCONA;
 238 __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits;
 239
 240 __at(0x038C) __sfr INLVLA;
 241 __at(0x038C) volatile __INLVLAbits_t INLVLAbits;
 242
 243 __at(0x0391) __sfr IOCAP;
 244
 245 __at(0x0392) __sfr IOCAN;
 246
 247 __at(0x0393) __sfr IOCAF;
 248
 249 __at(0x0413) __sfr T4TMR;
 250
 251 __at(0x0413) __sfr TMR4;
 252
 253 __at(0x0414) __sfr PR4;
 254
 255 __at(0x0414) __sfr T4PR;
 256
 257 __at(0x0415) __sfr T4CON;
 258 __at(0x0415) volatile __T4CONbits_t T4CONbits;
 259
 260 __at(0x0416) __sfr T4HLT;
 261 __at(0x0416) volatile __T4HLTbits_t T4HLTbits;
 262
 263 __at(0x0417) __sfr T4CLKCON;
 264 __at(0x0417) volatile __T4CLKCONbits_t T4CLKCONbits;
 265
 266 __at(0x0418) __sfr T4RST;
 267 __at(0x0418) volatile __T4RSTbits_t T4RSTbits;
 268
 269 __at(0x041A) __sfr T6TMR;
 270
 271 __at(0x041A) __sfr TMR6;
 272
 273 __at(0x041B) __sfr PR6;
 274
 275 __at(0x041B) __sfr T6PR;
 276
 277 __at(0x041C) __sfr T6CON;
 278 __at(0x041C) volatile __T6CONbits_t T6CONbits;
 279
 280 __at(0x041D) __sfr T6HLT;
 281 __at(0x041D) volatile __T6HLTbits_t T6HLTbits;
 282
 283 __at(0x041E) __sfr T6CLKCON;
 284 __at(0x041E) volatile __T6CLKCONbits_t T6CLKCONbits;
 285
 286 __at(0x041F) __sfr T6RST;
 287 __at(0x041F) volatile __T6RSTbits_t T6RSTbits;
 288
 289 __at(0x0691) __sfr CWG1DBR;
 290 __at(0x0691) volatile __CWG1DBRbits_t CWG1DBRbits;
 291
 292 __at(0x0692) __sfr CWG1DBF;
 293 __at(0x0692) volatile __CWG1DBFbits_t CWG1DBFbits;
 294
 295 __at(0x0693) __sfr CWG1AS0;
 296 __at(0x0693) volatile __CWG1AS0bits_t CWG1AS0bits;
 297
 298 __at(0x0694) __sfr CWG1AS1;
 299 __at(0x0694) volatile __CWG1AS1bits_t CWG1AS1bits;
 300
 301 __at(0x0695) __sfr CWG1OCON0;
 302 __at(0x0695) volatile __CWG1OCON0bits_t CWG1OCON0bits;
 303
 304 __at(0x0696) __sfr CWG1CON0;
 305 __at(0x0696) volatile __CWG1CON0bits_t CWG1CON0bits;
 306
 307 __at(0x0697) __sfr CWG1CON1;
 308 __at(0x0697) volatile __CWG1CON1bits_t CWG1CON1bits;
 309
 310 __at(0x0698) __sfr CWG1OCON1;
 311 __at(0x0698) volatile __CWG1OCON1bits_t CWG1OCON1bits;
 312
 313 __at(0x0699) __sfr CWG1CLKCON;
 314 __at(0x0699) volatile __CWG1CLKCONbits_t CWG1CLKCONbits;
 315
 316 __at(0x069A) __sfr CWG1ISM;
 317 __at(0x069A) volatile __CWG1ISMbits_t CWG1ISMbits;
 318
 319 __at(0x0711) __sfr WDTCON0;
 320 __at(0x0711) volatile __WDTCON0bits_t WDTCON0bits;
 321
 322 __at(0x0712) __sfr WDTCON1;
 323 __at(0x0712) volatile __WDTCON1bits_t WDTCON1bits;
 324
 325 __at(0x0713) __sfr WDTPSL;
 326 __at(0x0713) volatile __WDTPSLbits_t WDTPSLbits;
 327
 328 __at(0x0714) __sfr WDTPSH;
 329 __at(0x0714) volatile __WDTPSHbits_t WDTPSHbits;
 330
 331 __at(0x0715) __sfr WDTTMR;
 332 __at(0x0715) volatile __WDTTMRbits_t WDTTMRbits;
 333
 334 __at(0x0718) __sfr SCANLADR;
 335
 336 __at(0x0718) __sfr SCANLADRL;
 337 __at(0x0718) volatile __SCANLADRLbits_t SCANLADRLbits;
 338
 339 __at(0x0719) __sfr SCANLADRH;
 340 __at(0x0719) volatile __SCANLADRHbits_t SCANLADRHbits;
 341
 342 __at(0x071A) __sfr SCANHADR;
 343
 344 __at(0x071A) __sfr SCANHADRL;
 345 __at(0x071A) volatile __SCANHADRLbits_t SCANHADRLbits;
 346
 347 __at(0x071B) __sfr SCANHADRH;
 348 __at(0x071B) volatile __SCANHADRHbits_t SCANHADRHbits;
 349
 350 __at(0x071C) __sfr SCANCON0;
 351 __at(0x071C) volatile __SCANCON0bits_t SCANCON0bits;
 352
 353 __at(0x071D) __sfr SCANTRIG;
 354 __at(0x071D) volatile __SCANTRIGbits_t SCANTRIGbits;
 355
 356 __at(0x0791) __sfr CRCDAT;
 357
 358 __at(0x0791) __sfr CRCDATL;
 359 __at(0x0791) volatile __CRCDATLbits_t CRCDATLbits;
 360
 361 __at(0x0792) __sfr CRCDATH;
 362 __at(0x0792) volatile __CRCDATHbits_t CRCDATHbits;
 363
 364 __at(0x0793) __sfr CRCACC;
 365
 366 __at(0x0793) __sfr CRCACCL;
 367 __at(0x0793) volatile __CRCACCLbits_t CRCACCLbits;
 368
 369 __at(0x0794) __sfr CRCACCH;
 370 __at(0x0794) volatile __CRCACCHbits_t CRCACCHbits;
 371
 372 __at(0x0795) __sfr CRCSHIFT;
 373
 374 __at(0x0795) __sfr CRCSHIFTL;
 375 __at(0x0795) volatile __CRCSHIFTLbits_t CRCSHIFTLbits;
 376
 377 __at(0x0796) __sfr CRCSHIFTH;
 378 __at(0x0796) volatile __CRCSHIFTHbits_t CRCSHIFTHbits;
 379
 380 __at(0x0797) __sfr CRCXOR;
 381
 382 __at(0x0797) __sfr CRCXORL;
 383 __at(0x0797) volatile __CRCXORLbits_t CRCXORLbits;
 384
 385 __at(0x0798) __sfr CRCXORH;
 386 __at(0x0798) volatile __CRCXORHbits_t CRCXORHbits;
 387
 388 __at(0x0799) __sfr CRCCON0;
 389 __at(0x0799) volatile __CRCCON0bits_t CRCCON0bits;
 390
 391 __at(0x079A) __sfr CRCCON1;
 392 __at(0x079A) volatile __CRCCON1bits_t CRCCON1bits;
 393
 394 __at(0x0D8C) __sfr SMT1TMR;
 395
 396 __at(0x0D8C) __sfr SMT1TMRL;
 397 __at(0x0D8C) volatile __SMT1TMRLbits_t SMT1TMRLbits;
 398
 399 __at(0x0D8D) __sfr SMT1TMRH;
 400 __at(0x0D8D) volatile __SMT1TMRHbits_t SMT1TMRHbits;
 401
 402 __at(0x0D8E) __sfr SMT1TMRU;
 403 __at(0x0D8E) volatile __SMT1TMRUbits_t SMT1TMRUbits;
 404
 405 __at(0x0D8F) __sfr SMT1CPR;
 406
 407 __at(0x0D8F) __sfr SMT1CPRL;
 408 __at(0x0D8F) volatile __SMT1CPRLbits_t SMT1CPRLbits;
 409
 410 __at(0x0D90) __sfr SMT1CPRH;
 411 __at(0x0D90) volatile __SMT1CPRHbits_t SMT1CPRHbits;
 412
 413 __at(0x0D91) __sfr SMT1CPRU;
 414 __at(0x0D91) volatile __SMT1CPRUbits_t SMT1CPRUbits;
 415
 416 __at(0x0D92) __sfr SMT1CPW;
 417
 418 __at(0x0D92) __sfr SMT1CPWL;
 419 __at(0x0D92) volatile __SMT1CPWLbits_t SMT1CPWLbits;
 420
 421 __at(0x0D93) __sfr SMT1CPWH;
 422 __at(0x0D93) volatile __SMT1CPWHbits_t SMT1CPWHbits;
 423
 424 __at(0x0D94) __sfr SMT1CPWU;
 425 __at(0x0D94) volatile __SMT1CPWUbits_t SMT1CPWUbits;
 426
 427 __at(0x0D95) __sfr SMT1PR;
 428
 429 __at(0x0D95) __sfr SMT1PRL;
 430 __at(0x0D95) volatile __SMT1PRLbits_t SMT1PRLbits;
 431
 432 __at(0x0D96) __sfr SMT1PRH;
 433 __at(0x0D96) volatile __SMT1PRHbits_t SMT1PRHbits;
 434
 435 __at(0x0D97) __sfr SMT1PRU;
 436 __at(0x0D97) volatile __SMT1PRUbits_t SMT1PRUbits;
 437
 438 __at(0x0D98) __sfr SMT1CON0;
 439 __at(0x0D98) volatile __SMT1CON0bits_t SMT1CON0bits;
 440
 441 __at(0x0D99) __sfr SMT1CON1;
 442 __at(0x0D99) volatile __SMT1CON1bits_t SMT1CON1bits;
 443
 444 __at(0x0D9A) __sfr SMT1STAT;
 445 __at(0x0D9A) volatile __SMT1STATbits_t SMT1STATbits;
 446
 447 __at(0x0D9B) __sfr SMT1CLK;
 448 __at(0x0D9B) volatile __SMT1CLKbits_t SMT1CLKbits;
 449
 450 __at(0x0D9C) __sfr SMT1SIG;
 451 __at(0x0D9C) volatile __SMT1SIGbits_t SMT1SIGbits;
 452
 453 __at(0x0D9D) __sfr SMT1WIN;
 454 __at(0x0D9D) volatile __SMT1WINbits_t SMT1WINbits;
 455
 456 __at(0x0D9E) __sfr SMT2TMR;
 457
 458 __at(0x0D9E) __sfr SMT2TMRL;
 459 __at(0x0D9E) volatile __SMT2TMRLbits_t SMT2TMRLbits;
 460
 461 __at(0x0D9F) __sfr SMT2TMRH;
 462 __at(0x0D9F) volatile __SMT2TMRHbits_t SMT2TMRHbits;
 463
 464 __at(0x0DA0) __sfr SMT2TMRU;
 465 __at(0x0DA0) volatile __SMT2TMRUbits_t SMT2TMRUbits;
 466
 467 __at(0x0DA1) __sfr SMT2CPR;
 468
 469 __at(0x0DA1) __sfr SMT2CPRL;
 470 __at(0x0DA1) volatile __SMT2CPRLbits_t SMT2CPRLbits;
 471
 472 __at(0x0DA2) __sfr SMT2CPRH;
 473 __at(0x0DA2) volatile __SMT2CPRHbits_t SMT2CPRHbits;
 474
 475 __at(0x0DA3) __sfr SMT2CPRU;
 476 __at(0x0DA3) volatile __SMT2CPRUbits_t SMT2CPRUbits;
 477
 478 __at(0x0DA4) __sfr SMT2CPW;
 479
 480 __at(0x0DA4) __sfr SMT2CPWL;
 481 __at(0x0DA4) volatile __SMT2CPWLbits_t SMT2CPWLbits;
 482
 483 __at(0x0DA5) __sfr SMT2CPWH;
 484 __at(0x0DA5) volatile __SMT2CPWHbits_t SMT2CPWHbits;
 485
 486 __at(0x0DA6) __sfr SMT2CPWU;
 487 __at(0x0DA6) volatile __SMT2CPWUbits_t SMT2CPWUbits;
 488
 489 __at(0x0DA7) __sfr SMT2PR;
 490
 491 __at(0x0DA7) __sfr SMT2PRL;
 492 __at(0x0DA7) volatile __SMT2PRLbits_t SMT2PRLbits;
 493
 494 __at(0x0DA8) __sfr SMT2PRH;
 495 __at(0x0DA8) volatile __SMT2PRHbits_t SMT2PRHbits;
 496
 497 __at(0x0DA9) __sfr SMT2PRU;
 498 __at(0x0DA9) volatile __SMT2PRUbits_t SMT2PRUbits;
 499
 500 __at(0x0DAA) __sfr SMT2CON0;
 501 __at(0x0DAA) volatile __SMT2CON0bits_t SMT2CON0bits;
 502
 503 __at(0x0DAB) __sfr SMT2CON1;
 504 __at(0x0DAB) volatile __SMT2CON1bits_t SMT2CON1bits;
 505
 506 __at(0x0DAC) __sfr SMT2STAT;
 507 __at(0x0DAC) volatile __SMT2STATbits_t SMT2STATbits;
 508
 509 __at(0x0DAD) __sfr SMT2CLK;
 510 __at(0x0DAD) volatile __SMT2CLKbits_t SMT2CLKbits;
 511
 512 __at(0x0DAE) __sfr SMT2SIG;
 513 __at(0x0DAE) volatile __SMT2SIGbits_t SMT2SIGbits;
 514
 515 __at(0x0DAF) __sfr SMT2WIN;
 516 __at(0x0DAF) volatile __SMT2WINbits_t SMT2WINbits;
 517
 518 __at(0x0FE4) __sfr STATUS_SHAD;
 519 __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits;
 520
 521 __at(0x0FE5) __sfr WREG_SHAD;
 522
 523 __at(0x0FE6) __sfr BSR_SHAD;
 524
 525 __at(0x0FE7) __sfr PCLATH_SHAD;
 526
 527 __at(0x0FE8) __sfr FSR0L_SHAD;
 528
 529 __at(0x0FE9) __sfr FSR0H_SHAD;
 530
 531 __at(0x0FEA) __sfr FSR1L_SHAD;
 532
 533 __at(0x0FEB) __sfr FSR1H_SHAD;
 534
 535 __at(0x0FED) __sfr STKPTR;
 536
 537 __at(0x0FEE) __sfr TOSL;
 538
 539 __at(0x0FEF) __sfr TOSH;