sdcc/device/non-free/lib/pic14/libdev/pic16f18313.c

   1 /*
   2  * This definitions of the PIC16F18313 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:23 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic16f18313.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0000) __sfr INDF0;
  30
  31 __at(0x0001) __sfr INDF1;
  32
  33 __at(0x0002) __sfr PCL;
  34
  35 __at(0x0003) __sfr STATUS;
  36 __at(0x0003) volatile __STATUSbits_t STATUSbits;
  37
  38 __at(0x0004) __sfr FSR0;
  39
  40 __at(0x0004) __sfr FSR0L;
  41
  42 __at(0x0005) __sfr FSR0H;
  43
  44 __at(0x0006) __sfr FSR1;
  45
  46 __at(0x0006) __sfr FSR1L;
  47
  48 __at(0x0007) __sfr FSR1H;
  49
  50 __at(0x0008) __sfr BSR;
  51 __at(0x0008) volatile __BSRbits_t BSRbits;
  52
  53 __at(0x0009) __sfr WREG;
  54
  55 __at(0x000A) __sfr PCLATH;
  56
  57 __at(0x000B) __sfr INTCON;
  58 __at(0x000B) volatile __INTCONbits_t INTCONbits;
  59
  60 __at(0x000C) __sfr PORTA;
  61 __at(0x000C) volatile __PORTAbits_t PORTAbits;
  62
  63 __at(0x0010) __sfr PIR0;
  64 __at(0x0010) volatile __PIR0bits_t PIR0bits;
  65
  66 __at(0x0011) __sfr PIR1;
  67 __at(0x0011) volatile __PIR1bits_t PIR1bits;
  68
  69 __at(0x0012) __sfr PIR2;
  70 __at(0x0012) volatile __PIR2bits_t PIR2bits;
  71
  72 __at(0x0013) __sfr PIR3;
  73 __at(0x0013) volatile __PIR3bits_t PIR3bits;
  74
  75 __at(0x0014) __sfr PIR4;
  76 __at(0x0014) volatile __PIR4bits_t PIR4bits;
  77
  78 __at(0x0015) __sfr TMR0L;
  79 __at(0x0015) volatile __TMR0Lbits_t TMR0Lbits;
  80
  81 __at(0x0016) __sfr TMR0H;
  82 __at(0x0016) volatile __TMR0Hbits_t TMR0Hbits;
  83
  84 __at(0x0017) __sfr T0CON0;
  85 __at(0x0017) volatile __T0CON0bits_t T0CON0bits;
  86
  87 __at(0x0018) __sfr T0CON1;
  88 __at(0x0018) volatile __T0CON1bits_t T0CON1bits;
  89
  90 __at(0x0019) __sfr TMR1;
  91
  92 __at(0x0019) __sfr TMR1L;
  93
  94 __at(0x001A) __sfr TMR1H;
  95
  96 __at(0x001B) __sfr T1CON;
  97 __at(0x001B) volatile __T1CONbits_t T1CONbits;
  98
  99 __at(0x001C) __sfr T1GCON;
 100 __at(0x001C) volatile __T1GCONbits_t T1GCONbits;
 101
 102 __at(0x001D) __sfr TMR2;
 103
 104 __at(0x001E) __sfr PR2;
 105
 106 __at(0x001F) __sfr T2CON;
 107 __at(0x001F) volatile __T2CONbits_t T2CONbits;
 108
 109 __at(0x008C) __sfr TRISA;
 110 __at(0x008C) volatile __TRISAbits_t TRISAbits;
 111
 112 __at(0x0090) __sfr PIE0;
 113 __at(0x0090) volatile __PIE0bits_t PIE0bits;
 114
 115 __at(0x0091) __sfr PIE1;
 116 __at(0x0091) volatile __PIE1bits_t PIE1bits;
 117
 118 __at(0x0092) __sfr PIE2;
 119 __at(0x0092) volatile __PIE2bits_t PIE2bits;
 120
 121 __at(0x0093) __sfr PIE3;
 122 __at(0x0093) volatile __PIE3bits_t PIE3bits;
 123
 124 __at(0x0094) __sfr PIE4;
 125 __at(0x0094) volatile __PIE4bits_t PIE4bits;
 126
 127 __at(0x0097) __sfr WDTCON;
 128 __at(0x0097) volatile __WDTCONbits_t WDTCONbits;
 129
 130 __at(0x009B) __sfr ADRES;
 131
 132 __at(0x009B) __sfr ADRESL;
 133
 134 __at(0x009C) __sfr ADRESH;
 135
 136 __at(0x009D) __sfr ADCON0;
 137 __at(0x009D) volatile __ADCON0bits_t ADCON0bits;
 138
 139 __at(0x009E) __sfr ADCON1;
 140 __at(0x009E) volatile __ADCON1bits_t ADCON1bits;
 141
 142 __at(0x009F) __sfr ADACT;
 143 __at(0x009F) volatile __ADACTbits_t ADACTbits;
 144
 145 __at(0x010C) __sfr LATA;
 146 __at(0x010C) volatile __LATAbits_t LATAbits;
 147
 148 __at(0x0111) __sfr CM1CON0;
 149 __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits;
 150
 151 __at(0x0112) __sfr CM1CON1;
 152 __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits;
 153
 154 __at(0x0115) __sfr CMOUT;
 155 __at(0x0115) volatile __CMOUTbits_t CMOUTbits;
 156
 157 __at(0x0116) __sfr BORCON;
 158 __at(0x0116) volatile __BORCONbits_t BORCONbits;
 159
 160 __at(0x0117) __sfr FVRCON;
 161 __at(0x0117) volatile __FVRCONbits_t FVRCONbits;
 162
 163 __at(0x0118) __sfr DACCON0;
 164 __at(0x0118) volatile __DACCON0bits_t DACCON0bits;
 165
 166 __at(0x0119) __sfr DACCON1;
 167 __at(0x0119) volatile __DACCON1bits_t DACCON1bits;
 168
 169 __at(0x018C) __sfr ANSELA;
 170 __at(0x018C) volatile __ANSELAbits_t ANSELAbits;
 171
 172 __at(0x0197) __sfr VREGCON;
 173 __at(0x0197) volatile __VREGCONbits_t VREGCONbits;
 174
 175 __at(0x0199) __sfr RC1REG;
 176
 177 __at(0x0199) __sfr RCREG;
 178
 179 __at(0x0199) __sfr RCREG1;
 180
 181 __at(0x019A) __sfr TX1REG;
 182
 183 __at(0x019A) __sfr TXREG;
 184
 185 __at(0x019A) __sfr TXREG1;
 186
 187 __at(0x019B) __sfr SP1BRG;
 188
 189 __at(0x019B) __sfr SP1BRGL;
 190
 191 __at(0x019B) __sfr SPBRG;
 192
 193 __at(0x019B) __sfr SPBRG1;
 194
 195 __at(0x019B) __sfr SPBRGL;
 196
 197 __at(0x019C) __sfr SP1BRGH;
 198
 199 __at(0x019C) __sfr SPBRGH;
 200
 201 __at(0x019C) __sfr SPBRGH1;
 202
 203 __at(0x019D) __sfr RC1STA;
 204 __at(0x019D) volatile __RC1STAbits_t RC1STAbits;
 205
 206 __at(0x019D) __sfr RCSTA;
 207 __at(0x019D) volatile __RCSTAbits_t RCSTAbits;
 208
 209 __at(0x019D) __sfr RCSTA1;
 210 __at(0x019D) volatile __RCSTA1bits_t RCSTA1bits;
 211
 212 __at(0x019E) __sfr TX1STA;
 213 __at(0x019E) volatile __TX1STAbits_t TX1STAbits;
 214
 215 __at(0x019E) __sfr TXSTA;
 216 __at(0x019E) volatile __TXSTAbits_t TXSTAbits;
 217
 218 __at(0x019E) __sfr TXSTA1;
 219 __at(0x019E) volatile __TXSTA1bits_t TXSTA1bits;
 220
 221 __at(0x019F) __sfr BAUD1CON;
 222 __at(0x019F) volatile __BAUD1CONbits_t BAUD1CONbits;
 223
 224 __at(0x019F) __sfr BAUDCON;
 225 __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits;
 226
 227 __at(0x019F) __sfr BAUDCON1;
 228 __at(0x019F) volatile __BAUDCON1bits_t BAUDCON1bits;
 229
 230 __at(0x019F) __sfr BAUDCTL;
 231 __at(0x019F) volatile __BAUDCTLbits_t BAUDCTLbits;
 232
 233 __at(0x019F) __sfr BAUDCTL1;
 234 __at(0x019F) volatile __BAUDCTL1bits_t BAUDCTL1bits;
 235
 236 __at(0x020C) __sfr WPUA;
 237 __at(0x020C) volatile __WPUAbits_t WPUAbits;
 238
 239 __at(0x0211) __sfr SSP1BUF;
 240 __at(0x0211) volatile __SSP1BUFbits_t SSP1BUFbits;
 241
 242 __at(0x0211) __sfr SSPBUF;
 243 __at(0x0211) volatile __SSPBUFbits_t SSPBUFbits;
 244
 245 __at(0x0212) __sfr SSP1ADD;
 246 __at(0x0212) volatile __SSP1ADDbits_t SSP1ADDbits;
 247
 248 __at(0x0212) __sfr SSPADD;
 249 __at(0x0212) volatile __SSPADDbits_t SSPADDbits;
 250
 251 __at(0x0213) __sfr SSP1MSK;
 252 __at(0x0213) volatile __SSP1MSKbits_t SSP1MSKbits;
 253
 254 __at(0x0213) __sfr SSPMSK;
 255 __at(0x0213) volatile __SSPMSKbits_t SSPMSKbits;
 256
 257 __at(0x0214) __sfr SSP1STAT;
 258 __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits;
 259
 260 __at(0x0214) __sfr SSPSTAT;
 261 __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits;
 262
 263 __at(0x0215) __sfr SSP1CON;
 264 __at(0x0215) volatile __SSP1CONbits_t SSP1CONbits;
 265
 266 __at(0x0215) __sfr SSP1CON1;
 267 __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits;
 268
 269 __at(0x0215) __sfr SSPCON;
 270 __at(0x0215) volatile __SSPCONbits_t SSPCONbits;
 271
 272 __at(0x0215) __sfr SSPCON1;
 273 __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits;
 274
 275 __at(0x0216) __sfr SSP1CON2;
 276 __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits;
 277
 278 __at(0x0216) __sfr SSPCON2;
 279 __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits;
 280
 281 __at(0x0217) __sfr SSP1CON3;
 282 __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits;
 283
 284 __at(0x0217) __sfr SSPCON3;
 285 __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits;
 286
 287 __at(0x028C) __sfr ODCONA;
 288 __at(0x028C) volatile __ODCONAbits_t ODCONAbits;
 289
 290 __at(0x0291) __sfr CCPR1;
 291
 292 __at(0x0291) __sfr CCPR1L;
 293
 294 __at(0x0292) __sfr CCPR1H;
 295
 296 __at(0x0293) __sfr CCP1CON;
 297 __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits;
 298
 299 __at(0x0294) __sfr CCP1CAP;
 300 __at(0x0294) volatile __CCP1CAPbits_t CCP1CAPbits;
 301
 302 __at(0x0295) __sfr CCPR2;
 303
 304 __at(0x0295) __sfr CCPR2L;
 305
 306 __at(0x0296) __sfr CCPR2H;
 307
 308 __at(0x0297) __sfr CCP2CON;
 309 __at(0x0297) volatile __CCP2CONbits_t CCP2CONbits;
 310
 311 __at(0x0298) __sfr CCP2CAP;
 312 __at(0x0298) volatile __CCP2CAPbits_t CCP2CAPbits;
 313
 314 __at(0x029F) __sfr CCPTMRS;
 315 __at(0x029F) volatile __CCPTMRSbits_t CCPTMRSbits;
 316
 317 __at(0x030C) __sfr SLRCONA;
 318 __at(0x030C) volatile __SLRCONAbits_t SLRCONAbits;
 319
 320 __at(0x038C) __sfr INLVLA;
 321 __at(0x038C) volatile __INLVLAbits_t INLVLAbits;
 322
 323 __at(0x0391) __sfr IOCAP;
 324 __at(0x0391) volatile __IOCAPbits_t IOCAPbits;
 325
 326 __at(0x0392) __sfr IOCAN;
 327 __at(0x0392) volatile __IOCANbits_t IOCANbits;
 328
 329 __at(0x0393) __sfr IOCAF;
 330 __at(0x0393) volatile __IOCAFbits_t IOCAFbits;
 331
 332 __at(0x039A) __sfr CLKRCON;
 333 __at(0x039A) volatile __CLKRCONbits_t CLKRCONbits;
 334
 335 __at(0x039C) __sfr MDCON;
 336 __at(0x039C) volatile __MDCONbits_t MDCONbits;
 337
 338 __at(0x039D) __sfr MDSRC;
 339 __at(0x039D) volatile __MDSRCbits_t MDSRCbits;
 340
 341 __at(0x039E) __sfr MDCARH;
 342 __at(0x039E) volatile __MDCARHbits_t MDCARHbits;
 343
 344 __at(0x039F) __sfr MDCARL;
 345 __at(0x039F) volatile __MDCARLbits_t MDCARLbits;
 346
 347 __at(0x040C) __sfr CCDNA;
 348 __at(0x040C) volatile __CCDNAbits_t CCDNAbits;
 349
 350 __at(0x041F) __sfr CCDCON;
 351 __at(0x041F) volatile __CCDCONbits_t CCDCONbits;
 352
 353 __at(0x048C) __sfr CCDPA;
 354 __at(0x048C) volatile __CCDPAbits_t CCDPAbits;
 355
 356 __at(0x0498) __sfr NCO1ACC;
 357
 358 __at(0x0498) __sfr NCO1ACCL;
 359
 360 __at(0x0499) __sfr NCO1ACCH;
 361
 362 __at(0x049A) __sfr NCO1ACCU;
 363
 364 __at(0x049B) __sfr NCO1INC;
 365
 366 __at(0x049B) __sfr NCO1INCL;
 367
 368 __at(0x049C) __sfr NCO1INCH;
 369
 370 __at(0x049D) __sfr NCO1INCU;
 371
 372 __at(0x049E) __sfr NCO1CON;
 373 __at(0x049E) volatile __NCO1CONbits_t NCO1CONbits;
 374
 375 __at(0x049F) __sfr NCO1CLK;
 376
 377 __at(0x0617) __sfr PWM5DCL;
 378 __at(0x0617) volatile __PWM5DCLbits_t PWM5DCLbits;
 379
 380 __at(0x0618) __sfr PWM5DCH;
 381 __at(0x0618) volatile __PWM5DCHbits_t PWM5DCHbits;
 382
 383 __at(0x0619) __sfr PWM5CON;
 384 __at(0x0619) volatile __PWM5CONbits_t PWM5CONbits;
 385
 386 __at(0x0619) __sfr PWM5CON0;
 387 __at(0x0619) volatile __PWM5CON0bits_t PWM5CON0bits;
 388
 389 __at(0x061A) __sfr PWM6DCL;
 390 __at(0x061A) volatile __PWM6DCLbits_t PWM6DCLbits;
 391
 392 __at(0x061B) __sfr PWM6DCH;
 393 __at(0x061B) volatile __PWM6DCHbits_t PWM6DCHbits;
 394
 395 __at(0x061C) __sfr PWM6CON;
 396 __at(0x061C) volatile __PWM6CONbits_t PWM6CONbits;
 397
 398 __at(0x061C) __sfr PWM6CON0;
 399 __at(0x061C) volatile __PWM6CON0bits_t PWM6CON0bits;
 400
 401 __at(0x0691) __sfr CWG1CLKCON;
 402 __at(0x0691) volatile __CWG1CLKCONbits_t CWG1CLKCONbits;
 403
 404 __at(0x0692) __sfr CWG1DAT;
 405 __at(0x0692) volatile __CWG1DATbits_t CWG1DATbits;
 406
 407 __at(0x0693) __sfr CWG1DBR;
 408 __at(0x0693) volatile __CWG1DBRbits_t CWG1DBRbits;
 409
 410 __at(0x0694) __sfr CWG1DBF;
 411 __at(0x0694) volatile __CWG1DBFbits_t CWG1DBFbits;
 412
 413 __at(0x0695) __sfr CWG1CON0;
 414 __at(0x0695) volatile __CWG1CON0bits_t CWG1CON0bits;
 415
 416 __at(0x0696) __sfr CWG1CON1;
 417 __at(0x0696) volatile __CWG1CON1bits_t CWG1CON1bits;
 418
 419 __at(0x0697) __sfr CWG1AS0;
 420 __at(0x0697) volatile __CWG1AS0bits_t CWG1AS0bits;
 421
 422 __at(0x0698) __sfr CWG1AS1;
 423 __at(0x0698) volatile __CWG1AS1bits_t CWG1AS1bits;
 424
 425 __at(0x0699) __sfr CWG1STR;
 426 __at(0x0699) volatile __CWG1STRbits_t CWG1STRbits;
 427
 428 __at(0x0891) __sfr NVMADR;
 429
 430 __at(0x0891) __sfr NVMADRL;
 431 __at(0x0891) volatile __NVMADRLbits_t NVMADRLbits;
 432
 433 __at(0x0892) __sfr NVMADRH;
 434 __at(0x0892) volatile __NVMADRHbits_t NVMADRHbits;
 435
 436 __at(0x0893) __sfr NVMDAT;
 437
 438 __at(0x0893) __sfr NVMDATL;
 439 __at(0x0893) volatile __NVMDATLbits_t NVMDATLbits;
 440
 441 __at(0x0894) __sfr NVMDATH;
 442 __at(0x0894) volatile __NVMDATHbits_t NVMDATHbits;
 443
 444 __at(0x0895) __sfr NVMCON1;
 445 __at(0x0895) volatile __NVMCON1bits_t NVMCON1bits;
 446
 447 __at(0x0896) __sfr NVMCON2;
 448
 449 __at(0x089B) __sfr PCON0;
 450 __at(0x089B) volatile __PCON0bits_t PCON0bits;
 451
 452 __at(0x0911) __sfr PMD0;
 453 __at(0x0911) volatile __PMD0bits_t PMD0bits;
 454
 455 __at(0x0912) __sfr PMD1;
 456 __at(0x0912) volatile __PMD1bits_t PMD1bits;
 457
 458 __at(0x0913) __sfr PMD2;
 459 __at(0x0913) volatile __PMD2bits_t PMD2bits;
 460
 461 __at(0x0914) __sfr PMD3;
 462 __at(0x0914) volatile __PMD3bits_t PMD3bits;
 463
 464 __at(0x0915) __sfr PMD4;
 465 __at(0x0915) volatile __PMD4bits_t PMD4bits;
 466
 467 __at(0x0916) __sfr PMD5;
 468 __at(0x0916) volatile __PMD5bits_t PMD5bits;
 469
 470 __at(0x0918) __sfr CPUDOZE;
 471 __at(0x0918) volatile __CPUDOZEbits_t CPUDOZEbits;
 472
 473 __at(0x0919) __sfr OSCCON1;
 474 __at(0x0919) volatile __OSCCON1bits_t OSCCON1bits;
 475
 476 __at(0x091A) __sfr OSCCON2;
 477 __at(0x091A) volatile __OSCCON2bits_t OSCCON2bits;
 478
 479 __at(0x091B) __sfr OSCCON3;
 480 __at(0x091B) volatile __OSCCON3bits_t OSCCON3bits;
 481
 482 __at(0x091C) __sfr OSCSTAT1;
 483 __at(0x091C) volatile __OSCSTAT1bits_t OSCSTAT1bits;
 484
 485 __at(0x091D) __sfr OSCEN;
 486 __at(0x091D) volatile __OSCENbits_t OSCENbits;
 487
 488 __at(0x091E) __sfr OSCTUNE;
 489 __at(0x091E) volatile __OSCTUNEbits_t OSCTUNEbits;
 490
 491 __at(0x091F) __sfr OSCFRQ;
 492 __at(0x091F) volatile __OSCFRQbits_t OSCFRQbits;
 493
 494 __at(0x0E0F) __sfr PPSLOCK;
 495 __at(0x0E0F) volatile __PPSLOCKbits_t PPSLOCKbits;
 496
 497 __at(0x0E10) __sfr INTPPS;
 498 __at(0x0E10) volatile __INTPPSbits_t INTPPSbits;
 499
 500 __at(0x0E11) __sfr T0CKIPPS;
 501 __at(0x0E11) volatile __T0CKIPPSbits_t T0CKIPPSbits;
 502
 503 __at(0x0E12) __sfr T1CKIPPS;
 504 __at(0x0E12) volatile __T1CKIPPSbits_t T1CKIPPSbits;
 505
 506 __at(0x0E13) __sfr T1GPPS;
 507 __at(0x0E13) volatile __T1GPPSbits_t T1GPPSbits;
 508
 509 __at(0x0E14) __sfr CCP1PPS;
 510 __at(0x0E14) volatile __CCP1PPSbits_t CCP1PPSbits;
 511
 512 __at(0x0E15) __sfr CCP2PPS;
 513 __at(0x0E15) volatile __CCP2PPSbits_t CCP2PPSbits;
 514
 515 __at(0x0E18) __sfr CWG1PPS;
 516 __at(0x0E18) volatile __CWG1PPSbits_t CWG1PPSbits;
 517
 518 __at(0x0E1A) __sfr MDCIN1PPS;
 519 __at(0x0E1A) volatile __MDCIN1PPSbits_t MDCIN1PPSbits;
 520
 521 __at(0x0E1B) __sfr MDCIN2PPS;
 522 __at(0x0E1B) volatile __MDCIN2PPSbits_t MDCIN2PPSbits;
 523
 524 __at(0x0E1C) __sfr MDMINPPS;
 525 __at(0x0E1C) volatile __MDMINPPSbits_t MDMINPPSbits;
 526
 527 __at(0x0E20) __sfr SSP1CLKPPS;
 528 __at(0x0E20) volatile __SSP1CLKPPSbits_t SSP1CLKPPSbits;
 529
 530 __at(0x0E21) __sfr SSP1DATPPS;
 531 __at(0x0E21) volatile __SSP1DATPPSbits_t SSP1DATPPSbits;
 532
 533 __at(0x0E22) __sfr SSP1SSPPS;
 534 __at(0x0E22) volatile __SSP1SSPPSbits_t SSP1SSPPSbits;
 535
 536 __at(0x0E24) __sfr RXPPS;
 537 __at(0x0E24) volatile __RXPPSbits_t RXPPSbits;
 538
 539 __at(0x0E25) __sfr TXPPS;
 540 __at(0x0E25) volatile __TXPPSbits_t TXPPSbits;
 541
 542 __at(0x0E28) __sfr CLCIN0PPS;
 543 __at(0x0E28) volatile __CLCIN0PPSbits_t CLCIN0PPSbits;
 544
 545 __at(0x0E29) __sfr CLCIN1PPS;
 546 __at(0x0E29) volatile __CLCIN1PPSbits_t CLCIN1PPSbits;
 547
 548 __at(0x0E2A) __sfr CLCIN2PPS;
 549 __at(0x0E2A) volatile __CLCIN2PPSbits_t CLCIN2PPSbits;
 550
 551 __at(0x0E2B) __sfr CLCIN3PPS;
 552 __at(0x0E2B) volatile __CLCIN3PPSbits_t CLCIN3PPSbits;
 553
 554 __at(0x0E90) __sfr RA0PPS;
 555 __at(0x0E90) volatile __RA0PPSbits_t RA0PPSbits;
 556
 557 __at(0x0E91) __sfr RA1PPS;
 558 __at(0x0E91) volatile __RA1PPSbits_t RA1PPSbits;
 559
 560 __at(0x0E92) __sfr RA2PPS;
 561 __at(0x0E92) volatile __RA2PPSbits_t RA2PPSbits;
 562
 563 __at(0x0E94) __sfr RA4PPS;
 564 __at(0x0E94) volatile __RA4PPSbits_t RA4PPSbits;
 565
 566 __at(0x0E95) __sfr RA5PPS;
 567 __at(0x0E95) volatile __RA5PPSbits_t RA5PPSbits;
 568
 569 __at(0x0F0F) __sfr CLCDATA;
 570 __at(0x0F0F) volatile __CLCDATAbits_t CLCDATAbits;
 571
 572 __at(0x0F10) __sfr CLC1CON;
 573 __at(0x0F10) volatile __CLC1CONbits_t CLC1CONbits;
 574
 575 __at(0x0F11) __sfr CLC1POL;
 576 __at(0x0F11) volatile __CLC1POLbits_t CLC1POLbits;
 577
 578 __at(0x0F12) __sfr CLC1SEL0;
 579 __at(0x0F12) volatile __CLC1SEL0bits_t CLC1SEL0bits;
 580
 581 __at(0x0F13) __sfr CLC1SEL1;
 582 __at(0x0F13) volatile __CLC1SEL1bits_t CLC1SEL1bits;
 583
 584 __at(0x0F14) __sfr CLC1SEL2;
 585 __at(0x0F14) volatile __CLC1SEL2bits_t CLC1SEL2bits;
 586
 587 __at(0x0F15) __sfr CLC1SEL3;
 588 __at(0x0F15) volatile __CLC1SEL3bits_t CLC1SEL3bits;
 589
 590 __at(0x0F16) __sfr CLC1GLS0;
 591 __at(0x0F16) volatile __CLC1GLS0bits_t CLC1GLS0bits;
 592
 593 __at(0x0F17) __sfr CLC1GLS1;
 594 __at(0x0F17) volatile __CLC1GLS1bits_t CLC1GLS1bits;
 595
 596 __at(0x0F18) __sfr CLC1GLS2;
 597 __at(0x0F18) volatile __CLC1GLS2bits_t CLC1GLS2bits;
 598
 599 __at(0x0F19) __sfr CLC1GLS3;
 600 __at(0x0F19) volatile __CLC1GLS3bits_t CLC1GLS3bits;
 601
 602 __at(0x0F1A) __sfr CLC2CON;
 603 __at(0x0F1A) volatile __CLC2CONbits_t CLC2CONbits;
 604
 605 __at(0x0F1B) __sfr CLC2POL;
 606 __at(0x0F1B) volatile __CLC2POLbits_t CLC2POLbits;
 607
 608 __at(0x0F1C) __sfr CLC2SEL0;
 609 __at(0x0F1C) volatile __CLC2SEL0bits_t CLC2SEL0bits;
 610
 611 __at(0x0F1D) __sfr CLC2SEL1;
 612 __at(0x0F1D) volatile __CLC2SEL1bits_t CLC2SEL1bits;
 613
 614 __at(0x0F1E) __sfr CLC2SEL2;
 615 __at(0x0F1E) volatile __CLC2SEL2bits_t CLC2SEL2bits;
 616
 617 __at(0x0F1F) __sfr CLC2SEL3;
 618 __at(0x0F1F) volatile __CLC2SEL3bits_t CLC2SEL3bits;
 619
 620 __at(0x0F20) __sfr CLC2GLS0;
 621 __at(0x0F20) volatile __CLC2GLS0bits_t CLC2GLS0bits;
 622
 623 __at(0x0F21) __sfr CLC2GLS1;
 624 __at(0x0F21) volatile __CLC2GLS1bits_t CLC2GLS1bits;
 625
 626 __at(0x0F22) __sfr CLC2GLS2;
 627 __at(0x0F22) volatile __CLC2GLS2bits_t CLC2GLS2bits;
 628
 629 __at(0x0F23) __sfr CLC2GLS3;
 630 __at(0x0F23) volatile __CLC2GLS3bits_t CLC2GLS3bits;
 631
 632 __at(0x0FE4) __sfr STATUS_SHAD;
 633 __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits;
 634
 635 __at(0x0FE5) __sfr WREG_SHAD;
 636
 637 __at(0x0FE6) __sfr BSR_SHAD;
 638
 639 __at(0x0FE7) __sfr PCLATH_SHAD;
 640
 641 __at(0x0FE8) __sfr FSR0L_SHAD;
 642
 643 __at(0x0FE9) __sfr FSR0H_SHAD;
 644
 645 __at(0x0FEA) __sfr FSR1L_SHAD;
 646
 647 __at(0x0FEB) __sfr FSR1H_SHAD;
 648
 649 __at(0x0FED) __sfr STKPTR;
 650
 651 __at(0x0FEE) __sfr TOSL;
 652
 653 __at(0x0FEF) __sfr TOSH;