sdcc/device/non-free/lib/pic14/libdev/pic16lf1823.c

   1 /*
   2  * This definitions of the PIC16LF1823 MCU.
   3  *
   4  * This file is part of the GNU PIC library for SDCC, originally
   5  * created by Molnar Karoly <molnarkaroly@users.sf.net> 2016.
   6  *
   7  * This file is generated automatically by the cinc2h.pl, 2016-04-13 17:23:19 UTC.
   8  *
   9  * SDCC is licensed under the GNU Public license (GPL) v2. Note that
  10  * this license covers the code to the compiler and other executables,
  11  * but explicitly does not cover any code or objects generated by sdcc.
  12  *
  13  * For pic device libraries and header files which are derived from
  14  * Microchip header (.inc) and linker script (.lkr) files Microchip
  15  * requires that "The header files should state that they are only to be
  16  * used with authentic Microchip devices" which makes them incompatible
  17  * with the GPL. Pic device libraries and header files are located at
  18  * non-free/lib and non-free/include directories respectively.
  19  * Sdcc should be run with the --use-non-free command line option in
  20  * order to include non-free header files and libraries.
  21  *
  22  * See http://sdcc.sourceforge.net/ for the latest information on sdcc.
  23  */
  24
  25 #include <pic16lf1823.h>
  26
  27 //==============================================================================
  28
  29 __at(0x0000) __sfr INDF0;
  30
  31 __at(0x0001) __sfr INDF1;
  32
  33 __at(0x0002) __sfr PCL;
  34
  35 __at(0x0003) __sfr STATUS;
  36 __at(0x0003) volatile __STATUSbits_t STATUSbits;
  37
  38 __at(0x0004) __sfr FSR0;
  39
  40 __at(0x0004) __sfr FSR0L;
  41
  42 __at(0x0005) __sfr FSR0H;
  43
  44 __at(0x0006) __sfr FSR1;
  45
  46 __at(0x0006) __sfr FSR1L;
  47
  48 __at(0x0007) __sfr FSR1H;
  49
  50 __at(0x0008) __sfr BSR;
  51 __at(0x0008) volatile __BSRbits_t BSRbits;
  52
  53 __at(0x0009) __sfr WREG;
  54
  55 __at(0x000A) __sfr PCLATH;
  56
  57 __at(0x000B) __sfr INTCON;
  58 __at(0x000B) volatile __INTCONbits_t INTCONbits;
  59
  60 __at(0x000C) __sfr PORTA;
  61 __at(0x000C) volatile __PORTAbits_t PORTAbits;
  62
  63 __at(0x000E) __sfr PORTC;
  64 __at(0x000E) volatile __PORTCbits_t PORTCbits;
  65
  66 __at(0x0011) __sfr PIR1;
  67 __at(0x0011) volatile __PIR1bits_t PIR1bits;
  68
  69 __at(0x0012) __sfr PIR2;
  70 __at(0x0012) volatile __PIR2bits_t PIR2bits;
  71
  72 __at(0x0015) __sfr TMR0;
  73
  74 __at(0x0016) __sfr TMR1;
  75
  76 __at(0x0016) __sfr TMR1L;
  77
  78 __at(0x0017) __sfr TMR1H;
  79
  80 __at(0x0018) __sfr T1CON;
  81 __at(0x0018) volatile __T1CONbits_t T1CONbits;
  82
  83 __at(0x0019) __sfr T1GCON;
  84 __at(0x0019) volatile __T1GCONbits_t T1GCONbits;
  85
  86 __at(0x001A) __sfr TMR2;
  87
  88 __at(0x001B) __sfr PR2;
  89
  90 __at(0x001C) __sfr T2CON;
  91 __at(0x001C) volatile __T2CONbits_t T2CONbits;
  92
  93 __at(0x001E) __sfr CPSCON0;
  94 __at(0x001E) volatile __CPSCON0bits_t CPSCON0bits;
  95
  96 __at(0x001F) __sfr CPSCON1;
  97 __at(0x001F) volatile __CPSCON1bits_t CPSCON1bits;
  98
  99 __at(0x008C) __sfr TRISA;
 100 __at(0x008C) volatile __TRISAbits_t TRISAbits;
 101
 102 __at(0x008E) __sfr TRISC;
 103 __at(0x008E) volatile __TRISCbits_t TRISCbits;
 104
 105 __at(0x0091) __sfr PIE1;
 106 __at(0x0091) volatile __PIE1bits_t PIE1bits;
 107
 108 __at(0x0092) __sfr PIE2;
 109 __at(0x0092) volatile __PIE2bits_t PIE2bits;
 110
 111 __at(0x0095) __sfr OPTION_REG;
 112 __at(0x0095) volatile __OPTION_REGbits_t OPTION_REGbits;
 113
 114 __at(0x0096) __sfr PCON;
 115 __at(0x0096) volatile __PCONbits_t PCONbits;
 116
 117 __at(0x0097) __sfr WDTCON;
 118 __at(0x0097) volatile __WDTCONbits_t WDTCONbits;
 119
 120 __at(0x0098) __sfr OSCTUNE;
 121 __at(0x0098) volatile __OSCTUNEbits_t OSCTUNEbits;
 122
 123 __at(0x0099) __sfr OSCCON;
 124 __at(0x0099) volatile __OSCCONbits_t OSCCONbits;
 125
 126 __at(0x009A) __sfr OSCSTAT;
 127 __at(0x009A) volatile __OSCSTATbits_t OSCSTATbits;
 128
 129 __at(0x009B) __sfr ADRES;
 130
 131 __at(0x009B) __sfr ADRESL;
 132
 133 __at(0x009C) __sfr ADRESH;
 134
 135 __at(0x009D) __sfr ADCON0;
 136 __at(0x009D) volatile __ADCON0bits_t ADCON0bits;
 137
 138 __at(0x009E) __sfr ADCON1;
 139 __at(0x009E) volatile __ADCON1bits_t ADCON1bits;
 140
 141 __at(0x010C) __sfr LATA;
 142 __at(0x010C) volatile __LATAbits_t LATAbits;
 143
 144 __at(0x010E) __sfr LATC;
 145 __at(0x010E) volatile __LATCbits_t LATCbits;
 146
 147 __at(0x0111) __sfr CM1CON0;
 148 __at(0x0111) volatile __CM1CON0bits_t CM1CON0bits;
 149
 150 __at(0x0112) __sfr CM1CON1;
 151 __at(0x0112) volatile __CM1CON1bits_t CM1CON1bits;
 152
 153 __at(0x0113) __sfr CM2CON0;
 154 __at(0x0113) volatile __CM2CON0bits_t CM2CON0bits;
 155
 156 __at(0x0114) __sfr CM2CON1;
 157 __at(0x0114) volatile __CM2CON1bits_t CM2CON1bits;
 158
 159 __at(0x0115) __sfr CMOUT;
 160 __at(0x0115) volatile __CMOUTbits_t CMOUTbits;
 161
 162 __at(0x0116) __sfr BORCON;
 163 __at(0x0116) volatile __BORCONbits_t BORCONbits;
 164
 165 __at(0x0117) __sfr FVRCON;
 166 __at(0x0117) volatile __FVRCONbits_t FVRCONbits;
 167
 168 __at(0x0118) __sfr DACCON0;
 169 __at(0x0118) volatile __DACCON0bits_t DACCON0bits;
 170
 171 __at(0x0119) __sfr DACCON1;
 172 __at(0x0119) volatile __DACCON1bits_t DACCON1bits;
 173
 174 __at(0x011A) __sfr SRCON0;
 175 __at(0x011A) volatile __SRCON0bits_t SRCON0bits;
 176
 177 __at(0x011B) __sfr SRCON1;
 178 __at(0x011B) volatile __SRCON1bits_t SRCON1bits;
 179
 180 __at(0x011D) __sfr APFCON;
 181 __at(0x011D) volatile __APFCONbits_t APFCONbits;
 182
 183 __at(0x011D) __sfr APFCON0;
 184 __at(0x011D) volatile __APFCON0bits_t APFCON0bits;
 185
 186 __at(0x018C) __sfr ANSELA;
 187 __at(0x018C) volatile __ANSELAbits_t ANSELAbits;
 188
 189 __at(0x018E) __sfr ANSELC;
 190 __at(0x018E) volatile __ANSELCbits_t ANSELCbits;
 191
 192 __at(0x0191) __sfr EEADR;
 193
 194 __at(0x0191) __sfr EEADRL;
 195
 196 __at(0x0192) __sfr EEADRH;
 197
 198 __at(0x0193) __sfr EEDAT;
 199
 200 __at(0x0193) __sfr EEDATL;
 201
 202 __at(0x0194) __sfr EEDATH;
 203
 204 __at(0x0195) __sfr EECON1;
 205 __at(0x0195) volatile __EECON1bits_t EECON1bits;
 206
 207 __at(0x0196) __sfr EECON2;
 208
 209 __at(0x0199) __sfr RCREG;
 210
 211 __at(0x019A) __sfr TXREG;
 212
 213 __at(0x019B) __sfr SP1BRG;
 214
 215 __at(0x019B) __sfr SP1BRGL;
 216
 217 __at(0x019B) __sfr SPBRG;
 218
 219 __at(0x019B) __sfr SPBRGL;
 220
 221 __at(0x019C) __sfr SP1BRGH;
 222
 223 __at(0x019C) __sfr SPBRGH;
 224
 225 __at(0x019D) __sfr RCSTA;
 226 __at(0x019D) volatile __RCSTAbits_t RCSTAbits;
 227
 228 __at(0x019E) __sfr TXSTA;
 229 __at(0x019E) volatile __TXSTAbits_t TXSTAbits;
 230
 231 __at(0x019F) __sfr BAUDCON;
 232 __at(0x019F) volatile __BAUDCONbits_t BAUDCONbits;
 233
 234 __at(0x020C) __sfr WPUA;
 235 __at(0x020C) volatile __WPUAbits_t WPUAbits;
 236
 237 __at(0x020E) __sfr WPUC;
 238 __at(0x020E) volatile __WPUCbits_t WPUCbits;
 239
 240 __at(0x0211) __sfr SSP1BUF;
 241
 242 __at(0x0211) __sfr SSPBUF;
 243
 244 __at(0x0212) __sfr SSP1ADD;
 245
 246 __at(0x0212) __sfr SSPADD;
 247
 248 __at(0x0213) __sfr SSP1MSK;
 249
 250 __at(0x0213) __sfr SSPMSK;
 251
 252 __at(0x0214) __sfr SSP1STAT;
 253 __at(0x0214) volatile __SSP1STATbits_t SSP1STATbits;
 254
 255 __at(0x0214) __sfr SSPSTAT;
 256 __at(0x0214) volatile __SSPSTATbits_t SSPSTATbits;
 257
 258 __at(0x0215) __sfr SSP1CON1;
 259 __at(0x0215) volatile __SSP1CON1bits_t SSP1CON1bits;
 260
 261 __at(0x0215) __sfr SSPCON;
 262 __at(0x0215) volatile __SSPCONbits_t SSPCONbits;
 263
 264 __at(0x0215) __sfr SSPCON1;
 265 __at(0x0215) volatile __SSPCON1bits_t SSPCON1bits;
 266
 267 __at(0x0216) __sfr SSP1CON2;
 268 __at(0x0216) volatile __SSP1CON2bits_t SSP1CON2bits;
 269
 270 __at(0x0216) __sfr SSPCON2;
 271 __at(0x0216) volatile __SSPCON2bits_t SSPCON2bits;
 272
 273 __at(0x0217) __sfr SSP1CON3;
 274 __at(0x0217) volatile __SSP1CON3bits_t SSP1CON3bits;
 275
 276 __at(0x0217) __sfr SSPCON3;
 277 __at(0x0217) volatile __SSPCON3bits_t SSPCON3bits;
 278
 279 __at(0x0291) __sfr CCPR1;
 280
 281 __at(0x0291) __sfr CCPR1L;
 282
 283 __at(0x0292) __sfr CCPR1H;
 284
 285 __at(0x0293) __sfr CCP1CON;
 286 __at(0x0293) volatile __CCP1CONbits_t CCP1CONbits;
 287
 288 __at(0x0294) __sfr PWM1CON;
 289 __at(0x0294) volatile __PWM1CONbits_t PWM1CONbits;
 290
 291 __at(0x0295) __sfr CCP1AS;
 292 __at(0x0295) volatile __CCP1ASbits_t CCP1ASbits;
 293
 294 __at(0x0295) __sfr ECCP1AS;
 295 __at(0x0295) volatile __ECCP1ASbits_t ECCP1ASbits;
 296
 297 __at(0x0296) __sfr PSTR1CON;
 298 __at(0x0296) volatile __PSTR1CONbits_t PSTR1CONbits;
 299
 300 __at(0x0391) __sfr IOCAP;
 301 __at(0x0391) volatile __IOCAPbits_t IOCAPbits;
 302
 303 __at(0x0392) __sfr IOCAN;
 304 __at(0x0392) volatile __IOCANbits_t IOCANbits;
 305
 306 __at(0x0393) __sfr IOCAF;
 307 __at(0x0393) volatile __IOCAFbits_t IOCAFbits;
 308
 309 __at(0x039A) __sfr CLKRCON;
 310 __at(0x039A) volatile __CLKRCONbits_t CLKRCONbits;
 311
 312 __at(0x039C) __sfr MDCON;
 313 __at(0x039C) volatile __MDCONbits_t MDCONbits;
 314
 315 __at(0x039D) __sfr MDSRC;
 316 __at(0x039D) volatile __MDSRCbits_t MDSRCbits;
 317
 318 __at(0x039E) __sfr MDCARL;
 319 __at(0x039E) volatile __MDCARLbits_t MDCARLbits;
 320
 321 __at(0x039F) __sfr MDCARH;
 322 __at(0x039F) volatile __MDCARHbits_t MDCARHbits;
 323
 324 __at(0x0FE4) __sfr STATUS_SHAD;
 325 __at(0x0FE4) volatile __STATUS_SHADbits_t STATUS_SHADbits;
 326
 327 __at(0x0FE5) __sfr WREG_SHAD;
 328
 329 __at(0x0FE6) __sfr BSR_SHAD;
 330
 331 __at(0x0FE7) __sfr PCLATH_SHAD;
 332
 333 __at(0x0FE8) __sfr FSR0L_SHAD;
 334
 335 __at(0x0FE9) __sfr FSR0H_SHAD;
 336
 337 __at(0x0FEA) __sfr FSR1L_SHAD;
 338
 339 __at(0x0FEB) __sfr FSR1H_SHAD;
 340
 341 __at(0x0FED) __sfr STKPTR;
 342
 343 __at(0x0FEE) __sfr TOSL;
 344
 345 __at(0x0FEF) __sfr TOSH;