?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
struct / union in initializer, RFE #901.
[sdcc.git] / sdcc / sdas / as8xcxxx / ds8mch.c
blob7651a8a68cc1bc67763d7d078ef2d9503e405ff5
1 /* ds8mch.c */
2
3 /*
4 * Copyright (C) 1998-2009 Alan R. Baldwin
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 *
19 *
20 * Alan R. Baldwin
21 * 721 Berkeley St.
22 * Kent, Ohio 44240
23 *
24 * This Assember Ported by
25 * jhartman at compuserve dot com
26 * noice at noicedebugger dot com
27 *
28 * Modified from i51pst.c
29 * Bill McKinnon
30 * w_mckinnon at conknet dot com
31 *
32 */
33
34 #include "asxxxx.h"
35 #include "ds8.h"
36
37 char *cpu = "Dallas Semiconductor [User Defined]";
38 char *dsft = "asm";
39
40 static int amode;
41 static char buff[80];
42 static int ds8_bytes;
43 static int mchtyp;
44
45 /*
46 * Opcode Cycle Definitions
47 */
48 #define OPCY_SDP ((char) (0xFF))
49 #define OPCY_ERR ((char) (0xFE))
50
51 /* OPCY_NONE ((char) (0x80)) */
52 /* OPCY_MASK ((char) (0x7F)) */
53
54 #define OPCY_CPU ((char) (0xFD))
55 #define OPCY_AMODE ((char) (0xFC))
56 #define OPCY_BITS ((char) (0xFB))
57
58
59 #define UN ((char) (OPCY_NONE | 0x00))
60
61 /*
62 * ds8xcxxx Cycle Count
63 *
64 * opcycles = ds8pg1[opcode]
65 */
66 static char ds8pg1[256] = {
67 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
68 /*--*--* - - - - - - - - - - - - - - - - */
69 /*00*/ 4,12,16, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
70 /*10*/ 12,12,16, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
71 /*20*/ 12,12,16, 4, 8, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
72 /*30*/ 12,12,16, 4, 8, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
73 /*40*/ 12,12, 8,12, 8, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
74 /*50*/ 12,12, 8,12, 8, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
75 /*60*/ 12,12, 8,12, 8, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
76 /*70*/ 12,12, 8,12, 8,12, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
77 /*80*/ 12,12, 8,12,20,12, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
78 /*90*/ 12,12, 8,12, 8, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
79 /*A0*/ 8,12, 8,12,20,UN, 8, 8, 8, 8, 8, 8, 8, 8, 8, 8,
80 /*B0*/ 8,12, 8, 4,16,16,16,16,16,16,16,16,16,16,16,16,
81 /*C0*/ 8,12, 8, 4, 4, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
82 /*D0*/ 8,12, 8, 4, 4,16, 4, 4,12,12,12,12,12,12,12,12,
83 /*E0*/ 8,12, 8, 8, 4, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4,
84 /*F0*/ 8,12, 8, 8, 4, 8, 4, 4, 4, 4, 4, 4, 4, 4, 4, 4
85 };
86
87 /*
88 * Process machine ops.
89 */
90 VOID
91 machine(struct mne *mp)
92 {
93 char *p, *str;
94 char pid[NINPUT], id[NINPUT];
95 int c, d, t, t1, v1;
96 a_uint op;
97 struct sym *sp;
98 struct expr e, e1, e2;
99
100 clrexpr(&e);
101 clrexpr(&e1);
102 clrexpr(&e2);
103
104 op = mp->m_valu;
105 switch (mp->m_type) {
106
107 case S_CPU:
108 opcycles = OPCY_CPU;
109 lmode = SLIST;
110 switch(op) {
111 default: op = DS8XCXXX;
112 case DS8XCXXX: v1 = 2; str = "DS8XCXXX"; sym[2].s_addr = X_DS8XCXXX; break;
113 case DS80C310: v1 = 2; str = "DS80C310"; sym[2].s_addr = X_DS80C310; break;
114 case DS80C320: v1 = 2; str = "DS80C320"; sym[2].s_addr = X_DS80C320; break;
115 case DS80C323: v1 = 2; str = "DS80C323"; sym[2].s_addr = X_DS80C323; break;
116 case DS80C390: v1 = 3; str = "DS80C390"; sym[2].s_addr = X_DS80C390; break;
117 case DS83C520: v1 = 2; str = "DS83C520"; sym[2].s_addr = X_DS83C520; break;
118 case DS83C530: v1 = 2; str = "DS83C530"; sym[2].s_addr = X_DS83C530; break;
119 case DS83C550: v1 = 2; str = "DS83C550"; sym[2].s_addr = X_DS83C550; break;
120 case DS87C520: v1 = 2; str = "DS87C520"; sym[2].s_addr = X_DS87C520; break;
121 case DS87C530: v1 = 2; str = "DS87C530"; sym[2].s_addr = X_DS87C530; break;
122 case DS87C550: v1 = 2; str = "DS87C550"; sym[2].s_addr = X_DS87C550; break;
123 case DS______: v1 = 2; str = "DS______"; sym[2].s_addr = X_DS______;
124 if (more()) {
125 str = p = pid;
126 d = getnb();
127 while ((c = get()) != d) {
128 if (c == '\0') {
129 xerr('q', "Unquoted argument.");
130 }
131 if (p < &pid[sizeof(pid)-3]) {
132 *p++ = c;
133 } else {
134 break;
135 }
136 }
137 *p = 0;
138 }
139 break;
140 }
141 if (op != 0) {
142 ds8_bytes = v1;
143 exprmasks(v1);
144 }
145 mchtyp = (int) op;
146
147 /* GCC 10.2.0 error [-Wformat-overflow=] ? */
148 /* sprintf(id, "__%s", str); */
149 memcpy(id, "__", 2);
150 memcpy(&id[2], str, strlen(str)+1);
151 sp = lookup(id);
152 if (sp->s_type != S_NEW && (sp->s_flag & S_ASG) == 0) {
153 err('m');
154 }
155 sp->s_type = S_USER;
156 sp->s_addr = 1;
157 sp->s_flag |= S_ASG;
158
159 /* GCC 10.2.0 error [-Wformat-overflow=] ? */
160 /* sprintf(buff, "%s %s", DS_CPU, str); */
161 t = strlen(DS_CPU);
162 memcpy(buff, DS_CPU, t);
163 memcpy(&buff[t], " ", 1);
164 t1 = strlen(str);
165 memcpy(&buff[t+1], str, t1+1);
166 cpu = buff;
167
168 sp = lookup("__SFR_BITS");
169 if (sp->s_type != S_NEW && (sp->s_flag & S_ASG) == 0) {
170 err('m');
171 }
172 sp->s_type = S_USER;
173 sp->s_flag |= S_ASG;
174
175 if (more()) {
176 expr(&e, 0);
177 abscheck(&e);
178 sp->s_addr = e.e_addr;
179 } else {
180 sp->s_addr = 1;
181 }
182 break;
183
184 case S_AMODE:
185 opcycles = OPCY_AMODE;
186 if ((mchtyp != 0) && (mchtyp != DS80C390)) {
187 xerr('o', "Not a DS80C390 instruction.");
188 break;
189 } else
190 if ((mchtyp == 0) && ((a_bytes < 2) || (a_bytes > 3))) {
191 xerr('o', "Not a 16 or 24 Bit machine.");
192 break;
193 }
194 expr(&e, 0);
195 abscheck(&e);
196 amode = (int) e.e_addr;
197 if ((amode < 0) || (amode > 2)) {
198 amode = 0;
199 xerr('o', "Valid values are 0 -> 2.");
200 }
201 if ((c = getnb()) == ',') {
202 expr(&e1, 0);
203 abscheck(&e1);
204 if (e1.e_addr != 0) {
205 /* mov ta,#0aah */ outab(0x075); outab(0x0C7); outab(0x0AA);
206 /* mov ta,#055h */ outab(0x075); outab(0x0C7); outab(0x055);
207 /* mov acon,#amode */ outab(0x075); outab(0x09D); outab(amode);
208 } else {
209 lmode = SLIST;
210 }
211 } else {
212 unget(c);
213 lmode = SLIST;
214 }
215 break;
216
217 case S_BITS:
218 if (ds8_bytes == 0) {
219 ds8_bytes = (int) op;
220 exprmasks(ds8_bytes);
221 } else
222 if (ds8_bytes != (int) op) {
223 err('m');
224 }
225 opcycles = OPCY_BITS;
226 lmode = SLIST;
227 break;
228
229 case S_INH:
230 outab(op);
231 break;
232
233 case S_JMP11:
234 expr(&e, 0);
235 if (amode == 2) {
236 outr3bm(&e, R_J19, op);
237 } else {
238 outrwm(&e, R_J11, op);
239 }
240 break;
241
242 case S_JMP16:
243 expr(&e, 0);
244 outab(op);
245 if (amode == 2) {
246 outr3b(&e, R_NORM);
247 } else {
248 outrw(&e, R_NORM);
249 }
250 break;
251
252 case S_ACC:
253 t = addr(&e);
254 if (t != S_A)
255 xerr('a', "Argument must A.");
256 outab(op);
257 break;
258
259 case S_TYP1:
260 /* A, direct, @R0, @R1, R0 to R7. "INC" also allows DPTR */
261 t = addr(&e);
262
263 switch (t) {
264 case S_A:
265 outab(op + 4);
266 break;
267
268 case S_DIR:
269 case S_EXT:
270 /* Direct is also legal */
271 outab(op + 5);
272 outrb(&e, R_PAG0);
273 break;
274
275 case S_AT_R:
276 outab(op + 6 + e.e_addr);
277 break;
278
279 case S_REG:
280 outab(op + 8 + e.e_addr);
281 break;
282
283 case S_DPTR:
284 if (op != 0)
285 /* only INC (op=0) has DPTR mode */
286 xerr('a', "DPTR allowed only in INC instruction.");
287 else
288 outab( 0xA3);
289 break;
290
291 default:
292 xerr('a', "Invalid Addressing Mode.");
293 }
294 break;
295
296 case S_TYP2:
297 /* A,#imm; A,direct; A,@R0; A,@R1; A,R0 to A,R7 */
298 t = addr(&e);
299 if (t != S_A)
300 xerr('a', "First argument must be A.");
301 comma(1);
302 t1 = addr(&e1);
303
304 switch (t1) {
305 case S_IMMED:
306 outab(op + 4);
307 outrb(&e1, R_NORM);
308 break;
309
310 case S_DIR:
311 case S_EXT:
312 outab(op + 5);
313 outrb(&e1, R_PAG0);
314 break;
315
316 case S_AT_R:
317 outab(op + 6 + e1.e_addr);
318 break;
319
320 case S_REG:
321 outab(op + 8 + (e1.e_addr));
322 break;
323
324 default:
325 xerr('a', "Invalid Addressing Mode.");
326 }
327 break;
328
329 case S_TYP3:
330 /* dir,A; dir,#imm;
331 * A,#imm; A,direct; A,@R0; A,@R1; A,R0 to A,R7
332 * C,direct; C,/direct
333 */
334 t = addr(&e);
335 comma(1);
336 t1 = addr(&e1);
337
338 switch (t) {
339 case S_DIR:
340 case S_EXT:
341 switch (t1) {
342 case S_A:
343 outab(op + 2);
344 outrb(&e, R_PAG0);
345 break;
346
347 case S_IMMED:
348 outab(op + 3);
349 outrb(&e, R_PAG0);
350 outrb(&e1, R_NORM);
351 break;
352
353 default:
354 xerr('a', "Invalid Addressing Mode.");
355 }
356 break;
357
358 case S_A:
359 switch (t1) {
360 case S_IMMED:
361 outab(op + 4);
362 outrb(&e1, R_NORM);
363 break;
364
365 case S_DIR:
366 case S_EXT:
367 outab(op + 5);
368 outrb(&e1, R_PAG0);
369 break;
370
371 case S_AT_R:
372 outab(op + 6 + e1.e_addr);
373 break;
374
375 case S_REG:
376 outab(op + 8 + e1.e_addr);
377 break;
378
379 default:
380 xerr('a', "Invalid Addressing Mode.");
381 }
382 break;
383
384 case S_C:
385 /* XRL has no boolean version. Trap it */
386 if (op == 0x60)
387 xerr('a', "XRL does not support boolean.");
388
389 switch (t1) {
390 case S_DIR:
391 case S_EXT:
392 outab(op + 0x32);
393 outrb(&e1, R_PAG0);
394 break;
395
396 case S_NOT_BIT:
397 outab(op + 0x60);
398 outrb(&e1, R_PAG0);
399 break;
400
401 default:
402 xerr('a', "Invalid Addressing Mode.");
403 }
404 break;
405
406 default:
407 xerr('a', "Invalid Addressing Mode.");
408 }
409 break;
410
411 case S_TYP4:
412 /* A,direct; A,@R0; A,@R1; A,R0 to A,R7 */
413 t = addr(&e);
414 if (t != S_A)
415 xerr('a', "First argument must be A.");
416 comma(1);
417 t1 = addr(&e1);
418
419 switch (t1) {
420 case S_DIR:
421 case S_EXT:
422 outab(op + 5);
423 outrb(&e1, R_PAG0);
424 break;
425
426 case S_AT_R:
427 outab(op + 6 + e1.e_addr);
428 break;
429
430 case S_REG:
431 outab(op + 8 + e1.e_addr);
432 break;
433
434 default:
435 xerr('a', "Invalid Addressing Mode.");
436 }
437 break;
438
439 /* MOV instruction, all modes */
440 case S_MOV:
441 t = addr(&e);
442 comma(1);
443 t1 = addr(&e1);
444
445 switch (t) {
446 case S_A:
447 switch (t1) {
448 case S_IMMED:
449 outab(0x74);
450 outrb(&e1, R_NORM);
451 break;
452
453 case S_DIR:
454 case S_EXT:
455 outab(0xE5);
456 outrb(&e1, R_PAG0);
457 break;
458
459 case S_AT_R:
460 outab(0xE6 + e1.e_addr);
461 break;
462
463 case S_REG:
464 outab(0xE8 + e1.e_addr);
465 break;
466
467 default:
468 xerr('a', "Invalid Addressing Mode.");
469 }
470 break;
471
472 case S_REG:
473 switch (t1) {
474 case S_A:
475 outab(0xF8 + e.e_addr);
476 break;
477
478 case S_IMMED:
479 outab(0x78 + e.e_addr);
480 outrb(&e1, R_NORM);
481 break;
482
483 case S_DIR:
484 case S_EXT:
485 outab(0xA8 + e.e_addr);
486 outrb(&e1, R_PAG0);
487 break;
488
489 default:
490 xerr('a', "Invalid Addressing Mode.");
491 }
492 break;
493
494 case S_DIR:
495 case S_EXT:
496 switch (t1) {
497 case S_A:
498 outab(0xF5);
499 outrb(&e, R_PAG0);
500 break;
501
502 case S_IMMED:
503 outab(0x75);
504 outrb(&e, R_PAG0);
505 outrb(&e1, R_NORM);
506 break;
507
508 case S_DIR:
509 case S_EXT:
510 outab(0x85);
511 outrb(&e1, R_PAG0);
512 outrb(&e, R_PAG0);
513 break;
514
515 case S_AT_R:
516 outab(0x86 + e1.e_addr);
517 outrb(&e, R_PAG0);
518 break;
519
520 case S_REG:
521 outab(0x88 + e1.e_addr);
522 outrb(&e, R_PAG0);
523 break;
524
525 case S_C:
526 outab(0x92);
527 outrb(&e, R_PAG0);
528 break;
529
530 default:
531 xerr('a', "Invalid Addressing Mode.");
532 }
533 break;
534
535 case S_AT_R:
536 switch (t1) {
537 case S_IMMED:
538 outab(0x76 + e.e_addr);
539 outrb(&e1, R_NORM);
540 break;
541
542 case S_DIR:
543 case S_EXT:
544 outab(0xA6 + e.e_addr);
545 outrb(&e1, R_PAG0);
546 break;
547
548 case S_A:
549 outab(0xF6 + e.e_addr);
550 break;
551
552 default:
553 xerr('a', "Invalid Addressing Mode.");
554 }
555 break;
556
557 case S_C:
558 if ((t1 != S_DIR) && (t1 != S_EXT))
559 xerr('a', "Second argument must be an address.");
560 outab(0xA2);
561 outrb(&e1, R_PAG0);
562 break;
563
564 case S_DPTR:
565 if (t1 != S_IMMED)
566 xerr('a', "#__ is required second argument.");
567 outab(0x90);
568 if (amode == 2)
569 outr3b(&e1, R_NORM);
570 else
571 outrw(&e1, R_NORM);
572 break;
573
574 default:
575 xerr('a', "Invalid Addressing Mode.");
576 }
577 break;
578
579 case S_BITBR: /* JB, JBC, JNB bit,rel */
580 /* Branch on bit set/clear */
581 t = addr(&e);
582 if ((t != S_DIR) && (t != S_EXT))
583 xerr('a', "Argument must be an address.");
584 /* sdcc svn rev #4994: fixed bug 1865114 */
585 comma(1);
586 expr(&e1, 0);
587
588 outab(op);
589 outrb(&e, R_PAG0);
590
591 if (mchpcr(&e1)) {
592 v1 = (int) (e1.e_addr - dot.s_addr - 1);
593 /* sdcc svn rev #602: Fix some path problems */
594 if (pass == 2 && ((v1 < -128) || (v1 > 127)))
595 xerr('a', "Branching Range Exceeded.");
596 outab(v1);
597 } else {
598 outrb(&e1, R_PCR);
599 }
600 if (e1.e_mode != S_USER)
601 rerr();
602 break;
603
604 case S_BR: /* JC, JNC, JZ, JNZ */
605 /* Relative branch */
606 /* sdcc svn rev #4994: fixed bug 1865114 */
607 expr(&e1, 0);
608 outab(op);
609
610 if (mchpcr(&e1)) {
611 v1 = (int) (e1.e_addr - dot.s_addr - 1);
612 /* sdcc svn rev #602: Fix some path problems */
613 if (pass == 2 && ((v1 < -128) || (v1 > 127)))
614 xerr('a', "Branching Range Exceeded.");
615 outab(v1);
616 } else {
617 outrb(&e1, R_PCR);
618 }
619 if (e1.e_mode != S_USER)
620 rerr();
621 break;
622
623 case S_CJNE:
624 /* A,#; A,dir; @R0,#; @R1,#; Rn,# */
625 t = addr(&e);
626 comma(1);
627 t1 = addr(&e1);
628
629 /* Benny */
630 comma(1);
631 expr(&e2, 0);
632
633 switch (t) {
634 case S_A:
635 if (t1 == S_IMMED) {
636 outab(op + 4);
637 outrb(&e1, R_NORM);
638 }
639 else if ((t1 == S_DIR) || (t1 == S_EXT)) {
640 outab(op + 5);
641 outrb(&e1, R_PAG0);
642 }
643 else
644 xerr('a', "Invalid Addressing Mode.");
645 break;
646
647 case S_AT_R:
648 outab(op + 6 + e.e_addr);
649 if (t1 != S_IMMED)
650 xerr('a', "#__ is required second argument.");
651 outrb(&e1, R_NORM);
652 break;
653
654 case S_REG:
655 outab(op + 8 + e.e_addr);
656 if (t1 != S_IMMED)
657 xerr('a', "#__ is required second argument.");
658 outrb(&e1, R_NORM);
659 break;
660
661 default:
662 xerr('a', "Invalid Addressing Mode.");
663 break;
664 }
665
666 /* branch destination */
667 if (mchpcr(&e2)) {
668 v1 = (int) (e2.e_addr - dot.s_addr - 1);
669 /* sdcc svn rev #602: Fix some path problems */
670 if (pass == 2 && ((v1 < -128) || (v1 > 127)))
671 xerr('a', "Branching Range Exceeded.");
672 outab(v1);
673 } else {
674 outrb(&e2, R_PCR);
675 }
676 if (e2.e_mode != S_USER)
677 rerr();
678 break;
679
680 case S_DJNZ:
681 /* Dir,dest; Reg,dest */
682 t = addr(&e);
683 /* sdcc svn rev #4994: fixed bug 1865114 */
684 comma(1);
685 expr(&e1, 0);
686
687 switch (t) {
688 case S_DIR:
689 case S_EXT:
690 outab(op + 5);
691 outrb(&e, R_PAG0);
692 break;
693
694 case S_REG:
695 outab(op + 8 + e.e_addr);
696 break;
697
698 default:
699 xerr('a', "Invalid Addressing Mode.");
700 }
701
702 /* branch destination */
703 /* sdcc svn rev #4994: fixed bug 1865114 */
704 if (mchpcr(&e1)) {
705 v1 = (int) (e1.e_addr - dot.s_addr - 1);
706 /* sdcc svn rev #602: Fix some path problems */
707 if (pass == 2 && ((v1 < -128) || (v1 > 127)))
708 xerr('a', "Branching Range Exceeded.");
709 outab(v1);
710 } else {
711 outrb(&e1, R_PCR);
712 }
713 if (e1.e_mode != S_USER)
714 rerr();
715 break;
716
717 case S_JMP:
718 /* @A+DPTR */
719 t = addr(&e);
720 if (t != S_AT_ADP)
721 xerr('a', "JMP @A+DPTR is the only allowed mode.");
722 outab(op);
723 break;
724
725 case S_MOVC:
726 /* A,@A+DPTR A,@A+PC */
727 t = addr(&e);
728 if (t != S_A)
729 xerr('a', "First argument must be A.");
730 comma(1);
731 t1 = addr(&e1);
732 if (t1 == S_AT_ADP)
733 outab(0x93);
734 else if (t1 == S_AT_APC)
735 outab(0x83);
736 else
737 xerr('a', "MOVC A,@A+DPTR; A,@A+PC are the allowed modes.");
738 break;
739
740 case S_MOVX:
741 /* A,@DPTR A,@R0 A,@R1 @DPTR,A @R0,A @R1,A */
742 t = addr(&e);
743 comma(1);
744 t1 = addr(&e1);
745
746 switch (t) {
747 case S_A:
748 switch (t1) {
749 case S_AT_DP:
750 outab(0xE0);
751 break;
752
753 case S_AT_R:
754 outab(0xE2 + e1.e_addr);
755 break;
756
757 default:
758 xerr('a', "Second argument must be @DPTR or @Rn.");
759 }
760 break;
761
762 case S_AT_DP:
763 if (t1 == S_A)
764 outab(0xF0);
765 else
766 xerr('a', "Second argument must A.");
767 break;
768
769 case S_AT_R:
770 if (t1 == S_A)
771 outab(0xF2 + e.e_addr);
772 else
773 xerr('a', "Second argument must A.");
774 break;
775
776 default:
777 xerr('a', "Invalid Addressing Mode.");
778 }
779 break;
780
781 /* MUL/DIV A,B */
782 case S_AB:
783 t = addr(&e);
784 if (t != S_RAB)
785 xerr('a', "A,B is the only valid argument.");
786 outab(op);
787 break;
788
789 /* CLR or CPL: A, C, or bit */
790 case S_ACBIT:
791 t = addr(&e);
792 switch (t) {
793 case S_A:
794 if (op == 0xB2)
795 outab(0xF4);
796 else
797 outab(0xE4);
798 break;
799
800 case S_C:
801 outab(op+1);
802 break;
803
804 case S_DIR:
805 case S_EXT:
806 outab(op);
807 outrb(&e, R_PAG0);
808 break;
809
810 default:
811 xerr('a', "Invalid Addressing Mode.");
812 }
813 break;
814
815 /* SETB C or bit */
816 case S_SETB:
817 t = addr(&e);
818 switch (t) {
819 case S_C:
820 outab(op+1);
821 break;
822
823 case S_DIR:
824 case S_EXT:
825 outab(op);
826 outrb(&e, R_PAG0);
827 break;
828
829 default:
830 xerr('a', "Invalid Addressing Mode.");
831 }
832 break;
833
834 /* direct */
835 case S_DIRECT:
836 t = addr(&e);
837 if (t == S_A) {
838 e.e_addr = 0xE0;
839 e.e_mode = S_DIR;
840 } else
841 if ((t != S_DIR) && (t != S_EXT)) {
842 xerr('a', "Argument must be an address.");
843 break;
844 }
845 outab(op);
846 outrb(&e, R_PAG0);
847 break;
848
849 /* XCHD A,@Rn */
850 case S_XCHD:
851 t = addr(&e);
852 if (t != S_A)
853 xerr('a', "First argument must A.");
854 comma(1);
855 t1 = addr(&e1);
856 switch (t1) {
857 case S_AT_R:
858 outab(op + e1.e_addr);
859 break;
860
861 default:
862 xerr('a', "Invalid Addressing Mode.");
863 }
864 break;
865
866 default:
867 opcycles = OPCY_ERR;
868 xerr('o', "Internal Opcode Error.");
869 break;
870 }
871 if (opcycles == OPCY_NONE) {
872 opcycles = ds8pg1[cb[0] & 0xFF];
873 }
874 }
875
876 /*
877 * Branch/Jump PCR Mode Check
878 */
879 int
880 mchpcr(struct expr *esp)
881 {
882 if (esp->e_base.e_ap == dot.s_area) {
883 return(1);
884 }
885 if (esp->e_flag==0 && esp->e_base.e_ap==NULL) {
886 /*
887 * Absolute Destination
888 *
889 * Use the global symbol '.__.ABS.'
890 * of value zero and force the assembler
891 * to use this absolute constant as the
892 * base value for the relocation.
893 */
894 esp->e_flag = 1;
895 esp->e_base.e_sp = &sym[1];
896 }
897 return(0);
898 }
899
900 /*
901 * Machine specific initialization
902 */
903
904 VOID
905 minit(void)
906 {
907 struct sym *sp;
908 struct PreDef *pd;
909 int i;
910 char pid[8];
911 char *p;
912
913 /*
914 * Byte Order
915 */
916 hilo = 1;
917
918 amode = 0;
919 /*
920 * First time only:
921 * add the pre-defined symbols to the table
922 * as local symbols.
923 */
924 if (pass == 0) {
925 ds8_bytes = 0;
926 mchtyp = X_DS8XCXXX;
927 sym[2].s_addr = X_DS8XCXXX;
928
929 pd = preDef;
930 while (pd->id) {
931 strcpy(pid, pd->id);
932 for (i=0; i<2; i++) {
933 /*
934 * i == 0, Create Upper Case Symbols
935 * i == 1, Create Lower Case Symbols
936 */
937 if (i == 1) {
938 p = pid;
939 while (*p) {
940 *p = ccase[*p & 0x007F];
941 p++;
942 }
943 }
944 sp = lookup(pid);
945 if (sp->s_type == S_NEW) {
946 sp->s_addr = pd->value;
947 sp->s_type = S_USER;
948 sp->s_flag = S_LCL | S_ASG;
949 }
950 }
951 pd++;
952 }
953 }
954 }
SDCC git mirror