?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
struct / union in initializer, RFE #901.
[sdcc.git] / sdcc / sdas / asrab / rabmch.c
blob37c014854932e326ce88f65e2b1775a50c07ce0b
1 /* rabmch.c */
2
3 /*
4 * Copyright (C) 1989-2009 Alan R. Baldwin
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 *
19 *
20 * Alan R. Baldwin
21 * 721 Berkeley St.
22 * Kent, Ohio 44240
23 *
24 * ported to the Rabbit2000 by
25 * Ulrich Raich and Razaq Ijoduola
26 * PS Division
27 * CERN
28 * CH-1211 Geneva-23
29 * email: Ulrich dot Raich at cern dot ch
30 */
31
32 /*
33 * xerr messages Copyright (C) 1989-2021 Alan R. Baldwin
34 * from ASxxxx 5.40
35 */
36
37 /*
38 * Extensions: P. Felber
39 *
40 * Altered by Leland Morrison to support rabbit 2000
41 * and rabbit 4000 instruction sets (2011)
42 */
43
44 #include "asxxxx.h"
45 #include "rab.h"
46
47 char *cpu = "Rabbit 2000/4000";
48 char *dsft = "asm";
49
50 char imtab[3] = { 0x46, 0x56, 0x5E };
51
52 static const unsigned char ipset[4] = { 0x46, 0x56, 0x4E, 0x5E };
53
54
55 int r3k_mode;
56 int r4k_mode;
57 /* when set, generate op-code for Rabbit-4000 instead of Rabbit 2000/3000 */
58
59 int mchtyp;
60
61 /*
62 * Opcode Cycle Definitions
63 */
64 #define OPCY_SDP ((char) (0xFF))
65 #define OPCY_ERR ((char) (0xFE))
66
67 /* OPCY_NONE ((char) (0x80)) */
68 /* OPCY_MASK ((char) (0x7F)) */
69
70 #define OPCY_CPU ((char) (0xFD))
71
72 #define UN ((char) (OPCY_NONE | 0x00))
73 #define P2 ((char) (OPCY_NONE | 0x01))
74 #define P3 ((char) (OPCY_NONE | 0x02))
75 #define P4 ((char) (OPCY_NONE | 0x03))
76 #define P5 ((char) (OPCY_NONE | 0x04))
77 #define P6 ((char) (OPCY_NONE | 0x05))
78 #define P7 ((char) (OPCY_NONE | 0x06))
79
80 /*
81 * Process a machine op.
82 */
83 VOID machine(struct mne * mp)
84 {
85 int op, t1, t2;
86 struct expr e1, e2;
87 int rf, v1, v2;
88 struct expr *ep;
89
90 clrexpr(&e1);
91 clrexpr(&e2);
92 op = (int) mp->m_valu;
93 rf = mp->m_type;
94
95 if (!r4k_mode && rf > X_R4K_MODE)
96 rf = 0;
97
98 switch (rf) {
99 case S_CPU:
100 if (op == X_R2K)
101 r3k_mode=1;
102 if (op == X_R4K)
103 r4k_mode=1;
104 mchtyp = op;
105 sym[2].s_addr = op;
106 opcycles = OPCY_CPU;
107 lmode = SLIST;
108 break;
109
110 case S_INH1:
111 outab(op);
112 break;
113
114 case S_INH2:
115 outab(0xED);
116 outab(op);
117 break;
118
119 case S_RET:
120 if (more()) {
121 if ((v1 = admode(CND)) != 0) {
122 outab(op | (v1<<3));
123 } else {
124 xerr('a', "Condition code required.");
125 }
126 } else {
127 outab(0xC9);
128 }
129 break;
130
131 case S_PUSH:
132 if (admode(R16AF)) {
133 outab(op+0x30);
134 break;
135 } else if ((v1 = admode(R8IP)) != 0) {
136 outab(0xED);
137 if (op == 0xC5)
138 outab(0x76); /* push */
139 else
140 outab(0x7E); /* pop */
141 break;
142 } else
143 if ((v1 = admode(R16)) != 0 && (v1 &= 0xFF) != SP) {
144 if (v1 != gixiy(v1)) {
145 outab(op+0x20);
146 break;
147 }
148 outab(op | (v1<<4));
149 break;
150 } else if (r4k_mode) {
151 if ( (v1 = admode(R32_JKHL)) != 0 ) {
152 outab(JKHL_PG);
153 outab(op+0x30);
154 break;
155 } else if ( (v1 = admode(R32_BCDE)) != 0 ) {
156 outab(BCDE_PG);
157 outab(op+0x30);
158 break;
159 }
160 }
161 xerr('a', "Invalid Addressing Mode.");
162 break;
163
164 case S_RST:
165 v1 = (int) absexpr();
166 /* ljm comment -
167 * block RST 00, 08, and 30 b/c those opcodes
168 * are assigned to different instructions in the
169 * rabbit processor
170 */
171 if ((v1 == 0x00) || (v1 == 0x08) || (v1 == 0x30)) {
172 xerr('a', "Rabbit 2000/4000: 0x00, 0x08, and 0x30 are not allowed");
173 v1 = 0;
174 }
175 if (v1 & ~0x38) {
176 xerr('a', "Allowed values: N * 0x08, N = 0 -> 7.");
177 v1 = 0;
178 }
179 outab(op|v1);
180 break;
181
182 /* Rabbit processor use the opcode to set interrupt level */
183 case S_IM:
184 /* ipset 0-3 */
185 expr(&e1, 0);
186 abscheck(&e1);
187 if (e1.e_addr > 3) {
188 xerr('a', "Values of 0, 1, 2, and 3 are valid.");
189 e1.e_addr = 0;
190 }
191 outab(op);
192 outab(ipset[e1.e_addr]);
193 break;
194
195 case S_BIT:
196 expr(&e1, 0);
197 t1 = 0;
198 v1 = (int) e1.e_addr;
199 if (v1 > 7) {
200 v1 &= 0x07;
201 ++t1;
202 }
203 op |= (v1<<3);
204 comma(1);
205 addr(&e2);
206 abscheck(&e1);
207 if (genop(0xCB, op, &e2, 0) || t1)
208 xerr('a', "Invalid Addressing Mode.");
209 break;
210
211 case S_RL:
212 t1 = 0;
213 t2 = addr(&e2);
214 if ((t2 == S_IMMED) && r4k_mode)
215 {
216 v1 = (int) e2.e_addr;
217 /* v1 should be shift count of 1,2,4, or 8 */
218 comma(1);
219 clrexpr(&e2);
220 t2 = addr(&e2);
221
222 if ((t2 != S_R32_BCDE) && (t2 != S_R32_JKHL))
223 aerr( );
224
225 if (v1 == 1)
226 v1 = 0x48;
227 else if (v1 == 2)
228 v1 = 0x49;
229 else if (v1 == 4)
230 v1 = 0x4B;
231 else if ((v1 == 8) && (op < 0x20 /* op is rlc|rrc|rl|rr */))
232 v1 = 0x4F;
233 else {
234 err('o');
235 break;
236 }
237
238 /* 00 rlc, 08 rrc, 10 rl , 18 rr *
239 * 20 sla, 28 sra, 38 srl, [30 sll == sla] */
240 outab( ((t2 == S_R32_JKHL)?JKHL_PG:BCDE_PG) );
241 outab(v1 + (op << 1));
242 break;
243 }
244 else if (more()) {
245 if ((t2 != S_R8) || (e2.e_addr != A))
246 ++t1;
247 comma(1);
248 clrexpr(&e2);
249 t2 = addr(&e2);
250 } else if (t2 == S_R16) {
251 v2 = (int) e2.e_addr;
252 if ((v2 == DE) &&
253 ((op == 0x10 /* rl */) || (op == 0x18 /* rr */))) {
254 outab( 0xF3 - 0x10 + op );
255 break;
256 }
257
258 if ((v2 == HL) && (op == 0x18 /* rr */)) {
259 outab( 0xFC );
260 break;
261 }
262
263 if (r4k_mode) {
264 if ((v2 == HL) && (op == 0x10 /* rl */)) {
265 outab( 0x42 );
266 break;
267 }
268 if (((v2 == BC)||(v2 == DE)) &&
269 (op < 0x20 /* 00 rlc, 08 rrc, 10 rl, 18 rr */)) {
270 outab( 0x50 + (op >> 3) + ((v2==BC)?0x10:0x00) );
271 break;
272 }
273 }
274
275 aerr( );
276 }
277 if (genop(0xCB, op, &e2, 0) || t1)
278 aerr();
279 break;
280
281 case S_AND: /* and, xor, or, cp */
282 case S_SUB: /* sub */
283 case S_SBC: /* sbc */
284 t1 = addr(&e1);
285
286 if (!(more())) {
287 /* handle case for implicit target of 'A' register */
288 t2 = t1;
289 t1 = S_R8;
290 v1 = A;
291 v2 = (int) e1.e_addr;
292 ep = &e1;
293 } else {
294 comma(1);
295 t2 = addr(&e2);
296 v1 = (int) e1.e_addr;
297 v2 = (int) e2.e_addr;
298 ep = &e2;
299 }
300
301 if ((t1 == S_R8) && (v1 == A)) {
302 if ( ((t2 == S_R8) && (v2 == A)) &&
303 ((op == 0xA8) || (op == 0xB0)) ) {
304 /* AF: "xor a,a" || B7: "or a,a" */
305 outab( op | 0x07 );
306 break;
307 }
308
309 if ((t2 == S_R8) || (t2 == S_IDHL)) {
310 /* ljm - rabbit 4000 support
311 * (sub,sbc,and,xor,or,cp) A,R or A,(HL)
312 * needs a 0x7F prefix byte when
313 * operating in rabbit 4000 mode
314 */
315 if (r4k_mode)
316 outab(0x7F);
317 }
318
319 #if 0
320 if (t2 == S_IMMED) { /* AND,XOR,OR,CP,SUB A, #n */
321 /* opcode for (sub,sbc,and,xor,or,cp) A,#immediate
322 * do not need 0x7F prefix byte
323 */
324 outab(op|0x46); /* 0xA0 | 0x46 => 0xE6, etc */
325 outrb(ep, 0);
326 } else
327 #endif
328
329 if (genop(0, op, ep, 1))
330 aerr();
331 break;
332 }
333
334 if ((t1 == S_R16) && (v1 == HL) &&
335 (t2 == S_R16) && (rf == S_SBC)) {
336 /* sbc hl, [bc|de|hl|sp] */
337 if ( v2 != gixiy(v2) )
338 /* sorry, sbc hl, [ix|iy] do not exist */
339 xerr('a', "Second argument: must be BC, DE, HL or SP.");
340
341 outab(0xED);
342 outab(0x42 | v2 << 4);
343 break;
344 }
345 if ((t1 == S_R16) && (v1 == HL) &&
346 (t2 == S_R16) && (v2 == DE)) {
347 /* 55 sub hl, de */
348 /* sbc hl, de does not exist */
349 /* DC and hl, de */
350 /* 54 xor hl, de */
351 /* EC or hl, de */
352 /* ED 48 cp hl, de */
353 if (rf == S_SBC) /* op == 0x98 */
354 xerr('a', "Not valid for SBC.");
355
356 switch( op ) {
357 case 0x90: /* sub */ outab(0x55); break;
358 case 0xA0: /* and */ outab(0xDC); break;
359 case 0xA8: /* xor */ outab(0x54); break;
360 case 0xB0: /* or */ outab(0xEC); break;
361 case 0xB8: /* cp */
362 outab( 0xED );
363 outab( 0x48 );
364 break;
365 }
366 break;
367 }
368
369 if ((t1 == S_R16) && ((v1 == IX) || (v1 == IY)) &&
370 (t2 == S_R16) && (v2 == DE) &&
371 ((op == 0xA0 /* and */) || (op == 0xB0 /* or */))) {
372 v1 = gixiy(v1);
373 outab(op + 0x3C);
374 break;
375 }
376
377 if ((t1 == S_R32_JKHL) && (t2 == S_R32_BCDE)) {
378 /* ED D6 sub jkhl, bcde */
379 /* sbc jkhl, bcde does not exist */
380 /* ED E6 and jkhl, bcde */
381 /* ED EE xor jkhl, bcde */
382 /* ED F6 or jkhl, bcde */
383 /* ED 58 cp jkhl, bcde */
384 if (rf == S_SBC) /* op == 0x98 */
385 xerr('a', "Not valid for SBC.");
386
387 outab(0xED);
388 switch( op ) {
389 case 0x90: /* sub */ outab(0xD6); break;
390 case 0xA0: /* and */ outab(0xE6); break;
391 case 0xA8: /* xor */ outab(0xEE); break;
392 case 0xB0: /* or */ outab(0xF6); break;
393 case 0xB8: /* cp */ outab(0x58); break;
394 }
395 break;
396 }
397
398 if ((t1 == S_R16) && (v1 == HL) && (t2 == S_IMMED)) {
399 /* cp hl, #signed displacement */
400 outab(0x48);
401 outrb(&e2, 0);
402 break;
403 }
404
405 xerr('a', "Not valid for SBC.");
406 break;
407
408 case S_ADD:
409 case S_ADC:
410 t1 = addr(&e1);
411 t2 = 0;
412 if (more()) {
413 comma(1);
414 t2 = addr(&e2);
415 }
416 if (t2 == 0) {
417 /* implied destination of the 8-bit 'a' register */
418 if ((t1 == S_R8) || (t1 == S_IDHL)) {
419 /* ljm - rabbit 4000 support
420 * (add,adc,sub,sbc,and,xor,or,cp) A,R or A,(HL)
421 * needs a 0x7F prefix byte when
422 * operating in rabbit 4000 mode
423 */
424 if (r4k_mode)
425 outab(0x7F);
426 }
427
428 if (genop(0, op, &e1, 1))
429 xerr('a', "Invalid Addressing Mode.");
430 break;
431 }
432 if ((t1 == S_R8) && (e1.e_addr == A)) {
433 if ( ((t2 == S_R8) || (t2 == S_IDHL)) && r4k_mode )
434 /* ljm - rabbit 4000 support, see note in t2==0 */
435 outab(0x7F);
436
437 if (genop(0, op, &e2, 1))
438 xerr('a', "Second argument: Invalid Addressing Mode.");
439 break;
440 }
441
442 if ((t1 == S_R32_JKHL) && (t2 == S_R32_BCDE) &&
443 (rf == S_ADD)) {
444 /* rabbit 4000 - ED C6 "add jkhl, bcde" */
445 outab(0xED);
446 outab(0xC6);
447 break;
448 }
449
450 v1 = (int) e1.e_addr;
451 v2 = (int) e2.e_addr;
452
453 if ((t1 == S_R16) && (v1 == SP) && (t2 == S_IMMED)) {
454 /* rabbit 4000 - add sp,#n n=signed displacement */
455 outab(0x27);
456 outrb(&e2, 0);
457 break;
458 }
459
460 if ((t1 == S_R16) && (v1 == HL) && (t2 == S_R16)) {
461 if (v2 > SP)
462 aerr( );
463
464 if (rf == S_ADC)
465 outab(0xED);
466
467 op = (rf == S_ADD) ? 0x09 : 0x4A;
468 outab(op | (v2 << 4) );
469 break;
470 }
471
472 if ((t1 == S_R16) && ((v1 == IX) || (v1 == IY)) &&
473 (t2 == S_R16))
474 {
475 if ((v2 == HL) ||
476 (((v2 == IX) || (v2 == IY)) && (v2 != v1)))
477 aerr( );
478
479 if ((v2 == IX) || (v2 == IY))
480 v2 = HL;
481
482 gixiy(v1);
483 outab(0x09 | (v2 << 4));
484 break;
485 }
486 xerr('a', "Invalid Addressing Mode.");
487 break;
488
489 case S_LD:
490 t1 = addr(&e1);
491 v1 = (int) e1.e_addr;
492 comma(1);
493 t2 = addr(&e2);
494 v2 = (int) e2.e_addr;
495 if (t1 == S_R8)
496 {
497 if (t2 == S_IMMED) {
498 outab((e1.e_addr<<3) | 0x06);
499 outrb(&e2, 0);
500 break;
501 }
502
503 if (r4k_mode && (v1 == A) && (t2 == S_R8) && (v2 == A)) {
504 /* exception for "ld a,a"
505 * on rabbit 4000 0x7F is a prefix instead of "ld a,a"
506 */
507 xerr('a', "Not A Rabbit 4000 Instruction");
508 }
509
510 if ((v1 == A) && (t2 == S_R8)) {
511 /* "ld a,r", (except "ld a,a") */
512 v1 = op | e1.e_addr<<3;
513 if (genop(0, v1, &e2, 0))
514 aerr( );
515 break;
516 }
517
518 /* ld [b,c,d,e,h,l,a], _ */
519 if ((t2 == S_R8) && (v2 != A)) {
520 /* 8-bit register to 8-bit register */
521 /* use 0x7F prefix when in rabbit 4000 mode */
522 v1 = op | e1.e_addr<<3;
523 if (r4k_mode)
524 outab(0x7F);
525 if (genop(0, v1, &e2, 0) == 0)
526 break;
527
528 aerr( );
529 }
530
531 if ((t2 == S_R8) && (v2 == A) &&
532 ((v1 != A) || (!r4k_mode))) {
533 /* "ld r,a", but except "ld a,a"
534 * on rabbit 4000 0x7F is a prefix instead of "ld a,a" */
535 v1 = op | e1.e_addr<<3;
536 if (genop(0, v1, &e2, 0))
537 aerr( );
538 break;
539 }
540
541 if ((t2 == S_IDHL) || (t2 == S_IDIX) || (t2 == S_IDIY)) {
542 /* "ld r,(hl)" or "ld r,disp (ix|iy)" */
543 v1 = op | e1.e_addr<<3;
544 if (genop(0, v1, &e2, 0))
545 aerr( );
546 break;
547 }
548 }
549
550 if ((t1 == S_R16) && (t2 == S_IMMED)) {
551 v1 = gixiy(v1); /* generayes prefix when ix or iy */
552 outab(0x01|(v1<<4));
553 outrw(&e2, 0);
554 break;
555 }
556 if ((t1 == S_R16) && (t2 == S_INDM)) {
557 if (gixiy(v1) == HL) {
558 outab(0x2A);
559 } else {
560 outab(0xED);
561 outab(0x4B | (v1<<4));
562 }
563 outrw(&e2, 0);
564 break;
565 }
566 if ((t1 == S_R16) && (v1 == HL))
567 {
568 if ((t2 == S_IDIX) || (t2 == S_IDIY) ||
569 (t2 == S_IDHL) || (t2 == S_IDHL_OFFSET))
570 {
571 /* ljm - added rabbit instruction LD HL,n(IX|HL|IY) */
572 if (t2 == S_IDIY)
573 outab(0xFD);
574 else if ((t2 == S_IDHL) || (t2 == S_IDHL_OFFSET))
575 /* ljm - added rabbit instruction LD HL,n(IY)
576 * normally 0xFD generated by "gixiy(v1)", but
577 * 0xDD results in n(HL) instead of n(IX)
578 */
579 outab(0xDD);
580
581 outab(0xE4);
582 outrb(&e2, 0);
583 break;
584 }
585 if ((t2 == S_R16) && ((v2 == IX) || (v2 == IY))) {
586 outab( ((v2==IX)?0xDD:0xFD) );
587 outab(0x7C);
588 break;
589 }
590 if (r4k_mode) {
591 if ((t2 == S_R16) && ((v2 == BC) || (v2 == DE))) {
592 outab( 0x81 + ((v2 == DE) ? 0x20 : 0) );
593 break;
594 }
595 }
596 }
597 if ((t2 == S_R16) && (v2 == HL)) /* ld n(IX|IY|HL), HL */
598 {
599 if ((t1 == S_IDIY) || (t1 == S_IDHL) ||
600 (t1 == S_IDHL_OFFSET))
601 outab( ((t1==S_IDIY) ? 0xFD : 0xDD) );
602
603 if ((t1 == S_IDIY) || (t1 == S_IDIX) ||
604 (t1 == S_IDHL) || (t1 == S_IDHL_OFFSET)) {
605 outab(0xF4);
606 outrb(&e1, 0);
607 break;
608 }
609
610 if ((t1 == S_R16) && ((v1 == IX) || (v1 == IY))) {
611 outab( ((v1==IX)?0xDD:0xFD) );
612 outab(0x7D);
613 break;
614 }
615 }
616 if ((t1 == S_INDM) && (t2 == S_R16)) {
617 if (gixiy(v2) == HL) {
618 outab(0x22);
619 } else {
620 outab(0xED);
621 outab(0x43 | (v2<<4));
622 }
623 outrw(&e1, 0);
624 break;
625 }
626 if ((t1 == S_R8) && (v1 == A) && (t2 == S_INDM)) {
627 outab(0x3A);
628 outrw(&e2, 0);
629 break;
630 }
631 if ((t1 == S_INDM) && (t2 == S_R8) && (v2 == A)) {
632 outab(0x32);
633 outrw(&e1, 0);
634 break;
635 }
636 if ((t2 == S_R8) && (gixiy(t1) == S_IDHL)) {
637 outab(0x70|v2);
638 if (t1 != S_IDHL)
639 outrb(&e1, 0);
640 break;
641 }
642 if ((t2 == S_IMMED) && (gixiy(t1) == S_IDHL)) {
643 outab(0x36);
644 if (t1 != S_IDHL)
645 outrb(&e1, 0);
646 outrb(&e2, 0);
647 break;
648 }
649 if ((t1 == S_R8X) && (t2 == S_R8) && (v2 == A)) {
650 outab(0xED);
651 outab(v1);
652 break;
653 }
654 if ((t1 == S_R8) && (v1 == A) && (t2 == S_R8X)) {
655 outab(0xED);
656 outab(v2|0x10);
657 break;
658 }
659 if ((t1 == S_R16) && (v1 == SP)) {
660 if ((t2 == S_R16) && (gixiy(v2) == HL)) {
661 outab(0xF9);
662 break;
663 }
664 }
665 if ((t1 == S_R16) && (t2 == S_IDSP))
666 {
667 if ( (v1=gixiy(v1)) == HL ) {
668 /* ljm - added rabbit instruction:
669 * LD HL|IX|IY, n(SP)
670 */
671 outab(0xC4);
672 outrb(&e2, 0);
673 break;
674 }
675 }
676
677 if ((t1 == S_IDSP) && (t2 == S_R16))
678 {
679 //printf( "at %s: %d, t1=%d, v1=%d, t2=%d, v2=%d\n",
680 // __FILE__, __LINE__, t1, v1, t2, v2 );
681 if ( (v2=gixiy(v2)) == HL ) {
682 /* ljm - added rabbit instruction:
683 * LD HL|IX|IY, n(SP)
684 */
685 outab(0xD4);
686 outrb(&e1, 0);
687 break;
688 }
689 }
690 if ((t1 == S_R8) && (v1 == A)) {
691 if ((t2 == S_IDBC) || (t2 == S_IDDE)) {
692 outab(0x0A | ((t2-S_INDR)<<4));
693 break;
694 }
695 }
696 if ((t2 == S_R8) && (v2 == A)) {
697 if ((t1 == S_IDBC) || (t1 == S_IDDE)) {
698 outab(0x02 | ((t1-S_INDR)<<4));
699 break;
700 }
701 }
702
703 /* load/save code bank register "xpc" */
704 if ((t1 == S_RXPC) && (t2 == S_R8) && (v2 == A)) {
705 outab(0xED);
706 outab(0x67);
707 break;
708 }
709
710 if ((t1 == S_RXPC) && r4k_mode &&
711 (t2 == S_R16) && (v2 == HL)) {
712 outab(0x97);
713 break;
714 }
715
716 if ((t2 == S_RXPC) && (t1 == S_R8) && (v1 == A)) {
717 outab(0xED);
718 outab(0x77);
719 break;
720 }
721
722 if ((t2 == S_RXPC) && r4k_mode &&
723 (t1 == S_R16) && (v1 == HL)) {
724 outab(0x9F);
725 break;
726 }
727
728 if ((t1 == S_R16_ALT) && (t2 == S_R16)) {
729 if ((v2 == BC) || (v2 == DE)) {
730 /* LD BC'|DE'|HL', BC|DE */
731 outab(0xED);
732 outab(((v2 == BC) ? 0x49 : 0x41) | (v1 << 4));
733 break;
734 }
735 }
736
737 /* 16-bit operations valid only in rabbit 4000 mode */
738 if (r4k_mode && (t1 == S_R16) && (t2 == S_R16)) {
739 if ((v1 == HL) && ((v2 == BC) || (v2 == DE))) {
740 outab( 0x81 + ((v2==DE)?0x20:0x00) );
741 break;
742 }
743 if ((v2 == HL) && ((v1 == BC) || (v1 == DE))) {
744 outab( 0x91 + ((v1==DE)?0x20:0x00) );
745 break;
746 }
747 }
748
749 /* 32-bit operations valid in rabbit 4000 mode */
750 if (r4k_mode && ((t1 == S_R32_JKHL) || (t1 == S_R32_BCDE))) {
751 if (t2 == S_IDHL) {
752 outab( ((t1 == S_R32_JKHL)?JKHL_PG:BCDE_PG) );
753 outab( 0x1A );
754 break;
755 }
756 if ((t2 == S_IDIX) || (t2 == S_IDIY) || (t2 == S_IDSP)) {
757 outab( ((t1 == S_R32_JKHL)?JKHL_PG:BCDE_PG) );
758 if (t2 == S_IDSP)
759 v2 = 0x20;
760 else
761 v2 = ((t2 == S_IDIY) ? 0x10 : 0x00);
762
763 outab( 0xCE + v2 );
764 outrb(&e2, 0);
765 break;
766 }
767 if (t2 == S_INDM) {
768 outab( 0x93 + ((t1 == S_R32_JKHL) ? 1 : 0) );
769 outrw(&e2, 0);
770 break;
771 }
772 if (t2 == S_IMMED) {
773 outab( 0xA3 + ((t1 == S_R32_JKHL) ? 1 : 0) );
774 outrb(&e2, 0);
775 break;
776 }
777 }
778
779 if (r4k_mode && ((t2 == S_R32_JKHL) || (t2 == S_R32_BCDE))) {
780 if (t1 == S_IDHL) {
781 outab( ((t2 == S_R32_JKHL)?JKHL_PG:BCDE_PG) );
782 outab( 0x1B );
783 break;
784 }
785 if ((t1 == S_IDIX) || (t1 == S_IDIY) || (t1 == S_IDSP)) {
786 outab( ((t2 == S_R32_JKHL)?JKHL_PG:BCDE_PG) );
787 if (t1 == S_IDSP)
788 v1 = 0x20;
789 else
790 v1 = ((t1 == S_IDIY) ? 0x10 : 0x00);
791
792 outab( 0xCF + v1 );
793 outrb(&e1, 0);
794 break;
795 }
796 if (t1 == S_INDM) {
797 outab( 0x83 + ((t2 == S_R32_JKHL) ? 1 : 0) );
798 outrw(&e1, 0);
799 break;
800 }
801 }
802 xerr('a', "Invalid Addressing Mode.");
803 break;
804
805 case S_EX:
806 t1 = addr(&e1);
807 comma(1);
808 t2 = addr(&e2);
809 if (t2 == S_R16) {
810 v1 = (int) e1.e_addr;
811 v2 = (int) e2.e_addr;
812 if (t1 == S_R16) {
813 if ((v1 == DE) && (v2 == HL)) {
814 outab(0xEB);
815 break;
816 }
817 if (r4k_mode && (v1==BC) && (v2==HL)) {
818 outab(0xB3);
819 break;
820 }
821 }
822 else if (t1 == S_R16_ALT) {
823 if ((v1 == DE) && (v2 == HL)) {
824 /* EX DE', HL */
825 outab(0xE3);
826 break;
827 }
828 if (r4k_mode && (v1==BC) && (v2==HL)) {
829 /* EX BC', HL */
830 outab(0xED);
831 outab(0x74);
832 break;
833 }
834 }
835
836 if ((t1 == S_IDSP) && (v1 == 0)) {
837 /* 0xE3 is EX DE',HL on rabbit 2000
838 * but DD/FD E3 "ex (sp),ix|iy" is valid
839 */
840 if (v2 == HL) {
841 outab(0xED);
842 outab(0x54);
843 break;
844 }
845 else if (gixiy(v2) == HL) {
846 outab(op);
847 break;
848 }
849 }
850 }
851 if ((t1 == S_R16AF) && (t2 == S_R16AF_ALT)) {
852 outab(0x08);
853 break;
854 }
855 if ((t1==S_R32_JKHL) && (t2==S_R32_BCDE)) {
856 outab(0xB4);
857 break;
858 }
859 xerr('a', "Invalid Addressing Mode.");
860 break;
861
862 case S_IN:
863 case S_OUT:
864 outab(op);
865 break;
866
867 case S_DEC:
868 case S_INC:
869 t1 = addr(&e1);
870 v1 = (int) e1.e_addr;
871 if (t1 == S_R8) {
872 outab(op|(v1<<3));
873 break;
874 }
875 if (t1 == S_IDHL) {
876 outab(op|0x30);
877 break;
878 }
879 if (t1 != gixiy(t1)) {
880 outab(op|0x30);
881 outrb(&e1, 0);
882 break;
883 }
884 if (t1 == S_R16) {
885 v1 = gixiy(v1);
886 if (rf == S_INC) {
887 outab(0x03|(v1<<4));
888 break;
889 }
890 if (rf == S_DEC) {
891 outab(0x0B|(v1<<4));
892 break;
893 }
894 }
895 xerr('a', "Invalid Addressing Mode.");
896 break;
897
898 case S_NEG:
899 if (!more()) {
900 /* "neg" implies "neg a" */
901 outab(0xED);
902 outab(op);
903 break;
904 }
905 t1 = addr(&e1);
906 v1 = (int) e1.e_addr;
907 if ((t1 == S_R8) && (v1 == A)) { /* "neg a" */
908 outab(0xED);
909 outab(op);
910 break;
911 }
912
913 if ((t1 == S_R16) && (v1 == HL) && r4k_mode) { /* "neg hl" */
914 outab(0x4D);
915 break;
916 }
917
918 if (r4k_mode &&
919 ((t1 == S_R32_JKHL) || (t1 == S_R32_BCDE))) {
920 /* neg jkhl|bcde */
921 outab( ( (t1 == S_R32_BCDE) ? 0xDD : 0xFD ) );
922 outab(0x4D);
923 break;
924 }
925 break;
926
927 case S_DJNZ:
928 case S_JR:
929 if ((v1 = admode(CND)) != 0 && rf != S_DJNZ) {
930 if ((v1 &= 0xFF) <= 0x03) {
931 op += (v1+1)<<3;
932 } else {
933 xerr('a', "Condition code required.");
934 }
935 comma(1);
936 }
937 expr(&e2, 0);
938 outab(op);
939 if (mchpcr(&e2)) {
940 v2 = (int) (e2.e_addr - dot.s_addr - 1);
941 if (pass == 2 && ((v2 < -128) || (v2 > 127)))
942 xerr('a', "Branching Range Exceeded.");
943 outab(v2);
944 } else {
945 outrb(&e2, R_PCR);
946 }
947 if (e2.e_mode != S_USER)
948 rerr();
949 break;
950
951 case S_CALL:
952 op = 0xCD;
953 expr(&e1, 0);
954 outab(op);
955 outrw(&e1, 0);
956 break;
957
958 case S_JP:
959 if ((v1 = admode(CND)) != 0) {
960 op |= (v1&0xFF)<<3;
961 comma(1);
962 expr(&e1, 0);
963 outab(op);
964 outrw(&e1, 0);
965 break;
966 }
967 t1 = addr(&e1);
968 if (t1 == S_USER) {
969 outab(0xC3);
970 outrw(&e1, 0);
971 break;
972 }
973 if ((e1.e_addr == 0) && (gixiy(t1) == S_IDHL)) {
974 outab(0xE9);
975 break;
976 }
977 xerr('a', "Invalid Addressing Mode.");
978 break;
979 /*
980 case X_HD64:
981 ++hd64;
982 break;
983 */
984 case HD_INH2:
985 if (mchtyp != X_HD64)
986 xerr('a', "A Z180 Instruction.");
987 outab(0xED);
988 outab(op);
989 break;
990
991 case HD_IN:
992 case HD_OUT:
993 if (mchtyp != X_HD64)
994 xerr('a', "A Z180 Instruction.");
995 if (rf == HD_IN) {
996 t1 = addr(&e1);
997 comma(1);
998 t2 = addr(&e2);
999 } else {
1000 t2 = addr(&e2);
1001 comma(1);
1002 t1 = addr(&e1);
1003 }
1004 if ((t1 == S_R8) && (t2 == S_INDM)) {
1005 outab(0xED);
1006 outab(op | (e1.e_addr<<3));
1007 outrb(&e2, 0);
1008 break;
1009 }
1010 xerr('a', "Invalid Addressing Mode.");
1011 break;
1012
1013 case HD_MLT:
1014 if (mchtyp != X_HD64)
1015 xerr('a', "A Z180 Instruction.");
1016 t1 = addr(&e1);
1017 if ((t1 == S_R16) && ((v1 = (int) e1.e_addr) <= SP)) {
1018 outab(0xED);
1019 outab(op | (v1<<4));
1020 break;
1021 }
1022 xerr('a', "Only BC, DE, HL and SP are allowed.");
1023 break;
1024
1025 case HD_TST:
1026 if (mchtyp != X_HD64)
1027 xerr('a', "A Z180 Instruction.");
1028 t1 = addr(&e1);
1029 if (t1 == S_R8) {
1030 outab(0xED);
1031 outab(op | (e1.e_addr<<3));
1032 break;
1033 }
1034 if (t1 == S_IDHL) {
1035 outab(0xED);
1036 outab(0x34);
1037 break;
1038 }
1039 if (t1 == S_IMMED) {
1040 outab(0xED);
1041 outab(0x64);
1042 outrb(&e1, 0);
1043 break;
1044 }
1045 xerr('a', "Invalid Addressing Mode.");
1046 break;
1047
1048 case HD_TSTIO:
1049 if (mchtyp != X_HD64)
1050 xerr('a', "A Z180 Instruction.");
1051 t1 = addr(&e1);
1052 if (t1 == S_IMMED) {
1053 outab(0xED);
1054 outab(op);
1055 outrb(&e1, 0);
1056 break;
1057 }
1058 xerr('a', "Invalid Addressing Mode.");
1059 break;
1060
1061 case X_LJP:
1062 case X_LCALL:
1063 /* bank jump or call for rabbit processor */
1064 t1 = addr(&e1);
1065 comma(1);
1066 t2 = addr(&e2);
1067 v1 = (int) e1.e_addr;
1068 if ((t1 == S_USER) && (t2 == S_IMMED)) {
1069 outab(op);
1070 outrw(&e1, 0);
1071 outrb(&e2, 0);
1072 break;
1073 }
1074 break;
1075
1076 case X_BOOL:
1077 t1 = addr(&e1);
1078 v1 = (int) e1.e_addr;
1079 if ((t1 == S_R16) && ((v1 == HL) || (v1 == IX) || (v1 == IY))) {
1080 v1 = gixiy(v1);
1081 outab(op);
1082 break;
1083 }
1084 xerr('a', "Invalid Addressing Mode.");
1085 break;
1086
1087 case X_LDP:
1088 t1 = addr(&e1);
1089 v1 = (int) e1.e_addr;
1090 comma(1);
1091 t2 = addr(&e2);
1092 v2 = (int) e2.e_addr;
1093 /* LDP (mn), HL|IX|IY */
1094 if ((t1 == S_INDM) && (t2 == S_R16)) {
1095 if ((v2 != HL) && (v2 != IX) && (v2 != IY)) {
1096 xerr('a', "Second argument: must be HL, IX, or IY.");
1097 break;
1098 }
1099 if (v2 == HL) {
1100 outab(0xED);
1101 } else {
1102 gixiy(v2);
1103 }
1104 outab(op | 0x01);
1105 outrw(&e1, 0);
1106 break;
1107 }
1108 /* LDP HL|IX|IY, (mn) */
1109 if ((t1 == S_R16) && (t2 == S_INDM)) {
1110 if ((v1 != HL) && (v1 != IX) && (v1 != IY)) {
1111 xerr('a', "First argument: must be HL, IX, or IY.");
1112 break;
1113 }
1114 if (v1 == HL) {
1115 outab(0xED);
1116 } else {
1117 gixiy(v1);
1118 }
1119 outab(op | 0x09);
1120 outrw(&e2, 0);
1121 break;
1122 }
1123 /* LDP (HL|IX|IY), HL */
1124 if ((t2 == S_R16) && (v2 == HL)) {
1125 if ((t1 != S_IDHL) && (t1 != S_IDIX) && (t1 != S_IDIY)) {
1126 xerr('a', "First argument: must be (HL), (IX), or (IY).");
1127 break;
1128 }
1129 if ((e1.e_base.e_ap != NULL) || (v1 != 0)) {
1130 xerr('a', "First argument: (HL+D, (IX+D), and (IY+D) are invalid.");
1131 break;
1132 }
1133 if (t1 == S_IDHL) {
1134 outab(0xED);
1135 } else {
1136 gixiy(t1);
1137 }
1138 outab(op);
1139 break;
1140 }
1141 /* LDP HL, (HL|IX|IY) */
1142 if ((t1 == S_R16) && (v1 == HL)) {
1143 if ((t2 != S_IDHL) && (t2 != S_IDIX) && (t2 != S_IDIY)) {
1144 xerr('a', "Second argument: must be (HL), (IX), or (IY).");
1145 break;
1146 }
1147 if ((e2.e_base.e_ap != NULL) || (v2 != 0)) {
1148 xerr('a', "Second argument: (HL+D, (IX+D), and (IY+D) are invalid.");
1149 break;
1150 }
1151 if (t2 == S_IDHL) {
1152 outab(0xED);
1153 } else {
1154 gixiy(t2);
1155 }
1156 outab(op | 0x08);
1157 break;
1158 }
1159 xerr('a', "Invalid Addressing Mode.");
1160 break;
1161
1162 case R3K_INH1:
1163 if (!(r3k_mode || r4k_mode))
1164 xerr('o', "A Rabbit 3000/4000 Instruction.");
1165
1166 outab(op);
1167 break;
1168
1169 case R3K_INH2:
1170 if (!(r3k_mode || r4k_mode))
1171 xerr('o', "A Rabbit 3000/4000 Instruction.");
1172
1173 outab(0xED);
1174 outab(op);
1175 break;
1176
1177 case R4K_INH2:
1178 if (!r4k_mode)
1179 xerr('o', "A Rabbit 4000 Instruction.");
1180
1181 outab(0xED);
1182 outab(op);
1183 break;
1184
1185 case X_R4K_MULU:
1186 if (!r4k_mode)
1187 xerr('o', "A Rabbit 4000 Instruction.");
1188
1189 outab(op);
1190 break;
1191
1192 case X_JRE:
1193 if (!r4k_mode)
1194 xerr('o', "A Rabbit 4000 Instruction.");
1195
1196 if ((v1 = admode(ALT_CND)) != 0) {
1197 op += v1<<3;
1198 comma(1);
1199 } else {
1200 op = 0x98;
1201 }
1202 expr(&e2, 0);
1203 outab(op);
1204 if (mchpcr(&e2)) {
1205 v2 = (int) (e2.e_addr - dot.s_addr - 1);
1206 if (pass == 2 && ((v2 < -32768) || (v2 > 32767)))
1207 aerr();
1208 outab( (v2 & 0xFF) );
1209 outab( (v2 >> 8) );
1210 } else {
1211 outrb(&e2, R_PCR);
1212 }
1213 if (e2.e_mode != S_USER)
1214 rerr();
1215 break;
1216
1217 case X_CLR:
1218 if (!r4k_mode)
1219 xerr('o', "A Rabbit 4000 Instruction.");
1220 t1 = addr(&e1);
1221 v1 = (int) e1.e_addr;
1222 if ((t1 == S_R16) && (v1 == HL)) {
1223 outab(op);
1224 break;
1225 }
1226 aerr( );
1227 break;
1228
1229 default:
1230 xerr('o', "Internal Opcode Error.");
1231 break;
1232 }
1233 }
1234
1235 /*
1236 * general addressing evaluation
1237 * return(0) if general addressing mode output, else
1238 * return(esp->e_mode)
1239 */
1240 int
1241 genop(int pop, int op, struct expr *esp, int f)
1242 {
1243 int t1;
1244 /*
1245 * r
1246 */
1247 if ((t1 = esp->e_mode) == S_R8) {
1248 if (pop)
1249 outab(pop);
1250 outab(op|esp->e_addr);
1251 return(0);
1252 }
1253 /*
1254 * (hl)
1255 */
1256 if (t1 == S_IDHL) {
1257 if ((esp->e_base.e_ap != NULL) || (esp->e_addr != 0))
1258 xerr('a', "(HL+D) is invalid.");
1259 if (pop)
1260 outab(pop);
1261 outab(op|0x06);
1262 return(0);
1263 }
1264 /*
1265 * (ix) / (ix+d)
1266 * (iy) / (iy+d)
1267 */
1268 if (gixiy(t1) == S_IDHL) {
1269 if (pop) {
1270 outab(pop);
1271 outrb(esp, 0);
1272 outab(op|0x06);
1273 } else {
1274 outab(op|0x06);
1275 outrb(esp, 0);
1276 }
1277 return(0);
1278 }
1279 /*
1280 * n
1281 * #n
1282 */
1283 if ((t1 == S_IMMED) && (f)) {
1284 if (pop)
1285 outab(pop);
1286 outab(op|0x46);
1287 outrb(esp,0);
1288 return(0);
1289 }
1290 return(t1);
1291 }
1292
1293 /*
1294 * IX and IY prebyte check
1295 */
1296 int
1297 gixiy(int v)
1298 {
1299 if (v == IX) {
1300 v = HL;
1301 outab(0xDD);
1302 } else if (v == IY) {
1303 v = HL;
1304 outab(0xFD);
1305 } else if (v == S_IDIX) {
1306 v = S_IDHL;
1307 outab(0xDD);
1308 } else if (v == S_IDIY) {
1309 v = S_IDHL;
1310 outab(0xFD);
1311 }
1312 return(v);
1313 }
1314
1315 /*
1316 * Branch/Jump PCR Mode Check
1317 */
1318 int
1319 mchpcr(struct expr *esp)
1320 {
1321 if (esp->e_base.e_ap == dot.s_area) {
1322 return(1);
1323 }
1324 if (esp->e_flag==0 && esp->e_base.e_ap==NULL) {
1325 /*
1326 * Absolute Destination
1327 *
1328 * Use the global symbol '.__.ABS.'
1329 * of value zero and force the assembler
1330 * to use this absolute constant as the
1331 * base value for the relocation.
1332 */
1333 esp->e_flag = 1;
1334 esp->e_base.e_sp = &sym[1];
1335 }
1336 return(0);
1337 }
1338
1339 /*
1340 * Machine dependent initialization
1341 */
1342 VOID
1343 minit(void)
1344 {
1345 /*
1346 * Byte Order
1347 */
1348 hilo = 0;
1349
1350 /*
1351 * Address Space
1352 */
1353 exprmasks(3);
1354
1355 if (pass == 0) {
1356 mchtyp = X_R2K;
1357 sym[2].s_addr = X_R2K;
1358 }
1359 }
SDCC git mirror