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struct / union in initializer, RFE #901.
[sdcc.git] / sdcc / sdas / asz80 / z80mch.c
blob5ff06a49cc837a08f497f40902e80e749d811f94
1 /* z80mch.c */
2
3 /*
4 * Copyright (C) 1993-2006 Alan R. Baldwin
5 *
6 * This program is free software: you can redistribute it and/or modify
7 * it under the terms of the GNU General Public License as published by
8 * the Free Software Foundation, either version 3 of the License, or
9 * (at your option) any later version.
10 *
11 * This program is distributed in the hope that it will be useful,
12 * but WITHOUT ANY WARRANTY; without even the implied warranty of
13 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
14 * GNU General Public License for more details.
15 *
16 * You should have received a copy of the GNU General Public License
17 * along with this program. If not, see <http://www.gnu.org/licenses/>.
18 *
19 *
20 * Alan R. Baldwin
21 * 721 Berkeley St.
22 * Kent, Ohio 44240
23 */
24
25 /*
26 * Extensions: P. Felber
27 * eZ80 port (based on ASxxxx sources): H. Sladky
28 */
29
30 #include "asxxxx.h"
31 #include "z80.h"
32
33 char *cpu = "Zilog Z80 / Hitachi HD64180 / ZX-Next / eZ80 / R800";
34 char *dsft = "asm";
35
36 char imtab[3] = { 0x46, 0x56, 0x5E };
37 int mchtyp;
38 int allow_undoc;
39
40 static int ez80_adl = 0;
41
42 /*
43 * Opcode Cycle Definitions
44 */
45 #define OPCY_SDP ((char) (0xFF))
46 #define OPCY_ERR ((char) (0xFE))
47
48 /* OPCY_NONE ((char) (0x80)) */
49 /* OPCY_MASK ((char) (0x7F)) */
50
51 #define OPCY_CPU ((char) (0xFD))
52
53 #define UN ((char) (OPCY_NONE | 0x00))
54 #define P2 ((char) (OPCY_NONE | 0x01))
55 #define P3 ((char) (OPCY_NONE | 0x02))
56 #define P4 ((char) (OPCY_NONE | 0x03))
57 #define P5 ((char) (OPCY_NONE | 0x04))
58 #define P6 ((char) (OPCY_NONE | 0x05))
59 #define P7 ((char) (OPCY_NONE | 0x06))
60
61 #define PF ((char) (OPCY_NONE | 0x10))
62
63 /*
64 * Z80 Opcode Cycle Pages
65 */
66
67 static const char z80pg1[256] = {
68 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
69 /*--*--* - - - - - - - - - - - - - - - - */
70 /*00*/ 4,10, 7, 6, 4, 4, 7, 4, 4,11, 7, 6, 4, 4, 7, 4,
71 /*10*/ 13,10, 7, 6, 4, 4, 7, 4,12,11, 7, 6, 4, 4, 7, 4,
72 /*20*/ 12,10,16, 6, 4, 4, 7, 4,12,11,16, 6, 4, 4, 7, 4,
73 /*30*/ 12,10,13, 6,11,11,10, 4,12,11,13, 6, 4, 4, 7, 4,
74 /*40*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
75 /*50*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
76 /*60*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
77 /*70*/ 7, 7, 7, 7, 7, 7, 4, 7, 4, 4, 4, 4, 4, 4, 7, 4,
78 /*80*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
79 /*90*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
80 /*A0*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
81 /*B0*/ 4, 4, 4, 4, 4, 4, 7, 4, 4, 4, 4, 4, 4, 4, 7, 4,
82 /*C0*/ 11,10,10,10,17,11, 7,11,11,10,10,P2,17,17, 7,11,
83 /*D0*/ 11,10,10,11,17,11, 7,11,11, 4,10,11,17,P3, 7,11,
84 /*E0*/ 11,10,10,19,17,11, 7,11,11, 4,10, 4,17,P4, 7,11,
85 /*F0*/ 11,10,10, 4,17,11, 7,11,11, 6,10, 4,17,P5, 7,11
86 };
87
88 static const char z80pg2[256] = { /* P2 == CB */
89 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
90 /*--*--* - - - - - - - - - - - - - - - - */
91 /*00*/ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
92 /*10*/ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
93 /*20*/ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
94 /*30*/ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
95 /*40*/ 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
96 /*50*/ 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
97 /*60*/ 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
98 /*70*/ 8, 8, 8, 8, 8, 8,12, 8, 8, 8, 8, 8, 8, 8,12, 8,
99 /*80*/ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
100 /*90*/ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
101 /*A0*/ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
102 /*B0*/ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
103 /*C0*/ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
104 /*D0*/ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
105 /*E0*/ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8,
106 /*F0*/ 8, 8, 8, 8, 8, 8,15, 8, 8, 8, 8, 8, 8, 8,15, 8
107 };
108
109 static const char z80pg3[256] = { /* P3 == DD && P5 == FD */
110 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
111 /*--*--* - - - - - - - - - - - - - - - - */
112 /*00*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,15,UN,UN,UN,UN,UN,UN,
113 /*10*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,15,UN,UN,UN,UN,UN,UN,
114 /*20*/ UN,14,20,10, 8, 8,11,UN,UN,15,20,10, 8,8 ,11,UN,
115 /*30*/ UN,UN,UN,UN,23,23,19,UN,UN,15,UN,UN,UN,UN,UN,UN,
116 /*40*/ UN,UN,UN,UN, 8, 8,19,UN,UN,UN,UN,UN, 8, 8,19,UN,
117 /*50*/ UN,UN,UN,UN, 8, 8,19,UN,UN,UN,UN,UN, 8, 8,19,UN,
118 /*60*/ 8, 8, 8, 8, 8, 8,19, 8, 8, 8, 8, 8, 8, 8,19, 8,
119 /*70*/ 19,19,19,19,19,19,UN,19,UN,UN,UN,UN, 8, 8,19,UN,
120 /*80*/ UN,UN,UN,UN, 8, 8,19,UN,UN,UN,UN,UN, 8, 8,19,UN,
121 /*90*/ UN,UN,UN,UN, 8, 8,19,UN,UN,UN,UN,UN, 8, 8,19,UN,
122 /*A0*/ UN,UN,UN,UN, 8, 8,19,UN,UN,UN,UN,UN, 8, 8,19,UN,
123 /*B0*/ UN,UN,UN,UN, 8, 8,19,UN,UN,UN,UN,UN, 8, 8,19,UN,
124 /*C0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,P6,UN,UN,UN,UN,
125 /*D0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
126 /*E0*/ UN,14,UN,23,UN,15,UN,UN,UN, 8,UN,UN,UN,UN,UN,UN,
127 /*F0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,10,UN,UN,UN,UN,UN,UN
128 };
129
130 static const char z80pg4[256] = { /* P4 == ED */
131 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
132 /*--*--* - - - - - - - - - - - - - - - - */
133 /*00*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
134 /*10*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
135 /*20*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
136 /*30*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
137 /*40*/ 12,12,15,20, 8,14, 8, 9,12,12,15,20, 8,14, 8, 9,
138 /*50*/ 12,12,15,20, 8,14, 8, 9,12,12,15,20, 8,14, 8, 9,
139 /*60*/ 12,12,15,20, 8,14, 8,18,12,12,15,20, 8,14, 8,18,
140 /*70*/ 12,12,15,20, 8,14, 8,UN,12,12,15,20, 8,14, 8,UN,
141 /*80*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
142 /*90*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
143 /*A0*/ 16,16,16,16,UN,UN,UN,UN,16,16,16,16,UN,UN,UN,UN,
144 /*B0*/ 21,21,21,21,UN,UN,UN,UN,21,21,21,21,UN,UN,UN,UN,
145 /*C0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
146 /*D0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
147 /*E0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
148 /*F0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN
149 };
150
151 static const char z80pg6[256] = { /* P6 == FD CB && P6 == DD CB */
152 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
153 /*--*--* - - - - - - - - - - - - - - - - */
154 /*00*/ UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
155 /*10*/ UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
156 /*20*/ UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
157 /*30*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,23,UN,
158 /*40*/ UN,UN,UN,UN,UN,UN,20,UN,UN,UN,UN,UN,UN,UN,20,UN,
159 /*50*/ UN,UN,UN,UN,UN,UN,20,UN,UN,UN,UN,UN,UN,UN,20,UN,
160 /*60*/ UN,UN,UN,UN,UN,UN,20,UN,UN,UN,UN,UN,UN,UN,20,UN,
161 /*70*/ UN,UN,UN,UN,UN,UN,20,UN,UN,UN,UN,UN,UN,UN,20,UN,
162 /*80*/ UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
163 /*90*/ UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
164 /*A0*/ UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
165 /*B0*/ UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
166 /*C0*/ UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
167 /*D0*/ UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
168 /*E0*/ UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN,
169 /*F0*/ UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,UN,UN,23,UN
170 };
171
172 static const char *z80Page[7] = {
173 z80pg1, z80pg2, z80pg3, z80pg4,
174 z80pg3, z80pg6, z80pg6
175 };
176
177 /*
178 * HD64180 / Z180 Opcode Cycle Pages
179 */
180
181 static const char hd64pg1[256] = {
182 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
183 /*--*--* - - - - - - - - - - - - - - - - */
184 /*00*/ 3, 9, 7, 4, 4, 4, 6, 3, 4, 7, 6, 4, 4, 4, 6, 3,
185 /*10*/ 9, 9, 7, 4, 4, 4, 6, 3, 8, 7, 6, 4, 4, 4, 6, 3,
186 /*20*/ 8, 9,16, 4, 4, 4, 6, 4, 8, 7,15, 4, 4, 4, 6, 3,
187 /*30*/ 8, 9,13, 4,10,10, 9, 3, 8, 7,12, 4, 4, 4, 6, 3,
188 /*40*/ 4, 4, 4, 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 6, 4,
189 /*50*/ 4, 4, 4, 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 6, 4,
190 /*60*/ 4, 4, 4, 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 6, 4,
191 /*70*/ 7, 7, 7, 7, 7, 7, 3, 7, 4, 4, 4, 4, 4, 4, 6, 4,
192 /*80*/ 4, 4, 4, 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 6, 4,
193 /*90*/ 4, 4, 4, 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 6, 4,
194 /*A0*/ 4, 4, 4, 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 6, 4,
195 /*B0*/ 4, 4, 4, 4, 4, 4, 6, 4, 4, 4, 4, 4, 4, 4, 6, 4,
196 /*C0*/ 10, 9, 9, 9,16,11, 6,11,10, 9, 9,P2,16,16, 6,11,
197 /*D0*/ 10, 9, 9,10,16,11, 6,11,10, 3, 9, 9,16,P3, 6,11,
198 /*E0*/ 10, 9, 9,16,16,11, 6,11,10, 3, 9, 3,16,P4, 6,11,
199 /*F0*/ 10, 9, 9, 3,16,11, 6,11,10, 4, 9, 3,16,P5, 6,11
200 };
201
202 static const char hd64pg2[256] = { /* P2 == CB */
203 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
204 /*--*--* - - - - - - - - - - - - - - - - */
205 /*00*/ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
206 /*10*/ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
207 /*20*/ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
208 /*30*/ UN,UN,UN,UN,UN,UN,UN,UN, 7, 7, 7, 7, 7, 7,13, 7,
209 /*40*/ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
210 /*50*/ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
211 /*60*/ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
212 /*70*/ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
213 /*80*/ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
214 /*90*/ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
215 /*A0*/ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
216 /*B0*/ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
217 /*C0*/ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
218 /*D0*/ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
219 /*E0*/ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7,
220 /*F0*/ 7, 7, 7, 7, 7, 7,13, 7, 7, 7, 7, 7, 7, 7,13, 7
221 };
222
223 static const char hd64pg3[256] = { /* P3 == DD */
224 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
225 /*--*--* - - - - - - - - - - - - - - - - */
226 /*00*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,10,UN,UN,UN,UN,UN,UN,
227 /*10*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,10,UN,UN,UN,UN,UN,UN,
228 /*20*/ UN,12,19, 7,UN,UN,UN,UN,UN,10,18, 7,UN,UN,UN,UN,
229 /*30*/ UN,UN,UN,UN,18,18,15,UN,UN,10,UN,UN,UN,UN,UN,UN,
230 /*40*/ UN,UN,UN,UN,UN,UN,14,UN,UN,UN,UN,UN,UN,UN,14,UN,
231 /*50*/ UN,UN,UN,UN,UN,UN,14,UN,UN,UN,UN,UN,UN,UN,14,UN,
232 /*60*/ UN,UN,UN,UN,UN,UN,14,UN,UN,UN,UN,UN,UN,UN,14,UN,
233 /*70*/ 15,15,15,15,15,15,UN,15,UN,UN,UN,UN,UN,UN,14,UN,
234 /*80*/ UN,UN,UN,UN,UN,UN,14,UN,UN,UN,UN,UN,UN,UN,14,UN,
235 /*90*/ UN,UN,UN,UN,UN,UN,14,UN,UN,UN,UN,UN,UN,UN,14,UN,
236 /*A0*/ UN,UN,UN,UN,UN,UN,14,UN,UN,UN,UN,UN,UN,UN,14,UN,
237 /*B0*/ UN,UN,UN,UN,UN,UN,14,UN,UN,UN,UN,UN,UN,UN,14,UN,
238 /*C0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,P6,UN,UN,UN,UN,
239 /*D0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
240 /*E0*/ UN,12,UN,19,UN,14,UN,UN,UN, 6,UN,UN,UN,UN,UN,UN,
241 /*F0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN, 7,UN,UN,UN,UN,UN,UN
242 };
243
244 static const char hd64pg4[256] = { /* P4 == ED */
245 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
246 /*--*--* - - - - - - - - - - - - - - - - */
247 /*00*/ 12,13,UN,UN, 7,UN,UN,UN,12,13,UN,UN, 7,UN,UN,UN,
248 /*10*/ 12,13,UN,UN, 7,UN,UN,UN,12,13,UN,UN, 7,UN,UN,UN,
249 /*20*/ 12,13,UN,UN, 7,UN,UN,UN,12,13,UN,UN, 7,UN,UN,UN,
250 /*30*/ UN,UN,UN,UN,10,UN,UN,UN,12,13,UN,UN, 7,UN,UN,UN,
251 /*40*/ 9,10,10,19, 6,12, 6, 6, 9,10,10,18,17,12,UN, 6,
252 /*50*/ 9,10,10,19,UN,UN, 6, 6, 9,10,10,18,17,UN, 6, 6,
253 /*60*/ 9,10,10,19, 9,UN,UN,16, 9,10,10,18,17,UN,UN,16,
254 /*70*/ UN,10,10,19,12,UN, 8,UN, 9,10,10,18,17,UN,UN,UN,
255 /*80*/ UN,UN,UN,14,UN,UN,UN,UN,UN,UN,UN,14,UN,UN,UN,UN,
256 /*90*/ UN,UN,UN,16,UN,UN,UN,UN,UN,UN,UN,16,UN,UN,UN,UN,
257 /*A0*/ 12,12,12,12,UN,UN,UN,UN,12,12,12,12,UN,UN,UN,UN,
258 /*B0*/ 14,14,14,14,UN,UN,UN,UN,14,14,14,14,UN,UN,UN,UN,
259 /*C0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
260 /*D0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
261 /*E0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
262 /*F0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN
263 };
264
265 static const char hd64pg5[256] = { /* P5 == FD */
266 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
267 /*--*--* - - - - - - - - - - - - - - - - */
268 /*00*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,10,UN,UN,UN,UN,UN,UN,
269 /*10*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,10,UN,UN,UN,UN,UN,UN,
270 /*20*/ UN,12,19, 7,UN,UN,UN,UN,UN,10,18, 7,UN,UN,UN,UN,
271 /*30*/ UN,UN,UN,UN,18,18,15,UN,UN,10,UN,UN,UN,UN,UN,UN,
272 /*40*/ UN,UN,UN,UN,UN,UN,14,UN,UN,UN,UN,UN,UN,UN,14,UN,
273 /*50*/ UN,UN,UN,UN,UN,UN,14,UN,UN,UN,UN,UN,UN,UN,14,UN,
274 /*60*/ UN,UN,UN,UN,UN,UN,14,UN,UN,UN,UN,UN,UN,UN,14,UN,
275 /*70*/ 15,15,15,15,15,15,UN,15,UN,UN,UN,UN,UN,UN,14,UN,
276 /*80*/ UN,UN,UN,UN,UN,UN,14,UN,UN,UN,UN,UN,UN,UN,14,UN,
277 /*90*/ UN,UN,UN,UN,UN,UN,14,UN,UN,UN,UN,UN,UN,UN,14,UN,
278 /*A0*/ UN,UN,UN,UN,UN,UN,14,UN,UN,UN,UN,UN,UN,UN,14,UN,
279 /*B0*/ UN,UN,UN,UN,UN,UN,14,UN,UN,UN,UN,UN,UN,UN,14,UN,
280 /*C0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,P7,UN,UN,UN,UN,
281 /*D0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
282 /*E0*/ UN,12,UN,19,UN,14,UN,UN,UN, 6,UN,UN,UN,UN,UN,UN,
283 /*F0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN, 7,UN,UN,UN,UN,UN,UN
284 };
285
286 static const char hd64pg6[256] = { /* P6 == DD CB */
287 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
288 /*--*--* - - - - - - - - - - - - - - - - */
289 /*00*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
290 /*10*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
291 /*20*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
292 /*30*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,19,UN,
293 /*40*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
294 /*50*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
295 /*60*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
296 /*70*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
297 /*80*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
298 /*90*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
299 /*A0*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
300 /*B0*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
301 /*C0*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
302 /*D0*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
303 /*E0*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
304 /*F0*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN
305 };
306
307 static const char hd64pg7[256] = { /* P7 == FD CB */
308 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
309 /*--*--* - - - - - - - - - - - - - - - - */
310 /*00*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
311 /*10*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
312 /*20*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
313 /*30*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,19,UN,
314 /*40*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
315 /*50*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
316 /*60*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
317 /*70*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
318 /*80*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
319 /*90*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
320 /*A0*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
321 /*B0*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
322 /*C0*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
323 /*D0*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
324 /*E0*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN,
325 /*F0*/ UN,UN,UN,UN,UN,UN,19,UN,UN,UN,UN,UN,UN,UN,19,UN
326 };
327
328 static const char *hd64Page[7] = {
329 hd64pg1, hd64pg2, hd64pg3, hd64pg4,
330 hd64pg5, hd64pg6, hd64pg7
331 };
332
333 /*
334 * Z80-ZXN Opcode Cycle Pages
335 */
336
337 static const char zxnpg4[256] = { /* P4 == ED */
338 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
339 /*--*--* - - - - - - - - - - - - - - - - */
340 /*00*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
341 /*10*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
342 /*20*/ UN,UN,UN, 8, 8,UN,UN,11, 8, 8, 8, 8, 8,UN,UN,UN,
343 /*30*/ 8, 8, 8, 8,16,16,16,UN,UN,UN,UN,UN,UN,UN,UN,UN,
344 /*40*/ 12,12,15,20, 8,14, 8, 9,12,12,15,20, 8,14, 8, 9,
345 /*50*/ 12,12,15,20, 8,14, 8, 9,12,12,15,20, 8,14, 8, 9,
346 /*60*/ 12,12,15,20, 8,14, 8,18,12,12,15,20, 8,14, 8,18,
347 /*70*/ 12,12,15,20, 8,14, 8,UN,12,12,15,20, 8,14, 8,UN,
348 /*80*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,23,UN,UN,UN,UN,UN,
349 /*90*/ 16,20,17, 8, 8, 8,UN,UN,13,UN,UN,UN,UN,UN,UN,UN,
350 /*A0*/ 16,16,16,16,16,14,UN,UN,16,16,16,16,16,UN,UN,UN,
351 /*B0*/ 21,21,21,21,21,UN,UN,21,21,21,21,21,21,UN,UN,UN,
352 /*C0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
353 /*D0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
354 /*E0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
355 /*F0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN
356 };
357
358 static const char *zxnPage[7] = {
359 z80pg1, z80pg2, z80pg3, zxnpg4,
360 z80pg3, z80pg6, z80pg6
361 };
362
363 /*
364 * EZ80 Opcode Cycle Pages
365 */
366
367 static const char ez80pg1[256] = {
368 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
369 /*--*--* - - - - - - - - - - - - - - - - */
370 /*00*/ 1, 3, 2, 1, 1, 1, 2, 1, 1, 1, 2, 1, 1, 1, 2, 1,
371 /*10*/ 4, 3, 2, 1, 1, 1, 2, 1, 3, 1, 2, 1, 1, 1, 2, 1,
372 /*20*/ 3, 3, 7, 1, 1, 1, 2, 1, 3, 1, 5, 1, 1, 1, 2, 1,
373 /*30*/ 3, 3, 4, 1, 4, 4, 3, 1, 3, 1, 4, 1, 1, 1, 2, 1,
374 /*40*/ PF, 1, 1, 1, 1, 1, 2, 1, 1,PF, 1, 1, 1, 1, 2, 1,
375 /*50*/ 1, 1,PF, 1, 1, 1, 2, 1, 1, 1, 1,PF, 1, 1, 2, 1,
376 /*60*/ 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 2, 1,
377 /*70*/ 2, 2, 2, 2, 2, 2, 1, 2, 1, 1, 1, 1, 1, 1, 2, 1,
378 /*80*/ 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 2, 1,
379 /*90*/ 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 2, 1,
380 /*A0*/ 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 2, 1,
381 /*B0*/ 1, 1, 1, 1, 1, 1, 2, 1, 1, 1, 1, 1, 1, 1, 2, 1,
382 /*C0*/ 6, 3, 4, 4, 6, 3, 2, 5, 6, 5, 4,P2, 6, 5, 2, 5,
383 /*D0*/ 6, 3, 4, 3, 6, 3, 2, 5, 6, 1, 4, 3, 6,P3, 2, 5,
384 /*E0*/ 6, 3, 4, 5, 6, 3, 2, 5, 6, 3, 4, 1, 6,P4, 2, 5,
385 /*F0*/ 6, 3, 4, 1, 6, 3, 2, 5, 6, 1, 4, 1, 6,P5, 2, 5
386 };
387
388 static const char ez80pg2[256] = { /* P2 == CB */
389 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
390 /*--*--* - - - - - - - - - - - - - - - - */
391 /*00*/ 2, 2, 2, 2, 2, 2, 5, 2, 2, 2, 2, 2, 2, 2, 5, 2,
392 /*10*/ 2, 2, 2, 2, 2, 2, 5, 2, 2, 2, 2, 2, 2, 2, 5, 2,
393 /*20*/ 2, 2, 2, 2, 2, 2, 5, 2, 2, 2, 2, 2, 2, 2, 5, 2,
394 /*30*/ UN,UN,UN,UN,UN,UN,UN,UN, 2, 2, 2, 2, 2, 2, 5, 2,
395 /*40*/ 2, 2, 2, 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 3, 2,
396 /*50*/ 2, 2, 2, 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 3, 2,
397 /*60*/ 2, 2, 2, 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 3, 2,
398 /*70*/ 2, 2, 2, 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 3, 2,
399 /*80*/ 2, 2, 2, 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 3, 2,
400 /*90*/ 2, 2, 2, 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 3, 2,
401 /*A0*/ 2, 2, 2, 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 3, 2,
402 /*B0*/ 2, 2, 2, 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 3, 2,
403 /*C0*/ 2, 2, 2, 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 3, 2,
404 /*D0*/ 2, 2, 2, 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 3, 2,
405 /*E0*/ 2, 2, 2, 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 3, 2,
406 /*F0*/ 2, 2, 2, 2, 2, 2, 3, 2, 2, 2, 2, 2, 2, 2, 3, 2
407 };
408
409 static const char ez80pg3[256] = { /* P3 == DD */
410 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
411 /*--*--* - - - - - - - - - - - - - - - - */
412 /*00*/ UN,UN,UN,UN,UN,UN,UN, 5,UN, 2,UN,UN,UN,UN,UN, 5,
413 /*10*/ UN,UN,UN,UN,UN,UN,UN, 5,UN, 2,UN,UN,UN,UN,UN, 5,
414 /*20*/ UN, 4, 6, 2, 2, 2, 2, 5,UN, 2, 6, 2, 2, 2, 2, 5,
415 /*30*/ UN, 5,UN,UN, 6, 6, 5, 5,UN, 2,UN,UN,UN,UN, 5, 5,
416 /*40*/ UN,UN,UN,UN, 2, 2, 4,UN,UN,UN,UN,UN, 2, 2, 4,UN,
417 /*50*/ UN,UN,UN,UN, 2, 2, 4,UN,UN,UN,UN,UN, 2, 2, 4,UN,
418 /*60*/ 2, 2, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 4, 2,
419 /*70*/ 4, 4, 4, 4, 4, 4,UN, 4,UN,UN,UN,UN, 2, 2, 4,UN,
420 /*80*/ UN,UN,UN,UN, 2, 2, 4,UN,UN,UN,UN,UN, 2, 2, 4,UN,
421 /*90*/ UN,UN,UN,UN, 2, 2, 4,UN,UN,UN,UN,UN, 2, 2, 4,UN,
422 /*A0*/ UN,UN,UN,UN, 2, 2, 4,UN,UN,UN,UN,UN, 2, 2, 4,UN,
423 /*B0*/ UN,UN,UN,UN, 2, 2, 4,UN,UN,UN,UN,UN, 2, 2, 4,UN,
424 /*C0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,P6,UN,UN,UN,UN,
425 /*D0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
426 /*E0*/ UN, 4,UN, 6,UN, 4,UN,UN,UN, 4,UN,UN,UN,UN,UN,UN,
427 /*F0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN, 2,UN,UN,UN,UN,UN,UN
428 };
429
430 static const char ez80pg4[256] = { /* P4 == ED */
431 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
432 /*--*--* - - - - - - - - - - - - - - - - */
433 /*00*/ 4, 4, 3, 3, 2,UN,UN, 4, 4, 4,UN,UN, 2,UN,UN, 4,
434 /*10*/ 4, 4, 3, 3, 2,UN,UN, 4, 4, 4,UN,UN, 2,UN,UN, 4,
435 /*20*/ 4, 4, 3, 3, 2,UN,UN, 4, 4, 4,UN,UN, 2,UN,UN, 4,
436 /*30*/ UN, 4, 3, 3, 3,UN,UN, 4, 4, 4,UN,UN, 2,UN, 4, 4,
437 /*40*/ 3, 3, 2, 6, 2, 6, 2, 2, 3, 3, 2, 6, 6, 6,UN, 2,
438 /*50*/ 3, 3, 2, 6, 3, 3, 2, 2, 3, 3, 2, 6, 6,UN, 2, 2,
439 /*60*/ 3, 3, 2,UN, 3, 5, 5, 5, 3, 3, 2,UN, 6, 2, 2, 5,
440 /*70*/ UN,UN, 2, 6, 4,UN, 2,UN, 3, 3, 2, 5, 6, 2, 2,UN,
441 /*80*/ UN,UN, 5, 5, 5,UN,UN,UN,UN,UN, 5, 5, 5,UN,UN,UN,
442 /*90*/ UN,UN, 2, 2, 2,UN,UN,UN,UN,UN, 2, 2, 2,UN,UN,UN,
443 /*A0*/ 5, 3, 5, 5, 5,UN,UN,UN, 5, 3, 5, 5, 5,UN,UN,UN,
444 /*B0*/ 2, 1, 2, 2, 2,UN,UN,UN, 2, 1, 2, 2, 2,UN,UN,UN,
445 /*C0*/ UN,UN, 2, 3,UN,UN,UN, 2,UN,UN, 2, 2,UN,UN,UN,UN,
446 /*D0*/ UN,UN,UN,UN,UN,UN,UN, 2,UN,UN,UN,UN,UN,UN,UN,UN,
447 /*E0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
448 /*F0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN
449 };
450
451 static const char ez80pg5[256] = { /* P5 == FD */
452 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
453 /*--*--* - - - - - - - - - - - - - - - - */
454 /*00*/ UN,UN,UN,UN,UN,UN,UN, 5,UN, 2,UN,UN,UN,UN,UN, 5,
455 /*10*/ UN,UN,UN,UN,UN,UN,UN, 5,UN, 2,UN,UN,UN,UN,UN, 5,
456 /*20*/ UN, 4, 6, 2, 2, 2, 2, 5,UN, 2, 6, 2, 2, 2, 2, 5,
457 /*30*/ UN, 5,UN,UN, 6, 6, 5, 5,UN, 2,UN,UN,UN,UN, 5, 5,
458 /*40*/ UN,UN,UN,UN, 2, 2, 4,UN,UN,UN,UN,UN, 2, 2, 4,UN,
459 /*50*/ UN,UN,UN,UN, 2, 2, 4,UN,UN,UN,UN,UN, 2, 2, 4,UN,
460 /*60*/ 2, 2, 2, 2, 2, 2, 4, 2, 2, 2, 2, 2, 2, 2, 4, 2,
461 /*70*/ 4, 4, 4, 4, 4, 4,UN, 4,UN,UN,UN,UN, 2, 2, 4,UN,
462 /*80*/ UN,UN,UN,UN, 2, 2, 4,UN,UN,UN,UN,UN, 2, 2, 4,UN,
463 /*90*/ UN,UN,UN,UN, 2, 2, 4,UN,UN,UN,UN,UN, 2, 2, 4,UN,
464 /*A0*/ UN,UN,UN,UN, 2, 2, 4,UN,UN,UN,UN,UN, 2, 2, 4,UN,
465 /*B0*/ UN,UN,UN,UN, 2, 2, 4,UN,UN,UN,UN,UN, 2, 2, 4,UN,
466 /*C0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,P7,UN,UN,UN,UN,
467 /*D0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,
468 /*E0*/ UN, 4,UN, 6,UN, 4,UN,UN,UN, 4,UN,UN,UN,UN,UN,UN,
469 /*F0*/ UN,UN,UN,UN,UN,UN,UN,UN,UN, 2,UN,UN,UN,UN,UN,UN
470 };
471
472 static const char ez80pg6[256] = { /* P6 == DD CB */
473 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
474 /*--*--* - - - - - - - - - - - - - - - - */
475 /*00*/ UN,UN,UN,UN,UN,UN, 7,UN,UN,UN,UN,UN,UN,UN, 7,UN,
476 /*10*/ UN,UN,UN,UN,UN,UN, 7,UN,UN,UN,UN,UN,UN,UN, 7,UN,
477 /*20*/ UN,UN,UN,UN,UN,UN, 7,UN,UN,UN,UN,UN,UN,UN, 7,UN,
478 /*30*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN, 7,UN,
479 /*40*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
480 /*50*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
481 /*60*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
482 /*70*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
483 /*80*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
484 /*90*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
485 /*A0*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
486 /*B0*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
487 /*C0*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
488 /*D0*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
489 /*E0*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
490 /*F0*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN
491 };
492
493 static const char ez80pg7[256] = { /* P7 == FD CB */
494 /*--*--* 0 1 2 3 4 5 6 7 8 9 A B C D E F */
495 /*--*--* - - - - - - - - - - - - - - - - */
496 /*00*/ UN,UN,UN,UN,UN,UN, 7,UN,UN,UN,UN,UN,UN,UN, 7,UN,
497 /*10*/ UN,UN,UN,UN,UN,UN, 7,UN,UN,UN,UN,UN,UN,UN, 7,UN,
498 /*20*/ UN,UN,UN,UN,UN,UN, 7,UN,UN,UN,UN,UN,UN,UN, 7,UN,
499 /*30*/ UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN,UN, 7,UN,
500 /*40*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
501 /*50*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
502 /*60*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
503 /*70*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
504 /*80*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
505 /*90*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
506 /*A0*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
507 /*B0*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
508 /*C0*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
509 /*D0*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
510 /*E0*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN,
511 /*F0*/ UN,UN,UN,UN,UN,UN, 5,UN,UN,UN,UN,UN,UN,UN, 5,UN
512 };
513
514 static const char *ez80Page[7] = {
515 ez80pg1, ez80pg2, ez80pg3, ez80pg4,
516 ez80pg5, ez80pg6, ez80pg7
517 };
518
519 /*
520 * Process a machine op.
521 */
522 VOID
523 machine(mp)
524 struct mne *mp;
525 {
526 int op, t1, t2, t3;
527 struct expr e1, e2;
528 int rf, sf, v1, v2;
529
530 clrexpr(&e1);
531 clrexpr(&e2);
532 op = (int) mp->m_valu;
533 rf = mp->m_type;
534 sf = mp->m_flag;
535
536 /* check eZ80 flags in non-eZ80 mode and block such instruction */
537 if ((sf & (M_LIL | M_SIS)) != 0 && mchtyp != X_EZ80)
538 rf = 0;
539
540 switch (mchtyp) {
541 case X_Z80:
542 if (rf > S_CPU)
543 rf = 0;
544 break;
545 case X_HD64:
546 if (rf > X_TSTIO)
547 rf = 0;
548 break;
549 case X_ZXN:
550 if (rf > S_CPU && rf < X_ZXN_INH2 && rf != X_TST && rf != X_MLT)
551 rf = 0;
552 break;
553 case X_EZ80:
554 if (rf >= X_ZXN_INH2 && rf < X_EZ_ADL) {
555 rf = 0;
556 break;
557 }
558 /* handle eZ80 suffix and write it as prefix byte */
559 if (ez80_adl) {
560 switch (sf) {
561 case M_S:
562 sf = M_SIL;
563 case M_SIL:
564 outab (0x52);
565 break;
566 case M_IS:
567 sf = M_LIS;
568 case M_LIS:
569 outab (0x49);
570 break;
571 case M_L:
572 case M_IL:
573 sf = M_LIL;
574 case M_LIL:
575 outab (0x5B);
576 break;
577 case M_SIS:
578 outab (0x40);
579 break;
580 }
581 } else {
582 switch (sf) {
583 case M_S:
584 case M_IS:
585 sf = M_SIS;
586 case M_SIS:
587 outab (0x40);
588 break;
589 case M_L:
590 sf = M_LIS;
591 case M_LIS:
592 outab (0x49);
593 break;
594 case M_IL:
595 sf = M_SIL;
596 case M_SIL:
597 outab (0x52);
598 break;
599 case M_LIL:
600 outab (0x5B);
601 break;
602 }
603 }
604 break;
605
606 case X_R800:
607 if (rf > S_CPU && rf < X_Z280_MULTU)
608 rf = 0;
609 break;
610
611 default:
612 rf = 0;
613 }
614
615 switch (rf) {
616
617 case S_INH1:
618 outab(op);
619 break;
620
621 case S_INH2:
622 outab(0xED);
623 outab(op);
624 break;
625
626 case S_RET:
627 if (more()) {
628 /*
629 * ret cc
630 */
631 if ((v1 = admode(CND)) != 0) {
632 outab(op | (v1<<3));
633 } else {
634 xerr('a', "Require condition code NZ, Z, NC, or C.");
635 }
636 } else {
637 /*
638 * ret
639 */
640 outab(0xC9);
641 }
642 break;
643
644 case S_PUSH:
645 /*
646 * push/pop af
647 */
648 if (admode(R16X)) {
649 outab(op+0x30);
650 break;
651 } else
652 /*
653 * push/pop bc/de/hl/ix/iy (not sp)
654 */
655 if ((v1 = admode(R16)) != 0 && (v1 &= 0xFF) != SP) {
656 if (v1 != gixiy(v1)) {
657 outab(op+0x20);
658 break;
659 }
660 outab(op | (v1<<4));
661 break;
662 }
663 if (mchtyp == X_ZXN && op == 0xC5 && (t1 = addr(&e1)) == S_IMMED) {
664 // ZXN push is big-endian
665 outab(0xED);
666 outab(0x8A);
667 // ASXXXX do not check for R_MSB/R_LSB for constants!!!
668 if (e1.e_flag==0 && e1.e_base.e_ap==NULL) {
669 outab(hibyte(e1.e_addr));
670 outab(lobyte(e1.e_addr));
671 } else {
672 outrb(&e1, R_MSB);
673 outrb(&e1, R_LSB);
674 }
675 break;
676 }
677 if (mchtyp == X_ZXN && op == 0xC1 && (v1 = admode(RX)) != 0 && (v1 &= 0xFF) == X) {
678 outab(0xED);
679 outab(0x8B);
680 break;
681 }
682 xerr('a', "Only 16-Bit registers except SP.");
683 break;
684
685 case S_RST:
686 v1 = (int) absexpr();
687 if (v1 & ~0x38) {
688 xerr('a', "Allowed values: N * 0x08, N = 0 -> 7.");
689 v1 = 0;
690 }
691 outab(op|v1);
692 break;
693
694 case S_IM:
695 expr(&e1, 0);
696 abscheck(&e1);
697 if (e1.e_addr > 2) {
698 xerr('a', "Values of 0, 1, and 2 are valid.");
699 e1.e_addr = 0;
700 }
701 outab(op);
702 outab(imtab[(int) e1.e_addr]);
703 break;
704
705 case S_BIT:
706 expr(&e1, 0);
707 t1 = 0;
708 v1 = (int) e1.e_addr;
709 if (v1 > 7) {
710 ++t1;
711 v1 &= 0x07;
712 }
713 op |= (v1<<3);
714 comma(1);
715 addr(&e2);
716 abscheck(&e1);
717 /*
718 * bit b,(hl)
719 * bit b,(ix+d)
720 * bit b,(iy+d)
721 * bit b,r
722 */
723 if (genop(0xCB, op, &e2, 0) || t1)
724 xerr('a', "Invalid Addressing Mode.");
725 break;
726
727 case S_RL_UNDOCD:
728 if (!allow_undoc)
729 xerr('a', "Undocumented instructions not enabled.");
730
731 case S_RL:
732 t1 = 0;
733 t2 = addr(&e2);
734 /*
735 * rl (hl)
736 * rl (ix+d)
737 * rl (iy+d)
738 * rl r
739 */
740 if (more()) {
741 if ((t2 != S_R8) || (e2.e_addr != A))
742 ++t1;
743 comma(1);
744 clrexpr(&e2);
745 t2 = addr(&e2);
746 }
747 if (genop(0xCB, op, &e2, 0) || t1)
748 xerr('a', "Invalid Addressing Mode.");
749 break;
750
751 case S_AND:
752 case S_SUB:
753 /*
754 * op (hl)
755 * op (ix+d)
756 * op (iy+d)
757 * op r
758 * op n [#n]
759 * op ixl
760 * op ixh
761 * op iyl
762 * op iyh
763 */
764 t1 = 0;
765 t2 = addr(&e2);
766 if (more()) {
767 /*
768 * op a,(hl)
769 * op a,(ix+d)
770 * op a,(iy+d)
771 * op a,r
772 * op a,n [a,#n]
773 * op a,ixl
774 * op a,ixh
775 * op a,iyl
776 * op a,iyh
777 */
778 if ((t2 != S_R8) || (e2.e_addr != A))
779 ++t1;
780 comma(1);
781 clrexpr(&e2);
782 t2 = addr(&e2);
783 }
784
785 if ((!t1) && allow_undoc && ((t2 == S_R8U1) || (t2 == S_R8U2))) {
786 /* undocumented instruction: and/sub a,ixh|ixl|iyh|iyl */
787 outab( ((t2 == S_R8U1) ? 0xDD : 0xFD ) );
788 outab( op + e2.e_addr );
789 break;
790 }
791
792 /*
793 * op (hl)
794 * op (ix+d)
795 * op (iy+d)
796 * op r
797 * op n [#n]
798 *
799 * op a,(hl)
800 * op a,(ix+d)
801 * op a,(iy+d)
802 * op a,r
803 * op a,n [a,#n]
804 */
805 if (genop(0, op, &e2, 1) || t1)
806 xerr('a', "Invalid Addressing Mode.");
807 break;
808
809 case S_ADD:
810 case S_ADC:
811 case S_SBC:
812 t1 = addr(&e1);
813 t2 = 0;
814 if (more()) {
815 comma(1);
816 t2 = addr(&e2);
817 }
818 if (t2 == 0) {
819 if (allow_undoc && ((t1 == S_R8U1) || (t1 == S_R8U2))) {
820 /* undocumented instruction: add/adc/sbc a,ixh|ixl|iyh|iyl */
821 outab( ((t1 == S_R8U1) ? 0xDD : 0xFD ) );
822 outab( op + e1.e_addr );
823 break;
824 }
825
826 if (genop(0, op, &e1, 1))
827 xerr('a', "Invalid Addressing Mode.");
828 break;
829 }
830 if ((t1 == S_R8) && (e1.e_addr == A)) {
831
832 if (allow_undoc && ((t2 == S_R8U1) || (t2 == S_R8U2))) {
833 /* undocumented instruction: add/adc/sbc a,ixh|ixl|iyh|iyl */
834 outab( ((t2 == S_R8U1) ? 0xDD : 0xFD ) );
835 outab( op + e2.e_addr );
836 break;
837 }
838
839 if (genop(0, op, &e2, 1))
840 xerr('a', "Second argument: Invalid Addressing Mode.");
841 break;
842 }
843 if ((t1 == S_R16) && (t2 == S_R16)) {
844 if (rf == S_ADD)
845 op = 0x09;
846 if (rf == S_ADC)
847 op = 0x4A;
848 if (rf == S_SBC)
849 op = 0x42;
850 v1 = (int) e1.e_addr;
851 v2 = (int) e2.e_addr;
852 /*
853 * op hl,bc
854 * op hl,de
855 * op hl,hl
856 * op hl,sp
857 */
858 if ((v1 == HL) && (v2 <= SP)) {
859 if (rf != S_ADD)
860 outab(0xED);
861 outab(op | (v2<<4));
862 break;
863 }
864 if (rf != S_ADD) {
865 xerr('a', "Only valid with ADD.");
866 break;
867 }
868 /*
869 * add ix,bc
870 * add ix,de
871 * add ix,ix
872 * add ix,sp
873 */
874 if ((v1 == IX) && (v2 != HL) && (v2 != IY)) {
875 if (v2 == IX)
876 v2 = HL;
877 outab(0xDD);
878 outab(op | (v2<<4));
879 break;
880 }
881 /*
882 * add iy,bc
883 * add iy,de
884 * add iy,iy
885 * add iy,sp
886 */
887 if ((v1 == IY) && (v2 != HL) && (v2 != IX)) {
888 if (v2 == IY)
889 v2 = HL;
890 outab(0xFD);
891 outab(op | (v2<<4));
892 break;
893 }
894 }
895 if (mchtyp == X_ZXN && rf == S_ADD && t1 == S_R16) {
896 if (e1.e_addr == HL && t2 == S_R8 && e2.e_addr == A) {
897 outab(0xED);
898 outab(0x31);
899 break;
900 }
901 if (e1.e_addr == DE && t2 == S_R8 && e2.e_addr == A) {
902 outab(0xED);
903 outab(0x32);
904 break;
905 }
906 if (e1.e_addr == BC && t2 == S_R8 && e2.e_addr == A) {
907 outab(0xED);
908 outab(0x33);
909 break;
910 }
911 if (e1.e_addr == HL && t2 == S_IMMED) {
912 outab(0xED);
913 outab(0x34);
914 outrw(&e2, 0);
915 break;
916 }
917 if (e1.e_addr == DE && t2 == S_IMMED) {
918 outab(0xED);
919 outab(0x35);
920 outrw(&e2, 0);
921 break;
922 }
923 if (e1.e_addr == BC && t2 == S_IMMED) {
924 outab(0xED);
925 outab(0x36);
926 outrw(&e2, 0);
927 break;
928 }
929 }
930 xerr('a', "Invalid Addressing Mode.");
931 break;
932
933 case S_LD:
934 /*
935 * Enumerated ld instructions:
936 *
937 * ld
938 * ld.l ld.il ld.lil
939 * ld.s ld.is ld.sis
940 */
941 t1 = addr(&e1);
942 comma(1);
943 t2 = addr(&e2);
944 /*
945 * ld r,g
946 * ld r,n (r,#n)
947 * ld r,(hl)
948 * ld r,(ix+d)
949 * ld r,(iy+d)
950 */
951 if (t1 == S_R8) {
952 /*
953 * ld r,g
954 */
955 v1 = op | e1.e_addr<<3;
956 if (genop(0, v1, &e2, 0) == 0)
957 break;
958 /*
959 * ld r,n (r,#n)
960 */
961 if (t2 == S_IMMED) {
962 outab((e1.e_addr<<3) | 0x06);
963 outrb(&e2,0);
964 break;
965 }
966 }
967
968 if (allow_undoc &&
969 ((t1 == S_R8U1) || (t1 == S_R8U2)) &&
970 (t2 == S_IMMED))
971 {
972 outab( ((t1 == S_R8U1) ? 0xDD : 0xFD ) );
973 outab((e1.e_addr<<3) | 0x06);
974 outrb(&e2,0);
975 break;
976 }
977
978 v1 = (int) e1.e_addr;
979 v2 = (int) e2.e_addr;
980 /*
981 * ld be,mn [be,#mn]
982 * ld de,mn [de,#mn]
983 * ld hl,mn [hl,#mn]
984 * ld sp,mn [sp,#mn]
985 * ld ix,mn [ix,#mn]
986 * ld iy,mn [iy,#mn]
987 */
988 if ((t1 == S_R16) && (t2 == S_IMMED)) {
989 v1 = gixiy(v1);
990 outab(0x01|(v1<<4));
991 glilsis(sf, &e2);
992 break;
993 }
994
995 /*
996 * ld bc,(hl)
997 * ld de,(hl)
998 * ld hl,(hl)
999 * ld ix,(hl)
1000 * ld iy,(hl)
1001 */
1002 if (mchtyp == X_EZ80 && (t1 == S_R16) && (t2 == S_IDHL)) {
1003 if (v1 == SP) {
1004 aerr();
1005 break;
1006 }
1007 outab(0xED);
1008 if (v1 == IX) {
1009 outab(0x37);
1010 } else
1011 if (v1 == IY) {
1012 outab(0x31);
1013 } else {
1014 outab(7 + (v1 << 4));
1015 }
1016 break;
1017 }
1018
1019 /*
1020 * ld (hl),bc
1021 * ld (hl),de
1022 * ld (hl),hl
1023 * ld (hl),ix
1024 * ld (hl),iy
1025 */
1026 if (mchtyp == X_EZ80 && (t2 == S_R16) && (t1 == S_IDHL)) {
1027 if (v2 == SP) {
1028 aerr();
1029 break;
1030 }
1031 outab(0xED);
1032 if (v2 == IX) {
1033 outab(0x3f);
1034 } else
1035 if (v2 == IY) {
1036 outab(0x3e);
1037 } else {
1038 outab(0xf + (v2 << 4));
1039 }
1040 break;
1041 }
1042
1043 /*
1044 * ld bc,(ix+d) ld bc,(iy+d)
1045 * ld de,(ix+d) ld de,(iy+d)
1046 * ld hl,(ix+d) ld hl,(iy+d)
1047 * ld ix,(ix+d) ld ix,(iy+d)
1048 * ld iy,(ix+d) ld iy,(iy+d)
1049 */
1050 if (mchtyp == X_EZ80 && (t1 == S_R16) && ((t2 == S_IDIX) || (t2 == S_IDIY))) {
1051 if (v1 == SP) {
1052 xerr('a', "Only BC, DE, HL, IX and IY are allowed.");
1053 break;
1054 }
1055 if (t2 == S_IDIX) {
1056 outab(0xDD);
1057 if (v1 == IX) {
1058 outab(0x37);
1059 } else
1060 if (v1 == IY) {
1061 outab(0x31);
1062 }
1063 } else {
1064 outab(0xFD);
1065 if (v1 == IX) {
1066 outab(0x31);
1067 }else
1068 if (v1 == IY) {
1069 outab(0x37);
1070 }
1071 }
1072 if ((v1 == BC) || (v1 == DE) || (v1 == HL))
1073 outab((v1 << 4) + 7);
1074 outrb(&e2, R_SGND);
1075 break;
1076 }
1077
1078 /*
1079 * ld (ix+d),bc ld (iy+d),bc
1080 * ld (ix+d),de ld (iy+d),de
1081 * ld (ix+d),hl ld (iy+d),hl
1082 * ld (ix+d),ix ld (iy+d),ix
1083 * ld (ix+d),iy ld (iy+d),iy
1084 */
1085 if (mchtyp == X_EZ80 && (t2 == S_R16) && ((t1 == S_IDIX) || (t1 == S_IDIY))) {
1086 if (v2 == SP) {
1087 xerr('a', "Only BC, DE, HL, IX and IY are allowed.");
1088 break;
1089 }
1090 if (t1 == S_IDIX) {
1091 outab(0xDD);
1092 if (v2 == IX) {
1093 outab(0x3F);
1094 } else
1095 if (v2 == IY) {
1096 outab(0x3E);
1097 }
1098 } else {
1099 outab(0xFD);
1100 if (v2 == IX) {
1101 outab(0x3E);
1102 } else
1103 if (v2 == IY) {
1104 outab(0x3F);
1105 }
1106 }
1107 if ((v2 == BC) || (v2 == DE) || (v2 == HL))
1108 outab((v2 << 4) + 0xf);
1109 outrb(&e1, R_SGND);
1110 break;
1111 }
1112
1113 /*
1114 * ld be,(mn) [be,(#mn)]
1115 * ld de,(mn) [de,(#mn)]
1116 * ld hl,(mn) [hl,(#mn)]
1117 * ld sp,(mn) [sp,(#mn)]
1118 * ld ix,(mn) [ix,(#mn)]
1119 * ld iy,(mn) [iy,(#mn)]
1120 */
1121 if ((t1 == S_R16) && (t2 == S_INDM)) {
1122 if (gixiy(v1) == HL) {
1123 outab(0x2A);
1124 } else {
1125 outab(0xED);
1126 outab(0x4B | (v1<<4));
1127 }
1128 glilsis(sf, &e2);
1129 break;
1130 }
1131 /*
1132 * ld (mn),bc [(#mn),bc]
1133 * ld (mn),de [(#mn),de]
1134 * ld (mn),hl [(#mn),hl]
1135 * ld (mn),sp [(#mn),sp]
1136 * ld (mn),ix [(#mn),ix]
1137 * ld (mn),iy [(#mn),iy]
1138 */
1139 if ((t1 == S_INDM) && (t2 == S_R16)) {
1140 if (gixiy(v2) == HL) {
1141 outab(0x22);
1142 } else {
1143 outab(0xED);
1144 outab(0x43 | (v2<<4));
1145 }
1146 glilsis(sf, &e1);
1147 break;
1148 }
1149 /*
1150 * ld a,(mn) [a,(#mn)]
1151 */
1152 if ((t1 == S_R8) && (v1 == A) && (t2 == S_INDM)) {
1153 outab(0x3A);
1154 outrw(&e2, 0);
1155 break;
1156 }
1157 /*
1158 * ld (mn),a [(#mn),a]
1159 */
1160 if ((t1 == S_INDM) && (t2 == S_R8) && (v2 == A)) {
1161 outab(0x32);
1162 glilsis(sf, &e1);
1163 break;
1164 }
1165 /*
1166 * ld (hl),r
1167 * ld (ix+d),r
1168 * ld (iy+d),r
1169 */
1170 if ((t2 == S_R8) && (gixiy(t1) == S_IDHL)) {
1171 outab(0x70|v2);
1172 if (t1 != S_IDHL)
1173 outrb(&e1, 0);
1174 break;
1175 }
1176 /*
1177 * ld (hl),n [(hl),#n]
1178 * ld (ix+d),n [(ix+d),#n]
1179 * ld (iy+d),n [(iy+d),#n]
1180 */
1181 if ((t2 == S_IMMED) && (gixiy(t1) == S_IDHL)) {
1182 outab(0x36);
1183 if (t1 != S_IDHL)
1184 outrb(&e1, 0);
1185 outrb(&e2, 0);
1186 break;
1187 }
1188 /*
1189 * ld R,a
1190 * ld I,a
1191 */
1192 if ((t1 == S_R8X) && (t2 == S_R8) && (v2 == A)) {
1193 outab(0xED);
1194 outab(v1);
1195 break;
1196 }
1197 /*
1198 * ld MB,a
1199 */
1200 if ((t1 == S_R8MB) && (t2 == S_R8) && (v2 == A)) {
1201 outab(0xED);
1202 outab(0x6D);
1203 break;
1204 }
1205 /*
1206 * ld a,R
1207 * ld a,I
1208 */
1209 if ((t1 == S_R8) && (v1 == A) && (t2 == S_R8X)) {
1210 outab(0xED);
1211 outab(v2|0x10);
1212 break;
1213 }
1214 /*
1215 * ld a,R
1216 * ld a,I
1217 */
1218 if ((t1 == S_R8) && (v1 == A) && (t2 == S_R8MB)) {
1219 outab(0xED);
1220 outab(0x6E);
1221 break;
1222 }
1223 /*
1224 * ld sp,hl
1225 * ld sp,ix
1226 * ld sp,iy
1227 */
1228 if ((t1 == S_R16) && (v1 == SP)) {
1229 if ((t2 == S_R16) && (gixiy(v2) == HL)) {
1230 outab(0xF9);
1231 break;
1232 }
1233 }
1234 /*
1235 * ld a,(bc)
1236 * ld a,(de)
1237 */
1238 if ((t1 == S_R8) && (v1 == A)) {
1239 if ((t2 == S_IDBC) || (t2 == S_IDDE)) {
1240 outab(0x0A | ((t2-S_INDR)<<4));
1241 break;
1242 }
1243 }
1244 /*
1245 * ld (bc),a
1246 * ld (de),a
1247 */
1248 if ((t2 == S_R8) && (v2 == A)) {
1249 if ((t1 == S_IDBC) || (t1 == S_IDDE)) {
1250 outab(0x02 | ((t1-S_INDR)<<4));
1251 break;
1252 }
1253 }
1254
1255 /*
1256 * ld hl,i
1257 */
1258 if ((t1 == S_R16) && (v1 == HL) && (t2 == S_R8X) && (v2 == I)) {
1259 outab(0xED);
1260 outab(0xD7);
1261 break;
1262 }
1263 /*
1264 * ld i,hl
1265 */
1266 if ((t2 == S_R16) && (v2 == HL) && (t1 == S_R8X) && (v1 == I)) {
1267 outab(0xED);
1268 outab(0xC7);
1269 break;
1270 }
1271
1272 /*
1273 * ld r,ixl
1274 * ld r,ixh
1275 * ld r,iyl
1276 * ld r,iyh
1277 */
1278 if ( (t1 == S_R8) &&
1279 allow_undoc &&
1280 ((t2 == S_R8U1) || (t2 == S_R8U2)) )
1281 {
1282 if ( (e1.e_addr == H) || (e1.e_addr == L) )
1283 aerr();
1284 outab( ((t2 == S_R8U1) ? 0xDD : 0xFD ) );
1285 outab( (e1.e_addr << 3) | (0x40 + e2.e_addr) );
1286 break;
1287 }
1288 /*
1289 * ld ixl,r
1290 * ld ixh,r
1291 * ld iyl,r
1292 * ld iyh,r
1293 */
1294 if ( allow_undoc &&
1295 ((t1 == S_R8U1) || (t1 == S_R8U2)) &&
1296 (t2 == S_R8) )
1297 {
1298 if ( (e2.e_addr == H) || (e2.e_addr == L) )
1299 aerr();
1300
1301 outab( ((t1 == S_R8U1) ? 0xDD : 0xFD ) );
1302 outab( (e1.e_addr << 3) | (0x40 + e2.e_addr) );
1303 break;
1304 }
1305 /*
1306 * ld ixh,ihx
1307 * ld ixh,ixl
1308 * ld ixl,ixh
1309 * ld ixl,ixl
1310 * ld iyh,iyh
1311 * ld iyh,iyl
1312 * ld iyl,iyh
1313 * ld iyl,iyl
1314 */
1315 if ( allow_undoc &&
1316 ((t1 == S_R8U1) && (t2 == S_R8U1) || (t1 == S_R8U2) && (t2 == S_R8U2)) )
1317 {
1318 outab( ((t1 == S_R8U1) ? 0xDD : 0xFD ) );
1319 outab( (e1.e_addr << 3) | (0x40 + e2.e_addr) );
1320 break;
1321 }
1322 if (mchtyp == X_EZ80 && ((t1 == S_R8MB && v2 == A) || (v1 == A && t2 == S_R8MB))) {
1323 outab (0xED);
1324 outab ((v1 == A) ? 0x6E : 0x6D);
1325 break;
1326 }
1327 xerr('a', "Invalid Addressing Mode.");
1328 break;
1329
1330 case S_EX:
1331 t1 = addr(&e1);
1332 comma(1);
1333 t2 = addr(&e2);
1334 if (t2 == S_R16) {
1335 v1 = (int) e1.e_addr;
1336 v2 = (int) e2.e_addr;
1337 /*
1338 * ex (sp),hl
1339 * ex (sp),ix
1340 * ex (sp),iy
1341 */
1342 if ((t1 == S_IDSP) && (v1 == 0)) {
1343 if (gixiy(v2) == HL) {
1344 outab(op);
1345 break;
1346 }
1347 }
1348 /*
1349 * ex de,hl
1350 */
1351 if (t1 == S_R16) {
1352 if ((v1 == DE) && (v2 == HL)) {
1353 outab(0xEB);
1354 break;
1355 }
1356 }
1357 }
1358 /*
1359 * ex af,af'
1360 */
1361 if ((t1 == S_R16X) && (t2 == S_R16X)) {
1362 outab(0x08);
1363 break;
1364 }
1365 xerr('a', "Invalid Addressing Mode.");
1366 break;
1367
1368 case S_IN:
1369 case S_OUT:
1370 if (rf == S_IN) {
1371 t1 = addr(&e1);
1372 comma(1);
1373 t2 = addr(&e2);
1374 } else {
1375 t2 = addr(&e2);
1376 comma(1);
1377 t1 = addr(&e1);
1378 }
1379 v1 = (int) e1.e_addr;
1380 v2 = (int) e2.e_addr;
1381 if (t1 == S_R8) {
1382 /*
1383 * in a,(n) [in a,(#n)]
1384 * out (n),a [out (#n),a]
1385 */
1386 if ((v1 == A) && (t2 == S_INDM)) {
1387 outab(op);
1388 outab(v2);
1389 break;
1390 }
1391 /*
1392 * in r,(c) [in r,(bc)]
1393 * out (c),r [out (bc),r]
1394 */
1395 if (t2 == S_IDC) {
1396 outab(0xED);
1397 outab(((rf == S_IN) ? 0x40 : 0x41) + (v1<<3));
1398 break;
1399 }
1400 }
1401 xerr('a', "Invalid Addressing Mode.");
1402 break;
1403
1404 case S_DEC:
1405 case S_INC:
1406 t1 = addr(&e1);
1407 v1 = (int) e1.e_addr;
1408 /*
1409 * op r
1410 */
1411 if (t1 == S_R8) {
1412 outab(op|(v1<<3));
1413 break;
1414 }
1415 /*
1416 * op (hl)
1417 */
1418 if (t1 == S_IDHL) {
1419 outab(op|0x30);
1420 break;
1421 }
1422 /*
1423 * op (ix+d)
1424 * op (iy+d)
1425 */
1426 if (t1 != gixiy(t1)) {
1427 outab(op|0x30);
1428 outrb(&e1,0);
1429 break;
1430 }
1431 /*
1432 * op bc
1433 * op de
1434 * op hl
1435 * op sp
1436 * op ix
1437 * op iy
1438 */
1439 if (t1 == S_R16) {
1440 v1 = gixiy(v1);
1441 if (rf == S_INC) {
1442 outab(0x03|(v1<<4));
1443 break;
1444 }
1445 if (rf == S_DEC) {
1446 outab(0x0B|(v1<<4));
1447 break;
1448 }
1449 }
1450 /*
1451 * op IXL
1452 * op IXH
1453 * op IYL
1454 * op IYH
1455 */
1456 if (allow_undoc && ((t1 == S_R8U1)||(t1 == S_R8U2))) {
1457 outab( ((t1 == S_R8U1) ? 0xDD : 0xFD ) );
1458 outab(op|(v1<<3));
1459 break;
1460 }
1461 xerr('a', "Invalid Addressing Mode.");
1462 break;
1463
1464 case S_DJNZ:
1465 case S_JR:
1466 /*
1467 * jr cc,e
1468 */
1469 if (rf == S_JR && (v1 = admode(CND)) != 0) {
1470 if ((v1 &= 0xFF) <= 0x03) {
1471 op += (v1+1)<<3;
1472 } else {
1473 xerr('a', "Condition code required.");
1474 }
1475 comma(1);
1476 }
1477 /*
1478 * jr e
1479 */
1480 expr(&e2, 0);
1481 outab(op);
1482 if (mchpcr(&e2)) {
1483 v2 = (int) (e2.e_addr - dot.s_addr - 1);
1484 if (pass == 2 && ((v2 < -128) || (v2 > 127)))
1485 xerr('a', "Branching Range Exceeded.");
1486 outab(v2);
1487 } else {
1488 outrb(&e2, R_PCR);
1489 }
1490 if (e2.e_mode != S_USER)
1491 rerr();
1492 break;
1493
1494 case S_CALL:
1495 if ((v1 = admode(CND)) != 0) {
1496 /*
1497 * call cc,n
1498 */
1499 op |= (v1&0xFF)<<3;
1500 comma(1);
1501 } else {
1502 /*
1503 * call n
1504 */
1505 op = 0xCD;
1506 }
1507 expr(&e1, 0);
1508 outab(op);
1509 glilsis(sf, &e1);
1510 break;
1511
1512 case S_JP:
1513 /*
1514 * jp cc,mn
1515 */
1516 if ((v1 = admode(CND)) != 0) {
1517 op |= (v1&0xFF)<<3;
1518 comma(1);
1519 expr(&e1, 0);
1520 outab(op);
1521 glilsis(sf, &e1);
1522 break;
1523 }
1524 /*
1525 * jp mn
1526 */
1527 t1 = addr(&e1);
1528 if (t1 == S_USER) {
1529 outab(0xC3);
1530 glilsis(sf, &e1);
1531 break;
1532 }
1533 /*
1534 * jp (hl)
1535 * jp (ix)
1536 * jp (iy)
1537 */
1538 if ((e1.e_addr == 0) && (gixiy(t1) == S_IDHL)) {
1539 outab(0xE9);
1540 break;
1541 }
1542 /*
1543 * jp (c)
1544 */
1545 if (mchtyp == X_ZXN && t1 == S_IDC) {
1546 outab(0xED);
1547 outab(0x98);
1548 break;
1549 }
1550 xerr('a', "Invalid Addressing Mode.");
1551 break;
1552
1553 case X_UNDOCD:
1554 if (mchtyp != X_HD64)
1555 ++allow_undoc;
1556 else
1557 xerr('a', "HD64180/Z180: Traps on illegal instruction");
1558 break;
1559
1560 case S_CPU:
1561 opcycles = OPCY_CPU;
1562 mchtyp = op;
1563 sym[2].s_addr = op;
1564 lmode = SLIST;
1565 allow_undoc = (mchtyp == X_EZ80 || mchtyp == X_ZXN || mchtyp == X_R800);
1566 break;
1567
1568 case X_INH2:
1569 outab(0xED);
1570 outab(op);
1571 break;
1572
1573 case X_IN:
1574 case X_OUT:
1575 if (rf == X_IN) {
1576 t1 = addr(&e1);
1577 comma(1);
1578 t2 = addr(&e2);
1579 } else {
1580 t2 = addr(&e2);
1581 comma(1);
1582 t1 = addr(&e1);
1583 }
1584 if ((t1 == S_R8) && (t2 == S_INDM)) {
1585 outab(0xED);
1586 outab(op | (e1.e_addr<<3));
1587 outrb(&e2, 0);
1588 break;
1589 }
1590 xerr('a', "Invalid Addressing Mode.");
1591 break;
1592
1593 case X_MLT:
1594 /*
1595 * mlt bc/de/hl/sp
1596 */
1597 t1 = addr(&e1);
1598 if (mchtyp == X_ZXN && (t1 == S_R16) && (int) e1.e_addr == DE) {
1599 outab(0xED);
1600 outab(0x30);
1601 break;
1602 }
1603 else if ((t1 == S_R16) && ((v1 = (int) e1.e_addr) <= SP)) {
1604 outab(0xED);
1605 outab(op | (v1<<4));
1606 break;
1607 }
1608 xerr('a', "Only BC, DE, HL and SP are allowed.");
1609 break;
1610
1611 case X_TST:
1612 /*
1613 * op (hl)
1614 * op r
1615 * op n [#n]
1616 */
1617 t2 = addr(&e2);
1618 if (more()) {
1619 /*
1620 * op a,(hl)
1621 * op a,r
1622 * op a,n [a,#n]
1623 */
1624 if ((t2 != S_R8) || (e2.e_addr != A))
1625 aerr();
1626 comma(1);
1627 clrexpr(&e2);
1628 t2 = addr(&e2);
1629 }
1630 /*
1631 * tst (hl)
1632 */
1633 if ((mchtyp == X_HD64 || mchtyp == X_EZ80) && t2 == S_IDHL) {
1634 outab(0xED);
1635 outab(0x34);
1636 break;
1637 }
1638 /*
1639 * tst r
1640 */
1641 if ((mchtyp == X_HD64 || mchtyp == X_EZ80) && t2 == S_R8) {
1642 outab(0xED);
1643 outab(op | (e2.e_addr << 3));
1644 break;
1645 }
1646 /*
1647 * tst n [tst #n]
1648 */
1649 if (t2 == S_IMMED) {
1650 outab(0xED);
1651 if (mchtyp == X_HD64 || mchtyp == X_EZ80)
1652 outab(0x64);
1653 else if (mchtyp == X_ZXN)
1654 outab(0x27);
1655 else
1656 aerr();
1657 outrb(&e2, 0);
1658 break;
1659 }
1660 xerr('a', "Invalid Addressing Mode.");
1661 break;
1662
1663 case X_TSTIO:
1664 t1 = addr(&e1);
1665 /*
1666 * tstio n [tstio #n]
1667 */
1668 if (t1 == S_IMMED) {
1669 outab(0xED);
1670 outab(op);
1671 outrb(&e1, 0);
1672 break;
1673 }
1674 xerr('a', "Invalid Addressing Mode.");
1675 break;
1676
1677 case X_ZXN_INH2:
1678 switch (op) {
1679 case 0x23: //swap
1680 if (more()) { // Optional argument a on swap
1681 t1 = addr(&e1);
1682 if (t1 != S_R8 || e1.e_addr != A)
1683 aerr();
1684 }
1685 break;
1686 case 0x28: // BSLA DE,B
1687 case 0x29: // BSRA DE,B
1688 case 0x2a: // BSRL DE,B
1689 case 0x2b: // BSRF DE,B
1690 case 0x2c: // BRLC DE,B
1691 t1 = addr(&e1);
1692 comma(1);
1693 t2 = addr(&e2);
1694 if (t1 != S_R16 || e1.e_addr != DE || t2 != S_R8 || e2.e_addr != B)
1695 aerr();
1696 break;
1697 }
1698 outab(0xED);
1699 outab(op);
1700 break;
1701
1702 case X_ZXN_MUL:
1703 if ((t1 = addr(&e1)) == S_R8 && e1.e_addr == D &&
1704 more() && comma(1) &&
1705 (t2 = addr(&e2)) == S_R8 && e2.e_addr == E
1706 ) {
1707 outab(0xED);
1708 outab(op);
1709 break;
1710 }
1711 aerr();
1712 break;
1713
1714 case X_ZXN_MIRROR:
1715 t1 = addr(&e1);
1716 if (t1 == S_R8 && e1.e_addr == A) {
1717 outab(0xED);
1718 outab(0x24);
1719 break;
1720 }
1721 if (t1 == S_R16 && e1.e_addr == DE) {
1722 outab(0xED);
1723 outab(0x26);
1724 break;
1725 }
1726 aerr();
1727 break;
1728
1729 case X_ZXN_NEXTREG:
1730 t1 = addr(&e1);
1731 t2 = 0;
1732 if (more()) {
1733 comma(1);
1734 t2 = addr(&e2);
1735 }
1736 if (t1 == S_IMMED && t2 == S_IMMED) {
1737 outab(0xED);
1738 outab(0x91);
1739 outrb(&e1, 0);
1740 outrb(&e2, 0);
1741 break;
1742 }
1743 if (t1 == S_IMMED && t2 == S_R8 && e2.e_addr == A) {
1744 outab(0xED);
1745 outab(0x92);
1746 outrb(&e1, 0);
1747 break;
1748 }
1749 aerr();
1750 break;
1751
1752 case X_ZXN_CU_WAIT:
1753 t1 = addr(&e1);
1754 t2 = 0;
1755 if (more()) {
1756 comma(1);
1757 t2 = addr(&e2);
1758 }
1759 if (t1 == S_IMMED && t2 == S_IMMED) {
1760 if (e1.e_addr > 311 || e2.e_addr > 55) {
1761 aerr();
1762 break;
1763 }
1764 v1 = 0x8000 + (e2.e_addr << 9) + (e1.e_addr);
1765 outab(v1 >> 8);
1766 outab(v1 & 0xFF);
1767 opcycles = OPCY_ERR;
1768 break;
1769 }
1770 aerr();
1771 break;
1772
1773 case X_ZXN_CU_MOVE:
1774 t1 = addr(&e1);
1775 t2 = 0;
1776 if (more()) {
1777 comma(1);
1778 t2 = addr(&e2);
1779 }
1780 if (t1 == S_IMMED && t2 == S_IMMED) {
1781 if (e1.e_addr > 127 || e2.e_addr > 255) {
1782 aerr();
1783 break;
1784 }
1785 v1 = (e1.e_addr << 8) + (e2.e_addr);
1786 outab(v1 >> 8);
1787 outab(v1 & 0xFF);
1788 opcycles = OPCY_ERR;
1789 break;
1790 }
1791 aerr();
1792 break;
1793
1794 case X_ZXN_CU_STOP:
1795 outab(0xFF);
1796 outab(0xFF);
1797 opcycles = OPCY_ERR;
1798 break;
1799
1800 case X_ZXN_CU_NOP:
1801 outab(0x00);
1802 outab(0x00);
1803 opcycles = OPCY_ERR;
1804 break;
1805
1806 case X_EZ_ADL:
1807 expr(&e1,0);
1808 abscheck(&e1);
1809 ez80_adl = e1.e_addr;
1810 break;
1811
1812 case X_EZ_INH2:
1813 outab(0xED);
1814 outab(op);
1815 break;
1816
1817 case X_EZ_LEA:
1818 t1 = addr(&e1);
1819 v1 = (int) e1.e_addr;
1820 comma(1);
1821 t2 = addr(&e2);
1822 v2 = (int) e2.e_addr;
1823 comma(1);
1824 t3 = addr(&e2);
1825 if ((t1 == S_R16) && (v1 != SP) && (t2 == S_R16) && (v2==IX || v2==IY) && t3 == S_IMMED) {
1826 t2 = e2.e_mode = S_INDR + v2;
1827 outab(0xED);
1828 /*
1829 * op ix,ix,#d
1830 * op ix,iy,#d
1831 */
1832 if (v1 == IX) {
1833 if (t2 == S_IDIX) {
1834 outab(0x32);
1835 } else {
1836 outab(0x54);
1837 }
1838 } else
1839 /*
1840 * op iy,ix,#d
1841 * op iy,iy,#d
1842 */
1843 if (v1 == IY) {
1844 if (t2 == S_IDIX) {
1845 outab(0x55);
1846 } else {
1847 outab(0x33);
1848 }
1849 } else {
1850 if (t2 == S_IDIY) {
1851 /*
1852 * op bc,iy,#d
1853 * op de,iy,#d
1854 * op hl,iy,#d
1855 */
1856 outab((v1 << 4) + 3);
1857 } else {
1858 /*
1859 * op bc,ix,#d
1860 * op de,ix,#d
1861 * op hl,ix,#d
1862 */
1863 outab((v1 << 4) + 2);
1864 }
1865 }
1866 outrb(&e2, R_SGND);
1867 break;
1868 }
1869 aerr();
1870 break;
1871
1872 case X_EZ_PEA:
1873 t1 = addr(&e1);
1874 v1 = (int) e1.e_addr;
1875 comma(1);
1876 t2 = addr (&e1);
1877 /*
1878 * pea ix,#d
1879 * pea iy,#d
1880 */
1881 if ((t1 == S_R16) && (v1==IX || v1==IY) && t2 == S_IMMED) {
1882 t1 = e1.e_mode = S_INDR + v1;
1883 outab(0xED);
1884 if (t1 == S_IDIY)
1885 ++op;
1886 outab(op);
1887 outrb(&e1, R_SGND);
1888 break;
1889 }
1890 aerr();
1891 break;
1892
1893 case X_Z280_MULTU:
1894 t1 = addr(&e1);
1895 comma(1);
1896 t2 = addr(&e2);
1897 // For the R800, this instruction only works if the second operand is b, c, d, or e.
1898 if (t1 == S_R8 && e1.e_addr == A && t2 == S_R8 && (e2.e_addr == B || e2.e_addr == C || e2.e_addr == D || e2.e_addr == E)) {
1899 outab(0xED);
1900 outab(op | (e2.e_addr<<3));
1901 break;
1902 }
1903 aerr();
1904 break;
1905
1906 case X_Z280_MULTUW:
1907 t1 = addr(&e1);
1908 comma(1);
1909 t2 = addr(&e2);
1910 // For the R800, this instruction only works if the second operand is bc or sp.
1911 if (t1 == S_R16 && e1.e_addr == HL && t2 == S_R16 && (e2.e_addr == BC || e2.e_addr == SP)) {
1912 outab(0xED);
1913 outab(op | (e2.e_addr<<4));
1914 break;
1915 }
1916 aerr();
1917 break;
1918
1919 default:
1920 opcycles = OPCY_ERR;
1921 xerr('o', "Internal Opcode Error.");
1922 break;
1923 }
1924
1925 if (opcycles == OPCY_NONE) {
1926 switch (mchtyp) {
1927 case X_HD64:
1928 opcycles = hd64Page[0][cb[0] & 0xFF];
1929 while ((opcycles & OPCY_NONE) && (opcycles & OPCY_MASK)) {
1930 switch (opcycles) {
1931 case P2: /* CB xx */
1932 case P3: /* DD xx */
1933 case P4: /* ED xx */
1934 case P5: /* FD xx */
1935 opcycles = hd64Page[opcycles & OPCY_MASK][cb[1] & 0xFF];
1936 break;
1937 case P6: /* DD CB -- xx */
1938 case P7: /* FD CB -- xx */
1939 opcycles = hd64Page[opcycles & OPCY_MASK][cb[3] & 0xFF];
1940 break;
1941 default:
1942 opcycles = OPCY_NONE;
1943 break;
1944 }
1945 }
1946 break;
1947 case X_Z80:
1948 opcycles = z80Page[0][cb[0] & 0xFF];
1949 while ((opcycles & OPCY_NONE) && (opcycles & OPCY_MASK)) {
1950 switch (opcycles) {
1951 case P2: /* CB xx */
1952 case P3: /* DD xx */
1953 case P4: /* ED xx */
1954 case P5: /* FD xx */
1955 opcycles = z80Page[opcycles & OPCY_MASK][cb[1] & 0xFF];
1956 break;
1957 case P6: /* DD CB -- xx */
1958 case P7: /* FD CB -- xx */
1959 opcycles = z80Page[opcycles & OPCY_MASK][cb[3] & 0xFF];
1960 break;
1961 default:
1962 opcycles = OPCY_NONE;
1963 break;
1964 }
1965 }
1966 break;
1967 case X_ZXN:
1968 opcycles = zxnPage[0][cb[0] & 0xFF];
1969 while ((opcycles & OPCY_NONE) && (opcycles & OPCY_MASK)) {
1970 switch (opcycles) {
1971 case P2: /* CB xx */
1972 case P3: /* DD xx */
1973 case P4: /* ED xx */
1974 case P5: /* FD xx */
1975 opcycles = zxnPage[opcycles & OPCY_MASK][cb[1] & 0xFF];
1976 break;
1977 case P6: /* DD CB -- xx */
1978 case P7: /* FD CB -- xx */
1979 opcycles = zxnPage[opcycles & OPCY_MASK][cb[3] & 0xFF];
1980 break;
1981 default:
1982 opcycles = OPCY_NONE;
1983 break;
1984 }
1985 }
1986 break;
1987 case X_EZ80:
1988 {
1989 int of = 0;
1990 opcycles = ez80Page[0][cb[0] & 0xFF];
1991 while ((opcycles & OPCY_NONE) && (opcycles & OPCY_MASK)) {
1992 switch (opcycles) {
1993 case PF: /* 40 / 49 / 52 / 5B */
1994 of = 1;
1995 opcycles = ez80Page[0][cb[1] & 0xFF];
1996 break;
1997 case P2: /* CB xx */
1998 case P3: /* DD xx */
1999 case P4: /* ED xx */
2000 case P5: /* FD xx */
2001 opcycles = ez80Page[opcycles & OPCY_MASK][cb[of + 1] & 0xFF];
2002 break;
2003 case P6: /* DD CB -- xx */
2004 case P7: /* FD CB -- xx */
2005 opcycles = ez80Page[opcycles & OPCY_MASK][cb[of + 3] & 0xFF];
2006 break;
2007 default:
2008 opcycles = OPCY_NONE;
2009 break;
2010 }
2011 }
2012 }
2013 // ToDo: ASXX has 'Cycle Adjustment' here...
2014 break;
2015 default:
2016 break;
2017 }
2018 }
2019 }
2020
2021 /*
2022 * general addressing evaluation
2023 * return(0) if general addressing mode output, else
2024 * return(esp->e_mode)
2025 */
2026 int
2027 genop(pop, op, esp, f)
2028 int pop, op;
2029 struct expr *esp;
2030 int f;
2031 {
2032 int t1;
2033
2034 if ((t1 = esp->e_mode) == S_R8) {
2035 if (pop)
2036 outab(pop);
2037 outab(op|esp->e_addr);
2038 return(0);
2039 }
2040 if (t1 == S_IDHL) {
2041 if (pop)
2042 outab(pop);
2043 outab(op|0x06);
2044 return(0);
2045 }
2046 if (gixiy(t1) == S_IDHL) {
2047 if (pop) {
2048 outab(pop);
2049 outrb(esp,0);
2050 outab(op|0x06);
2051 } else {
2052 outab(op|0x06);
2053 outrb(esp,0);
2054 }
2055 return(0);
2056 }
2057 if ((t1 == S_IMMED) && (f)) {
2058 if (pop)
2059 outab(pop);
2060 outab(op|0x46);
2061 outrb(esp,0);
2062 return(0);
2063 }
2064 return(t1);
2065 }
2066
2067 /*
2068 * IX and IY prebyte check
2069 */
2070 int
2071 gixiy(v)
2072 int v;
2073 {
2074 if (v == IX) {
2075 v = HL;
2076 outab(0xDD);
2077 } else if (v == IY) {
2078 v = HL;
2079 outab(0xFD);
2080 } else if (v == S_IDIX) {
2081 v = S_IDHL;
2082 outab(0xDD);
2083 } else if (v == S_IDIY) {
2084 v = S_IDHL;
2085 outab(0xFD);
2086 }
2087 return(v);
2088 }
2089
2090 /*
2091 * .IL/.LIL and .IS/.SIS checks
2092 */
2093 VOID
2094 glilsis(sfx, esp)
2095 int sfx;
2096 struct expr *esp;
2097 {
2098
2099 // Pokus napsat zapis parametru 16/24-bit 'jinak'...
2100 if (ez80_adl && !(sfx & M_IS)) {
2101 outr3b(esp, R_ADL);
2102 } else {
2103 outrw(esp, 0);
2104 // warning "Proc je pro Z80 defaultni funkce outrwm()...?
2105 // funkce - viz asxxsrc/asout.c
2106 // zrejme se musim podivat do ASxx zdrojaku, jak se zpracovavaji priznaky R_ADL, R_Z80, R_PAGX1...
2107 // outrwm(esp, R_Z80|R_PAGX1, 0);
2108 }
2109 }
2110
2111 /*
2112 * Branch/Jump PCR Mode Check
2113 */
2114 int
2115 mchpcr(esp)
2116 struct expr *esp;
2117 {
2118 if (esp->e_base.e_ap == dot.s_area) {
2119 return(1);
2120 }
2121 if (esp->e_flag==0 && esp->e_base.e_ap==NULL) {
2122 /*
2123 * Absolute Destination
2124 *
2125 * Use the global symbol '.__.ABS.'
2126 * of value zero and force the assembler
2127 * to use this absolute constant as the
2128 * base value for the relocation.
2129 */
2130 esp->e_flag = 1;
2131 esp->e_base.e_sp = &sym[1];
2132 }
2133 return(0);
2134 }
2135
2136 /*
2137 * Machine dependent initialization
2138 */
2139 VOID
2140 minit()
2141 {
2142 /*
2143 * Byte Order
2144 */
2145 hilo = 0;
2146
2147 /*
2148 * Address Space
2149 */
2150 exprmasks(4);
2151
2152 if (pass == 0) {
2153 mchtyp = X_Z80;
2154 sym[2].s_addr = X_Z80;
2155 ez80_adl = 0;
2156 }
2157 }
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