sdcc/support/cpp/gcc/ira.h

   1 /* Communication between the Integrated Register Allocator (IRA) and
   2    the rest of the compiler.
   3    Copyright (C) 2006-2022 Free Software Foundation, Inc.
   4    Contributed by Vladimir Makarov <vmakarov@redhat.com>.
   5
   6 This file is part of GCC.
   7
   8 GCC is free software; you can redistribute it and/or modify it under
   9 the terms of the GNU General Public License as published by the Free
  10 Software Foundation; either version 3, or (at your option) any later
  11 version.
  12
  13 GCC is distributed in the hope that it will be useful, but WITHOUT ANY
  14 WARRANTY; without even the implied warranty of MERCHANTABILITY or
  15 FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License
  16 for more details.
  17
  18 You should have received a copy of the GNU General Public License
  19 along with GCC; see the file COPYING3.  If not see
  20 <http://www.gnu.org/licenses/>.  */
  21
  22 #if 0 // sdcpp ndef GCC_IRA_H
  23 #define GCC_IRA_H
  24
  25 #include "emit-rtl.h"
  26
  27 /* True when we use LRA instead of reload pass for the current
  28    function.  */
  29 extern bool ira_use_lra_p;
  30
  31 /* True if we have allocno conflicts.  It is false for non-optimized
  32    mode or when the conflict table is too big.  */
  33 extern bool ira_conflicts_p;
  34
  35 struct target_ira
  36 {
  37   /* Map: hard register number -> allocno class it belongs to.  If the
  38      corresponding class is NO_REGS, the hard register is not available
  39      for allocation.  */
  40   enum reg_class x_ira_hard_regno_allocno_class[FIRST_PSEUDO_REGISTER];
  41
  42   /* Number of allocno classes.  Allocno classes are register classes
  43      which can be used for allocations of allocnos.  */
  44   int x_ira_allocno_classes_num;
  45
  46   /* The array containing allocno classes.  Only first
  47      IRA_ALLOCNO_CLASSES_NUM elements are used for this.  */
  48   enum reg_class x_ira_allocno_classes[N_REG_CLASSES];
  49
  50   /* Map of all register classes to corresponding allocno classes
  51      containing the given class.  If given class is not a subset of an
  52      allocno class, we translate it into the cheapest allocno class.  */
  53   enum reg_class x_ira_allocno_class_translate[N_REG_CLASSES];
  54
  55   /* Number of pressure classes.  Pressure classes are register
  56      classes for which we calculate register pressure.  */
  57   int x_ira_pressure_classes_num;
  58
  59   /* The array containing pressure classes.  Only first
  60      IRA_PRESSURE_CLASSES_NUM elements are used for this.  */
  61   enum reg_class x_ira_pressure_classes[N_REG_CLASSES];
  62
  63   /* Map of all register classes to corresponding pressure classes
  64      containing the given class.  If given class is not a subset of an
  65      pressure class, we translate it into the cheapest pressure
  66      class.  */
  67   enum reg_class x_ira_pressure_class_translate[N_REG_CLASSES];
  68
  69   /* Biggest pressure register class containing stack registers.
  70      NO_REGS if there are no stack registers.  */
  71   enum reg_class x_ira_stack_reg_pressure_class;
  72
  73   /* Maps: register class x machine mode -> maximal/minimal number of
  74      hard registers of given class needed to store value of given
  75      mode.  */
  76   unsigned char x_ira_reg_class_max_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
  77   unsigned char x_ira_reg_class_min_nregs[N_REG_CLASSES][MAX_MACHINE_MODE];
  78
  79   /* Array analogous to target hook TARGET_MEMORY_MOVE_COST.  */
  80   short x_ira_memory_move_cost[MAX_MACHINE_MODE][N_REG_CLASSES][2];
  81
  82   /* Array of number of hard registers of given class which are
  83      available for the allocation.  The order is defined by the
  84      allocation order.  */
  85   short x_ira_class_hard_regs[N_REG_CLASSES][FIRST_PSEUDO_REGISTER];
  86
  87   /* The number of elements of the above array for given register
  88      class.  */
  89   int x_ira_class_hard_regs_num[N_REG_CLASSES];
  90
  91   /* Register class subset relation: TRUE if the first class is a subset
  92      of the second one considering only hard registers available for the
  93      allocation.  */
  94   int x_ira_class_subset_p[N_REG_CLASSES][N_REG_CLASSES];
  95
  96   /* The biggest class inside of intersection of the two classes (that
  97      is calculated taking only hard registers available for allocation
  98      into account.  If the both classes contain no hard registers
  99      available for allocation, the value is calculated with taking all
 100      hard-registers including fixed ones into account.  */
 101   enum reg_class x_ira_reg_class_subset[N_REG_CLASSES][N_REG_CLASSES];
 102
 103   /* True if the two classes (that is calculated taking only hard
 104      registers available for allocation into account; are
 105      intersected.  */
 106   bool x_ira_reg_classes_intersect_p[N_REG_CLASSES][N_REG_CLASSES];
 107
 108   /* If class CL has a single allocatable register of mode M,
 109      index [CL][M] gives the number of that register, otherwise it is -1.  */
 110   short x_ira_class_singleton[N_REG_CLASSES][MAX_MACHINE_MODE];
 111
 112   /* Function specific hard registers cannot be used for the register
 113      allocation.  */
 114   HARD_REG_SET x_ira_no_alloc_regs;
 115
 116   /* Array whose values are hard regset of hard registers available for
 117      the allocation of given register class whose targetm.hard_regno_mode_ok
 118      values for given mode are false.  */
 119   HARD_REG_SET x_ira_prohibited_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES];
 120
 121   /* When an allocatable hard register in given mode can not be placed in given
 122      register class, it is in the set of the following array element.  It can
 123      happen only when given mode requires more one hard register.  */
 124   HARD_REG_SET x_ira_exclude_class_mode_regs[N_REG_CLASSES][NUM_MACHINE_MODES];
 125 };
 126
 127 extern struct target_ira default_target_ira;
 128 #if SWITCHABLE_TARGET
 129 extern struct target_ira *this_target_ira;
 130 #else
 131 #define this_target_ira (&default_target_ira)
 132 #endif
 133
 134 #define ira_hard_regno_allocno_class \
 135   (this_target_ira->x_ira_hard_regno_allocno_class)
 136 #define ira_allocno_classes_num \
 137   (this_target_ira->x_ira_allocno_classes_num)
 138 #define ira_allocno_classes \
 139   (this_target_ira->x_ira_allocno_classes)
 140 #define ira_allocno_class_translate \
 141   (this_target_ira->x_ira_allocno_class_translate)
 142 #define ira_pressure_classes_num \
 143   (this_target_ira->x_ira_pressure_classes_num)
 144 #define ira_pressure_classes \
 145   (this_target_ira->x_ira_pressure_classes)
 146 #define ira_pressure_class_translate \
 147   (this_target_ira->x_ira_pressure_class_translate)
 148 #define ira_stack_reg_pressure_class \
 149   (this_target_ira->x_ira_stack_reg_pressure_class)
 150 #define ira_reg_class_max_nregs \
 151   (this_target_ira->x_ira_reg_class_max_nregs)
 152 #define ira_reg_class_min_nregs \
 153   (this_target_ira->x_ira_reg_class_min_nregs)
 154 #define ira_memory_move_cost \
 155   (this_target_ira->x_ira_memory_move_cost)
 156 #define ira_class_hard_regs \
 157   (this_target_ira->x_ira_class_hard_regs)
 158 #define ira_class_hard_regs_num \
 159   (this_target_ira->x_ira_class_hard_regs_num)
 160 #define ira_class_subset_p \
 161   (this_target_ira->x_ira_class_subset_p)
 162 #define ira_reg_class_subset \
 163   (this_target_ira->x_ira_reg_class_subset)
 164 #define ira_reg_classes_intersect_p \
 165   (this_target_ira->x_ira_reg_classes_intersect_p)
 166 #define ira_class_singleton \
 167   (this_target_ira->x_ira_class_singleton)
 168 #define ira_no_alloc_regs \
 169   (this_target_ira->x_ira_no_alloc_regs)
 170 #define ira_prohibited_class_mode_regs \
 171   (this_target_ira->x_ira_prohibited_class_mode_regs)
 172 #define ira_exclude_class_mode_regs \
 173   (this_target_ira->x_ira_exclude_class_mode_regs)
 174
 175 /* Major structure describing equivalence info for a pseudo.  */
 176 struct ira_reg_equiv_s
 177 {
 178   /* True if we can use this equivalence.  */
 179   bool defined_p;
 180   /* True if the usage of the equivalence is profitable.  */
 181   bool profitable_p;
 182   /* Equiv. memory, constant, invariant, and initializing insns of
 183      given pseudo-register or NULL_RTX.  */
 184   rtx memory;
 185   rtx constant;
 186   rtx invariant;
 187   /* Always NULL_RTX if defined_p is false.  */
 188   rtx_insn_list *init_insns;
 189 };
 190
 191 /* The length of the following array.  */
 192 extern int ira_reg_equiv_len;
 193
 194 /* Info about equiv. info for each register.  */
 195 extern struct ira_reg_equiv_s *ira_reg_equiv;
 196
 197 extern void ira_init_once (void);
 198 extern void ira_init (void);
 199 extern void ira_setup_eliminable_regset (void);
 200 extern rtx ira_eliminate_regs (rtx, machine_mode);
 201 extern void ira_set_pseudo_classes (bool, FILE *);
 202 extern void ira_expand_reg_equiv (void);
 203 extern void ira_update_equiv_info_by_shuffle_insn (int, int, rtx_insn *);
 204
 205 extern void ira_sort_regnos_for_alter_reg (int *, int, machine_mode *);
 206 extern void ira_mark_allocation_change (int);
 207 extern void ira_mark_memory_move_deletion (int, int);
 208 extern bool ira_reassign_pseudos (int *, int, HARD_REG_SET, HARD_REG_SET *,
 209                                   HARD_REG_SET *, bitmap);
 210 extern rtx ira_reuse_stack_slot (int, poly_uint64, poly_uint64);
 211 extern void ira_mark_new_stack_slot (rtx, int, poly_uint64);
 212 extern bool ira_better_spill_reload_regno_p (int *, int *, rtx, rtx, rtx_insn *);
 213 extern bool ira_bad_reload_regno (int, rtx, rtx);
 214
 215 extern void ira_adjust_equiv_reg_cost (unsigned, int);
 216
 217 extern bool ira_former_scratch_p (int regno);
 218 extern bool ira_former_scratch_operand_p (rtx_insn *insn, int nop);
 219 extern void ira_register_new_scratch_op (rtx_insn *insn, int nop, int icode);
 220 extern bool ira_remove_insn_scratches (rtx_insn *insn, bool all_p, FILE *dump_file,
 221                                        rtx (*get_reg) (rtx original));
 222 extern void ira_restore_scratches (FILE *dump_file);
 223 extern void ira_nullify_asm_goto (rtx_insn *insn);
 224
 225 /* ira-costs.cc */
 226 extern void ira_costs_cc_finalize (void);
 227
 228 /* ira-lives.cc */
 229 extern rtx non_conflicting_reg_copy_p (rtx_insn *);
 230
 231 /* Spilling static chain pseudo may result in generation of wrong
 232    non-local goto code using frame-pointer to address saved stack
 233    pointer value after restoring old frame pointer value.  The
 234    function returns TRUE if REGNO is such a static chain pseudo.  */
 235 static inline bool
 236 non_spilled_static_chain_regno_p (int regno)
 237 {
 238   return (cfun->static_chain_decl && crtl->has_nonlocal_goto
 239           && REG_EXPR (regno_reg_rtx[regno]) == cfun->static_chain_decl);
 240 }
 241
 242 #endif /* GCC_IRA_H */