7 #define NUM_CORE_STATES 4
9 int core_state_transition(unsigned char **instr
, unsigned long *transition_count
)
11 static unsigned long i
;
15 if (i
>= NUM_CORE_STATES
* 2)
18 return i
++ % NUM_CORE_STATES
;
21 unsigned int crcu32(unsigned long newval
, unsigned int crc
)
23 return (newval
>>16)+crc
;
26 #ifndef __SDCC_pdk14 // Lack of memory
27 unsigned int core_bench_state(unsigned long blksize
, unsigned char *memblock
, int seed2
, int step
, unsigned int crc
)
29 unsigned long final_counts
[NUM_CORE_STATES
];
30 unsigned long track_counts
[NUM_CORE_STATES
];
31 unsigned char *p
=memblock
;
34 for (i
=0; i
<NUM_CORE_STATES
; i
++) {
35 final_counts
[i
]=track_counts
[i
]=(1ul << 16) - 2 + i
;
41 int fstate
=core_state_transition(&p
,track_counts
);
42 final_counts
[fstate
]++; // Wrong code generated for increment here.
46 while (p
< (memblock
+blksize
)) {
48 *p
^=(unsigned char)seed2
;
52 for (i
=0; i
<NUM_CORE_STATES
; i
++) {
53 crc
=crcu32(final_counts
[i
],crc
);
54 crc
=crcu32(track_counts
[i
],crc
);
63 #ifndef __SDCC_pdk14 // Lack of memory
65 ASSERT(core_bench_state(0, &c
, 0x5a0a, 0x5a0a, 0) == 6);