sdcc/support/sdbinutils/include/opcode/arc.h

   1 /* Opcode table for the ARC.
   2    Copyright (C) 1994-2022 Free Software Foundation, Inc.
   3
   4    Contributed by Claudiu Zissulescu (claziss@synopsys.com)
   5
   6    This file is part of GAS, the GNU Assembler, GDB, the GNU debugger, and
   7    the GNU Binutils.
   8
   9    GAS/GDB is free software; you can redistribute it and/or modify
  10    it under the terms of the GNU General Public License as published by
  11    the Free Software Foundation; either version 3, or (at your option)
  12    any later version.
  13
  14    GAS/GDB is distributed in the hope that it will be useful,
  15    but WITHOUT ANY WARRANTY; without even the implied warranty of
  16    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  17    GNU General Public License for more details.
  18
  19    You should have received a copy of the GNU General Public License
  20    along with GAS or GDB; see the file COPYING3.  If not, write to
  21    the Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  22    MA 02110-1301, USA.  */
  23
  24 #ifndef OPCODE_ARC_H
  25 #define OPCODE_ARC_H
  26
  27 #ifdef __cplusplus
  28 extern "C" {
  29 #endif
  30
  31 #ifndef MAX_INSN_ARGS
  32 #define MAX_INSN_ARGS        16
  33 #endif
  34
  35 #ifndef MAX_INSN_FLGS
  36 #define MAX_INSN_FLGS        4
  37 #endif
  38
  39 /* Instruction Class.  */
  40 typedef enum
  41 {
  42   ACL,
  43   ARITH,
  44   AUXREG,
  45   BBIT0,
  46   BBIT1,
  47   BI,
  48   BIH,
  49   BITOP,
  50   BITSTREAM,
  51   BMU,
  52   BRANCH,
  53   BRCC,
  54   CONTROL,
  55   DIVREM,
  56   DMA,
  57   DPI,
  58   DSP,
  59   EI,
  60   ENTER,
  61   FLOAT,
  62   INVALID,
  63   JLI,
  64   JUMP,
  65   KERNEL,
  66   LEAVE,
  67   LLOCK,
  68   LOAD,
  69   LOGICAL,
  70   LOOP,
  71   MEMORY,
  72   MISC,
  73   MOVE,
  74   MPY,
  75   NET,
  76   PROTOCOL_DECODE,
  77   PMU,
  78   POP,
  79   PUSH,
  80   SCOND,
  81   SJLI,
  82   STORE,
  83   SUB,
  84   SWITCH,
  85   ULTRAIP,
  86   XY
  87 } insn_class_t;
  88
  89 /* Instruction Subclass.  */
  90 typedef enum
  91 {
  92   NONE     = 0,
  93   CVT      = (1U << 1),
  94   BTSCN    = (1U << 2),
  95   CD       = (1U << 3),
  96   CD1      = CD,
  97   CD2      = CD,
  98   COND     = (1U << 4),
  99   DIV      = (1U << 5),
 100   DP       = (1U << 6),
 101   DPA      = (1U << 7),
 102   DPX      = (1U << 8),
 103   FASTMATH = (1U << 23),
 104   LL64     = (1U << 9),
 105   MPY1E    = (1U << 10),
 106   MPY6E    = (1U << 11),
 107   MPY7E    = (1U << 12),
 108   MPY8E    = (1U << 13),
 109   MPY9E    = (1U << 14),
 110   NPS400   = (1U << 15),
 111   QUARKSE1 = (1U << 16),
 112   QUARKSE2 = (1U << 17),
 113   SHFT1    = (1U << 18),
 114   SHFT2    = (1U << 19),
 115   SWAP     = (1U << 20),
 116   SP       = (1U << 21),
 117   SPX      = (1U << 22)
 118 } insn_subclass_t;
 119
 120 /* Flags class.  */
 121 typedef enum
 122 {
 123   F_CLASS_NONE = 0,
 124
 125   /* At most one flag from the set of flags can appear in the
 126      instruction.  */
 127   F_CLASS_OPTIONAL = (1 << 0),
 128
 129   /* Exactly one from from the set of flags must appear in the
 130      instruction.  */
 131   F_CLASS_REQUIRED = (1 << 1),
 132
 133   /* The conditional code can be extended over the standard variants
 134      via .extCondCode pseudo-op.  */
 135   F_CLASS_EXTEND = (1 << 2),
 136
 137   /* Condition code flag.  */
 138   F_CLASS_COND = (1 << 3),
 139
 140   /* Write back mode.  */
 141   F_CLASS_WB = (1 << 4),
 142
 143   /* Data size.  */
 144   F_CLASS_ZZ = (1 << 5),
 145
 146   /* Implicit flag.  */
 147   F_CLASS_IMPLICIT = (1 << 6)
 148 } flag_class_t;
 149
 150 /* The opcode table is an array of struct arc_opcode.  */
 151 struct arc_opcode
 152 {
 153   /* The opcode name.  */
 154   const char * name;
 155
 156   /* The opcode itself.  Those bits which will be filled in with
 157      operands are zeroes.  */
 158   unsigned long long opcode;
 159
 160   /* The opcode mask.  This is used by the disassembler.  This is a
 161      mask containing ones indicating those bits which must match the
 162      opcode field, and zeroes indicating those bits which need not
 163      match (and are presumably filled in by operands).  */
 164   unsigned long long mask;
 165
 166   /* One bit flags for the opcode.  These are primarily used to
 167      indicate specific processors and environments support the
 168      instructions.  The defined values are listed below.  */
 169   unsigned cpu;
 170
 171   /* The instruction class.  This is used by gdb.  */
 172   insn_class_t insn_class;
 173
 174   /* The instruction subclass.  */
 175   insn_subclass_t subclass;
 176
 177   /* An array of operand codes.  Each code is an index into the
 178      operand table.  They appear in the order which the operands must
 179      appear in assembly code, and are terminated by a zero.  */
 180   unsigned char operands[MAX_INSN_ARGS + 1];
 181
 182   /* An array of flag codes.  Each code is an index into the flag
 183      table.  They appear in the order which the flags must appear in
 184      assembly code, and are terminated by a zero.  */
 185   unsigned char flags[MAX_INSN_FLGS + 1];
 186 };
 187
 188 /* The table itself is sorted by major opcode number, and is otherwise
 189    in the order in which the disassembler should consider
 190    instructions.  */
 191 extern const struct arc_opcode arc_opcodes[];
 192
 193 /* Return length of an instruction represented by OPCODE, in bytes.  */
 194 extern int arc_opcode_len (const struct arc_opcode *opcode);
 195
 196 /* CPU Availability.  */
 197 #define ARC_OPCODE_NONE     0x0000
 198 #define ARC_OPCODE_ARC600   0x0001  /* ARC 600 specific insns.  */
 199 #define ARC_OPCODE_ARC700   0x0002  /* ARC 700 specific insns.  */
 200 #define ARC_OPCODE_ARCv2EM  0x0004  /* ARCv2 EM specific insns.  */
 201 #define ARC_OPCODE_ARCv2HS  0x0008  /* ARCv2 HS specific insns.  */
 202
 203 /* CPU combi.  */
 204 #define ARC_OPCODE_ARCALL  (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700       \
 205                             | ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
 206 #define ARC_OPCODE_ARCFPX  (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCv2EM)
 207 #define ARC_OPCODE_ARCV1   (ARC_OPCODE_ARC600 | ARC_OPCODE_ARC700)
 208 #define ARC_OPCODE_ARCV2   (ARC_OPCODE_ARCv2EM | ARC_OPCODE_ARCv2HS)
 209 #define ARC_OPCODE_ARCMPY6E  (ARC_OPCODE_ARC700 | ARC_OPCODE_ARCV2)
 210
 211 /* The operands table is an array of struct arc_operand.  */
 212 struct arc_operand
 213 {
 214   /* The number of bits in the operand.  */
 215   unsigned int bits;
 216
 217   /* How far the operand is left shifted in the instruction.  */
 218   unsigned int shift;
 219
 220   /* The default relocation type for this operand.  */
 221   signed int default_reloc;
 222
 223   /* One bit syntax flags.  */
 224   unsigned int flags;
 225
 226   /* Insertion function.  This is used by the assembler.  To insert an
 227      operand value into an instruction, check this field.
 228
 229      If it is NULL, execute
 230          i |= (op & ((1 << o->bits) - 1)) << o->shift;
 231      (i is the instruction which we are filling in, o is a pointer to
 232      this structure, and op is the opcode value; this assumes twos
 233      complement arithmetic).
 234
 235      If this field is not NULL, then simply call it with the
 236      instruction and the operand value.  It will return the new value
 237      of the instruction.  If the ERRMSG argument is not NULL, then if
 238      the operand value is illegal, *ERRMSG will be set to a warning
 239      string (the operand will be inserted in any case).  If the
 240      operand value is legal, *ERRMSG will be unchanged (most operands
 241      can accept any value).  */
 242   unsigned long long (*insert) (unsigned long long instruction,
 243                                 long long int op,
 244                                 const char **errmsg);
 245
 246   /* Extraction function.  This is used by the disassembler.  To
 247      extract this operand type from an instruction, check this field.
 248
 249      If it is NULL, compute
 250          op = ((i) >> o->shift) & ((1 << o->bits) - 1);
 251          if ((o->flags & ARC_OPERAND_SIGNED) != 0
 252              && (op & (1 << (o->bits - 1))) != 0)
 253            op -= 1 << o->bits;
 254      (i is the instruction, o is a pointer to this structure, and op
 255      is the result; this assumes twos complement arithmetic).
 256
 257      If this field is not NULL, then simply call it with the
 258      instruction value.  It will return the value of the operand.  If
 259      the INVALID argument is not NULL, *INVALID will be set to
 260      TRUE if this operand type can not actually be extracted from
 261      this operand (i.e., the instruction does not match).  If the
 262      operand is valid, *INVALID will not be changed.  */
 263   long long int (*extract) (unsigned long long instruction, bool *invalid);
 264 };
 265
 266 /* Elements in the table are retrieved by indexing with values from
 267    the operands field of the arc_opcodes table.  */
 268 extern const struct arc_operand arc_operands[];
 269 extern const unsigned arc_num_operands;
 270 extern const unsigned arc_Toperand;
 271 extern const unsigned arc_NToperand;
 272
 273 /* Values defined for the flags field of a struct arc_operand.  */
 274
 275 /* This operand does not actually exist in the assembler input.  This
 276    is used to support extended mnemonics, for which two operands fields
 277    are identical.  The assembler should call the insert function with
 278    any op value.  The disassembler should call the extract function,
 279    ignore the return value, and check the value placed in the invalid
 280    argument.  */
 281 #define ARC_OPERAND_FAKE        0x0001
 282
 283 /* This operand names an integer register.  */
 284 #define ARC_OPERAND_IR          0x0002
 285
 286 /* This operand takes signed values.  */
 287 #define ARC_OPERAND_SIGNED      0x0004
 288
 289 /* This operand takes unsigned values.  This exists primarily so that
 290    a flags value of 0 can be treated as end-of-arguments.  */
 291 #define ARC_OPERAND_UNSIGNED    0x0008
 292
 293 /* This operand takes long immediate values.  */
 294 #define ARC_OPERAND_LIMM        0x0010
 295
 296 /* This operand is identical like the previous one.  */
 297 #define ARC_OPERAND_DUPLICATE   0x0020
 298
 299 /* This operand is PC relative.  Used for internal relocs.  */
 300 #define ARC_OPERAND_PCREL       0x0040
 301
 302 /* This operand is truncated.  The truncation is done accordingly to
 303    operand alignment attribute.  */
 304 #define ARC_OPERAND_TRUNCATE    0x0080
 305
 306 /* This operand is 16bit aligned.  */
 307 #define ARC_OPERAND_ALIGNED16   0x0100
 308
 309 /* This operand is 32bit aligned.  */
 310 #define ARC_OPERAND_ALIGNED32   0x0200
 311
 312 /* This operand can be ignored by matching process if it is not
 313    present.  */
 314 #define ARC_OPERAND_IGNORE      0x0400
 315
 316 /* Don't check the range when matching.  */
 317 #define ARC_OPERAND_NCHK        0x0800
 318
 319 /* Mark the braket possition.  */
 320 #define ARC_OPERAND_BRAKET      0x1000
 321
 322 /* Address type operand for NPS400.  */
 323 #define ARC_OPERAND_ADDRTYPE    0x2000
 324
 325 /* Mark the colon position.  */
 326 #define ARC_OPERAND_COLON       0x4000
 327
 328 /* Mask for selecting the type for typecheck purposes.  */
 329 #define ARC_OPERAND_TYPECHECK_MASK               \
 330   (ARC_OPERAND_IR                                \
 331    | ARC_OPERAND_LIMM     | ARC_OPERAND_SIGNED   \
 332    | ARC_OPERAND_UNSIGNED | ARC_OPERAND_BRAKET   \
 333    | ARC_OPERAND_ADDRTYPE | ARC_OPERAND_COLON)
 334
 335 /* Macro to determine if an operand is a fake operand.  */
 336 #define ARC_OPERAND_IS_FAKE(op)                     \
 337   ((operand->flags & ARC_OPERAND_FAKE)              \
 338    && !((operand->flags & ARC_OPERAND_BRAKET)       \
 339         || (operand->flags & ARC_OPERAND_COLON)))
 340
 341 /* The flags structure.  */
 342 struct arc_flag_operand
 343 {
 344   /* The flag name.  */
 345   const char * name;
 346
 347   /* The flag code.  */
 348   unsigned code;
 349
 350   /* The number of bits in the operand.  */
 351   unsigned int bits;
 352
 353   /* How far the operand is left shifted in the instruction.  */
 354   unsigned int shift;
 355
 356   /* Available for disassembler.  */
 357   unsigned char favail;
 358 };
 359
 360 /* The flag operands table.  */
 361 extern const struct arc_flag_operand arc_flag_operands[];
 362 extern const unsigned arc_num_flag_operands;
 363
 364 /* The flag's class structure.  */
 365 struct arc_flag_class
 366 {
 367   /* Flag class.  */
 368   flag_class_t flag_class;
 369
 370   /* List of valid flags (codes).  */
 371   unsigned flags[256];
 372 };
 373
 374 extern const struct arc_flag_class arc_flag_classes[];
 375
 376 /* Structure for special cases.  */
 377 struct arc_flag_special
 378 {
 379   /* Name of special case instruction.  */
 380   const char *name;
 381
 382   /* List of flags applicable for special case instruction.  */
 383   unsigned flags[32];
 384 };
 385
 386 extern const struct arc_flag_special arc_flag_special_cases[];
 387 extern const unsigned arc_num_flag_special;
 388
 389 /* Relocation equivalence structure.  */
 390 struct arc_reloc_equiv_tab
 391 {
 392   const char * name;       /* String to lookup.  */
 393   const char * mnemonic;   /* Extra matching condition.  */
 394   unsigned     flags[32];  /* Extra matching condition.  */
 395   signed int   oldreloc;   /* Old relocation.  */
 396   signed int   newreloc;   /* New relocation.  */
 397 };
 398
 399 extern const struct arc_reloc_equiv_tab arc_reloc_equiv[];
 400 extern const unsigned arc_num_equiv_tab;
 401
 402 /* Structure for operand operations for pseudo/alias instructions.  */
 403 struct arc_operand_operation
 404 {
 405   /* The index for operand from operand array.  */
 406   unsigned operand_idx;
 407
 408   /* Defines if it needs the operand inserted by the assembler or
 409      whether this operand comes from the pseudo instruction's
 410      operands.  */
 411   unsigned char needs_insert;
 412
 413   /* Count we have to add to the operand.  Use negative number to
 414      subtract from the operand.  Also use this number to add to 0 if
 415      the operand needs to be inserted (i.e. needs_insert == 1).  */
 416   int count;
 417
 418   /* Index of the operand to swap with.  To be done AFTER applying
 419      inc_count.  */
 420   unsigned swap_operand_idx;
 421 };
 422
 423 /* Structure for pseudo/alias instructions.  */
 424 struct arc_pseudo_insn
 425 {
 426   /* Mnemonic for pseudo/alias insn.  */
 427   const char * mnemonic_p;
 428
 429   /* Mnemonic for real instruction.  */
 430   const char * mnemonic_r;
 431
 432   /* Flag that will have to be added (if any).  */
 433   const char * flag_r;
 434
 435   /* Amount of operands.  */
 436   unsigned operand_cnt;
 437
 438   /* Array of operand operations.  */
 439   struct arc_operand_operation operand[6];
 440 };
 441
 442 extern const struct arc_pseudo_insn arc_pseudo_insns[];
 443 extern const unsigned arc_num_pseudo_insn;
 444
 445 /* Structure for AUXILIARY registers.  */
 446 struct arc_aux_reg
 447 {
 448   /* Register address.  */
 449   int address;
 450
 451   /* One bit flags for the opcode.  These are primarily used to
 452      indicate specific processors and environments support the
 453      instructions.  */
 454   unsigned cpu;
 455
 456   /* AUX register subclass.  */
 457   insn_subclass_t subclass;
 458
 459   /* Register name.  */
 460   const char * name;
 461
 462   /* Size of the string.  */
 463   size_t length;
 464 };
 465
 466 extern const struct arc_aux_reg arc_aux_regs[];
 467 extern const unsigned arc_num_aux_regs;
 468
 469 extern const struct arc_opcode arc_relax_opcodes[];
 470 extern const unsigned arc_num_relax_opcodes;
 471
 472 /* Macro used for generating one class of NPS instructions.  */
 473 #define NPS_CMEM_HIGH_VALUE 0x57f0
 474
 475 /* Macros to help generating regular pattern instructions.  */
 476 #define FIELDA(word) (word & 0x3F)
 477 #define FIELDB(word) (((word & 0x07) << 24) | (((word >> 3) & 0x07) << 12))
 478 #define FIELDC(word) ((word & 0x3F) << 6)
 479 #define FIELDF       (0x01 << 15)
 480 #define FIELDQ       (0x1F)
 481
 482 #define INSN3OP(MOP,SOP)        (((MOP & 0x1F) << 27) | ((SOP & 0x3F) << 16))
 483 #define INSN2OPX(MOP,SOP1,SOP2) (INSN3OP (MOP,SOP1) | (SOP2 & 0x3F))
 484 #define INSN2OP(MOP,SOP)        (INSN2OPX (MOP,0x2F,SOP))
 485
 486 #define INSN3OP_ABC(MOP,SOP)  (INSN3OP (MOP,SOP))
 487 #define INSN3OP_ALC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62))
 488 #define INSN3OP_ABL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDC (62))
 489 #define INSN3OP_ALL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDB (62) | FIELDC (62))
 490 #define INSN3OP_0BC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62))
 491 #define INSN3OP_0LC(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62))
 492 #define INSN3OP_0BL(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDC (62))
 493 #define INSN3OP_0LL(MOP,SOP)                                    \
 494   (INSN3OP (MOP,SOP) | FIELDA (62) | FIELDB (62) | FIELDC (62))
 495 #define INSN3OP_ABU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22))
 496 #define INSN3OP_ALU(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
 497 #define INSN3OP_0BU(MOP,SOP)  (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22))
 498 #define INSN3OP_0LU(MOP,SOP)                                    \
 499   (INSN3OP (MOP,SOP) | FIELDA (62) | (0x01 << 22) | FIELDB (62))
 500 #define INSN3OP_BBS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22))
 501 #define INSN3OP_0LS(MOP,SOP)  (INSN3OP (MOP,SOP) | (0x02 << 22) | FIELDB (62))
 502 #define INSN3OP_CBBC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22))
 503 #define INSN3OP_CBBL(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62))
 504 #define INSN3OP_C0LC(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDB (62))
 505 #define INSN3OP_C0LL(MOP,SOP)                                   \
 506   (INSN3OP (MOP,SOP) | (0x03 << 22) | FIELDC (62) | FIELDB (62))
 507 #define INSN3OP_CBBU(MOP,SOP) (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5))
 508 #define INSN3OP_C0LU(MOP,SOP)                                   \
 509   (INSN3OP (MOP,SOP) | (0x03 << 22) | (0x01 << 5) | FIELDB (62))
 510
 511 #define MASK_32BIT(VAL) (0xffffffff & (VAL))
 512
 513 #define MINSN3OP_ABC  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
 514 #define MINSN3OP_ALC  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
 515 #define MINSN3OP_ABL  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63))))
 516 #define MINSN3OP_ALL  (MASK_32BIT (~(FIELDF | FIELDA (63))))
 517 #define MINSN3OP_0BC  (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
 518 #define MINSN3OP_0LC  (MASK_32BIT (~(FIELDF | FIELDC (63))))
 519 #define MINSN3OP_0BL  (MASK_32BIT (~(FIELDF | FIELDB (63))))
 520 #define MINSN3OP_0LL  (MASK_32BIT (~(FIELDF)))
 521 #define MINSN3OP_ABU  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
 522 #define MINSN3OP_ALU  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
 523 #define MINSN3OP_0BU  (MASK_32BIT (~(FIELDF | FIELDB (63) | FIELDC (63))))
 524 #define MINSN3OP_0LU  (MASK_32BIT (~(FIELDF | FIELDC (63))))
 525 #define MINSN3OP_BBS  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDB (63) | FIELDC (63))))
 526 #define MINSN3OP_0LS  (MASK_32BIT (~(FIELDF | FIELDA (63) | FIELDC (63))))
 527 #define MINSN3OP_CBBC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
 528 #define MINSN3OP_CBBL (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63))))
 529 #define MINSN3OP_C0LC (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
 530 #define MINSN3OP_C0LL (MASK_32BIT (~(FIELDF | FIELDQ)))
 531 #define MINSN3OP_CBBU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDB (63) | FIELDC (63))))
 532 #define MINSN3OP_C0LU (MASK_32BIT (~(FIELDF | FIELDQ | FIELDC (63))))
 533
 534 #define INSN2OP_BC(MOP,SOP) (INSN2OP (MOP,SOP))
 535 #define INSN2OP_BL(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDC (62))
 536 #define INSN2OP_0C(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62))
 537 #define INSN2OP_0L(MOP,SOP) (INSN2OP (MOP,SOP) | FIELDB (62)  | FIELDC (62))
 538 #define INSN2OP_BU(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22))
 539 #define INSN2OP_0U(MOP,SOP) (INSN2OP (MOP,SOP) | (0x01 << 22) | FIELDB (62))
 540
 541 #define MINSN2OP_BC  (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
 542 #define MINSN2OP_BL  (MASK_32BIT ((~(FIELDF | FIELDB (63)))))
 543 #define MINSN2OP_0C  (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
 544 #define MINSN2OP_0L  (MASK_32BIT ((~(FIELDF))))
 545 #define MINSN2OP_BU  (MASK_32BIT ((~(FIELDF | FIELDB (63) | FIELDC (63)))))
 546 #define MINSN2OP_0U  (MASK_32BIT ((~(FIELDF | FIELDC (63)))))
 547
 548 /* Various constants used when defining an extension instruction.  */
 549 #define ARC_SYNTAX_3OP          (1 << 0)
 550 #define ARC_SYNTAX_2OP          (1 << 1)
 551 #define ARC_SYNTAX_1OP          (1 << 2)
 552 #define ARC_SYNTAX_NOP          (1 << 3)
 553 #define ARC_SYNTAX_MASK         (0x0F)
 554
 555 #define ARC_OP1_MUST_BE_IMM     (1 << 0)
 556 #define ARC_OP1_IMM_IMPLIED     (1 << 1)
 557
 558 #define ARC_SUFFIX_NONE         (1 << 0)
 559 #define ARC_SUFFIX_COND         (1 << 1)
 560 #define ARC_SUFFIX_FLAG         (1 << 2)
 561
 562 #define ARC_REGISTER_READONLY    (1 << 0)
 563 #define ARC_REGISTER_WRITEONLY   (1 << 1)
 564 #define ARC_REGISTER_NOSHORT_CUT (1 << 2)
 565
 566 /* Constants needed to initialize extension instructions.  */
 567 extern const unsigned char flags_none[MAX_INSN_FLGS + 1];
 568 extern const unsigned char flags_f[MAX_INSN_FLGS + 1];
 569 extern const unsigned char flags_cc[MAX_INSN_FLGS + 1];
 570 extern const unsigned char flags_ccf[MAX_INSN_FLGS + 1];
 571
 572 extern const unsigned char arg_none[MAX_INSN_ARGS + 1];
 573 extern const unsigned char arg_32bit_rarbrc[MAX_INSN_ARGS + 1];
 574 extern const unsigned char arg_32bit_zarbrc[MAX_INSN_ARGS + 1];
 575 extern const unsigned char arg_32bit_rbrbrc[MAX_INSN_ARGS + 1];
 576 extern const unsigned char arg_32bit_rarbu6[MAX_INSN_ARGS + 1];
 577 extern const unsigned char arg_32bit_zarbu6[MAX_INSN_ARGS + 1];
 578 extern const unsigned char arg_32bit_rbrbu6[MAX_INSN_ARGS + 1];
 579 extern const unsigned char arg_32bit_rbrbs12[MAX_INSN_ARGS + 1];
 580 extern const unsigned char arg_32bit_ralimmrc[MAX_INSN_ARGS + 1];
 581 extern const unsigned char arg_32bit_rarblimm[MAX_INSN_ARGS + 1];
 582 extern const unsigned char arg_32bit_zalimmrc[MAX_INSN_ARGS + 1];
 583 extern const unsigned char arg_32bit_zarblimm[MAX_INSN_ARGS + 1];
 584
 585 extern const unsigned char arg_32bit_rbrblimm[MAX_INSN_ARGS + 1];
 586 extern const unsigned char arg_32bit_ralimmu6[MAX_INSN_ARGS + 1];
 587 extern const unsigned char arg_32bit_zalimmu6[MAX_INSN_ARGS + 1];
 588
 589 extern const unsigned char arg_32bit_zalimms12[MAX_INSN_ARGS + 1];
 590 extern const unsigned char arg_32bit_ralimmlimm[MAX_INSN_ARGS + 1];
 591 extern const unsigned char arg_32bit_zalimmlimm[MAX_INSN_ARGS + 1];
 592
 593 extern const unsigned char arg_32bit_rbrc[MAX_INSN_ARGS + 1];
 594 extern const unsigned char arg_32bit_zarc[MAX_INSN_ARGS + 1];
 595 extern const unsigned char arg_32bit_rbu6[MAX_INSN_ARGS + 1];
 596 extern const unsigned char arg_32bit_zau6[MAX_INSN_ARGS + 1];
 597 extern const unsigned char arg_32bit_rblimm[MAX_INSN_ARGS + 1];
 598 extern const unsigned char arg_32bit_zalimm[MAX_INSN_ARGS + 1];
 599
 600 extern const unsigned char arg_32bit_limmrc[MAX_INSN_ARGS + 1];
 601 extern const unsigned char arg_32bit_limmu6[MAX_INSN_ARGS + 1];
 602 extern const unsigned char arg_32bit_limms12[MAX_INSN_ARGS + 1];
 603 extern const unsigned char arg_32bit_limmlimm[MAX_INSN_ARGS + 1];
 604
 605 extern const unsigned char arg_32bit_rc[MAX_INSN_ARGS + 1];
 606 extern const unsigned char arg_32bit_u6[MAX_INSN_ARGS + 1];
 607 extern const unsigned char arg_32bit_limm[MAX_INSN_ARGS + 1];
 608
 609 /* Address types used in the NPS-400. See page 367 of the NPS-400 CTOP
 610    Instruction Set Reference Manual v2.4 for a description of address types.  */
 611
 612 typedef enum
 613 {
 614   /* Addresses in memory.  */
 615
 616   /* Buffer descriptor.  */
 617   ARC_NPS400_ADDRTYPE_BD,
 618
 619   /* Job identifier.  */
 620   ARC_NPS400_ADDRTYPE_JID,
 621
 622   /* Linked Buffer Descriptor.  */
 623   ARC_NPS400_ADDRTYPE_LBD,
 624
 625   /* Multicast Buffer Descriptor.  */
 626   ARC_NPS400_ADDRTYPE_MBD,
 627
 628   /* Summarized Address.  */
 629   ARC_NPS400_ADDRTYPE_SD,
 630
 631   /* SMEM Security Context Local Memory.  */
 632   ARC_NPS400_ADDRTYPE_SM,
 633
 634   /* Extended Address.  */
 635   ARC_NPS400_ADDRTYPE_XA,
 636
 637   /* Extended Summarized Address.  */
 638   ARC_NPS400_ADDRTYPE_XD,
 639
 640   /* CMEM offset addresses.  */
 641
 642   /* On-demand Counter Descriptor.  */
 643   ARC_NPS400_ADDRTYPE_CD,
 644
 645   /* CMEM Buffer Descriptor.  */
 646   ARC_NPS400_ADDRTYPE_CBD,
 647
 648   /* CMEM Job Identifier.  */
 649   ARC_NPS400_ADDRTYPE_CJID,
 650
 651   /* CMEM Linked Buffer Descriptor.  */
 652   ARC_NPS400_ADDRTYPE_CLBD,
 653
 654   /* CMEM Offset.  */
 655   ARC_NPS400_ADDRTYPE_CM,
 656
 657   /* CMEM Summarized Address.  */
 658   ARC_NPS400_ADDRTYPE_CSD,
 659
 660   /* CMEM Extended Address.  */
 661   ARC_NPS400_ADDRTYPE_CXA,
 662
 663   /* CMEM Extended Summarized Address.  */
 664   ARC_NPS400_ADDRTYPE_CXD
 665
 666 } arc_nps_address_type;
 667
 668 #define ARC_NUM_ADDRTYPES 16
 669
 670 #ifdef __cplusplus
 671 }
 672 #endif
 673
 674 #endif /* OPCODE_ARC_H */