sdcc/support/sdbinutils/include/opcode/d30v.h

   1 /* d30v.h -- Header file for D30V opcode table
   2    Copyright (C) 1997-2022 Free Software Foundation, Inc.
   3    Written by Martin Hunt (hunt@cygnus.com), Cygnus Solutions
   4
   5    This file is part of GDB, GAS, and the GNU binutils.
   6
   7    GDB, GAS, and the GNU binutils are free software; you can redistribute
   8    them and/or modify them under the terms of the GNU General Public
   9    License as published by the Free Software Foundation; either version 3,
  10    or (at your option) any later version.
  11
  12    GDB, GAS, and the GNU binutils are distributed in the hope that they
  13    will be useful, but WITHOUT ANY WARRANTY; without even the implied
  14    warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See
  15    the GNU General Public License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING3.  If not, write to the Free
  19    Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA.  */
  21
  22 #ifndef D30V_H
  23 #define D30V_H
  24
  25 #ifdef __cplusplus
  26 extern "C" {
  27 #endif
  28
  29 #define NOP 0x00F00000
  30
  31 /* Structure to hold information about predefined registers.  */
  32 struct pd_reg
  33 {
  34   char *name;           /* name to recognize */
  35   char *pname;          /* name to print for this register */
  36   unsigned int value;
  37 };
  38
  39 extern const struct pd_reg pre_defined_registers[];
  40 int reg_name_cnt (void);
  41
  42 /* the number of control registers */
  43 #define MAX_CONTROL_REG 64
  44
  45 /* define the format specifiers */
  46 #define FM00    0
  47 #define FM01    0x80000000
  48 #define FM10    0x8000000000000000LL
  49 #define FM11    0x8000000080000000LL
  50
  51 /* define the opcode classes */
  52 #define BRA     0
  53 #define LOGIC   1
  54 #define IMEM    2
  55 #define IALU1   4
  56 #define IALU2   5
  57
  58 /* define the execution condition codes */
  59 #define ECC_AL  0       /* ALways (default) */
  60 #define ECC_TX  1       /* F0=True, F1=Don't care */
  61 #define ECC_FX  2       /* F0=False, F1=Don't care */
  62 #define ECC_XT  3       /* F0=Don't care, F1=True */
  63 #define ECC_XF  4       /* F0=Don't care, F1=False */
  64 #define ECC_TT  5       /* F0=True, F1=True */
  65 #define ECC_TF  6       /* F0=True, F1=False */
  66 #define ECC_RESERVED    7       /* reserved */
  67 #define ECC_MAX ECC_RESERVED
  68
  69 extern const char *d30v_ecc_names[];
  70
  71 /* condition code table for CMP and CMPU */
  72 extern const char *d30v_cc_names[];
  73
  74 /* The opcode table is an array of struct d30v_opcode.  */
  75 struct d30v_opcode
  76 {
  77   /* The opcode name.  */
  78   const char *name;
  79
  80   /* the opcode */
  81   int op1;      /* first part, "IALU1" for example */
  82   int op2;      /* the rest of the opcode */
  83
  84   /* opcode format(s).  These numbers correspond to entries */
  85   /* in the d30v_format_table */
  86   unsigned char format[4];
  87
  88 #define SHORT_M         1
  89 #define SHORT_M2        5       /* for ld2w and st2w */
  90 #define SHORT_A         9
  91 #define SHORT_B1        11
  92 #define SHORT_B2        12
  93 #define SHORT_B2r     13
  94 #define SHORT_B3      14
  95 #define SHORT_B3r     16
  96 #define SHORT_B3b     18
  97 #define SHORT_B3br    20
  98 #define SHORT_D1r     22
  99 #define SHORT_D2      24
 100 #define SHORT_D2r     26
 101 #define SHORT_D2Br    28
 102 #define SHORT_U       30      /* unary SHORT_A.  ABS for example */
 103 #define SHORT_F       31      /* SHORT_A with flag registers */
 104 #define SHORT_AF      33      /* SHORT_A with only the first register a flag register */
 105 #define SHORT_T       35      /* for trap instruction */
 106 #define SHORT_A5      36      /* SHORT_A with a 5-bit immediate instead of 6 */
 107 #define SHORT_CMP     38      /* special form for CMPcc */
 108 #define SHORT_CMPU    40      /* special form for CMPUcc */
 109 #define SHORT_A1      42      /* special form of SHORT_A for MACa opcodes where a=1 */
 110 #define SHORT_AA      44      /* SHORT_A with the first register an accumulator */
 111 #define SHORT_RA      46      /* SHORT_A with the second register an accumulator */
 112 #define SHORT_MODINC  48
 113 #define SHORT_MODDEC  49
 114 #define SHORT_C1      50
 115 #define SHORT_C2      51
 116 #define SHORT_UF      52
 117 #define SHORT_A2      53
 118 #define SHORT_NONE    55      /* no operands */
 119 #define SHORT_AR      56      /* like SHORT_AA but only accept register as third parameter  */
 120 #define LONG          57
 121 #define LONG_U        58      /* unary LONG */
 122 #define LONG_Ur       59      /* LONG pc-relative */
 123 #define LONG_CMP      60      /* special form for CMPcc and CMPUcc */
 124 #define LONG_M        61      /* Memory long for ldb, stb */
 125 #define LONG_M2       62      /* Memory long for ld2w, st2w */
 126 #define LONG_2        63      /* LONG with 2 operands; jmptnz */
 127 #define LONG_2r       64      /* LONG with 2 operands; bratnz */
 128 #define LONG_2b       65      /* LONG_2 with modifier of 3 */
 129 #define LONG_2br      66      /* LONG_2r with modifier of 3 */
 130 #define LONG_D        67      /* for DJMPI */
 131 #define LONG_Dr       68      /* for DBRAI */
 132 #define LONG_Dbr      69      /* for repeati */
 133
 134   /* the execution unit(s) used */
 135   int unit;
 136 #define EITHER  0
 137 #define IU      1
 138 #define MU      2
 139 #define EITHER_BUT_PREFER_MU 3
 140
 141   /* this field is used to decide if two instructions */
 142   /* can be executed in parallel */
 143   long flags_used;
 144   long flags_set;
 145 #define FLAG_0          (1L<<0)
 146 #define FLAG_1          (1L<<1)
 147 #define FLAG_2          (1L<<2)
 148 #define FLAG_3          (1L<<3)
 149 #define FLAG_4          (1L<<4)         /* S (saturation) */
 150 #define FLAG_5          (1L<<5)         /* V (overflow) */
 151 #define FLAG_6          (1L<<6)         /* VA (accumulated overflow) */
 152 #define FLAG_7          (1L<<7)         /* C (carry/borrow) */
 153 #define FLAG_SM         (1L<<8)         /* SM (stack mode) */
 154 #define FLAG_RP         (1L<<9)         /* RP (repeat enable) */
 155 #define FLAG_CONTROL    (1L<<10)        /* control registers */
 156 #define FLAG_A0         (1L<<11)        /* A0 */
 157 #define FLAG_A1         (1L<<12)        /* A1 */
 158 #define FLAG_JMP        (1L<<13)        /* instruction is a branch */
 159 #define FLAG_JSR        (1L<<14)        /* subroutine call.  must be aligned */
 160 #define FLAG_MEM        (1L<<15)        /* reads/writes memory */
 161 #define FLAG_NOT_WITH_ADDSUBppp  (1L<<16) /* Old meaning: a 2 word 4 byter operation
 162                                            New meaning: operation cannot be
 163                                            combined in parallel with ADD/SUBppp. */
 164 #define FLAG_MUL16      (1L<<17)        /* 16 bit multiply */
 165 #define FLAG_MUL32      (1L<<18)        /* 32 bit multiply */
 166 #define FLAG_ADDSUBppp  (1L<<19)        /* ADDppp or SUBppp */
 167 #define FLAG_DELAY      (1L<<20)        /* This is a delayed branch or jump */
 168 #define FLAG_LKR        (1L<<21)        /* insn in left slot kills right slot */
 169 #define FLAG_CVVA       (FLAG_5|FLAG_6|FLAG_7)
 170 #define FLAG_C          FLAG_7
 171 #define FLAG_ALL        (FLAG_0 | \
 172                          FLAG_1 | \
 173                          FLAG_2 | \
 174                          FLAG_3 | \
 175                          FLAG_4 | \
 176                          FLAG_5 | \
 177                          FLAG_6 | \
 178                          FLAG_7 | \
 179                          FLAG_SM | \
 180                          FLAG_RP | \
 181                          FLAG_CONTROL)
 182
 183   int reloc_flag;
 184 #define RELOC_PCREL     1
 185 #define RELOC_ABS       2
 186 };
 187
 188 extern const struct d30v_opcode d30v_opcode_table[];
 189 extern const int d30v_num_opcodes;
 190
 191 /* The operands table is an array of struct d30v_operand.  */
 192 struct d30v_operand
 193 {
 194   /* the length of the field */
 195   int length;
 196
 197   /* The number of significant bits in the operand.  */
 198   int bits;
 199
 200   /* position relative to Ra */
 201   int position;
 202
 203   /* syntax flags.  */
 204   long flags;
 205 };
 206 extern const struct d30v_operand d30v_operand_table[];
 207
 208 /* Values defined for the flags field of a struct d30v_operand.  */
 209
 210 /* this is the destination register; it will be modified */
 211 /* this is used by the optimizer */
 212 #define OPERAND_DEST    (1)
 213
 214 /* number or symbol */
 215 #define OPERAND_NUM     (2)
 216
 217 /* address or label */
 218 #define OPERAND_ADDR    (4)
 219
 220 /* register */
 221 #define OPERAND_REG     (8)
 222
 223 /* postincrement +  */
 224 #define OPERAND_PLUS    (0x10)
 225
 226 /* postdecrement -  */
 227 #define OPERAND_MINUS   (0x20)
 228
 229 /* signed number */
 230 #define OPERAND_SIGNED  (0x40)
 231
 232 /* this operand must be shifted left by 3 */
 233 #define OPERAND_SHIFT   (0x80)
 234
 235 /* flag register */
 236 #define OPERAND_FLAG    (0x100)
 237
 238 /* control register  */
 239 #define OPERAND_CONTROL (0x200)
 240
 241 /* accumulator */
 242 #define OPERAND_ACC     (0x400)
 243
 244 /* @  */
 245 #define OPERAND_ATSIGN  (0x800)
 246
 247 /* @(  */
 248 #define OPERAND_ATPAR   (0x1000)
 249
 250 /* predecrement mode '@-sp'  */
 251 #define OPERAND_ATMINUS (0x2000)
 252
 253 /* this operand changes the instruction name */
 254 /* for example, CPMcc, CMPUcc */
 255 #define OPERAND_NAME    (0x4000)
 256
 257 /* fake operand for mvtsys and mvfsys */
 258 #define OPERAND_SPECIAL (0x8000)
 259
 260 /* let the optimizer know that two registers are affected */
 261 #define OPERAND_2REG    (0x10000)
 262
 263 /* This operand is pc-relative.  Note that repeati can have two immediate
 264    operands, one of which is pcrel, the other (the IMM6U one) is not.  */
 265 #define OPERAND_PCREL   (0x20000)
 266
 267 /* The format table is an array of struct d30v_format.  */
 268 struct d30v_format
 269 {
 270   int   form;           /* SHORT_A, LONG, etc */
 271   int   modifier;       /* two bit modifier following opcode */
 272   unsigned char operands[5];
 273 };
 274 extern const struct d30v_format d30v_format_table[];
 275
 276
 277 /* an instruction is defined by an opcode and a format */
 278 /* for example, "add" has one opcode, but three different */
 279 /* formats, 2 SHORT_A forms and a LONG form. */
 280 struct d30v_insn
 281 {
 282   struct d30v_opcode *op;       /* pointer to an entry in the opcode table */
 283   struct d30v_format *form;     /* pointer to an entry in the format table */
 284   int ecc;                      /* execution condition code */
 285 };
 286
 287 /* an expressionS only has one register type, so we fake it */
 288 /* by setting high bits to indicate type */
 289 #define REGISTER_MASK   0xFF
 290
 291 #ifdef __cplusplus
 292 }
 293 #endif
 294
 295 #endif /* D30V_H */