sdcc/support/sdbinutils/include/opcode/msp430.h

   1 /* Opcode table for the TI MSP430 microcontrollers
   2
   3    Copyright (C) 2002-2022 Free Software Foundation, Inc.
   4    Contributed by Dmitry Diky <diwil@mail.ru>
   5
   6    This program is free software; you can redistribute it and/or modify
   7    it under the terms of the GNU General Public License as published by
   8    the Free Software Foundation; either version 3, or (at your option)
   9    any later version.
  10
  11    This program is distributed in the hope that it will be useful,
  12    but WITHOUT ANY WARRANTY; without even the implied warranty of
  13    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
  14    GNU General Public License for more details.
  15
  16    You should have received a copy of the GNU General Public License
  17    along with this program; if not, write to the Free Software
  18    Foundation, Inc., 51 Franklin Street - Fifth Floor, Boston,
  19    MA 02110-1301, USA.  */
  20
  21 #ifndef __MSP430_H_
  22 #define __MSP430_H_
  23
  24 enum msp430_expp_e
  25 {
  26   MSP_EXPP_ALL = 0,     /* Use full the value of the expression - default.  */
  27   MSP_EXPP_LO,          /* Extract least significant word from expression.  */
  28   MSP_EXPP_HI,          /* Extract 2nd word from expression.  */
  29   MSP_EXPP_LLO,         /* Extract least significant word from an
  30                            immediate value.  */
  31   MSP_EXPP_LHI,         /* Extract 2nd word from an immediate value.  */
  32   MSP_EXPP_HLO,         /* Extract 3rd word from an immediate value.  */
  33   MSP_EXPP_HHI,         /* Extract 4th word from an immediate value.  */
  34 };
  35
  36 struct msp430_operand_s
  37 {
  38   int ol;       /* Operand length words.  */
  39   int am;       /* Addr mode.  */
  40   int reg;      /* Register.  */
  41   int mode;     /* Operand mode.  */
  42   int vshift;   /* Number of bytes to shift operand down.  */
  43   enum msp430_expp_e expp;      /* For when the operand is a constant
  44                                    expression, the part of the expression to
  45                                    extract.  */
  46 #define OP_REG          0
  47 #define OP_EXP          1
  48 #ifndef DASM_SECTION
  49   expressionS   exp;
  50 #endif
  51 };
  52
  53 /* Byte operation flag for all instructions.  Also used as the
  54    A/L bit in the extension word to indicate a 20-bit operation.  */
  55 #define BYTE_OPERATION    (1 << 6)
  56 /* Z/C bit in the extension word.  If set the carry bit is ignored
  57    for the duration of the operation, although it may be changed as
  58    a result of the operation.  */
  59 #define IGNORE_CARRY_BIT  (1 << 8)
  60
  61 struct  msp430_opcode_s
  62 {
  63   const char *name;
  64   int fmt;
  65   int insn_opnumb;
  66   int bin_opcode;
  67   int bin_mask;
  68 };
  69
  70 #define MSP_INSN(name, fmt, numb, bin, mask) { #name, fmt, numb, bin, mask }
  71
  72 static struct msp430_opcode_s msp430_opcodes[] =
  73 {
  74   MSP_INSN (and,   1, 2, 0xf000, 0xf000),
  75   MSP_INSN (inv,   0, 1, 0xe330, 0xfff0),
  76   MSP_INSN (xor,   1, 2, 0xe000, 0xf000),
  77   MSP_INSN (setz,  0, 0, 0xd322, 0xffff),
  78   MSP_INSN (setc,  0, 0, 0xd312, 0xffff),
  79   MSP_INSN (eint,  0, 0, 0xd232, 0xffff),
  80   MSP_INSN (setn,  0, 0, 0xd222, 0xffff),
  81   MSP_INSN (bis,   1, 2, 0xd000, 0xf000),
  82   MSP_INSN (clrz,  0, 0, 0xc322, 0xffff),
  83   MSP_INSN (clrc,  0, 0, 0xc312, 0xffff),
  84   MSP_INSN (dint,  0, 0, 0xc232, 0xffff),
  85   MSP_INSN (clrn,  0, 0, 0xc222, 0xffff),
  86   MSP_INSN (bic,   1, 2, 0xc000, 0xf000),
  87   MSP_INSN (bit,   1, 2, 0xb000, 0xf000),
  88   MSP_INSN (dadc,  0, 1, 0xa300, 0xff30),
  89   MSP_INSN (dadd,  1, 2, 0xa000, 0xf000),
  90   MSP_INSN (tst,   0, 1, 0x9300, 0xff30),
  91   MSP_INSN (cmp,   1, 2, 0x9000, 0xf000),
  92   MSP_INSN (decd,  0, 1, 0x8320, 0xff30),
  93   MSP_INSN (dec,   0, 1, 0x8310, 0xff30),
  94   MSP_INSN (sub,   1, 2, 0x8000, 0xf000),
  95   MSP_INSN (sbc,   0, 1, 0x7300, 0xff30),
  96   MSP_INSN (subc,  1, 2, 0x7000, 0xf000),
  97   MSP_INSN (adc,   0, 1, 0x6300, 0xff30),
  98   MSP_INSN (rlc,   0, 2, 0x6000, 0xf000),
  99   MSP_INSN (addc,  1, 2, 0x6000, 0xf000),
 100   MSP_INSN (incd,  0, 1, 0x5320, 0xff30),
 101   MSP_INSN (inc,   0, 1, 0x5310, 0xff30),
 102   MSP_INSN (rla,   0, 2, 0x5000, 0xf000),
 103   MSP_INSN (add,   1, 2, 0x5000, 0xf000),
 104   MSP_INSN (nop,   0, 0, 0x4303, 0xffff),
 105   MSP_INSN (clr,   0, 1, 0x4300, 0xff30),
 106   MSP_INSN (ret,   0, 0, 0x4130, 0xff30),
 107   MSP_INSN (pop,   0, 1, 0x4130, 0xff30),
 108   MSP_INSN (br,    0, 3, 0x4000, 0xf000),
 109   MSP_INSN (mov,   1, 2, 0x4000, 0xf000),
 110   MSP_INSN (jmp,   3, 1, 0x3c00, 0xfc00),
 111   MSP_INSN (jl,    3, 1, 0x3800, 0xfc00),
 112   MSP_INSN (jge,   3, 1, 0x3400, 0xfc00),
 113   MSP_INSN (jn,    3, 1, 0x3000, 0xfc00),
 114   MSP_INSN (jc,    3, 1, 0x2c00, 0xfc00),
 115   MSP_INSN (jhs,   3, 1, 0x2c00, 0xfc00),
 116   MSP_INSN (jnc,   3, 1, 0x2800, 0xfc00),
 117   MSP_INSN (jlo,   3, 1, 0x2800, 0xfc00),
 118   MSP_INSN (jz,    3, 1, 0x2400, 0xfc00),
 119   MSP_INSN (jeq,   3, 1, 0x2400, 0xfc00),
 120   MSP_INSN (jnz,   3, 1, 0x2000, 0xfc00),
 121   MSP_INSN (jne,   3, 1, 0x2000, 0xfc00),
 122   MSP_INSN (reti,  2, 0, 0x1300, 0xffc0),
 123   MSP_INSN (call,  2, 1, 0x1280, 0xffc0),
 124   MSP_INSN (push,  2, 1, 0x1200, 0xff80),
 125   MSP_INSN (sxt,   2, 1, 0x1180, 0xffc0),
 126   MSP_INSN (rra,   2, 1, 0x1100, 0xff80),
 127   MSP_INSN (swpb,  2, 1, 0x1080, 0xffc0),
 128   MSP_INSN (rrc,   2, 1, 0x1000, 0xff80),
 129   /* Simple polymorphs.  */
 130   MSP_INSN (beq,   4, 0, 0, 0xffff),
 131   MSP_INSN (bne,   4, 1, 0, 0xffff),
 132   MSP_INSN (blt,   4, 2, 0, 0xffff),
 133   MSP_INSN (bltu,  4, 3, 0, 0xffff),
 134   MSP_INSN (bge,   4, 4, 0, 0xffff),
 135   MSP_INSN (bgeu,  4, 5, 0, 0xffff),
 136   MSP_INSN (bltn,  4, 6, 0, 0xffff),
 137   MSP_INSN (jump,  4, 7, 0, 0xffff),
 138   /* Long polymorphs.  */
 139   MSP_INSN (bgt,   5, 0, 0, 0xffff),
 140   MSP_INSN (bgtu,  5, 1, 0, 0xffff),
 141   MSP_INSN (bleu,  5, 2, 0, 0xffff),
 142   MSP_INSN (ble,   5, 3, 0, 0xffff),
 143
 144   /* MSP430X instructions - these ones use an extension word.
 145      A negative format indicates an MSP430X instruction.  */
 146   MSP_INSN (addcx, -2, 2, 0x6000, 0xf000),
 147   MSP_INSN (addx,  -2, 2, 0x5000, 0xf000),
 148   MSP_INSN (andx,  -2, 2, 0xf000, 0xf000),
 149   MSP_INSN (bicx,  -2, 2, 0xc000, 0xf000),
 150   MSP_INSN (bisx,  -2, 2, 0xd000, 0xf000),
 151   MSP_INSN (bitx,  -2, 2, 0xb000, 0xf000),
 152   MSP_INSN (cmpx,  -2, 2, 0x9000, 0xf000),
 153   MSP_INSN (daddx, -2, 2, 0xa000, 0xf000),
 154   MSP_INSN (movx,  -2, 2, 0x4000, 0xf000),
 155   MSP_INSN (subcx, -2, 2, 0x7000, 0xf000),
 156   MSP_INSN (subx,  -2, 2, 0x8000, 0xf000),
 157   MSP_INSN (xorx,  -2, 2, 0xe000, 0xf000),
 158
 159   /* MSP430X Synthetic instructions.  */
 160   MSP_INSN (adcx,  -1, 1, 0x6300, 0xff30),
 161   MSP_INSN (clra,  -1, 1, 0x4300, 0xff30),
 162   MSP_INSN (clrx,  -1, 1, 0x4300, 0xff30),
 163   MSP_INSN (dadcx, -1, 1, 0xa300, 0xff30),
 164   MSP_INSN (decx,  -1, 1, 0x8310, 0xff30),
 165   MSP_INSN (decda, -1, 1, 0x8320, 0xff30),
 166   MSP_INSN (decdx, -1, 1, 0x8320, 0xff30),
 167   MSP_INSN (incx,  -1, 1, 0x5310, 0xff30),
 168   MSP_INSN (incda, -1, 1, 0x5320, 0xff30),
 169   MSP_INSN (incdx, -1, 1, 0x5320, 0xff30),
 170   MSP_INSN (invx,  -1, 1, 0xe330, 0xfff0),
 171   MSP_INSN (popx,  -1, 1, 0x4130, 0xff30),
 172   MSP_INSN (rlax,  -1, 2, 0x5000, 0xf000),
 173   MSP_INSN (rlcx,  -1, 2, 0x6000, 0xf000),
 174   MSP_INSN (sbcx,  -1, 1, 0x7300, 0xff30),
 175   MSP_INSN (tsta,  -1, 1, 0x9300, 0xff30),
 176   MSP_INSN (tstx,  -1, 1, 0x9300, 0xff30),
 177
 178   MSP_INSN (pushx, -3, 1, 0x1200, 0xff80),
 179   MSP_INSN (rrax,  -3, 1, 0x1100, 0xff80),
 180   MSP_INSN (rrcx,  -3, 1, 0x1000, 0xff80), /* Synthesised as RRC but with the Z/C bit clear.  */
 181   MSP_INSN (rrux,  -3, 1, 0x1000, 0xff80), /* Synthesised as RRC but with the Z/C bit set.  */
 182   MSP_INSN (swpbx, -3, 1, 0x1080, 0xffc0),
 183   MSP_INSN (sxtx,  -3, 1, 0x1180, 0xffc0),
 184
 185   /* MSP430X Address instructions - no extension word needed.
 186      The insn_opnumb field is used to encode the nature of the
 187      instruction for assembly and disassembly purposes.  */
 188   MSP_INSN (calla, -1, 4, 0x1300, 0xff00),
 189
 190   MSP_INSN (popm,  -1, 5, 0x1600, 0xfe00),
 191   MSP_INSN (pushm, -1, 5, 0x1400, 0xfe00),
 192
 193   MSP_INSN (rrcm,  -1, 6, 0x0040, 0xf3e0),
 194   MSP_INSN (rram,  -1, 6, 0x0140, 0xf3e0),
 195   MSP_INSN (rlam,  -1, 6, 0x0240, 0xf3e0),
 196   MSP_INSN (rrum,  -1, 6, 0x0340, 0xf3e0),
 197
 198   MSP_INSN (adda,  -1, 8, 0x00a0, 0xf0b0),
 199   MSP_INSN (cmpa,  -1, 8, 0x0090, 0xf0b0),
 200   MSP_INSN (suba,  -1, 8, 0x00b0, 0xf0b0),
 201
 202   MSP_INSN (reta,  -1, 9, 0x0110, 0xffff),
 203   MSP_INSN (bra,   -1, 9, 0x0000, 0xf0cf),
 204   MSP_INSN (mova,  -1, 9, 0x0000, 0xf080),
 205   MSP_INSN (mova,  -1, 9, 0x0080, 0xf0b0),
 206   MSP_INSN (mova,  -1, 9, 0x00c0, 0xf0f0),
 207
 208   /* Pseudo instruction to set the repeat field in the extension word.  */
 209   MSP_INSN (rpt,   -1, 10, 0x0000, 0x0000),
 210
 211   /* End of instruction set.  */
 212   { NULL, 0, 0, 0, 0 }
 213 };
 214
 215 #endif