sdcc/support/sdbinutils/include/opcode/xgate.h

   1 /* xgate.h -- Freescale XGATE opcode list
   2    Copyright (C) 2010-2022 Free Software Foundation, Inc.
   3    Written by Sean Keys (skeys@ipdatasys.com)
   4
   5    This file is part of the GNU opcodes library.
   6
   7    This library is free software; you can redistribute it and/or modify
   8    it under the terms of the GNU General Public License as published by
   9    the Free Software Foundation; either version 3, or (at your option)
  10    any later version.
  11
  12    It is distributed in the hope that it will be useful, but WITHOUT
  13    ANY WARRANTY; without even the implied warranty of MERCHANTABILITY
  14    or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public
  15    License for more details.
  16
  17    You should have received a copy of the GNU General Public License
  18    along with this file; see the file COPYING.  If not, write to the
  19    Free Software Foundation, 51 Franklin Street - Fifth Floor, Boston,
  20    MA 02110-1301, USA. */
  21
  22 #ifndef _OPCODE_XGATE_H
  23 #define _OPCODE_XGATE_H
  24
  25 /* XGATE CCR flag definitions.  */
  26 #define XGATE_N_BIT   0x08      /* XGN - Sign Flag */
  27 #define XGATE_Z_BIT   0x04      /* XGZ - Zero Flag */
  28 #define XGATE_V_BIT   0x02      /* XGV - Overflow Flag */
  29 #define XGATE_C_BIT   0x01      /* XGC - Carry Flag */
  30
  31 /* Access Detail Notation
  32    V - Vector fetch: always an aligned word read, lasts for at least one RISC core cycle
  33    P - Program word fetch: always an aligned word read, lasts for at least one RISC core cycle
  34    r - 8-bit data read: lasts for at least one RISC core cycle
  35    R - 16-bit data read: lasts for at least one RISC core cycle
  36    w - 8-bit data write: lasts for at least one RISC core cycle
  37    W - 16-bit data write: lasts for at least one RISC core cycle
  38    A - Alignment cycle: no read or write, lasts for zero or one RISC core cycles
  39    f - Free cycle: no read or write, lasts for one RISC core cycles.  */
  40 #define XGATE_CYCLE_V   0x01
  41 #define XGATE_CYCLE_P   0x02
  42 #define XGATE_CYCLE_r   0x04
  43 #define XGATE_CYCLE_R   0x08
  44 #define XGATE_CYCLE_w   0x10
  45 #define XGATE_CYCLE_W   0x20
  46 #define XGATE_CYCLE_A   0x40
  47 #define XGATE_CYCLE_f   0x80
  48
  49 /* XGATE operand formats as stored in the XGATE_opcode table.
  50    They are only used by GAS to recognize operands.  */
  51 #define XGATE_OP_INH                  ""  /* Inherent.  */
  52 #define XGATE_OP_TRI             "r,r,r"  /* Register followed by two registers.                    */
  53 #define XGATE_OP_DYA               "r,r"  /* Register followed by a register.                       */
  54 #define XGATE_OP_IMM16            "r,if"  /* Register followed by 16-bit value.                    */
  55 #define XGATE_OP_IMM8             "r,i8"  /* Register followed by 8-bit value.                      */
  56 #define XGATE_OP_IMM4             "r,i4"  /* Register followed by 4-bit value.                     */
  57 #define XGATE_OP_IMM3               "i3"  /* Register followed by 3-bit value.                      */
  58 #define XGATE_OP_MON                 "r"  /* Single register.                                       */
  59 #define XGATE_OP_MON_R_C           "r,c"  /* General register followed by ccr register.             */
  60 #define XGATE_OP_MON_C_R           "c,r"  /* CCR register followed by a general register.           */
  61 #define XGATE_OP_MON_R_P           "r,p"  /* General register followed by pc register.              */
  62 #define XGATE_OP_IDR             "r,r,+"  /* Three registers with the third having a -/+ directive. */
  63 #define XGATE_OP_IDO5           "r,r,i5"  /* Two general registers followed by an immediate value.  */
  64 #define XGATE_OP_REL9               "b9"  /* 9-bit value that is relative to the current pc.        */
  65 #define XGATE_OP_REL10              "ba"  /* 10-bit value that is relative to the current pc.       */
  66 #define XGATE_OP_DYA_MON            "=r"
  67 /* Macro definitions.  */
  68 #define XGATE_OP_IMM16mADD    "r,if; addl addh"
  69 #define XGATE_OP_IMM16mAND    "r,if; andl andh"
  70 #define XGATE_OP_IMM16mCPC    "r,if; cmpl cpch"
  71 #define XGATE_OP_IMM16mSUB    "r,if; subl subh"
  72 #define XGATE_OP_IMM16mLDW    "r,if; ldl ldh"
  73
  74 /* CPU variant identification.  */
  75 #define XGATE_V1 0x1
  76 #define XGATE_V2 0x2
  77 #define XGATE_V3 0x4
  78
  79 /* The opcode table definitions.  */
  80 struct xgate_opcode
  81 {
  82   char * name;                  /* Op-code name.  */
  83   char * constraints;           /* Constraint chars.  */
  84   char * format;                /* Bit definitions.  */
  85   unsigned int size;            /* Opcode size in bytes.  */
  86   unsigned int bin_opcode;      /* Binary opcode with operands masked off.  */
  87   unsigned char cycles_min;     /* Minimum cpu cycles needed.  */
  88   unsigned char cycles_max;     /* Maximum cpu cycles needed.  */
  89   unsigned char set_flags_mask; /* CCR flags set.  */
  90   unsigned char clr_flags_mask; /* CCR flags cleared.  */
  91   unsigned char chg_flags_mask; /* CCR flags changed.  */
  92   unsigned char arch;           /* CPU variant.  */
  93 };
  94
  95 /* The opcode table.  The table contains all the opcodes (all pages).
  96    You can't rely on the order.  */
  97 extern const struct xgate_opcode xgate_opcodes[];
  98 extern const int xgate_num_opcodes;
  99
 100 #endif /* _OPCODE_XGATE_H */