hw/pc.h

   1 #ifndef HW_PC_H
   2 #define HW_PC_H
   3
   4 #include "qemu-common.h"
   5
   6 /* PC-style peripherals (also used by other machines).  */
   7
   8 /* serial.c */
   9
  10 SerialState *serial_init(int base, qemu_irq irq, int baudbase,
  11                          CharDriverState *chr);
  12 SerialState *serial_mm_init (target_phys_addr_t base, int it_shift,
  13                              qemu_irq irq, int baudbase,
  14                              CharDriverState *chr, int ioregister);
  15 uint32_t serial_mm_readb (void *opaque, target_phys_addr_t addr);
  16 void serial_mm_writeb (void *opaque, target_phys_addr_t addr, uint32_t value);
  17 uint32_t serial_mm_readw (void *opaque, target_phys_addr_t addr);
  18 void serial_mm_writew (void *opaque, target_phys_addr_t addr, uint32_t value);
  19 uint32_t serial_mm_readl (void *opaque, target_phys_addr_t addr);
  20 void serial_mm_writel (void *opaque, target_phys_addr_t addr, uint32_t value);
  21
  22 /* parallel.c */
  23
  24 typedef struct ParallelState ParallelState;
  25 ParallelState *parallel_init(int base, qemu_irq irq, CharDriverState *chr);
  26 ParallelState *parallel_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq, CharDriverState *chr);
  27
  28 /* i8259.c */
  29
  30 typedef struct PicState2 PicState2;
  31 extern PicState2 *isa_pic;
  32 void pic_set_irq(int irq, int level);
  33 void pic_set_irq_new(void *opaque, int irq, int level);
  34 qemu_irq *i8259_init(qemu_irq parent_irq);
  35 void pic_set_alt_irq_func(PicState2 *s, SetIRQFunc *alt_irq_func,
  36                           void *alt_irq_opaque);
  37 int pic_read_irq(PicState2 *s);
  38 void pic_update_irq(PicState2 *s);
  39 uint32_t pic_intack_read(PicState2 *s);
  40 void pic_info(Monitor *mon);
  41 void irq_info(Monitor *mon);
  42
  43 /* APIC */
  44 typedef struct IOAPICState IOAPICState;
  45 void apic_deliver_irq(uint8_t dest, uint8_t dest_mode,
  46                              uint8_t delivery_mode,
  47                              uint8_t vector_num, uint8_t polarity,
  48                              uint8_t trigger_mode);
  49 int apic_init(CPUState *env);
  50 int apic_accept_pic_intr(CPUState *env);
  51 void apic_deliver_pic_intr(CPUState *env, int level);
  52 int apic_get_interrupt(CPUState *env);
  53 IOAPICState *ioapic_init(void);
  54 void ioapic_set_irq(void *opaque, int vector, int level);
  55 void apic_reset_irq_delivered(void);
  56 int apic_get_irq_delivered(void);
  57
  58 /* i8254.c */
  59
  60 #define PIT_FREQ 1193182
  61
  62 typedef struct PITState PITState;
  63
  64 PITState *pit_init(int base, qemu_irq irq);
  65 void pit_set_gate(PITState *pit, int channel, int val);
  66 int pit_get_gate(PITState *pit, int channel);
  67 int pit_get_initial_count(PITState *pit, int channel);
  68 int pit_get_mode(PITState *pit, int channel);
  69 int pit_get_out(PITState *pit, int channel, int64_t current_time);
  70
  71 void hpet_pit_disable(void);
  72 void hpet_pit_enable(void);
  73
  74 /* vmport.c */
  75 void vmport_init(void);
  76 void vmport_register(unsigned char command, IOPortReadFunc *func, void *opaque);
  77
  78 /* vmmouse.c */
  79 void *vmmouse_init(void *m);
  80
  81 /* pckbd.c */
  82
  83 void i8042_init(qemu_irq kbd_irq, qemu_irq mouse_irq, uint32_t io_base);
  84 void i8042_mm_init(qemu_irq kbd_irq, qemu_irq mouse_irq,
  85                    target_phys_addr_t base, ram_addr_t size,
  86                    target_phys_addr_t mask);
  87
  88 /* mc146818rtc.c */
  89
  90 typedef struct RTCState RTCState;
  91
  92 RTCState *rtc_init(int base, qemu_irq irq, int base_year);
  93 RTCState *rtc_mm_init(target_phys_addr_t base, int it_shift, qemu_irq irq,
  94                       int base_year);
  95 void rtc_set_memory(RTCState *s, int addr, int val);
  96 void rtc_set_date(RTCState *s, const struct tm *tm);
  97 void cmos_set_s3_resume(void);
  98
  99 /* pc.c */
 100 extern int fd_bootchk;
 101
 102 void ioport_set_a20(int enable);
 103 int ioport_get_a20(void);
 104
 105 /* acpi.c */
 106 extern int acpi_enabled;
 107 extern char *acpi_tables;
 108 extern size_t acpi_tables_len;
 109
 110 i2c_bus *piix4_pm_init(PCIBus *bus, int devfn, uint32_t smb_io_base,
 111                        qemu_irq sci_irq);
 112 void piix4_smbus_register_device(SMBusDevice *dev, uint8_t addr);
 113 void acpi_bios_init(void);
 114 int acpi_table_add(const char *table_desc);
 115
 116 /* hpet.c */
 117 extern int no_hpet;
 118
 119 /* pcspk.c */
 120 void pcspk_init(PITState *);
 121 int pcspk_audio_init(AudioState *, qemu_irq *pic);
 122
 123 /* piix_pci.c */
 124 PCIBus *i440fx_init(PCIDevice **pi440fx_state, qemu_irq *pic);
 125 void i440fx_set_smm(PCIDevice *d, int val);
 126 int piix3_init(PCIBus *bus, int devfn);
 127 void i440fx_init_memory_mappings(PCIDevice *d);
 128
 129 extern PCIDevice *piix4_dev;
 130 int piix4_init(PCIBus *bus, int devfn);
 131
 132 /* vga.c */
 133 enum vga_retrace_method {
 134     VGA_RETRACE_DUMB,
 135     VGA_RETRACE_PRECISE
 136 };
 137
 138 extern enum vga_retrace_method vga_retrace_method;
 139
 140 #if !defined(TARGET_SPARC) || defined(TARGET_SPARC64)
 141 #define VGA_RAM_SIZE (8192 * 1024)
 142 #else
 143 #define VGA_RAM_SIZE (9 * 1024 * 1024)
 144 #endif
 145
 146 int isa_vga_init(uint8_t *vga_ram_base,
 147                  unsigned long vga_ram_offset, int vga_ram_size);
 148 int pci_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
 149                  unsigned long vga_ram_offset, int vga_ram_size,
 150                  unsigned long vga_bios_offset, int vga_bios_size);
 151 int isa_vga_mm_init(uint8_t *vga_ram_base,
 152                     unsigned long vga_ram_offset, int vga_ram_size,
 153                     target_phys_addr_t vram_base, target_phys_addr_t ctrl_base,
 154                     int it_shift);
 155
 156 /* cirrus_vga.c */
 157 void pci_cirrus_vga_init(PCIBus *bus, uint8_t *vga_ram_base,
 158                          ram_addr_t vga_ram_offset, int vga_ram_size);
 159 void isa_cirrus_vga_init(uint8_t *vga_ram_base,
 160                          ram_addr_t vga_ram_offset, int vga_ram_size);
 161
 162 /* ide.c */
 163 void isa_ide_init(int iobase, int iobase2, qemu_irq irq,
 164                   BlockDriverState *hd0, BlockDriverState *hd1);
 165 void pci_cmd646_ide_init(PCIBus *bus, BlockDriverState **hd_table,
 166                          int secondary_ide_enabled);
 167 void pci_piix3_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
 168                         qemu_irq *pic);
 169 void pci_piix4_ide_init(PCIBus *bus, BlockDriverState **hd_table, int devfn,
 170                         qemu_irq *pic);
 171
 172 /* ne2000.c */
 173
 174 void isa_ne2000_init(int base, qemu_irq irq, NICInfo *nd);
 175
 176 #endif