hw/s3c24xx_lcd.c

   1 /*
   2  * Samsung S3C24xx series LCD controller.
   3  *
   4  * Copyright (c) 2007 OpenMoko, Inc.
   5  * Author: Andrzej Zaborowski <andrew@openedhand.com>
   6  * With:        Michel Pollet <buserror@gmail.com>
   7  *
   8  * This code is licenced under the GNU GPL v2.
   9  */
  10
  11 #include "s3c.h"
  12 #include "hw.h"
  13 #include "console.h"
  14
  15 typedef void (*s3c_drawfn_t)(uint32_t *, uint8_t *, const uint8_t *, int, int);
  16
  17 struct s3c_lcd_state_s {
  18     target_phys_addr_t base;
  19     void *irq;
  20     DisplayState *ds;
  21     s3c_drawfn_t *line_fn;
  22
  23     uint32_t con[5];
  24     uint32_t saddr[3];
  25     uint32_t r;
  26     uint32_t g;
  27     uint16_t b;
  28     uint32_t dithmode;
  29     uint32_t tpal;
  30     uint8_t intpnd;
  31     uint8_t srcpnd;
  32     uint8_t intmsk;
  33     uint8_t lpcsel;
  34
  35     uint16_t raw_pal[0x100];
  36
  37     int width;
  38     int height;
  39     int bpp;
  40     int enable;
  41     int msb;
  42     int frm565;
  43     void *fb;
  44     uint32_t palette[0x100];
  45     int invalidate;
  46     int invalidatep;
  47     int src_width;
  48     int dest_width;
  49     s3c_drawfn_t fn;
  50 };
  51
  52 static void s3c_lcd_update(struct s3c_lcd_state_s *s)
  53 {
  54     s->intpnd |= s->srcpnd & ~s->intmsk;
  55     qemu_set_irq(s->irq, !!s->intpnd);
  56 }
  57
  58 void s3c_lcd_reset(struct s3c_lcd_state_s *s)
  59 {
  60     s->enable = 0;
  61     s->invalidate = 1;
  62     s->invalidatep = 1;
  63     s->width = -1;
  64     s->height = -1;
  65
  66     s->con[0] = 0x00000000;
  67     s->con[1] = 0x00000000;
  68     s->con[2] = 0x00000000;
  69     s->con[3] = 0x00000000;
  70     s->con[4] = 0x00000000;
  71     s->saddr[0] = 0x00000000;
  72     s->saddr[1] = 0x00000000;
  73     s->saddr[2] = 0x00000000;
  74     s->r = 0x00000000;
  75     s->g = 0x00000000;
  76     s->b = 0x0000;
  77     s->dithmode = 0x00000;
  78     s->tpal = 0x00000000;
  79     s->intpnd = 0;
  80     s->srcpnd = 0;
  81     s->intmsk = 3;
  82     s->lpcsel = 4;
  83     s3c_lcd_update(s);
  84 }
  85
  86 #define S3C_LCDCON1     0x00    /* LCD Control register 1 */
  87 #define S3C_LCDCON2     0x04    /* LCD Control register 2 */
  88 #define S3C_LCDCON3     0x08    /* LCD Control register 3 */
  89 #define S3C_LCDCON4     0x0c    /* LCD Control register 4 */
  90 #define S3C_LCDCON5     0x10    /* LCD Control register 5 */
  91 #define S3C_LCDSADDR1   0x14    /* Framebuffer Start Address 1 register */
  92 #define S3C_LCDSADDR2   0x18    /* Framebuffer Start Address 2 register */
  93 #define S3C_LCDSADDR3   0x1c    /* Framebuffer Start Address 3 register */
  94 #define S3C_REDLUT      0x20    /* Red Lookup Table register */
  95 #define S3C_GREENLUT    0x24    /* Green Lookup Table register */
  96 #define S3C_BLUELUT     0x28    /* Blue Lookup Table register */
  97 #define S3C_DITHMODE    0x4c    /* Dithering Mode register */
  98 #define S3C_TPAL        0x50    /* Temporary Palette register */
  99 #define S3C_LCDINTPND   0x54    /* LCD Interrupt Pending register */
 100 #define S3C_LCDSRCPND   0x58    /* LCD Interrupt Source Pending register */
 101 #define S3C_LCDINTMSK   0x5c    /* LCD Interrupt Mask register */
 102 #define S3C_LPCSEL      0x60    /* LPC3600 Control register */
 103
 104 #define S3C_PALETTE     0x400   /* Palette IO start offset */
 105 #define S3C_PALETTEEND  0x5ff   /* Palette IO end offset */
 106
 107 static uint32_t s3c_lcd_read(void *opaque, target_phys_addr_t addr)
 108 {
 109     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *) opaque;
 110
 111     switch (addr) {
 112     case S3C_LCDCON1:
 113         return s->con[0];               /* XXX Return random LINECNT? */
 114     case S3C_LCDCON2:
 115         return s->con[1];
 116     case S3C_LCDCON3:
 117         return s->con[2];
 118     case S3C_LCDCON4:
 119         return s->con[3];
 120     case S3C_LCDCON5:
 121         return s->con[4];               /* XXX Return random STATUS? */
 122     case S3C_LCDSADDR1:
 123         return s->saddr[0];
 124     case S3C_LCDSADDR2:
 125         return s->saddr[1];
 126     case S3C_LCDSADDR3:
 127         return s->saddr[2];
 128     case S3C_REDLUT:
 129         return s->r;
 130     case S3C_GREENLUT:
 131         return s->g;
 132     case S3C_BLUELUT:
 133         return s->b;
 134     case S3C_DITHMODE:
 135         return s->dithmode;
 136     case S3C_TPAL:
 137         return s->tpal;
 138     case S3C_LCDINTPND:
 139         return s->intpnd;
 140     case S3C_LCDSRCPND:
 141         return s->srcpnd;
 142     case S3C_LCDINTMSK:
 143         return s->intmsk;
 144     case S3C_LPCSEL:
 145         return s->lpcsel;
 146     case S3C_PALETTE ... S3C_PALETTEEND:
 147         /* XXX assuming 16bit access */
 148         return s->raw_pal[(addr - S3C_PALETTE) >> 1];
 149     default:
 150         printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
 151         break;
 152     }
 153     return 0;
 154 }
 155
 156 static void s3c_lcd_write(void *opaque, target_phys_addr_t addr,
 157                 uint32_t value)
 158 {
 159     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *) opaque;
 160
 161     switch (addr) {
 162     case S3C_LCDCON1:
 163         s->con[0] = value & 0x0003ffff;
 164         s->enable = value & 1;
 165         s->bpp = (value >> 1) & 0xf;
 166         s->invalidate = 1;
 167         s->invalidatep = 1;
 168         break;
 169     case S3C_LCDCON2:
 170         s->con[1] = value;
 171         s->invalidate = 1;
 172         break;
 173     case S3C_LCDCON3:
 174         s->con[2] = value;
 175         s->invalidate = 1;
 176         break;
 177     case S3C_LCDCON4:
 178         s->con[3] = value & 0xffff;
 179         break;
 180     case S3C_LCDCON5:
 181         s->con[4] = value & 0x1fff;
 182         s->frm565 = (value >> 11) & 1;
 183         s->msb = (value >> 12) & 1;
 184         s->invalidatep = 1;
 185         s->invalidate = 1;
 186         break;
 187     case S3C_LCDSADDR1:
 188         s->saddr[0] = value;
 189         s->fb = phys_ram_base +
 190                 (((s->saddr[0] << 1) & 0x7ffffffe) - S3C_RAM_BASE);
 191         s->invalidate = 1;
 192         break;
 193     case S3C_LCDSADDR2:
 194         s->saddr[1] = value;
 195         s->invalidate = 1;
 196         break;
 197     case S3C_LCDSADDR3:
 198         s->saddr[2] = value;
 199         s->invalidate = 1;
 200         break;
 201     case S3C_REDLUT:
 202         s->r = value;
 203         s->invalidatep = 1;
 204         s->invalidate = 1;
 205         break;
 206     case S3C_GREENLUT:
 207         s->g = value;
 208         s->invalidatep = 1;
 209         s->invalidate = 1;
 210         break;
 211     case S3C_BLUELUT:
 212         s->b = value;
 213         s->invalidatep = 1;
 214         s->invalidate = 1;
 215         break;
 216     case S3C_DITHMODE:
 217         s->dithmode = value;
 218         break;
 219     case S3C_TPAL:
 220         s->tpal = value;
 221         s->invalidatep = 1;
 222         s->invalidate = 1;
 223         break;
 224     case S3C_LCDINTPND:
 225         s->intpnd = value & 3;
 226         break;
 227     case S3C_LCDSRCPND:
 228         s->srcpnd = value & 3;
 229         break;
 230     case S3C_LCDINTMSK:
 231         s->intmsk = value & 7;
 232         s3c_lcd_update(s);
 233         break;
 234     case S3C_LPCSEL:
 235         s->lpcsel = (value & 3) | 4;
 236         if (value & 1)
 237             printf("%s: attempt to enable LPC3600\n", __FUNCTION__);
 238         break;
 239     case S3C_PALETTE ... S3C_PALETTEEND:
 240         /* XXX assuming 16bit access */
 241         s->raw_pal[(addr - S3C_PALETTE) >> 1] = value;
 242         break;
 243     default:
 244         printf("%s: Bad register 0x%lx\n", __FUNCTION__, (unsigned long)addr);
 245     }
 246 }
 247
 248 static CPUReadMemoryFunc *s3c_lcd_readfn[] = {
 249     s3c_lcd_read,
 250     s3c_lcd_read,
 251     s3c_lcd_read,
 252 };
 253
 254 static CPUWriteMemoryFunc *s3c_lcd_writefn[] = {
 255     s3c_lcd_write,
 256     s3c_lcd_write,
 257     s3c_lcd_write,
 258 };
 259
 260 static inline void s3c_lcd_resize(struct s3c_lcd_state_s *s)
 261 {
 262     int new_width, new_height;
 263     new_height = ((s->con[1] >> 14) & 0x3ff) + 1;
 264     new_width = ((s->con[2] >> 8) & 0x7ff) + 1;
 265     if (s->width != new_width || s->height != new_height) {
 266         s->width = new_width;
 267         s->height = new_height;
 268        // dpy_resize(s->ds, s->width, s->height);
 269         qemu_console_resize(s->ds, s->width, s->height);
 270         s->invalidate = 1;
 271     }
 272 }
 273
 274 static inline
 275 uint32_t s3c_rgb_to_pixel8(unsigned int r, unsigned int g, unsigned b)
 276 {
 277     return ((r >> 5) << 5) | ((g >> 5) << 2) | (b >> 6);
 278 }
 279
 280 static inline
 281 uint32_t s3c_rgb_to_pixel15(unsigned int r, unsigned int g, unsigned b)
 282 {
 283     return ((r >> 3) << 10) | ((g >> 3) << 5) | (b >> 3);
 284 }
 285
 286 static inline
 287 uint32_t s3c_rgb_to_pixel16(unsigned int r, unsigned int g, unsigned b)
 288 {
 289     return ((r >> 3) << 11) | ((g >> 2) << 5) | (b >> 3);
 290 }
 291
 292 static inline
 293 uint32_t s3c_rgb_to_pixel24(unsigned int r, unsigned int g, unsigned b)
 294 {
 295     return (r << 16) | (g << 8) | b;
 296 }
 297
 298 static inline
 299 uint32_t s3c_rgb_to_pixel32(unsigned int r, unsigned int g, unsigned b)
 300 {
 301     return (r << 16) | (g << 8) | b;
 302 }
 303
 304 static inline uint32_t s3c_rgb(struct s3c_lcd_state_s *s,
 305                 unsigned int r, unsigned int g, unsigned b)
 306 {
 307     switch (ds_get_bits_per_pixel(s->ds)) {
 308     case 8:
 309         return s3c_rgb_to_pixel32(r << 2, g << 2, b << 2);
 310     case 15:
 311         return s3c_rgb_to_pixel15(r << 2, g << 2, b << 2);
 312     case 16:
 313         return s3c_rgb_to_pixel16(r << 2, g << 2, b << 2);
 314     case 24:
 315         return s3c_rgb_to_pixel24(r << 2, g << 2, b << 2);
 316     case 32:
 317         return s3c_rgb_to_pixel32(r << 2, g << 2, b << 2);
 318     default:
 319         fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
 320         exit(1);
 321     }
 322 }
 323
 324 static void s3c_lcd_palette_load(struct s3c_lcd_state_s *s)
 325 {
 326     int i, n;
 327     switch (s->bpp) {
 328     case 0:
 329     case 8:
 330         n = 2;
 331         s->src_width = s->width >> 3;
 332         s->fn = s->line_fn[0];
 333         break;
 334     case 1:
 335     case 9:
 336         n = 4;
 337         s->src_width = s->width >> 2;
 338         s->fn = s->line_fn[1];
 339         break;
 340     case 2:
 341     case 10:
 342         n = 16;
 343         s->src_width = s->width >> 1;
 344         s->fn = s->line_fn[2];
 345         break;
 346     case 3:
 347     case 11:
 348         n = 256;
 349         s->src_width = s->width >> 0;
 350         s->fn = s->line_fn[3];
 351         break;
 352     case 6:
 353         s->src_width = (s->width * 3) >> 1;
 354         s->fn = s->line_fn[4];
 355         return;
 356     case 12:
 357         s->src_width = s->width << 1;
 358         if (s->frm565)
 359             s->fn = s->line_fn[5];
 360         else
 361             s->fn = s->line_fn[6];
 362         return;
 363     case 13:
 364         s->src_width = s->width << 2;
 365         s->fn = s->line_fn[7];
 366         return;
 367     default:
 368         return;
 369     }
 370     if (s->bpp & 8) {
 371         for (i = 0; i < n; i ++)
 372             if (s->frm565)
 373                 s->palette[i] = s3c_rgb(s,
 374                         (s->raw_pal[i] >> 10) & 0x3e,
 375                         (s->raw_pal[i] >> 5) & 0x3f,
 376                         (s->raw_pal[i] << 1) & 0x3e);
 377             else
 378                 s->palette[i] = s3c_rgb(s,
 379                         ((s->raw_pal[i] >> 10) & 0x3e) | (s->raw_pal[i] & 1),
 380                         ((s->raw_pal[i] >> 6) & 0x3e) | (s->raw_pal[i] & 1),
 381                         s->raw_pal[i] & 0x3f);
 382     } else {
 383         for (i = 0; i < n; i ++)
 384             if (n < 256)
 385                 s->palette[i] = s3c_rgb(s,
 386                         ((s->r >> (i * 4)) & 0xf) << 2,
 387                         ((s->g >> (i * 4)) & 0xf) << 2,
 388                         ((s->b >> (i * 4)) & 0xf) << 2);
 389             else
 390                 s->palette[i] = s3c_rgb(s,
 391                         ((s->r >> (((i >> 5) & 7) * 4)) & 0xf) << 2,
 392                         ((s->g >> (((i >> 2) & 7) * 4)) & 0xf) << 2,
 393                         ((s->b >> ((i & 3) * 4)) & 0xf) << 2);
 394     }
 395 }
 396
 397 static void s3c_update_display(void *opaque)
 398 {
 399     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *) opaque;
 400     int y, src_width, dest_width, dirty[2], miny, maxy;
 401     ram_addr_t x, addr, new_addr, start, end;
 402     uint8_t *src, *dest;
 403     if (!s->enable || !s->dest_width)
 404         return;
 405
 406     s3c_lcd_resize(s);
 407
 408     if (s->invalidatep) {
 409         s3c_lcd_palette_load(s);
 410         s->invalidatep = 0;
 411     }
 412
 413     src = s->fb;
 414     src_width = s->src_width;
 415
 416     dest = ds_get_data(s->ds);
 417     dest_width = s->width * s->dest_width;
 418
 419     addr = (ram_addr_t) (s->fb - (void *) phys_ram_base);
 420     start = addr + s->height * src_width;
 421     end = addr;
 422     dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG);
 423     miny = s->height;
 424     maxy = 0;
 425     for (y = 0; y < s->height; y ++) {
 426         new_addr = addr + src_width;
 427         for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
 428                         x += TARGET_PAGE_SIZE) {
 429             dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
 430             dirty[0] |= dirty[1];
 431         }
 432         if (dirty[0] || s->invalidate) {
 433             s->fn(s->palette, dest, src, s->width, s->dest_width);
 434             maxy = y;
 435             end = new_addr;
 436             if (y < miny) {
 437                 miny = y;
 438                 start = addr;
 439             }
 440         }
 441         addr = new_addr;
 442         dirty[0] = dirty[1];
 443         src += src_width;
 444         dest += dest_width;
 445     }
 446
 447     s->invalidate = 0;
 448     if (end > start)
 449         cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG);
 450     s->srcpnd |= (1 << 1);                      /* INT_FrSyn */
 451     s3c_lcd_update(s);
 452     dpy_update(s->ds, 0, miny, s->width, maxy);
 453 }
 454
 455 static void s3c_invalidate_display(void *opaque)
 456 {
 457     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *) opaque;
 458     s->invalidate = 1;
 459 }
 460
 461 static void s3c_screen_dump(void *opaque, const char *filename)
 462 {
 463     /* TODO */
 464 }
 465
 466 #define BITS 8
 467 #include "s3c24xx_template.h"
 468 #define BITS 15
 469 #include "s3c24xx_template.h"
 470 #define BITS 16
 471 #include "s3c24xx_template.h"
 472 #define BITS 24
 473 #include "s3c24xx_template.h"
 474 #define BITS 32
 475 #include "s3c24xx_template.h"
 476
 477 static void s3c_lcd_save(QEMUFile *f, void *opaque)
 478 {
 479     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *) opaque;
 480     int i;
 481     for (i = 0; i < 5; i ++)
 482         qemu_put_be32s(f, &s->con[i]);
 483     for (i = 0; i < 3; i ++)
 484         qemu_put_be32s(f, &s->saddr[i]);
 485     qemu_put_be32s(f, &s->r);
 486     qemu_put_be32s(f, &s->g);
 487     qemu_put_be16s(f, &s->b);
 488     qemu_put_be32s(f, &s->dithmode);
 489     qemu_put_be32s(f, &s->tpal);
 490     qemu_put_8s(f, &s->intpnd);
 491     qemu_put_8s(f, &s->srcpnd);
 492     qemu_put_8s(f, &s->intmsk);
 493     qemu_put_8s(f, &s->lpcsel);
 494     for (i = 0; i < 0x100; i ++)
 495         qemu_put_be16s(f, &s->raw_pal[i]);
 496 }
 497
 498 static int s3c_lcd_load(QEMUFile *f, void *opaque, int version_id)
 499 {
 500     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *) opaque;
 501     int i;
 502     for (i = 0; i < 5; i ++)
 503         qemu_get_be32s(f, &s->con[i]);
 504     for (i = 0; i < 3; i ++)
 505         qemu_get_be32s(f, &s->saddr[i]);
 506     qemu_get_be32s(f, &s->r);
 507     qemu_get_be32s(f, &s->g);
 508     qemu_get_be16s(f, &s->b);
 509     qemu_get_be32s(f, &s->dithmode);
 510     qemu_get_be32s(f, &s->tpal);
 511     qemu_get_8s(f, &s->intpnd);
 512     qemu_get_8s(f, &s->srcpnd);
 513     qemu_get_8s(f, &s->intmsk);
 514     qemu_get_8s(f, &s->lpcsel);
 515
 516     s->invalidate = 1;
 517     s->invalidatep = 1;
 518     s->width = -1;
 519     s->height = -1;
 520     s->bpp = (s->con[0] >> 1) & 0xf;
 521     s->enable = s->con[0] & 1;
 522     s->msb = (s->con[4] >> 12) & 1;
 523     s->frm565 = (s->con[4] >> 11) & 1;
 524     s->fb = phys_ram_base + (((s->saddr[0] << 1) & 0x7ffffffe) - S3C_RAM_BASE);
 525
 526     for (i = 0; i < 0x100; i ++)
 527         qemu_get_be16s(f, &s->raw_pal[i]);
 528
 529     return 0;
 530 }
 531
 532 struct s3c_lcd_state_s *s3c_lcd_init(target_phys_addr_t base,
 533                 qemu_irq irq)
 534 {
 535     int iomemtype;
 536     struct s3c_lcd_state_s *s = (struct s3c_lcd_state_s *)
 537             qemu_mallocz(sizeof(struct s3c_lcd_state_s));
 538
 539     s->base = base;
 540     s->irq = irq;
 541
 542     s3c_lcd_reset(s);
 543
 544     s->ds = graphic_console_init(
 545                                 s3c_update_display,
 546                     s3c_invalidate_display,
 547                     s3c_screen_dump, NULL, s);
 548
 549     iomemtype = cpu_register_io_memory(0, s3c_lcd_readfn,
 550                     s3c_lcd_writefn, s);
 551     cpu_register_physical_memory(s->base, 0xffffff, iomemtype);
 552
 553     register_savevm("s3c24xx_lcd", 0, 0, s3c_lcd_save, s3c_lcd_load, s);
 554
 555     switch (ds_get_bits_per_pixel(s->ds)) {
 556     case 0:
 557         s->dest_width = 0;
 558         break;
 559     case 8:
 560         s->line_fn = s3c_draw_fn_8;
 561         s->dest_width = 1;
 562         break;
 563     case 15:
 564         s->line_fn = s3c_draw_fn_15;
 565         s->dest_width = 2;
 566         break;
 567     case 16:
 568         s->line_fn = s3c_draw_fn_16;
 569         s->dest_width = 2;
 570         break;
 571     case 24:
 572         s->line_fn = s3c_draw_fn_24;
 573         s->dest_width = 3;
 574         break;
 575     case 32:
 576         s->line_fn = s3c_draw_fn_32;
 577         s->dest_width = 4;
 578         break;
 579     default:
 580         fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
 581         exit(1);
 582     }
 583     return s;
 584 }