?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
monitor: Don't change VNC server when disabled (Jan Kiszka)
[sniper_test.git] / hw / omap2.c
blob20b38116ffc402c199189d2b4bc6c6e2e3781e76
1 /*
2 * TI OMAP processors emulation.
3 *
4 * Copyright (C) 2007-2008 Nokia Corporation
5 * Written by Andrzej Zaborowski <andrew@openedhand.com>
6 *
7 * This program is free software; you can redistribute it and/or
8 * modify it under the terms of the GNU General Public License as
9 * published by the Free Software Foundation; either version 2 or
10 * (at your option) version 3 of the License.
11 *
12 * This program is distributed in the hope that it will be useful,
13 * but WITHOUT ANY WARRANTY; without even the implied warranty of
14 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
15 * GNU General Public License for more details.
16 *
17 * You should have received a copy of the GNU General Public License along
18 * with this program; if not, write to the Free Software Foundation, Inc.,
19 * 51 Franklin Street, Fifth Floor, Boston, MA 02110-1301 USA.
20 */
21 #include "hw.h"
22 #include "arm-misc.h"
23 #include "omap.h"
24 #include "sysemu.h"
25 #include "qemu-timer.h"
26 #include "qemu-char.h"
27 #include "flash.h"
28 #include "soc_dma.h"
29 #include "audio/audio.h"
30
31 /* GP timers */
32 struct omap_gp_timer_s {
33 qemu_irq irq;
34 qemu_irq wkup;
35 qemu_irq in;
36 qemu_irq out;
37 omap_clk clk;
38 QEMUTimer *timer;
39 QEMUTimer *match;
40 struct omap_target_agent_s *ta;
41
42 int in_val;
43 int out_val;
44 int64_t time;
45 int64_t rate;
46 int64_t ticks_per_sec;
47
48 int16_t config;
49 int status;
50 int it_ena;
51 int wu_ena;
52 int enable;
53 int inout;
54 int capt2;
55 int pt;
56 enum {
57 gpt_trigger_none, gpt_trigger_overflow, gpt_trigger_both
58 } trigger;
59 enum {
60 gpt_capture_none, gpt_capture_rising,
61 gpt_capture_falling, gpt_capture_both
62 } capture;
63 int scpwm;
64 int ce;
65 int pre;
66 int ptv;
67 int ar;
68 int st;
69 int posted;
70 uint32_t val;
71 uint32_t load_val;
72 uint32_t capture_val[2];
73 uint32_t match_val;
74 int capt_num;
75
76 uint16_t writeh; /* LSB */
77 uint16_t readh; /* MSB */
78 };
79
80 #define GPT_TCAR_IT (1 << 2)
81 #define GPT_OVF_IT (1 << 1)
82 #define GPT_MAT_IT (1 << 0)
83
84 static inline void omap_gp_timer_intr(struct omap_gp_timer_s *timer, int it)
85 {
86 if (timer->it_ena & it) {
87 if (!timer->status)
88 qemu_irq_raise(timer->irq);
89
90 timer->status |= it;
91 /* Or are the status bits set even when masked?
92 * i.e. is masking applied before or after the status register? */
93 }
94
95 if (timer->wu_ena & it)
96 qemu_irq_pulse(timer->wkup);
97 }
98
99 static inline void omap_gp_timer_out(struct omap_gp_timer_s *timer, int level)
100 {
101 if (!timer->inout && timer->out_val != level) {
102 timer->out_val = level;
103 qemu_set_irq(timer->out, level);
104 }
105 }
106
107 static inline uint32_t omap_gp_timer_read(struct omap_gp_timer_s *timer)
108 {
109 uint64_t distance;
110
111 if (timer->st && timer->rate) {
112 distance = qemu_get_clock(vm_clock) - timer->time;
113 distance = muldiv64(distance, timer->rate, timer->ticks_per_sec);
114
115 if (distance >= 0xffffffff - timer->val)
116 return 0xffffffff;
117 else
118 return timer->val + distance;
119 } else
120 return timer->val;
121 }
122
123 static inline void omap_gp_timer_sync(struct omap_gp_timer_s *timer)
124 {
125 if (timer->st) {
126 timer->val = omap_gp_timer_read(timer);
127 timer->time = qemu_get_clock(vm_clock);
128 }
129 }
130
131 static inline void omap_gp_timer_update(struct omap_gp_timer_s *timer)
132 {
133 int64_t expires, matches;
134
135 if (timer->st && timer->rate) {
136 expires = muldiv64(0x100000000ll - timer->val,
137 timer->ticks_per_sec, timer->rate);
138 qemu_mod_timer(timer->timer, timer->time + expires);
139
140 if (timer->ce && timer->match_val >= timer->val) {
141 matches = muldiv64(timer->match_val - timer->val,
142 timer->ticks_per_sec, timer->rate);
143 qemu_mod_timer(timer->match, timer->time + matches);
144 } else
145 qemu_del_timer(timer->match);
146 } else {
147 qemu_del_timer(timer->timer);
148 qemu_del_timer(timer->match);
149 omap_gp_timer_out(timer, timer->scpwm);
150 }
151 }
152
153 static inline void omap_gp_timer_trigger(struct omap_gp_timer_s *timer)
154 {
155 if (timer->pt)
156 /* TODO in overflow-and-match mode if the first event to
157 * occur is the match, don't toggle. */
158 omap_gp_timer_out(timer, !timer->out_val);
159 else
160 /* TODO inverted pulse on timer->out_val == 1? */
161 qemu_irq_pulse(timer->out);
162 }
163
164 static void omap_gp_timer_tick(void *opaque)
165 {
166 struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
167
168 if (!timer->ar) {
169 timer->st = 0;
170 timer->val = 0;
171 } else {
172 timer->val = timer->load_val;
173 timer->time = qemu_get_clock(vm_clock);
174 }
175
176 if (timer->trigger == gpt_trigger_overflow ||
177 timer->trigger == gpt_trigger_both)
178 omap_gp_timer_trigger(timer);
179
180 omap_gp_timer_intr(timer, GPT_OVF_IT);
181 omap_gp_timer_update(timer);
182 }
183
184 static void omap_gp_timer_match(void *opaque)
185 {
186 struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
187
188 if (timer->trigger == gpt_trigger_both)
189 omap_gp_timer_trigger(timer);
190
191 omap_gp_timer_intr(timer, GPT_MAT_IT);
192 }
193
194 static void omap_gp_timer_input(void *opaque, int line, int on)
195 {
196 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
197 int trigger;
198
199 switch (s->capture) {
200 default:
201 case gpt_capture_none:
202 trigger = 0;
203 break;
204 case gpt_capture_rising:
205 trigger = !s->in_val && on;
206 break;
207 case gpt_capture_falling:
208 trigger = s->in_val && !on;
209 break;
210 case gpt_capture_both:
211 trigger = (s->in_val == !on);
212 break;
213 }
214 s->in_val = on;
215
216 if (s->inout && trigger && s->capt_num < 2) {
217 s->capture_val[s->capt_num] = omap_gp_timer_read(s);
218
219 if (s->capt2 == s->capt_num ++)
220 omap_gp_timer_intr(s, GPT_TCAR_IT);
221 }
222 }
223
224 static void omap_gp_timer_clk_update(void *opaque, int line, int on)
225 {
226 struct omap_gp_timer_s *timer = (struct omap_gp_timer_s *) opaque;
227
228 omap_gp_timer_sync(timer);
229 timer->rate = on ? omap_clk_getrate(timer->clk) : 0;
230 omap_gp_timer_update(timer);
231 }
232
233 static void omap_gp_timer_clk_setup(struct omap_gp_timer_s *timer)
234 {
235 omap_clk_adduser(timer->clk,
236 qemu_allocate_irqs(omap_gp_timer_clk_update, timer, 1)[0]);
237 timer->rate = omap_clk_getrate(timer->clk);
238 }
239
240 static void omap_gp_timer_reset(struct omap_gp_timer_s *s)
241 {
242 s->config = 0x000;
243 s->status = 0;
244 s->it_ena = 0;
245 s->wu_ena = 0;
246 s->inout = 0;
247 s->capt2 = 0;
248 s->capt_num = 0;
249 s->pt = 0;
250 s->trigger = gpt_trigger_none;
251 s->capture = gpt_capture_none;
252 s->scpwm = 0;
253 s->ce = 0;
254 s->pre = 0;
255 s->ptv = 0;
256 s->ar = 0;
257 s->st = 0;
258 s->posted = 1;
259 s->val = 0x00000000;
260 s->load_val = 0x00000000;
261 s->capture_val[0] = 0x00000000;
262 s->capture_val[1] = 0x00000000;
263 s->match_val = 0x00000000;
264 omap_gp_timer_update(s);
265 }
266
267 static uint32_t omap_gp_timer_readw(void *opaque, target_phys_addr_t addr)
268 {
269 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
270
271 switch (addr) {
272 case 0x00: /* TIDR */
273 return 0x21;
274
275 case 0x10: /* TIOCP_CFG */
276 return s->config;
277
278 case 0x14: /* TISTAT */
279 /* ??? When's this bit reset? */
280 return 1; /* RESETDONE */
281
282 case 0x18: /* TISR */
283 return s->status;
284
285 case 0x1c: /* TIER */
286 return s->it_ena;
287
288 case 0x20: /* TWER */
289 return s->wu_ena;
290
291 case 0x24: /* TCLR */
292 return (s->inout << 14) |
293 (s->capt2 << 13) |
294 (s->pt << 12) |
295 (s->trigger << 10) |
296 (s->capture << 8) |
297 (s->scpwm << 7) |
298 (s->ce << 6) |
299 (s->pre << 5) |
300 (s->ptv << 2) |
301 (s->ar << 1) |
302 (s->st << 0);
303
304 case 0x28: /* TCRR */
305 return omap_gp_timer_read(s);
306
307 case 0x2c: /* TLDR */
308 return s->load_val;
309
310 case 0x30: /* TTGR */
311 return 0xffffffff;
312
313 case 0x34: /* TWPS */
314 return 0x00000000; /* No posted writes pending. */
315
316 case 0x38: /* TMAR */
317 return s->match_val;
318
319 case 0x3c: /* TCAR1 */
320 return s->capture_val[0];
321
322 case 0x40: /* TSICR */
323 return s->posted << 2;
324
325 case 0x44: /* TCAR2 */
326 return s->capture_val[1];
327 }
328
329 OMAP_BAD_REG(addr);
330 return 0;
331 }
332
333 static uint32_t omap_gp_timer_readh(void *opaque, target_phys_addr_t addr)
334 {
335 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
336 uint32_t ret;
337
338 if (addr & 2)
339 return s->readh;
340 else {
341 ret = omap_gp_timer_readw(opaque, addr);
342 s->readh = ret >> 16;
343 return ret & 0xffff;
344 }
345 }
346
347 static CPUReadMemoryFunc *omap_gp_timer_readfn[] = {
348 omap_badwidth_read32,
349 omap_gp_timer_readh,
350 omap_gp_timer_readw,
351 };
352
353 static void omap_gp_timer_write(void *opaque, target_phys_addr_t addr,
354 uint32_t value)
355 {
356 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
357
358 switch (addr) {
359 case 0x00: /* TIDR */
360 case 0x14: /* TISTAT */
361 case 0x34: /* TWPS */
362 case 0x3c: /* TCAR1 */
363 case 0x44: /* TCAR2 */
364 OMAP_RO_REG(addr);
365 break;
366
367 case 0x10: /* TIOCP_CFG */
368 s->config = value & 0x33d;
369 if (((value >> 3) & 3) == 3) /* IDLEMODE */
370 fprintf(stderr, "%s: illegal IDLEMODE value in TIOCP_CFG\n",
371 __FUNCTION__);
372 if (value & 2) /* SOFTRESET */
373 omap_gp_timer_reset(s);
374 break;
375
376 case 0x18: /* TISR */
377 if (value & GPT_TCAR_IT)
378 s->capt_num = 0;
379 if (s->status && !(s->status &= ~value))
380 qemu_irq_lower(s->irq);
381 break;
382
383 case 0x1c: /* TIER */
384 s->it_ena = value & 7;
385 break;
386
387 case 0x20: /* TWER */
388 s->wu_ena = value & 7;
389 break;
390
391 case 0x24: /* TCLR */
392 omap_gp_timer_sync(s);
393 s->inout = (value >> 14) & 1;
394 s->capt2 = (value >> 13) & 1;
395 s->pt = (value >> 12) & 1;
396 s->trigger = (value >> 10) & 3;
397 if (s->capture == gpt_capture_none &&
398 ((value >> 8) & 3) != gpt_capture_none)
399 s->capt_num = 0;
400 s->capture = (value >> 8) & 3;
401 s->scpwm = (value >> 7) & 1;
402 s->ce = (value >> 6) & 1;
403 s->pre = (value >> 5) & 1;
404 s->ptv = (value >> 2) & 7;
405 s->ar = (value >> 1) & 1;
406 s->st = (value >> 0) & 1;
407 if (s->inout && s->trigger != gpt_trigger_none)
408 fprintf(stderr, "%s: GP timer pin must be an output "
409 "for this trigger mode\n", __FUNCTION__);
410 if (!s->inout && s->capture != gpt_capture_none)
411 fprintf(stderr, "%s: GP timer pin must be an input "
412 "for this capture mode\n", __FUNCTION__);
413 if (s->trigger == gpt_trigger_none)
414 omap_gp_timer_out(s, s->scpwm);
415 /* TODO: make sure this doesn't overflow 32-bits */
416 s->ticks_per_sec = ticks_per_sec << (s->pre ? s->ptv + 1 : 0);
417 omap_gp_timer_update(s);
418 break;
419
420 case 0x28: /* TCRR */
421 s->time = qemu_get_clock(vm_clock);
422 s->val = value;
423 omap_gp_timer_update(s);
424 break;
425
426 case 0x2c: /* TLDR */
427 s->load_val = value;
428 break;
429
430 case 0x30: /* TTGR */
431 s->time = qemu_get_clock(vm_clock);
432 s->val = s->load_val;
433 omap_gp_timer_update(s);
434 break;
435
436 case 0x38: /* TMAR */
437 omap_gp_timer_sync(s);
438 s->match_val = value;
439 omap_gp_timer_update(s);
440 break;
441
442 case 0x40: /* TSICR */
443 s->posted = (value >> 2) & 1;
444 if (value & 2) /* How much exactly are we supposed to reset? */
445 omap_gp_timer_reset(s);
446 break;
447
448 default:
449 OMAP_BAD_REG(addr);
450 }
451 }
452
453 static void omap_gp_timer_writeh(void *opaque, target_phys_addr_t addr,
454 uint32_t value)
455 {
456 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *) opaque;
457
458 if (addr & 2)
459 return omap_gp_timer_write(opaque, addr, (value << 16) | s->writeh);
460 else
461 s->writeh = (uint16_t) value;
462 }
463
464 static CPUWriteMemoryFunc *omap_gp_timer_writefn[] = {
465 omap_badwidth_write32,
466 omap_gp_timer_writeh,
467 omap_gp_timer_write,
468 };
469
470 struct omap_gp_timer_s *omap_gp_timer_init(struct omap_target_agent_s *ta,
471 qemu_irq irq, omap_clk fclk, omap_clk iclk)
472 {
473 int iomemtype;
474 struct omap_gp_timer_s *s = (struct omap_gp_timer_s *)
475 qemu_mallocz(sizeof(struct omap_gp_timer_s));
476
477 s->ta = ta;
478 s->irq = irq;
479 s->clk = fclk;
480 s->timer = qemu_new_timer(vm_clock, omap_gp_timer_tick, s);
481 s->match = qemu_new_timer(vm_clock, omap_gp_timer_match, s);
482 s->in = qemu_allocate_irqs(omap_gp_timer_input, s, 1)[0];
483 omap_gp_timer_reset(s);
484 omap_gp_timer_clk_setup(s);
485
486 iomemtype = l4_register_io_memory(0, omap_gp_timer_readfn,
487 omap_gp_timer_writefn, s);
488 omap_l4_attach(ta, 0, iomemtype);
489
490 return s;
491 }
492
493 /* 32-kHz Sync Timer of the OMAP2 */
494 static uint32_t omap_synctimer_read(struct omap_synctimer_s *s) {
495 return muldiv64(qemu_get_clock(vm_clock), 0x8000, ticks_per_sec);
496 }
497
498 static void omap_synctimer_reset(struct omap_synctimer_s *s)
499 {
500 s->val = omap_synctimer_read(s);
501 }
502
503 static uint32_t omap_synctimer_readw(void *opaque, target_phys_addr_t addr)
504 {
505 struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
506
507 switch (addr) {
508 case 0x00: /* 32KSYNCNT_REV */
509 return 0x21;
510
511 case 0x10: /* CR */
512 return omap_synctimer_read(s) - s->val;
513 }
514
515 OMAP_BAD_REG(addr);
516 return 0;
517 }
518
519 static uint32_t omap_synctimer_readh(void *opaque, target_phys_addr_t addr)
520 {
521 struct omap_synctimer_s *s = (struct omap_synctimer_s *) opaque;
522 uint32_t ret;
523
524 if (addr & 2)
525 return s->readh;
526 else {
527 ret = omap_synctimer_readw(opaque, addr);
528 s->readh = ret >> 16;
529 return ret & 0xffff;
530 }
531 }
532
533 static CPUReadMemoryFunc *omap_synctimer_readfn[] = {
534 omap_badwidth_read32,
535 omap_synctimer_readh,
536 omap_synctimer_readw,
537 };
538
539 static void omap_synctimer_write(void *opaque, target_phys_addr_t addr,
540 uint32_t value)
541 {
542 OMAP_BAD_REG(addr);
543 }
544
545 static CPUWriteMemoryFunc *omap_synctimer_writefn[] = {
546 omap_badwidth_write32,
547 omap_synctimer_write,
548 omap_synctimer_write,
549 };
550
551 void omap_synctimer_init(struct omap_target_agent_s *ta,
552 struct omap_mpu_state_s *mpu, omap_clk fclk, omap_clk iclk)
553 {
554 struct omap_synctimer_s *s = &mpu->synctimer;
555
556 omap_synctimer_reset(s);
557 omap_l4_attach(ta, 0, l4_register_io_memory(0,
558 omap_synctimer_readfn, omap_synctimer_writefn, s));
559 }
560
561 /* General-Purpose Interface of OMAP2 */
562 struct omap2_gpio_s {
563 qemu_irq irq[2];
564 qemu_irq wkup;
565 qemu_irq *in;
566 qemu_irq handler[32];
567
568 uint8_t config[2];
569 uint32_t inputs;
570 uint32_t outputs;
571 uint32_t dir;
572 uint32_t level[2];
573 uint32_t edge[2];
574 uint32_t mask[2];
575 uint32_t wumask;
576 uint32_t ints[2];
577 uint32_t debounce;
578 uint8_t delay;
579 };
580
581 static inline void omap_gpio_module_int_update(struct omap2_gpio_s *s,
582 int line)
583 {
584 qemu_set_irq(s->irq[line], s->ints[line] & s->mask[line]);
585 }
586
587 static void omap_gpio_module_wake(struct omap2_gpio_s *s, int line)
588 {
589 if (!(s->config[0] & (1 << 2))) /* ENAWAKEUP */
590 return;
591 if (!(s->config[0] & (3 << 3))) /* Force Idle */
592 return;
593 if (!(s->wumask & (1 << line)))
594 return;
595
596 qemu_irq_raise(s->wkup);
597 }
598
599 static inline void omap_gpio_module_out_update(struct omap2_gpio_s *s,
600 uint32_t diff)
601 {
602 int ln;
603
604 s->outputs ^= diff;
605 diff &= ~s->dir;
606 while ((ln = ffs(diff))) {
607 ln --;
608 qemu_set_irq(s->handler[ln], (s->outputs >> ln) & 1);
609 diff &= ~(1 << ln);
610 }
611 }
612
613 static void omap_gpio_module_level_update(struct omap2_gpio_s *s, int line)
614 {
615 s->ints[line] |= s->dir &
616 ((s->inputs & s->level[1]) | (~s->inputs & s->level[0]));
617 omap_gpio_module_int_update(s, line);
618 }
619
620 static inline void omap_gpio_module_int(struct omap2_gpio_s *s, int line)
621 {
622 s->ints[0] |= 1 << line;
623 omap_gpio_module_int_update(s, 0);
624 s->ints[1] |= 1 << line;
625 omap_gpio_module_int_update(s, 1);
626 omap_gpio_module_wake(s, line);
627 }
628
629 static void omap_gpio_module_set(void *opaque, int line, int level)
630 {
631 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
632
633 if (level) {
634 if (s->dir & (1 << line) & ((~s->inputs & s->edge[0]) | s->level[1]))
635 omap_gpio_module_int(s, line);
636 s->inputs |= 1 << line;
637 } else {
638 if (s->dir & (1 << line) & ((s->inputs & s->edge[1]) | s->level[0]))
639 omap_gpio_module_int(s, line);
640 s->inputs &= ~(1 << line);
641 }
642 }
643
644 static void omap_gpio_module_reset(struct omap2_gpio_s *s)
645 {
646 s->config[0] = 0;
647 s->config[1] = 2;
648 s->ints[0] = 0;
649 s->ints[1] = 0;
650 s->mask[0] = 0;
651 s->mask[1] = 0;
652 s->wumask = 0;
653 s->dir = ~0;
654 s->level[0] = 0;
655 s->level[1] = 0;
656 s->edge[0] = 0;
657 s->edge[1] = 0;
658 s->debounce = 0;
659 s->delay = 0;
660 }
661
662 static uint32_t omap_gpio_module_read(void *opaque, target_phys_addr_t addr)
663 {
664 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
665
666 switch (addr) {
667 case 0x00: /* GPIO_REVISION */
668 return 0x18;
669
670 case 0x10: /* GPIO_SYSCONFIG */
671 return s->config[0];
672
673 case 0x14: /* GPIO_SYSSTATUS */
674 return 0x01;
675
676 case 0x18: /* GPIO_IRQSTATUS1 */
677 return s->ints[0];
678
679 case 0x1c: /* GPIO_IRQENABLE1 */
680 case 0x60: /* GPIO_CLEARIRQENABLE1 */
681 case 0x64: /* GPIO_SETIRQENABLE1 */
682 return s->mask[0];
683
684 case 0x20: /* GPIO_WAKEUPENABLE */
685 case 0x80: /* GPIO_CLEARWKUENA */
686 case 0x84: /* GPIO_SETWKUENA */
687 return s->wumask;
688
689 case 0x28: /* GPIO_IRQSTATUS2 */
690 return s->ints[1];
691
692 case 0x2c: /* GPIO_IRQENABLE2 */
693 case 0x70: /* GPIO_CLEARIRQENABLE2 */
694 case 0x74: /* GPIO_SETIREQNEABLE2 */
695 return s->mask[1];
696
697 case 0x30: /* GPIO_CTRL */
698 return s->config[1];
699
700 case 0x34: /* GPIO_OE */
701 return s->dir;
702
703 case 0x38: /* GPIO_DATAIN */
704 return s->inputs;
705
706 case 0x3c: /* GPIO_DATAOUT */
707 case 0x90: /* GPIO_CLEARDATAOUT */
708 case 0x94: /* GPIO_SETDATAOUT */
709 return s->outputs;
710
711 case 0x40: /* GPIO_LEVELDETECT0 */
712 return s->level[0];
713
714 case 0x44: /* GPIO_LEVELDETECT1 */
715 return s->level[1];
716
717 case 0x48: /* GPIO_RISINGDETECT */
718 return s->edge[0];
719
720 case 0x4c: /* GPIO_FALLINGDETECT */
721 return s->edge[1];
722
723 case 0x50: /* GPIO_DEBOUNCENABLE */
724 return s->debounce;
725
726 case 0x54: /* GPIO_DEBOUNCINGTIME */
727 return s->delay;
728 }
729
730 OMAP_BAD_REG(addr);
731 return 0;
732 }
733
734 static void omap_gpio_module_write(void *opaque, target_phys_addr_t addr,
735 uint32_t value)
736 {
737 struct omap2_gpio_s *s = (struct omap2_gpio_s *) opaque;
738 uint32_t diff;
739 int ln;
740
741 switch (addr) {
742 case 0x00: /* GPIO_REVISION */
743 case 0x14: /* GPIO_SYSSTATUS */
744 case 0x38: /* GPIO_DATAIN */
745 OMAP_RO_REG(addr);
746 break;
747
748 case 0x10: /* GPIO_SYSCONFIG */
749 if (((value >> 3) & 3) == 3)
750 fprintf(stderr, "%s: bad IDLEMODE value\n", __FUNCTION__);
751 if (value & 2)
752 omap_gpio_module_reset(s);
753 s->config[0] = value & 0x1d;
754 break;
755
756 case 0x18: /* GPIO_IRQSTATUS1 */
757 if (s->ints[0] & value) {
758 s->ints[0] &= ~value;
759 omap_gpio_module_level_update(s, 0);
760 }
761 break;
762
763 case 0x1c: /* GPIO_IRQENABLE1 */
764 s->mask[0] = value;
765 omap_gpio_module_int_update(s, 0);
766 break;
767
768 case 0x20: /* GPIO_WAKEUPENABLE */
769 s->wumask = value;
770 break;
771
772 case 0x28: /* GPIO_IRQSTATUS2 */
773 if (s->ints[1] & value) {
774 s->ints[1] &= ~value;
775 omap_gpio_module_level_update(s, 1);
776 }
777 break;
778
779 case 0x2c: /* GPIO_IRQENABLE2 */
780 s->mask[1] = value;
781 omap_gpio_module_int_update(s, 1);
782 break;
783
784 case 0x30: /* GPIO_CTRL */
785 s->config[1] = value & 7;
786 break;
787
788 case 0x34: /* GPIO_OE */
789 diff = s->outputs & (s->dir ^ value);
790 s->dir = value;
791
792 value = s->outputs & ~s->dir;
793 while ((ln = ffs(diff))) {
794 diff &= ~(1 <<-- ln);
795 qemu_set_irq(s->handler[ln], (value >> ln) & 1);
796 }
797
798 omap_gpio_module_level_update(s, 0);
799 omap_gpio_module_level_update(s, 1);
800 break;
801
802 case 0x3c: /* GPIO_DATAOUT */
803 omap_gpio_module_out_update(s, s->outputs ^ value);
804 break;
805
806 case 0x40: /* GPIO_LEVELDETECT0 */
807 s->level[0] = value;
808 omap_gpio_module_level_update(s, 0);
809 omap_gpio_module_level_update(s, 1);
810 break;
811
812 case 0x44: /* GPIO_LEVELDETECT1 */
813 s->level[1] = value;
814 omap_gpio_module_level_update(s, 0);
815 omap_gpio_module_level_update(s, 1);
816 break;
817
818 case 0x48: /* GPIO_RISINGDETECT */
819 s->edge[0] = value;
820 break;
821
822 case 0x4c: /* GPIO_FALLINGDETECT */
823 s->edge[1] = value;
824 break;
825
826 case 0x50: /* GPIO_DEBOUNCENABLE */
827 s->debounce = value;
828 break;
829
830 case 0x54: /* GPIO_DEBOUNCINGTIME */
831 s->delay = value;
832 break;
833
834 case 0x60: /* GPIO_CLEARIRQENABLE1 */
835 s->mask[0] &= ~value;
836 omap_gpio_module_int_update(s, 0);
837 break;
838
839 case 0x64: /* GPIO_SETIRQENABLE1 */
840 s->mask[0] |= value;
841 omap_gpio_module_int_update(s, 0);
842 break;
843
844 case 0x70: /* GPIO_CLEARIRQENABLE2 */
845 s->mask[1] &= ~value;
846 omap_gpio_module_int_update(s, 1);
847 break;
848
849 case 0x74: /* GPIO_SETIREQNEABLE2 */
850 s->mask[1] |= value;
851 omap_gpio_module_int_update(s, 1);
852 break;
853
854 case 0x80: /* GPIO_CLEARWKUENA */
855 s->wumask &= ~value;
856 break;
857
858 case 0x84: /* GPIO_SETWKUENA */
859 s->wumask |= value;
860 break;
861
862 case 0x90: /* GPIO_CLEARDATAOUT */
863 omap_gpio_module_out_update(s, s->outputs & value);
864 break;
865
866 case 0x94: /* GPIO_SETDATAOUT */
867 omap_gpio_module_out_update(s, ~s->outputs & value);
868 break;
869
870 default:
871 OMAP_BAD_REG(addr);
872 return;
873 }
874 }
875
876 static uint32_t omap_gpio_module_readp(void *opaque, target_phys_addr_t addr)
877 {
878 return omap_gpio_module_readp(opaque, addr) >> ((addr & 3) << 3);
879 }
880
881 static void omap_gpio_module_writep(void *opaque, target_phys_addr_t addr,
882 uint32_t value)
883 {
884 uint32_t cur = 0;
885 uint32_t mask = 0xffff;
886
887 switch (addr & ~3) {
888 case 0x00: /* GPIO_REVISION */
889 case 0x14: /* GPIO_SYSSTATUS */
890 case 0x38: /* GPIO_DATAIN */
891 OMAP_RO_REG(addr);
892 break;
893
894 case 0x10: /* GPIO_SYSCONFIG */
895 case 0x1c: /* GPIO_IRQENABLE1 */
896 case 0x20: /* GPIO_WAKEUPENABLE */
897 case 0x2c: /* GPIO_IRQENABLE2 */
898 case 0x30: /* GPIO_CTRL */
899 case 0x34: /* GPIO_OE */
900 case 0x3c: /* GPIO_DATAOUT */
901 case 0x40: /* GPIO_LEVELDETECT0 */
902 case 0x44: /* GPIO_LEVELDETECT1 */
903 case 0x48: /* GPIO_RISINGDETECT */
904 case 0x4c: /* GPIO_FALLINGDETECT */
905 case 0x50: /* GPIO_DEBOUNCENABLE */
906 case 0x54: /* GPIO_DEBOUNCINGTIME */
907 cur = omap_gpio_module_read(opaque, addr & ~3) &
908 ~(mask << ((addr & 3) << 3));
909
910 /* Fall through. */
911 case 0x18: /* GPIO_IRQSTATUS1 */
912 case 0x28: /* GPIO_IRQSTATUS2 */
913 case 0x60: /* GPIO_CLEARIRQENABLE1 */
914 case 0x64: /* GPIO_SETIRQENABLE1 */
915 case 0x70: /* GPIO_CLEARIRQENABLE2 */
916 case 0x74: /* GPIO_SETIREQNEABLE2 */
917 case 0x80: /* GPIO_CLEARWKUENA */
918 case 0x84: /* GPIO_SETWKUENA */
919 case 0x90: /* GPIO_CLEARDATAOUT */
920 case 0x94: /* GPIO_SETDATAOUT */
921 value <<= (addr & 3) << 3;
922 omap_gpio_module_write(opaque, addr, cur | value);
923 break;
924
925 default:
926 OMAP_BAD_REG(addr);
927 return;
928 }
929 }
930
931 static CPUReadMemoryFunc *omap_gpio_module_readfn[] = {
932 omap_gpio_module_readp,
933 omap_gpio_module_readp,
934 omap_gpio_module_read,
935 };
936
937 static CPUWriteMemoryFunc *omap_gpio_module_writefn[] = {
938 omap_gpio_module_writep,
939 omap_gpio_module_writep,
940 omap_gpio_module_write,
941 };
942
943 static void omap_gpio_module_init(struct omap2_gpio_s *s,
944 struct omap_target_agent_s *ta, int region,
945 qemu_irq mpu, qemu_irq dsp, qemu_irq wkup,
946 omap_clk fclk, omap_clk iclk)
947 {
948 int iomemtype;
949
950 s->irq[0] = mpu;
951 s->irq[1] = dsp;
952 s->wkup = wkup;
953 s->in = qemu_allocate_irqs(omap_gpio_module_set, s, 32);
954
955 iomemtype = l4_register_io_memory(0, omap_gpio_module_readfn,
956 omap_gpio_module_writefn, s);
957 omap_l4_attach(ta, region, iomemtype);
958 }
959
960 struct omap_gpif_s {
961 struct omap2_gpio_s module[5];
962 int modules;
963
964 int autoidle;
965 int gpo;
966 };
967
968 static void omap_gpif_reset(struct omap_gpif_s *s)
969 {
970 int i;
971
972 for (i = 0; i < s->modules; i ++)
973 omap_gpio_module_reset(s->module + i);
974
975 s->autoidle = 0;
976 s->gpo = 0;
977 }
978
979 static uint32_t omap_gpif_top_read(void *opaque, target_phys_addr_t addr)
980 {
981 struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
982
983 switch (addr) {
984 case 0x00: /* IPGENERICOCPSPL_REVISION */
985 return 0x18;
986
987 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
988 return s->autoidle;
989
990 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
991 return 0x01;
992
993 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
994 return 0x00;
995
996 case 0x40: /* IPGENERICOCPSPL_GPO */
997 return s->gpo;
998
999 case 0x50: /* IPGENERICOCPSPL_GPI */
1000 return 0x00;
1001 }
1002
1003 OMAP_BAD_REG(addr);
1004 return 0;
1005 }
1006
1007 static void omap_gpif_top_write(void *opaque, target_phys_addr_t addr,
1008 uint32_t value)
1009 {
1010 struct omap_gpif_s *s = (struct omap_gpif_s *) opaque;
1011
1012 switch (addr) {
1013 case 0x00: /* IPGENERICOCPSPL_REVISION */
1014 case 0x14: /* IPGENERICOCPSPL_SYSSTATUS */
1015 case 0x18: /* IPGENERICOCPSPL_IRQSTATUS */
1016 case 0x50: /* IPGENERICOCPSPL_GPI */
1017 OMAP_RO_REG(addr);
1018 break;
1019
1020 case 0x10: /* IPGENERICOCPSPL_SYSCONFIG */
1021 if (value & (1 << 1)) /* SOFTRESET */
1022 omap_gpif_reset(s);
1023 s->autoidle = value & 1;
1024 break;
1025
1026 case 0x40: /* IPGENERICOCPSPL_GPO */
1027 s->gpo = value & 1;
1028 break;
1029
1030 default:
1031 OMAP_BAD_REG(addr);
1032 return;
1033 }
1034 }
1035
1036 static CPUReadMemoryFunc *omap_gpif_top_readfn[] = {
1037 omap_gpif_top_read,
1038 omap_gpif_top_read,
1039 omap_gpif_top_read,
1040 };
1041
1042 static CPUWriteMemoryFunc *omap_gpif_top_writefn[] = {
1043 omap_gpif_top_write,
1044 omap_gpif_top_write,
1045 omap_gpif_top_write,
1046 };
1047
1048 struct omap_gpif_s *omap2_gpio_init(struct omap_target_agent_s *ta,
1049 qemu_irq *irq, omap_clk *fclk, omap_clk iclk, int modules)
1050 {
1051 int iomemtype, i;
1052 struct omap_gpif_s *s = (struct omap_gpif_s *)
1053 qemu_mallocz(sizeof(struct omap_gpif_s));
1054 int region[4] = { 0, 2, 4, 5 };
1055
1056 s->modules = modules;
1057 for (i = 0; i < modules; i ++)
1058 omap_gpio_module_init(s->module + i, ta, region[i],
1059 irq[i], 0, 0, fclk[i], iclk);
1060
1061 omap_gpif_reset(s);
1062
1063 iomemtype = l4_register_io_memory(0, omap_gpif_top_readfn,
1064 omap_gpif_top_writefn, s);
1065 omap_l4_attach(ta, 1, iomemtype);
1066
1067 return s;
1068 }
1069
1070 qemu_irq *omap2_gpio_in_get(struct omap_gpif_s *s, int start)
1071 {
1072 if (start >= s->modules * 32 || start < 0)
1073 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n",
1074 __FUNCTION__, start);
1075 return s->module[start >> 5].in + (start & 31);
1076 }
1077
1078 void omap2_gpio_out_set(struct omap_gpif_s *s, int line, qemu_irq handler)
1079 {
1080 if (line >= s->modules * 32 || line < 0)
1081 cpu_abort(cpu_single_env, "%s: No GPIO line %i\n", __FUNCTION__, line);
1082 s->module[line >> 5].handler[line & 31] = handler;
1083 }
1084
1085 /* Multichannel SPI */
1086 struct omap_mcspi_s {
1087 qemu_irq irq;
1088 int chnum;
1089
1090 uint32_t sysconfig;
1091 uint32_t systest;
1092 uint32_t irqst;
1093 uint32_t irqen;
1094 uint32_t wken;
1095 uint32_t control;
1096
1097 struct omap_mcspi_ch_s {
1098 qemu_irq txdrq;
1099 qemu_irq rxdrq;
1100 uint32_t (*txrx)(void *opaque, uint32_t, int);
1101 void *opaque;
1102
1103 uint32_t tx;
1104 uint32_t rx;
1105
1106 uint32_t config;
1107 uint32_t status;
1108 uint32_t control;
1109 } ch[4];
1110 };
1111
1112 static inline void omap_mcspi_interrupt_update(struct omap_mcspi_s *s)
1113 {
1114 qemu_set_irq(s->irq, s->irqst & s->irqen);
1115 }
1116
1117 static inline void omap_mcspi_dmarequest_update(struct omap_mcspi_ch_s *ch)
1118 {
1119 qemu_set_irq(ch->txdrq,
1120 (ch->control & 1) && /* EN */
1121 (ch->config & (1 << 14)) && /* DMAW */
1122 (ch->status & (1 << 1)) && /* TXS */
1123 ((ch->config >> 12) & 3) != 1); /* TRM */
1124 qemu_set_irq(ch->rxdrq,
1125 (ch->control & 1) && /* EN */
1126 (ch->config & (1 << 15)) && /* DMAW */
1127 (ch->status & (1 << 0)) && /* RXS */
1128 ((ch->config >> 12) & 3) != 2); /* TRM */
1129 }
1130
1131 static void omap_mcspi_transfer_run(struct omap_mcspi_s *s, int chnum)
1132 {
1133 struct omap_mcspi_ch_s *ch = s->ch + chnum;
1134
1135 if (!(ch->control & 1)) /* EN */
1136 return;
1137 if ((ch->status & (1 << 0)) && /* RXS */
1138 ((ch->config >> 12) & 3) != 2 && /* TRM */
1139 !(ch->config & (1 << 19))) /* TURBO */
1140 goto intr_update;
1141 if ((ch->status & (1 << 1)) && /* TXS */
1142 ((ch->config >> 12) & 3) != 1) /* TRM */
1143 goto intr_update;
1144
1145 if (!(s->control & 1) || /* SINGLE */
1146 (ch->config & (1 << 20))) { /* FORCE */
1147 if (ch->txrx)
1148 ch->rx = ch->txrx(ch->opaque, ch->tx, /* WL */
1149 1 + (0x1f & (ch->config >> 7)));
1150 }
1151
1152 ch->tx = 0;
1153 ch->status |= 1 << 2; /* EOT */
1154 ch->status |= 1 << 1; /* TXS */
1155 if (((ch->config >> 12) & 3) != 2) /* TRM */
1156 ch->status |= 1 << 0; /* RXS */
1157
1158 intr_update:
1159 if ((ch->status & (1 << 0)) && /* RXS */
1160 ((ch->config >> 12) & 3) != 2 && /* TRM */
1161 !(ch->config & (1 << 19))) /* TURBO */
1162 s->irqst |= 1 << (2 + 4 * chnum); /* RX_FULL */
1163 if ((ch->status & (1 << 1)) && /* TXS */
1164 ((ch->config >> 12) & 3) != 1) /* TRM */
1165 s->irqst |= 1 << (0 + 4 * chnum); /* TX_EMPTY */
1166 omap_mcspi_interrupt_update(s);
1167 omap_mcspi_dmarequest_update(ch);
1168 }
1169
1170 static void omap_mcspi_reset(struct omap_mcspi_s *s)
1171 {
1172 int ch;
1173
1174 s->sysconfig = 0;
1175 s->systest = 0;
1176 s->irqst = 0;
1177 s->irqen = 0;
1178 s->wken = 0;
1179 s->control = 4;
1180
1181 for (ch = 0; ch < 4; ch ++) {
1182 s->ch[ch].config = 0x060000;
1183 s->ch[ch].status = 2; /* TXS */
1184 s->ch[ch].control = 0;
1185
1186 omap_mcspi_dmarequest_update(s->ch + ch);
1187 }
1188
1189 omap_mcspi_interrupt_update(s);
1190 }
1191
1192 static uint32_t omap_mcspi_read(void *opaque, target_phys_addr_t addr)
1193 {
1194 struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
1195 int ch = 0;
1196 uint32_t ret;
1197
1198 switch (addr) {
1199 case 0x00: /* MCSPI_REVISION */
1200 return 0x91;
1201
1202 case 0x10: /* MCSPI_SYSCONFIG */
1203 return s->sysconfig;
1204
1205 case 0x14: /* MCSPI_SYSSTATUS */
1206 return 1; /* RESETDONE */
1207
1208 case 0x18: /* MCSPI_IRQSTATUS */
1209 return s->irqst;
1210
1211 case 0x1c: /* MCSPI_IRQENABLE */
1212 return s->irqen;
1213
1214 case 0x20: /* MCSPI_WAKEUPENABLE */
1215 return s->wken;
1216
1217 case 0x24: /* MCSPI_SYST */
1218 return s->systest;
1219
1220 case 0x28: /* MCSPI_MODULCTRL */
1221 return s->control;
1222
1223 case 0x68: ch ++;
1224 case 0x54: ch ++;
1225 case 0x40: ch ++;
1226 case 0x2c: /* MCSPI_CHCONF */
1227 return s->ch[ch].config;
1228
1229 case 0x6c: ch ++;
1230 case 0x58: ch ++;
1231 case 0x44: ch ++;
1232 case 0x30: /* MCSPI_CHSTAT */
1233 return s->ch[ch].status;
1234
1235 case 0x70: ch ++;
1236 case 0x5c: ch ++;
1237 case 0x48: ch ++;
1238 case 0x34: /* MCSPI_CHCTRL */
1239 return s->ch[ch].control;
1240
1241 case 0x74: ch ++;
1242 case 0x60: ch ++;
1243 case 0x4c: ch ++;
1244 case 0x38: /* MCSPI_TX */
1245 return s->ch[ch].tx;
1246
1247 case 0x78: ch ++;
1248 case 0x64: ch ++;
1249 case 0x50: ch ++;
1250 case 0x3c: /* MCSPI_RX */
1251 s->ch[ch].status &= ~(1 << 0); /* RXS */
1252 ret = s->ch[ch].rx;
1253 omap_mcspi_transfer_run(s, ch);
1254 return ret;
1255 }
1256
1257 OMAP_BAD_REG(addr);
1258 return 0;
1259 }
1260
1261 static void omap_mcspi_write(void *opaque, target_phys_addr_t addr,
1262 uint32_t value)
1263 {
1264 struct omap_mcspi_s *s = (struct omap_mcspi_s *) opaque;
1265 int ch = 0;
1266
1267 switch (addr) {
1268 case 0x00: /* MCSPI_REVISION */
1269 case 0x14: /* MCSPI_SYSSTATUS */
1270 case 0x30: /* MCSPI_CHSTAT0 */
1271 case 0x3c: /* MCSPI_RX0 */
1272 case 0x44: /* MCSPI_CHSTAT1 */
1273 case 0x50: /* MCSPI_RX1 */
1274 case 0x58: /* MCSPI_CHSTAT2 */
1275 case 0x64: /* MCSPI_RX2 */
1276 case 0x6c: /* MCSPI_CHSTAT3 */
1277 case 0x78: /* MCSPI_RX3 */
1278 OMAP_RO_REG(addr);
1279 return;
1280
1281 case 0x10: /* MCSPI_SYSCONFIG */
1282 if (value & (1 << 1)) /* SOFTRESET */
1283 omap_mcspi_reset(s);
1284 s->sysconfig = value & 0x31d;
1285 break;
1286
1287 case 0x18: /* MCSPI_IRQSTATUS */
1288 if (!((s->control & (1 << 3)) && (s->systest & (1 << 11)))) {
1289 s->irqst &= ~value;
1290 omap_mcspi_interrupt_update(s);
1291 }
1292 break;
1293
1294 case 0x1c: /* MCSPI_IRQENABLE */
1295 s->irqen = value & 0x1777f;
1296 omap_mcspi_interrupt_update(s);
1297 break;
1298
1299 case 0x20: /* MCSPI_WAKEUPENABLE */
1300 s->wken = value & 1;
1301 break;
1302
1303 case 0x24: /* MCSPI_SYST */
1304 if (s->control & (1 << 3)) /* SYSTEM_TEST */
1305 if (value & (1 << 11)) { /* SSB */
1306 s->irqst |= 0x1777f;
1307 omap_mcspi_interrupt_update(s);
1308 }
1309 s->systest = value & 0xfff;
1310 break;
1311
1312 case 0x28: /* MCSPI_MODULCTRL */
1313 if (value & (1 << 3)) /* SYSTEM_TEST */
1314 if (s->systest & (1 << 11)) { /* SSB */
1315 s->irqst |= 0x1777f;
1316 omap_mcspi_interrupt_update(s);
1317 }
1318 s->control = value & 0xf;
1319 break;
1320
1321 case 0x68: ch ++;
1322 case 0x54: ch ++;
1323 case 0x40: ch ++;
1324 case 0x2c: /* MCSPI_CHCONF */
1325 if ((value ^ s->ch[ch].config) & (3 << 14)) /* DMAR | DMAW */
1326 omap_mcspi_dmarequest_update(s->ch + ch);
1327 if (((value >> 12) & 3) == 3) /* TRM */
1328 fprintf(stderr, "%s: invalid TRM value (3)\n", __FUNCTION__);
1329 if (((value >> 7) & 0x1f) < 3) /* WL */
1330 fprintf(stderr, "%s: invalid WL value (%i)\n",
1331 __FUNCTION__, (value >> 7) & 0x1f);
1332 s->ch[ch].config = value & 0x7fffff;
1333 break;
1334
1335 case 0x70: ch ++;
1336 case 0x5c: ch ++;
1337 case 0x48: ch ++;
1338 case 0x34: /* MCSPI_CHCTRL */
1339 if (value & ~s->ch[ch].control & 1) { /* EN */
1340 s->ch[ch].control |= 1;
1341 omap_mcspi_transfer_run(s, ch);
1342 } else
1343 s->ch[ch].control = value & 1;
1344 break;
1345
1346 case 0x74: ch ++;
1347 case 0x60: ch ++;
1348 case 0x4c: ch ++;
1349 case 0x38: /* MCSPI_TX */
1350 s->ch[ch].tx = value;
1351 s->ch[ch].status &= ~(1 << 1); /* TXS */
1352 omap_mcspi_transfer_run(s, ch);
1353 break;
1354
1355 default:
1356 OMAP_BAD_REG(addr);
1357 return;
1358 }
1359 }
1360
1361 static CPUReadMemoryFunc *omap_mcspi_readfn[] = {
1362 omap_badwidth_read32,
1363 omap_badwidth_read32,
1364 omap_mcspi_read,
1365 };
1366
1367 static CPUWriteMemoryFunc *omap_mcspi_writefn[] = {
1368 omap_badwidth_write32,
1369 omap_badwidth_write32,
1370 omap_mcspi_write,
1371 };
1372
1373 struct omap_mcspi_s *omap_mcspi_init(struct omap_target_agent_s *ta, int chnum,
1374 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
1375 {
1376 int iomemtype;
1377 struct omap_mcspi_s *s = (struct omap_mcspi_s *)
1378 qemu_mallocz(sizeof(struct omap_mcspi_s));
1379 struct omap_mcspi_ch_s *ch = s->ch;
1380
1381 s->irq = irq;
1382 s->chnum = chnum;
1383 while (chnum --) {
1384 ch->txdrq = *drq ++;
1385 ch->rxdrq = *drq ++;
1386 ch ++;
1387 }
1388 omap_mcspi_reset(s);
1389
1390 iomemtype = l4_register_io_memory(0, omap_mcspi_readfn,
1391 omap_mcspi_writefn, s);
1392 omap_l4_attach(ta, 0, iomemtype);
1393
1394 return s;
1395 }
1396
1397 void omap_mcspi_attach(struct omap_mcspi_s *s,
1398 uint32_t (*txrx)(void *opaque, uint32_t, int), void *opaque,
1399 int chipselect)
1400 {
1401 if (chipselect < 0 || chipselect >= s->chnum)
1402 cpu_abort(cpu_single_env, "%s: Bad chipselect %i\n",
1403 __FUNCTION__, chipselect);
1404
1405 s->ch[chipselect].txrx = txrx;
1406 s->ch[chipselect].opaque = opaque;
1407 }
1408
1409 /* Enhanced Audio Controller (CODEC only) */
1410 struct omap_eac_s {
1411 qemu_irq irq;
1412
1413 uint16_t sysconfig;
1414 uint8_t config[4];
1415 uint8_t control;
1416 uint8_t address;
1417 uint16_t data;
1418 uint8_t vtol;
1419 uint8_t vtsl;
1420 uint16_t mixer;
1421 uint16_t gain[4];
1422 uint8_t att;
1423 uint16_t max[7];
1424
1425 struct {
1426 qemu_irq txdrq;
1427 qemu_irq rxdrq;
1428 uint32_t (*txrx)(void *opaque, uint32_t, int);
1429 void *opaque;
1430
1431 #define EAC_BUF_LEN 1024
1432 uint32_t rxbuf[EAC_BUF_LEN];
1433 int rxoff;
1434 int rxlen;
1435 int rxavail;
1436 uint32_t txbuf[EAC_BUF_LEN];
1437 int txlen;
1438 int txavail;
1439
1440 int enable;
1441 int rate;
1442
1443 uint16_t config[4];
1444
1445 /* These need to be moved to the actual codec */
1446 QEMUSoundCard card;
1447 SWVoiceIn *in_voice;
1448 SWVoiceOut *out_voice;
1449 int hw_enable;
1450 } codec;
1451
1452 struct {
1453 uint8_t control;
1454 uint16_t config;
1455 } modem, bt;
1456 };
1457
1458 static inline void omap_eac_interrupt_update(struct omap_eac_s *s)
1459 {
1460 qemu_set_irq(s->irq, (s->codec.config[1] >> 14) & 1); /* AURDI */
1461 }
1462
1463 static inline void omap_eac_in_dmarequest_update(struct omap_eac_s *s)
1464 {
1465 qemu_set_irq(s->codec.rxdrq, (s->codec.rxavail || s->codec.rxlen) &&
1466 ((s->codec.config[1] >> 12) & 1)); /* DMAREN */
1467 }
1468
1469 static inline void omap_eac_out_dmarequest_update(struct omap_eac_s *s)
1470 {
1471 qemu_set_irq(s->codec.txdrq, s->codec.txlen < s->codec.txavail &&
1472 ((s->codec.config[1] >> 11) & 1)); /* DMAWEN */
1473 }
1474
1475 static inline void omap_eac_in_refill(struct omap_eac_s *s)
1476 {
1477 int left = MIN(EAC_BUF_LEN - s->codec.rxlen, s->codec.rxavail) << 2;
1478 int start = ((s->codec.rxoff + s->codec.rxlen) & (EAC_BUF_LEN - 1)) << 2;
1479 int leftwrap = MIN(left, (EAC_BUF_LEN << 2) - start);
1480 int recv = 1;
1481 uint8_t *buf = (uint8_t *) s->codec.rxbuf + start;
1482
1483 left -= leftwrap;
1484 start = 0;
1485 while (leftwrap && (recv = AUD_read(s->codec.in_voice, buf + start,
1486 leftwrap)) > 0) { /* Be defensive */
1487 start += recv;
1488 leftwrap -= recv;
1489 }
1490 if (recv <= 0)
1491 s->codec.rxavail = 0;
1492 else
1493 s->codec.rxavail -= start >> 2;
1494 s->codec.rxlen += start >> 2;
1495
1496 if (recv > 0 && left > 0) {
1497 start = 0;
1498 while (left && (recv = AUD_read(s->codec.in_voice,
1499 (uint8_t *) s->codec.rxbuf + start,
1500 left)) > 0) { /* Be defensive */
1501 start += recv;
1502 left -= recv;
1503 }
1504 if (recv <= 0)
1505 s->codec.rxavail = 0;
1506 else
1507 s->codec.rxavail -= start >> 2;
1508 s->codec.rxlen += start >> 2;
1509 }
1510 }
1511
1512 static inline void omap_eac_out_empty(struct omap_eac_s *s)
1513 {
1514 int left = s->codec.txlen << 2;
1515 int start = 0;
1516 int sent = 1;
1517
1518 while (left && (sent = AUD_write(s->codec.out_voice,
1519 (uint8_t *) s->codec.txbuf + start,
1520 left)) > 0) { /* Be defensive */
1521 start += sent;
1522 left -= sent;
1523 }
1524
1525 if (!sent) {
1526 s->codec.txavail = 0;
1527 omap_eac_out_dmarequest_update(s);
1528 }
1529
1530 if (start)
1531 s->codec.txlen = 0;
1532 }
1533
1534 static void omap_eac_in_cb(void *opaque, int avail_b)
1535 {
1536 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
1537
1538 s->codec.rxavail = avail_b >> 2;
1539 omap_eac_in_refill(s);
1540 /* TODO: possibly discard current buffer if overrun */
1541 omap_eac_in_dmarequest_update(s);
1542 }
1543
1544 static void omap_eac_out_cb(void *opaque, int free_b)
1545 {
1546 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
1547
1548 s->codec.txavail = free_b >> 2;
1549 if (s->codec.txlen)
1550 omap_eac_out_empty(s);
1551 else
1552 omap_eac_out_dmarequest_update(s);
1553 }
1554
1555 static void omap_eac_enable_update(struct omap_eac_s *s)
1556 {
1557 s->codec.enable = !(s->codec.config[1] & 1) && /* EACPWD */
1558 (s->codec.config[1] & 2) && /* AUDEN */
1559 s->codec.hw_enable;
1560 }
1561
1562 static const int omap_eac_fsint[4] = {
1563 8000,
1564 11025,
1565 22050,
1566 44100,
1567 };
1568
1569 static const int omap_eac_fsint2[8] = {
1570 8000,
1571 11025,
1572 22050,
1573 44100,
1574 48000,
1575 0, 0, 0,
1576 };
1577
1578 static const int omap_eac_fsint3[16] = {
1579 8000,
1580 11025,
1581 16000,
1582 22050,
1583 24000,
1584 32000,
1585 44100,
1586 48000,
1587 0, 0, 0, 0, 0, 0, 0, 0,
1588 };
1589
1590 static void omap_eac_rate_update(struct omap_eac_s *s)
1591 {
1592 int fsint[3];
1593
1594 fsint[2] = (s->codec.config[3] >> 9) & 0xf;
1595 fsint[1] = (s->codec.config[2] >> 0) & 0x7;
1596 fsint[0] = (s->codec.config[0] >> 6) & 0x3;
1597 if (fsint[2] < 0xf)
1598 s->codec.rate = omap_eac_fsint3[fsint[2]];
1599 else if (fsint[1] < 0x7)
1600 s->codec.rate = omap_eac_fsint2[fsint[1]];
1601 else
1602 s->codec.rate = omap_eac_fsint[fsint[0]];
1603 }
1604
1605 static void omap_eac_volume_update(struct omap_eac_s *s)
1606 {
1607 /* TODO */
1608 }
1609
1610 static void omap_eac_format_update(struct omap_eac_s *s)
1611 {
1612 struct audsettings fmt;
1613
1614 /* The hardware buffers at most one sample */
1615 if (s->codec.rxlen)
1616 s->codec.rxlen = 1;
1617
1618 if (s->codec.in_voice) {
1619 AUD_set_active_in(s->codec.in_voice, 0);
1620 AUD_close_in(&s->codec.card, s->codec.in_voice);
1621 s->codec.in_voice = 0;
1622 }
1623 if (s->codec.out_voice) {
1624 omap_eac_out_empty(s);
1625 AUD_set_active_out(s->codec.out_voice, 0);
1626 AUD_close_out(&s->codec.card, s->codec.out_voice);
1627 s->codec.out_voice = 0;
1628 s->codec.txavail = 0;
1629 }
1630 /* Discard what couldn't be written */
1631 s->codec.txlen = 0;
1632
1633 omap_eac_enable_update(s);
1634 if (!s->codec.enable)
1635 return;
1636
1637 omap_eac_rate_update(s);
1638 fmt.endianness = ((s->codec.config[0] >> 8) & 1); /* LI_BI */
1639 fmt.nchannels = ((s->codec.config[0] >> 10) & 1) ? 2 : 1; /* MN_ST */
1640 fmt.freq = s->codec.rate;
1641 /* TODO: signedness possibly depends on the CODEC hardware - or
1642 * does I2S specify it? */
1643 /* All register writes are 16 bits so we we store 16-bit samples
1644 * in the buffers regardless of AGCFR[B8_16] value. */
1645 fmt.fmt = AUD_FMT_U16;
1646
1647 s->codec.in_voice = AUD_open_in(&s->codec.card, s->codec.in_voice,
1648 "eac.codec.in", s, omap_eac_in_cb, &fmt);
1649 s->codec.out_voice = AUD_open_out(&s->codec.card, s->codec.out_voice,
1650 "eac.codec.out", s, omap_eac_out_cb, &fmt);
1651
1652 omap_eac_volume_update(s);
1653
1654 AUD_set_active_in(s->codec.in_voice, 1);
1655 AUD_set_active_out(s->codec.out_voice, 1);
1656 }
1657
1658 static void omap_eac_reset(struct omap_eac_s *s)
1659 {
1660 s->sysconfig = 0;
1661 s->config[0] = 0x0c;
1662 s->config[1] = 0x09;
1663 s->config[2] = 0xab;
1664 s->config[3] = 0x03;
1665 s->control = 0x00;
1666 s->address = 0x00;
1667 s->data = 0x0000;
1668 s->vtol = 0x00;
1669 s->vtsl = 0x00;
1670 s->mixer = 0x0000;
1671 s->gain[0] = 0xe7e7;
1672 s->gain[1] = 0x6767;
1673 s->gain[2] = 0x6767;
1674 s->gain[3] = 0x6767;
1675 s->att = 0xce;
1676 s->max[0] = 0;
1677 s->max[1] = 0;
1678 s->max[2] = 0;
1679 s->max[3] = 0;
1680 s->max[4] = 0;
1681 s->max[5] = 0;
1682 s->max[6] = 0;
1683
1684 s->modem.control = 0x00;
1685 s->modem.config = 0x0000;
1686 s->bt.control = 0x00;
1687 s->bt.config = 0x0000;
1688 s->codec.config[0] = 0x0649;
1689 s->codec.config[1] = 0x0000;
1690 s->codec.config[2] = 0x0007;
1691 s->codec.config[3] = 0x1ffc;
1692 s->codec.rxoff = 0;
1693 s->codec.rxlen = 0;
1694 s->codec.txlen = 0;
1695 s->codec.rxavail = 0;
1696 s->codec.txavail = 0;
1697
1698 omap_eac_format_update(s);
1699 omap_eac_interrupt_update(s);
1700 }
1701
1702 static uint32_t omap_eac_read(void *opaque, target_phys_addr_t addr)
1703 {
1704 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
1705 uint32_t ret;
1706
1707 switch (addr) {
1708 case 0x000: /* CPCFR1 */
1709 return s->config[0];
1710 case 0x004: /* CPCFR2 */
1711 return s->config[1];
1712 case 0x008: /* CPCFR3 */
1713 return s->config[2];
1714 case 0x00c: /* CPCFR4 */
1715 return s->config[3];
1716
1717 case 0x010: /* CPTCTL */
1718 return s->control | ((s->codec.rxavail + s->codec.rxlen > 0) << 7) |
1719 ((s->codec.txlen < s->codec.txavail) << 5);
1720
1721 case 0x014: /* CPTTADR */
1722 return s->address;
1723 case 0x018: /* CPTDATL */
1724 return s->data & 0xff;
1725 case 0x01c: /* CPTDATH */
1726 return s->data >> 8;
1727 case 0x020: /* CPTVSLL */
1728 return s->vtol;
1729 case 0x024: /* CPTVSLH */
1730 return s->vtsl | (3 << 5); /* CRDY1 | CRDY2 */
1731 case 0x040: /* MPCTR */
1732 return s->modem.control;
1733 case 0x044: /* MPMCCFR */
1734 return s->modem.config;
1735 case 0x060: /* BPCTR */
1736 return s->bt.control;
1737 case 0x064: /* BPMCCFR */
1738 return s->bt.config;
1739 case 0x080: /* AMSCFR */
1740 return s->mixer;
1741 case 0x084: /* AMVCTR */
1742 return s->gain[0];
1743 case 0x088: /* AM1VCTR */
1744 return s->gain[1];
1745 case 0x08c: /* AM2VCTR */
1746 return s->gain[2];
1747 case 0x090: /* AM3VCTR */
1748 return s->gain[3];
1749 case 0x094: /* ASTCTR */
1750 return s->att;
1751 case 0x098: /* APD1LCR */
1752 return s->max[0];
1753 case 0x09c: /* APD1RCR */
1754 return s->max[1];
1755 case 0x0a0: /* APD2LCR */
1756 return s->max[2];
1757 case 0x0a4: /* APD2RCR */
1758 return s->max[3];
1759 case 0x0a8: /* APD3LCR */
1760 return s->max[4];
1761 case 0x0ac: /* APD3RCR */
1762 return s->max[5];
1763 case 0x0b0: /* APD4R */
1764 return s->max[6];
1765 case 0x0b4: /* ADWR */
1766 /* This should be write-only? Docs list it as read-only. */
1767 return 0x0000;
1768 case 0x0b8: /* ADRDR */
1769 if (likely(s->codec.rxlen > 1)) {
1770 ret = s->codec.rxbuf[s->codec.rxoff ++];
1771 s->codec.rxlen --;
1772 s->codec.rxoff &= EAC_BUF_LEN - 1;
1773 return ret;
1774 } else if (s->codec.rxlen) {
1775 ret = s->codec.rxbuf[s->codec.rxoff ++];
1776 s->codec.rxlen --;
1777 s->codec.rxoff &= EAC_BUF_LEN - 1;
1778 if (s->codec.rxavail)
1779 omap_eac_in_refill(s);
1780 omap_eac_in_dmarequest_update(s);
1781 return ret;
1782 }
1783 return 0x0000;
1784 case 0x0bc: /* AGCFR */
1785 return s->codec.config[0];
1786 case 0x0c0: /* AGCTR */
1787 return s->codec.config[1] | ((s->codec.config[1] & 2) << 14);
1788 case 0x0c4: /* AGCFR2 */
1789 return s->codec.config[2];
1790 case 0x0c8: /* AGCFR3 */
1791 return s->codec.config[3];
1792 case 0x0cc: /* MBPDMACTR */
1793 case 0x0d0: /* MPDDMARR */
1794 case 0x0d8: /* MPUDMARR */
1795 case 0x0e4: /* BPDDMARR */
1796 case 0x0ec: /* BPUDMARR */
1797 return 0x0000;
1798
1799 case 0x100: /* VERSION_NUMBER */
1800 return 0x0010;
1801
1802 case 0x104: /* SYSCONFIG */
1803 return s->sysconfig;
1804
1805 case 0x108: /* SYSSTATUS */
1806 return 1 | 0xe; /* RESETDONE | stuff */
1807 }
1808
1809 OMAP_BAD_REG(addr);
1810 return 0;
1811 }
1812
1813 static void omap_eac_write(void *opaque, target_phys_addr_t addr,
1814 uint32_t value)
1815 {
1816 struct omap_eac_s *s = (struct omap_eac_s *) opaque;
1817
1818 switch (addr) {
1819 case 0x098: /* APD1LCR */
1820 case 0x09c: /* APD1RCR */
1821 case 0x0a0: /* APD2LCR */
1822 case 0x0a4: /* APD2RCR */
1823 case 0x0a8: /* APD3LCR */
1824 case 0x0ac: /* APD3RCR */
1825 case 0x0b0: /* APD4R */
1826 case 0x0b8: /* ADRDR */
1827 case 0x0d0: /* MPDDMARR */
1828 case 0x0d8: /* MPUDMARR */
1829 case 0x0e4: /* BPDDMARR */
1830 case 0x0ec: /* BPUDMARR */
1831 case 0x100: /* VERSION_NUMBER */
1832 case 0x108: /* SYSSTATUS */
1833 OMAP_RO_REG(addr);
1834 return;
1835
1836 case 0x000: /* CPCFR1 */
1837 s->config[0] = value & 0xff;
1838 omap_eac_format_update(s);
1839 break;
1840 case 0x004: /* CPCFR2 */
1841 s->config[1] = value & 0xff;
1842 omap_eac_format_update(s);
1843 break;
1844 case 0x008: /* CPCFR3 */
1845 s->config[2] = value & 0xff;
1846 omap_eac_format_update(s);
1847 break;
1848 case 0x00c: /* CPCFR4 */
1849 s->config[3] = value & 0xff;
1850 omap_eac_format_update(s);
1851 break;
1852
1853 case 0x010: /* CPTCTL */
1854 /* Assuming TXF and TXE bits are read-only... */
1855 s->control = value & 0x5f;
1856 omap_eac_interrupt_update(s);
1857 break;
1858
1859 case 0x014: /* CPTTADR */
1860 s->address = value & 0xff;
1861 break;
1862 case 0x018: /* CPTDATL */
1863 s->data &= 0xff00;
1864 s->data |= value & 0xff;
1865 break;
1866 case 0x01c: /* CPTDATH */
1867 s->data &= 0x00ff;
1868 s->data |= value << 8;
1869 break;
1870 case 0x020: /* CPTVSLL */
1871 s->vtol = value & 0xf8;
1872 break;
1873 case 0x024: /* CPTVSLH */
1874 s->vtsl = value & 0x9f;
1875 break;
1876 case 0x040: /* MPCTR */
1877 s->modem.control = value & 0x8f;
1878 break;
1879 case 0x044: /* MPMCCFR */
1880 s->modem.config = value & 0x7fff;
1881 break;
1882 case 0x060: /* BPCTR */
1883 s->bt.control = value & 0x8f;
1884 break;
1885 case 0x064: /* BPMCCFR */
1886 s->bt.config = value & 0x7fff;
1887 break;
1888 case 0x080: /* AMSCFR */
1889 s->mixer = value & 0x0fff;
1890 break;
1891 case 0x084: /* AMVCTR */
1892 s->gain[0] = value & 0xffff;
1893 break;
1894 case 0x088: /* AM1VCTR */
1895 s->gain[1] = value & 0xff7f;
1896 break;
1897 case 0x08c: /* AM2VCTR */
1898 s->gain[2] = value & 0xff7f;
1899 break;
1900 case 0x090: /* AM3VCTR */
1901 s->gain[3] = value & 0xff7f;
1902 break;
1903 case 0x094: /* ASTCTR */
1904 s->att = value & 0xff;
1905 break;
1906
1907 case 0x0b4: /* ADWR */
1908 s->codec.txbuf[s->codec.txlen ++] = value;
1909 if (unlikely(s->codec.txlen == EAC_BUF_LEN ||
1910 s->codec.txlen == s->codec.txavail)) {
1911 if (s->codec.txavail)
1912 omap_eac_out_empty(s);
1913 /* Discard what couldn't be written */
1914 s->codec.txlen = 0;
1915 }
1916 break;
1917
1918 case 0x0bc: /* AGCFR */
1919 s->codec.config[0] = value & 0x07ff;
1920 omap_eac_format_update(s);
1921 break;
1922 case 0x0c0: /* AGCTR */
1923 s->codec.config[1] = value & 0x780f;
1924 omap_eac_format_update(s);
1925 break;
1926 case 0x0c4: /* AGCFR2 */
1927 s->codec.config[2] = value & 0x003f;
1928 omap_eac_format_update(s);
1929 break;
1930 case 0x0c8: /* AGCFR3 */
1931 s->codec.config[3] = value & 0xffff;
1932 omap_eac_format_update(s);
1933 break;
1934 case 0x0cc: /* MBPDMACTR */
1935 case 0x0d4: /* MPDDMAWR */
1936 case 0x0e0: /* MPUDMAWR */
1937 case 0x0e8: /* BPDDMAWR */
1938 case 0x0f0: /* BPUDMAWR */
1939 break;
1940
1941 case 0x104: /* SYSCONFIG */
1942 if (value & (1 << 1)) /* SOFTRESET */
1943 omap_eac_reset(s);
1944 s->sysconfig = value & 0x31d;
1945 break;
1946
1947 default:
1948 OMAP_BAD_REG(addr);
1949 return;
1950 }
1951 }
1952
1953 static CPUReadMemoryFunc *omap_eac_readfn[] = {
1954 omap_badwidth_read16,
1955 omap_eac_read,
1956 omap_badwidth_read16,
1957 };
1958
1959 static CPUWriteMemoryFunc *omap_eac_writefn[] = {
1960 omap_badwidth_write16,
1961 omap_eac_write,
1962 omap_badwidth_write16,
1963 };
1964
1965 struct omap_eac_s *omap_eac_init(struct omap_target_agent_s *ta,
1966 qemu_irq irq, qemu_irq *drq, omap_clk fclk, omap_clk iclk)
1967 {
1968 int iomemtype;
1969 struct omap_eac_s *s = (struct omap_eac_s *)
1970 qemu_mallocz(sizeof(struct omap_eac_s));
1971
1972 s->irq = irq;
1973 s->codec.rxdrq = *drq ++;
1974 s->codec.txdrq = *drq ++;
1975 omap_eac_reset(s);
1976
1977 #ifdef HAS_AUDIO
1978 /* TODO: do AUD_init globally for machine */
1979 AUD_register_card(AUD_init(), "OMAP EAC", &s->codec.card);
1980
1981 iomemtype = cpu_register_io_memory(0, omap_eac_readfn,
1982 omap_eac_writefn, s);
1983 omap_l4_attach(ta, 0, iomemtype);
1984 #endif
1985
1986 return s;
1987 }
1988
1989 /* STI/XTI (emulation interface) console - reverse engineered only */
1990 struct omap_sti_s {
1991 qemu_irq irq;
1992 CharDriverState *chr;
1993
1994 uint32_t sysconfig;
1995 uint32_t systest;
1996 uint32_t irqst;
1997 uint32_t irqen;
1998 uint32_t clkcontrol;
1999 uint32_t serial_config;
2000 };
2001
2002 #define STI_TRACE_CONSOLE_CHANNEL 239
2003 #define STI_TRACE_CONTROL_CHANNEL 253
2004
2005 static inline void omap_sti_interrupt_update(struct omap_sti_s *s)
2006 {
2007 qemu_set_irq(s->irq, s->irqst & s->irqen);
2008 }
2009
2010 static void omap_sti_reset(struct omap_sti_s *s)
2011 {
2012 s->sysconfig = 0;
2013 s->irqst = 0;
2014 s->irqen = 0;
2015 s->clkcontrol = 0;
2016 s->serial_config = 0;
2017
2018 omap_sti_interrupt_update(s);
2019 }
2020
2021 static uint32_t omap_sti_read(void *opaque, target_phys_addr_t addr)
2022 {
2023 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
2024
2025 switch (addr) {
2026 case 0x00: /* STI_REVISION */
2027 return 0x10;
2028
2029 case 0x10: /* STI_SYSCONFIG */
2030 return s->sysconfig;
2031
2032 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
2033 return 0x00;
2034
2035 case 0x18: /* STI_IRQSTATUS */
2036 return s->irqst;
2037
2038 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
2039 return s->irqen;
2040
2041 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
2042 case 0x28: /* STI_RX_DR / XTI_RXDATA */
2043 /* TODO */
2044 return 0;
2045
2046 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
2047 return s->clkcontrol;
2048
2049 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
2050 return s->serial_config;
2051 }
2052
2053 OMAP_BAD_REG(addr);
2054 return 0;
2055 }
2056
2057 static void omap_sti_write(void *opaque, target_phys_addr_t addr,
2058 uint32_t value)
2059 {
2060 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
2061
2062 switch (addr) {
2063 case 0x00: /* STI_REVISION */
2064 case 0x14: /* STI_SYSSTATUS / STI_RX_STATUS / XTI_SYSSTATUS */
2065 OMAP_RO_REG(addr);
2066 return;
2067
2068 case 0x10: /* STI_SYSCONFIG */
2069 if (value & (1 << 1)) /* SOFTRESET */
2070 omap_sti_reset(s);
2071 s->sysconfig = value & 0xfe;
2072 break;
2073
2074 case 0x18: /* STI_IRQSTATUS */
2075 s->irqst &= ~value;
2076 omap_sti_interrupt_update(s);
2077 break;
2078
2079 case 0x1c: /* STI_IRQSETEN / STI_IRQCLREN */
2080 s->irqen = value & 0xffff;
2081 omap_sti_interrupt_update(s);
2082 break;
2083
2084 case 0x2c: /* STI_CLK_CTRL / XTI_SCLKCRTL */
2085 s->clkcontrol = value & 0xff;
2086 break;
2087
2088 case 0x30: /* STI_SERIAL_CFG / XTI_SCONFIG */
2089 s->serial_config = value & 0xff;
2090 break;
2091
2092 case 0x24: /* STI_ER / STI_DR / XTI_TRACESELECT */
2093 case 0x28: /* STI_RX_DR / XTI_RXDATA */
2094 /* TODO */
2095 return;
2096
2097 default:
2098 OMAP_BAD_REG(addr);
2099 return;
2100 }
2101 }
2102
2103 static CPUReadMemoryFunc *omap_sti_readfn[] = {
2104 omap_badwidth_read32,
2105 omap_badwidth_read32,
2106 omap_sti_read,
2107 };
2108
2109 static CPUWriteMemoryFunc *omap_sti_writefn[] = {
2110 omap_badwidth_write32,
2111 omap_badwidth_write32,
2112 omap_sti_write,
2113 };
2114
2115 static uint32_t omap_sti_fifo_read(void *opaque, target_phys_addr_t addr)
2116 {
2117 OMAP_BAD_REG(addr);
2118 return 0;
2119 }
2120
2121 static void omap_sti_fifo_write(void *opaque, target_phys_addr_t addr,
2122 uint32_t value)
2123 {
2124 struct omap_sti_s *s = (struct omap_sti_s *) opaque;
2125 int ch = addr >> 6;
2126 uint8_t byte = value;
2127
2128 if (ch == STI_TRACE_CONTROL_CHANNEL) {
2129 /* Flush channel <i>value</i>. */
2130 qemu_chr_write(s->chr, (const uint8_t *) "\r", 1);
2131 } else if (ch == STI_TRACE_CONSOLE_CHANNEL || 1) {
2132 if (value == 0xc0 || value == 0xc3) {
2133 /* Open channel <i>ch</i>. */
2134 } else if (value == 0x00)
2135 qemu_chr_write(s->chr, (const uint8_t *) "\n", 1);
2136 else
2137 qemu_chr_write(s->chr, &byte, 1);
2138 }
2139 }
2140
2141 static CPUReadMemoryFunc *omap_sti_fifo_readfn[] = {
2142 omap_sti_fifo_read,
2143 omap_badwidth_read8,
2144 omap_badwidth_read8,
2145 };
2146
2147 static CPUWriteMemoryFunc *omap_sti_fifo_writefn[] = {
2148 omap_sti_fifo_write,
2149 omap_badwidth_write8,
2150 omap_badwidth_write8,
2151 };
2152
2153 static struct omap_sti_s *omap_sti_init(struct omap_target_agent_s *ta,
2154 target_phys_addr_t channel_base, qemu_irq irq, omap_clk clk,
2155 CharDriverState *chr)
2156 {
2157 int iomemtype;
2158 struct omap_sti_s *s = (struct omap_sti_s *)
2159 qemu_mallocz(sizeof(struct omap_sti_s));
2160
2161 s->irq = irq;
2162 omap_sti_reset(s);
2163
2164 s->chr = chr ?: qemu_chr_open("null", "null", NULL);
2165
2166 iomemtype = l4_register_io_memory(0, omap_sti_readfn,
2167 omap_sti_writefn, s);
2168 omap_l4_attach(ta, 0, iomemtype);
2169
2170 iomemtype = cpu_register_io_memory(0, omap_sti_fifo_readfn,
2171 omap_sti_fifo_writefn, s);
2172 cpu_register_physical_memory(channel_base, 0x10000, iomemtype);
2173
2174 return s;
2175 }
2176
2177 /* L4 Interconnect */
2178 struct omap_target_agent_s {
2179 struct omap_l4_s *bus;
2180 int regions;
2181 struct omap_l4_region_s *start;
2182 target_phys_addr_t base;
2183 uint32_t component;
2184 uint32_t control;
2185 uint32_t status;
2186 };
2187
2188 struct omap_l4_s {
2189 target_phys_addr_t base;
2190 int ta_num;
2191 struct omap_target_agent_s ta[0];
2192 };
2193
2194 #ifdef L4_MUX_HACK
2195 static int omap_l4_io_entries;
2196 static int omap_cpu_io_entry;
2197 static struct omap_l4_entry {
2198 CPUReadMemoryFunc **mem_read;
2199 CPUWriteMemoryFunc **mem_write;
2200 void *opaque;
2201 } *omap_l4_io_entry;
2202 static CPUReadMemoryFunc **omap_l4_io_readb_fn;
2203 static CPUReadMemoryFunc **omap_l4_io_readh_fn;
2204 static CPUReadMemoryFunc **omap_l4_io_readw_fn;
2205 static CPUWriteMemoryFunc **omap_l4_io_writeb_fn;
2206 static CPUWriteMemoryFunc **omap_l4_io_writeh_fn;
2207 static CPUWriteMemoryFunc **omap_l4_io_writew_fn;
2208 static void **omap_l4_io_opaque;
2209
2210 int l4_register_io_memory(int io_index, CPUReadMemoryFunc **mem_read,
2211 CPUWriteMemoryFunc **mem_write, void *opaque)
2212 {
2213 omap_l4_io_entry[omap_l4_io_entries].mem_read = mem_read;
2214 omap_l4_io_entry[omap_l4_io_entries].mem_write = mem_write;
2215 omap_l4_io_entry[omap_l4_io_entries].opaque = opaque;
2216
2217 return omap_l4_io_entries ++;
2218 }
2219
2220 static uint32_t omap_l4_io_readb(void *opaque, target_phys_addr_t addr)
2221 {
2222 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2223
2224 return omap_l4_io_readb_fn[i](omap_l4_io_opaque[i], addr);
2225 }
2226
2227 static uint32_t omap_l4_io_readh(void *opaque, target_phys_addr_t addr)
2228 {
2229 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2230
2231 return omap_l4_io_readh_fn[i](omap_l4_io_opaque[i], addr);
2232 }
2233
2234 static uint32_t omap_l4_io_readw(void *opaque, target_phys_addr_t addr)
2235 {
2236 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2237
2238 return omap_l4_io_readw_fn[i](omap_l4_io_opaque[i], addr);
2239 }
2240
2241 static void omap_l4_io_writeb(void *opaque, target_phys_addr_t addr,
2242 uint32_t value)
2243 {
2244 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2245
2246 return omap_l4_io_writeb_fn[i](omap_l4_io_opaque[i], addr, value);
2247 }
2248
2249 static void omap_l4_io_writeh(void *opaque, target_phys_addr_t addr,
2250 uint32_t value)
2251 {
2252 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2253
2254 return omap_l4_io_writeh_fn[i](omap_l4_io_opaque[i], addr, value);
2255 }
2256
2257 static void omap_l4_io_writew(void *opaque, target_phys_addr_t addr,
2258 uint32_t value)
2259 {
2260 unsigned int i = (addr - OMAP2_L4_BASE) >> TARGET_PAGE_BITS;
2261
2262 return omap_l4_io_writew_fn[i](omap_l4_io_opaque[i], addr, value);
2263 }
2264
2265 static CPUReadMemoryFunc *omap_l4_io_readfn[] = {
2266 omap_l4_io_readb,
2267 omap_l4_io_readh,
2268 omap_l4_io_readw,
2269 };
2270
2271 static CPUWriteMemoryFunc *omap_l4_io_writefn[] = {
2272 omap_l4_io_writeb,
2273 omap_l4_io_writeh,
2274 omap_l4_io_writew,
2275 };
2276 #endif
2277
2278 struct omap_l4_s *omap_l4_init(target_phys_addr_t base, int ta_num)
2279 {
2280 struct omap_l4_s *bus = qemu_mallocz(
2281 sizeof(*bus) + ta_num * sizeof(*bus->ta));
2282
2283 bus->ta_num = ta_num;
2284 bus->base = base;
2285
2286 #ifdef L4_MUX_HACK
2287 omap_l4_io_entries = 1;
2288 omap_l4_io_entry = qemu_mallocz(125 * sizeof(*omap_l4_io_entry));
2289
2290 omap_cpu_io_entry =
2291 cpu_register_io_memory(0, omap_l4_io_readfn,
2292 omap_l4_io_writefn, bus);
2293 # define L4_PAGES (0xb4000 / TARGET_PAGE_SIZE)
2294 omap_l4_io_readb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2295 omap_l4_io_readh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2296 omap_l4_io_readw_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2297 omap_l4_io_writeb_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2298 omap_l4_io_writeh_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2299 omap_l4_io_writew_fn = qemu_mallocz(sizeof(void *) * L4_PAGES);
2300 omap_l4_io_opaque = qemu_mallocz(sizeof(void *) * L4_PAGES);
2301 #endif
2302
2303 return bus;
2304 }
2305
2306 static uint32_t omap_l4ta_read(void *opaque, target_phys_addr_t addr)
2307 {
2308 struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
2309
2310 switch (addr) {
2311 case 0x00: /* COMPONENT */
2312 return s->component;
2313
2314 case 0x20: /* AGENT_CONTROL */
2315 return s->control;
2316
2317 case 0x28: /* AGENT_STATUS */
2318 return s->status;
2319 }
2320
2321 OMAP_BAD_REG(addr);
2322 return 0;
2323 }
2324
2325 static void omap_l4ta_write(void *opaque, target_phys_addr_t addr,
2326 uint32_t value)
2327 {
2328 struct omap_target_agent_s *s = (struct omap_target_agent_s *) opaque;
2329
2330 switch (addr) {
2331 case 0x00: /* COMPONENT */
2332 case 0x28: /* AGENT_STATUS */
2333 OMAP_RO_REG(addr);
2334 break;
2335
2336 case 0x20: /* AGENT_CONTROL */
2337 s->control = value & 0x01000700;
2338 if (value & 1) /* OCP_RESET */
2339 s->status &= ~1; /* REQ_TIMEOUT */
2340 break;
2341
2342 default:
2343 OMAP_BAD_REG(addr);
2344 }
2345 }
2346
2347 static CPUReadMemoryFunc *omap_l4ta_readfn[] = {
2348 omap_badwidth_read16,
2349 omap_l4ta_read,
2350 omap_badwidth_read16,
2351 };
2352
2353 static CPUWriteMemoryFunc *omap_l4ta_writefn[] = {
2354 omap_badwidth_write32,
2355 omap_badwidth_write32,
2356 omap_l4ta_write,
2357 };
2358
2359 #define L4TA(n) (n)
2360 #define L4TAO(n) ((n) + 39)
2361
2362 static struct omap_l4_region_s {
2363 target_phys_addr_t offset;
2364 size_t size;
2365 int access;
2366 } omap_l4_region[125] = {
2367 [ 1] = { 0x40800, 0x800, 32 }, /* Initiator agent */
2368 [ 2] = { 0x41000, 0x1000, 32 }, /* Link agent */
2369 [ 0] = { 0x40000, 0x800, 32 }, /* Address and protection */
2370 [ 3] = { 0x00000, 0x1000, 32 | 16 | 8 }, /* System Control and Pinout */
2371 [ 4] = { 0x01000, 0x1000, 32 | 16 | 8 }, /* L4TAO1 */
2372 [ 5] = { 0x04000, 0x1000, 32 | 16 }, /* 32K Timer */
2373 [ 6] = { 0x05000, 0x1000, 32 | 16 | 8 }, /* L4TAO2 */
2374 [ 7] = { 0x08000, 0x800, 32 }, /* PRCM Region A */
2375 [ 8] = { 0x08800, 0x800, 32 }, /* PRCM Region B */
2376 [ 9] = { 0x09000, 0x1000, 32 | 16 | 8 }, /* L4TAO */
2377 [ 10] = { 0x12000, 0x1000, 32 | 16 | 8 }, /* Test (BCM) */
2378 [ 11] = { 0x13000, 0x1000, 32 | 16 | 8 }, /* L4TA1 */
2379 [ 12] = { 0x14000, 0x1000, 32 }, /* Test/emulation (TAP) */
2380 [ 13] = { 0x15000, 0x1000, 32 | 16 | 8 }, /* L4TA2 */
2381 [ 14] = { 0x18000, 0x1000, 32 | 16 | 8 }, /* GPIO1 */
2382 [ 16] = { 0x1a000, 0x1000, 32 | 16 | 8 }, /* GPIO2 */
2383 [ 18] = { 0x1c000, 0x1000, 32 | 16 | 8 }, /* GPIO3 */
2384 [ 19] = { 0x1e000, 0x1000, 32 | 16 | 8 }, /* GPIO4 */
2385 [ 15] = { 0x19000, 0x1000, 32 | 16 | 8 }, /* Quad GPIO TOP */
2386 [ 17] = { 0x1b000, 0x1000, 32 | 16 | 8 }, /* L4TA3 */
2387 [ 20] = { 0x20000, 0x1000, 32 | 16 | 8 }, /* WD Timer 1 (Secure) */
2388 [ 22] = { 0x22000, 0x1000, 32 | 16 | 8 }, /* WD Timer 2 (OMAP) */
2389 [ 21] = { 0x21000, 0x1000, 32 | 16 | 8 }, /* Dual WD timer TOP */
2390 [ 23] = { 0x23000, 0x1000, 32 | 16 | 8 }, /* L4TA4 */
2391 [ 24] = { 0x28000, 0x1000, 32 | 16 | 8 }, /* GP Timer 1 */
2392 [ 25] = { 0x29000, 0x1000, 32 | 16 | 8 }, /* L4TA7 */
2393 [ 26] = { 0x48000, 0x2000, 32 | 16 | 8 }, /* Emulation (ARM11ETB) */
2394 [ 27] = { 0x4a000, 0x1000, 32 | 16 | 8 }, /* L4TA9 */
2395 [ 28] = { 0x50000, 0x400, 32 | 16 | 8 }, /* Display top */
2396 [ 29] = { 0x50400, 0x400, 32 | 16 | 8 }, /* Display control */
2397 [ 30] = { 0x50800, 0x400, 32 | 16 | 8 }, /* Display RFBI */
2398 [ 31] = { 0x50c00, 0x400, 32 | 16 | 8 }, /* Display encoder */
2399 [ 32] = { 0x51000, 0x1000, 32 | 16 | 8 }, /* L4TA10 */
2400 [ 33] = { 0x52000, 0x400, 32 | 16 | 8 }, /* Camera top */
2401 [ 34] = { 0x52400, 0x400, 32 | 16 | 8 }, /* Camera core */
2402 [ 35] = { 0x52800, 0x400, 32 | 16 | 8 }, /* Camera DMA */
2403 [ 36] = { 0x52c00, 0x400, 32 | 16 | 8 }, /* Camera MMU */
2404 [ 37] = { 0x53000, 0x1000, 32 | 16 | 8 }, /* L4TA11 */
2405 [ 38] = { 0x56000, 0x1000, 32 | 16 | 8 }, /* sDMA */
2406 [ 39] = { 0x57000, 0x1000, 32 | 16 | 8 }, /* L4TA12 */
2407 [ 40] = { 0x58000, 0x1000, 32 | 16 | 8 }, /* SSI top */
2408 [ 41] = { 0x59000, 0x1000, 32 | 16 | 8 }, /* SSI GDD */
2409 [ 42] = { 0x5a000, 0x1000, 32 | 16 | 8 }, /* SSI Port1 */
2410 [ 43] = { 0x5b000, 0x1000, 32 | 16 | 8 }, /* SSI Port2 */
2411 [ 44] = { 0x5c000, 0x1000, 32 | 16 | 8 }, /* L4TA13 */
2412 [ 45] = { 0x5e000, 0x1000, 32 | 16 | 8 }, /* USB OTG */
2413 [ 46] = { 0x5f000, 0x1000, 32 | 16 | 8 }, /* L4TAO4 */
2414 [ 47] = { 0x60000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER1SDRC) */
2415 [ 48] = { 0x61000, 0x1000, 32 | 16 | 8 }, /* L4TA14 */
2416 [ 49] = { 0x62000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER2GPMC) */
2417 [ 50] = { 0x63000, 0x1000, 32 | 16 | 8 }, /* L4TA15 */
2418 [ 51] = { 0x64000, 0x1000, 32 | 16 | 8 }, /* Emulation (WIN_TRACER3OCM) */
2419 [ 52] = { 0x65000, 0x1000, 32 | 16 | 8 }, /* L4TA16 */
2420 [ 53] = { 0x66000, 0x300, 32 | 16 | 8 }, /* Emulation (WIN_TRACER4L4) */
2421 [ 54] = { 0x67000, 0x1000, 32 | 16 | 8 }, /* L4TA17 */
2422 [ 55] = { 0x68000, 0x1000, 32 | 16 | 8 }, /* Emulation (XTI) */
2423 [ 56] = { 0x69000, 0x1000, 32 | 16 | 8 }, /* L4TA18 */
2424 [ 57] = { 0x6a000, 0x1000, 16 | 8 }, /* UART1 */
2425 [ 58] = { 0x6b000, 0x1000, 32 | 16 | 8 }, /* L4TA19 */
2426 [ 59] = { 0x6c000, 0x1000, 16 | 8 }, /* UART2 */
2427 [ 60] = { 0x6d000, 0x1000, 32 | 16 | 8 }, /* L4TA20 */
2428 [ 61] = { 0x6e000, 0x1000, 16 | 8 }, /* UART3 */
2429 [ 62] = { 0x6f000, 0x1000, 32 | 16 | 8 }, /* L4TA21 */
2430 [ 63] = { 0x70000, 0x1000, 16 }, /* I2C1 */
2431 [ 64] = { 0x71000, 0x1000, 32 | 16 | 8 }, /* L4TAO5 */
2432 [ 65] = { 0x72000, 0x1000, 16 }, /* I2C2 */
2433 [ 66] = { 0x73000, 0x1000, 32 | 16 | 8 }, /* L4TAO6 */
2434 [ 67] = { 0x74000, 0x1000, 16 }, /* McBSP1 */
2435 [ 68] = { 0x75000, 0x1000, 32 | 16 | 8 }, /* L4TAO7 */
2436 [ 69] = { 0x76000, 0x1000, 16 }, /* McBSP2 */
2437 [ 70] = { 0x77000, 0x1000, 32 | 16 | 8 }, /* L4TAO8 */
2438 [ 71] = { 0x24000, 0x1000, 32 | 16 | 8 }, /* WD Timer 3 (DSP) */
2439 [ 72] = { 0x25000, 0x1000, 32 | 16 | 8 }, /* L4TA5 */
2440 [ 73] = { 0x26000, 0x1000, 32 | 16 | 8 }, /* WD Timer 4 (IVA) */
2441 [ 74] = { 0x27000, 0x1000, 32 | 16 | 8 }, /* L4TA6 */
2442 [ 75] = { 0x2a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 2 */
2443 [ 76] = { 0x2b000, 0x1000, 32 | 16 | 8 }, /* L4TA8 */
2444 [ 77] = { 0x78000, 0x1000, 32 | 16 | 8 }, /* GP Timer 3 */
2445 [ 78] = { 0x79000, 0x1000, 32 | 16 | 8 }, /* L4TA22 */
2446 [ 79] = { 0x7a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 4 */
2447 [ 80] = { 0x7b000, 0x1000, 32 | 16 | 8 }, /* L4TA23 */
2448 [ 81] = { 0x7c000, 0x1000, 32 | 16 | 8 }, /* GP Timer 5 */
2449 [ 82] = { 0x7d000, 0x1000, 32 | 16 | 8 }, /* L4TA24 */
2450 [ 83] = { 0x7e000, 0x1000, 32 | 16 | 8 }, /* GP Timer 6 */
2451 [ 84] = { 0x7f000, 0x1000, 32 | 16 | 8 }, /* L4TA25 */
2452 [ 85] = { 0x80000, 0x1000, 32 | 16 | 8 }, /* GP Timer 7 */
2453 [ 86] = { 0x81000, 0x1000, 32 | 16 | 8 }, /* L4TA26 */
2454 [ 87] = { 0x82000, 0x1000, 32 | 16 | 8 }, /* GP Timer 8 */
2455 [ 88] = { 0x83000, 0x1000, 32 | 16 | 8 }, /* L4TA27 */
2456 [ 89] = { 0x84000, 0x1000, 32 | 16 | 8 }, /* GP Timer 9 */
2457 [ 90] = { 0x85000, 0x1000, 32 | 16 | 8 }, /* L4TA28 */
2458 [ 91] = { 0x86000, 0x1000, 32 | 16 | 8 }, /* GP Timer 10 */
2459 [ 92] = { 0x87000, 0x1000, 32 | 16 | 8 }, /* L4TA29 */
2460 [ 93] = { 0x88000, 0x1000, 32 | 16 | 8 }, /* GP Timer 11 */
2461 [ 94] = { 0x89000, 0x1000, 32 | 16 | 8 }, /* L4TA30 */
2462 [ 95] = { 0x8a000, 0x1000, 32 | 16 | 8 }, /* GP Timer 12 */
2463 [ 96] = { 0x8b000, 0x1000, 32 | 16 | 8 }, /* L4TA31 */
2464 [ 97] = { 0x90000, 0x1000, 16 }, /* EAC */
2465 [ 98] = { 0x91000, 0x1000, 32 | 16 | 8 }, /* L4TA32 */
2466 [ 99] = { 0x92000, 0x1000, 16 }, /* FAC */
2467 [100] = { 0x93000, 0x1000, 32 | 16 | 8 }, /* L4TA33 */
2468 [101] = { 0x94000, 0x1000, 32 | 16 | 8 }, /* IPC (MAILBOX) */
2469 [102] = { 0x95000, 0x1000, 32 | 16 | 8 }, /* L4TA34 */
2470 [103] = { 0x98000, 0x1000, 32 | 16 | 8 }, /* SPI1 */
2471 [104] = { 0x99000, 0x1000, 32 | 16 | 8 }, /* L4TA35 */
2472 [105] = { 0x9a000, 0x1000, 32 | 16 | 8 }, /* SPI2 */
2473 [106] = { 0x9b000, 0x1000, 32 | 16 | 8 }, /* L4TA36 */
2474 [107] = { 0x9c000, 0x1000, 16 | 8 }, /* MMC SDIO */
2475 [108] = { 0x9d000, 0x1000, 32 | 16 | 8 }, /* L4TAO9 */
2476 [109] = { 0x9e000, 0x1000, 32 | 16 | 8 }, /* MS_PRO */
2477 [110] = { 0x9f000, 0x1000, 32 | 16 | 8 }, /* L4TAO10 */
2478 [111] = { 0xa0000, 0x1000, 32 }, /* RNG */
2479 [112] = { 0xa1000, 0x1000, 32 | 16 | 8 }, /* L4TAO11 */
2480 [113] = { 0xa2000, 0x1000, 32 }, /* DES3DES */
2481 [114] = { 0xa3000, 0x1000, 32 | 16 | 8 }, /* L4TAO12 */
2482 [115] = { 0xa4000, 0x1000, 32 }, /* SHA1MD5 */
2483 [116] = { 0xa5000, 0x1000, 32 | 16 | 8 }, /* L4TAO13 */
2484 [117] = { 0xa6000, 0x1000, 32 }, /* AES */
2485 [118] = { 0xa7000, 0x1000, 32 | 16 | 8 }, /* L4TA37 */
2486 [119] = { 0xa8000, 0x2000, 32 }, /* PKA */
2487 [120] = { 0xaa000, 0x1000, 32 | 16 | 8 }, /* L4TA38 */
2488 [121] = { 0xb0000, 0x1000, 32 }, /* MG */
2489 [122] = { 0xb1000, 0x1000, 32 | 16 | 8 },
2490 [123] = { 0xb2000, 0x1000, 32 }, /* HDQ/1-Wire */
2491 [124] = { 0xb3000, 0x1000, 32 | 16 | 8 }, /* L4TA39 */
2492 };
2493
2494 static struct omap_l4_agent_info_s {
2495 int ta;
2496 int region;
2497 int regions;
2498 int ta_region;
2499 } omap_l4_agent_info[54] = {
2500 { 0, 0, 3, 2 }, /* L4IA initiatior agent */
2501 { L4TAO(1), 3, 2, 1 }, /* Control and pinout module */
2502 { L4TAO(2), 5, 2, 1 }, /* 32K timer */
2503 { L4TAO(3), 7, 3, 2 }, /* PRCM */
2504 { L4TA(1), 10, 2, 1 }, /* BCM */
2505 { L4TA(2), 12, 2, 1 }, /* Test JTAG */
2506 { L4TA(3), 14, 6, 3 }, /* Quad GPIO */
2507 { L4TA(4), 20, 4, 3 }, /* WD timer 1/2 */
2508 { L4TA(7), 24, 2, 1 }, /* GP timer 1 */
2509 { L4TA(9), 26, 2, 1 }, /* ATM11 ETB */
2510 { L4TA(10), 28, 5, 4 }, /* Display subsystem */
2511 { L4TA(11), 33, 5, 4 }, /* Camera subsystem */
2512 { L4TA(12), 38, 2, 1 }, /* sDMA */
2513 { L4TA(13), 40, 5, 4 }, /* SSI */
2514 { L4TAO(4), 45, 2, 1 }, /* USB */
2515 { L4TA(14), 47, 2, 1 }, /* Win Tracer1 */
2516 { L4TA(15), 49, 2, 1 }, /* Win Tracer2 */
2517 { L4TA(16), 51, 2, 1 }, /* Win Tracer3 */
2518 { L4TA(17), 53, 2, 1 }, /* Win Tracer4 */
2519 { L4TA(18), 55, 2, 1 }, /* XTI */
2520 { L4TA(19), 57, 2, 1 }, /* UART1 */
2521 { L4TA(20), 59, 2, 1 }, /* UART2 */
2522 { L4TA(21), 61, 2, 1 }, /* UART3 */
2523 { L4TAO(5), 63, 2, 1 }, /* I2C1 */
2524 { L4TAO(6), 65, 2, 1 }, /* I2C2 */
2525 { L4TAO(7), 67, 2, 1 }, /* McBSP1 */
2526 { L4TAO(8), 69, 2, 1 }, /* McBSP2 */
2527 { L4TA(5), 71, 2, 1 }, /* WD Timer 3 (DSP) */
2528 { L4TA(6), 73, 2, 1 }, /* WD Timer 4 (IVA) */
2529 { L4TA(8), 75, 2, 1 }, /* GP Timer 2 */
2530 { L4TA(22), 77, 2, 1 }, /* GP Timer 3 */
2531 { L4TA(23), 79, 2, 1 }, /* GP Timer 4 */
2532 { L4TA(24), 81, 2, 1 }, /* GP Timer 5 */
2533 { L4TA(25), 83, 2, 1 }, /* GP Timer 6 */
2534 { L4TA(26), 85, 2, 1 }, /* GP Timer 7 */
2535 { L4TA(27), 87, 2, 1 }, /* GP Timer 8 */
2536 { L4TA(28), 89, 2, 1 }, /* GP Timer 9 */
2537 { L4TA(29), 91, 2, 1 }, /* GP Timer 10 */
2538 { L4TA(30), 93, 2, 1 }, /* GP Timer 11 */
2539 { L4TA(31), 95, 2, 1 }, /* GP Timer 12 */
2540 { L4TA(32), 97, 2, 1 }, /* EAC */
2541 { L4TA(33), 99, 2, 1 }, /* FAC */
2542 { L4TA(34), 101, 2, 1 }, /* IPC */
2543 { L4TA(35), 103, 2, 1 }, /* SPI1 */
2544 { L4TA(36), 105, 2, 1 }, /* SPI2 */
2545 { L4TAO(9), 107, 2, 1 }, /* MMC SDIO */
2546 { L4TAO(10), 109, 2, 1 },
2547 { L4TAO(11), 111, 2, 1 }, /* RNG */
2548 { L4TAO(12), 113, 2, 1 }, /* DES3DES */
2549 { L4TAO(13), 115, 2, 1 }, /* SHA1MD5 */
2550 { L4TA(37), 117, 2, 1 }, /* AES */
2551 { L4TA(38), 119, 2, 1 }, /* PKA */
2552 { -1, 121, 2, 1 },
2553 { L4TA(39), 123, 2, 1 }, /* HDQ/1-Wire */
2554 };
2555
2556 #define omap_l4ta(bus, cs) omap_l4ta_get(bus, L4TA(cs))
2557 #define omap_l4tao(bus, cs) omap_l4ta_get(bus, L4TAO(cs))
2558
2559 struct omap_target_agent_s *omap_l4ta_get(struct omap_l4_s *bus, int cs)
2560 {
2561 int i, iomemtype;
2562 struct omap_target_agent_s *ta = 0;
2563 struct omap_l4_agent_info_s *info = 0;
2564
2565 for (i = 0; i < bus->ta_num; i ++)
2566 if (omap_l4_agent_info[i].ta == cs) {
2567 ta = &bus->ta[i];
2568 info = &omap_l4_agent_info[i];
2569 break;
2570 }
2571 if (!ta) {
2572 fprintf(stderr, "%s: bad target agent (%i)\n", __FUNCTION__, cs);
2573 exit(-1);
2574 }
2575
2576 ta->bus = bus;
2577 ta->start = &omap_l4_region[info->region];
2578 ta->regions = info->regions;
2579
2580 ta->component = ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2581 ta->status = 0x00000000;
2582 ta->control = 0x00000200; /* XXX 01000200 for L4TAO */
2583
2584 iomemtype = l4_register_io_memory(0, omap_l4ta_readfn,
2585 omap_l4ta_writefn, ta);
2586 ta->base = omap_l4_attach(ta, info->ta_region, iomemtype);
2587
2588 return ta;
2589 }
2590
2591 target_phys_addr_t omap_l4_attach(struct omap_target_agent_s *ta, int region,
2592 int iotype)
2593 {
2594 target_phys_addr_t base;
2595 ssize_t size;
2596 #ifdef L4_MUX_HACK
2597 int i;
2598 #endif
2599
2600 if (region < 0 || region >= ta->regions) {
2601 fprintf(stderr, "%s: bad io region (%i)\n", __FUNCTION__, region);
2602 exit(-1);
2603 }
2604
2605 base = ta->bus->base + ta->start[region].offset;
2606 size = ta->start[region].size;
2607 if (iotype) {
2608 #ifndef L4_MUX_HACK
2609 cpu_register_physical_memory(base, size, iotype);
2610 #else
2611 cpu_register_physical_memory(base, size, omap_cpu_io_entry);
2612 i = (base - ta->bus->base) / TARGET_PAGE_SIZE;
2613 for (; size > 0; size -= TARGET_PAGE_SIZE, i ++) {
2614 omap_l4_io_readb_fn[i] = omap_l4_io_entry[iotype].mem_read[0];
2615 omap_l4_io_readh_fn[i] = omap_l4_io_entry[iotype].mem_read[1];
2616 omap_l4_io_readw_fn[i] = omap_l4_io_entry[iotype].mem_read[2];
2617 omap_l4_io_writeb_fn[i] = omap_l4_io_entry[iotype].mem_write[0];
2618 omap_l4_io_writeh_fn[i] = omap_l4_io_entry[iotype].mem_write[1];
2619 omap_l4_io_writew_fn[i] = omap_l4_io_entry[iotype].mem_write[2];
2620 omap_l4_io_opaque[i] = omap_l4_io_entry[iotype].opaque;
2621 }
2622 #endif
2623 }
2624
2625 return base;
2626 }
2627
2628 /* TEST-Chip-level TAP */
2629 static uint32_t omap_tap_read(void *opaque, target_phys_addr_t addr)
2630 {
2631 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *) opaque;
2632
2633 switch (addr) {
2634 case 0x204: /* IDCODE_reg */
2635 switch (s->mpu_model) {
2636 case omap2420:
2637 case omap2422:
2638 case omap2423:
2639 return 0x5b5d902f; /* ES 2.2 */
2640 case omap2430:
2641 return 0x5b68a02f; /* ES 2.2 */
2642 case omap3430:
2643 return 0x1b7ae02f; /* ES 2 */
2644 default:
2645 cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
2646 }
2647
2648 case 0x208: /* PRODUCTION_ID_reg for OMAP2 */
2649 case 0x210: /* PRODUCTION_ID_reg for OMAP3 */
2650 switch (s->mpu_model) {
2651 case omap2420:
2652 return 0x000254f0; /* POP ESHS2.1.1 in N91/93/95, ES2 in N800 */
2653 case omap2422:
2654 return 0x000400f0;
2655 case omap2423:
2656 return 0x000800f0;
2657 case omap2430:
2658 return 0x000000f0;
2659 case omap3430:
2660 return 0x000000f0;
2661 default:
2662 cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
2663 }
2664
2665 case 0x20c:
2666 switch (s->mpu_model) {
2667 case omap2420:
2668 case omap2422:
2669 case omap2423:
2670 return 0xcafeb5d9; /* ES 2.2 */
2671 case omap2430:
2672 return 0xcafeb68a; /* ES 2.2 */
2673 case omap3430:
2674 return 0xcafeb7ae; /* ES 2 */
2675 default:
2676 cpu_abort(cpu_single_env, "%s: Bad mpu model\n", __FUNCTION__);
2677 }
2678
2679 case 0x218: /* DIE_ID_reg */
2680 return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2681 case 0x21c: /* DIE_ID_reg */
2682 return 0x54 << 24;
2683 case 0x220: /* DIE_ID_reg */
2684 return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2685 case 0x224: /* DIE_ID_reg */
2686 return ('Q' << 24) | ('E' << 16) | ('M' << 8) | ('U' << 0);
2687 }
2688
2689 OMAP_BAD_REG(addr);
2690 return 0;
2691 }
2692
2693 static void omap_tap_write(void *opaque, target_phys_addr_t addr,
2694 uint32_t value)
2695 {
2696 OMAP_BAD_REG(addr);
2697 }
2698
2699 static CPUReadMemoryFunc *omap_tap_readfn[] = {
2700 omap_badwidth_read32,
2701 omap_badwidth_read32,
2702 omap_tap_read,
2703 };
2704
2705 static CPUWriteMemoryFunc *omap_tap_writefn[] = {
2706 omap_badwidth_write32,
2707 omap_badwidth_write32,
2708 omap_tap_write,
2709 };
2710
2711 void omap_tap_init(struct omap_target_agent_s *ta,
2712 struct omap_mpu_state_s *mpu)
2713 {
2714 omap_l4_attach(ta, 0, l4_register_io_memory(0,
2715 omap_tap_readfn, omap_tap_writefn, mpu));
2716 }
2717
2718 /* Power, Reset, and Clock Management */
2719 struct omap_prcm_s {
2720 qemu_irq irq[3];
2721 struct omap_mpu_state_s *mpu;
2722
2723 uint32_t irqst[3];
2724 uint32_t irqen[3];
2725
2726 uint32_t sysconfig;
2727 uint32_t voltctrl;
2728 uint32_t scratch[20];
2729
2730 uint32_t clksrc[1];
2731 uint32_t clkout[1];
2732 uint32_t clkemul[1];
2733 uint32_t clkpol[1];
2734 uint32_t clksel[8];
2735 uint32_t clken[12];
2736 uint32_t clkctrl[4];
2737 uint32_t clkidle[7];
2738 uint32_t setuptime[2];
2739
2740 uint32_t wkup[3];
2741 uint32_t wken[3];
2742 uint32_t wkst[3];
2743 uint32_t rst[4];
2744 uint32_t rstctrl[1];
2745 uint32_t power[4];
2746 uint32_t rsttime_wkup;
2747
2748 uint32_t ev;
2749 uint32_t evtime[2];
2750
2751 int dpll_lock, apll_lock[2];
2752 };
2753
2754 static void omap_prcm_int_update(struct omap_prcm_s *s, int dom)
2755 {
2756 qemu_set_irq(s->irq[dom], s->irqst[dom] & s->irqen[dom]);
2757 /* XXX or is the mask applied before PRCM_IRQSTATUS_* ? */
2758 }
2759
2760 static uint32_t omap_prcm_read(void *opaque, target_phys_addr_t addr)
2761 {
2762 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
2763 uint32_t ret;
2764
2765 switch (addr) {
2766 case 0x000: /* PRCM_REVISION */
2767 return 0x10;
2768
2769 case 0x010: /* PRCM_SYSCONFIG */
2770 return s->sysconfig;
2771
2772 case 0x018: /* PRCM_IRQSTATUS_MPU */
2773 return s->irqst[0];
2774
2775 case 0x01c: /* PRCM_IRQENABLE_MPU */
2776 return s->irqen[0];
2777
2778 case 0x050: /* PRCM_VOLTCTRL */
2779 return s->voltctrl;
2780 case 0x054: /* PRCM_VOLTST */
2781 return s->voltctrl & 3;
2782
2783 case 0x060: /* PRCM_CLKSRC_CTRL */
2784 return s->clksrc[0];
2785 case 0x070: /* PRCM_CLKOUT_CTRL */
2786 return s->clkout[0];
2787 case 0x078: /* PRCM_CLKEMUL_CTRL */
2788 return s->clkemul[0];
2789 case 0x080: /* PRCM_CLKCFG_CTRL */
2790 case 0x084: /* PRCM_CLKCFG_STATUS */
2791 return 0;
2792
2793 case 0x090: /* PRCM_VOLTSETUP */
2794 return s->setuptime[0];
2795
2796 case 0x094: /* PRCM_CLKSSETUP */
2797 return s->setuptime[1];
2798
2799 case 0x098: /* PRCM_POLCTRL */
2800 return s->clkpol[0];
2801
2802 case 0x0b0: /* GENERAL_PURPOSE1 */
2803 case 0x0b4: /* GENERAL_PURPOSE2 */
2804 case 0x0b8: /* GENERAL_PURPOSE3 */
2805 case 0x0bc: /* GENERAL_PURPOSE4 */
2806 case 0x0c0: /* GENERAL_PURPOSE5 */
2807 case 0x0c4: /* GENERAL_PURPOSE6 */
2808 case 0x0c8: /* GENERAL_PURPOSE7 */
2809 case 0x0cc: /* GENERAL_PURPOSE8 */
2810 case 0x0d0: /* GENERAL_PURPOSE9 */
2811 case 0x0d4: /* GENERAL_PURPOSE10 */
2812 case 0x0d8: /* GENERAL_PURPOSE11 */
2813 case 0x0dc: /* GENERAL_PURPOSE12 */
2814 case 0x0e0: /* GENERAL_PURPOSE13 */
2815 case 0x0e4: /* GENERAL_PURPOSE14 */
2816 case 0x0e8: /* GENERAL_PURPOSE15 */
2817 case 0x0ec: /* GENERAL_PURPOSE16 */
2818 case 0x0f0: /* GENERAL_PURPOSE17 */
2819 case 0x0f4: /* GENERAL_PURPOSE18 */
2820 case 0x0f8: /* GENERAL_PURPOSE19 */
2821 case 0x0fc: /* GENERAL_PURPOSE20 */
2822 return s->scratch[(addr - 0xb0) >> 2];
2823
2824 case 0x140: /* CM_CLKSEL_MPU */
2825 return s->clksel[0];
2826 case 0x148: /* CM_CLKSTCTRL_MPU */
2827 return s->clkctrl[0];
2828
2829 case 0x158: /* RM_RSTST_MPU */
2830 return s->rst[0];
2831 case 0x1c8: /* PM_WKDEP_MPU */
2832 return s->wkup[0];
2833 case 0x1d4: /* PM_EVGENCTRL_MPU */
2834 return s->ev;
2835 case 0x1d8: /* PM_EVEGENONTIM_MPU */
2836 return s->evtime[0];
2837 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
2838 return s->evtime[1];
2839 case 0x1e0: /* PM_PWSTCTRL_MPU */
2840 return s->power[0];
2841 case 0x1e4: /* PM_PWSTST_MPU */
2842 return 0;
2843
2844 case 0x200: /* CM_FCLKEN1_CORE */
2845 return s->clken[0];
2846 case 0x204: /* CM_FCLKEN2_CORE */
2847 return s->clken[1];
2848 case 0x210: /* CM_ICLKEN1_CORE */
2849 return s->clken[2];
2850 case 0x214: /* CM_ICLKEN2_CORE */
2851 return s->clken[3];
2852 case 0x21c: /* CM_ICLKEN4_CORE */
2853 return s->clken[4];
2854
2855 case 0x220: /* CM_IDLEST1_CORE */
2856 /* TODO: check the actual iclk status */
2857 return 0x7ffffff9;
2858 case 0x224: /* CM_IDLEST2_CORE */
2859 /* TODO: check the actual iclk status */
2860 return 0x00000007;
2861 case 0x22c: /* CM_IDLEST4_CORE */
2862 /* TODO: check the actual iclk status */
2863 return 0x0000001f;
2864
2865 case 0x230: /* CM_AUTOIDLE1_CORE */
2866 return s->clkidle[0];
2867 case 0x234: /* CM_AUTOIDLE2_CORE */
2868 return s->clkidle[1];
2869 case 0x238: /* CM_AUTOIDLE3_CORE */
2870 return s->clkidle[2];
2871 case 0x23c: /* CM_AUTOIDLE4_CORE */
2872 return s->clkidle[3];
2873
2874 case 0x240: /* CM_CLKSEL1_CORE */
2875 return s->clksel[1];
2876 case 0x244: /* CM_CLKSEL2_CORE */
2877 return s->clksel[2];
2878
2879 case 0x248: /* CM_CLKSTCTRL_CORE */
2880 return s->clkctrl[1];
2881
2882 case 0x2a0: /* PM_WKEN1_CORE */
2883 return s->wken[0];
2884 case 0x2a4: /* PM_WKEN2_CORE */
2885 return s->wken[1];
2886
2887 case 0x2b0: /* PM_WKST1_CORE */
2888 return s->wkst[0];
2889 case 0x2b4: /* PM_WKST2_CORE */
2890 return s->wkst[1];
2891 case 0x2c8: /* PM_WKDEP_CORE */
2892 return 0x1e;
2893
2894 case 0x2e0: /* PM_PWSTCTRL_CORE */
2895 return s->power[1];
2896 case 0x2e4: /* PM_PWSTST_CORE */
2897 return 0x000030 | (s->power[1] & 0xfc00);
2898
2899 case 0x300: /* CM_FCLKEN_GFX */
2900 return s->clken[5];
2901 case 0x310: /* CM_ICLKEN_GFX */
2902 return s->clken[6];
2903 case 0x320: /* CM_IDLEST_GFX */
2904 /* TODO: check the actual iclk status */
2905 return 0x00000001;
2906 case 0x340: /* CM_CLKSEL_GFX */
2907 return s->clksel[3];
2908 case 0x348: /* CM_CLKSTCTRL_GFX */
2909 return s->clkctrl[2];
2910 case 0x350: /* RM_RSTCTRL_GFX */
2911 return s->rstctrl[0];
2912 case 0x358: /* RM_RSTST_GFX */
2913 return s->rst[1];
2914 case 0x3c8: /* PM_WKDEP_GFX */
2915 return s->wkup[1];
2916
2917 case 0x3e0: /* PM_PWSTCTRL_GFX */
2918 return s->power[2];
2919 case 0x3e4: /* PM_PWSTST_GFX */
2920 return s->power[2] & 3;
2921
2922 case 0x400: /* CM_FCLKEN_WKUP */
2923 return s->clken[7];
2924 case 0x410: /* CM_ICLKEN_WKUP */
2925 return s->clken[8];
2926 case 0x420: /* CM_IDLEST_WKUP */
2927 /* TODO: check the actual iclk status */
2928 return 0x0000003f;
2929 case 0x430: /* CM_AUTOIDLE_WKUP */
2930 return s->clkidle[4];
2931 case 0x440: /* CM_CLKSEL_WKUP */
2932 return s->clksel[4];
2933 case 0x450: /* RM_RSTCTRL_WKUP */
2934 return 0;
2935 case 0x454: /* RM_RSTTIME_WKUP */
2936 return s->rsttime_wkup;
2937 case 0x458: /* RM_RSTST_WKUP */
2938 return s->rst[2];
2939 case 0x4a0: /* PM_WKEN_WKUP */
2940 return s->wken[2];
2941 case 0x4b0: /* PM_WKST_WKUP */
2942 return s->wkst[2];
2943
2944 case 0x500: /* CM_CLKEN_PLL */
2945 return s->clken[9];
2946 case 0x520: /* CM_IDLEST_CKGEN */
2947 ret = 0x0000070 | (s->apll_lock[0] << 9) | (s->apll_lock[1] << 8);
2948 if (!(s->clksel[6] & 3))
2949 /* Core uses 32-kHz clock */
2950 ret |= 3 << 0;
2951 else if (!s->dpll_lock)
2952 /* DPLL not locked, core uses ref_clk */
2953 ret |= 1 << 0;
2954 else
2955 /* Core uses DPLL */
2956 ret |= 2 << 0;
2957 return ret;
2958 case 0x530: /* CM_AUTOIDLE_PLL */
2959 return s->clkidle[5];
2960 case 0x540: /* CM_CLKSEL1_PLL */
2961 return s->clksel[5];
2962 case 0x544: /* CM_CLKSEL2_PLL */
2963 return s->clksel[6];
2964
2965 case 0x800: /* CM_FCLKEN_DSP */
2966 return s->clken[10];
2967 case 0x810: /* CM_ICLKEN_DSP */
2968 return s->clken[11];
2969 case 0x820: /* CM_IDLEST_DSP */
2970 /* TODO: check the actual iclk status */
2971 return 0x00000103;
2972 case 0x830: /* CM_AUTOIDLE_DSP */
2973 return s->clkidle[6];
2974 case 0x840: /* CM_CLKSEL_DSP */
2975 return s->clksel[7];
2976 case 0x848: /* CM_CLKSTCTRL_DSP */
2977 return s->clkctrl[3];
2978 case 0x850: /* RM_RSTCTRL_DSP */
2979 return 0;
2980 case 0x858: /* RM_RSTST_DSP */
2981 return s->rst[3];
2982 case 0x8c8: /* PM_WKDEP_DSP */
2983 return s->wkup[2];
2984 case 0x8e0: /* PM_PWSTCTRL_DSP */
2985 return s->power[3];
2986 case 0x8e4: /* PM_PWSTST_DSP */
2987 return 0x008030 | (s->power[3] & 0x3003);
2988
2989 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
2990 return s->irqst[1];
2991 case 0x8f4: /* PRCM_IRQENABLE_DSP */
2992 return s->irqen[1];
2993
2994 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
2995 return s->irqst[2];
2996 case 0x8fc: /* PRCM_IRQENABLE_IVA */
2997 return s->irqen[2];
2998 }
2999
3000 OMAP_BAD_REG(addr);
3001 return 0;
3002 }
3003
3004 static void omap_prcm_apll_update(struct omap_prcm_s *s)
3005 {
3006 int mode[2];
3007
3008 mode[0] = (s->clken[9] >> 6) & 3;
3009 s->apll_lock[0] = (mode[0] == 3);
3010 mode[1] = (s->clken[9] >> 2) & 3;
3011 s->apll_lock[1] = (mode[1] == 3);
3012 /* TODO: update clocks */
3013
3014 if (mode[0] == 1 || mode[0] == 2 || mode[1] == 1 || mode[2] == 2)
3015 fprintf(stderr, "%s: bad EN_54M_PLL or bad EN_96M_PLL\n",
3016 __FUNCTION__);
3017 }
3018
3019 static void omap_prcm_dpll_update(struct omap_prcm_s *s)
3020 {
3021 omap_clk dpll = omap_findclk(s->mpu, "dpll");
3022 omap_clk dpll_x2 = omap_findclk(s->mpu, "dpll");
3023 omap_clk core = omap_findclk(s->mpu, "core_clk");
3024 int mode = (s->clken[9] >> 0) & 3;
3025 int mult, div;
3026
3027 mult = (s->clksel[5] >> 12) & 0x3ff;
3028 div = (s->clksel[5] >> 8) & 0xf;
3029 if (mult == 0 || mult == 1)
3030 mode = 1; /* Bypass */
3031
3032 s->dpll_lock = 0;
3033 switch (mode) {
3034 case 0:
3035 fprintf(stderr, "%s: bad EN_DPLL\n", __FUNCTION__);
3036 break;
3037 case 1: /* Low-power bypass mode (Default) */
3038 case 2: /* Fast-relock bypass mode */
3039 omap_clk_setrate(dpll, 1, 1);
3040 omap_clk_setrate(dpll_x2, 1, 1);
3041 break;
3042 case 3: /* Lock mode */
3043 s->dpll_lock = 1; /* After 20 FINT cycles (ref_clk / (div + 1)). */
3044
3045 omap_clk_setrate(dpll, div + 1, mult);
3046 omap_clk_setrate(dpll_x2, div + 1, mult * 2);
3047 break;
3048 }
3049
3050 switch ((s->clksel[6] >> 0) & 3) {
3051 case 0:
3052 omap_clk_reparent(core, omap_findclk(s->mpu, "clk32-kHz"));
3053 break;
3054 case 1:
3055 omap_clk_reparent(core, dpll);
3056 break;
3057 case 2:
3058 /* Default */
3059 omap_clk_reparent(core, dpll_x2);
3060 break;
3061 case 3:
3062 fprintf(stderr, "%s: bad CORE_CLK_SRC\n", __FUNCTION__);
3063 break;
3064 }
3065 }
3066
3067 static void omap_prcm_write(void *opaque, target_phys_addr_t addr,
3068 uint32_t value)
3069 {
3070 struct omap_prcm_s *s = (struct omap_prcm_s *) opaque;
3071
3072 switch (addr) {
3073 case 0x000: /* PRCM_REVISION */
3074 case 0x054: /* PRCM_VOLTST */
3075 case 0x084: /* PRCM_CLKCFG_STATUS */
3076 case 0x1e4: /* PM_PWSTST_MPU */
3077 case 0x220: /* CM_IDLEST1_CORE */
3078 case 0x224: /* CM_IDLEST2_CORE */
3079 case 0x22c: /* CM_IDLEST4_CORE */
3080 case 0x2c8: /* PM_WKDEP_CORE */
3081 case 0x2e4: /* PM_PWSTST_CORE */
3082 case 0x320: /* CM_IDLEST_GFX */
3083 case 0x3e4: /* PM_PWSTST_GFX */
3084 case 0x420: /* CM_IDLEST_WKUP */
3085 case 0x520: /* CM_IDLEST_CKGEN */
3086 case 0x820: /* CM_IDLEST_DSP */
3087 case 0x8e4: /* PM_PWSTST_DSP */
3088 OMAP_RO_REG(addr);
3089 return;
3090
3091 case 0x010: /* PRCM_SYSCONFIG */
3092 s->sysconfig = value & 1;
3093 break;
3094
3095 case 0x018: /* PRCM_IRQSTATUS_MPU */
3096 s->irqst[0] &= ~value;
3097 omap_prcm_int_update(s, 0);
3098 break;
3099 case 0x01c: /* PRCM_IRQENABLE_MPU */
3100 s->irqen[0] = value & 0x3f;
3101 omap_prcm_int_update(s, 0);
3102 break;
3103
3104 case 0x050: /* PRCM_VOLTCTRL */
3105 s->voltctrl = value & 0xf1c3;
3106 break;
3107
3108 case 0x060: /* PRCM_CLKSRC_CTRL */
3109 s->clksrc[0] = value & 0xdb;
3110 /* TODO update clocks */
3111 break;
3112
3113 case 0x070: /* PRCM_CLKOUT_CTRL */
3114 s->clkout[0] = value & 0xbbbb;
3115 /* TODO update clocks */
3116 break;
3117
3118 case 0x078: /* PRCM_CLKEMUL_CTRL */
3119 s->clkemul[0] = value & 1;
3120 /* TODO update clocks */
3121 break;
3122
3123 case 0x080: /* PRCM_CLKCFG_CTRL */
3124 break;
3125
3126 case 0x090: /* PRCM_VOLTSETUP */
3127 s->setuptime[0] = value & 0xffff;
3128 break;
3129 case 0x094: /* PRCM_CLKSSETUP */
3130 s->setuptime[1] = value & 0xffff;
3131 break;
3132
3133 case 0x098: /* PRCM_POLCTRL */
3134 s->clkpol[0] = value & 0x701;
3135 break;
3136
3137 case 0x0b0: /* GENERAL_PURPOSE1 */
3138 case 0x0b4: /* GENERAL_PURPOSE2 */
3139 case 0x0b8: /* GENERAL_PURPOSE3 */
3140 case 0x0bc: /* GENERAL_PURPOSE4 */
3141 case 0x0c0: /* GENERAL_PURPOSE5 */
3142 case 0x0c4: /* GENERAL_PURPOSE6 */
3143 case 0x0c8: /* GENERAL_PURPOSE7 */
3144 case 0x0cc: /* GENERAL_PURPOSE8 */
3145 case 0x0d0: /* GENERAL_PURPOSE9 */
3146 case 0x0d4: /* GENERAL_PURPOSE10 */
3147 case 0x0d8: /* GENERAL_PURPOSE11 */
3148 case 0x0dc: /* GENERAL_PURPOSE12 */
3149 case 0x0e0: /* GENERAL_PURPOSE13 */
3150 case 0x0e4: /* GENERAL_PURPOSE14 */
3151 case 0x0e8: /* GENERAL_PURPOSE15 */
3152 case 0x0ec: /* GENERAL_PURPOSE16 */
3153 case 0x0f0: /* GENERAL_PURPOSE17 */
3154 case 0x0f4: /* GENERAL_PURPOSE18 */
3155 case 0x0f8: /* GENERAL_PURPOSE19 */
3156 case 0x0fc: /* GENERAL_PURPOSE20 */
3157 s->scratch[(addr - 0xb0) >> 2] = value;
3158 break;
3159
3160 case 0x140: /* CM_CLKSEL_MPU */
3161 s->clksel[0] = value & 0x1f;
3162 /* TODO update clocks */
3163 break;
3164 case 0x148: /* CM_CLKSTCTRL_MPU */
3165 s->clkctrl[0] = value & 0x1f;
3166 break;
3167
3168 case 0x158: /* RM_RSTST_MPU */
3169 s->rst[0] &= ~value;
3170 break;
3171 case 0x1c8: /* PM_WKDEP_MPU */
3172 s->wkup[0] = value & 0x15;
3173 break;
3174
3175 case 0x1d4: /* PM_EVGENCTRL_MPU */
3176 s->ev = value & 0x1f;
3177 break;
3178 case 0x1d8: /* PM_EVEGENONTIM_MPU */
3179 s->evtime[0] = value;
3180 break;
3181 case 0x1dc: /* PM_EVEGENOFFTIM_MPU */
3182 s->evtime[1] = value;
3183 break;
3184
3185 case 0x1e0: /* PM_PWSTCTRL_MPU */
3186 s->power[0] = value & 0xc0f;
3187 break;
3188
3189 case 0x200: /* CM_FCLKEN1_CORE */
3190 s->clken[0] = value & 0xbfffffff;
3191 /* TODO update clocks */
3192 /* The EN_EAC bit only gets/puts func_96m_clk. */
3193 break;
3194 case 0x204: /* CM_FCLKEN2_CORE */
3195 s->clken[1] = value & 0x00000007;
3196 /* TODO update clocks */
3197 break;
3198 case 0x210: /* CM_ICLKEN1_CORE */
3199 s->clken[2] = value & 0xfffffff9;
3200 /* TODO update clocks */
3201 /* The EN_EAC bit only gets/puts core_l4_iclk. */
3202 break;
3203 case 0x214: /* CM_ICLKEN2_CORE */
3204 s->clken[3] = value & 0x00000007;
3205 /* TODO update clocks */
3206 break;
3207 case 0x21c: /* CM_ICLKEN4_CORE */
3208 s->clken[4] = value & 0x0000001f;
3209 /* TODO update clocks */
3210 break;
3211
3212 case 0x230: /* CM_AUTOIDLE1_CORE */
3213 s->clkidle[0] = value & 0xfffffff9;
3214 /* TODO update clocks */
3215 break;
3216 case 0x234: /* CM_AUTOIDLE2_CORE */
3217 s->clkidle[1] = value & 0x00000007;
3218 /* TODO update clocks */
3219 break;
3220 case 0x238: /* CM_AUTOIDLE3_CORE */
3221 s->clkidle[2] = value & 0x00000007;
3222 /* TODO update clocks */
3223 break;
3224 case 0x23c: /* CM_AUTOIDLE4_CORE */
3225 s->clkidle[3] = value & 0x0000001f;
3226 /* TODO update clocks */
3227 break;
3228
3229 case 0x240: /* CM_CLKSEL1_CORE */
3230 s->clksel[1] = value & 0x0fffbf7f;
3231 /* TODO update clocks */
3232 break;
3233
3234 case 0x244: /* CM_CLKSEL2_CORE */
3235 s->clksel[2] = value & 0x00fffffc;
3236 /* TODO update clocks */
3237 break;
3238
3239 case 0x248: /* CM_CLKSTCTRL_CORE */
3240 s->clkctrl[1] = value & 0x7;
3241 break;
3242
3243 case 0x2a0: /* PM_WKEN1_CORE */
3244 s->wken[0] = value & 0x04667ff8;
3245 break;
3246 case 0x2a4: /* PM_WKEN2_CORE */
3247 s->wken[1] = value & 0x00000005;
3248 break;
3249
3250 case 0x2b0: /* PM_WKST1_CORE */
3251 s->wkst[0] &= ~value;
3252 break;
3253 case 0x2b4: /* PM_WKST2_CORE */
3254 s->wkst[1] &= ~value;
3255 break;
3256
3257 case 0x2e0: /* PM_PWSTCTRL_CORE */
3258 s->power[1] = (value & 0x00fc3f) | (1 << 2);
3259 break;
3260
3261 case 0x300: /* CM_FCLKEN_GFX */
3262 s->clken[5] = value & 6;
3263 /* TODO update clocks */
3264 break;
3265 case 0x310: /* CM_ICLKEN_GFX */
3266 s->clken[6] = value & 1;
3267 /* TODO update clocks */
3268 break;
3269 case 0x340: /* CM_CLKSEL_GFX */
3270 s->clksel[3] = value & 7;
3271 /* TODO update clocks */
3272 break;
3273 case 0x348: /* CM_CLKSTCTRL_GFX */
3274 s->clkctrl[2] = value & 1;
3275 break;
3276 case 0x350: /* RM_RSTCTRL_GFX */
3277 s->rstctrl[0] = value & 1;
3278 /* TODO: reset */
3279 break;
3280 case 0x358: /* RM_RSTST_GFX */
3281 s->rst[1] &= ~value;
3282 break;
3283 case 0x3c8: /* PM_WKDEP_GFX */
3284 s->wkup[1] = value & 0x13;
3285 break;
3286 case 0x3e0: /* PM_PWSTCTRL_GFX */
3287 s->power[2] = (value & 0x00c0f) | (3 << 2);
3288 break;
3289
3290 case 0x400: /* CM_FCLKEN_WKUP */
3291 s->clken[7] = value & 0xd;
3292 /* TODO update clocks */
3293 break;
3294 case 0x410: /* CM_ICLKEN_WKUP */
3295 s->clken[8] = value & 0x3f;
3296 /* TODO update clocks */
3297 break;
3298 case 0x430: /* CM_AUTOIDLE_WKUP */
3299 s->clkidle[4] = value & 0x0000003f;
3300 /* TODO update clocks */
3301 break;
3302 case 0x440: /* CM_CLKSEL_WKUP */
3303 s->clksel[4] = value & 3;
3304 /* TODO update clocks */
3305 break;
3306 case 0x450: /* RM_RSTCTRL_WKUP */
3307 /* TODO: reset */
3308 if (value & 2)
3309 qemu_system_reset_request();
3310 break;
3311 case 0x454: /* RM_RSTTIME_WKUP */
3312 s->rsttime_wkup = value & 0x1fff;
3313 break;
3314 case 0x458: /* RM_RSTST_WKUP */
3315 s->rst[2] &= ~value;
3316 break;
3317 case 0x4a0: /* PM_WKEN_WKUP */
3318 s->wken[2] = value & 0x00000005;
3319 break;
3320 case 0x4b0: /* PM_WKST_WKUP */
3321 s->wkst[2] &= ~value;
3322 break;
3323
3324 case 0x500: /* CM_CLKEN_PLL */
3325 if (value & 0xffffff30)
3326 fprintf(stderr, "%s: write 0s in CM_CLKEN_PLL for "
3327 "future compatiblity\n", __FUNCTION__);
3328 if ((s->clken[9] ^ value) & 0xcc) {
3329 s->clken[9] &= ~0xcc;
3330 s->clken[9] |= value & 0xcc;
3331 omap_prcm_apll_update(s);
3332 }
3333 if ((s->clken[9] ^ value) & 3) {
3334 s->clken[9] &= ~3;
3335 s->clken[9] |= value & 3;
3336 omap_prcm_dpll_update(s);
3337 }
3338 break;
3339 case 0x530: /* CM_AUTOIDLE_PLL */
3340 s->clkidle[5] = value & 0x000000cf;
3341 /* TODO update clocks */
3342 break;
3343 case 0x540: /* CM_CLKSEL1_PLL */
3344 if (value & 0xfc4000d7)
3345 fprintf(stderr, "%s: write 0s in CM_CLKSEL1_PLL for "
3346 "future compatiblity\n", __FUNCTION__);
3347 if ((s->clksel[5] ^ value) & 0x003fff00) {
3348 s->clksel[5] = value & 0x03bfff28;
3349 omap_prcm_dpll_update(s);
3350 }
3351 /* TODO update the other clocks */
3352
3353 s->clksel[5] = value & 0x03bfff28;
3354 break;
3355 case 0x544: /* CM_CLKSEL2_PLL */
3356 if (value & ~3)
3357 fprintf(stderr, "%s: write 0s in CM_CLKSEL2_PLL[31:2] for "
3358 "future compatiblity\n", __FUNCTION__);
3359 if (s->clksel[6] != (value & 3)) {
3360 s->clksel[6] = value & 3;
3361 omap_prcm_dpll_update(s);
3362 }
3363 break;
3364
3365 case 0x800: /* CM_FCLKEN_DSP */
3366 s->clken[10] = value & 0x501;
3367 /* TODO update clocks */
3368 break;
3369 case 0x810: /* CM_ICLKEN_DSP */
3370 s->clken[11] = value & 0x2;
3371 /* TODO update clocks */
3372 break;
3373 case 0x830: /* CM_AUTOIDLE_DSP */
3374 s->clkidle[6] = value & 0x2;
3375 /* TODO update clocks */
3376 break;
3377 case 0x840: /* CM_CLKSEL_DSP */
3378 s->clksel[7] = value & 0x3fff;
3379 /* TODO update clocks */
3380 break;
3381 case 0x848: /* CM_CLKSTCTRL_DSP */
3382 s->clkctrl[3] = value & 0x101;
3383 break;
3384 case 0x850: /* RM_RSTCTRL_DSP */
3385 /* TODO: reset */
3386 break;
3387 case 0x858: /* RM_RSTST_DSP */
3388 s->rst[3] &= ~value;
3389 break;
3390 case 0x8c8: /* PM_WKDEP_DSP */
3391 s->wkup[2] = value & 0x13;
3392 break;
3393 case 0x8e0: /* PM_PWSTCTRL_DSP */
3394 s->power[3] = (value & 0x03017) | (3 << 2);
3395 break;
3396
3397 case 0x8f0: /* PRCM_IRQSTATUS_DSP */
3398 s->irqst[1] &= ~value;
3399 omap_prcm_int_update(s, 1);
3400 break;
3401 case 0x8f4: /* PRCM_IRQENABLE_DSP */
3402 s->irqen[1] = value & 0x7;
3403 omap_prcm_int_update(s, 1);
3404 break;
3405
3406 case 0x8f8: /* PRCM_IRQSTATUS_IVA */
3407 s->irqst[2] &= ~value;
3408 omap_prcm_int_update(s, 2);
3409 break;
3410 case 0x8fc: /* PRCM_IRQENABLE_IVA */
3411 s->irqen[2] = value & 0x7;
3412 omap_prcm_int_update(s, 2);
3413 break;
3414
3415 default:
3416 OMAP_BAD_REG(addr);
3417 return;
3418 }
3419 }
3420
3421 static CPUReadMemoryFunc *omap_prcm_readfn[] = {
3422 omap_badwidth_read32,
3423 omap_badwidth_read32,
3424 omap_prcm_read,
3425 };
3426
3427 static CPUWriteMemoryFunc *omap_prcm_writefn[] = {
3428 omap_badwidth_write32,
3429 omap_badwidth_write32,
3430 omap_prcm_write,
3431 };
3432
3433 static void omap_prcm_reset(struct omap_prcm_s *s)
3434 {
3435 s->sysconfig = 0;
3436 s->irqst[0] = 0;
3437 s->irqst[1] = 0;
3438 s->irqst[2] = 0;
3439 s->irqen[0] = 0;
3440 s->irqen[1] = 0;
3441 s->irqen[2] = 0;
3442 s->voltctrl = 0x1040;
3443 s->ev = 0x14;
3444 s->evtime[0] = 0;
3445 s->evtime[1] = 0;
3446 s->clkctrl[0] = 0;
3447 s->clkctrl[1] = 0;
3448 s->clkctrl[2] = 0;
3449 s->clkctrl[3] = 0;
3450 s->clken[1] = 7;
3451 s->clken[3] = 7;
3452 s->clken[4] = 0;
3453 s->clken[5] = 0;
3454 s->clken[6] = 0;
3455 s->clken[7] = 0xc;
3456 s->clken[8] = 0x3e;
3457 s->clken[9] = 0x0d;
3458 s->clken[10] = 0;
3459 s->clken[11] = 0;
3460 s->clkidle[0] = 0;
3461 s->clkidle[2] = 7;
3462 s->clkidle[3] = 0;
3463 s->clkidle[4] = 0;
3464 s->clkidle[5] = 0x0c;
3465 s->clkidle[6] = 0;
3466 s->clksel[0] = 0x01;
3467 s->clksel[1] = 0x02100121;
3468 s->clksel[2] = 0x00000000;
3469 s->clksel[3] = 0x01;
3470 s->clksel[4] = 0;
3471 s->clksel[7] = 0x0121;
3472 s->wkup[0] = 0x15;
3473 s->wkup[1] = 0x13;
3474 s->wkup[2] = 0x13;
3475 s->wken[0] = 0x04667ff8;
3476 s->wken[1] = 0x00000005;
3477 s->wken[2] = 5;
3478 s->wkst[0] = 0;
3479 s->wkst[1] = 0;
3480 s->wkst[2] = 0;
3481 s->power[0] = 0x00c;
3482 s->power[1] = 4;
3483 s->power[2] = 0x0000c;
3484 s->power[3] = 0x14;
3485 s->rstctrl[0] = 1;
3486 s->rst[3] = 1;
3487 omap_prcm_apll_update(s);
3488 omap_prcm_dpll_update(s);
3489 }
3490
3491 static void omap_prcm_coldreset(struct omap_prcm_s *s)
3492 {
3493 s->setuptime[0] = 0;
3494 s->setuptime[1] = 0;
3495 memset(&s->scratch, 0, sizeof(s->scratch));
3496 s->rst[0] = 0x01;
3497 s->rst[1] = 0x00;
3498 s->rst[2] = 0x01;
3499 s->clken[0] = 0;
3500 s->clken[2] = 0;
3501 s->clkidle[1] = 0;
3502 s->clksel[5] = 0;
3503 s->clksel[6] = 2;
3504 s->clksrc[0] = 0x43;
3505 s->clkout[0] = 0x0303;
3506 s->clkemul[0] = 0;
3507 s->clkpol[0] = 0x100;
3508 s->rsttime_wkup = 0x1002;
3509
3510 omap_prcm_reset(s);
3511 }
3512
3513 struct omap_prcm_s *omap_prcm_init(struct omap_target_agent_s *ta,
3514 qemu_irq mpu_int, qemu_irq dsp_int, qemu_irq iva_int,
3515 struct omap_mpu_state_s *mpu)
3516 {
3517 int iomemtype;
3518 struct omap_prcm_s *s = (struct omap_prcm_s *)
3519 qemu_mallocz(sizeof(struct omap_prcm_s));
3520
3521 s->irq[0] = mpu_int;
3522 s->irq[1] = dsp_int;
3523 s->irq[2] = iva_int;
3524 s->mpu = mpu;
3525 omap_prcm_coldreset(s);
3526
3527 iomemtype = l4_register_io_memory(0, omap_prcm_readfn,
3528 omap_prcm_writefn, s);
3529 omap_l4_attach(ta, 0, iomemtype);
3530 omap_l4_attach(ta, 1, iomemtype);
3531
3532 return s;
3533 }
3534
3535 /* System and Pinout control */
3536 struct omap_sysctl_s {
3537 struct omap_mpu_state_s *mpu;
3538
3539 uint32_t sysconfig;
3540 uint32_t devconfig;
3541 uint32_t psaconfig;
3542 uint32_t padconf[0x45];
3543 uint8_t obs;
3544 uint32_t msuspendmux[5];
3545 };
3546
3547 static uint32_t omap_sysctl_read8(void *opaque, target_phys_addr_t addr)
3548 {
3549
3550 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
3551 int pad_offset, byte_offset;
3552 int value;
3553
3554 switch (addr) {
3555 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
3556 pad_offset = (addr - 0x30) >> 2;
3557 byte_offset = (addr - 0x30) & (4 - 1);
3558
3559 value = s->padconf[pad_offset];
3560 value = (value >> (byte_offset * 8)) & 0xff;
3561
3562 return value;
3563
3564 default:
3565 break;
3566 }
3567
3568 OMAP_BAD_REG(addr);
3569 return 0;
3570 }
3571
3572 static uint32_t omap_sysctl_read(void *opaque, target_phys_addr_t addr)
3573 {
3574 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
3575
3576 switch (addr) {
3577 case 0x000: /* CONTROL_REVISION */
3578 return 0x20;
3579
3580 case 0x010: /* CONTROL_SYSCONFIG */
3581 return s->sysconfig;
3582
3583 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
3584 return s->padconf[(addr - 0x30) >> 2];
3585
3586 case 0x270: /* CONTROL_DEBOBS */
3587 return s->obs;
3588
3589 case 0x274: /* CONTROL_DEVCONF */
3590 return s->devconfig;
3591
3592 case 0x28c: /* CONTROL_EMU_SUPPORT */
3593 return 0;
3594
3595 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
3596 return s->msuspendmux[0];
3597 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
3598 return s->msuspendmux[1];
3599 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
3600 return s->msuspendmux[2];
3601 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
3602 return s->msuspendmux[3];
3603 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
3604 return s->msuspendmux[4];
3605 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
3606 return 0;
3607
3608 case 0x2b8: /* CONTROL_PSA_CTRL */
3609 return s->psaconfig;
3610 case 0x2bc: /* CONTROL_PSA_CMD */
3611 case 0x2c0: /* CONTROL_PSA_VALUE */
3612 return 0;
3613
3614 case 0x2b0: /* CONTROL_SEC_CTRL */
3615 return 0x800000f1;
3616 case 0x2d0: /* CONTROL_SEC_EMU */
3617 return 0x80000015;
3618 case 0x2d4: /* CONTROL_SEC_TAP */
3619 return 0x8000007f;
3620 case 0x2b4: /* CONTROL_SEC_TEST */
3621 case 0x2f0: /* CONTROL_SEC_STATUS */
3622 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
3623 /* Secure mode is not present on general-pusrpose device. Outside
3624 * secure mode these values cannot be read or written. */
3625 return 0;
3626
3627 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
3628 return 0xff;
3629 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
3630 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
3631 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
3632 /* No secure mode so no Extended Secure RAM present. */
3633 return 0;
3634
3635 case 0x2f8: /* CONTROL_STATUS */
3636 /* Device Type => General-purpose */
3637 return 0x0300;
3638 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
3639
3640 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
3641 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
3642 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
3643 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
3644 return 0xdecafbad;
3645
3646 case 0x310: /* CONTROL_RAND_KEY_0 */
3647 case 0x314: /* CONTROL_RAND_KEY_1 */
3648 case 0x318: /* CONTROL_RAND_KEY_2 */
3649 case 0x31c: /* CONTROL_RAND_KEY_3 */
3650 case 0x320: /* CONTROL_CUST_KEY_0 */
3651 case 0x324: /* CONTROL_CUST_KEY_1 */
3652 case 0x330: /* CONTROL_TEST_KEY_0 */
3653 case 0x334: /* CONTROL_TEST_KEY_1 */
3654 case 0x338: /* CONTROL_TEST_KEY_2 */
3655 case 0x33c: /* CONTROL_TEST_KEY_3 */
3656 case 0x340: /* CONTROL_TEST_KEY_4 */
3657 case 0x344: /* CONTROL_TEST_KEY_5 */
3658 case 0x348: /* CONTROL_TEST_KEY_6 */
3659 case 0x34c: /* CONTROL_TEST_KEY_7 */
3660 case 0x350: /* CONTROL_TEST_KEY_8 */
3661 case 0x354: /* CONTROL_TEST_KEY_9 */
3662 /* Can only be accessed in secure mode and when C_FieldAccEnable
3663 * bit is set in CONTROL_SEC_CTRL.
3664 * TODO: otherwise an interconnect access error is generated. */
3665 return 0;
3666 }
3667
3668 OMAP_BAD_REG(addr);
3669 return 0;
3670 }
3671
3672 static void omap_sysctl_write8(void *opaque, target_phys_addr_t addr,
3673 uint32_t value)
3674 {
3675 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
3676 int pad_offset, byte_offset;
3677 int prev_value;
3678
3679 switch (addr) {
3680 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
3681 pad_offset = (addr - 0x30) >> 2;
3682 byte_offset = (addr - 0x30) & (4 - 1);
3683
3684 prev_value = s->padconf[pad_offset];
3685 prev_value &= ~(0xff << (byte_offset * 8));
3686 prev_value |= ((value & 0x1f1f1f1f) << (byte_offset * 8)) & 0x1f1f1f1f;
3687 s->padconf[pad_offset] = prev_value;
3688 break;
3689
3690 default:
3691 OMAP_BAD_REG(addr);
3692 break;
3693 }
3694 }
3695
3696 static void omap_sysctl_write(void *opaque, target_phys_addr_t addr,
3697 uint32_t value)
3698 {
3699 struct omap_sysctl_s *s = (struct omap_sysctl_s *) opaque;
3700
3701 switch (addr) {
3702 case 0x000: /* CONTROL_REVISION */
3703 case 0x2a4: /* CONTROL_MSUSPENDMUX_5 */
3704 case 0x2c0: /* CONTROL_PSA_VALUE */
3705 case 0x2f8: /* CONTROL_STATUS */
3706 case 0x2fc: /* CONTROL_GENERAL_PURPOSE_STATUS */
3707 case 0x300: /* CONTROL_RPUB_KEY_H_0 */
3708 case 0x304: /* CONTROL_RPUB_KEY_H_1 */
3709 case 0x308: /* CONTROL_RPUB_KEY_H_2 */
3710 case 0x30c: /* CONTROL_RPUB_KEY_H_3 */
3711 case 0x310: /* CONTROL_RAND_KEY_0 */
3712 case 0x314: /* CONTROL_RAND_KEY_1 */
3713 case 0x318: /* CONTROL_RAND_KEY_2 */
3714 case 0x31c: /* CONTROL_RAND_KEY_3 */
3715 case 0x320: /* CONTROL_CUST_KEY_0 */
3716 case 0x324: /* CONTROL_CUST_KEY_1 */
3717 case 0x330: /* CONTROL_TEST_KEY_0 */
3718 case 0x334: /* CONTROL_TEST_KEY_1 */
3719 case 0x338: /* CONTROL_TEST_KEY_2 */
3720 case 0x33c: /* CONTROL_TEST_KEY_3 */
3721 case 0x340: /* CONTROL_TEST_KEY_4 */
3722 case 0x344: /* CONTROL_TEST_KEY_5 */
3723 case 0x348: /* CONTROL_TEST_KEY_6 */
3724 case 0x34c: /* CONTROL_TEST_KEY_7 */
3725 case 0x350: /* CONTROL_TEST_KEY_8 */
3726 case 0x354: /* CONTROL_TEST_KEY_9 */
3727 OMAP_RO_REG(addr);
3728 return;
3729
3730 case 0x010: /* CONTROL_SYSCONFIG */
3731 s->sysconfig = value & 0x1e;
3732 break;
3733
3734 case 0x030 ... 0x140: /* CONTROL_PADCONF - only used in the POP */
3735 /* XXX: should check constant bits */
3736 s->padconf[(addr - 0x30) >> 2] = value & 0x1f1f1f1f;
3737 break;
3738
3739 case 0x270: /* CONTROL_DEBOBS */
3740 s->obs = value & 0xff;
3741 break;
3742
3743 case 0x274: /* CONTROL_DEVCONF */
3744 s->devconfig = value & 0xffffc7ff;
3745 break;
3746
3747 case 0x28c: /* CONTROL_EMU_SUPPORT */
3748 break;
3749
3750 case 0x290: /* CONTROL_MSUSPENDMUX_0 */
3751 s->msuspendmux[0] = value & 0x3fffffff;
3752 break;
3753 case 0x294: /* CONTROL_MSUSPENDMUX_1 */
3754 s->msuspendmux[1] = value & 0x3fffffff;
3755 break;
3756 case 0x298: /* CONTROL_MSUSPENDMUX_2 */
3757 s->msuspendmux[2] = value & 0x3fffffff;
3758 break;
3759 case 0x29c: /* CONTROL_MSUSPENDMUX_3 */
3760 s->msuspendmux[3] = value & 0x3fffffff;
3761 break;
3762 case 0x2a0: /* CONTROL_MSUSPENDMUX_4 */
3763 s->msuspendmux[4] = value & 0x3fffffff;
3764 break;
3765
3766 case 0x2b8: /* CONTROL_PSA_CTRL */
3767 s->psaconfig = value & 0x1c;
3768 s->psaconfig |= (value & 0x20) ? 2 : 1;
3769 break;
3770 case 0x2bc: /* CONTROL_PSA_CMD */
3771 break;
3772
3773 case 0x2b0: /* CONTROL_SEC_CTRL */
3774 case 0x2b4: /* CONTROL_SEC_TEST */
3775 case 0x2d0: /* CONTROL_SEC_EMU */
3776 case 0x2d4: /* CONTROL_SEC_TAP */
3777 case 0x2d8: /* CONTROL_OCM_RAM_PERM */
3778 case 0x2dc: /* CONTROL_OCM_PUB_RAM_ADD */
3779 case 0x2e0: /* CONTROL_EXT_SEC_RAM_START_ADD */
3780 case 0x2e4: /* CONTROL_EXT_SEC_RAM_STOP_ADD */
3781 case 0x2f0: /* CONTROL_SEC_STATUS */
3782 case 0x2f4: /* CONTROL_SEC_ERR_STATUS */
3783 break;
3784
3785 default:
3786 OMAP_BAD_REG(addr);
3787 return;
3788 }
3789 }
3790
3791 static CPUReadMemoryFunc *omap_sysctl_readfn[] = {
3792 omap_sysctl_read8,
3793 omap_badwidth_read32, /* TODO */
3794 omap_sysctl_read,
3795 };
3796
3797 static CPUWriteMemoryFunc *omap_sysctl_writefn[] = {
3798 omap_sysctl_write8,
3799 omap_badwidth_write32, /* TODO */
3800 omap_sysctl_write,
3801 };
3802
3803 static void omap_sysctl_reset(struct omap_sysctl_s *s)
3804 {
3805 /* (power-on reset) */
3806 s->sysconfig = 0;
3807 s->obs = 0;
3808 s->devconfig = 0x0c000000;
3809 s->msuspendmux[0] = 0x00000000;
3810 s->msuspendmux[1] = 0x00000000;
3811 s->msuspendmux[2] = 0x00000000;
3812 s->msuspendmux[3] = 0x00000000;
3813 s->msuspendmux[4] = 0x00000000;
3814 s->psaconfig = 1;
3815
3816 s->padconf[0x00] = 0x000f0f0f;
3817 s->padconf[0x01] = 0x00000000;
3818 s->padconf[0x02] = 0x00000000;
3819 s->padconf[0x03] = 0x00000000;
3820 s->padconf[0x04] = 0x00000000;
3821 s->padconf[0x05] = 0x00000000;
3822 s->padconf[0x06] = 0x00000000;
3823 s->padconf[0x07] = 0x00000000;
3824 s->padconf[0x08] = 0x08080800;
3825 s->padconf[0x09] = 0x08080808;
3826 s->padconf[0x0a] = 0x08080808;
3827 s->padconf[0x0b] = 0x08080808;
3828 s->padconf[0x0c] = 0x08080808;
3829 s->padconf[0x0d] = 0x08080800;
3830 s->padconf[0x0e] = 0x08080808;
3831 s->padconf[0x0f] = 0x08080808;
3832 s->padconf[0x10] = 0x18181808; /* | 0x07070700 if SBoot3 */
3833 s->padconf[0x11] = 0x18181818; /* | 0x07070707 if SBoot3 */
3834 s->padconf[0x12] = 0x18181818; /* | 0x07070707 if SBoot3 */
3835 s->padconf[0x13] = 0x18181818; /* | 0x07070707 if SBoot3 */
3836 s->padconf[0x14] = 0x18181818; /* | 0x00070707 if SBoot3 */
3837 s->padconf[0x15] = 0x18181818;
3838 s->padconf[0x16] = 0x18181818; /* | 0x07000000 if SBoot3 */
3839 s->padconf[0x17] = 0x1f001f00;
3840 s->padconf[0x18] = 0x1f1f1f1f;
3841 s->padconf[0x19] = 0x00000000;
3842 s->padconf[0x1a] = 0x1f180000;
3843 s->padconf[0x1b] = 0x00001f1f;
3844 s->padconf[0x1c] = 0x1f001f00;
3845 s->padconf[0x1d] = 0x00000000;
3846 s->padconf[0x1e] = 0x00000000;
3847 s->padconf[0x1f] = 0x08000000;
3848 s->padconf[0x20] = 0x08080808;
3849 s->padconf[0x21] = 0x08080808;
3850 s->padconf[0x22] = 0x0f080808;
3851 s->padconf[0x23] = 0x0f0f0f0f;
3852 s->padconf[0x24] = 0x000f0f0f;
3853 s->padconf[0x25] = 0x1f1f1f0f;
3854 s->padconf[0x26] = 0x080f0f1f;
3855 s->padconf[0x27] = 0x070f1808;
3856 s->padconf[0x28] = 0x0f070707;
3857 s->padconf[0x29] = 0x000f0f1f;
3858 s->padconf[0x2a] = 0x0f0f0f1f;
3859 s->padconf[0x2b] = 0x08000000;
3860 s->padconf[0x2c] = 0x0000001f;
3861 s->padconf[0x2d] = 0x0f0f1f00;
3862 s->padconf[0x2e] = 0x1f1f0f0f;
3863 s->padconf[0x2f] = 0x0f1f1f1f;
3864 s->padconf[0x30] = 0x0f0f0f0f;
3865 s->padconf[0x31] = 0x0f1f0f1f;
3866 s->padconf[0x32] = 0x0f0f0f0f;
3867 s->padconf[0x33] = 0x0f1f0f1f;
3868 s->padconf[0x34] = 0x1f1f0f0f;
3869 s->padconf[0x35] = 0x0f0f1f1f;
3870 s->padconf[0x36] = 0x0f0f1f0f;
3871 s->padconf[0x37] = 0x0f0f0f0f;
3872 s->padconf[0x38] = 0x1f18180f;
3873 s->padconf[0x39] = 0x1f1f1f1f;
3874 s->padconf[0x3a] = 0x00001f1f;
3875 s->padconf[0x3b] = 0x00000000;
3876 s->padconf[0x3c] = 0x00000000;
3877 s->padconf[0x3d] = 0x0f0f0f0f;
3878 s->padconf[0x3e] = 0x18000f0f;
3879 s->padconf[0x3f] = 0x00070000;
3880 s->padconf[0x40] = 0x00000707;
3881 s->padconf[0x41] = 0x0f1f0700;
3882 s->padconf[0x42] = 0x1f1f070f;
3883 s->padconf[0x43] = 0x0008081f;
3884 s->padconf[0x44] = 0x00000800;
3885 }
3886
3887 struct omap_sysctl_s *omap_sysctl_init(struct omap_target_agent_s *ta,
3888 omap_clk iclk, struct omap_mpu_state_s *mpu)
3889 {
3890 int iomemtype;
3891 struct omap_sysctl_s *s = (struct omap_sysctl_s *)
3892 qemu_mallocz(sizeof(struct omap_sysctl_s));
3893
3894 s->mpu = mpu;
3895 omap_sysctl_reset(s);
3896
3897 iomemtype = l4_register_io_memory(0, omap_sysctl_readfn,
3898 omap_sysctl_writefn, s);
3899 omap_l4_attach(ta, 0, iomemtype);
3900
3901 return s;
3902 }
3903
3904 /* SDRAM Controller Subsystem */
3905 struct omap_sdrc_s {
3906 uint8_t config;
3907 };
3908
3909 static void omap_sdrc_reset(struct omap_sdrc_s *s)
3910 {
3911 s->config = 0x10;
3912 }
3913
3914 static uint32_t omap_sdrc_read(void *opaque, target_phys_addr_t addr)
3915 {
3916 struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
3917
3918 switch (addr) {
3919 case 0x00: /* SDRC_REVISION */
3920 return 0x20;
3921
3922 case 0x10: /* SDRC_SYSCONFIG */
3923 return s->config;
3924
3925 case 0x14: /* SDRC_SYSSTATUS */
3926 return 1; /* RESETDONE */
3927
3928 case 0x40: /* SDRC_CS_CFG */
3929 case 0x44: /* SDRC_SHARING */
3930 case 0x48: /* SDRC_ERR_ADDR */
3931 case 0x4c: /* SDRC_ERR_TYPE */
3932 case 0x60: /* SDRC_DLLA_SCTRL */
3933 case 0x64: /* SDRC_DLLA_STATUS */
3934 case 0x68: /* SDRC_DLLB_CTRL */
3935 case 0x6c: /* SDRC_DLLB_STATUS */
3936 case 0x70: /* SDRC_POWER */
3937 case 0x80: /* SDRC_MCFG_0 */
3938 case 0x84: /* SDRC_MR_0 */
3939 case 0x88: /* SDRC_EMR1_0 */
3940 case 0x8c: /* SDRC_EMR2_0 */
3941 case 0x90: /* SDRC_EMR3_0 */
3942 case 0x94: /* SDRC_DCDL1_CTRL */
3943 case 0x98: /* SDRC_DCDL2_CTRL */
3944 case 0x9c: /* SDRC_ACTIM_CTRLA_0 */
3945 case 0xa0: /* SDRC_ACTIM_CTRLB_0 */
3946 case 0xa4: /* SDRC_RFR_CTRL_0 */
3947 case 0xa8: /* SDRC_MANUAL_0 */
3948 case 0xb0: /* SDRC_MCFG_1 */
3949 case 0xb4: /* SDRC_MR_1 */
3950 case 0xb8: /* SDRC_EMR1_1 */
3951 case 0xbc: /* SDRC_EMR2_1 */
3952 case 0xc0: /* SDRC_EMR3_1 */
3953 case 0xc4: /* SDRC_ACTIM_CTRLA_1 */
3954 case 0xc8: /* SDRC_ACTIM_CTRLB_1 */
3955 case 0xd4: /* SDRC_RFR_CTRL_1 */
3956 case 0xd8: /* SDRC_MANUAL_1 */
3957 return 0x00;
3958 }
3959
3960 OMAP_BAD_REG(addr);
3961 return 0;
3962 }
3963
3964 static void omap_sdrc_write(void *opaque, target_phys_addr_t addr,
3965 uint32_t value)
3966 {
3967 struct omap_sdrc_s *s = (struct omap_sdrc_s *) opaque;
3968
3969 switch (addr) {
3970 case 0x00: /* SDRC_REVISION */
3971 case 0x14: /* SDRC_SYSSTATUS */
3972 case 0x48: /* SDRC_ERR_ADDR */
3973 case 0x64: /* SDRC_DLLA_STATUS */
3974 case 0x6c: /* SDRC_DLLB_STATUS */
3975 OMAP_RO_REG(addr);
3976 return;
3977
3978 case 0x10: /* SDRC_SYSCONFIG */
3979 if ((value >> 3) != 0x2)
3980 fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
3981 __FUNCTION__, value >> 3);
3982 if (value & 2)
3983 omap_sdrc_reset(s);
3984 s->config = value & 0x18;
3985 break;
3986
3987 case 0x40: /* SDRC_CS_CFG */
3988 case 0x44: /* SDRC_SHARING */
3989 case 0x4c: /* SDRC_ERR_TYPE */
3990 case 0x60: /* SDRC_DLLA_SCTRL */
3991 case 0x68: /* SDRC_DLLB_CTRL */
3992 case 0x70: /* SDRC_POWER */
3993 case 0x80: /* SDRC_MCFG_0 */
3994 case 0x84: /* SDRC_MR_0 */
3995 case 0x88: /* SDRC_EMR1_0 */
3996 case 0x8c: /* SDRC_EMR2_0 */
3997 case 0x90: /* SDRC_EMR3_0 */
3998 case 0x94: /* SDRC_DCDL1_CTRL */
3999 case 0x98: /* SDRC_DCDL2_CTRL */
4000 case 0x9c: /* SDRC_ACTIM_CTRLA_0 */
4001 case 0xa0: /* SDRC_ACTIM_CTRLB_0 */
4002 case 0xa4: /* SDRC_RFR_CTRL_0 */
4003 case 0xa8: /* SDRC_MANUAL_0 */
4004 case 0xb0: /* SDRC_MCFG_1 */
4005 case 0xb4: /* SDRC_MR_1 */
4006 case 0xb8: /* SDRC_EMR1_1 */
4007 case 0xbc: /* SDRC_EMR2_1 */
4008 case 0xc0: /* SDRC_EMR3_1 */
4009 case 0xc4: /* SDRC_ACTIM_CTRLA_1 */
4010 case 0xc8: /* SDRC_ACTIM_CTRLB_1 */
4011 case 0xd4: /* SDRC_RFR_CTRL_1 */
4012 case 0xd8: /* SDRC_MANUAL_1 */
4013 break;
4014
4015 default:
4016 OMAP_BAD_REG(addr);
4017 return;
4018 }
4019 }
4020
4021 static CPUReadMemoryFunc *omap_sdrc_readfn[] = {
4022 omap_badwidth_read32,
4023 omap_badwidth_read32,
4024 omap_sdrc_read,
4025 };
4026
4027 static CPUWriteMemoryFunc *omap_sdrc_writefn[] = {
4028 omap_badwidth_write32,
4029 omap_badwidth_write32,
4030 omap_sdrc_write,
4031 };
4032
4033 struct omap_sdrc_s *omap_sdrc_init(target_phys_addr_t base)
4034 {
4035 int iomemtype;
4036 struct omap_sdrc_s *s = (struct omap_sdrc_s *)
4037 qemu_mallocz(sizeof(struct omap_sdrc_s));
4038
4039 omap_sdrc_reset(s);
4040
4041 iomemtype = cpu_register_io_memory(0, omap_sdrc_readfn,
4042 omap_sdrc_writefn, s);
4043 cpu_register_physical_memory(base, 0x1000, iomemtype);
4044
4045 return s;
4046 }
4047
4048 /* General-Purpose Memory Controller */
4049 struct omap_gpmc_s {
4050 qemu_irq irq;
4051
4052 uint8_t sysconfig;
4053 uint16_t irqst;
4054 uint16_t irqen;
4055 uint16_t timeout;
4056 uint16_t config;
4057 uint32_t prefconfig[2];
4058 int prefcontrol;
4059 int preffifo;
4060 int prefcount;
4061 struct omap_gpmc_cs_file_s {
4062 uint32_t config[7];
4063 target_phys_addr_t base;
4064 size_t size;
4065 int iomemtype;
4066 void (*base_update)(void *opaque, target_phys_addr_t new);
4067 void (*unmap)(void *opaque);
4068 void *opaque;
4069 } cs_file[8];
4070 int ecc_cs;
4071 int ecc_ptr;
4072 uint32_t ecc_cfg;
4073 struct ecc_state_s ecc[9];
4074 };
4075
4076 static void omap_gpmc_int_update(struct omap_gpmc_s *s)
4077 {
4078 qemu_set_irq(s->irq, s->irqen & s->irqst);
4079 }
4080
4081 static void omap_gpmc_cs_map(struct omap_gpmc_cs_file_s *f, int base, int mask)
4082 {
4083 /* TODO: check for overlapping regions and report access errors */
4084 if ((mask != 0x8 && mask != 0xc && mask != 0xe && mask != 0xf) ||
4085 (base < 0 || base >= 0x40) ||
4086 (base & 0x0f & ~mask)) {
4087 fprintf(stderr, "%s: wrong cs address mapping/decoding!\n",
4088 __FUNCTION__);
4089 return;
4090 }
4091
4092 if (!f->opaque)
4093 return;
4094
4095 f->base = base << 24;
4096 f->size = (0x0fffffff & ~(mask << 24)) + 1;
4097 /* TODO: rather than setting the size of the mapping (which should be
4098 * constant), the mask should cause wrapping of the address space, so
4099 * that the same memory becomes accessible at every <i>size</i> bytes
4100 * starting from <i>base</i>. */
4101 if (f->iomemtype)
4102 cpu_register_physical_memory(f->base, f->size, f->iomemtype);
4103
4104 if (f->base_update)
4105 f->base_update(f->opaque, f->base);
4106 }
4107
4108 static void omap_gpmc_cs_unmap(struct omap_gpmc_cs_file_s *f)
4109 {
4110 if (f->size) {
4111 if (f->unmap)
4112 f->unmap(f->opaque);
4113 if (f->iomemtype)
4114 cpu_register_physical_memory(f->base, f->size, IO_MEM_UNASSIGNED);
4115 f->base = 0;
4116 f->size = 0;
4117 }
4118 }
4119
4120 static void omap_gpmc_reset(struct omap_gpmc_s *s)
4121 {
4122 int i;
4123
4124 s->sysconfig = 0;
4125 s->irqst = 0;
4126 s->irqen = 0;
4127 omap_gpmc_int_update(s);
4128 s->timeout = 0;
4129 s->config = 0xa00;
4130 s->prefconfig[0] = 0x00004000;
4131 s->prefconfig[1] = 0x00000000;
4132 s->prefcontrol = 0;
4133 s->preffifo = 0;
4134 s->prefcount = 0;
4135 for (i = 0; i < 8; i ++) {
4136 if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */
4137 omap_gpmc_cs_unmap(s->cs_file + i);
4138 s->cs_file[i].config[0] = i ? 1 << 12 : 0;
4139 s->cs_file[i].config[1] = 0x101001;
4140 s->cs_file[i].config[2] = 0x020201;
4141 s->cs_file[i].config[3] = 0x10031003;
4142 s->cs_file[i].config[4] = 0x10f1111;
4143 s->cs_file[i].config[5] = 0;
4144 s->cs_file[i].config[6] = 0xf00 | (i ? 0 : 1 << 6);
4145 if (s->cs_file[i].config[6] & (1 << 6)) /* CSVALID */
4146 omap_gpmc_cs_map(&s->cs_file[i],
4147 s->cs_file[i].config[6] & 0x1f, /* MASKADDR */
4148 (s->cs_file[i].config[6] >> 8 & 0xf)); /* BASEADDR */
4149 }
4150 omap_gpmc_cs_map(s->cs_file, 0, 0xf);
4151 s->ecc_cs = 0;
4152 s->ecc_ptr = 0;
4153 s->ecc_cfg = 0x3fcff000;
4154 for (i = 0; i < 9; i ++)
4155 ecc_reset(&s->ecc[i]);
4156 }
4157
4158 static uint32_t omap_gpmc_read(void *opaque, target_phys_addr_t addr)
4159 {
4160 struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
4161 int cs;
4162 struct omap_gpmc_cs_file_s *f;
4163
4164 switch (addr) {
4165 case 0x000: /* GPMC_REVISION */
4166 return 0x20;
4167
4168 case 0x010: /* GPMC_SYSCONFIG */
4169 return s->sysconfig;
4170
4171 case 0x014: /* GPMC_SYSSTATUS */
4172 return 1; /* RESETDONE */
4173
4174 case 0x018: /* GPMC_IRQSTATUS */
4175 return s->irqst;
4176
4177 case 0x01c: /* GPMC_IRQENABLE */
4178 return s->irqen;
4179
4180 case 0x040: /* GPMC_TIMEOUT_CONTROL */
4181 return s->timeout;
4182
4183 case 0x044: /* GPMC_ERR_ADDRESS */
4184 case 0x048: /* GPMC_ERR_TYPE */
4185 return 0;
4186
4187 case 0x050: /* GPMC_CONFIG */
4188 return s->config;
4189
4190 case 0x054: /* GPMC_STATUS */
4191 return 0x001;
4192
4193 case 0x060 ... 0x1d4:
4194 cs = (addr - 0x060) / 0x30;
4195 addr -= cs * 0x30;
4196 f = s->cs_file + cs;
4197 switch (addr) {
4198 case 0x60: /* GPMC_CONFIG1 */
4199 return f->config[0];
4200 case 0x64: /* GPMC_CONFIG2 */
4201 return f->config[1];
4202 case 0x68: /* GPMC_CONFIG3 */
4203 return f->config[2];
4204 case 0x6c: /* GPMC_CONFIG4 */
4205 return f->config[3];
4206 case 0x70: /* GPMC_CONFIG5 */
4207 return f->config[4];
4208 case 0x74: /* GPMC_CONFIG6 */
4209 return f->config[5];
4210 case 0x78: /* GPMC_CONFIG7 */
4211 return f->config[6];
4212 case 0x84: /* GPMC_NAND_DATA */
4213 return 0;
4214 }
4215 break;
4216
4217 case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
4218 return s->prefconfig[0];
4219 case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
4220 return s->prefconfig[1];
4221 case 0x1ec: /* GPMC_PREFETCH_CONTROL */
4222 return s->prefcontrol;
4223 case 0x1f0: /* GPMC_PREFETCH_STATUS */
4224 return (s->preffifo << 24) |
4225 ((s->preffifo >
4226 ((s->prefconfig[0] >> 8) & 0x7f) ? 1 : 0) << 16) |
4227 s->prefcount;
4228
4229 case 0x1f4: /* GPMC_ECC_CONFIG */
4230 return s->ecc_cs;
4231 case 0x1f8: /* GPMC_ECC_CONTROL */
4232 return s->ecc_ptr;
4233 case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
4234 return s->ecc_cfg;
4235 case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
4236 cs = (addr & 0x1f) >> 2;
4237 /* TODO: check correctness */
4238 return
4239 ((s->ecc[cs].cp & 0x07) << 0) |
4240 ((s->ecc[cs].cp & 0x38) << 13) |
4241 ((s->ecc[cs].lp[0] & 0x1ff) << 3) |
4242 ((s->ecc[cs].lp[1] & 0x1ff) << 19);
4243
4244 case 0x230: /* GPMC_TESTMODE_CTRL */
4245 return 0;
4246 case 0x234: /* GPMC_PSA_LSB */
4247 case 0x238: /* GPMC_PSA_MSB */
4248 return 0x00000000;
4249 }
4250
4251 OMAP_BAD_REG(addr);
4252 return 0;
4253 }
4254
4255 static void omap_gpmc_write(void *opaque, target_phys_addr_t addr,
4256 uint32_t value)
4257 {
4258 struct omap_gpmc_s *s = (struct omap_gpmc_s *) opaque;
4259 int cs;
4260 struct omap_gpmc_cs_file_s *f;
4261
4262 switch (addr) {
4263 case 0x000: /* GPMC_REVISION */
4264 case 0x014: /* GPMC_SYSSTATUS */
4265 case 0x054: /* GPMC_STATUS */
4266 case 0x1f0: /* GPMC_PREFETCH_STATUS */
4267 case 0x200 ... 0x220: /* GPMC_ECC_RESULT */
4268 case 0x234: /* GPMC_PSA_LSB */
4269 case 0x238: /* GPMC_PSA_MSB */
4270 OMAP_RO_REG(addr);
4271 break;
4272
4273 case 0x010: /* GPMC_SYSCONFIG */
4274 if ((value >> 3) == 0x3)
4275 fprintf(stderr, "%s: bad SDRAM idle mode %i\n",
4276 __FUNCTION__, value >> 3);
4277 if (value & 2)
4278 omap_gpmc_reset(s);
4279 s->sysconfig = value & 0x19;
4280 break;
4281
4282 case 0x018: /* GPMC_IRQSTATUS */
4283 s->irqen = ~value;
4284 omap_gpmc_int_update(s);
4285 break;
4286
4287 case 0x01c: /* GPMC_IRQENABLE */
4288 s->irqen = value & 0xf03;
4289 omap_gpmc_int_update(s);
4290 break;
4291
4292 case 0x040: /* GPMC_TIMEOUT_CONTROL */
4293 s->timeout = value & 0x1ff1;
4294 break;
4295
4296 case 0x044: /* GPMC_ERR_ADDRESS */
4297 case 0x048: /* GPMC_ERR_TYPE */
4298 break;
4299
4300 case 0x050: /* GPMC_CONFIG */
4301 s->config = value & 0xf13;
4302 break;
4303
4304 case 0x060 ... 0x1d4:
4305 cs = (addr - 0x060) / 0x30;
4306 addr -= cs * 0x30;
4307 f = s->cs_file + cs;
4308 switch (addr) {
4309 case 0x60: /* GPMC_CONFIG1 */
4310 f->config[0] = value & 0xffef3e13;
4311 break;
4312 case 0x64: /* GPMC_CONFIG2 */
4313 f->config[1] = value & 0x001f1f8f;
4314 break;
4315 case 0x68: /* GPMC_CONFIG3 */
4316 f->config[2] = value & 0x001f1f8f;
4317 break;
4318 case 0x6c: /* GPMC_CONFIG4 */
4319 f->config[3] = value & 0x1f8f1f8f;
4320 break;
4321 case 0x70: /* GPMC_CONFIG5 */
4322 f->config[4] = value & 0x0f1f1f1f;
4323 break;
4324 case 0x74: /* GPMC_CONFIG6 */
4325 f->config[5] = value & 0x00000fcf;
4326 break;
4327 case 0x78: /* GPMC_CONFIG7 */
4328 if ((f->config[6] ^ value) & 0xf7f) {
4329 if (f->config[6] & (1 << 6)) /* CSVALID */
4330 omap_gpmc_cs_unmap(f);
4331 if (value & (1 << 6)) /* CSVALID */
4332 omap_gpmc_cs_map(f, value & 0x1f, /* MASKADDR */
4333 (value >> 8 & 0xf)); /* BASEADDR */
4334 }
4335 f->config[6] = value & 0x00000f7f;
4336 break;
4337 case 0x7c: /* GPMC_NAND_COMMAND */
4338 case 0x80: /* GPMC_NAND_ADDRESS */
4339 case 0x84: /* GPMC_NAND_DATA */
4340 break;
4341
4342 default:
4343 goto bad_reg;
4344 }
4345 break;
4346
4347 case 0x1e0: /* GPMC_PREFETCH_CONFIG1 */
4348 s->prefconfig[0] = value & 0x7f8f7fbf;
4349 /* TODO: update interrupts, fifos, dmas */
4350 break;
4351
4352 case 0x1e4: /* GPMC_PREFETCH_CONFIG2 */
4353 s->prefconfig[1] = value & 0x3fff;
4354 break;
4355
4356 case 0x1ec: /* GPMC_PREFETCH_CONTROL */
4357 s->prefcontrol = value & 1;
4358 if (s->prefcontrol) {
4359 if (s->prefconfig[0] & 1)
4360 s->preffifo = 0x40;
4361 else
4362 s->preffifo = 0x00;
4363 }
4364 /* TODO: start */
4365 break;
4366
4367 case 0x1f4: /* GPMC_ECC_CONFIG */
4368 s->ecc_cs = 0x8f;
4369 break;
4370 case 0x1f8: /* GPMC_ECC_CONTROL */
4371 if (value & (1 << 8))
4372 for (cs = 0; cs < 9; cs ++)
4373 ecc_reset(&s->ecc[cs]);
4374 s->ecc_ptr = value & 0xf;
4375 if (s->ecc_ptr == 0 || s->ecc_ptr > 9) {
4376 s->ecc_ptr = 0;
4377 s->ecc_cs &= ~1;
4378 }
4379 break;
4380 case 0x1fc: /* GPMC_ECC_SIZE_CONFIG */
4381 s->ecc_cfg = value & 0x3fcff1ff;
4382 break;
4383 case 0x230: /* GPMC_TESTMODE_CTRL */
4384 if (value & 7)
4385 fprintf(stderr, "%s: test mode enable attempt\n", __FUNCTION__);
4386 break;
4387
4388 default:
4389 bad_reg:
4390 OMAP_BAD_REG(addr);
4391 return;
4392 }
4393 }
4394
4395 static CPUReadMemoryFunc *omap_gpmc_readfn[] = {
4396 omap_badwidth_read32, /* TODO */
4397 omap_badwidth_read32, /* TODO */
4398 omap_gpmc_read,
4399 };
4400
4401 static CPUWriteMemoryFunc *omap_gpmc_writefn[] = {
4402 omap_badwidth_write32, /* TODO */
4403 omap_badwidth_write32, /* TODO */
4404 omap_gpmc_write,
4405 };
4406
4407 struct omap_gpmc_s *omap_gpmc_init(target_phys_addr_t base, qemu_irq irq)
4408 {
4409 int iomemtype;
4410 struct omap_gpmc_s *s = (struct omap_gpmc_s *)
4411 qemu_mallocz(sizeof(struct omap_gpmc_s));
4412
4413 omap_gpmc_reset(s);
4414
4415 iomemtype = cpu_register_io_memory(0, omap_gpmc_readfn,
4416 omap_gpmc_writefn, s);
4417 cpu_register_physical_memory(base, 0x1000, iomemtype);
4418
4419 return s;
4420 }
4421
4422 void omap_gpmc_attach(struct omap_gpmc_s *s, int cs, int iomemtype,
4423 void (*base_upd)(void *opaque, target_phys_addr_t new),
4424 void (*unmap)(void *opaque), void *opaque)
4425 {
4426 struct omap_gpmc_cs_file_s *f;
4427
4428 if (cs < 0 || cs >= 8) {
4429 fprintf(stderr, "%s: bad chip-select %i\n", __FUNCTION__, cs);
4430 exit(-1);
4431 }
4432 f = &s->cs_file[cs];
4433
4434 f->iomemtype = iomemtype;
4435 f->base_update = base_upd;
4436 f->unmap = unmap;
4437 f->opaque = opaque;
4438
4439 if (f->config[6] & (1 << 6)) /* CSVALID */
4440 omap_gpmc_cs_map(f, f->config[6] & 0x1f, /* MASKADDR */
4441 (f->config[6] >> 8 & 0xf)); /* BASEADDR */
4442 }
4443
4444 /* General chip reset */
4445 static void omap2_mpu_reset(void *opaque)
4446 {
4447 struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque;
4448
4449 omap_inth_reset(mpu->ih[0]);
4450 omap_dma_reset(mpu->dma);
4451 omap_prcm_reset(mpu->prcm);
4452 omap_sysctl_reset(mpu->sysc);
4453 omap_gp_timer_reset(mpu->gptimer[0]);
4454 omap_gp_timer_reset(mpu->gptimer[1]);
4455 omap_gp_timer_reset(mpu->gptimer[2]);
4456 omap_gp_timer_reset(mpu->gptimer[3]);
4457 omap_gp_timer_reset(mpu->gptimer[4]);
4458 omap_gp_timer_reset(mpu->gptimer[5]);
4459 omap_gp_timer_reset(mpu->gptimer[6]);
4460 omap_gp_timer_reset(mpu->gptimer[7]);
4461 omap_gp_timer_reset(mpu->gptimer[8]);
4462 omap_gp_timer_reset(mpu->gptimer[9]);
4463 omap_gp_timer_reset(mpu->gptimer[10]);
4464 omap_gp_timer_reset(mpu->gptimer[11]);
4465 omap_synctimer_reset(&mpu->synctimer);
4466 omap_sdrc_reset(mpu->sdrc);
4467 omap_gpmc_reset(mpu->gpmc);
4468 omap_dss_reset(mpu->dss);
4469 omap_uart_reset(mpu->uart[0]);
4470 omap_uart_reset(mpu->uart[1]);
4471 omap_uart_reset(mpu->uart[2]);
4472 omap_mmc_reset(mpu->mmc);
4473 omap_gpif_reset(mpu->gpif);
4474 omap_mcspi_reset(mpu->mcspi[0]);
4475 omap_mcspi_reset(mpu->mcspi[1]);
4476 omap_i2c_reset(mpu->i2c[0]);
4477 omap_i2c_reset(mpu->i2c[1]);
4478 cpu_reset(mpu->env);
4479 }
4480
4481 static int omap2_validate_addr(struct omap_mpu_state_s *s,
4482 target_phys_addr_t addr)
4483 {
4484 return 1;
4485 }
4486
4487 static const struct dma_irq_map omap2_dma_irq_map[] = {
4488 { 0, OMAP_INT_24XX_SDMA_IRQ0 },
4489 { 0, OMAP_INT_24XX_SDMA_IRQ1 },
4490 { 0, OMAP_INT_24XX_SDMA_IRQ2 },
4491 { 0, OMAP_INT_24XX_SDMA_IRQ3 },
4492 };
4493
4494 struct omap_mpu_state_s *omap2420_mpu_init(unsigned long sdram_size,
4495 const char *core)
4496 {
4497 struct omap_mpu_state_s *s = (struct omap_mpu_state_s *)
4498 qemu_mallocz(sizeof(struct omap_mpu_state_s));
4499 ram_addr_t sram_base, q2_base;
4500 qemu_irq *cpu_irq;
4501 qemu_irq dma_irqs[4];
4502 omap_clk gpio_clks[4];
4503 int sdindex;
4504 int i;
4505
4506 /* Core */
4507 s->mpu_model = omap2420;
4508 s->env = cpu_init(core ?: "arm1136-r2");
4509 if (!s->env) {
4510 fprintf(stderr, "Unable to find CPU definition\n");
4511 exit(1);
4512 }
4513 s->sdram_size = sdram_size;
4514 s->sram_size = OMAP242X_SRAM_SIZE;
4515
4516 s->wakeup = qemu_allocate_irqs(omap_mpu_wakeup, s, 1)[0];
4517
4518 /* Clocks */
4519 omap_clk_init(s);
4520
4521 /* Memory-mapped stuff */
4522 cpu_register_physical_memory(OMAP2_Q2_BASE, s->sdram_size,
4523 (q2_base = qemu_ram_alloc(s->sdram_size)) | IO_MEM_RAM);
4524 cpu_register_physical_memory(OMAP2_SRAM_BASE, s->sram_size,
4525 (sram_base = qemu_ram_alloc(s->sram_size)) | IO_MEM_RAM);
4526
4527 s->l4 = omap_l4_init(OMAP2_L4_BASE, 54);
4528
4529 /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */
4530 cpu_irq = arm_pic_init_cpu(s->env);
4531 s->ih[0] = omap2_inth_init(0x480fe000, 0x1000, 3, &s->irq[0],
4532 cpu_irq[ARM_PIC_CPU_IRQ], cpu_irq[ARM_PIC_CPU_FIQ],
4533 omap_findclk(s, "mpu_intc_fclk"),
4534 omap_findclk(s, "mpu_intc_iclk"));
4535
4536 s->prcm = omap_prcm_init(omap_l4tao(s->l4, 3),
4537 s->irq[0][OMAP_INT_24XX_PRCM_MPU_IRQ], NULL, NULL, s);
4538
4539 s->sysc = omap_sysctl_init(omap_l4tao(s->l4, 1),
4540 omap_findclk(s, "omapctrl_iclk"), s);
4541
4542 for (i = 0; i < 4; i ++)
4543 dma_irqs[i] =
4544 s->irq[omap2_dma_irq_map[i].ih][omap2_dma_irq_map[i].intr];
4545 s->dma = omap_dma4_init(0x48056000, dma_irqs, s, 256, 32,
4546 omap_findclk(s, "sdma_iclk"),
4547 omap_findclk(s, "sdma_fclk"));
4548 s->port->addr_valid = omap2_validate_addr;
4549
4550 /* Register SDRAM and SRAM ports for fast DMA transfers. */
4551 soc_dma_port_add_mem_ram(s->dma, q2_base, OMAP2_Q2_BASE, s->sdram_size);
4552 soc_dma_port_add_mem_ram(s->dma, sram_base, OMAP2_SRAM_BASE, s->sram_size);
4553
4554 s->uart[0] = omap2_uart_init(omap_l4ta(s->l4, 19),
4555 s->irq[0][OMAP_INT_24XX_UART1_IRQ],
4556 omap_findclk(s, "uart1_fclk"),
4557 omap_findclk(s, "uart1_iclk"),
4558 s->drq[OMAP24XX_DMA_UART1_TX],
4559 s->drq[OMAP24XX_DMA_UART1_RX], serial_hds[0]);
4560 s->uart[1] = omap2_uart_init(omap_l4ta(s->l4, 20),
4561 s->irq[0][OMAP_INT_24XX_UART2_IRQ],
4562 omap_findclk(s, "uart2_fclk"),
4563 omap_findclk(s, "uart2_iclk"),
4564 s->drq[OMAP24XX_DMA_UART2_TX],
4565 s->drq[OMAP24XX_DMA_UART2_RX],
4566 serial_hds[0] ? serial_hds[1] : 0);
4567 s->uart[2] = omap2_uart_init(omap_l4ta(s->l4, 21),
4568 s->irq[0][OMAP_INT_24XX_UART3_IRQ],
4569 omap_findclk(s, "uart3_fclk"),
4570 omap_findclk(s, "uart3_iclk"),
4571 s->drq[OMAP24XX_DMA_UART3_TX],
4572 s->drq[OMAP24XX_DMA_UART3_RX],
4573 serial_hds[0] && serial_hds[1] ? serial_hds[2] : 0);
4574
4575 s->gptimer[0] = omap_gp_timer_init(omap_l4ta(s->l4, 7),
4576 s->irq[0][OMAP_INT_24XX_GPTIMER1],
4577 omap_findclk(s, "wu_gpt1_clk"),
4578 omap_findclk(s, "wu_l4_iclk"));
4579 s->gptimer[1] = omap_gp_timer_init(omap_l4ta(s->l4, 8),
4580 s->irq[0][OMAP_INT_24XX_GPTIMER2],
4581 omap_findclk(s, "core_gpt2_clk"),
4582 omap_findclk(s, "core_l4_iclk"));
4583 s->gptimer[2] = omap_gp_timer_init(omap_l4ta(s->l4, 22),
4584 s->irq[0][OMAP_INT_24XX_GPTIMER3],
4585 omap_findclk(s, "core_gpt3_clk"),
4586 omap_findclk(s, "core_l4_iclk"));
4587 s->gptimer[3] = omap_gp_timer_init(omap_l4ta(s->l4, 23),
4588 s->irq[0][OMAP_INT_24XX_GPTIMER4],
4589 omap_findclk(s, "core_gpt4_clk"),
4590 omap_findclk(s, "core_l4_iclk"));
4591 s->gptimer[4] = omap_gp_timer_init(omap_l4ta(s->l4, 24),
4592 s->irq[0][OMAP_INT_24XX_GPTIMER5],
4593 omap_findclk(s, "core_gpt5_clk"),
4594 omap_findclk(s, "core_l4_iclk"));
4595 s->gptimer[5] = omap_gp_timer_init(omap_l4ta(s->l4, 25),
4596 s->irq[0][OMAP_INT_24XX_GPTIMER6],
4597 omap_findclk(s, "core_gpt6_clk"),
4598 omap_findclk(s, "core_l4_iclk"));
4599 s->gptimer[6] = omap_gp_timer_init(omap_l4ta(s->l4, 26),
4600 s->irq[0][OMAP_INT_24XX_GPTIMER7],
4601 omap_findclk(s, "core_gpt7_clk"),
4602 omap_findclk(s, "core_l4_iclk"));
4603 s->gptimer[7] = omap_gp_timer_init(omap_l4ta(s->l4, 27),
4604 s->irq[0][OMAP_INT_24XX_GPTIMER8],
4605 omap_findclk(s, "core_gpt8_clk"),
4606 omap_findclk(s, "core_l4_iclk"));
4607 s->gptimer[8] = omap_gp_timer_init(omap_l4ta(s->l4, 28),
4608 s->irq[0][OMAP_INT_24XX_GPTIMER9],
4609 omap_findclk(s, "core_gpt9_clk"),
4610 omap_findclk(s, "core_l4_iclk"));
4611 s->gptimer[9] = omap_gp_timer_init(omap_l4ta(s->l4, 29),
4612 s->irq[0][OMAP_INT_24XX_GPTIMER10],
4613 omap_findclk(s, "core_gpt10_clk"),
4614 omap_findclk(s, "core_l4_iclk"));
4615 s->gptimer[10] = omap_gp_timer_init(omap_l4ta(s->l4, 30),
4616 s->irq[0][OMAP_INT_24XX_GPTIMER11],
4617 omap_findclk(s, "core_gpt11_clk"),
4618 omap_findclk(s, "core_l4_iclk"));
4619 s->gptimer[11] = omap_gp_timer_init(omap_l4ta(s->l4, 31),
4620 s->irq[0][OMAP_INT_24XX_GPTIMER12],
4621 omap_findclk(s, "core_gpt12_clk"),
4622 omap_findclk(s, "core_l4_iclk"));
4623
4624 omap_tap_init(omap_l4ta(s->l4, 2), s);
4625
4626 omap_synctimer_init(omap_l4tao(s->l4, 2), s,
4627 omap_findclk(s, "clk32-kHz"),
4628 omap_findclk(s, "core_l4_iclk"));
4629
4630 s->i2c[0] = omap2_i2c_init(omap_l4tao(s->l4, 5),
4631 s->irq[0][OMAP_INT_24XX_I2C1_IRQ],
4632 &s->drq[OMAP24XX_DMA_I2C1_TX],
4633 omap_findclk(s, "i2c1.fclk"),
4634 omap_findclk(s, "i2c1.iclk"));
4635 s->i2c[1] = omap2_i2c_init(omap_l4tao(s->l4, 6),
4636 s->irq[0][OMAP_INT_24XX_I2C2_IRQ],
4637 &s->drq[OMAP24XX_DMA_I2C2_TX],
4638 omap_findclk(s, "i2c2.fclk"),
4639 omap_findclk(s, "i2c2.iclk"));
4640
4641 gpio_clks[0] = omap_findclk(s, "gpio1_dbclk");
4642 gpio_clks[1] = omap_findclk(s, "gpio2_dbclk");
4643 gpio_clks[2] = omap_findclk(s, "gpio3_dbclk");
4644 gpio_clks[3] = omap_findclk(s, "gpio4_dbclk");
4645 s->gpif = omap2_gpio_init(omap_l4ta(s->l4, 3),
4646 &s->irq[0][OMAP_INT_24XX_GPIO_BANK1],
4647 gpio_clks, omap_findclk(s, "gpio_iclk"), 4);
4648
4649 s->sdrc = omap_sdrc_init(0x68009000);
4650 s->gpmc = omap_gpmc_init(0x6800a000, s->irq[0][OMAP_INT_24XX_GPMC_IRQ]);
4651
4652 sdindex = drive_get_index(IF_SD, 0, 0);
4653 if (sdindex == -1) {
4654 fprintf(stderr, "qemu: missing SecureDigital device\n");
4655 exit(1);
4656 }
4657 s->mmc = omap2_mmc_init(omap_l4tao(s->l4, 9), drives_table[sdindex].bdrv,
4658 s->irq[0][OMAP_INT_24XX_MMC_IRQ],
4659 &s->drq[OMAP24XX_DMA_MMC1_TX],
4660 omap_findclk(s, "mmc_fclk"), omap_findclk(s, "mmc_iclk"));
4661
4662 s->mcspi[0] = omap_mcspi_init(omap_l4ta(s->l4, 35), 4,
4663 s->irq[0][OMAP_INT_24XX_MCSPI1_IRQ],
4664 &s->drq[OMAP24XX_DMA_SPI1_TX0],
4665 omap_findclk(s, "spi1_fclk"),
4666 omap_findclk(s, "spi1_iclk"));
4667 s->mcspi[1] = omap_mcspi_init(omap_l4ta(s->l4, 36), 2,
4668 s->irq[0][OMAP_INT_24XX_MCSPI2_IRQ],
4669 &s->drq[OMAP24XX_DMA_SPI2_TX0],
4670 omap_findclk(s, "spi2_fclk"),
4671 omap_findclk(s, "spi2_iclk"));
4672
4673 s->dss = omap_dss_init(omap_l4ta(s->l4, 10), 0x68000800,
4674 /* XXX wire M_IRQ_25, D_L2_IRQ_30 and I_IRQ_13 together */
4675 s->irq[0][OMAP_INT_24XX_DSS_IRQ], s->drq[OMAP24XX_DMA_DSS],
4676 omap_findclk(s, "dss_clk1"), omap_findclk(s, "dss_clk2"),
4677 omap_findclk(s, "dss_54m_clk"),
4678 omap_findclk(s, "dss_l3_iclk"),
4679 omap_findclk(s, "dss_l4_iclk"));
4680
4681 omap_sti_init(omap_l4ta(s->l4, 18), 0x54000000,
4682 s->irq[0][OMAP_INT_24XX_STI], omap_findclk(s, "emul_ck"),
4683 serial_hds[0] && serial_hds[1] && serial_hds[2] ?
4684 serial_hds[3] : 0);
4685
4686 s->eac = omap_eac_init(omap_l4ta(s->l4, 32),
4687 s->irq[0][OMAP_INT_24XX_EAC_IRQ],
4688 /* Ten consecutive lines */
4689 &s->drq[OMAP24XX_DMA_EAC_AC_RD],
4690 omap_findclk(s, "func_96m_clk"),
4691 omap_findclk(s, "core_l4_iclk"));
4692
4693 /* All register mappings (includin those not currenlty implemented):
4694 * SystemControlMod 48000000 - 48000fff
4695 * SystemControlL4 48001000 - 48001fff
4696 * 32kHz Timer Mod 48004000 - 48004fff
4697 * 32kHz Timer L4 48005000 - 48005fff
4698 * PRCM ModA 48008000 - 480087ff
4699 * PRCM ModB 48008800 - 48008fff
4700 * PRCM L4 48009000 - 48009fff
4701 * TEST-BCM Mod 48012000 - 48012fff
4702 * TEST-BCM L4 48013000 - 48013fff
4703 * TEST-TAP Mod 48014000 - 48014fff
4704 * TEST-TAP L4 48015000 - 48015fff
4705 * GPIO1 Mod 48018000 - 48018fff
4706 * GPIO Top 48019000 - 48019fff
4707 * GPIO2 Mod 4801a000 - 4801afff
4708 * GPIO L4 4801b000 - 4801bfff
4709 * GPIO3 Mod 4801c000 - 4801cfff
4710 * GPIO4 Mod 4801e000 - 4801efff
4711 * WDTIMER1 Mod 48020000 - 48010fff
4712 * WDTIMER Top 48021000 - 48011fff
4713 * WDTIMER2 Mod 48022000 - 48012fff
4714 * WDTIMER L4 48023000 - 48013fff
4715 * WDTIMER3 Mod 48024000 - 48014fff
4716 * WDTIMER3 L4 48025000 - 48015fff
4717 * WDTIMER4 Mod 48026000 - 48016fff
4718 * WDTIMER4 L4 48027000 - 48017fff
4719 * GPTIMER1 Mod 48028000 - 48018fff
4720 * GPTIMER1 L4 48029000 - 48019fff
4721 * GPTIMER2 Mod 4802a000 - 4801afff
4722 * GPTIMER2 L4 4802b000 - 4801bfff
4723 * L4-Config AP 48040000 - 480407ff
4724 * L4-Config IP 48040800 - 48040fff
4725 * L4-Config LA 48041000 - 48041fff
4726 * ARM11ETB Mod 48048000 - 48049fff
4727 * ARM11ETB L4 4804a000 - 4804afff
4728 * DISPLAY Top 48050000 - 480503ff
4729 * DISPLAY DISPC 48050400 - 480507ff
4730 * DISPLAY RFBI 48050800 - 48050bff
4731 * DISPLAY VENC 48050c00 - 48050fff
4732 * DISPLAY L4 48051000 - 48051fff
4733 * CAMERA Top 48052000 - 480523ff
4734 * CAMERA core 48052400 - 480527ff
4735 * CAMERA DMA 48052800 - 48052bff
4736 * CAMERA MMU 48052c00 - 48052fff
4737 * CAMERA L4 48053000 - 48053fff
4738 * SDMA Mod 48056000 - 48056fff
4739 * SDMA L4 48057000 - 48057fff
4740 * SSI Top 48058000 - 48058fff
4741 * SSI GDD 48059000 - 48059fff
4742 * SSI Port1 4805a000 - 4805afff
4743 * SSI Port2 4805b000 - 4805bfff
4744 * SSI L4 4805c000 - 4805cfff
4745 * USB Mod 4805e000 - 480fefff
4746 * USB L4 4805f000 - 480fffff
4747 * WIN_TRACER1 Mod 48060000 - 48060fff
4748 * WIN_TRACER1 L4 48061000 - 48061fff
4749 * WIN_TRACER2 Mod 48062000 - 48062fff
4750 * WIN_TRACER2 L4 48063000 - 48063fff
4751 * WIN_TRACER3 Mod 48064000 - 48064fff
4752 * WIN_TRACER3 L4 48065000 - 48065fff
4753 * WIN_TRACER4 Top 48066000 - 480660ff
4754 * WIN_TRACER4 ETT 48066100 - 480661ff
4755 * WIN_TRACER4 WT 48066200 - 480662ff
4756 * WIN_TRACER4 L4 48067000 - 48067fff
4757 * XTI Mod 48068000 - 48068fff
4758 * XTI L4 48069000 - 48069fff
4759 * UART1 Mod 4806a000 - 4806afff
4760 * UART1 L4 4806b000 - 4806bfff
4761 * UART2 Mod 4806c000 - 4806cfff
4762 * UART2 L4 4806d000 - 4806dfff
4763 * UART3 Mod 4806e000 - 4806efff
4764 * UART3 L4 4806f000 - 4806ffff
4765 * I2C1 Mod 48070000 - 48070fff
4766 * I2C1 L4 48071000 - 48071fff
4767 * I2C2 Mod 48072000 - 48072fff
4768 * I2C2 L4 48073000 - 48073fff
4769 * McBSP1 Mod 48074000 - 48074fff
4770 * McBSP1 L4 48075000 - 48075fff
4771 * McBSP2 Mod 48076000 - 48076fff
4772 * McBSP2 L4 48077000 - 48077fff
4773 * GPTIMER3 Mod 48078000 - 48078fff
4774 * GPTIMER3 L4 48079000 - 48079fff
4775 * GPTIMER4 Mod 4807a000 - 4807afff
4776 * GPTIMER4 L4 4807b000 - 4807bfff
4777 * GPTIMER5 Mod 4807c000 - 4807cfff
4778 * GPTIMER5 L4 4807d000 - 4807dfff
4779 * GPTIMER6 Mod 4807e000 - 4807efff
4780 * GPTIMER6 L4 4807f000 - 4807ffff
4781 * GPTIMER7 Mod 48080000 - 48080fff
4782 * GPTIMER7 L4 48081000 - 48081fff
4783 * GPTIMER8 Mod 48082000 - 48082fff
4784 * GPTIMER8 L4 48083000 - 48083fff
4785 * GPTIMER9 Mod 48084000 - 48084fff
4786 * GPTIMER9 L4 48085000 - 48085fff
4787 * GPTIMER10 Mod 48086000 - 48086fff
4788 * GPTIMER10 L4 48087000 - 48087fff
4789 * GPTIMER11 Mod 48088000 - 48088fff
4790 * GPTIMER11 L4 48089000 - 48089fff
4791 * GPTIMER12 Mod 4808a000 - 4808afff
4792 * GPTIMER12 L4 4808b000 - 4808bfff
4793 * EAC Mod 48090000 - 48090fff
4794 * EAC L4 48091000 - 48091fff
4795 * FAC Mod 48092000 - 48092fff
4796 * FAC L4 48093000 - 48093fff
4797 * MAILBOX Mod 48094000 - 48094fff
4798 * MAILBOX L4 48095000 - 48095fff
4799 * SPI1 Mod 48098000 - 48098fff
4800 * SPI1 L4 48099000 - 48099fff
4801 * SPI2 Mod 4809a000 - 4809afff
4802 * SPI2 L4 4809b000 - 4809bfff
4803 * MMC/SDIO Mod 4809c000 - 4809cfff
4804 * MMC/SDIO L4 4809d000 - 4809dfff
4805 * MS_PRO Mod 4809e000 - 4809efff
4806 * MS_PRO L4 4809f000 - 4809ffff
4807 * RNG Mod 480a0000 - 480a0fff
4808 * RNG L4 480a1000 - 480a1fff
4809 * DES3DES Mod 480a2000 - 480a2fff
4810 * DES3DES L4 480a3000 - 480a3fff
4811 * SHA1MD5 Mod 480a4000 - 480a4fff
4812 * SHA1MD5 L4 480a5000 - 480a5fff
4813 * AES Mod 480a6000 - 480a6fff
4814 * AES L4 480a7000 - 480a7fff
4815 * PKA Mod 480a8000 - 480a9fff
4816 * PKA L4 480aa000 - 480aafff
4817 * MG Mod 480b0000 - 480b0fff
4818 * MG L4 480b1000 - 480b1fff
4819 * HDQ/1-wire Mod 480b2000 - 480b2fff
4820 * HDQ/1-wire L4 480b3000 - 480b3fff
4821 * MPU interrupt 480fe000 - 480fefff
4822 * STI channel base 54000000 - 5400ffff
4823 * IVA RAM 5c000000 - 5c01ffff
4824 * IVA ROM 5c020000 - 5c027fff
4825 * IMG_BUF_A 5c040000 - 5c040fff
4826 * IMG_BUF_B 5c042000 - 5c042fff
4827 * VLCDS 5c048000 - 5c0487ff
4828 * IMX_COEF 5c049000 - 5c04afff
4829 * IMX_CMD 5c051000 - 5c051fff
4830 * VLCDQ 5c053000 - 5c0533ff
4831 * VLCDH 5c054000 - 5c054fff
4832 * SEQ_CMD 5c055000 - 5c055fff
4833 * IMX_REG 5c056000 - 5c0560ff
4834 * VLCD_REG 5c056100 - 5c0561ff
4835 * SEQ_REG 5c056200 - 5c0562ff
4836 * IMG_BUF_REG 5c056300 - 5c0563ff
4837 * SEQIRQ_REG 5c056400 - 5c0564ff
4838 * OCP_REG 5c060000 - 5c060fff
4839 * SYSC_REG 5c070000 - 5c070fff
4840 * MMU_REG 5d000000 - 5d000fff
4841 * sDMA R 68000400 - 680005ff
4842 * sDMA W 68000600 - 680007ff
4843 * Display Control 68000800 - 680009ff
4844 * DSP subsystem 68000a00 - 68000bff
4845 * MPU subsystem 68000c00 - 68000dff
4846 * IVA subsystem 68001000 - 680011ff
4847 * USB 68001200 - 680013ff
4848 * Camera 68001400 - 680015ff
4849 * VLYNQ (firewall) 68001800 - 68001bff
4850 * VLYNQ 68001e00 - 68001fff
4851 * SSI 68002000 - 680021ff
4852 * L4 68002400 - 680025ff
4853 * DSP (firewall) 68002800 - 68002bff
4854 * DSP subsystem 68002e00 - 68002fff
4855 * IVA (firewall) 68003000 - 680033ff
4856 * IVA 68003600 - 680037ff
4857 * GFX 68003a00 - 68003bff
4858 * CMDWR emulation 68003c00 - 68003dff
4859 * SMS 68004000 - 680041ff
4860 * OCM 68004200 - 680043ff
4861 * GPMC 68004400 - 680045ff
4862 * RAM (firewall) 68005000 - 680053ff
4863 * RAM (err login) 68005400 - 680057ff
4864 * ROM (firewall) 68005800 - 68005bff
4865 * ROM (err login) 68005c00 - 68005fff
4866 * GPMC (firewall) 68006000 - 680063ff
4867 * GPMC (err login) 68006400 - 680067ff
4868 * SMS (err login) 68006c00 - 68006fff
4869 * SMS registers 68008000 - 68008fff
4870 * SDRC registers 68009000 - 68009fff
4871 * GPMC registers 6800a000 6800afff
4872 */
4873
4874 qemu_register_reset(omap2_mpu_reset, s);
4875
4876 return s;
4877 }