hw/pxa2xx_lcd.c

   1 /*
   2  * Intel XScale PXA255/270 LCDC emulation.
   3  *
   4  * Copyright (c) 2006 Openedhand Ltd.
   5  * Written by Andrzej Zaborowski <balrog@zabor.org>
   6  *
   7  * This code is licensed under the GPLv2.
   8  */
   9
  10 #include "hw.h"
  11 #include "console.h"
  12 #include "pxa.h"
  13 #include "pixel_ops.h"
  14 /* FIXME: For graphic_rotate. Should probably be done in common code.  */
  15 #include "sysemu.h"
  16
  17 typedef void (*drawfn)(uint32_t *, uint8_t *, const uint8_t *, int, int);
  18
  19 struct pxa2xx_lcdc_s {
  20     qemu_irq irq;
  21     int irqlevel;
  22
  23     int invalidated;
  24     DisplayState *ds;
  25     drawfn *line_fn[2];
  26     int dest_width;
  27     int xres, yres;
  28     int pal_for;
  29     int transp;
  30     enum {
  31         pxa_lcdc_2bpp = 1,
  32         pxa_lcdc_4bpp = 2,
  33         pxa_lcdc_8bpp = 3,
  34         pxa_lcdc_16bpp = 4,
  35         pxa_lcdc_18bpp = 5,
  36         pxa_lcdc_18pbpp = 6,
  37         pxa_lcdc_19bpp = 7,
  38         pxa_lcdc_19pbpp = 8,
  39         pxa_lcdc_24bpp = 9,
  40         pxa_lcdc_25bpp = 10,
  41     } bpp;
  42
  43     uint32_t control[6];
  44     uint32_t status[2];
  45     uint32_t ovl1c[2];
  46     uint32_t ovl2c[2];
  47     uint32_t ccr;
  48     uint32_t cmdcr;
  49     uint32_t trgbr;
  50     uint32_t tcr;
  51     uint32_t liidr;
  52     uint8_t bscntr;
  53
  54     struct {
  55         target_phys_addr_t branch;
  56         int up;
  57         uint8_t palette[1024];
  58         uint8_t pbuffer[1024];
  59         void (*redraw)(struct pxa2xx_lcdc_s *s, uint8_t *fb,
  60                         int *miny, int *maxy);
  61
  62         target_phys_addr_t descriptor;
  63         target_phys_addr_t source;
  64         uint32_t id;
  65         uint32_t command;
  66     } dma_ch[7];
  67
  68     qemu_irq vsync_cb;
  69     int orientation;
  70 };
  71
  72 struct __attribute__ ((__packed__)) pxa_frame_descriptor_s {
  73     uint32_t fdaddr;
  74     uint32_t fsaddr;
  75     uint32_t fidr;
  76     uint32_t ldcmd;
  77 };
  78
  79 #define LCCR0   0x000   /* LCD Controller Control register 0 */
  80 #define LCCR1   0x004   /* LCD Controller Control register 1 */
  81 #define LCCR2   0x008   /* LCD Controller Control register 2 */
  82 #define LCCR3   0x00c   /* LCD Controller Control register 3 */
  83 #define LCCR4   0x010   /* LCD Controller Control register 4 */
  84 #define LCCR5   0x014   /* LCD Controller Control register 5 */
  85
  86 #define FBR0    0x020   /* DMA Channel 0 Frame Branch register */
  87 #define FBR1    0x024   /* DMA Channel 1 Frame Branch register */
  88 #define FBR2    0x028   /* DMA Channel 2 Frame Branch register */
  89 #define FBR3    0x02c   /* DMA Channel 3 Frame Branch register */
  90 #define FBR4    0x030   /* DMA Channel 4 Frame Branch register */
  91 #define FBR5    0x110   /* DMA Channel 5 Frame Branch register */
  92 #define FBR6    0x114   /* DMA Channel 6 Frame Branch register */
  93
  94 #define LCSR1   0x034   /* LCD Controller Status register 1 */
  95 #define LCSR0   0x038   /* LCD Controller Status register 0 */
  96 #define LIIDR   0x03c   /* LCD Controller Interrupt ID register */
  97
  98 #define TRGBR   0x040   /* TMED RGB Seed register */
  99 #define TCR     0x044   /* TMED Control register */
 100
 101 #define OVL1C1  0x050   /* Overlay 1 Control register 1 */
 102 #define OVL1C2  0x060   /* Overlay 1 Control register 2 */
 103 #define OVL2C1  0x070   /* Overlay 2 Control register 1 */
 104 #define OVL2C2  0x080   /* Overlay 2 Control register 2 */
 105 #define CCR     0x090   /* Cursor Control register */
 106
 107 #define CMDCR   0x100   /* Command Control register */
 108 #define PRSR    0x104   /* Panel Read Status register */
 109
 110 #define PXA_LCDDMA_CHANS        7
 111 #define DMA_FDADR               0x00    /* Frame Descriptor Address register */
 112 #define DMA_FSADR               0x04    /* Frame Source Address register */
 113 #define DMA_FIDR                0x08    /* Frame ID register */
 114 #define DMA_LDCMD               0x0c    /* Command register */
 115
 116 /* LCD Buffer Strength Control register */
 117 #define BSCNTR  0x04000054
 118
 119 /* Bitfield masks */
 120 #define LCCR0_ENB       (1 << 0)
 121 #define LCCR0_CMS       (1 << 1)
 122 #define LCCR0_SDS       (1 << 2)
 123 #define LCCR0_LDM       (1 << 3)
 124 #define LCCR0_SOFM0     (1 << 4)
 125 #define LCCR0_IUM       (1 << 5)
 126 #define LCCR0_EOFM0     (1 << 6)
 127 #define LCCR0_PAS       (1 << 7)
 128 #define LCCR0_DPD       (1 << 9)
 129 #define LCCR0_DIS       (1 << 10)
 130 #define LCCR0_QDM       (1 << 11)
 131 #define LCCR0_PDD       (0xff << 12)
 132 #define LCCR0_BSM0      (1 << 20)
 133 #define LCCR0_OUM       (1 << 21)
 134 #define LCCR0_LCDT      (1 << 22)
 135 #define LCCR0_RDSTM     (1 << 23)
 136 #define LCCR0_CMDIM     (1 << 24)
 137 #define LCCR0_OUC       (1 << 25)
 138 #define LCCR0_LDDALT    (1 << 26)
 139 #define LCCR1_PPL(x)    ((x) & 0x3ff)
 140 #define LCCR2_LPP(x)    ((x) & 0x3ff)
 141 #define LCCR3_API       (15 << 16)
 142 #define LCCR3_BPP(x)    ((((x) >> 24) & 7) | (((x) >> 26) & 8))
 143 #define LCCR3_PDFOR(x)  (((x) >> 30) & 3)
 144 #define LCCR4_K1(x)     (((x) >> 0) & 7)
 145 #define LCCR4_K2(x)     (((x) >> 3) & 7)
 146 #define LCCR4_K3(x)     (((x) >> 6) & 7)
 147 #define LCCR4_PALFOR(x) (((x) >> 15) & 3)
 148 #define LCCR5_SOFM(ch)  (1 << (ch - 1))
 149 #define LCCR5_EOFM(ch)  (1 << (ch + 7))
 150 #define LCCR5_BSM(ch)   (1 << (ch + 15))
 151 #define LCCR5_IUM(ch)   (1 << (ch + 23))
 152 #define OVLC1_EN        (1 << 31)
 153 #define CCR_CEN         (1 << 31)
 154 #define FBR_BRA         (1 << 0)
 155 #define FBR_BINT        (1 << 1)
 156 #define FBR_SRCADDR     (0xfffffff << 4)
 157 #define LCSR0_LDD       (1 << 0)
 158 #define LCSR0_SOF0      (1 << 1)
 159 #define LCSR0_BER       (1 << 2)
 160 #define LCSR0_ABC       (1 << 3)
 161 #define LCSR0_IU0       (1 << 4)
 162 #define LCSR0_IU1       (1 << 5)
 163 #define LCSR0_OU        (1 << 6)
 164 #define LCSR0_QD        (1 << 7)
 165 #define LCSR0_EOF0      (1 << 8)
 166 #define LCSR0_BS0       (1 << 9)
 167 #define LCSR0_SINT      (1 << 10)
 168 #define LCSR0_RDST      (1 << 11)
 169 #define LCSR0_CMDINT    (1 << 12)
 170 #define LCSR0_BERCH(x)  (((x) & 7) << 28)
 171 #define LCSR1_SOF(ch)   (1 << (ch - 1))
 172 #define LCSR1_EOF(ch)   (1 << (ch + 7))
 173 #define LCSR1_BS(ch)    (1 << (ch + 15))
 174 #define LCSR1_IU(ch)    (1 << (ch + 23))
 175 #define LDCMD_LENGTH(x) ((x) & 0x001ffffc)
 176 #define LDCMD_EOFINT    (1 << 21)
 177 #define LDCMD_SOFINT    (1 << 22)
 178 #define LDCMD_PAL       (1 << 26)
 179
 180 /* Route internal interrupt lines to the global IC */
 181 static void pxa2xx_lcdc_int_update(struct pxa2xx_lcdc_s *s)
 182 {
 183     int level = 0;
 184     level |= (s->status[0] & LCSR0_LDD)    && !(s->control[0] & LCCR0_LDM);
 185     level |= (s->status[0] & LCSR0_SOF0)   && !(s->control[0] & LCCR0_SOFM0);
 186     level |= (s->status[0] & LCSR0_IU0)    && !(s->control[0] & LCCR0_IUM);
 187     level |= (s->status[0] & LCSR0_IU1)    && !(s->control[5] & LCCR5_IUM(1));
 188     level |= (s->status[0] & LCSR0_OU)     && !(s->control[0] & LCCR0_OUM);
 189     level |= (s->status[0] & LCSR0_QD)     && !(s->control[0] & LCCR0_QDM);
 190     level |= (s->status[0] & LCSR0_EOF0)   && !(s->control[0] & LCCR0_EOFM0);
 191     level |= (s->status[0] & LCSR0_BS0)    && !(s->control[0] & LCCR0_BSM0);
 192     level |= (s->status[0] & LCSR0_RDST)   && !(s->control[0] & LCCR0_RDSTM);
 193     level |= (s->status[0] & LCSR0_CMDINT) && !(s->control[0] & LCCR0_CMDIM);
 194     level |= (s->status[1] & ~s->control[5]);
 195
 196     qemu_set_irq(s->irq, !!level);
 197     s->irqlevel = level;
 198 }
 199
 200 /* Set Branch Status interrupt high and poke associated registers */
 201 static inline void pxa2xx_dma_bs_set(struct pxa2xx_lcdc_s *s, int ch)
 202 {
 203     int unmasked;
 204     if (ch == 0) {
 205         s->status[0] |= LCSR0_BS0;
 206         unmasked = !(s->control[0] & LCCR0_BSM0);
 207     } else {
 208         s->status[1] |= LCSR1_BS(ch);
 209         unmasked = !(s->control[5] & LCCR5_BSM(ch));
 210     }
 211
 212     if (unmasked) {
 213         if (s->irqlevel)
 214             s->status[0] |= LCSR0_SINT;
 215         else
 216             s->liidr = s->dma_ch[ch].id;
 217     }
 218 }
 219
 220 /* Set Start Of Frame Status interrupt high and poke associated registers */
 221 static inline void pxa2xx_dma_sof_set(struct pxa2xx_lcdc_s *s, int ch)
 222 {
 223     int unmasked;
 224     if (!(s->dma_ch[ch].command & LDCMD_SOFINT))
 225         return;
 226
 227     if (ch == 0) {
 228         s->status[0] |= LCSR0_SOF0;
 229         unmasked = !(s->control[0] & LCCR0_SOFM0);
 230     } else {
 231         s->status[1] |= LCSR1_SOF(ch);
 232         unmasked = !(s->control[5] & LCCR5_SOFM(ch));
 233     }
 234
 235     if (unmasked) {
 236         if (s->irqlevel)
 237             s->status[0] |= LCSR0_SINT;
 238         else
 239             s->liidr = s->dma_ch[ch].id;
 240     }
 241 }
 242
 243 /* Set End Of Frame Status interrupt high and poke associated registers */
 244 static inline void pxa2xx_dma_eof_set(struct pxa2xx_lcdc_s *s, int ch)
 245 {
 246     int unmasked;
 247     if (!(s->dma_ch[ch].command & LDCMD_EOFINT))
 248         return;
 249
 250     if (ch == 0) {
 251         s->status[0] |= LCSR0_EOF0;
 252         unmasked = !(s->control[0] & LCCR0_EOFM0);
 253     } else {
 254         s->status[1] |= LCSR1_EOF(ch);
 255         unmasked = !(s->control[5] & LCCR5_EOFM(ch));
 256     }
 257
 258     if (unmasked) {
 259         if (s->irqlevel)
 260             s->status[0] |= LCSR0_SINT;
 261         else
 262             s->liidr = s->dma_ch[ch].id;
 263     }
 264 }
 265
 266 /* Set Bus Error Status interrupt high and poke associated registers */
 267 static inline void pxa2xx_dma_ber_set(struct pxa2xx_lcdc_s *s, int ch)
 268 {
 269     s->status[0] |= LCSR0_BERCH(ch) | LCSR0_BER;
 270     if (s->irqlevel)
 271         s->status[0] |= LCSR0_SINT;
 272     else
 273         s->liidr = s->dma_ch[ch].id;
 274 }
 275
 276 /* Set Read Status interrupt high and poke associated registers */
 277 static inline void pxa2xx_dma_rdst_set(struct pxa2xx_lcdc_s *s)
 278 {
 279     s->status[0] |= LCSR0_RDST;
 280     if (s->irqlevel && !(s->control[0] & LCCR0_RDSTM))
 281         s->status[0] |= LCSR0_SINT;
 282 }
 283
 284 /* Load new Frame Descriptors from DMA */
 285 static void pxa2xx_descriptor_load(struct pxa2xx_lcdc_s *s)
 286 {
 287     struct pxa_frame_descriptor_s *desc[PXA_LCDDMA_CHANS];
 288     target_phys_addr_t descptr;
 289     int i;
 290
 291     for (i = 0; i < PXA_LCDDMA_CHANS; i ++) {
 292         desc[i] = 0;
 293         s->dma_ch[i].source = 0;
 294
 295         if (!s->dma_ch[i].up)
 296             continue;
 297
 298         if (s->dma_ch[i].branch & FBR_BRA) {
 299             descptr = s->dma_ch[i].branch & FBR_SRCADDR;
 300             if (s->dma_ch[i].branch & FBR_BINT)
 301                 pxa2xx_dma_bs_set(s, i);
 302             s->dma_ch[i].branch &= ~FBR_BRA;
 303         } else
 304             descptr = s->dma_ch[i].descriptor;
 305
 306         if (!(descptr >= PXA2XX_SDRAM_BASE && descptr +
 307                     sizeof(*desc[i]) <= PXA2XX_SDRAM_BASE + phys_ram_size))
 308             continue;
 309
 310         descptr -= PXA2XX_SDRAM_BASE;
 311         desc[i] = (struct pxa_frame_descriptor_s *) (phys_ram_base + descptr);
 312         s->dma_ch[i].descriptor = desc[i]->fdaddr;
 313         s->dma_ch[i].source = desc[i]->fsaddr;
 314         s->dma_ch[i].id = desc[i]->fidr;
 315         s->dma_ch[i].command = desc[i]->ldcmd;
 316     }
 317 }
 318
 319 static uint32_t pxa2xx_lcdc_read(void *opaque, target_phys_addr_t offset)
 320 {
 321     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 322     int ch;
 323
 324     switch (offset) {
 325     case LCCR0:
 326         return s->control[0];
 327     case LCCR1:
 328         return s->control[1];
 329     case LCCR2:
 330         return s->control[2];
 331     case LCCR3:
 332         return s->control[3];
 333     case LCCR4:
 334         return s->control[4];
 335     case LCCR5:
 336         return s->control[5];
 337
 338     case OVL1C1:
 339         return s->ovl1c[0];
 340     case OVL1C2:
 341         return s->ovl1c[1];
 342     case OVL2C1:
 343         return s->ovl2c[0];
 344     case OVL2C2:
 345         return s->ovl2c[1];
 346
 347     case CCR:
 348         return s->ccr;
 349
 350     case CMDCR:
 351         return s->cmdcr;
 352
 353     case TRGBR:
 354         return s->trgbr;
 355     case TCR:
 356         return s->tcr;
 357
 358     case 0x200 ... 0x1000:      /* DMA per-channel registers */
 359         ch = (offset - 0x200) >> 4;
 360         if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
 361             goto fail;
 362
 363         switch (offset & 0xf) {
 364         case DMA_FDADR:
 365             return s->dma_ch[ch].descriptor;
 366         case DMA_FSADR:
 367             return s->dma_ch[ch].source;
 368         case DMA_FIDR:
 369             return s->dma_ch[ch].id;
 370         case DMA_LDCMD:
 371             return s->dma_ch[ch].command;
 372         default:
 373             goto fail;
 374         }
 375
 376     case FBR0:
 377         return s->dma_ch[0].branch;
 378     case FBR1:
 379         return s->dma_ch[1].branch;
 380     case FBR2:
 381         return s->dma_ch[2].branch;
 382     case FBR3:
 383         return s->dma_ch[3].branch;
 384     case FBR4:
 385         return s->dma_ch[4].branch;
 386     case FBR5:
 387         return s->dma_ch[5].branch;
 388     case FBR6:
 389         return s->dma_ch[6].branch;
 390
 391     case BSCNTR:
 392         return s->bscntr;
 393
 394     case PRSR:
 395         return 0;
 396
 397     case LCSR0:
 398         return s->status[0];
 399     case LCSR1:
 400         return s->status[1];
 401     case LIIDR:
 402         return s->liidr;
 403
 404     default:
 405     fail:
 406         cpu_abort(cpu_single_env,
 407                 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 408     }
 409
 410     return 0;
 411 }
 412
 413 static void pxa2xx_lcdc_write(void *opaque,
 414                 target_phys_addr_t offset, uint32_t value)
 415 {
 416     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 417     int ch;
 418
 419     switch (offset) {
 420     case LCCR0:
 421         /* ACK Quick Disable done */
 422         if ((s->control[0] & LCCR0_ENB) && !(value & LCCR0_ENB))
 423             s->status[0] |= LCSR0_QD;
 424
 425         if (!(s->control[0] & LCCR0_LCDT) && (value & LCCR0_LCDT))
 426             printf("%s: internal frame buffer unsupported\n", __FUNCTION__);
 427
 428         if ((s->control[3] & LCCR3_API) &&
 429                 (value & LCCR0_ENB) && !(value & LCCR0_LCDT))
 430             s->status[0] |= LCSR0_ABC;
 431
 432         s->control[0] = value & 0x07ffffff;
 433         pxa2xx_lcdc_int_update(s);
 434
 435         s->dma_ch[0].up = !!(value & LCCR0_ENB);
 436         s->dma_ch[1].up = (s->ovl1c[0] & OVLC1_EN) || (value & LCCR0_SDS);
 437         break;
 438
 439     case LCCR1:
 440         s->control[1] = value;
 441         break;
 442
 443     case LCCR2:
 444         s->control[2] = value;
 445         break;
 446
 447     case LCCR3:
 448         s->control[3] = value & 0xefffffff;
 449         s->bpp = LCCR3_BPP(value);
 450         break;
 451
 452     case LCCR4:
 453         s->control[4] = value & 0x83ff81ff;
 454         break;
 455
 456     case LCCR5:
 457         s->control[5] = value & 0x3f3f3f3f;
 458         break;
 459
 460     case OVL1C1:
 461         if (!(s->ovl1c[0] & OVLC1_EN) && (value & OVLC1_EN))
 462             printf("%s: Overlay 1 not supported\n", __FUNCTION__);
 463
 464         s->ovl1c[0] = value & 0x80ffffff;
 465         s->dma_ch[1].up = (value & OVLC1_EN) || (s->control[0] & LCCR0_SDS);
 466         break;
 467
 468     case OVL1C2:
 469         s->ovl1c[1] = value & 0x000fffff;
 470         break;
 471
 472     case OVL2C1:
 473         if (!(s->ovl2c[0] & OVLC1_EN) && (value & OVLC1_EN))
 474             printf("%s: Overlay 2 not supported\n", __FUNCTION__);
 475
 476         s->ovl2c[0] = value & 0x80ffffff;
 477         s->dma_ch[2].up = !!(value & OVLC1_EN);
 478         s->dma_ch[3].up = !!(value & OVLC1_EN);
 479         s->dma_ch[4].up = !!(value & OVLC1_EN);
 480         break;
 481
 482     case OVL2C2:
 483         s->ovl2c[1] = value & 0x007fffff;
 484         break;
 485
 486     case CCR:
 487         if (!(s->ccr & CCR_CEN) && (value & CCR_CEN))
 488             printf("%s: Hardware cursor unimplemented\n", __FUNCTION__);
 489
 490         s->ccr = value & 0x81ffffe7;
 491         s->dma_ch[5].up = !!(value & CCR_CEN);
 492         break;
 493
 494     case CMDCR:
 495         s->cmdcr = value & 0xff;
 496         break;
 497
 498     case TRGBR:
 499         s->trgbr = value & 0x00ffffff;
 500         break;
 501
 502     case TCR:
 503         s->tcr = value & 0x7fff;
 504         break;
 505
 506     case 0x200 ... 0x1000:      /* DMA per-channel registers */
 507         ch = (offset - 0x200) >> 4;
 508         if (!(ch >= 0 && ch < PXA_LCDDMA_CHANS))
 509             goto fail;
 510
 511         switch (offset & 0xf) {
 512         case DMA_FDADR:
 513             s->dma_ch[ch].descriptor = value & 0xfffffff0;
 514             break;
 515
 516         default:
 517             goto fail;
 518         }
 519         break;
 520
 521     case FBR0:
 522         s->dma_ch[0].branch = value & 0xfffffff3;
 523         break;
 524     case FBR1:
 525         s->dma_ch[1].branch = value & 0xfffffff3;
 526         break;
 527     case FBR2:
 528         s->dma_ch[2].branch = value & 0xfffffff3;
 529         break;
 530     case FBR3:
 531         s->dma_ch[3].branch = value & 0xfffffff3;
 532         break;
 533     case FBR4:
 534         s->dma_ch[4].branch = value & 0xfffffff3;
 535         break;
 536     case FBR5:
 537         s->dma_ch[5].branch = value & 0xfffffff3;
 538         break;
 539     case FBR6:
 540         s->dma_ch[6].branch = value & 0xfffffff3;
 541         break;
 542
 543     case BSCNTR:
 544         s->bscntr = value & 0xf;
 545         break;
 546
 547     case PRSR:
 548         break;
 549
 550     case LCSR0:
 551         s->status[0] &= ~(value & 0xfff);
 552         if (value & LCSR0_BER)
 553             s->status[0] &= ~LCSR0_BERCH(7);
 554         break;
 555
 556     case LCSR1:
 557         s->status[1] &= ~(value & 0x3e3f3f);
 558         break;
 559
 560     default:
 561     fail:
 562         cpu_abort(cpu_single_env,
 563                 "%s: Bad offset " REG_FMT "\n", __FUNCTION__, offset);
 564     }
 565 }
 566
 567 static CPUReadMemoryFunc *pxa2xx_lcdc_readfn[] = {
 568     pxa2xx_lcdc_read,
 569     pxa2xx_lcdc_read,
 570     pxa2xx_lcdc_read
 571 };
 572
 573 static CPUWriteMemoryFunc *pxa2xx_lcdc_writefn[] = {
 574     pxa2xx_lcdc_write,
 575     pxa2xx_lcdc_write,
 576     pxa2xx_lcdc_write
 577 };
 578
 579 /* Load new palette for a given DMA channel, convert to internal format */
 580 static void pxa2xx_palette_parse(struct pxa2xx_lcdc_s *s, int ch, int bpp)
 581 {
 582     int i, n, format, r, g, b, alpha;
 583     uint32_t *dest, *src;
 584     s->pal_for = LCCR4_PALFOR(s->control[4]);
 585     format = s->pal_for;
 586
 587     switch (bpp) {
 588     case pxa_lcdc_2bpp:
 589         n = 4;
 590         break;
 591     case pxa_lcdc_4bpp:
 592         n = 16;
 593         break;
 594     case pxa_lcdc_8bpp:
 595         n = 256;
 596         break;
 597     default:
 598         format = 0;
 599         return;
 600     }
 601
 602     src = (uint32_t *) s->dma_ch[ch].pbuffer;
 603     dest = (uint32_t *) s->dma_ch[ch].palette;
 604     alpha = r = g = b = 0;
 605
 606     for (i = 0; i < n; i ++) {
 607         switch (format) {
 608         case 0: /* 16 bpp, no transparency */
 609             alpha = 0;
 610             if (s->control[0] & LCCR0_CMS)
 611                 r = g = b = *src & 0xff;
 612             else {
 613                 r = (*src & 0xf800) >> 8;
 614                 g = (*src & 0x07e0) >> 3;
 615                 b = (*src & 0x001f) << 3;
 616             }
 617             break;
 618         case 1: /* 16 bpp plus transparency */
 619             alpha = *src & (1 << 24);
 620             if (s->control[0] & LCCR0_CMS)
 621                 r = g = b = *src & 0xff;
 622             else {
 623                 r = (*src & 0xf800) >> 8;
 624                 g = (*src & 0x07e0) >> 3;
 625                 b = (*src & 0x001f) << 3;
 626             }
 627             break;
 628         case 2: /* 18 bpp plus transparency */
 629             alpha = *src & (1 << 24);
 630             if (s->control[0] & LCCR0_CMS)
 631                 r = g = b = *src & 0xff;
 632             else {
 633                 r = (*src & 0xf80000) >> 16;
 634                 g = (*src & 0x00fc00) >> 8;
 635                 b = (*src & 0x0000f8);
 636             }
 637             break;
 638         case 3: /* 24 bpp plus transparency */
 639             alpha = *src & (1 << 24);
 640             if (s->control[0] & LCCR0_CMS)
 641                 r = g = b = *src & 0xff;
 642             else {
 643                 r = (*src & 0xff0000) >> 16;
 644                 g = (*src & 0x00ff00) >> 8;
 645                 b = (*src & 0x0000ff);
 646             }
 647             break;
 648         }
 649         switch (ds_get_bits_per_pixel(s->ds)) {
 650         case 8:
 651             *dest = rgb_to_pixel8(r, g, b) | alpha;
 652             break;
 653         case 15:
 654             *dest = rgb_to_pixel15(r, g, b) | alpha;
 655             break;
 656         case 16:
 657             *dest = rgb_to_pixel16(r, g, b) | alpha;
 658             break;
 659         case 24:
 660             *dest = rgb_to_pixel24(r, g, b) | alpha;
 661             break;
 662         case 32:
 663             *dest = rgb_to_pixel32(r, g, b) | alpha;
 664             break;
 665         }
 666         src ++;
 667         dest ++;
 668     }
 669 }
 670
 671 static void pxa2xx_lcdc_dma0_redraw_horiz(struct pxa2xx_lcdc_s *s,
 672                 uint8_t *fb, int *miny, int *maxy)
 673 {
 674     int y, src_width, dest_width, dirty[2];
 675     uint8_t *src, *dest;
 676     ram_addr_t x, addr, new_addr, start, end;
 677     drawfn fn = 0;
 678     if (s->dest_width)
 679         fn = s->line_fn[s->transp][s->bpp];
 680     if (!fn)
 681         return;
 682
 683     src = fb;
 684     src_width = (s->xres + 3) & ~3;     /* Pad to a 4 pixels multiple */
 685     if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
 686         src_width *= 3;
 687     else if (s->bpp > pxa_lcdc_16bpp)
 688         src_width *= 4;
 689     else if (s->bpp > pxa_lcdc_8bpp)
 690         src_width *= 2;
 691
 692     dest = ds_get_data(s->ds);
 693     dest_width = s->xres * s->dest_width;
 694
 695     addr = (ram_addr_t) (fb - phys_ram_base);
 696     start = addr + s->yres * src_width;
 697     end = addr;
 698     dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(addr, VGA_DIRTY_FLAG);
 699     for (y = 0; y < s->yres; y ++) {
 700         new_addr = addr + src_width;
 701         for (x = addr + TARGET_PAGE_SIZE; x < new_addr;
 702                         x += TARGET_PAGE_SIZE) {
 703             dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
 704             dirty[0] |= dirty[1];
 705         }
 706         if (dirty[0] || s->invalidated) {
 707             fn((uint32_t *) s->dma_ch[0].palette,
 708                             dest, src, s->xres, s->dest_width);
 709             if (addr < start)
 710                 start = addr;
 711             end = new_addr;
 712             if (y < *miny)
 713                 *miny = y;
 714             if (y >= *maxy)
 715                 *maxy = y + 1;
 716         }
 717         addr = new_addr;
 718         dirty[0] = dirty[1];
 719         src += src_width;
 720         dest += dest_width;
 721     }
 722
 723     if (end > start)
 724         cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG);
 725 }
 726
 727 static void pxa2xx_lcdc_dma0_redraw_vert(struct pxa2xx_lcdc_s *s,
 728                 uint8_t *fb, int *miny, int *maxy)
 729 {
 730     int y, src_width, dest_width, dirty[2];
 731     uint8_t *src, *dest;
 732     ram_addr_t x, addr, new_addr, start, end;
 733     drawfn fn = 0;
 734     if (s->dest_width)
 735         fn = s->line_fn[s->transp][s->bpp];
 736     if (!fn)
 737         return;
 738
 739     src = fb;
 740     src_width = (s->xres + 3) & ~3;     /* Pad to a 4 pixels multiple */
 741     if (s->bpp == pxa_lcdc_19pbpp || s->bpp == pxa_lcdc_18pbpp)
 742         src_width *= 3;
 743     else if (s->bpp > pxa_lcdc_16bpp)
 744         src_width *= 4;
 745     else if (s->bpp > pxa_lcdc_8bpp)
 746         src_width *= 2;
 747
 748     dest_width = s->yres * s->dest_width;
 749     dest = ds_get_data(s->ds) + dest_width * (s->xres - 1);
 750
 751     addr = (ram_addr_t) (fb - phys_ram_base);
 752     start = addr + s->yres * src_width;
 753     end = addr;
 754     x = addr + TARGET_PAGE_SIZE;
 755     dirty[0] = dirty[1] = cpu_physical_memory_get_dirty(start, VGA_DIRTY_FLAG);
 756     for (y = 0; y < s->yres; y ++) {
 757         new_addr = addr + src_width;
 758         for (; x < new_addr; x += TARGET_PAGE_SIZE) {
 759             dirty[1] = cpu_physical_memory_get_dirty(x, VGA_DIRTY_FLAG);
 760             dirty[0] |= dirty[1];
 761         }
 762         if (dirty[0] || s->invalidated) {
 763             fn((uint32_t *) s->dma_ch[0].palette,
 764                             dest, src, s->xres, -dest_width);
 765             if (addr < start)
 766                 start = addr;
 767             end = new_addr;
 768             if (y < *miny)
 769                 *miny = y;
 770             if (y >= *maxy)
 771                 *maxy = y + 1;
 772         }
 773         addr = new_addr;
 774         dirty[0] = dirty[1];
 775         src += src_width;
 776         dest += s->dest_width;
 777     }
 778
 779     if (end > start)
 780         cpu_physical_memory_reset_dirty(start, end, VGA_DIRTY_FLAG);
 781 }
 782
 783 static void pxa2xx_lcdc_resize(struct pxa2xx_lcdc_s *s)
 784 {
 785     int width, height;
 786     if (!(s->control[0] & LCCR0_ENB))
 787         return;
 788
 789     width = LCCR1_PPL(s->control[1]) + 1;
 790     height = LCCR2_LPP(s->control[2]) + 1;
 791
 792     if (width != s->xres || height != s->yres) {
 793         if (s->orientation)
 794             qemu_console_resize(s->ds, height, width);
 795         else
 796             qemu_console_resize(s->ds, width, height);
 797         s->invalidated = 1;
 798         s->xres = width;
 799         s->yres = height;
 800     }
 801 }
 802
 803 static void pxa2xx_update_display(void *opaque)
 804 {
 805     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 806     uint8_t *fb;
 807     target_phys_addr_t fbptr;
 808     int miny, maxy;
 809     int ch;
 810     if (!(s->control[0] & LCCR0_ENB))
 811         return;
 812
 813     pxa2xx_descriptor_load(s);
 814
 815     pxa2xx_lcdc_resize(s);
 816     miny = s->yres;
 817     maxy = 0;
 818     s->transp = s->dma_ch[2].up || s->dma_ch[3].up;
 819     /* Note: With overlay planes the order depends on LCCR0 bit 25.  */
 820     for (ch = 0; ch < PXA_LCDDMA_CHANS; ch ++)
 821         if (s->dma_ch[ch].up) {
 822             if (!s->dma_ch[ch].source) {
 823                 pxa2xx_dma_ber_set(s, ch);
 824                 continue;
 825             }
 826             fbptr = s->dma_ch[ch].source;
 827             if (!(fbptr >= PXA2XX_SDRAM_BASE &&
 828                     fbptr <= PXA2XX_SDRAM_BASE + phys_ram_size)) {
 829                 pxa2xx_dma_ber_set(s, ch);
 830                 continue;
 831             }
 832             fbptr -= PXA2XX_SDRAM_BASE;
 833             fb = phys_ram_base + fbptr;
 834
 835             if (s->dma_ch[ch].command & LDCMD_PAL) {
 836                 memcpy(s->dma_ch[ch].pbuffer, fb,
 837                                 MAX(LDCMD_LENGTH(s->dma_ch[ch].command),
 838                                 sizeof(s->dma_ch[ch].pbuffer)));
 839                 pxa2xx_palette_parse(s, ch, s->bpp);
 840             } else {
 841                 /* Do we need to reparse palette */
 842                 if (LCCR4_PALFOR(s->control[4]) != s->pal_for)
 843                     pxa2xx_palette_parse(s, ch, s->bpp);
 844
 845                 /* ACK frame start */
 846                 pxa2xx_dma_sof_set(s, ch);
 847
 848                 s->dma_ch[ch].redraw(s, fb, &miny, &maxy);
 849                 s->invalidated = 0;
 850
 851                 /* ACK frame completed */
 852                 pxa2xx_dma_eof_set(s, ch);
 853             }
 854         }
 855
 856     if (s->control[0] & LCCR0_DIS) {
 857         /* ACK last frame completed */
 858         s->control[0] &= ~LCCR0_ENB;
 859         s->status[0] |= LCSR0_LDD;
 860     }
 861
 862     if (s->orientation)
 863         dpy_update(s->ds, miny, 0, maxy, s->xres);
 864     else
 865         dpy_update(s->ds, 0, miny, s->xres, maxy);
 866     pxa2xx_lcdc_int_update(s);
 867
 868     qemu_irq_raise(s->vsync_cb);
 869 }
 870
 871 static void pxa2xx_invalidate_display(void *opaque)
 872 {
 873     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 874     s->invalidated = 1;
 875 }
 876
 877 static void pxa2xx_screen_dump(void *opaque, const char *filename)
 878 {
 879     /* TODO */
 880 }
 881
 882 static void pxa2xx_lcdc_orientation(void *opaque, int angle)
 883 {
 884     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 885
 886     if (angle) {
 887         s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_vert;
 888     } else {
 889         s->dma_ch[0].redraw = pxa2xx_lcdc_dma0_redraw_horiz;
 890     }
 891
 892     s->orientation = angle;
 893     s->xres = s->yres = -1;
 894     pxa2xx_lcdc_resize(s);
 895 }
 896
 897 static void pxa2xx_lcdc_save(QEMUFile *f, void *opaque)
 898 {
 899     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 900     int i;
 901
 902     qemu_put_be32(f, s->irqlevel);
 903     qemu_put_be32(f, s->transp);
 904
 905     for (i = 0; i < 6; i ++)
 906         qemu_put_be32s(f, &s->control[i]);
 907     for (i = 0; i < 2; i ++)
 908         qemu_put_be32s(f, &s->status[i]);
 909     for (i = 0; i < 2; i ++)
 910         qemu_put_be32s(f, &s->ovl1c[i]);
 911     for (i = 0; i < 2; i ++)
 912         qemu_put_be32s(f, &s->ovl2c[i]);
 913     qemu_put_be32s(f, &s->ccr);
 914     qemu_put_be32s(f, &s->cmdcr);
 915     qemu_put_be32s(f, &s->trgbr);
 916     qemu_put_be32s(f, &s->tcr);
 917     qemu_put_be32s(f, &s->liidr);
 918     qemu_put_8s(f, &s->bscntr);
 919
 920     for (i = 0; i < 7; i ++) {
 921         qemu_put_betl(f, s->dma_ch[i].branch);
 922         qemu_put_byte(f, s->dma_ch[i].up);
 923         qemu_put_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
 924
 925         qemu_put_betl(f, s->dma_ch[i].descriptor);
 926         qemu_put_betl(f, s->dma_ch[i].source);
 927         qemu_put_be32s(f, &s->dma_ch[i].id);
 928         qemu_put_be32s(f, &s->dma_ch[i].command);
 929     }
 930 }
 931
 932 static int pxa2xx_lcdc_load(QEMUFile *f, void *opaque, int version_id)
 933 {
 934     struct pxa2xx_lcdc_s *s = (struct pxa2xx_lcdc_s *) opaque;
 935     int i;
 936
 937     s->irqlevel = qemu_get_be32(f);
 938     s->transp = qemu_get_be32(f);
 939
 940     for (i = 0; i < 6; i ++)
 941         qemu_get_be32s(f, &s->control[i]);
 942     for (i = 0; i < 2; i ++)
 943         qemu_get_be32s(f, &s->status[i]);
 944     for (i = 0; i < 2; i ++)
 945         qemu_get_be32s(f, &s->ovl1c[i]);
 946     for (i = 0; i < 2; i ++)
 947         qemu_get_be32s(f, &s->ovl2c[i]);
 948     qemu_get_be32s(f, &s->ccr);
 949     qemu_get_be32s(f, &s->cmdcr);
 950     qemu_get_be32s(f, &s->trgbr);
 951     qemu_get_be32s(f, &s->tcr);
 952     qemu_get_be32s(f, &s->liidr);
 953     qemu_get_8s(f, &s->bscntr);
 954
 955     for (i = 0; i < 7; i ++) {
 956         s->dma_ch[i].branch = qemu_get_betl(f);
 957         s->dma_ch[i].up = qemu_get_byte(f);
 958         qemu_get_buffer(f, s->dma_ch[i].pbuffer, sizeof(s->dma_ch[i].pbuffer));
 959
 960         s->dma_ch[i].descriptor = qemu_get_betl(f);
 961         s->dma_ch[i].source = qemu_get_betl(f);
 962         qemu_get_be32s(f, &s->dma_ch[i].id);
 963         qemu_get_be32s(f, &s->dma_ch[i].command);
 964     }
 965
 966     s->bpp = LCCR3_BPP(s->control[3]);
 967     s->xres = s->yres = s->pal_for = -1;
 968
 969     return 0;
 970 }
 971
 972 #define BITS 8
 973 #include "pxa2xx_template.h"
 974 #define BITS 15
 975 #include "pxa2xx_template.h"
 976 #define BITS 16
 977 #include "pxa2xx_template.h"
 978 #define BITS 24
 979 #include "pxa2xx_template.h"
 980 #define BITS 32
 981 #include "pxa2xx_template.h"
 982
 983 struct pxa2xx_lcdc_s *pxa2xx_lcdc_init(target_phys_addr_t base, qemu_irq irq)
 984 {
 985     int iomemtype;
 986     struct pxa2xx_lcdc_s *s;
 987
 988     s = (struct pxa2xx_lcdc_s *) qemu_mallocz(sizeof(struct pxa2xx_lcdc_s));
 989     s->invalidated = 1;
 990     s->irq = irq;
 991
 992     pxa2xx_lcdc_orientation(s, graphic_rotate);
 993
 994     iomemtype = cpu_register_io_memory(0, pxa2xx_lcdc_readfn,
 995                     pxa2xx_lcdc_writefn, s);
 996     cpu_register_physical_memory(base, 0x00100000, iomemtype);
 997
 998     s->ds = graphic_console_init(pxa2xx_update_display,
 999                                  pxa2xx_invalidate_display,
1000                                  pxa2xx_screen_dump, NULL, s);
1001
1002     switch (ds_get_bits_per_pixel(s->ds)) {
1003     case 0:
1004         s->dest_width = 0;
1005         break;
1006     case 8:
1007         s->line_fn[0] = pxa2xx_draw_fn_8;
1008         s->line_fn[1] = pxa2xx_draw_fn_8t;
1009         s->dest_width = 1;
1010         break;
1011     case 15:
1012         s->line_fn[0] = pxa2xx_draw_fn_15;
1013         s->line_fn[1] = pxa2xx_draw_fn_15t;
1014         s->dest_width = 2;
1015         break;
1016     case 16:
1017         s->line_fn[0] = pxa2xx_draw_fn_16;
1018         s->line_fn[1] = pxa2xx_draw_fn_16t;
1019         s->dest_width = 2;
1020         break;
1021     case 24:
1022         s->line_fn[0] = pxa2xx_draw_fn_24;
1023         s->line_fn[1] = pxa2xx_draw_fn_24t;
1024         s->dest_width = 3;
1025         break;
1026     case 32:
1027         s->line_fn[0] = pxa2xx_draw_fn_32;
1028         s->line_fn[1] = pxa2xx_draw_fn_32t;
1029         s->dest_width = 4;
1030         break;
1031     default:
1032         fprintf(stderr, "%s: Bad color depth\n", __FUNCTION__);
1033         exit(1);
1034     }
1035
1036     register_savevm("pxa2xx_lcdc", 0, 0,
1037                     pxa2xx_lcdc_save, pxa2xx_lcdc_load, s);
1038
1039     return s;
1040 }
1041
1042 void pxa2xx_lcd_vsync_notifier(struct pxa2xx_lcdc_s *s, qemu_irq handler)
1043 {
1044     s->vsync_cb = handler;
1045 }